gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 88, 92-97, 1998 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_regnotes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #ifdef __STDC__
  79 #include <stdarg.h>
  80 #else
  81 #include <varargs.h>
  82 #endif
  83
  84 /* stdio.h must precede rtl.h for FFS.  */
  85 #include "system.h"
  86
  87 #include "rtl.h"
  88 #include "flags.h"
  89 #include "regs.h"
  90 #include "hard-reg-set.h"
  91 #include "basic-block.h"
  92 #include "insn-config.h"
  93 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
  94 #include "expr.h"
  95 #include "insn-flags.h"
  96 #include "insn-codes.h"
  97 #include "insn-attr.h"
  98 #include "recog.h"
  99 #include "real.h"
 100
 101 /* It is not safe to use ordinary gen_lowpart in combine.
 102    Use gen_lowpart_for_combine instead.  See comments there.  */
 103 #define gen_lowpart dont_use_gen_lowpart_you_dummy
 104
 105 /* Number of attempts to combine instructions in this function.  */
 106
 107 static int combine_attempts;
 108
 109 /* Number of attempts that got as far as substitution in this function.  */
 110
 111 static int combine_merges;
 112
 113 /* Number of instructions combined with added SETs in this function.  */
 114
 115 static int combine_extras;
 116
 117 /* Number of instructions combined in this function.  */
 118
 119 static int combine_successes;
 120
 121 /* Totals over entire compilation.  */
 122
 123 static int total_attempts, total_merges, total_extras, total_successes;
 124
 125 /* Define a default value for REVERSIBLE_CC_MODE.
 126    We can never assume that a condition code mode is safe to reverse unless
 127    the md tells us so.  */
 128 #ifndef REVERSIBLE_CC_MODE
 129 #define REVERSIBLE_CC_MODE(MODE) 0
 130 #endif
 131 \f
 132 /* Vector mapping INSN_UIDs to cuids.
 133    The cuids are like uids but increase monotonically always.
 134    Combine always uses cuids so that it can compare them.
 135    But actually renumbering the uids, which we used to do,
 136    proves to be a bad idea because it makes it hard to compare
 137    the dumps produced by earlier passes with those from later passes.  */
 138
 139 static int *uid_cuid;
 140 static int max_uid_cuid;
 141
 142 /* Get the cuid of an insn.  */
 143
 144 #define INSN_CUID(INSN) \
 145 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 146
 147 /* Maximum register number, which is the size of the tables below.  */
 148
 149 static int combine_max_regno;
 150
 151 /* Record last point of death of (hard or pseudo) register n.  */
 152
 153 static rtx *reg_last_death;
 154
 155 /* Record last point of modification of (hard or pseudo) register n.  */
 156
 157 static rtx *reg_last_set;
 158
 159 /* Record the cuid of the last insn that invalidated memory
 160    (anything that writes memory, and subroutine calls, but not pushes).  */
 161
 162 static int mem_last_set;
 163
 164 /* Record the cuid of the last CALL_INSN
 165    so we can tell whether a potential combination crosses any calls.  */
 166
 167 static int last_call_cuid;
 168
 169 /* When `subst' is called, this is the insn that is being modified
 170    (by combining in a previous insn).  The PATTERN of this insn
 171    is still the old pattern partially modified and it should not be
 172    looked at, but this may be used to examine the successors of the insn
 173    to judge whether a simplification is valid.  */
 174
 175 static rtx subst_insn;
 176
 177 /* This is an insn that belongs before subst_insn, but is not currently
 178    on the insn chain.  */
 179
 180 static rtx subst_prev_insn;
 181
 182 /* This is the lowest CUID that `subst' is currently dealing with.
 183    get_last_value will not return a value if the register was set at or
 184    after this CUID.  If not for this mechanism, we could get confused if
 185    I2 or I1 in try_combine were an insn that used the old value of a register
 186    to obtain a new value.  In that case, we might erroneously get the
 187    new value of the register when we wanted the old one.  */
 188
 189 static int subst_low_cuid;
 190
 191 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 192    must consider all these registers to be always live.  */
 193
 194 static HARD_REG_SET newpat_used_regs;
 195
 196 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 197    insn is the earlier than I2 or I3, combine should rescan starting at
 198    that location.  */
 199
 200 static rtx added_links_insn;
 201
 202 /* Basic block number of the block in which we are performing combines.  */
 203 static int this_basic_block;
 204 \f
 205 /* The next group of arrays allows the recording of the last value assigned
 206    to (hard or pseudo) register n.  We use this information to see if a
 207    operation being processed is redundant given a prior operation performed
 208    on the register.  For example, an `and' with a constant is redundant if
 209    all the zero bits are already known to be turned off.
 210
 211    We use an approach similar to that used by cse, but change it in the
 212    following ways:
 213
 214    (1) We do not want to reinitialize at each label.
 215    (2) It is useful, but not critical, to know the actual value assigned
 216        to a register.  Often just its form is helpful.
 217
 218    Therefore, we maintain the following arrays:
 219
 220    reg_last_set_value           the last value assigned
 221    reg_last_set_label           records the value of label_tick when the
 222                                 register was assigned
 223    reg_last_set_table_tick      records the value of label_tick when a
 224                                 value using the register is assigned
 225    reg_last_set_invalid         set to non-zero when it is not valid
 226                                 to use the value of this register in some
 227                                 register's value
 228
 229    To understand the usage of these tables, it is important to understand
 230    the distinction between the value in reg_last_set_value being valid
 231    and the register being validly contained in some other expression in the
 232    table.
 233
 234    Entry I in reg_last_set_value is valid if it is non-zero, and either
 235    reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
 236
 237    Register I may validly appear in any expression returned for the value
 238    of another register if reg_n_sets[i] is 1.  It may also appear in the
 239    value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
 240    reg_last_set_invalid[j] is zero.
 241
 242    If an expression is found in the table containing a register which may
 243    not validly appear in an expression, the register is replaced by
 244    something that won't match, (clobber (const_int 0)).
 245
 246    reg_last_set_invalid[i] is set non-zero when register I is being assigned
 247    to and reg_last_set_table_tick[i] == label_tick.  */
 248
 249 /* Record last value assigned to (hard or pseudo) register n.  */
 250
 251 static rtx *reg_last_set_value;
 252
 253 /* Record the value of label_tick when the value for register n is placed in
 254    reg_last_set_value[n].  */
 255
 256 static int *reg_last_set_label;
 257
 258 /* Record the value of label_tick when an expression involving register n
 259    is placed in reg_last_set_value.  */
 260
 261 static int *reg_last_set_table_tick;
 262
 263 /* Set non-zero if references to register n in expressions should not be
 264    used.  */
 265
 266 static char *reg_last_set_invalid;
 267
 268 /* Incremented for each label.  */
 269
 270 static int label_tick;
 271
 272 /* Some registers that are set more than once and used in more than one
 273    basic block are nevertheless always set in similar ways.  For example,
 274    a QImode register may be loaded from memory in two places on a machine
 275    where byte loads zero extend.
 276
 277    We record in the following array what we know about the nonzero
 278    bits of a register, specifically which bits are known to be zero.
 279
 280    If an entry is zero, it means that we don't know anything special.  */
 281
 282 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
 283
 284 /* Mode used to compute significance in reg_nonzero_bits.  It is the largest
 285    integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 286
 287 static enum machine_mode nonzero_bits_mode;
 288
 289 /* Nonzero if we know that a register has some leading bits that are always
 290    equal to the sign bit.  */
 291
 292 static char *reg_sign_bit_copies;
 293
 294 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
 295    It is zero while computing them and after combine has completed.  This
 296    former test prevents propagating values based on previously set values,
 297    which can be incorrect if a variable is modified in a loop.  */
 298
 299 static int nonzero_sign_valid;
 300
 301 /* These arrays are maintained in parallel with reg_last_set_value
 302    and are used to store the mode in which the register was last set,
 303    the bits that were known to be zero when it was last set, and the
 304    number of sign bits copies it was known to have when it was last set.  */
 305
 306 static enum machine_mode *reg_last_set_mode;
 307 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
 308 static char *reg_last_set_sign_bit_copies;
 309 \f
 310 /* Record one modification to rtl structure
 311    to be undone by storing old_contents into *where.
 312    is_int is 1 if the contents are an int.  */
 313
 314 struct undo
 315 {
 316   struct undo *next;
 317   int is_int;
 318   union {rtx r; int i;} old_contents;
 319   union {rtx *r; int *i;} where;
 320 };
 321
 322 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 323    num_undo says how many are currently recorded.
 324
 325    storage is nonzero if we must undo the allocation of new storage.
 326    The value of storage is what to pass to obfree.
 327
 328    other_insn is nonzero if we have modified some other insn in the process
 329    of working on subst_insn.  It must be verified too.
 330
 331    previous_undos is the value of undobuf.undos when we started processing
 332    this substitution.  This will prevent gen_rtx_combine from re-used a piece
 333    from the previous expression.  Doing so can produce circular rtl
 334    structures.  */
 335
 336 struct undobuf
 337 {
 338   char *storage;
 339   struct undo *undos;
 340   struct undo *frees;
 341   struct undo *previous_undos;
 342   rtx other_insn;
 343 };
 344
 345 static struct undobuf undobuf;
 346
 347 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 348    insn.  The substitution can be undone by undo_all.  If INTO is already
 349    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 350    also call SUBST, we have to compute it before we put anything into
 351    the undo table.  */
 352
 353 #define SUBST(INTO, NEWVAL)  \
 354  do { rtx _new = (NEWVAL);                                      \
 355       struct undo *_buf;                                        \
 356                                                                 \
 357       if (undobuf.frees)                                        \
 358         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 359       else                                                      \
 360         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 361                                                                 \
 362       _buf->is_int = 0;                                         \
 363       _buf->where.r = &INTO;                                    \
 364       _buf->old_contents.r = INTO;                              \
 365       INTO = _new;                                              \
 366       if (_buf->old_contents.r == INTO)                         \
 367         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 368       else                                                      \
 369         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 370     } while (0)
 371
 372 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 373    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 374    not safe.  */
 375
 376 #define SUBST_INT(INTO, NEWVAL)  \
 377  do { struct undo *_buf;                                        \
 378                                                                 \
 379       if (undobuf.frees)                                        \
 380         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 381       else                                                      \
 382         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 383                                                                 \
 384       _buf->is_int = 1;                                         \
 385       _buf->where.i = (int *) &INTO;                            \
 386       _buf->old_contents.i = INTO;                              \
 387       INTO = NEWVAL;                                            \
 388       if (_buf->old_contents.i == INTO)                         \
 389         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 390       else                                                      \
 391         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 392      } while (0)
 393
 394 /* Number of times the pseudo being substituted for
 395    was found and replaced.  */
 396
 397 static int n_occurrences;
 398
 399 static void init_reg_last_arrays        PROTO((void));
 400 static void setup_incoming_promotions   PROTO((void));
 401 static void set_nonzero_bits_and_sign_copies  PROTO((rtx, rtx));
 402 static int can_combine_p        PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
 403 static int sets_function_arg_p  PROTO((rtx));
 404 static int combinable_i3pat     PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
 405 static rtx try_combine          PROTO((rtx, rtx, rtx));
 406 static void undo_all            PROTO((void));
 407 static rtx *find_split_point    PROTO((rtx *, rtx));
 408 static rtx subst                PROTO((rtx, rtx, rtx, int, int));
 409 static rtx simplify_rtx         PROTO((rtx, enum machine_mode, int, int));
 410 static rtx simplify_if_then_else  PROTO((rtx));
 411 static rtx simplify_set         PROTO((rtx));
 412 static rtx simplify_logical     PROTO((rtx, int));
 413 static rtx expand_compound_operation  PROTO((rtx));
 414 static rtx expand_field_assignment  PROTO((rtx));
 415 static rtx make_extraction      PROTO((enum machine_mode, rtx, int, rtx, int,
 416                                        int, int, int));
 417 static rtx extract_left_shift   PROTO((rtx, int));
 418 static rtx make_compound_operation  PROTO((rtx, enum rtx_code));
 419 static int get_pos_from_mask    PROTO((unsigned HOST_WIDE_INT, int *));
 420 static rtx force_to_mode        PROTO((rtx, enum machine_mode,
 421                                        unsigned HOST_WIDE_INT, rtx, int));
 422 static rtx if_then_else_cond    PROTO((rtx, rtx *, rtx *));
 423 static rtx known_cond           PROTO((rtx, enum rtx_code, rtx, rtx));
 424 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
 425 static rtx make_field_assignment  PROTO((rtx));
 426 static rtx apply_distributive_law  PROTO((rtx));
 427 static rtx simplify_and_const_int  PROTO((rtx, enum machine_mode, rtx,
 428                                           unsigned HOST_WIDE_INT));
 429 static unsigned HOST_WIDE_INT nonzero_bits  PROTO((rtx, enum machine_mode));
 430 static int num_sign_bit_copies  PROTO((rtx, enum machine_mode));
 431 static int merge_outer_ops      PROTO((enum rtx_code *, HOST_WIDE_INT *,
 432                                        enum rtx_code, HOST_WIDE_INT,
 433                                        enum machine_mode, int *));
 434 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
 435                                        rtx, int));
 436 static int recog_for_combine    PROTO((rtx *, rtx, rtx *, int *));
 437 static rtx gen_lowpart_for_combine  PROTO((enum machine_mode, rtx));
 438 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
 439                                   ...));
 440 static rtx gen_binary           PROTO((enum rtx_code, enum machine_mode,
 441                                        rtx, rtx));
 442 static rtx gen_unary            PROTO((enum rtx_code, enum machine_mode,
 443                                        enum machine_mode, rtx));
 444 static enum rtx_code simplify_comparison  PROTO((enum rtx_code, rtx *, rtx *));
 445 static int reversible_comparison_p  PROTO((rtx));
 446 static void update_table_tick   PROTO((rtx));
 447 static void record_value_for_reg  PROTO((rtx, rtx, rtx));
 448 static void record_dead_and_set_regs_1  PROTO((rtx, rtx));
 449 static void record_dead_and_set_regs  PROTO((rtx));
 450 static int get_last_value_validate  PROTO((rtx *, rtx, int, int));
 451 static rtx get_last_value       PROTO((rtx));
 452 static int use_crosses_set_p    PROTO((rtx, int));
 453 static void reg_dead_at_p_1     PROTO((rtx, rtx));
 454 static int reg_dead_at_p        PROTO((rtx, rtx));
 455 static void move_deaths         PROTO((rtx, rtx, int, rtx, rtx *));
 456 static int reg_bitfield_target_p  PROTO((rtx, rtx));
 457 static void distribute_notes    PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
 458 static void distribute_links    PROTO((rtx));
 459 static void mark_used_regs_combine PROTO((rtx));
 460 static int insn_cuid            PROTO((rtx));
 461 \f
 462 /* Main entry point for combiner.  F is the first insn of the function.
 463    NREGS is the first unused pseudo-reg number.  */
 464
 465 void
 466 combine_instructions (f, nregs)
 467      rtx f;
 468      int nregs;
 469 {
 470   register rtx insn, next;
 471 #ifdef HAVE_cc0
 472   register rtx prev;
 473 #endif
 474   register int i;
 475   register rtx links, nextlinks;
 476
 477   combine_attempts = 0;
 478   combine_merges = 0;
 479   combine_extras = 0;
 480   combine_successes = 0;
 481   undobuf.undos = undobuf.previous_undos = 0;
 482
 483   combine_max_regno = nregs;
 484
 485   reg_nonzero_bits
 486     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 487   reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
 488
 489   bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 490   bzero (reg_sign_bit_copies, nregs * sizeof (char));
 491
 492   reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
 493   reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
 494   reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
 495   reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
 496   reg_last_set_label = (int *) alloca (nregs * sizeof (int));
 497   reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
 498   reg_last_set_mode
 499     = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
 500   reg_last_set_nonzero_bits
 501     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 502   reg_last_set_sign_bit_copies
 503     = (char *) alloca (nregs * sizeof (char));
 504
 505   init_reg_last_arrays ();
 506
 507   init_recog_no_volatile ();
 508
 509   /* Compute maximum uid value so uid_cuid can be allocated.  */
 510
 511   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 512     if (INSN_UID (insn) > i)
 513       i = INSN_UID (insn);
 514
 515   uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
 516   max_uid_cuid = i;
 517
 518   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 519
 520   /* Don't use reg_nonzero_bits when computing it.  This can cause problems
 521      when, for example, we have j <<= 1 in a loop.  */
 522
 523   nonzero_sign_valid = 0;
 524
 525   /* Compute the mapping from uids to cuids.
 526      Cuids are numbers assigned to insns, like uids,
 527      except that cuids increase monotonically through the code.
 528
 529      Scan all SETs and see if we can deduce anything about what
 530      bits are known to be zero for some registers and how many copies
 531      of the sign bit are known to exist for those registers.
 532
 533      Also set any known values so that we can use it while searching
 534      for what bits are known to be set.  */
 535
 536   label_tick = 1;
 537
 538   /* We need to initialize it here, because record_dead_and_set_regs may call
 539      get_last_value.  */
 540   subst_prev_insn = NULL_RTX;
 541
 542   setup_incoming_promotions ();
 543
 544   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 545     {
 546       uid_cuid[INSN_UID (insn)] = ++i;
 547       subst_low_cuid = i;
 548       subst_insn = insn;
 549
 550       if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 551         {
 552           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
 553           record_dead_and_set_regs (insn);
 554
 555 #ifdef AUTO_INC_DEC
 556           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 557             if (REG_NOTE_KIND (links) == REG_INC)
 558               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
 559 #endif
 560         }
 561
 562       if (GET_CODE (insn) == CODE_LABEL)
 563         label_tick++;
 564     }
 565
 566   nonzero_sign_valid = 1;
 567
 568   /* Now scan all the insns in forward order.  */
 569
 570   this_basic_block = -1;
 571   label_tick = 1;
 572   last_call_cuid = 0;
 573   mem_last_set = 0;
 574   init_reg_last_arrays ();
 575   setup_incoming_promotions ();
 576
 577   for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
 578     {
 579       next = 0;
 580
 581       /* If INSN starts a new basic block, update our basic block number.  */
 582       if (this_basic_block + 1 < n_basic_blocks
 583           && basic_block_head[this_basic_block + 1] == insn)
 584         this_basic_block++;
 585
 586       if (GET_CODE (insn) == CODE_LABEL)
 587         label_tick++;
 588
 589       else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 590         {
 591           /* Try this insn with each insn it links back to.  */
 592
 593           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 594             if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
 595               goto retry;
 596
 597           /* Try each sequence of three linked insns ending with this one.  */
 598
 599           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 600             for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
 601                  nextlinks = XEXP (nextlinks, 1))
 602               if ((next = try_combine (insn, XEXP (links, 0),
 603                                        XEXP (nextlinks, 0))) != 0)
 604                 goto retry;
 605
 606 #ifdef HAVE_cc0
 607           /* Try to combine a jump insn that uses CC0
 608              with a preceding insn that sets CC0, and maybe with its
 609              logical predecessor as well.
 610              This is how we make decrement-and-branch insns.
 611              We need this special code because data flow connections
 612              via CC0 do not get entered in LOG_LINKS.  */
 613
 614           if (GET_CODE (insn) == JUMP_INSN
 615               && (prev = prev_nonnote_insn (insn)) != 0
 616               && GET_CODE (prev) == INSN
 617               && sets_cc0_p (PATTERN (prev)))
 618             {
 619               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 620                 goto retry;
 621
 622               for (nextlinks = LOG_LINKS (prev); nextlinks;
 623                    nextlinks = XEXP (nextlinks, 1))
 624                 if ((next = try_combine (insn, prev,
 625                                          XEXP (nextlinks, 0))) != 0)
 626                   goto retry;
 627             }
 628
 629           /* Do the same for an insn that explicitly references CC0.  */
 630           if (GET_CODE (insn) == INSN
 631               && (prev = prev_nonnote_insn (insn)) != 0
 632               && GET_CODE (prev) == INSN
 633               && sets_cc0_p (PATTERN (prev))
 634               && GET_CODE (PATTERN (insn)) == SET
 635               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 636             {
 637               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 638                 goto retry;
 639
 640               for (nextlinks = LOG_LINKS (prev); nextlinks;
 641                    nextlinks = XEXP (nextlinks, 1))
 642                 if ((next = try_combine (insn, prev,
 643                                          XEXP (nextlinks, 0))) != 0)
 644                   goto retry;
 645             }
 646
 647           /* Finally, see if any of the insns that this insn links to
 648              explicitly references CC0.  If so, try this insn, that insn,
 649              and its predecessor if it sets CC0.  */
 650           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 651             if (GET_CODE (XEXP (links, 0)) == INSN
 652                 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 653                 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 654                 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 655                 && GET_CODE (prev) == INSN
 656                 && sets_cc0_p (PATTERN (prev))
 657                 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
 658               goto retry;
 659 #endif
 660
 661           /* Try combining an insn with two different insns whose results it
 662              uses.  */
 663           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 664             for (nextlinks = XEXP (links, 1); nextlinks;
 665                  nextlinks = XEXP (nextlinks, 1))
 666               if ((next = try_combine (insn, XEXP (links, 0),
 667                                        XEXP (nextlinks, 0))) != 0)
 668                 goto retry;
 669
 670           if (GET_CODE (insn) != NOTE)
 671             record_dead_and_set_regs (insn);
 672
 673         retry:
 674           ;
 675         }
 676     }
 677
 678   total_attempts += combine_attempts;
 679   total_merges += combine_merges;
 680   total_extras += combine_extras;
 681   total_successes += combine_successes;
 682
 683   nonzero_sign_valid = 0;
 684 }
 685
 686 /* Wipe the reg_last_xxx arrays in preparation for another pass.  */
 687
 688 static void
 689 init_reg_last_arrays ()
 690 {
 691   int nregs = combine_max_regno;
 692
 693   bzero ((char *) reg_last_death, nregs * sizeof (rtx));
 694   bzero ((char *) reg_last_set, nregs * sizeof (rtx));
 695   bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
 696   bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
 697   bzero ((char *) reg_last_set_label, nregs * sizeof (int));
 698   bzero (reg_last_set_invalid, nregs * sizeof (char));
 699   bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
 700   bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 701   bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
 702 }
 703 \f
 704 /* Set up any promoted values for incoming argument registers.  */
 705
 706 static void
 707 setup_incoming_promotions ()
 708 {
 709 #ifdef PROMOTE_FUNCTION_ARGS
 710   int regno;
 711   rtx reg;
 712   enum machine_mode mode;
 713   int unsignedp;
 714   rtx first = get_insns ();
 715
 716   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 717     if (FUNCTION_ARG_REGNO_P (regno)
 718         && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 719       {
 720         record_value_for_reg
 721           (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
 722                                        : SIGN_EXTEND),
 723                                       GET_MODE (reg),
 724                                       gen_rtx_CLOBBER (mode, const0_rtx)));
 725       }
 726 #endif
 727 }
 728 \f
 729 /* Called via note_stores.  If X is a pseudo that is narrower than
 730    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 731
 732    If we are setting only a portion of X and we can't figure out what
 733    portion, assume all bits will be used since we don't know what will
 734    be happening.
 735
 736    Similarly, set how many bits of X are known to be copies of the sign bit
 737    at all locations in the function.  This is the smallest number implied
 738    by any set of X.  */
 739
 740 static void
 741 set_nonzero_bits_and_sign_copies (x, set)
 742      rtx x;
 743      rtx set;
 744 {
 745   int num;
 746
 747   if (GET_CODE (x) == REG
 748       && REGNO (x) >= FIRST_PSEUDO_REGISTER
 749       /* If this register is undefined at the start of the file, we can't
 750          say what its contents were.  */
 751       && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
 752       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
 753     {
 754       if (set == 0 || GET_CODE (set) == CLOBBER)
 755         {
 756           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 757           reg_sign_bit_copies[REGNO (x)] = 1;
 758           return;
 759         }
 760
 761       /* If this is a complex assignment, see if we can convert it into a
 762          simple assignment.  */
 763       set = expand_field_assignment (set);
 764
 765       /* If this is a simple assignment, or we have a paradoxical SUBREG,
 766          set what we know about X.  */
 767
 768       if (SET_DEST (set) == x
 769           || (GET_CODE (SET_DEST (set)) == SUBREG
 770               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
 771                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
 772               && SUBREG_REG (SET_DEST (set)) == x))
 773         {
 774           rtx src = SET_SRC (set);
 775
 776 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
 777           /* If X is narrower than a word and SRC is a non-negative
 778              constant that would appear negative in the mode of X,
 779              sign-extend it for use in reg_nonzero_bits because some
 780              machines (maybe most) will actually do the sign-extension
 781              and this is the conservative approach.
 782
 783              ??? For 2.5, try to tighten up the MD files in this regard
 784              instead of this kludge.  */
 785
 786           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
 787               && GET_CODE (src) == CONST_INT
 788               && INTVAL (src) > 0
 789               && 0 != (INTVAL (src)
 790                        & ((HOST_WIDE_INT) 1
 791                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 792             src = GEN_INT (INTVAL (src)
 793                            | ((HOST_WIDE_INT) (-1)
 794                               << GET_MODE_BITSIZE (GET_MODE (x))));
 795 #endif
 796
 797           reg_nonzero_bits[REGNO (x)]
 798             |= nonzero_bits (src, nonzero_bits_mode);
 799           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
 800           if (reg_sign_bit_copies[REGNO (x)] == 0
 801               || reg_sign_bit_copies[REGNO (x)] > num)
 802             reg_sign_bit_copies[REGNO (x)] = num;
 803         }
 804       else
 805         {
 806           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 807           reg_sign_bit_copies[REGNO (x)] = 1;
 808         }
 809     }
 810 }
 811 \f
 812 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
 813    insns that were previously combined into I3 or that will be combined
 814    into the merger of INSN and I3.
 815
 816    Return 0 if the combination is not allowed for any reason.
 817
 818    If the combination is allowed, *PDEST will be set to the single
 819    destination of INSN and *PSRC to the single source, and this function
 820    will return 1.  */
 821
 822 static int
 823 can_combine_p (insn, i3, pred, succ, pdest, psrc)
 824      rtx insn;
 825      rtx i3;
 826      rtx pred, succ;
 827      rtx *pdest, *psrc;
 828 {
 829   int i;
 830   rtx set = 0, src, dest;
 831   rtx p;
 832 #ifdef AUTO_INC_DEC
 833   rtx link;
 834 #endif
 835   int all_adjacent = (succ ? (next_active_insn (insn) == succ
 836                               && next_active_insn (succ) == i3)
 837                       : next_active_insn (insn) == i3);
 838
 839   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
 840      or a PARALLEL consisting of such a SET and CLOBBERs.
 841
 842      If INSN has CLOBBER parallel parts, ignore them for our processing.
 843      By definition, these happen during the execution of the insn.  When it
 844      is merged with another insn, all bets are off.  If they are, in fact,
 845      needed and aren't also supplied in I3, they may be added by
 846      recog_for_combine.  Otherwise, it won't match.
 847
 848      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
 849      note.
 850
 851      Get the source and destination of INSN.  If more than one, can't
 852      combine.  */
 853
 854   if (GET_CODE (PATTERN (insn)) == SET)
 855     set = PATTERN (insn);
 856   else if (GET_CODE (PATTERN (insn)) == PARALLEL
 857            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
 858     {
 859       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 860         {
 861           rtx elt = XVECEXP (PATTERN (insn), 0, i);
 862
 863           switch (GET_CODE (elt))
 864             {
 865             /* This is important to combine floating point insns
 866                for the SH4 port.  */
 867             case USE:
 868               /* Combining an isolated USE doesn't make sense.
 869                  We depend here on combinable_i3_pat to reject them.  */
 870               /* The code below this loop only verifies that the inputs of
 871                  the SET in INSN do not change.  We call reg_set_between_p
 872                  to verify that the REG in the USE does not change betweeen
 873                  I3 and INSN.
 874                  If the USE in INSN was for a pseudo register, the matching
 875                  insn pattern will likely match any register; combining this
 876                  with any other USE would only be safe if we knew that the
 877                  used registers have identical values, or if there was
 878                  something to tell them apart, e.g. different modes.  For
 879                  now, we forgo such compilcated tests and simply disallow
 880                  combining of USES of pseudo registers with any other USE.  */
 881               if (GET_CODE (XEXP (elt, 0)) == REG
 882                   && GET_CODE (PATTERN (i3)) == PARALLEL)
 883                 {
 884                   rtx i3pat = PATTERN (i3);
 885                   int i = XVECLEN (i3pat, 0) - 1;
 886                   int regno = REGNO (XEXP (elt, 0));
 887                   do
 888                     {
 889                       rtx i3elt = XVECEXP (i3pat, 0, i);
 890                       if (GET_CODE (i3elt) == USE
 891                           && GET_CODE (XEXP (i3elt, 0)) == REG
 892                           && (REGNO (XEXP (i3elt, 0)) == regno
 893                               ? reg_set_between_p (XEXP (elt, 0),
 894                                                    PREV_INSN (insn), i3)
 895                               : regno >= FIRST_PSEUDO_REGISTER))
 896                         return 0;
 897                     }
 898                   while (--i >= 0);
 899                 }
 900               break;
 901
 902               /* We can ignore CLOBBERs.  */
 903             case CLOBBER:
 904               break;
 905
 906             case SET:
 907               /* Ignore SETs whose result isn't used but not those that
 908                  have side-effects.  */
 909               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
 910                   && ! side_effects_p (elt))
 911                 break;
 912
 913               /* If we have already found a SET, this is a second one and
 914                  so we cannot combine with this insn.  */
 915               if (set)
 916                 return 0;
 917
 918               set = elt;
 919               break;
 920
 921             default:
 922               /* Anything else means we can't combine.  */
 923               return 0;
 924             }
 925         }
 926
 927       if (set == 0
 928           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
 929              so don't do anything with it.  */
 930           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
 931         return 0;
 932     }
 933   else
 934     return 0;
 935
 936   if (set == 0)
 937     return 0;
 938
 939   set = expand_field_assignment (set);
 940   src = SET_SRC (set), dest = SET_DEST (set);
 941
 942   /* Don't eliminate a store in the stack pointer.  */
 943   if (dest == stack_pointer_rtx
 944       /* If we couldn't eliminate a field assignment, we can't combine.  */
 945       || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
 946       /* Don't combine with an insn that sets a register to itself if it has
 947          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
 948       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
 949       /* Can't merge a function call.  */
 950       || GET_CODE (src) == CALL
 951       /* Don't eliminate a function call argument.  */
 952       || (GET_CODE (i3) == CALL_INSN
 953           && (find_reg_fusage (i3, USE, dest)
 954               || (GET_CODE (dest) == REG
 955                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
 956                   && global_regs[REGNO (dest)])))
 957       /* Don't substitute into an incremented register.  */
 958       || FIND_REG_INC_NOTE (i3, dest)
 959       || (succ && FIND_REG_INC_NOTE (succ, dest))
 960       /* Don't combine the end of a libcall into anything.  */
 961       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
 962       /* Make sure that DEST is not used after SUCC but before I3.  */
 963       || (succ && ! all_adjacent
 964           && reg_used_between_p (dest, succ, i3))
 965       /* Make sure that the value that is to be substituted for the register
 966          does not use any registers whose values alter in between.  However,
 967          If the insns are adjacent, a use can't cross a set even though we
 968          think it might (this can happen for a sequence of insns each setting
 969          the same destination; reg_last_set of that register might point to
 970          a NOTE).  If INSN has a REG_EQUIV note, the register is always
 971          equivalent to the memory so the substitution is valid even if there
 972          are intervening stores.  Also, don't move a volatile asm or
 973          UNSPEC_VOLATILE across any other insns.  */
 974       || (! all_adjacent
 975           && (((GET_CODE (src) != MEM
 976                 || ! find_reg_note (insn, REG_EQUIV, src))
 977                && use_crosses_set_p (src, INSN_CUID (insn)))
 978               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
 979               || GET_CODE (src) == UNSPEC_VOLATILE))
 980       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
 981          better register allocation by not doing the combine.  */
 982       || find_reg_note (i3, REG_NO_CONFLICT, dest)
 983       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
 984       /* Don't combine across a CALL_INSN, because that would possibly
 985          change whether the life span of some REGs crosses calls or not,
 986          and it is a pain to update that information.
 987          Exception: if source is a constant, moving it later can't hurt.
 988          Accept that special case, because it helps -fforce-addr a lot.  */
 989       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
 990     return 0;
 991
 992   /* DEST must either be a REG or CC0.  */
 993   if (GET_CODE (dest) == REG)
 994     {
 995       /* If register alignment is being enforced for multi-word items in all
 996          cases except for parameters, it is possible to have a register copy
 997          insn referencing a hard register that is not allowed to contain the
 998          mode being copied and which would not be valid as an operand of most
 999          insns.  Eliminate this problem by not combining with such an insn.
1000
1001          Also, on some machines we don't want to extend the life of a hard
1002          register.
1003
1004          This is the same test done in can_combine except that we don't test
1005          if SRC is a CALL operation to permit a hard register with
1006          SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1007          into account.  */
1008
1009       if (GET_CODE (src) == REG
1010           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1011                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1012               /* Don't extend the life of a hard register unless it is
1013                  user variable (if we have few registers) or it can't
1014                  fit into the desired register (meaning something special
1015                  is going on).
1016                  Also avoid substituting a return register into I3, because
1017                  reload can't handle a conflict with constraints of other
1018                  inputs.  */
1019               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1020                   && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1021                       || (SMALL_REGISTER_CLASSES
1022                           && ((! all_adjacent && ! REG_USERVAR_P (src))
1023                               || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1024                                   && ! REG_USERVAR_P (src))))))))
1025         return 0;
1026     }
1027   else if (GET_CODE (dest) != CC0)
1028     return 0;
1029
1030   /* Don't substitute for a register intended as a clobberable operand.
1031      Similarly, don't substitute an expression containing a register that
1032      will be clobbered in I3.  */
1033   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1034     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1035       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1036           && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1037                                        src)
1038               || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1039         return 0;
1040
1041   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1042      or not), reject, unless nothing volatile comes between it and I3 */
1043
1044   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1045     {
1046       /* Make sure succ doesn't contain a volatile reference.  */
1047       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1048         return 0;
1049
1050       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1051         if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1052           && p != succ && volatile_refs_p (PATTERN (p)))
1053         return 0;
1054     }
1055
1056   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1057      to be an explicit register variable, and was chosen for a reason.  */
1058
1059   if (GET_CODE (src) == ASM_OPERANDS
1060       && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1061     return 0;
1062
1063   /* If there are any volatile insns between INSN and I3, reject, because
1064      they might affect machine state.  */
1065
1066   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1067     if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1068         && p != succ && volatile_insn_p (PATTERN (p)))
1069       return 0;
1070
1071   /* If INSN or I2 contains an autoincrement or autodecrement,
1072      make sure that register is not used between there and I3,
1073      and not already used in I3 either.
1074      Also insist that I3 not be a jump; if it were one
1075      and the incremented register were spilled, we would lose.  */
1076
1077 #ifdef AUTO_INC_DEC
1078   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1079     if (REG_NOTE_KIND (link) == REG_INC
1080         && (GET_CODE (i3) == JUMP_INSN
1081             || reg_used_between_p (XEXP (link, 0), insn, i3)
1082             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1083       return 0;
1084 #endif
1085
1086 #ifdef HAVE_cc0
1087   /* Don't combine an insn that follows a CC0-setting insn.
1088      An insn that uses CC0 must not be separated from the one that sets it.
1089      We do, however, allow I2 to follow a CC0-setting insn if that insn
1090      is passed as I1; in that case it will be deleted also.
1091      We also allow combining in this case if all the insns are adjacent
1092      because that would leave the two CC0 insns adjacent as well.
1093      It would be more logical to test whether CC0 occurs inside I1 or I2,
1094      but that would be much slower, and this ought to be equivalent.  */
1095
1096   p = prev_nonnote_insn (insn);
1097   if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1098       && ! all_adjacent)
1099     return 0;
1100 #endif
1101
1102   /* If we get here, we have passed all the tests and the combination is
1103      to be allowed.  */
1104
1105   *pdest = dest;
1106   *psrc = src;
1107
1108   return 1;
1109 }
1110 \f
1111 /* Check if PAT is an insn - or a part of it - used to set up an
1112    argument for a function in a hard register.  */
1113
1114 static int
1115 sets_function_arg_p (pat)
1116      rtx pat;
1117 {
1118   int i;
1119   rtx inner_dest;
1120
1121   switch (GET_CODE (pat))
1122     {
1123     case INSN:
1124       return sets_function_arg_p (PATTERN (pat));
1125
1126     case PARALLEL:
1127       for (i = XVECLEN (pat, 0); --i >= 0;)
1128         if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1129           return 1;
1130
1131       break;
1132
1133     case SET:
1134       inner_dest = SET_DEST (pat);
1135       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1136              || GET_CODE (inner_dest) == SUBREG
1137              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1138         inner_dest = XEXP (inner_dest, 0);
1139
1140       return (GET_CODE (inner_dest) == REG
1141               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1142               && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1143
1144     default:
1145       break;
1146     }
1147
1148   return 0;
1149 }
1150
1151 /* LOC is the location within I3 that contains its pattern or the component
1152    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1153
1154    One problem is if I3 modifies its output, as opposed to replacing it
1155    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1156    so would produce an insn that is not equivalent to the original insns.
1157
1158    Consider:
1159
1160          (set (reg:DI 101) (reg:DI 100))
1161          (set (subreg:SI (reg:DI 101) 0) <foo>)
1162
1163    This is NOT equivalent to:
1164
1165          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1166                     (set (reg:DI 101) (reg:DI 100))])
1167
1168    Not only does this modify 100 (in which case it might still be valid
1169    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1170
1171    We can also run into a problem if I2 sets a register that I1
1172    uses and I1 gets directly substituted into I3 (not via I2).  In that
1173    case, we would be getting the wrong value of I2DEST into I3, so we
1174    must reject the combination.  This case occurs when I2 and I1 both
1175    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1176    If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1177    of a SET must prevent combination from occurring.
1178
1179    On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1180    if the destination of a SET is a hard register that isn't a user
1181    variable.
1182
1183    Before doing the above check, we first try to expand a field assignment
1184    into a set of logical operations.
1185
1186    If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1187    we place a register that is both set and used within I3.  If more than one
1188    such register is detected, we fail.
1189
1190    Return 1 if the combination is valid, zero otherwise.  */
1191
1192 static int
1193 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1194      rtx i3;
1195      rtx *loc;
1196      rtx i2dest;
1197      rtx i1dest;
1198      int i1_not_in_src;
1199      rtx *pi3dest_killed;
1200 {
1201   rtx x = *loc;
1202
1203   if (GET_CODE (x) == SET)
1204     {
1205       rtx set = expand_field_assignment (x);
1206       rtx dest = SET_DEST (set);
1207       rtx src = SET_SRC (set);
1208       rtx inner_dest = dest;
1209
1210 #if 0
1211       rtx inner_src = src;
1212 #endif
1213
1214       SUBST (*loc, set);
1215
1216       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1217              || GET_CODE (inner_dest) == SUBREG
1218              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1219         inner_dest = XEXP (inner_dest, 0);
1220
1221   /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1222      was added.  */
1223 #if 0
1224       while (GET_CODE (inner_src) == STRICT_LOW_PART
1225              || GET_CODE (inner_src) == SUBREG
1226              || GET_CODE (inner_src) == ZERO_EXTRACT)
1227         inner_src = XEXP (inner_src, 0);
1228
1229       /* If it is better that two different modes keep two different pseudos,
1230          avoid combining them.  This avoids producing the following pattern
1231          on a 386:
1232           (set (subreg:SI (reg/v:QI 21) 0)
1233                (lshiftrt:SI (reg/v:SI 20)
1234                    (const_int 24)))
1235          If that were made, reload could not handle the pair of
1236          reg 20/21, since it would try to get any GENERAL_REGS
1237          but some of them don't handle QImode.  */
1238
1239       if (rtx_equal_p (inner_src, i2dest)
1240           && GET_CODE (inner_dest) == REG
1241           && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1242         return 0;
1243 #endif
1244
1245       /* Check for the case where I3 modifies its output, as
1246          discussed above.  */
1247       if ((inner_dest != dest
1248            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1249                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1250
1251           /* This is the same test done in can_combine_p except that we
1252              allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1253              CALL operation. Moreover, we can't test all_adjacent; we don't
1254              have to, since this instruction will stay in place, thus we are
1255              not considering increasing the lifetime of INNER_DEST.
1256
1257              Also, if this insn sets a function argument, combining it with
1258              something that might need a spill could clobber a previous
1259              function argument; the all_adjacent test in can_combine_p also
1260              checks this; here, we do a more specific test for this case.  */
1261
1262           || (GET_CODE (inner_dest) == REG
1263               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1264               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1265                                         GET_MODE (inner_dest))
1266                  || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1267                      && ! REG_USERVAR_P (inner_dest)
1268                      && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1269                          || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1270                              && i3 != 0
1271                              && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1272           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1273         return 0;
1274
1275       /* If DEST is used in I3, it is being killed in this insn,
1276          so record that for later.
1277          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1278          STACK_POINTER_REGNUM, since these are always considered to be
1279          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1280       if (pi3dest_killed && GET_CODE (dest) == REG
1281           && reg_referenced_p (dest, PATTERN (i3))
1282           && REGNO (dest) != FRAME_POINTER_REGNUM
1283 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1284           && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1285 #endif
1286 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1287           && (REGNO (dest) != ARG_POINTER_REGNUM
1288               || ! fixed_regs [REGNO (dest)])
1289 #endif
1290           && REGNO (dest) != STACK_POINTER_REGNUM)
1291         {
1292           if (*pi3dest_killed)
1293             return 0;
1294
1295           *pi3dest_killed = dest;
1296         }
1297     }
1298
1299   else if (GET_CODE (x) == PARALLEL)
1300     {
1301       int i;
1302
1303       for (i = 0; i < XVECLEN (x, 0); i++)
1304         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1305                                 i1_not_in_src, pi3dest_killed))
1306           return 0;
1307     }
1308
1309   return 1;
1310 }
1311 \f
1312 /* Try to combine the insns I1 and I2 into I3.
1313    Here I1 and I2 appear earlier than I3.
1314    I1 can be zero; then we combine just I2 into I3.
1315
1316    It we are combining three insns and the resulting insn is not recognized,
1317    try splitting it into two insns.  If that happens, I2 and I3 are retained
1318    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1319    are pseudo-deleted.
1320
1321    Return 0 if the combination does not work.  Then nothing is changed.
1322    If we did the combination, return the insn at which combine should
1323    resume scanning.  */
1324
1325 static rtx
1326 try_combine (i3, i2, i1)
1327      register rtx i3, i2, i1;
1328 {
1329   /* New patterns for I3 and I3, respectively.  */
1330   rtx newpat, newi2pat = 0;
1331   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1332   int added_sets_1, added_sets_2;
1333   /* Total number of SETs to put into I3.  */
1334   int total_sets;
1335   /* Nonzero is I2's body now appears in I3.  */
1336   int i2_is_used;
1337   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1338   int insn_code_number, i2_code_number, other_code_number;
1339   /* Contains I3 if the destination of I3 is used in its source, which means
1340      that the old life of I3 is being killed.  If that usage is placed into
1341      I2 and not in I3, a REG_DEAD note must be made.  */
1342   rtx i3dest_killed = 0;
1343   /* SET_DEST and SET_SRC of I2 and I1.  */
1344   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1345   /* PATTERN (I2), or a copy of it in certain cases.  */
1346   rtx i2pat;
1347   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1348   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1349   int i1_feeds_i3 = 0;
1350   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1351   rtx new_i3_notes, new_i2_notes;
1352   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1353   int i3_subst_into_i2 = 0;
1354   /* Notes that I1, I2 or I3 is a MULT operation.  */
1355   int have_mult = 0;
1356   /* Number of clobbers of SCRATCH we had to add.  */
1357   int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1358
1359   int maxreg;
1360   rtx temp;
1361   register rtx link;
1362   int i;
1363
1364   /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1365      This can occur when flow deletes an insn that it has merged into an
1366      auto-increment address.  We also can't do anything if I3 has a
1367      REG_LIBCALL note since we don't want to disrupt the contiguity of a
1368      libcall.  */
1369
1370   if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1371       || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1372       || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1373       || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1374     return 0;
1375
1376   combine_attempts++;
1377
1378   undobuf.undos = undobuf.previous_undos = 0;
1379   undobuf.other_insn = 0;
1380
1381   /* Save the current high-water-mark so we can free storage if we didn't
1382      accept this combination.  */
1383   undobuf.storage = (char *) oballoc (0);
1384
1385   /* Reset the hard register usage information.  */
1386   CLEAR_HARD_REG_SET (newpat_used_regs);
1387
1388   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1389      code below, set I1 to be the earlier of the two insns.  */
1390   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1391     temp = i1, i1 = i2, i2 = temp;
1392
1393   added_links_insn = 0;
1394
1395   /* First check for one important special-case that the code below will
1396      not handle.  Namely, the case where I1 is zero, I2 has multiple sets,
1397      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1398      we may be able to replace that destination with the destination of I3.
1399      This occurs in the common code where we compute both a quotient and
1400      remainder into a structure, in which case we want to do the computation
1401      directly into the structure to avoid register-register copies.
1402
1403      We make very conservative checks below and only try to handle the
1404      most common cases of this.  For example, we only handle the case
1405      where I2 and I3 are adjacent to avoid making difficult register
1406      usage tests.  */
1407
1408   if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1409       && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1410       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1411       && (! SMALL_REGISTER_CLASSES
1412           || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1413               || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1414               || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1415       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1416       && GET_CODE (PATTERN (i2)) == PARALLEL
1417       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1418       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1419          below would need to check what is inside (and reg_overlap_mentioned_p
1420          doesn't support those codes anyway).  Don't allow those destinations;
1421          the resulting insn isn't likely to be recognized anyway.  */
1422       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1423       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1424       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1425                                     SET_DEST (PATTERN (i3)))
1426       && next_real_insn (i2) == i3)
1427     {
1428       rtx p2 = PATTERN (i2);
1429
1430       /* Make sure that the destination of I3,
1431          which we are going to substitute into one output of I2,
1432          is not used within another output of I2.  We must avoid making this:
1433          (parallel [(set (mem (reg 69)) ...)
1434                     (set (reg 69) ...)])
1435          which is not well-defined as to order of actions.
1436          (Besides, reload can't handle output reloads for this.)
1437
1438          The problem can also happen if the dest of I3 is a memory ref,
1439          if another dest in I2 is an indirect memory ref.  */
1440       for (i = 0; i < XVECLEN (p2, 0); i++)
1441         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1442              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1443             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1444                                         SET_DEST (XVECEXP (p2, 0, i))))
1445           break;
1446
1447       if (i == XVECLEN (p2, 0))
1448         for (i = 0; i < XVECLEN (p2, 0); i++)
1449           if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1450             {
1451               combine_merges++;
1452
1453               subst_insn = i3;
1454               subst_low_cuid = INSN_CUID (i2);
1455
1456               added_sets_2 = added_sets_1 = 0;
1457               i2dest = SET_SRC (PATTERN (i3));
1458
1459               /* Replace the dest in I2 with our dest and make the resulting
1460                  insn the new pattern for I3.  Then skip to where we
1461                  validate the pattern.  Everything was set up above.  */
1462               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1463                      SET_DEST (PATTERN (i3)));
1464
1465               newpat = p2;
1466               i3_subst_into_i2 = 1;
1467               goto validate_replacement;
1468             }
1469     }
1470
1471 #ifndef HAVE_cc0
1472   /* If we have no I1 and I2 looks like:
1473         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1474                    (set Y OP)])
1475      make up a dummy I1 that is
1476         (set Y OP)
1477      and change I2 to be
1478         (set (reg:CC X) (compare:CC Y (const_int 0)))
1479
1480      (We can ignore any trailing CLOBBERs.)
1481
1482      This undoes a previous combination and allows us to match a branch-and-
1483      decrement insn.  */
1484
1485   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1486       && XVECLEN (PATTERN (i2), 0) >= 2
1487       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1488       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1489           == MODE_CC)
1490       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1491       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1492       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1493       && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1494       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1495                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1496     {
1497       for (i =  XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1498         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1499           break;
1500
1501       if (i == 1)
1502         {
1503           /* We make I1 with the same INSN_UID as I2.  This gives it
1504              the same INSN_CUID for value tracking.  Our fake I1 will
1505              never appear in the insn stream so giving it the same INSN_UID
1506              as I2 will not cause a problem.  */
1507
1508           subst_prev_insn = i1
1509             = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1510                             XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1511                             NULL_RTX);
1512
1513           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1514           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1515                  SET_DEST (PATTERN (i1)));
1516         }
1517     }
1518 #endif
1519
1520   /* Verify that I2 and I1 are valid for combining.  */
1521   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1522       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1523     {
1524       undo_all ();
1525       return 0;
1526     }
1527
1528   /* Record whether I2DEST is used in I2SRC and similarly for the other
1529      cases.  Knowing this will help in register status updating below.  */
1530   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1531   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1532   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1533
1534   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
1535      in I2SRC.  */
1536   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1537
1538   /* Ensure that I3's pattern can be the destination of combines.  */
1539   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1540                           i1 && i2dest_in_i1src && i1_feeds_i3,
1541                           &i3dest_killed))
1542     {
1543       undo_all ();
1544       return 0;
1545     }
1546
1547   /* See if any of the insns is a MULT operation.  Unless one is, we will
1548      reject a combination that is, since it must be slower.  Be conservative
1549      here.  */
1550   if (GET_CODE (i2src) == MULT
1551       || (i1 != 0 && GET_CODE (i1src) == MULT)
1552       || (GET_CODE (PATTERN (i3)) == SET
1553           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1554     have_mult = 1;
1555
1556   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1557      We used to do this EXCEPT in one case: I3 has a post-inc in an
1558      output operand.  However, that exception can give rise to insns like
1559         mov r3,(r3)+
1560      which is a famous insn on the PDP-11 where the value of r3 used as the
1561      source was model-dependent.  Avoid this sort of thing.  */
1562
1563 #if 0
1564   if (!(GET_CODE (PATTERN (i3)) == SET
1565         && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1566         && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1567         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1568             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1569     /* It's not the exception.  */
1570 #endif
1571 #ifdef AUTO_INC_DEC
1572     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1573       if (REG_NOTE_KIND (link) == REG_INC
1574           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1575               || (i1 != 0
1576                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1577         {
1578           undo_all ();
1579           return 0;
1580         }
1581 #endif
1582
1583   /* See if the SETs in I1 or I2 need to be kept around in the merged
1584      instruction: whenever the value set there is still needed past I3.
1585      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1586
1587      For the SET in I1, we have two cases:  If I1 and I2 independently
1588      feed into I3, the set in I1 needs to be kept around if I1DEST dies
1589      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
1590      in I1 needs to be kept around unless I1DEST dies or is set in either
1591      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
1592      I1DEST.  If so, we know I1 feeds into I2.  */
1593
1594   added_sets_2 = ! dead_or_set_p (i3, i2dest);
1595
1596   added_sets_1
1597     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1598                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1599
1600   /* If the set in I2 needs to be kept around, we must make a copy of
1601      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1602      PATTERN (I2), we are only substituting for the original I1DEST, not into
1603      an already-substituted copy.  This also prevents making self-referential
1604      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1605      I2DEST.  */
1606
1607   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1608            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1609            : PATTERN (i2));
1610
1611   if (added_sets_2)
1612     i2pat = copy_rtx (i2pat);
1613
1614   combine_merges++;
1615
1616   /* Substitute in the latest insn for the regs set by the earlier ones.  */
1617
1618   maxreg = max_reg_num ();
1619
1620   subst_insn = i3;
1621
1622   /* It is possible that the source of I2 or I1 may be performing an
1623      unneeded operation, such as a ZERO_EXTEND of something that is known
1624      to have the high part zero.  Handle that case by letting subst look at
1625      the innermost one of them.
1626
1627      Another way to do this would be to have a function that tries to
1628      simplify a single insn instead of merging two or more insns.  We don't
1629      do this because of the potential of infinite loops and because
1630      of the potential extra memory required.  However, doing it the way
1631      we are is a bit of a kludge and doesn't catch all cases.
1632
1633      But only do this if -fexpensive-optimizations since it slows things down
1634      and doesn't usually win.  */
1635
1636   if (flag_expensive_optimizations)
1637     {
1638       /* Pass pc_rtx so no substitutions are done, just simplifications.
1639          The cases that we are interested in here do not involve the few
1640          cases were is_replaced is checked.  */
1641       if (i1)
1642         {
1643           subst_low_cuid = INSN_CUID (i1);
1644           i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1645         }
1646       else
1647         {
1648           subst_low_cuid = INSN_CUID (i2);
1649           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1650         }
1651
1652       undobuf.previous_undos = undobuf.undos;
1653     }
1654
1655 #ifndef HAVE_cc0
1656   /* Many machines that don't use CC0 have insns that can both perform an
1657      arithmetic operation and set the condition code.  These operations will
1658      be represented as a PARALLEL with the first element of the vector
1659      being a COMPARE of an arithmetic operation with the constant zero.
1660      The second element of the vector will set some pseudo to the result
1661      of the same arithmetic operation.  If we simplify the COMPARE, we won't
1662      match such a pattern and so will generate an extra insn.   Here we test
1663      for this case, where both the comparison and the operation result are
1664      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1665      I2SRC.  Later we will make the PARALLEL that contains I2.  */
1666
1667   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1668       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1669       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1670       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1671     {
1672 #ifdef EXTRA_CC_MODES
1673       rtx *cc_use;
1674       enum machine_mode compare_mode;
1675 #endif
1676
1677       newpat = PATTERN (i3);
1678       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1679
1680       i2_is_used = 1;
1681
1682 #ifdef EXTRA_CC_MODES
1683       /* See if a COMPARE with the operand we substituted in should be done
1684          with the mode that is currently being used.  If not, do the same
1685          processing we do in `subst' for a SET; namely, if the destination
1686          is used only once, try to replace it with a register of the proper
1687          mode and also replace the COMPARE.  */
1688       if (undobuf.other_insn == 0
1689           && (cc_use = find_single_use (SET_DEST (newpat), i3,
1690                                         &undobuf.other_insn))
1691           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1692                                               i2src, const0_rtx))
1693               != GET_MODE (SET_DEST (newpat))))
1694         {
1695           int regno = REGNO (SET_DEST (newpat));
1696           rtx new_dest = gen_rtx_REG (compare_mode, regno);
1697
1698           if (regno < FIRST_PSEUDO_REGISTER
1699               || (REG_N_SETS (regno) == 1 && ! added_sets_2
1700                   && ! REG_USERVAR_P (SET_DEST (newpat))))
1701             {
1702               if (regno >= FIRST_PSEUDO_REGISTER)
1703                 SUBST (regno_reg_rtx[regno], new_dest);
1704
1705               SUBST (SET_DEST (newpat), new_dest);
1706               SUBST (XEXP (*cc_use, 0), new_dest);
1707               SUBST (SET_SRC (newpat),
1708                      gen_rtx_combine (COMPARE, compare_mode,
1709                                       i2src, const0_rtx));
1710             }
1711           else
1712             undobuf.other_insn = 0;
1713         }
1714 #endif
1715     }
1716   else
1717 #endif
1718     {
1719       n_occurrences = 0;                /* `subst' counts here */
1720
1721       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1722          need to make a unique copy of I2SRC each time we substitute it
1723          to avoid self-referential rtl.  */
1724
1725       subst_low_cuid = INSN_CUID (i2);
1726       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1727                       ! i1_feeds_i3 && i1dest_in_i1src);
1728       undobuf.previous_undos = undobuf.undos;
1729
1730       /* Record whether i2's body now appears within i3's body.  */
1731       i2_is_used = n_occurrences;
1732     }
1733
1734   /* If we already got a failure, don't try to do more.  Otherwise,
1735      try to substitute in I1 if we have it.  */
1736
1737   if (i1 && GET_CODE (newpat) != CLOBBER)
1738     {
1739       /* Before we can do this substitution, we must redo the test done
1740          above (see detailed comments there) that ensures  that I1DEST
1741          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
1742
1743       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1744                               0, NULL_PTR))
1745         {
1746           undo_all ();
1747           return 0;
1748         }
1749
1750       n_occurrences = 0;
1751       subst_low_cuid = INSN_CUID (i1);
1752       newpat = subst (newpat, i1dest, i1src, 0, 0);
1753       undobuf.previous_undos = undobuf.undos;
1754     }
1755
1756   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
1757      to count all the ways that I2SRC and I1SRC can be used.  */
1758   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1759        && i2_is_used + added_sets_2 > 1)
1760       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1761           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1762               > 1))
1763       /* Fail if we tried to make a new register (we used to abort, but there's
1764          really no reason to).  */
1765       || max_reg_num () != maxreg
1766       /* Fail if we couldn't do something and have a CLOBBER.  */
1767       || GET_CODE (newpat) == CLOBBER
1768       /* Fail if this new pattern is a MULT and we didn't have one before
1769          at the outer level.  */
1770       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1771           && ! have_mult))
1772     {
1773       undo_all ();
1774       return 0;
1775     }
1776
1777   /* If the actions of the earlier insns must be kept
1778      in addition to substituting them into the latest one,
1779      we must make a new PARALLEL for the latest insn
1780      to hold additional the SETs.  */
1781
1782   if (added_sets_1 || added_sets_2)
1783     {
1784       combine_extras++;
1785
1786       if (GET_CODE (newpat) == PARALLEL)
1787         {
1788           rtvec old = XVEC (newpat, 0);
1789           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1790           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1791           bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1792                  sizeof (old->elem[0]) * old->num_elem);
1793         }
1794       else
1795         {
1796           rtx old = newpat;
1797           total_sets = 1 + added_sets_1 + added_sets_2;
1798           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1799           XVECEXP (newpat, 0, 0) = old;
1800         }
1801
1802      if (added_sets_1)
1803        XVECEXP (newpat, 0, --total_sets)
1804          = (GET_CODE (PATTERN (i1)) == PARALLEL
1805             ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1806
1807      if (added_sets_2)
1808         {
1809           /* If there is no I1, use I2's body as is.  We used to also not do
1810              the subst call below if I2 was substituted into I3,
1811              but that could lose a simplification.  */
1812           if (i1 == 0)
1813             XVECEXP (newpat, 0, --total_sets) = i2pat;
1814           else
1815             /* See comment where i2pat is assigned.  */
1816             XVECEXP (newpat, 0, --total_sets)
1817               = subst (i2pat, i1dest, i1src, 0, 0);
1818         }
1819     }
1820
1821   /* We come here when we are replacing a destination in I2 with the
1822      destination of I3.  */
1823  validate_replacement:
1824
1825   /* Note which hard regs this insn has as inputs.  */
1826   mark_used_regs_combine (newpat);
1827
1828   /* Is the result of combination a valid instruction?  */
1829   insn_code_number
1830     = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1831
1832   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1833      the second SET's destination is a register that is unused.  In that case,
1834      we just need the first SET.   This can occur when simplifying a divmod
1835      insn.  We *must* test for this case here because the code below that
1836      splits two independent SETs doesn't handle this case correctly when it
1837      updates the register status.  Also check the case where the first
1838      SET's destination is unused.  That would not cause incorrect code, but
1839      does cause an unneeded insn to remain.  */
1840
1841   if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1842       && XVECLEN (newpat, 0) == 2
1843       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1844       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1845       && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1846       && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1847       && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1848       && asm_noperands (newpat) < 0)
1849     {
1850       newpat = XVECEXP (newpat, 0, 0);
1851       insn_code_number
1852         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1853     }
1854
1855   else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1856            && XVECLEN (newpat, 0) == 2
1857            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1858            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1859            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1860            && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1861            && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1862            && asm_noperands (newpat) < 0)
1863     {
1864       newpat = XVECEXP (newpat, 0, 1);
1865       insn_code_number
1866         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1867     }
1868
1869   /* If we were combining three insns and the result is a simple SET
1870      with no ASM_OPERANDS that wasn't recognized, try to split it into two
1871      insns.  There are two ways to do this.  It can be split using a
1872      machine-specific method (like when you have an addition of a large
1873      constant) or by combine in the function find_split_point.  */
1874
1875   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1876       && asm_noperands (newpat) < 0)
1877     {
1878       rtx m_split, *split;
1879       rtx ni2dest = i2dest;
1880
1881       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
1882          use I2DEST as a scratch register will help.  In the latter case,
1883          convert I2DEST to the mode of the source of NEWPAT if we can.  */
1884
1885       m_split = split_insns (newpat, i3);
1886
1887       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1888          inputs of NEWPAT.  */
1889
1890       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1891          possible to try that as a scratch reg.  This would require adding
1892          more code to make it work though.  */
1893
1894       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1895         {
1896           /* If I2DEST is a hard register or the only use of a pseudo,
1897              we can change its mode.  */
1898           if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1899               && GET_MODE (SET_DEST (newpat)) != VOIDmode
1900               && GET_CODE (i2dest) == REG
1901               && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1902                   || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1903                       && ! REG_USERVAR_P (i2dest))))
1904             ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
1905                                REGNO (i2dest));
1906
1907           m_split = split_insns
1908             (gen_rtx_PARALLEL (VOIDmode,
1909                                gen_rtvec (2, newpat,
1910                                           gen_rtx_CLOBBER (VOIDmode,
1911                                                            ni2dest))),
1912              i3);
1913         }
1914
1915       if (m_split && GET_CODE (m_split) == SEQUENCE
1916           && XVECLEN (m_split, 0) == 2
1917           && (next_real_insn (i2) == i3
1918               || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1919                                       INSN_CUID (i2))))
1920         {
1921           rtx i2set, i3set;
1922           rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1923           newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1924
1925           i3set = single_set (XVECEXP (m_split, 0, 1));
1926           i2set = single_set (XVECEXP (m_split, 0, 0));
1927
1928           /* In case we changed the mode of I2DEST, replace it in the
1929              pseudo-register table here.  We can't do it above in case this
1930              code doesn't get executed and we do a split the other way.  */
1931
1932           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1933             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1934
1935           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1936                                               &i2_scratches);
1937
1938           /* If I2 or I3 has multiple SETs, we won't know how to track
1939              register status, so don't use these insns.  If I2's destination
1940              is used between I2 and I3, we also can't use these insns.  */
1941
1942           if (i2_code_number >= 0 && i2set && i3set
1943               && (next_real_insn (i2) == i3
1944                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1945             insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1946                                                   &i3_scratches);
1947           if (insn_code_number >= 0)
1948             newpat = newi3pat;
1949
1950           /* It is possible that both insns now set the destination of I3.
1951              If so, we must show an extra use of it.  */
1952
1953           if (insn_code_number >= 0)
1954             {
1955               rtx new_i3_dest = SET_DEST (i3set);
1956               rtx new_i2_dest = SET_DEST (i2set);
1957
1958               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1959                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1960                      || GET_CODE (new_i3_dest) == SUBREG)
1961                 new_i3_dest = XEXP (new_i3_dest, 0);
1962
1963               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1964                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1965                      || GET_CODE (new_i2_dest) == SUBREG)
1966                 new_i2_dest = XEXP (new_i2_dest, 0);
1967
1968               if (GET_CODE (new_i3_dest) == REG
1969                   && GET_CODE (new_i2_dest) == REG
1970                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1971                 REG_N_SETS (REGNO (new_i2_dest))++;
1972             }
1973         }
1974
1975       /* If we can split it and use I2DEST, go ahead and see if that
1976          helps things be recognized.  Verify that none of the registers
1977          are set between I2 and I3.  */
1978       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1979 #ifdef HAVE_cc0
1980           && GET_CODE (i2dest) == REG
1981 #endif
1982           /* We need I2DEST in the proper mode.  If it is a hard register
1983              or the only use of a pseudo, we can change its mode.  */
1984           && (GET_MODE (*split) == GET_MODE (i2dest)
1985               || GET_MODE (*split) == VOIDmode
1986               || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1987               || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1988                   && ! REG_USERVAR_P (i2dest)))
1989           && (next_real_insn (i2) == i3
1990               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1991           /* We can't overwrite I2DEST if its value is still used by
1992              NEWPAT.  */
1993           && ! reg_referenced_p (i2dest, newpat))
1994         {
1995           rtx newdest = i2dest;
1996           enum rtx_code split_code = GET_CODE (*split);
1997           enum machine_mode split_mode = GET_MODE (*split);
1998
1999           /* Get NEWDEST as a register in the proper mode.  We have already
2000              validated that we can do this.  */
2001           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2002             {
2003               newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2004
2005               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2006                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2007             }
2008
2009           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2010              an ASHIFT.  This can occur if it was inside a PLUS and hence
2011              appeared to be a memory address.  This is a kludge.  */
2012           if (split_code == MULT
2013               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2014               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2015             {
2016               SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2017                                               XEXP (*split, 0), GEN_INT (i)));
2018               /* Update split_code because we may not have a multiply
2019                  anymore.  */
2020               split_code = GET_CODE (*split);
2021             }
2022
2023 #ifdef INSN_SCHEDULING
2024           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2025              be written as a ZERO_EXTEND.  */
2026           if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2027             SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2028                                             XEXP (*split, 0)));
2029 #endif
2030
2031           newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2032           SUBST (*split, newdest);
2033           i2_code_number
2034             = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2035
2036           /* If the split point was a MULT and we didn't have one before,
2037              don't use one now.  */
2038           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2039             insn_code_number
2040               = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2041         }
2042     }
2043
2044   /* Check for a case where we loaded from memory in a narrow mode and
2045      then sign extended it, but we need both registers.  In that case,
2046      we have a PARALLEL with both loads from the same memory location.
2047      We can split this into a load from memory followed by a register-register
2048      copy.  This saves at least one insn, more if register allocation can
2049      eliminate the copy.
2050
2051      We cannot do this if the destination of the second assignment is
2052      a register that we have already assumed is zero-extended.  Similarly
2053      for a SUBREG of such a register.  */
2054
2055   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2056            && GET_CODE (newpat) == PARALLEL
2057            && XVECLEN (newpat, 0) == 2
2058            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2059            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2060            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2061            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2062                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2063            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2064                                    INSN_CUID (i2))
2065            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2066            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2067            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2068                  (GET_CODE (temp) == REG
2069                   && reg_nonzero_bits[REGNO (temp)] != 0
2070                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2071                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2072                   && (reg_nonzero_bits[REGNO (temp)]
2073                       != GET_MODE_MASK (word_mode))))
2074            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2075                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2076                      (GET_CODE (temp) == REG
2077                       && reg_nonzero_bits[REGNO (temp)] != 0
2078                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2079                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2080                       && (reg_nonzero_bits[REGNO (temp)]
2081                           != GET_MODE_MASK (word_mode)))))
2082            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2083                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2084            && ! find_reg_note (i3, REG_UNUSED,
2085                                SET_DEST (XVECEXP (newpat, 0, 0))))
2086     {
2087       rtx ni2dest;
2088
2089       newi2pat = XVECEXP (newpat, 0, 0);
2090       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2091       newpat = XVECEXP (newpat, 0, 1);
2092       SUBST (SET_SRC (newpat),
2093              gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2094       i2_code_number
2095         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2096
2097       if (i2_code_number >= 0)
2098         insn_code_number
2099           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2100
2101       if (insn_code_number >= 0)
2102         {
2103           rtx insn;
2104           rtx link;
2105
2106           /* If we will be able to accept this, we have made a change to the
2107              destination of I3.  This can invalidate a LOG_LINKS pointing
2108              to I3.  No other part of combine.c makes such a transformation.
2109
2110              The new I3 will have a destination that was previously the
2111              destination of I1 or I2 and which was used in i2 or I3.  Call
2112              distribute_links to make a LOG_LINK from the next use of
2113              that destination.  */
2114
2115           PATTERN (i3) = newpat;
2116           distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2117
2118           /* I3 now uses what used to be its destination and which is
2119              now I2's destination.  That means we need a LOG_LINK from
2120              I3 to I2.  But we used to have one, so we still will.
2121
2122              However, some later insn might be using I2's dest and have
2123              a LOG_LINK pointing at I3.  We must remove this link.
2124              The simplest way to remove the link is to point it at I1,
2125              which we know will be a NOTE.  */
2126
2127           for (insn = NEXT_INSN (i3);
2128                insn && (this_basic_block == n_basic_blocks - 1
2129                         || insn != basic_block_head[this_basic_block + 1]);
2130                insn = NEXT_INSN (insn))
2131             {
2132               if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2133                   && reg_referenced_p (ni2dest, PATTERN (insn)))
2134                 {
2135                   for (link = LOG_LINKS (insn); link;
2136                        link = XEXP (link, 1))
2137                     if (XEXP (link, 0) == i3)
2138                       XEXP (link, 0) = i1;
2139
2140                   break;
2141                 }
2142             }
2143         }
2144     }
2145
2146   /* Similarly, check for a case where we have a PARALLEL of two independent
2147      SETs but we started with three insns.  In this case, we can do the sets
2148      as two separate insns.  This case occurs when some SET allows two
2149      other insns to combine, but the destination of that SET is still live.  */
2150
2151   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2152            && GET_CODE (newpat) == PARALLEL
2153            && XVECLEN (newpat, 0) == 2
2154            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2155            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2156            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2157            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2158            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2159            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2160            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2161                                    INSN_CUID (i2))
2162            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2163            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2164            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2165            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2166                                   XVECEXP (newpat, 0, 0))
2167            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2168                                   XVECEXP (newpat, 0, 1)))
2169     {
2170       /* Normally, it doesn't matter which of the two is done first,
2171          but it does if one references cc0.  In that case, it has to
2172          be first.  */
2173 #ifdef HAVE_cc0
2174       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2175         {
2176           newi2pat = XVECEXP (newpat, 0, 0);
2177           newpat = XVECEXP (newpat, 0, 1);
2178         }
2179       else
2180 #endif
2181         {
2182           newi2pat = XVECEXP (newpat, 0, 1);
2183           newpat = XVECEXP (newpat, 0, 0);
2184         }
2185
2186       i2_code_number
2187         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2188
2189       if (i2_code_number >= 0)
2190         insn_code_number
2191           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2192     }
2193
2194   /* If it still isn't recognized, fail and change things back the way they
2195      were.  */
2196   if ((insn_code_number < 0
2197        /* Is the result a reasonable ASM_OPERANDS?  */
2198        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2199     {
2200       undo_all ();
2201       return 0;
2202     }
2203
2204   /* If we had to change another insn, make sure it is valid also.  */
2205   if (undobuf.other_insn)
2206     {
2207       rtx other_pat = PATTERN (undobuf.other_insn);
2208       rtx new_other_notes;
2209       rtx note, next;
2210
2211       CLEAR_HARD_REG_SET (newpat_used_regs);
2212
2213       other_code_number
2214         = recog_for_combine (&other_pat, undobuf.other_insn,
2215                              &new_other_notes, &other_scratches);
2216
2217       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2218         {
2219           undo_all ();
2220           return 0;
2221         }
2222
2223       PATTERN (undobuf.other_insn) = other_pat;
2224
2225       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2226          are still valid.  Then add any non-duplicate notes added by
2227          recog_for_combine.  */
2228       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2229         {
2230           next = XEXP (note, 1);
2231
2232           if (REG_NOTE_KIND (note) == REG_UNUSED
2233               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2234             {
2235               if (GET_CODE (XEXP (note, 0)) == REG)
2236                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2237
2238               remove_note (undobuf.other_insn, note);
2239             }
2240         }
2241
2242       for (note = new_other_notes; note; note = XEXP (note, 1))
2243         if (GET_CODE (XEXP (note, 0)) == REG)
2244           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2245
2246       distribute_notes (new_other_notes, undobuf.other_insn,
2247                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2248     }
2249
2250   /* We now know that we can do this combination.  Merge the insns and
2251      update the status of registers and LOG_LINKS.  */
2252
2253   {
2254     rtx i3notes, i2notes, i1notes = 0;
2255     rtx i3links, i2links, i1links = 0;
2256     rtx midnotes = 0;
2257     register int regno;
2258     /* Compute which registers we expect to eliminate.  newi2pat may be setting
2259        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
2260        same as i3dest, in which case newi2pat may be setting i1dest.  */
2261     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2262                    || i2dest_in_i2src || i2dest_in_i1src
2263                    ? 0 : i2dest);
2264     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2265                    || (newi2pat && reg_set_p (i1dest, newi2pat))
2266                    ? 0 : i1dest);
2267
2268     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2269        clear them.  */
2270     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2271     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2272     if (i1)
2273       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2274
2275     /* Ensure that we do not have something that should not be shared but
2276        occurs multiple times in the new insns.  Check this by first
2277        resetting all the `used' flags and then copying anything is shared.  */
2278
2279     reset_used_flags (i3notes);
2280     reset_used_flags (i2notes);
2281     reset_used_flags (i1notes);
2282     reset_used_flags (newpat);
2283     reset_used_flags (newi2pat);
2284     if (undobuf.other_insn)
2285       reset_used_flags (PATTERN (undobuf.other_insn));
2286
2287     i3notes = copy_rtx_if_shared (i3notes);
2288     i2notes = copy_rtx_if_shared (i2notes);
2289     i1notes = copy_rtx_if_shared (i1notes);
2290     newpat = copy_rtx_if_shared (newpat);
2291     newi2pat = copy_rtx_if_shared (newi2pat);
2292     if (undobuf.other_insn)
2293       reset_used_flags (PATTERN (undobuf.other_insn));
2294
2295     INSN_CODE (i3) = insn_code_number;
2296     PATTERN (i3) = newpat;
2297     if (undobuf.other_insn)
2298       INSN_CODE (undobuf.other_insn) = other_code_number;
2299
2300     /* We had one special case above where I2 had more than one set and
2301        we replaced a destination of one of those sets with the destination
2302        of I3.  In that case, we have to update LOG_LINKS of insns later
2303        in this basic block.  Note that this (expensive) case is rare.
2304
2305        Also, in this case, we must pretend that all REG_NOTEs for I2
2306        actually came from I3, so that REG_UNUSED notes from I2 will be
2307        properly handled.  */
2308
2309     if (i3_subst_into_i2)
2310       {
2311         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2312           if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2313               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2314               && ! find_reg_note (i2, REG_UNUSED,
2315                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2316             for (temp = NEXT_INSN (i2);
2317                  temp && (this_basic_block == n_basic_blocks - 1
2318                           || basic_block_head[this_basic_block] != temp);
2319                  temp = NEXT_INSN (temp))
2320               if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2321                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2322                   if (XEXP (link, 0) == i2)
2323                     XEXP (link, 0) = i3;
2324
2325         if (i3notes)
2326           {
2327             rtx link = i3notes;
2328             while (XEXP (link, 1))
2329               link = XEXP (link, 1);
2330             XEXP (link, 1) = i2notes;
2331           }
2332         else
2333           i3notes = i2notes;
2334         i2notes = 0;
2335       }
2336
2337     LOG_LINKS (i3) = 0;
2338     REG_NOTES (i3) = 0;
2339     LOG_LINKS (i2) = 0;
2340     REG_NOTES (i2) = 0;
2341
2342     if (newi2pat)
2343       {
2344         INSN_CODE (i2) = i2_code_number;
2345         PATTERN (i2) = newi2pat;
2346       }
2347     else
2348       {
2349         PUT_CODE (i2, NOTE);
2350         NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2351         NOTE_SOURCE_FILE (i2) = 0;
2352       }
2353
2354     if (i1)
2355       {
2356         LOG_LINKS (i1) = 0;
2357         REG_NOTES (i1) = 0;
2358         PUT_CODE (i1, NOTE);
2359         NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2360         NOTE_SOURCE_FILE (i1) = 0;
2361       }
2362
2363     /* Get death notes for everything that is now used in either I3 or
2364        I2 and used to die in a previous insn.  If we built two new
2365        patterns, move from I1 to I2 then I2 to I3 so that we get the
2366        proper movement on registers that I2 modifies.  */
2367
2368     if (newi2pat)
2369       {
2370         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2371         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2372       }
2373     else
2374       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2375                    i3, &midnotes);
2376
2377     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
2378     if (i3notes)
2379       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2380                         elim_i2, elim_i1);
2381     if (i2notes)
2382       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2383                         elim_i2, elim_i1);
2384     if (i1notes)
2385       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2386                         elim_i2, elim_i1);
2387     if (midnotes)
2388       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2389                         elim_i2, elim_i1);
2390
2391     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
2392        know these are REG_UNUSED and want them to go to the desired insn,
2393        so we always pass it as i3.  We have not counted the notes in
2394        reg_n_deaths yet, so we need to do so now.  */
2395
2396     if (newi2pat && new_i2_notes)
2397       {
2398         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2399           if (GET_CODE (XEXP (temp, 0)) == REG)
2400             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2401
2402         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2403       }
2404
2405     if (new_i3_notes)
2406       {
2407         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2408           if (GET_CODE (XEXP (temp, 0)) == REG)
2409             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2410
2411         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2412       }
2413
2414     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
2415        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
2416        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
2417        in that case, it might delete I2.  Similarly for I2 and I1.
2418        Show an additional death due to the REG_DEAD note we make here.  If
2419        we discard it in distribute_notes, we will decrement it again.  */
2420
2421     if (i3dest_killed)
2422       {
2423         if (GET_CODE (i3dest_killed) == REG)
2424           REG_N_DEATHS (REGNO (i3dest_killed))++;
2425
2426         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2427           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2428                                                NULL_RTX),
2429                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2430         else
2431           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2432                                                NULL_RTX),
2433                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2434                             elim_i2, elim_i1);
2435       }
2436
2437     if (i2dest_in_i2src)
2438       {
2439         if (GET_CODE (i2dest) == REG)
2440           REG_N_DEATHS (REGNO (i2dest))++;
2441
2442         if (newi2pat && reg_set_p (i2dest, newi2pat))
2443           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2444                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2445         else
2446           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2447                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2448                             NULL_RTX, NULL_RTX);
2449       }
2450
2451     if (i1dest_in_i1src)
2452       {
2453         if (GET_CODE (i1dest) == REG)
2454           REG_N_DEATHS (REGNO (i1dest))++;
2455
2456         if (newi2pat && reg_set_p (i1dest, newi2pat))
2457           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2458                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2459         else
2460           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2461                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2462                             NULL_RTX, NULL_RTX);
2463       }
2464
2465     distribute_links (i3links);
2466     distribute_links (i2links);
2467     distribute_links (i1links);
2468
2469     if (GET_CODE (i2dest) == REG)
2470       {
2471         rtx link;
2472         rtx i2_insn = 0, i2_val = 0, set;
2473
2474         /* The insn that used to set this register doesn't exist, and
2475            this life of the register may not exist either.  See if one of
2476            I3's links points to an insn that sets I2DEST.  If it does,
2477            that is now the last known value for I2DEST. If we don't update
2478            this and I2 set the register to a value that depended on its old
2479            contents, we will get confused.  If this insn is used, thing
2480            will be set correctly in combine_instructions.  */
2481
2482         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2483           if ((set = single_set (XEXP (link, 0))) != 0
2484               && rtx_equal_p (i2dest, SET_DEST (set)))
2485             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2486
2487         record_value_for_reg (i2dest, i2_insn, i2_val);
2488
2489         /* If the reg formerly set in I2 died only once and that was in I3,
2490            zero its use count so it won't make `reload' do any work.  */
2491         if (! added_sets_2
2492             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2493             && ! i2dest_in_i2src)
2494           {
2495             regno = REGNO (i2dest);
2496             REG_N_SETS (regno)--;
2497             if (REG_N_SETS (regno) == 0
2498                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2499               REG_N_REFS (regno) = 0;
2500           }
2501       }
2502
2503     if (i1 && GET_CODE (i1dest) == REG)
2504       {
2505         rtx link;
2506         rtx i1_insn = 0, i1_val = 0, set;
2507
2508         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2509           if ((set = single_set (XEXP (link, 0))) != 0
2510               && rtx_equal_p (i1dest, SET_DEST (set)))
2511             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2512
2513         record_value_for_reg (i1dest, i1_insn, i1_val);
2514
2515         regno = REGNO (i1dest);
2516         if (! added_sets_1 && ! i1dest_in_i1src)
2517           {
2518             REG_N_SETS (regno)--;
2519             if (REG_N_SETS (regno) == 0
2520                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2521               REG_N_REFS (regno) = 0;
2522           }
2523       }
2524
2525     /* Update reg_nonzero_bits et al for any changes that may have been made
2526        to this insn.  */
2527
2528     note_stores (newpat, set_nonzero_bits_and_sign_copies);
2529     if (newi2pat)
2530       note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2531
2532     /* If we added any (clobber (scratch)), add them to the max for a
2533        block.  This is a very pessimistic calculation, since we might
2534        have had them already and this might not be the worst block, but
2535        it's not worth doing any better.  */
2536     max_scratch += i3_scratches + i2_scratches + other_scratches;
2537
2538     /* If I3 is now an unconditional jump, ensure that it has a
2539        BARRIER following it since it may have initially been a
2540        conditional jump.  It may also be the last nonnote insn.  */
2541
2542     if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2543         && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2544             || GET_CODE (temp) != BARRIER))
2545       emit_barrier_after (i3);
2546   }
2547
2548   combine_successes++;
2549
2550   /* Clear this here, so that subsequent get_last_value calls are not
2551      affected.  */
2552   subst_prev_insn = NULL_RTX;
2553
2554   if (added_links_insn
2555       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2556       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2557     return added_links_insn;
2558   else
2559     return newi2pat ? i2 : i3;
2560 }
2561 \f
2562 /* Undo all the modifications recorded in undobuf.  */
2563
2564 static void
2565 undo_all ()
2566 {
2567   struct undo *undo, *next;
2568
2569   for (undo = undobuf.undos; undo; undo = next)
2570     {
2571       next = undo->next;
2572       if (undo->is_int)
2573         *undo->where.i = undo->old_contents.i;
2574       else
2575         *undo->where.r = undo->old_contents.r;
2576
2577       undo->next = undobuf.frees;
2578       undobuf.frees = undo;
2579     }
2580
2581   obfree (undobuf.storage);
2582   undobuf.undos = undobuf.previous_undos = 0;
2583
2584   /* Clear this here, so that subsequent get_last_value calls are not
2585      affected.  */
2586   subst_prev_insn = NULL_RTX;
2587 }
2588 \f
2589 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2590    where we have an arithmetic expression and return that point.  LOC will
2591    be inside INSN.
2592
2593    try_combine will call this function to see if an insn can be split into
2594    two insns.  */
2595
2596 static rtx *
2597 find_split_point (loc, insn)
2598      rtx *loc;
2599      rtx insn;
2600 {
2601   rtx x = *loc;
2602   enum rtx_code code = GET_CODE (x);
2603   rtx *split;
2604   int len = 0, pos, unsignedp;
2605   rtx inner;
2606
2607   /* First special-case some codes.  */
2608   switch (code)
2609     {
2610     case SUBREG:
2611 #ifdef INSN_SCHEDULING
2612       /* If we are making a paradoxical SUBREG invalid, it becomes a split
2613          point.  */
2614       if (GET_CODE (SUBREG_REG (x)) == MEM)
2615         return loc;
2616 #endif
2617       return find_split_point (&SUBREG_REG (x), insn);
2618
2619     case MEM:
2620 #ifdef HAVE_lo_sum
2621       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2622          using LO_SUM and HIGH.  */
2623       if (GET_CODE (XEXP (x, 0)) == CONST
2624           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2625         {
2626           SUBST (XEXP (x, 0),
2627                  gen_rtx_combine (LO_SUM, Pmode,
2628                                   gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2629                                   XEXP (x, 0)));
2630           return &XEXP (XEXP (x, 0), 0);
2631         }
2632 #endif
2633
2634       /* If we have a PLUS whose second operand is a constant and the
2635          address is not valid, perhaps will can split it up using
2636          the machine-specific way to split large constants.  We use
2637          the first pseudo-reg (one of the virtual regs) as a placeholder;
2638          it will not remain in the result.  */
2639       if (GET_CODE (XEXP (x, 0)) == PLUS
2640           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2641           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2642         {
2643           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2644           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2645                                  subst_insn);
2646
2647           /* This should have produced two insns, each of which sets our
2648              placeholder.  If the source of the second is a valid address,
2649              we can make put both sources together and make a split point
2650              in the middle.  */
2651
2652           if (seq && XVECLEN (seq, 0) == 2
2653               && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2654               && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2655               && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2656               && ! reg_mentioned_p (reg,
2657                                     SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2658               && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2659               && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2660               && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2661               && memory_address_p (GET_MODE (x),
2662                                    SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2663             {
2664               rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2665               rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2666
2667               /* Replace the placeholder in SRC2 with SRC1.  If we can
2668                  find where in SRC2 it was placed, that can become our
2669                  split point and we can replace this address with SRC2.
2670                  Just try two obvious places.  */
2671
2672               src2 = replace_rtx (src2, reg, src1);
2673               split = 0;
2674               if (XEXP (src2, 0) == src1)
2675                 split = &XEXP (src2, 0);
2676               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2677                        && XEXP (XEXP (src2, 0), 0) == src1)
2678                 split = &XEXP (XEXP (src2, 0), 0);
2679
2680               if (split)
2681                 {
2682                   SUBST (XEXP (x, 0), src2);
2683                   return split;
2684                 }
2685             }
2686
2687           /* If that didn't work, perhaps the first operand is complex and
2688              needs to be computed separately, so make a split point there.
2689              This will occur on machines that just support REG + CONST
2690              and have a constant moved through some previous computation.  */
2691
2692           else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2693                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2694                          && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2695                              == 'o')))
2696             return &XEXP (XEXP (x, 0), 0);
2697         }
2698       break;
2699
2700     case SET:
2701 #ifdef HAVE_cc0
2702       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2703          ZERO_EXTRACT, the most likely reason why this doesn't match is that
2704          we need to put the operand into a register.  So split at that
2705          point.  */
2706
2707       if (SET_DEST (x) == cc0_rtx
2708           && GET_CODE (SET_SRC (x)) != COMPARE
2709           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2710           && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2711           && ! (GET_CODE (SET_SRC (x)) == SUBREG
2712                 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2713         return &SET_SRC (x);
2714 #endif
2715
2716       /* See if we can split SET_SRC as it stands.  */
2717       split = find_split_point (&SET_SRC (x), insn);
2718       if (split && split != &SET_SRC (x))
2719         return split;
2720
2721       /* See if we can split SET_DEST as it stands.  */
2722       split = find_split_point (&SET_DEST (x), insn);
2723       if (split && split != &SET_DEST (x))
2724         return split;
2725
2726       /* See if this is a bitfield assignment with everything constant.  If
2727          so, this is an IOR of an AND, so split it into that.  */
2728       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2729           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2730               <= HOST_BITS_PER_WIDE_INT)
2731           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2732           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2733           && GET_CODE (SET_SRC (x)) == CONST_INT
2734           && ((INTVAL (XEXP (SET_DEST (x), 1))
2735               + INTVAL (XEXP (SET_DEST (x), 2)))
2736               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2737           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2738         {
2739           int pos = INTVAL (XEXP (SET_DEST (x), 2));
2740           int len = INTVAL (XEXP (SET_DEST (x), 1));
2741           int src = INTVAL (SET_SRC (x));
2742           rtx dest = XEXP (SET_DEST (x), 0);
2743           enum machine_mode mode = GET_MODE (dest);
2744           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2745
2746           if (BITS_BIG_ENDIAN)
2747             pos = GET_MODE_BITSIZE (mode) - len - pos;
2748
2749           if (src == mask)
2750             SUBST (SET_SRC (x),
2751                    gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2752           else
2753             SUBST (SET_SRC (x),
2754                    gen_binary (IOR, mode,
2755                                gen_binary (AND, mode, dest,
2756                                            GEN_INT (~ (mask << pos)
2757                                                     & GET_MODE_MASK (mode))),
2758                                GEN_INT (src << pos)));
2759
2760           SUBST (SET_DEST (x), dest);
2761
2762           split = find_split_point (&SET_SRC (x), insn);
2763           if (split && split != &SET_SRC (x))
2764             return split;
2765         }
2766
2767       /* Otherwise, see if this is an operation that we can split into two.
2768          If so, try to split that.  */
2769       code = GET_CODE (SET_SRC (x));
2770
2771       switch (code)
2772         {
2773         case AND:
2774           /* If we are AND'ing with a large constant that is only a single
2775              bit and the result is only being used in a context where we
2776              need to know if it is zero or non-zero, replace it with a bit
2777              extraction.  This will avoid the large constant, which might
2778              have taken more than one insn to make.  If the constant were
2779              not a valid argument to the AND but took only one insn to make,
2780              this is no worse, but if it took more than one insn, it will
2781              be better.  */
2782
2783           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2784               && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2785               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2786               && GET_CODE (SET_DEST (x)) == REG
2787               && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2788               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2789               && XEXP (*split, 0) == SET_DEST (x)
2790               && XEXP (*split, 1) == const0_rtx)
2791             {
2792               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2793                                                 XEXP (SET_SRC (x), 0),
2794                                                 pos, NULL_RTX, 1, 1, 0, 0);
2795               if (extraction != 0)
2796                 {
2797                   SUBST (SET_SRC (x), extraction);
2798                   return find_split_point (loc, insn);
2799                 }
2800             }
2801           break;
2802
2803         case NE:
2804           /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2805              is known to be on, this can be converted into a NEG of a shift. */
2806           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2807               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2808               && 1 <= (pos = exact_log2
2809                        (nonzero_bits (XEXP (SET_SRC (x), 0),
2810                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
2811             {
2812               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2813
2814               SUBST (SET_SRC (x),
2815                      gen_rtx_combine (NEG, mode,
2816                                       gen_rtx_combine (LSHIFTRT, mode,
2817                                                        XEXP (SET_SRC (x), 0),
2818                                                        GEN_INT (pos))));
2819
2820               split = find_split_point (&SET_SRC (x), insn);
2821               if (split && split != &SET_SRC (x))
2822                 return split;
2823             }
2824           break;
2825
2826         case SIGN_EXTEND:
2827           inner = XEXP (SET_SRC (x), 0);
2828
2829           /* We can't optimize if either mode is a partial integer
2830              mode as we don't know how many bits are significant
2831              in those modes.  */
2832           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2833               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2834             break;
2835
2836           pos = 0;
2837           len = GET_MODE_BITSIZE (GET_MODE (inner));
2838           unsignedp = 0;
2839           break;
2840
2841         case SIGN_EXTRACT:
2842         case ZERO_EXTRACT:
2843           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2844               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2845             {
2846               inner = XEXP (SET_SRC (x), 0);
2847               len = INTVAL (XEXP (SET_SRC (x), 1));
2848               pos = INTVAL (XEXP (SET_SRC (x), 2));
2849
2850               if (BITS_BIG_ENDIAN)
2851                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2852               unsignedp = (code == ZERO_EXTRACT);
2853             }
2854           break;
2855
2856         default:
2857           break;
2858         }
2859
2860       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2861         {
2862           enum machine_mode mode = GET_MODE (SET_SRC (x));
2863
2864           /* For unsigned, we have a choice of a shift followed by an
2865              AND or two shifts.  Use two shifts for field sizes where the
2866              constant might be too large.  We assume here that we can
2867              always at least get 8-bit constants in an AND insn, which is
2868              true for every current RISC.  */
2869
2870           if (unsignedp && len <= 8)
2871             {
2872               SUBST (SET_SRC (x),
2873                      gen_rtx_combine
2874                      (AND, mode,
2875                       gen_rtx_combine (LSHIFTRT, mode,
2876                                        gen_lowpart_for_combine (mode, inner),
2877                                        GEN_INT (pos)),
2878                       GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2879
2880               split = find_split_point (&SET_SRC (x), insn);
2881               if (split && split != &SET_SRC (x))
2882                 return split;
2883             }
2884           else
2885             {
2886               SUBST (SET_SRC (x),
2887                      gen_rtx_combine
2888                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2889                       gen_rtx_combine (ASHIFT, mode,
2890                                        gen_lowpart_for_combine (mode, inner),
2891                                        GEN_INT (GET_MODE_BITSIZE (mode)
2892                                                 - len - pos)),
2893                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2894
2895               split = find_split_point (&SET_SRC (x), insn);
2896               if (split && split != &SET_SRC (x))
2897                 return split;
2898             }
2899         }
2900
2901       /* See if this is a simple operation with a constant as the second
2902          operand.  It might be that this constant is out of range and hence
2903          could be used as a split point.  */
2904       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2905            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2906            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2907           && CONSTANT_P (XEXP (SET_SRC (x), 1))
2908           && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2909               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2910                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2911                       == 'o'))))
2912         return &XEXP (SET_SRC (x), 1);
2913
2914       /* Finally, see if this is a simple operation with its first operand
2915          not in a register.  The operation might require this operand in a
2916          register, so return it as a split point.  We can always do this
2917          because if the first operand were another operation, we would have
2918          already found it as a split point.  */
2919       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2920            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2921            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2922            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2923           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2924         return &XEXP (SET_SRC (x), 0);
2925
2926       return 0;
2927
2928     case AND:
2929     case IOR:
2930       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2931          it is better to write this as (not (ior A B)) so we can split it.
2932          Similarly for IOR.  */
2933       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2934         {
2935           SUBST (*loc,
2936                  gen_rtx_combine (NOT, GET_MODE (x),
2937                                   gen_rtx_combine (code == IOR ? AND : IOR,
2938                                                    GET_MODE (x),
2939                                                    XEXP (XEXP (x, 0), 0),
2940                                                    XEXP (XEXP (x, 1), 0))));
2941           return find_split_point (loc, insn);
2942         }
2943
2944       /* Many RISC machines have a large set of logical insns.  If the
2945          second operand is a NOT, put it first so we will try to split the
2946          other operand first.  */
2947       if (GET_CODE (XEXP (x, 1)) == NOT)
2948         {
2949           rtx tem = XEXP (x, 0);
2950           SUBST (XEXP (x, 0), XEXP (x, 1));
2951           SUBST (XEXP (x, 1), tem);
2952         }
2953       break;
2954
2955     default:
2956       break;
2957     }
2958
2959   /* Otherwise, select our actions depending on our rtx class.  */
2960   switch (GET_RTX_CLASS (code))
2961     {
2962     case 'b':                   /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
2963     case '3':
2964       split = find_split_point (&XEXP (x, 2), insn);
2965       if (split)
2966         return split;
2967       /* ... fall through ...  */
2968     case '2':
2969     case 'c':
2970     case '<':
2971       split = find_split_point (&XEXP (x, 1), insn);
2972       if (split)
2973         return split;
2974       /* ... fall through ...  */
2975     case '1':
2976       /* Some machines have (and (shift ...) ...) insns.  If X is not
2977          an AND, but XEXP (X, 0) is, use it as our split point.  */
2978       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2979         return &XEXP (x, 0);
2980
2981       split = find_split_point (&XEXP (x, 0), insn);
2982       if (split)
2983         return split;
2984       return loc;
2985     }
2986
2987   /* Otherwise, we don't have a split point.  */
2988   return 0;
2989 }
2990 \f
2991 /* Throughout X, replace FROM with TO, and return the result.
2992    The result is TO if X is FROM;
2993    otherwise the result is X, but its contents may have been modified.
2994    If they were modified, a record was made in undobuf so that
2995    undo_all will (among other things) return X to its original state.
2996
2997    If the number of changes necessary is too much to record to undo,
2998    the excess changes are not made, so the result is invalid.
2999    The changes already made can still be undone.
3000    undobuf.num_undo is incremented for such changes, so by testing that
3001    the caller can tell whether the result is valid.
3002
3003    `n_occurrences' is incremented each time FROM is replaced.
3004
3005    IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3006
3007    UNIQUE_COPY is non-zero if each substitution must be unique.  We do this
3008    by copying if `n_occurrences' is non-zero.  */
3009
3010 static rtx
3011 subst (x, from, to, in_dest, unique_copy)
3012      register rtx x, from, to;
3013      int in_dest;
3014      int unique_copy;
3015 {
3016   register enum rtx_code code = GET_CODE (x);
3017   enum machine_mode op0_mode = VOIDmode;
3018   register char *fmt;
3019   register int len, i;
3020   rtx new;
3021
3022 /* Two expressions are equal if they are identical copies of a shared
3023    RTX or if they are both registers with the same register number
3024    and mode.  */
3025
3026 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3027   ((X) == (Y)                                           \
3028    || (GET_CODE (X) == REG && GET_CODE (Y) == REG       \
3029        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3030
3031   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3032     {
3033       n_occurrences++;
3034       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3035     }
3036
3037   /* If X and FROM are the same register but different modes, they will
3038      not have been seen as equal above.  However, flow.c will make a
3039      LOG_LINKS entry for that case.  If we do nothing, we will try to
3040      rerecognize our original insn and, when it succeeds, we will
3041      delete the feeding insn, which is incorrect.
3042
3043      So force this insn not to match in this (rare) case.  */
3044   if (! in_dest && code == REG && GET_CODE (from) == REG
3045       && REGNO (x) == REGNO (from))
3046     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3047
3048   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3049      of which may contain things that can be combined.  */
3050   if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3051     return x;
3052
3053   /* It is possible to have a subexpression appear twice in the insn.
3054      Suppose that FROM is a register that appears within TO.
3055      Then, after that subexpression has been scanned once by `subst',
3056      the second time it is scanned, TO may be found.  If we were
3057      to scan TO here, we would find FROM within it and create a
3058      self-referent rtl structure which is completely wrong.  */
3059   if (COMBINE_RTX_EQUAL_P (x, to))
3060     return to;
3061
3062   len = GET_RTX_LENGTH (code);
3063   fmt = GET_RTX_FORMAT (code);
3064
3065   /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
3066      set up to skip this common case.  All other cases where we want to
3067      suppress replacing something inside a SET_SRC are handled via the
3068      IN_DEST operand.  */
3069   if (code == SET
3070       && (GET_CODE (SET_DEST (x)) == REG
3071         || GET_CODE (SET_DEST (x)) == CC0
3072         || GET_CODE (SET_DEST (x)) == PC))
3073     fmt = "ie";
3074
3075   /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3076      constant.  */
3077   if (fmt[0] == 'e')
3078     op0_mode = GET_MODE (XEXP (x, 0));
3079
3080   for (i = 0; i < len; i++)
3081     {
3082       if (fmt[i] == 'E')
3083         {
3084           register int j;
3085           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3086             {
3087               if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3088                 {
3089                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3090                   n_occurrences++;
3091                 }
3092               else
3093                 {
3094                   new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
3095
3096                   /* If this substitution failed, this whole thing fails.  */
3097                   if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3098                     return new;
3099                 }
3100
3101               SUBST (XVECEXP (x, i, j), new);
3102             }
3103         }
3104       else if (fmt[i] == 'e')
3105         {
3106           if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3107             {
3108               /* In general, don't install a subreg involving two modes not
3109                  tieable.  It can worsen register allocation, and can even
3110                  make invalid reload insns, since the reg inside may need to
3111                  be copied from in the outside mode, and that may be invalid
3112                  if it is an fp reg copied in integer mode.
3113
3114                  We allow two exceptions to this: It is valid if it is inside
3115                  another SUBREG and the mode of that SUBREG and the mode of
3116                  the inside of TO is tieable and it is valid if X is a SET
3117                  that copies FROM to CC0.  */
3118               if (GET_CODE (to) == SUBREG
3119                   && ! MODES_TIEABLE_P (GET_MODE (to),
3120                                         GET_MODE (SUBREG_REG (to)))
3121                   && ! (code == SUBREG
3122                         && MODES_TIEABLE_P (GET_MODE (x),
3123                                             GET_MODE (SUBREG_REG (to))))
3124 #ifdef HAVE_cc0
3125                   && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3126 #endif
3127                   )
3128                 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3129
3130               new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3131               n_occurrences++;
3132             }
3133           else
3134             /* If we are in a SET_DEST, suppress most cases unless we
3135                have gone inside a MEM, in which case we want to
3136                simplify the address.  We assume here that things that
3137                are actually part of the destination have their inner
3138                parts in the first expression.  This is true for SUBREG,
3139                STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3140                things aside from REG and MEM that should appear in a
3141                SET_DEST.  */
3142             new = subst (XEXP (x, i), from, to,
3143                          (((in_dest
3144                             && (code == SUBREG || code == STRICT_LOW_PART
3145                                 || code == ZERO_EXTRACT))
3146                            || code == SET)
3147                           && i == 0), unique_copy);
3148
3149           /* If we found that we will have to reject this combination,
3150              indicate that by returning the CLOBBER ourselves, rather than
3151              an expression containing it.  This will speed things up as
3152              well as prevent accidents where two CLOBBERs are considered
3153              to be equal, thus producing an incorrect simplification.  */
3154
3155           if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3156             return new;
3157
3158           SUBST (XEXP (x, i), new);
3159         }
3160     }
3161
3162   /* Try to simplify X.  If the simplification changed the code, it is likely
3163      that further simplification will help, so loop, but limit the number
3164      of repetitions that will be performed.  */
3165
3166   for (i = 0; i < 4; i++)
3167     {
3168       /* If X is sufficiently simple, don't bother trying to do anything
3169          with it.  */
3170       if (code != CONST_INT && code != REG && code != CLOBBER)
3171         x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3172
3173       if (GET_CODE (x) == code)
3174         break;
3175
3176       code = GET_CODE (x);
3177
3178       /* We no longer know the original mode of operand 0 since we
3179          have changed the form of X)  */
3180       op0_mode = VOIDmode;
3181     }
3182
3183   return x;
3184 }
3185 \f
3186 /* Simplify X, a piece of RTL.  We just operate on the expression at the
3187    outer level; call `subst' to simplify recursively.  Return the new
3188    expression.
3189
3190    OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3191    will be the iteration even if an expression with a code different from
3192    X is returned; IN_DEST is nonzero if we are inside a SET_DEST.  */
3193
3194 static rtx
3195 simplify_rtx (x, op0_mode, last, in_dest)
3196      rtx x;
3197      enum machine_mode op0_mode;
3198      int last;
3199      int in_dest;
3200 {
3201   enum rtx_code code = GET_CODE (x);
3202   enum machine_mode mode = GET_MODE (x);
3203   rtx temp;
3204   int i;
3205
3206   /* If this is a commutative operation, put a constant last and a complex
3207      expression first.  We don't need to do this for comparisons here.  */
3208   if (GET_RTX_CLASS (code) == 'c'
3209       && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3210           || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3211               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3212           || (GET_CODE (XEXP (x, 0)) == SUBREG
3213               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3214               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3215     {
3216       temp = XEXP (x, 0);
3217       SUBST (XEXP (x, 0), XEXP (x, 1));
3218       SUBST (XEXP (x, 1), temp);
3219     }
3220
3221   /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3222      sign extension of a PLUS with a constant, reverse the order of the sign
3223      extension and the addition. Note that this not the same as the original
3224      code, but overflow is undefined for signed values.  Also note that the
3225      PLUS will have been partially moved "inside" the sign-extension, so that
3226      the first operand of X will really look like:
3227          (ashiftrt (plus (ashift A C4) C5) C4).
3228      We convert this to
3229          (plus (ashiftrt (ashift A C4) C2) C4)
3230      and replace the first operand of X with that expression.  Later parts
3231      of this function may simplify the expression further.
3232
3233      For example, if we start with (mult (sign_extend (plus A C1)) C2),
3234      we swap the SIGN_EXTEND and PLUS.  Later code will apply the
3235      distributive law to produce (plus (mult (sign_extend X) C1) C3).
3236
3237      We do this to simplify address expressions.  */
3238
3239   if ((code == PLUS || code == MINUS || code == MULT)
3240       && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3241       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3242       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3243       && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3244       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3245       && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3246       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3247       && (temp = simplify_binary_operation (ASHIFTRT, mode,
3248                                             XEXP (XEXP (XEXP (x, 0), 0), 1),
3249                                             XEXP (XEXP (x, 0), 1))) != 0)
3250     {
3251       rtx new
3252         = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3253                                 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3254                                 INTVAL (XEXP (XEXP (x, 0), 1)));
3255
3256       new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3257                                   INTVAL (XEXP (XEXP (x, 0), 1)));
3258
3259       SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3260     }
3261
3262   /* If this is a simple operation applied to an IF_THEN_ELSE, try
3263      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
3264      things.  Check for cases where both arms are testing the same
3265      condition.
3266
3267      Don't do anything if all operands are very simple.  */
3268
3269   if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3270         || GET_RTX_CLASS (code) == '<')
3271        && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3272             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3273                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3274                       == 'o')))
3275            || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3276                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3277                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3278                          == 'o')))))
3279       || (GET_RTX_CLASS (code) == '1'
3280           && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3281                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3282                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3283                          == 'o'))))))
3284     {
3285       rtx cond, true, false;
3286
3287       cond = if_then_else_cond (x, &true, &false);
3288       if (cond != 0
3289           /* If everything is a comparison, what we have is highly unlikely
3290              to be simpler, so don't use it.  */
3291           && ! (GET_RTX_CLASS (code) == '<'
3292                 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3293                     || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3294         {
3295           rtx cop1 = const0_rtx;
3296           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3297
3298           if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3299             return x;
3300
3301           /* Simplify the alternative arms; this may collapse the true and
3302              false arms to store-flag values.  */
3303           true = subst (true, pc_rtx, pc_rtx, 0, 0);
3304           false = subst (false, pc_rtx, pc_rtx, 0, 0);
3305
3306           /* Restarting if we generate a store-flag expression will cause
3307              us to loop.  Just drop through in this case.  */
3308
3309           /* If the result values are STORE_FLAG_VALUE and zero, we can
3310              just make the comparison operation.  */
3311           if (true == const_true_rtx && false == const0_rtx)
3312             x = gen_binary (cond_code, mode, cond, cop1);
3313           else if (true == const0_rtx && false == const_true_rtx)
3314             x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3315
3316           /* Likewise, we can make the negate of a comparison operation
3317              if the result values are - STORE_FLAG_VALUE and zero.  */
3318           else if (GET_CODE (true) == CONST_INT
3319                    && INTVAL (true) == - STORE_FLAG_VALUE
3320                    && false == const0_rtx)
3321             x = gen_unary (NEG, mode, mode,
3322                            gen_binary (cond_code, mode, cond, cop1));
3323           else if (GET_CODE (false) == CONST_INT
3324                    && INTVAL (false) == - STORE_FLAG_VALUE
3325                    && true == const0_rtx)
3326             x = gen_unary (NEG, mode, mode,
3327                            gen_binary (reverse_condition (cond_code),
3328                                        mode, cond, cop1));
3329           else
3330             return gen_rtx_IF_THEN_ELSE (mode,
3331                                          gen_binary (cond_code, VOIDmode,
3332                                                      cond, cop1),
3333                                          true, false);
3334
3335           code = GET_CODE (x);
3336           op0_mode = VOIDmode;
3337         }
3338     }
3339
3340   /* Try to fold this expression in case we have constants that weren't
3341      present before.  */
3342   temp = 0;
3343   switch (GET_RTX_CLASS (code))
3344     {
3345     case '1':
3346       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3347       break;
3348     case '<':
3349       temp = simplify_relational_operation (code, op0_mode,
3350                                             XEXP (x, 0), XEXP (x, 1));
3351 #ifdef FLOAT_STORE_FLAG_VALUE
3352       if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3353         temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3354                 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3355 #endif
3356       break;
3357     case 'c':
3358     case '2':
3359       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3360       break;
3361     case 'b':
3362     case '3':
3363       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3364                                          XEXP (x, 1), XEXP (x, 2));
3365       break;
3366     }
3367
3368   if (temp)
3369     x = temp, code = GET_CODE (temp);
3370
3371   /* First see if we can apply the inverse distributive law.  */
3372   if (code == PLUS || code == MINUS
3373       || code == AND || code == IOR || code == XOR)
3374     {
3375       x = apply_distributive_law (x);
3376       code = GET_CODE (x);
3377     }
3378
3379   /* If CODE is an associative operation not otherwise handled, see if we
3380      can associate some operands.  This can win if they are constants or
3381      if they are logically related (i.e. (a & b) & a.  */
3382   if ((code == PLUS || code == MINUS
3383        || code == MULT || code == AND || code == IOR || code == XOR
3384        || code == DIV || code == UDIV
3385        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3386       && INTEGRAL_MODE_P (mode))
3387     {
3388       if (GET_CODE (XEXP (x, 0)) == code)
3389         {
3390           rtx other = XEXP (XEXP (x, 0), 0);
3391           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3392           rtx inner_op1 = XEXP (x, 1);
3393           rtx inner;
3394
3395           /* Make sure we pass the constant operand if any as the second
3396              one if this is a commutative operation.  */
3397           if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3398             {
3399               rtx tem = inner_op0;
3400               inner_op0 = inner_op1;
3401               inner_op1 = tem;
3402             }
3403           inner = simplify_binary_operation (code == MINUS ? PLUS
3404                                              : code == DIV ? MULT
3405                                              : code == UDIV ? MULT
3406                                              : code,
3407                                              mode, inner_op0, inner_op1);
3408
3409           /* For commutative operations, try the other pair if that one
3410              didn't simplify.  */
3411           if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3412             {
3413               other = XEXP (XEXP (x, 0), 1);
3414               inner = simplify_binary_operation (code, mode,
3415                                                  XEXP (XEXP (x, 0), 0),
3416                                                  XEXP (x, 1));
3417             }
3418
3419           if (inner)
3420             return gen_binary (code, mode, other, inner);
3421         }
3422     }
3423
3424   /* A little bit of algebraic simplification here.  */
3425   switch (code)
3426     {
3427     case MEM:
3428       /* Ensure that our address has any ASHIFTs converted to MULT in case
3429          address-recognizing predicates are called later.  */
3430       temp = make_compound_operation (XEXP (x, 0), MEM);
3431       SUBST (XEXP (x, 0), temp);
3432       break;
3433
3434     case SUBREG:
3435       /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3436          is paradoxical.  If we can't do that safely, then it becomes
3437          something nonsensical so that this combination won't take place.  */
3438
3439       if (GET_CODE (SUBREG_REG (x)) == MEM
3440           && (GET_MODE_SIZE (mode)
3441               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3442         {
3443           rtx inner = SUBREG_REG (x);
3444           int endian_offset = 0;
3445           /* Don't change the mode of the MEM
3446              if that would change the meaning of the address.  */
3447           if (MEM_VOLATILE_P (SUBREG_REG (x))
3448               || mode_dependent_address_p (XEXP (inner, 0)))
3449             return gen_rtx_CLOBBER (mode, const0_rtx);
3450
3451           if (BYTES_BIG_ENDIAN)
3452             {
3453               if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3454                 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3455               if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3456                 endian_offset -= (UNITS_PER_WORD
3457                                   - GET_MODE_SIZE (GET_MODE (inner)));
3458             }
3459           /* Note if the plus_constant doesn't make a valid address
3460              then this combination won't be accepted.  */
3461           x = gen_rtx_MEM (mode,
3462                            plus_constant (XEXP (inner, 0),
3463                                           (SUBREG_WORD (x) * UNITS_PER_WORD
3464                                            + endian_offset)));
3465           MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3466           RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3467           MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3468           return x;
3469         }
3470
3471       /* If we are in a SET_DEST, these other cases can't apply.  */
3472       if (in_dest)
3473         return x;
3474
3475       /* Changing mode twice with SUBREG => just change it once,
3476          or not at all if changing back to starting mode.  */
3477       if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3478         {
3479           if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3480               && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3481             return SUBREG_REG (SUBREG_REG (x));
3482
3483           SUBST_INT (SUBREG_WORD (x),
3484                      SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3485           SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3486         }
3487
3488       /* SUBREG of a hard register => just change the register number
3489          and/or mode.  If the hard register is not valid in that mode,
3490          suppress this combination.  If the hard register is the stack,
3491          frame, or argument pointer, leave this as a SUBREG.  */
3492
3493       if (GET_CODE (SUBREG_REG (x)) == REG
3494           && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3495           && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3496 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3497           && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3498 #endif
3499 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3500           && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3501 #endif
3502           && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3503         {
3504           if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3505                                   mode))
3506             return gen_rtx_REG (mode,
3507                                 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3508           else
3509             return gen_rtx_CLOBBER (mode, const0_rtx);
3510         }
3511
3512       /* For a constant, try to pick up the part we want.  Handle a full
3513          word and low-order part.  Only do this if we are narrowing
3514          the constant; if it is being widened, we have no idea what
3515          the extra bits will have been set to.  */
3516
3517       if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3518           && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3519           && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3520           && GET_MODE_CLASS (mode) == MODE_INT)
3521         {
3522           temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3523                                   0, op0_mode);
3524           if (temp)
3525             return temp;
3526         }
3527
3528       /* If we want a subreg of a constant, at offset 0,
3529          take the low bits.  On a little-endian machine, that's
3530          always valid.  On a big-endian machine, it's valid
3531          only if the constant's mode fits in one word.   Note that we
3532          cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode.  */
3533       if (CONSTANT_P (SUBREG_REG (x))
3534           && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3535               || ! WORDS_BIG_ENDIAN)
3536               ? SUBREG_WORD (x) == 0
3537               : (SUBREG_WORD (x)
3538                  == ((GET_MODE_SIZE (op0_mode)
3539                       - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3540                      / UNITS_PER_WORD)))
3541           && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3542           && (! WORDS_BIG_ENDIAN
3543               || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3544         return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3545
3546       /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3547          since we are saying that the high bits don't matter.  */
3548       if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3549           && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3550         return SUBREG_REG (x);
3551
3552       /* Note that we cannot do any narrowing for non-constants since
3553          we might have been counting on using the fact that some bits were
3554          zero.  We now do this in the SET.  */
3555
3556       break;
3557
3558     case NOT:
3559       /* (not (plus X -1)) can become (neg X).  */
3560       if (GET_CODE (XEXP (x, 0)) == PLUS
3561           && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3562         return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3563
3564       /* Similarly, (not (neg X)) is (plus X -1).  */
3565       if (GET_CODE (XEXP (x, 0)) == NEG)
3566         return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3567                                 constm1_rtx);
3568
3569       /* (not (xor X C)) for C constant is (xor X D) with D = ~ C.  */
3570       if (GET_CODE (XEXP (x, 0)) == XOR
3571           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3572           && (temp = simplify_unary_operation (NOT, mode,
3573                                                XEXP (XEXP (x, 0), 1),
3574                                                mode)) != 0)
3575         return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3576
3577       /* (not (ashift 1 X)) is (rotate ~1 X).  We used to do this for operands
3578          other than 1, but that is not valid.  We could do a similar
3579          simplification for (not (lshiftrt C X)) where C is just the sign bit,
3580          but this doesn't seem common enough to bother with.  */
3581       if (GET_CODE (XEXP (x, 0)) == ASHIFT
3582           && XEXP (XEXP (x, 0), 0) == const1_rtx)
3583         return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3584                                XEXP (XEXP (x, 0), 1));
3585
3586       if (GET_CODE (XEXP (x, 0)) == SUBREG
3587           && subreg_lowpart_p (XEXP (x, 0))
3588           && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3589               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3590           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3591           && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3592         {
3593           enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3594
3595           x = gen_rtx_ROTATE (inner_mode,
3596                               gen_unary (NOT, inner_mode, inner_mode,
3597                                          const1_rtx),
3598                               XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3599           return gen_lowpart_for_combine (mode, x);
3600         }
3601
3602       /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3603          reversing the comparison code if valid.  */
3604       if (STORE_FLAG_VALUE == -1
3605           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3606           && reversible_comparison_p (XEXP (x, 0)))
3607         return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3608                                 mode, XEXP (XEXP (x, 0), 0),
3609                                 XEXP (XEXP (x, 0), 1));
3610
3611       /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3612          is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3613          perform the above simplification.  */
3614
3615       if (STORE_FLAG_VALUE == -1
3616           && XEXP (x, 1) == const1_rtx
3617           && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3618           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3619           && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3620         return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3621
3622       /* Apply De Morgan's laws to reduce number of patterns for machines
3623          with negating logical insns (and-not, nand, etc.).  If result has
3624          only one NOT, put it first, since that is how the patterns are
3625          coded.  */
3626
3627       if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3628         {
3629          rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3630
3631          if (GET_CODE (in1) == NOT)
3632            in1 = XEXP (in1, 0);
3633          else
3634            in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3635
3636          if (GET_CODE (in2) == NOT)
3637            in2 = XEXP (in2, 0);
3638          else if (GET_CODE (in2) == CONST_INT
3639                   && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3640            in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3641          else
3642            in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3643
3644          if (GET_CODE (in2) == NOT)
3645            {
3646              rtx tem = in2;
3647              in2 = in1; in1 = tem;
3648            }
3649
3650          return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3651                                  mode, in1, in2);
3652        }
3653       break;
3654
3655     case NEG:
3656       /* (neg (plus X 1)) can become (not X).  */
3657       if (GET_CODE (XEXP (x, 0)) == PLUS
3658           && XEXP (XEXP (x, 0), 1) == const1_rtx)
3659         return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3660
3661       /* Similarly, (neg (not X)) is (plus X 1).  */
3662       if (GET_CODE (XEXP (x, 0)) == NOT)
3663         return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3664
3665       /* (neg (minus X Y)) can become (minus Y X).  */
3666       if (GET_CODE (XEXP (x, 0)) == MINUS
3667           && (! FLOAT_MODE_P (mode)
3668               /* x-y != -(y-x) with IEEE floating point.  */
3669               || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3670               || flag_fast_math))
3671         return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3672                            XEXP (XEXP (x, 0), 0));
3673
3674       /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
3675       if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3676           && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3677         return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3678
3679       /* NEG commutes with ASHIFT since it is multiplication.  Only do this
3680          if we can then eliminate the NEG (e.g.,
3681          if the operand is a constant).  */
3682
3683       if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3684         {
3685           temp = simplify_unary_operation (NEG, mode,
3686                                            XEXP (XEXP (x, 0), 0), mode);
3687           if (temp)
3688             {
3689               SUBST (XEXP (XEXP (x, 0), 0), temp);
3690               return XEXP (x, 0);
3691             }
3692         }
3693
3694       temp = expand_compound_operation (XEXP (x, 0));
3695
3696       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3697          replaced by (lshiftrt X C).  This will convert
3698          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
3699
3700       if (GET_CODE (temp) == ASHIFTRT
3701           && GET_CODE (XEXP (temp, 1)) == CONST_INT
3702           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3703         return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3704                                      INTVAL (XEXP (temp, 1)));
3705
3706       /* If X has only a single bit that might be nonzero, say, bit I, convert
3707          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3708          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
3709          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
3710          or a SUBREG of one since we'd be making the expression more
3711          complex if it was just a register.  */
3712
3713       if (GET_CODE (temp) != REG
3714           && ! (GET_CODE (temp) == SUBREG
3715                 && GET_CODE (SUBREG_REG (temp)) == REG)
3716           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3717         {
3718           rtx temp1 = simplify_shift_const
3719             (NULL_RTX, ASHIFTRT, mode,
3720              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3721                                    GET_MODE_BITSIZE (mode) - 1 - i),
3722              GET_MODE_BITSIZE (mode) - 1 - i);
3723
3724           /* If all we did was surround TEMP with the two shifts, we
3725              haven't improved anything, so don't use it.  Otherwise,
3726              we are better off with TEMP1.  */
3727           if (GET_CODE (temp1) != ASHIFTRT
3728               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3729               || XEXP (XEXP (temp1, 0), 0) != temp)
3730             return temp1;
3731         }
3732       break;
3733
3734     case TRUNCATE:
3735       /* We can't handle truncation to a partial integer mode here
3736          because we don't know the real bitsize of the partial
3737          integer mode.  */
3738       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3739         break;
3740
3741       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3742           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3743                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3744         SUBST (XEXP (x, 0),
3745                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3746                               GET_MODE_MASK (mode), NULL_RTX, 0));
3747
3748       /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
3749       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3750            || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3751           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3752         return XEXP (XEXP (x, 0), 0);
3753
3754       /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3755          (OP:SI foo:SI) if OP is NEG or ABS.  */
3756       if ((GET_CODE (XEXP (x, 0)) == ABS
3757            || GET_CODE (XEXP (x, 0)) == NEG)
3758           && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3759               || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3760           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3761         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3762                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3763
3764       /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3765          (truncate:SI x).  */
3766       if (GET_CODE (XEXP (x, 0)) == SUBREG
3767           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3768           && subreg_lowpart_p (XEXP (x, 0)))
3769         return SUBREG_REG (XEXP (x, 0));
3770
3771       /* If we know that the value is already truncated, we can
3772          replace the TRUNCATE with a SUBREG.  */
3773       if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3774           && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3775               &~ GET_MODE_MASK (mode)) == 0)
3776         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3777
3778       /* A truncate of a comparison can be replaced with a subreg if
3779          STORE_FLAG_VALUE permits.  This is like the previous test,
3780          but it works even if the comparison is done in a mode larger
3781          than HOST_BITS_PER_WIDE_INT.  */
3782       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3783           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3784           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3785         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3786
3787       /* Similarly, a truncate of a register whose value is a
3788          comparison can be replaced with a subreg if STORE_FLAG_VALUE
3789          permits.  */
3790       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3791           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3792           && (temp = get_last_value (XEXP (x, 0)))
3793           && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3794         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3795
3796       break;
3797
3798     case FLOAT_TRUNCATE:
3799       /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
3800       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3801           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3802         return XEXP (XEXP (x, 0), 0);
3803
3804       /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3805          (OP:SF foo:SF) if OP is NEG or ABS.  */
3806       if ((GET_CODE (XEXP (x, 0)) == ABS
3807            || GET_CODE (XEXP (x, 0)) == NEG)
3808           && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3809           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3810         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3811                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3812
3813       /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3814          is (float_truncate:SF x).  */
3815       if (GET_CODE (XEXP (x, 0)) == SUBREG
3816           && subreg_lowpart_p (XEXP (x, 0))
3817           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3818         return SUBREG_REG (XEXP (x, 0));
3819       break;
3820
3821 #ifdef HAVE_cc0
3822     case COMPARE:
3823       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3824          using cc0, in which case we want to leave it as a COMPARE
3825          so we can distinguish it from a register-register-copy.  */
3826       if (XEXP (x, 1) == const0_rtx)
3827         return XEXP (x, 0);
3828
3829       /* In IEEE floating point, x-0 is not the same as x.  */
3830       if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3831            || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3832            || flag_fast_math)
3833           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3834         return XEXP (x, 0);
3835       break;
3836 #endif
3837
3838     case CONST:
3839       /* (const (const X)) can become (const X).  Do it this way rather than
3840          returning the inner CONST since CONST can be shared with a
3841          REG_EQUAL note.  */
3842       if (GET_CODE (XEXP (x, 0)) == CONST)
3843         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3844       break;
3845
3846 #ifdef HAVE_lo_sum
3847     case LO_SUM:
3848       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
3849          can add in an offset.  find_split_point will split this address up
3850          again if it doesn't match.  */
3851       if (GET_CODE (XEXP (x, 0)) == HIGH
3852           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3853         return XEXP (x, 1);
3854       break;
3855 #endif
3856
3857     case PLUS:
3858       /* If we have (plus (plus (A const) B)), associate it so that CONST is
3859          outermost.  That's because that's the way indexed addresses are
3860          supposed to appear.  This code used to check many more cases, but
3861          they are now checked elsewhere.  */
3862       if (GET_CODE (XEXP (x, 0)) == PLUS
3863           && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3864         return gen_binary (PLUS, mode,
3865                            gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3866                                        XEXP (x, 1)),
3867                            XEXP (XEXP (x, 0), 1));
3868
3869       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3870          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3871          bit-field and can be replaced by either a sign_extend or a
3872          sign_extract.  The `and' may be a zero_extend.  */
3873       if (GET_CODE (XEXP (x, 0)) == XOR
3874           && GET_CODE (XEXP (x, 1)) == CONST_INT
3875           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3876           && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3877           && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3878           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3879           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3880                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3881                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3882                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3883               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3884                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3885                       == i + 1))))
3886         return simplify_shift_const
3887           (NULL_RTX, ASHIFTRT, mode,
3888            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3889                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
3890                                  GET_MODE_BITSIZE (mode) - (i + 1)),
3891            GET_MODE_BITSIZE (mode) - (i + 1));
3892
3893       /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3894          C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3895          is 1.  This produces better code than the alternative immediately
3896          below.  */
3897       if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3898           && reversible_comparison_p (XEXP (x, 0))
3899           && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3900               || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3901         return
3902           gen_unary (NEG, mode, mode,
3903                      gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3904                                  mode, XEXP (XEXP (x, 0), 0),
3905                                  XEXP (XEXP (x, 0), 1)));
3906
3907       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3908          can become (ashiftrt (ashift (xor x 1) C) C) where C is
3909          the bitsize of the mode - 1.  This allows simplification of
3910          "a = (b & 8) == 0;"  */
3911       if (XEXP (x, 1) == constm1_rtx
3912           && GET_CODE (XEXP (x, 0)) != REG
3913           && ! (GET_CODE (XEXP (x,0)) == SUBREG
3914                 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3915           && nonzero_bits (XEXP (x, 0), mode) == 1)
3916         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3917            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3918                                  gen_rtx_combine (XOR, mode,
3919                                                   XEXP (x, 0), const1_rtx),
3920                                  GET_MODE_BITSIZE (mode) - 1),
3921            GET_MODE_BITSIZE (mode) - 1);
3922
3923       /* If we are adding two things that have no bits in common, convert
3924          the addition into an IOR.  This will often be further simplified,
3925          for example in cases like ((a & 1) + (a & 2)), which can
3926          become a & 3.  */
3927
3928       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3929           && (nonzero_bits (XEXP (x, 0), mode)
3930               & nonzero_bits (XEXP (x, 1), mode)) == 0)
3931         return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3932       break;
3933
3934     case MINUS:
3935       /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3936          by reversing the comparison code if valid.  */
3937       if (STORE_FLAG_VALUE == 1
3938           && XEXP (x, 0) == const1_rtx
3939           && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3940           && reversible_comparison_p (XEXP (x, 1)))
3941         return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3942                            mode, XEXP (XEXP (x, 1), 0),
3943                                 XEXP (XEXP (x, 1), 1));
3944
3945       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3946          (and <foo> (const_int pow2-1))  */
3947       if (GET_CODE (XEXP (x, 1)) == AND
3948           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3949           && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3950           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3951         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3952                                        - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3953
3954       /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3955          integers.  */
3956       if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3957         return gen_binary (MINUS, mode,
3958                            gen_binary (MINUS, mode, XEXP (x, 0),
3959                                        XEXP (XEXP (x, 1), 0)),
3960                            XEXP (XEXP (x, 1), 1));
3961       break;
3962
3963     case MULT:
3964       /* If we have (mult (plus A B) C), apply the distributive law and then
3965          the inverse distributive law to see if things simplify.  This
3966          occurs mostly in addresses, often when unrolling loops.  */
3967
3968       if (GET_CODE (XEXP (x, 0)) == PLUS)
3969         {
3970           x = apply_distributive_law
3971             (gen_binary (PLUS, mode,
3972                          gen_binary (MULT, mode,
3973                                      XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3974                          gen_binary (MULT, mode,
3975                                      XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3976
3977           if (GET_CODE (x) != MULT)
3978             return x;
3979         }
3980       break;
3981
3982     case UDIV:
3983       /* If this is a divide by a power of two, treat it as a shift if
3984          its first operand is a shift.  */
3985       if (GET_CODE (XEXP (x, 1)) == CONST_INT
3986           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3987           && (GET_CODE (XEXP (x, 0)) == ASHIFT
3988               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3989               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3990               || GET_CODE (XEXP (x, 0)) == ROTATE
3991               || GET_CODE (XEXP (x, 0)) == ROTATERT))
3992         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3993       break;
3994
3995     case EQ:  case NE:
3996     case GT:  case GTU:  case GE:  case GEU:
3997     case LT:  case LTU:  case LE:  case LEU:
3998       /* If the first operand is a condition code, we can't do anything
3999          with it.  */
4000       if (GET_CODE (XEXP (x, 0)) == COMPARE
4001           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4002 #ifdef HAVE_cc0
4003               && XEXP (x, 0) != cc0_rtx
4004 #endif
4005                ))
4006         {
4007           rtx op0 = XEXP (x, 0);
4008           rtx op1 = XEXP (x, 1);
4009           enum rtx_code new_code;
4010
4011           if (GET_CODE (op0) == COMPARE)
4012             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4013
4014           /* Simplify our comparison, if possible.  */
4015           new_code = simplify_comparison (code, &op0, &op1);
4016
4017           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4018              if only the low-order bit is possibly nonzero in X (such as when
4019              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4020              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4021              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4022              (plus X 1).
4023
4024              Remove any ZERO_EXTRACT we made when thinking this was a
4025              comparison.  It may now be simpler to use, e.g., an AND.  If a
4026              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4027              the call to make_compound_operation in the SET case.  */
4028
4029           if (STORE_FLAG_VALUE == 1
4030               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4031               && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4032             return gen_lowpart_for_combine (mode,
4033                                             expand_compound_operation (op0));
4034
4035           else if (STORE_FLAG_VALUE == 1
4036                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4037                    && op1 == const0_rtx
4038                    && (num_sign_bit_copies (op0, mode)
4039                        == GET_MODE_BITSIZE (mode)))
4040             {
4041               op0 = expand_compound_operation (op0);
4042               return gen_unary (NEG, mode, mode,
4043                                 gen_lowpart_for_combine (mode, op0));
4044             }
4045
4046           else if (STORE_FLAG_VALUE == 1
4047                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4048                    && op1 == const0_rtx
4049                    && nonzero_bits (op0, mode) == 1)
4050             {
4051               op0 = expand_compound_operation (op0);
4052               return gen_binary (XOR, mode,
4053                                  gen_lowpart_for_combine (mode, op0),
4054                                  const1_rtx);
4055             }
4056
4057           else if (STORE_FLAG_VALUE == 1
4058                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4059                    && op1 == const0_rtx
4060                    && (num_sign_bit_copies (op0, mode)
4061                        == GET_MODE_BITSIZE (mode)))
4062             {
4063               op0 = expand_compound_operation (op0);
4064               return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4065             }
4066
4067           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4068              those above.  */
4069           if (STORE_FLAG_VALUE == -1
4070               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4071               && op1 == const0_rtx
4072               && (num_sign_bit_copies (op0, mode)
4073                   == GET_MODE_BITSIZE (mode)))
4074             return gen_lowpart_for_combine (mode,
4075                                             expand_compound_operation (op0));
4076
4077           else if (STORE_FLAG_VALUE == -1
4078                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4079                    && op1 == const0_rtx
4080                    && nonzero_bits (op0, mode) == 1)
4081             {
4082               op0 = expand_compound_operation (op0);
4083               return gen_unary (NEG, mode, mode,
4084                                 gen_lowpart_for_combine (mode, op0));
4085             }
4086
4087           else if (STORE_FLAG_VALUE == -1
4088                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4089                    && op1 == const0_rtx
4090                    && (num_sign_bit_copies (op0, mode)
4091                        == GET_MODE_BITSIZE (mode)))
4092             {
4093               op0 = expand_compound_operation (op0);
4094               return gen_unary (NOT, mode, mode,
4095                                 gen_lowpart_for_combine (mode, op0));
4096             }
4097
4098           /* If X is 0/1, (eq X 0) is X-1.  */
4099           else if (STORE_FLAG_VALUE == -1
4100                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4101                    && op1 == const0_rtx
4102                    && nonzero_bits (op0, mode) == 1)
4103             {
4104               op0 = expand_compound_operation (op0);
4105               return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4106             }
4107
4108           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4109              one bit that might be nonzero, we can convert (ne x 0) to
4110              (ashift x c) where C puts the bit in the sign bit.  Remove any
4111              AND with STORE_FLAG_VALUE when we are done, since we are only
4112              going to test the sign bit.  */
4113           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4114               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4115               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4116                   == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4117               && op1 == const0_rtx
4118               && mode == GET_MODE (op0)
4119               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4120             {
4121               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4122                                         expand_compound_operation (op0),
4123                                         GET_MODE_BITSIZE (mode) - 1 - i);
4124               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4125                 return XEXP (x, 0);
4126               else
4127                 return x;
4128             }
4129
4130           /* If the code changed, return a whole new comparison.  */
4131           if (new_code != code)
4132             return gen_rtx_combine (new_code, mode, op0, op1);
4133
4134           /* Otherwise, keep this operation, but maybe change its operands.
4135              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4136           SUBST (XEXP (x, 0), op0);
4137           SUBST (XEXP (x, 1), op1);
4138         }
4139       break;
4140
4141     case IF_THEN_ELSE:
4142       return simplify_if_then_else (x);
4143
4144     case ZERO_EXTRACT:
4145     case SIGN_EXTRACT:
4146     case ZERO_EXTEND:
4147     case SIGN_EXTEND:
4148       /* If we are processing SET_DEST, we are done.  */
4149       if (in_dest)
4150         return x;
4151
4152       return expand_compound_operation (x);
4153
4154     case SET:
4155       return simplify_set (x);
4156
4157     case AND:
4158     case IOR:
4159     case XOR:
4160       return simplify_logical (x, last);
4161
4162     case ABS:
4163       /* (abs (neg <foo>)) -> (abs <foo>) */
4164       if (GET_CODE (XEXP (x, 0)) == NEG)
4165         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4166
4167       /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4168          do nothing.  */
4169       if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4170         break;
4171
4172       /* If operand is something known to be positive, ignore the ABS.  */
4173       if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4174           || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4175                <= HOST_BITS_PER_WIDE_INT)
4176               && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4177                    & ((HOST_WIDE_INT) 1
4178                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4179                   == 0)))
4180         return XEXP (x, 0);
4181
4182
4183       /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
4184       if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4185         return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4186
4187       break;
4188
4189     case FFS:
4190       /* (ffs (*_extend <X>)) = (ffs <X>) */
4191       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4192           || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4193         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4194       break;
4195
4196     case FLOAT:
4197       /* (float (sign_extend <X>)) = (float <X>).  */
4198       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4199         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4200       break;
4201
4202     case ASHIFT:
4203     case LSHIFTRT:
4204     case ASHIFTRT:
4205     case ROTATE:
4206     case ROTATERT:
4207       /* If this is a shift by a constant amount, simplify it.  */
4208       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4209         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4210                                      INTVAL (XEXP (x, 1)));
4211
4212 #ifdef SHIFT_COUNT_TRUNCATED
4213       else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4214         SUBST (XEXP (x, 1),
4215                force_to_mode (XEXP (x, 1), GET_MODE (x),
4216                               ((HOST_WIDE_INT) 1
4217                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4218                               - 1,
4219                               NULL_RTX, 0));
4220 #endif
4221
4222       break;
4223
4224     default:
4225       break;
4226     }
4227
4228   return x;
4229 }
4230 \f
4231 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4232
4233 static rtx
4234 simplify_if_then_else (x)
4235      rtx x;
4236 {
4237   enum machine_mode mode = GET_MODE (x);
4238   rtx cond = XEXP (x, 0);
4239   rtx true = XEXP (x, 1);
4240   rtx false = XEXP (x, 2);
4241   enum rtx_code true_code = GET_CODE (cond);
4242   int comparison_p = GET_RTX_CLASS (true_code) == '<';
4243   rtx temp;
4244   int i;
4245
4246   /* Simplify storing of the truth value.  */
4247   if (comparison_p && true == const_true_rtx && false == const0_rtx)
4248     return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4249
4250   /* Also when the truth value has to be reversed.  */
4251   if (comparison_p && reversible_comparison_p (cond)
4252       && true == const0_rtx && false == const_true_rtx)
4253     return gen_binary (reverse_condition (true_code),
4254                        mode, XEXP (cond, 0), XEXP (cond, 1));
4255
4256   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4257      in it is being compared against certain values.  Get the true and false
4258      comparisons and see if that says anything about the value of each arm.  */
4259
4260   if (comparison_p && reversible_comparison_p (cond)
4261       && GET_CODE (XEXP (cond, 0)) == REG)
4262     {
4263       HOST_WIDE_INT nzb;
4264       rtx from = XEXP (cond, 0);
4265       enum rtx_code false_code = reverse_condition (true_code);
4266       rtx true_val = XEXP (cond, 1);
4267       rtx false_val = true_val;
4268       int swapped = 0;
4269
4270       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4271
4272       if (false_code == EQ)
4273         {
4274           swapped = 1, true_code = EQ, false_code = NE;
4275           temp = true, true = false, false = temp;
4276         }
4277
4278       /* If we are comparing against zero and the expression being tested has
4279          only a single bit that might be nonzero, that is its value when it is
4280          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4281
4282       if (true_code == EQ && true_val == const0_rtx
4283           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4284         false_code = EQ, false_val = GEN_INT (nzb);
4285       else if (true_code == EQ && true_val == const0_rtx
4286                && (num_sign_bit_copies (from, GET_MODE (from))
4287                    == GET_MODE_BITSIZE (GET_MODE (from))))
4288         false_code = EQ, false_val = constm1_rtx;
4289
4290       /* Now simplify an arm if we know the value of the register in the
4291          branch and it is used in the arm.  Be careful due to the potential
4292          of locally-shared RTL.  */
4293
4294       if (reg_mentioned_p (from, true))
4295         true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4296                       pc_rtx, pc_rtx, 0, 0);
4297       if (reg_mentioned_p (from, false))
4298         false = subst (known_cond (copy_rtx (false), false_code,
4299                                    from, false_val),
4300                        pc_rtx, pc_rtx, 0, 0);
4301
4302       SUBST (XEXP (x, 1), swapped ? false : true);
4303       SUBST (XEXP (x, 2), swapped ? true : false);
4304
4305       true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4306     }
4307
4308   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4309      reversed, do so to avoid needing two sets of patterns for
4310      subtract-and-branch insns.  Similarly if we have a constant in the true
4311      arm, the false arm is the same as the first operand of the comparison, or
4312      the false arm is more complicated than the true arm.  */
4313
4314   if (comparison_p && reversible_comparison_p (cond)
4315       && (true == pc_rtx
4316           || (CONSTANT_P (true)
4317               && GET_CODE (false) != CONST_INT && false != pc_rtx)
4318           || true == const0_rtx
4319           || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4320               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4321           || (GET_CODE (true) == SUBREG
4322               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4323               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4324           || reg_mentioned_p (true, false)
4325           || rtx_equal_p (false, XEXP (cond, 0))))
4326     {
4327       true_code = reverse_condition (true_code);
4328       SUBST (XEXP (x, 0),
4329              gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4330                          XEXP (cond, 1)));
4331
4332       SUBST (XEXP (x, 1), false);
4333       SUBST (XEXP (x, 2), true);
4334
4335       temp = true, true = false, false = temp, cond = XEXP (x, 0);
4336
4337       /* It is possible that the conditional has been simplified out.  */
4338       true_code = GET_CODE (cond);
4339       comparison_p = GET_RTX_CLASS (true_code) == '<';
4340     }
4341
4342   /* If the two arms are identical, we don't need the comparison.  */
4343
4344   if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4345     return true;
4346
4347   /* Convert a == b ? b : a to "a".  */
4348   if (true_code == EQ && ! side_effects_p (cond)
4349       && rtx_equal_p (XEXP (cond, 0), false)
4350       && rtx_equal_p (XEXP (cond, 1), true))
4351     return false;
4352   else if (true_code == NE && ! side_effects_p (cond)
4353            && rtx_equal_p (XEXP (cond, 0), true)
4354            && rtx_equal_p (XEXP (cond, 1), false))
4355     return true;
4356
4357   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4358
4359   if (GET_MODE_CLASS (mode) == MODE_INT
4360       && GET_CODE (false) == NEG
4361       && rtx_equal_p (true, XEXP (false, 0))
4362       && comparison_p
4363       && rtx_equal_p (true, XEXP (cond, 0))
4364       && ! side_effects_p (true))
4365     switch (true_code)
4366       {
4367       case GT:
4368       case GE:
4369         return gen_unary (ABS, mode, mode, true);
4370       case LT:
4371       case LE:
4372         return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4373     default:
4374       break;
4375       }
4376
4377   /* Look for MIN or MAX.  */
4378
4379   if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4380       && comparison_p
4381       && rtx_equal_p (XEXP (cond, 0), true)
4382       && rtx_equal_p (XEXP (cond, 1), false)
4383       && ! side_effects_p (cond))
4384     switch (true_code)
4385       {
4386       case GE:
4387       case GT:
4388         return gen_binary (SMAX, mode, true, false);
4389       case LE:
4390       case LT:
4391         return gen_binary (SMIN, mode, true, false);
4392       case GEU:
4393       case GTU:
4394         return gen_binary (UMAX, mode, true, false);
4395       case LEU:
4396       case LTU:
4397         return gen_binary (UMIN, mode, true, false);
4398       default:
4399         break;
4400       }
4401
4402   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4403      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4404      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4405      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4406      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4407      neither 1 or -1, but it isn't worth checking for.  */
4408
4409   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4410       && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4411     {
4412       rtx t = make_compound_operation (true, SET);
4413       rtx f = make_compound_operation (false, SET);
4414       rtx cond_op0 = XEXP (cond, 0);
4415       rtx cond_op1 = XEXP (cond, 1);
4416       enum rtx_code op, extend_op = NIL;
4417       enum machine_mode m = mode;
4418       rtx z = 0, c1;
4419
4420       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4421            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4422            || GET_CODE (t) == ASHIFT
4423            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4424           && rtx_equal_p (XEXP (t, 0), f))
4425         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4426
4427       /* If an identity-zero op is commutative, check whether there
4428          would be a match if we swapped the operands.  */
4429       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4430                 || GET_CODE (t) == XOR)
4431                && rtx_equal_p (XEXP (t, 1), f))
4432         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4433       else if (GET_CODE (t) == SIGN_EXTEND
4434                && (GET_CODE (XEXP (t, 0)) == PLUS
4435                    || GET_CODE (XEXP (t, 0)) == MINUS
4436                    || GET_CODE (XEXP (t, 0)) == IOR
4437                    || GET_CODE (XEXP (t, 0)) == XOR
4438                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4439                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4440                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4441                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4442                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4443                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4444                && (num_sign_bit_copies (f, GET_MODE (f))
4445                    > (GET_MODE_BITSIZE (mode)
4446                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4447         {
4448           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4449           extend_op = SIGN_EXTEND;
4450           m = GET_MODE (XEXP (t, 0));
4451         }
4452       else if (GET_CODE (t) == SIGN_EXTEND
4453                && (GET_CODE (XEXP (t, 0)) == PLUS
4454                    || GET_CODE (XEXP (t, 0)) == IOR
4455                    || GET_CODE (XEXP (t, 0)) == XOR)
4456                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4457                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4458                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4459                && (num_sign_bit_copies (f, GET_MODE (f))
4460                    > (GET_MODE_BITSIZE (mode)
4461                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4462         {
4463           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4464           extend_op = SIGN_EXTEND;
4465           m = GET_MODE (XEXP (t, 0));
4466         }
4467       else if (GET_CODE (t) == ZERO_EXTEND
4468                && (GET_CODE (XEXP (t, 0)) == PLUS
4469                    || GET_CODE (XEXP (t, 0)) == MINUS
4470                    || GET_CODE (XEXP (t, 0)) == IOR
4471                    || GET_CODE (XEXP (t, 0)) == XOR
4472                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4473                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4474                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4475                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4476                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4477                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4478                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4479                && ((nonzero_bits (f, GET_MODE (f))
4480                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4481                    == 0))
4482         {
4483           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4484           extend_op = ZERO_EXTEND;
4485           m = GET_MODE (XEXP (t, 0));
4486         }
4487       else if (GET_CODE (t) == ZERO_EXTEND
4488                && (GET_CODE (XEXP (t, 0)) == PLUS
4489                    || GET_CODE (XEXP (t, 0)) == IOR
4490                    || GET_CODE (XEXP (t, 0)) == XOR)
4491                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4492                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4493                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4494                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4495                && ((nonzero_bits (f, GET_MODE (f))
4496                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4497                    == 0))
4498         {
4499           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4500           extend_op = ZERO_EXTEND;
4501           m = GET_MODE (XEXP (t, 0));
4502         }
4503
4504       if (z)
4505         {
4506           temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4507                         pc_rtx, pc_rtx, 0, 0);
4508           temp = gen_binary (MULT, m, temp,
4509                              gen_binary (MULT, m, c1, const_true_rtx));
4510           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4511           temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4512
4513           if (extend_op != NIL)
4514             temp = gen_unary (extend_op, mode, m, temp);
4515
4516           return temp;
4517         }
4518     }
4519
4520   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4521      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4522      negation of a single bit, we can convert this operation to a shift.  We
4523      can actually do this more generally, but it doesn't seem worth it.  */
4524
4525   if (true_code == NE && XEXP (cond, 1) == const0_rtx
4526       && false == const0_rtx && GET_CODE (true) == CONST_INT
4527       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4528            && (i = exact_log2 (INTVAL (true))) >= 0)
4529           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4530                == GET_MODE_BITSIZE (mode))
4531               && (i = exact_log2 (- INTVAL (true))) >= 0)))
4532     return
4533       simplify_shift_const (NULL_RTX, ASHIFT, mode,
4534                             gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4535
4536   return x;
4537 }
4538 \f
4539 /* Simplify X, a SET expression.  Return the new expression.  */
4540
4541 static rtx
4542 simplify_set (x)
4543      rtx x;
4544 {
4545   rtx src = SET_SRC (x);
4546   rtx dest = SET_DEST (x);
4547   enum machine_mode mode
4548     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4549   rtx other_insn;
4550   rtx *cc_use;
4551
4552   /* (set (pc) (return)) gets written as (return).  */
4553   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4554     return src;
4555
4556   /* Now that we know for sure which bits of SRC we are using, see if we can
4557      simplify the expression for the object knowing that we only need the
4558      low-order bits.  */
4559
4560   if (GET_MODE_CLASS (mode) == MODE_INT)
4561     src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4562
4563   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4564      the comparison result and try to simplify it unless we already have used
4565      undobuf.other_insn.  */
4566   if ((GET_CODE (src) == COMPARE
4567 #ifdef HAVE_cc0
4568        || dest == cc0_rtx
4569 #endif
4570        )
4571       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4572       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4573       && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4574       && rtx_equal_p (XEXP (*cc_use, 0), dest))
4575     {
4576       enum rtx_code old_code = GET_CODE (*cc_use);
4577       enum rtx_code new_code;
4578       rtx op0, op1;
4579       int other_changed = 0;
4580       enum machine_mode compare_mode = GET_MODE (dest);
4581
4582       if (GET_CODE (src) == COMPARE)
4583         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4584       else
4585         op0 = src, op1 = const0_rtx;
4586
4587       /* Simplify our comparison, if possible.  */
4588       new_code = simplify_comparison (old_code, &op0, &op1);
4589
4590 #ifdef EXTRA_CC_MODES
4591       /* If this machine has CC modes other than CCmode, check to see if we
4592          need to use a different CC mode here.  */
4593       compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4594 #endif /* EXTRA_CC_MODES */
4595
4596 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4597       /* If the mode changed, we have to change SET_DEST, the mode in the
4598          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
4599          a hard register, just build new versions with the proper mode.  If it
4600          is a pseudo, we lose unless it is only time we set the pseudo, in
4601          which case we can safely change its mode.  */
4602       if (compare_mode != GET_MODE (dest))
4603         {
4604           int regno = REGNO (dest);
4605           rtx new_dest = gen_rtx_REG (compare_mode, regno);
4606
4607           if (regno < FIRST_PSEUDO_REGISTER
4608               || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4609             {
4610               if (regno >= FIRST_PSEUDO_REGISTER)
4611                 SUBST (regno_reg_rtx[regno], new_dest);
4612
4613               SUBST (SET_DEST (x), new_dest);
4614               SUBST (XEXP (*cc_use, 0), new_dest);
4615               other_changed = 1;
4616
4617               dest = new_dest;
4618             }
4619         }
4620 #endif
4621
4622       /* If the code changed, we have to build a new comparison in
4623          undobuf.other_insn.  */
4624       if (new_code != old_code)
4625         {
4626           unsigned HOST_WIDE_INT mask;
4627
4628           SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4629                                            dest, const0_rtx));
4630
4631           /* If the only change we made was to change an EQ into an NE or
4632              vice versa, OP0 has only one bit that might be nonzero, and OP1
4633              is zero, check if changing the user of the condition code will
4634              produce a valid insn.  If it won't, we can keep the original code
4635              in that insn by surrounding our operation with an XOR.  */
4636
4637           if (((old_code == NE && new_code == EQ)
4638                || (old_code == EQ && new_code == NE))
4639               && ! other_changed && op1 == const0_rtx
4640               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4641               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4642             {
4643               rtx pat = PATTERN (other_insn), note = 0;
4644               int scratches;
4645
4646               if ((recog_for_combine (&pat, other_insn, &note, &scratches) < 0
4647                    && ! check_asm_operands (pat)))
4648                 {
4649                   PUT_CODE (*cc_use, old_code);
4650                   other_insn = 0;
4651
4652                   op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4653                 }
4654             }
4655
4656           other_changed = 1;
4657         }
4658
4659       if (other_changed)
4660         undobuf.other_insn = other_insn;
4661
4662 #ifdef HAVE_cc0
4663       /* If we are now comparing against zero, change our source if
4664          needed.  If we do not use cc0, we always have a COMPARE.  */
4665       if (op1 == const0_rtx && dest == cc0_rtx)
4666         {
4667           SUBST (SET_SRC (x), op0);
4668           src = op0;
4669         }
4670       else
4671 #endif
4672
4673       /* Otherwise, if we didn't previously have a COMPARE in the
4674          correct mode, we need one.  */
4675       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4676         {
4677           SUBST (SET_SRC (x),
4678                  gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4679           src = SET_SRC (x);
4680         }
4681       else
4682         {
4683           /* Otherwise, update the COMPARE if needed.  */
4684           SUBST (XEXP (src, 0), op0);
4685           SUBST (XEXP (src, 1), op1);
4686         }
4687     }
4688   else
4689     {
4690       /* Get SET_SRC in a form where we have placed back any
4691          compound expressions.  Then do the checks below.  */
4692       src = make_compound_operation (src, SET);
4693       SUBST (SET_SRC (x), src);
4694     }
4695
4696   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4697      and X being a REG or (subreg (reg)), we may be able to convert this to
4698      (set (subreg:m2 x) (op)).
4699
4700      We can always do this if M1 is narrower than M2 because that means that
4701      we only care about the low bits of the result.
4702
4703      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4704      perform a narrower operation that requested since the high-order bits will
4705      be undefined.  On machine where it is defined, this transformation is safe
4706      as long as M1 and M2 have the same number of words.  */
4707
4708   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4709       && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4710       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4711            / UNITS_PER_WORD)
4712           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4713                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4714 #ifndef WORD_REGISTER_OPERATIONS
4715       && (GET_MODE_SIZE (GET_MODE (src))
4716           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4717 #endif
4718 #ifdef CLASS_CANNOT_CHANGE_SIZE
4719       && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4720             && (TEST_HARD_REG_BIT
4721                 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4722                  REGNO (dest)))
4723             && (GET_MODE_SIZE (GET_MODE (src))
4724                 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4725 #endif
4726       && (GET_CODE (dest) == REG
4727           || (GET_CODE (dest) == SUBREG
4728               && GET_CODE (SUBREG_REG (dest)) == REG)))
4729     {
4730       SUBST (SET_DEST (x),
4731              gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4732                                       dest));
4733       SUBST (SET_SRC (x), SUBREG_REG (src));
4734
4735       src = SET_SRC (x), dest = SET_DEST (x);
4736     }
4737
4738 #ifdef LOAD_EXTEND_OP
4739   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4740      would require a paradoxical subreg.  Replace the subreg with a
4741      zero_extend to avoid the reload that would otherwise be required.  */
4742
4743   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4744       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4745       && SUBREG_WORD (src) == 0
4746       && (GET_MODE_SIZE (GET_MODE (src))
4747           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4748       && GET_CODE (SUBREG_REG (src)) == MEM)
4749     {
4750       SUBST (SET_SRC (x),
4751              gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4752                               GET_MODE (src), XEXP (src, 0)));
4753
4754       src = SET_SRC (x);
4755     }
4756 #endif
4757
4758   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4759      are comparing an item known to be 0 or -1 against 0, use a logical
4760      operation instead. Check for one of the arms being an IOR of the other
4761      arm with some value.  We compute three terms to be IOR'ed together.  In
4762      practice, at most two will be nonzero.  Then we do the IOR's.  */
4763
4764   if (GET_CODE (dest) != PC
4765       && GET_CODE (src) == IF_THEN_ELSE
4766       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4767       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4768       && XEXP (XEXP (src, 0), 1) == const0_rtx
4769       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4770 #ifdef HAVE_conditional_move
4771       && ! can_conditionally_move_p (GET_MODE (src))
4772 #endif
4773       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4774                                GET_MODE (XEXP (XEXP (src, 0), 0)))
4775           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4776       && ! side_effects_p (src))
4777     {
4778       rtx true = (GET_CODE (XEXP (src, 0)) == NE
4779                       ? XEXP (src, 1) : XEXP (src, 2));
4780       rtx false = (GET_CODE (XEXP (src, 0)) == NE
4781                    ? XEXP (src, 2) : XEXP (src, 1));
4782       rtx term1 = const0_rtx, term2, term3;
4783
4784       if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4785         term1 = false, true = XEXP (true, 1), false = const0_rtx;
4786       else if (GET_CODE (true) == IOR
4787                && rtx_equal_p (XEXP (true, 1), false))
4788         term1 = false, true = XEXP (true, 0), false = const0_rtx;
4789       else if (GET_CODE (false) == IOR
4790                && rtx_equal_p (XEXP (false, 0), true))
4791         term1 = true, false = XEXP (false, 1), true = const0_rtx;
4792       else if (GET_CODE (false) == IOR
4793                && rtx_equal_p (XEXP (false, 1), true))
4794         term1 = true, false = XEXP (false, 0), true = const0_rtx;
4795
4796       term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4797       term3 = gen_binary (AND, GET_MODE (src),
4798                           gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4799                                      XEXP (XEXP (src, 0), 0)),
4800                           false);
4801
4802       SUBST (SET_SRC (x),
4803              gen_binary (IOR, GET_MODE (src),
4804                          gen_binary (IOR, GET_MODE (src), term1, term2),
4805                          term3));
4806
4807       src = SET_SRC (x);
4808     }
4809
4810   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4811      whole thing fail.  */
4812   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4813     return src;
4814   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4815     return dest;
4816   else
4817     /* Convert this into a field assignment operation, if possible.  */
4818     return make_field_assignment (x);
4819 }
4820 \f
4821 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4822    result.  LAST is nonzero if this is the last retry.  */
4823
4824 static rtx
4825 simplify_logical (x, last)
4826      rtx x;
4827      int last;
4828 {
4829   enum machine_mode mode = GET_MODE (x);
4830   rtx op0 = XEXP (x, 0);
4831   rtx op1 = XEXP (x, 1);
4832
4833   switch (GET_CODE (x))
4834     {
4835     case AND:
4836       /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4837          insn (and may simplify more).  */
4838       if (GET_CODE (op0) == XOR
4839           && rtx_equal_p (XEXP (op0, 0), op1)
4840           && ! side_effects_p (op1))
4841         x = gen_binary (AND, mode,
4842                         gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4843
4844       if (GET_CODE (op0) == XOR
4845           && rtx_equal_p (XEXP (op0, 1), op1)
4846           && ! side_effects_p (op1))
4847         x = gen_binary (AND, mode,
4848                         gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4849
4850       /* Similarly for (~ (A ^ B)) & A.  */
4851       if (GET_CODE (op0) == NOT
4852           && GET_CODE (XEXP (op0, 0)) == XOR
4853           && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4854           && ! side_effects_p (op1))
4855         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4856
4857       if (GET_CODE (op0) == NOT
4858           && GET_CODE (XEXP (op0, 0)) == XOR
4859           && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4860           && ! side_effects_p (op1))
4861         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4862
4863       if (GET_CODE (op1) == CONST_INT)
4864         {
4865           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4866
4867           /* If we have (ior (and (X C1) C2)) and the next restart would be
4868              the last, simplify this by making C1 as small as possible
4869              and then exit.  */
4870           if (last
4871               && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4872               && GET_CODE (XEXP (op0, 1)) == CONST_INT
4873               && GET_CODE (op1) == CONST_INT)
4874             return gen_binary (IOR, mode,
4875                                gen_binary (AND, mode, XEXP (op0, 0),
4876                                            GEN_INT (INTVAL (XEXP (op0, 1))
4877                                                     & ~ INTVAL (op1))), op1);
4878
4879           if (GET_CODE (x) != AND)
4880             return x;
4881
4882           if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4883               || GET_RTX_CLASS (GET_CODE (x)) == '2')
4884             op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4885         }
4886
4887       /* Convert (A | B) & A to A.  */
4888       if (GET_CODE (op0) == IOR
4889           && (rtx_equal_p (XEXP (op0, 0), op1)
4890               || rtx_equal_p (XEXP (op0, 1), op1))
4891           && ! side_effects_p (XEXP (op0, 0))
4892           && ! side_effects_p (XEXP (op0, 1)))
4893         return op1;
4894
4895       /* In the following group of tests (and those in case IOR below),
4896          we start with some combination of logical operations and apply
4897          the distributive law followed by the inverse distributive law.
4898          Most of the time, this results in no change.  However, if some of
4899          the operands are the same or inverses of each other, simplifications
4900          will result.
4901
4902          For example, (and (ior A B) (not B)) can occur as the result of
4903          expanding a bit field assignment.  When we apply the distributive
4904          law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4905          which then simplifies to (and (A (not B))).
4906
4907          If we have (and (ior A B) C), apply the distributive law and then
4908          the inverse distributive law to see if things simplify.  */
4909
4910       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4911         {
4912           x = apply_distributive_law
4913             (gen_binary (GET_CODE (op0), mode,
4914                          gen_binary (AND, mode, XEXP (op0, 0), op1),
4915                          gen_binary (AND, mode, XEXP (op0, 1), op1)));
4916           if (GET_CODE (x) != AND)
4917             return x;
4918         }
4919
4920       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4921         return apply_distributive_law
4922           (gen_binary (GET_CODE (op1), mode,
4923                        gen_binary (AND, mode, XEXP (op1, 0), op0),
4924                        gen_binary (AND, mode, XEXP (op1, 1), op0)));
4925
4926       /* Similarly, taking advantage of the fact that
4927          (and (not A) (xor B C)) == (xor (ior A B) (ior A C))  */
4928
4929       if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4930         return apply_distributive_law
4931           (gen_binary (XOR, mode,
4932                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4933                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4934
4935       else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4936         return apply_distributive_law
4937           (gen_binary (XOR, mode,
4938                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4939                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4940       break;
4941
4942     case IOR:
4943       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
4944       if (GET_CODE (op1) == CONST_INT
4945           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4946           && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4947         return op1;
4948
4949       /* Convert (A & B) | A to A.  */
4950       if (GET_CODE (op0) == AND
4951           && (rtx_equal_p (XEXP (op0, 0), op1)
4952               || rtx_equal_p (XEXP (op0, 1), op1))
4953           && ! side_effects_p (XEXP (op0, 0))
4954           && ! side_effects_p (XEXP (op0, 1)))
4955         return op1;
4956
4957       /* If we have (ior (and A B) C), apply the distributive law and then
4958          the inverse distributive law to see if things simplify.  */
4959
4960       if (GET_CODE (op0) == AND)
4961         {
4962           x = apply_distributive_law
4963             (gen_binary (AND, mode,
4964                          gen_binary (IOR, mode, XEXP (op0, 0), op1),
4965                          gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4966
4967           if (GET_CODE (x) != IOR)
4968             return x;
4969         }
4970
4971       if (GET_CODE (op1) == AND)
4972         {
4973           x = apply_distributive_law
4974             (gen_binary (AND, mode,
4975                          gen_binary (IOR, mode, XEXP (op1, 0), op0),
4976                          gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4977
4978           if (GET_CODE (x) != IOR)
4979             return x;
4980         }
4981
4982       /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4983          mode size to (rotate A CX).  */
4984
4985       if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4986            || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4987           && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4988           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4989           && GET_CODE (XEXP (op1, 1)) == CONST_INT
4990           && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4991               == GET_MODE_BITSIZE (mode)))
4992         return gen_rtx_ROTATE (mode, XEXP (op0, 0),
4993                                (GET_CODE (op0) == ASHIFT
4994                                 ? XEXP (op0, 1) : XEXP (op1, 1)));
4995
4996       /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4997          a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
4998          does not affect any of the bits in OP1, it can really be done
4999          as a PLUS and we can associate.  We do this by seeing if OP1
5000          can be safely shifted left C bits.  */
5001       if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5002           && GET_CODE (XEXP (op0, 0)) == PLUS
5003           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5004           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5005           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5006         {
5007           int count = INTVAL (XEXP (op0, 1));
5008           HOST_WIDE_INT mask = INTVAL (op1) << count;
5009
5010           if (mask >> count == INTVAL (op1)
5011               && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5012             {
5013               SUBST (XEXP (XEXP (op0, 0), 1),
5014                      GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5015               return op0;
5016             }
5017         }
5018       break;
5019
5020     case XOR:
5021       /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5022          Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5023          (NOT y).  */
5024       {
5025         int num_negated = 0;
5026
5027         if (GET_CODE (op0) == NOT)
5028           num_negated++, op0 = XEXP (op0, 0);
5029         if (GET_CODE (op1) == NOT)
5030           num_negated++, op1 = XEXP (op1, 0);
5031
5032         if (num_negated == 2)
5033           {
5034             SUBST (XEXP (x, 0), op0);
5035             SUBST (XEXP (x, 1), op1);
5036           }
5037         else if (num_negated == 1)
5038           return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5039       }
5040
5041       /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
5042          correspond to a machine insn or result in further simplifications
5043          if B is a constant.  */
5044
5045       if (GET_CODE (op0) == AND
5046           && rtx_equal_p (XEXP (op0, 1), op1)
5047           && ! side_effects_p (op1))
5048         return gen_binary (AND, mode,
5049                            gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5050                            op1);
5051
5052       else if (GET_CODE (op0) == AND
5053                && rtx_equal_p (XEXP (op0, 0), op1)
5054                && ! side_effects_p (op1))
5055         return gen_binary (AND, mode,
5056                            gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5057                            op1);
5058
5059       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5060          comparison if STORE_FLAG_VALUE is 1.  */
5061       if (STORE_FLAG_VALUE == 1
5062           && op1 == const1_rtx
5063           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5064           && reversible_comparison_p (op0))
5065         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5066                                 mode, XEXP (op0, 0), XEXP (op0, 1));
5067
5068       /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5069          is (lt foo (const_int 0)), so we can perform the above
5070          simplification if STORE_FLAG_VALUE is 1.  */
5071
5072       if (STORE_FLAG_VALUE == 1
5073           && op1 == const1_rtx
5074           && GET_CODE (op0) == LSHIFTRT
5075           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5076           && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5077         return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5078
5079       /* (xor (comparison foo bar) (const_int sign-bit))
5080          when STORE_FLAG_VALUE is the sign bit.  */
5081       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5082           && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5083               == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5084           && op1 == const_true_rtx
5085           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5086           && reversible_comparison_p (op0))
5087         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5088                                 mode, XEXP (op0, 0), XEXP (op0, 1));
5089       break;
5090
5091     default:
5092       abort ();
5093     }
5094
5095   return x;
5096 }
5097 \f
5098 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5099    operations" because they can be replaced with two more basic operations.
5100    ZERO_EXTEND is also considered "compound" because it can be replaced with
5101    an AND operation, which is simpler, though only one operation.
5102
5103    The function expand_compound_operation is called with an rtx expression
5104    and will convert it to the appropriate shifts and AND operations,
5105    simplifying at each stage.
5106
5107    The function make_compound_operation is called to convert an expression
5108    consisting of shifts and ANDs into the equivalent compound expression.
5109    It is the inverse of this function, loosely speaking.  */
5110
5111 static rtx
5112 expand_compound_operation (x)
5113      rtx x;
5114 {
5115   int pos = 0, len;
5116   int unsignedp = 0;
5117   int modewidth;
5118   rtx tem;
5119
5120   switch (GET_CODE (x))
5121     {
5122     case ZERO_EXTEND:
5123       unsignedp = 1;
5124     case SIGN_EXTEND:
5125       /* We can't necessarily use a const_int for a multiword mode;
5126          it depends on implicitly extending the value.
5127          Since we don't know the right way to extend it,
5128          we can't tell whether the implicit way is right.
5129
5130          Even for a mode that is no wider than a const_int,
5131          we can't win, because we need to sign extend one of its bits through
5132          the rest of it, and we don't know which bit.  */
5133       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5134         return x;
5135
5136       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5137          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5138          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5139          reloaded. If not for that, MEM's would very rarely be safe.
5140
5141          Reject MODEs bigger than a word, because we might not be able
5142          to reference a two-register group starting with an arbitrary register
5143          (and currently gen_lowpart might crash for a SUBREG).  */
5144
5145       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5146         return x;
5147
5148       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5149       /* If the inner object has VOIDmode (the only way this can happen
5150          is if it is a ASM_OPERANDS), we can't do anything since we don't
5151          know how much masking to do.  */
5152       if (len == 0)
5153         return x;
5154
5155       break;
5156
5157     case ZERO_EXTRACT:
5158       unsignedp = 1;
5159     case SIGN_EXTRACT:
5160       /* If the operand is a CLOBBER, just return it.  */
5161       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5162         return XEXP (x, 0);
5163
5164       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5165           || GET_CODE (XEXP (x, 2)) != CONST_INT
5166           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5167         return x;
5168
5169       len = INTVAL (XEXP (x, 1));
5170       pos = INTVAL (XEXP (x, 2));
5171
5172       /* If this goes outside the object being extracted, replace the object
5173          with a (use (mem ...)) construct that only combine understands
5174          and is used only for this purpose.  */
5175       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5176         SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5177
5178       if (BITS_BIG_ENDIAN)
5179         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5180
5181       break;
5182
5183     default:
5184       return x;
5185     }
5186
5187   /* We can optimize some special cases of ZERO_EXTEND.  */
5188   if (GET_CODE (x) == ZERO_EXTEND)
5189     {
5190       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5191          know that the last value didn't have any inappropriate bits
5192          set.  */
5193       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5194           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5195           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5196           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5197               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5198         return XEXP (XEXP (x, 0), 0);
5199
5200       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5201       if (GET_CODE (XEXP (x, 0)) == SUBREG
5202           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5203           && subreg_lowpart_p (XEXP (x, 0))
5204           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5205           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5206               & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5207         return SUBREG_REG (XEXP (x, 0));
5208
5209       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5210          is a comparison and STORE_FLAG_VALUE permits.  This is like
5211          the first case, but it works even when GET_MODE (x) is larger
5212          than HOST_WIDE_INT.  */
5213       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5214           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5215           && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5216           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5217               <= HOST_BITS_PER_WIDE_INT)
5218           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5219               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5220         return XEXP (XEXP (x, 0), 0);
5221
5222       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5223       if (GET_CODE (XEXP (x, 0)) == SUBREG
5224           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5225           && subreg_lowpart_p (XEXP (x, 0))
5226           && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5227           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5228               <= HOST_BITS_PER_WIDE_INT)
5229           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5230               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5231         return SUBREG_REG (XEXP (x, 0));
5232
5233       /* If sign extension is cheaper than zero extension, then use it
5234          if we know that no extraneous bits are set, and that the high
5235          bit is not set.  */
5236       if (flag_expensive_optimizations
5237           && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5238                && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5239                     & ~ (((unsigned HOST_WIDE_INT)
5240                           GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5241                          >> 1))
5242                    == 0))
5243               || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5244                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5245                       <= HOST_BITS_PER_WIDE_INT)
5246                   && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5247                        & ~ (((unsigned HOST_WIDE_INT)
5248                              GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5249                             >> 1))
5250                       == 0))))
5251         {
5252           rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
5253
5254           if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5255             return expand_compound_operation (temp);
5256         }
5257     }
5258
5259   /* If we reach here, we want to return a pair of shifts.  The inner
5260      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5261      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5262      logical depending on the value of UNSIGNEDP.
5263
5264      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5265      converted into an AND of a shift.
5266
5267      We must check for the case where the left shift would have a negative
5268      count.  This can happen in a case like (x >> 31) & 255 on machines
5269      that can't shift by a constant.  On those machines, we would first
5270      combine the shift with the AND to produce a variable-position
5271      extraction.  Then the constant of 31 would be substituted in to produce
5272      a such a position.  */
5273
5274   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5275   if (modewidth >= pos - len)
5276     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5277                                 GET_MODE (x),
5278                                 simplify_shift_const (NULL_RTX, ASHIFT,
5279                                                       GET_MODE (x),
5280                                                       XEXP (x, 0),
5281                                                       modewidth - pos - len),
5282                                 modewidth - len);
5283
5284   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5285     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5286                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5287                                                         GET_MODE (x),
5288                                                         XEXP (x, 0), pos),
5289                                   ((HOST_WIDE_INT) 1 << len) - 1);
5290   else
5291     /* Any other cases we can't handle.  */
5292     return x;
5293
5294
5295   /* If we couldn't do this for some reason, return the original
5296      expression.  */
5297   if (GET_CODE (tem) == CLOBBER)
5298     return x;
5299
5300   return tem;
5301 }
5302 \f
5303 /* X is a SET which contains an assignment of one object into
5304    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5305    or certain SUBREGS). If possible, convert it into a series of
5306    logical operations.
5307
5308    We half-heartedly support variable positions, but do not at all
5309    support variable lengths.  */
5310
5311 static rtx
5312 expand_field_assignment (x)
5313      rtx x;
5314 {
5315   rtx inner;
5316   rtx pos;                      /* Always counts from low bit.  */
5317   int len;
5318   rtx mask;
5319   enum machine_mode compute_mode;
5320
5321   /* Loop until we find something we can't simplify.  */
5322   while (1)
5323     {
5324       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5325           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5326         {
5327           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5328           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5329           pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5330         }
5331       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5332                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5333         {
5334           inner = XEXP (SET_DEST (x), 0);
5335           len = INTVAL (XEXP (SET_DEST (x), 1));
5336           pos = XEXP (SET_DEST (x), 2);
5337
5338           /* If the position is constant and spans the width of INNER,
5339              surround INNER  with a USE to indicate this.  */
5340           if (GET_CODE (pos) == CONST_INT
5341               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5342             inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5343
5344           if (BITS_BIG_ENDIAN)
5345             {
5346               if (GET_CODE (pos) == CONST_INT)
5347                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5348                                - INTVAL (pos));
5349               else if (GET_CODE (pos) == MINUS
5350                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5351                        && (INTVAL (XEXP (pos, 1))
5352                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5353                 /* If position is ADJUST - X, new position is X.  */
5354                 pos = XEXP (pos, 0);
5355               else
5356                 pos = gen_binary (MINUS, GET_MODE (pos),
5357                                   GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5358                                            - len),
5359                                   pos);
5360             }
5361         }
5362
5363       /* A SUBREG between two modes that occupy the same numbers of words
5364          can be done by moving the SUBREG to the source.  */
5365       else if (GET_CODE (SET_DEST (x)) == SUBREG
5366                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5367                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5368                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5369                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5370         {
5371           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5372                            gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5373                                                     SET_SRC (x)));
5374           continue;
5375         }
5376       else
5377         break;
5378
5379       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5380         inner = SUBREG_REG (inner);
5381
5382       compute_mode = GET_MODE (inner);
5383
5384       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5385       if (len < HOST_BITS_PER_WIDE_INT)
5386         mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5387       else
5388         break;
5389
5390       /* Now compute the equivalent expression.  Make a copy of INNER
5391          for the SET_DEST in case it is a MEM into which we will substitute;
5392          we don't want shared RTL in that case.  */
5393       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5394                        gen_binary (IOR, compute_mode,
5395                                    gen_binary (AND, compute_mode,
5396                                                gen_unary (NOT, compute_mode,
5397                                                           compute_mode,
5398                                                           gen_binary (ASHIFT,
5399                                                                       compute_mode,
5400                                                                       mask, pos)),
5401                                                inner),
5402                                    gen_binary (ASHIFT, compute_mode,
5403                                                gen_binary (AND, compute_mode,
5404                                                            gen_lowpart_for_combine
5405                                                            (compute_mode,
5406                                                             SET_SRC (x)),
5407                                                            mask),
5408                                                pos)));
5409     }
5410
5411   return x;
5412 }
5413 \f
5414 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5415    it is an RTX that represents a variable starting position; otherwise,
5416    POS is the (constant) starting bit position (counted from the LSB).
5417
5418    INNER may be a USE.  This will occur when we started with a bitfield
5419    that went outside the boundary of the object in memory, which is
5420    allowed on most machines.  To isolate this case, we produce a USE
5421    whose mode is wide enough and surround the MEM with it.  The only
5422    code that understands the USE is this routine.  If it is not removed,
5423    it will cause the resulting insn not to match.
5424
5425    UNSIGNEDP is non-zero for an unsigned reference and zero for a
5426    signed reference.
5427
5428    IN_DEST is non-zero if this is a reference in the destination of a
5429    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If non-zero,
5430    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5431    be used.
5432
5433    IN_COMPARE is non-zero if we are in a COMPARE.  This means that a
5434    ZERO_EXTRACT should be built even for bits starting at bit 0.
5435
5436    MODE is the desired mode of the result (if IN_DEST == 0).
5437
5438    The result is an RTX for the extraction or NULL_RTX if the target
5439    can't handle it.  */
5440
5441 static rtx
5442 make_extraction (mode, inner, pos, pos_rtx, len,
5443                  unsignedp, in_dest, in_compare)
5444      enum machine_mode mode;
5445      rtx inner;
5446      int pos;
5447      rtx pos_rtx;
5448      int len;
5449      int unsignedp;
5450      int in_dest, in_compare;
5451 {
5452   /* This mode describes the size of the storage area
5453      to fetch the overall value from.  Within that, we
5454      ignore the POS lowest bits, etc.  */
5455   enum machine_mode is_mode = GET_MODE (inner);
5456   enum machine_mode inner_mode;
5457   enum machine_mode wanted_inner_mode = byte_mode;
5458   enum machine_mode wanted_inner_reg_mode = word_mode;
5459   enum machine_mode pos_mode = word_mode;
5460   enum machine_mode extraction_mode = word_mode;
5461   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5462   int spans_byte = 0;
5463   rtx new = 0;
5464   rtx orig_pos_rtx = pos_rtx;
5465   int orig_pos;
5466
5467   /* Get some information about INNER and get the innermost object.  */
5468   if (GET_CODE (inner) == USE)
5469     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5470     /* We don't need to adjust the position because we set up the USE
5471        to pretend that it was a full-word object.  */
5472     spans_byte = 1, inner = XEXP (inner, 0);
5473   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5474     {
5475       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5476          consider just the QI as the memory to extract from.
5477          The subreg adds or removes high bits; its mode is
5478          irrelevant to the meaning of this extraction,
5479          since POS and LEN count from the lsb.  */
5480       if (GET_CODE (SUBREG_REG (inner)) == MEM)
5481         is_mode = GET_MODE (SUBREG_REG (inner));
5482       inner = SUBREG_REG (inner);
5483     }
5484
5485   inner_mode = GET_MODE (inner);
5486
5487   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5488     pos = INTVAL (pos_rtx), pos_rtx = 0;
5489
5490   /* See if this can be done without an extraction.  We never can if the
5491      width of the field is not the same as that of some integer mode. For
5492      registers, we can only avoid the extraction if the position is at the
5493      low-order bit and this is either not in the destination or we have the
5494      appropriate STRICT_LOW_PART operation available.
5495
5496      For MEM, we can avoid an extract if the field starts on an appropriate
5497      boundary and we can change the mode of the memory reference.  However,
5498      we cannot directly access the MEM if we have a USE and the underlying
5499      MEM is not TMODE.  This combination means that MEM was being used in a
5500      context where bits outside its mode were being referenced; that is only
5501      valid in bit-field insns.  */
5502
5503   if (tmode != BLKmode
5504       && ! (spans_byte && inner_mode != tmode)
5505       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5506            && GET_CODE (inner) != MEM
5507            && (! in_dest
5508                || (GET_CODE (inner) == REG
5509                    && (movstrict_optab->handlers[(int) tmode].insn_code
5510                        != CODE_FOR_nothing))))
5511           || (GET_CODE (inner) == MEM && pos_rtx == 0
5512               && (pos
5513                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5514                      : BITS_PER_UNIT)) == 0
5515               /* We can't do this if we are widening INNER_MODE (it
5516                  may not be aligned, for one thing).  */
5517               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5518               && (inner_mode == tmode
5519                   || (! mode_dependent_address_p (XEXP (inner, 0))
5520                       && ! MEM_VOLATILE_P (inner))))))
5521     {
5522       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5523          field.  If the original and current mode are the same, we need not
5524          adjust the offset.  Otherwise, we do if bytes big endian.
5525
5526          If INNER is not a MEM, get a piece consisting of just the field
5527          of interest (in this case POS % BITS_PER_WORD must be 0).  */
5528
5529       if (GET_CODE (inner) == MEM)
5530         {
5531           int offset;
5532           /* POS counts from lsb, but make OFFSET count in memory order.  */
5533           if (BYTES_BIG_ENDIAN)
5534             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5535           else
5536             offset = pos / BITS_PER_UNIT;
5537
5538           new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5539           RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5540           MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5541           MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5542         }
5543       else if (GET_CODE (inner) == REG)
5544         {
5545           /* We can't call gen_lowpart_for_combine here since we always want
5546              a SUBREG and it would sometimes return a new hard register.  */
5547           if (tmode != inner_mode)
5548             new = gen_rtx_SUBREG (tmode, inner,
5549                                   (WORDS_BIG_ENDIAN
5550                                    && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5551                                    ? (((GET_MODE_SIZE (inner_mode)
5552                                         - GET_MODE_SIZE (tmode))
5553                                        / UNITS_PER_WORD)
5554                                       - pos / BITS_PER_WORD)
5555                                    : pos / BITS_PER_WORD));
5556           else
5557             new = inner;
5558         }
5559       else
5560         new = force_to_mode (inner, tmode,
5561                              len >= HOST_BITS_PER_WIDE_INT
5562                              ? GET_MODE_MASK (tmode)
5563                              : ((HOST_WIDE_INT) 1 << len) - 1,
5564                              NULL_RTX, 0);
5565
5566       /* If this extraction is going into the destination of a SET,
5567          make a STRICT_LOW_PART unless we made a MEM.  */
5568
5569       if (in_dest)
5570         return (GET_CODE (new) == MEM ? new
5571                 : (GET_CODE (new) != SUBREG
5572                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
5573                    : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5574
5575       /* Otherwise, sign- or zero-extend unless we already are in the
5576          proper mode.  */
5577
5578       return (mode == tmode ? new
5579               : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5580                                  mode, new));
5581     }
5582
5583   /* Unless this is a COMPARE or we have a funny memory reference,
5584      don't do anything with zero-extending field extracts starting at
5585      the low-order bit since they are simple AND operations.  */
5586   if (pos_rtx == 0 && pos == 0 && ! in_dest
5587       && ! in_compare && ! spans_byte && unsignedp)
5588     return 0;
5589
5590   /* Unless we are allowed to span bytes, reject this if we would be
5591      spanning bytes or if the position is not a constant and the length
5592      is not 1.  In all other cases, we would only be going outside
5593      out object in cases when an original shift would have been
5594      undefined.  */
5595   if (! spans_byte
5596       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5597           || (pos_rtx != 0 && len != 1)))
5598     return 0;
5599
5600   /* Get the mode to use should INNER not be a MEM, the mode for the position,
5601      and the mode for the result.  */
5602 #ifdef HAVE_insv
5603   if (in_dest)
5604     {
5605       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5606       pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5607       extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5608     }
5609 #endif
5610
5611 #ifdef HAVE_extzv
5612   if (! in_dest && unsignedp)
5613     {
5614       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5615       pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5616       extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5617     }
5618 #endif
5619
5620 #ifdef HAVE_extv
5621   if (! in_dest && ! unsignedp)
5622     {
5623       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5624       pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5625       extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5626     }
5627 #endif
5628
5629   /* Never narrow an object, since that might not be safe.  */
5630
5631   if (mode != VOIDmode
5632       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5633     extraction_mode = mode;
5634
5635   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5636       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5637     pos_mode = GET_MODE (pos_rtx);
5638
5639   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5640      if we have to change the mode of memory and cannot, the desired mode is
5641      EXTRACTION_MODE.  */
5642   if (GET_CODE (inner) != MEM)
5643     wanted_inner_mode = wanted_inner_reg_mode;
5644   else if (inner_mode != wanted_inner_mode
5645            && (mode_dependent_address_p (XEXP (inner, 0))
5646                || MEM_VOLATILE_P (inner)))
5647     wanted_inner_mode = extraction_mode;
5648
5649   orig_pos = pos;
5650
5651   if (BITS_BIG_ENDIAN)
5652     {
5653       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5654          BITS_BIG_ENDIAN style.  If position is constant, compute new
5655          position.  Otherwise, build subtraction.
5656          Note that POS is relative to the mode of the original argument.
5657          If it's a MEM we need to recompute POS relative to that.
5658          However, if we're extracting from (or inserting into) a register,
5659          we want to recompute POS relative to wanted_inner_mode.  */
5660       int width = (GET_CODE (inner) == MEM
5661                    ? GET_MODE_BITSIZE (is_mode)
5662                    : GET_MODE_BITSIZE (wanted_inner_mode));
5663
5664       if (pos_rtx == 0)
5665         pos = width - len - pos;
5666       else
5667         pos_rtx
5668           = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5669                              GEN_INT (width - len), pos_rtx);
5670       /* POS may be less than 0 now, but we check for that below.
5671          Note that it can only be less than 0 if GET_CODE (inner) != MEM.  */
5672     }
5673
5674   /* If INNER has a wider mode, make it smaller.  If this is a constant
5675      extract, try to adjust the byte to point to the byte containing
5676      the value.  */
5677   if (wanted_inner_mode != VOIDmode
5678       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5679       && ((GET_CODE (inner) == MEM
5680            && (inner_mode == wanted_inner_mode
5681                || (! mode_dependent_address_p (XEXP (inner, 0))
5682                    && ! MEM_VOLATILE_P (inner))))))
5683     {
5684       int offset = 0;
5685
5686       /* The computations below will be correct if the machine is big
5687          endian in both bits and bytes or little endian in bits and bytes.
5688          If it is mixed, we must adjust.  */
5689
5690       /* If bytes are big endian and we had a paradoxical SUBREG, we must
5691          adjust OFFSET to compensate.  */
5692       if (BYTES_BIG_ENDIAN
5693           && ! spans_byte
5694           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5695         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5696
5697       /* If this is a constant position, we can move to the desired byte.  */
5698       if (pos_rtx == 0)
5699         {
5700           offset += pos / BITS_PER_UNIT;
5701           pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5702         }
5703
5704       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5705           && ! spans_byte
5706           && is_mode != wanted_inner_mode)
5707         offset = (GET_MODE_SIZE (is_mode)
5708                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
5709
5710       if (offset != 0 || inner_mode != wanted_inner_mode)
5711         {
5712           rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5713                                     plus_constant (XEXP (inner, 0), offset));
5714           RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5715           MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5716           MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5717           inner = newmem;
5718         }
5719     }
5720
5721   /* If INNER is not memory, we can always get it into the proper mode.  If we
5722      are changing its mode, POS must be a constant and smaller than the size
5723      of the new mode.  */
5724   else if (GET_CODE (inner) != MEM)
5725     {
5726       if (GET_MODE (inner) != wanted_inner_mode
5727           && (pos_rtx != 0
5728               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5729         return 0;
5730
5731       inner = force_to_mode (inner, wanted_inner_mode,
5732                              pos_rtx
5733                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5734                              ? GET_MODE_MASK (wanted_inner_mode)
5735                              : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5736                              NULL_RTX, 0);
5737     }
5738
5739   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
5740      have to zero extend.  Otherwise, we can just use a SUBREG.  */
5741   if (pos_rtx != 0
5742       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5743     pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5744   else if (pos_rtx != 0
5745            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5746     pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5747
5748   /* Make POS_RTX unless we already have it and it is correct.  If we don't
5749      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5750      be a CONST_INT.  */
5751   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5752     pos_rtx = orig_pos_rtx;
5753
5754   else if (pos_rtx == 0)
5755     pos_rtx = GEN_INT (pos);
5756
5757   /* Make the required operation.  See if we can use existing rtx.  */
5758   new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5759                          extraction_mode, inner, GEN_INT (len), pos_rtx);
5760   if (! in_dest)
5761     new = gen_lowpart_for_combine (mode, new);
5762
5763   return new;
5764 }
5765 \f
5766 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5767    with any other operations in X.  Return X without that shift if so.  */
5768
5769 static rtx
5770 extract_left_shift (x, count)
5771      rtx x;
5772      int count;
5773 {
5774   enum rtx_code code = GET_CODE (x);
5775   enum machine_mode mode = GET_MODE (x);
5776   rtx tem;
5777
5778   switch (code)
5779     {
5780     case ASHIFT:
5781       /* This is the shift itself.  If it is wide enough, we will return
5782          either the value being shifted if the shift count is equal to
5783          COUNT or a shift for the difference.  */
5784       if (GET_CODE (XEXP (x, 1)) == CONST_INT
5785           && INTVAL (XEXP (x, 1)) >= count)
5786         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5787                                      INTVAL (XEXP (x, 1)) - count);
5788       break;
5789
5790     case NEG:  case NOT:
5791       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5792         return gen_unary (code, mode, mode, tem);
5793
5794       break;
5795
5796     case PLUS:  case IOR:  case XOR:  case AND:
5797       /* If we can safely shift this constant and we find the inner shift,
5798          make a new operation.  */
5799       if (GET_CODE (XEXP (x,1)) == CONST_INT
5800           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
5801           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5802         return gen_binary (code, mode, tem,
5803                            GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5804
5805       break;
5806
5807     default:
5808       break;
5809     }
5810
5811   return 0;
5812 }
5813 \f
5814 /* Look at the expression rooted at X.  Look for expressions
5815    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5816    Form these expressions.
5817
5818    Return the new rtx, usually just X.
5819
5820    Also, for machines like the Vax that don't have logical shift insns,
5821    try to convert logical to arithmetic shift operations in cases where
5822    they are equivalent.  This undoes the canonicalizations to logical
5823    shifts done elsewhere.
5824
5825    We try, as much as possible, to re-use rtl expressions to save memory.
5826
5827    IN_CODE says what kind of expression we are processing.  Normally, it is
5828    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
5829    being kludges), it is MEM.  When processing the arguments of a comparison
5830    or a COMPARE against zero, it is COMPARE.  */
5831
5832 static rtx
5833 make_compound_operation (x, in_code)
5834      rtx x;
5835      enum rtx_code in_code;
5836 {
5837   enum rtx_code code = GET_CODE (x);
5838   enum machine_mode mode = GET_MODE (x);
5839   int mode_width = GET_MODE_BITSIZE (mode);
5840   rtx rhs, lhs;
5841   enum rtx_code next_code;
5842   int i;
5843   rtx new = 0;
5844   rtx tem;
5845   char *fmt;
5846
5847   /* Select the code to be used in recursive calls.  Once we are inside an
5848      address, we stay there.  If we have a comparison, set to COMPARE,
5849      but once inside, go back to our default of SET.  */
5850
5851   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5852                : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5853                   && XEXP (x, 1) == const0_rtx) ? COMPARE
5854                : in_code == COMPARE ? SET : in_code);
5855
5856   /* Process depending on the code of this operation.  If NEW is set
5857      non-zero, it will be returned.  */
5858
5859   switch (code)
5860     {
5861     case ASHIFT:
5862       /* Convert shifts by constants into multiplications if inside
5863          an address.  */
5864       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5865           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5866           && INTVAL (XEXP (x, 1)) >= 0)
5867         {
5868           new = make_compound_operation (XEXP (x, 0), next_code);
5869           new = gen_rtx_combine (MULT, mode, new,
5870                                  GEN_INT ((HOST_WIDE_INT) 1
5871                                           << INTVAL (XEXP (x, 1))));
5872         }
5873       break;
5874
5875     case AND:
5876       /* If the second operand is not a constant, we can't do anything
5877          with it.  */
5878       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5879         break;
5880
5881       /* If the constant is a power of two minus one and the first operand
5882          is a logical right shift, make an extraction.  */
5883       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5884           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5885         {
5886           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5887           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5888                                  0, in_code == COMPARE);
5889         }
5890
5891       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
5892       else if (GET_CODE (XEXP (x, 0)) == SUBREG
5893                && subreg_lowpart_p (XEXP (x, 0))
5894                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5895                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5896         {
5897           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5898                                          next_code);
5899           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5900                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5901                                  0, in_code == COMPARE);
5902         }
5903       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
5904       else if ((GET_CODE (XEXP (x, 0)) == XOR
5905                 || GET_CODE (XEXP (x, 0)) == IOR)
5906                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5907                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5908                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5909         {
5910           /* Apply the distributive law, and then try to make extractions.  */
5911           new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5912                                  gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5913                                               XEXP (x, 1)),
5914                                  gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5915                                               XEXP (x, 1)));
5916           new = make_compound_operation (new, in_code);
5917         }
5918
5919       /* If we are have (and (rotate X C) M) and C is larger than the number
5920          of bits in M, this is an extraction.  */
5921
5922       else if (GET_CODE (XEXP (x, 0)) == ROTATE
5923                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5924                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5925                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5926         {
5927           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5928           new = make_extraction (mode, new,
5929                                  (GET_MODE_BITSIZE (mode)
5930                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
5931                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
5932         }
5933
5934       /* On machines without logical shifts, if the operand of the AND is
5935          a logical shift and our mask turns off all the propagated sign
5936          bits, we can replace the logical shift with an arithmetic shift.  */
5937       else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5938                && (lshr_optab->handlers[(int) mode].insn_code
5939                    == CODE_FOR_nothing)
5940                && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5941                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5942                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5943                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5944                && mode_width <= HOST_BITS_PER_WIDE_INT)
5945         {
5946           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5947
5948           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5949           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5950             SUBST (XEXP (x, 0),
5951                    gen_rtx_combine (ASHIFTRT, mode,
5952                                     make_compound_operation (XEXP (XEXP (x, 0), 0),
5953                                                              next_code),
5954                                     XEXP (XEXP (x, 0), 1)));
5955         }
5956
5957       /* If the constant is one less than a power of two, this might be
5958          representable by an extraction even if no shift is present.
5959          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5960          we are in a COMPARE.  */
5961       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5962         new = make_extraction (mode,
5963                                make_compound_operation (XEXP (x, 0),
5964                                                         next_code),
5965                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5966
5967       /* If we are in a comparison and this is an AND with a power of two,
5968          convert this into the appropriate bit extract.  */
5969       else if (in_code == COMPARE
5970                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5971         new = make_extraction (mode,
5972                                make_compound_operation (XEXP (x, 0),
5973                                                         next_code),
5974                                i, NULL_RTX, 1, 1, 0, 1);
5975
5976       break;
5977
5978     case LSHIFTRT:
5979       /* If the sign bit is known to be zero, replace this with an
5980          arithmetic shift.  */
5981       if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5982           && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5983           && mode_width <= HOST_BITS_PER_WIDE_INT
5984           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5985         {
5986           new = gen_rtx_combine (ASHIFTRT, mode,
5987                                  make_compound_operation (XEXP (x, 0),
5988                                                           next_code),
5989                                  XEXP (x, 1));
5990           break;
5991         }
5992
5993       /* ... fall through ...  */
5994
5995     case ASHIFTRT:
5996       lhs = XEXP (x, 0);
5997       rhs = XEXP (x, 1);
5998
5999       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6000          this is a SIGN_EXTRACT.  */
6001       if (GET_CODE (rhs) == CONST_INT
6002           && GET_CODE (lhs) == ASHIFT
6003           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6004           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6005         {
6006           new = make_compound_operation (XEXP (lhs, 0), next_code);
6007           new = make_extraction (mode, new,
6008                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6009                                  NULL_RTX, mode_width - INTVAL (rhs),
6010                                  code == LSHIFTRT, 0, in_code == COMPARE);
6011         }
6012
6013       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6014          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6015          also do this for some cases of SIGN_EXTRACT, but it doesn't
6016          seem worth the effort; the case checked for occurs on Alpha.  */
6017
6018       if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6019           && ! (GET_CODE (lhs) == SUBREG
6020                 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6021           && GET_CODE (rhs) == CONST_INT
6022           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6023           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6024         new = make_extraction (mode, make_compound_operation (new, next_code),
6025                                0, NULL_RTX, mode_width - INTVAL (rhs),
6026                                code == LSHIFTRT, 0, in_code == COMPARE);
6027
6028       break;
6029
6030     case SUBREG:
6031       /* Call ourselves recursively on the inner expression.  If we are
6032          narrowing the object and it has a different RTL code from
6033          what it originally did, do this SUBREG as a force_to_mode.  */
6034
6035       tem = make_compound_operation (SUBREG_REG (x), in_code);
6036       if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6037           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6038           && subreg_lowpart_p (x))
6039         {
6040           rtx newer = force_to_mode (tem, mode,
6041                                      GET_MODE_MASK (mode), NULL_RTX, 0);
6042
6043           /* If we have something other than a SUBREG, we might have
6044              done an expansion, so rerun outselves.  */
6045           if (GET_CODE (newer) != SUBREG)
6046             newer = make_compound_operation (newer, in_code);
6047
6048           return newer;
6049         }
6050
6051       /* If this is a paradoxical subreg, and the new code is a sign or
6052          zero extension, omit the subreg and widen the extension.  If it
6053          is a regular subreg, we can still get rid of the subreg by not
6054          widening so much, or in fact removing the extension entirely.  */
6055       if ((GET_CODE (tem) == SIGN_EXTEND
6056            || GET_CODE (tem) == ZERO_EXTEND)
6057           && subreg_lowpart_p (x))
6058         {
6059           if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6060               || (GET_MODE_SIZE (mode) >
6061                   GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6062             tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6063           else
6064             tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6065           return tem;
6066         }
6067       break;
6068
6069     default:
6070       break;
6071     }
6072
6073   if (new)
6074     {
6075       x = gen_lowpart_for_combine (mode, new);
6076       code = GET_CODE (x);
6077     }
6078
6079   /* Now recursively process each operand of this operation.  */
6080   fmt = GET_RTX_FORMAT (code);
6081   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6082     if (fmt[i] == 'e')
6083       {
6084         new = make_compound_operation (XEXP (x, i), next_code);
6085         SUBST (XEXP (x, i), new);
6086       }
6087
6088   return x;
6089 }
6090 \f
6091 /* Given M see if it is a value that would select a field of bits
6092     within an item, but not the entire word.  Return -1 if not.
6093     Otherwise, return the starting position of the field, where 0 is the
6094     low-order bit.
6095
6096    *PLEN is set to the length of the field.  */
6097
6098 static int
6099 get_pos_from_mask (m, plen)
6100      unsigned HOST_WIDE_INT m;
6101      int *plen;
6102 {
6103   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6104   int pos = exact_log2 (m & - m);
6105
6106   if (pos < 0)
6107     return -1;
6108
6109   /* Now shift off the low-order zero bits and see if we have a power of
6110      two minus 1.  */
6111   *plen = exact_log2 ((m >> pos) + 1);
6112
6113   if (*plen <= 0)
6114     return -1;
6115
6116   return pos;
6117 }
6118 \f
6119 /* See if X can be simplified knowing that we will only refer to it in
6120    MODE and will only refer to those bits that are nonzero in MASK.
6121    If other bits are being computed or if masking operations are done
6122    that select a superset of the bits in MASK, they can sometimes be
6123    ignored.
6124
6125    Return a possibly simplified expression, but always convert X to
6126    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6127
6128    Also, if REG is non-zero and X is a register equal in value to REG,
6129    replace X with REG.
6130
6131    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6132    are all off in X.  This is used when X will be complemented, by either
6133    NOT, NEG, or XOR.  */
6134
6135 static rtx
6136 force_to_mode (x, mode, mask, reg, just_select)
6137      rtx x;
6138      enum machine_mode mode;
6139      unsigned HOST_WIDE_INT mask;
6140      rtx reg;
6141      int just_select;
6142 {
6143   enum rtx_code code = GET_CODE (x);
6144   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6145   enum machine_mode op_mode;
6146   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6147   rtx op0, op1, temp;
6148
6149   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6150      code below will do the wrong thing since the mode of such an
6151      expression is VOIDmode.
6152
6153      Also do nothing if X is a CLOBBER; this can happen if X was
6154      the return value from a call to gen_lowpart_for_combine.  */
6155   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6156     return x;
6157
6158   /* We want to perform the operation is its present mode unless we know
6159      that the operation is valid in MODE, in which case we do the operation
6160      in MODE.  */
6161   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6162               && code_to_optab[(int) code] != 0
6163               && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6164                   != CODE_FOR_nothing))
6165              ? mode : GET_MODE (x));
6166
6167   /* It is not valid to do a right-shift in a narrower mode
6168      than the one it came in with.  */
6169   if ((code == LSHIFTRT || code == ASHIFTRT)
6170       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6171     op_mode = GET_MODE (x);
6172
6173   /* Truncate MASK to fit OP_MODE.  */
6174   if (op_mode)
6175     mask &= GET_MODE_MASK (op_mode);
6176
6177   /* When we have an arithmetic operation, or a shift whose count we
6178      do not know, we need to assume that all bit the up to the highest-order
6179      bit in MASK will be needed.  This is how we form such a mask.  */
6180   if (op_mode)
6181     fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6182                    ? GET_MODE_MASK (op_mode)
6183                    : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6184   else
6185     fuller_mask = ~ (HOST_WIDE_INT) 0;
6186
6187   /* Determine what bits of X are guaranteed to be (non)zero.  */
6188   nonzero = nonzero_bits (x, mode);
6189
6190   /* If none of the bits in X are needed, return a zero.  */
6191   if (! just_select && (nonzero & mask) == 0)
6192     return const0_rtx;
6193
6194   /* If X is a CONST_INT, return a new one.  Do this here since the
6195      test below will fail.  */
6196   if (GET_CODE (x) == CONST_INT)
6197     {
6198       HOST_WIDE_INT cval = INTVAL (x) & mask;
6199       int width = GET_MODE_BITSIZE (mode);
6200
6201       /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6202          number, sign extend it.  */
6203       if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6204           && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6205         cval |= (HOST_WIDE_INT) -1 << width;
6206
6207       return GEN_INT (cval);
6208     }
6209
6210   /* If X is narrower than MODE and we want all the bits in X's mode, just
6211      get X in the proper mode.  */
6212   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6213       && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6214     return gen_lowpart_for_combine (mode, x);
6215
6216   /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6217      MASK are already known to be zero in X, we need not do anything.  */
6218   if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6219     return x;
6220
6221   switch (code)
6222     {
6223     case CLOBBER:
6224       /* If X is a (clobber (const_int)), return it since we know we are
6225          generating something that won't match.  */
6226       return x;
6227
6228     case USE:
6229       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6230          spanned the boundary of the MEM.  If we are now masking so it is
6231          within that boundary, we don't need the USE any more.  */
6232       if (! BITS_BIG_ENDIAN
6233           && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6234         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6235       break;
6236
6237     case SIGN_EXTEND:
6238     case ZERO_EXTEND:
6239     case ZERO_EXTRACT:
6240     case SIGN_EXTRACT:
6241       x = expand_compound_operation (x);
6242       if (GET_CODE (x) != code)
6243         return force_to_mode (x, mode, mask, reg, next_select);
6244       break;
6245
6246     case REG:
6247       if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6248                        || rtx_equal_p (reg, get_last_value (x))))
6249         x = reg;
6250       break;
6251
6252     case SUBREG:
6253       if (subreg_lowpart_p (x)
6254           /* We can ignore the effect of this SUBREG if it narrows the mode or
6255              if the constant masks to zero all the bits the mode doesn't
6256              have.  */
6257           && ((GET_MODE_SIZE (GET_MODE (x))
6258                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6259               || (0 == (mask
6260                         & GET_MODE_MASK (GET_MODE (x))
6261                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6262         return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6263       break;
6264
6265     case AND:
6266       /* If this is an AND with a constant, convert it into an AND
6267          whose constant is the AND of that constant with MASK.  If it
6268          remains an AND of MASK, delete it since it is redundant.  */
6269
6270       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6271         {
6272           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6273                                       mask & INTVAL (XEXP (x, 1)));
6274
6275           /* If X is still an AND, see if it is an AND with a mask that
6276              is just some low-order bits.  If so, and it is MASK, we don't
6277              need it.  */
6278
6279           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6280               && INTVAL (XEXP (x, 1)) == mask)
6281             x = XEXP (x, 0);
6282
6283           /* If it remains an AND, try making another AND with the bits
6284              in the mode mask that aren't in MASK turned on.  If the
6285              constant in the AND is wide enough, this might make a
6286              cheaper constant.  */
6287
6288           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6289               && GET_MODE_MASK (GET_MODE (x)) != mask
6290               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6291             {
6292               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6293                                     | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6294               int width = GET_MODE_BITSIZE (GET_MODE (x));
6295               rtx y;
6296
6297               /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6298                  number, sign extend it.  */
6299               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6300                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6301                 cval |= (HOST_WIDE_INT) -1 << width;
6302
6303               y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6304               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6305                 x = y;
6306             }
6307
6308           break;
6309         }
6310
6311       goto binop;
6312
6313     case PLUS:
6314       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6315          low-order bits (as in an alignment operation) and FOO is already
6316          aligned to that boundary, mask C1 to that boundary as well.
6317          This may eliminate that PLUS and, later, the AND.  */
6318
6319       {
6320         int width = GET_MODE_BITSIZE (mode);
6321         unsigned HOST_WIDE_INT smask = mask;
6322
6323         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6324            number, sign extend it.  */
6325
6326         if (width < HOST_BITS_PER_WIDE_INT
6327             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6328           smask |= (HOST_WIDE_INT) -1 << width;
6329
6330         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6331             && exact_log2 (- smask) >= 0)
6332           {
6333 #ifdef STACK_BIAS
6334             if (STACK_BIAS
6335                 && (XEXP (x, 0) == stack_pointer_rtx
6336                     || XEXP (x, 0) == frame_pointer_rtx))
6337               {
6338                 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6339                 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6340
6341                 sp_mask &= ~ (sp_alignment - 1);
6342                 if ((sp_mask & ~ mask) == 0
6343                     && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ mask) != 0)
6344                   return force_to_mode (plus_constant (XEXP (x, 0),
6345                                                        ((INTVAL (XEXP (x, 1)) -
6346                                                          STACK_BIAS) & mask)
6347                                                        + STACK_BIAS),
6348                                         mode, mask, reg, next_select);
6349               }
6350 #endif
6351             if ((nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6352                 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6353               return force_to_mode (plus_constant (XEXP (x, 0),
6354                                                    INTVAL (XEXP (x, 1)) & mask),
6355                                     mode, mask, reg, next_select);
6356           }
6357       }
6358
6359       /* ... fall through ...  */
6360
6361     case MINUS:
6362     case MULT:
6363       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6364          most significant bit in MASK since carries from those bits will
6365          affect the bits we are interested in.  */
6366       mask = fuller_mask;
6367       goto binop;
6368
6369     case IOR:
6370     case XOR:
6371       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6372          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6373          operation which may be a bitfield extraction.  Ensure that the
6374          constant we form is not wider than the mode of X.  */
6375
6376       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6377           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6378           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6379           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6380           && GET_CODE (XEXP (x, 1)) == CONST_INT
6381           && ((INTVAL (XEXP (XEXP (x, 0), 1))
6382                + floor_log2 (INTVAL (XEXP (x, 1))))
6383               < GET_MODE_BITSIZE (GET_MODE (x)))
6384           && (INTVAL (XEXP (x, 1))
6385               & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6386         {
6387           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6388                               << INTVAL (XEXP (XEXP (x, 0), 1)));
6389           temp = gen_binary (GET_CODE (x), GET_MODE (x),
6390                              XEXP (XEXP (x, 0), 0), temp);
6391           x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6392                           XEXP (XEXP (x, 0), 1));
6393           return force_to_mode (x, mode, mask, reg, next_select);
6394         }
6395
6396     binop:
6397       /* For most binary operations, just propagate into the operation and
6398          change the mode if we have an operation of that mode.   */
6399
6400       op0 = gen_lowpart_for_combine (op_mode,
6401                                      force_to_mode (XEXP (x, 0), mode, mask,
6402                                                     reg, next_select));
6403       op1 = gen_lowpart_for_combine (op_mode,
6404                                      force_to_mode (XEXP (x, 1), mode, mask,
6405                                                     reg, next_select));
6406
6407       /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6408          MASK since OP1 might have been sign-extended but we never want
6409          to turn on extra bits, since combine might have previously relied
6410          on them being off.  */
6411       if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6412           && (INTVAL (op1) & mask) != 0)
6413         op1 = GEN_INT (INTVAL (op1) & mask);
6414
6415       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6416         x = gen_binary (code, op_mode, op0, op1);
6417       break;
6418
6419     case ASHIFT:
6420       /* For left shifts, do the same, but just for the first operand.
6421          However, we cannot do anything with shifts where we cannot
6422          guarantee that the counts are smaller than the size of the mode
6423          because such a count will have a different meaning in a
6424          wider mode.  */
6425
6426       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6427              && INTVAL (XEXP (x, 1)) >= 0
6428              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6429           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6430                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6431                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6432         break;
6433
6434       /* If the shift count is a constant and we can do arithmetic in
6435          the mode of the shift, refine which bits we need.  Otherwise, use the
6436          conservative form of the mask.  */
6437       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6438           && INTVAL (XEXP (x, 1)) >= 0
6439           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6440           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6441         mask >>= INTVAL (XEXP (x, 1));
6442       else
6443         mask = fuller_mask;
6444
6445       op0 = gen_lowpart_for_combine (op_mode,
6446                                      force_to_mode (XEXP (x, 0), op_mode,
6447                                                     mask, reg, next_select));
6448
6449       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6450         x =  gen_binary (code, op_mode, op0, XEXP (x, 1));
6451       break;
6452
6453     case LSHIFTRT:
6454       /* Here we can only do something if the shift count is a constant,
6455          this shift constant is valid for the host, and we can do arithmetic
6456          in OP_MODE.  */
6457
6458       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6459           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6460           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6461         {
6462           rtx inner = XEXP (x, 0);
6463
6464           /* Select the mask of the bits we need for the shift operand.  */
6465           mask <<= INTVAL (XEXP (x, 1));
6466
6467           /* We can only change the mode of the shift if we can do arithmetic
6468              in the mode of the shift and MASK is no wider than the width of
6469              OP_MODE.  */
6470           if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6471               || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6472             op_mode = GET_MODE (x);
6473
6474           inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6475
6476           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6477             x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6478         }
6479
6480       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6481          shift and AND produces only copies of the sign bit (C2 is one less
6482          than a power of two), we can do this with just a shift.  */
6483
6484       if (GET_CODE (x) == LSHIFTRT
6485           && GET_CODE (XEXP (x, 1)) == CONST_INT
6486           && ((INTVAL (XEXP (x, 1))
6487                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6488               >= GET_MODE_BITSIZE (GET_MODE (x)))
6489           && exact_log2 (mask + 1) >= 0
6490           && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6491               >= exact_log2 (mask + 1)))
6492         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6493                         GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6494                                  - exact_log2 (mask + 1)));
6495       break;
6496
6497     case ASHIFTRT:
6498       /* If we are just looking for the sign bit, we don't need this shift at
6499          all, even if it has a variable count.  */
6500       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6501           && (mask == ((HOST_WIDE_INT) 1
6502                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6503         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6504
6505       /* If this is a shift by a constant, get a mask that contains those bits
6506          that are not copies of the sign bit.  We then have two cases:  If
6507          MASK only includes those bits, this can be a logical shift, which may
6508          allow simplifications.  If MASK is a single-bit field not within
6509          those bits, we are requesting a copy of the sign bit and hence can
6510          shift the sign bit to the appropriate location.  */
6511
6512       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6513           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6514         {
6515           int i = -1;
6516
6517           /* If the considered data is wider then HOST_WIDE_INT, we can't
6518              represent a mask for all its bits in a single scalar.
6519              But we only care about the lower bits, so calculate these.  */
6520
6521           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6522             {
6523               nonzero = ~ (HOST_WIDE_INT) 0;
6524
6525               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6526                  is the number of bits a full-width mask would have set.
6527                  We need only shift if these are fewer than nonzero can
6528                  hold.  If not, we must keep all bits set in nonzero.  */
6529
6530               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6531                   < HOST_BITS_PER_WIDE_INT)
6532                 nonzero >>= INTVAL (XEXP (x, 1))
6533                             + HOST_BITS_PER_WIDE_INT
6534                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
6535             }
6536           else
6537             {
6538               nonzero = GET_MODE_MASK (GET_MODE (x));
6539               nonzero >>= INTVAL (XEXP (x, 1));
6540             }
6541
6542           if ((mask & ~ nonzero) == 0
6543               || (i = exact_log2 (mask)) >= 0)
6544             {
6545               x = simplify_shift_const
6546                 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6547                  i < 0 ? INTVAL (XEXP (x, 1))
6548                  : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6549
6550               if (GET_CODE (x) != ASHIFTRT)
6551                 return force_to_mode (x, mode, mask, reg, next_select);
6552             }
6553         }
6554
6555       /* If MASK is 1, convert this to a LSHIFTRT.  This can be done
6556          even if the shift count isn't a constant.  */
6557       if (mask == 1)
6558         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6559
6560       /* If this is a sign-extension operation that just affects bits
6561          we don't care about, remove it.  Be sure the call above returned
6562          something that is still a shift.  */
6563
6564       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6565           && GET_CODE (XEXP (x, 1)) == CONST_INT
6566           && INTVAL (XEXP (x, 1)) >= 0
6567           && (INTVAL (XEXP (x, 1))
6568               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6569           && GET_CODE (XEXP (x, 0)) == ASHIFT
6570           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6571           && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6572         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6573                               reg, next_select);
6574
6575       break;
6576
6577     case ROTATE:
6578     case ROTATERT:
6579       /* If the shift count is constant and we can do computations
6580          in the mode of X, compute where the bits we care about are.
6581          Otherwise, we can't do anything.  Don't change the mode of
6582          the shift or propagate MODE into the shift, though.  */
6583       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6584           && INTVAL (XEXP (x, 1)) >= 0)
6585         {
6586           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6587                                             GET_MODE (x), GEN_INT (mask),
6588                                             XEXP (x, 1));
6589           if (temp && GET_CODE(temp) == CONST_INT)
6590             SUBST (XEXP (x, 0),
6591                    force_to_mode (XEXP (x, 0), GET_MODE (x),
6592                                   INTVAL (temp), reg, next_select));
6593         }
6594       break;
6595
6596     case NEG:
6597       /* If we just want the low-order bit, the NEG isn't needed since it
6598          won't change the low-order bit.    */
6599       if (mask == 1)
6600         return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6601
6602       /* We need any bits less significant than the most significant bit in
6603          MASK since carries from those bits will affect the bits we are
6604          interested in.  */
6605       mask = fuller_mask;
6606       goto unop;
6607
6608     case NOT:
6609       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6610          same as the XOR case above.  Ensure that the constant we form is not
6611          wider than the mode of X.  */
6612
6613       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6614           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6615           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6616           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6617               < GET_MODE_BITSIZE (GET_MODE (x)))
6618           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6619         {
6620           temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6621           temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6622           x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6623
6624           return force_to_mode (x, mode, mask, reg, next_select);
6625         }
6626
6627       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6628          use the full mask inside the NOT.  */
6629       mask = fuller_mask;
6630
6631     unop:
6632       op0 = gen_lowpart_for_combine (op_mode,
6633                                      force_to_mode (XEXP (x, 0), mode, mask,
6634                                                     reg, next_select));
6635       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6636         x = gen_unary (code, op_mode, op_mode, op0);
6637       break;
6638
6639     case NE:
6640       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6641          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6642          which is equal to STORE_FLAG_VALUE.  */
6643       if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6644           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6645           && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6646         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6647
6648       break;
6649
6650     case IF_THEN_ELSE:
6651       /* We have no way of knowing if the IF_THEN_ELSE can itself be
6652          written in a narrower mode.  We play it safe and do not do so.  */
6653
6654       SUBST (XEXP (x, 1),
6655              gen_lowpart_for_combine (GET_MODE (x),
6656                                       force_to_mode (XEXP (x, 1), mode,
6657                                                      mask, reg, next_select)));
6658       SUBST (XEXP (x, 2),
6659              gen_lowpart_for_combine (GET_MODE (x),
6660                                       force_to_mode (XEXP (x, 2), mode,
6661                                                      mask, reg,next_select)));
6662       break;
6663
6664     default:
6665       break;
6666     }
6667
6668   /* Ensure we return a value of the proper mode.  */
6669   return gen_lowpart_for_combine (mode, x);
6670 }
6671 \f
6672 /* Return nonzero if X is an expression that has one of two values depending on
6673    whether some other value is zero or nonzero.  In that case, we return the
6674    value that is being tested, *PTRUE is set to the value if the rtx being
6675    returned has a nonzero value, and *PFALSE is set to the other alternative.
6676
6677    If we return zero, we set *PTRUE and *PFALSE to X.  */
6678
6679 static rtx
6680 if_then_else_cond (x, ptrue, pfalse)
6681      rtx x;
6682      rtx *ptrue, *pfalse;
6683 {
6684   enum machine_mode mode = GET_MODE (x);
6685   enum rtx_code code = GET_CODE (x);
6686   int size = GET_MODE_BITSIZE (mode);
6687   rtx cond0, cond1, true0, true1, false0, false1;
6688   unsigned HOST_WIDE_INT nz;
6689
6690   /* If this is a unary operation whose operand has one of two values, apply
6691      our opcode to compute those values.  */
6692   if (GET_RTX_CLASS (code) == '1'
6693       && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6694     {
6695       *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6696       *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6697       return cond0;
6698     }
6699
6700   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6701      make can't possibly match and would suppress other optimizations.  */
6702   else if (code == COMPARE)
6703     ;
6704
6705   /* If this is a binary operation, see if either side has only one of two
6706      values.  If either one does or if both do and they are conditional on
6707      the same value, compute the new true and false values.  */
6708   else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6709            || GET_RTX_CLASS (code) == '<')
6710     {
6711       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6712       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6713
6714       if ((cond0 != 0 || cond1 != 0)
6715           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6716         {
6717           /* If if_then_else_cond returned zero, then true/false are the
6718              same rtl.  We must copy one of them to prevent invalid rtl
6719              sharing.  */
6720           if (cond0 == 0)
6721             true0 = copy_rtx (true0);
6722           else if (cond1 == 0)
6723             true1 = copy_rtx (true1);
6724
6725           *ptrue = gen_binary (code, mode, true0, true1);
6726           *pfalse = gen_binary (code, mode, false0, false1);
6727           return cond0 ? cond0 : cond1;
6728         }
6729
6730       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6731          operands is zero when the other is non-zero, and vice-versa,
6732          and STORE_FLAG_VALUE is 1 or -1.  */
6733
6734       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6735           && (code == PLUS || code == IOR || code == XOR || code == MINUS
6736            || code == UMAX)
6737           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6738         {
6739           rtx op0 = XEXP (XEXP (x, 0), 1);
6740           rtx op1 = XEXP (XEXP (x, 1), 1);
6741
6742           cond0 = XEXP (XEXP (x, 0), 0);
6743           cond1 = XEXP (XEXP (x, 1), 0);
6744
6745           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6746               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6747               && reversible_comparison_p (cond1)
6748               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6749                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6750                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6751                   || ((swap_condition (GET_CODE (cond0))
6752                        == reverse_condition (GET_CODE (cond1)))
6753                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6754                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6755               && ! side_effects_p (x))
6756             {
6757               *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6758               *pfalse = gen_binary (MULT, mode,
6759                                     (code == MINUS
6760                                      ? gen_unary (NEG, mode, mode, op1) : op1),
6761                                     const_true_rtx);
6762               return cond0;
6763             }
6764         }
6765
6766       /* Similarly for MULT, AND and UMIN, execpt that for these the result
6767          is always zero.  */
6768       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6769           && (code == MULT || code == AND || code == UMIN)
6770           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6771         {
6772           cond0 = XEXP (XEXP (x, 0), 0);
6773           cond1 = XEXP (XEXP (x, 1), 0);
6774
6775           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6776               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6777               && reversible_comparison_p (cond1)
6778               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6779                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6780                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6781                   || ((swap_condition (GET_CODE (cond0))
6782                        == reverse_condition (GET_CODE (cond1)))
6783                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6784                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6785               && ! side_effects_p (x))
6786             {
6787               *ptrue = *pfalse = const0_rtx;
6788               return cond0;
6789             }
6790         }
6791     }
6792
6793   else if (code == IF_THEN_ELSE)
6794     {
6795       /* If we have IF_THEN_ELSE already, extract the condition and
6796          canonicalize it if it is NE or EQ.  */
6797       cond0 = XEXP (x, 0);
6798       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6799       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6800         return XEXP (cond0, 0);
6801       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6802         {
6803           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6804           return XEXP (cond0, 0);
6805         }
6806       else
6807         return cond0;
6808     }
6809
6810   /* If X is a normal SUBREG with both inner and outer modes integral,
6811      we can narrow both the true and false values of the inner expression,
6812      if there is a condition.  */
6813   else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6814            && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6815            && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6816            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6817                                                &true0, &false0)))
6818     {
6819       *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6820       *pfalse
6821         = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6822
6823       return cond0;
6824     }
6825
6826   /* If X is a constant, this isn't special and will cause confusions
6827      if we treat it as such.  Likewise if it is equivalent to a constant.  */
6828   else if (CONSTANT_P (x)
6829            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6830     ;
6831
6832   /* If X is known to be either 0 or -1, those are the true and
6833      false values when testing X.  */
6834   else if (num_sign_bit_copies (x, mode) == size)
6835     {
6836       *ptrue = constm1_rtx, *pfalse = const0_rtx;
6837       return x;
6838     }
6839
6840   /* Likewise for 0 or a single bit.  */
6841   else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6842     {
6843       *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6844       return x;
6845     }
6846
6847   /* Otherwise fail; show no condition with true and false values the same.  */
6848   *ptrue = *pfalse = x;
6849   return 0;
6850 }
6851 \f
6852 /* Return the value of expression X given the fact that condition COND
6853    is known to be true when applied to REG as its first operand and VAL
6854    as its second.  X is known to not be shared and so can be modified in
6855    place.
6856
6857    We only handle the simplest cases, and specifically those cases that
6858    arise with IF_THEN_ELSE expressions.  */
6859
6860 static rtx
6861 known_cond (x, cond, reg, val)
6862      rtx x;
6863      enum rtx_code cond;
6864      rtx reg, val;
6865 {
6866   enum rtx_code code = GET_CODE (x);
6867   rtx temp;
6868   char *fmt;
6869   int i, j;
6870
6871   if (side_effects_p (x))
6872     return x;
6873
6874   if (cond == EQ && rtx_equal_p (x, reg))
6875     return val;
6876
6877   /* If X is (abs REG) and we know something about REG's relationship
6878      with zero, we may be able to simplify this.  */
6879
6880   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6881     switch (cond)
6882       {
6883       case GE:  case GT:  case EQ:
6884         return XEXP (x, 0);
6885       case LT:  case LE:
6886         return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6887                           XEXP (x, 0));
6888       default:
6889         break;
6890       }
6891
6892   /* The only other cases we handle are MIN, MAX, and comparisons if the
6893      operands are the same as REG and VAL.  */
6894
6895   else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6896     {
6897       if (rtx_equal_p (XEXP (x, 0), val))
6898         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6899
6900       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6901         {
6902           if (GET_RTX_CLASS (code) == '<')
6903             return (comparison_dominates_p (cond, code) ? const_true_rtx
6904                     : (comparison_dominates_p (cond,
6905                                                reverse_condition (code))
6906                        ? const0_rtx : x));
6907
6908           else if (code == SMAX || code == SMIN
6909                    || code == UMIN || code == UMAX)
6910             {
6911               int unsignedp = (code == UMIN || code == UMAX);
6912
6913               if (code == SMAX || code == UMAX)
6914                 cond = reverse_condition (cond);
6915
6916               switch (cond)
6917                 {
6918                 case GE:   case GT:
6919                   return unsignedp ? x : XEXP (x, 1);
6920                 case LE:   case LT:
6921                   return unsignedp ? x : XEXP (x, 0);
6922                 case GEU:  case GTU:
6923                   return unsignedp ? XEXP (x, 1) : x;
6924                 case LEU:  case LTU:
6925                   return unsignedp ? XEXP (x, 0) : x;
6926                 default:
6927                   break;
6928                 }
6929             }
6930         }
6931     }
6932
6933   fmt = GET_RTX_FORMAT (code);
6934   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6935     {
6936       if (fmt[i] == 'e')
6937         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6938       else if (fmt[i] == 'E')
6939         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6940           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6941                                                 cond, reg, val));
6942     }
6943
6944   return x;
6945 }
6946 \f
6947 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6948    assignment as a field assignment.  */
6949
6950 static int
6951 rtx_equal_for_field_assignment_p (x, y)
6952      rtx x;
6953      rtx y;
6954 {
6955   rtx last_x, last_y;
6956
6957   if (x == y || rtx_equal_p (x, y))
6958     return 1;
6959
6960   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6961     return 0;
6962
6963   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6964      Note that all SUBREGs of MEM are paradoxical; otherwise they
6965      would have been rewritten.  */
6966   if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6967       && GET_CODE (SUBREG_REG (y)) == MEM
6968       && rtx_equal_p (SUBREG_REG (y),
6969                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6970     return 1;
6971
6972   if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6973       && GET_CODE (SUBREG_REG (x)) == MEM
6974       && rtx_equal_p (SUBREG_REG (x),
6975                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6976     return 1;
6977
6978   last_x = get_last_value (x);
6979   last_y = get_last_value (y);
6980
6981   return ((last_x != 0
6982            && GET_CODE (last_x) != CLOBBER
6983            && rtx_equal_for_field_assignment_p (last_x, y))
6984           || (last_y != 0
6985               && GET_CODE (last_y) != CLOBBER
6986               && rtx_equal_for_field_assignment_p (x, last_y))
6987           || (last_x != 0 && last_y != 0
6988               && GET_CODE (last_x) != CLOBBER
6989               && GET_CODE (last_y) != CLOBBER
6990               && rtx_equal_for_field_assignment_p (last_x, last_y)));
6991 }
6992 \f
6993 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6994    Return that assignment if so.
6995
6996    We only handle the most common cases.  */
6997
6998 static rtx
6999 make_field_assignment (x)
7000      rtx x;
7001 {
7002   rtx dest = SET_DEST (x);
7003   rtx src = SET_SRC (x);
7004   rtx assign;
7005   rtx rhs, lhs;
7006   HOST_WIDE_INT c1;
7007   int pos, len;
7008   rtx other;
7009   enum machine_mode mode;
7010
7011   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7012      a clear of a one-bit field.  We will have changed it to
7013      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7014      for a SUBREG.  */
7015
7016   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7017       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7018       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7019       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7020     {
7021       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7022                                 1, 1, 1, 0);
7023       if (assign != 0)
7024         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7025       return x;
7026     }
7027
7028   else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7029            && subreg_lowpart_p (XEXP (src, 0))
7030            && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7031                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7032            && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7033            && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7034            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7035     {
7036       assign = make_extraction (VOIDmode, dest, 0,
7037                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7038                                 1, 1, 1, 0);
7039       if (assign != 0)
7040         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7041       return x;
7042     }
7043
7044   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7045      one-bit field.  */
7046   else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7047            && XEXP (XEXP (src, 0), 0) == const1_rtx
7048            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7049     {
7050       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7051                                 1, 1, 1, 0);
7052       if (assign != 0)
7053         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7054       return x;
7055     }
7056
7057   /* The other case we handle is assignments into a constant-position
7058      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7059      a mask that has all one bits except for a group of zero bits and
7060      OTHER is known to have zeros where C1 has ones, this is such an
7061      assignment.  Compute the position and length from C1.  Shift OTHER
7062      to the appropriate position, force it to the required mode, and
7063      make the extraction.  Check for the AND in both operands.  */
7064
7065   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7066     return x;
7067
7068   rhs = expand_compound_operation (XEXP (src, 0));
7069   lhs = expand_compound_operation (XEXP (src, 1));
7070
7071   if (GET_CODE (rhs) == AND
7072       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7073       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7074     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7075   else if (GET_CODE (lhs) == AND
7076            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7077            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7078     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7079   else
7080     return x;
7081
7082   pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7083   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7084       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7085       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7086     return x;
7087
7088   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7089   if (assign == 0)
7090     return x;
7091
7092   /* The mode to use for the source is the mode of the assignment, or of
7093      what is inside a possible STRICT_LOW_PART.  */
7094   mode = (GET_CODE (assign) == STRICT_LOW_PART
7095           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7096
7097   /* Shift OTHER right POS places and make it the source, restricting it
7098      to the proper length and mode.  */
7099
7100   src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7101                                              GET_MODE (src), other, pos),
7102                        mode,
7103                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7104                        ? GET_MODE_MASK (mode)
7105                        : ((HOST_WIDE_INT) 1 << len) - 1,
7106                        dest, 0);
7107
7108   return gen_rtx_combine (SET, VOIDmode, assign, src);
7109 }
7110 \f
7111 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7112    if so.  */
7113
7114 static rtx
7115 apply_distributive_law (x)
7116      rtx x;
7117 {
7118   enum rtx_code code = GET_CODE (x);
7119   rtx lhs, rhs, other;
7120   rtx tem;
7121   enum rtx_code inner_code;
7122
7123   /* Distributivity is not true for floating point.
7124      It can change the value.  So don't do it.
7125      -- rms and moshier@world.std.com.  */
7126   if (FLOAT_MODE_P (GET_MODE (x)))
7127     return x;
7128
7129   /* The outer operation can only be one of the following:  */
7130   if (code != IOR && code != AND && code != XOR
7131       && code != PLUS && code != MINUS)
7132     return x;
7133
7134   lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7135
7136   /* If either operand is a primitive we can't do anything, so get out
7137      fast.  */
7138   if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7139       || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7140     return x;
7141
7142   lhs = expand_compound_operation (lhs);
7143   rhs = expand_compound_operation (rhs);
7144   inner_code = GET_CODE (lhs);
7145   if (inner_code != GET_CODE (rhs))
7146     return x;
7147
7148   /* See if the inner and outer operations distribute.  */
7149   switch (inner_code)
7150     {
7151     case LSHIFTRT:
7152     case ASHIFTRT:
7153     case AND:
7154     case IOR:
7155       /* These all distribute except over PLUS.  */
7156       if (code == PLUS || code == MINUS)
7157         return x;
7158       break;
7159
7160     case MULT:
7161       if (code != PLUS && code != MINUS)
7162         return x;
7163       break;
7164
7165     case ASHIFT:
7166       /* This is also a multiply, so it distributes over everything.  */
7167       break;
7168
7169     case SUBREG:
7170       /* Non-paradoxical SUBREGs distributes over all operations, provided
7171          the inner modes and word numbers are the same, this is an extraction
7172          of a low-order part, we don't convert an fp operation to int or
7173          vice versa, and we would not be converting a single-word
7174          operation into a multi-word operation.  The latter test is not
7175          required, but it prevents generating unneeded multi-word operations.
7176          Some of the previous tests are redundant given the latter test, but
7177          are retained because they are required for correctness.
7178
7179          We produce the result slightly differently in this case.  */
7180
7181       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7182           || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7183           || ! subreg_lowpart_p (lhs)
7184           || (GET_MODE_CLASS (GET_MODE (lhs))
7185               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7186           || (GET_MODE_SIZE (GET_MODE (lhs))
7187               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7188           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7189         return x;
7190
7191       tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7192                         SUBREG_REG (lhs), SUBREG_REG (rhs));
7193       return gen_lowpart_for_combine (GET_MODE (x), tem);
7194
7195     default:
7196       return x;
7197     }
7198
7199   /* Set LHS and RHS to the inner operands (A and B in the example
7200      above) and set OTHER to the common operand (C in the example).
7201      These is only one way to do this unless the inner operation is
7202      commutative.  */
7203   if (GET_RTX_CLASS (inner_code) == 'c'
7204       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7205     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7206   else if (GET_RTX_CLASS (inner_code) == 'c'
7207            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7208     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7209   else if (GET_RTX_CLASS (inner_code) == 'c'
7210            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7211     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7212   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7213     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7214   else
7215     return x;
7216
7217   /* Form the new inner operation, seeing if it simplifies first.  */
7218   tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7219
7220   /* There is one exception to the general way of distributing:
7221      (a ^ b) | (a ^ c) -> (~a) & (b ^ c)  */
7222   if (code == XOR && inner_code == IOR)
7223     {
7224       inner_code = AND;
7225       other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7226     }
7227
7228   /* We may be able to continuing distributing the result, so call
7229      ourselves recursively on the inner operation before forming the
7230      outer operation, which we return.  */
7231   return gen_binary (inner_code, GET_MODE (x),
7232                      apply_distributive_law (tem), other);
7233 }
7234 \f
7235 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7236    in MODE.
7237
7238    Return an equivalent form, if different from X.  Otherwise, return X.  If
7239    X is zero, we are to always construct the equivalent form.  */
7240
7241 static rtx
7242 simplify_and_const_int (x, mode, varop, constop)
7243      rtx x;
7244      enum machine_mode mode;
7245      rtx varop;
7246      unsigned HOST_WIDE_INT constop;
7247 {
7248   unsigned HOST_WIDE_INT nonzero;
7249   int width = GET_MODE_BITSIZE (mode);
7250   int i;
7251
7252   /* Simplify VAROP knowing that we will be only looking at some of the
7253      bits in it.  */
7254   varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7255
7256   /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7257      CONST_INT, we are done.  */
7258   if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7259     return varop;
7260
7261   /* See what bits may be nonzero in VAROP.  Unlike the general case of
7262      a call to nonzero_bits, here we don't care about bits outside
7263      MODE.  */
7264
7265   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7266
7267   /* If this would be an entire word for the target, but is not for
7268      the host, then sign-extend on the host so that the number will look
7269      the same way on the host that it would on the target.
7270
7271      For example, when building a 64 bit alpha hosted 32 bit sparc
7272      targeted compiler, then we want the 32 bit unsigned value -1 to be
7273      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7274      The later confuses the sparc backend.  */
7275
7276   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7277       && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7278     nonzero |= ((HOST_WIDE_INT) (-1) << width);
7279
7280   /* Turn off all bits in the constant that are known to already be zero.
7281      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7282      which is tested below.  */
7283
7284   constop &= nonzero;
7285
7286   /* If we don't have any bits left, return zero.  */
7287   if (constop == 0)
7288     return const0_rtx;
7289
7290   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7291      a power of two, we can replace this with a ASHIFT.  */
7292   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7293       && (i = exact_log2 (constop)) >= 0)
7294     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7295
7296   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7297      or XOR, then try to apply the distributive law.  This may eliminate
7298      operations if either branch can be simplified because of the AND.
7299      It may also make some cases more complex, but those cases probably
7300      won't match a pattern either with or without this.  */
7301
7302   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7303     return
7304       gen_lowpart_for_combine
7305         (mode,
7306          apply_distributive_law
7307          (gen_binary (GET_CODE (varop), GET_MODE (varop),
7308                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7309                                               XEXP (varop, 0), constop),
7310                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7311                                               XEXP (varop, 1), constop))));
7312
7313   /* Get VAROP in MODE.  Try to get a SUBREG if not.  Don't make a new SUBREG
7314      if we already had one (just check for the simplest cases).  */
7315   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7316       && GET_MODE (XEXP (x, 0)) == mode
7317       && SUBREG_REG (XEXP (x, 0)) == varop)
7318     varop = XEXP (x, 0);
7319   else
7320     varop = gen_lowpart_for_combine (mode, varop);
7321
7322   /* If we can't make the SUBREG, try to return what we were given.  */
7323   if (GET_CODE (varop) == CLOBBER)
7324     return x ? x : varop;
7325
7326   /* If we are only masking insignificant bits, return VAROP.  */
7327   if (constop == nonzero)
7328     x = varop;
7329
7330   /* Otherwise, return an AND.  See how much, if any, of X we can use.  */
7331   else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7332     x = gen_binary (AND, mode, varop, GEN_INT (constop));
7333
7334   else
7335     {
7336       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7337           || INTVAL (XEXP (x, 1)) != constop)
7338         SUBST (XEXP (x, 1), GEN_INT (constop));
7339
7340       SUBST (XEXP (x, 0), varop);
7341     }
7342
7343   return x;
7344 }
7345 \f
7346 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7347    We don't let nonzero_bits recur into num_sign_bit_copies, because that
7348    is less useful.  We can't allow both, because that results in exponential
7349    run time recursion.  There is a nullstone testcase that triggered
7350    this.  This macro avoids accidental uses of num_sign_bit_copies.  */
7351 #define num_sign_bit_copies()
7352
7353 /* Given an expression, X, compute which bits in X can be non-zero.
7354    We don't care about bits outside of those defined in MODE.
7355
7356    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7357    a shift, AND, or zero_extract, we can do better.  */
7358
7359 static unsigned HOST_WIDE_INT
7360 nonzero_bits (x, mode)
7361      rtx x;
7362      enum machine_mode mode;
7363 {
7364   unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7365   unsigned HOST_WIDE_INT inner_nz;
7366   enum rtx_code code;
7367   int mode_width = GET_MODE_BITSIZE (mode);
7368   rtx tem;
7369
7370   /* For floating-point values, assume all bits are needed.  */
7371   if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7372     return nonzero;
7373
7374   /* If X is wider than MODE, use its mode instead.  */
7375   if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7376     {
7377       mode = GET_MODE (x);
7378       nonzero = GET_MODE_MASK (mode);
7379       mode_width = GET_MODE_BITSIZE (mode);
7380     }
7381
7382   if (mode_width > HOST_BITS_PER_WIDE_INT)
7383     /* Our only callers in this case look for single bit values.  So
7384        just return the mode mask.  Those tests will then be false.  */
7385     return nonzero;
7386
7387 #ifndef WORD_REGISTER_OPERATIONS
7388   /* If MODE is wider than X, but both are a single word for both the host
7389      and target machines, we can compute this from which bits of the
7390      object might be nonzero in its own mode, taking into account the fact
7391      that on many CISC machines, accessing an object in a wider mode
7392      causes the high-order bits to become undefined.  So they are
7393      not known to be zero.  */
7394
7395   if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7396       && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7397       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7398       && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7399     {
7400       nonzero &= nonzero_bits (x, GET_MODE (x));
7401       nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7402       return nonzero;
7403     }
7404 #endif
7405
7406   code = GET_CODE (x);
7407   switch (code)
7408     {
7409     case REG:
7410 #ifdef POINTERS_EXTEND_UNSIGNED
7411       /* If pointers extend unsigned and this is a pointer in Pmode, say that
7412          all the bits above ptr_mode are known to be zero.  */
7413       if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7414           && REGNO_POINTER_FLAG (REGNO (x)))
7415         nonzero &= GET_MODE_MASK (ptr_mode);
7416 #endif
7417
7418 #ifdef STACK_BOUNDARY
7419       /* If this is the stack pointer, we may know something about its
7420          alignment.  If PUSH_ROUNDING is defined, it is possible for the
7421          stack to be momentarily aligned only to that amount, so we pick
7422          the least alignment.  */
7423
7424       /* We can't check for arg_pointer_rtx here, because it is not
7425          guaranteed to have as much alignment as the stack pointer.
7426          In particular, in the Irix6 n64 ABI, the stack has 128 bit
7427          alignment but the argument pointer has only 64 bit alignment.  */
7428
7429       if ((x == frame_pointer_rtx
7430            || x == stack_pointer_rtx
7431            || x == hard_frame_pointer_rtx
7432            || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7433                && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7434 #ifdef STACK_BIAS
7435           && !STACK_BIAS
7436 #endif
7437               )
7438         {
7439           int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7440
7441 #ifdef PUSH_ROUNDING
7442           if (REGNO (x) == STACK_POINTER_REGNUM)
7443             sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7444 #endif
7445
7446           /* We must return here, otherwise we may get a worse result from
7447              one of the choices below.  There is nothing useful below as
7448              far as the stack pointer is concerned.  */
7449           return nonzero &= ~ (sp_alignment - 1);
7450         }
7451 #endif
7452
7453       /* If X is a register whose nonzero bits value is current, use it.
7454          Otherwise, if X is a register whose value we can find, use that
7455          value.  Otherwise, use the previously-computed global nonzero bits
7456          for this register.  */
7457
7458       if (reg_last_set_value[REGNO (x)] != 0
7459           && reg_last_set_mode[REGNO (x)] == mode
7460           && (REG_N_SETS (REGNO (x)) == 1
7461               || reg_last_set_label[REGNO (x)] == label_tick)
7462           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7463         return reg_last_set_nonzero_bits[REGNO (x)];
7464
7465       tem = get_last_value (x);
7466
7467       if (tem)
7468         {
7469 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7470           /* If X is narrower than MODE and TEM is a non-negative
7471              constant that would appear negative in the mode of X,
7472              sign-extend it for use in reg_nonzero_bits because some
7473              machines (maybe most) will actually do the sign-extension
7474              and this is the conservative approach.
7475
7476              ??? For 2.5, try to tighten up the MD files in this regard
7477              instead of this kludge.  */
7478
7479           if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7480               && GET_CODE (tem) == CONST_INT
7481               && INTVAL (tem) > 0
7482               && 0 != (INTVAL (tem)
7483                        & ((HOST_WIDE_INT) 1
7484                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7485             tem = GEN_INT (INTVAL (tem)
7486                            | ((HOST_WIDE_INT) (-1)
7487                               << GET_MODE_BITSIZE (GET_MODE (x))));
7488 #endif
7489           return nonzero_bits (tem, mode);
7490         }
7491       else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7492         return reg_nonzero_bits[REGNO (x)] & nonzero;
7493       else
7494         return nonzero;
7495
7496     case CONST_INT:
7497 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7498       /* If X is negative in MODE, sign-extend the value.  */
7499       if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7500           && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7501         return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7502 #endif
7503
7504       return INTVAL (x);
7505
7506     case MEM:
7507 #ifdef LOAD_EXTEND_OP
7508       /* In many, if not most, RISC machines, reading a byte from memory
7509          zeros the rest of the register.  Noticing that fact saves a lot
7510          of extra zero-extends.  */
7511       if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7512         nonzero &= GET_MODE_MASK (GET_MODE (x));
7513 #endif
7514       break;
7515
7516     case EQ:  case NE:
7517     case GT:  case GTU:
7518     case LT:  case LTU:
7519     case GE:  case GEU:
7520     case LE:  case LEU:
7521
7522       /* If this produces an integer result, we know which bits are set.
7523          Code here used to clear bits outside the mode of X, but that is
7524          now done above.  */
7525
7526       if (GET_MODE_CLASS (mode) == MODE_INT
7527           && mode_width <= HOST_BITS_PER_WIDE_INT)
7528         nonzero = STORE_FLAG_VALUE;
7529       break;
7530
7531     case NEG:
7532 #if 0
7533       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7534          and num_sign_bit_copies.  */
7535       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7536           == GET_MODE_BITSIZE (GET_MODE (x)))
7537         nonzero = 1;
7538 #endif
7539
7540       if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7541         nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7542       break;
7543
7544     case ABS:
7545 #if 0
7546       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7547          and num_sign_bit_copies.  */
7548       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7549           == GET_MODE_BITSIZE (GET_MODE (x)))
7550         nonzero = 1;
7551 #endif
7552       break;
7553
7554     case TRUNCATE:
7555       nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7556       break;
7557
7558     case ZERO_EXTEND:
7559       nonzero &= nonzero_bits (XEXP (x, 0), mode);
7560       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7561         nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7562       break;
7563
7564     case SIGN_EXTEND:
7565       /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7566          Otherwise, show all the bits in the outer mode but not the inner
7567          may be non-zero.  */
7568       inner_nz = nonzero_bits (XEXP (x, 0), mode);
7569       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7570         {
7571           inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7572           if (inner_nz
7573               & (((HOST_WIDE_INT) 1
7574                   << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7575             inner_nz |= (GET_MODE_MASK (mode)
7576                           & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7577         }
7578
7579       nonzero &= inner_nz;
7580       break;
7581
7582     case AND:
7583       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7584                   & nonzero_bits (XEXP (x, 1), mode));
7585       break;
7586
7587     case XOR:   case IOR:
7588     case UMIN:  case UMAX:  case SMIN:  case SMAX:
7589       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7590                   | nonzero_bits (XEXP (x, 1), mode));
7591       break;
7592
7593     case PLUS:  case MINUS:
7594     case MULT:
7595     case DIV:   case UDIV:
7596     case MOD:   case UMOD:
7597       /* We can apply the rules of arithmetic to compute the number of
7598          high- and low-order zero bits of these operations.  We start by
7599          computing the width (position of the highest-order non-zero bit)
7600          and the number of low-order zero bits for each value.  */
7601       {
7602         unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7603         unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7604         int width0 = floor_log2 (nz0) + 1;
7605         int width1 = floor_log2 (nz1) + 1;
7606         int low0 = floor_log2 (nz0 & -nz0);
7607         int low1 = floor_log2 (nz1 & -nz1);
7608         HOST_WIDE_INT op0_maybe_minusp
7609           = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7610         HOST_WIDE_INT op1_maybe_minusp
7611           = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7612         int result_width = mode_width;
7613         int result_low = 0;
7614
7615         switch (code)
7616           {
7617           case PLUS:
7618 #ifdef STACK_BIAS
7619             if (STACK_BIAS
7620                 && (XEXP (x, 0) == stack_pointer_rtx
7621                     || XEXP (x, 0) == frame_pointer_rtx)
7622                 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7623               {
7624                 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7625
7626                 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7627                 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7628                 width0 = floor_log2 (nz0) + 1;
7629                 width1 = floor_log2 (nz1) + 1;
7630                 low0 = floor_log2 (nz0 & -nz0);
7631                 low1 = floor_log2 (nz1 & -nz1);
7632               }
7633 #endif
7634             result_width = MAX (width0, width1) + 1;
7635             result_low = MIN (low0, low1);
7636             break;
7637           case MINUS:
7638             result_low = MIN (low0, low1);
7639             break;
7640           case MULT:
7641             result_width = width0 + width1;
7642             result_low = low0 + low1;
7643             break;
7644           case DIV:
7645             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7646               result_width = width0;
7647             break;
7648           case UDIV:
7649             result_width = width0;
7650             break;
7651           case MOD:
7652             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7653               result_width = MIN (width0, width1);
7654             result_low = MIN (low0, low1);
7655             break;
7656           case UMOD:
7657             result_width = MIN (width0, width1);
7658             result_low = MIN (low0, low1);
7659             break;
7660           default:
7661             abort ();
7662           }
7663
7664         if (result_width < mode_width)
7665           nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7666
7667         if (result_low > 0)
7668           nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7669       }
7670       break;
7671
7672     case ZERO_EXTRACT:
7673       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7674           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7675         nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7676       break;
7677
7678     case SUBREG:
7679       /* If this is a SUBREG formed for a promoted variable that has
7680          been zero-extended, we know that at least the high-order bits
7681          are zero, though others might be too.  */
7682
7683       if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7684         nonzero = (GET_MODE_MASK (GET_MODE (x))
7685                    & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7686
7687       /* If the inner mode is a single word for both the host and target
7688          machines, we can compute this from which bits of the inner
7689          object might be nonzero.  */
7690       if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7691           && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7692               <= HOST_BITS_PER_WIDE_INT))
7693         {
7694           nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7695
7696 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7697           /* If this is a typical RISC machine, we only have to worry
7698              about the way loads are extended.  */
7699           if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7700               ? (nonzero
7701                  & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7702               : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
7703 #endif
7704             {
7705               /* On many CISC machines, accessing an object in a wider mode
7706                  causes the high-order bits to become undefined.  So they are
7707                  not known to be zero.  */
7708               if (GET_MODE_SIZE (GET_MODE (x))
7709                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7710                 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7711                             & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7712             }
7713         }
7714       break;
7715
7716     case ASHIFTRT:
7717     case LSHIFTRT:
7718     case ASHIFT:
7719     case ROTATE:
7720       /* The nonzero bits are in two classes: any bits within MODE
7721          that aren't in GET_MODE (x) are always significant.  The rest of the
7722          nonzero bits are those that are significant in the operand of
7723          the shift when shifted the appropriate number of bits.  This
7724          shows that high-order bits are cleared by the right shift and
7725          low-order bits by left shifts.  */
7726       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7727           && INTVAL (XEXP (x, 1)) >= 0
7728           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7729         {
7730           enum machine_mode inner_mode = GET_MODE (x);
7731           int width = GET_MODE_BITSIZE (inner_mode);
7732           int count = INTVAL (XEXP (x, 1));
7733           unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7734           unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7735           unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7736           unsigned HOST_WIDE_INT outer = 0;
7737
7738           if (mode_width > width)
7739             outer = (op_nonzero & nonzero & ~ mode_mask);
7740
7741           if (code == LSHIFTRT)
7742             inner >>= count;
7743           else if (code == ASHIFTRT)
7744             {
7745               inner >>= count;
7746
7747               /* If the sign bit may have been nonzero before the shift, we
7748                  need to mark all the places it could have been copied to
7749                  by the shift as possibly nonzero.  */
7750               if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7751                 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7752             }
7753           else if (code == ASHIFT)
7754             inner <<= count;
7755           else
7756             inner = ((inner << (count % width)
7757                       | (inner >> (width - (count % width)))) & mode_mask);
7758
7759           nonzero &= (outer | inner);
7760         }
7761       break;
7762
7763     case FFS:
7764       /* This is at most the number of bits in the mode.  */
7765       nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7766       break;
7767
7768     case IF_THEN_ELSE:
7769       nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7770                   | nonzero_bits (XEXP (x, 2), mode));
7771       break;
7772
7773     default:
7774       break;
7775     }
7776
7777   return nonzero;
7778 }
7779
7780 /* See the macro definition above.  */
7781 #undef num_sign_bit_copies
7782 \f
7783 /* Return the number of bits at the high-order end of X that are known to
7784    be equal to the sign bit.  X will be used in mode MODE; if MODE is
7785    VOIDmode, X will be used in its own mode.  The returned value  will always
7786    be between 1 and the number of bits in MODE.  */
7787
7788 static int
7789 num_sign_bit_copies (x, mode)
7790      rtx x;
7791      enum machine_mode mode;
7792 {
7793   enum rtx_code code = GET_CODE (x);
7794   int bitwidth;
7795   int num0, num1, result;
7796   unsigned HOST_WIDE_INT nonzero;
7797   rtx tem;
7798
7799   /* If we weren't given a mode, use the mode of X.  If the mode is still
7800      VOIDmode, we don't know anything.  Likewise if one of the modes is
7801      floating-point.  */
7802
7803   if (mode == VOIDmode)
7804     mode = GET_MODE (x);
7805
7806   if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7807     return 1;
7808
7809   bitwidth = GET_MODE_BITSIZE (mode);
7810
7811   /* For a smaller object, just ignore the high bits.  */
7812   if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7813     return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7814                     - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7815
7816   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7817     {
7818 #ifndef WORD_REGISTER_OPERATIONS
7819   /* If this machine does not do all register operations on the entire
7820      register and MODE is wider than the mode of X, we can say nothing
7821      at all about the high-order bits.  */
7822       return 1;
7823 #else
7824       /* Likewise on machines that do, if the mode of the object is smaller
7825          than a word and loads of that size don't sign extend, we can say
7826          nothing about the high order bits.  */
7827       if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7828 #ifdef LOAD_EXTEND_OP
7829           && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7830 #endif
7831           )
7832         return 1;
7833 #endif
7834     }
7835
7836   switch (code)
7837     {
7838     case REG:
7839
7840 #ifdef POINTERS_EXTEND_UNSIGNED
7841       /* If pointers extend signed and this is a pointer in Pmode, say that
7842          all the bits above ptr_mode are known to be sign bit copies.  */
7843       if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7844           && REGNO_POINTER_FLAG (REGNO (x)))
7845         return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7846 #endif
7847
7848       if (reg_last_set_value[REGNO (x)] != 0
7849           && reg_last_set_mode[REGNO (x)] == mode
7850           && (REG_N_SETS (REGNO (x)) == 1
7851               || reg_last_set_label[REGNO (x)] == label_tick)
7852           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7853         return reg_last_set_sign_bit_copies[REGNO (x)];
7854
7855       tem =  get_last_value (x);
7856       if (tem != 0)
7857         return num_sign_bit_copies (tem, mode);
7858
7859       if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7860         return reg_sign_bit_copies[REGNO (x)];
7861       break;
7862
7863     case MEM:
7864 #ifdef LOAD_EXTEND_OP
7865       /* Some RISC machines sign-extend all loads of smaller than a word.  */
7866       if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7867         return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7868 #endif
7869       break;
7870
7871     case CONST_INT:
7872       /* If the constant is negative, take its 1's complement and remask.
7873          Then see how many zero bits we have.  */
7874       nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7875       if (bitwidth <= HOST_BITS_PER_WIDE_INT
7876           && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7877         nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7878
7879       return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7880
7881     case SUBREG:
7882       /* If this is a SUBREG for a promoted object that is sign-extended
7883          and we are looking at it in a wider mode, we know that at least the
7884          high-order bits are known to be sign bit copies.  */
7885
7886       if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7887         return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7888                     num_sign_bit_copies (SUBREG_REG (x), mode));
7889
7890       /* For a smaller object, just ignore the high bits.  */
7891       if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7892         {
7893           num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7894           return MAX (1, (num0
7895                           - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7896                              - bitwidth)));
7897         }
7898
7899 #ifdef WORD_REGISTER_OPERATIONS
7900 #ifdef LOAD_EXTEND_OP
7901       /* For paradoxical SUBREGs on machines where all register operations
7902          affect the entire register, just look inside.  Note that we are
7903          passing MODE to the recursive call, so the number of sign bit copies
7904          will remain relative to that mode, not the inner mode.  */
7905
7906       /* This works only if loads sign extend.  Otherwise, if we get a
7907          reload for the inner part, it may be loaded from the stack, and
7908          then we lose all sign bit copies that existed before the store
7909          to the stack.  */
7910
7911       if ((GET_MODE_SIZE (GET_MODE (x))
7912            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7913           && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7914         return num_sign_bit_copies (SUBREG_REG (x), mode);
7915 #endif
7916 #endif
7917       break;
7918
7919     case SIGN_EXTRACT:
7920       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7921         return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7922       break;
7923
7924     case SIGN_EXTEND:
7925       return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7926               + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7927
7928     case TRUNCATE:
7929       /* For a smaller object, just ignore the high bits.  */
7930       num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7931       return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7932                               - bitwidth)));
7933
7934     case NOT:
7935       return num_sign_bit_copies (XEXP (x, 0), mode);
7936
7937     case ROTATE:       case ROTATERT:
7938       /* If we are rotating left by a number of bits less than the number
7939          of sign bit copies, we can just subtract that amount from the
7940          number.  */
7941       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7942           && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7943         {
7944           num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7945           return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7946                                  : bitwidth - INTVAL (XEXP (x, 1))));
7947         }
7948       break;
7949
7950     case NEG:
7951       /* In general, this subtracts one sign bit copy.  But if the value
7952          is known to be positive, the number of sign bit copies is the
7953          same as that of the input.  Finally, if the input has just one bit
7954          that might be nonzero, all the bits are copies of the sign bit.  */
7955       nonzero = nonzero_bits (XEXP (x, 0), mode);
7956       if (nonzero == 1)
7957         return bitwidth;
7958
7959       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7960       if (num0 > 1
7961           && bitwidth <= HOST_BITS_PER_WIDE_INT
7962           && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7963         num0--;
7964
7965       return num0;
7966
7967     case IOR:   case AND:   case XOR:
7968     case SMIN:  case SMAX:  case UMIN:  case UMAX:
7969       /* Logical operations will preserve the number of sign-bit copies.
7970          MIN and MAX operations always return one of the operands.  */
7971       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7972       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7973       return MIN (num0, num1);
7974
7975     case PLUS:  case MINUS:
7976       /* For addition and subtraction, we can have a 1-bit carry.  However,
7977          if we are subtracting 1 from a positive number, there will not
7978          be such a carry.  Furthermore, if the positive number is known to
7979          be 0 or 1, we know the result is either -1 or 0.  */
7980
7981       if (code == PLUS && XEXP (x, 1) == constm1_rtx
7982           && bitwidth <= HOST_BITS_PER_WIDE_INT)
7983         {
7984           nonzero = nonzero_bits (XEXP (x, 0), mode);
7985           if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7986             return (nonzero == 1 || nonzero == 0 ? bitwidth
7987                     : bitwidth - floor_log2 (nonzero) - 1);
7988         }
7989
7990       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7991       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7992       return MAX (1, MIN (num0, num1) - 1);
7993
7994     case MULT:
7995       /* The number of bits of the product is the sum of the number of
7996          bits of both terms.  However, unless one of the terms if known
7997          to be positive, we must allow for an additional bit since negating
7998          a negative number can remove one sign bit copy.  */
7999
8000       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8001       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8002
8003       result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8004       if (result > 0
8005           && bitwidth <= HOST_BITS_PER_WIDE_INT
8006           && ((nonzero_bits (XEXP (x, 0), mode)
8007                & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8008           && ((nonzero_bits (XEXP (x, 1), mode)
8009               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8010         result--;
8011
8012       return MAX (1, result);
8013
8014     case UDIV:
8015       /* The result must be <= the first operand.  */
8016       return num_sign_bit_copies (XEXP (x, 0), mode);
8017
8018     case UMOD:
8019       /* The result must be <= the scond operand.  */
8020       return num_sign_bit_copies (XEXP (x, 1), mode);
8021
8022     case DIV:
8023       /* Similar to unsigned division, except that we have to worry about
8024          the case where the divisor is negative, in which case we have
8025          to add 1.  */
8026       result = num_sign_bit_copies (XEXP (x, 0), mode);
8027       if (result > 1
8028           && bitwidth <= HOST_BITS_PER_WIDE_INT
8029           && (nonzero_bits (XEXP (x, 1), mode)
8030               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8031         result --;
8032
8033       return result;
8034
8035     case MOD:
8036       result = num_sign_bit_copies (XEXP (x, 1), mode);
8037       if (result > 1
8038           && bitwidth <= HOST_BITS_PER_WIDE_INT
8039           && (nonzero_bits (XEXP (x, 1), mode)
8040               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8041         result --;
8042
8043       return result;
8044
8045     case ASHIFTRT:
8046       /* Shifts by a constant add to the number of bits equal to the
8047          sign bit.  */
8048       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8049       if (GET_CODE (XEXP (x, 1)) == CONST_INT
8050           && INTVAL (XEXP (x, 1)) > 0)
8051         num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8052
8053       return num0;
8054
8055     case ASHIFT:
8056       /* Left shifts destroy copies.  */
8057       if (GET_CODE (XEXP (x, 1)) != CONST_INT
8058           || INTVAL (XEXP (x, 1)) < 0
8059           || INTVAL (XEXP (x, 1)) >= bitwidth)
8060         return 1;
8061
8062       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8063       return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8064
8065     case IF_THEN_ELSE:
8066       num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8067       num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8068       return MIN (num0, num1);
8069
8070     case EQ:  case NE:  case GE:  case GT:  case LE:  case LT:
8071     case GEU: case GTU: case LEU: case LTU:
8072       if (STORE_FLAG_VALUE == -1)
8073         return bitwidth;
8074       break;
8075
8076     default:
8077       break;
8078     }
8079
8080   /* If we haven't been able to figure it out by one of the above rules,
8081      see if some of the high-order bits are known to be zero.  If so,
8082      count those bits and return one less than that amount.  If we can't
8083      safely compute the mask for this mode, always return BITWIDTH.  */
8084
8085   if (bitwidth > HOST_BITS_PER_WIDE_INT)
8086     return 1;
8087
8088   nonzero = nonzero_bits (x, mode);
8089   return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8090           ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8091 }
8092 \f
8093 /* Return the number of "extended" bits there are in X, when interpreted
8094    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8095    unsigned quantities, this is the number of high-order zero bits.
8096    For signed quantities, this is the number of copies of the sign bit
8097    minus 1.  In both case, this function returns the number of "spare"
8098    bits.  For example, if two quantities for which this function returns
8099    at least 1 are added, the addition is known not to overflow.
8100
8101    This function will always return 0 unless called during combine, which
8102    implies that it must be called from a define_split.  */
8103
8104 int
8105 extended_count (x, mode, unsignedp)
8106      rtx x;
8107      enum machine_mode mode;
8108      int unsignedp;
8109 {
8110   if (nonzero_sign_valid == 0)
8111     return 0;
8112
8113   return (unsignedp
8114           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8115              && (GET_MODE_BITSIZE (mode) - 1
8116                  - floor_log2 (nonzero_bits (x, mode))))
8117           : num_sign_bit_copies (x, mode) - 1);
8118 }
8119 \f
8120 /* This function is called from `simplify_shift_const' to merge two
8121    outer operations.  Specifically, we have already found that we need
8122    to perform operation *POP0 with constant *PCONST0 at the outermost
8123    position.  We would now like to also perform OP1 with constant CONST1
8124    (with *POP0 being done last).
8125
8126    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8127    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8128    complement the innermost operand, otherwise it is unchanged.
8129
8130    MODE is the mode in which the operation will be done.  No bits outside
8131    the width of this mode matter.  It is assumed that the width of this mode
8132    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8133
8134    If *POP0 or OP1 are NIL, it means no operation is required.  Only NEG, PLUS,
8135    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8136    result is simply *PCONST0.
8137
8138    If the resulting operation cannot be expressed as one operation, we
8139    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8140
8141 static int
8142 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8143      enum rtx_code *pop0;
8144      HOST_WIDE_INT *pconst0;
8145      enum rtx_code op1;
8146      HOST_WIDE_INT const1;
8147      enum machine_mode mode;
8148      int *pcomp_p;
8149 {
8150   enum rtx_code op0 = *pop0;
8151   HOST_WIDE_INT const0 = *pconst0;
8152   int width = GET_MODE_BITSIZE (mode);
8153
8154   const0 &= GET_MODE_MASK (mode);
8155   const1 &= GET_MODE_MASK (mode);
8156
8157   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8158   if (op0 == AND)
8159     const1 &= const0;
8160
8161   /* If OP0 or OP1 is NIL, this is easy.  Similarly if they are the same or
8162      if OP0 is SET.  */
8163
8164   if (op1 == NIL || op0 == SET)
8165     return 1;
8166
8167   else if (op0 == NIL)
8168     op0 = op1, const0 = const1;
8169
8170   else if (op0 == op1)
8171     {
8172       switch (op0)
8173         {
8174         case AND:
8175           const0 &= const1;
8176           break;
8177         case IOR:
8178           const0 |= const1;
8179           break;
8180         case XOR:
8181           const0 ^= const1;
8182           break;
8183         case PLUS:
8184           const0 += const1;
8185           break;
8186         case NEG:
8187           op0 = NIL;
8188           break;
8189         default:
8190           break;
8191         }
8192     }
8193
8194   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8195   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8196     return 0;
8197
8198   /* If the two constants aren't the same, we can't do anything.  The
8199      remaining six cases can all be done.  */
8200   else if (const0 != const1)
8201     return 0;
8202
8203   else
8204     switch (op0)
8205       {
8206       case IOR:
8207         if (op1 == AND)
8208           /* (a & b) | b == b */
8209           op0 = SET;
8210         else /* op1 == XOR */
8211           /* (a ^ b) | b == a | b */
8212           {;}
8213         break;
8214
8215       case XOR:
8216         if (op1 == AND)
8217           /* (a & b) ^ b == (~a) & b */
8218           op0 = AND, *pcomp_p = 1;
8219         else /* op1 == IOR */
8220           /* (a | b) ^ b == a & ~b */
8221           op0 = AND, *pconst0 = ~ const0;
8222         break;
8223
8224       case AND:
8225         if (op1 == IOR)
8226           /* (a | b) & b == b */
8227         op0 = SET;
8228         else /* op1 == XOR */
8229           /* (a ^ b) & b) == (~a) & b */
8230           *pcomp_p = 1;
8231         break;
8232       default:
8233         break;
8234       }
8235
8236   /* Check for NO-OP cases.  */
8237   const0 &= GET_MODE_MASK (mode);
8238   if (const0 == 0
8239       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8240     op0 = NIL;
8241   else if (const0 == 0 && op0 == AND)
8242     op0 = SET;
8243   else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8244     op0 = NIL;
8245
8246   /* If this would be an entire word for the target, but is not for
8247      the host, then sign-extend on the host so that the number will look
8248      the same way on the host that it would on the target.
8249
8250      For example, when building a 64 bit alpha hosted 32 bit sparc
8251      targeted compiler, then we want the 32 bit unsigned value -1 to be
8252      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8253      The later confuses the sparc backend.  */
8254
8255   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8256       && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8257     const0 |= ((HOST_WIDE_INT) (-1) << width);
8258
8259   *pop0 = op0;
8260   *pconst0 = const0;
8261
8262   return 1;
8263 }
8264 \f
8265 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8266    The result of the shift is RESULT_MODE.  X, if non-zero, is an expression
8267    that we started with.
8268
8269    The shift is normally computed in the widest mode we find in VAROP, as
8270    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8271    are ASHIFTRT and ROTATE, which are always done in their original mode,  */
8272
8273 static rtx
8274 simplify_shift_const (x, code, result_mode, varop, count)
8275      rtx x;
8276      enum rtx_code code;
8277      enum machine_mode result_mode;
8278      rtx varop;
8279      int count;
8280 {
8281   enum rtx_code orig_code = code;
8282   int orig_count = count;
8283   enum machine_mode mode = result_mode;
8284   enum machine_mode shift_mode, tmode;
8285   int mode_words
8286     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8287   /* We form (outer_op (code varop count) (outer_const)).  */
8288   enum rtx_code outer_op = NIL;
8289   HOST_WIDE_INT outer_const = 0;
8290   rtx const_rtx;
8291   int complement_p = 0;
8292   rtx new;
8293
8294   /* If we were given an invalid count, don't do anything except exactly
8295      what was requested.  */
8296
8297   if (count < 0 || count > GET_MODE_BITSIZE (mode))
8298     {
8299       if (x)
8300         return x;
8301
8302       return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8303     }
8304
8305   /* Unless one of the branches of the `if' in this loop does a `continue',
8306      we will `break' the loop after the `if'.  */
8307
8308   while (count != 0)
8309     {
8310       /* If we have an operand of (clobber (const_int 0)), just return that
8311          value.  */
8312       if (GET_CODE (varop) == CLOBBER)
8313         return varop;
8314
8315       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8316          here would cause an infinite loop.  */
8317       if (complement_p)
8318         break;
8319
8320       /* Convert ROTATERT to ROTATE.  */
8321       if (code == ROTATERT)
8322         code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8323
8324       /* We need to determine what mode we will do the shift in.  If the
8325          shift is a right shift or a ROTATE, we must always do it in the mode
8326          it was originally done in.  Otherwise, we can do it in MODE, the
8327          widest mode encountered.  */
8328       shift_mode
8329         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8330            ? result_mode : mode);
8331
8332       /* Handle cases where the count is greater than the size of the mode
8333          minus 1.  For ASHIFT, use the size minus one as the count (this can
8334          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8335          take the count modulo the size.  For other shifts, the result is
8336          zero.
8337
8338          Since these shifts are being produced by the compiler by combining
8339          multiple operations, each of which are defined, we know what the
8340          result is supposed to be.  */
8341
8342       if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8343         {
8344           if (code == ASHIFTRT)
8345             count = GET_MODE_BITSIZE (shift_mode) - 1;
8346           else if (code == ROTATE || code == ROTATERT)
8347             count %= GET_MODE_BITSIZE (shift_mode);
8348           else
8349             {
8350               /* We can't simply return zero because there may be an
8351                  outer op.  */
8352               varop = const0_rtx;
8353               count = 0;
8354               break;
8355             }
8356         }
8357
8358       /* Negative counts are invalid and should not have been made (a
8359          programmer-specified negative count should have been handled
8360          above).  */
8361       else if (count < 0)
8362         abort ();
8363
8364       /* An arithmetic right shift of a quantity known to be -1 or 0
8365          is a no-op.  */
8366       if (code == ASHIFTRT
8367           && (num_sign_bit_copies (varop, shift_mode)
8368               == GET_MODE_BITSIZE (shift_mode)))
8369         {
8370           count = 0;
8371           break;
8372         }
8373
8374       /* If we are doing an arithmetic right shift and discarding all but
8375          the sign bit copies, this is equivalent to doing a shift by the
8376          bitsize minus one.  Convert it into that shift because it will often
8377          allow other simplifications.  */
8378
8379       if (code == ASHIFTRT
8380           && (count + num_sign_bit_copies (varop, shift_mode)
8381               >= GET_MODE_BITSIZE (shift_mode)))
8382         count = GET_MODE_BITSIZE (shift_mode) - 1;
8383
8384       /* We simplify the tests below and elsewhere by converting
8385          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8386          `make_compound_operation' will convert it to a ASHIFTRT for
8387          those machines (such as Vax) that don't have a LSHIFTRT.  */
8388       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8389           && code == ASHIFTRT
8390           && ((nonzero_bits (varop, shift_mode)
8391                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8392               == 0))
8393         code = LSHIFTRT;
8394
8395       switch (GET_CODE (varop))
8396         {
8397         case SIGN_EXTEND:
8398         case ZERO_EXTEND:
8399         case SIGN_EXTRACT:
8400         case ZERO_EXTRACT:
8401           new = expand_compound_operation (varop);
8402           if (new != varop)
8403             {
8404               varop = new;
8405               continue;
8406             }
8407           break;
8408
8409         case MEM:
8410           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8411              minus the width of a smaller mode, we can do this with a
8412              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8413           if ((code == ASHIFTRT || code == LSHIFTRT)
8414               && ! mode_dependent_address_p (XEXP (varop, 0))
8415               && ! MEM_VOLATILE_P (varop)
8416               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8417                                          MODE_INT, 1)) != BLKmode)
8418             {
8419               if (BYTES_BIG_ENDIAN)
8420                 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8421               else
8422                 new = gen_rtx_MEM (tmode,
8423                                    plus_constant (XEXP (varop, 0),
8424                                                   count / BITS_PER_UNIT));
8425               RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8426               MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8427               MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8428               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8429                                        : ZERO_EXTEND, mode, new);
8430               count = 0;
8431               continue;
8432             }
8433           break;
8434
8435         case USE:
8436           /* Similar to the case above, except that we can only do this if
8437              the resulting mode is the same as that of the underlying
8438              MEM and adjust the address depending on the *bits* endianness
8439              because of the way that bit-field extract insns are defined.  */
8440           if ((code == ASHIFTRT || code == LSHIFTRT)
8441               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8442                                          MODE_INT, 1)) != BLKmode
8443               && tmode == GET_MODE (XEXP (varop, 0)))
8444             {
8445               if (BITS_BIG_ENDIAN)
8446                 new = XEXP (varop, 0);
8447               else
8448                 {
8449                   new = copy_rtx (XEXP (varop, 0));
8450                   SUBST (XEXP (new, 0),
8451                          plus_constant (XEXP (new, 0),
8452                                         count / BITS_PER_UNIT));
8453                 }
8454
8455               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8456                                        : ZERO_EXTEND, mode, new);
8457               count = 0;
8458               continue;
8459             }
8460           break;
8461
8462         case SUBREG:
8463           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8464              the same number of words as what we've seen so far.  Then store
8465              the widest mode in MODE.  */
8466           if (subreg_lowpart_p (varop)
8467               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8468                   > GET_MODE_SIZE (GET_MODE (varop)))
8469               && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8470                     + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8471                   == mode_words))
8472             {
8473               varop = SUBREG_REG (varop);
8474               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8475                 mode = GET_MODE (varop);
8476               continue;
8477             }
8478           break;
8479
8480         case MULT:
8481           /* Some machines use MULT instead of ASHIFT because MULT
8482              is cheaper.  But it is still better on those machines to
8483              merge two shifts into one.  */
8484           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8485               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8486             {
8487               varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8488                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8489               continue;
8490             }
8491           break;
8492
8493         case UDIV:
8494           /* Similar, for when divides are cheaper.  */
8495           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8496               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8497             {
8498               varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8499                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8500               continue;
8501             }
8502           break;
8503
8504         case ASHIFTRT:
8505           /* If we are extracting just the sign bit of an arithmetic right
8506              shift, that shift is not needed.  */
8507           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8508             {
8509               varop = XEXP (varop, 0);
8510               continue;
8511             }
8512
8513           /* ... fall through ...  */
8514
8515         case LSHIFTRT:
8516         case ASHIFT:
8517         case ROTATE:
8518           /* Here we have two nested shifts.  The result is usually the
8519              AND of a new shift with a mask.  We compute the result below.  */
8520           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8521               && INTVAL (XEXP (varop, 1)) >= 0
8522               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8523               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8524               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8525             {
8526               enum rtx_code first_code = GET_CODE (varop);
8527               int first_count = INTVAL (XEXP (varop, 1));
8528               unsigned HOST_WIDE_INT mask;
8529               rtx mask_rtx;
8530
8531               /* We have one common special case.  We can't do any merging if
8532                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8533                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8534                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8535                  we can convert it to
8536                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8537                  This simplifies certain SIGN_EXTEND operations.  */
8538               if (code == ASHIFT && first_code == ASHIFTRT
8539                   && (GET_MODE_BITSIZE (result_mode)
8540                       - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8541                 {
8542                   /* C3 has the low-order C1 bits zero.  */
8543
8544                   mask = (GET_MODE_MASK (mode)
8545                           & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8546
8547                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8548                                                   XEXP (varop, 0), mask);
8549                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8550                                                 varop, count);
8551                   count = first_count;
8552                   code = ASHIFTRT;
8553                   continue;
8554                 }
8555
8556               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8557                  than C1 high-order bits equal to the sign bit, we can convert
8558                  this to either an ASHIFT or a ASHIFTRT depending on the
8559                  two counts.
8560
8561                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8562
8563               if (code == ASHIFTRT && first_code == ASHIFT
8564                   && GET_MODE (varop) == shift_mode
8565                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8566                       > first_count))
8567                 {
8568                   count -= first_count;
8569                   if (count < 0)
8570                     count = - count, code = ASHIFT;
8571                   varop = XEXP (varop, 0);
8572                   continue;
8573                 }
8574
8575               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8576                  we can only do this if FIRST_CODE is also ASHIFTRT.
8577
8578                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8579                  ASHIFTRT.
8580
8581                  If the mode of this shift is not the mode of the outer shift,
8582                  we can't do this if either shift is a right shift or ROTATE.
8583
8584                  Finally, we can't do any of these if the mode is too wide
8585                  unless the codes are the same.
8586
8587                  Handle the case where the shift codes are the same
8588                  first.  */
8589
8590               if (code == first_code)
8591                 {
8592                   if (GET_MODE (varop) != result_mode
8593                       && (code == ASHIFTRT || code == LSHIFTRT
8594                           || code == ROTATE))
8595                     break;
8596
8597                   count += first_count;
8598                   varop = XEXP (varop, 0);
8599                   continue;
8600                 }
8601
8602               if (code == ASHIFTRT
8603                   || (code == ROTATE && first_code == ASHIFTRT)
8604                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8605                   || (GET_MODE (varop) != result_mode
8606                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8607                           || first_code == ROTATE
8608                           || code == ROTATE)))
8609                 break;
8610
8611               /* To compute the mask to apply after the shift, shift the
8612                  nonzero bits of the inner shift the same way the
8613                  outer shift will.  */
8614
8615               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8616
8617               mask_rtx
8618                 = simplify_binary_operation (code, result_mode, mask_rtx,
8619                                              GEN_INT (count));
8620
8621               /* Give up if we can't compute an outer operation to use.  */
8622               if (mask_rtx == 0
8623                   || GET_CODE (mask_rtx) != CONST_INT
8624                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8625                                         INTVAL (mask_rtx),
8626                                         result_mode, &complement_p))
8627                 break;
8628
8629               /* If the shifts are in the same direction, we add the
8630                  counts.  Otherwise, we subtract them.  */
8631               if ((code == ASHIFTRT || code == LSHIFTRT)
8632                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8633                 count += first_count;
8634               else
8635                 count -= first_count;
8636
8637               /* If COUNT is positive, the new shift is usually CODE,
8638                  except for the two exceptions below, in which case it is
8639                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8640                  always be used  */
8641               if (count > 0
8642                   && ((first_code == ROTATE && code == ASHIFT)
8643                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8644                 code = first_code;
8645               else if (count < 0)
8646                 code = first_code, count = - count;
8647
8648               varop = XEXP (varop, 0);
8649               continue;
8650             }
8651
8652           /* If we have (A << B << C) for any shift, we can convert this to
8653              (A << C << B).  This wins if A is a constant.  Only try this if
8654              B is not a constant.  */
8655
8656           else if (GET_CODE (varop) == code
8657                    && GET_CODE (XEXP (varop, 1)) != CONST_INT
8658                    && 0 != (new
8659                             = simplify_binary_operation (code, mode,
8660                                                          XEXP (varop, 0),
8661                                                          GEN_INT (count))))
8662             {
8663               varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8664               count = 0;
8665               continue;
8666             }
8667           break;
8668
8669         case NOT:
8670           /* Make this fit the case below.  */
8671           varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8672                                    GEN_INT (GET_MODE_MASK (mode)));
8673           continue;
8674
8675         case IOR:
8676         case AND:
8677         case XOR:
8678           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8679              with C the size of VAROP - 1 and the shift is logical if
8680              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8681              we have an (le X 0) operation.   If we have an arithmetic shift
8682              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8683              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8684
8685           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8686               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8687               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8688               && (code == LSHIFTRT || code == ASHIFTRT)
8689               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8690               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8691             {
8692               count = 0;
8693               varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8694                                        const0_rtx);
8695
8696               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8697                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8698
8699               continue;
8700             }
8701
8702           /* If we have (shift (logical)), move the logical to the outside
8703              to allow it to possibly combine with another logical and the
8704              shift to combine with another shift.  This also canonicalizes to
8705              what a ZERO_EXTRACT looks like.  Also, some machines have
8706              (and (shift)) insns.  */
8707
8708           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8709               && (new = simplify_binary_operation (code, result_mode,
8710                                                    XEXP (varop, 1),
8711                                                    GEN_INT (count))) != 0
8712               && GET_CODE(new) == CONST_INT
8713               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8714                                   INTVAL (new), result_mode, &complement_p))
8715             {
8716               varop = XEXP (varop, 0);
8717               continue;
8718             }
8719
8720           /* If we can't do that, try to simplify the shift in each arm of the
8721              logical expression, make a new logical expression, and apply
8722              the inverse distributive law.  */
8723           {
8724             rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8725                                             XEXP (varop, 0), count);
8726             rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8727                                             XEXP (varop, 1), count);
8728
8729             varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8730             varop = apply_distributive_law (varop);
8731
8732             count = 0;
8733           }
8734           break;
8735
8736         case EQ:
8737           /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8738              says that the sign bit can be tested, FOO has mode MODE, C is
8739              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8740              that may be nonzero.  */
8741           if (code == LSHIFTRT
8742               && XEXP (varop, 1) == const0_rtx
8743               && GET_MODE (XEXP (varop, 0)) == result_mode
8744               && count == GET_MODE_BITSIZE (result_mode) - 1
8745               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8746               && ((STORE_FLAG_VALUE
8747                    & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8748               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8749               && merge_outer_ops (&outer_op, &outer_const, XOR,
8750                                   (HOST_WIDE_INT) 1, result_mode,
8751                                   &complement_p))
8752             {
8753               varop = XEXP (varop, 0);
8754               count = 0;
8755               continue;
8756             }
8757           break;
8758
8759         case NEG:
8760           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8761              than the number of bits in the mode is equivalent to A.  */
8762           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8763               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8764             {
8765               varop = XEXP (varop, 0);
8766               count = 0;
8767               continue;
8768             }
8769
8770           /* NEG commutes with ASHIFT since it is multiplication.  Move the
8771              NEG outside to allow shifts to combine.  */
8772           if (code == ASHIFT
8773               && merge_outer_ops (&outer_op, &outer_const, NEG,
8774                                   (HOST_WIDE_INT) 0, result_mode,
8775                                   &complement_p))
8776             {
8777               varop = XEXP (varop, 0);
8778               continue;
8779             }
8780           break;
8781
8782         case PLUS:
8783           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8784              is one less than the number of bits in the mode is
8785              equivalent to (xor A 1).  */
8786           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8787               && XEXP (varop, 1) == constm1_rtx
8788               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8789               && merge_outer_ops (&outer_op, &outer_const, XOR,
8790                                   (HOST_WIDE_INT) 1, result_mode,
8791                                   &complement_p))
8792             {
8793               count = 0;
8794               varop = XEXP (varop, 0);
8795               continue;
8796             }
8797
8798           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8799              that might be nonzero in BAR are those being shifted out and those
8800              bits are known zero in FOO, we can replace the PLUS with FOO.
8801              Similarly in the other operand order.  This code occurs when
8802              we are computing the size of a variable-size array.  */
8803
8804           if ((code == ASHIFTRT || code == LSHIFTRT)
8805               && count < HOST_BITS_PER_WIDE_INT
8806               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8807               && (nonzero_bits (XEXP (varop, 1), result_mode)
8808                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8809             {
8810               varop = XEXP (varop, 0);
8811               continue;
8812             }
8813           else if ((code == ASHIFTRT || code == LSHIFTRT)
8814                    && count < HOST_BITS_PER_WIDE_INT
8815                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8816                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8817                             >> count)
8818                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8819                             & nonzero_bits (XEXP (varop, 1),
8820                                                  result_mode)))
8821             {
8822               varop = XEXP (varop, 1);
8823               continue;
8824             }
8825
8826           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
8827           if (code == ASHIFT
8828               && GET_CODE (XEXP (varop, 1)) == CONST_INT
8829               && (new = simplify_binary_operation (ASHIFT, result_mode,
8830                                                    XEXP (varop, 1),
8831                                                    GEN_INT (count))) != 0
8832               && GET_CODE(new) == CONST_INT
8833               && merge_outer_ops (&outer_op, &outer_const, PLUS,
8834                                   INTVAL (new), result_mode, &complement_p))
8835             {
8836               varop = XEXP (varop, 0);
8837               continue;
8838             }
8839           break;
8840
8841         case MINUS:
8842           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8843              with C the size of VAROP - 1 and the shift is logical if
8844              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8845              we have a (gt X 0) operation.  If the shift is arithmetic with
8846              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8847              we have a (neg (gt X 0)) operation.  */
8848
8849           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8850               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8851               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8852               && (code == LSHIFTRT || code == ASHIFTRT)
8853               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8854               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8855               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8856             {
8857               count = 0;
8858               varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8859                                        const0_rtx);
8860
8861               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8862                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8863
8864               continue;
8865             }
8866           break;
8867
8868         case TRUNCATE:
8869           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8870              if the truncate does not affect the value.  */
8871           if (code == LSHIFTRT
8872               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8873               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8874               && (INTVAL (XEXP (XEXP (varop, 0), 1))
8875                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8876                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
8877             {
8878               rtx varop_inner = XEXP (varop, 0);
8879
8880               varop_inner = gen_rtx_combine (LSHIFTRT,
8881                                              GET_MODE (varop_inner),
8882                                              XEXP (varop_inner, 0),
8883                                              GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8884               varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8885                                        varop_inner);
8886               count = 0;
8887               continue;
8888             }
8889           break;
8890
8891         default:
8892           break;
8893         }
8894
8895       break;
8896     }
8897
8898   /* We need to determine what mode to do the shift in.  If the shift is
8899      a right shift or ROTATE, we must always do it in the mode it was
8900      originally done in.  Otherwise, we can do it in MODE, the widest mode
8901      encountered.  The code we care about is that of the shift that will
8902      actually be done, not the shift that was originally requested.  */
8903   shift_mode
8904     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8905        ? result_mode : mode);
8906
8907   /* We have now finished analyzing the shift.  The result should be
8908      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
8909      OUTER_OP is non-NIL, it is an operation that needs to be applied
8910      to the result of the shift.  OUTER_CONST is the relevant constant,
8911      but we must turn off all bits turned off in the shift.
8912
8913      If we were passed a value for X, see if we can use any pieces of
8914      it.  If not, make new rtx.  */
8915
8916   if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8917       && GET_CODE (XEXP (x, 1)) == CONST_INT
8918       && INTVAL (XEXP (x, 1)) == count)
8919     const_rtx = XEXP (x, 1);
8920   else
8921     const_rtx = GEN_INT (count);
8922
8923   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8924       && GET_MODE (XEXP (x, 0)) == shift_mode
8925       && SUBREG_REG (XEXP (x, 0)) == varop)
8926     varop = XEXP (x, 0);
8927   else if (GET_MODE (varop) != shift_mode)
8928     varop = gen_lowpart_for_combine (shift_mode, varop);
8929
8930   /* If we can't make the SUBREG, try to return what we were given.  */
8931   if (GET_CODE (varop) == CLOBBER)
8932     return x ? x : varop;
8933
8934   new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8935   if (new != 0)
8936     x = new;
8937   else
8938     {
8939       if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8940         x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8941
8942       SUBST (XEXP (x, 0), varop);
8943       SUBST (XEXP (x, 1), const_rtx);
8944     }
8945
8946   /* If we have an outer operation and we just made a shift, it is
8947      possible that we could have simplified the shift were it not
8948      for the outer operation.  So try to do the simplification
8949      recursively.  */
8950
8951   if (outer_op != NIL && GET_CODE (x) == code
8952       && GET_CODE (XEXP (x, 1)) == CONST_INT)
8953     x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8954                               INTVAL (XEXP (x, 1)));
8955
8956   /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8957      turn off all the bits that the shift would have turned off.  */
8958   if (orig_code == LSHIFTRT && result_mode != shift_mode)
8959     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8960                                 GET_MODE_MASK (result_mode) >> orig_count);
8961
8962   /* Do the remainder of the processing in RESULT_MODE.  */
8963   x = gen_lowpart_for_combine (result_mode, x);
8964
8965   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8966      operation.  */
8967   if (complement_p)
8968     x = gen_unary (NOT, result_mode, result_mode, x);
8969
8970   if (outer_op != NIL)
8971     {
8972       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8973         {
8974           int width = GET_MODE_BITSIZE (result_mode);
8975
8976           outer_const &= GET_MODE_MASK (result_mode);
8977
8978           /* If this would be an entire word for the target, but is not for
8979              the host, then sign-extend on the host so that the number will
8980              look the same way on the host that it would on the target.
8981
8982              For example, when building a 64 bit alpha hosted 32 bit sparc
8983              targeted compiler, then we want the 32 bit unsigned value -1 to be
8984              represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8985              The later confuses the sparc backend.  */
8986
8987           if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8988               && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8989             outer_const |= ((HOST_WIDE_INT) (-1) << width);
8990         }
8991
8992       if (outer_op == AND)
8993         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8994       else if (outer_op == SET)
8995         /* This means that we have determined that the result is
8996            equivalent to a constant.  This should be rare.  */
8997         x = GEN_INT (outer_const);
8998       else if (GET_RTX_CLASS (outer_op) == '1')
8999         x = gen_unary (outer_op, result_mode, result_mode, x);
9000       else
9001         x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9002     }
9003
9004   return x;
9005 }
9006 \f
9007 /* Like recog, but we receive the address of a pointer to a new pattern.
9008    We try to match the rtx that the pointer points to.
9009    If that fails, we may try to modify or replace the pattern,
9010    storing the replacement into the same pointer object.
9011
9012    Modifications include deletion or addition of CLOBBERs.
9013
9014    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9015    the CLOBBERs are placed.
9016
9017    PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
9018    we had to add.
9019
9020    The value is the final insn code from the pattern ultimately matched,
9021    or -1.  */
9022
9023 static int
9024 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
9025      rtx *pnewpat;
9026      rtx insn;
9027      rtx *pnotes;
9028      int *padded_scratches;
9029 {
9030   register rtx pat = *pnewpat;
9031   int insn_code_number;
9032   int num_clobbers_to_add = 0;
9033   int i;
9034   rtx notes = 0;
9035
9036   *padded_scratches = 0;
9037
9038   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9039      we use to indicate that something didn't match.  If we find such a
9040      thing, force rejection.  */
9041   if (GET_CODE (pat) == PARALLEL)
9042     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9043       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9044           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9045         return -1;
9046
9047   /* Is the result of combination a valid instruction?  */
9048   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9049
9050   /* If it isn't, there is the possibility that we previously had an insn
9051      that clobbered some register as a side effect, but the combined
9052      insn doesn't need to do that.  So try once more without the clobbers
9053      unless this represents an ASM insn.  */
9054
9055   if (insn_code_number < 0 && ! check_asm_operands (pat)
9056       && GET_CODE (pat) == PARALLEL)
9057     {
9058       int pos;
9059
9060       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9061         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9062           {
9063             if (i != pos)
9064               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9065             pos++;
9066           }
9067
9068       SUBST_INT (XVECLEN (pat, 0), pos);
9069
9070       if (pos == 1)
9071         pat = XVECEXP (pat, 0, 0);
9072
9073       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9074     }
9075
9076   /* If we had any clobbers to add, make a new pattern than contains
9077      them.  Then check to make sure that all of them are dead.  */
9078   if (num_clobbers_to_add)
9079     {
9080       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9081                                      gen_rtvec (GET_CODE (pat) == PARALLEL
9082                                                 ? XVECLEN (pat, 0) + num_clobbers_to_add
9083                                                 : num_clobbers_to_add + 1));
9084
9085       if (GET_CODE (pat) == PARALLEL)
9086         for (i = 0; i < XVECLEN (pat, 0); i++)
9087           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9088       else
9089         XVECEXP (newpat, 0, 0) = pat;
9090
9091       add_clobbers (newpat, insn_code_number);
9092
9093       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9094            i < XVECLEN (newpat, 0); i++)
9095         {
9096           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9097               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9098             return -1;
9099           else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
9100             (*padded_scratches)++;
9101           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9102                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9103         }
9104       pat = newpat;
9105     }
9106
9107   *pnewpat = pat;
9108   *pnotes = notes;
9109
9110   return insn_code_number;
9111 }
9112 \f
9113 /* Like gen_lowpart but for use by combine.  In combine it is not possible
9114    to create any new pseudoregs.  However, it is safe to create
9115    invalid memory addresses, because combine will try to recognize
9116    them and all they will do is make the combine attempt fail.
9117
9118    If for some reason this cannot do its job, an rtx
9119    (clobber (const_int 0)) is returned.
9120    An insn containing that will not be recognized.  */
9121
9122 #undef gen_lowpart
9123
9124 static rtx
9125 gen_lowpart_for_combine (mode, x)
9126      enum machine_mode mode;
9127      register rtx x;
9128 {
9129   rtx result;
9130
9131   if (GET_MODE (x) == mode)
9132     return x;
9133
9134   /* We can only support MODE being wider than a word if X is a
9135      constant integer or has a mode the same size.  */
9136
9137   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9138       && ! ((GET_MODE (x) == VOIDmode
9139              && (GET_CODE (x) == CONST_INT
9140                  || GET_CODE (x) == CONST_DOUBLE))
9141             || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9142     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9143
9144   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9145      won't know what to do.  So we will strip off the SUBREG here and
9146      process normally.  */
9147   if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9148     {
9149       x = SUBREG_REG (x);
9150       if (GET_MODE (x) == mode)
9151         return x;
9152     }
9153
9154   result = gen_lowpart_common (mode, x);
9155   if (result != 0
9156       && GET_CODE (result) == SUBREG
9157       && GET_CODE (SUBREG_REG (result)) == REG
9158       && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9159       && (GET_MODE_SIZE (GET_MODE (result))
9160           != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9161     REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9162
9163   if (result)
9164     return result;
9165
9166   if (GET_CODE (x) == MEM)
9167     {
9168       register int offset = 0;
9169       rtx new;
9170
9171       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9172          address.  */
9173       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9174         return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9175
9176       /* If we want to refer to something bigger than the original memref,
9177          generate a perverse subreg instead.  That will force a reload
9178          of the original memref X.  */
9179       if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9180         return gen_rtx_SUBREG (mode, x, 0);
9181
9182       if (WORDS_BIG_ENDIAN)
9183         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9184                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9185       if (BYTES_BIG_ENDIAN)
9186         {
9187           /* Adjust the address so that the address-after-the-data is
9188              unchanged.  */
9189           offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9190                      - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9191         }
9192       new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9193       RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9194       MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9195       MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9196       return new;
9197     }
9198
9199   /* If X is a comparison operator, rewrite it in a new mode.  This
9200      probably won't match, but may allow further simplifications.  */
9201   else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9202     return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9203
9204   /* If we couldn't simplify X any other way, just enclose it in a
9205      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9206      include an explicit SUBREG or we may simplify it further in combine.  */
9207   else
9208     {
9209       int word = 0;
9210
9211       if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9212         word = ((GET_MODE_SIZE (GET_MODE (x))
9213                  - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9214                 / UNITS_PER_WORD);
9215       return gen_rtx_SUBREG (mode, x, word);
9216     }
9217 }
9218 \f
9219 /* Make an rtx expression.  This is a subset of gen_rtx and only supports
9220    expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9221
9222    If the identical expression was previously in the insn (in the undobuf),
9223    it will be returned.  Only if it is not found will a new expression
9224    be made.  */
9225
9226 /*VARARGS2*/
9227 static rtx
9228 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9229 {
9230 #ifndef __STDC__
9231   enum rtx_code code;
9232   enum machine_mode mode;
9233 #endif
9234   va_list p;
9235   int n_args;
9236   rtx args[3];
9237   int j;
9238   char *fmt;
9239   rtx rt;
9240   struct undo *undo;
9241
9242   VA_START (p, mode);
9243
9244 #ifndef __STDC__
9245   code = va_arg (p, enum rtx_code);
9246   mode = va_arg (p, enum machine_mode);
9247 #endif
9248
9249   n_args = GET_RTX_LENGTH (code);
9250   fmt = GET_RTX_FORMAT (code);
9251
9252   if (n_args == 0 || n_args > 3)
9253     abort ();
9254
9255   /* Get each arg and verify that it is supposed to be an expression.  */
9256   for (j = 0; j < n_args; j++)
9257     {
9258       if (*fmt++ != 'e')
9259         abort ();
9260
9261       args[j] = va_arg (p, rtx);
9262     }
9263
9264   /* See if this is in undobuf.  Be sure we don't use objects that came
9265      from another insn; this could produce circular rtl structures.  */
9266
9267   for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9268     if (!undo->is_int
9269         && GET_CODE (undo->old_contents.r) == code
9270         && GET_MODE (undo->old_contents.r) == mode)
9271       {
9272         for (j = 0; j < n_args; j++)
9273           if (XEXP (undo->old_contents.r, j) != args[j])
9274             break;
9275
9276         if (j == n_args)
9277           return undo->old_contents.r;
9278       }
9279
9280   /* Otherwise make a new rtx.  We know we have 1, 2, or 3 args.
9281      Use rtx_alloc instead of gen_rtx because it's faster on RISC.  */
9282   rt = rtx_alloc (code);
9283   PUT_MODE (rt, mode);
9284   XEXP (rt, 0) = args[0];
9285   if (n_args > 1)
9286     {
9287       XEXP (rt, 1) = args[1];
9288       if (n_args > 2)
9289         XEXP (rt, 2) = args[2];
9290     }
9291   return rt;
9292 }
9293
9294 /* These routines make binary and unary operations by first seeing if they
9295    fold; if not, a new expression is allocated.  */
9296
9297 static rtx
9298 gen_binary (code, mode, op0, op1)
9299      enum rtx_code code;
9300      enum machine_mode mode;
9301      rtx op0, op1;
9302 {
9303   rtx result;
9304   rtx tem;
9305
9306   if (GET_RTX_CLASS (code) == 'c'
9307       && (GET_CODE (op0) == CONST_INT
9308           || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9309     tem = op0, op0 = op1, op1 = tem;
9310
9311   if (GET_RTX_CLASS (code) == '<')
9312     {
9313       enum machine_mode op_mode = GET_MODE (op0);
9314
9315       /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9316          just (REL_OP X Y).  */
9317       if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9318         {
9319           op1 = XEXP (op0, 1);
9320           op0 = XEXP (op0, 0);
9321           op_mode = GET_MODE (op0);
9322         }
9323
9324       if (op_mode == VOIDmode)
9325         op_mode = GET_MODE (op1);
9326       result = simplify_relational_operation (code, op_mode, op0, op1);
9327     }
9328   else
9329     result = simplify_binary_operation (code, mode, op0, op1);
9330
9331   if (result)
9332     return result;
9333
9334   /* Put complex operands first and constants second.  */
9335   if (GET_RTX_CLASS (code) == 'c'
9336       && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9337           || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9338               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9339           || (GET_CODE (op0) == SUBREG
9340               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9341               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9342     return gen_rtx_combine (code, mode, op1, op0);
9343
9344   /* If we are turning off bits already known off in OP0, we need not do
9345      an AND.  */
9346   else if (code == AND && GET_CODE (op1) == CONST_INT
9347            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9348            && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9349     return op0;
9350
9351   return gen_rtx_combine (code, mode, op0, op1);
9352 }
9353
9354 static rtx
9355 gen_unary (code, mode, op0_mode, op0)
9356      enum rtx_code code;
9357      enum machine_mode mode, op0_mode;
9358      rtx op0;
9359 {
9360   rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9361
9362   if (result)
9363     return result;
9364
9365   return gen_rtx_combine (code, mode, op0);
9366 }
9367 \f
9368 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9369    comparison code that will be tested.
9370
9371    The result is a possibly different comparison code to use.  *POP0 and
9372    *POP1 may be updated.
9373
9374    It is possible that we might detect that a comparison is either always
9375    true or always false.  However, we do not perform general constant
9376    folding in combine, so this knowledge isn't useful.  Such tautologies
9377    should have been detected earlier.  Hence we ignore all such cases.  */
9378
9379 static enum rtx_code
9380 simplify_comparison (code, pop0, pop1)
9381      enum rtx_code code;
9382      rtx *pop0;
9383      rtx *pop1;
9384 {
9385   rtx op0 = *pop0;
9386   rtx op1 = *pop1;
9387   rtx tem, tem1;
9388   int i;
9389   enum machine_mode mode, tmode;
9390
9391   /* Try a few ways of applying the same transformation to both operands.  */
9392   while (1)
9393     {
9394 #ifndef WORD_REGISTER_OPERATIONS
9395       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9396          so check specially.  */
9397       if (code != GTU && code != GEU && code != LTU && code != LEU
9398           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9399           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9400           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9401           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9402           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9403           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9404               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9405           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9406           && GET_CODE (XEXP (op1, 1)) == CONST_INT
9407           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9408           && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9409           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9410           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9411           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9412           && (INTVAL (XEXP (op0, 1))
9413               == (GET_MODE_BITSIZE (GET_MODE (op0))
9414                   - (GET_MODE_BITSIZE
9415                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9416         {
9417           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9418           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9419         }
9420 #endif
9421
9422       /* If both operands are the same constant shift, see if we can ignore the
9423          shift.  We can if the shift is a rotate or if the bits shifted out of
9424          this shift are known to be zero for both inputs and if the type of
9425          comparison is compatible with the shift.  */
9426       if (GET_CODE (op0) == GET_CODE (op1)
9427           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9428           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9429               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9430                   && (code != GT && code != LT && code != GE && code != LE))
9431               || (GET_CODE (op0) == ASHIFTRT
9432                   && (code != GTU && code != LTU
9433                       && code != GEU && code != GEU)))
9434           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9435           && INTVAL (XEXP (op0, 1)) >= 0
9436           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9437           && XEXP (op0, 1) == XEXP (op1, 1))
9438         {
9439           enum machine_mode mode = GET_MODE (op0);
9440           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9441           int shift_count = INTVAL (XEXP (op0, 1));
9442
9443           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9444             mask &= (mask >> shift_count) << shift_count;
9445           else if (GET_CODE (op0) == ASHIFT)
9446             mask = (mask & (mask << shift_count)) >> shift_count;
9447
9448           if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9449               && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9450             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9451           else
9452             break;
9453         }
9454
9455       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9456          SUBREGs are of the same mode, and, in both cases, the AND would
9457          be redundant if the comparison was done in the narrower mode,
9458          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9459          and the operand's possibly nonzero bits are 0xffffff01; in that case
9460          if we only care about QImode, we don't need the AND).  This case
9461          occurs if the output mode of an scc insn is not SImode and
9462          STORE_FLAG_VALUE == 1 (e.g., the 386).
9463
9464          Similarly, check for a case where the AND's are ZERO_EXTEND
9465          operations from some narrower mode even though a SUBREG is not
9466          present.  */
9467
9468       else if  (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9469                 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9470                 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9471         {
9472           rtx inner_op0 = XEXP (op0, 0);
9473           rtx inner_op1 = XEXP (op1, 0);
9474           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9475           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9476           int changed = 0;
9477
9478           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9479               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9480                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9481               && (GET_MODE (SUBREG_REG (inner_op0))
9482                   == GET_MODE (SUBREG_REG (inner_op1)))
9483               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9484                   <= HOST_BITS_PER_WIDE_INT)
9485               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9486                                              GET_MODE (SUBREG_REG (op0)))))
9487               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9488                                              GET_MODE (SUBREG_REG (inner_op1))))))
9489             {
9490               op0 = SUBREG_REG (inner_op0);
9491               op1 = SUBREG_REG (inner_op1);
9492
9493               /* The resulting comparison is always unsigned since we masked
9494                  off the original sign bit.  */
9495               code = unsigned_condition (code);
9496
9497               changed = 1;
9498             }
9499
9500           else if (c0 == c1)
9501             for (tmode = GET_CLASS_NARROWEST_MODE
9502                  (GET_MODE_CLASS (GET_MODE (op0)));
9503                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9504               if (c0 == GET_MODE_MASK (tmode))
9505                 {
9506                   op0 = gen_lowpart_for_combine (tmode, inner_op0);
9507                   op1 = gen_lowpart_for_combine (tmode, inner_op1);
9508                   code = unsigned_condition (code);
9509                   changed = 1;
9510                   break;
9511                 }
9512
9513           if (! changed)
9514             break;
9515         }
9516
9517       /* If both operands are NOT, we can strip off the outer operation
9518          and adjust the comparison code for swapped operands; similarly for
9519          NEG, except that this must be an equality comparison.  */
9520       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9521                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9522                    && (code == EQ || code == NE)))
9523         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9524
9525       else
9526         break;
9527     }
9528
9529   /* If the first operand is a constant, swap the operands and adjust the
9530      comparison code appropriately, but don't do this if the second operand
9531      is already a constant integer.  */
9532   if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9533     {
9534       tem = op0, op0 = op1, op1 = tem;
9535       code = swap_condition (code);
9536     }
9537
9538   /* We now enter a loop during which we will try to simplify the comparison.
9539      For the most part, we only are concerned with comparisons with zero,
9540      but some things may really be comparisons with zero but not start
9541      out looking that way.  */
9542
9543   while (GET_CODE (op1) == CONST_INT)
9544     {
9545       enum machine_mode mode = GET_MODE (op0);
9546       int mode_width = GET_MODE_BITSIZE (mode);
9547       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9548       int equality_comparison_p;
9549       int sign_bit_comparison_p;
9550       int unsigned_comparison_p;
9551       HOST_WIDE_INT const_op;
9552
9553       /* We only want to handle integral modes.  This catches VOIDmode,
9554          CCmode, and the floating-point modes.  An exception is that we
9555          can handle VOIDmode if OP0 is a COMPARE or a comparison
9556          operation.  */
9557
9558       if (GET_MODE_CLASS (mode) != MODE_INT
9559           && ! (mode == VOIDmode
9560                 && (GET_CODE (op0) == COMPARE
9561                     || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9562         break;
9563
9564       /* Get the constant we are comparing against and turn off all bits
9565          not on in our mode.  */
9566       const_op = INTVAL (op1);
9567       if (mode_width <= HOST_BITS_PER_WIDE_INT)
9568         const_op &= mask;
9569
9570       /* If we are comparing against a constant power of two and the value
9571          being compared can only have that single bit nonzero (e.g., it was
9572          `and'ed with that bit), we can replace this with a comparison
9573          with zero.  */
9574       if (const_op
9575           && (code == EQ || code == NE || code == GE || code == GEU
9576               || code == LT || code == LTU)
9577           && mode_width <= HOST_BITS_PER_WIDE_INT
9578           && exact_log2 (const_op) >= 0
9579           && nonzero_bits (op0, mode) == const_op)
9580         {
9581           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9582           op1 = const0_rtx, const_op = 0;
9583         }
9584
9585       /* Similarly, if we are comparing a value known to be either -1 or
9586          0 with -1, change it to the opposite comparison against zero.  */
9587
9588       if (const_op == -1
9589           && (code == EQ || code == NE || code == GT || code == LE
9590               || code == GEU || code == LTU)
9591           && num_sign_bit_copies (op0, mode) == mode_width)
9592         {
9593           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9594           op1 = const0_rtx, const_op = 0;
9595         }
9596
9597       /* Do some canonicalizations based on the comparison code.  We prefer
9598          comparisons against zero and then prefer equality comparisons.
9599          If we can reduce the size of a constant, we will do that too.  */
9600
9601       switch (code)
9602         {
9603         case LT:
9604           /* < C is equivalent to <= (C - 1) */
9605           if (const_op > 0)
9606             {
9607               const_op -= 1;
9608               op1 = GEN_INT (const_op);
9609               code = LE;
9610               /* ... fall through to LE case below.  */
9611             }
9612           else
9613             break;
9614
9615         case LE:
9616           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9617           if (const_op < 0)
9618             {
9619               const_op += 1;
9620               op1 = GEN_INT (const_op);
9621               code = LT;
9622             }
9623
9624           /* If we are doing a <= 0 comparison on a value known to have
9625              a zero sign bit, we can replace this with == 0.  */
9626           else if (const_op == 0
9627                    && mode_width <= HOST_BITS_PER_WIDE_INT
9628                    && (nonzero_bits (op0, mode)
9629                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9630             code = EQ;
9631           break;
9632
9633         case GE:
9634           /* >= C is equivalent to > (C - 1).  */
9635           if (const_op > 0)
9636             {
9637               const_op -= 1;
9638               op1 = GEN_INT (const_op);
9639               code = GT;
9640               /* ... fall through to GT below.  */
9641             }
9642           else
9643             break;
9644
9645         case GT:
9646           /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9647           if (const_op < 0)
9648             {
9649               const_op += 1;
9650               op1 = GEN_INT (const_op);
9651               code = GE;
9652             }
9653
9654           /* If we are doing a > 0 comparison on a value known to have
9655              a zero sign bit, we can replace this with != 0.  */
9656           else if (const_op == 0
9657                    && mode_width <= HOST_BITS_PER_WIDE_INT
9658                    && (nonzero_bits (op0, mode)
9659                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9660             code = NE;
9661           break;
9662
9663         case LTU:
9664           /* < C is equivalent to <= (C - 1).  */
9665           if (const_op > 0)
9666             {
9667               const_op -= 1;
9668               op1 = GEN_INT (const_op);
9669               code = LEU;
9670               /* ... fall through ...  */
9671             }
9672
9673           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9674           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9675                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9676             {
9677               const_op = 0, op1 = const0_rtx;
9678               code = GE;
9679               break;
9680             }
9681           else
9682             break;
9683
9684         case LEU:
9685           /* unsigned <= 0 is equivalent to == 0 */
9686           if (const_op == 0)
9687             code = EQ;
9688
9689           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9690           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9691                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9692             {
9693               const_op = 0, op1 = const0_rtx;
9694               code = GE;
9695             }
9696           break;
9697
9698         case GEU:
9699           /* >= C is equivalent to < (C - 1).  */
9700           if (const_op > 1)
9701             {
9702               const_op -= 1;
9703               op1 = GEN_INT (const_op);
9704               code = GTU;
9705               /* ... fall through ...  */
9706             }
9707
9708           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9709           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9710                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9711             {
9712               const_op = 0, op1 = const0_rtx;
9713               code = LT;
9714               break;
9715             }
9716           else
9717             break;
9718
9719         case GTU:
9720           /* unsigned > 0 is equivalent to != 0 */
9721           if (const_op == 0)
9722             code = NE;
9723
9724           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9725           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9726                     && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9727             {
9728               const_op = 0, op1 = const0_rtx;
9729               code = LT;
9730             }
9731           break;
9732
9733         default:
9734           break;
9735         }
9736
9737       /* Compute some predicates to simplify code below.  */
9738
9739       equality_comparison_p = (code == EQ || code == NE);
9740       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9741       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9742                                || code == LEU);
9743
9744       /* If this is a sign bit comparison and we can do arithmetic in
9745          MODE, say that we will only be needing the sign bit of OP0.  */
9746       if (sign_bit_comparison_p
9747           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9748         op0 = force_to_mode (op0, mode,
9749                              ((HOST_WIDE_INT) 1
9750                               << (GET_MODE_BITSIZE (mode) - 1)),
9751                              NULL_RTX, 0);
9752
9753       /* Now try cases based on the opcode of OP0.  If none of the cases
9754          does a "continue", we exit this loop immediately after the
9755          switch.  */
9756
9757       switch (GET_CODE (op0))
9758         {
9759         case ZERO_EXTRACT:
9760           /* If we are extracting a single bit from a variable position in
9761              a constant that has only a single bit set and are comparing it
9762              with zero, we can convert this into an equality comparison
9763              between the position and the location of the single bit.  */
9764
9765           if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9766               && XEXP (op0, 1) == const1_rtx
9767               && equality_comparison_p && const_op == 0
9768               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9769             {
9770               if (BITS_BIG_ENDIAN)
9771 #ifdef HAVE_extzv
9772                 i = (GET_MODE_BITSIZE
9773                      (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9774 #else
9775                 i = BITS_PER_WORD - 1 - i;
9776 #endif
9777
9778               op0 = XEXP (op0, 2);
9779               op1 = GEN_INT (i);
9780               const_op = i;
9781
9782               /* Result is nonzero iff shift count is equal to I.  */
9783               code = reverse_condition (code);
9784               continue;
9785             }
9786
9787           /* ... fall through ...  */
9788
9789         case SIGN_EXTRACT:
9790           tem = expand_compound_operation (op0);
9791           if (tem != op0)
9792             {
9793               op0 = tem;
9794               continue;
9795             }
9796           break;
9797
9798         case NOT:
9799           /* If testing for equality, we can take the NOT of the constant.  */
9800           if (equality_comparison_p
9801               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9802             {
9803               op0 = XEXP (op0, 0);
9804               op1 = tem;
9805               continue;
9806             }
9807
9808           /* If just looking at the sign bit, reverse the sense of the
9809              comparison.  */
9810           if (sign_bit_comparison_p)
9811             {
9812               op0 = XEXP (op0, 0);
9813               code = (code == GE ? LT : GE);
9814               continue;
9815             }
9816           break;
9817
9818         case NEG:
9819           /* If testing for equality, we can take the NEG of the constant.  */
9820           if (equality_comparison_p
9821               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9822             {
9823               op0 = XEXP (op0, 0);
9824               op1 = tem;
9825               continue;
9826             }
9827
9828           /* The remaining cases only apply to comparisons with zero.  */
9829           if (const_op != 0)
9830             break;
9831
9832           /* When X is ABS or is known positive,
9833              (neg X) is < 0 if and only if X != 0.  */
9834
9835           if (sign_bit_comparison_p
9836               && (GET_CODE (XEXP (op0, 0)) == ABS
9837                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9838                       && (nonzero_bits (XEXP (op0, 0), mode)
9839                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9840             {
9841               op0 = XEXP (op0, 0);
9842               code = (code == LT ? NE : EQ);
9843               continue;
9844             }
9845
9846           /* If we have NEG of something whose two high-order bits are the
9847              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9848           if (num_sign_bit_copies (op0, mode) >= 2)
9849             {
9850               op0 = XEXP (op0, 0);
9851               code = swap_condition (code);
9852               continue;
9853             }
9854           break;
9855
9856         case ROTATE:
9857           /* If we are testing equality and our count is a constant, we
9858              can perform the inverse operation on our RHS.  */
9859           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9860               && (tem = simplify_binary_operation (ROTATERT, mode,
9861                                                    op1, XEXP (op0, 1))) != 0)
9862             {
9863               op0 = XEXP (op0, 0);
9864               op1 = tem;
9865               continue;
9866             }
9867
9868           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9869              a particular bit.  Convert it to an AND of a constant of that
9870              bit.  This will be converted into a ZERO_EXTRACT.  */
9871           if (const_op == 0 && sign_bit_comparison_p
9872               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9873               && mode_width <= HOST_BITS_PER_WIDE_INT)
9874             {
9875               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9876                                             ((HOST_WIDE_INT) 1
9877                                              << (mode_width - 1
9878                                                  - INTVAL (XEXP (op0, 1)))));
9879               code = (code == LT ? NE : EQ);
9880               continue;
9881             }
9882
9883           /* ... fall through ...  */
9884
9885         case ABS:
9886           /* ABS is ignorable inside an equality comparison with zero.  */
9887           if (const_op == 0 && equality_comparison_p)
9888             {
9889               op0 = XEXP (op0, 0);
9890               continue;
9891             }
9892           break;
9893
9894
9895         case SIGN_EXTEND:
9896           /* Can simplify (compare (zero/sign_extend FOO) CONST)
9897              to (compare FOO CONST) if CONST fits in FOO's mode and we
9898              are either testing inequality or have an unsigned comparison
9899              with ZERO_EXTEND or a signed comparison with SIGN_EXTEND.  */
9900           if (! unsigned_comparison_p
9901               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9902                   <= HOST_BITS_PER_WIDE_INT)
9903               && ((unsigned HOST_WIDE_INT) const_op
9904                   < (((HOST_WIDE_INT) 1
9905                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9906             {
9907               op0 = XEXP (op0, 0);
9908               continue;
9909             }
9910           break;
9911
9912         case SUBREG:
9913           /* Check for the case where we are comparing A - C1 with C2,
9914              both constants are smaller than 1/2 the maximum positive
9915              value in MODE, and the comparison is equality or unsigned.
9916              In that case, if A is either zero-extended to MODE or has
9917              sufficient sign bits so that the high-order bit in MODE
9918              is a copy of the sign in the inner mode, we can prove that it is
9919              safe to do the operation in the wider mode.  This simplifies
9920              many range checks.  */
9921
9922           if (mode_width <= HOST_BITS_PER_WIDE_INT
9923               && subreg_lowpart_p (op0)
9924               && GET_CODE (SUBREG_REG (op0)) == PLUS
9925               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9926               && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9927               && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9928                   < GET_MODE_MASK (mode) / 2)
9929               && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9930               && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9931                                       GET_MODE (SUBREG_REG (op0)))
9932                         & ~ GET_MODE_MASK (mode))
9933                   || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9934                                            GET_MODE (SUBREG_REG (op0)))
9935                       > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9936                          - GET_MODE_BITSIZE (mode)))))
9937             {
9938               op0 = SUBREG_REG (op0);
9939               continue;
9940             }
9941
9942           /* If the inner mode is narrower and we are extracting the low part,
9943              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
9944           if (subreg_lowpart_p (op0)
9945               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9946             /* Fall through */ ;
9947           else
9948             break;
9949
9950           /* ... fall through ...  */
9951
9952         case ZERO_EXTEND:
9953           if ((unsigned_comparison_p || equality_comparison_p)
9954               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9955                   <= HOST_BITS_PER_WIDE_INT)
9956               && ((unsigned HOST_WIDE_INT) const_op
9957                   < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9958             {
9959               op0 = XEXP (op0, 0);
9960               continue;
9961             }
9962           break;
9963
9964         case PLUS:
9965           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
9966              this for equality comparisons due to pathological cases involving
9967              overflows.  */
9968           if (equality_comparison_p
9969               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9970                                                         op1, XEXP (op0, 1))))
9971             {
9972               op0 = XEXP (op0, 0);
9973               op1 = tem;
9974               continue;
9975             }
9976
9977           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
9978           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9979               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9980             {
9981               op0 = XEXP (XEXP (op0, 0), 0);
9982               code = (code == LT ? EQ : NE);
9983               continue;
9984             }
9985           break;
9986
9987         case MINUS:
9988           /* (eq (minus A B) C) -> (eq A (plus B C)) or
9989              (eq B (minus A C)), whichever simplifies.  We can only do
9990              this for equality comparisons due to pathological cases involving
9991              overflows.  */
9992           if (equality_comparison_p
9993               && 0 != (tem = simplify_binary_operation (PLUS, mode,
9994                                                         XEXP (op0, 1), op1)))
9995             {
9996               op0 = XEXP (op0, 0);
9997               op1 = tem;
9998               continue;
9999             }
10000
10001           if (equality_comparison_p
10002               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10003                                                         XEXP (op0, 0), op1)))
10004             {
10005               op0 = XEXP (op0, 1);
10006               op1 = tem;
10007               continue;
10008             }
10009
10010           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10011              of bits in X minus 1, is one iff X > 0.  */
10012           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10013               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10014               && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10015               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10016             {
10017               op0 = XEXP (op0, 1);
10018               code = (code == GE ? LE : GT);
10019               continue;
10020             }
10021           break;
10022
10023         case XOR:
10024           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10025              if C is zero or B is a constant.  */
10026           if (equality_comparison_p
10027               && 0 != (tem = simplify_binary_operation (XOR, mode,
10028                                                         XEXP (op0, 1), op1)))
10029             {
10030               op0 = XEXP (op0, 0);
10031               op1 = tem;
10032               continue;
10033             }
10034           break;
10035
10036         case EQ:  case NE:
10037         case LT:  case LTU:  case LE:  case LEU:
10038         case GT:  case GTU:  case GE:  case GEU:
10039           /* We can't do anything if OP0 is a condition code value, rather
10040              than an actual data value.  */
10041           if (const_op != 0
10042 #ifdef HAVE_cc0
10043               || XEXP (op0, 0) == cc0_rtx
10044 #endif
10045               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10046             break;
10047
10048           /* Get the two operands being compared.  */
10049           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10050             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10051           else
10052             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10053
10054           /* Check for the cases where we simply want the result of the
10055              earlier test or the opposite of that result.  */
10056           if (code == NE
10057               || (code == EQ && reversible_comparison_p (op0))
10058               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10059                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10060                   && (STORE_FLAG_VALUE
10061                       & (((HOST_WIDE_INT) 1
10062                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10063                   && (code == LT
10064                       || (code == GE && reversible_comparison_p (op0)))))
10065             {
10066               code = (code == LT || code == NE
10067                       ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10068               op0 = tem, op1 = tem1;
10069               continue;
10070             }
10071           break;
10072
10073         case IOR:
10074           /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10075              iff X <= 0.  */
10076           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10077               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10078               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10079             {
10080               op0 = XEXP (op0, 1);
10081               code = (code == GE ? GT : LE);
10082               continue;
10083             }
10084           break;
10085
10086         case AND:
10087           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10088              will be converted to a ZERO_EXTRACT later.  */
10089           if (const_op == 0 && equality_comparison_p
10090               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10091               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10092             {
10093               op0 = simplify_and_const_int
10094                 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10095                                              XEXP (op0, 1),
10096                                              XEXP (XEXP (op0, 0), 1)),
10097                  (HOST_WIDE_INT) 1);
10098               continue;
10099             }
10100
10101           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10102              zero and X is a comparison and C1 and C2 describe only bits set
10103              in STORE_FLAG_VALUE, we can compare with X.  */
10104           if (const_op == 0 && equality_comparison_p
10105               && mode_width <= HOST_BITS_PER_WIDE_INT
10106               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10107               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10108               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10109               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10110               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10111             {
10112               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10113                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10114               if ((~ STORE_FLAG_VALUE & mask) == 0
10115                   && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10116                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10117                           && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10118                 {
10119                   op0 = XEXP (XEXP (op0, 0), 0);
10120                   continue;
10121                 }
10122             }
10123
10124           /* If we are doing an equality comparison of an AND of a bit equal
10125              to the sign bit, replace this with a LT or GE comparison of
10126              the underlying value.  */
10127           if (equality_comparison_p
10128               && const_op == 0
10129               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10130               && mode_width <= HOST_BITS_PER_WIDE_INT
10131               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10132                   == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10133             {
10134               op0 = XEXP (op0, 0);
10135               code = (code == EQ ? GE : LT);
10136               continue;
10137             }
10138
10139           /* If this AND operation is really a ZERO_EXTEND from a narrower
10140              mode, the constant fits within that mode, and this is either an
10141              equality or unsigned comparison, try to do this comparison in
10142              the narrower mode.  */
10143           if ((equality_comparison_p || unsigned_comparison_p)
10144               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10145               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10146                                    & GET_MODE_MASK (mode))
10147                                   + 1)) >= 0
10148               && const_op >> i == 0
10149               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10150             {
10151               op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10152               continue;
10153             }
10154
10155           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10156              in both M1 and M2 and the SUBREG is either paradoxical or
10157              represents the low part, permute the SUBREG and the AND and
10158              try again.  */
10159           if (GET_CODE (XEXP (op0, 0)) == SUBREG
10160               && ((mode_width
10161                    >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10162                   || subreg_lowpart_p (XEXP (op0, 0)))
10163               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10164               && mode_width <= HOST_BITS_PER_WIDE_INT
10165               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10166                   <= HOST_BITS_PER_WIDE_INT)
10167               && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10168               && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10169                        & INTVAL (XEXP (op0, 1))))
10170
10171             {
10172               op0
10173                 = gen_lowpart_for_combine
10174                   (mode,
10175                    gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10176                                SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10177               continue;
10178             }
10179
10180           break;
10181
10182         case ASHIFT:
10183           /* If we have (compare (ashift FOO N) (const_int C)) and
10184              the high order N bits of FOO (N+1 if an inequality comparison)
10185              are known to be zero, we can do this by comparing FOO with C
10186              shifted right N bits so long as the low-order N bits of C are
10187              zero.  */
10188           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10189               && INTVAL (XEXP (op0, 1)) >= 0
10190               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10191                   < HOST_BITS_PER_WIDE_INT)
10192               && ((const_op
10193                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10194               && mode_width <= HOST_BITS_PER_WIDE_INT
10195               && (nonzero_bits (XEXP (op0, 0), mode)
10196                   & ~ (mask >> (INTVAL (XEXP (op0, 1))
10197                                 + ! equality_comparison_p))) == 0)
10198             {
10199               const_op >>= INTVAL (XEXP (op0, 1));
10200               op1 = GEN_INT (const_op);
10201               op0 = XEXP (op0, 0);
10202               continue;
10203             }
10204
10205           /* If we are doing a sign bit comparison, it means we are testing
10206              a particular bit.  Convert it to the appropriate AND.  */
10207           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10208               && mode_width <= HOST_BITS_PER_WIDE_INT)
10209             {
10210               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10211                                             ((HOST_WIDE_INT) 1
10212                                              << (mode_width - 1
10213                                                  - INTVAL (XEXP (op0, 1)))));
10214               code = (code == LT ? NE : EQ);
10215               continue;
10216             }
10217
10218           /* If this an equality comparison with zero and we are shifting
10219              the low bit to the sign bit, we can convert this to an AND of the
10220              low-order bit.  */
10221           if (const_op == 0 && equality_comparison_p
10222               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10223               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10224             {
10225               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10226                                             (HOST_WIDE_INT) 1);
10227               continue;
10228             }
10229           break;
10230
10231         case ASHIFTRT:
10232           /* If this is an equality comparison with zero, we can do this
10233              as a logical shift, which might be much simpler.  */
10234           if (equality_comparison_p && const_op == 0
10235               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10236             {
10237               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10238                                           XEXP (op0, 0),
10239                                           INTVAL (XEXP (op0, 1)));
10240               continue;
10241             }
10242
10243           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10244              do the comparison in a narrower mode.  */
10245           if (! unsigned_comparison_p
10246               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10247               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10248               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10249               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10250                                          MODE_INT, 1)) != BLKmode
10251               && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10252                   || ((unsigned HOST_WIDE_INT) - const_op
10253                       <= GET_MODE_MASK (tmode))))
10254             {
10255               op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10256               continue;
10257             }
10258
10259           /* ... fall through ...  */
10260         case LSHIFTRT:
10261           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10262              the low order N bits of FOO are known to be zero, we can do this
10263              by comparing FOO with C shifted left N bits so long as no
10264              overflow occurs.  */
10265           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10266               && INTVAL (XEXP (op0, 1)) >= 0
10267               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10268               && mode_width <= HOST_BITS_PER_WIDE_INT
10269               && (nonzero_bits (XEXP (op0, 0), mode)
10270                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10271               && (const_op == 0
10272                   || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10273                       < mode_width)))
10274             {
10275               const_op <<= INTVAL (XEXP (op0, 1));
10276               op1 = GEN_INT (const_op);
10277               op0 = XEXP (op0, 0);
10278               continue;
10279             }
10280
10281           /* If we are using this shift to extract just the sign bit, we
10282              can replace this with an LT or GE comparison.  */
10283           if (const_op == 0
10284               && (equality_comparison_p || sign_bit_comparison_p)
10285               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10286               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10287             {
10288               op0 = XEXP (op0, 0);
10289               code = (code == NE || code == GT ? LT : GE);
10290               continue;
10291             }
10292           break;
10293
10294         default:
10295           break;
10296         }
10297
10298       break;
10299     }
10300
10301   /* Now make any compound operations involved in this comparison.  Then,
10302      check for an outmost SUBREG on OP0 that is not doing anything or is
10303      paradoxical.  The latter case can only occur when it is known that the
10304      "extra" bits will be zero.  Therefore, it is safe to remove the SUBREG.
10305      We can never remove a SUBREG for a non-equality comparison because the
10306      sign bit is in a different place in the underlying object.  */
10307
10308   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10309   op1 = make_compound_operation (op1, SET);
10310
10311   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10312       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10313       && (code == NE || code == EQ)
10314       && ((GET_MODE_SIZE (GET_MODE (op0))
10315            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10316     {
10317       op0 = SUBREG_REG (op0);
10318       op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10319     }
10320
10321   else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10322            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10323            && (code == NE || code == EQ)
10324            && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10325                <= HOST_BITS_PER_WIDE_INT)
10326            && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10327                & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10328            && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10329                                               op1),
10330                (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10331                 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10332     op0 = SUBREG_REG (op0), op1 = tem;
10333
10334   /* We now do the opposite procedure: Some machines don't have compare
10335      insns in all modes.  If OP0's mode is an integer mode smaller than a
10336      word and we can't do a compare in that mode, see if there is a larger
10337      mode for which we can do the compare.  There are a number of cases in
10338      which we can use the wider mode.  */
10339
10340   mode = GET_MODE (op0);
10341   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10342       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10343       && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10344     for (tmode = GET_MODE_WIDER_MODE (mode);
10345          (tmode != VOIDmode
10346           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10347          tmode = GET_MODE_WIDER_MODE (tmode))
10348       if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10349         {
10350           /* If the only nonzero bits in OP0 and OP1 are those in the
10351              narrower mode and this is an equality or unsigned comparison,
10352              we can use the wider mode.  Similarly for sign-extended
10353              values, in which case it is true for all comparisons.  */
10354           if (((code == EQ || code == NE
10355                 || code == GEU || code == GTU || code == LEU || code == LTU)
10356                && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10357                && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10358               || ((num_sign_bit_copies (op0, tmode)
10359                    > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10360                   && (num_sign_bit_copies (op1, tmode)
10361                       > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10362             {
10363               op0 = gen_lowpart_for_combine (tmode, op0);
10364               op1 = gen_lowpart_for_combine (tmode, op1);
10365               break;
10366             }
10367
10368           /* If this is a test for negative, we can make an explicit
10369              test of the sign bit.  */
10370
10371           if (op1 == const0_rtx && (code == LT || code == GE)
10372               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10373             {
10374               op0 = gen_binary (AND, tmode,
10375                                 gen_lowpart_for_combine (tmode, op0),
10376                                 GEN_INT ((HOST_WIDE_INT) 1
10377                                          << (GET_MODE_BITSIZE (mode) - 1)));
10378               code = (code == LT) ? NE : EQ;
10379               break;
10380             }
10381         }
10382
10383 #ifdef CANONICALIZE_COMPARISON
10384   /* If this machine only supports a subset of valid comparisons, see if we
10385      can convert an unsupported one into a supported one.  */
10386   CANONICALIZE_COMPARISON (code, op0, op1);
10387 #endif
10388
10389   *pop0 = op0;
10390   *pop1 = op1;
10391
10392   return code;
10393 }
10394 \f
10395 /* Return 1 if we know that X, a comparison operation, is not operating
10396    on a floating-point value or is EQ or NE, meaning that we can safely
10397    reverse it.  */
10398
10399 static int
10400 reversible_comparison_p (x)
10401      rtx x;
10402 {
10403   if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10404       || flag_fast_math
10405       || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10406     return 1;
10407
10408   switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10409     {
10410     case MODE_INT:
10411     case MODE_PARTIAL_INT:
10412     case MODE_COMPLEX_INT:
10413       return 1;
10414
10415     case MODE_CC:
10416       /* If the mode of the condition codes tells us that this is safe,
10417          we need look no further.  */
10418       if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10419         return 1;
10420
10421       /* Otherwise try and find where the condition codes were last set and
10422          use that.  */
10423       x = get_last_value (XEXP (x, 0));
10424       return (x && GET_CODE (x) == COMPARE
10425               && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10426
10427     default:
10428       return 0;
10429     }
10430 }
10431 \f
10432 /* Utility function for following routine.  Called when X is part of a value
10433    being stored into reg_last_set_value.  Sets reg_last_set_table_tick
10434    for each register mentioned.  Similar to mention_regs in cse.c  */
10435
10436 static void
10437 update_table_tick (x)
10438      rtx x;
10439 {
10440   register enum rtx_code code = GET_CODE (x);
10441   register char *fmt = GET_RTX_FORMAT (code);
10442   register int i;
10443
10444   if (code == REG)
10445     {
10446       int regno = REGNO (x);
10447       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10448                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10449
10450       for (i = regno; i < endregno; i++)
10451         reg_last_set_table_tick[i] = label_tick;
10452
10453       return;
10454     }
10455
10456   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10457     /* Note that we can't have an "E" in values stored; see
10458        get_last_value_validate.  */
10459     if (fmt[i] == 'e')
10460       update_table_tick (XEXP (x, i));
10461 }
10462
10463 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10464    are saying that the register is clobbered and we no longer know its
10465    value.  If INSN is zero, don't update reg_last_set; this is only permitted
10466    with VALUE also zero and is used to invalidate the register.  */
10467
10468 static void
10469 record_value_for_reg (reg, insn, value)
10470      rtx reg;
10471      rtx insn;
10472      rtx value;
10473 {
10474   int regno = REGNO (reg);
10475   int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10476                           ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10477   int i;
10478
10479   /* If VALUE contains REG and we have a previous value for REG, substitute
10480      the previous value.  */
10481   if (value && insn && reg_overlap_mentioned_p (reg, value))
10482     {
10483       rtx tem;
10484
10485       /* Set things up so get_last_value is allowed to see anything set up to
10486          our insn.  */
10487       subst_low_cuid = INSN_CUID (insn);
10488       tem = get_last_value (reg);
10489
10490       if (tem)
10491         value = replace_rtx (copy_rtx (value), reg, tem);
10492     }
10493
10494   /* For each register modified, show we don't know its value, that
10495      we don't know about its bitwise content, that its value has been
10496      updated, and that we don't know the location of the death of the
10497      register.  */
10498   for (i = regno; i < endregno; i ++)
10499     {
10500       if (insn)
10501         reg_last_set[i] = insn;
10502       reg_last_set_value[i] = 0;
10503       reg_last_set_mode[i] = 0;
10504       reg_last_set_nonzero_bits[i] = 0;
10505       reg_last_set_sign_bit_copies[i] = 0;
10506       reg_last_death[i] = 0;
10507     }
10508
10509   /* Mark registers that are being referenced in this value.  */
10510   if (value)
10511     update_table_tick (value);
10512
10513   /* Now update the status of each register being set.
10514      If someone is using this register in this block, set this register
10515      to invalid since we will get confused between the two lives in this
10516      basic block.  This makes using this register always invalid.  In cse, we
10517      scan the table to invalidate all entries using this register, but this
10518      is too much work for us.  */
10519
10520   for (i = regno; i < endregno; i++)
10521     {
10522       reg_last_set_label[i] = label_tick;
10523       if (value && reg_last_set_table_tick[i] == label_tick)
10524         reg_last_set_invalid[i] = 1;
10525       else
10526         reg_last_set_invalid[i] = 0;
10527     }
10528
10529   /* The value being assigned might refer to X (like in "x++;").  In that
10530      case, we must replace it with (clobber (const_int 0)) to prevent
10531      infinite loops.  */
10532   if (value && ! get_last_value_validate (&value, insn,
10533                                           reg_last_set_label[regno], 0))
10534     {
10535       value = copy_rtx (value);
10536       if (! get_last_value_validate (&value, insn,
10537                                      reg_last_set_label[regno], 1))
10538         value = 0;
10539     }
10540
10541   /* For the main register being modified, update the value, the mode, the
10542      nonzero bits, and the number of sign bit copies.  */
10543
10544   reg_last_set_value[regno] = value;
10545
10546   if (value)
10547     {
10548       subst_low_cuid = INSN_CUID (insn);
10549       reg_last_set_mode[regno] = GET_MODE (reg);
10550       reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10551       reg_last_set_sign_bit_copies[regno]
10552         = num_sign_bit_copies (value, GET_MODE (reg));
10553     }
10554 }
10555
10556 /* Used for communication between the following two routines.  */
10557 static rtx record_dead_insn;
10558
10559 /* Called via note_stores from record_dead_and_set_regs to handle one
10560    SET or CLOBBER in an insn.  */
10561
10562 static void
10563 record_dead_and_set_regs_1 (dest, setter)
10564      rtx dest, setter;
10565 {
10566   if (GET_CODE (dest) == SUBREG)
10567     dest = SUBREG_REG (dest);
10568
10569   if (GET_CODE (dest) == REG)
10570     {
10571       /* If we are setting the whole register, we know its value.  Otherwise
10572          show that we don't know the value.  We can handle SUBREG in
10573          some cases.  */
10574       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10575         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10576       else if (GET_CODE (setter) == SET
10577                && GET_CODE (SET_DEST (setter)) == SUBREG
10578                && SUBREG_REG (SET_DEST (setter)) == dest
10579                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10580                && subreg_lowpart_p (SET_DEST (setter)))
10581         record_value_for_reg (dest, record_dead_insn,
10582                               gen_lowpart_for_combine (GET_MODE (dest),
10583                                                        SET_SRC (setter)));
10584       else
10585         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10586     }
10587   else if (GET_CODE (dest) == MEM
10588            /* Ignore pushes, they clobber nothing.  */
10589            && ! push_operand (dest, GET_MODE (dest)))
10590     mem_last_set = INSN_CUID (record_dead_insn);
10591 }
10592
10593 /* Update the records of when each REG was most recently set or killed
10594    for the things done by INSN.  This is the last thing done in processing
10595    INSN in the combiner loop.
10596
10597    We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10598    reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10599    and also the similar information mem_last_set (which insn most recently
10600    modified memory) and last_call_cuid (which insn was the most recent
10601    subroutine call).  */
10602
10603 static void
10604 record_dead_and_set_regs (insn)
10605      rtx insn;
10606 {
10607   register rtx link;
10608   int i;
10609
10610   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10611     {
10612       if (REG_NOTE_KIND (link) == REG_DEAD
10613           && GET_CODE (XEXP (link, 0)) == REG)
10614         {
10615           int regno = REGNO (XEXP (link, 0));
10616           int endregno
10617             = regno + (regno < FIRST_PSEUDO_REGISTER
10618                        ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10619                        : 1);
10620
10621           for (i = regno; i < endregno; i++)
10622             reg_last_death[i] = insn;
10623         }
10624       else if (REG_NOTE_KIND (link) == REG_INC)
10625         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10626     }
10627
10628   if (GET_CODE (insn) == CALL_INSN)
10629     {
10630       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10631         if (call_used_regs[i])
10632           {
10633             reg_last_set_value[i] = 0;
10634             reg_last_set_mode[i] = 0;
10635             reg_last_set_nonzero_bits[i] = 0;
10636             reg_last_set_sign_bit_copies[i] = 0;
10637             reg_last_death[i] = 0;
10638           }
10639
10640       last_call_cuid = mem_last_set = INSN_CUID (insn);
10641     }
10642
10643   record_dead_insn = insn;
10644   note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10645 }
10646 \f
10647 /* Utility routine for the following function.  Verify that all the registers
10648    mentioned in *LOC are valid when *LOC was part of a value set when
10649    label_tick == TICK.  Return 0 if some are not.
10650
10651    If REPLACE is non-zero, replace the invalid reference with
10652    (clobber (const_int 0)) and return 1.  This replacement is useful because
10653    we often can get useful information about the form of a value (e.g., if
10654    it was produced by a shift that always produces -1 or 0) even though
10655    we don't know exactly what registers it was produced from.  */
10656
10657 static int
10658 get_last_value_validate (loc, insn, tick, replace)
10659      rtx *loc;
10660      rtx insn;
10661      int tick;
10662      int replace;
10663 {
10664   rtx x = *loc;
10665   char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10666   int len = GET_RTX_LENGTH (GET_CODE (x));
10667   int i;
10668
10669   if (GET_CODE (x) == REG)
10670     {
10671       int regno = REGNO (x);
10672       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10673                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10674       int j;
10675
10676       for (j = regno; j < endregno; j++)
10677         if (reg_last_set_invalid[j]
10678             /* If this is a pseudo-register that was only set once, it is
10679                always valid.  */
10680             || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10681                 && reg_last_set_label[j] > tick))
10682           {
10683             if (replace)
10684               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10685             return replace;
10686           }
10687
10688       return 1;
10689     }
10690   /* If this is a memory reference, make sure that there were
10691      no stores after it that might have clobbered the value.  We don't
10692      have alias info, so we assume any store invalidates it.  */
10693   else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10694            && INSN_CUID (insn) <= mem_last_set)
10695     {
10696       if (replace)
10697         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10698       return replace;
10699     }
10700
10701   for (i = 0; i < len; i++)
10702     if ((fmt[i] == 'e'
10703          && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10704         /* Don't bother with these.  They shouldn't occur anyway.  */
10705         || fmt[i] == 'E')
10706       return 0;
10707
10708   /* If we haven't found a reason for it to be invalid, it is valid.  */
10709   return 1;
10710 }
10711
10712 /* Get the last value assigned to X, if known.  Some registers
10713    in the value may be replaced with (clobber (const_int 0)) if their value
10714    is known longer known reliably.  */
10715
10716 static rtx
10717 get_last_value (x)
10718      rtx x;
10719 {
10720   int regno;
10721   rtx value;
10722
10723   /* If this is a non-paradoxical SUBREG, get the value of its operand and
10724      then convert it to the desired mode.  If this is a paradoxical SUBREG,
10725      we cannot predict what values the "extra" bits might have.  */
10726   if (GET_CODE (x) == SUBREG
10727       && subreg_lowpart_p (x)
10728       && (GET_MODE_SIZE (GET_MODE (x))
10729           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10730       && (value = get_last_value (SUBREG_REG (x))) != 0)
10731     return gen_lowpart_for_combine (GET_MODE (x), value);
10732
10733   if (GET_CODE (x) != REG)
10734     return 0;
10735
10736   regno = REGNO (x);
10737   value = reg_last_set_value[regno];
10738
10739   /* If we don't have a value or if it isn't for this basic block,
10740      return 0.  */
10741
10742   if (value == 0
10743       || (REG_N_SETS (regno) != 1
10744           && reg_last_set_label[regno] != label_tick))
10745     return 0;
10746
10747   /* If the value was set in a later insn than the ones we are processing,
10748      we can't use it even if the register was only set once, but make a quick
10749      check to see if the previous insn set it to something.  This is commonly
10750      the case when the same pseudo is used by repeated insns.
10751
10752      This does not work if there exists an instruction which is temporarily
10753      not on the insn chain.  */
10754
10755   if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10756     {
10757       rtx insn, set;
10758
10759       /* We can not do anything useful in this case, because there is
10760          an instruction which is not on the insn chain.  */
10761       if (subst_prev_insn)
10762         return 0;
10763
10764       /* Skip over USE insns.  They are not useful here, and they may have
10765          been made by combine, in which case they do not have a INSN_CUID
10766          value.  We can't use prev_real_insn, because that would incorrectly
10767          take us backwards across labels.  Skip over BARRIERs also, since
10768          they could have been made by combine.  If we see one, we must be
10769          optimizing dead code, so it doesn't matter what we do.  */
10770       for (insn = prev_nonnote_insn (subst_insn);
10771            insn && ((GET_CODE (insn) == INSN
10772                      && GET_CODE (PATTERN (insn)) == USE)
10773                     || GET_CODE (insn) == BARRIER
10774                     || INSN_CUID (insn) >= subst_low_cuid);
10775            insn = prev_nonnote_insn (insn))
10776         ;
10777
10778       if (insn
10779           && (set = single_set (insn)) != 0
10780           && rtx_equal_p (SET_DEST (set), x))
10781         {
10782           value = SET_SRC (set);
10783
10784           /* Make sure that VALUE doesn't reference X.  Replace any
10785              explicit references with a CLOBBER.  If there are any remaining
10786              references (rare), don't use the value.  */
10787
10788           if (reg_mentioned_p (x, value))
10789             value = replace_rtx (copy_rtx (value), x,
10790                                  gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
10791
10792           if (reg_overlap_mentioned_p (x, value))
10793             return 0;
10794         }
10795       else
10796         return 0;
10797     }
10798
10799   /* If the value has all its registers valid, return it.  */
10800   if (get_last_value_validate (&value, reg_last_set[regno],
10801                                reg_last_set_label[regno], 0))
10802     return value;
10803
10804   /* Otherwise, make a copy and replace any invalid register with
10805      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
10806
10807   value = copy_rtx (value);
10808   if (get_last_value_validate (&value, reg_last_set[regno],
10809                                reg_last_set_label[regno], 1))
10810     return value;
10811
10812   return 0;
10813 }
10814 \f
10815 /* Return nonzero if expression X refers to a REG or to memory
10816    that is set in an instruction more recent than FROM_CUID.  */
10817
10818 static int
10819 use_crosses_set_p (x, from_cuid)
10820      register rtx x;
10821      int from_cuid;
10822 {
10823   register char *fmt;
10824   register int i;
10825   register enum rtx_code code = GET_CODE (x);
10826
10827   if (code == REG)
10828     {
10829       register int regno = REGNO (x);
10830       int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10831                             ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10832
10833 #ifdef PUSH_ROUNDING
10834       /* Don't allow uses of the stack pointer to be moved,
10835          because we don't know whether the move crosses a push insn.  */
10836       if (regno == STACK_POINTER_REGNUM)
10837         return 1;
10838 #endif
10839       for (;regno < endreg; regno++)
10840         if (reg_last_set[regno]
10841             && INSN_CUID (reg_last_set[regno]) > from_cuid)
10842           return 1;
10843       return 0;
10844     }
10845
10846   if (code == MEM && mem_last_set > from_cuid)
10847     return 1;
10848
10849   fmt = GET_RTX_FORMAT (code);
10850
10851   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10852     {
10853       if (fmt[i] == 'E')
10854         {
10855           register int j;
10856           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10857             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10858               return 1;
10859         }
10860       else if (fmt[i] == 'e'
10861                && use_crosses_set_p (XEXP (x, i), from_cuid))
10862         return 1;
10863     }
10864   return 0;
10865 }
10866 \f
10867 /* Define three variables used for communication between the following
10868    routines.  */
10869
10870 static int reg_dead_regno, reg_dead_endregno;
10871 static int reg_dead_flag;
10872
10873 /* Function called via note_stores from reg_dead_at_p.
10874
10875    If DEST is within [reg_dead_regno, reg_dead_endregno), set
10876    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
10877
10878 static void
10879 reg_dead_at_p_1 (dest, x)
10880      rtx dest;
10881      rtx x;
10882 {
10883   int regno, endregno;
10884
10885   if (GET_CODE (dest) != REG)
10886     return;
10887
10888   regno = REGNO (dest);
10889   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10890                       ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10891
10892   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10893     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10894 }
10895
10896 /* Return non-zero if REG is known to be dead at INSN.
10897
10898    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
10899    referencing REG, it is dead.  If we hit a SET referencing REG, it is
10900    live.  Otherwise, see if it is live or dead at the start of the basic
10901    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
10902    must be assumed to be always live.  */
10903
10904 static int
10905 reg_dead_at_p (reg, insn)
10906      rtx reg;
10907      rtx insn;
10908 {
10909   int block, i;
10910
10911   /* Set variables for reg_dead_at_p_1.  */
10912   reg_dead_regno = REGNO (reg);
10913   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10914                                         ? HARD_REGNO_NREGS (reg_dead_regno,
10915                                                             GET_MODE (reg))
10916                                         : 1);
10917
10918   reg_dead_flag = 0;
10919
10920   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  */
10921   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10922     {
10923       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10924         if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10925           return 0;
10926     }
10927
10928   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10929      beginning of function.  */
10930   for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10931        insn = prev_nonnote_insn (insn))
10932     {
10933       note_stores (PATTERN (insn), reg_dead_at_p_1);
10934       if (reg_dead_flag)
10935         return reg_dead_flag == 1 ? 1 : 0;
10936
10937       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10938         return 1;
10939     }
10940
10941   /* Get the basic block number that we were in.  */
10942   if (insn == 0)
10943     block = 0;
10944   else
10945     {
10946       for (block = 0; block < n_basic_blocks; block++)
10947         if (insn == basic_block_head[block])
10948           break;
10949
10950       if (block == n_basic_blocks)
10951         return 0;
10952     }
10953
10954   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10955     if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10956       return 0;
10957
10958   return 1;
10959 }
10960 \f
10961 /* Note hard registers in X that are used.  This code is similar to
10962    that in flow.c, but much simpler since we don't care about pseudos.  */
10963
10964 static void
10965 mark_used_regs_combine (x)
10966      rtx x;
10967 {
10968   register RTX_CODE code = GET_CODE (x);
10969   register int regno;
10970   int i;
10971
10972   switch (code)
10973     {
10974     case LABEL_REF:
10975     case SYMBOL_REF:
10976     case CONST_INT:
10977     case CONST:
10978     case CONST_DOUBLE:
10979     case PC:
10980     case ADDR_VEC:
10981     case ADDR_DIFF_VEC:
10982     case ASM_INPUT:
10983 #ifdef HAVE_cc0
10984     /* CC0 must die in the insn after it is set, so we don't need to take
10985        special note of it here.  */
10986     case CC0:
10987 #endif
10988       return;
10989
10990     case CLOBBER:
10991       /* If we are clobbering a MEM, mark any hard registers inside the
10992          address as used.  */
10993       if (GET_CODE (XEXP (x, 0)) == MEM)
10994         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10995       return;
10996
10997     case REG:
10998       regno = REGNO (x);
10999       /* A hard reg in a wide mode may really be multiple registers.
11000          If so, mark all of them just like the first.  */
11001       if (regno < FIRST_PSEUDO_REGISTER)
11002         {
11003           /* None of this applies to the stack, frame or arg pointers */
11004           if (regno == STACK_POINTER_REGNUM
11005 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11006               || regno == HARD_FRAME_POINTER_REGNUM
11007 #endif
11008 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11009               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11010 #endif
11011               || regno == FRAME_POINTER_REGNUM)
11012             return;
11013
11014           i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11015           while (i-- > 0)
11016             SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11017         }
11018       return;
11019
11020     case SET:
11021       {
11022         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11023            the address.  */
11024         register rtx testreg = SET_DEST (x);
11025
11026         while (GET_CODE (testreg) == SUBREG
11027                || GET_CODE (testreg) == ZERO_EXTRACT
11028                || GET_CODE (testreg) == SIGN_EXTRACT
11029                || GET_CODE (testreg) == STRICT_LOW_PART)
11030           testreg = XEXP (testreg, 0);
11031
11032         if (GET_CODE (testreg) == MEM)
11033           mark_used_regs_combine (XEXP (testreg, 0));
11034
11035         mark_used_regs_combine (SET_SRC (x));
11036       }
11037       return;
11038
11039     default:
11040       break;
11041     }
11042
11043   /* Recursively scan the operands of this expression.  */
11044
11045   {
11046     register char *fmt = GET_RTX_FORMAT (code);
11047
11048     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11049       {
11050         if (fmt[i] == 'e')
11051           mark_used_regs_combine (XEXP (x, i));
11052         else if (fmt[i] == 'E')
11053           {
11054             register int j;
11055
11056             for (j = 0; j < XVECLEN (x, i); j++)
11057               mark_used_regs_combine (XVECEXP (x, i, j));
11058           }
11059       }
11060   }
11061 }
11062
11063 \f
11064 /* Remove register number REGNO from the dead registers list of INSN.
11065
11066    Return the note used to record the death, if there was one.  */
11067
11068 rtx
11069 remove_death (regno, insn)
11070      int regno;
11071      rtx insn;
11072 {
11073   register rtx note = find_regno_note (insn, REG_DEAD, regno);
11074
11075   if (note)
11076     {
11077       REG_N_DEATHS (regno)--;
11078       remove_note (insn, note);
11079     }
11080
11081   return note;
11082 }
11083
11084 /* For each register (hardware or pseudo) used within expression X, if its
11085    death is in an instruction with cuid between FROM_CUID (inclusive) and
11086    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11087    list headed by PNOTES.
11088
11089    That said, don't move registers killed by maybe_kill_insn.
11090
11091    This is done when X is being merged by combination into TO_INSN.  These
11092    notes will then be distributed as needed.  */
11093
11094 static void
11095 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11096      rtx x;
11097      rtx maybe_kill_insn;
11098      int from_cuid;
11099      rtx to_insn;
11100      rtx *pnotes;
11101 {
11102   register char *fmt;
11103   register int len, i;
11104   register enum rtx_code code = GET_CODE (x);
11105
11106   if (code == REG)
11107     {
11108       register int regno = REGNO (x);
11109       register rtx where_dead = reg_last_death[regno];
11110       register rtx before_dead, after_dead;
11111
11112       /* Don't move the register if it gets killed in between from and to */
11113       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11114           && !reg_referenced_p (x, maybe_kill_insn))
11115         return;
11116
11117       /* WHERE_DEAD could be a USE insn made by combine, so first we
11118          make sure that we have insns with valid INSN_CUID values.  */
11119       before_dead = where_dead;
11120       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11121         before_dead = PREV_INSN (before_dead);
11122       after_dead = where_dead;
11123       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11124         after_dead = NEXT_INSN (after_dead);
11125
11126       if (before_dead && after_dead
11127           && INSN_CUID (before_dead) >= from_cuid
11128           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11129               || (where_dead != after_dead
11130                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11131         {
11132           rtx note = remove_death (regno, where_dead);
11133
11134           /* It is possible for the call above to return 0.  This can occur
11135              when reg_last_death points to I2 or I1 that we combined with.
11136              In that case make a new note.
11137
11138              We must also check for the case where X is a hard register
11139              and NOTE is a death note for a range of hard registers
11140              including X.  In that case, we must put REG_DEAD notes for
11141              the remaining registers in place of NOTE.  */
11142
11143           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11144               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11145                   > GET_MODE_SIZE (GET_MODE (x))))
11146             {
11147               int deadregno = REGNO (XEXP (note, 0));
11148               int deadend
11149                 = (deadregno + HARD_REGNO_NREGS (deadregno,
11150                                                  GET_MODE (XEXP (note, 0))));
11151               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11152               int i;
11153
11154               for (i = deadregno; i < deadend; i++)
11155                 if (i < regno || i >= ourend)
11156                   REG_NOTES (where_dead)
11157                     = gen_rtx_EXPR_LIST (REG_DEAD,
11158                                          gen_rtx_REG (reg_raw_mode[i], i),
11159                                          REG_NOTES (where_dead));
11160             }
11161           /* If we didn't find any note, or if we found a REG_DEAD note that
11162              covers only part of the given reg, and we have a multi-reg hard
11163              register, then to be safe we must check for REG_DEAD notes
11164              for each register other than the first.  They could have
11165              their own REG_DEAD notes lying around.  */
11166           else if ((note == 0
11167                     || (note != 0
11168                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11169                             < GET_MODE_SIZE (GET_MODE (x)))))
11170                    && regno < FIRST_PSEUDO_REGISTER
11171                    && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11172             {
11173               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11174               int i, offset;
11175               rtx oldnotes = 0;
11176
11177               if (note)
11178                 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11179               else
11180                 offset = 1;
11181
11182               for (i = regno + offset; i < ourend; i++)
11183                 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11184                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11185             }
11186
11187           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11188             {
11189               XEXP (note, 1) = *pnotes;
11190               *pnotes = note;
11191             }
11192           else
11193             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11194
11195           REG_N_DEATHS (regno)++;
11196         }
11197
11198       return;
11199     }
11200
11201   else if (GET_CODE (x) == SET)
11202     {
11203       rtx dest = SET_DEST (x);
11204
11205       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11206
11207       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11208          that accesses one word of a multi-word item, some
11209          piece of everything register in the expression is used by
11210          this insn, so remove any old death.  */
11211
11212       if (GET_CODE (dest) == ZERO_EXTRACT
11213           || GET_CODE (dest) == STRICT_LOW_PART
11214           || (GET_CODE (dest) == SUBREG
11215               && (((GET_MODE_SIZE (GET_MODE (dest))
11216                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11217                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11218                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11219         {
11220           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11221           return;
11222         }
11223
11224       /* If this is some other SUBREG, we know it replaces the entire
11225          value, so use that as the destination.  */
11226       if (GET_CODE (dest) == SUBREG)
11227         dest = SUBREG_REG (dest);
11228
11229       /* If this is a MEM, adjust deaths of anything used in the address.
11230          For a REG (the only other possibility), the entire value is
11231          being replaced so the old value is not used in this insn.  */
11232
11233       if (GET_CODE (dest) == MEM)
11234         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11235                      to_insn, pnotes);
11236       return;
11237     }
11238
11239   else if (GET_CODE (x) == CLOBBER)
11240     return;
11241
11242   len = GET_RTX_LENGTH (code);
11243   fmt = GET_RTX_FORMAT (code);
11244
11245   for (i = 0; i < len; i++)
11246     {
11247       if (fmt[i] == 'E')
11248         {
11249           register int j;
11250           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11251             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11252                          to_insn, pnotes);
11253         }
11254       else if (fmt[i] == 'e')
11255         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11256     }
11257 }
11258 \f
11259 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11260    pattern of an insn.  X must be a REG.  */
11261
11262 static int
11263 reg_bitfield_target_p (x, body)
11264      rtx x;
11265      rtx body;
11266 {
11267   int i;
11268
11269   if (GET_CODE (body) == SET)
11270     {
11271       rtx dest = SET_DEST (body);
11272       rtx target;
11273       int regno, tregno, endregno, endtregno;
11274
11275       if (GET_CODE (dest) == ZERO_EXTRACT)
11276         target = XEXP (dest, 0);
11277       else if (GET_CODE (dest) == STRICT_LOW_PART)
11278         target = SUBREG_REG (XEXP (dest, 0));
11279       else
11280         return 0;
11281
11282       if (GET_CODE (target) == SUBREG)
11283         target = SUBREG_REG (target);
11284
11285       if (GET_CODE (target) != REG)
11286         return 0;
11287
11288       tregno = REGNO (target), regno = REGNO (x);
11289       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11290         return target == x;
11291
11292       endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11293       endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11294
11295       return endregno > tregno && regno < endtregno;
11296     }
11297
11298   else if (GET_CODE (body) == PARALLEL)
11299     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11300       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11301         return 1;
11302
11303   return 0;
11304 }
11305 \f
11306 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11307    as appropriate.  I3 and I2 are the insns resulting from the combination
11308    insns including FROM (I2 may be zero).
11309
11310    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11311    not need REG_DEAD notes because they are being substituted for.  This
11312    saves searching in the most common cases.
11313
11314    Each note in the list is either ignored or placed on some insns, depending
11315    on the type of note.  */
11316
11317 static void
11318 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11319      rtx notes;
11320      rtx from_insn;
11321      rtx i3, i2;
11322      rtx elim_i2, elim_i1;
11323 {
11324   rtx note, next_note;
11325   rtx tem;
11326
11327   for (note = notes; note; note = next_note)
11328     {
11329       rtx place = 0, place2 = 0;
11330
11331       /* If this NOTE references a pseudo register, ensure it references
11332          the latest copy of that register.  */
11333       if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11334           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11335         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11336
11337       next_note = XEXP (note, 1);
11338       switch (REG_NOTE_KIND (note))
11339         {
11340         case REG_BR_PROB:
11341         case REG_EXEC_COUNT:
11342           /* Doesn't matter much where we put this, as long as it's somewhere.
11343              It is preferable to keep these notes on branches, which is most
11344              likely to be i3.  */
11345           place = i3;
11346           break;
11347
11348         case REG_UNUSED:
11349           /* Any clobbers for i3 may still exist, and so we must process
11350              REG_UNUSED notes from that insn.
11351
11352              Any clobbers from i2 or i1 can only exist if they were added by
11353              recog_for_combine.  In that case, recog_for_combine created the
11354              necessary REG_UNUSED notes.  Trying to keep any original
11355              REG_UNUSED notes from these insns can cause incorrect output
11356              if it is for the same register as the original i3 dest.
11357              In that case, we will notice that the register is set in i3,
11358              and then add a REG_UNUSED note for the destination of i3, which
11359              is wrong.  However, it is possible to have REG_UNUSED notes from
11360              i2 or i1 for register which were both used and clobbered, so
11361              we keep notes from i2 or i1 if they will turn into REG_DEAD
11362              notes.  */
11363
11364           /* If this register is set or clobbered in I3, put the note there
11365              unless there is one already.  */
11366           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11367             {
11368               if (from_insn != i3)
11369                 break;
11370
11371               if (! (GET_CODE (XEXP (note, 0)) == REG
11372                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11373                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11374                 place = i3;
11375             }
11376           /* Otherwise, if this register is used by I3, then this register
11377              now dies here, so we must put a REG_DEAD note here unless there
11378              is one already.  */
11379           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11380                    && ! (GET_CODE (XEXP (note, 0)) == REG
11381                          ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11382                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11383             {
11384               PUT_REG_NOTE_KIND (note, REG_DEAD);
11385               place = i3;
11386             }
11387           break;
11388
11389         case REG_EQUAL:
11390         case REG_EQUIV:
11391         case REG_NONNEG:
11392         case REG_NOALIAS:
11393           /* These notes say something about results of an insn.  We can
11394              only support them if they used to be on I3 in which case they
11395              remain on I3.  Otherwise they are ignored.
11396
11397              If the note refers to an expression that is not a constant, we
11398              must also ignore the note since we cannot tell whether the
11399              equivalence is still true.  It might be possible to do
11400              slightly better than this (we only have a problem if I2DEST
11401              or I1DEST is present in the expression), but it doesn't
11402              seem worth the trouble.  */
11403
11404           if (from_insn == i3
11405               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11406             place = i3;
11407           break;
11408
11409         case REG_INC:
11410         case REG_NO_CONFLICT:
11411         case REG_LABEL:
11412           /* These notes say something about how a register is used.  They must
11413              be present on any use of the register in I2 or I3.  */
11414           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11415             place = i3;
11416
11417           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11418             {
11419               if (place)
11420                 place2 = i2;
11421               else
11422                 place = i2;
11423             }
11424           break;
11425
11426         case REG_WAS_0:
11427           /* It is too much trouble to try to see if this note is still
11428              correct in all situations.  It is better to simply delete it.  */
11429           break;
11430
11431         case REG_RETVAL:
11432           /* If the insn previously containing this note still exists,
11433              put it back where it was.  Otherwise move it to the previous
11434              insn.  Adjust the corresponding REG_LIBCALL note.  */
11435           if (GET_CODE (from_insn) != NOTE)
11436             place = from_insn;
11437           else
11438             {
11439               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11440               place = prev_real_insn (from_insn);
11441               if (tem && place)
11442                 XEXP (tem, 0) = place;
11443             }
11444           break;
11445
11446         case REG_LIBCALL:
11447           /* This is handled similarly to REG_RETVAL.  */
11448           if (GET_CODE (from_insn) != NOTE)
11449             place = from_insn;
11450           else
11451             {
11452               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11453               place = next_real_insn (from_insn);
11454               if (tem && place)
11455                 XEXP (tem, 0) = place;
11456             }
11457           break;
11458
11459         case REG_DEAD:
11460           /* If the register is used as an input in I3, it dies there.
11461              Similarly for I2, if it is non-zero and adjacent to I3.
11462
11463              If the register is not used as an input in either I3 or I2
11464              and it is not one of the registers we were supposed to eliminate,
11465              there are two possibilities.  We might have a non-adjacent I2
11466              or we might have somehow eliminated an additional register
11467              from a computation.  For example, we might have had A & B where
11468              we discover that B will always be zero.  In this case we will
11469              eliminate the reference to A.
11470
11471              In both cases, we must search to see if we can find a previous
11472              use of A and put the death note there.  */
11473
11474           if (from_insn
11475               && GET_CODE (from_insn) == CALL_INSN
11476               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11477             place = from_insn;
11478           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11479             place = i3;
11480           else if (i2 != 0 && next_nonnote_insn (i2) == i3
11481                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11482             place = i2;
11483
11484           if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11485             break;
11486
11487           /* If the register is used in both I2 and I3 and it dies in I3,
11488              we might have added another reference to it.  If reg_n_refs
11489              was 2, bump it to 3.  This has to be correct since the
11490              register must have been set somewhere.  The reason this is
11491              done is because local-alloc.c treats 2 references as a
11492              special case.  */
11493
11494           if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11495               && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11496               && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11497             REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11498
11499           if (place == 0)
11500             {
11501               for (tem = prev_nonnote_insn (i3);
11502                    place == 0 && tem
11503                    && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11504                    tem = prev_nonnote_insn (tem))
11505                 {
11506                   /* If the register is being set at TEM, see if that is all
11507                      TEM is doing.  If so, delete TEM.  Otherwise, make this
11508                      into a REG_UNUSED note instead.  */
11509                   if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11510                     {
11511                       rtx set = single_set (tem);
11512                       rtx inner_dest = 0;
11513
11514                       if (set != 0)
11515                         for (inner_dest = SET_DEST (set);
11516                              GET_CODE (inner_dest) == STRICT_LOW_PART
11517                              || GET_CODE (inner_dest) == SUBREG
11518                              || GET_CODE (inner_dest) == ZERO_EXTRACT;
11519                              inner_dest = XEXP (inner_dest, 0))
11520                           ;
11521
11522                       /* Verify that it was the set, and not a clobber that
11523                          modified the register.  */
11524
11525                       if (set != 0 && ! side_effects_p (SET_SRC (set))
11526                           && rtx_equal_p (XEXP (note, 0), inner_dest))
11527                         {
11528                           /* Move the notes and links of TEM elsewhere.
11529                              This might delete other dead insns recursively.
11530                              First set the pattern to something that won't use
11531                              any register.  */
11532
11533                           PATTERN (tem) = pc_rtx;
11534
11535                           distribute_notes (REG_NOTES (tem), tem, tem,
11536                                             NULL_RTX, NULL_RTX, NULL_RTX);
11537                           distribute_links (LOG_LINKS (tem));
11538
11539                           PUT_CODE (tem, NOTE);
11540                           NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11541                           NOTE_SOURCE_FILE (tem) = 0;
11542                         }
11543                       /* If the register is both set and used here, put the
11544                          REG_DEAD note here, but place a REG_UNUSED note
11545                          here too unless there already is one.  */
11546                       else if (reg_referenced_p (XEXP (note, 0),
11547                                                  PATTERN (tem)))
11548                         {
11549                           place = tem;
11550
11551                           if (! find_regno_note (tem, REG_UNUSED,
11552                                                  REGNO (XEXP (note, 0))))
11553                             REG_NOTES (tem)
11554                               = gen_rtx (EXPR_LIST, REG_UNUSED, XEXP (note, 0),
11555                                          REG_NOTES (tem));
11556                         }
11557                       else
11558                         {
11559                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
11560
11561                           /*  If there isn't already a REG_UNUSED note, put one
11562                               here.  */
11563                           if (! find_regno_note (tem, REG_UNUSED,
11564                                                  REGNO (XEXP (note, 0))))
11565                             place = tem;
11566                           break;
11567                       }
11568                   }
11569                 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11570                          || (GET_CODE (tem) == CALL_INSN
11571                              && find_reg_fusage (tem, USE, XEXP (note, 0))))
11572                   {
11573                     place = tem;
11574
11575                     /* If we are doing a 3->2 combination, and we have a
11576                        register which formerly died in i3 and was not used
11577                        by i2, which now no longer dies in i3 and is used in
11578                        i2 but does not die in i2, and place is between i2
11579                        and i3, then we may need to move a link from place to
11580                        i2.  */
11581                     if (i2 && INSN_UID (place) <= max_uid_cuid
11582                         && INSN_CUID (place) > INSN_CUID (i2)
11583                         && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11584                         && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11585                       {
11586                         rtx links = LOG_LINKS (place);
11587                         LOG_LINKS (place) = 0;
11588                         distribute_links (links);
11589                       }
11590                     break;
11591                   }
11592                 }
11593
11594               /* If we haven't found an insn for the death note and it
11595                  is still a REG_DEAD note, but we have hit a CODE_LABEL,
11596                  insert a USE insn for the register at that label and
11597                  put the death node there.  This prevents problems with
11598                  call-state tracking in caller-save.c.  */
11599               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11600                 {
11601                   place
11602                     = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
11603                                        tem);
11604
11605                   /* If this insn was emitted between blocks, then update
11606                      basic_block_head of the current block to include it.  */
11607                   if (basic_block_end[this_basic_block - 1] == tem)
11608                     basic_block_head[this_basic_block] = place;
11609                 }
11610             }
11611
11612           /* If the register is set or already dead at PLACE, we needn't do
11613              anything with this note if it is still a REG_DEAD note.
11614              We can here if it is set at all, not if is it totally replace,
11615              which is what `dead_or_set_p' checks, so also check for it being
11616              set partially.  */
11617
11618
11619           if (place && REG_NOTE_KIND (note) == REG_DEAD)
11620             {
11621               int regno = REGNO (XEXP (note, 0));
11622
11623               if (dead_or_set_p (place, XEXP (note, 0))
11624                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11625                 {
11626                   /* Unless the register previously died in PLACE, clear
11627                      reg_last_death.  [I no longer understand why this is
11628                      being done.] */
11629                   if (reg_last_death[regno] != place)
11630                     reg_last_death[regno] = 0;
11631                   place = 0;
11632                 }
11633               else
11634                 reg_last_death[regno] = place;
11635
11636               /* If this is a death note for a hard reg that is occupying
11637                  multiple registers, ensure that we are still using all
11638                  parts of the object.  If we find a piece of the object
11639                  that is unused, we must add a USE for that piece before
11640                  PLACE and put the appropriate REG_DEAD note on it.
11641
11642                  An alternative would be to put a REG_UNUSED for the pieces
11643                  on the insn that set the register, but that can't be done if
11644                  it is not in the same block.  It is simpler, though less
11645                  efficient, to add the USE insns.  */
11646
11647               if (place && regno < FIRST_PSEUDO_REGISTER
11648                   && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11649                 {
11650                   int endregno
11651                     = regno + HARD_REGNO_NREGS (regno,
11652                                                 GET_MODE (XEXP (note, 0)));
11653                   int all_used = 1;
11654                   int i;
11655
11656                   for (i = regno; i < endregno; i++)
11657                     if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11658                         && ! find_regno_fusage (place, USE, i))
11659                       {
11660                         rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11661                         rtx p;
11662
11663                         /* See if we already placed a USE note for this
11664                            register in front of PLACE.  */
11665                         for (p = place;
11666                              GET_CODE (PREV_INSN (p)) == INSN
11667                              && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11668                              p = PREV_INSN (p))
11669                           if (rtx_equal_p (piece,
11670                                            XEXP (PATTERN (PREV_INSN (p)), 0)))
11671                             {
11672                               p = 0;
11673                               break;
11674                             }
11675
11676                         if (p)
11677                           {
11678                             rtx use_insn
11679                               = emit_insn_before (gen_rtx_USE (VOIDmode,
11680                                                                piece),
11681                                                   p);
11682                             REG_NOTES (use_insn)
11683                               = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11684                                                    REG_NOTES (use_insn));
11685                           }
11686
11687                         all_used = 0;
11688                       }
11689
11690                   /* Check for the case where the register dying partially
11691                      overlaps the register set by this insn.  */
11692                   if (all_used)
11693                     for (i = regno; i < endregno; i++)
11694                       if (dead_or_set_regno_p (place, i))
11695                           {
11696                             all_used = 0;
11697                             break;
11698                           }
11699
11700                   if (! all_used)
11701                     {
11702                       /* Put only REG_DEAD notes for pieces that are
11703                          still used and that are not already dead or set.  */
11704
11705                       for (i = regno; i < endregno; i++)
11706                         {
11707                           rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11708
11709                           if ((reg_referenced_p (piece, PATTERN (place))
11710                                || (GET_CODE (place) == CALL_INSN
11711                                    && find_reg_fusage (place, USE, piece)))
11712                               && ! dead_or_set_p (place, piece)
11713                               && ! reg_bitfield_target_p (piece,
11714                                                           PATTERN (place)))
11715                             REG_NOTES (place)
11716                               = gen_rtx_EXPR_LIST (REG_DEAD,
11717                                                    piece, REG_NOTES (place));
11718                         }
11719
11720                       place = 0;
11721                     }
11722                 }
11723             }
11724           break;
11725
11726         default:
11727           /* Any other notes should not be present at this point in the
11728              compilation.  */
11729           abort ();
11730         }
11731
11732       if (place)
11733         {
11734           XEXP (note, 1) = REG_NOTES (place);
11735           REG_NOTES (place) = note;
11736         }
11737       else if ((REG_NOTE_KIND (note) == REG_DEAD
11738                 || REG_NOTE_KIND (note) == REG_UNUSED)
11739                && GET_CODE (XEXP (note, 0)) == REG)
11740         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11741
11742       if (place2)
11743         {
11744           if ((REG_NOTE_KIND (note) == REG_DEAD
11745                || REG_NOTE_KIND (note) == REG_UNUSED)
11746               && GET_CODE (XEXP (note, 0)) == REG)
11747             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11748
11749           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11750                                                REG_NOTE_KIND (note),
11751                                                XEXP (note, 0),
11752                                                REG_NOTES (place2));
11753         }
11754     }
11755 }
11756 \f
11757 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11758    I3, I2, and I1 to new locations.  This is also called in one case to
11759    add a link pointing at I3 when I3's destination is changed.  */
11760
11761 static void
11762 distribute_links (links)
11763      rtx links;
11764 {
11765   rtx link, next_link;
11766
11767   for (link = links; link; link = next_link)
11768     {
11769       rtx place = 0;
11770       rtx insn;
11771       rtx set, reg;
11772
11773       next_link = XEXP (link, 1);
11774
11775       /* If the insn that this link points to is a NOTE or isn't a single
11776          set, ignore it.  In the latter case, it isn't clear what we
11777          can do other than ignore the link, since we can't tell which
11778          register it was for.  Such links wouldn't be used by combine
11779          anyway.
11780
11781          It is not possible for the destination of the target of the link to
11782          have been changed by combine.  The only potential of this is if we
11783          replace I3, I2, and I1 by I3 and I2.  But in that case the
11784          destination of I2 also remains unchanged.  */
11785
11786       if (GET_CODE (XEXP (link, 0)) == NOTE
11787           || (set = single_set (XEXP (link, 0))) == 0)
11788         continue;
11789
11790       reg = SET_DEST (set);
11791       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11792              || GET_CODE (reg) == SIGN_EXTRACT
11793              || GET_CODE (reg) == STRICT_LOW_PART)
11794         reg = XEXP (reg, 0);
11795
11796       /* A LOG_LINK is defined as being placed on the first insn that uses
11797          a register and points to the insn that sets the register.  Start
11798          searching at the next insn after the target of the link and stop
11799          when we reach a set of the register or the end of the basic block.
11800
11801          Note that this correctly handles the link that used to point from
11802          I3 to I2.  Also note that not much searching is typically done here
11803          since most links don't point very far away.  */
11804
11805       for (insn = NEXT_INSN (XEXP (link, 0));
11806            (insn && (this_basic_block == n_basic_blocks - 1
11807                      || basic_block_head[this_basic_block + 1] != insn));
11808            insn = NEXT_INSN (insn))
11809         if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11810             && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11811           {
11812             if (reg_referenced_p (reg, PATTERN (insn)))
11813               place = insn;
11814             break;
11815           }
11816         else if (GET_CODE (insn) == CALL_INSN
11817               && find_reg_fusage (insn, USE, reg))
11818           {
11819             place = insn;
11820             break;
11821           }
11822
11823       /* If we found a place to put the link, place it there unless there
11824          is already a link to the same insn as LINK at that point.  */
11825
11826       if (place)
11827         {
11828           rtx link2;
11829
11830           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11831             if (XEXP (link2, 0) == XEXP (link, 0))
11832               break;
11833
11834           if (link2 == 0)
11835             {
11836               XEXP (link, 1) = LOG_LINKS (place);
11837               LOG_LINKS (place) = link;
11838
11839               /* Set added_links_insn to the earliest insn we added a
11840                  link to.  */
11841               if (added_links_insn == 0
11842                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
11843                 added_links_insn = place;
11844             }
11845         }
11846     }
11847 }
11848 \f
11849 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
11850
11851 static int
11852 insn_cuid (insn)
11853      rtx insn;
11854 {
11855   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11856          && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11857     insn = NEXT_INSN (insn);
11858
11859   if (INSN_UID (insn) > max_uid_cuid)
11860     abort ();
11861
11862   return INSN_CUID (insn);
11863 }
11864 \f
11865 void
11866 dump_combine_stats (file)
11867      FILE *file;
11868 {
11869   fprintf
11870     (file,
11871      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11872      combine_attempts, combine_merges, combine_extras, combine_successes);
11873 }
11874
11875 void
11876 dump_combine_total_stats (file)
11877      FILE *file;
11878 {
11879   fprintf
11880     (file,
11881      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11882      total_attempts, total_merges, total_extras, total_successes);
11883 }