1 /* { dg-do compile } */
2 /* { dg-options "-O -msve-vector-bits=256" } */
6 typedef int64_t vnx2di
__attribute__((vector_size (32)));
7 typedef int32_t vnx4si
__attribute__((vector_size (32)));
8 typedef int16_t vnx8hi
__attribute__((vector_size (32)));
9 typedef int8_t vnx16qi
__attribute__((vector_size (32)));
10 typedef double vnx2df
__attribute__((vector_size (32)));
11 typedef float vnx4sf
__attribute__((vector_size (32)));
12 typedef _Float16 vnx8hf
__attribute__((vector_size (32)));
14 #define UZP1(TYPE, MASK) \
15 TYPE uzp1_##TYPE (TYPE values1, TYPE values2) \
17 return __builtin_shuffle (values1, values2, MASK); \
21 UZP1 (vnx2di
, ((vnx2di
) { 0, 2, 4, 6 }));
22 UZP1 (vnx4si
, ((vnx4si
) { 0, 2, 4, 6, 8, 10, 12, 14 }));
23 UZP1 (vnx8hi
, ((vnx8hi
) { 0, 2, 4, 6, 8, 10, 12, 14,
24 16, 18, 20, 22, 24, 26, 28, 30 }));
25 UZP1 (vnx16qi
, ((vnx16qi
) { 0, 2, 4, 6, 8, 10, 12, 14,
26 16, 18, 20, 22, 24, 26, 28, 30,
27 32, 34, 36, 38, 40, 42, 44, 46,
28 48, 50, 52, 54, 56, 58, 60, 62 }));
29 UZP1 (vnx2df
, ((vnx2di
) { 0, 2, 4, 6 }));
30 UZP1 (vnx4sf
, ((vnx4si
) { 0, 2, 4, 6, 8, 10, 12, 14 }));
31 UZP1 (vnx8hf
, ((vnx8hi
) { 0, 2, 4, 6, 8, 10, 12, 14,
32 16, 18, 20, 22, 24, 26, 28, 30 }));
34 /* { dg-final { scan-assembler-not {\ttbl\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} } } */
35 /* { dg-final { scan-assembler-not {\ttbl\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} } } */
36 /* { dg-final { scan-assembler-not {\ttbl\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} } } */
37 /* { dg-final { scan-assembler-not {\ttbl\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b\n} } } */
39 /* { dg-final { scan-assembler-times {\tuzp1\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
40 /* { dg-final { scan-assembler-times {\tuzp1\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
41 /* { dg-final { scan-assembler-times {\tuzp1\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
42 /* { dg-final { scan-assembler-times {\tuzp1\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */