1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "langhooks.h"
54 #include "sched-int.h"
57 #include "diagnostic.h"
58 #include "target-globals.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
83 up to 0x7f8 bytes and can usually save or restore all the registers
84 that we need to save or restore. (Note that we can only use these
85 instructions for o32, for which the stack alignment is 8 bytes.)
87 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
88 RESTORE are not available. We can then use unextended instructions
89 to save and restore registers, and to allocate and deallocate the top
91 #define MIPS_MAX_FIRST_STACK_STEP \
92 (!TARGET_MIPS16 ? 0x7ff0 \
93 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
94 : TARGET_64BIT ? 0x100 : 0x400)
96 /* True if INSN is a mips.md pattern or asm statement. */
97 #define USEFUL_INSN_P(INSN) \
98 (NONDEBUG_INSN_P (INSN) \
99 && GET_CODE (PATTERN (INSN)) != USE \
100 && GET_CODE (PATTERN (INSN)) != CLOBBER \
101 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
102 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104 /* If INSN is a delayed branch sequence, return the first instruction
105 in the sequence, otherwise return INSN itself. */
106 #define SEQ_BEGIN(INSN) \
107 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
108 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 /* Likewise for the last instruction in a delayed branch sequence. */
112 #define SEQ_END(INSN) \
113 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
114 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 /* Execute the following loop body with SUBINSN set to each instruction
118 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
119 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
120 for ((SUBINSN) = SEQ_BEGIN (INSN); \
121 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
122 (SUBINSN) = NEXT_INSN (SUBINSN))
124 /* True if bit BIT is set in VALUE. */
125 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127 /* Return the opcode for a ptr_mode load of the form:
129 l[wd] DEST, OFFSET(BASE). */
130 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
131 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
136 /* Return the opcode to move register SRC into register DEST. */
137 #define MIPS_MOVE(DEST, SRC) \
138 ((TARGET_64BIT ? 0x2d : 0x21) \
142 /* Return the opcode for:
145 #define MIPS_LUI(DEST, VALUE) \
146 ((0xf << 26) | ((DEST) << 16) | (VALUE))
148 /* Return the opcode to jump to register DEST. */
149 #define MIPS_JR(DEST) \
150 (((DEST) << 21) | 0x8)
152 /* Return the opcode for:
154 bal . + (1 + OFFSET) * 4. */
155 #define MIPS_BAL(OFFSET) \
156 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
158 /* Return the usual opcode for a nop. */
161 /* Classifies an address.
164 A natural register + offset address. The register satisfies
165 mips_valid_base_register_p and the offset is a const_arith_operand.
168 A LO_SUM rtx. The first operand is a valid base register and
169 the second operand is a symbolic address.
172 A signed 16-bit constant address.
175 A constant symbolic address. */
176 enum mips_address_type
{
183 /* Macros to create an enumeration identifier for a function prototype. */
184 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
185 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
186 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
187 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
189 /* Classifies the prototype of a built-in function. */
190 enum mips_function_type
{
191 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
192 #include "config/mips/mips-ftypes.def"
193 #undef DEF_MIPS_FTYPE
197 /* Specifies how a built-in function should be converted into rtl. */
198 enum mips_builtin_type
{
199 /* The function corresponds directly to an .md pattern. The return
200 value is mapped to operand 0 and the arguments are mapped to
201 operands 1 and above. */
204 /* The function corresponds directly to an .md pattern. There is no return
205 value and the arguments are mapped to operands 0 and above. */
206 MIPS_BUILTIN_DIRECT_NO_TARGET
,
208 /* The function corresponds to a comparison instruction followed by
209 a mips_cond_move_tf_ps pattern. The first two arguments are the
210 values to compare and the second two arguments are the vector
211 operands for the movt.ps or movf.ps instruction (in assembly order). */
215 /* The function corresponds to a V2SF comparison instruction. Operand 0
216 of this instruction is the result of the comparison, which has mode
217 CCV2 or CCV4. The function arguments are mapped to operands 1 and
218 above. The function's return value is an SImode boolean that is
219 true under the following conditions:
221 MIPS_BUILTIN_CMP_ANY: one of the registers is true
222 MIPS_BUILTIN_CMP_ALL: all of the registers are true
223 MIPS_BUILTIN_CMP_LOWER: the first register is true
224 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
225 MIPS_BUILTIN_CMP_ANY
,
226 MIPS_BUILTIN_CMP_ALL
,
227 MIPS_BUILTIN_CMP_UPPER
,
228 MIPS_BUILTIN_CMP_LOWER
,
230 /* As above, but the instruction only sets a single $fcc register. */
231 MIPS_BUILTIN_CMP_SINGLE
,
233 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
234 MIPS_BUILTIN_BPOSGE32
237 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
238 #define MIPS_FP_CONDITIONS(MACRO) \
256 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
257 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
258 enum mips_fp_condition
{
259 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
262 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
263 #define STRINGIFY(X) #X
264 static const char *const mips_fp_conditions
[] = {
265 MIPS_FP_CONDITIONS (STRINGIFY
)
268 /* Information about a function's frame layout. */
269 struct GTY(()) mips_frame_info
{
270 /* The size of the frame in bytes. */
271 HOST_WIDE_INT total_size
;
273 /* The number of bytes allocated to variables. */
274 HOST_WIDE_INT var_size
;
276 /* The number of bytes allocated to outgoing function arguments. */
277 HOST_WIDE_INT args_size
;
279 /* The number of bytes allocated to the .cprestore slot, or 0 if there
281 HOST_WIDE_INT cprestore_size
;
283 /* Bit X is set if the function saves or restores GPR X. */
286 /* Likewise FPR X. */
289 /* Likewise doubleword accumulator X ($acX). */
290 unsigned int acc_mask
;
292 /* The number of GPRs, FPRs, doubleword accumulators and COP0
296 unsigned int num_acc
;
297 unsigned int num_cop0_regs
;
299 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
300 save slots from the top of the frame, or zero if no such slots are
302 HOST_WIDE_INT gp_save_offset
;
303 HOST_WIDE_INT fp_save_offset
;
304 HOST_WIDE_INT acc_save_offset
;
305 HOST_WIDE_INT cop0_save_offset
;
307 /* Likewise, but giving offsets from the bottom of the frame. */
308 HOST_WIDE_INT gp_sp_offset
;
309 HOST_WIDE_INT fp_sp_offset
;
310 HOST_WIDE_INT acc_sp_offset
;
311 HOST_WIDE_INT cop0_sp_offset
;
313 /* Similar, but the value passed to _mcount. */
314 HOST_WIDE_INT ra_fp_offset
;
316 /* The offset of arg_pointer_rtx from the bottom of the frame. */
317 HOST_WIDE_INT arg_pointer_offset
;
319 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
320 HOST_WIDE_INT hard_frame_pointer_offset
;
323 struct GTY(()) machine_function
{
324 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
325 rtx mips16_gp_pseudo_rtx
;
327 /* The number of extra stack bytes taken up by register varargs.
328 This area is allocated by the callee at the very top of the frame. */
331 /* The current frame information, calculated by mips_compute_frame_info. */
332 struct mips_frame_info frame
;
334 /* The register to use as the function's global pointer, or INVALID_REGNUM
335 if the function doesn't need one. */
336 unsigned int global_pointer
;
338 /* How many instructions it takes to load a label into $AT, or 0 if
339 this property hasn't yet been calculated. */
340 unsigned int load_label_num_insns
;
342 /* True if mips_adjust_insn_length should ignore an instruction's
344 bool ignore_hazard_length_p
;
346 /* True if the whole function is suitable for .set noreorder and
348 bool all_noreorder_p
;
350 /* True if the function has "inflexible" and "flexible" references
351 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
352 and mips_cfun_has_flexible_gp_ref_p for details. */
353 bool has_inflexible_gp_insn_p
;
354 bool has_flexible_gp_insn_p
;
356 /* True if the function's prologue must load the global pointer
357 value into pic_offset_table_rtx and store the same value in
358 the function's cprestore slot (if any). Even if this value
359 is currently false, we may decide to set it to true later;
360 see mips_must_initialize_gp_p () for details. */
361 bool must_initialize_gp_p
;
363 /* True if the current function must restore $gp after any potential
364 clobber. This value is only meaningful during the first post-epilogue
365 split_insns pass; see mips_must_initialize_gp_p () for details. */
366 bool must_restore_gp_when_clobbered_p
;
368 /* True if this is an interrupt handler. */
369 bool interrupt_handler_p
;
371 /* True if this is an interrupt handler that uses shadow registers. */
372 bool use_shadow_register_set_p
;
374 /* True if this is an interrupt handler that should keep interrupts
376 bool keep_interrupts_masked_p
;
378 /* True if this is an interrupt handler that should use DERET
380 bool use_debug_exception_return_p
;
383 /* Information about a single argument. */
384 struct mips_arg_info
{
385 /* True if the argument is passed in a floating-point register, or
386 would have been if we hadn't run out of registers. */
389 /* The number of words passed in registers, rounded up. */
390 unsigned int reg_words
;
392 /* For EABI, the offset of the first register from GP_ARG_FIRST or
393 FP_ARG_FIRST. For other ABIs, the offset of the first register from
394 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
395 comment for details).
397 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
399 unsigned int reg_offset
;
401 /* The number of words that must be passed on the stack, rounded up. */
402 unsigned int stack_words
;
404 /* The offset from the start of the stack overflow area of the argument's
405 first stack word. Only meaningful when STACK_WORDS is nonzero. */
406 unsigned int stack_offset
;
409 /* Information about an address described by mips_address_type.
415 REG is the base register and OFFSET is the constant offset.
418 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
419 is the type of symbol it references.
422 SYMBOL_TYPE is the type of symbol that the address references. */
423 struct mips_address_info
{
424 enum mips_address_type type
;
427 enum mips_symbol_type symbol_type
;
430 /* One stage in a constant building sequence. These sequences have
434 A = A CODE[1] VALUE[1]
435 A = A CODE[2] VALUE[2]
438 where A is an accumulator, each CODE[i] is a binary rtl operation
439 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
440 struct mips_integer_op
{
442 unsigned HOST_WIDE_INT value
;
445 /* The largest number of operations needed to load an integer constant.
446 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
447 When the lowest bit is clear, we can try, but reject a sequence with
448 an extra SLL at the end. */
449 #define MIPS_MAX_INTEGER_OPS 7
451 /* Information about a MIPS16e SAVE or RESTORE instruction. */
452 struct mips16e_save_restore_info
{
453 /* The number of argument registers saved by a SAVE instruction.
454 0 for RESTORE instructions. */
457 /* Bit X is set if the instruction saves or restores GPR X. */
460 /* The total number of bytes to allocate. */
464 /* Costs of various operations on the different architectures. */
466 struct mips_rtx_cost_data
468 unsigned short fp_add
;
469 unsigned short fp_mult_sf
;
470 unsigned short fp_mult_df
;
471 unsigned short fp_div_sf
;
472 unsigned short fp_div_df
;
473 unsigned short int_mult_si
;
474 unsigned short int_mult_di
;
475 unsigned short int_div_si
;
476 unsigned short int_div_di
;
477 unsigned short branch_cost
;
478 unsigned short memory_latency
;
481 /* Global variables for machine-dependent things. */
483 /* The -G setting, or the configuration's default small-data limit if
484 no -G option is given. */
485 static unsigned int mips_small_data_threshold
;
487 /* The number of file directives written by mips_output_filename. */
488 int num_source_filenames
;
490 /* The name that appeared in the last .file directive written by
491 mips_output_filename, or "" if mips_output_filename hasn't
492 written anything yet. */
493 const char *current_function_file
= "";
495 /* Arrays that map GCC register numbers to debugger register numbers. */
496 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
497 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
499 /* Information about the current function's epilogue, used only while
502 /* A list of queued REG_CFA_RESTORE notes. */
505 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
507 HOST_WIDE_INT cfa_offset
;
509 /* The offset of the CFA from the stack pointer while restoring
511 HOST_WIDE_INT cfa_restore_sp_offset
;
514 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
515 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
516 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
517 struct mips_asm_switch mips_noat
= { "at", 0 };
519 /* True if we're writing out a branch-likely instruction rather than a
521 static bool mips_branch_likely
;
523 /* The current instruction-set architecture. */
524 enum processor mips_arch
;
525 const struct mips_cpu_info
*mips_arch_info
;
527 /* The processor that we should tune the code for. */
528 enum processor mips_tune
;
529 const struct mips_cpu_info
*mips_tune_info
;
531 /* The ISA level associated with mips_arch. */
534 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
535 static const struct mips_cpu_info
*mips_isa_option_info
;
537 /* Which cost information to use. */
538 static const struct mips_rtx_cost_data
*mips_cost
;
540 /* The ambient target flags, excluding MASK_MIPS16. */
541 static int mips_base_target_flags
;
543 /* True if MIPS16 is the default mode. */
544 bool mips_base_mips16
;
546 /* The ambient values of other global variables. */
547 static int mips_base_schedule_insns
; /* flag_schedule_insns */
548 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
549 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
550 static int mips_base_align_loops
; /* align_loops */
551 static int mips_base_align_jumps
; /* align_jumps */
552 static int mips_base_align_functions
; /* align_functions */
554 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
555 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
557 /* Index C is true if character C is a valid PRINT_OPERAND punctation
559 static bool mips_print_operand_punct
[256];
561 static GTY (()) int mips_output_filename_first_time
= 1;
563 /* mips_split_p[X] is true if symbols of type X can be split by
564 mips_split_symbol. */
565 bool mips_split_p
[NUM_SYMBOL_TYPES
];
567 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
568 can be split by mips_split_symbol. */
569 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
571 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
572 forced into a PC-relative constant pool. */
573 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
575 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
576 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
577 if they are matched by a special .md file pattern. */
578 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
580 /* Likewise for HIGHs. */
581 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
583 /* Target state for MIPS16. */
584 struct target_globals
*mips16_globals
;
586 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
587 and returned from mips_sched_reorder2. */
588 static int cached_can_issue_more
;
590 /* True if the output uses __mips16_rdhwr. */
591 static bool mips_need_mips16_rdhwr_p
;
593 /* Index R is the smallest register class that contains register R. */
594 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
595 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
596 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
597 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
598 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
599 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
600 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
601 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
602 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
603 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
604 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
605 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
606 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
607 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
608 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
609 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
610 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
611 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
612 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
613 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
614 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
615 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
616 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
617 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
618 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
619 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
620 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
621 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
622 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
623 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
624 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
625 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
626 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
627 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
628 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
629 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
630 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
631 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
632 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
633 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
634 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
635 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
636 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
637 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
638 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
639 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
640 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
641 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
644 /* The value of TARGET_ATTRIBUTE_TABLE. */
645 static const struct attribute_spec mips_attribute_table
[] = {
646 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
648 { "long_call", 0, 0, false, true, true, NULL
, false },
649 { "far", 0, 0, false, true, true, NULL
, false },
650 { "near", 0, 0, false, true, true, NULL
, false },
651 /* We would really like to treat "mips16" and "nomips16" as type
652 attributes, but GCC doesn't provide the hooks we need to support
653 the right conversion rules. As declaration attributes, they affect
654 code generation but don't carry other semantics. */
655 { "mips16", 0, 0, true, false, false, NULL
, false },
656 { "nomips16", 0, 0, true, false, false, NULL
, false },
657 /* Allow functions to be specified as interrupt handlers */
658 { "interrupt", 0, 0, false, true, true, NULL
, false },
659 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
660 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
661 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
662 { NULL
, 0, 0, false, false, false, NULL
, false }
665 /* A table describing all the processors GCC knows about; see
666 mips-cpus.def for details. */
667 static const struct mips_cpu_info mips_cpu_info_table
[] = {
668 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
669 { NAME, CPU, ISA, FLAGS },
670 #include "mips-cpus.def"
674 /* Default costs. If these are used for a processor we should look
675 up the actual costs. */
676 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
677 COSTS_N_INSNS (7), /* fp_mult_sf */ \
678 COSTS_N_INSNS (8), /* fp_mult_df */ \
679 COSTS_N_INSNS (23), /* fp_div_sf */ \
680 COSTS_N_INSNS (36), /* fp_div_df */ \
681 COSTS_N_INSNS (10), /* int_mult_si */ \
682 COSTS_N_INSNS (10), /* int_mult_di */ \
683 COSTS_N_INSNS (69), /* int_div_si */ \
684 COSTS_N_INSNS (69), /* int_div_di */ \
685 2, /* branch_cost */ \
686 4 /* memory_latency */
688 /* Floating-point costs for processors without an FPU. Just assume that
689 all floating-point libcalls are very expensive. */
690 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
691 COSTS_N_INSNS (256), /* fp_mult_sf */ \
692 COSTS_N_INSNS (256), /* fp_mult_df */ \
693 COSTS_N_INSNS (256), /* fp_div_sf */ \
694 COSTS_N_INSNS (256) /* fp_div_df */
696 /* Costs to use when optimizing for size. */
697 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
698 COSTS_N_INSNS (1), /* fp_add */
699 COSTS_N_INSNS (1), /* fp_mult_sf */
700 COSTS_N_INSNS (1), /* fp_mult_df */
701 COSTS_N_INSNS (1), /* fp_div_sf */
702 COSTS_N_INSNS (1), /* fp_div_df */
703 COSTS_N_INSNS (1), /* int_mult_si */
704 COSTS_N_INSNS (1), /* int_mult_di */
705 COSTS_N_INSNS (1), /* int_div_si */
706 COSTS_N_INSNS (1), /* int_div_di */
708 4 /* memory_latency */
711 /* Costs to use when optimizing for speed, indexed by processor. */
712 static const struct mips_rtx_cost_data
713 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
715 COSTS_N_INSNS (2), /* fp_add */
716 COSTS_N_INSNS (4), /* fp_mult_sf */
717 COSTS_N_INSNS (5), /* fp_mult_df */
718 COSTS_N_INSNS (12), /* fp_div_sf */
719 COSTS_N_INSNS (19), /* fp_div_df */
720 COSTS_N_INSNS (12), /* int_mult_si */
721 COSTS_N_INSNS (12), /* int_mult_di */
722 COSTS_N_INSNS (35), /* int_div_si */
723 COSTS_N_INSNS (35), /* int_div_di */
725 4 /* memory_latency */
729 COSTS_N_INSNS (6), /* int_mult_si */
730 COSTS_N_INSNS (6), /* int_mult_di */
731 COSTS_N_INSNS (36), /* int_div_si */
732 COSTS_N_INSNS (36), /* int_div_di */
734 4 /* memory_latency */
738 COSTS_N_INSNS (36), /* int_mult_si */
739 COSTS_N_INSNS (36), /* int_mult_di */
740 COSTS_N_INSNS (37), /* int_div_si */
741 COSTS_N_INSNS (37), /* int_div_di */
743 4 /* memory_latency */
747 COSTS_N_INSNS (4), /* int_mult_si */
748 COSTS_N_INSNS (11), /* int_mult_di */
749 COSTS_N_INSNS (36), /* int_div_si */
750 COSTS_N_INSNS (68), /* int_div_di */
752 4 /* memory_latency */
755 COSTS_N_INSNS (4), /* fp_add */
756 COSTS_N_INSNS (4), /* fp_mult_sf */
757 COSTS_N_INSNS (5), /* fp_mult_df */
758 COSTS_N_INSNS (17), /* fp_div_sf */
759 COSTS_N_INSNS (32), /* fp_div_df */
760 COSTS_N_INSNS (4), /* int_mult_si */
761 COSTS_N_INSNS (11), /* int_mult_di */
762 COSTS_N_INSNS (36), /* int_div_si */
763 COSTS_N_INSNS (68), /* int_div_di */
765 4 /* memory_latency */
768 COSTS_N_INSNS (4), /* fp_add */
769 COSTS_N_INSNS (4), /* fp_mult_sf */
770 COSTS_N_INSNS (5), /* fp_mult_df */
771 COSTS_N_INSNS (17), /* fp_div_sf */
772 COSTS_N_INSNS (32), /* fp_div_df */
773 COSTS_N_INSNS (4), /* int_mult_si */
774 COSTS_N_INSNS (7), /* int_mult_di */
775 COSTS_N_INSNS (42), /* int_div_si */
776 COSTS_N_INSNS (72), /* int_div_di */
778 4 /* memory_latency */
782 COSTS_N_INSNS (5), /* int_mult_si */
783 COSTS_N_INSNS (5), /* int_mult_di */
784 COSTS_N_INSNS (41), /* int_div_si */
785 COSTS_N_INSNS (41), /* int_div_di */
787 4 /* memory_latency */
790 COSTS_N_INSNS (8), /* fp_add */
791 COSTS_N_INSNS (8), /* fp_mult_sf */
792 COSTS_N_INSNS (10), /* fp_mult_df */
793 COSTS_N_INSNS (34), /* fp_div_sf */
794 COSTS_N_INSNS (64), /* fp_div_df */
795 COSTS_N_INSNS (5), /* int_mult_si */
796 COSTS_N_INSNS (5), /* int_mult_di */
797 COSTS_N_INSNS (41), /* int_div_si */
798 COSTS_N_INSNS (41), /* int_div_di */
800 4 /* memory_latency */
803 COSTS_N_INSNS (4), /* fp_add */
804 COSTS_N_INSNS (4), /* fp_mult_sf */
805 COSTS_N_INSNS (5), /* fp_mult_df */
806 COSTS_N_INSNS (17), /* fp_div_sf */
807 COSTS_N_INSNS (32), /* fp_div_df */
808 COSTS_N_INSNS (5), /* int_mult_si */
809 COSTS_N_INSNS (5), /* int_mult_di */
810 COSTS_N_INSNS (41), /* int_div_si */
811 COSTS_N_INSNS (41), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (5), /* int_mult_si */
818 COSTS_N_INSNS (5), /* int_mult_di */
819 COSTS_N_INSNS (41), /* int_div_si */
820 COSTS_N_INSNS (41), /* int_div_di */
822 4 /* memory_latency */
825 COSTS_N_INSNS (8), /* fp_add */
826 COSTS_N_INSNS (8), /* fp_mult_sf */
827 COSTS_N_INSNS (10), /* fp_mult_df */
828 COSTS_N_INSNS (34), /* fp_div_sf */
829 COSTS_N_INSNS (64), /* fp_div_df */
830 COSTS_N_INSNS (5), /* int_mult_si */
831 COSTS_N_INSNS (5), /* int_mult_di */
832 COSTS_N_INSNS (41), /* int_div_si */
833 COSTS_N_INSNS (41), /* int_div_di */
835 4 /* memory_latency */
838 COSTS_N_INSNS (4), /* fp_add */
839 COSTS_N_INSNS (4), /* fp_mult_sf */
840 COSTS_N_INSNS (5), /* fp_mult_df */
841 COSTS_N_INSNS (17), /* fp_div_sf */
842 COSTS_N_INSNS (32), /* fp_div_df */
843 COSTS_N_INSNS (5), /* int_mult_si */
844 COSTS_N_INSNS (5), /* int_mult_di */
845 COSTS_N_INSNS (41), /* int_div_si */
846 COSTS_N_INSNS (41), /* int_div_di */
848 4 /* memory_latency */
851 COSTS_N_INSNS (6), /* fp_add */
852 COSTS_N_INSNS (6), /* fp_mult_sf */
853 COSTS_N_INSNS (7), /* fp_mult_df */
854 COSTS_N_INSNS (25), /* fp_div_sf */
855 COSTS_N_INSNS (48), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
878 COSTS_N_INSNS (5), /* int_mult_si */
879 COSTS_N_INSNS (5), /* int_mult_di */
880 COSTS_N_INSNS (72), /* int_div_si */
881 COSTS_N_INSNS (72), /* int_div_di */
883 4 /* memory_latency */
888 COSTS_N_INSNS (6), /* int_mult_si */
889 COSTS_N_INSNS (6), /* int_mult_di */
890 COSTS_N_INSNS (18), /* int_div_si */
891 COSTS_N_INSNS (35), /* int_div_di */
893 4 /* memory_latency */
896 COSTS_N_INSNS (2), /* fp_add */
897 COSTS_N_INSNS (4), /* fp_mult_sf */
898 COSTS_N_INSNS (5), /* fp_mult_df */
899 COSTS_N_INSNS (12), /* fp_div_sf */
900 COSTS_N_INSNS (19), /* fp_div_df */
901 COSTS_N_INSNS (2), /* int_mult_si */
902 COSTS_N_INSNS (2), /* int_mult_di */
903 COSTS_N_INSNS (35), /* int_div_si */
904 COSTS_N_INSNS (35), /* int_div_di */
906 4 /* memory_latency */
909 COSTS_N_INSNS (3), /* fp_add */
910 COSTS_N_INSNS (5), /* fp_mult_sf */
911 COSTS_N_INSNS (6), /* fp_mult_df */
912 COSTS_N_INSNS (15), /* fp_div_sf */
913 COSTS_N_INSNS (16), /* fp_div_df */
914 COSTS_N_INSNS (17), /* int_mult_si */
915 COSTS_N_INSNS (17), /* int_mult_di */
916 COSTS_N_INSNS (38), /* int_div_si */
917 COSTS_N_INSNS (38), /* int_div_di */
919 6 /* memory_latency */
922 COSTS_N_INSNS (6), /* fp_add */
923 COSTS_N_INSNS (7), /* fp_mult_sf */
924 COSTS_N_INSNS (8), /* fp_mult_df */
925 COSTS_N_INSNS (23), /* fp_div_sf */
926 COSTS_N_INSNS (36), /* fp_div_df */
927 COSTS_N_INSNS (10), /* int_mult_si */
928 COSTS_N_INSNS (10), /* int_mult_di */
929 COSTS_N_INSNS (69), /* int_div_si */
930 COSTS_N_INSNS (69), /* int_div_di */
932 6 /* memory_latency */
944 /* The only costs that appear to be updated here are
945 integer multiplication. */
947 COSTS_N_INSNS (4), /* int_mult_si */
948 COSTS_N_INSNS (6), /* int_mult_di */
949 COSTS_N_INSNS (69), /* int_div_si */
950 COSTS_N_INSNS (69), /* int_div_di */
952 4 /* memory_latency */
967 COSTS_N_INSNS (6), /* fp_add */
968 COSTS_N_INSNS (4), /* fp_mult_sf */
969 COSTS_N_INSNS (5), /* fp_mult_df */
970 COSTS_N_INSNS (23), /* fp_div_sf */
971 COSTS_N_INSNS (36), /* fp_div_df */
972 COSTS_N_INSNS (5), /* int_mult_si */
973 COSTS_N_INSNS (5), /* int_mult_di */
974 COSTS_N_INSNS (36), /* int_div_si */
975 COSTS_N_INSNS (36), /* int_div_di */
977 4 /* memory_latency */
980 COSTS_N_INSNS (6), /* fp_add */
981 COSTS_N_INSNS (5), /* fp_mult_sf */
982 COSTS_N_INSNS (6), /* fp_mult_df */
983 COSTS_N_INSNS (30), /* fp_div_sf */
984 COSTS_N_INSNS (59), /* fp_div_df */
985 COSTS_N_INSNS (3), /* int_mult_si */
986 COSTS_N_INSNS (4), /* int_mult_di */
987 COSTS_N_INSNS (42), /* int_div_si */
988 COSTS_N_INSNS (74), /* int_div_di */
990 4 /* memory_latency */
993 COSTS_N_INSNS (6), /* fp_add */
994 COSTS_N_INSNS (5), /* fp_mult_sf */
995 COSTS_N_INSNS (6), /* fp_mult_df */
996 COSTS_N_INSNS (30), /* fp_div_sf */
997 COSTS_N_INSNS (59), /* fp_div_df */
998 COSTS_N_INSNS (5), /* int_mult_si */
999 COSTS_N_INSNS (9), /* int_mult_di */
1000 COSTS_N_INSNS (42), /* int_div_si */
1001 COSTS_N_INSNS (74), /* int_div_di */
1002 1, /* branch_cost */
1003 4 /* memory_latency */
1006 /* The only costs that are changed here are
1007 integer multiplication. */
1008 COSTS_N_INSNS (6), /* fp_add */
1009 COSTS_N_INSNS (7), /* fp_mult_sf */
1010 COSTS_N_INSNS (8), /* fp_mult_df */
1011 COSTS_N_INSNS (23), /* fp_div_sf */
1012 COSTS_N_INSNS (36), /* fp_div_df */
1013 COSTS_N_INSNS (5), /* int_mult_si */
1014 COSTS_N_INSNS (9), /* int_mult_di */
1015 COSTS_N_INSNS (69), /* int_div_si */
1016 COSTS_N_INSNS (69), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1024 /* The only costs that are changed here are
1025 integer multiplication. */
1026 COSTS_N_INSNS (6), /* fp_add */
1027 COSTS_N_INSNS (7), /* fp_mult_sf */
1028 COSTS_N_INSNS (8), /* fp_mult_df */
1029 COSTS_N_INSNS (23), /* fp_div_sf */
1030 COSTS_N_INSNS (36), /* fp_div_df */
1031 COSTS_N_INSNS (3), /* int_mult_si */
1032 COSTS_N_INSNS (8), /* int_mult_di */
1033 COSTS_N_INSNS (69), /* int_div_si */
1034 COSTS_N_INSNS (69), /* int_div_di */
1035 1, /* branch_cost */
1036 4 /* memory_latency */
1039 COSTS_N_INSNS (2), /* fp_add */
1040 COSTS_N_INSNS (2), /* fp_mult_sf */
1041 COSTS_N_INSNS (2), /* fp_mult_df */
1042 COSTS_N_INSNS (12), /* fp_div_sf */
1043 COSTS_N_INSNS (19), /* fp_div_df */
1044 COSTS_N_INSNS (5), /* int_mult_si */
1045 COSTS_N_INSNS (9), /* int_mult_di */
1046 COSTS_N_INSNS (34), /* int_div_si */
1047 COSTS_N_INSNS (66), /* int_div_di */
1048 1, /* branch_cost */
1049 4 /* memory_latency */
1052 /* These costs are the same as the SB-1A below. */
1053 COSTS_N_INSNS (4), /* fp_add */
1054 COSTS_N_INSNS (4), /* fp_mult_sf */
1055 COSTS_N_INSNS (4), /* fp_mult_df */
1056 COSTS_N_INSNS (24), /* fp_div_sf */
1057 COSTS_N_INSNS (32), /* fp_div_df */
1058 COSTS_N_INSNS (3), /* int_mult_si */
1059 COSTS_N_INSNS (4), /* int_mult_di */
1060 COSTS_N_INSNS (36), /* int_div_si */
1061 COSTS_N_INSNS (68), /* int_div_di */
1062 1, /* branch_cost */
1063 4 /* memory_latency */
1066 /* These costs are the same as the SB-1 above. */
1067 COSTS_N_INSNS (4), /* fp_add */
1068 COSTS_N_INSNS (4), /* fp_mult_sf */
1069 COSTS_N_INSNS (4), /* fp_mult_df */
1070 COSTS_N_INSNS (24), /* fp_div_sf */
1071 COSTS_N_INSNS (32), /* fp_div_df */
1072 COSTS_N_INSNS (3), /* int_mult_si */
1073 COSTS_N_INSNS (4), /* int_mult_di */
1074 COSTS_N_INSNS (36), /* int_div_si */
1075 COSTS_N_INSNS (68), /* int_div_di */
1076 1, /* branch_cost */
1077 4 /* memory_latency */
1084 COSTS_N_INSNS (8), /* int_mult_si */
1085 COSTS_N_INSNS (8), /* int_mult_di */
1086 COSTS_N_INSNS (72), /* int_div_si */
1087 COSTS_N_INSNS (72), /* int_div_di */
1088 1, /* branch_cost */
1089 4 /* memory_latency */
1092 /* These costs are the same as 5KF above. */
1093 COSTS_N_INSNS (4), /* fp_add */
1094 COSTS_N_INSNS (4), /* fp_mult_sf */
1095 COSTS_N_INSNS (5), /* fp_mult_df */
1096 COSTS_N_INSNS (17), /* fp_div_sf */
1097 COSTS_N_INSNS (32), /* fp_div_df */
1098 COSTS_N_INSNS (4), /* int_mult_si */
1099 COSTS_N_INSNS (11), /* int_mult_di */
1100 COSTS_N_INSNS (36), /* int_div_si */
1101 COSTS_N_INSNS (68), /* int_div_di */
1102 1, /* branch_cost */
1103 4 /* memory_latency */
1107 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1108 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1110 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1112 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1113 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1114 struct GTY (()) mflip_mips16_entry
{
1118 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1120 /* Hash table callbacks for mflip_mips16_htab. */
1123 mflip_mips16_htab_hash (const void *entry
)
1125 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1129 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1131 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1132 (const char *) name
) == 0;
1135 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1136 mode, false if it should next add an attribute for the opposite mode. */
1137 static GTY(()) bool mips16_flipper
;
1139 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1140 for -mflip-mips16. Return true if it should use "mips16" and false if
1141 it should use "nomips16". */
1144 mflip_mips16_use_mips16_p (tree decl
)
1146 struct mflip_mips16_entry
*entry
;
1151 /* Use the opposite of the command-line setting for anonymous decls. */
1152 if (!DECL_NAME (decl
))
1153 return !mips_base_mips16
;
1155 if (!mflip_mips16_htab
)
1156 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1157 mflip_mips16_htab_eq
, NULL
);
1159 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1160 hash
= htab_hash_string (name
);
1161 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1162 entry
= (struct mflip_mips16_entry
*) *slot
;
1165 mips16_flipper
= !mips16_flipper
;
1166 entry
= ggc_alloc_mflip_mips16_entry ();
1168 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1171 return entry
->mips16_p
;
1174 /* Predicates to test for presence of "near" and "far"/"long_call"
1175 attributes on the given TYPE. */
1178 mips_near_type_p (const_tree type
)
1180 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1184 mips_far_type_p (const_tree type
)
1186 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1187 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1190 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1193 mips_mips16_decl_p (const_tree decl
)
1195 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1199 mips_nomips16_decl_p (const_tree decl
)
1201 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1204 /* Check if the interrupt attribute is set for a function. */
1207 mips_interrupt_type_p (tree type
)
1209 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1212 /* Check if the attribute to use shadow register set is set for a function. */
1215 mips_use_shadow_register_set_p (tree type
)
1217 return lookup_attribute ("use_shadow_register_set",
1218 TYPE_ATTRIBUTES (type
)) != NULL
;
1221 /* Check if the attribute to keep interrupts masked is set for a function. */
1224 mips_keep_interrupts_masked_p (tree type
)
1226 return lookup_attribute ("keep_interrupts_masked",
1227 TYPE_ATTRIBUTES (type
)) != NULL
;
1230 /* Check if the attribute to use debug exception return is set for
1234 mips_use_debug_exception_return_p (tree type
)
1236 return lookup_attribute ("use_debug_exception_return",
1237 TYPE_ATTRIBUTES (type
)) != NULL
;
1240 /* Return true if function DECL is a MIPS16 function. Return the ambient
1241 setting if DECL is null. */
1244 mips_use_mips16_mode_p (tree decl
)
1248 /* Nested functions must use the same frame pointer as their
1249 parent and must therefore use the same ISA mode. */
1250 tree parent
= decl_function_context (decl
);
1253 if (mips_mips16_decl_p (decl
))
1255 if (mips_nomips16_decl_p (decl
))
1258 return mips_base_mips16
;
1261 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1264 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1266 /* Disallow mixed near/far attributes. */
1267 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1269 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1274 /* Implement TARGET_INSERT_ATTRIBUTES. */
1277 mips_insert_attributes (tree decl
, tree
*attributes
)
1280 bool mips16_p
, nomips16_p
;
1282 /* Check for "mips16" and "nomips16" attributes. */
1283 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1284 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1285 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1288 error ("%qs attribute only applies to functions", "mips16");
1290 error ("%qs attribute only applies to functions", "nomips16");
1294 mips16_p
|= mips_mips16_decl_p (decl
);
1295 nomips16_p
|= mips_nomips16_decl_p (decl
);
1296 if (mips16_p
|| nomips16_p
)
1298 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1299 if (mips16_p
&& nomips16_p
)
1300 error ("%qE cannot have both %<mips16%> and "
1301 "%<nomips16%> attributes",
1304 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1306 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1307 "mips16" attribute, arbitrarily pick one. We must pick the same
1308 setting for duplicate declarations of a function. */
1309 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1310 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1315 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1318 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1320 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1321 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1322 error ("%qE redeclared with conflicting %qs attributes",
1323 DECL_NAME (newdecl
), "mips16");
1324 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1325 error ("%qE redeclared with conflicting %qs attributes",
1326 DECL_NAME (newdecl
), "nomips16");
1328 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1329 DECL_ATTRIBUTES (newdecl
));
1332 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1333 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1336 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1338 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1340 *base_ptr
= XEXP (x
, 0);
1341 *offset_ptr
= INTVAL (XEXP (x
, 1));
1350 static unsigned int mips_build_integer (struct mips_integer_op
*,
1351 unsigned HOST_WIDE_INT
);
1353 /* A subroutine of mips_build_integer, with the same interface.
1354 Assume that the final action in the sequence should be a left shift. */
1357 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1359 unsigned int i
, shift
;
1361 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1362 since signed numbers are easier to load than unsigned ones. */
1364 while ((value
& 1) == 0)
1365 value
/= 2, shift
++;
1367 i
= mips_build_integer (codes
, value
);
1368 codes
[i
].code
= ASHIFT
;
1369 codes
[i
].value
= shift
;
1373 /* As for mips_build_shift, but assume that the final action will be
1374 an IOR or PLUS operation. */
1377 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1379 unsigned HOST_WIDE_INT high
;
1382 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1383 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1385 /* The constant is too complex to load with a simple LUI/ORI pair,
1386 so we want to give the recursive call as many trailing zeros as
1387 possible. In this case, we know bit 16 is set and that the
1388 low 16 bits form a negative number. If we subtract that number
1389 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1390 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1391 codes
[i
].code
= PLUS
;
1392 codes
[i
].value
= CONST_LOW_PART (value
);
1396 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1397 bits gives a value with at least 17 trailing zeros. */
1398 i
= mips_build_integer (codes
, high
);
1399 codes
[i
].code
= IOR
;
1400 codes
[i
].value
= value
& 0xffff;
1405 /* Fill CODES with a sequence of rtl operations to load VALUE.
1406 Return the number of operations needed. */
1409 mips_build_integer (struct mips_integer_op
*codes
,
1410 unsigned HOST_WIDE_INT value
)
1412 if (SMALL_OPERAND (value
)
1413 || SMALL_OPERAND_UNSIGNED (value
)
1414 || LUI_OPERAND (value
))
1416 /* The value can be loaded with a single instruction. */
1417 codes
[0].code
= UNKNOWN
;
1418 codes
[0].value
= value
;
1421 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1423 /* Either the constant is a simple LUI/ORI combination or its
1424 lowest bit is set. We don't want to shift in this case. */
1425 return mips_build_lower (codes
, value
);
1427 else if ((value
& 0xffff) == 0)
1429 /* The constant will need at least three actions. The lowest
1430 16 bits are clear, so the final action will be a shift. */
1431 return mips_build_shift (codes
, value
);
1435 /* The final action could be a shift, add or inclusive OR.
1436 Rather than use a complex condition to select the best
1437 approach, try both mips_build_shift and mips_build_lower
1438 and pick the one that gives the shortest sequence.
1439 Note that this case is only used once per constant. */
1440 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1441 unsigned int cost
, alt_cost
;
1443 cost
= mips_build_shift (codes
, value
);
1444 alt_cost
= mips_build_lower (alt_codes
, value
);
1445 if (alt_cost
< cost
)
1447 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1454 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1457 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1459 return mips_const_insns (x
) > 0;
1462 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1465 mips16_stub_function (const char *name
)
1469 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1470 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1474 /* Return true if symbols of type TYPE require a GOT access. */
1477 mips_got_symbol_type_p (enum mips_symbol_type type
)
1481 case SYMBOL_GOT_PAGE_OFST
:
1482 case SYMBOL_GOT_DISP
:
1490 /* Return true if X is a thread-local symbol. */
1493 mips_tls_symbol_p (rtx x
)
1495 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1498 /* Return true if SYMBOL_REF X is associated with a global symbol
1499 (in the STB_GLOBAL sense). */
1502 mips_global_symbol_p (const_rtx x
)
1504 const_tree decl
= SYMBOL_REF_DECL (x
);
1507 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1509 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1510 or weak symbols. Relocations in the object file will be against
1511 the target symbol, so it's that symbol's binding that matters here. */
1512 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1515 /* Return true if function X is a libgcc MIPS16 stub function. */
1518 mips16_stub_function_p (const_rtx x
)
1520 return (GET_CODE (x
) == SYMBOL_REF
1521 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1524 /* Return true if function X is a locally-defined and locally-binding
1528 mips16_local_function_p (const_rtx x
)
1530 return (GET_CODE (x
) == SYMBOL_REF
1531 && SYMBOL_REF_LOCAL_P (x
)
1532 && !SYMBOL_REF_EXTERNAL_P (x
)
1533 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x
)));
1536 /* Return true if SYMBOL_REF X binds locally. */
1539 mips_symbol_binds_local_p (const_rtx x
)
1541 return (SYMBOL_REF_DECL (x
)
1542 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1543 : SYMBOL_REF_LOCAL_P (x
));
1546 /* Return true if rtx constants of mode MODE should be put into a small
1550 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1552 return (!TARGET_EMBEDDED_DATA
1553 && TARGET_LOCAL_SDATA
1554 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1557 /* Return true if X should not be moved directly into register $25.
1558 We need this because many versions of GAS will treat "la $25,foo" as
1559 part of a call sequence and so allow a global "foo" to be lazily bound. */
1562 mips_dangerous_for_la25_p (rtx x
)
1564 return (!TARGET_EXPLICIT_RELOCS
1566 && GET_CODE (x
) == SYMBOL_REF
1567 && mips_global_symbol_p (x
));
1570 /* Return true if calls to X might need $25 to be valid on entry. */
1573 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1575 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1578 /* MIPS16 stub functions are guaranteed not to use $25. */
1579 if (mips16_stub_function_p (x
))
1582 if (GET_CODE (x
) == SYMBOL_REF
)
1584 /* If PLTs and copy relocations are available, the static linker
1585 will make sure that $25 is valid on entry to the target function. */
1586 if (TARGET_ABICALLS_PIC0
)
1589 /* Locally-defined functions use absolute accesses to set up
1590 the global pointer. */
1591 if (TARGET_ABSOLUTE_ABICALLS
1592 && mips_symbol_binds_local_p (x
)
1593 && !SYMBOL_REF_EXTERNAL_P (x
))
1600 /* Return the method that should be used to access SYMBOL_REF or
1601 LABEL_REF X in context CONTEXT. */
1603 static enum mips_symbol_type
1604 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1607 return SYMBOL_GOT_DISP
;
1609 if (GET_CODE (x
) == LABEL_REF
)
1611 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1612 code and if we know that the label is in the current function's
1613 text section. LABEL_REFs are used for jump tables as well as
1614 text labels, so we must check whether jump tables live in the
1616 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1617 && !LABEL_REF_NONLOCAL_P (x
))
1618 return SYMBOL_PC_RELATIVE
;
1620 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1621 return SYMBOL_GOT_PAGE_OFST
;
1623 return SYMBOL_ABSOLUTE
;
1626 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1628 if (SYMBOL_REF_TLS_MODEL (x
))
1631 if (CONSTANT_POOL_ADDRESS_P (x
))
1633 if (TARGET_MIPS16_TEXT_LOADS
)
1634 return SYMBOL_PC_RELATIVE
;
1636 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1637 return SYMBOL_PC_RELATIVE
;
1639 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1640 return SYMBOL_GP_RELATIVE
;
1643 /* Do not use small-data accesses for weak symbols; they may end up
1645 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1646 return SYMBOL_GP_RELATIVE
;
1648 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1650 if (TARGET_ABICALLS_PIC2
1651 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1653 /* There are three cases to consider:
1655 - o32 PIC (either with or without explicit relocs)
1656 - n32/n64 PIC without explicit relocs
1657 - n32/n64 PIC with explicit relocs
1659 In the first case, both local and global accesses will use an
1660 R_MIPS_GOT16 relocation. We must correctly predict which of
1661 the two semantics (local or global) the assembler and linker
1662 will apply. The choice depends on the symbol's binding rather
1663 than its visibility.
1665 In the second case, the assembler will not use R_MIPS_GOT16
1666 relocations, but it chooses between local and global accesses
1667 in the same way as for o32 PIC.
1669 In the third case we have more freedom since both forms of
1670 access will work for any kind of symbol. However, there seems
1671 little point in doing things differently. */
1672 if (mips_global_symbol_p (x
))
1673 return SYMBOL_GOT_DISP
;
1675 return SYMBOL_GOT_PAGE_OFST
;
1678 return SYMBOL_ABSOLUTE
;
1681 /* Classify the base of symbolic expression X, given that X appears in
1684 static enum mips_symbol_type
1685 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1689 split_const (x
, &x
, &offset
);
1690 if (UNSPEC_ADDRESS_P (x
))
1691 return UNSPEC_ADDRESS_TYPE (x
);
1693 return mips_classify_symbol (x
, context
);
1696 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1697 is the alignment in bytes of SYMBOL_REF X. */
1700 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1702 HOST_WIDE_INT align
;
1704 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1705 return IN_RANGE (offset
, 0, align
- 1);
1708 /* Return true if X is a symbolic constant that can be used in context
1709 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1712 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1713 enum mips_symbol_type
*symbol_type
)
1717 split_const (x
, &x
, &offset
);
1718 if (UNSPEC_ADDRESS_P (x
))
1720 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1721 x
= UNSPEC_ADDRESS (x
);
1723 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1725 *symbol_type
= mips_classify_symbol (x
, context
);
1726 if (*symbol_type
== SYMBOL_TLS
)
1732 if (offset
== const0_rtx
)
1735 /* Check whether a nonzero offset is valid for the underlying
1737 switch (*symbol_type
)
1739 case SYMBOL_ABSOLUTE
:
1740 case SYMBOL_64_HIGH
:
1743 /* If the target has 64-bit pointers and the object file only
1744 supports 32-bit symbols, the values of those symbols will be
1745 sign-extended. In this case we can't allow an arbitrary offset
1746 in case the 32-bit value X + OFFSET has a different sign from X. */
1747 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1748 return offset_within_block_p (x
, INTVAL (offset
));
1750 /* In other cases the relocations can handle any offset. */
1753 case SYMBOL_PC_RELATIVE
:
1754 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1755 In this case, we no longer have access to the underlying constant,
1756 but the original symbol-based access was known to be valid. */
1757 if (GET_CODE (x
) == LABEL_REF
)
1762 case SYMBOL_GP_RELATIVE
:
1763 /* Make sure that the offset refers to something within the
1764 same object block. This should guarantee that the final
1765 PC- or GP-relative offset is within the 16-bit limit. */
1766 return offset_within_block_p (x
, INTVAL (offset
));
1768 case SYMBOL_GOT_PAGE_OFST
:
1769 case SYMBOL_GOTOFF_PAGE
:
1770 /* If the symbol is global, the GOT entry will contain the symbol's
1771 address, and we will apply a 16-bit offset after loading it.
1772 If the symbol is local, the linker should provide enough local
1773 GOT entries for a 16-bit offset, but larger offsets may lead
1775 return SMALL_INT (offset
);
1779 /* There is no carry between the HI and LO REL relocations, so the
1780 offset is only valid if we know it won't lead to such a carry. */
1781 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1783 case SYMBOL_GOT_DISP
:
1784 case SYMBOL_GOTOFF_DISP
:
1785 case SYMBOL_GOTOFF_CALL
:
1786 case SYMBOL_GOTOFF_LOADGP
:
1789 case SYMBOL_GOTTPREL
:
1797 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1798 single instruction. We rely on the fact that, in the worst case,
1799 all instructions involved in a MIPS16 address calculation are usually
1803 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1805 if (mips_use_pcrel_pool_p
[(int) type
])
1807 if (mode
== MAX_MACHINE_MODE
)
1808 /* LEAs will be converted into constant-pool references by
1810 type
= SYMBOL_PC_RELATIVE
;
1812 /* The constant must be loaded and then dereferenced. */
1818 case SYMBOL_ABSOLUTE
:
1819 /* When using 64-bit symbols, we need 5 preparatory instructions,
1822 lui $at,%highest(symbol)
1823 daddiu $at,$at,%higher(symbol)
1825 daddiu $at,$at,%hi(symbol)
1828 The final address is then $at + %lo(symbol). With 32-bit
1829 symbols we just need a preparatory LUI for normal mode and
1830 a preparatory LI and SLL for MIPS16. */
1831 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1833 case SYMBOL_GP_RELATIVE
:
1834 /* Treat GP-relative accesses as taking a single instruction on
1835 MIPS16 too; the copy of $gp can often be shared. */
1838 case SYMBOL_PC_RELATIVE
:
1839 /* PC-relative constants can be only be used with ADDIUPC,
1840 DADDIUPC, LWPC and LDPC. */
1841 if (mode
== MAX_MACHINE_MODE
1842 || GET_MODE_SIZE (mode
) == 4
1843 || GET_MODE_SIZE (mode
) == 8)
1846 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1849 case SYMBOL_GOT_DISP
:
1850 /* The constant will have to be loaded from the GOT before it
1851 is used in an address. */
1852 if (mode
!= MAX_MACHINE_MODE
)
1857 case SYMBOL_GOT_PAGE_OFST
:
1858 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1859 local/global classification is accurate. The worst cases are:
1861 (1) For local symbols when generating o32 or o64 code. The assembler
1867 ...and the final address will be $at + %lo(symbol).
1869 (2) For global symbols when -mxgot. The assembler will use:
1871 lui $at,%got_hi(symbol)
1874 ...and the final address will be $at + %got_lo(symbol). */
1877 case SYMBOL_GOTOFF_PAGE
:
1878 case SYMBOL_GOTOFF_DISP
:
1879 case SYMBOL_GOTOFF_CALL
:
1880 case SYMBOL_GOTOFF_LOADGP
:
1881 case SYMBOL_64_HIGH
:
1887 case SYMBOL_GOTTPREL
:
1890 /* A 16-bit constant formed by a single relocation, or a 32-bit
1891 constant formed from a high 16-bit relocation and a low 16-bit
1892 relocation. Use mips_split_p to determine which. 32-bit
1893 constants need an "lui; addiu" sequence for normal mode and
1894 an "li; sll; addiu" sequence for MIPS16 mode. */
1895 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1898 /* We don't treat a bare TLS symbol as a constant. */
1904 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1905 to load symbols of type TYPE into a register. Return 0 if the given
1906 type of symbol cannot be used as an immediate operand.
1908 Otherwise, return the number of instructions needed to load or store
1909 values of mode MODE to or from addresses of type TYPE. Return 0 if
1910 the given type of symbol is not valid in addresses.
1912 In both cases, treat extended MIPS16 instructions as two instructions. */
1915 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1917 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1920 /* A for_each_rtx callback. Stop the search if *X references a
1921 thread-local symbol. */
1924 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1926 return mips_tls_symbol_p (*x
);
1929 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1932 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
1934 enum mips_symbol_type type
;
1937 /* There is no assembler syntax for expressing an address-sized
1939 if (GET_CODE (x
) == HIGH
)
1942 /* As an optimization, reject constants that mips_legitimize_move
1945 Suppose we have a multi-instruction sequence that loads constant C
1946 into register R. If R does not get allocated a hard register, and
1947 R is used in an operand that allows both registers and memory
1948 references, reload will consider forcing C into memory and using
1949 one of the instruction's memory alternatives. Returning false
1950 here will force it to use an input reload instead. */
1951 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
1954 split_const (x
, &base
, &offset
);
1955 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
1957 /* See whether we explicitly want these symbols in the pool. */
1958 if (mips_use_pcrel_pool_p
[(int) type
])
1961 /* The same optimization as for CONST_INT. */
1962 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
1965 /* If MIPS16 constant pools live in the text section, they should
1966 not refer to anything that might need run-time relocation. */
1967 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
1971 /* TLS symbols must be computed by mips_legitimize_move. */
1972 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
1978 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1979 constants when we're using a per-function constant pool. */
1982 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1983 const_rtx x ATTRIBUTE_UNUSED
)
1985 return !TARGET_MIPS16_PCREL_LOADS
;
1988 /* Return true if register REGNO is a valid base register for mode MODE.
1989 STRICT_P is true if REG_OK_STRICT is in effect. */
1992 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
1995 if (!HARD_REGISTER_NUM_P (regno
))
1999 regno
= reg_renumber
[regno
];
2002 /* These fake registers will be eliminated to either the stack or
2003 hard frame pointer, both of which are usually valid base registers.
2004 Reload deals with the cases where the eliminated form isn't valid. */
2005 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2008 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2009 values, nothing smaller. There are two problems here:
2011 (a) Instantiating virtual registers can introduce new uses of the
2012 stack pointer. If these virtual registers are valid addresses,
2013 the stack pointer should be too.
2015 (b) Most uses of the stack pointer are not made explicit until
2016 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2017 We don't know until that stage whether we'll be eliminating to the
2018 stack pointer (which needs the restriction) or the hard frame
2019 pointer (which doesn't).
2021 All in all, it seems more consistent to only enforce this restriction
2022 during and after reload. */
2023 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2024 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2026 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2029 /* Return true if X is a valid base register for mode MODE.
2030 STRICT_P is true if REG_OK_STRICT is in effect. */
2033 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2035 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2039 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2042 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2043 can address a value of mode MODE. */
2046 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2048 /* Check that X is a signed 16-bit number. */
2049 if (!const_arith_operand (x
, Pmode
))
2052 /* We may need to split multiword moves, so make sure that every word
2054 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2055 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2061 /* Return true if a LO_SUM can address a value of mode MODE when the
2062 LO_SUM symbol has type SYMBOL_TYPE. */
2065 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2067 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2069 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2072 /* Check that there is a known low-part relocation. */
2073 if (mips_lo_relocs
[symbol_type
] == NULL
)
2076 /* We may need to split multiword moves, so make sure that each word
2077 can be accessed without inducing a carry. This is mainly needed
2078 for o64, which has historically only guaranteed 64-bit alignment
2079 for 128-bit types. */
2080 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2081 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2087 /* Return true if X is a valid address for machine mode MODE. If it is,
2088 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2092 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2093 enum machine_mode mode
, bool strict_p
)
2095 switch (GET_CODE (x
))
2099 info
->type
= ADDRESS_REG
;
2101 info
->offset
= const0_rtx
;
2102 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2105 info
->type
= ADDRESS_REG
;
2106 info
->reg
= XEXP (x
, 0);
2107 info
->offset
= XEXP (x
, 1);
2108 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2109 && mips_valid_offset_p (info
->offset
, mode
));
2112 info
->type
= ADDRESS_LO_SUM
;
2113 info
->reg
= XEXP (x
, 0);
2114 info
->offset
= XEXP (x
, 1);
2115 /* We have to trust the creator of the LO_SUM to do something vaguely
2116 sane. Target-independent code that creates a LO_SUM should also
2117 create and verify the matching HIGH. Target-independent code that
2118 adds an offset to a LO_SUM must prove that the offset will not
2119 induce a carry. Failure to do either of these things would be
2120 a bug, and we are not required to check for it here. The MIPS
2121 backend itself should only create LO_SUMs for valid symbolic
2122 constants, with the high part being either a HIGH or a copy
2125 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2126 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2127 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2130 /* Small-integer addresses don't occur very often, but they
2131 are legitimate if $0 is a valid base register. */
2132 info
->type
= ADDRESS_CONST_INT
;
2133 return !TARGET_MIPS16
&& SMALL_INT (x
);
2138 info
->type
= ADDRESS_SYMBOLIC
;
2139 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2141 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2142 && !mips_split_p
[info
->symbol_type
]);
2149 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2152 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2154 struct mips_address_info addr
;
2156 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2159 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2162 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2164 struct mips_address_info addr
;
2166 return (mips_classify_address (&addr
, x
, mode
, false)
2167 && addr
.type
== ADDRESS_REG
2168 && addr
.reg
== stack_pointer_rtx
);
2171 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2172 address instruction. Note that such addresses are not considered
2173 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2174 is so restricted. */
2177 mips_lwxs_address_p (rtx addr
)
2180 && GET_CODE (addr
) == PLUS
2181 && REG_P (XEXP (addr
, 1)))
2183 rtx offset
= XEXP (addr
, 0);
2184 if (GET_CODE (offset
) == MULT
2185 && REG_P (XEXP (offset
, 0))
2186 && CONST_INT_P (XEXP (offset
, 1))
2187 && INTVAL (XEXP (offset
, 1)) == 4)
2193 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2194 indexed address instruction. Note that such addresses are
2195 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2196 sense, because their use is so restricted. */
2199 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2201 if (GET_CODE (addr
) != PLUS
2202 || !REG_P (XEXP (addr
, 0))
2203 || !REG_P (XEXP (addr
, 1)))
2205 if (ISA_HAS_LBX
&& mode
== QImode
)
2207 if (ISA_HAS_LHX
&& mode
== HImode
)
2209 if (ISA_HAS_LWX
&& mode
== SImode
)
2211 if (ISA_HAS_LDX
&& mode
== DImode
)
2216 /* Return true if a value at OFFSET bytes from base register BASE can be
2217 accessed using an unextended MIPS16 instruction. MODE is the mode of
2220 Usually the offset in an unextended instruction is a 5-bit field.
2221 The offset is unsigned and shifted left once for LH and SH, twice
2222 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2223 an 8-bit immediate field that's shifted left twice. */
2226 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2227 unsigned HOST_WIDE_INT offset
)
2229 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2231 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2232 return offset
< 256U * GET_MODE_SIZE (mode
);
2233 return offset
< 32U * GET_MODE_SIZE (mode
);
2238 /* Return the number of instructions needed to load or store a value
2239 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2240 Assume that multiword moves may need to be split into word moves
2241 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2244 For MIPS16 code, count extended instructions as two instructions. */
2247 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2249 struct mips_address_info addr
;
2252 /* BLKmode is used for single unaligned loads and stores and should
2253 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2254 meaningless, so we have to single it out as a special case one way
2256 if (mode
!= BLKmode
&& might_split_p
)
2257 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2261 if (mips_classify_address (&addr
, x
, mode
, false))
2266 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2267 UINTVAL (addr
.offset
)))
2271 case ADDRESS_LO_SUM
:
2272 return TARGET_MIPS16
? factor
* 2 : factor
;
2274 case ADDRESS_CONST_INT
:
2277 case ADDRESS_SYMBOLIC
:
2278 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2283 /* Return the number of instructions needed to load constant X.
2284 Return 0 if X isn't a valid constant. */
2287 mips_const_insns (rtx x
)
2289 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2290 enum mips_symbol_type symbol_type
;
2293 switch (GET_CODE (x
))
2296 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2298 || !mips_split_p
[symbol_type
])
2301 /* This is simply an LUI for normal mode. It is an extended
2302 LI followed by an extended SLL for MIPS16. */
2303 return TARGET_MIPS16
? 4 : 1;
2307 /* Unsigned 8-bit constants can be loaded using an unextended
2308 LI instruction. Unsigned 16-bit constants can be loaded
2309 using an extended LI. Negative constants must be loaded
2310 using LI and then negated. */
2311 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2312 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2313 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2314 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2317 return mips_build_integer (codes
, INTVAL (x
));
2321 /* Allow zeros for normal mode, where we can use $0. */
2322 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2328 /* See if we can refer to X directly. */
2329 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2330 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2332 /* Otherwise try splitting the constant into a base and offset.
2333 If the offset is a 16-bit value, we can load the base address
2334 into a register and then use (D)ADDIU to add in the offset.
2335 If the offset is larger, we can load the base and offset
2336 into separate registers and add them together with (D)ADDU.
2337 However, the latter is only possible before reload; during
2338 and after reload, we must have the option of forcing the
2339 constant into the pool instead. */
2340 split_const (x
, &x
, &offset
);
2343 int n
= mips_const_insns (x
);
2346 if (SMALL_INT (offset
))
2348 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2349 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2356 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2364 /* X is a doubleword constant that can be handled by splitting it into
2365 two words and loading each word separately. Return the number of
2366 instructions required to do this. */
2369 mips_split_const_insns (rtx x
)
2371 unsigned int low
, high
;
2373 low
= mips_const_insns (mips_subword (x
, false));
2374 high
= mips_const_insns (mips_subword (x
, true));
2375 gcc_assert (low
> 0 && high
> 0);
2379 /* Return the number of instructions needed to implement INSN,
2380 given that it loads from or stores to MEM. Count extended
2381 MIPS16 instructions as two instructions. */
2384 mips_load_store_insns (rtx mem
, rtx insn
)
2386 enum machine_mode mode
;
2390 gcc_assert (MEM_P (mem
));
2391 mode
= GET_MODE (mem
);
2393 /* Try to prove that INSN does not need to be split. */
2394 might_split_p
= true;
2395 if (GET_MODE_BITSIZE (mode
) == 64)
2397 set
= single_set (insn
);
2398 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2399 might_split_p
= false;
2402 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2405 /* Return the number of instructions needed for an integer division. */
2408 mips_idiv_insns (void)
2413 if (TARGET_CHECK_ZERO_DIV
)
2415 if (GENERATE_DIVIDE_TRAPS
)
2421 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2426 /* Emit a move from SRC to DEST. Assume that the move expanders can
2427 handle all moves if !can_create_pseudo_p (). The distinction is
2428 important because, unlike emit_move_insn, the move expanders know
2429 how to force Pmode objects into the constant pool even when the
2430 constant pool address is not itself legitimate. */
2433 mips_emit_move (rtx dest
, rtx src
)
2435 return (can_create_pseudo_p ()
2436 ? emit_move_insn (dest
, src
)
2437 : emit_move_insn_1 (dest
, src
));
2440 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2443 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2445 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2446 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2449 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2450 Return that new register. */
2453 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2457 reg
= gen_reg_rtx (mode
);
2458 mips_emit_unary (code
, reg
, op0
);
2462 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2465 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2467 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2468 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2471 /* Compute (CODE OP0 OP1) and store the result in a new register
2472 of mode MODE. Return that new register. */
2475 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2479 reg
= gen_reg_rtx (mode
);
2480 mips_emit_binary (code
, reg
, op0
, op1
);
2484 /* Copy VALUE to a register and return that register. If new pseudos
2485 are allowed, copy it into a new register, otherwise use DEST. */
2488 mips_force_temporary (rtx dest
, rtx value
)
2490 if (can_create_pseudo_p ())
2491 return force_reg (Pmode
, value
);
2494 mips_emit_move (dest
, value
);
2499 /* Emit a call sequence with call pattern PATTERN and return the call
2500 instruction itself (which is not necessarily the last instruction
2501 emitted). ORIG_ADDR is the original, unlegitimized address,
2502 ADDR is the legitimized form, and LAZY_P is true if the call
2503 address is lazily-bound. */
2506 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2510 insn
= emit_call_insn (pattern
);
2512 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2514 /* MIPS16 JALRs only take MIPS16 registers. If the target
2515 function requires $25 to be valid on entry, we must copy it
2516 there separately. The move instruction can be put in the
2517 call's delay slot. */
2518 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2519 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2520 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2524 /* Lazy-binding stubs require $gp to be valid on entry. */
2525 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2529 /* See the comment above load_call<mode> for details. */
2530 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2531 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2532 emit_insn (gen_update_got_version ());
2537 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2538 then add CONST_INT OFFSET to the result. */
2541 mips_unspec_address_offset (rtx base
, rtx offset
,
2542 enum mips_symbol_type symbol_type
)
2544 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2545 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2546 if (offset
!= const0_rtx
)
2547 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2548 return gen_rtx_CONST (Pmode
, base
);
2551 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2552 type SYMBOL_TYPE. */
2555 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2559 split_const (address
, &base
, &offset
);
2560 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2563 /* If OP is an UNSPEC address, return the address to which it refers,
2564 otherwise return OP itself. */
2567 mips_strip_unspec_address (rtx op
)
2571 split_const (op
, &base
, &offset
);
2572 if (UNSPEC_ADDRESS_P (base
))
2573 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2577 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2578 high part to BASE and return the result. Just return BASE otherwise.
2579 TEMP is as for mips_force_temporary.
2581 The returned expression can be used as the first operand to a LO_SUM. */
2584 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2585 enum mips_symbol_type symbol_type
)
2587 if (mips_split_p
[symbol_type
])
2589 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2590 addr
= mips_force_temporary (temp
, addr
);
2591 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2596 /* Return an instruction that copies $gp into register REG. We want
2597 GCC to treat the register's value as constant, so that its value
2598 can be rematerialized on demand. */
2601 gen_load_const_gp (rtx reg
)
2603 return PMODE_INSN (gen_load_const_gp
, (reg
));
2606 /* Return a pseudo register that contains the value of $gp throughout
2607 the current function. Such registers are needed by MIPS16 functions,
2608 for which $gp itself is not a valid base register or addition operand. */
2611 mips16_gp_pseudo_reg (void)
2613 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2617 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2619 push_topmost_sequence ();
2621 scan
= get_insns ();
2622 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2623 scan
= NEXT_INSN (scan
);
2625 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2626 insn
= emit_insn_after (insn
, scan
);
2627 INSN_LOCATOR (insn
) = 0;
2629 pop_topmost_sequence ();
2632 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2635 /* Return a base register that holds pic_offset_table_rtx.
2636 TEMP, if nonnull, is a scratch Pmode base register. */
2639 mips_pic_base_register (rtx temp
)
2642 return pic_offset_table_rtx
;
2644 if (currently_expanding_to_rtl
)
2645 return mips16_gp_pseudo_reg ();
2647 if (can_create_pseudo_p ())
2648 temp
= gen_reg_rtx (Pmode
);
2651 /* The first post-reload split exposes all references to $gp
2652 (both uses and definitions). All references must remain
2653 explicit after that point.
2655 It is safe to introduce uses of $gp at any time, so for
2656 simplicity, we do that before the split too. */
2657 mips_emit_move (temp
, pic_offset_table_rtx
);
2659 emit_insn (gen_load_const_gp (temp
));
2663 /* Return the RHS of a load_call<mode> insn. */
2666 mips_unspec_call (rtx reg
, rtx symbol
)
2670 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2671 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2674 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2675 reference. Return NULL_RTX otherwise. */
2678 mips_strip_unspec_call (rtx src
)
2680 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2681 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2685 /* Create and return a GOT reference of type TYPE for address ADDR.
2686 TEMP, if nonnull, is a scratch Pmode base register. */
2689 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2691 rtx base
, high
, lo_sum_symbol
;
2693 base
= mips_pic_base_register (temp
);
2695 /* If we used the temporary register to load $gp, we can't use
2696 it for the high part as well. */
2697 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2700 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2701 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2703 if (type
== SYMBOL_GOTOFF_CALL
)
2704 return mips_unspec_call (high
, lo_sum_symbol
);
2706 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2709 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2710 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2711 constant in that context and can be split into high and low parts.
2712 If so, and if LOW_OUT is nonnull, emit the high part and store the
2713 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2715 TEMP is as for mips_force_temporary and is used to load the high
2716 part into a register.
2718 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2719 a legitimize SET_SRC for an .md pattern, otherwise the low part
2720 is guaranteed to be a legitimate address for mode MODE. */
2723 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2725 enum mips_symbol_context context
;
2726 enum mips_symbol_type symbol_type
;
2729 context
= (mode
== MAX_MACHINE_MODE
2730 ? SYMBOL_CONTEXT_LEA
2731 : SYMBOL_CONTEXT_MEM
);
2732 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2734 addr
= XEXP (addr
, 0);
2735 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2736 && mips_symbol_insns (symbol_type
, mode
) > 0
2737 && mips_split_hi_p
[symbol_type
])
2740 switch (symbol_type
)
2742 case SYMBOL_GOT_PAGE_OFST
:
2743 /* The high part of a page/ofst pair is loaded from the GOT. */
2744 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2755 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2756 && mips_symbol_insns (symbol_type
, mode
) > 0
2757 && mips_split_p
[symbol_type
])
2760 switch (symbol_type
)
2762 case SYMBOL_GOT_DISP
:
2763 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2764 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2767 case SYMBOL_GP_RELATIVE
:
2768 high
= mips_pic_base_register (temp
);
2769 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2773 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2774 high
= mips_force_temporary (temp
, high
);
2775 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2784 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2785 mips_force_temporary; it is only needed when OFFSET is not a
2789 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2791 if (!SMALL_OPERAND (offset
))
2797 /* Load the full offset into a register so that we can use
2798 an unextended instruction for the address itself. */
2799 high
= GEN_INT (offset
);
2804 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2805 The addition inside the macro CONST_HIGH_PART may cause an
2806 overflow, so we need to force a sign-extension check. */
2807 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
2808 offset
= CONST_LOW_PART (offset
);
2810 high
= mips_force_temporary (temp
, high
);
2811 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2813 return plus_constant (Pmode
, reg
, offset
);
2816 /* The __tls_get_attr symbol. */
2817 static GTY(()) rtx mips_tls_symbol
;
2819 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2820 the TLS symbol we are referencing and TYPE is the symbol type to use
2821 (either global dynamic or local dynamic). V0 is an RTX for the
2822 return value location. */
2825 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2829 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2831 if (!mips_tls_symbol
)
2832 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2834 loc
= mips_unspec_address (sym
, type
);
2838 emit_insn (gen_rtx_SET (Pmode
, a0
,
2839 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2840 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
2841 const0_rtx
, NULL_RTX
, false);
2842 RTL_CONST_CALL_P (insn
) = 1;
2843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2844 insn
= get_insns ();
2851 /* Return a pseudo register that contains the current thread pointer. */
2858 tp
= gen_reg_rtx (Pmode
);
2861 mips_need_mips16_rdhwr_p
= true;
2862 fn
= mips16_stub_function ("__mips16_rdhwr");
2863 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
2864 if (!call_insn_operand (fn
, VOIDmode
))
2865 fn
= force_reg (Pmode
, fn
);
2866 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
2869 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
2873 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2874 its address. The return value will be both a valid address and a valid
2875 SET_SRC (either a REG or a LO_SUM). */
2878 mips_legitimize_tls_address (rtx loc
)
2880 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
2881 enum tls_model model
;
2883 model
= SYMBOL_REF_TLS_MODEL (loc
);
2884 /* Only TARGET_ABICALLS code can have more than one module; other
2885 code must be be static and should not use a GOT. All TLS models
2886 reduce to local exec in this situation. */
2887 if (!TARGET_ABICALLS
)
2888 model
= TLS_MODEL_LOCAL_EXEC
;
2892 case TLS_MODEL_GLOBAL_DYNAMIC
:
2893 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2894 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2895 dest
= gen_reg_rtx (Pmode
);
2896 emit_libcall_block (insn
, dest
, v0
, loc
);
2899 case TLS_MODEL_LOCAL_DYNAMIC
:
2900 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2901 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2902 tmp1
= gen_reg_rtx (Pmode
);
2904 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2905 share the LDM result with other LD model accesses. */
2906 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2908 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2910 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
2911 if (mips_split_p
[SYMBOL_DTPREL
])
2913 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2914 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
2917 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
2918 0, 0, OPTAB_DIRECT
);
2921 case TLS_MODEL_INITIAL_EXEC
:
2922 tp
= mips_get_tp ();
2923 tmp1
= gen_reg_rtx (Pmode
);
2924 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2925 if (Pmode
== DImode
)
2926 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2928 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2929 dest
= gen_reg_rtx (Pmode
);
2930 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
2933 case TLS_MODEL_LOCAL_EXEC
:
2934 tmp1
= mips_get_tp ();
2935 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
2936 if (mips_split_p
[SYMBOL_TPREL
])
2938 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
2939 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
2942 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
2943 0, 0, OPTAB_DIRECT
);
2952 /* If X is not a valid address for mode MODE, force it into a register. */
2955 mips_force_address (rtx x
, enum machine_mode mode
)
2957 if (!mips_legitimate_address_p (mode
, x
, false))
2958 x
= force_reg (Pmode
, x
);
2962 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2963 be legitimized in a way that the generic machinery might not expect,
2964 return a new address, otherwise return NULL. MODE is the mode of
2965 the memory being accessed. */
2968 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
2969 enum machine_mode mode
)
2972 HOST_WIDE_INT offset
;
2974 if (mips_tls_symbol_p (x
))
2975 return mips_legitimize_tls_address (x
);
2977 /* See if the address can split into a high part and a LO_SUM. */
2978 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
2979 return mips_force_address (addr
, mode
);
2981 /* Handle BASE + OFFSET using mips_add_offset. */
2982 mips_split_plus (x
, &base
, &offset
);
2985 if (!mips_valid_base_register_p (base
, mode
, false))
2986 base
= copy_to_mode_reg (Pmode
, base
);
2987 addr
= mips_add_offset (NULL
, base
, offset
);
2988 return mips_force_address (addr
, mode
);
2994 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2997 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
2999 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3000 enum machine_mode mode
;
3001 unsigned int i
, num_ops
;
3004 mode
= GET_MODE (dest
);
3005 num_ops
= mips_build_integer (codes
, value
);
3007 /* Apply each binary operation to X. Invariant: X is a legitimate
3008 source operand for a SET pattern. */
3009 x
= GEN_INT (codes
[0].value
);
3010 for (i
= 1; i
< num_ops
; i
++)
3012 if (!can_create_pseudo_p ())
3014 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3018 x
= force_reg (mode
, x
);
3019 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3022 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3025 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3026 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3030 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3034 /* Split moves of big integers into smaller pieces. */
3035 if (splittable_const_int_operand (src
, mode
))
3037 mips_move_integer (dest
, dest
, INTVAL (src
));
3041 /* Split moves of symbolic constants into high/low pairs. */
3042 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3044 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3048 /* Generate the appropriate access sequences for TLS symbols. */
3049 if (mips_tls_symbol_p (src
))
3051 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3055 /* If we have (const (plus symbol offset)), and that expression cannot
3056 be forced into memory, load the symbol first and add in the offset.
3057 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3058 forced into memory, as it usually produces better code. */
3059 split_const (src
, &base
, &offset
);
3060 if (offset
!= const0_rtx
3061 && (targetm
.cannot_force_const_mem (mode
, src
)
3062 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3064 base
= mips_force_temporary (dest
, base
);
3065 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3069 src
= force_const_mem (mode
, src
);
3071 /* When using explicit relocs, constant pool references are sometimes
3072 not legitimate addresses. */
3073 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3074 mips_emit_move (dest
, src
);
3077 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3078 sequence that is valid. */
3081 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3083 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3085 mips_emit_move (dest
, force_reg (mode
, src
));
3089 /* We need to deal with constants that would be legitimate
3090 immediate_operands but aren't legitimate move_operands. */
3091 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3093 mips_legitimize_const_move (mode
, dest
, src
);
3094 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3100 /* Return true if value X in context CONTEXT is a small-data address
3101 that can be rewritten as a LO_SUM. */
3104 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3106 enum mips_symbol_type symbol_type
;
3108 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3109 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3110 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3111 && symbol_type
== SYMBOL_GP_RELATIVE
);
3114 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3115 containing MEM, or null if none. */
3118 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3120 enum mips_symbol_context context
;
3122 /* Ignore things like "g" constraints in asms. We make no particular
3123 guarantee about which symbolic constants are acceptable as asm operands
3124 versus which must be forced into a GPR. */
3125 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3130 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3135 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3136 return mips_rewrite_small_data_p (*loc
, context
);
3139 /* Return true if OP refers to small data symbols directly, not through
3143 mips_small_data_pattern_p (rtx op
)
3145 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3148 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3149 DATA is the containing MEM, or null if none. */
3152 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3154 enum mips_symbol_context context
;
3158 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3162 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3163 if (mips_rewrite_small_data_p (*loc
, context
))
3164 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3166 if (GET_CODE (*loc
) == LO_SUM
)
3172 /* Rewrite instruction pattern PATTERN so that it refers to small data
3173 using explicit relocations. */
3176 mips_rewrite_small_data (rtx pattern
)
3178 pattern
= copy_insn (pattern
);
3179 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3183 /* We need a lot of little routines to check the range of MIPS16 immediate
3187 m16_check_op (rtx op
, int low
, int high
, int mask
)
3189 return (CONST_INT_P (op
)
3190 && IN_RANGE (INTVAL (op
), low
, high
)
3191 && (INTVAL (op
) & mask
) == 0);
3195 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3197 return m16_check_op (op
, 0x1, 0x8, 0);
3201 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3203 return m16_check_op (op
, -0x8, 0x7, 0);
3207 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3209 return m16_check_op (op
, -0x7, 0x8, 0);
3213 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3215 return m16_check_op (op
, -0x10, 0xf, 0);
3219 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3221 return m16_check_op (op
, -0xf, 0x10, 0);
3225 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3227 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
3231 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3233 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
3237 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3239 return m16_check_op (op
, -0x80, 0x7f, 0);
3243 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3245 return m16_check_op (op
, -0x7f, 0x80, 0);
3249 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3251 return m16_check_op (op
, 0x0, 0xff, 0);
3255 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3257 return m16_check_op (op
, -0xff, 0x0, 0);
3261 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3263 return m16_check_op (op
, -0x1, 0xfe, 0);
3267 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3269 return m16_check_op (op
, 0x0, 0xff << 2, 3);
3273 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3275 return m16_check_op (op
, -0xff << 2, 0x0, 3);
3279 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3281 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
3285 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3287 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
3290 /* The cost of loading values from the constant pool. It should be
3291 larger than the cost of any constant we want to synthesize inline. */
3292 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3294 /* Return the cost of X when used as an operand to the MIPS16 instruction
3295 that implements CODE. Return -1 if there is no such instruction, or if
3296 X is not a valid immediate operand for it. */
3299 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3306 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3307 other shifts are extended. The shift patterns truncate the shift
3308 count to the right size, so there are no out-of-range values. */
3309 if (IN_RANGE (x
, 1, 8))
3311 return COSTS_N_INSNS (1);
3314 if (IN_RANGE (x
, -128, 127))
3316 if (SMALL_OPERAND (x
))
3317 return COSTS_N_INSNS (1);
3321 /* Like LE, but reject the always-true case. */
3325 /* We add 1 to the immediate and use SLT. */
3328 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3331 if (IN_RANGE (x
, 0, 255))
3333 if (SMALL_OPERAND_UNSIGNED (x
))
3334 return COSTS_N_INSNS (1);
3339 /* Equality comparisons with 0 are cheap. */
3349 /* Return true if there is a non-MIPS16 instruction that implements CODE
3350 and if that instruction accepts X as an immediate operand. */
3353 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3360 /* All shift counts are truncated to a valid constant. */
3365 /* Likewise rotates, if the target supports rotates at all. */
3371 /* These instructions take 16-bit unsigned immediates. */
3372 return SMALL_OPERAND_UNSIGNED (x
);
3377 /* These instructions take 16-bit signed immediates. */
3378 return SMALL_OPERAND (x
);
3384 /* The "immediate" forms of these instructions are really
3385 implemented as comparisons with register 0. */
3390 /* Likewise, meaning that the only valid immediate operand is 1. */
3394 /* We add 1 to the immediate and use SLT. */
3395 return SMALL_OPERAND (x
+ 1);
3398 /* Likewise SLTU, but reject the always-true case. */
3399 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3403 /* The bit position and size are immediate operands. */
3404 return ISA_HAS_EXT_INS
;
3407 /* By default assume that $0 can be used for 0. */
3412 /* Return the cost of binary operation X, given that the instruction
3413 sequence for a word-sized or smaller operation has cost SINGLE_COST
3414 and that the sequence of a double-word operation has cost DOUBLE_COST.
3415 If SPEED is true, optimize for speed otherwise optimize for size. */
3418 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3422 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3427 + set_src_cost (XEXP (x
, 0), speed
)
3428 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3431 /* Return the cost of floating-point multiplications of mode MODE. */
3434 mips_fp_mult_cost (enum machine_mode mode
)
3436 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3439 /* Return the cost of floating-point divisions of mode MODE. */
3442 mips_fp_div_cost (enum machine_mode mode
)
3444 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3447 /* Return the cost of sign-extending OP to mode MODE, not including the
3448 cost of OP itself. */
3451 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3454 /* Extended loads are as cheap as unextended ones. */
3457 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3458 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3461 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3462 /* We can use SEB or SEH. */
3463 return COSTS_N_INSNS (1);
3465 /* We need to use a shift left and a shift right. */
3466 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3469 /* Return the cost of zero-extending OP to mode MODE, not including the
3470 cost of OP itself. */
3473 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3476 /* Extended loads are as cheap as unextended ones. */
3479 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3480 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3481 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3483 if (GENERATE_MIPS16E
)
3484 /* We can use ZEB or ZEH. */
3485 return COSTS_N_INSNS (1);
3488 /* We need to load 0xff or 0xffff into a register and use AND. */
3489 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3491 /* We can use ANDI. */
3492 return COSTS_N_INSNS (1);
3495 /* Return the cost of moving between two registers of mode MODE,
3496 assuming that the move will be in pieces of at most UNITS bytes. */
3499 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3501 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3504 /* Return the cost of moving between two registers of mode MODE. */
3507 mips_set_reg_reg_cost (enum machine_mode mode
)
3509 switch (GET_MODE_CLASS (mode
))
3512 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3515 case MODE_COMPLEX_FLOAT
:
3516 case MODE_VECTOR_FLOAT
:
3517 if (TARGET_HARD_FLOAT
)
3518 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3522 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3526 /* Implement TARGET_RTX_COSTS. */
3529 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3530 int *total
, bool speed
)
3532 enum machine_mode mode
= GET_MODE (x
);
3533 bool float_mode_p
= FLOAT_MODE_P (mode
);
3537 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3538 appear in the instruction stream, and the cost of a comparison is
3539 really the cost of the branch or scc condition. At the time of
3540 writing, GCC only uses an explicit outer COMPARE code when optabs
3541 is testing whether a constant is expensive enough to force into a
3542 register. We want optabs to pass such constants through the MIPS
3543 expanders instead, so make all constants very cheap here. */
3544 if (outer_code
== COMPARE
)
3546 gcc_assert (CONSTANT_P (x
));
3554 /* Treat *clear_upper32-style ANDs as having zero cost in the
3555 second operand. The cost is entirely in the first operand.
3557 ??? This is needed because we would otherwise try to CSE
3558 the constant operand. Although that's the right thing for
3559 instructions that continue to be a register operation throughout
3560 compilation, it is disastrous for instructions that could
3561 later be converted into a memory operation. */
3563 && outer_code
== AND
3564 && UINTVAL (x
) == 0xffffffff)
3572 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3581 /* When not optimizing for size, we care more about the cost
3582 of hot code, and hot code is often in a loop. If a constant
3583 operand needs to be forced into a register, we will often be
3584 able to hoist the constant load out of the loop, so the load
3585 should not contribute to the cost. */
3586 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3598 if (force_to_mem_operand (x
, VOIDmode
))
3600 *total
= COSTS_N_INSNS (1);
3603 cost
= mips_const_insns (x
);
3606 /* If the constant is likely to be stored in a GPR, SETs of
3607 single-insn constants are as cheap as register sets; we
3608 never want to CSE them.
3610 Don't reduce the cost of storing a floating-point zero in
3611 FPRs. If we have a zero in an FPR for other reasons, we
3612 can get better cfg-cleanup and delayed-branch results by
3613 using it consistently, rather than using $0 sometimes and
3614 an FPR at other times. Also, moves between floating-point
3615 registers are sometimes cheaper than (D)MTC1 $0. */
3617 && outer_code
== SET
3618 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3620 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3621 want to CSE the constant itself. It is usually better to
3622 have N copies of the last operation in the sequence and one
3623 shared copy of the other operations. (Note that this is
3624 not true for MIPS16 code, where the final operation in the
3625 sequence is often an extended instruction.)
3627 Also, if we have a CONST_INT, we don't know whether it is
3628 for a word or doubleword operation, so we cannot rely on
3629 the result of mips_build_integer. */
3630 else if (!TARGET_MIPS16
3631 && (outer_code
== SET
|| mode
== VOIDmode
))
3633 *total
= COSTS_N_INSNS (cost
);
3636 /* The value will need to be fetched from the constant pool. */
3637 *total
= CONSTANT_POOL_COST
;
3641 /* If the address is legitimate, return the number of
3642 instructions it needs. */
3644 cost
= mips_address_insns (addr
, mode
, true);
3647 *total
= COSTS_N_INSNS (cost
+ 1);
3650 /* Check for a scaled indexed address. */
3651 if (mips_lwxs_address_p (addr
)
3652 || mips_lx_address_p (addr
, mode
))
3654 *total
= COSTS_N_INSNS (2);
3657 /* Otherwise use the default handling. */
3661 *total
= COSTS_N_INSNS (6);
3665 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3669 /* Check for a *clear_upper32 pattern and treat it like a zero
3670 extension. See the pattern's comment for details. */
3673 && CONST_INT_P (XEXP (x
, 1))
3674 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3676 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3677 + set_src_cost (XEXP (x
, 0), speed
));
3684 /* Double-word operations use two single-word operations. */
3685 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3694 if (CONSTANT_P (XEXP (x
, 1)))
3695 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3698 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3704 *total
= mips_cost
->fp_add
;
3706 *total
= COSTS_N_INSNS (4);
3710 /* Low-part immediates need an extended MIPS16 instruction. */
3711 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3712 + set_src_cost (XEXP (x
, 0), speed
));
3727 /* Branch comparisons have VOIDmode, so use the first operand's
3729 mode
= GET_MODE (XEXP (x
, 0));
3730 if (FLOAT_MODE_P (mode
))
3732 *total
= mips_cost
->fp_add
;
3735 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3741 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3742 && TARGET_FUSED_MADD
3743 && !HONOR_NANS (mode
)
3744 && !HONOR_SIGNED_ZEROS (mode
))
3746 /* See if we can use NMADD or NMSUB. See mips.md for the
3747 associated patterns. */
3748 rtx op0
= XEXP (x
, 0);
3749 rtx op1
= XEXP (x
, 1);
3750 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3752 *total
= (mips_fp_mult_cost (mode
)
3753 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3754 + set_src_cost (XEXP (op0
, 1), speed
)
3755 + set_src_cost (op1
, speed
));
3758 if (GET_CODE (op1
) == MULT
)
3760 *total
= (mips_fp_mult_cost (mode
)
3761 + set_src_cost (op0
, speed
)
3762 + set_src_cost (XEXP (op1
, 0), speed
)
3763 + set_src_cost (XEXP (op1
, 1), speed
));
3772 /* If this is part of a MADD or MSUB, treat the PLUS as
3775 && TARGET_FUSED_MADD
3776 && GET_CODE (XEXP (x
, 0)) == MULT
)
3779 *total
= mips_cost
->fp_add
;
3783 /* Double-word operations require three single-word operations and
3784 an SLTU. The MIPS16 version then needs to move the result of
3785 the SLTU from $24 to a MIPS16 register. */
3786 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3787 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3793 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3794 && TARGET_FUSED_MADD
3795 && !HONOR_NANS (mode
)
3796 && HONOR_SIGNED_ZEROS (mode
))
3798 /* See if we can use NMADD or NMSUB. See mips.md for the
3799 associated patterns. */
3800 rtx op
= XEXP (x
, 0);
3801 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3802 && GET_CODE (XEXP (op
, 0)) == MULT
)
3804 *total
= (mips_fp_mult_cost (mode
)
3805 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3806 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3807 + set_src_cost (XEXP (op
, 1), speed
));
3813 *total
= mips_cost
->fp_add
;
3815 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3820 *total
= mips_fp_mult_cost (mode
);
3821 else if (mode
== DImode
&& !TARGET_64BIT
)
3822 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3823 where the mulsidi3 always includes an MFHI and an MFLO. */
3825 ? mips_cost
->int_mult_si
* 3 + 6
3826 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3828 *total
= (ISA_HAS_MUL3
? 1 : 2);
3829 else if (mode
== DImode
)
3830 *total
= mips_cost
->int_mult_di
;
3832 *total
= mips_cost
->int_mult_si
;
3836 /* Check for a reciprocal. */
3839 && flag_unsafe_math_optimizations
3840 && XEXP (x
, 0) == CONST1_RTX (mode
))
3842 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3843 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3844 division as being free. */
3845 *total
= set_src_cost (XEXP (x
, 1), speed
);
3847 *total
= (mips_fp_div_cost (mode
)
3848 + set_src_cost (XEXP (x
, 1), speed
));
3857 *total
= mips_fp_div_cost (mode
);
3866 /* It is our responsibility to make division by a power of 2
3867 as cheap as 2 register additions if we want the division
3868 expanders to be used for such operations; see the setting
3869 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3870 should always produce shorter code than using
3871 expand_sdiv2_pow2. */
3873 && CONST_INT_P (XEXP (x
, 1))
3874 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3876 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
3879 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3881 else if (mode
== DImode
)
3882 *total
= mips_cost
->int_div_di
;
3884 *total
= mips_cost
->int_div_si
;
3888 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3892 if (outer_code
== SET
3894 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
3895 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
3896 && GET_MODE (XEXP (x
, 0)) == QImode
3897 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3899 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
3902 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3906 case UNSIGNED_FLOAT
:
3909 case FLOAT_TRUNCATE
:
3910 *total
= mips_cost
->fp_add
;
3914 if (register_operand (SET_DEST (x
), VOIDmode
)
3915 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
3917 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
3927 /* Implement TARGET_ADDRESS_COST. */
3930 mips_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
3932 return mips_address_insns (addr
, SImode
, false);
3935 /* Information about a single instruction in a multi-instruction
3937 struct mips_multi_member
{
3938 /* True if this is a label, false if it is code. */
3941 /* The output_asm_insn format of the instruction. */
3944 /* The operands to the instruction. */
3945 rtx operands
[MAX_RECOG_OPERANDS
];
3947 typedef struct mips_multi_member mips_multi_member
;
3949 /* Vector definitions for the above. */
3950 DEF_VEC_O(mips_multi_member
);
3951 DEF_VEC_ALLOC_O(mips_multi_member
, heap
);
3953 /* The instructions that make up the current multi-insn sequence. */
3954 static VEC (mips_multi_member
, heap
) *mips_multi_members
;
3956 /* How many instructions (as opposed to labels) are in the current
3957 multi-insn sequence. */
3958 static unsigned int mips_multi_num_insns
;
3960 /* Start a new multi-insn sequence. */
3963 mips_multi_start (void)
3965 VEC_truncate (mips_multi_member
, mips_multi_members
, 0);
3966 mips_multi_num_insns
= 0;
3969 /* Add a new, uninitialized member to the current multi-insn sequence. */
3971 static struct mips_multi_member
*
3972 mips_multi_add (void)
3974 return VEC_safe_push (mips_multi_member
, heap
, mips_multi_members
, 0);
3977 /* Add a normal insn with the given asm format to the current multi-insn
3978 sequence. The other arguments are a null-terminated list of operands. */
3981 mips_multi_add_insn (const char *format
, ...)
3983 struct mips_multi_member
*member
;
3988 member
= mips_multi_add ();
3989 member
->is_label_p
= false;
3990 member
->format
= format
;
3991 va_start (ap
, format
);
3993 while ((op
= va_arg (ap
, rtx
)))
3994 member
->operands
[i
++] = op
;
3996 mips_multi_num_insns
++;
3999 /* Add the given label definition to the current multi-insn sequence.
4000 The definition should include the colon. */
4003 mips_multi_add_label (const char *label
)
4005 struct mips_multi_member
*member
;
4007 member
= mips_multi_add ();
4008 member
->is_label_p
= true;
4009 member
->format
= label
;
4012 /* Return the index of the last member of the current multi-insn sequence. */
4015 mips_multi_last_index (void)
4017 return VEC_length (mips_multi_member
, mips_multi_members
) - 1;
4020 /* Add a copy of an existing instruction to the current multi-insn
4021 sequence. I is the index of the instruction that should be copied. */
4024 mips_multi_copy_insn (unsigned int i
)
4026 struct mips_multi_member
*member
;
4028 member
= mips_multi_add ();
4029 memcpy (member
, VEC_index (mips_multi_member
, mips_multi_members
, i
),
4031 gcc_assert (!member
->is_label_p
);
4034 /* Change the operand of an existing instruction in the current
4035 multi-insn sequence. I is the index of the instruction,
4036 OP is the index of the operand, and X is the new value. */
4039 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4041 VEC_index (mips_multi_member
, mips_multi_members
, i
)->operands
[op
] = x
;
4044 /* Write out the asm code for the current multi-insn sequence. */
4047 mips_multi_write (void)
4049 struct mips_multi_member
*member
;
4052 FOR_EACH_VEC_ELT (mips_multi_member
, mips_multi_members
, i
, member
)
4053 if (member
->is_label_p
)
4054 fprintf (asm_out_file
, "%s\n", member
->format
);
4056 output_asm_insn (member
->format
, member
->operands
);
4059 /* Return one word of double-word value OP, taking into account the fixed
4060 endianness of certain registers. HIGH_P is true to select the high part,
4061 false to select the low part. */
4064 mips_subword (rtx op
, bool high_p
)
4066 unsigned int byte
, offset
;
4067 enum machine_mode mode
;
4069 mode
= GET_MODE (op
);
4070 if (mode
== VOIDmode
)
4071 mode
= TARGET_64BIT
? TImode
: DImode
;
4073 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4074 byte
= UNITS_PER_WORD
;
4078 if (FP_REG_RTX_P (op
))
4080 /* Paired FPRs are always ordered little-endian. */
4081 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4082 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4086 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4088 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4091 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4094 mips_split_64bit_move_p (rtx dest
, rtx src
)
4099 /* FPR-to-FPR moves can be done in a single instruction, if they're
4101 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4104 /* Check for floating-point loads and stores. */
4105 if (ISA_HAS_LDC1_SDC1
)
4107 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4109 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4115 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4116 this function handles 64-bit moves for which mips_split_64bit_move_p
4117 holds. For 64-bit targets, this function handles 128-bit moves. */
4120 mips_split_doubleword_move (rtx dest
, rtx src
)
4124 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4126 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4127 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4128 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4129 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4130 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4131 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4132 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4133 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4134 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4135 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4136 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4137 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4138 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4139 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4143 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4145 low_dest
= mips_subword (dest
, false);
4146 mips_emit_move (low_dest
, mips_subword (src
, false));
4148 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4150 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4152 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4154 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4156 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4158 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4162 /* The operation can be split into two normal moves. Decide in
4163 which order to do them. */
4164 low_dest
= mips_subword (dest
, false);
4165 if (REG_P (low_dest
)
4166 && reg_overlap_mentioned_p (low_dest
, src
))
4168 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4169 mips_emit_move (low_dest
, mips_subword (src
, false));
4173 mips_emit_move (low_dest
, mips_subword (src
, false));
4174 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4179 /* Return the appropriate instructions to move SRC into DEST. Assume
4180 that SRC is operand 1 and DEST is operand 0. */
4183 mips_output_move (rtx dest
, rtx src
)
4185 enum rtx_code dest_code
, src_code
;
4186 enum machine_mode mode
;
4187 enum mips_symbol_type symbol_type
;
4190 dest_code
= GET_CODE (dest
);
4191 src_code
= GET_CODE (src
);
4192 mode
= GET_MODE (dest
);
4193 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4195 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
4198 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4199 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4201 if (dest_code
== REG
)
4203 if (GP_REG_P (REGNO (dest
)))
4204 return "move\t%0,%z1";
4206 /* Moves to HI are handled by special .md insns. */
4207 if (REGNO (dest
) == LO_REGNUM
)
4210 if (DSP_ACC_REG_P (REGNO (dest
)))
4212 static char retval
[] = "mt__\t%z1,%q0";
4214 retval
[2] = reg_names
[REGNO (dest
)][4];
4215 retval
[3] = reg_names
[REGNO (dest
)][5];
4219 if (FP_REG_P (REGNO (dest
)))
4220 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4222 if (ALL_COP_REG_P (REGNO (dest
)))
4224 static char retval
[] = "dmtc_\t%z1,%0";
4226 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4227 return dbl_p
? retval
: retval
+ 1;
4230 if (dest_code
== MEM
)
4231 switch (GET_MODE_SIZE (mode
))
4233 case 1: return "sb\t%z1,%0";
4234 case 2: return "sh\t%z1,%0";
4235 case 4: return "sw\t%z1,%0";
4236 case 8: return "sd\t%z1,%0";
4239 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4241 if (src_code
== REG
)
4243 /* Moves from HI are handled by special .md insns. */
4244 if (REGNO (src
) == LO_REGNUM
)
4246 /* When generating VR4120 or VR4130 code, we use MACC and
4247 DMACC instead of MFLO. This avoids both the normal
4248 MIPS III HI/LO hazards and the errata related to
4251 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4255 if (DSP_ACC_REG_P (REGNO (src
)))
4257 static char retval
[] = "mf__\t%0,%q1";
4259 retval
[2] = reg_names
[REGNO (src
)][4];
4260 retval
[3] = reg_names
[REGNO (src
)][5];
4264 if (FP_REG_P (REGNO (src
)))
4265 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4267 if (ALL_COP_REG_P (REGNO (src
)))
4269 static char retval
[] = "dmfc_\t%0,%1";
4271 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4272 return dbl_p
? retval
: retval
+ 1;
4275 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
4276 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4279 if (src_code
== MEM
)
4280 switch (GET_MODE_SIZE (mode
))
4282 case 1: return "lbu\t%0,%1";
4283 case 2: return "lhu\t%0,%1";
4284 case 4: return "lw\t%0,%1";
4285 case 8: return "ld\t%0,%1";
4288 if (src_code
== CONST_INT
)
4290 /* Don't use the X format for the operand itself, because that
4291 will give out-of-range numbers for 64-bit hosts and 32-bit
4294 return "li\t%0,%1\t\t\t# %X1";
4296 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4299 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4303 if (src_code
== HIGH
)
4304 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4306 if (CONST_GP_P (src
))
4307 return "move\t%0,%1";
4309 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4310 && mips_lo_relocs
[symbol_type
] != 0)
4312 /* A signed 16-bit constant formed by applying a relocation
4313 operator to a symbolic address. */
4314 gcc_assert (!mips_split_p
[symbol_type
]);
4315 return "li\t%0,%R1";
4318 if (symbolic_operand (src
, VOIDmode
))
4320 gcc_assert (TARGET_MIPS16
4321 ? TARGET_MIPS16_TEXT_LOADS
4322 : !TARGET_EXPLICIT_RELOCS
);
4323 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4326 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4328 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4330 if (GET_MODE (dest
) == V2SFmode
)
4331 return "mov.ps\t%0,%1";
4333 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4336 if (dest_code
== MEM
)
4337 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4339 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4341 if (src_code
== MEM
)
4342 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4344 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4346 static char retval
[] = "l_c_\t%0,%1";
4348 retval
[1] = (dbl_p
? 'd' : 'w');
4349 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4352 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4354 static char retval
[] = "s_c_\t%1,%0";
4356 retval
[1] = (dbl_p
? 'd' : 'w');
4357 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4363 /* Return true if CMP1 is a suitable second operand for integer ordering
4364 test CODE. See also the *sCC patterns in mips.md. */
4367 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4373 return reg_or_0_operand (cmp1
, VOIDmode
);
4377 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4381 return arith_operand (cmp1
, VOIDmode
);
4384 return sle_operand (cmp1
, VOIDmode
);
4387 return sleu_operand (cmp1
, VOIDmode
);
4394 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4395 integer ordering test *CODE, or if an equivalent combination can
4396 be formed by adjusting *CODE and *CMP1. When returning true, update
4397 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4401 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4402 enum machine_mode mode
)
4404 HOST_WIDE_INT plus_one
;
4406 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4409 if (CONST_INT_P (*cmp1
))
4413 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4414 if (INTVAL (*cmp1
) < plus_one
)
4417 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4423 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4427 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4438 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4439 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4440 is nonnull, it's OK to set TARGET to the inverse of the result and
4441 flip *INVERT_PTR instead. */
4444 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4445 rtx target
, rtx cmp0
, rtx cmp1
)
4447 enum machine_mode mode
;
4449 /* First see if there is a MIPS instruction that can do this operation.
4450 If not, try doing the same for the inverse operation. If that also
4451 fails, force CMP1 into a register and try again. */
4452 mode
= GET_MODE (cmp0
);
4453 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4454 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4457 enum rtx_code inv_code
= reverse_condition (code
);
4458 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4460 cmp1
= force_reg (mode
, cmp1
);
4461 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4463 else if (invert_ptr
== 0)
4467 inv_target
= mips_force_binary (GET_MODE (target
),
4468 inv_code
, cmp0
, cmp1
);
4469 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4473 *invert_ptr
= !*invert_ptr
;
4474 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4479 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4480 The register will have the same mode as CMP0. */
4483 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4485 if (cmp1
== const0_rtx
)
4488 if (uns_arith_operand (cmp1
, VOIDmode
))
4489 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4490 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4492 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4493 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4496 /* Convert *CODE into a code that can be used in a floating-point
4497 scc instruction (C.cond.fmt). Return true if the values of
4498 the condition code registers will be inverted, with 0 indicating
4499 that the condition holds. */
4502 mips_reversed_fp_cond (enum rtx_code
*code
)
4509 *code
= reverse_condition_maybe_unordered (*code
);
4517 /* Convert a comparison into something that can be used in a branch or
4518 conditional move. On entry, *OP0 and *OP1 are the values being
4519 compared and *CODE is the code used to compare them.
4521 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4522 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4523 otherwise any standard branch condition can be used. The standard branch
4526 - EQ or NE between two registers.
4527 - any comparison between a register and zero. */
4530 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4535 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4537 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4539 else if (*code
== EQ
|| *code
== NE
)
4543 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4547 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4551 /* The comparison needs a separate scc instruction. Store the
4552 result of the scc in *OP0 and compare it against zero. */
4553 bool invert
= false;
4554 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4555 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4556 *code
= (invert
? EQ
: NE
);
4560 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4562 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4563 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4569 enum rtx_code cmp_code
;
4571 /* Floating-point tests use a separate C.cond.fmt comparison to
4572 set a condition code register. The branch or conditional move
4573 will then compare that register against zero.
4575 Set CMP_CODE to the code of the comparison instruction and
4576 *CODE to the code that the branch or move should use. */
4578 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4580 ? gen_reg_rtx (CCmode
)
4581 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4583 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4587 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4588 and OPERAND[3]. Store the result in OPERANDS[0].
4590 On 64-bit targets, the mode of the comparison and target will always be
4591 SImode, thus possibly narrower than that of the comparison's operands. */
4594 mips_expand_scc (rtx operands
[])
4596 rtx target
= operands
[0];
4597 enum rtx_code code
= GET_CODE (operands
[1]);
4598 rtx op0
= operands
[2];
4599 rtx op1
= operands
[3];
4601 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4603 if (code
== EQ
|| code
== NE
)
4606 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4607 mips_emit_binary (code
, target
, op0
, op1
);
4610 rtx zie
= mips_zero_if_equal (op0
, op1
);
4611 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4615 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4618 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4619 CODE and jump to OPERANDS[3] if the condition holds. */
4622 mips_expand_conditional_branch (rtx
*operands
)
4624 enum rtx_code code
= GET_CODE (operands
[0]);
4625 rtx op0
= operands
[1];
4626 rtx op1
= operands
[2];
4629 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4630 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4631 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4636 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4637 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4640 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4641 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4646 reversed_p
= mips_reversed_fp_cond (&cond
);
4647 cmp_result
= gen_reg_rtx (CCV2mode
);
4648 emit_insn (gen_scc_ps (cmp_result
,
4649 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4651 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4654 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4658 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4659 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4662 mips_expand_conditional_move (rtx
*operands
)
4665 enum rtx_code code
= GET_CODE (operands
[1]);
4666 rtx op0
= XEXP (operands
[1], 0);
4667 rtx op1
= XEXP (operands
[1], 1);
4669 mips_emit_compare (&code
, &op0
, &op1
, true);
4670 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4671 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4672 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4673 operands
[2], operands
[3])));
4676 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4679 mips_expand_conditional_trap (rtx comparison
)
4682 enum machine_mode mode
;
4685 /* MIPS conditional trap instructions don't have GT or LE flavors,
4686 so we must swap the operands and convert to LT and GE respectively. */
4687 code
= GET_CODE (comparison
);
4694 code
= swap_condition (code
);
4695 op0
= XEXP (comparison
, 1);
4696 op1
= XEXP (comparison
, 0);
4700 op0
= XEXP (comparison
, 0);
4701 op1
= XEXP (comparison
, 1);
4705 mode
= GET_MODE (XEXP (comparison
, 0));
4706 op0
= force_reg (mode
, op0
);
4707 if (!arith_operand (op1
, mode
))
4708 op1
= force_reg (mode
, op1
);
4710 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4711 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4715 /* Initialize *CUM for a call to a function of type FNTYPE. */
4718 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4720 memset (cum
, 0, sizeof (*cum
));
4721 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4722 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4725 /* Fill INFO with information about a single argument. CUM is the
4726 cumulative state for earlier arguments. MODE is the mode of this
4727 argument and TYPE is its type (if known). NAMED is true if this
4728 is a named (fixed) argument rather than a variable one. */
4731 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4732 enum machine_mode mode
, const_tree type
, bool named
)
4734 bool doubleword_aligned_p
;
4735 unsigned int num_bytes
, num_words
, max_regs
;
4737 /* Work out the size of the argument. */
4738 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4739 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4741 /* Decide whether it should go in a floating-point register, assuming
4742 one is free. Later code checks for availability.
4744 The checks against UNITS_PER_FPVALUE handle the soft-float and
4745 single-float cases. */
4749 /* The EABI conventions have traditionally been defined in terms
4750 of TYPE_MODE, regardless of the actual type. */
4751 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4752 || mode
== V2SFmode
)
4753 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4758 /* Only leading floating-point scalars are passed in
4759 floating-point registers. We also handle vector floats the same
4760 say, which is OK because they are not covered by the standard ABI. */
4761 info
->fpr_p
= (!cum
->gp_reg_found
4762 && cum
->arg_number
< 2
4764 || SCALAR_FLOAT_TYPE_P (type
)
4765 || VECTOR_FLOAT_TYPE_P (type
))
4766 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4767 || mode
== V2SFmode
)
4768 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4773 /* Scalar, complex and vector floating-point types are passed in
4774 floating-point registers, as long as this is a named rather
4775 than a variable argument. */
4776 info
->fpr_p
= (named
4777 && (type
== 0 || FLOAT_TYPE_P (type
))
4778 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4779 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4780 || mode
== V2SFmode
)
4781 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4783 /* ??? According to the ABI documentation, the real and imaginary
4784 parts of complex floats should be passed in individual registers.
4785 The real and imaginary parts of stack arguments are supposed
4786 to be contiguous and there should be an extra word of padding
4789 This has two problems. First, it makes it impossible to use a
4790 single "void *" va_list type, since register and stack arguments
4791 are passed differently. (At the time of writing, MIPSpro cannot
4792 handle complex float varargs correctly.) Second, it's unclear
4793 what should happen when there is only one register free.
4795 For now, we assume that named complex floats should go into FPRs
4796 if there are two FPRs free, otherwise they should be passed in the
4797 same way as a struct containing two floats. */
4799 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4800 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4802 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4803 info
->fpr_p
= false;
4813 /* See whether the argument has doubleword alignment. */
4814 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
4817 /* Set REG_OFFSET to the register count we're interested in.
4818 The EABI allocates the floating-point registers separately,
4819 but the other ABIs allocate them like integer registers. */
4820 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4824 /* Advance to an even register if the argument is doubleword-aligned. */
4825 if (doubleword_aligned_p
)
4826 info
->reg_offset
+= info
->reg_offset
& 1;
4828 /* Work out the offset of a stack argument. */
4829 info
->stack_offset
= cum
->stack_words
;
4830 if (doubleword_aligned_p
)
4831 info
->stack_offset
+= info
->stack_offset
& 1;
4833 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4835 /* Partition the argument between registers and stack. */
4836 info
->reg_words
= MIN (num_words
, max_regs
);
4837 info
->stack_words
= num_words
- info
->reg_words
;
4840 /* INFO describes a register argument that has the normal format for the
4841 argument's mode. Return the register it uses, assuming that FPRs are
4842 available if HARD_FLOAT_P. */
4845 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4847 if (!info
->fpr_p
|| !hard_float_p
)
4848 return GP_ARG_FIRST
+ info
->reg_offset
;
4849 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4850 /* In o32, the second argument is always passed in $f14
4851 for TARGET_DOUBLE_FLOAT, regardless of whether the
4852 first argument was a word or doubleword. */
4853 return FP_ARG_FIRST
+ 2;
4855 return FP_ARG_FIRST
+ info
->reg_offset
;
4858 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4861 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
4863 return !TARGET_OLDABI
;
4866 /* Implement TARGET_FUNCTION_ARG. */
4869 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
4870 const_tree type
, bool named
)
4872 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4873 struct mips_arg_info info
;
4875 /* We will be called with a mode of VOIDmode after the last argument
4876 has been seen. Whatever we return will be passed to the call expander.
4877 If we need a MIPS16 fp_code, return a REG with the code stored as
4879 if (mode
== VOIDmode
)
4881 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4882 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4887 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4889 /* Return straight away if the whole argument is passed on the stack. */
4890 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4893 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4894 contains a double in its entirety, then that 64-bit chunk is passed
4895 in a floating-point register. */
4897 && TARGET_HARD_FLOAT
4900 && TREE_CODE (type
) == RECORD_TYPE
4901 && TYPE_SIZE_UNIT (type
)
4902 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4906 /* First check to see if there is any such field. */
4907 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
4908 if (TREE_CODE (field
) == FIELD_DECL
4909 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4910 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4911 && host_integerp (bit_position (field
), 0)
4912 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4917 /* Now handle the special case by returning a PARALLEL
4918 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4919 chunks are passed in registers. */
4921 HOST_WIDE_INT bitpos
;
4924 /* assign_parms checks the mode of ENTRY_PARM, so we must
4925 use the actual mode here. */
4926 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4929 field
= TYPE_FIELDS (type
);
4930 for (i
= 0; i
< info
.reg_words
; i
++)
4934 for (; field
; field
= DECL_CHAIN (field
))
4935 if (TREE_CODE (field
) == FIELD_DECL
4936 && int_bit_position (field
) >= bitpos
)
4940 && int_bit_position (field
) == bitpos
4941 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4942 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4943 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4945 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4948 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4949 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4951 bitpos
+= BITS_PER_WORD
;
4957 /* Handle the n32/n64 conventions for passing complex floating-point
4958 arguments in FPR pairs. The real part goes in the lower register
4959 and the imaginary part goes in the upper register. */
4962 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4965 enum machine_mode inner
;
4968 inner
= GET_MODE_INNER (mode
);
4969 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4970 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4972 /* Real part in registers, imaginary part on stack. */
4973 gcc_assert (info
.stack_words
== info
.reg_words
);
4974 return gen_rtx_REG (inner
, regno
);
4978 gcc_assert (info
.stack_words
== 0);
4979 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4980 gen_rtx_REG (inner
, regno
),
4982 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4984 regno
+ info
.reg_words
/ 2),
4985 GEN_INT (GET_MODE_SIZE (inner
)));
4986 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4990 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4993 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4996 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
4997 const_tree type
, bool named
)
4999 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5000 struct mips_arg_info info
;
5002 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5005 cum
->gp_reg_found
= true;
5007 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5008 an explanation of what this code does. It assumes that we're using
5009 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5011 if (cum
->arg_number
< 2 && info
.fpr_p
)
5012 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5014 /* Advance the register count. This has the effect of setting
5015 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5016 argument required us to skip the final GPR and pass the whole
5017 argument on the stack. */
5018 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5019 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5020 else if (info
.reg_words
> 0)
5021 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5023 /* Advance the stack word count. */
5024 if (info
.stack_words
> 0)
5025 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5030 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5033 mips_arg_partial_bytes (cumulative_args_t cum
,
5034 enum machine_mode mode
, tree type
, bool named
)
5036 struct mips_arg_info info
;
5038 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5039 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5042 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5043 least PARM_BOUNDARY bits of alignment, but will be given anything up
5044 to STACK_BOUNDARY bits if the type requires it. */
5047 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5049 unsigned int alignment
;
5051 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5052 if (alignment
< PARM_BOUNDARY
)
5053 alignment
= PARM_BOUNDARY
;
5054 if (alignment
> STACK_BOUNDARY
)
5055 alignment
= STACK_BOUNDARY
;
5059 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5060 upward rather than downward. In other words, return true if the
5061 first byte of the stack slot has useful data, false if the last
5065 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5067 /* On little-endian targets, the first byte of every stack argument
5068 is passed in the first byte of the stack slot. */
5069 if (!BYTES_BIG_ENDIAN
)
5072 /* Otherwise, integral types are padded downward: the last byte of a
5073 stack argument is passed in the last byte of the stack slot. */
5075 ? (INTEGRAL_TYPE_P (type
)
5076 || POINTER_TYPE_P (type
)
5077 || FIXED_POINT_TYPE_P (type
))
5078 : (SCALAR_INT_MODE_P (mode
)
5079 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5082 /* Big-endian o64 pads floating-point arguments downward. */
5083 if (mips_abi
== ABI_O64
)
5084 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5087 /* Other types are padded upward for o32, o64, n32 and n64. */
5088 if (mips_abi
!= ABI_EABI
)
5091 /* Arguments smaller than a stack slot are padded downward. */
5092 if (mode
!= BLKmode
)
5093 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5095 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5098 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5099 if the least significant byte of the register has useful data. Return
5100 the opposite if the most significant byte does. */
5103 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5105 /* No shifting is required for floating-point arguments. */
5106 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5107 return !BYTES_BIG_ENDIAN
;
5109 /* Otherwise, apply the same padding to register arguments as we do
5110 to stack arguments. */
5111 return mips_pad_arg_upward (mode
, type
);
5114 /* Return nonzero when an argument must be passed by reference. */
5117 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5118 enum machine_mode mode
, const_tree type
,
5119 bool named ATTRIBUTE_UNUSED
)
5121 if (mips_abi
== ABI_EABI
)
5125 /* ??? How should SCmode be handled? */
5126 if (mode
== DImode
|| mode
== DFmode
5127 || mode
== DQmode
|| mode
== UDQmode
5128 || mode
== DAmode
|| mode
== UDAmode
)
5131 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5132 return size
== -1 || size
> UNITS_PER_WORD
;
5136 /* If we have a variable-sized parameter, we have no choice. */
5137 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5141 /* Implement TARGET_CALLEE_COPIES. */
5144 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5145 enum machine_mode mode ATTRIBUTE_UNUSED
,
5146 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5148 return mips_abi
== ABI_EABI
&& named
;
5151 /* See whether VALTYPE is a record whose fields should be returned in
5152 floating-point registers. If so, return the number of fields and
5153 list them in FIELDS (which should have two elements). Return 0
5156 For n32 & n64, a structure with one or two fields is returned in
5157 floating-point registers as long as every field has a floating-point
5161 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5169 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5173 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5175 if (TREE_CODE (field
) != FIELD_DECL
)
5178 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5184 fields
[i
++] = field
;
5189 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5190 a value in the most significant part of $2/$3 if:
5192 - the target is big-endian;
5194 - the value has a structure or union type (we generalize this to
5195 cover aggregates from other languages too); and
5197 - the structure is not returned in floating-point registers. */
5200 mips_return_in_msb (const_tree valtype
)
5204 return (TARGET_NEWABI
5205 && TARGET_BIG_ENDIAN
5206 && AGGREGATE_TYPE_P (valtype
)
5207 && mips_fpr_return_fields (valtype
, fields
) == 0);
5210 /* Return true if the function return value MODE will get returned in a
5211 floating-point register. */
5214 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5216 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5218 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5219 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5222 /* Return the representation of an FPR return register when the
5223 value being returned in FP_RETURN has mode VALUE_MODE and the
5224 return type itself has mode TYPE_MODE. On NewABI targets,
5225 the two modes may be different for structures like:
5227 struct __attribute__((packed)) foo { float f; }
5229 where we return the SFmode value of "f" in FP_RETURN, but where
5230 the structure itself has mode BLKmode. */
5233 mips_return_fpr_single (enum machine_mode type_mode
,
5234 enum machine_mode value_mode
)
5238 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5239 if (type_mode
!= value_mode
)
5241 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5242 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5247 /* Return a composite value in a pair of floating-point registers.
5248 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5249 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5252 For n32 & n64, $f0 always holds the first value and $f2 the second.
5253 Otherwise the values are packed together as closely as possible. */
5256 mips_return_fpr_pair (enum machine_mode mode
,
5257 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5258 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5262 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5263 return gen_rtx_PARALLEL
5266 gen_rtx_EXPR_LIST (VOIDmode
,
5267 gen_rtx_REG (mode1
, FP_RETURN
),
5269 gen_rtx_EXPR_LIST (VOIDmode
,
5270 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5271 GEN_INT (offset2
))));
5275 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5276 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5277 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5280 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5281 enum machine_mode mode
)
5289 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5290 func
= fn_decl_or_type
;
5294 mode
= TYPE_MODE (valtype
);
5295 unsigned_p
= TYPE_UNSIGNED (valtype
);
5297 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5298 return values, promote the mode here too. */
5299 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5301 /* Handle structures whose fields are returned in $f0/$f2. */
5302 switch (mips_fpr_return_fields (valtype
, fields
))
5305 return mips_return_fpr_single (mode
,
5306 TYPE_MODE (TREE_TYPE (fields
[0])));
5309 return mips_return_fpr_pair (mode
,
5310 TYPE_MODE (TREE_TYPE (fields
[0])),
5311 int_byte_position (fields
[0]),
5312 TYPE_MODE (TREE_TYPE (fields
[1])),
5313 int_byte_position (fields
[1]));
5316 /* If a value is passed in the most significant part of a register, see
5317 whether we have to round the mode up to a whole number of words. */
5318 if (mips_return_in_msb (valtype
))
5320 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5321 if (size
% UNITS_PER_WORD
!= 0)
5323 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5324 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5328 /* For EABI, the class of return register depends entirely on MODE.
5329 For example, "struct { some_type x; }" and "union { some_type x; }"
5330 are returned in the same way as a bare "some_type" would be.
5331 Other ABIs only use FPRs for scalar, complex or vector types. */
5332 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5333 return gen_rtx_REG (mode
, GP_RETURN
);
5338 /* Handle long doubles for n32 & n64. */
5340 return mips_return_fpr_pair (mode
,
5342 DImode
, GET_MODE_SIZE (mode
) / 2);
5344 if (mips_return_mode_in_fpr_p (mode
))
5346 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5347 return mips_return_fpr_pair (mode
,
5348 GET_MODE_INNER (mode
), 0,
5349 GET_MODE_INNER (mode
),
5350 GET_MODE_SIZE (mode
) / 2);
5352 return gen_rtx_REG (mode
, FP_RETURN
);
5356 return gen_rtx_REG (mode
, GP_RETURN
);
5359 /* Implement TARGET_FUNCTION_VALUE. */
5362 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5363 bool outgoing ATTRIBUTE_UNUSED
)
5365 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5368 /* Implement TARGET_LIBCALL_VALUE. */
5371 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5373 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5376 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5378 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5379 Currently, R2 and F0 are only implemented here (C has no complex type). */
5382 mips_function_value_regno_p (const unsigned int regno
)
5384 if (regno
== GP_RETURN
5385 || regno
== FP_RETURN
5386 || (LONG_DOUBLE_TYPE_SIZE
== 128
5387 && FP_RETURN
!= GP_RETURN
5388 && regno
== FP_RETURN
+ 2))
5394 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5395 all BLKmode objects are returned in memory. Under the n32, n64
5396 and embedded ABIs, small structures are returned in a register.
5397 Objects with varying size must still be returned in memory, of
5401 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5403 return (TARGET_OLDABI
5404 ? TYPE_MODE (type
) == BLKmode
5405 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5408 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5411 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5412 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5415 CUMULATIVE_ARGS local_cum
;
5416 int gp_saved
, fp_saved
;
5418 /* The caller has advanced CUM up to, but not beyond, the last named
5419 argument. Advance a local copy of CUM past the last "real" named
5420 argument, to find out how many registers are left over. */
5421 local_cum
= *get_cumulative_args (cum
);
5422 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5425 /* Found out how many registers we need to save. */
5426 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5427 fp_saved
= (EABI_FLOAT_VARARGS_P
5428 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5437 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5438 REG_PARM_STACK_SPACE (cfun
->decl
)
5439 - gp_saved
* UNITS_PER_WORD
);
5440 mem
= gen_frame_mem (BLKmode
, ptr
);
5441 set_mem_alias_set (mem
, get_varargs_alias_set ());
5443 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5448 /* We can't use move_block_from_reg, because it will use
5450 enum machine_mode mode
;
5453 /* Set OFF to the offset from virtual_incoming_args_rtx of
5454 the first float register. The FP save area lies below
5455 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5456 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5457 off
-= fp_saved
* UNITS_PER_FPREG
;
5459 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5461 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5462 i
+= MAX_FPRS_PER_FMT
)
5466 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5467 mem
= gen_frame_mem (mode
, ptr
);
5468 set_mem_alias_set (mem
, get_varargs_alias_set ());
5469 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5470 off
+= UNITS_PER_HWFPVALUE
;
5474 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5475 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5476 + fp_saved
* UNITS_PER_FPREG
);
5479 /* Implement TARGET_BUILTIN_VA_LIST. */
5482 mips_build_builtin_va_list (void)
5484 if (EABI_FLOAT_VARARGS_P
)
5486 /* We keep 3 pointers, and two offsets.
5488 Two pointers are to the overflow area, which starts at the CFA.
5489 One of these is constant, for addressing into the GPR save area
5490 below it. The other is advanced up the stack through the
5493 The third pointer is to the bottom of the GPR save area.
5494 Since the FPR save area is just below it, we can address
5495 FPR slots off this pointer.
5497 We also keep two one-byte offsets, which are to be subtracted
5498 from the constant pointers to yield addresses in the GPR and
5499 FPR save areas. These are downcounted as float or non-float
5500 arguments are used, and when they get to zero, the argument
5501 must be obtained from the overflow region. */
5502 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5505 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5507 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5508 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5510 f_gtop
= build_decl (BUILTINS_LOCATION
,
5511 FIELD_DECL
, get_identifier ("__gpr_top"),
5513 f_ftop
= build_decl (BUILTINS_LOCATION
,
5514 FIELD_DECL
, get_identifier ("__fpr_top"),
5516 f_goff
= build_decl (BUILTINS_LOCATION
,
5517 FIELD_DECL
, get_identifier ("__gpr_offset"),
5518 unsigned_char_type_node
);
5519 f_foff
= build_decl (BUILTINS_LOCATION
,
5520 FIELD_DECL
, get_identifier ("__fpr_offset"),
5521 unsigned_char_type_node
);
5522 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5523 warn on every user file. */
5524 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5525 array
= build_array_type (unsigned_char_type_node
,
5526 build_index_type (index
));
5527 f_res
= build_decl (BUILTINS_LOCATION
,
5528 FIELD_DECL
, get_identifier ("__reserved"), array
);
5530 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5531 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5532 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5533 DECL_FIELD_CONTEXT (f_goff
) = record
;
5534 DECL_FIELD_CONTEXT (f_foff
) = record
;
5535 DECL_FIELD_CONTEXT (f_res
) = record
;
5537 TYPE_FIELDS (record
) = f_ovfl
;
5538 DECL_CHAIN (f_ovfl
) = f_gtop
;
5539 DECL_CHAIN (f_gtop
) = f_ftop
;
5540 DECL_CHAIN (f_ftop
) = f_goff
;
5541 DECL_CHAIN (f_goff
) = f_foff
;
5542 DECL_CHAIN (f_foff
) = f_res
;
5544 layout_type (record
);
5548 /* Otherwise, we use 'void *'. */
5549 return ptr_type_node
;
5552 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5555 mips_va_start (tree valist
, rtx nextarg
)
5557 if (EABI_FLOAT_VARARGS_P
)
5559 const CUMULATIVE_ARGS
*cum
;
5560 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5561 tree ovfl
, gtop
, ftop
, goff
, foff
;
5563 int gpr_save_area_size
;
5564 int fpr_save_area_size
;
5567 cum
= &crtl
->args
.info
;
5569 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5571 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5573 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5574 f_gtop
= DECL_CHAIN (f_ovfl
);
5575 f_ftop
= DECL_CHAIN (f_gtop
);
5576 f_goff
= DECL_CHAIN (f_ftop
);
5577 f_foff
= DECL_CHAIN (f_goff
);
5579 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5581 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5583 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5585 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5587 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5590 /* Emit code to initialize OVFL, which points to the next varargs
5591 stack argument. CUM->STACK_WORDS gives the number of stack
5592 words used by named arguments. */
5593 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5594 if (cum
->stack_words
> 0)
5595 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5596 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5597 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5599 /* Emit code to initialize GTOP, the top of the GPR save area. */
5600 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5601 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5602 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5604 /* Emit code to initialize FTOP, the top of the FPR save area.
5605 This address is gpr_save_area_bytes below GTOP, rounded
5606 down to the next fp-aligned boundary. */
5607 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5608 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5609 fpr_offset
&= -UNITS_PER_FPVALUE
;
5611 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5612 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5613 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5615 /* Emit code to initialize GOFF, the offset from GTOP of the
5616 next GPR argument. */
5617 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5618 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5619 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5621 /* Likewise emit code to initialize FOFF, the offset from FTOP
5622 of the next FPR argument. */
5623 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5624 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5625 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5629 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5630 std_expand_builtin_va_start (valist
, nextarg
);
5634 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5638 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5641 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5642 unsigned HOST_WIDE_INT align
, boundary
;
5645 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5647 type
= build_pointer_type (type
);
5649 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5650 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5652 /* When we align parameter on stack for caller, if the parameter
5653 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5654 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5655 here with caller. */
5656 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5657 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5659 boundary
/= BITS_PER_UNIT
;
5661 /* Hoist the valist value into a temporary for the moment. */
5662 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5664 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5665 requires greater alignment, we must perform dynamic alignment. */
5666 if (boundary
> align
)
5668 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5669 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5670 gimplify_and_add (t
, pre_p
);
5672 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5673 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5675 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5676 gimplify_and_add (t
, pre_p
);
5681 /* If the actual alignment is less than the alignment of the type,
5682 adjust the type accordingly so that we don't assume strict alignment
5683 when dereferencing the pointer. */
5684 boundary
*= BITS_PER_UNIT
;
5685 if (boundary
< TYPE_ALIGN (type
))
5687 type
= build_variant_type_copy (type
);
5688 TYPE_ALIGN (type
) = boundary
;
5691 /* Compute the rounded size of the type. */
5692 type_size
= size_in_bytes (type
);
5693 rounded_size
= round_up (type_size
, align
);
5695 /* Reduce rounded_size so it's sharable with the postqueue. */
5696 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5700 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
5702 /* Small args are padded downward. */
5703 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
5704 rounded_size
, size_int (align
));
5705 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
5706 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
5707 addr
= fold_build_pointer_plus (addr
, t
);
5710 /* Compute new value for AP. */
5711 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
5712 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5713 gimplify_and_add (t
, pre_p
);
5715 addr
= fold_convert (build_pointer_type (type
), addr
);
5718 addr
= build_va_arg_indirect_ref (addr
);
5720 return build_va_arg_indirect_ref (addr
);
5723 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5726 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5732 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5734 type
= build_pointer_type (type
);
5736 if (!EABI_FLOAT_VARARGS_P
)
5737 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5740 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5741 tree ovfl
, top
, off
, align
;
5742 HOST_WIDE_INT size
, rsize
, osize
;
5745 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5746 f_gtop
= DECL_CHAIN (f_ovfl
);
5747 f_ftop
= DECL_CHAIN (f_gtop
);
5748 f_goff
= DECL_CHAIN (f_ftop
);
5749 f_foff
= DECL_CHAIN (f_goff
);
5753 TOP be the top of the GPR or FPR save area;
5754 OFF be the offset from TOP of the next register;
5755 ADDR_RTX be the address of the argument;
5756 SIZE be the number of bytes in the argument type;
5757 RSIZE be the number of bytes used to store the argument
5758 when it's in the register save area; and
5759 OSIZE be the number of bytes used to store it when it's
5760 in the stack overflow area.
5762 The code we want is:
5764 1: off &= -rsize; // round down
5767 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5772 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5773 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5777 [1] and [9] can sometimes be optimized away. */
5779 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5781 size
= int_size_in_bytes (type
);
5783 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
5784 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
5786 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
5787 unshare_expr (valist
), f_ftop
, NULL_TREE
);
5788 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
5789 unshare_expr (valist
), f_foff
, NULL_TREE
);
5791 /* When va_start saves FPR arguments to the stack, each slot
5792 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5793 argument's precision. */
5794 rsize
= UNITS_PER_HWFPVALUE
;
5796 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5797 (= PARM_BOUNDARY bits). This can be different from RSIZE
5800 (1) On 32-bit targets when TYPE is a structure such as:
5802 struct s { float f; };
5804 Such structures are passed in paired FPRs, so RSIZE
5805 will be 8 bytes. However, the structure only takes
5806 up 4 bytes of memory, so OSIZE will only be 4.
5808 (2) In combinations such as -mgp64 -msingle-float
5809 -fshort-double. Doubles passed in registers will then take
5810 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5811 stack take up UNITS_PER_WORD bytes. */
5812 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
5816 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
5817 unshare_expr (valist
), f_gtop
, NULL_TREE
);
5818 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
5819 unshare_expr (valist
), f_goff
, NULL_TREE
);
5820 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5821 if (rsize
> UNITS_PER_WORD
)
5823 /* [1] Emit code for: off &= -rsize. */
5824 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
5825 build_int_cst (TREE_TYPE (off
), -rsize
));
5826 gimplify_assign (unshare_expr (off
), t
, pre_p
);
5831 /* [2] Emit code to branch if off == 0. */
5832 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
5833 build_int_cst (TREE_TYPE (off
), 0));
5834 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
5836 /* [5] Emit code for: off -= rsize. We do this as a form of
5837 post-decrement not available to C. */
5838 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
5839 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
5841 /* [4] Emit code for:
5842 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5843 t
= fold_convert (sizetype
, t
);
5844 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
5845 t
= fold_build_pointer_plus (top
, t
);
5846 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
5847 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
5848 COND_EXPR_THEN (addr
) = t
;
5850 if (osize
> UNITS_PER_WORD
)
5852 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5853 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
5854 u
= build_int_cst (TREE_TYPE (t
), -osize
);
5855 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
5856 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
5857 unshare_expr (ovfl
), t
);
5862 /* [10, 11] Emit code for:
5863 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5865 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
5866 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5867 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5868 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
5870 /* String [9] and [10, 11] together. */
5872 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5873 COND_EXPR_ELSE (addr
) = t
;
5875 addr
= fold_convert (build_pointer_type (type
), addr
);
5876 addr
= build_va_arg_indirect_ref (addr
);
5880 addr
= build_va_arg_indirect_ref (addr
);
5885 /* Declare a unique, locally-binding function called NAME, then start
5889 mips_start_unique_function (const char *name
)
5893 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
5894 get_identifier (name
),
5895 build_function_type_list (void_type_node
, NULL_TREE
));
5896 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
5897 NULL_TREE
, void_type_node
);
5898 TREE_PUBLIC (decl
) = 1;
5899 TREE_STATIC (decl
) = 1;
5901 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
5903 targetm
.asm_out
.unique_section (decl
, 0);
5904 switch_to_section (get_named_section (decl
, NULL
, 0));
5906 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
5907 fputs ("\t.hidden\t", asm_out_file
);
5908 assemble_name (asm_out_file
, name
);
5909 putc ('\n', asm_out_file
);
5912 /* Start a definition of function NAME. MIPS16_P indicates whether the
5913 function contains MIPS16 code. */
5916 mips_start_function_definition (const char *name
, bool mips16_p
)
5919 fprintf (asm_out_file
, "\t.set\tmips16\n");
5921 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5923 if (!flag_inhibit_size_directive
)
5925 fputs ("\t.ent\t", asm_out_file
);
5926 assemble_name (asm_out_file
, name
);
5927 fputs ("\n", asm_out_file
);
5930 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
5932 /* Start the definition proper. */
5933 assemble_name (asm_out_file
, name
);
5934 fputs (":\n", asm_out_file
);
5937 /* End a function definition started by mips_start_function_definition. */
5940 mips_end_function_definition (const char *name
)
5942 if (!flag_inhibit_size_directive
)
5944 fputs ("\t.end\t", asm_out_file
);
5945 assemble_name (asm_out_file
, name
);
5946 fputs ("\n", asm_out_file
);
5950 /* Output a definition of the __mips16_rdhwr function. */
5953 mips_output_mips16_rdhwr (void)
5957 name
= "__mips16_rdhwr";
5958 mips_start_unique_function (name
);
5959 mips_start_function_definition (name
, false);
5960 fprintf (asm_out_file
,
5962 "\t.set\tmips32r2\n"
5963 "\t.set\tnoreorder\n"
5967 mips_end_function_definition (name
);
5970 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5973 mips_ok_for_lazy_binding_p (rtx x
)
5975 return (TARGET_USE_GOT
5976 && GET_CODE (x
) == SYMBOL_REF
5977 && !SYMBOL_REF_BIND_NOW_P (x
)
5978 && !mips_symbol_binds_local_p (x
));
5981 /* Load function address ADDR into register DEST. TYPE is as for
5982 mips_expand_call. Return true if we used an explicit lazy-binding
5986 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
5988 /* If we're generating PIC, and this call is to a global function,
5989 try to allow its address to be resolved lazily. This isn't
5990 possible for sibcalls when $gp is call-saved because the value
5991 of $gp on entry to the stub would be our caller's gp, not ours. */
5992 if (TARGET_EXPLICIT_RELOCS
5993 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
5994 && mips_ok_for_lazy_binding_p (addr
))
5996 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
5997 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6002 mips_emit_move (dest
, addr
);
6007 /* Each locally-defined hard-float MIPS16 function has a local symbol
6008 associated with it. This hash table maps the function symbol (FUNC)
6009 to the local symbol (LOCAL). */
6010 struct GTY(()) mips16_local_alias
{
6014 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6016 /* Hash table callbacks for mips16_local_aliases. */
6019 mips16_local_aliases_hash (const void *entry
)
6021 const struct mips16_local_alias
*alias
;
6023 alias
= (const struct mips16_local_alias
*) entry
;
6024 return htab_hash_string (XSTR (alias
->func
, 0));
6028 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6030 const struct mips16_local_alias
*alias1
, *alias2
;
6032 alias1
= (const struct mips16_local_alias
*) entry1
;
6033 alias2
= (const struct mips16_local_alias
*) entry2
;
6034 return rtx_equal_p (alias1
->func
, alias2
->func
);
6037 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6038 Return a local alias for it, creating a new one if necessary. */
6041 mips16_local_alias (rtx func
)
6043 struct mips16_local_alias
*alias
, tmp_alias
;
6046 /* Create the hash table if this is the first call. */
6047 if (mips16_local_aliases
== NULL
)
6048 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6049 mips16_local_aliases_eq
, NULL
);
6051 /* Look up the function symbol, creating a new entry if need be. */
6052 tmp_alias
.func
= func
;
6053 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6054 gcc_assert (slot
!= NULL
);
6056 alias
= (struct mips16_local_alias
*) *slot
;
6059 const char *func_name
, *local_name
;
6062 /* Create a new SYMBOL_REF for the local symbol. The choice of
6063 __fn_local_* is based on the __fn_stub_* names that we've
6064 traditionally used for the non-MIPS16 stub. */
6065 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6066 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6067 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6068 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6070 /* Create a new structure to represent the mapping. */
6071 alias
= ggc_alloc_mips16_local_alias ();
6073 alias
->local
= local
;
6076 return alias
->local
;
6079 /* A chained list of functions for which mips16_build_call_stub has already
6080 generated a stub. NAME is the name of the function and FP_RET_P is true
6081 if the function returns a value in floating-point registers. */
6082 struct mips16_stub
{
6083 struct mips16_stub
*next
;
6087 static struct mips16_stub
*mips16_stubs
;
6089 /* Return the two-character string that identifies floating-point
6090 return mode MODE in the name of a MIPS16 function stub. */
6093 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6097 else if (mode
== DFmode
)
6099 else if (mode
== SCmode
)
6101 else if (mode
== DCmode
)
6103 else if (mode
== V2SFmode
)
6109 /* Write instructions to move a 32-bit value between general register
6110 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6111 from GPREG to FPREG and 'f' to move in the opposite direction. */
6114 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6116 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6117 reg_names
[gpreg
], reg_names
[fpreg
]);
6120 /* Likewise for 64-bit values. */
6123 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6126 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6127 reg_names
[gpreg
], reg_names
[fpreg
]);
6128 else if (TARGET_FLOAT64
)
6130 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6131 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6132 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6133 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6137 /* Move the least-significant word. */
6138 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6139 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6140 /* ...then the most significant word. */
6141 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6142 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6146 /* Write out code to move floating-point arguments into or out of
6147 general registers. FP_CODE is the code describing which arguments
6148 are present (see the comment above the definition of CUMULATIVE_ARGS
6149 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6152 mips_output_args_xfer (int fp_code
, char direction
)
6154 unsigned int gparg
, fparg
, f
;
6155 CUMULATIVE_ARGS cum
;
6157 /* This code only works for o32 and o64. */
6158 gcc_assert (TARGET_OLDABI
);
6160 mips_init_cumulative_args (&cum
, NULL
);
6162 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6164 enum machine_mode mode
;
6165 struct mips_arg_info info
;
6169 else if ((f
& 3) == 2)
6174 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6175 gparg
= mips_arg_regno (&info
, false);
6176 fparg
= mips_arg_regno (&info
, true);
6179 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6181 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6183 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6187 /* Write a MIPS16 stub for the current function. This stub is used
6188 for functions which take arguments in the floating-point registers.
6189 It is normal-mode code that moves the floating-point arguments
6190 into the general registers and then jumps to the MIPS16 code. */
6193 mips16_build_function_stub (void)
6195 const char *fnname
, *alias_name
, *separator
;
6196 char *secname
, *stubname
;
6201 /* Create the name of the stub, and its unique section. */
6202 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6203 alias
= mips16_local_alias (symbol
);
6205 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6206 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6207 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6208 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6210 /* Build a decl for the stub. */
6211 stubdecl
= build_decl (BUILTINS_LOCATION
,
6212 FUNCTION_DECL
, get_identifier (stubname
),
6213 build_function_type_list (void_type_node
, NULL_TREE
));
6214 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6215 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6216 RESULT_DECL
, NULL_TREE
, void_type_node
);
6218 /* Output a comment. */
6219 fprintf (asm_out_file
, "\t# Stub function for %s (",
6220 current_function_name ());
6222 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6224 fprintf (asm_out_file
, "%s%s", separator
,
6225 (f
& 3) == 1 ? "float" : "double");
6228 fprintf (asm_out_file
, ")\n");
6230 /* Start the function definition. */
6231 assemble_start_function (stubdecl
, stubname
);
6232 mips_start_function_definition (stubname
, false);
6234 /* If generating pic2 code, either set up the global pointer or
6236 if (TARGET_ABICALLS_PIC2
)
6238 if (TARGET_ABSOLUTE_ABICALLS
)
6239 fprintf (asm_out_file
, "\t.option\tpic0\n");
6242 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6243 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6244 target function is. Use a local GOT access when loading the
6245 symbol, to cut down on the number of unnecessary GOT entries
6246 for stubs that aren't needed. */
6247 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6252 /* Load the address of the MIPS16 function into $25. Do this first so
6253 that targets with coprocessor interlocks can use an MFC1 to fill the
6255 output_asm_insn ("la\t%^,%0", &symbol
);
6257 /* Move the arguments from floating-point registers to general registers. */
6258 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6260 /* Jump to the MIPS16 function. */
6261 output_asm_insn ("jr\t%^", NULL
);
6263 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6264 fprintf (asm_out_file
, "\t.option\tpic2\n");
6266 mips_end_function_definition (stubname
);
6268 /* If the linker needs to create a dynamic symbol for the target
6269 function, it will associate the symbol with the stub (which,
6270 unlike the target function, follows the proper calling conventions).
6271 It is therefore useful to have a local alias for the target function,
6272 so that it can still be identified as MIPS16 code. As an optimization,
6273 this symbol can also be used for indirect MIPS16 references from
6274 within this file. */
6275 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6277 switch_to_section (function_section (current_function_decl
));
6280 /* The current function is a MIPS16 function that returns a value in an FPR.
6281 Copy the return value from its soft-float to its hard-float location.
6282 libgcc2 has special non-MIPS16 helper functions for each case. */
6285 mips16_copy_fpr_return_value (void)
6287 rtx fn
, insn
, retval
;
6289 enum machine_mode return_mode
;
6292 return_type
= DECL_RESULT (current_function_decl
);
6293 return_mode
= DECL_MODE (return_type
);
6295 name
= ACONCAT (("__mips16_ret_",
6296 mips16_call_stub_mode_suffix (return_mode
),
6298 fn
= mips16_stub_function (name
);
6300 /* The function takes arguments in $2 (and possibly $3), so calls
6301 to it cannot be lazily bound. */
6302 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6304 /* Model the call as something that takes the GPR return value as
6305 argument and returns an "updated" value. */
6306 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6307 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6308 const0_rtx
, NULL_RTX
, false);
6309 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6312 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6313 RETVAL is the location of the return value, or null if this is
6314 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6315 arguments and FP_CODE is the code built by mips_function_arg;
6316 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6318 There are three alternatives:
6320 - If a stub was needed, emit the call and return the call insn itself.
6322 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6323 to the new target and return null.
6325 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6328 A stub is needed for calls to functions that, in normal mode,
6329 receive arguments in FPRs or return values in FPRs. The stub
6330 copies the arguments from their soft-float positions to their
6331 hard-float positions, calls the real function, then copies the
6332 return value from its hard-float position to its soft-float
6335 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6336 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6337 automatically redirects the JAL to the stub, otherwise the JAL
6338 continues to call FN directly. */
6341 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6345 struct mips16_stub
*l
;
6348 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6349 we were invoked with the -msoft-float option. */
6350 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6353 /* Figure out whether the value might come back in a floating-point
6355 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6357 /* We don't need to do anything if there were no floating-point
6358 arguments and the value will not be returned in a floating-point
6360 if (fp_code
== 0 && !fp_ret_p
)
6363 /* We don't need to do anything if this is a call to a special
6364 MIPS16 support function. */
6366 if (mips16_stub_function_p (fn
))
6369 /* If we're calling a locally-defined MIPS16 function, we know that
6370 it will return values in both the "soft-float" and "hard-float"
6371 registers. There is no need to use a stub to move the latter
6373 if (fp_code
== 0 && mips16_local_function_p (fn
))
6376 /* This code will only work for o32 and o64 abis. The other ABI's
6377 require more sophisticated support. */
6378 gcc_assert (TARGET_OLDABI
);
6380 /* If we're calling via a function pointer, use one of the magic
6381 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6382 Each stub expects the function address to arrive in register $2. */
6383 if (GET_CODE (fn
) != SYMBOL_REF
6384 || !call_insn_operand (fn
, VOIDmode
))
6387 rtx stub_fn
, insn
, addr
;
6390 /* If this is a locally-defined and locally-binding function,
6391 avoid the stub by calling the local alias directly. */
6392 if (mips16_local_function_p (fn
))
6394 *fn_ptr
= mips16_local_alias (fn
);
6398 /* Create a SYMBOL_REF for the libgcc.a function. */
6400 sprintf (buf
, "__mips16_call_stub_%s_%d",
6401 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6404 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6405 stub_fn
= mips16_stub_function (buf
);
6407 /* The function uses $2 as an argument, so calls to it
6408 cannot be lazily bound. */
6409 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6411 /* Load the target function into $2. */
6412 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6413 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6415 /* Emit the call. */
6416 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6417 args_size
, NULL_RTX
, lazy_p
);
6419 /* Tell GCC that this call does indeed use the value of $2. */
6420 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6422 /* If we are handling a floating-point return value, we need to
6423 save $18 in the function prologue. Putting a note on the
6424 call will mean that df_regs_ever_live_p ($18) will be true if the
6425 call is not eliminated, and we can check that in the prologue
6428 CALL_INSN_FUNCTION_USAGE (insn
) =
6429 gen_rtx_EXPR_LIST (VOIDmode
,
6430 gen_rtx_CLOBBER (VOIDmode
,
6431 gen_rtx_REG (word_mode
, 18)),
6432 CALL_INSN_FUNCTION_USAGE (insn
));
6437 /* We know the function we are going to call. If we have already
6438 built a stub, we don't need to do anything further. */
6439 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6440 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6441 if (strcmp (l
->name
, fnname
) == 0)
6446 const char *separator
;
6447 char *secname
, *stubname
;
6448 tree stubid
, stubdecl
;
6451 /* If the function does not return in FPRs, the special stub
6455 If the function does return in FPRs, the stub section is named
6456 .mips16.call.fp.FNNAME
6458 Build a decl for the stub. */
6459 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6461 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6463 stubid
= get_identifier (stubname
);
6464 stubdecl
= build_decl (BUILTINS_LOCATION
,
6465 FUNCTION_DECL
, stubid
,
6466 build_function_type_list (void_type_node
,
6468 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6469 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6470 RESULT_DECL
, NULL_TREE
,
6473 /* Output a comment. */
6474 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6476 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6480 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6482 fprintf (asm_out_file
, "%s%s", separator
,
6483 (f
& 3) == 1 ? "float" : "double");
6486 fprintf (asm_out_file
, ")\n");
6488 /* Start the function definition. */
6489 assemble_start_function (stubdecl
, stubname
);
6490 mips_start_function_definition (stubname
, false);
6494 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6496 /* Create a fake CFA 4 bytes below the stack pointer.
6497 This works around unwinders (like libgcc's) that expect
6498 the CFA for non-signal frames to be unique. */
6499 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6501 /* "Save" $sp in itself so we don't use the fake CFA.
6502 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6503 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6507 /* Load the address of the MIPS16 function into $25. Do this
6508 first so that targets with coprocessor interlocks can use
6509 an MFC1 to fill the delay slot. */
6510 if (TARGET_EXPLICIT_RELOCS
)
6512 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6513 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6516 output_asm_insn ("la\t%^,%0", &fn
);
6519 /* Move the arguments from general registers to floating-point
6521 mips_output_args_xfer (fp_code
, 't');
6525 /* Save the return address in $18 and call the non-MIPS16 function.
6526 The stub's caller knows that $18 might be clobbered, even though
6527 $18 is usually a call-saved register. */
6528 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6529 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6530 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6531 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6533 /* Move the result from floating-point registers to
6534 general registers. */
6535 switch (GET_MODE (retval
))
6538 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6540 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6542 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6543 TARGET_LITTLE_ENDIAN
6544 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6546 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6548 /* On 64-bit targets, complex floats are returned in
6549 a single GPR, such that "sd" on a suitably-aligned
6550 target would store the value correctly. */
6551 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6552 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6553 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6554 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6555 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6556 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6557 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6558 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6559 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6560 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6561 reg_names
[GP_RETURN
],
6562 reg_names
[GP_RETURN
],
6563 reg_names
[GP_RETURN
+ 1]);
6568 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6572 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6573 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6577 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6583 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6584 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6588 /* Jump to the previously-loaded address. */
6589 output_asm_insn ("jr\t%^", NULL
);
6592 #ifdef ASM_DECLARE_FUNCTION_SIZE
6593 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6596 mips_end_function_definition (stubname
);
6598 /* Record this stub. */
6599 l
= XNEW (struct mips16_stub
);
6600 l
->name
= xstrdup (fnname
);
6601 l
->fp_ret_p
= fp_ret_p
;
6602 l
->next
= mips16_stubs
;
6606 /* If we expect a floating-point return value, but we've built a
6607 stub which does not expect one, then we're in trouble. We can't
6608 use the existing stub, because it won't handle the floating-point
6609 value. We can't build a new stub, because the linker won't know
6610 which stub to use for the various calls in this object file.
6611 Fortunately, this case is illegal, since it means that a function
6612 was declared in two different ways in a single compilation. */
6613 if (fp_ret_p
&& !l
->fp_ret_p
)
6614 error ("cannot handle inconsistent calls to %qs", fnname
);
6616 if (retval
== NULL_RTX
)
6617 insn
= gen_call_internal_direct (fn
, args_size
);
6619 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6620 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6622 /* If we are calling a stub which handles a floating-point return
6623 value, we need to arrange to save $18 in the prologue. We do this
6624 by marking the function call as using the register. The prologue
6625 will later see that it is used, and emit code to save it. */
6627 CALL_INSN_FUNCTION_USAGE (insn
) =
6628 gen_rtx_EXPR_LIST (VOIDmode
,
6629 gen_rtx_CLOBBER (VOIDmode
,
6630 gen_rtx_REG (word_mode
, 18)),
6631 CALL_INSN_FUNCTION_USAGE (insn
));
6636 /* Expand a call of type TYPE. RESULT is where the result will go (null
6637 for "call"s and "sibcall"s), ADDR is the address of the function,
6638 ARGS_SIZE is the size of the arguments and AUX is the value passed
6639 to us by mips_function_arg. LAZY_P is true if this call already
6640 involves a lazily-bound function address (such as when calling
6641 functions through a MIPS16 hard-float stub).
6643 Return the call itself. */
6646 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6647 rtx args_size
, rtx aux
, bool lazy_p
)
6649 rtx orig_addr
, pattern
, insn
;
6652 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6653 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6656 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6661 if (!call_insn_operand (addr
, VOIDmode
))
6663 if (type
== MIPS_CALL_EPILOGUE
)
6664 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6666 addr
= gen_reg_rtx (Pmode
);
6667 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6672 rtx (*fn
) (rtx
, rtx
);
6674 if (type
== MIPS_CALL_SIBCALL
)
6675 fn
= gen_sibcall_internal
;
6677 fn
= gen_call_internal
;
6679 pattern
= fn (addr
, args_size
);
6681 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6683 /* Handle return values created by mips_return_fpr_pair. */
6684 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6687 if (type
== MIPS_CALL_SIBCALL
)
6688 fn
= gen_sibcall_value_multiple_internal
;
6690 fn
= gen_call_value_multiple_internal
;
6692 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6693 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6694 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6698 rtx (*fn
) (rtx
, rtx
, rtx
);
6700 if (type
== MIPS_CALL_SIBCALL
)
6701 fn
= gen_sibcall_value_internal
;
6703 fn
= gen_call_value_internal
;
6705 /* Handle return values created by mips_return_fpr_single. */
6706 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6707 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6708 pattern
= fn (result
, addr
, args_size
);
6711 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6714 /* Split call instruction INSN into a $gp-clobbering call and
6715 (where necessary) an instruction to restore $gp from its save slot.
6716 CALL_PATTERN is the pattern of the new call. */
6719 mips_split_call (rtx insn
, rtx call_pattern
)
6721 emit_call_insn (call_pattern
);
6722 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6723 /* Pick a temporary register that is suitable for both MIPS16 and
6724 non-MIPS16 code. $4 and $5 are used for returning complex double
6725 values in soft-float code, so $6 is the first suitable candidate. */
6726 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6729 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6732 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6734 if (!TARGET_SIBCALLS
)
6737 /* Interrupt handlers need special epilogue code and therefore can't
6739 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
6742 /* We can't do a sibcall if the called function is a MIPS16 function
6743 because there is no direct "jx" instruction equivalent to "jalx" to
6744 switch the ISA mode. We only care about cases where the sibling
6745 and normal calls would both be direct. */
6747 && mips_use_mips16_mode_p (decl
)
6748 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6751 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6752 functions could be MIPS16 ones unless an attribute explicitly tells
6754 if (TARGET_INTERLINK_MIPS16
6756 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
6757 && !mips_nomips16_decl_p (decl
)
6758 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6765 /* Emit code to move general operand SRC into condition-code
6766 register DEST given that SCRATCH is a scratch TFmode FPR.
6773 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6776 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
6780 /* Change the source to SFmode. */
6782 src
= adjust_address (src
, SFmode
, 0);
6783 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
6784 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
6786 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
6787 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
6789 mips_emit_move (copy_rtx (fp1
), src
);
6790 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
6791 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
6794 /* Implement MOVE_BY_PIECES_P. */
6797 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
6801 /* movmemsi is meant to generate code that is at least as good as
6802 move_by_pieces. However, movmemsi effectively uses a by-pieces
6803 implementation both for moves smaller than a word and for
6804 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6805 bytes. We should allow the tree-level optimisers to do such
6806 moves by pieces, as it often exposes other optimization
6807 opportunities. We might as well continue to use movmemsi at
6808 the rtl level though, as it produces better code when
6809 scheduling is disabled (such as at -O). */
6810 if (currently_expanding_to_rtl
)
6812 if (align
< BITS_PER_WORD
)
6813 return size
< UNITS_PER_WORD
;
6814 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
6816 /* The default value. If this becomes a target hook, we should
6817 call the default definition instead. */
6818 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
6819 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
6822 /* Implement STORE_BY_PIECES_P. */
6825 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
6827 /* Storing by pieces involves moving constants into registers
6828 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
6829 We need to decide whether it is cheaper to load the address of
6830 constant data into a register and use a block move instead. */
6832 /* If the data is only byte aligned, then:
6834 (a1) A block move of less than 4 bytes would involve three 3 LBs and
6835 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
6838 (a2) A block move of 4 bytes from aligned source data can use an
6839 LW/SWL/SWR sequence. This is often better than the 4 LIs and
6840 4 SBs that we would generate when storing by pieces. */
6841 if (align
<= BITS_PER_UNIT
)
6844 /* If the data is 2-byte aligned, then:
6846 (b1) A block move of less than 4 bytes would use a combination of LBs,
6847 LHs, SBs and SHs. We get better code by using single-instruction
6848 LIs, SBs and SHs instead.
6850 (b2) A block move of 4 bytes from aligned source data would again use
6851 an LW/SWL/SWR sequence. In most cases, loading the address of
6852 the source data would require at least one extra instruction.
6853 It is often more efficient to use 2 single-instruction LIs and
6856 (b3) A block move of up to 3 additional bytes would be like (b1).
6858 (b4) A block move of 8 bytes from aligned source data can use two
6859 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
6860 sequences are better than the 4 LIs and 4 SHs that we'd generate
6861 when storing by pieces.
6863 The reasoning for higher alignments is similar:
6865 (c1) A block move of less than 4 bytes would be the same as (b1).
6867 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
6868 loading the address of the source data would typically require
6869 at least one extra instruction. It is generally better to use
6872 (c3) A block move of up to 3 additional bytes would be like (b1).
6874 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
6875 LD/SD sequence, and in these cases we've traditionally preferred
6876 the memory copy over the more bulky constant moves. */
6880 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6881 Assume that the areas do not overlap. */
6884 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
6886 HOST_WIDE_INT offset
, delta
;
6887 unsigned HOST_WIDE_INT bits
;
6889 enum machine_mode mode
;
6892 /* Work out how many bits to move at a time. If both operands have
6893 half-word alignment, it is usually better to move in half words.
6894 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6895 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6896 Otherwise move word-sized chunks. */
6897 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
6898 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
6899 bits
= BITS_PER_WORD
/ 2;
6901 bits
= BITS_PER_WORD
;
6903 mode
= mode_for_size (bits
, MODE_INT
, 0);
6904 delta
= bits
/ BITS_PER_UNIT
;
6906 /* Allocate a buffer for the temporary registers. */
6907 regs
= XALLOCAVEC (rtx
, length
/ delta
);
6909 /* Load as many BITS-sized chunks as possible. Use a normal load if
6910 the source has enough alignment, otherwise use left/right pairs. */
6911 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6913 regs
[i
] = gen_reg_rtx (mode
);
6914 if (MEM_ALIGN (src
) >= bits
)
6915 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
6918 rtx part
= adjust_address (src
, BLKmode
, offset
);
6919 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
6924 /* Copy the chunks to the destination. */
6925 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6926 if (MEM_ALIGN (dest
) >= bits
)
6927 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
6930 rtx part
= adjust_address (dest
, BLKmode
, offset
);
6931 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
6935 /* Mop up any left-over bytes. */
6936 if (offset
< length
)
6938 src
= adjust_address (src
, BLKmode
, offset
);
6939 dest
= adjust_address (dest
, BLKmode
, offset
);
6940 move_by_pieces (dest
, src
, length
- offset
,
6941 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
6945 /* Helper function for doing a loop-based block operation on memory
6946 reference MEM. Each iteration of the loop will operate on LENGTH
6949 Create a new base register for use within the loop and point it to
6950 the start of MEM. Create a new memory reference that uses this
6951 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6954 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
6955 rtx
*loop_reg
, rtx
*loop_mem
)
6957 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
6959 /* Although the new mem does not refer to a known location,
6960 it does keep up to LENGTH bytes of alignment. */
6961 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
6962 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
6965 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6966 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6967 the memory regions do not overlap. */
6970 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
6971 HOST_WIDE_INT bytes_per_iter
)
6973 rtx label
, src_reg
, dest_reg
, final_src
, test
;
6974 HOST_WIDE_INT leftover
;
6976 leftover
= length
% bytes_per_iter
;
6979 /* Create registers and memory references for use within the loop. */
6980 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
6981 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
6983 /* Calculate the value that SRC_REG should have after the last iteration
6985 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
6988 /* Emit the start of the loop. */
6989 label
= gen_label_rtx ();
6992 /* Emit the loop body. */
6993 mips_block_move_straight (dest
, src
, bytes_per_iter
);
6995 /* Move on to the next block. */
6996 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
6997 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
6999 /* Emit the loop condition. */
7000 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7001 if (Pmode
== DImode
)
7002 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7004 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7006 /* Mop up any left-over bytes. */
7008 mips_block_move_straight (dest
, src
, leftover
);
7011 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7012 memory reference SRC to memory reference DEST. */
7015 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7017 if (CONST_INT_P (length
))
7019 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7021 mips_block_move_straight (dest
, src
, INTVAL (length
));
7026 mips_block_move_loop (dest
, src
, INTVAL (length
),
7027 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7034 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7037 mips_expand_synci_loop (rtx begin
, rtx end
)
7039 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7041 /* Create end_label. */
7042 end_label
= gen_label_rtx ();
7044 /* Check if begin equals end. */
7045 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7046 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7048 /* Load INC with the cache line size (rdhwr INC,$1). */
7049 inc
= gen_reg_rtx (Pmode
);
7050 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7052 /* Check if inc is 0. */
7053 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7054 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7056 /* Calculate mask. */
7057 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7059 /* Mask out begin by mask. */
7060 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7062 /* Calculate length. */
7063 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7065 /* Loop back to here. */
7066 label
= gen_label_rtx ();
7069 emit_insn (gen_synci (begin
));
7071 /* Update length. */
7072 mips_emit_binary (MINUS
, length
, length
, inc
);
7075 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7077 /* Check if length is greater than 0. */
7078 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7079 emit_jump_insn (gen_condjump (cmp_result
, label
));
7081 emit_label (end_label
);
7084 /* Expand a QI or HI mode atomic memory operation.
7086 GENERATOR contains a pointer to the gen_* function that generates
7087 the SI mode underlying atomic operation using masks that we
7090 RESULT is the return register for the operation. Its value is NULL
7093 MEM is the location of the atomic access.
7095 OLDVAL is the first operand for the operation.
7097 NEWVAL is the optional second operand for the operation. Its value
7098 is NULL if unused. */
7101 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7102 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7104 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7105 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7107 enum machine_mode mode
;
7109 mode
= GET_MODE (mem
);
7111 /* Compute the address of the containing SImode value. */
7112 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7113 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7114 force_reg (Pmode
, GEN_INT (-4)));
7116 /* Create a memory reference for it. */
7117 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7118 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7119 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7121 /* Work out the byte offset of the QImode or HImode value,
7122 counting from the least significant byte. */
7123 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7124 if (TARGET_BIG_ENDIAN
)
7125 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7127 /* Multiply by eight to convert the shift value from bytes to bits. */
7128 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7130 /* Make the final shift an SImode value, so that it can be used in
7131 SImode operations. */
7132 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7134 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7135 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7136 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7137 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7139 /* Compute the equivalent exclusive mask. */
7140 inverted_mask
= gen_reg_rtx (SImode
);
7141 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7142 gen_rtx_NOT (SImode
, mask
)));
7144 /* Shift the old value into place. */
7145 if (oldval
!= const0_rtx
)
7147 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7148 oldval
= force_reg (SImode
, oldval
);
7149 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7152 /* Do the same for the new value. */
7153 if (newval
&& newval
!= const0_rtx
)
7155 newval
= convert_modes (SImode
, mode
, newval
, true);
7156 newval
= force_reg (SImode
, newval
);
7157 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7160 /* Do the SImode atomic access. */
7162 res
= gen_reg_rtx (SImode
);
7164 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7166 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7168 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7174 /* Shift and convert the result. */
7175 mips_emit_binary (AND
, res
, res
, mask
);
7176 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7177 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7181 /* Return true if it is possible to use left/right accesses for a
7182 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7183 returning true, update *OP, *LEFT and *RIGHT as follows:
7185 *OP is a BLKmode reference to the whole field.
7187 *LEFT is a QImode reference to the first byte if big endian or
7188 the last byte if little endian. This address can be used in the
7189 left-side instructions (LWL, SWL, LDL, SDL).
7191 *RIGHT is a QImode reference to the opposite end of the field and
7192 can be used in the patterning right-side instruction. */
7195 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7196 rtx
*left
, rtx
*right
)
7200 /* Check that the operand really is a MEM. Not all the extv and
7201 extzv predicates are checked. */
7205 /* Check that the size is valid. */
7206 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7209 /* We can only access byte-aligned values. Since we are always passed
7210 a reference to the first byte of the field, it is not necessary to
7211 do anything with BITPOS after this check. */
7212 if (bitpos
% BITS_PER_UNIT
!= 0)
7215 /* Reject aligned bitfields: we want to use a normal load or store
7216 instead of a left/right pair. */
7217 if (MEM_ALIGN (*op
) >= width
)
7220 /* Create a copy of *OP that refers to the whole field. This also has
7221 the effect of legitimizing *OP's address for BLKmode, possibly
7223 *op
= copy_rtx (adjust_address (*op
, BLKmode
, 0));
7224 set_mem_size (*op
, width
/ BITS_PER_UNIT
);
7226 /* Get references to both ends of the field. We deliberately don't
7227 use the original QImode *OP for FIRST since the new BLKmode one
7228 might have a simpler address. */
7229 first
= adjust_address (*op
, QImode
, 0);
7230 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7232 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7233 correspond to the MSB and RIGHT to the LSB. */
7234 if (TARGET_BIG_ENDIAN
)
7235 *left
= first
, *right
= last
;
7237 *left
= last
, *right
= first
;
7242 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7243 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7244 the operation is the equivalent of:
7246 (set DEST (*_extract SRC WIDTH BITPOS))
7248 Return true on success. */
7251 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7252 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7254 rtx left
, right
, temp
;
7255 rtx dest1
= NULL_RTX
;
7257 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7258 be a paradoxical word_mode subreg. This is the only case in which
7259 we allow the destination to be larger than the source. */
7260 if (GET_CODE (dest
) == SUBREG
7261 && GET_MODE (dest
) == DImode
7262 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
7263 dest
= SUBREG_REG (dest
);
7265 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7266 be a DImode, create a new temp and emit a zero extend at the end. */
7267 if (GET_MODE (dest
) == DImode
7269 && GET_MODE_BITSIZE (SImode
) == width
)
7272 dest
= gen_reg_rtx (SImode
);
7275 /* After the above adjustment, the destination must be the same
7276 width as the source. */
7277 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
7280 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
7283 temp
= gen_reg_rtx (GET_MODE (dest
));
7284 if (GET_MODE (dest
) == DImode
)
7286 emit_insn (gen_mov_ldl (temp
, src
, left
));
7287 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7291 emit_insn (gen_mov_lwl (temp
, src
, left
));
7292 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7295 /* If we were loading 32bits and the original register was DI then
7296 sign/zero extend into the orignal dest. */
7300 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7302 emit_insn (gen_extendsidi2 (dest1
, dest
));
7307 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7308 BITPOS and SRC are the operands passed to the expander; the operation
7309 is the equivalent of:
7311 (set (zero_extract DEST WIDTH BITPOS) SRC)
7313 Return true on success. */
7316 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7317 HOST_WIDE_INT bitpos
)
7320 enum machine_mode mode
;
7322 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
7325 mode
= mode_for_size (width
, MODE_INT
, 0);
7326 src
= gen_lowpart (mode
, src
);
7329 emit_insn (gen_mov_sdl (dest
, src
, left
));
7330 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7334 emit_insn (gen_mov_swl (dest
, src
, left
));
7335 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7340 /* Return true if X is a MEM with the same size as MODE. */
7343 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7346 && MEM_SIZE_KNOWN_P (x
)
7347 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7350 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7351 source of an "ext" instruction or the destination of an "ins"
7352 instruction. OP must be a register operand and the following
7353 conditions must hold:
7355 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7356 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7357 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7359 Also reject lengths equal to a word as they are better handled
7360 by the move patterns. */
7363 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7365 if (!ISA_HAS_EXT_INS
7366 || !register_operand (op
, VOIDmode
)
7367 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7370 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7373 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7379 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7380 operation if MAXLEN is the maxium length of consecutive bits that
7381 can make up MASK. MODE is the mode of the operation. See
7382 mask_low_and_shift_len for the actual definition. */
7385 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7387 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7390 /* Return true iff OP1 and OP2 are valid operands together for the
7391 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7392 see the table in the comment before the pattern. */
7395 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7397 return (memory_operand (op1
, mode
)
7398 ? and_load_operand (op2
, mode
)
7399 : and_reg_operand (op2
, mode
));
7402 /* The canonical form of a mask-low-and-shift-left operation is
7403 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7404 cleared. Thus we need to shift MASK to the right before checking if it
7405 is a valid mask value. MODE is the mode of the operation. If true
7406 return the length of the mask, otherwise return -1. */
7409 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7411 HOST_WIDE_INT shval
;
7413 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7414 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7417 /* Return true if -msplit-addresses is selected and should be honored.
7419 -msplit-addresses is a half-way house between explicit relocations
7420 and the traditional assembler macros. It can split absolute 32-bit
7421 symbolic constants into a high/lo_sum pair but uses macros for other
7424 Like explicit relocation support for REL targets, it relies
7425 on GNU extensions in the assembler and the linker.
7427 Although this code should work for -O0, it has traditionally
7428 been treated as an optimization. */
7431 mips_split_addresses_p (void)
7433 return (TARGET_SPLIT_ADDRESSES
7437 && !ABI_HAS_64BIT_SYMBOLS
);
7440 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7443 mips_init_relocs (void)
7445 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7446 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7447 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7448 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7449 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7451 if (TARGET_MIPS16_PCREL_LOADS
)
7452 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7455 if (ABI_HAS_64BIT_SYMBOLS
)
7457 if (TARGET_EXPLICIT_RELOCS
)
7459 mips_split_p
[SYMBOL_64_HIGH
] = true;
7460 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7461 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7463 mips_split_p
[SYMBOL_64_MID
] = true;
7464 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7465 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7467 mips_split_p
[SYMBOL_64_LOW
] = true;
7468 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7469 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7471 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7472 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7477 if (TARGET_EXPLICIT_RELOCS
7478 || mips_split_addresses_p ()
7481 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7482 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7483 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7490 /* The high part is provided by a pseudo copy of $gp. */
7491 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7492 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7494 else if (TARGET_EXPLICIT_RELOCS
)
7495 /* Small data constants are kept whole until after reload,
7496 then lowered by mips_rewrite_small_data. */
7497 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7499 if (TARGET_EXPLICIT_RELOCS
)
7501 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7504 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7505 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7509 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7510 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7513 /* Expose the use of $28 as soon as possible. */
7514 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7518 /* The HIGH and LO_SUM are matched by special .md patterns. */
7519 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7521 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7522 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7523 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7525 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7526 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7527 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7532 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7534 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7535 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7537 /* Expose the use of $28 as soon as possible. */
7538 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7544 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7545 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7546 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7549 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7550 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7552 if (TARGET_MIPS16_PCREL_LOADS
)
7554 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7555 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7559 mips_split_p
[SYMBOL_DTPREL
] = true;
7560 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7561 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7563 mips_split_p
[SYMBOL_TPREL
] = true;
7564 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7565 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7568 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7569 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7572 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7573 in context CONTEXT. RELOCS is the array of relocations to use. */
7576 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7577 const char **relocs
)
7579 enum mips_symbol_type symbol_type
;
7582 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7583 gcc_assert (relocs
[symbol_type
]);
7585 fputs (relocs
[symbol_type
], file
);
7586 output_addr_const (file
, mips_strip_unspec_address (op
));
7587 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7592 /* Start a new block with the given asm switch enabled. If we need
7593 to print a directive, emit PREFIX before it and SUFFIX after it. */
7596 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7597 const char *prefix
, const char *suffix
)
7599 if (asm_switch
->nesting_level
== 0)
7600 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7601 asm_switch
->nesting_level
++;
7604 /* Likewise, but end a block. */
7607 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7608 const char *prefix
, const char *suffix
)
7610 gcc_assert (asm_switch
->nesting_level
);
7611 asm_switch
->nesting_level
--;
7612 if (asm_switch
->nesting_level
== 0)
7613 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7616 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7617 that either print a complete line or print nothing. */
7620 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7622 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7626 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7628 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7631 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7632 The punctuation characters are:
7634 '(' Start a nested ".set noreorder" block.
7635 ')' End a nested ".set noreorder" block.
7636 '[' Start a nested ".set noat" block.
7637 ']' End a nested ".set noat" block.
7638 '<' Start a nested ".set nomacro" block.
7639 '>' End a nested ".set nomacro" block.
7640 '*' Behave like %(%< if generating a delayed-branch sequence.
7641 '#' Print a nop if in a ".set noreorder" block.
7642 '/' Like '#', but do nothing within a delayed-branch sequence.
7643 '?' Print "l" if mips_branch_likely is true
7644 '~' Print a nop if mips_branch_likely is true
7645 '.' Print the name of the register with a hard-wired zero (zero or $0).
7646 '@' Print the name of the assembler temporary register (at or $1).
7647 '^' Print the name of the pic call-through register (t9 or $25).
7648 '+' Print the name of the gp register (usually gp or $28).
7649 '$' Print the name of the stack pointer register (sp or $29).
7651 See also mips_init_print_operand_pucnt. */
7654 mips_print_operand_punctuation (FILE *file
, int ch
)
7659 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7663 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7667 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7671 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7675 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7679 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7683 if (final_sequence
!= 0)
7685 mips_print_operand_punctuation (file
, '(');
7686 mips_print_operand_punctuation (file
, '<');
7691 if (mips_noreorder
.nesting_level
> 0)
7692 fputs ("\n\tnop", file
);
7696 /* Print an extra newline so that the delayed insn is separated
7697 from the following ones. This looks neater and is consistent
7698 with non-nop delayed sequences. */
7699 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7700 fputs ("\n\tnop\n", file
);
7704 if (mips_branch_likely
)
7709 if (mips_branch_likely
)
7710 fputs ("\n\tnop", file
);
7714 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7718 fputs (reg_names
[AT_REGNUM
], file
);
7722 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7726 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7730 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7739 /* Initialize mips_print_operand_punct. */
7742 mips_init_print_operand_punct (void)
7746 for (p
= "()[]<>*#/?~.@^+$"; *p
; p
++)
7747 mips_print_operand_punct
[(unsigned char) *p
] = true;
7750 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7751 associated with condition CODE. Print the condition part of the
7755 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7769 /* Conveniently, the MIPS names for these conditions are the same
7770 as their RTL equivalents. */
7771 fputs (GET_RTX_NAME (code
), file
);
7775 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7780 /* Likewise floating-point branches. */
7783 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7788 fputs ("c1f", file
);
7792 fputs ("c1t", file
);
7796 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7801 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7804 mips_print_operand_punct_valid_p (unsigned char code
)
7806 return mips_print_operand_punct
[code
];
7809 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7811 'X' Print CONST_INT OP in hexadecimal format.
7812 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7813 'd' Print CONST_INT OP in decimal.
7814 'm' Print one less than CONST_INT OP in decimal.
7815 'h' Print the high-part relocation associated with OP, after stripping
7817 'R' Print the low-part relocation associated with OP.
7818 'C' Print the integer branch condition for comparison OP.
7819 'N' Print the inverse of the integer branch condition for comparison OP.
7820 'F' Print the FPU branch condition for comparison OP.
7821 'W' Print the inverse of the FPU branch condition for comparison OP.
7822 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7823 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7824 't' Like 'T', but with the EQ/NE cases reversed
7825 'Y' Print mips_fp_conditions[INTVAL (OP)]
7826 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7827 'q' Print a DSP accumulator register.
7828 'D' Print the second part of a double-word register or memory operand.
7829 'L' Print the low-order register in a double-word register operand.
7830 'M' Print high-order register in a double-word register operand.
7831 'z' Print $0 if OP is zero, otherwise print OP normally.
7832 'b' Print the address of a memory operand, without offset. */
7835 mips_print_operand (FILE *file
, rtx op
, int letter
)
7839 if (mips_print_operand_punct_valid_p (letter
))
7841 mips_print_operand_punctuation (file
, letter
);
7846 code
= GET_CODE (op
);
7851 if (CONST_INT_P (op
))
7852 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
7854 output_operand_lossage ("invalid use of '%%%c'", letter
);
7858 if (CONST_INT_P (op
))
7859 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
7861 output_operand_lossage ("invalid use of '%%%c'", letter
);
7865 if (CONST_INT_P (op
))
7866 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
7868 output_operand_lossage ("invalid use of '%%%c'", letter
);
7872 if (CONST_INT_P (op
))
7873 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
7875 output_operand_lossage ("invalid use of '%%%c'", letter
);
7881 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
7885 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
7889 mips_print_int_branch_condition (file
, code
, letter
);
7893 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
7897 mips_print_float_branch_condition (file
, code
, letter
);
7901 mips_print_float_branch_condition (file
, reverse_condition (code
),
7908 int truth
= (code
== NE
) == (letter
== 'T');
7909 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
7914 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
7915 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
7917 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7924 mips_print_operand (file
, op
, 0);
7930 if (code
== REG
&& MD_REG_P (REGNO (op
)))
7931 fprintf (file
, "$ac0");
7932 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
7933 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
7935 output_operand_lossage ("invalid use of '%%%c'", letter
);
7943 unsigned int regno
= REGNO (op
);
7944 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
7945 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
7948 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
7949 output_operand_lossage ("invalid use of '%%%c'", letter
);
7950 /* We need to print $0 .. $31 for COP0 registers. */
7951 if (COP0_REG_P (regno
))
7952 fprintf (file
, "$%s", ®_names
[regno
][4]);
7954 fprintf (file
, "%s", reg_names
[regno
]);
7960 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
7961 else if (letter
== 'b')
7963 gcc_assert (REG_P (XEXP (op
, 0)));
7964 mips_print_operand (file
, XEXP (op
, 0), 0);
7966 else if (letter
&& letter
!= 'z')
7967 output_operand_lossage ("invalid use of '%%%c'", letter
);
7969 output_address (XEXP (op
, 0));
7973 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
7974 fputs (reg_names
[GP_REG_FIRST
], file
);
7975 else if (letter
&& letter
!= 'z')
7976 output_operand_lossage ("invalid use of '%%%c'", letter
);
7977 else if (CONST_GP_P (op
))
7978 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
7980 output_addr_const (file
, mips_strip_unspec_address (op
));
7986 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7989 mips_print_operand_address (FILE *file
, rtx x
)
7991 struct mips_address_info addr
;
7993 if (mips_classify_address (&addr
, x
, word_mode
, true))
7997 mips_print_operand (file
, addr
.offset
, 0);
7998 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8001 case ADDRESS_LO_SUM
:
8002 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8004 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8007 case ADDRESS_CONST_INT
:
8008 output_addr_const (file
, x
);
8009 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8012 case ADDRESS_SYMBOLIC
:
8013 output_addr_const (file
, mips_strip_unspec_address (x
));
8019 /* Implement TARGET_ENCODE_SECTION_INFO. */
8022 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8024 default_encode_section_info (decl
, rtl
, first
);
8026 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8028 rtx symbol
= XEXP (rtl
, 0);
8029 tree type
= TREE_TYPE (decl
);
8031 /* Encode whether the symbol is short or long. */
8032 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8033 || mips_far_type_p (type
))
8034 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8038 /* Implement TARGET_SELECT_RTX_SECTION. */
8041 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8042 unsigned HOST_WIDE_INT align
)
8044 /* ??? Consider using mergeable small data sections. */
8045 if (mips_rtx_constant_in_small_data_p (mode
))
8046 return get_named_section (NULL
, ".sdata", 0);
8048 return default_elf_select_rtx_section (mode
, x
, align
);
8051 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8053 The complication here is that, with the combination TARGET_ABICALLS
8054 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8055 absolute addresses, and should therefore not be included in the
8056 read-only part of a DSO. Handle such cases by selecting a normal
8057 data section instead of a read-only one. The logic apes that in
8058 default_function_rodata_section. */
8061 mips_function_rodata_section (tree decl
)
8063 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8064 return default_function_rodata_section (decl
);
8066 if (decl
&& DECL_SECTION_NAME (decl
))
8068 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8069 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8071 char *rname
= ASTRDUP (name
);
8073 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8075 else if (flag_function_sections
8076 && flag_data_sections
8077 && strncmp (name
, ".text.", 6) == 0)
8079 char *rname
= ASTRDUP (name
);
8080 memcpy (rname
+ 1, "data", 4);
8081 return get_section (rname
, SECTION_WRITE
, decl
);
8084 return data_section
;
8087 /* Implement TARGET_IN_SMALL_DATA_P. */
8090 mips_in_small_data_p (const_tree decl
)
8092 unsigned HOST_WIDE_INT size
;
8094 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8097 /* We don't yet generate small-data references for -mabicalls
8098 or VxWorks RTP code. See the related -G handling in
8099 mips_option_override. */
8100 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8103 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8107 /* Reject anything that isn't in a known small-data section. */
8108 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8109 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8112 /* If a symbol is defined externally, the assembler will use the
8113 usual -G rules when deciding how to implement macros. */
8114 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8117 else if (TARGET_EMBEDDED_DATA
)
8119 /* Don't put constants into the small data section: we want them
8120 to be in ROM rather than RAM. */
8121 if (TREE_CODE (decl
) != VAR_DECL
)
8124 if (TREE_READONLY (decl
)
8125 && !TREE_SIDE_EFFECTS (decl
)
8126 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8130 /* Enforce -mlocal-sdata. */
8131 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8134 /* Enforce -mextern-sdata. */
8135 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8137 if (DECL_EXTERNAL (decl
))
8139 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8143 /* We have traditionally not treated zero-sized objects as small data,
8144 so this is now effectively part of the ABI. */
8145 size
= int_size_in_bytes (TREE_TYPE (decl
));
8146 return size
> 0 && size
<= mips_small_data_threshold
;
8149 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8150 anchors for small data: the GP register acts as an anchor in that
8151 case. We also don't want to use them for PC-relative accesses,
8152 where the PC acts as an anchor. */
8155 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8157 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8159 case SYMBOL_PC_RELATIVE
:
8160 case SYMBOL_GP_RELATIVE
:
8164 return default_use_anchors_for_symbol_p (symbol
);
8168 /* The MIPS debug format wants all automatic variables and arguments
8169 to be in terms of the virtual frame pointer (stack pointer before
8170 any adjustment in the function), while the MIPS 3.0 linker wants
8171 the frame pointer to be the stack pointer after the initial
8172 adjustment. So, we do the adjustment here. The arg pointer (which
8173 is eliminated) points to the virtual frame pointer, while the frame
8174 pointer (which may be eliminated) points to the stack pointer after
8175 the initial adjustments. */
8178 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8180 rtx offset2
= const0_rtx
;
8181 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8184 offset
= INTVAL (offset2
);
8186 if (reg
== stack_pointer_rtx
8187 || reg
== frame_pointer_rtx
8188 || reg
== hard_frame_pointer_rtx
)
8190 offset
-= cfun
->machine
->frame
.total_size
;
8191 if (reg
== hard_frame_pointer_rtx
)
8192 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8198 /* Implement ASM_OUTPUT_EXTERNAL. */
8201 mips_output_external (FILE *file
, tree decl
, const char *name
)
8203 default_elf_asm_output_external (file
, decl
, name
);
8205 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8206 set in order to avoid putting out names that are never really
8208 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8210 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8212 /* When using assembler macros, emit .extern directives for
8213 all small-data externs so that the assembler knows how
8216 In most cases it would be safe (though pointless) to emit
8217 .externs for other symbols too. One exception is when an
8218 object is within the -G limit but declared by the user to
8219 be in a section other than .sbss or .sdata. */
8220 fputs ("\t.extern\t", file
);
8221 assemble_name (file
, name
);
8222 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8223 int_size_in_bytes (TREE_TYPE (decl
)));
8228 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8231 mips_output_filename (FILE *stream
, const char *name
)
8233 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8235 if (write_symbols
== DWARF2_DEBUG
)
8237 else if (mips_output_filename_first_time
)
8239 mips_output_filename_first_time
= 0;
8240 num_source_filenames
+= 1;
8241 current_function_file
= name
;
8242 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8243 output_quoted_string (stream
, name
);
8244 putc ('\n', stream
);
8246 /* If we are emitting stabs, let dbxout.c handle this (except for
8247 the mips_output_filename_first_time case). */
8248 else if (write_symbols
== DBX_DEBUG
)
8250 else if (name
!= current_function_file
8251 && strcmp (name
, current_function_file
) != 0)
8253 num_source_filenames
+= 1;
8254 current_function_file
= name
;
8255 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8256 output_quoted_string (stream
, name
);
8257 putc ('\n', stream
);
8261 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8263 static void ATTRIBUTE_UNUSED
8264 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8269 fputs ("\t.dtprelword\t", file
);
8273 fputs ("\t.dtpreldword\t", file
);
8279 output_addr_const (file
, x
);
8280 fputs ("+0x8000", file
);
8283 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8286 mips_dwarf_register_span (rtx reg
)
8289 enum machine_mode mode
;
8291 /* By default, GCC maps increasing register numbers to increasing
8292 memory locations, but paired FPRs are always little-endian,
8293 regardless of the prevailing endianness. */
8294 mode
= GET_MODE (reg
);
8295 if (FP_REG_P (REGNO (reg
))
8296 && TARGET_BIG_ENDIAN
8297 && MAX_FPRS_PER_FMT
> 1
8298 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8300 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8301 high
= mips_subword (reg
, true);
8302 low
= mips_subword (reg
, false);
8303 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8309 /* Implement ASM_OUTPUT_ASCII. */
8312 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8318 fprintf (stream
, "\t.ascii\t\"");
8319 for (i
= 0; i
< len
; i
++)
8323 c
= (unsigned char) string
[i
];
8326 if (c
== '\\' || c
== '\"')
8328 putc ('\\', stream
);
8336 fprintf (stream
, "\\%03o", c
);
8340 if (cur_pos
> 72 && i
+1 < len
)
8343 fprintf (stream
, "\"\n\t.ascii\t\"");
8346 fprintf (stream
, "\"\n");
8349 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8350 Update *ADDR with the operand that should be printed. */
8353 mips_output_tls_reloc_directive (rtx
*addr
)
8355 enum mips_symbol_type type
;
8357 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8358 *addr
= mips_strip_unspec_address (*addr
);
8362 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8365 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8372 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8373 macros, mark the symbol as written so that mips_asm_output_external
8374 won't emit an .extern for it. STREAM is the output file, NAME is the
8375 name of the symbol, INIT_STRING is the string that should be written
8376 before the symbol and FINAL_STRING is the string that should be
8377 written after it. FINAL_STRING is a printf format that consumes the
8378 remaining arguments. */
8381 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8382 const char *final_string
, ...)
8386 fputs (init_string
, stream
);
8387 assemble_name (stream
, name
);
8388 va_start (ap
, final_string
);
8389 vfprintf (stream
, final_string
, ap
);
8392 if (!TARGET_EXPLICIT_RELOCS
)
8394 tree name_tree
= get_identifier (name
);
8395 TREE_ASM_WRITTEN (name_tree
) = 1;
8399 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8400 NAME is the name of the object and ALIGN is the required alignment
8401 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8402 alignment argument. */
8405 mips_declare_common_object (FILE *stream
, const char *name
,
8406 const char *init_string
,
8407 unsigned HOST_WIDE_INT size
,
8408 unsigned int align
, bool takes_alignment_p
)
8410 if (!takes_alignment_p
)
8412 size
+= (align
/ BITS_PER_UNIT
) - 1;
8413 size
-= size
% (align
/ BITS_PER_UNIT
);
8414 mips_declare_object (stream
, name
, init_string
,
8415 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8418 mips_declare_object (stream
, name
, init_string
,
8419 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8420 size
, align
/ BITS_PER_UNIT
);
8423 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8424 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8427 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8428 unsigned HOST_WIDE_INT size
,
8431 /* If the target wants uninitialized const declarations in
8432 .rdata then don't put them in .comm. */
8433 if (TARGET_EMBEDDED_DATA
8434 && TARGET_UNINIT_CONST_IN_RODATA
8435 && TREE_CODE (decl
) == VAR_DECL
8436 && TREE_READONLY (decl
)
8437 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8439 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8440 targetm
.asm_out
.globalize_label (stream
, name
);
8442 switch_to_section (readonly_data_section
);
8443 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8444 mips_declare_object (stream
, name
, "",
8445 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8449 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8453 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8454 extern int size_directive_output
;
8456 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8457 definitions except that it uses mips_declare_object to emit the label. */
8460 mips_declare_object_name (FILE *stream
, const char *name
,
8461 tree decl ATTRIBUTE_UNUSED
)
8463 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8464 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8467 size_directive_output
= 0;
8468 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8472 size_directive_output
= 1;
8473 size
= int_size_in_bytes (TREE_TYPE (decl
));
8474 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8477 mips_declare_object (stream
, name
, "", ":\n");
8480 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8483 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8487 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8488 if (!flag_inhibit_size_directive
8489 && DECL_SIZE (decl
) != 0
8492 && DECL_INITIAL (decl
) == error_mark_node
8493 && !size_directive_output
)
8497 size_directive_output
= 1;
8498 size
= int_size_in_bytes (TREE_TYPE (decl
));
8499 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8504 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8505 with the current ABI. */
8508 mips_mdebug_abi_name (void)
8521 return TARGET_64BIT
? "eabi64" : "eabi32";
8527 /* Implement TARGET_ASM_FILE_START. */
8530 mips_file_start (void)
8532 default_file_start ();
8534 /* Generate a special section to describe the ABI switches used to
8535 produce the resultant binary. */
8537 /* Record the ABI itself. Modern versions of binutils encode
8538 this information in the ELF header flags, but GDB needs the
8539 information in order to correctly debug binaries produced by
8540 older binutils. See the function mips_gdbarch_init in
8542 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8543 mips_mdebug_abi_name ());
8545 /* There is no ELF header flag to distinguish long32 forms of the
8546 EABI from long64 forms. Emit a special section to help tools
8547 such as GDB. Do the same for o64, which is sometimes used with
8549 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8550 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8551 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8553 #ifdef HAVE_AS_GNU_ATTRIBUTE
8557 /* No floating-point operations, -mno-float. */
8558 if (TARGET_NO_FLOAT
)
8560 /* Soft-float code, -msoft-float. */
8561 else if (!TARGET_HARD_FLOAT_ABI
)
8563 /* Single-float code, -msingle-float. */
8564 else if (!TARGET_DOUBLE_FLOAT
)
8566 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8567 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8569 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8573 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8577 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8578 if (TARGET_ABICALLS
)
8580 fprintf (asm_out_file
, "\t.abicalls\n");
8581 if (TARGET_ABICALLS_PIC0
)
8582 fprintf (asm_out_file
, "\t.option\tpic0\n");
8585 if (flag_verbose_asm
)
8586 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8588 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8591 /* Implement TARGET_ASM_CODE_END. */
8594 mips_code_end (void)
8596 if (mips_need_mips16_rdhwr_p
)
8597 mips_output_mips16_rdhwr ();
8600 /* Make the last instruction frame-related and note that it performs
8601 the operation described by FRAME_PATTERN. */
8604 mips_set_frame_expr (rtx frame_pattern
)
8608 insn
= get_last_insn ();
8609 RTX_FRAME_RELATED_P (insn
) = 1;
8610 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8615 /* Return a frame-related rtx that stores REG at MEM.
8616 REG must be a single register. */
8619 mips_frame_set (rtx mem
, rtx reg
)
8623 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8624 RTX_FRAME_RELATED_P (set
) = 1;
8629 /* Record that the epilogue has restored call-saved register REG. */
8632 mips_add_cfa_restore (rtx reg
)
8634 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8635 mips_epilogue
.cfa_restores
);
8638 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8639 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8640 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8641 static const unsigned char mips16e_s2_s8_regs
[] = {
8642 30, 23, 22, 21, 20, 19, 18
8644 static const unsigned char mips16e_a0_a3_regs
[] = {
8648 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8649 ordered from the uppermost in memory to the lowest in memory. */
8650 static const unsigned char mips16e_save_restore_regs
[] = {
8651 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8654 /* Return the index of the lowest X in the range [0, SIZE) for which
8655 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8658 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8663 for (i
= 0; i
< size
; i
++)
8664 if (BITSET_P (mask
, regs
[i
]))
8670 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8671 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8672 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8673 is true for all indexes (X, SIZE). */
8676 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8677 unsigned int size
, unsigned int *num_regs_ptr
)
8681 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8682 for (i
++; i
< size
; i
++)
8683 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8686 *mask_ptr
|= 1 << regs
[i
];
8690 /* Return a simplified form of X using the register values in REG_VALUES.
8691 REG_VALUES[R] is the last value assigned to hard register R, or null
8692 if R has not been modified.
8694 This function is rather limited, but is good enough for our purposes. */
8697 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8699 x
= avoid_constant_pool_reference (x
);
8703 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8704 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8705 x0
, GET_MODE (XEXP (x
, 0)));
8708 if (ARITHMETIC_P (x
))
8710 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8711 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8712 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8716 && reg_values
[REGNO (x
)]
8717 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8718 return reg_values
[REGNO (x
)];
8723 /* Return true if (set DEST SRC) stores an argument register into its
8724 caller-allocated save slot, storing the number of that argument
8725 register in *REGNO_PTR if so. REG_VALUES is as for
8726 mips16e_collect_propagate_value. */
8729 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
8730 unsigned int *regno_ptr
)
8732 unsigned int argno
, regno
;
8733 HOST_WIDE_INT offset
, required_offset
;
8736 /* Check that this is a word-mode store. */
8737 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
8740 /* Check that the register being saved is an unmodified argument
8742 regno
= REGNO (src
);
8743 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
8745 argno
= regno
- GP_ARG_FIRST
;
8747 /* Check whether the address is an appropriate stack-pointer or
8748 frame-pointer access. */
8749 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
8750 mips_split_plus (addr
, &base
, &offset
);
8751 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
8752 if (base
== hard_frame_pointer_rtx
)
8753 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8754 else if (base
!= stack_pointer_rtx
)
8756 if (offset
!= required_offset
)
8763 /* A subroutine of mips_expand_prologue, called only when generating
8764 MIPS16e SAVE instructions. Search the start of the function for any
8765 instructions that save argument registers into their caller-allocated
8766 save slots. Delete such instructions and return a value N such that
8767 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8768 instructions redundant. */
8771 mips16e_collect_argument_saves (void)
8773 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
8774 rtx insn
, next
, set
, dest
, src
;
8775 unsigned int nargs
, regno
;
8777 push_topmost_sequence ();
8779 memset (reg_values
, 0, sizeof (reg_values
));
8780 for (insn
= get_insns (); insn
; insn
= next
)
8782 next
= NEXT_INSN (insn
);
8783 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
8789 set
= PATTERN (insn
);
8790 if (GET_CODE (set
) != SET
)
8793 dest
= SET_DEST (set
);
8794 src
= SET_SRC (set
);
8795 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
8797 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
8800 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
8803 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
8804 reg_values
[REGNO (dest
)]
8805 = mips16e_collect_propagate_value (src
, reg_values
);
8809 pop_topmost_sequence ();
8814 /* Return a move between register REGNO and memory location SP + OFFSET.
8815 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
8816 Make the move a load if RESTORE_P, otherwise make it a store. */
8819 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
8820 HOST_WIDE_INT offset
, unsigned int regno
)
8824 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
8826 reg
= gen_rtx_REG (SImode
, regno
);
8829 mips_add_cfa_restore (reg
);
8830 return gen_rtx_SET (VOIDmode
, reg
, mem
);
8833 return gen_rtx_SET (VOIDmode
, mem
, reg
);
8834 return mips_frame_set (mem
, reg
);
8837 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8838 The instruction must:
8840 - Allocate or deallocate SIZE bytes in total; SIZE is known
8843 - Save or restore as many registers in *MASK_PTR as possible.
8844 The instruction saves the first registers at the top of the
8845 allocated area, with the other registers below it.
8847 - Save NARGS argument registers above the allocated area.
8849 (NARGS is always zero if RESTORE_P.)
8851 The SAVE and RESTORE instructions cannot save and restore all general
8852 registers, so there may be some registers left over for the caller to
8853 handle. Destructively modify *MASK_PTR so that it contains the registers
8854 that still need to be saved or restored. The caller can save these
8855 registers in the memory immediately below *OFFSET_PTR, which is a
8856 byte offset from the bottom of the allocated stack area. */
8859 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
8860 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
8864 HOST_WIDE_INT offset
, top_offset
;
8865 unsigned int i
, regno
;
8868 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
8870 /* Calculate the number of elements in the PARALLEL. We need one element
8871 for the stack adjustment, one for each argument register save, and one
8872 for each additional register move. */
8874 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8875 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
8878 /* Create the final PARALLEL. */
8879 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
8882 /* Add the stack pointer adjustment. */
8883 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8884 plus_constant (Pmode
, stack_pointer_rtx
,
8885 restore_p
? size
: -size
));
8886 RTX_FRAME_RELATED_P (set
) = 1;
8887 XVECEXP (pattern
, 0, n
++) = set
;
8889 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8890 top_offset
= restore_p
? size
: 0;
8892 /* Save the arguments. */
8893 for (i
= 0; i
< nargs
; i
++)
8895 offset
= top_offset
+ i
* UNITS_PER_WORD
;
8896 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
8898 XVECEXP (pattern
, 0, n
++) = set
;
8901 /* Then fill in the other register moves. */
8902 offset
= top_offset
;
8903 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8905 regno
= mips16e_save_restore_regs
[i
];
8906 if (BITSET_P (*mask_ptr
, regno
))
8908 offset
-= UNITS_PER_WORD
;
8909 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
8910 XVECEXP (pattern
, 0, n
++) = set
;
8911 *mask_ptr
&= ~(1 << regno
);
8915 /* Tell the caller what offset it should use for the remaining registers. */
8916 *offset_ptr
= size
+ (offset
- top_offset
);
8918 gcc_assert (n
== XVECLEN (pattern
, 0));
8923 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8924 pointer. Return true if PATTERN matches the kind of instruction
8925 generated by mips16e_build_save_restore. If INFO is nonnull,
8926 initialize it when returning true. */
8929 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
8930 struct mips16e_save_restore_info
*info
)
8932 unsigned int i
, nargs
, mask
, extra
;
8933 HOST_WIDE_INT top_offset
, save_offset
, offset
;
8934 rtx set
, reg
, mem
, base
;
8937 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
8940 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8941 top_offset
= adjust
> 0 ? adjust
: 0;
8943 /* Interpret all other members of the PARALLEL. */
8944 save_offset
= top_offset
- UNITS_PER_WORD
;
8948 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
8950 /* Check that we have a SET. */
8951 set
= XVECEXP (pattern
, 0, n
);
8952 if (GET_CODE (set
) != SET
)
8955 /* Check that the SET is a load (if restoring) or a store
8957 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
8961 /* Check that the address is the sum of the stack pointer and a
8962 possibly-zero constant offset. */
8963 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
8964 if (base
!= stack_pointer_rtx
)
8967 /* Check that SET's other operand is a register. */
8968 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
8972 /* Check for argument saves. */
8973 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
8974 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
8976 else if (offset
== save_offset
)
8978 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
8979 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
8982 mask
|= 1 << REGNO (reg
);
8983 save_offset
-= UNITS_PER_WORD
;
8989 /* Check that the restrictions on register ranges are met. */
8991 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
8992 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
8993 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
8994 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
8998 /* Make sure that the topmost argument register is not saved twice.
8999 The checks above ensure that the same is then true for the other
9000 argument registers. */
9001 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9004 /* Pass back information, if requested. */
9007 info
->nargs
= nargs
;
9009 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9015 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9016 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9017 the null terminator. */
9020 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9021 unsigned int max_reg
)
9023 if (min_reg
!= max_reg
)
9024 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9026 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9030 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9031 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9034 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9036 static char buffer
[300];
9038 struct mips16e_save_restore_info info
;
9039 unsigned int i
, end
;
9042 /* Parse the pattern. */
9043 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9046 /* Add the mnemonic. */
9047 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9050 /* Save the arguments. */
9052 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9053 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9054 else if (info
.nargs
== 1)
9055 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9057 /* Emit the amount of stack space to allocate or deallocate. */
9058 s
+= sprintf (s
, "%d", (int) info
.size
);
9060 /* Save or restore $16. */
9061 if (BITSET_P (info
.mask
, 16))
9062 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9064 /* Save or restore $17. */
9065 if (BITSET_P (info
.mask
, 17))
9066 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9068 /* Save or restore registers in the range $s2...$s8, which
9069 mips16e_s2_s8_regs lists in decreasing order. Note that this
9070 is a software register range; the hardware registers are not
9071 numbered consecutively. */
9072 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9073 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9075 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9076 mips16e_s2_s8_regs
[i
]);
9078 /* Save or restore registers in the range $a0...$a3. */
9079 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9080 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9082 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9083 mips16e_a0_a3_regs
[end
- 1]);
9085 /* Save or restore $31. */
9086 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9087 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9092 /* Return true if the current function returns its value in a floating-point
9093 register in MIPS16 mode. */
9096 mips16_cfun_returns_in_fpr_p (void)
9098 tree return_type
= DECL_RESULT (current_function_decl
);
9099 return (TARGET_MIPS16
9100 && TARGET_HARD_FLOAT_ABI
9101 && !aggregate_value_p (return_type
, current_function_decl
)
9102 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9105 /* Return true if predicate PRED is true for at least one instruction.
9106 Cache the result in *CACHE, and assume that the result is true
9107 if *CACHE is already true. */
9110 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9116 push_topmost_sequence ();
9117 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9118 if (USEFUL_INSN_P (insn
) && pred (insn
))
9123 pop_topmost_sequence ();
9128 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9129 See mips_cfun_has_inflexible_gp_ref_p for details. */
9132 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9134 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9135 indicate that the target could be a traditional MIPS
9136 lazily-binding stub. */
9137 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9140 /* Return true if the current function refers to the global pointer
9141 in a way that forces $28 to be valid. This means that we can't
9142 change the choice of global pointer, even for NewABI code.
9144 One example of this (and one which needs several checks) is that
9145 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9146 (This restriction does not apply to PLTs.) */
9149 mips_cfun_has_inflexible_gp_ref_p (void)
9151 /* If the function has a nonlocal goto, $28 must hold the correct
9152 global pointer for the target function. That is, the target
9153 of the goto implicitly uses $28. */
9154 if (crtl
->has_nonlocal_goto
)
9157 if (TARGET_ABICALLS_PIC2
)
9159 /* Symbolic accesses implicitly use the global pointer unless
9160 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9161 might go to traditional MIPS lazy-binding stubs. */
9162 if (!TARGET_EXPLICIT_RELOCS
)
9165 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9166 can be lazily-bound. */
9170 /* MIPS16 functions that return in FPRs need to call an
9171 external libgcc routine. This call is only made explict
9172 during mips_expand_epilogue, and it too might be lazily bound. */
9173 if (mips16_cfun_returns_in_fpr_p ())
9177 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9178 mips_insn_has_inflexible_gp_ref_p
);
9181 /* Return true if INSN refers to the global pointer in a "flexible" way.
9182 See mips_cfun_has_flexible_gp_ref_p for details. */
9185 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9187 return (get_attr_got (insn
) != GOT_UNSET
9188 || mips_small_data_pattern_p (PATTERN (insn
))
9189 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9192 /* Return true if the current function references the global pointer,
9193 but if those references do not inherently require the global pointer
9194 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9197 mips_cfun_has_flexible_gp_ref_p (void)
9199 /* Reload can sometimes introduce constant pool references
9200 into a function that otherwise didn't need them. For example,
9201 suppose we have an instruction like:
9203 (set (reg:DF R1) (float:DF (reg:SI R2)))
9205 If R2 turns out to be a constant such as 1, the instruction may
9206 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9207 the option of using this constant if R2 doesn't get allocated
9210 In cases like these, reload will have added the constant to the
9211 pool but no instruction will yet refer to it. */
9212 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9215 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9216 mips_insn_has_flexible_gp_ref_p
);
9219 /* Return the register that should be used as the global pointer
9220 within this function. Return INVALID_REGNUM if the function
9221 doesn't need a global pointer. */
9224 mips_global_pointer (void)
9228 /* $gp is always available unless we're using a GOT. */
9229 if (!TARGET_USE_GOT
)
9230 return GLOBAL_POINTER_REGNUM
;
9232 /* If there are inflexible references to $gp, we must use the
9233 standard register. */
9234 if (mips_cfun_has_inflexible_gp_ref_p ())
9235 return GLOBAL_POINTER_REGNUM
;
9237 /* If there are no current references to $gp, then the only uses
9238 we can introduce later are those involved in long branches. */
9239 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9240 return INVALID_REGNUM
;
9242 /* If the global pointer is call-saved, try to use a call-clobbered
9244 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9245 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9246 if (!df_regs_ever_live_p (regno
)
9247 && call_really_used_regs
[regno
]
9248 && !fixed_regs
[regno
]
9249 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9252 return GLOBAL_POINTER_REGNUM
;
9255 /* Return true if the current function's prologue must load the global
9256 pointer value into pic_offset_table_rtx and store the same value in
9257 the function's cprestore slot (if any).
9259 One problem we have to deal with is that, when emitting GOT-based
9260 position independent code, long-branch sequences will need to load
9261 the address of the branch target from the GOT. We don't know until
9262 the very end of compilation whether (and where) the function needs
9263 long branches, so we must ensure that _any_ branch can access the
9264 global pointer in some form. However, we do not want to pessimize
9265 the usual case in which all branches are short.
9267 We handle this as follows:
9269 (1) During reload, we set cfun->machine->global_pointer to
9270 INVALID_REGNUM if we _know_ that the current function
9271 doesn't need a global pointer. This is only valid if
9272 long branches don't need the GOT.
9274 Otherwise, we assume that we might need a global pointer
9275 and pick an appropriate register.
9277 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9278 we ensure that the global pointer is available at every
9279 block boundary bar entry and exit. We do this in one of two ways:
9281 - If the function has a cprestore slot, we ensure that this
9282 slot is valid at every branch. However, as explained in
9283 point (6) below, there is no guarantee that pic_offset_table_rtx
9284 itself is valid if new uses of the global pointer are introduced
9285 after the first post-epilogue split.
9287 We guarantee that the cprestore slot is valid by loading it
9288 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9289 this register live at every block boundary bar function entry
9290 and exit. It is then invalid to move the load (and thus the
9291 preceding store) across a block boundary.
9293 - If the function has no cprestore slot, we guarantee that
9294 pic_offset_table_rtx itself is valid at every branch.
9296 See mips_eh_uses for the handling of the register liveness.
9298 (3) During prologue and epilogue generation, we emit "ghost"
9299 placeholder instructions to manipulate the global pointer.
9301 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9302 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9303 that the function needs a global pointer. (There is no need to set
9304 them earlier than this, and doing it as late as possible leads to
9305 fewer false positives.)
9307 (5) If cfun->machine->must_initialize_gp_p is true during a
9308 split_insns pass, we split the ghost instructions into real
9309 instructions. These split instructions can then be optimized in
9310 the usual way. Otherwise, we keep the ghost instructions intact,
9311 and optimize for the case where they aren't needed. We still
9312 have the option of splitting them later, if we need to introduce
9313 new uses of the global pointer.
9315 For example, the scheduler ignores a ghost instruction that
9316 stores $28 to the stack, but it handles the split form of
9317 the ghost instruction as an ordinary store.
9319 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9320 is true during the first post-epilogue split_insns pass, we split
9321 calls and restore_gp patterns into instructions that explicitly
9322 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9323 we split these patterns into instructions that _don't_ load from
9326 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9327 time of the split, then any instructions that exist at that time
9328 can make free use of pic_offset_table_rtx. However, if we want
9329 to introduce new uses of the global pointer after the split,
9330 we must explicitly load the value from the cprestore slot, since
9331 pic_offset_table_rtx itself might not be valid at a given point
9334 The idea is that we want to be able to delete redundant
9335 loads from the cprestore slot in the usual case where no
9336 long branches are needed.
9338 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9339 of md_reorg, we decide whether the global pointer is needed for
9340 long branches. If so, we set cfun->machine->must_initialize_gp_p
9341 to true and split the ghost instructions into real instructions
9344 Note that the ghost instructions must have a zero length for three reasons:
9346 - Giving the length of the underlying $gp sequence might cause
9347 us to use long branches in cases where they aren't really needed.
9349 - They would perturb things like alignment calculations.
9351 - More importantly, the hazard detection in md_reorg relies on
9352 empty instructions having a zero length.
9354 If we find a long branch and split the ghost instructions at the
9355 end of md_reorg, the split could introduce more long branches.
9356 That isn't a problem though, because we still do the split before
9357 the final shorten_branches pass.
9359 This is extremely ugly, but it seems like the best compromise between
9360 correctness and efficiency. */
9363 mips_must_initialize_gp_p (void)
9365 return cfun
->machine
->must_initialize_gp_p
;
9368 /* Return true if REGNO is a register that is ordinarily call-clobbered
9369 but must nevertheless be preserved by an interrupt handler. */
9372 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9374 if (MD_REG_P (regno
))
9377 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9380 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9382 /* $0 is hard-wired. */
9383 if (regno
== GP_REG_FIRST
)
9386 /* The interrupt handler can treat kernel registers as
9387 scratch registers. */
9388 if (KERNEL_REG_P (regno
))
9391 /* The function will return the stack pointer to its original value
9393 if (regno
== STACK_POINTER_REGNUM
)
9396 /* Otherwise, return true for registers that aren't ordinarily
9398 return call_really_used_regs
[regno
];
9404 /* Return true if the current function should treat register REGNO
9408 mips_cfun_call_saved_reg_p (unsigned int regno
)
9410 /* If the user makes an ordinarily-call-saved register global,
9411 that register is no longer call-saved. */
9412 if (global_regs
[regno
])
9415 /* Interrupt handlers need to save extra registers. */
9416 if (cfun
->machine
->interrupt_handler_p
9417 && mips_interrupt_extra_call_saved_reg_p (regno
))
9420 /* call_insns preserve $28 unless they explicitly say otherwise,
9421 so call_really_used_regs[] treats $28 as call-saved. However,
9422 we want the ABI property rather than the default call_insn
9424 return (regno
== GLOBAL_POINTER_REGNUM
9425 ? TARGET_CALL_SAVED_GP
9426 : !call_really_used_regs
[regno
]);
9429 /* Return true if the function body might clobber register REGNO.
9430 We know that REGNO is call-saved. */
9433 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9435 /* Some functions should be treated as clobbering all call-saved
9437 if (crtl
->saves_all_registers
)
9440 /* DF handles cases where a register is explicitly referenced in
9441 the rtl. Incoming values are passed in call-clobbered registers,
9442 so we can assume that any live call-saved register is set within
9444 if (df_regs_ever_live_p (regno
))
9447 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9448 These clobbers are not explicit in the rtl. */
9449 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9452 /* If we're using a call-saved global pointer, the function's
9453 prologue will need to set it up. */
9454 if (cfun
->machine
->global_pointer
== regno
)
9457 /* The function's prologue will need to set the frame pointer if
9458 frame_pointer_needed. */
9459 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9462 /* If a MIPS16 function returns a value in FPRs, its epilogue
9463 will need to call an external libgcc routine. This yet-to-be
9464 generated call_insn will clobber $31. */
9465 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9468 /* If REGNO is ordinarily call-clobbered, we must assume that any
9469 called function could modify it. */
9470 if (cfun
->machine
->interrupt_handler_p
9472 && mips_interrupt_extra_call_saved_reg_p (regno
))
9478 /* Return true if the current function must save register REGNO. */
9481 mips_save_reg_p (unsigned int regno
)
9483 if (mips_cfun_call_saved_reg_p (regno
))
9485 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9488 /* Save both registers in an FPR pair if either one is used. This is
9489 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9490 register to be used without the even register. */
9491 if (FP_REG_P (regno
)
9492 && MAX_FPRS_PER_FMT
== 2
9493 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9497 /* We need to save the incoming return address if __builtin_eh_return
9498 is being used to set a different return address. */
9499 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9505 /* Populate the current function's mips_frame_info structure.
9507 MIPS stack frames look like:
9509 +-------------------------------+
9511 | incoming stack arguments |
9513 +-------------------------------+
9515 | caller-allocated save area |
9516 A | for register arguments |
9518 +-------------------------------+ <-- incoming stack pointer
9520 | callee-allocated save area |
9521 B | for arguments that are |
9522 | split between registers and |
9525 +-------------------------------+ <-- arg_pointer_rtx
9527 C | callee-allocated save area |
9528 | for register varargs |
9530 +-------------------------------+ <-- frame_pointer_rtx
9531 | | + cop0_sp_offset
9532 | COP0 reg save area | + UNITS_PER_WORD
9534 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9535 | | + UNITS_PER_WORD
9536 | accumulator save area |
9538 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9539 | | + UNITS_PER_HWFPVALUE
9542 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9543 | | + UNITS_PER_WORD
9546 +-------------------------------+ <-- frame_pointer_rtx with
9547 | | \ -fstack-protector
9548 | local variables | | var_size
9550 +-------------------------------+
9552 | $gp save area | | cprestore_size
9554 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9556 | outgoing stack arguments | |
9558 +-------------------------------+ | args_size
9560 | caller-allocated save area | |
9561 | for register arguments | |
9563 +-------------------------------+ <-- stack_pointer_rtx
9564 frame_pointer_rtx without
9566 hard_frame_pointer_rtx for
9569 At least two of A, B and C will be empty.
9571 Dynamic stack allocations such as alloca insert data at point P.
9572 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9573 hard_frame_pointer_rtx unchanged. */
9576 mips_compute_frame_info (void)
9578 struct mips_frame_info
*frame
;
9579 HOST_WIDE_INT offset
, size
;
9580 unsigned int regno
, i
;
9582 /* Set this function's interrupt properties. */
9583 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9586 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9587 else if (TARGET_HARD_FLOAT
)
9588 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9589 else if (TARGET_MIPS16
)
9590 error ("interrupt handlers cannot be MIPS16 functions");
9593 cfun
->machine
->interrupt_handler_p
= true;
9594 cfun
->machine
->use_shadow_register_set_p
=
9595 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9596 cfun
->machine
->keep_interrupts_masked_p
=
9597 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9598 cfun
->machine
->use_debug_exception_return_p
=
9599 mips_use_debug_exception_return_p (TREE_TYPE
9600 (current_function_decl
));
9604 frame
= &cfun
->machine
->frame
;
9605 memset (frame
, 0, sizeof (*frame
));
9606 size
= get_frame_size ();
9608 cfun
->machine
->global_pointer
= mips_global_pointer ();
9610 /* The first two blocks contain the outgoing argument area and the $gp save
9611 slot. This area isn't needed in leaf functions, but if the
9612 target-independent frame size is nonzero, we have already committed to
9613 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9614 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9616 /* The MIPS 3.0 linker does not like functions that dynamically
9617 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9618 looks like we are trying to create a second frame pointer to the
9619 function, so allocate some stack space to make it happy. */
9620 if (cfun
->calls_alloca
)
9621 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9623 frame
->args_size
= 0;
9624 frame
->cprestore_size
= 0;
9628 frame
->args_size
= crtl
->outgoing_args_size
;
9629 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9631 offset
= frame
->args_size
+ frame
->cprestore_size
;
9633 /* Move above the local variables. */
9634 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9635 offset
+= frame
->var_size
;
9637 /* Find out which GPRs we need to save. */
9638 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9639 if (mips_save_reg_p (regno
))
9642 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9645 /* If this function calls eh_return, we must also save and restore the
9646 EH data registers. */
9647 if (crtl
->calls_eh_return
)
9648 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9651 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9654 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9655 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9656 save all later registers too. */
9657 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9659 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9660 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9661 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9662 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9665 /* Move above the GPR save area. */
9666 if (frame
->num_gp
> 0)
9668 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9669 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9672 /* Find out which FPRs we need to save. This loop must iterate over
9673 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9674 if (TARGET_HARD_FLOAT
)
9675 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9676 if (mips_save_reg_p (regno
))
9678 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9679 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9682 /* Move above the FPR save area. */
9683 if (frame
->num_fp
> 0)
9685 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9686 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9689 /* Add in space for the interrupt context information. */
9690 if (cfun
->machine
->interrupt_handler_p
)
9693 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9696 frame
->acc_mask
|= (1 << 0);
9699 /* Check accumulators 1, 2, 3. */
9700 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9701 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
9704 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
9707 /* All interrupt context functions need space to preserve STATUS. */
9708 frame
->num_cop0_regs
++;
9710 /* If we don't keep interrupts masked, we need to save EPC. */
9711 if (!cfun
->machine
->keep_interrupts_masked_p
)
9712 frame
->num_cop0_regs
++;
9715 /* Move above the accumulator save area. */
9716 if (frame
->num_acc
> 0)
9718 /* Each accumulator needs 2 words. */
9719 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
9720 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
9723 /* Move above the COP0 register save area. */
9724 if (frame
->num_cop0_regs
> 0)
9726 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
9727 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
9730 /* Move above the callee-allocated varargs save area. */
9731 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
9732 frame
->arg_pointer_offset
= offset
;
9734 /* Move above the callee-allocated area for pretend stack arguments. */
9735 offset
+= crtl
->args
.pretend_args_size
;
9736 frame
->total_size
= offset
;
9738 /* Work out the offsets of the save areas from the top of the frame. */
9739 if (frame
->gp_sp_offset
> 0)
9740 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
9741 if (frame
->fp_sp_offset
> 0)
9742 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
9743 if (frame
->acc_sp_offset
> 0)
9744 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
9745 if (frame
->num_cop0_regs
> 0)
9746 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
9748 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9749 arguments. This tends to increase the chances of using unextended
9750 instructions for local variables and incoming arguments. */
9752 frame
->hard_frame_pointer_offset
= frame
->args_size
;
9755 /* Return the style of GP load sequence that is being used for the
9756 current function. */
9758 enum mips_loadgp_style
9759 mips_current_loadgp_style (void)
9761 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
9767 if (TARGET_ABSOLUTE_ABICALLS
)
9768 return LOADGP_ABSOLUTE
;
9770 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
9773 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9776 mips_frame_pointer_required (void)
9778 /* If the function contains dynamic stack allocations, we need to
9779 use the frame pointer to access the static parts of the frame. */
9780 if (cfun
->calls_alloca
)
9783 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9784 reload may be unable to compute the address of a local variable,
9785 since there is no way to add a large constant to the stack pointer
9786 without using a second temporary register. */
9789 mips_compute_frame_info ();
9790 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
9797 /* Make sure that we're not trying to eliminate to the wrong hard frame
9801 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
9803 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
9806 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9807 or argument pointer. TO is either the stack pointer or hard frame
9811 mips_initial_elimination_offset (int from
, int to
)
9813 HOST_WIDE_INT offset
;
9815 mips_compute_frame_info ();
9817 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9820 case FRAME_POINTER_REGNUM
:
9821 if (FRAME_GROWS_DOWNWARD
)
9822 offset
= (cfun
->machine
->frame
.args_size
9823 + cfun
->machine
->frame
.cprestore_size
9824 + cfun
->machine
->frame
.var_size
);
9829 case ARG_POINTER_REGNUM
:
9830 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
9837 if (to
== HARD_FRAME_POINTER_REGNUM
)
9838 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9843 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9846 mips_extra_live_on_entry (bitmap regs
)
9850 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9851 the global pointer. */
9852 if (!TARGET_ABSOLUTE_ABICALLS
)
9853 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
9855 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9856 the global pointer. */
9858 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
9860 /* See the comment above load_call<mode> for details. */
9861 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
9865 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9869 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
9874 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
9877 /* Emit code to change the current function's return address to
9878 ADDRESS. SCRATCH is available as a scratch register, if needed.
9879 ADDRESS and SCRATCH are both word-mode GPRs. */
9882 mips_set_return_address (rtx address
, rtx scratch
)
9886 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
9887 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
9888 cfun
->machine
->frame
.gp_sp_offset
);
9889 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
9892 /* Return true if the current function has a cprestore slot. */
9895 mips_cfun_has_cprestore_slot_p (void)
9897 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
9898 && cfun
->machine
->frame
.cprestore_size
> 0);
9901 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9902 cprestore slot. LOAD_P is true if the caller wants to load from
9903 the cprestore slot; it is false if the caller wants to store to
9907 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
9910 const struct mips_frame_info
*frame
;
9912 frame
= &cfun
->machine
->frame
;
9913 /* .cprestore always uses the stack pointer instead of the frame pointer.
9914 We have a free choice for direct stores for non-MIPS16 functions,
9915 and for MIPS16 functions whose cprestore slot is in range of the
9916 stack pointer. Using the stack pointer would sometimes give more
9917 (early) scheduling freedom, but using the frame pointer would
9918 sometimes give more (late) scheduling freedom. It's hard to
9919 predict which applies to a given function, so let's keep things
9922 Loads must always use the frame pointer in functions that call
9923 alloca, and there's little benefit to using the stack pointer
9925 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
9927 *base
= hard_frame_pointer_rtx
;
9928 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
9932 *base
= stack_pointer_rtx
;
9933 *offset
= frame
->args_size
;
9937 /* Return true if X is the load or store address of the cprestore slot;
9938 LOAD_P says which. */
9941 mips_cprestore_address_p (rtx x
, bool load_p
)
9943 rtx given_base
, required_base
;
9944 HOST_WIDE_INT given_offset
, required_offset
;
9946 mips_split_plus (x
, &given_base
, &given_offset
);
9947 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
9948 return given_base
== required_base
&& given_offset
== required_offset
;
9951 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9952 going to load from it, false if we are going to store to it.
9953 Use TEMP as a temporary register if need be. */
9956 mips_cprestore_slot (rtx temp
, bool load_p
)
9959 HOST_WIDE_INT offset
;
9961 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
9962 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
9965 /* Emit instructions to save global pointer value GP into cprestore
9966 slot MEM. OFFSET is the offset that MEM applies to the base register.
9968 MEM may not be a legitimate address. If it isn't, TEMP is a
9969 temporary register that can be used, otherwise it is a SCRATCH. */
9972 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
9974 if (TARGET_CPRESTORE_DIRECTIVE
)
9976 gcc_assert (gp
== pic_offset_table_rtx
);
9977 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
9980 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
9983 /* Restore $gp from its save slot, using TEMP as a temporary base register
9984 if need be. This function is for o32 and o64 abicalls only.
9986 See mips_must_initialize_gp_p for details about how we manage the
9990 mips_restore_gp_from_cprestore_slot (rtx temp
)
9992 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
9994 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
9996 emit_note (NOTE_INSN_DELETED
);
10002 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10003 mips_emit_move (pic_offset_table_rtx
, temp
);
10006 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10007 if (!TARGET_EXPLICIT_RELOCS
)
10008 emit_insn (gen_blockage ());
10011 /* A function to save or store a register. The first argument is the
10012 register and the second is the stack slot. */
10013 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10015 /* Use FN to save or restore register REGNO. MODE is the register's
10016 mode and OFFSET is the offset of its save slot from the current
10020 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10021 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10025 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10027 fn (gen_rtx_REG (mode
, regno
), mem
);
10030 /* Call FN for each accumlator that is saved by the current function.
10031 SP_OFFSET is the offset of the current stack pointer from the start
10035 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10037 HOST_WIDE_INT offset
;
10040 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10041 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10043 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10044 offset
-= UNITS_PER_WORD
;
10045 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10046 offset
-= UNITS_PER_WORD
;
10049 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10050 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10051 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10053 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10054 offset
-= UNITS_PER_WORD
;
10058 /* Call FN for each register that is saved by the current function.
10059 SP_OFFSET is the offset of the current stack pointer from the start
10063 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10064 mips_save_restore_fn fn
)
10066 enum machine_mode fpr_mode
;
10067 HOST_WIDE_INT offset
;
10070 /* Save registers starting from high to low. The debuggers prefer at least
10071 the return register be stored at func+4, and also it allows us not to
10072 need a nop in the epilogue if at least one register is reloaded in
10073 addition to return address. */
10074 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
10075 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10076 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
10078 /* Record the ra offset for use by mips_function_profiler. */
10079 if (regno
== RETURN_ADDR_REGNUM
)
10080 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10081 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10082 offset
-= UNITS_PER_WORD
;
10085 /* This loop must iterate over the same space as its companion in
10086 mips_compute_frame_info. */
10087 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10088 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10089 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10090 regno
>= FP_REG_FIRST
;
10091 regno
-= MAX_FPRS_PER_FMT
)
10092 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10094 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10095 offset
-= GET_MODE_SIZE (fpr_mode
);
10099 /* Return true if a move between register REGNO and its save slot (MEM)
10100 can be done in a single move. LOAD_P is true if we are loading
10101 from the slot, false if we are storing to it. */
10104 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10106 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10107 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10110 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10111 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10114 /* Emit a move from SRC to DEST, given that one of them is a register
10115 save slot and that the other is a register. TEMP is a temporary
10116 GPR of the same mode that is available if need be. */
10119 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10121 unsigned int regno
;
10126 regno
= REGNO (src
);
10131 regno
= REGNO (dest
);
10135 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10137 /* We don't yet know whether we'll need this instruction or not.
10138 Postpone the decision by emitting a ghost move. This move
10139 is specifically not frame-related; only the split version is. */
10141 emit_insn (gen_move_gpdi (dest
, src
));
10143 emit_insn (gen_move_gpsi (dest
, src
));
10147 if (regno
== HI_REGNUM
)
10151 mips_emit_move (temp
, src
);
10153 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10154 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10156 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10157 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10162 emit_insn (gen_mfhidi_ti (temp
,
10163 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10165 emit_insn (gen_mfhisi_di (temp
,
10166 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10167 mips_emit_move (dest
, temp
);
10170 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10171 mips_emit_move (dest
, src
);
10174 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10175 mips_emit_move (temp
, src
);
10176 mips_emit_move (dest
, temp
);
10179 mips_set_frame_expr (mips_frame_set (dest
, src
));
10182 /* If we're generating n32 or n64 abicalls, and the current function
10183 does not use $28 as its global pointer, emit a cplocal directive.
10184 Use pic_offset_table_rtx as the argument to the directive. */
10187 mips_output_cplocal (void)
10189 if (!TARGET_EXPLICIT_RELOCS
10190 && mips_must_initialize_gp_p ()
10191 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10192 output_asm_insn (".cplocal %+", 0);
10195 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10198 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10200 const char *fnname
;
10202 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10203 floating-point arguments. */
10205 && TARGET_HARD_FLOAT_ABI
10206 && crtl
->args
.info
.fp_code
!= 0)
10207 mips16_build_function_stub ();
10209 /* Get the function name the same way that toplev.c does before calling
10210 assemble_start_function. This is needed so that the name used here
10211 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10212 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10213 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10215 /* Output MIPS-specific frame information. */
10216 if (!flag_inhibit_size_directive
)
10218 const struct mips_frame_info
*frame
;
10220 frame
= &cfun
->machine
->frame
;
10222 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10224 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10225 "# vars= " HOST_WIDE_INT_PRINT_DEC
10227 ", args= " HOST_WIDE_INT_PRINT_DEC
10228 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10229 reg_names
[frame_pointer_needed
10230 ? HARD_FRAME_POINTER_REGNUM
10231 : STACK_POINTER_REGNUM
],
10232 (frame_pointer_needed
10233 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10234 : frame
->total_size
),
10235 reg_names
[RETURN_ADDR_REGNUM
],
10237 frame
->num_gp
, frame
->num_fp
,
10239 frame
->cprestore_size
);
10241 /* .mask MASK, OFFSET. */
10242 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10243 frame
->mask
, frame
->gp_save_offset
);
10245 /* .fmask MASK, OFFSET. */
10246 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10247 frame
->fmask
, frame
->fp_save_offset
);
10250 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10251 Also emit the ".set noreorder; .set nomacro" sequence for functions
10253 if (mips_must_initialize_gp_p ()
10254 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10258 /* This is a fixed-form sequence. The position of the
10259 first two instructions is important because of the
10260 way _gp_disp is defined. */
10261 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10262 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10263 output_asm_insn ("sll\t$2,16", 0);
10264 output_asm_insn ("addu\t$2,$3", 0);
10268 /* .cpload must be in a .set noreorder but not a
10269 .set nomacro block. */
10270 mips_push_asm_switch (&mips_noreorder
);
10271 output_asm_insn (".cpload\t%^", 0);
10272 if (!cfun
->machine
->all_noreorder_p
)
10273 mips_pop_asm_switch (&mips_noreorder
);
10275 mips_push_asm_switch (&mips_nomacro
);
10278 else if (cfun
->machine
->all_noreorder_p
)
10280 mips_push_asm_switch (&mips_noreorder
);
10281 mips_push_asm_switch (&mips_nomacro
);
10284 /* Tell the assembler which register we're using as the global
10285 pointer. This is needed for thunks, since they can use either
10286 explicit relocs or assembler macros. */
10287 mips_output_cplocal ();
10290 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10293 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10294 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10296 const char *fnname
;
10298 /* Reinstate the normal $gp. */
10299 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10300 mips_output_cplocal ();
10302 if (cfun
->machine
->all_noreorder_p
)
10304 mips_pop_asm_switch (&mips_nomacro
);
10305 mips_pop_asm_switch (&mips_noreorder
);
10308 /* Get the function name the same way that toplev.c does before calling
10309 assemble_start_function. This is needed so that the name used here
10310 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10311 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10312 mips_end_function_definition (fnname
);
10315 /* Emit an optimisation barrier for accesses to the current frame. */
10318 mips_frame_barrier (void)
10320 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10323 /* Save register REG to MEM. Make the instruction frame-related. */
10326 mips_save_reg (rtx reg
, rtx mem
)
10328 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10332 if (mips_split_64bit_move_p (mem
, reg
))
10333 mips_split_doubleword_move (mem
, reg
);
10335 mips_emit_move (mem
, reg
);
10337 x1
= mips_frame_set (mips_subword (mem
, false),
10338 mips_subword (reg
, false));
10339 x2
= mips_frame_set (mips_subword (mem
, true),
10340 mips_subword (reg
, true));
10341 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10344 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10347 /* The __gnu_local_gp symbol. */
10349 static GTY(()) rtx mips_gnu_local_gp
;
10351 /* If we're generating n32 or n64 abicalls, emit instructions
10352 to set up the global pointer. */
10355 mips_emit_loadgp (void)
10357 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10359 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10360 switch (mips_current_loadgp_style ())
10362 case LOADGP_ABSOLUTE
:
10363 if (mips_gnu_local_gp
== NULL
)
10365 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10366 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10368 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10369 (pic_reg
, mips_gnu_local_gp
)));
10372 case LOADGP_OLDABI
:
10373 /* Added by mips_output_function_prologue. */
10376 case LOADGP_NEWABI
:
10377 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10378 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10379 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10380 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10381 (pic_reg
, offset
, incoming_address
)));
10385 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10386 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10387 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10395 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10396 (pic_offset_table_rtx
, pic_reg
)));
10398 /* Emit a blockage if there are implicit uses of the GP register.
10399 This includes profiled functions, because FUNCTION_PROFILE uses
10401 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10402 emit_insn (gen_loadgp_blockage ());
10405 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10408 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10410 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10413 /* Expand the "prologue" pattern. */
10416 mips_expand_prologue (void)
10418 const struct mips_frame_info
*frame
;
10419 HOST_WIDE_INT size
;
10420 unsigned int nargs
;
10423 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10425 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10426 or implicitly. If so, we can commit to using a global pointer
10427 straight away, otherwise we need to defer the decision. */
10428 if (mips_cfun_has_inflexible_gp_ref_p ()
10429 || mips_cfun_has_flexible_gp_ref_p ())
10431 cfun
->machine
->must_initialize_gp_p
= true;
10432 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10435 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10438 frame
= &cfun
->machine
->frame
;
10439 size
= frame
->total_size
;
10441 if (flag_stack_usage_info
)
10442 current_function_static_stack_size
= size
;
10444 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10445 bytes beforehand; this is enough to cover the register save area
10446 without going out of range. */
10447 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10448 || frame
->num_cop0_regs
> 0)
10450 HOST_WIDE_INT step1
;
10452 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10453 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10455 HOST_WIDE_INT offset
;
10456 unsigned int mask
, regno
;
10458 /* Try to merge argument stores into the save instruction. */
10459 nargs
= mips16e_collect_argument_saves ();
10461 /* Build the save instruction. */
10462 mask
= frame
->mask
;
10463 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
10465 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10466 mips_frame_barrier ();
10469 /* Check if we need to save other registers. */
10470 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10471 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10473 offset
-= UNITS_PER_WORD
;
10474 mips_save_restore_reg (word_mode
, regno
,
10475 offset
, mips_save_reg
);
10480 if (cfun
->machine
->interrupt_handler_p
)
10482 HOST_WIDE_INT offset
;
10485 /* If this interrupt is using a shadow register set, we need to
10486 get the stack pointer from the previous register set. */
10487 if (cfun
->machine
->use_shadow_register_set_p
)
10488 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
10489 stack_pointer_rtx
));
10491 if (!cfun
->machine
->keep_interrupts_masked_p
)
10493 /* Move from COP0 Cause to K0. */
10494 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
10495 gen_rtx_REG (SImode
,
10496 COP0_CAUSE_REG_NUM
)));
10497 /* Move from COP0 EPC to K1. */
10498 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10499 gen_rtx_REG (SImode
,
10500 COP0_EPC_REG_NUM
)));
10503 /* Allocate the first part of the frame. */
10504 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
10506 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10507 mips_frame_barrier ();
10510 /* Start at the uppermost location for saving. */
10511 offset
= frame
->cop0_sp_offset
- size
;
10512 if (!cfun
->machine
->keep_interrupts_masked_p
)
10514 /* Push EPC into its stack slot. */
10515 mem
= gen_frame_mem (word_mode
,
10516 plus_constant (Pmode
, stack_pointer_rtx
,
10518 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10519 offset
-= UNITS_PER_WORD
;
10522 /* Move from COP0 Status to K1. */
10523 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10524 gen_rtx_REG (SImode
,
10525 COP0_STATUS_REG_NUM
)));
10527 /* Right justify the RIPL in k0. */
10528 if (!cfun
->machine
->keep_interrupts_masked_p
)
10529 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
10530 gen_rtx_REG (SImode
, K0_REG_NUM
),
10531 GEN_INT (CAUSE_IPL
)));
10533 /* Push Status into its stack slot. */
10534 mem
= gen_frame_mem (word_mode
,
10535 plus_constant (Pmode
, stack_pointer_rtx
,
10537 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10538 offset
-= UNITS_PER_WORD
;
10540 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10541 if (!cfun
->machine
->keep_interrupts_masked_p
)
10542 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10545 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10547 if (!cfun
->machine
->keep_interrupts_masked_p
)
10548 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10549 IE is already the correct value, so we don't have to do
10550 anything explicit. */
10551 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10554 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10556 /* Disable interrupts by clearing the KSU, ERL, EXL,
10558 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10561 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10565 insn
= gen_add3_insn (stack_pointer_rtx
,
10568 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10569 mips_frame_barrier ();
10572 mips_for_each_saved_acc (size
, mips_save_reg
);
10573 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
10577 /* Allocate the rest of the frame. */
10580 if (SMALL_OPERAND (-size
))
10581 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
10583 GEN_INT (-size
)))) = 1;
10586 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
10589 /* There are no instructions to add or subtract registers
10590 from the stack pointer, so use the frame pointer as a
10591 temporary. We should always be using a frame pointer
10592 in this case anyway. */
10593 gcc_assert (frame_pointer_needed
);
10594 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10595 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
10596 hard_frame_pointer_rtx
,
10597 MIPS_PROLOGUE_TEMP (Pmode
)));
10598 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
10601 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
10603 MIPS_PROLOGUE_TEMP (Pmode
)));
10605 /* Describe the combined effect of the previous instructions. */
10606 mips_set_frame_expr
10607 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10608 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
10610 mips_frame_barrier ();
10613 /* Set up the frame pointer, if we're using one. */
10614 if (frame_pointer_needed
)
10616 HOST_WIDE_INT offset
;
10618 offset
= frame
->hard_frame_pointer_offset
;
10621 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10622 RTX_FRAME_RELATED_P (insn
) = 1;
10624 else if (SMALL_OPERAND (offset
))
10626 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
10627 stack_pointer_rtx
, GEN_INT (offset
));
10628 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10632 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
10633 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10634 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
10635 hard_frame_pointer_rtx
,
10636 MIPS_PROLOGUE_TEMP (Pmode
)));
10637 mips_set_frame_expr
10638 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
10639 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
10643 mips_emit_loadgp ();
10645 /* Initialize the $gp save slot. */
10646 if (mips_cfun_has_cprestore_slot_p ())
10648 rtx base
, mem
, gp
, temp
;
10649 HOST_WIDE_INT offset
;
10651 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
10652 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
10653 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10654 temp
= (SMALL_OPERAND (offset
)
10655 ? gen_rtx_SCRATCH (Pmode
)
10656 : MIPS_PROLOGUE_TEMP (Pmode
));
10657 emit_insn (PMODE_INSN (gen_potential_cprestore
,
10658 (mem
, GEN_INT (offset
), gp
, temp
)));
10660 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
10661 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
10662 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
10665 /* We need to search back to the last use of K0 or K1. */
10666 if (cfun
->machine
->interrupt_handler_p
)
10668 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
10670 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
10672 /* Emit a move from K1 to COP0 Status after insn. */
10673 gcc_assert (insn
!= NULL_RTX
);
10674 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10675 gen_rtx_REG (SImode
, K1_REG_NUM
)),
10679 /* If we are profiling, make sure no instructions are scheduled before
10680 the call to mcount. */
10682 emit_insn (gen_blockage ());
10685 /* Attach all pending register saves to the previous instruction.
10686 Return that instruction. */
10689 mips_epilogue_emit_cfa_restores (void)
10693 insn
= get_last_insn ();
10694 gcc_assert (insn
&& !REG_NOTES (insn
));
10695 if (mips_epilogue
.cfa_restores
)
10697 RTX_FRAME_RELATED_P (insn
) = 1;
10698 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
10699 mips_epilogue
.cfa_restores
= 0;
10704 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10705 now at REG + OFFSET. */
10708 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
10712 insn
= mips_epilogue_emit_cfa_restores ();
10713 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
10715 RTX_FRAME_RELATED_P (insn
) = 1;
10716 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
10717 plus_constant (Pmode
, reg
, offset
),
10719 mips_epilogue
.cfa_reg
= reg
;
10720 mips_epilogue
.cfa_offset
= offset
;
10724 /* Emit instructions to restore register REG from slot MEM. Also update
10725 the cfa_restores list. */
10728 mips_restore_reg (rtx reg
, rtx mem
)
10730 /* There's no MIPS16 instruction to load $31 directly. Load into
10731 $7 instead and adjust the return insn appropriately. */
10732 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
10733 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
10734 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10736 mips_add_cfa_restore (mips_subword (reg
, true));
10737 mips_add_cfa_restore (mips_subword (reg
, false));
10740 mips_add_cfa_restore (reg
);
10742 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
10743 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
10744 /* The CFA is currently defined in terms of the register whose
10745 value we have just restored. Redefine the CFA in terms of
10746 the stack pointer. */
10747 mips_epilogue_set_cfa (stack_pointer_rtx
,
10748 mips_epilogue
.cfa_restore_sp_offset
);
10751 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10752 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10753 BASE, if not the stack pointer, is available as a temporary. */
10756 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
10758 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
10761 mips_frame_barrier ();
10762 if (offset
== const0_rtx
)
10764 emit_move_insn (stack_pointer_rtx
, base
);
10765 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
10767 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
10769 emit_insn (gen_add3_insn (base
, base
, offset
));
10770 mips_epilogue_set_cfa (base
, new_frame_size
);
10771 emit_move_insn (stack_pointer_rtx
, base
);
10775 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
10776 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
10780 /* Emit any instructions needed before a return. */
10783 mips_expand_before_return (void)
10785 /* When using a call-clobbered gp, we start out with unified call
10786 insns that include instructions to restore the gp. We then split
10787 these unified calls after reload. These split calls explicitly
10788 clobber gp, so there is no need to define
10789 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10791 For consistency, we should also insert an explicit clobber of $28
10792 before return insns, so that the post-reload optimizers know that
10793 the register is not live on exit. */
10794 if (TARGET_CALL_CLOBBERED_GP
)
10795 emit_clobber (pic_offset_table_rtx
);
10798 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10802 mips_expand_epilogue (bool sibcall_p
)
10804 const struct mips_frame_info
*frame
;
10805 HOST_WIDE_INT step1
, step2
;
10806 rtx base
, adjust
, insn
;
10808 if (!sibcall_p
&& mips_can_use_return_insn ())
10810 emit_jump_insn (gen_return ());
10814 /* In MIPS16 mode, if the return value should go into a floating-point
10815 register, we need to call a helper routine to copy it over. */
10816 if (mips16_cfun_returns_in_fpr_p ())
10817 mips16_copy_fpr_return_value ();
10819 /* Split the frame into two. STEP1 is the amount of stack we should
10820 deallocate before restoring the registers. STEP2 is the amount we
10821 should deallocate afterwards.
10823 Start off by assuming that no registers need to be restored. */
10824 frame
= &cfun
->machine
->frame
;
10825 step1
= frame
->total_size
;
10828 /* Work out which register holds the frame address. */
10829 if (!frame_pointer_needed
)
10830 base
= stack_pointer_rtx
;
10833 base
= hard_frame_pointer_rtx
;
10834 step1
-= frame
->hard_frame_pointer_offset
;
10836 mips_epilogue
.cfa_reg
= base
;
10837 mips_epilogue
.cfa_offset
= step1
;
10838 mips_epilogue
.cfa_restores
= NULL_RTX
;
10840 /* If we need to restore registers, deallocate as much stack as
10841 possible in the second step without going out of range. */
10842 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
10843 || frame
->num_cop0_regs
> 0)
10845 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
10849 /* Get an rtx for STEP1 that we can add to BASE. */
10850 adjust
= GEN_INT (step1
);
10851 if (!SMALL_OPERAND (step1
))
10853 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
10854 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
10856 mips_deallocate_stack (base
, adjust
, step2
);
10858 /* If we're using addressing macros, $gp is implicitly used by all
10859 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10861 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
10862 emit_insn (gen_blockage ());
10864 mips_epilogue
.cfa_restore_sp_offset
= step2
;
10865 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
10867 unsigned int regno
, mask
;
10868 HOST_WIDE_INT offset
;
10871 /* Generate the restore instruction. */
10872 mask
= frame
->mask
;
10873 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
10875 /* Restore any other registers manually. */
10876 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10877 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10879 offset
-= UNITS_PER_WORD
;
10880 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
10883 /* Restore the remaining registers and deallocate the final bit
10885 mips_frame_barrier ();
10886 emit_insn (restore
);
10887 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
10891 /* Restore the registers. */
10892 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
10893 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
10896 if (cfun
->machine
->interrupt_handler_p
)
10898 HOST_WIDE_INT offset
;
10901 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
10902 if (!cfun
->machine
->keep_interrupts_masked_p
)
10904 /* Restore the original EPC. */
10905 mem
= gen_frame_mem (word_mode
,
10906 plus_constant (Pmode
, stack_pointer_rtx
,
10908 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10909 offset
-= UNITS_PER_WORD
;
10911 /* Move to COP0 EPC. */
10912 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
10913 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10916 /* Restore the original Status. */
10917 mem
= gen_frame_mem (word_mode
,
10918 plus_constant (Pmode
, stack_pointer_rtx
,
10920 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10921 offset
-= UNITS_PER_WORD
;
10923 /* If we don't use shoadow register set, we need to update SP. */
10924 if (!cfun
->machine
->use_shadow_register_set_p
)
10925 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
10927 /* The choice of position is somewhat arbitrary in this case. */
10928 mips_epilogue_emit_cfa_restores ();
10930 /* Move to COP0 Status. */
10931 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10932 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10935 /* Deallocate the final bit of the frame. */
10936 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
10938 gcc_assert (!mips_epilogue
.cfa_restores
);
10940 /* Add in the __builtin_eh_return stack adjustment. We need to
10941 use a temporary in MIPS16 code. */
10942 if (crtl
->calls_eh_return
)
10946 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
10947 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
10948 MIPS_EPILOGUE_TEMP (Pmode
),
10949 EH_RETURN_STACKADJ_RTX
));
10950 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
10953 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10955 EH_RETURN_STACKADJ_RTX
));
10960 mips_expand_before_return ();
10961 if (cfun
->machine
->interrupt_handler_p
)
10963 /* Interrupt handlers generate eret or deret. */
10964 if (cfun
->machine
->use_debug_exception_return_p
)
10965 emit_jump_insn (gen_mips_deret ());
10967 emit_jump_insn (gen_mips_eret ());
10973 /* When generating MIPS16 code, the normal
10974 mips_for_each_saved_gpr_and_fpr path will restore the return
10975 address into $7 rather than $31. */
10977 && !GENERATE_MIPS16E_SAVE_RESTORE
10978 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
10980 /* simple_returns cannot rely on values that are only available
10981 on paths through the epilogue (because return paths that do
10982 not pass through the epilogue may nevertheless reuse a
10983 simple_return that occurs at the end of the epilogue).
10984 Use a normal return here instead. */
10985 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
10986 pat
= gen_return_internal (reg
);
10990 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
10991 pat
= gen_simple_return_internal (reg
);
10993 emit_jump_insn (pat
);
10997 /* Search from the beginning to the first use of K0 or K1. */
10998 if (cfun
->machine
->interrupt_handler_p
10999 && !cfun
->machine
->keep_interrupts_masked_p
)
11001 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11003 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11005 gcc_assert (insn
!= NULL_RTX
);
11006 /* Insert disable interrupts before the first use of K0 or K1. */
11007 emit_insn_before (gen_mips_di (), insn
);
11008 emit_insn_before (gen_mips_ehb (), insn
);
11012 /* Return nonzero if this function is known to have a null epilogue.
11013 This allows the optimizer to omit jumps to jumps if no stack
11017 mips_can_use_return_insn (void)
11019 /* Interrupt handlers need to go through the epilogue. */
11020 if (cfun
->machine
->interrupt_handler_p
)
11023 if (!reload_completed
)
11029 /* In MIPS16 mode, a function that returns a floating-point value
11030 needs to arrange to copy the return value into the floating-point
11032 if (mips16_cfun_returns_in_fpr_p ())
11035 return cfun
->machine
->frame
.total_size
== 0;
11038 /* Return true if register REGNO can store a value of mode MODE.
11039 The result of this function is cached in mips_hard_regno_mode_ok. */
11042 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11045 enum mode_class mclass
;
11047 if (mode
== CCV2mode
)
11048 return (ISA_HAS_8CC
11049 && ST_REG_P (regno
)
11050 && (regno
- ST_REG_FIRST
) % 2 == 0);
11052 if (mode
== CCV4mode
)
11053 return (ISA_HAS_8CC
11054 && ST_REG_P (regno
)
11055 && (regno
- ST_REG_FIRST
) % 4 == 0);
11057 if (mode
== CCmode
)
11060 return regno
== FPSW_REGNUM
;
11062 return (ST_REG_P (regno
)
11063 || GP_REG_P (regno
)
11064 || FP_REG_P (regno
));
11067 size
= GET_MODE_SIZE (mode
);
11068 mclass
= GET_MODE_CLASS (mode
);
11070 if (GP_REG_P (regno
))
11071 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11073 if (FP_REG_P (regno
)
11074 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11075 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11077 /* Allow TFmode for CCmode reloads. */
11078 if (mode
== TFmode
&& ISA_HAS_8CC
)
11081 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11082 if (TARGET_LOONGSON_VECTORS
11083 && (mode
== V2SImode
11084 || mode
== V4HImode
11085 || mode
== V8QImode
11086 || mode
== DImode
))
11089 if (mclass
== MODE_FLOAT
11090 || mclass
== MODE_COMPLEX_FLOAT
11091 || mclass
== MODE_VECTOR_FLOAT
)
11092 return size
<= UNITS_PER_FPVALUE
;
11094 /* Allow integer modes that fit into a single register. We need
11095 to put integers into FPRs when using instructions like CVT
11096 and TRUNC. There's no point allowing sizes smaller than a word,
11097 because the FPU has no appropriate load/store instructions. */
11098 if (mclass
== MODE_INT
)
11099 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11102 if (ACC_REG_P (regno
)
11103 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11105 if (MD_REG_P (regno
))
11107 /* After a multiplication or division, clobbering HI makes
11108 the value of LO unpredictable, and vice versa. This means
11109 that, for all interesting cases, HI and LO are effectively
11112 We model this by requiring that any value that uses HI
11114 if (size
<= UNITS_PER_WORD
* 2)
11115 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11119 /* DSP accumulators do not have the same restrictions as
11120 HI and LO, so we can treat them as normal doubleword
11122 if (size
<= UNITS_PER_WORD
)
11125 if (size
<= UNITS_PER_WORD
* 2
11126 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11131 if (ALL_COP_REG_P (regno
))
11132 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11134 if (regno
== GOT_VERSION_REGNUM
)
11135 return mode
== SImode
;
11140 /* Implement HARD_REGNO_NREGS. */
11143 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11145 if (ST_REG_P (regno
))
11146 /* The size of FP status registers is always 4, because they only hold
11147 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11148 return (GET_MODE_SIZE (mode
) + 3) / 4;
11150 if (FP_REG_P (regno
))
11151 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11153 /* All other registers are word-sized. */
11154 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11157 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11158 in mips_hard_regno_nregs. */
11161 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11167 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11168 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11170 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11171 size
= MIN (size
, 4);
11172 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11174 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11176 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11177 size
= MIN (size
, UNITS_PER_FPREG
);
11178 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11180 if (!hard_reg_set_empty_p (left
))
11181 size
= MIN (size
, UNITS_PER_WORD
);
11182 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11185 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11188 mips_cannot_change_mode_class (enum machine_mode from
,
11189 enum machine_mode to
,
11190 enum reg_class rclass
)
11192 /* Allow conversions between different Loongson integer vectors,
11193 and between those vectors and DImode. */
11194 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11195 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11198 /* Otherwise, there are several problems with changing the modes of
11199 values in floating-point registers:
11201 - When a multi-word value is stored in paired floating-point
11202 registers, the first register always holds the low word. We
11203 therefore can't allow FPRs to change between single-word and
11204 multi-word modes on big-endian targets.
11206 - GCC assumes that each word of a multiword register can be
11207 accessed individually using SUBREGs. This is not true for
11208 floating-point registers if they are bigger than a word.
11210 - Loading a 32-bit value into a 64-bit floating-point register
11211 will not sign-extend the value, despite what LOAD_EXTEND_OP
11212 says. We can't allow FPRs to change from SImode to a wider
11213 mode on 64-bit targets.
11215 - If the FPU has already interpreted a value in one format, we
11216 must not ask it to treat the value as having a different
11219 We therefore disallow all mode changes involving FPRs. */
11221 return reg_classes_intersect_p (FP_REGS
, rclass
);
11224 /* Implement target hook small_register_classes_for_mode_p. */
11227 mips_small_register_classes_for_mode_p (enum machine_mode mode
11230 return TARGET_MIPS16
;
11233 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11236 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11241 return TARGET_HARD_FLOAT
;
11244 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11247 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11254 /* Implement MODES_TIEABLE_P. */
11257 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11259 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11260 prefer to put one of them in FPRs. */
11261 return (mode1
== mode2
11262 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11263 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11266 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11269 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11271 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11274 if (reg_class_subset_p (FP_REGS
, rclass
)
11275 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11278 if (reg_class_subset_p (GR_REGS
, rclass
))
11281 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11287 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11288 Return a "canonical" class to represent it in later calculations. */
11291 mips_canonicalize_move_class (reg_class_t rclass
)
11293 /* All moves involving accumulator registers have the same cost. */
11294 if (reg_class_subset_p (rclass
, ACC_REGS
))
11297 /* Likewise promote subclasses of general registers to the most
11298 interesting containing class. */
11299 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11301 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11302 rclass
= GENERAL_REGS
;
11307 /* Return the cost of moving a value of mode MODE from a register of
11308 class FROM to a GPR. Return 0 for classes that are unions of other
11309 classes handled by this function. */
11312 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11318 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11322 /* MFLO and MFHI. */
11330 /* LUI followed by MOVF. */
11336 /* This choice of value is historical. */
11344 /* Return the cost of moving a value of mode MODE from a GPR to a
11345 register of class TO. Return 0 for classes that are unions of
11346 other classes handled by this function. */
11349 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11354 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11358 /* MTLO and MTHI. */
11366 /* A secondary reload through an FPR scratch. */
11367 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11368 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11373 /* This choice of value is historical. */
11381 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11382 maximum of the move costs for subclasses; regclass will work out
11383 the maximum for us. */
11386 mips_register_move_cost (enum machine_mode mode
,
11387 reg_class_t from
, reg_class_t to
)
11392 from
= mips_canonicalize_move_class (from
);
11393 to
= mips_canonicalize_move_class (to
);
11395 /* Handle moves that can be done without using general-purpose registers. */
11396 if (from
== FP_REGS
)
11398 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
11402 /* The sequence generated by mips_expand_fcc_reload. */
11406 /* Handle cases in which only one class deviates from the ideal. */
11407 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
11409 return mips_move_from_gpr_cost (mode
, to
);
11411 return mips_move_to_gpr_cost (mode
, from
);
11413 /* Handles cases that require a GPR temporary. */
11414 cost1
= mips_move_to_gpr_cost (mode
, from
);
11417 cost2
= mips_move_from_gpr_cost (mode
, to
);
11419 return cost1
+ cost2
;
11425 /* Implement TARGET_MEMORY_MOVE_COST. */
11428 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
11430 return (mips_cost
->memory_latency
11431 + memory_move_secondary_cost (mode
, rclass
, in
));
11434 /* Return the register class required for a secondary register when
11435 copying between one of the registers in RCLASS and value X, which
11436 has mode MODE. X is the source of the move if IN_P, otherwise it
11437 is the destination. Return NO_REGS if no secondary register is
11441 mips_secondary_reload_class (enum reg_class rclass
,
11442 enum machine_mode mode
, rtx x
, bool in_p
)
11446 /* If X is a constant that cannot be loaded into $25, it must be loaded
11447 into some other GPR. No other register class allows a direct move. */
11448 if (mips_dangerous_for_la25_p (x
))
11449 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11451 regno
= true_regnum (x
);
11454 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11455 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
11461 /* Copying from accumulator registers to anywhere other than a general
11462 register requires a temporary general register. */
11463 if (reg_class_subset_p (rclass
, ACC_REGS
))
11464 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11465 if (ACC_REG_P (regno
))
11466 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11468 /* We can only copy a value to a condition code register from a
11469 floating-point register, and even then we require a scratch
11470 floating-point register. We can only copy a value out of a
11471 condition-code register into a general register. */
11472 if (reg_class_subset_p (rclass
, ST_REGS
))
11476 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11478 if (ST_REG_P (regno
))
11482 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11485 if (reg_class_subset_p (rclass
, FP_REGS
))
11488 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
11489 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11490 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11493 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
11494 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11497 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
11498 /* We can force the constant to memory and use lwc1
11499 and ldc1. As above, we will use pairs of lwc1s if
11500 ldc1 is not supported. */
11503 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
11504 /* In this case we can use mov.fmt. */
11507 /* Otherwise, we need to reload through an integer register. */
11510 if (FP_REG_P (regno
))
11511 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11516 /* Implement TARGET_MODE_REP_EXTENDED. */
11519 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
11521 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11522 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
11523 return SIGN_EXTEND
;
11528 /* Implement TARGET_VALID_POINTER_MODE. */
11531 mips_valid_pointer_mode (enum machine_mode mode
)
11533 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
11536 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11539 mips_vector_mode_supported_p (enum machine_mode mode
)
11544 return TARGET_PAIRED_SINGLE_FLOAT
;
11559 return TARGET_LOONGSON_VECTORS
;
11566 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11569 mips_scalar_mode_supported_p (enum machine_mode mode
)
11571 if (ALL_FIXED_POINT_MODE_P (mode
)
11572 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
11575 return default_scalar_mode_supported_p (mode
);
11578 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11580 static enum machine_mode
11581 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
11583 if (TARGET_PAIRED_SINGLE_FLOAT
11589 /* Implement TARGET_INIT_LIBFUNCS. */
11592 mips_init_libfuncs (void)
11594 if (TARGET_FIX_VR4120
)
11596 /* Register the special divsi3 and modsi3 functions needed to work
11597 around VR4120 division errata. */
11598 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
11599 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
11602 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
11604 /* Register the MIPS16 -mhard-float stubs. */
11605 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
11606 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
11607 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
11608 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
11610 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
11611 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
11612 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
11613 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
11614 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
11615 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
11616 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
11618 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
11619 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
11620 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
11622 if (TARGET_DOUBLE_FLOAT
)
11624 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
11625 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
11626 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
11627 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
11629 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
11630 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
11631 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
11632 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
11633 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
11634 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
11635 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
11637 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
11638 "__mips16_extendsfdf2");
11639 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
11640 "__mips16_truncdfsf2");
11641 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
11642 "__mips16_fix_truncdfsi");
11643 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
11644 "__mips16_floatsidf");
11645 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
11646 "__mips16_floatunsidf");
11650 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11651 on an external non-MIPS16 routine to implement __sync_synchronize.
11652 Similarly for the rest of the ll/sc libfuncs. */
11655 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
11656 init_sync_libfuncs (UNITS_PER_WORD
);
11660 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11663 mips_process_load_label (rtx target
)
11665 rtx base
, gp
, intop
;
11666 HOST_WIDE_INT offset
;
11668 mips_multi_start ();
11672 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
11673 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11677 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
11678 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11682 gp
= pic_offset_table_rtx
;
11683 if (mips_cfun_has_cprestore_slot_p ())
11685 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
11686 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11687 if (!SMALL_OPERAND (offset
))
11689 intop
= GEN_INT (CONST_HIGH_PART (offset
));
11690 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
11691 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
11694 offset
= CONST_LOW_PART (offset
);
11696 intop
= GEN_INT (offset
);
11697 if (ISA_HAS_LOAD_DELAY
)
11698 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
11700 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
11702 if (ISA_HAS_LOAD_DELAY
)
11703 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
11705 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
11706 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
11711 /* Return the number of instructions needed to load a label into $AT. */
11713 static unsigned int
11714 mips_load_label_num_insns (void)
11716 if (cfun
->machine
->load_label_num_insns
== 0)
11718 mips_process_load_label (pc_rtx
);
11719 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
11721 return cfun
->machine
->load_label_num_insns
;
11724 /* Emit an asm sequence to start a noat block and load the address
11725 of a label into $1. */
11728 mips_output_load_label (rtx target
)
11730 mips_push_asm_switch (&mips_noat
);
11731 if (TARGET_EXPLICIT_RELOCS
)
11733 mips_process_load_label (target
);
11734 mips_multi_write ();
11738 if (Pmode
== DImode
)
11739 output_asm_insn ("dla\t%@,%0", &target
);
11741 output_asm_insn ("la\t%@,%0", &target
);
11745 /* Return the length of INSN. LENGTH is the initial length computed by
11746 attributes in the machine-description file. */
11749 mips_adjust_insn_length (rtx insn
, int length
)
11751 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11752 of a PIC long-branch sequence. Substitute the correct value. */
11753 if (length
== MAX_PIC_BRANCH_LENGTH
11754 && INSN_CODE (insn
) >= 0
11755 && get_attr_type (insn
) == TYPE_BRANCH
)
11757 /* Add the branch-over instruction and its delay slot, if this
11758 is a conditional branch. */
11759 length
= simplejump_p (insn
) ? 0 : 8;
11761 /* Load the label into $AT and jump to it. Ignore the delay
11762 slot of the jump. */
11763 length
+= 4 * mips_load_label_num_insns() + 4;
11766 /* A unconditional jump has an unfilled delay slot if it is not part
11767 of a sequence. A conditional jump normally has a delay slot, but
11768 does not on MIPS16. */
11769 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
11772 /* See how many nops might be needed to avoid hardware hazards. */
11773 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
11774 switch (get_attr_hazard (insn
))
11788 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11789 the .md file length attributes are 4-based for both modes.
11790 Adjust the MIPS16 ones here. */
11797 /* Return the assembly code for INSN, which has the operands given by
11798 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11799 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11800 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11801 version of BRANCH_IF_TRUE. */
11804 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
11805 const char *branch_if_true
,
11806 const char *branch_if_false
)
11808 unsigned int length
;
11809 rtx taken
, not_taken
;
11811 gcc_assert (LABEL_P (operands
[0]));
11813 length
= get_attr_length (insn
);
11816 /* Just a simple conditional branch. */
11817 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
11818 return branch_if_true
;
11821 /* Generate a reversed branch around a direct jump. This fallback does
11822 not use branch-likely instructions. */
11823 mips_branch_likely
= false;
11824 not_taken
= gen_label_rtx ();
11825 taken
= operands
[0];
11827 /* Generate the reversed branch to NOT_TAKEN. */
11828 operands
[0] = not_taken
;
11829 output_asm_insn (branch_if_false
, operands
);
11831 /* If INSN has a delay slot, we must provide delay slots for both the
11832 branch to NOT_TAKEN and the conditional jump. We must also ensure
11833 that INSN's delay slot is executed in the appropriate cases. */
11834 if (final_sequence
)
11836 /* This first delay slot will always be executed, so use INSN's
11837 delay slot if is not annulled. */
11838 if (!INSN_ANNULLED_BRANCH_P (insn
))
11840 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11841 asm_out_file
, optimize
, 1, NULL
);
11842 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11845 output_asm_insn ("nop", 0);
11846 fprintf (asm_out_file
, "\n");
11849 /* Output the unconditional branch to TAKEN. */
11850 if (TARGET_ABSOLUTE_JUMPS
)
11851 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
11854 mips_output_load_label (taken
);
11855 output_asm_insn ("jr\t%@%]%/", 0);
11858 /* Now deal with its delay slot; see above. */
11859 if (final_sequence
)
11861 /* This delay slot will only be executed if the branch is taken.
11862 Use INSN's delay slot if is annulled. */
11863 if (INSN_ANNULLED_BRANCH_P (insn
))
11865 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11866 asm_out_file
, optimize
, 1, NULL
);
11867 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11870 output_asm_insn ("nop", 0);
11871 fprintf (asm_out_file
, "\n");
11874 /* Output NOT_TAKEN. */
11875 targetm
.asm_out
.internal_label (asm_out_file
, "L",
11876 CODE_LABEL_NUMBER (not_taken
));
11880 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11881 if some ordering condition is true. The condition is given by
11882 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11883 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11884 its second is always zero. */
11887 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
11889 const char *branch
[2];
11891 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11892 Make BRANCH[0] branch on the inverse condition. */
11893 switch (GET_CODE (operands
[1]))
11895 /* These cases are equivalent to comparisons against zero. */
11897 inverted_p
= !inverted_p
;
11898 /* Fall through. */
11900 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
11901 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
11904 /* These cases are always true or always false. */
11906 inverted_p
= !inverted_p
;
11907 /* Fall through. */
11909 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
11910 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
11914 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
11915 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
11918 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
11921 /* Start a block of code that needs access to the LL, SC and SYNC
11925 mips_start_ll_sc_sync_block (void)
11927 if (!ISA_HAS_LL_SC
)
11929 output_asm_insn (".set\tpush", 0);
11930 output_asm_insn (".set\tmips2", 0);
11934 /* End a block started by mips_start_ll_sc_sync_block. */
11937 mips_end_ll_sc_sync_block (void)
11939 if (!ISA_HAS_LL_SC
)
11940 output_asm_insn (".set\tpop", 0);
11943 /* Output and/or return the asm template for a sync instruction. */
11946 mips_output_sync (void)
11948 mips_start_ll_sc_sync_block ();
11949 output_asm_insn ("sync", 0);
11950 mips_end_ll_sc_sync_block ();
11954 /* Return the asm template associated with sync_insn1 value TYPE.
11955 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11957 static const char *
11958 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
11962 case SYNC_INSN1_MOVE
:
11963 return "move\t%0,%z2";
11964 case SYNC_INSN1_LI
:
11965 return "li\t%0,%2";
11966 case SYNC_INSN1_ADDU
:
11967 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11968 case SYNC_INSN1_ADDIU
:
11969 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11970 case SYNC_INSN1_SUBU
:
11971 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11972 case SYNC_INSN1_AND
:
11973 return "and\t%0,%1,%z2";
11974 case SYNC_INSN1_ANDI
:
11975 return "andi\t%0,%1,%2";
11976 case SYNC_INSN1_OR
:
11977 return "or\t%0,%1,%z2";
11978 case SYNC_INSN1_ORI
:
11979 return "ori\t%0,%1,%2";
11980 case SYNC_INSN1_XOR
:
11981 return "xor\t%0,%1,%z2";
11982 case SYNC_INSN1_XORI
:
11983 return "xori\t%0,%1,%2";
11985 gcc_unreachable ();
11988 /* Return the asm template associated with sync_insn2 value TYPE. */
11990 static const char *
11991 mips_sync_insn2_template (enum attr_sync_insn2 type
)
11995 case SYNC_INSN2_NOP
:
11996 gcc_unreachable ();
11997 case SYNC_INSN2_AND
:
11998 return "and\t%0,%1,%z2";
11999 case SYNC_INSN2_XOR
:
12000 return "xor\t%0,%1,%z2";
12001 case SYNC_INSN2_NOT
:
12002 return "nor\t%0,%1,%.";
12004 gcc_unreachable ();
12007 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12008 the value of the one of the sync_* attributes. Return the operand
12009 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12010 have the associated attribute. */
12013 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12016 default_value
= operands
[index
- 1];
12017 return default_value
;
12020 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12021 sequence for it. */
12024 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12026 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12027 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12028 unsigned int tmp3_insn
;
12029 enum attr_sync_insn1 insn1
;
12030 enum attr_sync_insn2 insn2
;
12033 enum memmodel model
;
12035 /* Read an operand from the sync_WHAT attribute and store it in
12036 variable WHAT. DEFAULT is the default value if no attribute
12038 #define READ_OPERAND(WHAT, DEFAULT) \
12039 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12042 /* Read the memory. */
12043 READ_OPERAND (mem
, 0);
12045 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12047 /* Read the other attributes. */
12048 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12049 READ_OPERAND (oldval
, at
);
12050 READ_OPERAND (cmp
, 0);
12051 READ_OPERAND (newval
, at
);
12052 READ_OPERAND (inclusive_mask
, 0);
12053 READ_OPERAND (exclusive_mask
, 0);
12054 READ_OPERAND (required_oldval
, 0);
12055 READ_OPERAND (insn1_op2
, 0);
12056 insn1
= get_attr_sync_insn1 (insn
);
12057 insn2
= get_attr_sync_insn2 (insn
);
12059 /* Don't bother setting CMP result that is never used. */
12060 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12063 memmodel_attr
= get_attr_sync_memmodel (insn
);
12064 switch (memmodel_attr
)
12067 model
= MEMMODEL_ACQ_REL
;
12070 model
= MEMMODEL_ACQUIRE
;
12073 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12076 mips_multi_start ();
12078 /* Output the release side of the memory barrier. */
12079 if (need_atomic_barrier_p (model
, true))
12081 if (required_oldval
== 0 && TARGET_OCTEON
)
12083 /* Octeon doesn't reorder reads, so a full barrier can be
12084 created by using SYNCW to order writes combined with the
12085 write from the following SC. When the SC successfully
12086 completes, we know that all preceding writes are also
12087 committed to the coherent memory system. It is possible
12088 for a single SYNCW to fail, but a pair of them will never
12089 fail, so we use two. */
12090 mips_multi_add_insn ("syncw", NULL
);
12091 mips_multi_add_insn ("syncw", NULL
);
12094 mips_multi_add_insn ("sync", NULL
);
12097 /* Output the branch-back label. */
12098 mips_multi_add_label ("1:");
12100 /* OLDVAL = *MEM. */
12101 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12102 oldval
, mem
, NULL
);
12104 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12105 if (required_oldval
)
12107 if (inclusive_mask
== 0)
12111 gcc_assert (oldval
!= at
);
12112 mips_multi_add_insn ("and\t%0,%1,%2",
12113 at
, oldval
, inclusive_mask
, NULL
);
12116 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12118 /* CMP = 0 [delay slot]. */
12120 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12123 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12124 if (exclusive_mask
== 0)
12128 gcc_assert (oldval
!= at
);
12129 mips_multi_add_insn ("and\t%0,%1,%z2",
12130 at
, oldval
, exclusive_mask
, NULL
);
12134 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12136 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12137 at least one instruction in that case. */
12138 if (insn1
== SYNC_INSN1_MOVE
12139 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12143 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12144 newval
, oldval
, insn1_op2
, NULL
);
12148 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12149 if (insn2
== SYNC_INSN2_NOP
)
12153 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12154 newval
, tmp2
, inclusive_mask
, NULL
);
12157 tmp3_insn
= mips_multi_last_index ();
12159 /* $AT = $TMP1 | $TMP3. */
12160 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12162 mips_multi_set_operand (tmp3_insn
, 0, at
);
12167 gcc_assert (tmp1
!= tmp3
);
12168 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12171 /* if (!commit (*MEM = $AT)) goto 1.
12173 This will sometimes be a delayed branch; see the write code below
12175 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12176 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12178 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12179 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12181 mips_multi_copy_insn (tmp3_insn
);
12182 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12184 else if (!(required_oldval
&& cmp
))
12185 mips_multi_add_insn ("nop", NULL
);
12187 /* CMP = 1 -- either standalone or in a delay slot. */
12188 if (required_oldval
&& cmp
)
12189 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12191 /* Output the acquire side of the memory barrier. */
12192 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12193 mips_multi_add_insn ("sync", NULL
);
12195 /* Output the exit label, if needed. */
12196 if (required_oldval
)
12197 mips_multi_add_label ("2:");
12199 #undef READ_OPERAND
12202 /* Output and/or return the asm template for sync loop INSN, which has
12203 the operands given by OPERANDS. */
12206 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12208 mips_process_sync_loop (insn
, operands
);
12210 /* Use branch-likely instructions to work around the LL/SC R10000
12212 mips_branch_likely
= TARGET_FIX_R10000
;
12214 mips_push_asm_switch (&mips_noreorder
);
12215 mips_push_asm_switch (&mips_nomacro
);
12216 mips_push_asm_switch (&mips_noat
);
12217 mips_start_ll_sc_sync_block ();
12219 mips_multi_write ();
12221 mips_end_ll_sc_sync_block ();
12222 mips_pop_asm_switch (&mips_noat
);
12223 mips_pop_asm_switch (&mips_nomacro
);
12224 mips_pop_asm_switch (&mips_noreorder
);
12229 /* Return the number of individual instructions in sync loop INSN,
12230 which has the operands given by OPERANDS. */
12233 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12235 mips_process_sync_loop (insn
, operands
);
12236 return mips_multi_num_insns
;
12239 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12240 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12242 When working around R4000 and R4400 errata, we need to make sure that
12243 the division is not immediately followed by a shift[1][2]. We also
12244 need to stop the division from being put into a branch delay slot[3].
12245 The easiest way to avoid both problems is to add a nop after the
12246 division. When a divide-by-zero check is needed, this nop can be
12247 used to fill the branch delay slot.
12249 [1] If a double-word or a variable shift executes immediately
12250 after starting an integer division, the shift may give an
12251 incorrect result. See quotations of errata #16 and #28 from
12252 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12253 in mips.md for details.
12255 [2] A similar bug to [1] exists for all revisions of the
12256 R4000 and the R4400 when run in an MC configuration.
12257 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12259 "19. In this following sequence:
12261 ddiv (or ddivu or div or divu)
12262 dsll32 (or dsrl32, dsra32)
12264 if an MPT stall occurs, while the divide is slipping the cpu
12265 pipeline, then the following double shift would end up with an
12268 Workaround: The compiler needs to avoid generating any
12269 sequence with divide followed by extended double shift."
12271 This erratum is also present in "MIPS R4400MC Errata, Processor
12272 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12273 & 3.0" as errata #10 and #4, respectively.
12275 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12276 (also valid for MIPS R4000MC processors):
12278 "52. R4000SC: This bug does not apply for the R4000PC.
12280 There are two flavors of this bug:
12282 1) If the instruction just after divide takes an RF exception
12283 (tlb-refill, tlb-invalid) and gets an instruction cache
12284 miss (both primary and secondary) and the line which is
12285 currently in secondary cache at this index had the first
12286 data word, where the bits 5..2 are set, then R4000 would
12287 get a wrong result for the div.
12292 ------------------- # end-of page. -tlb-refill
12297 ------------------- # end-of page. -tlb-invalid
12300 2) If the divide is in the taken branch delay slot, where the
12301 target takes RF exception and gets an I-cache miss for the
12302 exception vector or where I-cache miss occurs for the
12303 target address, under the above mentioned scenarios, the
12304 div would get wrong results.
12307 j r2 # to next page mapped or unmapped
12308 div r8,r9 # this bug would be there as long
12309 # as there is an ICache miss and
12310 nop # the "data pattern" is present
12313 beq r0, r0, NextPage # to Next page
12317 This bug is present for div, divu, ddiv, and ddivu
12320 Workaround: For item 1), OS could make sure that the next page
12321 after the divide instruction is also mapped. For item 2), the
12322 compiler could make sure that the divide instruction is not in
12323 the branch delay slot."
12325 These processors have PRId values of 0x00004220 and 0x00004300 for
12326 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12329 mips_output_division (const char *division
, rtx
*operands
)
12334 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12336 output_asm_insn (s
, operands
);
12339 if (TARGET_CHECK_ZERO_DIV
)
12343 output_asm_insn (s
, operands
);
12344 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12346 else if (GENERATE_DIVIDE_TRAPS
)
12348 /* Avoid long replay penalty on load miss by putting the trap before
12351 output_asm_insn ("teq\t%2,%.,7", operands
);
12354 output_asm_insn (s
, operands
);
12355 s
= "teq\t%2,%.,7";
12360 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12361 output_asm_insn (s
, operands
);
12362 s
= "break\t7%)\n1:";
12368 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12369 instruction and if OUT_INSN assigns to the accumulator operand. */
12372 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12376 x
= single_set (in_insn
);
12382 if (GET_CODE (x
) == PLUS
12383 && GET_CODE (XEXP (x
, 0)) == MULT
12384 && reg_set_p (XEXP (x
, 1), out_insn
))
12387 if (GET_CODE (x
) == MINUS
12388 && GET_CODE (XEXP (x
, 1)) == MULT
12389 && reg_set_p (XEXP (x
, 0), out_insn
))
12395 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12396 data rather than the address. We need this because the cprestore
12397 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12398 which causes the default routine to abort. We just return false
12402 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
12404 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
12407 return !store_data_bypass_p (out_insn
, in_insn
);
12411 /* Variables and flags used in scheduler hooks when tuning for
12415 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12418 /* If true, then next ALU1/2 instruction will go to ALU1. */
12421 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12424 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12425 int alu1_core_unit_code
;
12426 int alu2_core_unit_code
;
12427 int falu1_core_unit_code
;
12428 int falu2_core_unit_code
;
12430 /* True if current cycle has a multi instruction.
12431 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12432 bool cycle_has_multi_p
;
12434 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12435 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12437 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12438 instruction to go ALU1. */
12439 rtx alu1_turn_enabled_insn
;
12440 rtx alu2_turn_enabled_insn
;
12441 rtx falu1_turn_enabled_insn
;
12442 rtx falu2_turn_enabled_insn
;
12445 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12446 dependencies have no cost, except on the 20Kc where output-dependence
12447 is treated like input-dependence. */
12450 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
12451 rtx dep ATTRIBUTE_UNUSED
, int cost
)
12453 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
12456 if (REG_NOTE_KIND (link
) != 0)
12461 /* Return the number of instructions that can be issued per cycle. */
12464 mips_issue_rate (void)
12468 case PROCESSOR_74KC
:
12469 case PROCESSOR_74KF2_1
:
12470 case PROCESSOR_74KF1_1
:
12471 case PROCESSOR_74KF3_2
:
12472 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12473 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12474 but in reality only a maximum of 3 insns can be issued as
12475 floating-point loads and stores also require a slot in the
12477 case PROCESSOR_R10000
:
12478 /* All R10K Processors are quad-issue (being the first MIPS
12479 processors to support this feature). */
12482 case PROCESSOR_20KC
:
12483 case PROCESSOR_R4130
:
12484 case PROCESSOR_R5400
:
12485 case PROCESSOR_R5500
:
12486 case PROCESSOR_R7000
:
12487 case PROCESSOR_R9000
:
12488 case PROCESSOR_OCTEON
:
12489 case PROCESSOR_OCTEON2
:
12492 case PROCESSOR_SB1
:
12493 case PROCESSOR_SB1A
:
12494 /* This is actually 4, but we get better performance if we claim 3.
12495 This is partly because of unwanted speculative code motion with the
12496 larger number, and partly because in most common cases we can't
12497 reach the theoretical max of 4. */
12500 case PROCESSOR_LOONGSON_2E
:
12501 case PROCESSOR_LOONGSON_2F
:
12502 case PROCESSOR_LOONGSON_3A
:
12505 case PROCESSOR_XLP
:
12506 return (reload_completed
? 4 : 3);
12513 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12516 mips_ls2_init_dfa_post_cycle_insn (void)
12519 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12520 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
12524 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12525 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
12529 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12530 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
12534 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12535 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
12538 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
12539 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
12540 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
12541 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
12544 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12545 Init data used in mips_dfa_post_advance_cycle. */
12548 mips_init_dfa_post_cycle_insn (void)
12550 if (TUNE_LOONGSON_2EF
)
12551 mips_ls2_init_dfa_post_cycle_insn ();
12554 /* Initialize STATE when scheduling for Loongson 2E/2F.
12555 Support round-robin dispatch scheme by enabling only one of
12556 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12560 mips_ls2_dfa_post_advance_cycle (state_t state
)
12562 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
12564 /* Though there are no non-pipelined ALU1 insns,
12565 we can get an instruction of type 'multi' before reload. */
12566 gcc_assert (mips_ls2
.cycle_has_multi_p
);
12567 mips_ls2
.alu1_turn_p
= false;
12570 mips_ls2
.cycle_has_multi_p
= false;
12572 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
12573 /* We have a non-pipelined alu instruction in the core,
12574 adjust round-robin counter. */
12575 mips_ls2
.alu1_turn_p
= true;
12577 if (mips_ls2
.alu1_turn_p
)
12579 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
12580 gcc_unreachable ();
12584 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
12585 gcc_unreachable ();
12588 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
12590 /* There are no non-pipelined FALU1 insns. */
12591 gcc_unreachable ();
12592 mips_ls2
.falu1_turn_p
= false;
12595 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
12596 /* We have a non-pipelined falu instruction in the core,
12597 adjust round-robin counter. */
12598 mips_ls2
.falu1_turn_p
= true;
12600 if (mips_ls2
.falu1_turn_p
)
12602 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
12603 gcc_unreachable ();
12607 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
12608 gcc_unreachable ();
12612 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12613 This hook is being called at the start of each cycle. */
12616 mips_dfa_post_advance_cycle (void)
12618 if (TUNE_LOONGSON_2EF
)
12619 mips_ls2_dfa_post_advance_cycle (curr_state
);
12622 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12623 be as wide as the scheduling freedom in the DFA. */
12626 mips_multipass_dfa_lookahead (void)
12628 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12632 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
12641 /* Remove the instruction at index LOWER from ready queue READY and
12642 reinsert it in front of the instruction at index HIGHER. LOWER must
12646 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
12651 new_head
= ready
[lower
];
12652 for (i
= lower
; i
< higher
; i
++)
12653 ready
[i
] = ready
[i
+ 1];
12654 ready
[i
] = new_head
;
12657 /* If the priority of the instruction at POS2 in the ready queue READY
12658 is within LIMIT units of that of the instruction at POS1, swap the
12659 instructions if POS2 is not already less than POS1. */
12662 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
12665 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
12669 temp
= ready
[pos1
];
12670 ready
[pos1
] = ready
[pos2
];
12671 ready
[pos2
] = temp
;
12675 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12676 that may clobber hi or lo. */
12677 static rtx mips_macc_chains_last_hilo
;
12679 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12680 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12683 mips_macc_chains_record (rtx insn
)
12685 if (get_attr_may_clobber_hilo (insn
))
12686 mips_macc_chains_last_hilo
= insn
;
12689 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12690 has NREADY elements, looking for a multiply-add or multiply-subtract
12691 instruction that is cumulative with mips_macc_chains_last_hilo.
12692 If there is one, promote it ahead of anything else that might
12693 clobber hi or lo. */
12696 mips_macc_chains_reorder (rtx
*ready
, int nready
)
12700 if (mips_macc_chains_last_hilo
!= 0)
12701 for (i
= nready
- 1; i
>= 0; i
--)
12702 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
12704 for (j
= nready
- 1; j
> i
; j
--)
12705 if (recog_memoized (ready
[j
]) >= 0
12706 && get_attr_may_clobber_hilo (ready
[j
]))
12708 mips_promote_ready (ready
, i
, j
);
12715 /* The last instruction to be scheduled. */
12716 static rtx vr4130_last_insn
;
12718 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12719 points to an rtx that is initially an instruction. Nullify the rtx
12720 if the instruction uses the value of register X. */
12723 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
12728 insn_ptr
= (rtx
*) data
;
12731 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
12735 /* Return true if there is true register dependence between vr4130_last_insn
12739 vr4130_true_reg_dependence_p (rtx insn
)
12741 note_stores (PATTERN (vr4130_last_insn
),
12742 vr4130_true_reg_dependence_p_1
, &insn
);
12746 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12747 the ready queue and that INSN2 is the instruction after it, return
12748 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12749 in which INSN1 and INSN2 can probably issue in parallel, but for
12750 which (INSN2, INSN1) should be less sensitive to instruction
12751 alignment than (INSN1, INSN2). See 4130.md for more details. */
12754 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
12756 sd_iterator_def sd_it
;
12759 /* Check for the following case:
12761 1) there is some other instruction X with an anti dependence on INSN1;
12762 2) X has a higher priority than INSN2; and
12763 3) X is an arithmetic instruction (and thus has no unit restrictions).
12765 If INSN1 is the last instruction blocking X, it would better to
12766 choose (INSN1, X) over (INSN2, INSN1). */
12767 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
12768 if (DEP_TYPE (dep
) == REG_DEP_ANTI
12769 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
12770 && recog_memoized (DEP_CON (dep
)) >= 0
12771 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
12774 if (vr4130_last_insn
!= 0
12775 && recog_memoized (insn1
) >= 0
12776 && recog_memoized (insn2
) >= 0)
12778 /* See whether INSN1 and INSN2 use different execution units,
12779 or if they are both ALU-type instructions. If so, they can
12780 probably execute in parallel. */
12781 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
12782 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
12783 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
12785 /* If only one of the instructions has a dependence on
12786 vr4130_last_insn, prefer to schedule the other one first. */
12787 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
12788 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
12789 if (dep1_p
!= dep2_p
)
12792 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12793 is not an ALU-type instruction and if INSN1 uses the same
12794 execution unit. (Note that if this condition holds, we already
12795 know that INSN2 uses a different execution unit.) */
12796 if (class1
!= VR4130_CLASS_ALU
12797 && recog_memoized (vr4130_last_insn
) >= 0
12798 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
12805 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12806 queue with at least two instructions. Swap the first two if
12807 vr4130_swap_insns_p says that it could be worthwhile. */
12810 vr4130_reorder (rtx
*ready
, int nready
)
12812 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
12813 mips_promote_ready (ready
, nready
- 2, nready
- 1);
12816 /* Record whether last 74k AGEN instruction was a load or store. */
12817 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12819 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12820 resets to TYPE_UNKNOWN state. */
12823 mips_74k_agen_init (rtx insn
)
12825 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
12826 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12829 enum attr_type type
= get_attr_type (insn
);
12830 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
12831 mips_last_74k_agen_insn
= type
;
12835 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12836 loads to be grouped together, and multiple stores to be grouped
12837 together. Swap things around in the ready queue to make this happen. */
12840 mips_74k_agen_reorder (rtx
*ready
, int nready
)
12843 int store_pos
, load_pos
;
12848 for (i
= nready
- 1; i
>= 0; i
--)
12850 rtx insn
= ready
[i
];
12851 if (USEFUL_INSN_P (insn
))
12852 switch (get_attr_type (insn
))
12855 if (store_pos
== -1)
12860 if (load_pos
== -1)
12869 if (load_pos
== -1 || store_pos
== -1)
12872 switch (mips_last_74k_agen_insn
)
12875 /* Prefer to schedule loads since they have a higher latency. */
12877 /* Swap loads to the front of the queue. */
12878 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
12881 /* Swap stores to the front of the queue. */
12882 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
12889 /* Implement TARGET_SCHED_INIT. */
12892 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12893 int max_ready ATTRIBUTE_UNUSED
)
12895 mips_macc_chains_last_hilo
= 0;
12896 vr4130_last_insn
= 0;
12897 mips_74k_agen_init (NULL_RTX
);
12899 /* When scheduling for Loongson2, branch instructions go to ALU1,
12900 therefore basic block is most likely to start with round-robin counter
12901 pointed to ALU2. */
12902 mips_ls2
.alu1_turn_p
= false;
12903 mips_ls2
.falu1_turn_p
= true;
12906 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12909 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12910 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12912 if (!reload_completed
12913 && TUNE_MACC_CHAINS
12915 mips_macc_chains_reorder (ready
, *nreadyp
);
12917 if (reload_completed
12919 && !TARGET_VR4130_ALIGN
12921 vr4130_reorder (ready
, *nreadyp
);
12924 mips_74k_agen_reorder (ready
, *nreadyp
);
12927 /* Implement TARGET_SCHED_REORDER. */
12930 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12931 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12933 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12934 return mips_issue_rate ();
12937 /* Implement TARGET_SCHED_REORDER2. */
12940 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12941 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12943 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12944 return cached_can_issue_more
;
12947 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12950 mips_ls2_variable_issue (rtx insn
)
12952 if (mips_ls2
.alu1_turn_p
)
12954 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
12955 mips_ls2
.alu1_turn_p
= false;
12959 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
12960 mips_ls2
.alu1_turn_p
= true;
12963 if (mips_ls2
.falu1_turn_p
)
12965 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
12966 mips_ls2
.falu1_turn_p
= false;
12970 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
12971 mips_ls2
.falu1_turn_p
= true;
12974 if (recog_memoized (insn
) >= 0)
12975 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
12978 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12981 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12982 rtx insn
, int more
)
12984 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12985 if (USEFUL_INSN_P (insn
))
12987 if (get_attr_type (insn
) != TYPE_GHOST
)
12989 if (!reload_completed
&& TUNE_MACC_CHAINS
)
12990 mips_macc_chains_record (insn
);
12991 vr4130_last_insn
= insn
;
12993 mips_74k_agen_init (insn
);
12994 else if (TUNE_LOONGSON_2EF
)
12995 mips_ls2_variable_issue (insn
);
12998 /* Instructions of type 'multi' should all be split before
12999 the second scheduling pass. */
13000 gcc_assert (!reload_completed
13001 || recog_memoized (insn
) < 0
13002 || get_attr_type (insn
) != TYPE_MULTI
);
13004 cached_can_issue_more
= more
;
13008 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13009 return the first operand of the associated PREF or PREFX insn. */
13012 mips_prefetch_cookie (rtx write
, rtx locality
)
13014 /* store_streamed / load_streamed. */
13015 if (INTVAL (locality
) <= 0)
13016 return GEN_INT (INTVAL (write
) + 4);
13018 /* store / load. */
13019 if (INTVAL (locality
) <= 2)
13022 /* store_retained / load_retained. */
13023 return GEN_INT (INTVAL (write
) + 6);
13026 /* Flags that indicate when a built-in function is available.
13028 BUILTIN_AVAIL_NON_MIPS16
13029 The function is available on the current target, but only
13030 in non-MIPS16 mode. */
13031 #define BUILTIN_AVAIL_NON_MIPS16 1
13033 /* Declare an availability predicate for built-in functions that
13034 require non-MIPS16 mode and also require COND to be true.
13035 NAME is the main part of the predicate's name. */
13036 #define AVAIL_NON_MIPS16(NAME, COND) \
13037 static unsigned int \
13038 mips_builtin_avail_##NAME (void) \
13040 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13043 /* This structure describes a single built-in function. */
13044 struct mips_builtin_description
{
13045 /* The code of the main .md file instruction. See mips_builtin_type
13046 for more information. */
13047 enum insn_code icode
;
13049 /* The floating-point comparison code to use with ICODE, if any. */
13050 enum mips_fp_condition cond
;
13052 /* The name of the built-in function. */
13055 /* Specifies how the function should be expanded. */
13056 enum mips_builtin_type builtin_type
;
13058 /* The function's prototype. */
13059 enum mips_function_type function_type
;
13061 /* Whether the function is available. */
13062 unsigned int (*avail
) (void);
13065 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13066 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13067 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13068 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13069 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13070 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13071 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13072 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13073 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13074 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13076 /* Construct a mips_builtin_description from the given arguments.
13078 INSN is the name of the associated instruction pattern, without the
13079 leading CODE_FOR_mips_.
13081 CODE is the floating-point condition code associated with the
13082 function. It can be 'f' if the field is not applicable.
13084 NAME is the name of the function itself, without the leading
13087 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13089 AVAIL is the name of the availability predicate, without the leading
13090 mips_builtin_avail_. */
13091 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13092 FUNCTION_TYPE, AVAIL) \
13093 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13094 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13095 mips_builtin_avail_ ## AVAIL }
13097 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13098 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13099 are as for MIPS_BUILTIN. */
13100 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13101 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13103 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13104 are subject to mips_builtin_avail_<AVAIL>. */
13105 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13106 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13107 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13108 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13109 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13111 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13112 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13113 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13114 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13115 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13116 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13118 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13119 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13121 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13122 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13124 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13125 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13128 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13129 are subject to mips_builtin_avail_mips3d. */
13130 #define CMP_4S_BUILTINS(INSN, COND) \
13131 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13132 MIPS_BUILTIN_CMP_ANY, \
13133 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13134 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13135 MIPS_BUILTIN_CMP_ALL, \
13136 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13138 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13139 instruction requires mips_builtin_avail_<AVAIL>. */
13140 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13141 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13142 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13144 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13145 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13148 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13149 #define CMP_BUILTINS(COND) \
13150 MOVTF_BUILTINS (c, COND, paired_single), \
13151 MOVTF_BUILTINS (cabs, COND, mips3d), \
13152 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13153 CMP_PS_BUILTINS (c, COND, paired_single), \
13154 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13155 CMP_4S_BUILTINS (c, COND), \
13156 CMP_4S_BUILTINS (cabs, COND)
13158 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13159 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13160 and AVAIL are as for MIPS_BUILTIN. */
13161 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13162 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13163 FUNCTION_TYPE, AVAIL)
13165 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13166 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13167 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13168 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13169 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13171 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13172 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13173 builtin_description field. */
13174 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13175 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13176 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13177 FUNCTION_TYPE, mips_builtin_avail_loongson }
13179 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13180 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13181 builtin_description field. */
13182 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13183 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13185 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13186 We use functions of this form when the same insn can be usefully applied
13187 to more than one datatype. */
13188 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13189 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13191 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13192 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13193 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13194 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13195 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13196 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13197 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13198 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13200 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13201 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13202 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13203 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13204 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13205 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13206 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13207 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13208 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13209 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13210 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13211 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13212 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13213 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13214 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13215 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13216 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13217 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13218 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13219 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13220 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13221 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13222 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13223 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13224 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13225 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13226 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13227 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13228 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13229 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13231 static const struct mips_builtin_description mips_builtins
[] = {
13232 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13233 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13234 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13235 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13236 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13237 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13238 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13239 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13241 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13242 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13243 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13244 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13245 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13247 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13248 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13249 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13250 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13251 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13252 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13254 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13255 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13256 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13257 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13258 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13259 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13261 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13263 /* Built-in functions for the SB-1 processor. */
13264 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13266 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13267 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13268 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13269 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13270 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13271 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13272 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13273 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13274 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13275 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13276 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13277 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13278 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13279 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13280 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13281 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13282 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13283 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13284 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13285 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13286 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13287 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13288 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13289 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13290 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13291 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13292 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13293 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13294 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13295 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13296 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13297 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13298 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13299 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13300 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13301 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13302 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13303 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13304 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13305 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13306 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13307 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13308 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13309 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13310 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13311 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13312 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13313 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13314 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13315 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13316 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13317 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13318 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13319 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13320 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13321 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13322 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13323 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13324 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13325 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13326 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13327 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13328 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13329 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13330 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13331 BPOSGE_BUILTIN (32, dsp
),
13333 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13334 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13335 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13336 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13337 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13338 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13339 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13340 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13341 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13342 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13343 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13344 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13345 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13346 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13347 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13348 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13349 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13350 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13351 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13352 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13353 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13354 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13355 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13356 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13357 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13358 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13359 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13360 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13361 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13362 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13363 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13364 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13365 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13366 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13367 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13369 /* Built-in functions for the DSP ASE (32-bit only). */
13370 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13371 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13372 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13373 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13374 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13375 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13376 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13377 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13378 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13379 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13380 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13381 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13382 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13383 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13384 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13385 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13386 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13387 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13388 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13389 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13390 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13391 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13392 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13393 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13394 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13395 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
13396 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
13398 /* Built-in functions for the DSP ASE (64-bit only). */
13399 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
13401 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13402 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13403 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13404 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13405 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13406 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13407 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13408 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13409 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13410 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13412 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13413 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
13414 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
13415 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
13416 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13417 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13418 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13419 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13420 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13421 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13422 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13423 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
13424 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13425 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13426 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13427 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13428 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
13429 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13430 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13431 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13432 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
13433 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13434 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13435 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13436 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13437 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13438 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13439 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13440 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13441 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13442 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13443 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13444 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13445 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13446 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13447 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13448 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13449 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13450 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
13451 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
13452 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13453 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13454 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13455 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13456 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13457 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13458 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13459 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13460 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
13461 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13462 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13463 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13464 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13465 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
13466 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
13467 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13468 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13469 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13470 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
13471 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13472 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
13473 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
13474 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13475 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13476 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13477 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13478 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13479 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13480 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13481 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13482 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13483 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13484 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13485 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13486 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13487 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13488 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13489 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13490 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13491 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13492 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13493 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13494 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13495 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
13496 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13497 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13498 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13499 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13500 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13501 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13502 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13503 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13504 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13505 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13506 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13507 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13508 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13509 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13510 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13511 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13513 /* Sundry other built-in functions. */
13514 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
13517 /* Index I is the function declaration for mips_builtins[I], or null if the
13518 function isn't defined on this target. */
13519 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
13521 /* MODE is a vector mode whose elements have type TYPE. Return the type
13522 of the vector itself. */
13525 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
13527 static tree types
[2 * (int) MAX_MACHINE_MODE
];
13530 mode_index
= (int) mode
;
13532 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
13533 mode_index
+= MAX_MACHINE_MODE
;
13535 if (types
[mode_index
] == NULL_TREE
)
13536 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
13537 return types
[mode_index
];
13540 /* Return a type for 'const volatile void *'. */
13543 mips_build_cvpointer_type (void)
13547 if (cache
== NULL_TREE
)
13548 cache
= build_pointer_type (build_qualified_type
13550 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
13554 /* Source-level argument types. */
13555 #define MIPS_ATYPE_VOID void_type_node
13556 #define MIPS_ATYPE_INT integer_type_node
13557 #define MIPS_ATYPE_POINTER ptr_type_node
13558 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13560 /* Standard mode-based argument types. */
13561 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13562 #define MIPS_ATYPE_SI intSI_type_node
13563 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13564 #define MIPS_ATYPE_DI intDI_type_node
13565 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13566 #define MIPS_ATYPE_SF float_type_node
13567 #define MIPS_ATYPE_DF double_type_node
13569 /* Vector argument types. */
13570 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13571 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13572 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13573 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13574 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13575 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13576 #define MIPS_ATYPE_UV2SI \
13577 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13578 #define MIPS_ATYPE_UV4HI \
13579 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13580 #define MIPS_ATYPE_UV8QI \
13581 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13583 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13584 their associated MIPS_ATYPEs. */
13585 #define MIPS_FTYPE_ATYPES1(A, B) \
13586 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13588 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13589 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13591 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13592 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13594 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13595 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13598 /* Return the function type associated with function prototype TYPE. */
13601 mips_build_function_type (enum mips_function_type type
)
13603 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
13605 if (types
[(int) type
] == NULL_TREE
)
13608 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13609 case MIPS_FTYPE_NAME##NUM ARGS: \
13610 types[(int) type] \
13611 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13614 #include "config/mips/mips-ftypes.def"
13615 #undef DEF_MIPS_FTYPE
13617 gcc_unreachable ();
13620 return types
[(int) type
];
13623 /* Implement TARGET_INIT_BUILTINS. */
13626 mips_init_builtins (void)
13628 const struct mips_builtin_description
*d
;
13631 /* Iterate through all of the bdesc arrays, initializing all of the
13632 builtin functions. */
13633 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
13635 d
= &mips_builtins
[i
];
13637 mips_builtin_decls
[i
]
13638 = add_builtin_function (d
->name
,
13639 mips_build_function_type (d
->function_type
),
13640 i
, BUILT_IN_MD
, NULL
, NULL
);
13644 /* Implement TARGET_BUILTIN_DECL. */
13647 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
13649 if (code
>= ARRAY_SIZE (mips_builtins
))
13650 return error_mark_node
;
13651 return mips_builtin_decls
[code
];
13654 /* Take argument ARGNO from EXP's argument list and convert it into
13655 an expand operand. Store the operand in *OP. */
13658 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
13659 unsigned int argno
)
13664 arg
= CALL_EXPR_ARG (exp
, argno
);
13665 value
= expand_normal (arg
);
13666 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
13669 /* Expand instruction ICODE as part of a built-in function sequence.
13670 Use the first NOPS elements of OPS as the instruction's operands.
13671 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13672 instruction has no target.
13674 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13677 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
13678 struct expand_operand
*ops
, bool has_target_p
)
13680 if (!maybe_expand_insn (icode
, nops
, ops
))
13682 error ("invalid argument to built-in function");
13683 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
13685 return has_target_p
? ops
[0].value
: const0_rtx
;
13688 /* Expand a floating-point comparison for built-in function call EXP.
13689 The first NARGS arguments are the values to be compared. ICODE is
13690 the .md pattern that does the comparison and COND is the condition
13691 that is being tested. Return an rtx for the result. */
13694 mips_expand_builtin_compare_1 (enum insn_code icode
,
13695 enum mips_fp_condition cond
,
13696 tree exp
, int nargs
)
13698 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
13701 /* The instruction should have a target operand, an operand for each
13702 argument, and an operand for COND. */
13703 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
13706 create_output_operand (&ops
[opno
++], NULL_RTX
,
13707 insn_data
[(int) icode
].operand
[0].mode
);
13708 for (argno
= 0; argno
< nargs
; argno
++)
13709 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
13710 create_integer_operand (&ops
[opno
++], (int) cond
);
13711 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
13714 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13715 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13716 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13717 suggests a good place to put the result. */
13720 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
13723 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
13726 /* Map any target to operand 0. */
13729 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
13731 /* Map the arguments to the other operands. */
13732 gcc_assert (opno
+ call_expr_nargs (exp
)
13733 == insn_data
[icode
].n_generator_args
);
13734 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
13735 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
13737 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
13740 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13741 function; TYPE says which. EXP is the CALL_EXPR that calls the
13742 function, ICODE is the instruction that should be used to compare
13743 the first two arguments, and COND is the condition it should test.
13744 TARGET, if nonnull, suggests a good place to put the result. */
13747 mips_expand_builtin_movtf (enum mips_builtin_type type
,
13748 enum insn_code icode
, enum mips_fp_condition cond
,
13749 rtx target
, tree exp
)
13751 struct expand_operand ops
[4];
13754 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
13755 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
13756 if (type
== MIPS_BUILTIN_MOVT
)
13758 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
13759 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
13763 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
13764 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
13766 create_fixed_operand (&ops
[3], cmp_result
);
13767 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
13771 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13772 into TARGET otherwise. Return TARGET. */
13775 mips_builtin_branch_and_move (rtx condition
, rtx target
,
13776 rtx value_if_true
, rtx value_if_false
)
13778 rtx true_label
, done_label
;
13780 true_label
= gen_label_rtx ();
13781 done_label
= gen_label_rtx ();
13783 /* First assume that CONDITION is false. */
13784 mips_emit_move (target
, value_if_false
);
13786 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13787 emit_jump_insn (gen_condjump (condition
, true_label
));
13788 emit_jump_insn (gen_jump (done_label
));
13791 /* Fix TARGET if CONDITION is true. */
13792 emit_label (true_label
);
13793 mips_emit_move (target
, value_if_true
);
13795 emit_label (done_label
);
13799 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13800 the CALL_EXPR that calls the function, ICODE is the code of the
13801 comparison instruction, and COND is the condition it should test.
13802 TARGET, if nonnull, suggests a good place to put the boolean result. */
13805 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
13806 enum insn_code icode
, enum mips_fp_condition cond
,
13807 rtx target
, tree exp
)
13809 rtx offset
, condition
, cmp_result
;
13811 if (target
== 0 || GET_MODE (target
) != SImode
)
13812 target
= gen_reg_rtx (SImode
);
13813 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
13814 call_expr_nargs (exp
));
13816 /* If the comparison sets more than one register, we define the result
13817 to be 0 if all registers are false and -1 if all registers are true.
13818 The value of the complete result is indeterminate otherwise. */
13819 switch (builtin_type
)
13821 case MIPS_BUILTIN_CMP_ALL
:
13822 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
13823 return mips_builtin_branch_and_move (condition
, target
,
13824 const0_rtx
, const1_rtx
);
13826 case MIPS_BUILTIN_CMP_UPPER
:
13827 case MIPS_BUILTIN_CMP_LOWER
:
13828 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
13829 condition
= gen_single_cc (cmp_result
, offset
);
13830 return mips_builtin_branch_and_move (condition
, target
,
13831 const1_rtx
, const0_rtx
);
13834 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
13835 return mips_builtin_branch_and_move (condition
, target
,
13836 const1_rtx
, const0_rtx
);
13840 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13841 if nonnull, suggests a good place to put the boolean result. */
13844 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
13846 rtx condition
, cmp_result
;
13849 if (target
== 0 || GET_MODE (target
) != SImode
)
13850 target
= gen_reg_rtx (SImode
);
13852 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
13854 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
13859 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
13860 return mips_builtin_branch_and_move (condition
, target
,
13861 const1_rtx
, const0_rtx
);
13864 /* Implement TARGET_EXPAND_BUILTIN. */
13867 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13868 enum machine_mode mode
, int ignore
)
13871 unsigned int fcode
, avail
;
13872 const struct mips_builtin_description
*d
;
13874 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13875 fcode
= DECL_FUNCTION_CODE (fndecl
);
13876 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
13877 d
= &mips_builtins
[fcode
];
13878 avail
= d
->avail ();
13879 gcc_assert (avail
!= 0);
13882 error ("built-in function %qE not supported for MIPS16",
13883 DECL_NAME (fndecl
));
13884 return ignore
? const0_rtx
: CONST0_RTX (mode
);
13886 switch (d
->builtin_type
)
13888 case MIPS_BUILTIN_DIRECT
:
13889 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
13891 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
13892 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
13894 case MIPS_BUILTIN_MOVT
:
13895 case MIPS_BUILTIN_MOVF
:
13896 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
13897 d
->cond
, target
, exp
);
13899 case MIPS_BUILTIN_CMP_ANY
:
13900 case MIPS_BUILTIN_CMP_ALL
:
13901 case MIPS_BUILTIN_CMP_UPPER
:
13902 case MIPS_BUILTIN_CMP_LOWER
:
13903 case MIPS_BUILTIN_CMP_SINGLE
:
13904 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
13905 d
->cond
, target
, exp
);
13907 case MIPS_BUILTIN_BPOSGE32
:
13908 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
13910 gcc_unreachable ();
13913 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13914 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13915 struct mips16_constant
{
13916 struct mips16_constant
*next
;
13919 enum machine_mode mode
;
13922 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13923 first constant, HIGHEST_ADDRESS is the highest address that the first
13924 byte of the pool can have, and INSN_ADDRESS is the current instruction
13926 struct mips16_constant_pool
{
13927 struct mips16_constant
*first
;
13928 int highest_address
;
13932 /* Add constant VALUE to POOL and return its label. MODE is the
13933 value's mode (used for CONST_INTs, etc.). */
13936 mips16_add_constant (struct mips16_constant_pool
*pool
,
13937 rtx value
, enum machine_mode mode
)
13939 struct mips16_constant
**p
, *c
;
13940 bool first_of_size_p
;
13942 /* See whether the constant is already in the pool. If so, return the
13943 existing label, otherwise leave P pointing to the place where the
13944 constant should be added.
13946 Keep the pool sorted in increasing order of mode size so that we can
13947 reduce the number of alignments needed. */
13948 first_of_size_p
= true;
13949 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
13951 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
13952 return (*p
)->label
;
13953 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
13955 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
13956 first_of_size_p
= false;
13959 /* In the worst case, the constant needed by the earliest instruction
13960 will end up at the end of the pool. The entire pool must then be
13961 accessible from that instruction.
13963 When adding the first constant, set the pool's highest address to
13964 the address of the first out-of-range byte. Adjust this address
13965 downwards each time a new constant is added. */
13966 if (pool
->first
== 0)
13967 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13968 of the instruction with the lowest two bits clear. The base PC
13969 value for LDPC has the lowest three bits clear. Assume the worst
13970 case here; namely that the PC-relative instruction occupies the
13971 last 2 bytes in an aligned word. */
13972 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
13973 pool
->highest_address
-= GET_MODE_SIZE (mode
);
13974 if (first_of_size_p
)
13975 /* Take into account the worst possible padding due to alignment. */
13976 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
13978 /* Create a new entry. */
13979 c
= XNEW (struct mips16_constant
);
13982 c
->label
= gen_label_rtx ();
13989 /* Output constant VALUE after instruction INSN and return the last
13990 instruction emitted. MODE is the mode of the constant. */
13993 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
13995 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
13997 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
13998 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14001 if (SCALAR_FLOAT_MODE_P (mode
))
14002 return emit_insn_after (gen_consttable_float (value
), insn
);
14004 if (VECTOR_MODE_P (mode
))
14008 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14009 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14010 CONST_VECTOR_ELT (value
, i
), insn
);
14014 gcc_unreachable ();
14017 /* Dump out the constants in CONSTANTS after INSN. */
14020 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14022 struct mips16_constant
*c
, *next
;
14026 for (c
= constants
; c
!= NULL
; c
= next
)
14028 /* If necessary, increase the alignment of PC. */
14029 if (align
< GET_MODE_SIZE (c
->mode
))
14031 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14032 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14034 align
= GET_MODE_SIZE (c
->mode
);
14036 insn
= emit_label_after (c
->label
, insn
);
14037 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14043 emit_barrier_after (insn
);
14046 /* Return the length of instruction INSN. */
14049 mips16_insn_length (rtx insn
)
14053 rtx body
= PATTERN (insn
);
14054 if (GET_CODE (body
) == ADDR_VEC
)
14055 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14056 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14057 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14059 return get_attr_length (insn
);
14062 /* If *X is a symbolic constant that refers to the constant pool, add
14063 the constant to POOL and rewrite *X to use the constant's label. */
14066 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14068 rtx base
, offset
, label
;
14070 split_const (*x
, &base
, &offset
);
14071 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14073 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14074 get_pool_mode (base
));
14075 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14076 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14080 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14081 INSN is the instruction we're rewriting and POOL points to the current
14083 struct mips16_rewrite_pool_refs_info
{
14085 struct mips16_constant_pool
*pool
;
14088 /* Rewrite *X so that constant pool references refer to the constant's
14089 label instead. DATA points to a mips16_rewrite_pool_refs_info
14093 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14095 struct mips16_rewrite_pool_refs_info
*info
=
14096 (struct mips16_rewrite_pool_refs_info
*) data
;
14098 if (force_to_mem_operand (*x
, Pmode
))
14100 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14101 validate_change (info
->insn
, x
, mem
, false);
14106 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14110 /* Don't rewrite the __mips16_rdwr symbol. */
14111 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14114 if (TARGET_MIPS16_TEXT_LOADS
)
14115 mips16_rewrite_pool_constant (info
->pool
, x
);
14117 return GET_CODE (*x
) == CONST
? -1 : 0;
14120 /* Return whether CFG is used in mips_reorg. */
14123 mips_cfg_in_reorg (void)
14125 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14126 || TARGET_RELAX_PIC_CALLS
);
14129 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14130 otherwise assume that they are already split. */
14133 mips16_lay_out_constants (bool split_p
)
14135 struct mips16_constant_pool pool
;
14136 struct mips16_rewrite_pool_refs_info info
;
14139 if (!TARGET_MIPS16_PCREL_LOADS
)
14144 if (mips_cfg_in_reorg ())
14145 split_all_insns ();
14147 split_all_insns_noflow ();
14150 memset (&pool
, 0, sizeof (pool
));
14151 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14153 /* Rewrite constant pool references in INSN. */
14154 if (USEFUL_INSN_P (insn
))
14158 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14161 pool
.insn_address
+= mips16_insn_length (insn
);
14163 if (pool
.first
!= NULL
)
14165 /* If there are no natural barriers between the first user of
14166 the pool and the highest acceptable address, we'll need to
14167 create a new instruction to jump around the constant pool.
14168 In the worst case, this instruction will be 4 bytes long.
14170 If it's too late to do this transformation after INSN,
14171 do it immediately before INSN. */
14172 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14176 label
= gen_label_rtx ();
14178 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14179 JUMP_LABEL (jump
) = label
;
14180 LABEL_NUSES (label
) = 1;
14181 barrier
= emit_barrier_after (jump
);
14183 emit_label_after (label
, barrier
);
14184 pool
.insn_address
+= 4;
14187 /* See whether the constant pool is now out of range of the first
14188 user. If so, output the constants after the previous barrier.
14189 Note that any instructions between BARRIER and INSN (inclusive)
14190 will use negative offsets to refer to the pool. */
14191 if (pool
.insn_address
> pool
.highest_address
)
14193 mips16_emit_constants (pool
.first
, barrier
);
14197 else if (BARRIER_P (insn
))
14201 mips16_emit_constants (pool
.first
, get_last_insn ());
14204 /* Return true if it is worth r10k_simplify_address's while replacing
14205 an address with X. We are looking for constants, and for addresses
14206 at a known offset from the incoming stack pointer. */
14209 r10k_simplified_address_p (rtx x
)
14211 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14213 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14216 /* X is an expression that appears in INSN. Try to use the UD chains
14217 to simplify it, returning the simplified form on success and the
14218 original form otherwise. Replace the incoming value of $sp with
14219 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14222 r10k_simplify_address (rtx x
, rtx insn
)
14224 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14226 struct df_link
*defs
;
14231 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14232 if (op0
!= XEXP (x
, 0))
14233 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14234 op0
, GET_MODE (XEXP (x
, 0)));
14236 else if (BINARY_P (x
))
14238 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14239 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14240 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14241 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14243 else if (GET_CODE (x
) == LO_SUM
)
14245 /* LO_SUMs can be offset from HIGHs, if we know they won't
14246 overflow. See mips_classify_address for the rationale behind
14248 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14249 if (GET_CODE (op0
) == HIGH
)
14250 newx
= XEXP (x
, 1);
14252 else if (REG_P (x
))
14254 /* Uses are recorded by regno_reg_rtx, not X itself. */
14255 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14257 defs
= DF_REF_CHAIN (use
);
14259 /* Require a single definition. */
14260 if (defs
&& defs
->next
== NULL
)
14263 if (DF_REF_IS_ARTIFICIAL (def
))
14265 /* Replace the incoming value of $sp with
14266 virtual_incoming_args_rtx. */
14267 if (x
== stack_pointer_rtx
14268 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
14269 newx
= virtual_incoming_args_rtx
;
14271 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14274 /* Make sure that DEF_INSN is a single set of REG. */
14275 def_insn
= DF_REF_INSN (def
);
14276 if (NONJUMP_INSN_P (def_insn
))
14278 set
= single_set (def_insn
);
14279 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14281 /* Prefer to use notes, since the def-use chains
14282 are often shorter. */
14283 note
= find_reg_equal_equiv_note (def_insn
);
14285 newx
= XEXP (note
, 0);
14287 newx
= SET_SRC (set
);
14288 newx
= r10k_simplify_address (newx
, def_insn
);
14294 if (newx
&& r10k_simplified_address_p (newx
))
14299 /* Return true if ADDRESS is known to be an uncached address
14300 on R10K systems. */
14303 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14305 unsigned HOST_WIDE_INT upper
;
14307 /* Check for KSEG1. */
14308 if (address
+ 0x60000000 < 0x20000000)
14311 /* Check for uncached XKPHYS addresses. */
14312 if (Pmode
== DImode
)
14314 upper
= (address
>> 40) & 0xf9ffff;
14315 if (upper
== 0x900000 || upper
== 0xb80000)
14321 /* Return true if we can prove that an access to address X in instruction
14322 INSN would be safe from R10K speculation. This X is a general
14323 expression; it might not be a legitimate address. */
14326 r10k_safe_address_p (rtx x
, rtx insn
)
14329 HOST_WIDE_INT offset_val
;
14331 x
= r10k_simplify_address (x
, insn
);
14333 /* Check for references to the stack frame. It doesn't really matter
14334 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14335 allows us to assume that accesses to any part of the eventual frame
14336 is safe from speculation at any point in the function. */
14337 mips_split_plus (x
, &base
, &offset_val
);
14338 if (base
== virtual_incoming_args_rtx
14339 && offset_val
>= -cfun
->machine
->frame
.total_size
14340 && offset_val
< cfun
->machine
->frame
.args_size
)
14343 /* Check for uncached addresses. */
14344 if (CONST_INT_P (x
))
14345 return r10k_uncached_address_p (INTVAL (x
));
14347 /* Check for accesses to a static object. */
14348 split_const (x
, &base
, &offset
);
14349 return offset_within_block_p (base
, INTVAL (offset
));
14352 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14353 an in-range access to an automatic variable, or to an object with
14354 a link-time-constant address. */
14357 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
14359 if (offset
< 0 || offset
>= int_size_in_bytes (TREE_TYPE (expr
)))
14362 while (TREE_CODE (expr
) == COMPONENT_REF
)
14364 expr
= TREE_OPERAND (expr
, 0);
14365 if (expr
== NULL_TREE
)
14369 return DECL_P (expr
);
14372 /* A for_each_rtx callback for which DATA points to the instruction
14373 containing *X. Stop the search if we find a MEM that is not safe
14374 from R10K speculation. */
14377 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
14386 && MEM_OFFSET_KNOWN_P (mem
)
14387 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
14390 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
14396 /* A note_stores callback for which DATA points to an instruction pointer.
14397 If *DATA is nonnull, make it null if it X contains a MEM that is not
14398 safe from R10K speculation. */
14401 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14406 insn_ptr
= (rtx
*) data
;
14407 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
14408 *insn_ptr
= NULL_RTX
;
14411 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14412 Return nonzero if the call is not to a declared function. */
14415 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
14424 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
14430 /* Return true if instruction INSN needs to be protected by an R10K
14434 r10k_needs_protection_p (rtx insn
)
14437 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
14439 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
14441 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
14442 return insn
== NULL_RTX
;
14445 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
14448 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14449 edge is unconditional. */
14452 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
14457 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14458 if (!single_succ_p (e
->src
)
14459 || !TEST_BIT (protected_bbs
, e
->src
->index
)
14460 || (e
->flags
& EDGE_COMPLEX
) != 0)
14465 /* Implement -mr10k-cache-barrier= for the current function. */
14468 r10k_insert_cache_barriers (void)
14470 int *rev_post_order
;
14473 sbitmap protected_bbs
;
14474 rtx insn
, end
, unprotected_region
;
14478 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14482 /* Calculate dominators. */
14483 calculate_dominance_info (CDI_DOMINATORS
);
14485 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14486 X is protected by a cache barrier. */
14487 protected_bbs
= sbitmap_alloc (last_basic_block
);
14488 sbitmap_zero (protected_bbs
);
14490 /* Iterate over the basic blocks in reverse post-order. */
14491 rev_post_order
= XNEWVEC (int, last_basic_block
);
14492 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
14493 for (i
= 0; i
< n
; i
++)
14495 bb
= BASIC_BLOCK (rev_post_order
[i
]);
14497 /* If this block is only reached by unconditional edges, and if the
14498 source of every edge is protected, the beginning of the block is
14500 if (r10k_protected_bb_p (bb
, protected_bbs
))
14501 unprotected_region
= NULL_RTX
;
14503 unprotected_region
= pc_rtx
;
14504 end
= NEXT_INSN (BB_END (bb
));
14506 /* UNPROTECTED_REGION is:
14508 - null if we are processing a protected region,
14509 - pc_rtx if we are processing an unprotected region but have
14510 not yet found the first instruction in it
14511 - the first instruction in an unprotected region otherwise. */
14512 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
14514 if (unprotected_region
&& USEFUL_INSN_P (insn
))
14516 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
14517 /* This CACHE instruction protects the following code. */
14518 unprotected_region
= NULL_RTX
;
14521 /* See if INSN is the first instruction in this
14522 unprotected region. */
14523 if (unprotected_region
== pc_rtx
)
14524 unprotected_region
= insn
;
14526 /* See if INSN needs to be protected. If so,
14527 we must insert a cache barrier somewhere between
14528 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14529 clear which position is better performance-wise,
14530 but as a tie-breaker, we assume that it is better
14531 to allow delay slots to be back-filled where
14532 possible, and that it is better not to insert
14533 barriers in the middle of already-scheduled code.
14534 We therefore insert the barrier at the beginning
14536 if (r10k_needs_protection_p (insn
))
14538 emit_insn_before (gen_r10k_cache_barrier (),
14539 unprotected_region
);
14540 unprotected_region
= NULL_RTX
;
14546 /* The called function is not required to protect the exit path.
14547 The code that follows a call is therefore unprotected. */
14548 unprotected_region
= pc_rtx
;
14551 /* Record whether the end of this block is protected. */
14552 if (unprotected_region
== NULL_RTX
)
14553 SET_BIT (protected_bbs
, bb
->index
);
14555 XDELETEVEC (rev_post_order
);
14557 sbitmap_free (protected_bbs
);
14559 free_dominance_info (CDI_DOMINATORS
);
14562 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14563 otherwise. If INSN has two call rtx, then store the second one in
14567 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
14572 if (!CALL_P (insn
))
14575 x
= PATTERN (insn
);
14576 if (GET_CODE (x
) == PARALLEL
)
14578 /* Calls returning complex values have two CALL rtx. Look for the second
14579 one here, and return it via the SECOND_CALL arg. */
14580 x2
= XVECEXP (x
, 0, 1);
14581 if (GET_CODE (x2
) == SET
)
14583 if (GET_CODE (x2
) == CALL
)
14586 x
= XVECEXP (x
, 0, 0);
14588 if (GET_CODE (x
) == SET
)
14590 gcc_assert (GET_CODE (x
) == CALL
);
14595 /* REG is set in DEF. See if the definition is one of the ways we load a
14596 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14597 If it is, return the symbol reference of the function, otherwise return
14600 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14601 the values of source registers, otherwise treat such registers as
14602 having an unknown value. */
14605 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
14609 if (DF_REF_IS_ARTIFICIAL (def
))
14612 def_insn
= DF_REF_INSN (def
);
14613 set
= single_set (def_insn
);
14614 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
14616 rtx note
, src
, symbol
;
14618 /* First, look at REG_EQUAL/EQUIV notes. */
14619 note
= find_reg_equal_equiv_note (def_insn
);
14620 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
14621 return XEXP (note
, 0);
14623 /* For %call16 references we don't have REG_EQUAL. */
14624 src
= SET_SRC (set
);
14625 symbol
= mips_strip_unspec_call (src
);
14628 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14632 /* Follow at most one simple register copy. Such copies are
14633 interesting in cases like:
14637 locally_binding_fn (...);
14642 locally_binding_fn (...);
14644 locally_binding_fn (...);
14646 where the load of locally_binding_fn can legitimately be
14647 hoisted or shared. However, we do not expect to see complex
14648 chains of copies, so a full worklist solution to the problem
14649 would probably be overkill. */
14650 if (recurse_p
&& REG_P (src
))
14651 return mips_find_pic_call_symbol (def_insn
, src
, false);
14657 /* Find the definition of the use of REG in INSN. See if the definition
14658 is one of the ways we load a register with a symbol address for a
14659 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14660 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14661 mips_pic_call_symbol_from_set. */
14664 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
14667 struct df_link
*defs
;
14670 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
14673 defs
= DF_REF_CHAIN (use
);
14676 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
14680 /* If we have more than one definition, they need to be identical. */
14681 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
14685 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
14686 if (!rtx_equal_p (symbol
, other
))
14693 /* Replace the args_size operand of the call expression CALL with the
14694 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14697 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
14701 args_size
= XEXP (call
, 1);
14702 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
14703 gen_rtvec (2, args_size
, symbol
),
14707 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14708 if instead of the arg_size argument it contains the call attributes. If
14709 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14710 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14714 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
14716 rtx args_size
, symbol
;
14718 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
14721 args_size
= operands
[args_size_opno
];
14722 if (GET_CODE (args_size
) != UNSPEC
)
14724 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
14726 symbol
= XVECEXP (args_size
, 0, 1);
14727 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14729 operands
[args_size_opno
] = symbol
;
14733 /* Use DF to annotate PIC indirect calls with the function symbol they
14737 mips_annotate_pic_calls (void)
14743 FOR_BB_INSNS (bb
, insn
)
14745 rtx call
, reg
, symbol
, second_call
;
14748 call
= mips_call_expr_from_insn (insn
, &second_call
);
14751 gcc_assert (MEM_P (XEXP (call
, 0)));
14752 reg
= XEXP (XEXP (call
, 0), 0);
14756 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
14759 mips_annotate_pic_call_expr (call
, symbol
);
14761 mips_annotate_pic_call_expr (second_call
, symbol
);
14766 /* A temporary variable used by for_each_rtx callbacks, etc. */
14767 static rtx mips_sim_insn
;
14769 /* A structure representing the state of the processor pipeline.
14770 Used by the mips_sim_* family of functions. */
14772 /* The maximum number of instructions that can be issued in a cycle.
14773 (Caches mips_issue_rate.) */
14774 unsigned int issue_rate
;
14776 /* The current simulation time. */
14779 /* How many more instructions can be issued in the current cycle. */
14780 unsigned int insns_left
;
14782 /* LAST_SET[X].INSN is the last instruction to set register X.
14783 LAST_SET[X].TIME is the time at which that instruction was issued.
14784 INSN is null if no instruction has yet set register X. */
14788 } last_set
[FIRST_PSEUDO_REGISTER
];
14790 /* The pipeline's current DFA state. */
14794 /* Reset STATE to the initial simulation state. */
14797 mips_sim_reset (struct mips_sim
*state
)
14800 state
->insns_left
= state
->issue_rate
;
14801 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
14802 state_reset (state
->dfa_state
);
14805 /* Initialize STATE before its first use. DFA_STATE points to an
14806 allocated but uninitialized DFA state. */
14809 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
14811 state
->issue_rate
= mips_issue_rate ();
14812 state
->dfa_state
= dfa_state
;
14813 mips_sim_reset (state
);
14816 /* Advance STATE by one clock cycle. */
14819 mips_sim_next_cycle (struct mips_sim
*state
)
14822 state
->insns_left
= state
->issue_rate
;
14823 state_transition (state
->dfa_state
, 0);
14826 /* Advance simulation state STATE until instruction INSN can read
14830 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
14832 unsigned int regno
, end_regno
;
14834 end_regno
= END_REGNO (reg
);
14835 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
14836 if (state
->last_set
[regno
].insn
!= 0)
14840 t
= (state
->last_set
[regno
].time
14841 + insn_latency (state
->last_set
[regno
].insn
, insn
));
14842 while (state
->time
< t
)
14843 mips_sim_next_cycle (state
);
14847 /* A for_each_rtx callback. If *X is a register, advance simulation state
14848 DATA until mips_sim_insn can read the register's value. */
14851 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
14854 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
14858 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14861 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
14863 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
14866 /* Advance simulation state STATE until all of INSN's register
14867 dependencies are satisfied. */
14870 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
14872 mips_sim_insn
= insn
;
14873 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
14876 /* Advance simulation state STATE until the units required by
14877 instruction INSN are available. */
14880 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
14884 tmp_state
= alloca (state_size ());
14885 while (state
->insns_left
== 0
14886 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
14887 state_transition (tmp_state
, insn
) >= 0))
14888 mips_sim_next_cycle (state
);
14891 /* Advance simulation state STATE until INSN is ready to issue. */
14894 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
14896 mips_sim_wait_regs (state
, insn
);
14897 mips_sim_wait_units (state
, insn
);
14900 /* mips_sim_insn has just set X. Update the LAST_SET array
14901 in simulation state DATA. */
14904 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
14906 struct mips_sim
*state
;
14908 state
= (struct mips_sim
*) data
;
14911 unsigned int regno
, end_regno
;
14913 end_regno
= END_REGNO (x
);
14914 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
14916 state
->last_set
[regno
].insn
= mips_sim_insn
;
14917 state
->last_set
[regno
].time
= state
->time
;
14922 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14923 can issue immediately (i.e., that mips_sim_wait_insn has already
14927 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
14929 state_transition (state
->dfa_state
, insn
);
14930 state
->insns_left
--;
14932 mips_sim_insn
= insn
;
14933 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
14936 /* Simulate issuing a NOP in state STATE. */
14939 mips_sim_issue_nop (struct mips_sim
*state
)
14941 if (state
->insns_left
== 0)
14942 mips_sim_next_cycle (state
);
14943 state
->insns_left
--;
14946 /* Update simulation state STATE so that it's ready to accept the instruction
14947 after INSN. INSN should be part of the main rtl chain, not a member of a
14951 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
14953 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14955 mips_sim_issue_nop (state
);
14957 switch (GET_CODE (SEQ_BEGIN (insn
)))
14961 /* We can't predict the processor state after a call or label. */
14962 mips_sim_reset (state
);
14966 /* The delay slots of branch likely instructions are only executed
14967 when the branch is taken. Therefore, if the caller has simulated
14968 the delay slot instruction, STATE does not really reflect the state
14969 of the pipeline for the instruction after the delay slot. Also,
14970 branch likely instructions tend to incur a penalty when not taken,
14971 so there will probably be an extra delay between the branch and
14972 the instruction after the delay slot. */
14973 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
14974 mips_sim_reset (state
);
14982 /* The VR4130 pipeline issues aligned pairs of instructions together,
14983 but it stalls the second instruction if it depends on the first.
14984 In order to cut down the amount of logic required, this dependence
14985 check is not based on a full instruction decode. Instead, any non-SPECIAL
14986 instruction is assumed to modify the register specified by bits 20-16
14987 (which is usually the "rt" field).
14989 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14990 input, so we can end up with a false dependence between the branch
14991 and its delay slot. If this situation occurs in instruction INSN,
14992 try to avoid it by swapping rs and rt. */
14995 vr4130_avoid_branch_rt_conflict (rtx insn
)
14999 first
= SEQ_BEGIN (insn
);
15000 second
= SEQ_END (insn
);
15002 && NONJUMP_INSN_P (second
)
15003 && GET_CODE (PATTERN (first
)) == SET
15004 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15005 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15007 /* Check for the right kind of condition. */
15008 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15009 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15010 && REG_P (XEXP (cond
, 0))
15011 && REG_P (XEXP (cond
, 1))
15012 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15013 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15015 /* SECOND mentions the rt register but not the rs register. */
15016 rtx tmp
= XEXP (cond
, 0);
15017 XEXP (cond
, 0) = XEXP (cond
, 1);
15018 XEXP (cond
, 1) = tmp
;
15023 /* Implement -mvr4130-align. Go through each basic block and simulate the
15024 processor pipeline. If we find that a pair of instructions could execute
15025 in parallel, and the first of those instructions is not 8-byte aligned,
15026 insert a nop to make it aligned. */
15029 vr4130_align_insns (void)
15031 struct mips_sim state
;
15032 rtx insn
, subinsn
, last
, last2
, next
;
15037 /* LAST is the last instruction before INSN to have a nonzero length.
15038 LAST2 is the last such instruction before LAST. */
15042 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15045 mips_sim_init (&state
, alloca (state_size ()));
15046 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15048 unsigned int length
;
15050 next
= NEXT_INSN (insn
);
15052 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15053 This isn't really related to the alignment pass, but we do it on
15054 the fly to avoid a separate instruction walk. */
15055 vr4130_avoid_branch_rt_conflict (insn
);
15057 if (USEFUL_INSN_P (insn
))
15058 FOR_EACH_SUBINSN (subinsn
, insn
)
15060 mips_sim_wait_insn (&state
, subinsn
);
15062 /* If we want this instruction to issue in parallel with the
15063 previous one, make sure that the previous instruction is
15064 aligned. There are several reasons why this isn't worthwhile
15065 when the second instruction is a call:
15067 - Calls are less likely to be performance critical,
15068 - There's a good chance that the delay slot can execute
15069 in parallel with the call.
15070 - The return address would then be unaligned.
15072 In general, if we're going to insert a nop between instructions
15073 X and Y, it's better to insert it immediately after X. That
15074 way, if the nop makes Y aligned, it will also align any labels
15075 between X and Y. */
15076 if (state
.insns_left
!= state
.issue_rate
15077 && !CALL_P (subinsn
))
15079 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15081 /* SUBINSN is the first instruction in INSN and INSN is
15082 aligned. We want to align the previous instruction
15083 instead, so insert a nop between LAST2 and LAST.
15085 Note that LAST could be either a single instruction
15086 or a branch with a delay slot. In the latter case,
15087 LAST, like INSN, is already aligned, but the delay
15088 slot must have some extra delay that stops it from
15089 issuing at the same time as the branch. We therefore
15090 insert a nop before the branch in order to align its
15092 emit_insn_after (gen_nop (), last2
);
15095 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15097 /* SUBINSN is the delay slot of INSN, but INSN is
15098 currently unaligned. Insert a nop between
15099 LAST and INSN to align it. */
15100 emit_insn_after (gen_nop (), last
);
15104 mips_sim_issue_insn (&state
, subinsn
);
15106 mips_sim_finish_insn (&state
, insn
);
15108 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15109 length
= get_attr_length (insn
);
15112 /* If the instruction is an asm statement or multi-instruction
15113 mips.md patern, the length is only an estimate. Insert an
15114 8 byte alignment after it so that the following instructions
15115 can be handled correctly. */
15116 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15117 && (recog_memoized (insn
) < 0 || length
>= 8))
15119 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15120 next
= NEXT_INSN (next
);
15121 mips_sim_next_cycle (&state
);
15124 else if (length
& 4)
15125 aligned_p
= !aligned_p
;
15130 /* See whether INSN is an aligned label. */
15131 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15137 /* This structure records that the current function has a LO_SUM
15138 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15139 the largest offset applied to BASE by all such LO_SUMs. */
15140 struct mips_lo_sum_offset
{
15142 HOST_WIDE_INT offset
;
15145 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15148 mips_hash_base (rtx base
)
15150 int do_not_record_p
;
15152 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15155 /* Hash-table callbacks for mips_lo_sum_offsets. */
15158 mips_lo_sum_offset_hash (const void *entry
)
15160 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
15164 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
15166 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
15167 (const_rtx
) value
);
15170 /* Look up symbolic constant X in HTAB, which is a hash table of
15171 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15172 paired with a recorded LO_SUM, otherwise record X in the table. */
15175 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
15179 struct mips_lo_sum_offset
*entry
;
15181 /* Split X into a base and offset. */
15182 split_const (x
, &base
, &offset
);
15183 if (UNSPEC_ADDRESS_P (base
))
15184 base
= UNSPEC_ADDRESS (base
);
15186 /* Look up the base in the hash table. */
15187 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
15191 entry
= (struct mips_lo_sum_offset
*) *slot
;
15192 if (option
== INSERT
)
15196 entry
= XNEW (struct mips_lo_sum_offset
);
15197 entry
->base
= base
;
15198 entry
->offset
= INTVAL (offset
);
15203 if (INTVAL (offset
) > entry
->offset
)
15204 entry
->offset
= INTVAL (offset
);
15207 return INTVAL (offset
) <= entry
->offset
;
15210 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15211 Record every LO_SUM in *LOC. */
15214 mips_record_lo_sum (rtx
*loc
, void *data
)
15216 if (GET_CODE (*loc
) == LO_SUM
)
15217 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
15221 /* Return true if INSN is a SET of an orphaned high-part relocation.
15222 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15223 LO_SUMs in the current function. */
15226 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
15228 enum mips_symbol_type type
;
15231 set
= single_set (insn
);
15234 /* Check for %his. */
15236 if (GET_CODE (x
) == HIGH
15237 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
15238 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
15240 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15241 if (GET_CODE (x
) == UNSPEC
15242 && XINT (x
, 1) == UNSPEC_LOAD_GOT
15243 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
15244 SYMBOL_CONTEXT_LEA
, &type
)
15245 && type
== SYMBOL_GOTOFF_PAGE
)
15246 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
15251 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15252 INSN and a previous instruction, avoid it by inserting nops after
15255 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15256 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15257 before using the value of that register. *HILO_DELAY counts the
15258 number of instructions since the last hilo hazard (that is,
15259 the number of instructions since the last MFLO or MFHI).
15261 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15262 for the next instruction.
15264 LO_REG is an rtx for the LO register, used in dependence checking. */
15267 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
15268 rtx
*delayed_reg
, rtx lo_reg
)
15273 pattern
= PATTERN (insn
);
15275 /* Do not put the whole function in .set noreorder if it contains
15276 an asm statement. We don't know whether there will be hazards
15277 between the asm statement and the gcc-generated code. */
15278 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
15279 cfun
->machine
->all_noreorder_p
= false;
15281 /* Ignore zero-length instructions (barriers and the like). */
15282 ninsns
= get_attr_length (insn
) / 4;
15286 /* Work out how many nops are needed. Note that we only care about
15287 registers that are explicitly mentioned in the instruction's pattern.
15288 It doesn't matter that calls use the argument registers or that they
15289 clobber hi and lo. */
15290 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
15291 nops
= 2 - *hilo_delay
;
15292 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
15297 /* Insert the nops between this instruction and the previous one.
15298 Each new nop takes us further from the last hilo hazard. */
15299 *hilo_delay
+= nops
;
15301 emit_insn_after (gen_hazard_nop (), after
);
15303 /* Set up the state for the next instruction. */
15304 *hilo_delay
+= ninsns
;
15306 if (INSN_CODE (insn
) >= 0)
15307 switch (get_attr_hazard (insn
))
15317 set
= single_set (insn
);
15319 *delayed_reg
= SET_DEST (set
);
15324 /* Go through the instruction stream and insert nops where necessary.
15325 Also delete any high-part relocations whose partnering low parts
15326 are now all dead. See if the whole function can then be put into
15327 .set noreorder and .set nomacro. */
15330 mips_reorg_process_insns (void)
15332 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
15336 /* Force all instructions to be split into their final form. */
15337 split_all_insns_noflow ();
15339 /* Recalculate instruction lengths without taking nops into account. */
15340 cfun
->machine
->ignore_hazard_length_p
= true;
15341 shorten_branches (get_insns ());
15343 cfun
->machine
->all_noreorder_p
= true;
15345 /* We don't track MIPS16 PC-relative offsets closely enough to make
15346 a good job of "set .noreorder" code in MIPS16 mode. */
15348 cfun
->machine
->all_noreorder_p
= false;
15350 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15351 if (!TARGET_EXPLICIT_RELOCS
)
15352 cfun
->machine
->all_noreorder_p
= false;
15354 /* Profiled functions can't be all noreorder because the profiler
15355 support uses assembler macros. */
15357 cfun
->machine
->all_noreorder_p
= false;
15359 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15360 because we rely on the assembler to work around some errata. */
15361 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
)
15362 cfun
->machine
->all_noreorder_p
= false;
15364 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15365 MFHI instructions. Note that we avoid using MFLO and MFHI if
15366 the VR4130 MACC and DMACC instructions are available instead;
15367 see the *mfhilo_{si,di}_macc patterns. */
15368 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
15369 cfun
->machine
->all_noreorder_p
= false;
15371 htab
= htab_create (37, mips_lo_sum_offset_hash
,
15372 mips_lo_sum_offset_eq
, free
);
15374 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15375 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
15376 FOR_EACH_SUBINSN (subinsn
, insn
)
15377 if (USEFUL_INSN_P (subinsn
))
15378 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
15383 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
15385 /* Make a second pass over the instructions. Delete orphaned
15386 high-part relocations or turn them into NOPs. Avoid hazards
15387 by inserting NOPs. */
15388 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
15390 next_insn
= NEXT_INSN (insn
);
15391 if (USEFUL_INSN_P (insn
))
15393 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
15395 /* If we find an orphaned high-part relocation in a delay
15396 slot, it's easier to turn that instruction into a NOP than
15397 to delete it. The delay slot will be a NOP either way. */
15398 FOR_EACH_SUBINSN (subinsn
, insn
)
15399 if (INSN_P (subinsn
))
15401 if (mips_orphaned_high_part_p (htab
, subinsn
))
15403 PATTERN (subinsn
) = gen_nop ();
15404 INSN_CODE (subinsn
) = CODE_FOR_nop
;
15406 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
15407 &delayed_reg
, lo_reg
);
15413 /* INSN is a single instruction. Delete it if it's an
15414 orphaned high-part relocation. */
15415 if (mips_orphaned_high_part_p (htab
, insn
))
15416 delete_insn (insn
);
15417 /* Also delete cache barriers if the last instruction
15418 was an annulled branch. INSN will not be speculatively
15420 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
15422 && JUMP_P (SEQ_BEGIN (last_insn
))
15423 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
15424 delete_insn (insn
);
15427 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
15428 &delayed_reg
, lo_reg
);
15435 htab_delete (htab
);
15438 /* If we are using a GOT, but have not decided to use a global pointer yet,
15439 see whether we need one to implement long branches. Convert the ghost
15440 global-pointer instructions into real ones if so. */
15443 mips_expand_ghost_gp_insns (void)
15448 /* Quick exit if we already know that we will or won't need a
15450 if (!TARGET_USE_GOT
15451 || cfun
->machine
->global_pointer
== INVALID_REGNUM
15452 || mips_must_initialize_gp_p ())
15455 shorten_branches (get_insns ());
15457 /* Look for a branch that is longer than normal. The normal length for
15458 non-MIPS16 branches is 8, because the length includes the delay slot.
15459 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15460 but they have no delay slot. */
15461 normal_length
= (TARGET_MIPS16
? 4 : 8);
15462 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15464 && USEFUL_INSN_P (insn
)
15465 && get_attr_length (insn
) > normal_length
)
15468 if (insn
== NULL_RTX
)
15471 /* We've now established that we need $gp. */
15472 cfun
->machine
->must_initialize_gp_p
= true;
15473 split_all_insns_noflow ();
15478 /* Subroutine of mips_reorg to manage passes that require DF. */
15481 mips_df_reorg (void)
15483 /* Create def-use chains. */
15484 df_set_flags (DF_EQ_NOTES
);
15485 df_chain_add_problem (DF_UD_CHAIN
);
15488 if (TARGET_RELAX_PIC_CALLS
)
15489 mips_annotate_pic_calls ();
15491 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
15492 r10k_insert_cache_barriers ();
15494 df_finish_pass (false);
15497 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
15498 called very late in mips_reorg, but the caller is required to run
15499 mips16_lay_out_constants on the result. */
15502 mips16_load_branch_target (rtx dest
, rtx src
)
15504 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
15508 if (mips_cfun_has_cprestore_slot_p ())
15509 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
15511 mips_emit_move (dest
, pic_offset_table_rtx
);
15512 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
15513 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
15514 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
15515 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
15516 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
15517 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
15521 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
15522 mips_emit_move (dest
, src
);
15526 /* If we're compiling a MIPS16 function, look for and split any long branches.
15527 This must be called after all other instruction modifications in
15531 mips16_split_long_branches (void)
15533 bool something_changed
;
15535 if (!TARGET_MIPS16
)
15538 /* Loop until the alignments for all targets are sufficient. */
15543 shorten_branches (get_insns ());
15544 something_changed
= false;
15545 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15547 && USEFUL_INSN_P (insn
)
15548 && get_attr_length (insn
) > 8)
15550 rtx old_label
, new_label
, temp
, saved_temp
;
15551 rtx target
, jump
, jump_sequence
;
15555 /* Free up a MIPS16 register by saving it in $1. */
15556 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
15557 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
15558 emit_move_insn (saved_temp
, temp
);
15560 /* Load the branch target into TEMP. */
15561 old_label
= JUMP_LABEL (insn
);
15562 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
15563 mips16_load_branch_target (temp
, target
);
15565 /* Jump to the target and restore the register's
15567 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
15568 (temp
, temp
, saved_temp
)));
15569 JUMP_LABEL (jump
) = old_label
;
15570 LABEL_NUSES (old_label
)++;
15572 /* Rewrite any symbolic references that are supposed to use
15573 a PC-relative constant pool. */
15574 mips16_lay_out_constants (false);
15576 if (simplejump_p (insn
))
15577 /* We're going to replace INSN with a longer form. */
15578 new_label
= NULL_RTX
;
15581 /* Create a branch-around label for the original
15583 new_label
= gen_label_rtx ();
15584 emit_label (new_label
);
15587 jump_sequence
= get_insns ();
15590 emit_insn_after (jump_sequence
, insn
);
15592 invert_jump (insn
, new_label
, false);
15594 delete_insn (insn
);
15595 something_changed
= true;
15598 while (something_changed
);
15601 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15606 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15607 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15608 to date if the CFG is available. */
15609 if (mips_cfg_in_reorg ())
15610 compute_bb_for_insn ();
15611 mips16_lay_out_constants (true);
15612 if (mips_cfg_in_reorg ())
15615 free_bb_for_insn ();
15618 if (optimize
> 0 && flag_delayed_branch
)
15619 dbr_schedule (get_insns ());
15620 mips_reorg_process_insns ();
15622 && TARGET_EXPLICIT_RELOCS
15624 && TARGET_VR4130_ALIGN
)
15625 vr4130_align_insns ();
15626 if (mips_expand_ghost_gp_insns ())
15627 /* The expansion could invalidate some of the VR4130 alignment
15628 optimizations, but this should be an extremely rare case anyhow. */
15629 mips_reorg_process_insns ();
15630 mips16_split_long_branches ();
15633 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15634 in order to avoid duplicating too much logic from elsewhere. */
15637 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
15638 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
15641 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
15642 bool use_sibcall_p
;
15644 /* Pretend to be a post-reload pass while generating rtl. */
15645 reload_completed
= 1;
15647 /* Mark the end of the (empty) prologue. */
15648 emit_note (NOTE_INSN_PROLOGUE_END
);
15650 /* Determine if we can use a sibcall to call FUNCTION directly. */
15651 fnaddr
= XEXP (DECL_RTL (function
), 0);
15652 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
15653 && const_call_insn_operand (fnaddr
, Pmode
));
15655 /* Determine if we need to load FNADDR from the GOT. */
15657 && (mips_got_symbol_type_p
15658 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
15660 /* Pick a global pointer. Use a call-clobbered register if
15661 TARGET_CALL_SAVED_GP. */
15662 cfun
->machine
->global_pointer
15663 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
15664 cfun
->machine
->must_initialize_gp_p
= true;
15665 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
15667 /* Set up the global pointer for n32 or n64 abicalls. */
15668 mips_emit_loadgp ();
15671 /* We need two temporary registers in some cases. */
15672 temp1
= gen_rtx_REG (Pmode
, 2);
15673 temp2
= gen_rtx_REG (Pmode
, 3);
15675 /* Find out which register contains the "this" pointer. */
15676 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
15677 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
15679 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
15681 /* Add DELTA to THIS_RTX. */
15684 rtx offset
= GEN_INT (delta
);
15685 if (!SMALL_OPERAND (delta
))
15687 mips_emit_move (temp1
, offset
);
15690 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
15693 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15694 if (vcall_offset
!= 0)
15698 /* Set TEMP1 to *THIS_RTX. */
15699 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
15701 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15702 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
15704 /* Load the offset and add it to THIS_RTX. */
15705 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
15706 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
15709 /* Jump to the target function. Use a sibcall if direct jumps are
15710 allowed, otherwise load the address into a register first. */
15713 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
15714 SIBLING_CALL_P (insn
) = 1;
15718 /* This is messy. GAS treats "la $25,foo" as part of a call
15719 sequence and may allow a global "foo" to be lazily bound.
15720 The general move patterns therefore reject this combination.
15722 In this context, lazy binding would actually be OK
15723 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15724 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15725 We must therefore load the address via a temporary
15726 register if mips_dangerous_for_la25_p.
15728 If we jump to the temporary register rather than $25,
15729 the assembler can use the move insn to fill the jump's
15732 We can use the same technique for MIPS16 code, where $25
15733 is not a valid JR register. */
15734 if (TARGET_USE_PIC_FN_ADDR_REG
15736 && !mips_dangerous_for_la25_p (fnaddr
))
15737 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
15738 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
15740 if (TARGET_USE_PIC_FN_ADDR_REG
15741 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
15742 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
15743 emit_jump_insn (gen_indirect_jump (temp1
));
15746 /* Run just enough of rest_of_compilation. This sequence was
15747 "borrowed" from alpha.c. */
15748 insn
= get_insns ();
15749 insn_locators_alloc ();
15750 split_all_insns_noflow ();
15751 mips16_lay_out_constants (true);
15752 shorten_branches (insn
);
15753 final_start_function (insn
, file
, 1);
15754 final (insn
, file
, 1);
15755 final_end_function ();
15757 /* Clean up the vars set above. Note that final_end_function resets
15758 the global pointer for us. */
15759 reload_completed
= 0;
15762 /* The last argument passed to mips_set_mips16_mode, or negative if the
15763 function hasn't been called yet. */
15764 static int was_mips16_p
= -1;
15766 /* Set up the target-dependent global state so that it matches the
15767 current function's ISA mode. */
15770 mips_set_mips16_mode (int mips16_p
)
15772 if (mips16_p
== was_mips16_p
)
15775 /* Restore base settings of various flags. */
15776 target_flags
= mips_base_target_flags
;
15777 flag_schedule_insns
= mips_base_schedule_insns
;
15778 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
15779 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
15780 align_loops
= mips_base_align_loops
;
15781 align_jumps
= mips_base_align_jumps
;
15782 align_functions
= mips_base_align_functions
;
15786 /* Switch to MIPS16 mode. */
15787 target_flags
|= MASK_MIPS16
;
15789 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
15790 target_flags
&= ~MASK_SYNCI
;
15792 /* Don't run the scheduler before reload, since it tends to
15793 increase register pressure. */
15794 flag_schedule_insns
= 0;
15796 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15797 the whole function to be in a single section. */
15798 flag_reorder_blocks_and_partition
= 0;
15800 /* Don't move loop invariants, because it tends to increase
15801 register pressure. It also introduces an extra move in cases
15802 where the constant is the first operand in a two-operand binary
15803 instruction, or when it forms a register argument to a functon
15805 flag_move_loop_invariants
= 0;
15807 target_flags
|= MASK_EXPLICIT_RELOCS
;
15809 /* Experiments suggest we get the best overall section-anchor
15810 results from using the range of an unextended LW or SW. Code
15811 that makes heavy use of byte or short accesses can do better
15812 with ranges of 0...31 and 0...63 respectively, but most code is
15813 sensitive to the range of LW and SW instead. */
15814 targetm
.min_anchor_offset
= 0;
15815 targetm
.max_anchor_offset
= 127;
15817 targetm
.const_anchor
= 0;
15819 /* MIPS16 has no BAL instruction. */
15820 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15822 /* The R4000 errata don't apply to any known MIPS16 cores.
15823 It's simpler to make the R4000 fixes and MIPS16 mode
15824 mutually exclusive. */
15825 target_flags
&= ~MASK_FIX_R4000
;
15827 if (flag_pic
&& !TARGET_OLDABI
)
15828 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15831 sorry ("MIPS16 -mxgot code");
15833 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
15834 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15838 /* Switch to normal (non-MIPS16) mode. */
15839 target_flags
&= ~MASK_MIPS16
;
15841 /* Provide default values for align_* for 64-bit targets. */
15844 if (align_loops
== 0)
15846 if (align_jumps
== 0)
15848 if (align_functions
== 0)
15849 align_functions
= 8;
15852 targetm
.min_anchor_offset
= -32768;
15853 targetm
.max_anchor_offset
= 32767;
15855 targetm
.const_anchor
= 0x8000;
15858 /* (Re)initialize MIPS target internals for new ISA. */
15859 mips_init_relocs ();
15863 if (!mips16_globals
)
15864 mips16_globals
= save_target_globals ();
15866 restore_target_globals (mips16_globals
);
15869 restore_target_globals (&default_target_globals
);
15871 was_mips16_p
= mips16_p
;
15874 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15875 function should use the MIPS16 ISA and switch modes accordingly. */
15878 mips_set_current_function (tree fndecl
)
15880 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
15883 /* Allocate a chunk of memory for per-function machine-dependent data. */
15885 static struct machine_function
*
15886 mips_init_machine_status (void)
15888 return ggc_alloc_cleared_machine_function ();
15891 /* Return the processor associated with the given ISA level, or null
15892 if the ISA isn't valid. */
15894 static const struct mips_cpu_info
*
15895 mips_cpu_info_from_isa (int isa
)
15899 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15900 if (mips_cpu_info_table
[i
].isa
== isa
)
15901 return mips_cpu_info_table
+ i
;
15906 /* Return a mips_cpu_info entry determined by an option valued
15909 static const struct mips_cpu_info
*
15910 mips_cpu_info_from_opt (int opt
)
15914 case MIPS_ARCH_OPTION_FROM_ABI
:
15915 /* 'from-abi' selects the most compatible architecture for the
15916 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15917 ABIs. For the EABIs, we have to decide whether we're using
15918 the 32-bit or 64-bit version. */
15919 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
15920 : ABI_NEEDS_64BIT_REGS
? 3
15921 : (TARGET_64BIT
? 3 : 1));
15923 case MIPS_ARCH_OPTION_NATIVE
:
15924 gcc_unreachable ();
15927 return &mips_cpu_info_table
[opt
];
15931 /* Return a default mips_cpu_info entry, given that no -march= option
15932 was explicitly specified. */
15934 static const struct mips_cpu_info
*
15935 mips_default_arch (void)
15937 #if defined (MIPS_CPU_STRING_DEFAULT)
15939 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15940 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
15941 return mips_cpu_info_table
+ i
;
15942 gcc_unreachable ();
15943 #elif defined (MIPS_ISA_DEFAULT)
15944 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
15946 /* 'from-abi' makes a good default: you get whatever the ABI
15948 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
15952 /* Set up globals to generate code for the ISA or processor
15953 described by INFO. */
15956 mips_set_architecture (const struct mips_cpu_info
*info
)
15960 mips_arch_info
= info
;
15961 mips_arch
= info
->cpu
;
15962 mips_isa
= info
->isa
;
15966 /* Likewise for tuning. */
15969 mips_set_tune (const struct mips_cpu_info
*info
)
15973 mips_tune_info
= info
;
15974 mips_tune
= info
->cpu
;
15978 /* Implement TARGET_OPTION_OVERRIDE. */
15981 mips_option_override (void)
15983 int i
, start
, regno
, mode
;
15985 if (global_options_set
.x_mips_isa_option
)
15986 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
15988 /* Process flags as though we were generating non-MIPS16 code. */
15989 mips_base_mips16
= TARGET_MIPS16
;
15990 target_flags
&= ~MASK_MIPS16
;
15992 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15993 SUBTARGET_OVERRIDE_OPTIONS
;
15996 /* -mno-float overrides -mhard-float and -msoft-float. */
15997 if (TARGET_NO_FLOAT
)
15999 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16000 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16003 if (TARGET_FLIP_MIPS16
)
16004 TARGET_INTERLINK_MIPS16
= 1;
16006 /* Set the small data limit. */
16007 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16009 : MIPS_DEFAULT_GVALUE
);
16011 /* The following code determines the architecture and register size.
16012 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16013 The GAS and GCC code should be kept in sync as much as possible. */
16015 if (global_options_set
.x_mips_arch_option
)
16016 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16018 if (mips_isa_option_info
!= 0)
16020 if (mips_arch_info
== 0)
16021 mips_set_architecture (mips_isa_option_info
);
16022 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16023 error ("%<-%s%> conflicts with the other architecture options, "
16024 "which specify a %s processor",
16025 mips_isa_option_info
->name
,
16026 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16029 if (mips_arch_info
== 0)
16030 mips_set_architecture (mips_default_arch ());
16032 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16033 error ("%<-march=%s%> is not compatible with the selected ABI",
16034 mips_arch_info
->name
);
16036 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16037 if (global_options_set
.x_mips_tune_option
)
16038 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16040 if (mips_tune_info
== 0)
16041 mips_set_tune (mips_arch_info
);
16043 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16045 /* The user specified the size of the integer registers. Make sure
16046 it agrees with the ABI and ISA. */
16047 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16048 error ("%<-mgp64%> used with a 32-bit processor");
16049 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16050 error ("%<-mgp32%> used with a 64-bit ABI");
16051 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16052 error ("%<-mgp64%> used with a 32-bit ABI");
16056 /* Infer the integer register size from the ABI and processor.
16057 Restrict ourselves to 32-bit registers if that's all the
16058 processor has, or if the ABI cannot handle 64-bit registers. */
16059 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16060 target_flags
&= ~MASK_64BIT
;
16062 target_flags
|= MASK_64BIT
;
16065 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16067 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16068 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16069 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16070 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16071 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16073 if (!ISA_HAS_MXHC1
)
16074 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16075 " the target supports the mfhc1 and mthc1 instructions");
16076 else if (mips_abi
!= ABI_32
)
16077 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16083 /* -msingle-float selects 32-bit float registers. Otherwise the
16084 float registers should be the same size as the integer ones. */
16085 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16086 target_flags
|= MASK_FLOAT64
;
16088 target_flags
&= ~MASK_FLOAT64
;
16091 /* End of code shared with GAS. */
16093 /* If a -mlong* option was given, check that it matches the ABI,
16094 otherwise infer the -mlong* setting from the other options. */
16095 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16099 if (mips_abi
== ABI_N32
)
16100 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16101 else if (mips_abi
== ABI_32
)
16102 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16103 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16104 /* We have traditionally allowed non-abicalls code to use
16105 an LP64 form of o64. However, it would take a bit more
16106 effort to support the combination of 32-bit GOT entries
16107 and 64-bit pointers, so we treat the abicalls case as
16109 error ("the combination of %qs and %qs is incompatible with %qs",
16110 "-mabi=o64", "-mabicalls", "-mlong64");
16114 if (mips_abi
== ABI_64
)
16115 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16120 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16121 target_flags
|= MASK_LONG64
;
16123 target_flags
&= ~MASK_LONG64
;
16126 if (!TARGET_OLDABI
)
16127 flag_pcc_struct_return
= 0;
16129 /* Decide which rtx_costs structure to use. */
16131 mips_cost
= &mips_rtx_cost_optimize_size
;
16133 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16135 /* If the user hasn't specified a branch cost, use the processor's
16137 if (mips_branch_cost
== 0)
16138 mips_branch_cost
= mips_cost
->branch_cost
;
16140 /* If neither -mbranch-likely nor -mno-branch-likely was given
16141 on the command line, set MASK_BRANCHLIKELY based on the target
16142 architecture and tuning flags. Annulled delay slots are a
16143 size win, so we only consider the processor-specific tuning
16144 for !optimize_size. */
16145 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
16147 if (ISA_HAS_BRANCHLIKELY
16149 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
16150 target_flags
|= MASK_BRANCHLIKELY
;
16152 target_flags
&= ~MASK_BRANCHLIKELY
;
16154 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
16155 warning (0, "the %qs architecture does not support branch-likely"
16156 " instructions", mips_arch_info
->name
);
16158 /* The effect of -mabicalls isn't defined for the EABI. */
16159 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
16161 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16162 target_flags
&= ~MASK_ABICALLS
;
16165 /* PIC requires -mabicalls. */
16168 if (mips_abi
== ABI_EABI
)
16169 error ("cannot generate position-independent code for %qs",
16171 else if (!TARGET_ABICALLS
)
16172 error ("position-independent code requires %qs", "-mabicalls");
16175 if (TARGET_ABICALLS_PIC2
)
16176 /* We need to set flag_pic for executables as well as DSOs
16177 because we may reference symbols that are not defined in
16178 the final executable. (MIPS does not use things like
16179 copy relocs, for example.)
16181 There is a body of code that uses __PIC__ to distinguish
16182 between -mabicalls and -mno-abicalls code. The non-__PIC__
16183 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16184 long as any indirect jumps use $25. */
16187 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16188 faster code, but at the expense of more nops. Enable it at -O3 and
16190 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
16191 target_flags
|= MASK_VR4130_ALIGN
;
16193 /* Prefer a call to memcpy over inline code when optimizing for size,
16194 though see MOVE_RATIO in mips.h. */
16195 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
16196 target_flags
|= MASK_MEMCPY
;
16198 /* If we have a nonzero small-data limit, check that the -mgpopt
16199 setting is consistent with the other target flags. */
16200 if (mips_small_data_threshold
> 0)
16204 if (!TARGET_EXPLICIT_RELOCS
)
16205 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16207 TARGET_LOCAL_SDATA
= false;
16208 TARGET_EXTERN_SDATA
= false;
16212 if (TARGET_VXWORKS_RTP
)
16213 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16215 if (TARGET_ABICALLS
)
16216 warning (0, "cannot use small-data accesses for %qs",
16221 /* Make sure that the user didn't turn off paired single support when
16222 MIPS-3D support is requested. */
16224 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
16225 && !TARGET_PAIRED_SINGLE_FLOAT
)
16226 error ("%<-mips3d%> requires %<-mpaired-single%>");
16228 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16230 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
16232 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16233 and TARGET_HARD_FLOAT_ABI are both true. */
16234 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
16235 error ("%qs must be used with %qs",
16236 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
16237 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
16239 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16241 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
16242 warning (0, "the %qs architecture does not support paired-single"
16243 " instructions", mips_arch_info
->name
);
16245 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
16246 && !TARGET_CACHE_BUILTIN
)
16248 error ("%qs requires a target that provides the %qs instruction",
16249 "-mr10k-cache-barrier", "cache");
16250 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
16253 /* If TARGET_DSPR2, enable MASK_DSP. */
16255 target_flags
|= MASK_DSP
;
16257 /* .eh_frame addresses should be the same width as a C pointer.
16258 Most MIPS ABIs support only one pointer size, so the assembler
16259 will usually know exactly how big an .eh_frame address is.
16261 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16262 originally defined to use 64-bit pointers (i.e. it is LP64), and
16263 this is still the default mode. However, we also support an n32-like
16264 ILP32 mode, which is selected by -mlong32. The problem is that the
16265 assembler has traditionally not had an -mlong option, so it has
16266 traditionally not known whether we're using the ILP32 or LP64 form.
16268 As it happens, gas versions up to and including 2.19 use _32-bit_
16269 addresses for EABI64 .cfi_* directives. This is wrong for the
16270 default LP64 mode, so we can't use the directives by default.
16271 Moreover, since gas's current behavior is at odds with gcc's
16272 default behavior, it seems unwise to rely on future versions
16273 of gas behaving the same way. We therefore avoid using .cfi
16274 directives for -mlong32 as well. */
16275 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
16276 flag_dwarf2_cfi_asm
= 0;
16278 /* .cfi_* directives generate a read-only section, so fall back on
16279 manual .eh_frame creation if we need the section to be writable. */
16280 if (TARGET_WRITABLE_EH_FRAME
)
16281 flag_dwarf2_cfi_asm
= 0;
16283 mips_init_print_operand_punct ();
16285 /* Set up array to map GCC register number to debug register number.
16286 Ignore the special purpose register numbers. */
16288 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
16290 mips_dbx_regno
[i
] = INVALID_REGNUM
;
16291 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
16292 mips_dwarf_regno
[i
] = i
;
16294 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
16297 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
16298 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
16299 mips_dbx_regno
[i
] = i
+ start
;
16301 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
16302 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
16303 mips_dbx_regno
[i
] = i
+ start
;
16305 /* Accumulator debug registers use big-endian ordering. */
16306 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
16307 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
16308 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
16309 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
16310 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
16312 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
16313 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
16316 /* Set up mips_hard_regno_mode_ok. */
16317 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
16318 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
16319 mips_hard_regno_mode_ok
[mode
][regno
]
16320 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
16322 /* Function to allocate machine-dependent function status. */
16323 init_machine_status
= &mips_init_machine_status
;
16325 /* Default to working around R4000 errata only if the processor
16326 was selected explicitly. */
16327 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
16328 && strcmp (mips_arch_info
->name
, "r4000") == 0)
16329 target_flags
|= MASK_FIX_R4000
;
16331 /* Default to working around R4400 errata only if the processor
16332 was selected explicitly. */
16333 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
16334 && strcmp (mips_arch_info
->name
, "r4400") == 0)
16335 target_flags
|= MASK_FIX_R4400
;
16337 /* Default to working around R10000 errata only if the processor
16338 was selected explicitly. */
16339 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
16340 && strcmp (mips_arch_info
->name
, "r10000") == 0)
16341 target_flags
|= MASK_FIX_R10000
;
16343 /* Make sure that branch-likely instructions available when using
16344 -mfix-r10000. The instructions are not available if either:
16346 1. -mno-branch-likely was passed.
16347 2. The selected ISA does not support branch-likely and
16348 the command line does not include -mbranch-likely. */
16349 if (TARGET_FIX_R10000
16350 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
16351 ? !ISA_HAS_BRANCHLIKELY
16352 : !TARGET_BRANCHLIKELY
))
16353 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16355 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
16357 warning (0, "the %qs architecture does not support the synci "
16358 "instruction", mips_arch_info
->name
);
16359 target_flags
&= ~MASK_SYNCI
;
16362 /* Only optimize PIC indirect calls if they are actually required. */
16363 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
16364 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16366 /* Save base state of options. */
16367 mips_base_target_flags
= target_flags
;
16368 mips_base_schedule_insns
= flag_schedule_insns
;
16369 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
16370 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
16371 mips_base_align_loops
= align_loops
;
16372 mips_base_align_jumps
= align_jumps
;
16373 mips_base_align_functions
= align_functions
;
16375 /* Now select the ISA mode.
16377 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16378 MIPS16 mode afterwards if need be. */
16379 mips_set_mips16_mode (false);
16382 /* Swap the register information for registers I and I + 1, which
16383 currently have the wrong endianness. Note that the registers'
16384 fixedness and call-clobberedness might have been set on the
16388 mips_swap_registers (unsigned int i
)
16393 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16394 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16396 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
16397 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
16398 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
16399 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
16405 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16408 mips_conditional_register_usage (void)
16413 /* These DSP control register fields are global. */
16414 global_regs
[CCDSP_PO_REGNUM
] = 1;
16415 global_regs
[CCDSP_SC_REGNUM
] = 1;
16418 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16419 reg_class_contents
[(int) DSP_ACC_REGS
]);
16421 if (!TARGET_HARD_FLOAT
)
16423 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16424 reg_class_contents
[(int) FP_REGS
]);
16425 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16426 reg_class_contents
[(int) ST_REGS
]);
16428 else if (!ISA_HAS_8CC
)
16430 /* We only have a single condition-code register. We implement
16431 this by fixing all the condition-code registers and generating
16432 RTL that refers directly to ST_REG_FIRST. */
16433 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16434 reg_class_contents
[(int) ST_REGS
]);
16435 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
16436 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
16440 /* In MIPS16 mode, we permit the $t temporary registers to be used
16441 for reload. We prohibit the unused $s registers, since they
16442 are call-saved, and saving them via a MIPS16 register would
16443 probably waste more time than just reloading the value. */
16444 fixed_regs
[18] = call_used_regs
[18] = 1;
16445 fixed_regs
[19] = call_used_regs
[19] = 1;
16446 fixed_regs
[20] = call_used_regs
[20] = 1;
16447 fixed_regs
[21] = call_used_regs
[21] = 1;
16448 fixed_regs
[22] = call_used_regs
[22] = 1;
16449 fixed_regs
[23] = call_used_regs
[23] = 1;
16450 fixed_regs
[26] = call_used_regs
[26] = 1;
16451 fixed_regs
[27] = call_used_regs
[27] = 1;
16452 fixed_regs
[30] = call_used_regs
[30] = 1;
16454 /* Do not allow HI and LO to be treated as register operands.
16455 There are no MTHI or MTLO instructions (or any real need
16456 for them) and one-way registers cannot easily be reloaded. */
16457 AND_COMPL_HARD_REG_SET (operand_reg_set
,
16458 reg_class_contents
[(int) MD_REGS
]);
16460 /* $f20-$f23 are call-clobbered for n64. */
16461 if (mips_abi
== ABI_64
)
16464 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
16465 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
16467 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16469 if (mips_abi
== ABI_N32
)
16472 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
16473 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
16475 /* Make sure that double-register accumulator values are correctly
16476 ordered for the current endianness. */
16477 if (TARGET_LITTLE_ENDIAN
)
16479 unsigned int regno
;
16481 mips_swap_registers (MD_REG_FIRST
);
16482 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
16483 mips_swap_registers (regno
);
16487 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16488 other registers for instructions for which it is possible. This
16489 encourages the compiler to use CMP in cases where an XOR would
16490 require some register shuffling. */
16493 mips_order_regs_for_local_alloc (void)
16497 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
16498 reg_alloc_order
[i
] = i
;
16502 /* It really doesn't matter where we put register 0, since it is
16503 a fixed register anyhow. */
16504 reg_alloc_order
[0] = 24;
16505 reg_alloc_order
[24] = 0;
16509 /* Implement EH_USES. */
16512 mips_eh_uses (unsigned int regno
)
16514 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
16516 /* We need to force certain registers to be live in order to handle
16517 PIC long branches correctly. See mips_must_initialize_gp_p for
16519 if (mips_cfun_has_cprestore_slot_p ())
16521 if (regno
== CPRESTORE_SLOT_REGNUM
)
16526 if (cfun
->machine
->global_pointer
== regno
)
16534 /* Implement EPILOGUE_USES. */
16537 mips_epilogue_uses (unsigned int regno
)
16539 /* Say that the epilogue uses the return address register. Note that
16540 in the case of sibcalls, the values "used by the epilogue" are
16541 considered live at the start of the called function. */
16542 if (regno
== RETURN_ADDR_REGNUM
)
16545 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16546 See the comment above load_call<mode> for details. */
16547 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
16550 /* An interrupt handler must preserve some registers that are
16551 ordinarily call-clobbered. */
16552 if (cfun
->machine
->interrupt_handler_p
16553 && mips_interrupt_extra_call_saved_reg_p (regno
))
16559 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16562 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
16564 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
16567 /* Return true if INSN needs to be wrapped in ".set noat".
16568 INSN has NOPERANDS operands, stored in OPVEC. */
16571 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
16575 if (recog_memoized (insn
) >= 0)
16576 for (i
= 0; i
< noperands
; i
++)
16577 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
16582 /* Implement FINAL_PRESCAN_INSN. */
16585 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
16587 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16588 mips_push_asm_switch (&mips_noat
);
16591 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16594 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
16595 rtx
*opvec
, int noperands
)
16597 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16598 mips_pop_asm_switch (&mips_noat
);
16601 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16602 EXT_CODE is the code of the extension used. Return NULL if widening
16603 multiplication shouldn't be used. */
16606 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
16610 signed_p
= ext_code
== SIGN_EXTEND
;
16613 /* Don't use widening multiplication with MULT when we have DMUL. Even
16614 with the extension of its input operands DMUL is faster. Note that
16615 the extension is not needed for signed multiplication. In order to
16616 ensure that we always remove the redundant sign-extension in this
16617 case we still expand mulsidi3 for DMUL. */
16619 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
16622 ? gen_mulsidi3_64bit_mips16
16623 : gen_umulsidi3_64bit_mips16
);
16624 if (TARGET_FIX_R4000
)
16626 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
16632 ? gen_mulsidi3_32bit_mips16
16633 : gen_umulsidi3_32bit_mips16
);
16634 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
16635 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
16636 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
16640 /* Return the size in bytes of the trampoline code, padded to
16641 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16642 function address immediately follow. */
16645 mips_trampoline_code_size (void)
16647 if (TARGET_USE_PIC_FN_ADDR_REG
)
16649 else if (ptr_mode
== DImode
)
16651 else if (ISA_HAS_LOAD_DELAY
)
16657 /* Implement TARGET_TRAMPOLINE_INIT. */
16660 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
16662 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
16665 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
16667 /* Work out the offsets of the pointers from the start of the
16668 trampoline code. */
16669 end_addr_offset
= mips_trampoline_code_size ();
16670 static_chain_offset
= end_addr_offset
;
16671 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
16673 /* Get pointers to the beginning and end of the code block. */
16674 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
16675 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
16677 #define OP(X) gen_int_mode (X, SImode)
16679 /* Build up the code in TRAMPOLINE. */
16681 if (TARGET_USE_PIC_FN_ADDR_REG
)
16683 /* $25 contains the address of the trampoline. Emit code of the form:
16685 l[wd] $1, target_function_offset($25)
16686 l[wd] $static_chain, static_chain_offset($25)
16689 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
16690 target_function_offset
,
16691 PIC_FUNCTION_ADDR_REGNUM
));
16692 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16693 static_chain_offset
,
16694 PIC_FUNCTION_ADDR_REGNUM
));
16695 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
16696 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
16698 else if (ptr_mode
== DImode
)
16700 /* It's too cumbersome to create the full 64-bit address, so let's
16706 1: l[wd] $25, target_function_offset - 12($31)
16707 l[wd] $static_chain, static_chain_offset - 12($31)
16711 where 12 is the offset of "1:" from the start of the code block. */
16712 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
16713 trampoline
[i
++] = OP (MIPS_BAL (1));
16714 trampoline
[i
++] = OP (MIPS_NOP
);
16715 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16716 target_function_offset
- 12,
16717 RETURN_ADDR_REGNUM
));
16718 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16719 static_chain_offset
- 12,
16720 RETURN_ADDR_REGNUM
));
16721 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16722 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
16726 /* If the target has load delays, emit:
16728 lui $1, %hi(end_addr)
16729 lw $25, %lo(end_addr + ...)($1)
16730 lw $static_chain, %lo(end_addr + ...)($1)
16736 lui $1, %hi(end_addr)
16737 lw $25, %lo(end_addr + ...)($1)
16739 lw $static_chain, %lo(end_addr + ...)($1). */
16741 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16742 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16743 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
16744 NULL
, false, OPTAB_WIDEN
);
16745 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
16746 NULL
, false, OPTAB_WIDEN
);
16747 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
16749 /* Emit the LUI. */
16750 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
16751 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
16752 NULL
, false, OPTAB_WIDEN
);
16754 /* Emit the load of the target function. */
16755 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16756 target_function_offset
- end_addr_offset
,
16758 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16759 NULL
, false, OPTAB_WIDEN
);
16761 /* Emit the JR here, if we can. */
16762 if (!ISA_HAS_LOAD_DELAY
)
16763 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16765 /* Emit the load of the static chain register. */
16766 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16767 static_chain_offset
- end_addr_offset
,
16769 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16770 NULL
, false, OPTAB_WIDEN
);
16772 /* Emit the JR, if we couldn't above. */
16773 if (ISA_HAS_LOAD_DELAY
)
16775 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16776 trampoline
[i
++] = OP (MIPS_NOP
);
16782 /* Copy the trampoline code. Leave any padding uninitialized. */
16783 for (j
= 0; j
< i
; j
++)
16785 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
16786 mips_emit_move (mem
, trampoline
[j
]);
16789 /* Set up the static chain pointer field. */
16790 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
16791 mips_emit_move (mem
, chain_value
);
16793 /* Set up the target function field. */
16794 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
16795 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
16797 /* Flush the code part of the trampoline. */
16798 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
16799 emit_insn (gen_clear_cache (addr
, end_addr
));
16802 /* Implement FUNCTION_PROFILER. */
16804 void mips_function_profiler (FILE *file
)
16807 sorry ("mips16 function profiling");
16808 if (TARGET_LONG_CALLS
)
16810 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16811 if (Pmode
== DImode
)
16812 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
16814 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
16816 mips_push_asm_switch (&mips_noat
);
16817 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
16818 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
16819 /* _mcount treats $2 as the static chain register. */
16820 if (cfun
->static_chain_decl
!= NULL
)
16821 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
16822 reg_names
[STATIC_CHAIN_REGNUM
]);
16823 if (TARGET_MCOUNT_RA_ADDRESS
)
16825 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16826 ra save location. */
16827 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
16828 /* ra not saved, pass zero. */
16829 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
16831 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
16832 Pmode
== DImode
? "dla" : "la", reg_names
[12],
16833 cfun
->machine
->frame
.ra_fp_offset
,
16834 reg_names
[STACK_POINTER_REGNUM
]);
16836 if (!TARGET_NEWABI
)
16838 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16839 TARGET_64BIT
? "dsubu" : "subu",
16840 reg_names
[STACK_POINTER_REGNUM
],
16841 reg_names
[STACK_POINTER_REGNUM
],
16842 Pmode
== DImode
? 16 : 8);
16844 if (TARGET_LONG_CALLS
)
16845 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
16847 fprintf (file
, "\tjal\t_mcount\n");
16848 mips_pop_asm_switch (&mips_noat
);
16849 /* _mcount treats $2 as the static chain register. */
16850 if (cfun
->static_chain_decl
!= NULL
)
16851 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
16855 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16856 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16857 when TARGET_LOONGSON_VECTORS is true. */
16859 static unsigned HOST_WIDE_INT
16860 mips_shift_truncation_mask (enum machine_mode mode
)
16862 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
16865 return GET_MODE_BITSIZE (mode
) - 1;
16868 /* Implement TARGET_PREPARE_PCH_SAVE. */
16871 mips_prepare_pch_save (void)
16873 /* We are called in a context where the current MIPS16 vs. non-MIPS16
16874 setting should be irrelevant. The question then is: which setting
16875 makes most sense at load time?
16877 The PCH is loaded before the first token is read. We should never
16878 have switched into MIPS16 mode by that point, and thus should not
16879 have populated mips16_globals. Nor can we load the entire contents
16880 of mips16_globals from the PCH file, because mips16_globals contains
16881 a combination of GGC and non-GGC data.
16883 There is therefore no point in trying save the GGC part of
16884 mips16_globals to the PCH file, or to preserve MIPS16ness across
16885 the PCH save and load. The loading compiler would not have access
16886 to the non-GGC parts of mips16_globals (either from the PCH file,
16887 or from a copy that the loading compiler generated itself) and would
16888 have to call target_reinit anyway.
16890 It therefore seems best to switch back to non-MIPS16 mode at
16891 save time, and to ensure that mips16_globals remains null after
16893 mips_set_mips16_mode (false);
16894 mips16_globals
= 0;
16897 /* Generate or test for an insn that supports a constant permutation. */
16899 #define MAX_VECT_LEN 8
16901 struct expand_vec_perm_d
16903 rtx target
, op0
, op1
;
16904 unsigned char perm
[MAX_VECT_LEN
];
16905 enum machine_mode vmode
;
16906 unsigned char nelt
;
16911 /* Construct (set target (vec_select op0 (parallel perm))) and
16912 return true if that's a valid instruction in the active ISA. */
16915 mips_expand_vselect (rtx target
, rtx op0
,
16916 const unsigned char *perm
, unsigned nelt
)
16918 rtx rperm
[MAX_VECT_LEN
], x
;
16921 for (i
= 0; i
< nelt
; ++i
)
16922 rperm
[i
] = GEN_INT (perm
[i
]);
16924 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
16925 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
16926 x
= gen_rtx_SET (VOIDmode
, target
, x
);
16929 if (recog_memoized (x
) < 0)
16937 /* Similar, but generate a vec_concat from op0 and op1 as well. */
16940 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
16941 const unsigned char *perm
, unsigned nelt
)
16943 enum machine_mode v2mode
;
16946 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
16947 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
16948 return mips_expand_vselect (target
, x
, perm
, nelt
);
16951 /* Recognize patterns for even-odd extraction. */
16954 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
16956 unsigned i
, odd
, nelt
= d
->nelt
;
16957 rtx t0
, t1
, t2
, t3
;
16959 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
16961 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
16968 for (i
= 1; i
< nelt
; ++i
)
16969 if (d
->perm
[i
] != i
* 2 + odd
)
16975 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
16976 t0
= gen_reg_rtx (d
->vmode
);
16977 t1
= gen_reg_rtx (d
->vmode
);
16981 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
16982 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
16984 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
16986 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
16990 t2
= gen_reg_rtx (d
->vmode
);
16991 t3
= gen_reg_rtx (d
->vmode
);
16992 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
16993 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
16994 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
16995 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
16997 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
16999 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
17003 gcc_unreachable ();
17008 /* Recognize patterns for the Loongson PSHUFH instruction. */
17011 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
17016 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17018 if (d
->vmode
!= V4HImode
)
17023 /* Convert the selector into the packed 8-bit form for pshufh. */
17024 /* Recall that loongson is little-endian only. No big-endian
17025 adjustment required. */
17026 for (i
= mask
= 0; i
< 4; i
++)
17027 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
17028 rmask
= force_reg (SImode
, GEN_INT (mask
));
17030 if (d
->one_vector_p
)
17031 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
17034 rtx t0
, t1
, x
, merge
, rmerge
[4];
17036 t0
= gen_reg_rtx (V4HImode
);
17037 t1
= gen_reg_rtx (V4HImode
);
17038 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
17039 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
17041 for (i
= 0; i
< 4; ++i
)
17042 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
17043 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
17044 merge
= force_reg (V4HImode
, merge
);
17046 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
17047 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
17049 x
= gen_rtx_NOT (V4HImode
, merge
);
17050 x
= gen_rtx_AND (V4HImode
, x
, t0
);
17051 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
17053 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
17054 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
17060 /* Recognize broadcast patterns for the Loongson. */
17063 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
17068 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17070 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
17071 if (d
->vmode
!= V8QImode
)
17073 if (!d
->one_vector_p
)
17077 for (i
= 1; i
< 8; ++i
)
17078 if (d
->perm
[i
] != elt
)
17084 /* With one interleave we put two of the desired element adjacent. */
17085 t0
= gen_reg_rtx (V8QImode
);
17087 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
17089 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
17091 /* Shuffle that one HImode element into all locations. */
17094 t1
= gen_reg_rtx (V4HImode
);
17095 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
17096 force_reg (SImode
, GEN_INT (elt
))));
17098 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
17103 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
17105 unsigned int i
, nelt
= d
->nelt
;
17106 unsigned char perm2
[MAX_VECT_LEN
];
17108 if (d
->one_vector_p
)
17110 /* Try interleave with alternating operands. */
17111 memcpy (perm2
, d
->perm
, sizeof(perm2
));
17112 for (i
= 1; i
< nelt
; i
+= 2)
17114 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
17119 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
17123 /* Try again with swapped operands. */
17124 for (i
= 0; i
< nelt
; ++i
)
17125 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
17126 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
17130 if (mips_expand_vpc_loongson_even_odd (d
))
17132 if (mips_expand_vpc_loongson_pshufh (d
))
17134 if (mips_expand_vpc_loongson_bcast (d
))
17139 /* Expand a vec_perm_const pattern. */
17142 mips_expand_vec_perm_const (rtx operands
[4])
17144 struct expand_vec_perm_d d
;
17145 int i
, nelt
, which
;
17146 unsigned char orig_perm
[MAX_VECT_LEN
];
17150 d
.target
= operands
[0];
17151 d
.op0
= operands
[1];
17152 d
.op1
= operands
[2];
17155 d
.vmode
= GET_MODE (d
.target
);
17156 gcc_assert (VECTOR_MODE_P (d
.vmode
));
17157 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
17158 d
.testing_p
= false;
17160 for (i
= which
= 0; i
< nelt
; ++i
)
17162 rtx e
= XVECEXP (sel
, 0, i
);
17163 int ei
= INTVAL (e
) & (2 * nelt
- 1);
17164 which
|= (ei
< nelt
? 1 : 2);
17167 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
17175 d
.one_vector_p
= false;
17176 if (!rtx_equal_p (d
.op0
, d
.op1
))
17181 for (i
= 0; i
< nelt
; ++i
)
17182 d
.perm
[i
] &= nelt
- 1;
17184 d
.one_vector_p
= true;
17189 d
.one_vector_p
= true;
17193 ok
= mips_expand_vec_perm_const_1 (&d
);
17195 /* If we were given a two-vector permutation which just happened to
17196 have both input vectors equal, we folded this into a one-vector
17197 permutation. There are several loongson patterns that are matched
17198 via direct vec_select+vec_concat expansion, but we do not have
17199 support in mips_expand_vec_perm_const_1 to guess the adjustment
17200 that should be made for a single operand. Just try again with
17201 the original permutation. */
17202 if (!ok
&& which
== 3)
17204 d
.op0
= operands
[1];
17205 d
.op1
= operands
[2];
17206 d
.one_vector_p
= false;
17207 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
17208 ok
= mips_expand_vec_perm_const_1 (&d
);
17214 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17217 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
17218 const unsigned char *sel
)
17220 struct expand_vec_perm_d d
;
17221 unsigned int i
, nelt
, which
;
17225 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
17226 d
.testing_p
= true;
17227 memcpy (d
.perm
, sel
, nelt
);
17229 /* Categorize the set of elements in the selector. */
17230 for (i
= which
= 0; i
< nelt
; ++i
)
17232 unsigned char e
= d
.perm
[i
];
17233 gcc_assert (e
< 2 * nelt
);
17234 which
|= (e
< nelt
? 1 : 2);
17237 /* For all elements from second vector, fold the elements to first. */
17239 for (i
= 0; i
< nelt
; ++i
)
17242 /* Check whether the mask can be applied to the vector type. */
17243 d
.one_vector_p
= (which
!= 3);
17245 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
17246 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
17247 if (!d
.one_vector_p
)
17248 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
17251 ret
= mips_expand_vec_perm_const_1 (&d
);
17257 /* Expand an integral vector unpack operation. */
17260 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
17262 enum machine_mode imode
= GET_MODE (operands
[1]);
17263 rtx (*unpack
) (rtx
, rtx
, rtx
);
17264 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
17265 rtx tmp
, dest
, zero
;
17271 unpack
= gen_loongson_punpckhbh
;
17273 unpack
= gen_loongson_punpcklbh
;
17274 cmpgt
= gen_loongson_pcmpgtb
;
17278 unpack
= gen_loongson_punpckhhw
;
17280 unpack
= gen_loongson_punpcklhw
;
17281 cmpgt
= gen_loongson_pcmpgth
;
17284 gcc_unreachable ();
17287 zero
= force_reg (imode
, CONST0_RTX (imode
));
17292 tmp
= gen_reg_rtx (imode
);
17293 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
17296 dest
= gen_reg_rtx (imode
);
17297 emit_insn (unpack (dest
, operands
[1], tmp
));
17299 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
17302 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17305 mips_constant_elt_p (rtx x
)
17307 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
17310 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17313 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
17315 struct expand_vec_perm_d d
;
17319 if (elt
!= const0_rtx
)
17320 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
17322 elt
= gen_lowpart (DImode
, elt
);
17324 t1
= gen_reg_rtx (vmode
);
17328 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
17331 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
17334 gcc_unreachable ();
17337 memset (&d
, 0, sizeof (d
));
17342 d
.nelt
= GET_MODE_NUNITS (vmode
);
17343 d
.one_vector_p
= true;
17345 ok
= mips_expand_vec_perm_const_1 (&d
);
17349 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17350 elements of VALS with zeros, copy the constant vector to TARGET. */
17353 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
17354 rtx target
, rtx vals
)
17356 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
17359 for (i
= 0; i
< nelt
; ++i
)
17361 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
17362 RTVEC_ELT (vec
, i
) = const0_rtx
;
17365 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
17369 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17372 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
17374 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
17376 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
17377 GEN_INT (one_var
)));
17380 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17383 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
17384 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
17386 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
17387 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
17390 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
17392 for (i
= 0; i
< nelt
; ++i
)
17394 rtx x
= XVECEXP (vals
, 0, i
);
17395 if (!mips_constant_elt_p (x
))
17396 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
17399 emit_move_insn (target
, mem
);
17402 /* Expand a vector initialization. */
17405 mips_expand_vector_init (rtx target
, rtx vals
)
17407 enum machine_mode vmode
= GET_MODE (target
);
17408 enum machine_mode imode
= GET_MODE_INNER (vmode
);
17409 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
17410 unsigned nvar
= 0, one_var
= -1u;
17411 bool all_same
= true;
17414 for (i
= 0; i
< nelt
; ++i
)
17416 x
= XVECEXP (vals
, 0, i
);
17417 if (!mips_constant_elt_p (x
))
17418 nvar
++, one_var
= i
;
17419 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
17423 /* Load constants from the pool, or whatever's handy. */
17426 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
17430 /* For two-part initialization, always use CONCAT. */
17433 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
17434 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
17435 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
17436 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
17440 /* Loongson is the only cpu with vectors with more elements. */
17441 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
17443 /* If all values are identical, broadcast the value. */
17446 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
17450 /* If we've only got one non-variable V4HImode, use PINSRH. */
17451 if (nvar
== 1 && vmode
== V4HImode
)
17453 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
17457 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
17460 /* Expand a vector reduction. */
17463 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
17465 enum machine_mode vmode
= GET_MODE (in
);
17466 unsigned char perm2
[2];
17467 rtx last
, next
, fold
, x
;
17471 fold
= gen_reg_rtx (vmode
);
17475 /* Use PUL/PLU to produce { L, H } op { H, L }.
17476 By reversing the pair order, rather than a pure interleave high,
17477 we avoid erroneous exceptional conditions that we might otherwise
17478 produce from the computation of H op H. */
17481 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
17486 /* Use interleave to produce { H, L } op { H, H }. */
17487 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
17491 /* Perform the first reduction with interleave,
17492 and subsequent reductions with shifts. */
17493 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
17495 next
= gen_reg_rtx (vmode
);
17496 emit_insn (gen (next
, last
, fold
));
17499 fold
= gen_reg_rtx (vmode
);
17500 x
= force_reg (SImode
, GEN_INT (16));
17501 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
17505 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
17507 next
= gen_reg_rtx (vmode
);
17508 emit_insn (gen (next
, last
, fold
));
17511 fold
= gen_reg_rtx (vmode
);
17512 x
= force_reg (SImode
, GEN_INT (16));
17513 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
17515 next
= gen_reg_rtx (vmode
);
17516 emit_insn (gen (next
, last
, fold
));
17519 fold
= gen_reg_rtx (vmode
);
17520 x
= force_reg (SImode
, GEN_INT (8));
17521 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
17525 gcc_unreachable ();
17528 emit_insn (gen (target
, last
, fold
));
17531 /* Expand a vector minimum/maximum. */
17534 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
17535 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
17537 enum machine_mode vmode
= GET_MODE (target
);
17540 tc
= gen_reg_rtx (vmode
);
17541 t0
= gen_reg_rtx (vmode
);
17542 t1
= gen_reg_rtx (vmode
);
17545 emit_insn (cmp (tc
, op0
, op1
));
17547 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
17548 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
17550 x
= gen_rtx_NOT (vmode
, tc
);
17551 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
17552 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
17554 x
= gen_rtx_IOR (vmode
, t0
, t1
);
17555 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
17558 /* Initialize the GCC target structure. */
17559 #undef TARGET_ASM_ALIGNED_HI_OP
17560 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
17561 #undef TARGET_ASM_ALIGNED_SI_OP
17562 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
17563 #undef TARGET_ASM_ALIGNED_DI_OP
17564 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
17566 #undef TARGET_OPTION_OVERRIDE
17567 #define TARGET_OPTION_OVERRIDE mips_option_override
17569 #undef TARGET_LEGITIMIZE_ADDRESS
17570 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
17572 #undef TARGET_ASM_FUNCTION_PROLOGUE
17573 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
17574 #undef TARGET_ASM_FUNCTION_EPILOGUE
17575 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
17576 #undef TARGET_ASM_SELECT_RTX_SECTION
17577 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
17578 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
17579 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
17581 #undef TARGET_SCHED_INIT
17582 #define TARGET_SCHED_INIT mips_sched_init
17583 #undef TARGET_SCHED_REORDER
17584 #define TARGET_SCHED_REORDER mips_sched_reorder
17585 #undef TARGET_SCHED_REORDER2
17586 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
17587 #undef TARGET_SCHED_VARIABLE_ISSUE
17588 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
17589 #undef TARGET_SCHED_ADJUST_COST
17590 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
17591 #undef TARGET_SCHED_ISSUE_RATE
17592 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
17593 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
17594 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
17595 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
17596 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
17597 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17598 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17599 mips_multipass_dfa_lookahead
17600 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
17601 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
17602 mips_small_register_classes_for_mode_p
17604 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17605 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
17607 #undef TARGET_INSERT_ATTRIBUTES
17608 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
17609 #undef TARGET_MERGE_DECL_ATTRIBUTES
17610 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
17611 #undef TARGET_SET_CURRENT_FUNCTION
17612 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
17614 #undef TARGET_VALID_POINTER_MODE
17615 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
17616 #undef TARGET_REGISTER_MOVE_COST
17617 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
17618 #undef TARGET_MEMORY_MOVE_COST
17619 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
17620 #undef TARGET_RTX_COSTS
17621 #define TARGET_RTX_COSTS mips_rtx_costs
17622 #undef TARGET_ADDRESS_COST
17623 #define TARGET_ADDRESS_COST mips_address_cost
17625 #undef TARGET_IN_SMALL_DATA_P
17626 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
17628 #undef TARGET_MACHINE_DEPENDENT_REORG
17629 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
17631 #undef TARGET_PREFERRED_RELOAD_CLASS
17632 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
17634 #undef TARGET_ASM_FILE_START
17635 #define TARGET_ASM_FILE_START mips_file_start
17636 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
17637 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
17638 #undef TARGET_ASM_CODE_END
17639 #define TARGET_ASM_CODE_END mips_code_end
17641 #undef TARGET_INIT_LIBFUNCS
17642 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
17644 #undef TARGET_BUILD_BUILTIN_VA_LIST
17645 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
17646 #undef TARGET_EXPAND_BUILTIN_VA_START
17647 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
17648 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17649 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
17651 #undef TARGET_PROMOTE_FUNCTION_MODE
17652 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
17653 #undef TARGET_PROMOTE_PROTOTYPES
17654 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
17656 #undef TARGET_FUNCTION_VALUE
17657 #define TARGET_FUNCTION_VALUE mips_function_value
17658 #undef TARGET_LIBCALL_VALUE
17659 #define TARGET_LIBCALL_VALUE mips_libcall_value
17660 #undef TARGET_FUNCTION_VALUE_REGNO_P
17661 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
17662 #undef TARGET_RETURN_IN_MEMORY
17663 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
17664 #undef TARGET_RETURN_IN_MSB
17665 #define TARGET_RETURN_IN_MSB mips_return_in_msb
17667 #undef TARGET_ASM_OUTPUT_MI_THUNK
17668 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
17669 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17670 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
17672 #undef TARGET_PRINT_OPERAND
17673 #define TARGET_PRINT_OPERAND mips_print_operand
17674 #undef TARGET_PRINT_OPERAND_ADDRESS
17675 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
17676 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
17677 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
17679 #undef TARGET_SETUP_INCOMING_VARARGS
17680 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
17681 #undef TARGET_STRICT_ARGUMENT_NAMING
17682 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
17683 #undef TARGET_MUST_PASS_IN_STACK
17684 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17685 #undef TARGET_PASS_BY_REFERENCE
17686 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
17687 #undef TARGET_CALLEE_COPIES
17688 #define TARGET_CALLEE_COPIES mips_callee_copies
17689 #undef TARGET_ARG_PARTIAL_BYTES
17690 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
17691 #undef TARGET_FUNCTION_ARG
17692 #define TARGET_FUNCTION_ARG mips_function_arg
17693 #undef TARGET_FUNCTION_ARG_ADVANCE
17694 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
17695 #undef TARGET_FUNCTION_ARG_BOUNDARY
17696 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
17698 #undef TARGET_MODE_REP_EXTENDED
17699 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
17701 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17702 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
17704 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17705 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
17707 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17708 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
17710 #undef TARGET_INIT_BUILTINS
17711 #define TARGET_INIT_BUILTINS mips_init_builtins
17712 #undef TARGET_BUILTIN_DECL
17713 #define TARGET_BUILTIN_DECL mips_builtin_decl
17714 #undef TARGET_EXPAND_BUILTIN
17715 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
17717 #undef TARGET_HAVE_TLS
17718 #define TARGET_HAVE_TLS HAVE_AS_TLS
17720 #undef TARGET_CANNOT_FORCE_CONST_MEM
17721 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
17723 #undef TARGET_LEGITIMATE_CONSTANT_P
17724 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
17726 #undef TARGET_ENCODE_SECTION_INFO
17727 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
17729 #undef TARGET_ATTRIBUTE_TABLE
17730 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
17731 /* All our function attributes are related to how out-of-line copies should
17732 be compiled or called. They don't in themselves prevent inlining. */
17733 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
17734 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
17736 #undef TARGET_EXTRA_LIVE_ON_ENTRY
17737 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
17739 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17740 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
17741 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
17742 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
17744 #undef TARGET_COMP_TYPE_ATTRIBUTES
17745 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
17747 #ifdef HAVE_AS_DTPRELWORD
17748 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
17749 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
17751 #undef TARGET_DWARF_REGISTER_SPAN
17752 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
17754 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
17755 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
17757 #undef TARGET_LEGITIMATE_ADDRESS_P
17758 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
17760 #undef TARGET_FRAME_POINTER_REQUIRED
17761 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
17763 #undef TARGET_CAN_ELIMINATE
17764 #define TARGET_CAN_ELIMINATE mips_can_eliminate
17766 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17767 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
17769 #undef TARGET_TRAMPOLINE_INIT
17770 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
17772 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
17773 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
17775 #undef TARGET_SHIFT_TRUNCATION_MASK
17776 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
17778 #undef TARGET_PREPARE_PCH_SAVE
17779 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
17781 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
17782 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
17784 struct gcc_target targetm
= TARGET_INITIALIZER
;
17786 #include "gt-mips.h"