| blob | ec40a1f919c12d310b786b72404ae08b66e3d050 |
1 2024-03-22 Georg-Johann Lay <avr@gjlay.de>
3 * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
4 for deprecated SIGNAL and INTERRUPT usage without respective header.
6 2024-03-22 Andrew Stubbs <ams@baylibre.com>
8 * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
9 (atomic_load<mode>): Adjust RDNA cache settings.
10 (atomic_store<mode>): Likewise.
11 (atomic_exchange<mode>): Likewise.
13 2024-03-22 Andrew Stubbs <ams@baylibre.com>
15 * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
16 RDNA devices.
18 2024-03-22 Andrew Stubbs <ams@baylibre.com>
20 * config.gcc (amdgcn): Add gfx1103 entries.
21 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
22 (gcn_local_sym_hash): Likewise.
23 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
24 (TARGET_GFX1103): New macro.
25 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
26 (gcn_omp_device_kind_arch_isa): Likewise.
27 (output_file_start): Likewise.
28 (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
29 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
30 * config/gcn/gcn.opt: Add gfx1103.
31 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
32 (main): Handle gfx1103.
33 * config/gcn/t-omp-device: Add gfx1103 isa.
34 * doc/install.texi (amdgcn): Add gfx1103.
35 * doc/invoke.texi (-march): Likewise.
37 2024-03-22 Andrew Stubbs <ams@baylibre.com>
39 * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
40 bitmasks.
41 (do_compare_and_jump): Remove now-redundant similar code.
42 * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
43 bitmasks.
44 (add_mask_and_len_args): Likewise.
46 2024-03-22 Pan Li <pan2.li@intel.com>
48 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
49 macro __riscv_v_fixed_vlen when zvl.
50 * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
51 New static func to take care of the RVV types decorated by
52 the attributes.
54 2024-03-22 Andrew Pinski <quic_apinski@quicinc.com>
56 PR c/109619
57 * builtins.cc (fold_builtin_1): Use error_operand_p
58 instead of checking against ERROR_MARK.
59 (fold_builtin_2): Likewise.
60 (fold_builtin_3): Likewise.
62 2024-03-22 Jakub Jelinek <jakub@redhat.com>
64 PR sanitizer/111736
65 * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
66 SANITIZE_NULL instrumentation for non-generic address spaces
67 for which targetm.addr_space.zero_address_valid (as) is true.
69 2024-03-22 Jakub Jelinek <jakub@redhat.com>
71 PR tree-optimization/114405
72 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
73 Set rprec to limb_prec rather than 0 if tprec is divisible by
74 limb_prec. In the last bf_cur handling, set rprec to (tprec + bo_bit)
75 % limb_prec rather than tprec % limb_prec and use just rprec instead
76 of rprec + bo_bit. For build_bit_field_ref offset, divide
77 (tprec + bo_bit) by limb_prec rather than just tprec.
79 2024-03-22 Christoph Müllner <christoph.muellner@vrull.eu>
81 PR target/114194
82 * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
83 Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
85 2024-03-22 Jeff Law <jlaw@ventanamicro.com>
87 * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
88 tie for scalable and final stack adjustment if needed.
89 Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
91 2024-03-22 Pan Li <pan2.li@intel.com>
93 PR target/114352
94 * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
95 New struct for func decl and target name.
96 (struct riscv_func_target_hasher): New hasher for hash table mapping
97 from the fn_decl to fn_target_name.
98 (riscv_func_decl_hash): New func to compute the hash for fn_decl.
99 (riscv_func_target_hasher::hash): New func to impl hash interface.
100 (riscv_func_target_hasher::equal): New func to impl equal interface.
101 (riscv_cmdline_subset_list): New static var for cmdline subset list.
102 (riscv_func_target_table_lazy_init): New func to lazy init the func
103 target hash table.
104 (riscv_func_target_get): New func to get target name from hash table.
105 (riscv_func_target_put): New func to put target name into hash table.
106 (riscv_func_target_remove_and_destory): New func to remove target
107 info from the hash table and destory it.
108 (riscv_parse_arch_string): Set the static var cmdline_subset_list.
109 * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
110 var for cmdline subset list.
111 (riscv_func_target_get): New func decl.
112 (riscv_func_target_put): Ditto.
113 (riscv_func_target_remove_and_destory): Ditto.
114 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
115 Take cmdline_subset_list instead of current_subset_list when clone.
116 (riscv_process_target_attr): Record the func target info to hash table.
117 (riscv_option_valid_attribute_p): Add new arg tree fndel.
118 * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
119 func target info and print the arch message.
121 2024-03-22 Pan Li <pan2.li@intel.com>
123 PR target/114352
124 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
125 Replace implied, combine and check to func finalize.
126 (riscv_subset_list::finalize): New func impl to take care of
127 implied, combine ext and related checks.
128 * config/riscv/riscv-subset.h: Add func decl for finalize.
129 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
130 Finalize the ext before return succeed.
131 * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
132 machine mode before when set cur function.
134 2024-03-21 Andrew Stubbs <ams@baylibre.com>
136 * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
138 2024-03-21 Andrew Stubbs <ams@baylibre.com>
140 * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
142 2024-03-21 Andrew Stubbs <ams@baylibre.com>
144 * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
145 device_malloc call.
147 2024-03-21 liuhongt <hongtao.liu@intel.com>
149 PR tree-optimization/114396
150 * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
151 and true to wi::from_mpz.
153 2024-03-21 Richard Biener <rguenther@suse.de>
155 PR tree-optimization/111736
156 * asan.cc (instrument_derefs): Do not instrument accesses
157 to non-generic address-spaces.
159 2024-03-21 Richard Biener <rguenther@suse.de>
161 PR tree-optimization/113727
162 * tree-sra.cc (analyze_access_subtree): Do not allow
163 replacements in subtrees when grp_partial_lhs.
165 2024-03-21 liuhongt <hongtao.liu@intel.com>
167 PR middle-end/114347
168 * doc/invoke.texi: Document -fexcess-precision=16.
170 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
172 * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
173 field contains a DECL_NAME.
175 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
177 * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
178 Add assert to validate the string is set.
179 * config/bpf/core-builtins.cc (cr_final): Make string struct
180 field as const.
181 (process_enum_value): Correct for field type change.
182 (process_type): Set access string to "0".
184 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
186 * config/bpf/core-builtins.cc (core_field_info): Add
187 support for POINTER_PLUS_EXPR in the root of the field expression.
188 (bpf_core_get_index): Likewise.
189 (pack_field_expr): Make the BTF type to point to the structure
190 related node, instead of its pointer type.
191 (make_core_safe_access_index): Correct to new code.
193 2024-03-20 Xi Ruoyao <xry111@xry111.site>
195 PR target/114407
196 * config/loongarch/loongarch-opts.cc (loongarch_config_target):
197 Fix typo in diagnostic message, enabing -> enabling.
199 2024-03-20 Jakub Jelinek <jakub@redhat.com>
201 PR target/114175
202 * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
203 TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
204 if arg.type is NULL.
206 2024-03-20 Jakub Jelinek <jakub@redhat.com>
208 PR target/114175
209 * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
210 nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
211 if arg.type is NULL.
213 2024-03-20 Jakub Jelinek <jakub@redhat.com>
215 PR target/114175
216 * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
217 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
218 if arg.type is NULL.
220 2024-03-20 Jakub Jelinek <jakub@redhat.com>
222 PR target/114175
223 * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
224 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
225 if arg.type is NULL.
227 2024-03-20 Jakub Jelinek <jakub@redhat.com>
229 PR target/114175
230 * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
231 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
232 if arg.type is NULL.
234 2024-03-20 Jakub Jelinek <jakub@redhat.com>
236 PR target/114175
237 * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
238 skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
239 if arg.type is NULL.
241 2024-03-20 Jakub Jelinek <jakub@redhat.com>
243 PR target/114175
244 * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
245 csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
246 if arg.type is NULL.
248 2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
250 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
252 2024-03-20 Jakub Jelinek <jakub@redhat.com>
254 PR tree-optimization/114365
255 * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
256 a PHI node, set iv2 to its result afterwards.
258 2024-03-20 Jakub Jelinek <jakub@redhat.com>
260 * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
261 probabbility -> probability.
262 (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
264 2024-03-20 Jakub Jelinek <jakub@redhat.com>
266 PR bootstrap/114369
267 * system.h (vec_step): Define to vec_step_ when compiling
268 with clang on PowerPC.
270 2024-03-20 demin.han <demin.han@starfivetech.com>
272 PR target/112651
273 * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
274 (enum rvv_max_lmul_enum): Ditto
275 (TARGET_MAX_LMUL): Ditto
276 * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
277 * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
278 (costs::better_main_loop_than_p): Ditto
279 * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
281 2024-03-20 Richard Biener <rguenther@suse.de>
283 PR middle-end/113396
284 * tree-dfa.cc (get_ref_base_and_extent): Use index range
285 bounds only if they fit within the address-range constraints
286 of offset_int.
288 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
290 * config/loongarch/loongarch.cc
291 (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
292 UNITS_PER_FPREG macros.
293 (loongarch_hard_regno_nregs): Ditto.
294 (loongarch_class_max_nregs): Ditto.
295 (loongarch_get_separate_components): Ditto.
296 (loongarch_process_components): Ditto.
297 * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
298 (UNITS_PER_HWFPVALUE): Ditto.
299 (UNITS_PER_FPVALUE): Ditto.
301 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
303 * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
304 of loongarch_expand_vec_cmp()'s return value.
305 (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
306 * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
307 (vec_cmpu<ILSX:mode><mode_i>): Ditto.
308 * config/loongarch/loongarch-protos.h
309 (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
310 type from bool to void.
311 * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
313 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
315 * config/loongarch/loongarch-protos.h
316 (loongarch_cfun_has_cprestore_slot_p): Delete.
317 (loongarch_adjust_insn_length): Delete.
318 (current_section_name): Delete.
319 (loongarch_split_symbol_type): Delete.
320 * config/loongarch/loongarch.cc
321 (loongarch_case_values_threshold): Delete.
322 (loongarch_spill_class): Delete.
323 (TARGET_OPTAB_SUPPORTED_P): Delete.
324 (TARGET_CASE_VALUES_THRESHOLD): Delete.
325 (TARGET_SPILL_CLASS): Delete.
327 2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
329 PR c++/111918
330 * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
331 * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
332 Make use of DK_ANY to indicate a diagnostic was initially enabled.
333 (diagnostic_context::diagnostic_enabled): Do not change the type of
334 a diagnostic if the saved classification is type DK_ANY.
336 2024-03-19 Martin Jambor <mjambor@suse.cz>
338 PR ipa/108802
339 PR ipa/114254
340 * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
341 at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
342 a pointer parameter.
343 (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
344 parameter, also recognize the case when pfn pointer is loaded in its
345 own BB.
347 2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
349 PR target/99829
350 * lra-constraints.cc (lra_constraints): Prevent removing insn
351 with reverse equivalence to memory if the memory was reloaded.
353 2024-03-19 David Malcolm <dmalcolm@redhat.com>
355 PR middle-end/114348
356 * diagnostic-format-json.cc
357 (json_stderr_output_format::machine_readable_stderr_p): New.
358 (json_file_output_format::machine_readable_stderr_p): New.
359 * diagnostic-format-sarif.cc
360 (sarif_stream_output_format::machine_readable_stderr_p): New.
361 (sarif_file_output_format::machine_readable_stderr_p): New.
362 * diagnostic.cc (diagnostic_context::action_after_output): Move
363 "fnotice" to before "finish" call, so that we still have the
364 diagnostic_context.
365 (fnotice): Bail out if the user requested one of the
366 machine-readable diagnostic output formats on stderr.
367 * diagnostic.h
368 (diagnostic_output_format::machine_readable_stderr_p): New pure
369 virtual function.
370 (diagnostic_text_output_format::machine_readable_stderr_p): New.
371 (diagnostic_context::get_output_format): New accessor.
373 2024-03-19 Edwin Lu <ewlu@rivosinc.com>
375 PR target/114175
376 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
377 riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
378 if arg.type is NULL
380 2024-03-19 Jonathan Wakely <jwakely@redhat.com>
382 * doc/install.texi (Prerequisites): Document use of autogen for
383 libstdc++.
385 2024-03-19 Richard Biener <rguenther@suse.de>
387 PR tree-optimization/114151
388 PR tree-optimization/114269
389 PR tree-optimization/114322
390 PR tree-optimization/114074
391 * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
392 unsigned arithmetic when actual overflow on constant operands
393 is observed.
395 2024-03-19 Jakub Jelinek <jakub@redhat.com>
397 PR target/114175
398 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
399 arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
400 if arg.type is NULL.
402 2024-03-19 Xi Ruoyao <xry111@xry111.site>
404 PR target/114175
405 * config/loongarch/loongarch.cc
406 (loongarch_setup_incoming_varargs): Only skip
407 loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
408 functions if arg.type is NULL.
410 2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
412 PR target/114323
413 * config/arm/arm-mve-builtins.cc
414 (function_instance::reads_global_state_p): Take CP_READ_MEMORY
415 into account.
417 2024-03-19 Jakub Jelinek <jakub@redhat.com>
419 PR target/114175
420 * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
421 function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
422 if arg.type is NULL.
424 2024-03-19 Jakub Jelinek <jakub@redhat.com>
426 PR target/114175
427 * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
428 rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
429 if arg.type is NULL.
431 2024-03-19 Richard Biener <rguenther@suse.de>
433 PR tree-optimization/114375
434 * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
435 load permutation for masked loads but reject it when any
436 such is necessary.
437 * tree-vect-stmts.cc (vectorizable_load): Reject masked
438 VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
439 supported.
441 2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
443 * common/config/riscv/riscv-common.cc: Create XCVbi extension
444 support.
445 * config/riscv/riscv.opt: Likewise.
446 * config/riscv/corev.md: Implement cv_branch<mode> pattern
447 for cv.beqimm and cv.bneimm.
448 * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
449 branch instruction pattern.
450 * config/riscv/constraints.md: Implement constraints
451 cv_bi_s5 - signed 5-bit immediate.
452 * config/riscv/predicates.md: Implement predicate
453 const_int5s_operand - signed 5 bit immediate.
454 * doc/sourcebuild.texi: Add XCVbi documentation.
456 2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
458 * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
459 (RISCV_CORE): Ditto.
460 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
461 option.
462 * config/riscv/riscv.cc: New def.
463 * config/riscv/riscv.md: New include.
464 * config/riscv/xiangshan.md: New file.
466 2024-03-18 David Malcolm <dmalcolm@redhat.com>
468 PR analyzer/110902
469 PR analyzer/110928
470 PR analyzer/111305
471 PR analyzer/111441
472 * selftest.h (ASSERT_NE_AT): New macro.
474 2024-03-18 Uros Bizjak <ubizjak@gmail.com>
476 PR target/111822
477 * config/i386/i386-features.cc (smode_convert_cst): New function
478 to handle SImode, DImode and TImode immediates, generalized from
479 timode_convert_cst.
480 (timode_convert_cst): Remove.
481 (scalar_chain::convert_op): Unify from
482 general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
483 (general_scalar_chain::convert_op): Remove.
484 (timode_scalar_chain::convert_op): Remove.
485 (timode_scalar_chain::convert_insn): Update the call to
486 renamed timode_convert_cst.
487 * config/i386/i386-features.h (class scalar_chain):
488 Redeclare convert_op as protected class member.
489 (class general_calar_chain): Remove convert_op.
490 (class timode_scalar_chain): Ditto.
492 2024-03-18 Jan Hubicka <jh@suse.cz>
494 * config/i386/zn4zn5.md: Add file missed in the previous commit.
496 2024-03-18 Jan Hubicka <jh@suse.cz>
497 Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
499 * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
500 * common/config/i386/i386-common.cc (processor_names): Add znver5.
501 (processor_alias_table): Likewise.
502 * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
503 family.
504 (processor_subtypes): Add znver5.
505 * config.gcc (x86_64-*-* |...): Likewise.
506 * config/i386/driver-i386.cc (host_detect_local_cpu): Let
507 march=native detect znver5 cpu's.
508 * config/i386/i386-c.cc (ix86_target_macros_internal): Add
509 znver5.
510 * config/i386/i386-options.cc (m_ZNVER5): New definition
511 (processor_cost_table): Add znver5.
512 * config/i386/i386.cc (ix86_reassociation_width): Likewise.
513 * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
514 (PTA_ZNVER5): New definition.
515 * config/i386/i386.md (define_attr "cpu"): Add znver5.
516 (Scheduling descriptions) Add znver5.md.
517 * config/i386/x86-tune-costs.h (znver5_cost): New definition.
518 * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
519 (ix86_adjust_cost): Likewise.
520 * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
521 (avx512_store_by_pieces): Add m_ZNVER5.
522 * doc/extend.texi: Add znver5.
523 * doc/invoke.texi: Likewise.
524 * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
526 2024-03-18 Georg-Johann Lay <avr@gjlay.de>
528 * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
529 * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
530 * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
531 * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
532 (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
533 (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
535 2024-03-18 liuhongt <hongtao.liu@intel.com>
537 PR target/114334
538 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
539 (MODEF248): New mode iterator.
540 (ssevecmodesuffix): Hanlde BF and HF.
541 * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
542 (<code><mode>3): Ditto.
544 2024-03-18 John David Anglin <danglin@gcc.gnu.org>
546 PR rtl-optimization/112415
547 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
548 for symbolic memory operands.
549 (pa_legitimate_address_p): Revise LO_SUM condition.
550 * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
551 comment about GNU linker to predicates.md.
552 * config/pa/predicates.md (floating_point_store_memory_operand):
553 Revise condition for symbolic memory operands. Update
554 comment.
556 2024-03-17 John David Anglin <danglin@gcc.gnu.org>
558 * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
560 2024-03-16 Jakub Jelinek <jakub@redhat.com>
562 PR target/114175
563 * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
564 ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
565 if arg.type is NULL.
567 2024-03-16 Jakub Jelinek <jakub@redhat.com>
569 PR tree-optimization/114329
570 * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
571 build_bit_field_ref method.
572 (bitint_large_huge::build_bit_field_ref): New method.
573 (bitint_large_huge::lower_mergeable_stmt): Use it.
575 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
577 * config/riscv/riscv.opt.urls: Regenerated.
578 * config/rs6000/sysv4.opt.urls: Likewise.
579 * config/xtensa/xtensa.opt.urls: Likewise.
581 2024-03-15 Jakub Jelinek <jakub@redhat.com>
583 * lower-subreg.cc (resolve_simple_move): Fix comment typo,
584 betwee -> between.
585 * edit-context.cc (class line_event): Fix comment typo,
586 betweeen -> between.
588 2024-03-15 Jakub Jelinek <jakub@redhat.com>
590 PR target/114339
591 * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
592 a pasto, compare code against LE rather than GE.
594 2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
596 * match.pd: Fix truncation pattern for -fno-signed-zeroes
598 2024-03-15 Jakub Jelinek <jakub@redhat.com>
600 PR middle-end/114332
601 * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
603 2024-03-15 Jakub Jelinek <jakub@redhat.com>
605 PR tree-optimization/113466
606 * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
607 member.
608 (bitint_large_huge::bitint_large_huge): Initialize it.
609 (bitint_large_huge::~bitint_large_huge): Release it.
610 (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
611 before which at least one statement has been inserted.
612 (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
613 calls to a different block and add corresponding PHIs.
615 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
617 * config/mips/mips.opt: Support -mstrict-align, and use
618 TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
619 as alias.
620 * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
621 * config/mips/mips.opt.urls: Regenerate.
622 * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
624 2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
626 PR middle-end/114108
627 * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
628 vect_convert_output with the correct vecitype.
630 2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
632 * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
633 Remove masking of operand 3.
635 2024-03-14 Jason Merrill <jason@redhat.com>
637 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
638 comments.
640 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
642 PR target/114288
643 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
644 14-bit displacements before reload for modes that may use
645 a floating-point load or store.
647 2024-03-14 David Faust <david.faust@oracle.com>
649 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
651 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
653 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
654 patterns ahead of the l32i.n and s32i.n.
656 2024-03-14 Jakub Jelinek <jakub@redhat.com>
658 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
660 2024-03-14 Jakub Jelinek <jakub@redhat.com>
662 PR middle-end/113907
663 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
664 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
665 functions.
667 2024-03-14 Xi Ruoyao <xry111@xry111.site>
669 * config/loongarch/loongarch.md (any_ge): Remove.
670 (sge<u>_<X:mode><GPR:mode>): Remove.
672 2024-03-14 Jakub Jelinek <jakub@redhat.com>
674 PR target/114310
675 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
676 TImode force newval into a register.
678 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
680 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
681 (OMP_CLAUSE__CACHE__READONLY): New macro.
682 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
683 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
684 OMP_CLAUSE__CACHE__READONLY.
685 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
686 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
688 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
690 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
691 for misaligned symbols.
692 * config/s390/s390.opt: Improve documentation.
694 2024-03-14 Jakub Jelinek <jakub@redhat.com>
696 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
697 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
698 are computed, recompute immediate dominator of other_edge->src
699 and other_edge->dest.
700 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
701 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
702 with update it for bb splitting.
704 2024-03-14 liuhongt <hongtao.liu@intel.com>
706 * config/i386/i386-features.cc
707 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
708 (convert_scalars_to_vector): Ditto.
709 * config/i386/i386-features.h (class scalar_chain): New
710 memeber control_flow_insns.
712 2024-03-13 Jakub Jelinek <jakub@redhat.com>
714 PR middle-end/114319
715 * gimple-ssa-store-merging.cc
716 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
717 allow matching __builtin_bswap64 if there is bswapsi2 optab.
719 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
721 * config/s390/s390.cc (s390_secondary_reload): Guard
722 SYMBOL_FLAG_NOTALIGN2_P.
724 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
726 * config/s390/s390-builtin-types.def: Update to reflect latest
727 changes.
728 * config/s390/s390-builtins.def: Streamline vector builtins with
729 LLVM.
731 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
733 * config/s390/s390-builtins.def (vec_permi): Deprecate.
734 (vec_ctd): Deprecate.
735 (vec_ctd_s64): Deprecate.
736 (vec_ctd_u64): Deprecate.
737 (vec_ctsl): Deprecate.
738 (vec_ctul): Deprecate.
739 (vec_ld2f): Deprecate.
740 (vec_st2f): Deprecate.
741 (vec_insert): Deprecate overloads with bool vectors.
743 2024-03-13 Jakub Jelinek <jakub@redhat.com>
745 PR middle-end/114313
746 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
747 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
748 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
749 rhs_type to limb_access for the bitfield load cases.
750 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
751 lhs_type to limb_access if nlhs is non-NULL.
753 2024-03-13 Jakub Jelinek <jakub@redhat.com>
755 PR sanitizer/112709
756 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
757 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
758 gsi_safe_insert_before instead of gsi_insert_before.
760 2024-03-13 Jakub Jelinek <jakub@redhat.com>
762 PR sanitizer/112709
763 * gimple-iterator.h (gsi_safe_insert_before,
764 gsi_safe_insert_seq_before): Declare.
765 * gimple-iterator.cc: Include gimplify.h.
766 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
767 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
768 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
769 instrument_nonnull_arg, instrument_nonnull_return): Use
770 gsi_safe_insert_before instead of gsi_insert_before.
771 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
772 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
773 instead of force_gimple_operand_gsi.
774 (instrument_object_size): Likewise. Use gsi_safe_insert_before
775 instead of gsi_insert_before.
777 2024-03-12 Richard Biener <rguenther@suse.de>
779 PR tree-optimization/114121
780 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
781 converted operand properly.
782 (chrec_fold_multiply): Likewise. Handle missed recursion.
784 2024-03-12 Jakub Jelinek <jakub@redhat.com>
786 PR sanitizer/112709
787 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
788 stores on the caller side unless it is a call to a builtin or
789 internal function or function doesn't return by hidden reference.
790 (maybe_instrument_call): Likewise.
791 (instrument_derefs): Instrument stores to RESULT_DECL if
792 returning by hidden reference.
794 2024-03-12 Jakub Jelinek <jakub@redhat.com>
796 PR tree-optimization/114293
797 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
798 max is smaller than min, set max to ~(size_t)0.
800 2024-03-12 Pan Li <pan2.li@intel.com>
802 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
803 code style greater than 80 chars.
804 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
805 with 3 space(s) and argument unalignment.
807 2024-03-12 Richard Biener <rguenther@suse.de>
809 PR tree-optimization/114297
810 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
811 live stmts SLP node to vect_create_epilog_for_reduction.
813 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
815 PR driver/114314
816 * common.opt (fmultiflags): Add RejectNegative.
818 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
820 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
821 * config/aarch64/aarch64.opt: Likewise.
822 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
823 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
824 (aarch64_expand_epilogue): Likewise.
825 (aarch64_post_cfi_startproc): Likewise.
826 (aarch64_handle_no_branch_protection): Copy and rename.
827 (aarch64_handle_standard_branch_protection): Likewise.
828 (aarch64_handle_pac_ret_protection): Likewise.
829 (aarch64_handle_pac_ret_leaf): Likewise.
830 (aarch64_handle_pac_ret_b_key): Likewise.
831 (aarch64_handle_bti_protection): Likewise.
832 (aarch64_override_options): Update branch protection validation.
833 (aarch64_handle_attr_branch_protection): Likewise.
834 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
835 Pass branch protection type description as argument.
836 (struct aarch_branch_protect_type): Move from aarch-common.h.
837 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
838 Remove.
839 (aarch_handle_standard_branch_protection): Remove.
840 (aarch_handle_pac_ret_protection): Remove.
841 (aarch_handle_pac_ret_leaf): Remove.
842 (aarch_handle_pac_ret_b_key): Remove.
843 (aarch_handle_bti_protection): Remove.
844 (aarch_validate_mbranch_protection): Pass branch protection type
845 description as argument.
846 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
847 (struct aarch_branch_protect_type): Remove.
848 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
849 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
850 (arm_handle_standard_branch_protection): Likewise.
851 (arm_handle_pac_ret_protection): Likewise.
852 (arm_handle_pac_ret_leaf): Likewise.
853 (arm_handle_bti_protection): Likewise.
854 (arm_configure_build_target): Update branch protection validation.
855 * config/arm/arm.opt: Remove aarch_ra_sign_key.
857 2024-03-11 Richard Biener <rguenther@suse.de>
859 PR middle-end/114299
860 * gimplify.cc (internal_get_tmp_var): When gimplification
861 of VAL failed, return a decl.
863 2024-03-11 Jakub Jelinek <jakub@redhat.com>
865 PR tree-optimization/114278
866 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
867 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
869 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
871 PR debug/113519
872 PR debug/113777
873 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
874 generate the DIE with the same parent as in the regular case.
876 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
878 PR middle-end/95351
879 * fold-const.cc (merge_truthop_with_opposite_arm): Use
880 the type of the operands of the comparison and not the type
881 of the comparison.
883 2024-03-10 jlaw <jeffreyalaw@gmail.com>
885 PR tree-optimization/110199
886 * tree-ssa-scopedtables.cc
887 (avail_exprs_stack::simplify_binary_operation): Generalize handling
888 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
889 comparison operands for other cases.
891 2024-03-10 Pan Li <pan2.li@intel.com>
893 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
894 during transform process.
895 (vectorizable_load): Ditto.
897 2024-03-10 jlaw <jeffreyalaw@gmail.com>
899 PR target/102250
900 * doc/install.texi: Document need for python when building
901 RISC-V compilers.
903 2024-03-10 jlaw <jeffreyalaw@gmail.com>
905 PR target/111362
906 * mode-switching.cc (optimize_mode_switching): Only process
907 NONDEBUG insns.
909 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
911 * config/avr/avr.md: Fix typos in comment, indentation glitches
912 and some other nits.
914 2024-03-09 Jakub Jelinek <jakub@redhat.com>
916 PR target/114284
917 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
918 src containing MEMs unless prop.likely_profitable_p ().
920 2024-03-09 Xi Ruoyao <xry111@xry111.site>
922 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
923 Support 'Q' for R_LARCH_RELAX for TLS IE.
924 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
925 IE.
926 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
928 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
930 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
931 usum_widenqihi and add_zero_extend1.
932 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
933 sub+sign_extend.
934 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
935 Compute exact insn lengths.
936 (*usum_widenqihi3): Allow input operands to commute.
938 2024-03-09 Jakub Jelinek <jakub@redhat.com>
940 * config/i386/i386.opt.urls: Regenerate.
942 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
944 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
945 In loongarch64, a sign extension operation is added when
946 operands[2] is a register operand and the mode is SImode.
948 2024-03-08 Martin Jambor <mjambor@suse.cz>
950 PR ipa/113757
951 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
952 id->killed_new_ssa_names.
954 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
956 PR target/113790
957 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
958 for non-reload pseudo too.
960 2024-03-08 David Faust <david.faust@oracle.com>
962 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
963 not attempt inline expansion if size is above threshold.
964 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
965 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
966 Document.
968 2024-03-08 Richard Biener <rguenther@suse.de>
970 PR tree-optimization/114269
971 PR tree-optimization/114074
972 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
973 in the third CASE_CONVERT case as well.
974 (chrec_fold_multiply): Handle sign-conversions from unsigned
975 by performing the operation in the unsigned type.
977 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
979 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
980 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
982 2024-03-08 Jakub Jelinek <jakub@redhat.com>
984 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
985 asm_noperands < 0 means it is not asm goto too.
987 2024-03-08 Jakub Jelinek <jakub@redhat.com>
989 PR target/38534
990 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
991 option.
992 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
993 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
994 ix86_noreturn_no_callee_saved_registers is enabled.
995 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
997 2024-03-08 Jakub Jelinek <jakub@redhat.com>
999 PR debug/113918
1000 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
1001 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
1003 2024-03-08 demin.han <demin.han@starfivetech.com>
1005 PR target/114264
1006 * config/riscv/riscv-vector-costs.cc: Fix ICE
1008 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
1010 * fwprop.cc (forward_propagate_into): Return false for volatile set
1011 source rtx.
1013 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
1015 PR target/113618
1016 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
1017 (aarch64_expand_cpymem): Emit single load/store only.
1018 (aarch64_set_one_block): Emit single stores only.
1020 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
1022 PR middle-end/114196
1023 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
1024 vectorization guards.
1026 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
1028 * doc/cppopts.texi: Remove incorrect claim about -dD not
1029 outputting predefined macros.
1031 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
1033 PR target/113950
1034 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
1035 and simplify else if with else.
1037 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
1039 * system.h: Include safe-ctype.h after C++ standard headers.
1041 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1043 PR rtl-optimization/110079
1044 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
1045 asm goto.
1047 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1049 PR middle-end/105533
1050 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
1051 if val is not HOST_WIDE_INT_MIN or if mode has exactly
1052 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
1053 val - 1.
1055 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1057 PR middle-end/105533
1058 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
1059 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
1060 LOG2_BITS_PER_UNIT.
1062 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
1064 * config.gcc: Add a case for loongarch*-*-linux-musl*.
1065 * config/loongarch/linux.h: Disable the multilib-compatible
1066 treatment for *musl* targets.
1067 * config/loongarch/musl.h: New file.
1069 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1071 PR tree-optimization/114009
1072 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
1073 argument even for GENERIC, not just for GIMPLE.
1074 * match.pd (a * !a -> 0): New simplifications.
1076 2024-03-07 demin.han <demin.han@starfivetech.com>
1078 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
1079 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
1080 (expand_vec_cmp_float): Adapt arguments
1082 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1084 PR target/114232
1085 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
1086 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1087 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1088 (<plusminus:insn>v2qi3): Enable for optimize_size instead
1089 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1090 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1091 (<any_shift:insn>v2qi3): Enable for optimize_size instead
1092 of optimize_function_for_size_p.
1094 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1096 PR target/114200
1097 PR target/114202
1098 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
1100 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1102 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
1103 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
1104 offset handling.
1105 (costs::add_stmt_cost): Also adjust cost for statements without
1106 stmt_info.
1107 * config/riscv/riscv-vector-costs.h: Define zero constant.
1109 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
1111 PR target/113915
1112 * config/arm/arm.md (NOCOND): Improve comment.
1113 (arm_rev*) Add predicable.
1114 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
1115 PREDICABLE_YES.
1117 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
1119 PR target/113001
1120 PR target/112871
1121 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
1122 operands when the comparison operand is the same as the false
1123 arm for a NE test.
1125 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1127 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
1128 Eliminate common code and use generic code instead.
1130 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
1132 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
1133 rtx cost.
1135 2024-03-06 Richard Biener <rguenther@suse.de>
1137 PR tree-optimization/114239
1138 * tree-vect-loop.cc (vect_get_vect_def): Remove.
1139 (vect_create_epilog_for_reduction): The passed in stmt_info
1140 should now be the live stmt that produces the scalar reduction
1141 result. Revert PR114192 fix. Base reduction info off
1142 info_for_reduction. Remove special handling of
1143 early-break/peeled, restore original vector def gathering.
1144 Make sure to pick the correct exit PHIs.
1145 (vectorizable_live_operation): Pass in the proper stmt_info
1146 for early break exits.
1148 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
1150 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
1151 out-of-class definitions of static constants.
1153 2024-03-06 Richard Biener <rguenther@suse.de>
1155 PR tree-optimization/114249
1156 * tree-vect-slp.cc (vect_build_slp_instance): Move making
1157 a BB reduction lane number even ...
1158 (vect_slp_check_for_roots): ... here to avoid leaking
1159 pattern defs.
1161 2024-03-06 Richard Biener <rguenther@suse.de>
1163 PR tree-optimization/114246
1164 * tree-ssa-dse.cc (increment_start_addr): Strip useless
1165 type conversions from the adjusted address.
1167 2024-03-06 Jakub Jelinek <jakub@redhat.com>
1169 PR rtl-optimization/114190
1170 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1171 Call df_remove_problem for df_note before calling df_analyze.
1173 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
1174 Indu Bhagat <indu.bhagat@oracle.com>
1176 PR debug/114186
1177 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
1178 in the correct order of the dimensions.
1179 (gen_ctf_subrange_type): Refactor out handling of
1180 DW_TAG_subrange_type DIE to here.
1182 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1184 PR sanitizer/97696
1185 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
1187 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1189 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
1190 and luti_strided.
1191 * config/aarch64/aarch64-sme.md
1192 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
1193 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
1194 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
1195 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
1196 (early_ra::maybe_convert_to_strided_access): Remove support for
1197 strided LUTI2 and LUTI4.
1199 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
1201 PR target/113510
1202 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
1203 low_register_operand.
1205 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
1207 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
1208 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
1209 to "X = Y, X o= CST".
1211 2024-03-05 Xi Ruoyao <xry111@xry111.site>
1213 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
1214 s9 as an alias of r22.
1216 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
1218 * config/avr/avr-protos.h (avr_out_insv): New proto.
1219 * config/avr/avr.cc (avr_out_insv): New function.
1220 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
1221 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
1222 * config/avr/avr.md (define_attr "adjust_len") Add insv.
1223 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
1224 Add constraint alternative where the 3rd operand is a power
1225 of 2, and the source register may differ from the destination.
1226 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
1227 instructions. Set attr "length" to "insv".
1228 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
1230 2024-03-05 Richard Biener <rguenther@suse.de>
1232 PR tree-optimization/114231
1233 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
1234 processing a BB SLP root.
1236 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1238 PR rtl-optimization/114211
1239 * lower-subreg.cc (resolve_simple_move): For double-word
1240 rotates by BITS_PER_WORD if there is overlap between source
1241 and destination use a temporary.
1243 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1245 PR middle-end/114157
1246 * gimple-lower-bitint.cc: Include stor-layout.h.
1247 (mergeable_op): Return true for BIT_FIELD_REF.
1248 (struct bitint_large_huge): Declare handle_bit_field_ref method.
1249 (bitint_large_huge::handle_bit_field_ref): New method.
1250 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
1252 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1254 PR target/114116
1255 * config/i386/i386.h (enum call_saved_registers_type): Add
1256 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
1257 * config/i386/i386-options.cc (ix86_set_func_type): Remove
1258 has_no_callee_saved_registers variable, add no_callee_saved_registers
1259 instead, initialize it depending on whether it is
1260 no_callee_saved_registers function or not. Don't set it if
1261 no_caller_saved_registers attribute is present. Adjust users.
1262 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
1263 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
1264 TYPE_NO_CALLEE_SAVED_REGISTERS.
1265 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
1267 2024-03-05 Pan Li <pan2.li@intel.com>
1269 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
1270 mode_size related code.
1272 2024-03-05 Patrick Palka <ppalka@redhat.com>
1274 * doc/invoke.texi (-Wno-global-module): Document.
1276 2024-03-04 David Faust <david.faust@oracle.com>
1278 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
1279 * config/bpf/bpf.cc (bpf_expand_setmem): New.
1280 * config/bpf/bpf.md (setmemdi): New define_expand.
1282 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1284 PR rtl-optimization/113010
1285 * combine.cc (simplify_comparison): Guard the
1286 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
1287 and initialize inner_mode.
1289 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1291 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1292 VMLALDAVAXQ_U cases.
1293 (VMLALDAVXQ): Remove iterator.
1294 (VMLALDAVXQ_P): Likewise.
1295 (VMLALDAVAXQ): Likewise.
1296 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
1297 mode iterator attribute with V4BI mode.
1298 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1299 VMLALDAVAXQ_U): Remove unused unspecs.
1301 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1303 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
1304 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
1305 attribute.
1306 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
1307 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
1308 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
1309 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
1310 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
1311 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
1312 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
1313 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
1314 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
1315 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
1317 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1319 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
1320 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
1321 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
1322 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
1323 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
1324 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
1325 (arm_vcx1q<a>v16qi): Likewise.
1326 (arm_vcx1qav16qi): Likewise.
1327 (arm_vcx1qv16qi): Likewise.
1328 (arm_vcx2q<a>_p_v16qi): Likewise.
1329 (arm_vcx2q<a>v16qi): Likewise.
1330 (arm_vcx2qav16qi): Likewise.
1331 (arm_vcx2qv16qi): Likewise.
1332 (arm_vcx3q<a>_p_v16qi): Likewise.
1333 (arm_vcx3q<a>v16qi): Likewise.
1334 (arm_vcx3qav16qi): Likewise.
1335 (arm_vcx3qv16qi): Likewise.
1336 (@mve_<mve_insn>q_<supf><mode>): Likewise.
1337 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
1338 (@mve_<mve_insn>q_<supf>v4si): Likewise.
1339 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
1340 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
1341 (@mve_<mve_insn>q_f<mode>): Likewise.
1342 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
1343 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
1344 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
1345 (@mve_<mve_insn>q_m_f<mode>): Likewise.
1346 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
1347 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
1348 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
1349 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
1350 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
1351 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
1352 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
1353 (mve_v<absneg_str>q_f<mode>): Likewise.
1354 (mve_<mve_addsubmul>q<mode>): Likewise.
1355 (mve_<mve_addsubmul>q_f<mode>): Likewise.
1356 (mve_vadciq_<supf>v4si): Likewise.
1357 (mve_vadciq_m_<supf>v4si): Likewise.
1358 (mve_vadcq_<supf>v4si): Likewise.
1359 (mve_vadcq_m_<supf>v4si): Likewise.
1360 (mve_vandq_<supf><mode>): Likewise.
1361 (mve_vandq_f<mode>): Likewise.
1362 (mve_vandq_m_<supf><mode>): Likewise.
1363 (mve_vandq_m_f<mode>): Likewise.
1364 (mve_vandq_s<mode>): Likewise.
1365 (mve_vandq_u<mode>): Likewise.
1366 (mve_vbicq_<supf><mode>): Likewise.
1367 (mve_vbicq_f<mode>): Likewise.
1368 (mve_vbicq_m_<supf><mode>): Likewise.
1369 (mve_vbicq_m_f<mode>): Likewise.
1370 (mve_vbicq_m_n_<supf><mode>): Likewise.
1371 (mve_vbicq_n_<supf><mode>): Likewise.
1372 (mve_vbicq_s<mode>): Likewise.
1373 (mve_vbicq_u<mode>): Likewise.
1374 (@mve_vclzq_s<mode>): Likewise.
1375 (mve_vclzq_u<mode>): Likewise.
1376 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
1377 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
1378 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
1379 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
1380 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
1381 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
1382 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
1383 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
1384 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
1385 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
1386 (mve_vcvtaq_<supf><mode>): Likewise.
1387 (mve_vcvtaq_m_<supf><mode>): Likewise.
1388 (mve_vcvtbq_f16_f32v8hf): Likewise.
1389 (mve_vcvtbq_f32_f16v4sf): Likewise.
1390 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
1391 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
1392 (mve_vcvtmq_<supf><mode>): Likewise.
1393 (mve_vcvtmq_m_<supf><mode>): Likewise.
1394 (mve_vcvtnq_<supf><mode>): Likewise.
1395 (mve_vcvtnq_m_<supf><mode>): Likewise.
1396 (mve_vcvtpq_<supf><mode>): Likewise.
1397 (mve_vcvtpq_m_<supf><mode>): Likewise.
1398 (mve_vcvtq_from_f_<supf><mode>): Likewise.
1399 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
1400 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
1401 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
1402 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
1403 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
1404 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
1405 (mve_vcvtq_to_f_<supf><mode>): Likewise.
1406 (mve_vcvttq_f16_f32v8hf): Likewise.
1407 (mve_vcvttq_f32_f16v4sf): Likewise.
1408 (mve_vcvttq_m_f16_f32v8hf): Likewise.
1409 (mve_vcvttq_m_f32_f16v4sf): Likewise.
1410 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
1411 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
1412 (mve_veorq_s><mode>): Likewise.
1413 (mve_veorq_u><mode>): Likewise.
1414 (mve_veorq_f<mode>): Likewise.
1415 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
1416 (mve_vidupq_u<mode>_insn): Likewise.
1417 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
1418 (mve_viwdupq_wb_u<mode>_insn): Likewise.
1419 (mve_vldrbq_<supf><mode>): Likewise.
1420 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
1421 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
1422 (mve_vldrbq_z_<supf><mode>): Likewise.
1423 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
1424 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
1425 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
1426 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
1427 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
1428 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
1429 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
1430 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
1431 (mve_vldrhq_<supf><mode>): Likewise.
1432 (mve_vldrhq_fv8hf): Likewise.
1433 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
1434 (mve_vldrhq_gather_offset_fv8hf): Likewise.
1435 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
1436 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
1437 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
1438 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
1439 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
1440 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
1441 (mve_vldrhq_z_<supf><mode>): Likewise.
1442 (mve_vldrhq_z_fv8hf): Likewise.
1443 (mve_vldrwq_<supf>v4si): Likewise.
1444 (mve_vldrwq_fv4sf): Likewise.
1445 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
1446 (mve_vldrwq_gather_base_fv4sf): Likewise.
1447 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
1448 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
1449 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
1450 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
1451 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
1452 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
1453 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
1454 (mve_vldrwq_gather_offset_fv4sf): Likewise.
1455 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
1456 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
1457 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
1458 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
1459 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
1460 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
1461 (mve_vldrwq_z_<supf>v4si): Likewise.
1462 (mve_vldrwq_z_fv4sf): Likewise.
1463 (mve_vmvnq_s<mode>): Likewise.
1464 (mve_vmvnq_u<mode>): Likewise.
1465 (mve_vornq_<supf><mode>): Likewise.
1466 (mve_vornq_f<mode>): Likewise.
1467 (mve_vornq_m_<supf><mode>): Likewise.
1468 (mve_vornq_m_f<mode>): Likewise.
1469 (mve_vornq_s<mode>): Likewise.
1470 (mve_vornq_u<mode>): Likewise.
1471 (mve_vorrq_<supf><mode>): Likewise.
1472 (mve_vorrq_f<mode>): Likewise.
1473 (mve_vorrq_m_<supf><mode>): Likewise.
1474 (mve_vorrq_m_f<mode>): Likewise.
1475 (mve_vorrq_m_n_<supf><mode>): Likewise.
1476 (mve_vorrq_n_<supf><mode>): Likewise.
1477 (mve_vorrq_s<mode>): Likewise.
1478 (mve_vorrq_s<mode>): Likewise.
1479 (mve_vsbciq_<supf>v4si): Likewise.
1480 (mve_vsbciq_m_<supf>v4si): Likewise.
1481 (mve_vsbcq_<supf>v4si): Likewise.
1482 (mve_vsbcq_m_<supf>v4si): Likewise.
1483 (mve_vshlcq_<supf><mode>): Likewise.
1484 (mve_vshlcq_m_<supf><mode>): Likewise.
1485 (mve_vshrq_m_n_<supf><mode>): Likewise.
1486 (mve_vshrq_n_<supf><mode>): Likewise.
1487 (mve_vstrbq_<supf><mode>): Likewise.
1488 (mve_vstrbq_p_<supf><mode>): Likewise.
1489 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
1490 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
1491 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
1492 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
1493 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
1494 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
1495 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
1496 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
1497 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
1498 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
1499 (mve_vstrhq_<supf><mode>): Likewise.
1500 (mve_vstrhq_fv8hf): Likewise.
1501 (mve_vstrhq_p_<supf><mode>): Likewise.
1502 (mve_vstrhq_p_fv8hf): Likewise.
1503 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
1504 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
1505 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
1506 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
1507 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
1508 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
1509 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
1510 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
1511 (mve_vstrwq_<supf>v4si): Likewise.
1512 (mve_vstrwq_fv4sf): Likewise.
1513 (mve_vstrwq_p_<supf>v4si): Likewise.
1514 (mve_vstrwq_p_fv4sf): Likewise.
1515 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
1516 (mve_vstrwq_scatter_base_fv4sf): Likewise.
1517 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
1518 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
1519 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
1520 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
1521 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
1522 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
1523 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
1524 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
1525 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
1526 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
1527 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
1528 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
1529 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
1530 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
1532 2024-03-04 Marek Polacek <polacek@redhat.com>
1534 * doc/extend.texi: Update [[gnu::no_dangling]].
1536 2024-03-04 Andrew Stubbs <ams@baylibre.com>
1538 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
1539 * expr.cc (store_constructor): Likewise.
1540 (do_store_flag): Likewise.
1542 2024-03-04 Mark Wielaard <mark@klomp.org>
1544 * common.opt.urls: Regenerate.
1545 * config/avr/avr.opt.urls: Likewise.
1546 * config/i386/i386.opt.urls: Likewise.
1547 * config/pru/pru.opt.urls: Likewise.
1548 * config/riscv/riscv.opt.urls: Likewise.
1549 * config/rs6000/rs6000.opt.urls: Likewise.
1551 2024-03-04 Richard Biener <rguenther@suse.de>
1553 PR tree-optimization/114197
1554 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
1555 there are volatile bitfield accesses.
1556 (pass_if_conversion::execute): Throw away result if the
1557 if-converted and original loops are not nested as expected.
1559 2024-03-04 Richard Biener <rguenther@suse.de>
1561 PR tree-optimization/114164
1562 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
1563 the code generated for mask argument setup is not supported.
1565 2024-03-04 Richard Biener <rguenther@suse.de>
1567 PR tree-optimization/114203
1568 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
1569 adjustment before making the result defined at zero.
1571 2024-03-04 Richard Biener <rguenther@suse.de>
1573 PR tree-optimization/114192
1574 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
1575 appropriate def for the live out stmt in case of an alternate
1576 exit.
1578 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1580 PR middle-end/114209
1581 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
1582 unshare_expr when creating a MEM_REF from MEM_REF.
1583 (bitint_large_huge::lower_stmt): Call unshare_expr.
1585 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1587 PR target/114184
1588 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
1589 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
1590 register.
1592 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
1594 PR target/114187
1595 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
1596 lowpart_subreg to perform type conversion, to avoid confusion
1597 over the offset to use in the call to simplify_reg_subreg.
1599 2024-03-03 Greg McGary <gkm@rivosinc.com>
1601 PR rtl-optimization/113010
1602 * combine.cc (simplify_comparison): Simplify a SUBREG on
1603 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
1604 MEM load.
1606 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1608 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
1609 Use bool in place of int for boolean logic (if possible).
1610 Move declarations to definitions (if possible).
1611 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
1612 * config/avr/avr-dimode.md: Same.
1613 * config/avr/constraints.md: Same.
1614 * config/avr/predicates.md: Same.
1616 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
1618 PR target/113720
1619 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
1620 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
1621 simplify insn RTX using UMUL_HIGHPART rtx_code.
1622 (*umuldi3_highpart_const): Remove.
1624 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1626 PR target/114100
1627 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
1628 * config/avr/avr.cc (_reg_unused_after): Make static. And
1629 add 3rd argument to skip the current insn.
1630 (reg_unused_after): Adjust call of reg_unused_after.
1631 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
1632 unneeded frame pointer adjustments.
1634 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1636 PR target/92729
1637 * config/avr/avr.md (define_attr "cc"): Remove.
1638 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
1639 from prototype.
1640 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
1641 its uses. Add insn argument.
1642 (avr_out_plus_symbol): Remove pcc argument and its uses.
1643 (avr_out_plus): Remove pcc argument and its uses.
1644 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
1645 (avr_out_round): Adjust call of avr_out_plus.
1647 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1649 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
1650 from r14-9273.
1652 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
1654 PR target/101737
1655 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
1656 is not an insn, but e.g. a code label.
1658 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1660 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
1661 * config/avr/avr.cc: Use them instead of magic numbers when it
1662 means a register number.
1664 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1666 * config/avr/avr.cc: Adjust some comments.
1668 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1670 PR target/114100
1671 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
1672 the low part of the frame pointer with 8-bit stack pointer.
1674 2024-03-01 Patrick Palka <ppalka@redhat.com>
1676 PR c++/104919
1677 PR c++/106009
1678 * tree-inline.cc (remap_decl): Handle copy_decl returning the
1679 original decl.
1680 (remap_decls): Handle remap_decl returning the original decl.
1681 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
1682 CONST_DECL.
1684 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
1686 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
1687 type attribute.
1688 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
1689 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
1690 (movhi_internal, movqi_internal): Likewise.
1691 (movsf_softfloat, movsf_hardfloat): Likewise.
1692 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
1693 (movdf_softfloat): Likewise.
1695 2024-03-01 Marek Polacek <polacek@redhat.com>
1697 PR c++/110358
1698 PR c++/109642
1699 * doc/extend.texi: Document gnu::no_dangling.
1700 * doc/invoke.texi: Mention that gnu::no_dangling disables
1701 -Wdangling-reference.
1703 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1705 * config/avr/avr.opt: Overhaul help screen.
1707 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1708 Tobias Burnus <tburnus@baylibre.com>
1710 PR c++/110347
1711 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
1712 lang_hooks.decls.omp_disregard_value_expr for
1713 (first)private in target regions.
1715 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1717 PR middle-end/114136
1718 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
1719 n_named_args initially before INIT_CUMULATIVE_ARGS to
1720 structure_value_addr_parm rather than 0, after it don't modify
1721 it if strict_argument_naming and clear only if
1722 !pretend_outgoing_varargs_named.
1724 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1726 PR debug/114015
1727 * dwarf2out.cc (should_move_die_to_comdat): Return false for
1728 aggregates without DW_AT_byte_size attribute or with non-constant
1729 DW_AT_byte_size.
1731 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1733 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
1734 valid values for level.
1736 2024-03-01 Richard Biener <rguenther@suse.de>
1738 PR middle-end/114070
1739 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
1740 Allow the folding if before lowering and the current IL
1741 isn't supported with vcond_mask.
1743 2024-03-01 xuli <xuli1@eswincomputing.com>
1745 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
1746 attribute to riscv_attribute_table.
1747 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
1748 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
1749 * doc/extend.texi: Add riscv_vector_cc attribute description.
1751 2024-03-01 Pan Li <pan2.li@intel.com>
1753 PR target/112817
1754 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
1755 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
1756 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
1757 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
1758 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
1759 comments for option replacement.
1760 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
1761 riscv_autovec_preference to rvv_vector_bits.
1762 (vls_mode_valid_p): Ditto.
1763 (estimated_poly_value): Ditto.
1764 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
1765 vector chunks and honor new option mrvv-vector-bits.
1766 (riscv_override_options_internal): Update comments and rename the
1767 vector chunks.
1768 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
1769 internal option param=riscv-autovec-preference.
1771 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1773 * function.cc (assign_parms): Only call assign_parms_setup_varargs
1774 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
1776 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1778 PR middle-end/114156
1779 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
1780 rhs1 of a VCE to have no underlying variable if it is a load and
1781 handle that case.
1783 2024-02-29 David Malcolm <dmalcolm@redhat.com>
1785 PR analyzer/114159
1786 * function.cc (function_name): Make param const.
1787 * function.h (function_name): Likewise.
1789 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1791 PR target/114100
1792 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
1793 * config/avr/avr.opt (-mfuse-add=): New target option.
1794 * common/config/avr/avr-common.cc (avr_option_optimization_table)
1795 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
1796 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
1797 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
1798 * config/avr/avr-protos.h (avr_split_tiny_move)
1799 (make_avr_pass_fuse_add): New protos.
1800 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
1801 avr_split_tiny_move to split indirect memory accesses.
1802 (gen_move_clobbercc): New define_expand helper.
1803 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
1804 (avr_pass_fuse_add): New class from rtl_opt_pass.
1805 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
1806 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
1807 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
1808 of PLUS addressing for AVR_TINY.
1809 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
1810 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
1811 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
1813 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1815 PR target/114132
1816 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
1817 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
1818 (avr_function_arg): Set it.
1819 (avr_frame_pointer_required_p): Use it instead of .nregs.
1821 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
1823 PR target/108174
1824 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
1825 static and mark with GTY.
1827 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1829 * config/loongarch/loongarch.md
1830 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
1832 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1834 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
1835 (crc): New define_int_attr.
1836 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
1837 into ...
1838 (loongarch_<crc>_w_<size>_w): ... here.
1840 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
1842 PR target/114130
1843 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
1844 extend the expected value if needed.
1846 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1848 * config.gcc (target_gtfiles): Change coreout to btfext-out.
1849 (extra_objs): Change coreout to btfext-out.
1850 * config/bpf/coreout.cc: Rename to btfext-out.cc.
1851 * config/bpf/btfext-out.cc: Add.
1852 * config/bpf/coreout.h: Rename to btfext-out.h.
1853 * config/bpf/btfext-out.h: Add.
1854 * config/bpf/core-builtins.cc: Change include.
1855 * config/bpf/core-builtins.h: Change include.
1856 * config/bpf/t-bpf: Accomodate renamed files.
1858 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1860 PR target/113453
1861 * config/bpf/bpf.cc (bpf_function_prologue): Define target
1862 hook.
1863 * config/bpf/coreout.cc (brf_ext_info_section)
1864 (btf_ext_info): Move from coreout.h
1865 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
1866 (bpf_core_reloc): Rename to btf_ext_core_reloc.
1867 (btf_ext): Add static variable.
1868 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
1869 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
1870 (btf_ext_add_string, btf_funcinfo_type_callback)
1871 (btf_add_func_info_for, btf_validate_funcinfo)
1872 (btf_ext_info_len, output_btfext_func_info): Add function.
1873 (output_btfext_header, bpf_core_reloc_add)
1874 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
1875 Change to support new structs.
1876 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
1877 Move and change in coreout.cc.
1878 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
1880 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1882 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
1883 enabled by default for BPF.
1884 (bpf_file_end): Call BTF deallocation.
1885 (bpf_asm_init_sections): Correct condition.
1886 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
1887 deallocation.
1888 (ctf_debuf_finish): Correct condition for calling
1889 ctf_debug_finalize.
1891 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1893 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
1894 (traverse_btf_func_types): Define function.
1895 * ctfc.h (funcs_traverse_callback): Typedef for function
1896 prototype.
1897 (traverse_btf_func_types): Add prototype.
1899 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1901 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
1903 2024-02-28 Richard Biener <rguenther@suse.de>
1905 PR tree-optimization/113831
1906 PR tree-optimization/108355
1907 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
1908 PR113831 fix.
1910 2024-02-28 Richard Biener <rguenther@suse.de>
1912 PR tree-optimization/114121
1913 * tree-ssa-sccvn.h (vn_reference_s::offset,
1914 vn_reference_s::max_size): New fields.
1915 (vn_reference_insert_pieces): Adjust prototype.
1916 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
1917 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
1918 size, allow using "don't know" state.
1919 (vn_walk_cb_data::finish): Pass along offset/max_size.
1920 (vn_reference_lookup_or_insert_for_pieces): Take offset and
1921 max_size as argument and use it.
1922 (vn_reference_lookup_3): Properly adjust offset and max_size
1923 according to the adjusted ao_ref.
1924 (vn_reference_lookup_pieces): Initialize offset and max_size.
1925 (vn_reference_lookup): Likewise.
1926 (vn_reference_lookup_call): Likewise.
1927 (vn_reference_insert): Likewise.
1928 (visit_reference_op_call): Likewise.
1929 (vn_reference_insert_pieces): Take offset and max_size
1930 as argument and use it.
1932 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
1934 PR tree-optimization/114075
1935 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
1936 point vectors
1938 2024-02-28 Jakub Jelinek <jakub@redhat.com>
1940 PR tree-optimization/114041
1941 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
1942 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
1944 2024-02-28 Jakub Jelinek <jakub@redhat.com>
1946 PR tree-optimization/113988
1947 * stor-layout.h (bitwise_mode_for_size): Declare.
1948 * stor-layout.cc (bitwise_mode_for_size): New function.
1949 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
1950 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
1951 Use BITS_PER_UNIT instead of 8.
1953 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
1955 PR target/113871
1956 * config/i386/mmx.md (V248FI): Add V2BF mode.
1957 (V24FI_32): Ditto.
1959 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
1961 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
1962 if either ref->offset is not byte aligned or ref->size is not known
1963 to be equal to ref->max_size.
1964 (maybe_trim_complex_store): Fix description.
1965 (maybe_trim_constructor_store): Likewise.
1966 (maybe_trim_partially_dead_store): Likewise.
1968 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
1970 * config/arm/mmintrin.h: Warn if this header is included without
1971 defining __ENABLE_DEPRECATED_IWMMXT.
1973 2024-02-27 Richard Biener <rguenther@suse.de>
1975 PR tree-optimization/114074
1976 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
1977 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
1978 Handle poly vs. non-poly multiplication correctly with respect
1979 to undefined behavior on overflow.
1981 2024-02-27 Jakub Jelinek <jakub@redhat.com>
1983 PR rtl-optimization/114044
1984 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
1985 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
1986 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
1987 expand_PARITY): Declare.
1988 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
1989 expand_CTZ, expand_FFS, expand_PARITY): New functions.
1990 (expand_POPCOUNT): Use expand_bitquery.
1992 2024-02-27 Richard Biener <rguenther@suse.de>
1994 PR tree-optimization/114081
1995 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1996 Perform manual dominator update for prologue peeling.
1997 (vect_do_peeling): Properly update dominators after adding the
1998 prologue-around guard.
2000 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2002 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
2003 (mstrict-X): Tag as "Optimization".
2005 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2007 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
2008 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
2010 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2011 H.J. Lu <hjl.tools@gmail.com>
2013 PR rtl-optimization/113617
2014 * varasm.cc (default_elf_select_rtx_section): For
2015 references to private symbols in comdat sections
2016 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
2017 or .rodata.<comdat> comdat sections.
2019 2024-02-26 Richard Biener <rguenther@suse.de>
2021 PR tree-optimization/114099
2022 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2023 Create and fill in a needed virtual LC PHI for the alternate
2024 exits. Remove code dealing with that missing.
2026 2024-02-26 Richard Biener <rguenther@suse.de>
2028 PR tree-optimization/114068
2029 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
2030 New function.
2031 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
2032 on the main exit if needed. Remove band-aid for the case
2033 it was missing.
2035 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2037 PR target/114097
2038 * config/i386/i386-options.cc (ix86_set_func_type): Check
2039 interrupt instead of noreturn attribute.
2041 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2043 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
2044 !TARGET_64BIT.
2046 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2048 PR tree-optimization/114090
2049 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
2050 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
2051 types.
2052 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
2054 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2056 PR middle-end/114084
2057 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
2058 if all subtrees of var0 come from one of the op0 or op1 operands
2059 and all subtrees of con0 come from the other one. Don't clear
2060 variables which are never used afterwards.
2062 2024-02-26 Richard Biener <rguenther@suse.de>
2064 PR middle-end/114070
2065 * genmatch.cc (parser::parse_c_expr): Do not record operand
2066 lists but only mark operators used.
2067 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
2068 Properly guard the case of tcc_comparison changing the VEC_COND
2069 value operand type.
2071 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2073 PR target/114094
2074 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
2075 to printed instruction.
2077 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2079 PR target/114098
2080 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
2081 __builtin_ia32_ldtilecfg.
2082 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
2083 * config/i386/i386-builtin.def (BDESC): Add
2084 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
2085 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
2086 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
2087 * config/i386/i386.md (ldtilecfg): New pattern.
2088 (sttilecfg): Likewise.
2090 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
2092 PR tree-optimization/113205
2093 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
2094 the proposed layout if it does not allow a source partition with
2095 layout 2 to keep that layout.
2097 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2099 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
2100 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
2101 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
2102 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
2103 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
2104 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
2105 macros.
2106 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
2107 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
2108 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
2109 HOST_WIDE_INT_UC macros.
2110 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
2111 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
2112 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
2113 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
2114 macros.
2115 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
2116 * config/i386/constraints.md (define_constraint "L"): Use
2117 HOST_WIDE_INT_C macro.
2118 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
2119 macro.
2120 (movl + movb peephole2): Likewise.
2121 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
2122 (const_32bit_mask): Likewise.
2124 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2126 PR middle-end/114073
2127 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
2128 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
2129 types like vector or complex types.
2130 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
2131 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
2132 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
2134 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
2136 PR target/114028
2137 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
2138 Return false if inner mode is already Pmode.
2139 (rvv_builder::is_all_same_sequence): New function.
2140 (expand_vec_init): Emit broadcast if sequence is all same.
2142 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2144 PR target/113613
2145 * config/aarch64/aarch64-early-ra.cc
2146 (early_ra::m_current_region): New member variable.
2147 (early_ra::m_fpr_recency): Likewise.
2148 (early_ra::start_new_region): Bump m_current_region.
2149 (early_ra::allocate_colors): Prefer less recently used registers
2150 in the event of a tie. Add a comment to explain why we prefer(ed)
2151 higher-numbered registers.
2152 (early_ra::find_oldest_color): Prefer less recently used registers
2153 here too.
2154 (early_ra::finalize_allocation): Update recency information for
2155 allocated registers.
2156 (early_ra::process_blocks): Initialize m_current_region and
2157 m_fpr_recency.
2159 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2161 PR target/113295
2162 * config/aarch64/aarch64-early-ra.cc
2163 (early_ra::test_strictness): New enum.
2164 (early_ra::is_chain_candidate): Add a strictness parameter to
2165 control whether only correctness matters, or whether both correctness
2166 and heuristics should be used. Handle multiple levels of equivalence.
2167 (early_ra::find_related_start): Update call accordingly.
2168 (early_ra::strided_polarity_pref): Likewise.
2169 (early_ra::form_chains): Likewise.
2170 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
2171 correctness mode rather than trying to inline the test.
2173 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2175 PR target/113295
2176 * config/aarch64/aarch64-early-ra.cc
2177 (early_ra::find_related_start): Account for definitions by shared
2178 registers when testing for a single register definition.
2179 (early_ra::accumulate_defs): New function.
2180 (early_ra::record_copy): If A shares B's register, fold A's
2181 definition information into B's. Fold A's use information into B's.
2183 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
2185 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
2186 if R_X86_64_CODE_6_GOTTPOFF is supported.
2187 * config.in: Regenerated.
2188 * configure: Likewise.
2189 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
2190 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
2192 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
2194 PR target/108120
2195 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
2196 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
2198 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2200 PR rtl-optimization/114054
2201 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
2202 temp variable instead of target parameter for result.
2204 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2206 PR tree-optimization/114040
2207 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
2208 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
2209 probability from likely to unlikely. When handling the true true
2210 store, first cast to limb_access_type and then to l's type.
2212 2024-02-23 Richard Biener <rguenther@suse.de>
2214 PR target/90785
2215 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
2217 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2219 PR other/109668
2220 * config/riscv/arch-canonicalize: Move to python3
2221 * config/riscv/multilib-generator: Likewise
2223 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2225 * doc/invoke.texi: Document -mcpu.
2227 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
2229 * configure: Regenerate.
2230 * configure.ac: Add parameter "--fatal-warnings" to assemble
2231 when checking whether the assemble support conditional branch
2232 relaxation.
2234 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2236 PR c/114007
2237 * doc/extend.texi: (__extension__): Remove comments about scope
2238 tokens vs. two colons.
2240 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
2242 PR tree-optimization/109804
2243 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
2244 DEMANGLE_COMPONENT_UNNAMED_TYPE.
2246 2024-02-22 Richard Biener <rguenther@suse.de>
2248 PR tree-optimization/114048
2249 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
2250 can also produce -1 off.
2252 2024-02-22 Richard Biener <rguenther@suse.de>
2254 PR tree-optimization/114027
2255 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
2256 condition reduction classification only for single-element
2257 chains.
2259 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2261 PR ipa/111960
2262 * profile-count.h (profile_count::dump): Remove overload with
2263 char * first argument.
2264 * profile-count.cc (profile_count::dump): Change overload with char *
2265 first argument which uses sprintf into the overfload with FILE *
2266 first argument and use fprintf instead. Remove overload which wrapped
2267 it.
2269 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2271 PR tree-optimization/113993
2272 * tree-call-cdce.cc (get_no_error_domain): Handle
2273 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
2274 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
2275 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2276 the as the F128 suffixed cases, otherwise as non-suffixed ones.
2277 Handle BUILT_IN_{EXP,POW}10L for
2278 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2279 as (-inf, 4932).
2281 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2283 PR tree-optimization/114038
2284 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
2285 loop exit condition if end is divisible by limb_prec.
2287 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
2289 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
2290 problem of mabi=, mno-flush-func, mexplicit-relocs;
2291 add missing leading - of mbranch-cost option.
2292 * config/mips/mips.opt.urls: Regenerate.
2294 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
2296 PR target/109987
2297 * config/rs6000/constraints.md (we): Update internal doc without
2298 referring to option -mpower9-vector.
2299 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
2300 special handlings.
2301 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
2302 OTHER_P8_VECTOR_MASKS): Merge to ...
2303 (OTHER_VSX_VECTOR_MASKS): ... here.
2304 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
2305 some error message handlings and explicit option mask adjustments on
2306 explicit option power{8,9}-vector conflicting with other options.
2307 (rs6000_print_isa_options): Update comments.
2308 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
2309 related array items and handlings.
2310 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
2311 special handlings.
2312 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
2313 WarnRemoved.
2314 * doc/extend.texi: Remove documentation referring to option
2315 -mpower8-vector.
2316 * doc/invoke.texi: Remove documentation for option
2317 -mpower{8,9}-vector and adjust some documentation referring to them.
2318 * doc/md.texi: Update documentation for constraint we.
2319 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
2321 2024-02-22 Pan Li <pan2.li@intel.com>
2323 PR target/114017
2324 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
2325 the version to 0.12.
2327 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2329 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
2331 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2332 Robin Dapp <rdapp.gcc@gmail.com>
2334 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2335 (generic_ooo_vec_load): Ditto
2336 (generic_ooo_vec_store): Ditto
2337 (generic_ooo_vec_loadstore_seg): Ditto
2338 (generic_ooo_vec_alu): Ditto
2339 (generic_ooo_vec_fcmp): Ditto
2340 (generic_ooo_vec_imul): Ditto
2341 (generic_ooo_vec_fadd): Ditto
2342 (generic_ooo_vec_fmul): Ditto
2343 (generic_ooo_crypto): Ditto
2344 (generic_ooo_perm): Ditto
2345 (generic_ooo_vec_reduction): Ditto
2346 (generic_ooo_vec_ordered_reduction): Ditto
2347 (generic_ooo_vec_idiv): Ditto
2348 (generic_ooo_vec_float_divsqrt): Ditto
2349 (generic_ooo_vec_mask): Ditto
2350 (generic_ooo_vec_vesetvl): Ditto
2351 (generic_ooo_vec_setrm): Ditto
2352 (generic_ooo_vec_readlen): Ditto
2353 * config/riscv/riscv.md: Include generic-vector-ooo
2354 * config/riscv/generic-vector-ooo.md: New file. To here
2356 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2358 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2359 (generic_ooo_branch): Ditto
2360 * config/riscv/generic.md (generic_sfb_alu): Ditto
2361 (generic_fmul_half): Ditto
2362 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2363 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
2364 (sifive_7_popcount): Ditto
2365 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
2366 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
2367 * config/riscv/vector.md: Change rdfrm to fmove
2368 * config/riscv/zc.md: Change pushpop to load/store
2370 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
2372 * doc/invoke.texi (Warning Options): Fix typos.
2374 2024-02-21 David Faust <david.faust@oracle.com>
2376 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
2377 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
2378 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
2380 2024-02-21 Martin Jambor <mjambor@suse.cz>
2382 PR ipa/113476
2383 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
2384 initializers in the contructor.
2385 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
2386 * ipa-cp.h: New file.
2387 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
2388 (ipcp_value_source): Move to ipa-cp.h.
2389 (ipcp_value_base): Likewise.
2390 (ipcp_value): Likewise.
2391 (ipcp_lattice): Likewise.
2392 (ipcp_agg_lattice): Likewise.
2393 (ipcp_bits_lattice): Likewise.
2394 (ipcp_vr_lattice): Likewise.
2395 (ipcp_param_lattices): Likewise.
2396 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
2397 (ipa_value_from_jfunc): Adjust a check for empty lattices.
2398 (ipa_context_from_jfunc): Likewise.
2399 (ipa_agg_value_from_jfunc): Likewise.
2400 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
2401 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
2402 just in contiguous memory.
2403 (ipcp_store_vr_results): Adjust a check for empty lattices.
2404 * auto-profile.cc: Include sreal.h and ipa-cp.h.
2405 * cgraph.cc: Likewise.
2406 * cgraphclones.cc: Likewise.
2407 * cgraphunit.cc: Likewise.
2408 * config/aarch64/aarch64.cc: Likewise.
2409 * config/i386/i386-builtins.cc: Likewise.
2410 * config/i386/i386-expand.cc: Likewise.
2411 * config/i386/i386-features.cc: Likewise.
2412 * config/i386/i386-options.cc: Likewise.
2413 * config/i386/i386.cc: Likewise.
2414 * config/rs6000/rs6000.cc: Likewise.
2415 * config/s390/s390.cc: Likewise.
2416 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
2417 files to be included in gtype-desc.cc.
2418 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
2419 * ipa-devirt.cc: Likewise.
2420 * ipa-fnsummary.cc: Likewise.
2421 * ipa-icf.cc: Likewise.
2422 * ipa-inline-analysis.cc: Likewise.
2423 * ipa-inline-transform.cc: Likewise.
2424 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
2425 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
2426 * ipa-param-manipulation.cc: Likewise.
2427 * ipa-predicate.cc: Likewise.
2428 * ipa-profile.cc: Likewise.
2429 * ipa-prop.cc: Likewise.
2430 (ipa_node_params_t::duplicate): Assert new lattices remain empty
2431 instead of setting them to NULL.
2432 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
2433 * ipa-split.cc: Likewise.
2434 * ipa-sra.cc: Likewise.
2435 * ipa-strub.cc: Likewise.
2436 * ipa-utils.cc: Likewise.
2437 * ipa.cc: Likewise.
2438 * toplev.cc: Likewise.
2439 * tree-ssa-ccp.cc: Likewise.
2440 * tree-ssa-sccvn.cc: Likewise.
2441 * tree-vrp.cc: Likewise.
2443 2024-02-21 Tamar Christina <tamar.christina@arm.com>
2445 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
2446 Armv8.7-a.
2448 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2450 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2451 Use aarch64_gen_compare_zero_and_branch rather than emitting
2452 a CBZ directly.
2454 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2456 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
2457 Remove duplicated call.
2459 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2461 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
2462 Check that each individual piece of state is shared in the same
2463 way, rather than using an aggregate check for PSTATE.ZA.
2465 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2467 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2468 In the code that commits a lazy save, only zero ZA if the function
2469 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
2471 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2473 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
2474 directly inserting the associated sequence
2475 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2476 ...here instead.
2478 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2480 PR target/113995
2481 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
2482 fold the SVE allocation into the initial allocation if the
2483 initial allocation includes a VG save.
2485 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2487 PR target/113220
2488 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
2489 contain jumps even if called after initial RTL expansion.
2490 * mode-switching.cc: Include cfgbuild.h.
2491 (optimize_mode_switching): Allow the sequence returned by the
2492 emit hook to contain internal jumps. Record which blocks
2493 contain such jumps and split the blocks at the end.
2494 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
2495 non-debug insns when scanning the sequence.
2497 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
2499 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
2500 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
2502 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2504 * doc/invoke.texi (-mmcu): Add information about MCU specs.
2506 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2508 * doc/invoke.texi (-minrt): Clarify that main
2509 must take no arguments.
2511 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2513 * config/avr/builtins.def: Use function prototypes of given size
2514 and signedness.
2515 * config/avr/avr.cc (avr_init_builtins): Adjust types required
2516 by builtins.def.
2517 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2519 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2521 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
2522 instead of @table.
2524 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
2526 * config/bpf/bpf.opt: Add help information for -mcpu.
2528 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
2530 PR target/113805
2531 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
2532 New pass.
2533 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
2534 Declare.
2535 * config/aarch64/aarch64.md (is_call): New attribute.
2536 (*and<mode>3nr_compare0): Rename to...
2537 (@aarch64_and<mode>3nr_compare0): ...this.
2538 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
2539 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
2540 * config/aarch64/aarch64-speculation.cc: Update file comment to
2541 describe the new late pass.
2542 (aarch64_do_track_speculation): Handle is_call insns like other calls.
2543 (pass_track_speculation): Add an is_late member variable.
2544 (pass_track_speculation::gate): Run the late pass for streaming-
2545 compatible functions and the early pass for other functions.
2546 (make_pass_track_speculation): Update accordingly.
2547 (make_pass_late_track_speculation): New function.
2548 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
2549 function.
2550 (aarch64_guard_switch_pstate_sm): Use it.
2552 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
2554 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
2555 Register these builtins with a pointer to uint64_t rather than unsigned
2556 DI mode.
2558 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2560 PR target/113615
2561 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
2562 Conditionalize on '!TARGET_RDNA2_PLUS'.
2563 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
2564 (gcn_expand_reduc_scalar):
2565 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2567 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2569 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
2570 '__gfx90a__' target CPU definition. Add some safeguards for the future.
2572 2024-02-19 Richard Biener <rguenther@suse.de>
2574 PR rtl-optimization/54052
2575 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
2576 local defs by LR_OUT.
2578 2024-02-19 Jakub Jelinek <jakub@redhat.com>
2580 PR tree-optimization/113967
2581 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
2582 in condition that @rpos is multiple of vector element size.
2584 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2586 PR target/113696
2587 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
2588 Suppress vsetvl fusion.
2590 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
2592 PR target/113912
2593 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
2594 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
2595 (ix86_emit_save_regs): Don't generate push2 if
2596 ix86_can_use_push2pop2 return false.
2597 (ix86_expand_epilogue): Don't generate pop2 if
2598 ix86_can_use_push2pop2 return false.
2600 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2602 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
2603 Note on complete device support.
2605 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2607 * doc/extend.texi (AVR Function Attributes): Fuse description
2608 of "signal" and "interrupt" attribute. Link pseudo instruction.
2610 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2612 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
2613 symbol type conversions.
2614 (__cacop_d): Likewise.
2615 (__cpucfg): Likewise.
2616 (__asrtle_d): Likewise.
2617 (__asrtgt_d): Likewise.
2618 (__lddir_d): Likewise.
2619 (__ldpte_d): Likewise.
2620 (__crc_w_b_w): Likewise.
2621 (__crc_w_h_w): Likewise.
2622 (__crc_w_w_w): Likewise.
2623 (__crc_w_d_w): Likewise.
2624 (__crcc_w_b_w): Likewise.
2625 (__crcc_w_h_w): Likewise.
2626 (__crcc_w_w_w): Likewise.
2627 (__crcc_w_d_w): Likewise.
2628 (__csrrd_w): Likewise.
2629 (__csrwr_w): Likewise.
2630 (__csrxchg_w): Likewise.
2631 (__csrrd_d): Likewise.
2632 (__csrwr_d): Likewise.
2633 (__csrxchg_d): Likewise.
2634 (__iocsrrd_b): Likewise.
2635 (__iocsrrd_h): Likewise.
2636 (__iocsrrd_w): Likewise.
2637 (__iocsrrd_d): Likewise.
2638 (__iocsrwr_b): Likewise.
2639 (__iocsrwr_h): Likewise.
2640 (__iocsrwr_w): Likewise.
2641 (__iocsrwr_d): Likewise.
2642 (__frecipe_s): Likewise.
2643 (__frecipe_d): Likewise.
2644 (__frsqrte_s): Likewise.
2645 (__frsqrte_d): Likewise.
2647 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2649 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
2650 function return value type to unsigned short.
2652 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
2654 * doc/sourcebuild.texi: add scan-assembler-bound
2656 2024-02-16 Jason Merrill <jason@redhat.com>
2658 * gdbhooks.py: Fix regex syntax.
2660 2024-02-16 Richard Biener <rguenther@suse.de>
2662 PR tree-optimization/113895
2663 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
2664 consistency checking when there are out-of-bound array
2665 accesses. Allow -1 off when from an array reference with
2666 constant index.
2668 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2670 PR target/106543
2671 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
2672 pattern.
2674 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2676 * doc/sourcebuild.texi (Effective-Target Keywords, Other
2677 attribugs): Document linker_plugin.
2678 (Require Support): Document dg-require-linker-plugin.
2680 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2682 PR target/109349
2683 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
2684 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
2685 (RISCV_MINOR_VERSION_BASE): Ditto.
2686 (RISCV_REVISION_VERSION_BASE): Ditto.
2687 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
2688 rather than magic number.
2689 * config/riscv/riscv.h (riscv_arch_help): New.
2690 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
2691 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
2692 --print-supported-extensions.
2693 * config/riscv/riscv.opt (march=help): New.
2694 (print-supported-extensions): New.
2695 (-print-supported-extensions): New.
2696 * doc/invoke.texi (RISC-V Options): Document -march=help.
2698 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
2700 PR target/113780
2701 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
2702 for indirect calls with 4 or more arguments in pac-enabled functions.
2704 2024-02-15 David Faust <david.faust@oracle.com>
2706 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
2707 use ldxb instead of ldxh.
2709 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2711 PR middle-end/113921
2712 * cfgrtl.h (prepend_insn_to_edge): New declaration.
2713 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
2714 comment.
2715 (prepend_insn_to_edge): New function.
2716 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
2717 insert_insn_on_edge.
2719 2024-02-15 Richard Biener <rguenther@suse.de>
2721 PR tree-optimization/111156
2722 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
2723 at the pattern stmt if any.
2725 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
2727 PR target/113927
2728 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
2729 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
2730 * config/avr/avr.cc (avr_adiw_reg_p): New function.
2731 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
2732 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
2733 * config/avr/avr.md: Same.
2734 (attr "isa") <tiny, no_tiny>: Remove.
2735 <adiw, no_adiw>: Add.
2736 (define_insn, define_insn_and_split): When an alternative has
2737 constraint "w", then set attribute "isa" to "adiw".
2738 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
2739 Built-in define __AVR_HAVE_ADIW__.
2740 * doc/invoke.texi (AVR Options): Document it.
2742 2024-02-15 Andrew Stubbs <ams@baylibre.com>
2744 * config/gcn/gcn-valu.md
2745 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
2746 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
2747 details are supported on RDNA devices.
2749 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2751 PR middle-end/113508
2752 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
2753 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
2754 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
2755 Add sentence about what the mode m is.
2757 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2759 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
2760 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
2761 var.
2763 2024-02-15 Richard Biener <rguenther@suse.de>
2765 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
2766 stmts.
2768 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2770 PR tree-optimization/113567
2771 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
2772 _BitInt multiplication, division or modulo with
2773 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
2774 force the affected inputs into a new SSA_NAME.
2776 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
2778 PR target/113871
2779 * config/i386/mmx.md (V248FI): New mode iterator.
2780 (V24FI_32): DItto.
2781 (vec_shl_<V248FI:mode>): New expander.
2782 (vec_shl_<V24FI_32:mode>): Ditto.
2783 (vec_shr_<V248FI:mode>): Ditto.
2784 (vec_shr_<V24FI_32:mode>): Ditto.
2785 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
2786 (vec_shr_<V248FI:mode>): Ditto.
2788 2024-02-14 Jan Hubicka <jh@suse.cz>
2790 PR tree-optimization/111054
2791 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
2793 2024-02-14 Tamar Christina <tamar.christina@arm.com>
2795 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
2797 2024-02-14 Richard Biener <rguenther@suse.de>
2799 PR tree-optimization/113910
2800 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
2801 the hashval_t hash.
2803 2024-02-14 Jakub Jelinek <jakub@redhat.com>
2805 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
2806 (pp_integer_with_precision): For unsigned ptrdiff_t printing
2807 with u, o or x print ptrdiff_t argument converted to
2808 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
2810 2024-02-14 Richard Biener <rguenther@suse.de>
2812 PR middle-end/113576
2813 * expr.cc (do_store_flag): For vector bool compares of vectors
2814 with padding zero that.
2815 * dojump.cc (do_compare_and_jump): Likewise.
2817 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
2819 * doc/install.texi (Prerequisites): Update gettext link.
2821 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
2823 PR target/113876
2824 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
2825 Return false if the incoming stack isn't 16-byte aligned.
2827 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
2829 PR middle-end/113904
2830 * omp-general.cc (struct omp_ts_info): Update for splitting of
2831 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2832 * omp-selectors.h (enum omp_tp_type): Replace
2833 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2835 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
2837 PR target/113742
2838 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
2839 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
2841 2024-02-13 Richard Biener <rguenther@suse.de>
2843 PR tree-optimization/113895
2844 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
2845 offset to discover constant array indices in bits, handle
2846 COMPONENT_REF to bitfields.
2848 2024-02-13 Richard Biener <rguenther@suse.de>
2850 PR tree-optimization/113831
2851 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
2852 typo in comment.
2854 2024-02-13 Richard Biener <rguenther@suse.de>
2856 PR tree-optimization/113902
2857 * tree-vect-loop.cc (move_early_exit_stmts): Track
2858 last_seen_vuse for VUSE updating.
2860 2024-02-13 Tamar Christina <tamar.christina@arm.com>
2862 PR tree-optimization/113734
2863 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
2864 an early break loop as partial.
2866 2024-02-13 Richard Biener <rguenther@suse.de>
2868 PR tree-optimization/113898
2869 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
2870 missing accumulated off adjustment.
2872 2024-02-13 Jakub Jelinek <jakub@redhat.com>
2874 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
2875 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
2876 it against UINT_MAX and ULONG_MAX.
2878 2024-02-13 David Malcolm <dmalcolm@redhat.com>
2880 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
2881 to...
2882 (emit_diagnostic_valist_meta): ...this.
2883 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
2884 (emit_diagnostic_valist_meta): ...this.
2886 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2888 PR tree-optimization/113849
2889 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
2890 fast path for widening casts where !m_upwards_2limb and lhs_type
2891 has precision which is a multiple of limb_prec.
2893 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2895 PR c++/113674
2896 * attribs.cc (extract_attribute_substring): Remove.
2897 (lookup_scoped_attribute_spec): Don't call it.
2899 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2901 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
2902 and cast to fmt_size_t instead of %lu and cast to unsigned long.
2904 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
2906 * Makefile.in: Add no-info dependency.
2907 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
2908 available.
2909 * configure: Regenerate.
2911 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
2913 PR target/113855
2914 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
2915 available to all sub-targets.
2916 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2917 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2919 2024-02-12 Richard Biener <rguenther@suse.de>
2921 PR tree-optimization/113831
2922 PR tree-optimization/108355
2923 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
2924 we see variable array indices and get_ref_base_and_extent
2925 can resolve those to constants fix up the ops to constants
2926 as well.
2927 (ao_ref_init_from_vn_reference): Use 'off' member for
2928 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
2929 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
2931 2024-02-12 Pan Li <pan2.li@intel.com>
2933 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
2934 Replace args to arguments for misspelled term.
2936 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
2938 PR target/112944
2939 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
2940 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
2941 when not linked with -mrodata-in-ram.
2943 2024-02-12 Richard Biener <rguenther@suse.de>
2945 PR tree-optimization/113863
2946 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2947 Record crossed virtual PHIs.
2948 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
2949 virtual PHIs.
2951 2024-02-10 Marek Polacek <polacek@redhat.com>
2953 DR 2237
2954 PR c++/107126
2955 PR c++/97202
2956 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
2958 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2960 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
2961 computation of idx for i == 4 of bitint_prec_huge.
2963 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2965 PR middle-end/110754
2966 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
2967 decls create PARM_DECL with pointer to original type, set
2968 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
2969 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
2970 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
2971 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
2972 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
2973 of the var as argument.
2975 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2977 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
2978 size_t and precision 4 for ptrdiff_t. Formatting fix.
2979 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
2980 Formatting fixes.
2981 (test_pp_format): Test t and z modifiers.
2982 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
2984 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2986 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
2987 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
2988 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2989 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
2990 and casts to fmt_size_t instead of "%ld" and casts to long.
2991 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
2992 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
2993 instead of "%lu" and casts to unsigned long.
2994 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
2995 unsigned long.
2996 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2997 and casts to fmt_size_t instead of "%ld" and casts to long.
2998 * cfgexpand.cc (dump_stack_var_partition): Use
2999 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
3000 and casts to unsigned long.
3001 * gengtype.cc (adjust_field_rtx_def): Likewise.
3002 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3003 and casts to fmt_size_t instead of "%ld" and casts to long.
3004 * postreload-gcse.cc (dump_hash_table): Likewise.
3005 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
3006 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3007 (ggc_internal_alloc, ggc_free): Likewise.
3008 * genpreds.cc (write_lookup_constraint_1): Likewise.
3009 (write_insn_constraint_len): Likewise.
3010 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
3011 and casts to fmt_size_t instead of "%ld" and casts to long.
3012 * varasm.cc (output_constant_pool_contents): Use
3013 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
3014 * var-tracking.cc (dump_var): Likewise.
3016 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3018 PR tree-optimization/113783
3019 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
3020 through VIEW_CONVERT_EXPR for final cast checks. Handle
3021 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
3022 INTEGER_TYPEs.
3023 (gimple_lower_bitint): Don't merge mergeable operations or other
3024 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
3025 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
3026 mode is BLKmode.
3028 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3030 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
3031 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
3032 HOST_SIZE_T_PRINT_HEX_PURE): Define.
3033 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
3034 fixes.
3036 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3038 PR middle-end/113415
3039 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
3040 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
3041 of hand written loop with emit_insn of copy_insn and emit original
3042 after_rtl_seq on the last edge.
3044 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3046 PR tree-optimization/113818
3047 * gimple-lower-bitint.cc (add_eh_edge): New function.
3048 (bitint_large_huge::handle_load,
3049 bitint_large_huge::lower_mergeable_stmt,
3050 bitint_large_huge::lower_muldiv_stmt): Use it.
3052 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3054 PR tree-optimization/113774
3055 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
3056 emit any comparison if m_first and low + 1 is equal to
3057 m_upwards_2limb, simplify condition for that. If not
3058 single_comparison, not m_first and we can prove that the idx <= low
3059 comparison will be always true, emit instead of idx <= low
3060 comparison low <= low such that cfg cleanup will optimize it at
3061 the end of the pass.
3063 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
3065 PR tree-optimization/113735
3066 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
3067 limit_check().
3069 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3071 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
3072 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
3074 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
3076 PR target/113711
3077 PR target/113733
3078 * config/i386/constraints.md: List all constraints with j prefix.
3079 (j>): Change auto-dec to auto-inc in documentation.
3080 (je): Changed to a memory constraint with APX NDD TLS operand
3081 check.
3082 (jM): New memory constraint for APX NDD instructions.
3083 (jO): Likewise.
3084 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
3085 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
3086 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
3087 (*add<mode>_1[SWI48]): Use je and jM.
3088 (addsi_1_zext): Use jM.
3089 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
3090 (*sub<mode>_1[SWI]): Use jM.
3091 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
3092 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
3093 (*and<dwi>3_doubleword): Likewise.
3094 (*anddi_1): Use jM.
3095 (*andsi_1_zext): Likewise.
3096 (*and<mode>_1[SWI24]): Likewise.
3097 (*<code><dwi>3_doubleword[any_or]): Use rjO
3098 (*code<mode>_1[any_or SWI248]): Use jM.
3099 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
3100 * config/i386/predicates.md (apx_ndd_memory_operand): New.
3101 (apx_ndd_add_memory_operand): Likewise.
3103 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3105 PR target/113824
3106 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
3107 * doc/avr-mmcu.texi: Rebuild.
3109 2024-02-08 Tamar Christina <tamar.christina@arm.com>
3111 PR tree-optimization/113808
3112 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
3113 value cross iterations.
3115 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3117 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
3118 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
3120 2024-02-08 Richard Biener <rguenther@suse.de>
3122 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3123 Revert last change to dr_may_alias_p.
3125 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3127 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
3128 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
3129 Remove spec asm_misc.
3130 * config/avr/specs.h: Same.
3132 2024-02-08 Pan Li <pan2.li@intel.com>
3134 PR target/113766
3135 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
3136 sure the c.arg_num is >= 2 before checking.
3137 (struct build_frm_base): Ditto.
3138 (struct narrow_alu_def): Ditto.
3140 2024-02-07 Richard Biener <rguenther@suse.de>
3142 PR tree-optimization/113796
3143 * tree-if-conv.cc (combine_blocks): Wipe range-info before
3144 replacing PHIs and inserting predicates.
3146 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
3147 Uros Bizjak <ubizjak@gmail.com>
3149 PR target/113690
3150 * config/i386/i386-features.cc (timode_convert_cst): New helper
3151 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
3152 CONST_VECTOR.
3153 (timode_scalar_chain::convert_op): Use timode_convert_cst.
3154 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
3155 Use timode_convert_cst.
3157 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
3159 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
3160 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
3161 (AARCH64_FL_DEBUGv8p9): Likewise.
3162 (AARCH64_FL_FGT2): Likewise.Likewise.
3163 (AARCH64_FL_ITE): Likewise.
3164 (AARCH64_FL_PFAR): Likewise.
3165 (AARCH64_FL_PMUv3_ICNTR): Likewise.
3166 (AARCH64_FL_PMUv3_SS): Likewise.
3167 (AARCH64_FL_PMUv3p9): Likewise.
3168 (AARCH64_FL_RASv2): Likewise.
3169 (AARCH64_FL_S1PIE): Likewise.
3170 (AARCH64_FL_S1POE): Likewise.
3171 (AARCH64_FL_S2PIE): Likewise.
3172 (AARCH64_FL_S2POE): Likewise.
3173 (AARCH64_FL_SCTLR2): Likewise.
3174 (AARCH64_FL_SEBEP): Likewise.
3175 (AARCH64_FL_SPE_FDS): Likewise.
3176 (AARCH64_FL_TCR2): Likewise.
3178 2024-02-07 Richard Biener <rguenther@suse.de>
3180 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3181 Only check whether reads are in-bound in places that are not safe.
3182 Fix dependence check. Add missing newline. Clarify comments.
3184 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3186 PR tree-optimization/113750
3187 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
3188 for single predecessor when doing early break vect.
3189 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
3190 after labels.
3192 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3194 PR tree-optimization/113731
3195 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
3196 method.
3197 * gimple-iterator.h (gsi_move_before): Default new param to
3198 GSI_SAME_STMT.
3199 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
3200 GSI_NEW_STMT.
3202 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3204 PR tree-optimization/113756
3205 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
3206 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
3207 of lh_bits value and mask.
3209 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3211 PR tree-optimization/113753
3212 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
3213 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
3214 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
3215 so that they start with r[half_blocks_needed] lowest bit. Fix up
3216 computation of top mask for SIGNED.
3218 2024-02-07 Pan Li <pan2.li@intel.com>
3220 PR target/113766
3221 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
3222 the signature of func.
3223 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
3224 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
3225 overloaded func with empty args error.
3227 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
3229 PR target/113689
3230 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
3231 R10_REG after sorry.
3233 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
3235 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
3236 Move before new caller, and add ".default" suffix.
3237 (get_suffixed_assembler_name): New.
3238 (make_resolver_func): Use get_suffixed_assembler_name.
3239 (aarch64_generate_version_dispatcher_body): Redo name mangling.
3241 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3243 PR target/113763
3244 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
3245 element from std::pair<unsigned int, char> to an unnamed struct.
3246 Adjust uses of tile range variable.
3248 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3250 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
3251 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
3253 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3255 PR sanitizer/110676
3256 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
3257 reset maxlen to sizetype maximum.
3259 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3261 PR tree-optimization/113736
3262 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
3263 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
3265 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3267 PR tree-optimization/113759
3268 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
3269 or from_unsignedN differs from properties of typeN, update typeN
3270 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
3271 uselessly convertible to typeN, convert it using fold_convert or
3272 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
3273 (convert_plusminus_to_widen): Likewise.
3275 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
3277 PR target/112577
3278 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
3279 vector structure modes correctly.
3281 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
3283 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
3284 warning.
3286 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
3288 PR target/113689
3289 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
3290 (x86_function_profiler): Call x86_64_select_profile_regnum to
3291 get a scratch register for large model profiling.
3293 2024-02-05 Richard Ball <richard.ball@arm.com>
3295 * config/arm/arm.cc (arm_output_mi_thunk): Emit
3296 insn for bti_c when bti is enabled.
3298 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3300 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
3301 neg.
3303 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3305 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
3306 (neg<mode>2): Change the mode iterator from MSA to IMSA because
3307 in FP arithmetic we cannot use (0 - x) for -x.
3308 (neg<mode>2): New define_insn to implement FP vector negation,
3309 using a bnegi instruction to negate the sign bit.
3311 2024-02-05 Richard Biener <rguenther@suse.de>
3313 PR tree-optimization/113707
3314 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
3315 checking the avail set treat out-of-region defines as
3316 available.
3318 2024-02-05 Richard Biener <rguenther@suse.de>
3320 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
3321 the default mode when building a pointer.
3323 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3325 PR tree-optimization/113737
3326 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
3327 has just a single label, remove it and make single successor edge
3328 EDGE_FALLTHRU.
3330 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3332 PR target/113059
3333 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
3334 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
3335 df_analyze call.
3337 2024-02-05 Richard Biener <rguenther@suse.de>
3339 PR target/113255
3340 * config/i386/i386-expand.cc
3341 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
3342 Use a new pseudo for the skipped number of bytes.
3344 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3346 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
3347 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
3348 sifive-p670.
3350 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3352 * config/riscv/riscv.md: Include sifive-p400.md.
3353 * config/riscv/sifive-p400.md: New file.
3354 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3355 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3356 Add sifive_p400.
3357 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
3358 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3359 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
3361 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3363 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
3364 Add missing ":SI" to the match_operator.
3366 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3368 * config/xtensa/xtensa.md (SHI): New mode iterator.
3369 (2 split patterns related to constsynth):
3370 Change to also accept HImode operands.
3372 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
3374 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
3375 similarly.
3377 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3379 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
3380 incorrect expand.
3381 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
3382 (elmsgnbit): Likewise.
3383 (neg<mode:FVEC>2): New define_insn.
3384 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
3385 are now instantiated in simd.md.
3387 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3389 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
3390 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
3391 MAX_MACHINE_MODE.
3393 2024-02-04 Li Wei <liwei@loongson.cn>
3395 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
3396 (loongarch_expand_vselect_vconcat): Ditto.
3397 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
3398 all 128-bit constant permutation situations.
3399 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
3400 (loongarch_is_imm_set_shuffle): Renamed function name.
3401 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
3402 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
3403 extract-even and extract-odd permutations.
3404 (loongarch_is_odd_extraction): Delete.
3405 (loongarch_is_even_extraction): Ditto.
3406 (loongarch_expand_vec_perm_const): Adjust.
3408 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3410 PR middle-end/113722
3411 * wide-int.cc (wi::bswap_large): Rename third argument from
3412 len to xlen and adjust use in safe_uhwi. Add len variable, set
3413 it to BLOCKS_NEEDED (precision) and use it for clearing of val
3414 and as canonize argument. Clear val using memset instead of
3415 a loop.
3417 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3419 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
3420 mmi.preferred_base + mmi.size - sizeof (void *).
3422 2024-02-03 Xi Ruoyao <xry111@xry111.site>
3424 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
3425 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
3426 the ODR-violating locale declaration.
3428 2024-02-02 Tamar Christina <tamar.christina@arm.com>
3430 PR tree-optimization/113588
3431 PR tree-optimization/113467
3432 * tree-vect-data-refs.cc
3433 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
3434 (vect_analyze_early_break_dependences): Update comments.
3436 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
3438 PR target/59778
3439 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
3440 and PA_BUILTIN_SET_FPSR builtins.
3441 * (pa_builtins_icode): Declare.
3442 * (def_builtin, pa_fpu_init_builtins): New.
3443 * (pa_init_builtins): Initialize FPU builtins.
3444 * (pa_builtin_decl, pa_expand_builtin_1): New.
3445 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
3446 PA_BUILTIN_SET_FPSR builtins.
3447 * (pa_atomic_assign_expand_fenv): New.
3448 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
3449 UNSPECV constants.
3450 (get_fpsr, put_fpsr): New expanders.
3451 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
3452 insn patterns.
3454 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3456 PR target/113697
3457 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
3459 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
3461 * doc/extend.texi (Common Type Attributes): Fix typo in
3462 description of hardbool.
3464 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3466 PR tree-optimization/113692
3467 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
3468 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
3469 final_cast_p.
3471 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3473 PR middle-end/113699
3474 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
3475 uninitialized large/huge _BitInt SSA_NAME inputs.
3477 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3479 PR middle-end/113705
3480 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
3481 around wi::to_wide in order to compare value in prec precision.
3483 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
3485 Revert:
3486 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3488 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3490 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3492 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3494 2024-02-02 Pan Li <pan2.li@intel.com>
3496 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
3497 (riscv_pass_by_reference): Ditto.
3498 (riscv_fntype_abi): Ditto.
3500 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3502 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
3503 (pre_vsetvl::cleaup): Remove vsetvl_pre.
3504 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
3506 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
3508 * config/loongarch/larchintrin.h
3509 (__frecipe_s): Update function return type.
3510 (__frecipe_d): Ditto.
3511 (__frsqrte_s): Ditto.
3512 (__frsqrte_d): Ditto.
3514 2024-02-02 Li Wei <liwei@loongson.cn>
3516 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
3517 (loongarch_vector_costs::add_stmt_cost): Adjust.
3519 2024-02-02 Xi Ruoyao <xry111@xry111.site>
3521 * config/loongarch/loongarch.md (unspec): Add
3522 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
3523 (la_pcrel64_two_parts): New define_insn.
3524 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
3525 typo in the comment.
3526 (loongarch_call_tls_get_addr): If -mcmodel=extreme
3527 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
3528 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
3529 note to allow CSE addressing __tls_get_addr.
3530 (loongarch_legitimize_tls_address): If -mcmodel=extreme
3531 -mexplicit-relocs={always,auto}, address TLS IE symbols with
3532 la_pcrel64_two_parts.
3533 (loongarch_split_symbol): If -mcmodel=extreme
3534 -mexplicit-relocs={always,auto}, address symbols with
3535 la_pcrel64_two_parts.
3536 (loongarch_output_mi_thunk): Clean up unreachable code. If
3537 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
3538 thunks with la_pcrel64_two_parts.
3540 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3542 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
3543 Add support for call36.
3545 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3547 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3548 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
3549 the macro instruction loading symbol address is not applicable.
3550 (loongarch_call_tls_get_addr): Adjust code.
3551 (loongarch_legitimize_tls_address): Likewise.
3553 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3555 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
3556 Add function declaration.
3557 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3558 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
3559 is not allowed
3560 (loongarch_load_tls): Added macro support in extreme mode.
3561 (loongarch_call_tls_get_addr): Likewise.
3562 (loongarch_legitimize_tls_address): Likewise.
3563 (loongarch_force_address): Likewise.
3564 (loongarch_legitimize_move): Likewise.
3565 (loongarch_output_mi_thunk): Likewise.
3566 (loongarch_option_override_internal): Remove the code that detects
3567 explicit relocs status.
3568 (loongarch_handle_model_attribute): Likewise.
3569 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
3570 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
3571 (symbolic_off64_or_reg_operand): Likewise.
3573 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3575 * config/loongarch/loongarch.cc (loongarch_load_tls):
3576 Load all types of tls symbols through one function.
3577 (loongarch_got_load_tls_gd): Delete.
3578 (loongarch_got_load_tls_ld): Delete.
3579 (loongarch_got_load_tls_ie): Delete.
3580 (loongarch_got_load_tls_le): Delete.
3581 (loongarch_call_tls_get_addr): Modify the called function name.
3582 (loongarch_legitimize_tls_address): Likewise.
3583 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
3584 (@load_tls<mode>): New template.
3585 (@got_load_tls_ld<mode>): Delete.
3586 (@got_load_tls_le<mode>): Delete.
3587 (@got_load_tls_ie<mode>): Delete.
3589 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3591 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
3592 (loongarch_legitimize_address): Add logical transformation code.
3594 2024-02-01 Marek Polacek <polacek@redhat.com>
3596 * doc/invoke.texi: Update -Wdangling-reference documentation.
3598 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
3600 PR target/113701
3601 * config/i386/i386.md (*cmp<dwi>_doubleword):
3602 Do not force SUBREG pieces to pseudos.
3604 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
3606 * config/pa/pa.md (atomic_storedi_1): Fix bug in
3607 alternative 1.
3609 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
3611 * config/avr/avr.cc: Tabify.
3613 2024-02-01 Richard Ball <richard.ball@arm.com>
3615 PR tree-optimization/111268
3616 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
3617 Add variable-length check for vector input arguments
3618 to a function.
3620 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3622 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
3623 hard-code number of SGPR/VGPR/AVGPR registers.
3624 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
3625 SGPR/VGPR/AVGPR registers.
3627 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3629 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
3630 attribute, and include sifive-p600.md.
3631 * config/riscv/generic-ooo.md: Update type attribute.
3632 * config/riscv/generic.md: Update type attribute.
3633 * config/riscv/sifive-7.md: Update type attribute.
3634 * config/riscv/sifive-p600.md: New file.
3635 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3636 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3637 Add sifive_p600.
3638 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
3639 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3640 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
3642 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3644 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
3645 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
3646 * config/riscv/riscv.opt: New macro for 7 new unprivileged
3647 extensions.
3648 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
3649 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
3651 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3653 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
3654 -static-libasan. Add missing whitespace.
3656 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3658 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
3659 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
3660 Don't 'define_constants'.
3662 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3664 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
3666 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3668 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
3669 [TARGET_RDNA3]: Adjust.
3671 2024-02-01 Richard Biener <rguenther@suse.de>
3673 PR tree-optimization/113693
3674 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
3675 data when available.
3677 2024-02-01 Jakub Jelinek <jakub@redhat.com>
3678 Jason Merrill <jason@redhat.com>
3680 PR c++/113531
3681 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
3682 on variables which were promoted to TREE_STATIC.
3684 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
3685 Richard Biener <rguenther@suse.de>
3687 PR target/113560
3688 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
3689 information via tree_non_zero_bits to check if this operand
3690 is suitably extended for a widening (or highpart) multiplication.
3691 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
3692 isn't already of the claimed type.
3694 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3696 Revert:
3697 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3699 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3700 (generic_ooo_branch): ditto
3701 * config/riscv/generic.md (generic_sfb_alu): ditto
3702 (generic_fmul_half): ditto
3703 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3704 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3705 (sifive_7_popcount): ditto
3706 * config/riscv/vector.md: change rdfrm to fmove
3707 * config/riscv/zc.md: change pushpop to load/store
3709 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3711 Revert:
3712 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3713 Robin Dapp <rdapp.gcc@gmail.com>
3715 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3716 (generic_ooo_vec_load): ditto
3717 (generic_ooo_vec_store): ditto
3718 (generic_ooo_vec_loadstore_seg): ditto
3719 (generic_ooo_vec_alu): ditto
3720 (generic_ooo_vec_fcmp): ditto
3721 (generic_ooo_vec_imul): ditto
3722 (generic_ooo_vec_fadd): ditto
3723 (generic_ooo_vec_fmul): ditto
3724 (generic_ooo_crypto): ditto
3725 (generic_ooo_perm): ditto
3726 (generic_ooo_vec_reduction): ditto
3727 (generic_ooo_vec_ordered_reduction): ditto
3728 (generic_ooo_vec_idiv): ditto
3729 (generic_ooo_vec_float_divsqrt): ditto
3730 (generic_ooo_vec_mask): ditto
3731 (generic_ooo_vec_vesetvl): ditto
3732 (generic_ooo_vec_setrm): ditto
3733 (generic_ooo_vec_readlen): ditto
3734 * config/riscv/riscv.md: include generic-vector-ooo
3735 * config/riscv/generic-vector-ooo.md: New file. to here
3737 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3739 Revert:
3740 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3742 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3744 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3746 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3748 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3749 Robin Dapp <rdapp.gcc@gmail.com>
3751 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3752 (generic_ooo_vec_load): ditto
3753 (generic_ooo_vec_store): ditto
3754 (generic_ooo_vec_loadstore_seg): ditto
3755 (generic_ooo_vec_alu): ditto
3756 (generic_ooo_vec_fcmp): ditto
3757 (generic_ooo_vec_imul): ditto
3758 (generic_ooo_vec_fadd): ditto
3759 (generic_ooo_vec_fmul): ditto
3760 (generic_ooo_crypto): ditto
3761 (generic_ooo_perm): ditto
3762 (generic_ooo_vec_reduction): ditto
3763 (generic_ooo_vec_ordered_reduction): ditto
3764 (generic_ooo_vec_idiv): ditto
3765 (generic_ooo_vec_float_divsqrt): ditto
3766 (generic_ooo_vec_mask): ditto
3767 (generic_ooo_vec_vesetvl): ditto
3768 (generic_ooo_vec_setrm): ditto
3769 (generic_ooo_vec_readlen): ditto
3770 * config/riscv/riscv.md: include generic-vector-ooo
3771 * config/riscv/generic-vector-ooo.md: New file. to here
3773 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3775 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3776 (generic_ooo_branch): ditto
3777 * config/riscv/generic.md (generic_sfb_alu): ditto
3778 (generic_fmul_half): ditto
3779 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3780 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3781 (sifive_7_popcount): ditto
3782 * config/riscv/vector.md: change rdfrm to fmove
3783 * config/riscv/zc.md: change pushpop to load/store
3785 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
3787 PR target/113657
3788 * config/aarch64/aarch64-simd.md (split for movv8di):
3789 For strict aligned mode, use DImode instead of TImode.
3791 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
3793 PR middle-end/113607
3794 * match.pd: Make sure else values match when folding a
3795 vec_cond into a conditional operation.
3797 2024-01-31 Marek Polacek <polacek@redhat.com>
3799 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
3801 2024-01-31 Tamar Christina <tamar.christina@arm.com>
3802 Matthew Malcomson <matthew.malcomson@arm.com>
3804 PR sanitizer/112644
3805 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
3806 memcmp.
3807 * builtins.cc (expand_builtin): Include HWASAN when checking for
3808 builtin inlining.
3810 2024-01-31 Richard Biener <rguenther@suse.de>
3812 PR middle-end/110176
3813 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
3814 to match INTEGER_CST only without outstanding conversion.
3816 2024-01-31 Alex Coplan <alex.coplan@arm.com>
3818 PR target/111677
3819 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
3820 V16QImode for the full 16-byte FPR saves in the vector PCS case.
3822 2024-01-31 Richard Biener <rguenther@suse.de>
3824 PR tree-optimization/111444
3825 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
3826 vn_reference_lookup_2 when optimistically skipping may-defs.
3828 2024-01-31 Richard Biener <rguenther@suse.de>
3830 PR tree-optimization/113630
3831 * tree-ssa-pre.cc (compute_avail): Avoid registering a
3832 reference with a representation with not matching base
3833 access size.
3835 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3837 PR rtl-optimization/113656
3838 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
3839 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
3841 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3843 PR debug/113637
3844 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
3845 with BLKmode are larger than DWARF2_ADDR_SIZE.
3847 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3849 PR tree-optimization/113639
3850 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3851 For VIEW_CONVERT_EXPR set rhs1 to its operand.
3853 2024-01-31 Richard Biener <rguenther@suse.de>
3855 PR tree-optimization/113670
3856 * tree-vect-data-refs.cc (vect_check_gather_scatter):
3857 Make sure we can take the address of the reference base.
3859 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
3861 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
3862 ATA5835, ATtiny64AUTO, ATA5700M322.
3863 * doc/avr-mmcu.texi: Rebuild.
3865 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3867 PR debug/113394
3868 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
3869 caller.
3871 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3873 PR middle-end/112917
3874 PR middle-end/113100
3875 * builtins.cc (expand_builtin_stack_address): Use
3876 STACK_ADDRESS_OFFSET.
3877 * doc/extend.texi (__builtin_stack_address): Adjust.
3878 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
3879 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
3880 * doc/tm.texi: Rebuilt.
3882 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3884 PR target/113495
3885 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
3886 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
3887 (pre_vsetvl::compute_transparent): New function.
3888 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
3890 2024-01-30 Fangrui Song <maskray@google.com>
3892 PR target/105576
3893 * config/i386/constraints.md: Define constraint "Ws".
3894 * doc/md.texi: Document it.
3896 2024-01-30 Marek Polacek <polacek@redhat.com>
3898 PR c++/110358
3899 PR c++/109640
3900 * doc/invoke.texi: Update -Wdangling-reference description.
3902 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3904 * config/xtensa/constraints.md (R, T, U):
3905 Change define_constraint to define_memory_constraint.
3906 * config/xtensa/predicates.md (move_operand): Don't check that a
3907 constant pool operand size is a multiple of UNITS_PER_WORD.
3908 * config/xtensa/xtensa.cc
3909 (xtensa_lra_p, TARGET_LRA_P): Remove.
3910 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
3911 clause as it can no longer be true.
3912 (fixup_subreg_mem): Drop function.
3913 (xtensa_output_integer_literal_parts): Consider 16-bit wide
3914 constants.
3915 (xtensa_legitimate_constant_p): Add short-circuit path for
3916 integer load instructions. Don't check that mode size is
3917 at least UNITS_PER_WORD.
3918 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
3919 rather reload_in_progress and reload_completed.
3920 (doloop_end): Drop operand 2.
3921 (movhi_internal): Add alternative loading constant from a
3922 literal pool.
3923 (define_split for DI register_operand): Don't limit to
3924 !TARGET_AUTO_LITPOOLS.
3925 * config/xtensa/xtensa.opt (mlra): Change to no effect.
3927 2024-01-30 Pan Li <pan2.li@intel.com>
3929 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
3930 calculate the gpr count required by vls mode.
3931 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
3932 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
3933 for vls mode.
3934 (riscv_get_arg_info): Add vls mode handling.
3935 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
3937 2024-01-30 Richard Biener <rguenther@suse.de>
3939 PR tree-optimization/113659
3940 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3941 Handle main exit without virtual use.
3943 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
3945 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
3947 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
3949 PR libgcc/113403
3950 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
3951 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
3952 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
3953 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
3954 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
3955 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
3957 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3959 PR target/113623
3960 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
3961 Mark all registers that occur in addresses as needing a GPR.
3963 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3965 PR target/113636
3966 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
3967 the containing insn as an extra parameter. Reset debug instructions
3968 if they reference a register that is no longer used by real insns.
3969 (early_ra::apply_allocation): Update calls accordingly.
3971 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3973 PR tree-optimization/113603
3974 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
3975 count_nonzero_bytes call refetch si using get_strinfo in case it
3976 has been unshared in the meantime.
3978 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3980 PR middle-end/101195
3981 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
3982 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
3984 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
3986 * config/riscv/thead.cc (th_print_operand_address): Change %ld
3987 to %lld.
3989 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
3990 Manolis Tsamis <manolis.tsamis@vrull.eu>
3991 Philipp Tomsich <philipp.tomsich@vrull.eu>
3993 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
3994 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
3995 Likewise.
3996 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
3997 Call on framework moved later.
3999 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
4001 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
4002 instruction in naked function epilogues.
4004 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
4006 PR target/113655
4007 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
4008 gcc_cv_as_mips_explicit_relocs.
4009 * configure: Regnerated.
4011 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
4013 PR target/108933
4014 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
4015 Correct generated RTL.
4016 (arm_rev16si2_alt1): Correctly handle conditional execution.
4017 (arm_rev16si2_alt2): Likewise.
4019 2024-01-29 Richard Biener <rguenther@suse.de>
4021 PR middle-end/113622
4022 * expr.cc (expand_assignment): Spill hard registers if
4023 we index them with a variable offset.
4025 2024-01-29 Richard Biener <rguenther@suse.de>
4027 PR middle-end/113622
4028 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
4029 Also allow DECL_HARD_REGISTER variables.
4031 2024-01-29 Alex Coplan <alex.coplan@arm.com>
4033 PR target/113616
4034 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
4035 Use iterate_safely when iterating over debug uses.
4036 (fixup_debug_uses): Likewise.
4037 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
4038 over nondebug insns instead of manually maintaining the next insn.
4039 * iterator-utils.h (class safe_iterator): New.
4040 (iterate_safely): New.
4042 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
4044 PR target/38534
4045 * config/i386/i386-options.cc (ix86_set_func_type): Save
4046 callee-saved registers in noreturn functions for -O0/-Og.
4048 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4050 PR target/113615
4051 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
4052 define for !TARGET_RDNA2_PLUS.
4054 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
4056 PR target/113281
4057 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
4058 workaround for right shifts.
4059 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
4060 (vect_determine_precisions_from_range): Be more selective about
4061 which codes can be narrowed based on their input and output ranges.
4062 For shifts, require at least one more bit of precision than the
4063 maximum shift amount.
4065 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4067 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
4069 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4071 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
4072 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
4073 LLVM 13.0.1+.
4075 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4077 PR other/111966
4078 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
4079 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
4080 (SET_SRAM_ECC_UNSET): ... this.
4081 (copy_early_debug_info): Remove gfx900 special case, now handled as
4082 part of the generic handling.
4083 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
4085 2024-01-29 Jakub Jelinek <jakub@redhat.com>
4087 PR tree-optimization/110603
4088 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
4089 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
4090 overwritten anyway). Avoid creating invalid range with minlen
4091 larger than maxlen. Formatting fix.
4093 2024-01-29 Richard Biener <rguenther@suse.de>
4095 PR debug/103047
4096 * tree-inline.cc (initialize_inlined_parameters): Reverse
4097 the decl chain of inlined parameters.
4099 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4101 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
4102 alignment of CFString constants by setting DECL_USER_ALIGN.
4104 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4105 Jakub Jelinek <jakub@redhat.com>
4107 PR libgcc/113402
4108 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
4109 and BUILT_IN_GCC_NESTED_PTR_DELETED.
4110 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
4111 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
4112 rename the library fallbacks to __gcc_nested_func_ptr_created and
4113 __gcc_nested_func_ptr_deleted.
4114 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
4115 and __gcc_nested_func_ptr_deleted.
4116 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
4117 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
4118 * tree.cc (build_common_builtin_nodes): Build the
4119 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
4120 builtins only for non-explicit.
4122 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
4124 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
4126 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4128 PR target/38534
4129 * config/i386/i386-options.cc (ix86_set_func_type): Don't
4130 save and restore callee saved registers for a noreturn function
4131 with nothrow or compiled with -fno-exceptions.
4133 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4135 PR target/103503
4136 PR target/113312
4137 * config/i386/i386-expand.cc (ix86_expand_call): Replace
4138 no_caller_saved_registers check with call_saved_registers check.
4139 Clobber all registers that are not used by the callee with
4140 no_callee_saved_registers attribute.
4141 * config/i386/i386-options.cc (ix86_set_func_type): Set
4142 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
4143 noreturn function. Disallow no_callee_saved_registers with
4144 interrupt or no_caller_saved_registers attributes together.
4145 (ix86_set_current_function): Replace no_caller_saved_registers
4146 check with call_saved_registers check.
4147 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
4148 (ix86_handle_call_saved_registers_attribute): This.
4149 (ix86_gnu_attributes): Add
4150 ix86_handle_call_saved_registers_attribute.
4151 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
4152 no_caller_saved_registers check with call_saved_registers check.
4153 (ix86_function_ok_for_sibcall): Don't allow callee with
4154 no_callee_saved_registers attribute when the calling function
4155 has callee-saved registers.
4156 (ix86_comp_type_attributes): Also check
4157 no_callee_saved_registers.
4158 (ix86_epilogue_uses): Replace no_caller_saved_registers check
4159 with call_saved_registers check.
4160 (ix86_hard_regno_scratch_ok): Likewise.
4161 (ix86_save_reg): Replace no_caller_saved_registers check with
4162 call_saved_registers check. Don't save any registers for
4163 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
4164 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
4165 no_callee_saved_registers attribute is called.
4166 (find_drap_reg): Replace no_caller_saved_registers check with
4167 call_saved_registers check.
4168 * config/i386/i386.h (call_saved_registers_type): New enum.
4169 (machine_function): Replace no_caller_saved_registers with
4170 call_saved_registers.
4171 * doc/extend.texi: Document no_callee_saved_registers attribute.
4173 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4175 PR tree-optimization/113614
4176 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
4177 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
4178 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
4180 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4182 PR tree-optimization/113568
4183 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
4184 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
4185 in the widening extension checks.
4187 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4189 * gimple-lower-bitint.cc (gimple_lower_bitint): For
4190 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
4192 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
4194 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
4195 the warning for an attribute-always_inline without inline declaration.
4197 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
4199 PR other/113575
4200 * genopinit.cc (main): Split init_all_optabs into functions
4201 of 1000 patterns each.
4203 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4205 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
4206 TM_MULTILIB_CONFIG.
4207 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
4208 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
4209 -march/-mtune.
4211 2024-01-26 Andrew Stubbs <ams@baylibre.com>
4213 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
4214 * config/gcn/gcn-valu.md (all_convert): New iterator.
4215 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
4216 define_expand, and rename the old one to ...
4217 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
4218 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
4219 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
4220 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
4221 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
4222 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
4223 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
4224 (<u>mulqihi3_scalar): Likewise.
4226 2024-01-26 Richard Biener <rguenther@suse.de>
4228 PR tree-optimization/113602
4229 * tree-data-ref.cc (dr_analyze_innermost): Fail when
4230 the base object isn't addressable.
4232 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4234 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
4235 "--amdhsa-code-object-version=" argument.
4236 (ASM_SPEC): Use it; replace previous version of it.
4238 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4240 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
4241 (pre_vsetvl::emit_vsetvl): Ditto.
4243 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4245 * config/loongarch/lasx.md (vec_extract<mode>_0):
4246 New define_insn_and_split patten.
4248 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4250 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
4252 2024-01-26 Li Wei <liwei@loongson.cn>
4254 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
4256 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4258 PR target/113469
4259 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
4261 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
4263 PR target/100212
4264 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
4265 undefined shift after the call to exact_log2.
4267 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
4269 PR target/100204
4270 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
4271 before taking the negative of it.
4273 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
4275 PR target/113526
4276 * lra-constraints.cc (curr_insn_transform): Change class even for
4277 spilled pseudo successfully matched with with NO_REGS.
4279 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
4281 PR target/113601
4282 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
4284 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
4286 PR target/112987
4287 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
4288 (aarch64_expand_epilogue): Use the new function.
4289 (aarch64_split_compare_and_swap): Likewise.
4290 (aarch64_split_atomic_op): Likewise.
4292 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
4294 PR middle-end/112971
4295 * fold-const.cc (simplify_const_binop): New function for binop
4296 simplification of two constant vectors when element-wise
4297 handling is not necessary.
4298 (const_binop): Call new function.
4300 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
4302 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
4303 * config/riscv/constraints.md: Likewise.
4304 * config/riscv/corev.def: Likewise.
4305 * config/riscv/corev.md: Likewise.
4306 * config/riscv/predicates.md: Likewise.
4307 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
4308 * config/riscv/riscv-ftypes.def: Likewise.
4309 * config/riscv/riscv.opt: Likewise.
4310 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
4311 * doc/extend.texi: Add XCVbitmanip builtin documentation.
4312 * doc/sourcebuild.texi: Likewise.
4314 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
4316 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
4318 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
4320 PR target/113538
4321 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
4322 (riscv_fntype_abi): Ditto.
4323 * config/riscv/riscv.opt: Ditto.
4325 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4327 PR middle-end/113574
4328 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
4329 count against TYPE_PRECISION rather than TYPE_SIZE.
4331 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4333 PR target/113572
4334 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
4335 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
4337 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4339 PR target/113550
4340 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
4341 whether each split instruction is a load that clobbers the source
4342 address. Emit that instruction last if so.
4344 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4346 PR target/113485
4347 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
4348 pattern.
4349 (<optab><Vnarrowq><mode>2): Use it instead of generating a
4350 paradoxical subreg for the input.
4352 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4354 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
4355 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
4356 predecessors dump information.
4358 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4360 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
4361 redundant full available computation.
4362 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4364 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4366 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
4367 * doc/rtl.texi (CONST_VECTOR): Likewise.
4369 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4371 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
4372 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
4373 (pass_vsetvl::execute): Ditto.
4374 * config/riscv/riscv.opt: Ditto.
4376 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
4378 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
4379 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
4381 2024-01-25 Richard Biener <rguenther@suse.de>
4383 PR tree-optimization/113576
4384 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
4385 exits with may_be_zero niters when its the last one.
4387 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
4389 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4390 For symbols of type tls, non-zero Offset is not generated.
4392 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
4394 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
4395 P9 with m32 and mpowerpc64.
4397 2024-01-25 liuhongt <hongtao.liu@intel.com>
4399 * config/i386/i386-options.cc (ix86_option_override_internal):
4400 Enable -mlam=u57 by default when compiled with
4401 -fsanitize=hwaddress.
4403 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
4405 * common/config/riscv/riscv-common.cc (riscv_implied_info):
4406 Remove {"ztso", "a"}.
4408 2024-01-24 Martin Jambor <mjambor@suse.cz>
4410 PR ipa/108007
4411 PR ipa/112616
4412 * cgraph.h (cgraph_edge): Add a parameter to
4413 redirect_call_stmt_to_callee.
4414 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
4415 parameter to modify_call.
4416 (ipa_release_ssas_in_hash): Declare.
4417 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
4418 parameter killed_ssas, pass it to padjs->modify_call.
4419 * ipa-param-manipulation.cc (purge_all_uses): New function.
4420 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
4421 Instead of substituting uses, invoke purge_all_uses. If
4422 hash of killed SSAs has not been provided, create a temporary one
4423 and release SSAs that have been added to it.
4424 (compare_ssa_versions): New function.
4425 (ipa_release_ssas_in_hash): Likewise.
4426 * tree-inline.cc (redirect_all_calls): Create
4427 id->killed_new_ssa_names earlier, pass it to edge redirection,
4428 adjust a comment.
4429 (copy_body): Release SSAs in id->killed_new_ssa_names.
4431 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
4433 PR target/113486
4434 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
4435 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
4437 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
4439 PR target/113095
4440 * config/riscv/sfb.md: New splitters to rewrite single bit
4441 sign extension as the condition to SFB instructions.
4443 2024-01-24 Jan Hubicka <jh@suse.cz>
4445 PR middle-end/88345
4446 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
4447 (fmin-function-alignment): New parameter.
4448 * doc/invoke.texi: (-fmin-function-alignment): Document.
4449 (-falign-functions,-falign-loops,-falign-labels): Mention that
4450 aglinments are ignored in cold code.
4451 * varasm.cc (assemble_start_function): Handle min-function-alignment.
4453 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4455 PR target/109636
4456 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
4457 mulv2di3): Remove.
4458 * config/aarch64/iterators.md (VQDIV): Remove.
4459 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
4460 SVE_I_SIMD_DI): New.
4461 (VPRED, sve_lane_con): Add V4SI and V2DI.
4462 * config/aarch64/aarch64-sve.md (<optab><mode>3,
4463 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
4464 (mul<mode>3): New, split from <optab><mode>3.
4465 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
4466 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
4467 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
4468 SVE_FULL_HSDI_SIMD_DI.
4470 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4472 PR tree-optimization/113552
4473 * config/aarch64/aarch64.cc
4474 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
4476 2024-01-24 Martin Jambor <mjambor@suse.cz>
4478 PR ipa/113490
4479 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
4480 count is equal or greater than the limit. Use the limit from the
4481 callee.
4483 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
4485 * configure.ac: Detect the explicit relocs support for
4486 mips, and define C macro MIPS_EXPLICIT_RELOCS.
4487 * config.in: Regenerated.
4488 * configure: Regenerated.
4489 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
4490 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
4491 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
4492 !TARGET_EXPLICIT_RELOCS instead of just set it.
4493 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
4494 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
4495 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
4496 and define -m(no-)explicit-relocs as aliases.
4498 2024-01-24 Alex Coplan <alex.coplan@arm.com>
4500 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4501 to 1.
4502 (-mlate-ldp-fusion): Likewise.
4504 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4506 * tree-vect-loop.cc (vect_get_vect_def,
4507 vect_create_epilog_for_reduction): Rename main_exit_p to
4508 last_val_reduc_p.
4510 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4512 PR tree-optimization/113364
4513 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
4514 early exits then we must reduce from the first offset for all of them.
4516 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4518 PR target/113495
4519 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
4520 (get_regno): Ditto.
4521 (get_bb_index): Ditto.
4522 (pre_vsetvl::compute_avl_def_data): Ditto.
4523 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
4524 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4526 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
4527 Richard Sandiford <richard.sandiford@arm.com>
4529 PR target/100942
4530 * ccmp.cc (ccmp_candidate_p): Add outer argument.
4531 Allow if the outer is true and the lhs is used more
4532 than once.
4533 (expand_ccmp_expr): Update call to ccmp_candidate_p.
4534 * expr.h (expand_expr_real_gassign): Declare.
4535 * expr.cc (expand_expr_real_gassign): New function, split out from...
4536 (expand_expr_real_1): ...here.
4537 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
4539 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4541 PR target/113089
4542 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
4543 (fixup_debug_use): New.
4544 (fixup_debug_uses_trailing_add): New.
4545 (fixup_debug_uses): New. Use it ...
4546 (ldp_bb_info::fuse_pair): ... here.
4547 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
4548 fix up debug uses of the base register that are affected by
4549 folding in the trailing add insn.
4551 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4553 PR target/113089
4554 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
4555 Update trailing nondebug uses of the base register in the case
4556 of cancelling writeback.
4558 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4560 PR target/113089
4561 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
4562 (debug_insn_use_iterator): New.
4563 (set_info::first_debug_insn_use): New.
4564 (set_info::debug_insn_uses): New.
4565 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
4566 (set_info::first_debug_insn_use): New.
4567 (set_info::debug_insn_uses): New.
4569 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4571 PR target/113356
4572 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
4573 Don't record hazards against the opposite insn in the pair.
4575 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4577 PR target/113070
4578 * config/aarch64/aarch64-ldp-fusion.cc
4579 (struct stp_change_builder): New.
4580 (decide_stp_strategy): Reanme to ...
4581 (try_repurpose_store): ... this.
4582 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
4583 construct stp changes. Fix up uses when inserting new stp insns.
4585 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4587 PR target/113070
4588 * rtl-ssa.h: Include hash-set.h.
4589 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
4590 new_sets parameter and use it to keep track of new user-created sets.
4591 (function_info::apply_changes_to_insn): Also call add_def on new sets.
4592 (function_info::change_insns): Add hash_set to keep track of new
4593 user-created defs. Plumb it through.
4594 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
4595 apply_changes_to_insn.
4597 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4599 PR target/113070
4600 * rtl-ssa/accesses.cc (function_info::create_use): New.
4601 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
4602 Ensure new uses end up referring to permanent defs.
4603 * rtl-ssa/functions.h (function_info::create_use): Declare.
4605 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4607 PR target/113070
4608 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
4609 to finalize_new_accesses from the backwards placement loop, run it
4610 forwards in a separate loop.
4612 2024-01-23 Richard Biener <rguenther@suse.de>
4614 PR tree-optimization/113552
4615 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
4616 floor_log2 instead of exact_log2 on the number of calls.
4618 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
4619 Jakub Jelinek <jakub@redhat.com>
4621 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
4622 decl.
4624 2024-01-23 Richard Biener <rguenther@suse.de>
4626 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4627 Separate single and multi-exit case when creating PHIs between
4628 the main and epilogue.
4630 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
4632 PR target/112989
4633 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
4634 MODE_single variants of functions that don't take tuple arguments.
4636 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4638 PR target/113114
4639 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
4640 Don't assert recog success, just punt if the writeback pair
4641 isn't recognized.
4643 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4645 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
4646 ATTRIBUTE_UNUSED to decl.
4648 2024-01-23 Richard Biener <rguenther@suse.de>
4650 PR debug/107058
4651 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
4652 handle unexpected but bogus DIE contexts when not checking
4653 enabled.
4655 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4657 PR tree-optimization/113462
4658 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
4659 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
4660 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
4661 sizes between 129 and 8192 bytes.
4663 2024-01-23 Xi Ruoyao <xry111@xry111.site>
4665 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4666 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
4667 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
4668 (loongarch_call_tls_get_addr): Do not split symbols of
4669 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
4670 EXPLICIT_RELOCS_AUTO.
4672 2024-01-23 Richard Biener <rguenther@suse.de>
4674 * alias.cc (known_base_value_p): Remove.
4675 (find_base_value): Remove PLUS/MINUS handling
4676 when both operands are not CONST_INT_P.
4678 2024-01-23 Richard Biener <rguenther@suse.de>
4680 PR rtl-optimization/113255
4681 * alias.cc (find_base_term): Remove PLUS/MINUS handling
4682 when both operands are not CONST_INT_P.
4684 2024-01-23 Richard Biener <rguenther@suse.de>
4686 PR debug/112718
4687 * dwarf2out.cc (dwarf2out_finish): Reset all type units
4688 for the fat part of an LTO compile.
4690 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
4692 * doc/sourcebuild.texi: Add attributes for keywords.
4694 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
4696 PR c++/90463
4697 * doc/invoke.texi (Warning Options): Correct lists of options
4698 enabled by -Wall and -Wextra by checking against common.opt
4699 and c-family/c.opt.
4701 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
4703 PR target/113030
4704 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
4705 instead of cpu_optaliases.
4706 (check_arch): Use arch_opt_alias instead of arch_optaliases.
4708 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4710 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
4711 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
4712 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
4714 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4716 PR target/109092
4717 * config/riscv/riscv.md: Use reg instead of subreg.
4719 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
4721 PR other/111966
4722 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
4723 to match the compiler default.
4724 (simple_object_copy_lto_debug_sections): Never unlink the outfile
4725 on error as the caller does so.
4726 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
4727 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
4729 2024-01-22 Richard Biener <rguenther@suse.de>
4731 PR tree-optimization/113373
4732 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4733 Create LC PHIs in the exit blocks where necessary.
4734 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
4735 to handle missing LC PHIs.
4736 (find_connected_edge): Remove.
4737 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
4739 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4741 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
4743 2024-01-22 xuli <xuli1@eswincomputing.com>
4745 PR target/113420
4746 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
4747 (registered_function::overloaded_hash):refactor.
4748 (resolve_overloaded_builtin):avoid internal ICE.
4750 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
4752 PR target/82420
4753 PR target/111279
4754 * calls.cc (emit_library_call_value_1): Pass valid TYPE
4755 to emit_push_insn.
4756 * expr.cc (emit_push_insn): Likewise.
4758 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4760 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
4761 correcction version of last change.
4763 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4765 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
4766 fix bugs in signature.
4768 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
4769 Richard Biener <rguenther@suse.de>
4771 PR rtl-optimization/111267
4772 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
4773 profitable_p method to likely_profitable_p.
4774 (try_fwprop_subst_node): Update call to likely_profitable_p.
4775 Only bail-out early when !prop.likely_profitable_p for instructions
4776 that are not single sets. When comparing costs, bail-out if the
4777 cost is unchanged and !prop.likely_profitable_p.
4779 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4781 PR c++/90464
4782 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
4783 isn't enabled by -Wunused unless -Wextra is provided, and that
4784 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
4785 -Wunused doesn't enable -Wunused-* options documented as behaving
4786 otherwise, and list them explicitly.
4788 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4790 PR c/109708
4791 * doc/invoke.texi (Warning Options): Fix broken example and
4792 clean up/reorganize the others. Also describe what the short-form
4793 options mean.
4795 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
4797 PR c/102998
4798 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
4799 (Warning Options): Correct/edit discussion of -Warray-parameter
4800 to make the first example less confusing, and fill in missing info.
4802 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4804 PR tree-optimization/113462
4805 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
4806 Handle rhs1 INTEGER_CST like SSA_NAME.
4808 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4810 PR tree-optimization/113491
4811 * tree-switch-conversion.cc (switch_conversion::build_constructors):
4812 If elt.index has precision higher than sizetype, fold_convert it to
4813 sizetype.
4814 (switch_conversion::array_value_type): Return type if type is
4815 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
4816 (switch_conversion::build_arrays): Use unsigned_type_for rather than
4817 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
4818 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
4819 higher than sizetype, use sizetype as tidx type and fold_convert the
4820 subtraction to sizetype.
4822 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4824 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
4825 (riscv_vector_mode_supported_any_target_p): Ditto.
4827 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4829 PR target/110934
4830 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
4831 (TARGET_ZERO_CALL_USED_REGS): Define.
4833 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4835 PR target/108640
4836 * config/m68k/m68k.cc (output_andsi3): Use QImode for
4837 address adjusted for 1-byte RMW access.
4838 (output_iorsi3): Likewise.
4839 (output_xorsi3): Likewise.
4841 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4843 * doc/invoke.texi (RISC-V Options): Add list of supported
4844 extensions.
4846 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4848 PR target/113495
4849 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
4850 (RVV_VUNDEF): Ditto.
4851 * config/riscv/riscv-vsetvl.cc: Add timevar.
4853 2024-01-19 Richard Biener <rguenther@suse.de>
4855 PR debug/113488
4856 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
4857 an early DIE but there should be, do not pretend there is.
4859 2024-01-19 Richard Biener <rguenther@suse.de>
4861 PR tree-optimization/113494
4862 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4863 Handle endless loop on exit. Handle re-allocated PHI.
4865 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4867 PR tree-optimization/113464
4868 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
4869 optimize loads into GIMPLE_ASM stmts.
4871 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4873 PR tree-optimization/113463
4874 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
4875 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
4876 lhs.
4878 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4880 PR tree-optimization/113459
4881 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
4882 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
4883 of SCALAR_INT_TYPE_MODE if type has BLKmode.
4884 (vn_reference_lookup_3): Likewise. Formatting fix.
4886 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4887 Richard Biener <rguenther@suse.de>
4889 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
4890 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
4891 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
4892 but adjust_address also for BLKmode mode and MEM op0.
4894 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
4896 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
4897 extensions.
4899 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4901 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
4903 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4905 * common/config/riscv/riscv-common.cc
4906 (riscv_subset_list::parse_std_ext): Remove.
4907 (riscv_subset_list::parse_multiletter_ext): Remove.
4908 * config/riscv/riscv-subset.h
4909 (riscv_subset_list::parse_std_ext): Remove.
4910 (riscv_subset_list::parse_multiletter_ext): Remove.
4912 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4914 * common/config/riscv/riscv-common.cc
4915 (riscv_subset_list::parse_single_std_ext): New parameter.
4916 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4917 (riscv_subset_list::parse_single_ext): Ditto.
4918 (riscv_subset_list::parse): Relax the order for the input of ISA
4919 string.
4920 * config/riscv/riscv-subset.h
4921 (riscv_subset_list::parse_single_std_ext): New parameter.
4922 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4923 (riscv_subset_list::parse_single_ext): Ditto.
4925 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4927 * common/config/riscv/riscv-common.cc
4928 (riscv_subset_list::parse_base_ext): New.
4929 (riscv_subset_list::parse): Extract part of logic into
4930 riscv_subset_list::parse_base_ext.
4931 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
4932 New.
4934 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4936 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
4937 sorry message.
4939 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
4941 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
4942 UNSPEC_CLMUL_VC.
4944 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
4946 PR c/110029
4947 * doc/extend.texi (Common Variable Attributes): Explain what
4948 happens when multiple variables with cleanups are in the same scope.
4950 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4952 PR ipa/108470
4953 * doc/extend.texi (Common Function Attributes): Document that
4954 noinline also disables some interprocedural optimizations and
4955 improve flow to the part about using inline asm instead to
4956 disable calls from being optimized away completely. Remove the
4957 sentence that says noipa is mainly for internal compiler testing.
4959 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
4961 PR tree-optimization/69807
4962 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
4964 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
4966 PR target/108521
4967 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
4968 from x86 Windows Options.
4970 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4972 PR c/107942
4973 * doc/extend.texi (C Extensions): Add new section to menu.
4974 (Function Attributes): Move dangling index entries to....
4975 (Const and Volatile Functions): New section.
4977 2024-01-18 David Malcolm <dmalcolm@redhat.com>
4979 PR middle-end/112684
4980 * toplev.cc (toplev::main): Don't ICE in
4981 -fdiagnostics-generate-patch when exiting after options,
4982 since no edit context will have been created.
4984 2024-01-18 Richard Biener <rguenther@suse.de>
4986 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
4987 operands vector.
4989 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4991 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
4992 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
4994 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4995 Jin Ma <jinma@linux.alibaba.com>
4996 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4997 Christoph Müllner <christoph.muellner@vrull.eu>
4999 * config/riscv/thead.cc
5000 (th_asm_output_opcode): Rewrite some instructions.
5002 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5003 Jin Ma <jinma@linux.alibaba.com>
5004 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5005 Christoph Müllner <christoph.muellner@vrull.eu>
5007 * config/riscv/riscv.md (none,thv,rvv): New attribute.
5008 (no,yes): Add an attribute to disable alternative
5009 for xtheadvector or RVV1.0.
5010 * config/riscv/vector.md:
5011 Disable alternatives that destination register overlaps
5012 source register group for xtheadvector.
5014 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5015 Jin Ma <jinma@linux.alibaba.com>
5016 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5017 Christoph Müllner <christoph.muellner@vrull.eu>
5019 * config/riscv/riscv-vector-builtins-bases.cc
5020 (class th_loadstore_width): Define new builtin bases.
5021 (class th_extract): Define new builtin bases.
5022 (BASE): Define new builtin bases.
5023 * config/riscv/riscv-vector-builtins-bases.h:
5024 Define new builtin class.
5025 * config/riscv/riscv-vector-builtins-shapes.cc
5026 (struct th_loadstore_width_def): Define new builtin shapes.
5027 (struct th_indexed_loadstore_width_def):
5028 Define new builtin shapes.
5029 (struct th_extract_def): Define new builtin shapes.
5030 (SHAPE): Define new builtin shapes.
5031 * config/riscv/riscv-vector-builtins-shapes.h:
5032 Define new builtin shapes.
5033 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
5034 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
5035 * config/riscv/riscv-vector-builtins.h
5036 (enum required_ext): Add new XTheadVector member.
5037 (struct function_group_info): Likewise.
5038 * config/riscv/t-riscv:
5039 Add thead-vector-builtins-functions.def
5040 * config/riscv/thead-vector.md
5041 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
5042 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
5043 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
5044 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
5045 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
5046 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
5047 (@pred_th_extract<mode>): Likewise.
5048 (*pred_th_extract<mode>): Likewise.
5049 * config/riscv/thead-vector-builtins-functions.def: New file.
5051 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5052 Jin Ma <jinma@linux.alibaba.com>
5053 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5054 Christoph Müllner <christoph.muellner@vrull.eu>
5056 * config.gcc: Add files for XTheadVector intrinsics.
5057 * config/riscv/autovec.md: Guard XTheadVector.
5058 * config/riscv/predicates.md: Disable immediate vl
5059 for XTheadVector.
5060 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
5061 Add pragma for XTheadVector.
5062 * config/riscv/riscv-string.cc (riscv_expand_block_move):
5063 Guard XTheadVector.
5064 * config/riscv/riscv-v.cc (vls_mode_valid_p):
5065 Avoid autovec.
5066 * config/riscv/riscv-vector-builtins-bases.cc:
5067 Do not normalize vsetvl instructions for XTheadVector.
5068 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
5069 New check type function.
5070 (build_one): Adjust for XTheadVector.
5071 * config/riscv/riscv-vector-switch.def (ENTRY):
5072 Disable fractional mode for the XTheadVector extension.
5073 (TUPLE_ENTRY): Likewise.
5074 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
5075 Guard XTheadVector.
5076 (riscv_preferred_simd_mode): Likewsie.
5077 (riscv_autovectorize_vector_modes): Likewise.
5078 (riscv_vector_mode_supported_any_target_p): Likewise.
5079 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
5080 * config/riscv/thead.cc (th_asm_output_opcode):
5081 Rewrite vsetvl instructions.
5082 * config/riscv/vector.md:
5083 Include thead-vector.md and change fractional LMUL
5084 into 1 for vbool.
5085 * config/riscv/riscv_th_vector.h: New file.
5086 * config/riscv/thead-vector.md: New file.
5088 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5089 Jin Ma <jinma@linux.alibaba.com>
5090 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5091 Christoph Müllner <christoph.muellner@vrull.eu>
5093 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
5094 Add new function to add assembler insn code prefix/suffix.
5095 (th_asm_output_opcode):
5096 Add Thead function to add assembler insn code prefix/suffix.
5097 * config/riscv/riscv.cc (riscv_asm_output_opcode):
5098 Implement function to add assembler insn code prefix/suffix.
5099 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
5100 Add new function to add assembler insn code prefix/suffix.
5101 * config/riscv/thead.cc (th_asm_output_opcode):
5102 Implement Thead function to add assembler insn code
5103 prefix/suffix.
5105 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5106 Jin Ma <jinma@linux.alibaba.com>
5107 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5108 Christoph Müllner <christoph.muellner@vrull.eu>
5110 * common/config/riscv/riscv-common.cc
5111 (riscv_subset_list::parse): Add new vendor extension.
5112 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
5113 Add test marco.
5114 * config/riscv/riscv.opt: Add new mask.
5116 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5118 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
5119 to be conditional on macosx-version-min.
5121 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5123 * config/darwin.cc (darwin_objc1_section): Use the correct
5124 meta-data version for constant strings.
5125 (machopic_select_section): Assert if we fail to handle CFString
5126 sections as Obejctive-C meta-data or drectly.
5128 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5130 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
5131 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
5132 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
5133 versions when the object format is Mach-O.
5135 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5137 PR target/105522
5138 * config/darwin.cc (machopic_select_section): Handle C and C++
5139 CFStrings.
5140 (darwin_rename_builtins): Move this out of the CFString code.
5141 (darwin_libc_has_function): Likewise.
5142 (darwin_build_constant_cfstring): Create an anonymous var to
5143 hold each CFString.
5144 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
5145 CFstrings.
5147 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5149 PR bootstrap/113445
5150 * haifa-sched.cc (dep_list_size): Make global.
5151 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
5152 * sched-int.h (dep_list_size): Declare.
5154 2024-01-18 Martin Jambor <mjambor@suse.cz>
5156 PR tree-optimization/110422
5157 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
5158 gotos.
5160 2024-01-18 Richard Biener <rguenther@suse.de>
5162 PR tree-optimization/113475
5163 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
5164 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
5165 (phi_analyzer::~phi_analyzer): Deallocate and free collected
5166 phi_grous.
5167 (phi_analyzer::process_phi): Record allocated phi_groups.
5169 2024-01-18 Richard Biener <rguenther@suse.de>
5171 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
5172 storage for gvec_oprnds elements.
5174 2024-01-18 Richard Biener <rguenther@suse.de>
5176 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
5177 prefer all later exits we can handle.
5178 (vect_analyze_loop_form): Free the allocated loop body.
5179 Adjust comments.
5181 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5183 * config/avr/avr-log.cc: Tabify.
5185 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5187 * config/riscv/autovec.md: Support vi variant.
5189 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5191 * config/avr/avr-devices.cc: Tabify.
5193 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5195 * config/avr/avr-c.cc: Tabify.
5197 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5199 * config/avr/driver-avr.cc: Tabify.
5201 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5203 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
5205 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5207 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
5209 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5211 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
5212 minline-strcmp, minline-strncmp, minline-strlen,
5213 -param=riscv-vector-abi): Remove Bool keywords.
5215 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5217 PR target/113122
5218 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
5219 support. Add missing space after , in emitted assembly in some
5220 cases. Formatting fixes.
5222 2024-01-18 Xi Ruoyao <xry111@xry111.site>
5224 * config/loongarch/loongarch.md (movsi_internal): Remove
5225 constraint z.
5227 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5229 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
5230 in the diagnostic, and capitalize the device name.
5231 (print_mcu): Generate specs such that:
5232 <*check_rodata_in_ram>: New.
5233 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
5234 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
5235 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
5237 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5239 PR other/113399
5240 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
5241 Common and Optimization.
5243 2024-01-18 Richard Biener <rguenther@suse.de>
5245 PR tree-optimization/113431
5246 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
5247 When there is an invariant load we might not preserve
5248 scalar order.
5250 2024-01-18 Richard Biener <rguenther@suse.de>
5252 PR tree-optimization/113374
5253 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
5254 * tree-vect-loop.cc (move_early_exit_stmts): Update
5255 virtual LC PHIs.
5256 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5257 Refactor. Preserve virtual LC PHIs on all exits.
5259 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
5261 * config/loongarch/loongarch.cc (loongarch_split_symbol):
5262 Assign the '/u' attribute to the mem.
5264 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5266 PR middle-end/110847
5267 * doc/invoke.texi (Option Summary): Document negative forms of
5268 -Wtsan and -Wxor-used-as-pow.
5269 (Warning Options): Likewise.
5271 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5273 PR target/113429
5274 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
5276 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5278 * doc/extend.texi (Common Function Attributes): Re-alphabetize
5279 the table.
5280 (Common Variable Attributes): Likewise.
5281 (Common Type Attributes): Likewise.
5283 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5285 PR middle-end/111659
5286 * doc/extend.texi (Common Variable Attributes): Fix long lines
5287 in documentation of strict_flex_array + other minor copy-editing.
5288 Add a cross-reference to -Wstrict-flex-arrays.
5289 * doc/invoke.texi (Option Summary): Fix whitespace in tables
5290 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
5291 (C Dialect Options): Combine the docs for the two
5292 -fstrict-flex-arrays forms into a single entry. Note this option
5293 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
5294 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
5295 Minor copy-editing. Add cross references to the strict_flex_array
5296 attribute and -fstrict-flex-arrays option. Add note that this
5297 option depends on -ftree-vrp.
5299 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
5301 PR target/113221
5302 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
5303 only allow REG operands instead of allowing all.
5305 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5307 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
5308 Remove redundant checks in else condition for readablity.
5309 (earliest_fuse_vsetvl_info) Print iteration count in debug
5310 prints.
5311 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
5312 dump details in certain cases.
5314 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5316 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
5317 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
5318 * config/riscv/riscv-vsetvl.cc
5319 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
5320 (pass_vsetvl::execute): Use vsetvl_strategy.
5322 2024-01-17 Jan Hubicka <jh@suse.cz>
5324 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
5325 accidental hack reseting offset.
5327 2024-01-17 Jan Hubicka <jh@suse.cz>
5329 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
5330 handling of X86_TUNE_AVOID_512FMA_CHAINS.
5332 2024-01-17 Jan Hubicka <jh@suse.cz>
5333 Jakub Jelinek <jakub@redhat.com>
5335 PR tree-optimization/110852
5336 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
5337 binary operations
5338 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
5339 PRED_COMBINED_VALUE_PREDICTIONS_PHI
5340 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
5341 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
5343 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5345 PR tree-optimization/113421
5346 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
5347 comment.
5348 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
5349 formatting. Start at vop rather than cvop even if stmt is a store
5350 and needs_operand_addr.
5352 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5354 PR middle-end/113410
5355 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
5356 If access_nelts is integral with larger precision than sizetype,
5357 fold_convert it to sizetype.
5359 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5361 PR tree-optimization/113408
5362 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
5363 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
5364 to handle_cast.
5366 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5368 PR middle-end/113406
5369 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
5370 regardless of whether is_gimple_reg_type (restype) or not.
5372 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5374 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
5375 funcions -> functions, and use were instead of was.
5376 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
5377 and guaranteee -> guarantee.
5378 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
5380 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5382 PR middle-end/113409
5383 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
5384 INTEGER_TYPE.
5385 (omp_extract_for_data): Use build_bitint_type rather than
5386 build_nonstandard_integer_type if either iter_type or loop->v type
5387 is BITINT_TYPE.
5388 * omp-expand.cc (expand_omp_for_generic,
5389 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
5390 BITINT_TYPE like INTEGER_TYPE.
5392 2024-01-17 Richard Biener <rguenther@suse.de>
5394 PR tree-optimization/113371
5395 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
5396 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5397 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
5398 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5400 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5402 PR rtl-optimization/96388
5403 PR rtl-optimization/111554
5404 * sched-deps.cc (find_inc): Avoid exponential behavior.
5406 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5408 PR c/111693
5409 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
5410 from C++ Language Options to Warning Options. Add entry for
5411 -Wuse-after-free.
5412 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
5413 from here....
5414 (Warning Options): ...to here. Minor copy-editing to fix typo
5415 and grammar.
5417 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
5419 * config/mips/mips.cc (mips_compute_frame_info): If another
5420 register is used as global_pointer, mark $GP live false.
5422 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5424 PR target/112973
5425 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
5426 give the section a light copy-editing pass.
5428 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5430 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
5431 * config/aarch64/aarch64-tune.md: Regenerated.
5432 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
5434 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5436 PR target/112573
5437 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
5438 badly formed CONST expressions.
5440 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5442 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
5444 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5446 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
5447 * config/sparc/sync.md (membar_storeload): Turn into named insn
5448 and add GR712RC errata workaround.
5449 (membar_v8): Add GR712RC errata workaround.
5451 2024-01-16 Andreas Larsson <andreas@gaisler.com>
5453 * config/sparc/sync.md (*membar_storeload_leon3): Remove
5454 (*membar_storeload): Enable for LEON
5456 2024-01-16 Jakub Jelinek <jakub@redhat.com>
5458 PR tree-optimization/113372
5459 PR middle-end/90348
5460 PR middle-end/110115
5461 PR middle-end/111422
5462 * cfgexpand.cc (add_scope_conflicts_2): New function.
5463 (add_scope_conflicts_1): Use it.
5465 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
5467 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
5468 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
5469 * doc/avr-mmcu.texi: Regenerate.
5471 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
5473 PR tree-optimization/113091
5474 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
5475 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
5476 scalar use with new function.
5477 (vect_bb_slp_mark_live_stmts): New function as entry to existing
5478 overriden functions with same name.
5479 (vect_slp_analyze_operations): Call new entry function to mark
5480 live statements.
5482 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5484 PR target/113404
5485 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
5486 for RVV in big-endian mode.
5488 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
5490 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
5491 (riscv_pass_in_vector_p): Delete.
5492 (riscv_init_cumulative_args): Delete the checking.
5493 (riscv_get_arg_info): Delete the checking.
5494 (riscv_function_value): Delete the checking.
5495 * config/riscv/riscv.h: Delete the member for checking.
5497 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5499 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
5501 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5503 * config.gcc: Include riscv_bitmanip.h.
5504 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
5505 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
5506 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
5507 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
5508 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
5509 * config/riscv/riscv-ftypes.def (2): New ftypes.
5510 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
5511 (RISCV_BUILTIN_NO_PREFIX): Likewise.
5512 * config/riscv/riscv_bitmanip.h: New file.
5514 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5516 * config.gcc: Include riscv_crypto.h.
5517 * config/riscv/riscv_crypto.h: New file.
5519 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
5521 PR middle-end/113354
5522 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
5523 in the insn if the corresponding operand does not require hard
5524 register anymore.
5526 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5528 PR target/107201
5529 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
5530 * config/avr/driver-avr.cc (avr_no_devlib): New function.
5531 (avr_devicespecs_file): Use it to remove -nodevicelib from the
5532 options for cores only.
5533 * config/avr/avr-arch.h (avr_get_parch): New prototype.
5534 * config/avr/avr-devices.cc (avr_get_parch): New function.
5536 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5538 PR target/113247
5539 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
5540 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
5541 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
5543 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5545 PR target/113281
5546 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
5547 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
5548 * config/riscv/riscv-vector-costs.h: New function.
5550 2024-01-15 Richard Biener <rguenther@suse.de>
5552 PR tree-optimization/113385
5553 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5554 First redirect, then split the exit edge.
5556 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5558 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
5559 Remove m_num_vector_iterations.
5560 * config/riscv/riscv-vector-costs.h: Ditto.
5562 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
5564 PR target/113156
5565 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
5566 (-mbranch-cost): Set "Optimization" flag.
5568 2024-01-15 Jakub Jelinek <jakub@redhat.com>
5570 PR tree-optimization/113370
5571 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
5572 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
5573 set it to just prec % limb_prec.
5575 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5577 PR target/113393
5578 * config/riscv/vector.md: Fix ternary attributes.
5580 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
5582 PR target/112944
5583 * configure.ac [target=avr]: Check availability of emulations
5584 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
5585 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
5586 * configure: Regenerate.
5587 * config.in: Regenerate.
5588 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
5589 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
5590 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
5591 * config/avr/avr-arch.h (enum avr_device_specific_features):
5592 Add AVR_ISA_FLMAP.
5593 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
5594 AVR_ISA_FLMAP.
5595 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
5596 (avr_set_core_architecture): Set avr_arch_index.
5597 (have_avrxmega2_flmap, have_avrxmega4_flmap)
5598 (have_avrxmega3_rodata_in_flash): Set new static const bool according
5599 to configure results.
5600 (avr_rodata_in_flash_p): New function using them.
5601 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
5602 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
5603 (avr_asm_named_section): Track avr_has_rodata_p.
5604 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
5605 and not avr_rodata_in_flash_p ().
5606 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
5607 (LINK_SPEC): Add %(link_rodata_in_ram).
5608 (LINK_ARCH_SPEC): Remove.
5609 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
5610 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
5611 const bool according to configure results.
5612 (diagnose_mrodata_in_ram): New function.
5613 (print_mcu): Generate specs with the following changes:
5614 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
5615 need to extend avr/specs.h each time we add a new bell or whistle.
5616 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
5617 -m[no-]rodata-in-ram.
5618 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
5619 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
5620 <*cpp>: Add %(cpp_rodata_in_ram).
5621 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
5622 requested.
5623 <*self_spec>: Add -mflmap or %<mflmap as needed.
5625 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
5627 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
5628 not the GPR iterator. Adjust pattern name and mode attribute
5629 accordingly.
5631 2024-01-13 Jakub Jelinek <jakub@redhat.com>
5633 PR tree-optimization/113361
5634 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5635 Fix up determination of the type for > limb_prec constants.
5637 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5639 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
5640 Add web-link to the avr-gcc wiki.
5642 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5644 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
5645 documentation for a version without argument, which is not supported.
5647 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5649 * config/arm/arm_neon.h
5650 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
5651 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
5652 (vld1_f16_x4, vld1_f32_x4): New.
5653 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
5654 (vld1_bf16_x4): New.
5655 (vld1q_types_x4): Updated to use vld1q_x4
5656 from arm_neon_builtins.def
5657 * config/arm/arm_neon_builtins.def
5658 (vld1_x4): Updated entries.
5659 (vld1q_x4): New entries, but comes from the old vld1_x4
5660 * config/arm/neon.md
5661 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
5663 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5665 * config/arm/arm_neon.h
5666 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
5667 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
5668 (vld1_f16_x3, vld1_f32_x3): New.
5669 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
5670 (vld1_bf16_x3): New.
5671 (vld1q_types_x3): Updated to use vld1q_x3 from
5672 arm_neon_builtins.def
5673 * config/arm/arm_neon_builtins.def
5674 (vld1_x3): Updated entries.
5675 (vld1q_x3): New entries, but comes from the old vld1_x2
5676 * config/arm/neon.md
5677 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
5679 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5681 * config/arm/arm_neon.h
5682 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
5683 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
5684 (vld1_f16_x2, vld1_f32_x2): New.
5685 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
5686 (vld1_bf16_x2): New.
5687 (vld1q_types_x2): Updated to use vld1q_x2 from
5688 arm_neon_builtins.def
5689 * config/arm/arm_neon_builtins.def
5690 (vld1_x2): Updated entries.
5691 (vld1q_x2): New entries, but comes from the old vld1_x2
5692 * config/arm/neon.md
5693 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5694 neon_vld1_x2<mode>.
5696 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5698 * config/arm/arm_neon.h
5699 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
5700 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
5701 (vst1q_f16_x4, vst1q_f32_x4): New.
5702 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
5703 (vst1q_bf16_x4): New.
5704 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
5705 * config/arm/neon.md
5706 (neon_vst1q_x4<mode>): New.
5707 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
5708 * config/arm/unspecs.md
5709 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
5711 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5713 * config/arm/arm_neon.h
5714 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
5715 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
5716 (vst1q_f16_x3, vst1q_f32_x3): New.
5717 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
5718 (vst1q_bf16_x3): New.
5719 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
5720 * config/arm/neon.md
5721 (neon_vst1q_x3<mode>): New.
5722 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
5723 * config/arm/unspecs.md
5724 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
5726 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5728 * config/arm/arm_neon.h
5729 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
5730 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
5731 (vst1q_f16_x2, vst1q_f32_x2): New.
5732 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
5733 (vst1q_bf16_x2): New.
5734 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
5735 * config/arm/neon.md
5736 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5737 neon_vst1_x2<mode>.
5738 * config/arm/iterators.md
5739 (VMEMX2): New mode iterator.
5740 (VMEMX2_q): New mode attribute.
5742 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5744 * config/arm/arm_neon.h
5745 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
5746 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
5747 (vst1_f16_x4, vst1_f32_x4): New.
5748 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
5749 (vst1_bf16_x4): New.
5750 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
5751 * config/arm/neon.md (vst1_x4<mode>): New.
5753 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5755 * config/arm/arm_neon.h
5756 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
5757 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
5758 (vst1_f16_x3, vst1_f32_x3): New.
5759 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
5760 (vst1_bf16_x3): New.
5761 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
5762 * config/arm/neon.md (vst1_x3<mode>): New.
5764 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5766 * config/arm/arm_neon.h
5767 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
5768 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
5769 (vst1_f16_x2, vst1_f32_x2): New.
5770 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
5771 (vst1_bf16_x2): New.
5772 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
5773 * config/arm/neon.md (vst1_x2<mode>): New.
5775 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5777 * config/arm/arm_neon.h
5778 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
5779 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
5780 (vld1q_f16_x4, vld1q_f32_x4): New.
5781 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
5782 (vld1q_bf16_x4): New.
5783 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
5784 * config/arm/neon.md
5785 (neon_vld1_x4<mode>): New.
5786 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
5787 * config/arm/unspecs.md
5788 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
5790 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5792 * config/arm/arm_neon.h
5793 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
5794 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
5795 (vld1q_f16_x3, vld1q_f32_x3): New.
5796 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
5797 (vld1q_bf16_x3): New.
5798 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
5799 * config/arm/neon.md
5800 (neon_vld1_x3<mode>): New.
5801 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
5802 * config/arm/unspecs.md
5803 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
5805 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5807 * config/arm/arm_neon.h
5808 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
5809 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
5810 (vld1q_f16_x2, vld1q_f32_x2): New.
5811 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
5812 (vld1q_bf16_x2): New.
5813 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
5814 * config/arm/neon.md (vld1_x2<mode>): New.
5816 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5818 PR tree-optimization/113287
5819 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
5821 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5823 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
5824 * tree-vect-loop.cc (vect_transform_loop): Likewise.
5826 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5828 PR tree-optimization/113178
5829 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
5830 alternate exits.
5832 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5834 PR tree-optimization/113237
5835 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
5836 existing LCSSA variable for exit when all exits are early break.
5838 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5840 PR tree-optimization/113137
5841 PR tree-optimization/113136
5842 PR tree-optimization/113172
5843 PR tree-optimization/113178
5844 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5845 Maintain PHIs on inverted loops.
5846 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
5847 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
5848 latch.
5849 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
5851 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5853 PR tree-optimization/113135
5854 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
5855 dependency analysis.
5857 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
5859 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
5860 diagnostics class member name for abort of error.
5862 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5864 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
5865 format string to %s argument.
5867 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
5868 Jakub Jelinek <jakub@redhat.com>
5870 PR middle-end/113182
5871 * varasm.cc (process_pending_assemble_externals,
5872 assemble_external_libcall): Use targetm.strip_name_encoding
5873 before calling get_identifier.
5875 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5877 PR target/113196
5878 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
5879 New member variable.
5880 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
5881 Declare.
5882 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
5883 * config/aarch64/aarch64-simd.md
5884 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
5885 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
5886 zip2 for zero-extends to...
5887 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
5888 instruction. Fix big-endian handling.
5889 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
5890 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
5891 zip1 for zero-extends to...
5892 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
5893 Fix big-endian handling.
5894 (*aarch64_zip1_uxtl): New pattern.
5895 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
5896 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
5897 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
5898 (aarch64_gen_shareable_zero): Use it.
5899 (aarch64_split_simd_shift_p): New function.
5901 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5903 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
5904 (function_beg_insn): New macro.
5905 * function.cc (expand_function_start): Initialize function_beg_insn.
5907 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5909 PR target/112989
5910 * config/aarch64/aarch64-sve-builtins.h
5911 (function_builder::m_overload_names): Replace with...
5912 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
5913 new global.
5914 (add_overloaded_function): Update accordingly, using get_identifier
5915 to get a GGC-friendly record of the name.
5917 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5919 PR target/112989
5920 * config/aarch64/aarch64-sve-builtins.def: Don't include
5921 aarch64-sve-builtins-sme.def.
5922 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
5923 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
5924 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
5925 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
5926 requires AARCH64_FL_SME2.
5927 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
5928 AARCH64_FL_SME adjustment here.
5929 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
5930 include SME intrinsics.
5931 (sme_function_groups): New array.
5932 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
5933 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
5935 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5937 PR target/113281
5938 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
5939 (struct cpu_vector_cost): Add regmove struct.
5940 (get_vector_costs): Export as global.
5941 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
5942 (costs::add_stmt_cost): Ditto.
5943 * config/riscv/riscv.cc (get_common_costs): Export global function.
5945 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5947 PR tree-optimization/113334
5948 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
5949 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
5950 to determine if number should be extended by all ones rather than zero
5951 extended.
5953 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5955 PR tree-optimization/113330
5956 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
5957 too large size.
5959 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5961 PR tree-optimization/113323
5962 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
5963 check for lhs being large/huge _BitInt not in m_names.
5965 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5967 PR tree-optimization/113316
5968 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
5969 uninitialized large/huge _BitInt arguments to calls.
5971 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5973 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
5974 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
5975 CEIL (TYPE_PRECISION (t), limb_prec).
5976 (bitint_large_huge::handle_cast): Likewise.
5978 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
5980 PR sanitizer/113284
5981 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5982 Use assemble_function_label_final () for Power ELF V1 ABI.
5983 * output.h (assemble_function_label_final): New function.
5984 * varasm.cc (assemble_function_label_raw): Use
5985 assemble_function_label_final ().
5986 (assemble_function_label_final): New function.
5988 2024-01-12 Richard Biener <rguenther@suse.de>
5990 PR middle-end/113344
5991 * match.pd ((double)float CMP (double)float -> float CMP float):
5992 Perform result type check only for vectors.
5993 * fold-const.cc (fold_binary_loc): Likewise.
5995 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
5997 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
5998 (usdot_prod<mode>): Ditto.
5999 (sdot_prod<mode>): Ditto.
6000 (udot_prod<mode>): Ditto.
6002 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6004 PR target/113288
6005 * config/i386/i386-c.cc (ix86_target_macros_internal):
6006 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
6008 2024-01-12 Richard Biener <rguenther@suse.de>
6010 PR target/112280
6011 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
6012 Do not generate code when d.testing_p.
6014 2024-01-12 liuhongt <hongtao.liu@intel.com>
6016 PR target/113039
6017 * doc/invoke.texi (fcf-protection=): Update documents.
6019 2024-01-12 Pan Li <pan2.li@intel.com>
6021 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
6022 comments of predicate func riscv_v_ext_mode_p.
6024 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
6026 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
6027 Modify ABI-name length of vfloat16m8_t
6029 2024-01-12 Li Wei <liwei@loongson.cn>
6031 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
6032 Adjust.
6034 2024-01-12 Li Wei <liwei@loongson.cn>
6036 * config/loongarch/loongarch.md (add<mode>3): Removed.
6037 (*addsi3): New.
6038 (addsi3): Ditto.
6039 (adddi3): Ditto.
6040 (*addsi3_extended): Removed.
6041 (addsi3_extended): New.
6043 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
6045 * config/riscv/thead.md: Add limits for splits.
6047 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6049 PR middle-end/113322
6050 * expr.cc (do_store_flag): Don't try single bit tests with
6051 comparison on vector types.
6053 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6055 PR tree-optimization/113301
6056 * match.pd (`1/x`): Delay signed case until late.
6058 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6060 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
6061 and -msp8 to...
6062 (AVR Internal Options): ...this new @subsubsection.
6064 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
6066 PR rtl-optimization/112918
6067 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
6068 (in_class_p): Restrict condition for narrowing class in case of
6069 allow_all_reload_class_changes_p.
6070 (process_alt_operands): Try to match operand without and with
6071 narrowing reg class. Discourage narrowing the class. Finish insn
6072 matching only if there is no class narrowing.
6073 (curr_insn_transform): Pass true to in_class_p for reg operand win.
6075 2024-01-11 Richard Biener <rguenther@suse.de>
6077 PR tree-optimization/112505
6078 * tree-vect-loop.cc (vectorizable_induction): Reject
6079 bit-precision induction.
6081 2024-01-11 Richard Biener <rguenther@suse.de>
6083 PR tree-optimization/113126
6084 * match.pd ((double)float CMP (double)float -> float CMP float):
6085 Make sure the boolean type is the same.
6086 * fold-const.cc (fold_binary_loc): Likewise.
6088 2024-01-11 Richard Biener <rguenther@suse.de>
6090 PR tree-optimization/112636
6091 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
6092 estimate_numbers_of_iterations before querying
6093 get_max_loop_iterations_int.
6094 (pass_ch::execute): Initialize SCEV and loops appropriately.
6096 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6098 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
6099 Reduced Tiny.
6100 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
6101 * doc/extend.texi (AVR Variable Attributes): Improve documentation
6102 of io, io_low and address attributes.
6103 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
6104 * doc/avr-mmcu.texi: Rebuild.
6106 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
6108 PR target/113233
6109 * config/loongarch/genopts/loongarch.opt.in: Mark options with
6110 the "Save" property.
6111 * config/loongarch/loongarch.opt: Same.
6112 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
6113 according to la_target.
6114 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
6115 RESTORE} for the la_target structure; Rename option conditions
6116 to have the same "la_" prefix.
6117 * config/loongarch/loongarch.h: Same.
6119 2024-01-11 Pan Li <pan2.li@intel.com>
6121 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
6122 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
6124 2024-01-11 Alex Coplan <alex.coplan@arm.com>
6126 PR target/113077
6127 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
6128 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
6129 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
6130 synthesize these if needed. Update caller ...
6131 (ldp_bb_info::fuse_pair): ... here.
6132 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
6133 and either insn is frame-related.
6134 (find_trailing_add): Punt on frame-related insns.
6135 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
6136 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
6138 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
6140 * config/mips/mips.cc (mips_start_function_definition):
6141 Add ATTRIBUTE_UNUSED.
6143 2024-01-11 Richard Biener <rguenther@suse.de>
6145 PR middle-end/112740
6146 * expr.cc (store_constructor): Check the integer vector
6147 mask has a single bit per element before using sign-extension
6148 to expand an uniform vector.
6150 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6152 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
6153 preempt VLS on unknown NITERS loop.
6155 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
6157 * doc/invoke.texi: Add -mevex512.
6159 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
6161 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
6162 (*nor<mode>3): Likewise.
6163 (nor<mode>3): Likewise.
6164 (*negsi2_extended): New template.
6165 (*<optab>si3_internal): Likewise.
6166 (*one_cmplsi2_internal): Likewise.
6167 (*norsi3_internal): Likewise.
6168 (*<optab>nsi_internal): Likewise.
6169 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
6170 modified bit operation to make the optimization work.
6172 2024-01-11 liuhongt <hongtao.liu@intel.com>
6174 PR target/104401
6175 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
6177 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6179 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
6180 (get_vector_costs): Ditto.
6181 (riscv_builtin_vectorization_cost): Ditto.
6183 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6185 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
6187 2024-01-10 Antoni Boucher <bouanto@zoho.com>
6189 PR jit/111396
6190 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
6191 ipa_free_size_summary.
6192 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
6193 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
6194 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
6195 * ipa-prop.h (ipa_prop_cc_finalize): New function.
6196 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
6197 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
6198 ipa_sra_cc_finalize): New functions.
6199 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
6200 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
6201 ipa_sra_cc_finalize
6202 Include ipa-utils.h.
6204 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
6206 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
6207 (th_int_get_save_adjustment): Likewise.
6208 (th_int_adjust_cfi_prologue): Likewise.
6209 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
6210 (TH_INT_INTERRUPT): New macro.
6211 (riscv_expand_prologue): Add the processing of XTheadInt.
6212 (riscv_expand_epilogue): Likewise.
6213 * config/riscv/riscv.h (BITSET_P): Moved to here.
6214 * config/riscv/riscv.md: New unspec.
6215 * config/riscv/thead.cc (th_int_get_mask): New function.
6216 (th_int_get_save_adjustment): Likewise.
6217 (th_int_adjust_cfi_prologue): Likewise.
6218 * config/riscv/thead.md (th_int_push): New pattern.
6219 (th_int_pop): new pattern.
6221 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6223 PR tree-optimization/112468
6224 * doc/sourcebuild.texi: Document ifn_copysign.
6225 * match.pd: Only apply transformation if target supports the IFN.
6227 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
6229 PR tree-optimization/112581
6230 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
6231 mark_ssa_maybe_undefs.
6232 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
6233 variables can not be reassociated.
6234 (init_range_entry): Check for uninitialized variables too.
6235 (init_reassoc): Call mark_ssa_maybe_undefs.
6237 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
6239 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
6240 Also handle sign extension.
6242 2024-01-10 Alex Coplan <alex.coplan@arm.com>
6244 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
6245 to 0.
6246 (-mlate-ldp-fusion): Likewise.
6248 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6250 PR tree-optimization/113287
6251 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
6252 instead of using BRANCH_EDGE to determine true edge.
6254 2024-01-10 Richard Biener <rguenther@suse.de>
6256 PR tree-optimization/113078
6257 * tree-vect-loop.cc (check_reduction_path): Canonicalize
6258 .COND_SUB to .COND_ADD.
6260 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6262 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
6263 Handle prefix mappings before calling find_opt.
6264 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
6265 "-fno-"-prefixed command-line option.
6266 * opts-common.cc (get_option_prefix_remapping): New.
6267 * opts.h (get_option_prefix_remapping): New decl.
6269 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6271 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
6272 m_urlifier to pp_output_formatted_text.
6273 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
6274 (obstack_append_string): New overload, taking a length.
6275 (urlify_quoted_string): Pass in an obstack ptr, rather than using
6276 that of the pp's buffer. Generalize to handle trailing text in
6277 the buffer beyond the run of quoted text.
6278 (class quoting_info): New.
6279 (on_begin_quote): New.
6280 (on_end_quote): New.
6281 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
6282 it to calls to on_begin_quote and on_end_quote.
6283 (struct auto_obstack): New.
6284 (quoting_info::handle_phase_3): New.
6285 (pp_output_formatted_text): Add urlifier param. Use it if there
6286 is deferred urlification. Delete m_quotes.
6287 (selftest::pp_printf_with_urlifier): Pass urlifier to
6288 pp_output_formatted_text.
6289 (selftest::test_urlification): Update results for the existing
6290 case of quoted text stradding chunks; add more such test cases.
6291 * pretty-print.h (class quoting_info): New forward decl.
6292 (chunk_info::m_quotes): New field.
6293 (pp_output_formatted_text): Add optional urlifier param.
6295 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6297 * pretty-print.cc (selftest::test_pp_format): Add selftest
6298 coverage for numbered args.
6300 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6302 PR tree-optimization/113144
6303 PR tree-optimization/113145
6304 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6305 Update all BB that the original exits dominated.
6307 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
6309 * dwarf2out.cc (modified_type_die): Extend the support of reverse
6310 storage order to enumeration types if -gstrict-dwarf is not passed.
6311 (gen_enumeration_type_die): Add REVERSE parameter and generate the
6312 DIE immediately after the existing one if it is true.
6313 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
6314 call to gen_enumeration_type_die.
6315 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
6316 first recursive call as well as the call to gen_tagged_type_die.
6317 (gen_type_die): Add REVERSE parameter and pass it in the call to
6318 gen_type_die_with_usage.
6320 2024-01-10 Jakub Jelinek <jakub@redhat.com>
6322 PR tree-optimization/113120
6323 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
6324 with root->size TYPE_PRECISION don't build anything new.
6325 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
6326 rather than build_nonstandard_integer_type.
6328 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
6330 * config/i386/i386.opt: Adjust document.
6331 * doc/invoke.texi: Add description for
6332 -mapx-inline-asm-use-gpr32.
6334 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6336 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
6337 (avg<v_double_trunc>3_floor): New pattern.
6338 (<u>avg<v_double_trunc>3_ceil): Remove.
6339 (avg<v_double_trunc>3_ceil): New pattern.
6340 (uavg<mode>3_floor): Ditto.
6341 (uavg<mode>3_ceil): Ditto.
6342 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
6343 (enum insn_type): Ditto.
6344 * config/riscv/riscv-v.cc: Ditto.
6345 * config/riscv/vector-iterators.md (ashiftrt): Remove.
6346 (ASHIFTRT): Ditto.
6347 * config/riscv/vector.md: Add VLS modes.
6349 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6351 PR target/111480
6352 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
6353 (vczlsbb_char): New int attribute.
6354 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
6355 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
6356 (*vctzlsbb_zext_<mode>): Rename to ...
6357 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
6358 cover vclzlsbb.
6360 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6362 PR target/112606
6363 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
6364 of the last argument from altivec_register_operand to any_operand. If
6365 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
6366 otherwise if it doesn't satisfy altivec_register_operand, force it to
6367 REG using copy_to_mode_reg.
6369 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6371 PR middle-end/113100
6372 * builtins.cc (expand_builtin_stack_address): Guard stack point
6373 adjustment with SPARC_STACK_BOUNDARY_HACK.
6375 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6377 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
6378 argument string definitions.
6379 * config/loongarch/loongarch-str.h: Same.
6380 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
6381 as aliases to -mexplicit-relocs={always,none}
6382 * config/loongarch/loongarch.opt: Regenerate.
6383 * config/loongarch/loongarch.cc: Same.
6385 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6387 * config/loongarch/loongarch-def.h: Define constants with
6388 enums instead of Macros.
6390 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6392 * config/loongarch/genopts/loongarch-strings: Rename.
6393 * config/loongarch/genopts/loongarch.opt.in: Same.
6394 * config/loongarch/loongarch-cpu.cc: Same.
6395 * config/loongarch/loongarch-def.cc: Same.
6396 * config/loongarch/loongarch-def.h: Same.
6397 * config/loongarch/loongarch-opts.cc: Same.
6398 * config/loongarch/loongarch-opts.h: Same.
6399 * config/loongarch/loongarch-str.h: Same.
6400 * config/loongarch/loongarch.opt: Same.
6402 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6404 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
6405 variable with the common la_ prefix.
6406 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
6407 flags as saved using TargetVariable.
6408 * config/loongarch/loongarch.opt: Same.
6409 * config/loongarch/loongarch-def.h: Define evolution_set to
6410 mark changes to the -march default.
6411 * config/loongarch/loongarch-driver.cc: Same.
6412 * config/loongarch/loongarch-opts.cc: Same.
6413 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
6414 conditions around the la_target structure.
6415 * config/loongarch/loongarch.cc: Same.
6416 * config/loongarch/loongarch.md: Same.
6417 * config/loongarch/loongarch-builtins.cc: Same.
6418 * config/loongarch/loongarch-c.cc: Same.
6419 * config/loongarch/lasx.md: Same.
6420 * config/loongarch/lsx.md: Same.
6421 * config/loongarch/sync.md: Same.
6423 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
6425 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
6426 no less.
6428 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
6430 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
6432 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6434 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
6435 restart_loop.
6436 (vectorizable_live_operation): Likewise.
6438 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6440 PR tree-optimization/113199
6441 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
6442 BIT_FIELD_REF.
6444 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6446 PR target/113270
6447 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
6448 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
6449 GTY(()) declaration before the definition, drop GTY(()) drom the
6450 definition.
6452 2024-01-09 Richard Biener <rguenther@suse.de>
6454 PR tree-optimization/113026
6455 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
6456 redundant and wrong niter bound setting. Move niter
6457 bound adjustment down.
6459 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6461 PR middle-end/113163
6462 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
6463 Reject non-linear inductions that aren't supported.
6465 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6467 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
6468 left shift implementation strategies.
6469 (arc_shift_info): Type for each entry of the shift strategy table.
6470 (arc_shift_context_idx): Return a integer value for each code
6471 generation context, used as an index
6472 (arc_ashl_alg): Table indexed by context and shifted bit count.
6473 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
6474 left shift implementation.
6475 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
6476 provide accurate costs, when optimizing for speed or size.
6478 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6480 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
6482 2024-01-09 Julian Brown <julian@codesourcery.com>
6484 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
6485 processed out before gimplification.
6486 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
6487 * tree.def (OMP_ARRAY_SECTION): New tree code.
6489 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6491 PR tree-optimization/113210
6492 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
6493 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
6494 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
6495 minus 1.
6497 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
6499 PR rtl-optimization/113140
6500 * reorg.cc (fill_slots_from_thread): If we are to branch after the
6501 last instruction of the function, create an end label.
6503 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6504 Hongtao Liu <hongtao.liu@intel.com>
6506 PR target/112992
6507 * config/i386/i386-expand.cc
6508 (ix86_convert_const_wide_int_to_broadcast): Allow call to
6509 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
6510 (ix86_broadcast_from_constant): Revert recent change; Return a
6511 suitable MEMREF independently of mode/target combinations.
6512 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
6513 to decide whether expansion is possible/preferrable. Only try
6514 forcing DImode constants to memory (and trying again) if calling
6515 ix86_expand_vector_init_duplicate fails with an DImode immediate
6516 constant.
6517 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
6518 V4SImode for suitable immediate constants.
6519 <case E_V4DImode>: Try using V8SImode for suitable constants.
6520 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
6521 <case E_V2HImode>: Likewise.
6522 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
6523 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
6524 <label widen>: Handle CONT_INTs via simplify_binary_operation.
6525 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
6526 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
6527 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
6528 (ix86_expand_vector_init): Move try using a broadcast for all_same
6529 with ix86_expand_vector_init_duplicate before using constant pool.
6531 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6533 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
6535 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6537 * config/arm/arm-cpus.in (cortex-m52): New cpu.
6538 * config/arm/arm-tables.opt: Regenerate.
6539 * config/arm/arm-tune.md: Regenerate.
6541 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
6543 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
6544 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
6545 (@vec_concatz<mode>): New insn pattern.
6546 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
6547 Handle VALS containing two vectors.
6549 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6551 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
6552 (vundefined): Ditto.
6554 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
6556 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6557 Add new function_base for crypto vector.
6558 (class bitmanip): Ditto.
6559 (class b_reverse):Ditto.
6560 (class vwsll): Ditto.
6561 (class clmul): Ditto.
6562 (class vg_nhab): Ditto.
6563 (class crypto_vv):Ditto.
6564 (class crypto_vi):Ditto.
6565 (class vaeskf2_vsm3c):Ditto.
6566 (class vsm3me): Ditto.
6567 (BASE): Add BASE declaration for crypto vector.
6568 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6569 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6570 Add crypto vector intrinsic definition.
6571 (vbrev): Ditto.
6572 (vclz): Ditto.
6573 (vctz): Ditto.
6574 (vwsll): Ditto.
6575 (vandn): Ditto.
6576 (vbrev8): Ditto.
6577 (vrev8): Ditto.
6578 (vrol): Ditto.
6579 (vror): Ditto.
6580 (vclmul): Ditto.
6581 (vclmulh): Ditto.
6582 (vghsh): Ditto.
6583 (vgmul): Ditto.
6584 (vaesef): Ditto.
6585 (vaesem): Ditto.
6586 (vaesdf): Ditto.
6587 (vaesdm): Ditto.
6588 (vaesz): Ditto.
6589 (vaeskf1): Ditto.
6590 (vaeskf2): Ditto.
6591 (vsha2ms): Ditto.
6592 (vsha2ch): Ditto.
6593 (vsha2cl): Ditto.
6594 (vsm4k): Ditto.
6595 (vsm4r): Ditto.
6596 (vsm3me): Ditto.
6597 (vsm3c): Ditto.
6598 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6599 Add new function_shape for crypto vector.
6600 (struct crypto_vi_def): Ditto.
6601 (struct crypto_vv_no_op_type_def): Ditto.
6602 (SHAPE): Add SHAPE declaration of crypto vector.
6603 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6604 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6605 Add new data type for crypto vector.
6606 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6607 (vuint32mf2_t): Ditto.
6608 (vuint32m1_t): Ditto.
6609 (vuint32m2_t): Ditto.
6610 (vuint32m4_t): Ditto.
6611 (vuint32m8_t): Ditto.
6612 (vuint64m1_t): Ditto.
6613 (vuint64m2_t): Ditto.
6614 (vuint64m4_t): Ditto.
6615 (vuint64m8_t): Ditto.
6616 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6617 Add new data struct for crypto vector.
6618 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6619 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6620 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6622 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
6624 PR sanitizer/113251
6625 * varasm.cc (assemble_function_label_raw): Do not call
6626 asan_function_start () without the current function.
6628 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6630 PR target/113225
6631 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
6632 extern and kernel_helper attributed function decls.
6634 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6636 * btfout.cc (output_btf_strs): Changed.
6638 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6640 * config/gcn/mkoffload.cc (main): Handle gfx1100
6641 when setting the default XNACK.
6643 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6645 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
6646 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
6647 (ASM_SPEC): Handle gfx1100.
6648 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
6649 (enum gcn_isa): Add ISA_RDNA3.
6650 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
6651 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6652 * config/gcn/gcn.cc (gcn_option_override,
6653 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
6654 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
6655 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6656 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
6657 with gfx1100.
6658 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
6659 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
6660 __gfx1100__.
6661 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6662 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
6663 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
6664 (isa_has_combined_avgprs, main): Handle gfx1100.
6665 * config/gcn/t-omp-device (isa): Add gfx1100.
6667 2024-01-08 Richard Biener <rguenther@suse.de>
6669 * doc/invoke.texi (-mmovbe): Clarify.
6671 2024-01-08 Richard Biener <rguenther@suse.de>
6673 PR tree-optimization/113026
6674 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
6675 Avoid an epilog in more cases.
6676 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
6677 epilogues niter upper bounds and estimates.
6679 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6681 PR tree-optimization/113228
6682 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
6684 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6686 PR tree-optimization/113120
6687 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
6688 large _BitInt zero INTEGER_CST PHI argument.
6690 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6692 PR tree-optimization/113119
6693 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
6694 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
6695 is before REALPART_EXPR.
6697 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
6699 PR target/112952
6700 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
6701 range when diagnosing attribute "io" and "io_low" are out of range.
6702 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
6703 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
6704 in contexts other than static storage.
6705 (avr_asm_output_aligned_decl_common): Move output of decls with
6706 attribute "address", "io", and "io_low" to...
6707 (avr_output_addr_attrib): ...this new function.
6708 (avr_asm_asm_output_aligned_bss): Remove output for decls with
6709 attribute "address", "io", and "io_low".
6710 (avr_encode_section_info): Rectify handling of decls with attribute
6711 "address", "io", and "io_low".
6713 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6715 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
6716 (elf_flags): Remove XNACK from the default value.
6717 (main): Set a default XNACK according to the arch.
6719 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6721 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
6722 (process_asm): Don't count avgprs.
6724 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
6726 * config/i386/i386.opt: Add supported sub-features.
6727 * doc/extend.texi: Add description for target attribute.
6729 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
6731 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
6733 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
6734 Uros Bizjak <ubizjak@gmail.com>
6736 PR target/113231
6737 * config/i386/i386-features.cc (compute_convert_gain): Include
6738 the overhead of explicit load and store (movd) instructions when
6739 converting non-store scalar operations with memory destinations.
6740 Various indentation whitespace fixes.
6742 2024-01-07 Tamar Christina <tamar.christina@arm.com>
6744 * config/arm/neon.md (cbranch<mode>4): New.
6746 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6748 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
6750 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
6752 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
6754 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6756 PR target/113248
6757 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
6758 Update the MAX_SEW.
6760 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6762 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
6763 (variable_vectorized_p): Teach loop invariant.
6764 (has_unexpected_spills_p): Ditto.
6766 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6768 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
6769 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
6770 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
6772 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
6774 PR target/113104
6775 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
6776 (aarch64-vect-compare-costs): ...this.
6777 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
6778 Replace with...
6779 (-param=aarch64-vect-compare-costs=): ...this new param.
6780 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
6781 Don't disable it when vectorizing for Advanced SIMD only.
6782 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
6783 whenever aarch64_vect_compare_costs is true.
6785 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
6787 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
6788 Modify the method of determining the memory offset of [x]vld/[x]vst.
6789 (lasx_mxst_<lasxfmt_f>): Likewise.
6790 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
6791 (loongarch_address_insns): Likewise.
6792 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
6793 (lsx_st_<lsxfmt_f>): Likewise.
6794 * config/loongarch/predicates.md (aq10b_operand): Likewise.
6795 (aq10h_operand): Likewise.
6796 (aq10w_operand): Likewise.
6797 (aq10d_operand): Likewise.
6799 2024-01-05 Alex Coplan <alex.coplan@arm.com>
6801 PR target/113217
6802 * config/aarch64/aarch64-ldp-fusion.cc
6803 (ldp_bb_info::try_fuse_pair): If the second access can throw,
6804 narrow the move range to exactly that insn.
6806 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6808 * asan.cc (asan_function_start): Drop switch_to_section ().
6809 (asan_emit_stack_protection): Set .LASANPC alignment.
6810 * config/i386/i386.cc: Use assemble_function_label_raw ()
6811 instead of ASM_OUTPUT_LABEL ().
6812 * config/s390/s390.cc (s390_asm_output_function_label):
6813 Likewise.
6814 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
6815 * final.cc (final_start_function_1): Drop
6816 asan_function_start ().
6817 * output.h (assemble_function_label_raw): New function.
6818 * varasm.cc (assemble_function_label_raw): Likewise.
6820 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6822 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
6823 Use ASM_OUTPUT_FUNCTION_LABEL ().
6824 * config/alpha/alpha.cc (alpha_start_function): Likewise.
6825 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6826 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
6827 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6828 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6829 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
6830 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6831 * config/ia64/ia64.cc (ia64_start_function): Likewise.
6832 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
6833 Likewise.
6834 * config/microblaze/microblaze.cc (microblaze_function_prologue):
6835 Likewise.
6836 * config/mips/mips.cc (mips_start_unique_function): Return the
6837 tree.
6838 (mips_start_function_definition): Use
6839 ASM_OUTPUT_FUNCTION_LABEL ().
6840 (mips_finish_stub): Pass the tree to
6841 mips_start_function_definition ().
6842 (mips16_build_function_stub): Likewise.
6843 (mips16_build_call_stub): Likewise.
6844 (mips_output_function_prologue): Likewise.
6845 * config/pa/pa.cc (pa_output_function_label): Use
6846 ASM_OUTPUT_FUNCTION_LABEL ().
6847 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
6848 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6849 Likewise.
6850 (rs6000_xcoff_declare_function_name): Likewise.
6852 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6854 PR tree-optimization/113201
6855 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
6856 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
6858 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6860 PR tree-optimization/90693
6861 * tree-ssa-math-opts.cc (match_single_bit_test): If
6862 tree_expr_nonzero_p (arg), remember it in the second argument to
6863 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
6864 arg ^ (arg - 1) > arg - 1.
6865 * internal-fn.cc (expand_POPCOUNT): If second argument to
6866 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
6867 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
6869 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
6871 * config/riscv/riscv-v.cc (expand_load_store):
6872 Remove `value`.
6873 (expand_cond_len_op): Ditto.
6874 (expand_gather_scatter): Ditto.
6875 (expand_lanes_load_store): Ditto.
6876 (expand_fold_extract_last): Ditto.
6878 2024-01-05 Pan Li <pan2.li@intel.com>
6880 Revert:
6881 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6883 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6884 Add new function_base for crypto vector.
6885 (class bitmanip): Ditto.
6886 (class b_reverse):Ditto.
6887 (class vwsll): Ditto.
6888 (class clmul): Ditto.
6889 (class vg_nhab): Ditto.
6890 (class crypto_vv):Ditto.
6891 (class crypto_vi):Ditto.
6892 (class vaeskf2_vsm3c):Ditto.
6893 (class vsm3me): Ditto.
6894 (BASE): Add BASE declaration for crypto vector.
6895 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6896 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6897 Add crypto vector intrinsic definition.
6898 (vbrev): Ditto.
6899 (vclz): Ditto.
6900 (vctz): Ditto.
6901 (vwsll): Ditto.
6902 (vandn): Ditto.
6903 (vbrev8): Ditto.
6904 (vrev8): Ditto.
6905 (vrol): Ditto.
6906 (vror): Ditto.
6907 (vclmul): Ditto.
6908 (vclmulh): Ditto.
6909 (vghsh): Ditto.
6910 (vgmul): Ditto.
6911 (vaesef): Ditto.
6912 (vaesem): Ditto.
6913 (vaesdf): Ditto.
6914 (vaesdm): Ditto.
6915 (vaesz): Ditto.
6916 (vaeskf1): Ditto.
6917 (vaeskf2): Ditto.
6918 (vsha2ms): Ditto.
6919 (vsha2ch): Ditto.
6920 (vsha2cl): Ditto.
6921 (vsm4k): Ditto.
6922 (vsm4r): Ditto.
6923 (vsm3me): Ditto.
6924 (vsm3c): Ditto.
6925 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6926 Add new function_shape for crypto vector.
6927 (struct crypto_vi_def): Ditto.
6928 (struct crypto_vv_no_op_type_def): Ditto.
6929 (SHAPE): Add SHAPE declaration of crypto vector.
6930 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6931 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6932 Add new data type for crypto vector.
6933 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6934 (vuint32mf2_t): Ditto.
6935 (vuint32m1_t): Ditto.
6936 (vuint32m2_t): Ditto.
6937 (vuint32m4_t): Ditto.
6938 (vuint32m8_t): Ditto.
6939 (vuint64m1_t): Ditto.
6940 (vuint64m2_t): Ditto.
6941 (vuint64m4_t): Ditto.
6942 (vuint64m8_t): Ditto.
6943 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6944 Add new data struct for crypto vector.
6945 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6946 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6947 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6949 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6951 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6952 Add new function_base for crypto vector.
6953 (class bitmanip): Ditto.
6954 (class b_reverse):Ditto.
6955 (class vwsll): Ditto.
6956 (class clmul): Ditto.
6957 (class vg_nhab): Ditto.
6958 (class crypto_vv):Ditto.
6959 (class crypto_vi):Ditto.
6960 (class vaeskf2_vsm3c):Ditto.
6961 (class vsm3me): Ditto.
6962 (BASE): Add BASE declaration for crypto vector.
6963 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6964 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6965 Add crypto vector intrinsic definition.
6966 (vbrev): Ditto.
6967 (vclz): Ditto.
6968 (vctz): Ditto.
6969 (vwsll): Ditto.
6970 (vandn): Ditto.
6971 (vbrev8): Ditto.
6972 (vrev8): Ditto.
6973 (vrol): Ditto.
6974 (vror): Ditto.
6975 (vclmul): Ditto.
6976 (vclmulh): Ditto.
6977 (vghsh): Ditto.
6978 (vgmul): Ditto.
6979 (vaesef): Ditto.
6980 (vaesem): Ditto.
6981 (vaesdf): Ditto.
6982 (vaesdm): Ditto.
6983 (vaesz): Ditto.
6984 (vaeskf1): Ditto.
6985 (vaeskf2): Ditto.
6986 (vsha2ms): Ditto.
6987 (vsha2ch): Ditto.
6988 (vsha2cl): Ditto.
6989 (vsm4k): Ditto.
6990 (vsm4r): Ditto.
6991 (vsm3me): Ditto.
6992 (vsm3c): Ditto.
6993 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6994 Add new function_shape for crypto vector.
6995 (struct crypto_vi_def): Ditto.
6996 (struct crypto_vv_no_op_type_def): Ditto.
6997 (SHAPE): Add SHAPE declaration of crypto vector.
6998 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6999 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7000 Add new data type for crypto vector.
7001 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7002 (vuint32mf2_t): Ditto.
7003 (vuint32m1_t): Ditto.
7004 (vuint32m2_t): Ditto.
7005 (vuint32m4_t): Ditto.
7006 (vuint32m8_t): Ditto.
7007 (vuint64m1_t): Ditto.
7008 (vuint64m2_t): Ditto.
7009 (vuint64m4_t): Ditto.
7010 (vuint64m8_t): Ditto.
7011 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7012 Add new data struct for crypto vector.
7013 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7014 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7015 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7017 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7019 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7021 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
7023 PR tree-optimization/113186
7024 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
7025 Match `^` with the `==` for 1bit integral types.
7026 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
7027 integral types.
7029 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7031 * toplev.cc (general_init): Pass lang_mask to urlifier.
7033 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7035 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
7036 param.
7037 (diagnostic_context::make_option_url): Update for lang_mask param.
7038 * gcc-urlifier.cc: Include "opts.h" and "options.h".
7039 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
7040 (gcc_urlifier::m_lang_mask): New field.
7041 (doc_urls): Make static.
7042 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
7043 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7044 Look for an option by name before trying a binary search in
7045 doc_urls.
7046 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7047 (gcc_urlifier::get_url_suffix_for_option): New.
7048 (make_gcc_urlifier): Add lang_mask param.
7049 (selftest::gcc_urlifier_cc_tests): Update for above changes.
7050 Verify that a URL is found for "-fpack-struct".
7051 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
7052 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
7053 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
7054 to make_gcc_urlifier.
7055 * opts-diagnostic.h (get_option_url): Add lang_mask param.
7056 * opts.cc (get_option_html_page): Remove special-casing for
7057 analyzer and LTO.
7058 (get_option_url_suffix): New.
7059 (get_option_url): Reimplement.
7060 (selftest::test_get_option_html_page): Rename to...
7061 (selftest::test_get_option_url_suffix): ...this and update for
7062 above changes.
7063 (selftest::opts_cc_tests): Update for renaming.
7064 * opts.h: Include "rich-location.h".
7065 (get_option_url_suffix): New decl.
7067 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7069 * Makefile.in (ALL_OPT_URL_FILES): New.
7070 (GCC_OBJS): Add options-urls.o.
7071 (OBJS): Likewise.
7072 (OBJS-libcommon): Likewise.
7073 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
7074 inputs to opt-gather.awk.
7075 (options-urls.cc): New Makefile target.
7076 * opt-functions.awk (url_suffix): New function.
7077 (lang_url_suffix): New function.
7078 * options-urls-cc-gen.awk: New file.
7079 * opts.h (get_opt_url_suffix): New decl.
7081 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7083 * params.opt.urls: New file, autogenerated by
7084 regenerate-opt-urls.py.
7086 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7088 * common.opt.urls: New file, autogenerated by
7089 regenerate-opt-urls.py.
7090 * config/aarch64/aarch64.opt.urls: Likewise.
7091 * config/alpha/alpha.opt.urls: Likewise.
7092 * config/alpha/elf.opt.urls: Likewise.
7093 * config/arc/arc-tables.opt.urls: Likewise.
7094 * config/arc/arc.opt.urls: Likewise.
7095 * config/arm/arm-tables.opt.urls: Likewise.
7096 * config/arm/arm.opt.urls: Likewise.
7097 * config/arm/vxworks.opt.urls: Likewise.
7098 * config/avr/avr.opt.urls: Likewise.
7099 * config/bpf/bpf.opt.urls: Likewise.
7100 * config/c6x/c6x-tables.opt.urls: Likewise.
7101 * config/c6x/c6x.opt.urls: Likewise.
7102 * config/cris/cris.opt.urls: Likewise.
7103 * config/cris/elf.opt.urls: Likewise.
7104 * config/csky/csky.opt.urls: Likewise.
7105 * config/csky/csky_tables.opt.urls: Likewise.
7106 * config/darwin.opt.urls: Likewise.
7107 * config/dragonfly.opt.urls: Likewise.
7108 * config/epiphany/epiphany.opt.urls: Likewise.
7109 * config/fr30/fr30.opt.urls: Likewise.
7110 * config/freebsd.opt.urls: Likewise.
7111 * config/frv/frv.opt.urls: Likewise.
7112 * config/ft32/ft32.opt.urls: Likewise.
7113 * config/fused-madd.opt.urls: Likewise.
7114 * config/g.opt.urls: Likewise.
7115 * config/gcn/gcn.opt.urls: Likewise.
7116 * config/gnu-user.opt.urls: Likewise.
7117 * config/h8300/h8300.opt.urls: Likewise.
7118 * config/hpux11.opt.urls: Likewise.
7119 * config/i386/cygming.opt.urls: Likewise.
7120 * config/i386/cygwin.opt.urls: Likewise.
7121 * config/i386/djgpp.opt.urls: Likewise.
7122 * config/i386/i386.opt.urls: Likewise.
7123 * config/i386/mingw-w64.opt.urls: Likewise.
7124 * config/i386/mingw.opt.urls: Likewise.
7125 * config/i386/nto.opt.urls: Likewise.
7126 * config/ia64/ia64.opt.urls: Likewise.
7127 * config/ia64/ilp32.opt.urls: Likewise.
7128 * config/ia64/vms.opt.urls: Likewise.
7129 * config/iq2000/iq2000.opt.urls: Likewise.
7130 * config/linux-android.opt.urls: Likewise.
7131 * config/linux.opt.urls: Likewise.
7132 * config/lm32/lm32.opt.urls: Likewise.
7133 * config/loongarch/loongarch.opt.urls: Likewise.
7134 * config/lynx.opt.urls: Likewise.
7135 * config/m32c/m32c.opt.urls: Likewise.
7136 * config/m32r/m32r.opt.urls: Likewise.
7137 * config/m68k/ieee.opt.urls: Likewise.
7138 * config/m68k/m68k-tables.opt.urls: Likewise.
7139 * config/m68k/m68k.opt.urls: Likewise.
7140 * config/m68k/uclinux.opt.urls: Likewise.
7141 * config/mcore/mcore.opt.urls: Likewise.
7142 * config/microblaze/microblaze.opt.urls: Likewise.
7143 * config/mips/mips-tables.opt.urls: Likewise.
7144 * config/mips/mips.opt.urls: Likewise.
7145 * config/mips/sde.opt.urls: Likewise.
7146 * config/mmix/mmix.opt.urls: Likewise.
7147 * config/mn10300/mn10300.opt.urls: Likewise.
7148 * config/moxie/moxie.opt.urls: Likewise.
7149 * config/msp430/msp430.opt.urls: Likewise.
7150 * config/nds32/nds32-elf.opt.urls: Likewise.
7151 * config/nds32/nds32-linux.opt.urls: Likewise.
7152 * config/nds32/nds32.opt.urls: Likewise.
7153 * config/netbsd-elf.opt.urls: Likewise.
7154 * config/netbsd.opt.urls: Likewise.
7155 * config/nios2/elf.opt.urls: Likewise.
7156 * config/nios2/nios2.opt.urls: Likewise.
7157 * config/nvptx/nvptx-gen.opt.urls: Likewise.
7158 * config/nvptx/nvptx.opt.urls: Likewise.
7159 * config/openbsd.opt.urls: Likewise.
7160 * config/or1k/elf.opt.urls: Likewise.
7161 * config/or1k/or1k.opt.urls: Likewise.
7162 * config/pa/pa-hpux.opt.urls: Likewise.
7163 * config/pa/pa-hpux1010.opt.urls: Likewise.
7164 * config/pa/pa-hpux1111.opt.urls: Likewise.
7165 * config/pa/pa-hpux1131.opt.urls: Likewise.
7166 * config/pa/pa.opt.urls: Likewise.
7167 * config/pa/pa64-hpux.opt.urls: Likewise.
7168 * config/pdp11/pdp11.opt.urls: Likewise.
7169 * config/pru/pru.opt.urls: Likewise.
7170 * config/riscv/riscv.opt.urls: Likewise.
7171 * config/rl78/rl78.opt.urls: Likewise.
7172 * config/rpath.opt.urls: Likewise.
7173 * config/rs6000/476.opt.urls: Likewise.
7174 * config/rs6000/aix64.opt.urls: Likewise.
7175 * config/rs6000/darwin.opt.urls: Likewise.
7176 * config/rs6000/linux64.opt.urls: Likewise.
7177 * config/rs6000/rs6000-tables.opt.urls: Likewise.
7178 * config/rs6000/rs6000.opt.urls: Likewise.
7179 * config/rs6000/sysv4.opt.urls: Likewise.
7180 * config/rtems.opt.urls: Likewise.
7181 * config/rx/elf.opt.urls: Likewise.
7182 * config/rx/rx.opt.urls: Likewise.
7183 * config/s390/s390.opt.urls: Likewise.
7184 * config/s390/tpf.opt.urls: Likewise.
7185 * config/sh/sh.opt.urls: Likewise.
7186 * config/sh/superh.opt.urls: Likewise.
7187 * config/sol2.opt.urls: Likewise.
7188 * config/sparc/long-double-switch.opt.urls: Likewise.
7189 * config/sparc/sparc.opt.urls: Likewise.
7190 * config/stormy16/stormy16.opt.urls: Likewise.
7191 * config/v850/v850.opt.urls: Likewise.
7192 * config/vax/elf.opt.urls: Likewise.
7193 * config/vax/vax.opt.urls: Likewise.
7194 * config/visium/visium.opt.urls: Likewise.
7195 * config/vms/vms.opt.urls: Likewise.
7196 * config/vxworks-smp.opt.urls: Likewise.
7197 * config/vxworks.opt.urls: Likewise.
7198 * config/xtensa/elf.opt.urls: Likewise.
7199 * config/xtensa/uclinux.opt.urls: Likewise.
7200 * config/xtensa/xtensa.opt.urls: Likewise.
7201 * config/bfin/bfin.opt.urls: New file.
7203 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7205 * Makefile.in (OPT_URLS_HTML_DEPS): New.
7206 (regenerate-opt-urls): New target.
7207 (regenerate-opt-urls-unit-test): New target.
7208 * doc/options.texi (Option properties): Add UrlSuffix and
7209 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
7210 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
7211 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
7212 and Makefile.in's OPT_URLS_HTML_DEPS.
7213 (Anatomy of a Target Back End): Add
7214 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
7215 * regenerate-opt-urls.py: New file.
7217 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7219 * diagnostic-format-sarif.cc
7220 (sarif_builder::make_logical_location_object): Convert to...
7221 (make_sarif_logical_location_object): ...this.
7222 (sarif_builder::set_any_logical_locs_arr): Update for above
7223 change.
7224 (sarif_builder::make_thread_flow_location_object): Call
7225 maybe_add_sarif_properties on each diagnostic_event.
7226 * diagnostic-format-sarif.h (class logical_location): New forward
7227 decl.
7228 (make_sarif_logical_location_object): New decl.
7229 * diagnostic-path.h (class sarif_object): New forward decl.
7230 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
7232 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
7233 Patrick Lin <patrick@andestech.com>
7234 Rufus Chen <rufus@andestech.com>
7235 Monk Chiang <monk.chiang@sifive.com>
7237 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
7238 with Nan-boxing value.
7239 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
7241 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
7242 Jeff Law <jlaw@ventanamicro.com>
7244 PR rtl-optimization/104914
7245 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
7246 a sign or zero extension is only required if the modified field
7247 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
7248 targets, don't refer to the temporarily incorrectly extended value
7249 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
7251 2024-01-04 Pan Li <pan2.li@intel.com>
7253 Revert:
7254 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7256 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7258 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7260 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7262 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
7264 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
7265 offset of fcsr.
7267 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7269 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
7270 (compute_nregs_for_mode): Refine LMUL.
7271 (max_number_of_live_regs): Ditto.
7272 (compute_estimated_lmul): Ditto.
7273 (has_unexpected_spills_p): Ditto.
7275 2024-01-04 Li Wei <liwei@loongson.cn>
7277 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
7278 Remove useless forward declaration.
7279 (loongarch_is_even_extraction): Remove useless forward declaration.
7280 (loongarch_try_expand_lsx_vshuf_const): Removed.
7281 (loongarch_expand_vec_perm_const_1): Merged.
7282 (loongarch_is_double_duplicate): Removed.
7283 (loongarch_is_center_extraction): Ditto.
7284 (loongarch_is_reversing_permutation): Ditto.
7285 (loongarch_is_di_misalign_extract): Ditto.
7286 (loongarch_is_si_misalign_extract): Ditto.
7287 (loongarch_is_lasx_lowpart_extract): Ditto.
7288 (loongarch_is_op_reverse_perm): Ditto.
7289 (loongarch_is_single_op_perm): Ditto.
7290 (loongarch_is_divisible_perm): Ditto.
7291 (loongarch_is_triple_stride_extract): Ditto.
7292 (loongarch_expand_vec_perm_const_2): Merged.
7293 (loongarch_expand_vec_perm_const): New.
7294 (loongarch_vectorize_vec_perm_const): Adjust.
7296 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
7298 * omp-general.cc: Fix comment typos and misplaced/confusing
7299 comments. Delete redundant include of omp-general.h.
7301 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7303 PR rtl-optimization/104914
7304 * config/mips/mips.md (insqisi_extended): New patterns.
7305 (inshisi_extended): Ditto.
7307 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7309 * config/mips/mips.cc (mips_insn_cost): New function.
7311 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7313 * config/mips/mips.md (perf_ratio): New attribute.
7315 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7317 PR target/113206
7318 PR target/113209
7319 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
7320 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
7321 blocks belong to infinite loop.
7322 (pre_vsetvl::emit_vsetvl): Remove fake edges.
7323 * config/riscv/t-riscv: Add a new include file.
7325 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7327 * config/riscv/vector.md: Fix indent.
7329 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7331 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
7332 OMP_CLAUSE__SIMDUID_.
7333 * tree.cc (omp_clause_num_ops): Update position of entry for
7334 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
7335 (omp_clause_code_name): Likewise.
7337 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7339 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
7340 printing of FUNC_MAP/IND_FUNC_MAP labels.
7342 2024-01-03 Jakub Jelinek <jakub@redhat.com>
7344 * gcc.cc (process_command): Update copyright notice dates.
7345 * gcov-dump.cc (print_version): Ditto.
7346 * gcov.cc (print_version): Ditto.
7347 * gcov-tool.cc (print_version): Ditto.
7348 * gengtype.cc (create_file): Ditto.
7349 * doc/cpp.texi: Bump @copying's copyright year.
7350 * doc/cppinternals.texi: Ditto.
7351 * doc/gcc.texi: Ditto.
7352 * doc/gccint.texi: Ditto.
7353 * doc/gcov.texi: Ditto.
7354 * doc/install.texi: Ditto.
7355 * doc/invoke.texi: Ditto.
7357 2024-01-03 Xi Ruoyao <xry111@xry111.site>
7359 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
7360 (fmin<mode>3): Likewise.
7361 (reduc_fmax_scal_<mode>3): New define_expand.
7362 (reduc_fmin_scal_<mode>3): Likewise.
7364 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7366 PR target/113112
7367 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
7368 (max_number_of_live_regs): Ditto.
7369 (has_unexpected_spills_p): Ditto.
7371 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
7372 Jin Ma <jinma@linux.alibaba.com>
7373 Xianmiao Qu <cooper.qu@linux.alibaba.com>
7374 Christoph Müllner <christoph.muellner@vrull.eu>
7376 * config/riscv/vector.md:
7377 Use vector_length_operand for vsetvl patterns.
7379 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7381 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
7382 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
7384 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
7386 * config/aarch64/aarch64-tuning-flags.def
7387 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
7388 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
7389 * config/aarch64/aarch64.cc
7390 (aarch64_override_options_internal): Set
7391 param_fully_pipelined_fma according to tuning option.
7392 * config/aarch64/tuning_models/ampere1.h: Add
7393 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
7394 * config/aarch64/tuning_models/ampere1a.h: Likewise.
7395 * config/aarch64/tuning_models/ampere1b.h: Likewise.
7397 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7399 * config/riscv/vector-crypto.md: Modify copyright year.
7401 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7403 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
7405 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
7407 * config.in: Regenerate.
7408 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
7409 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
7410 Added TLS Le Relax support.
7411 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
7412 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
7413 * configure: Regenerate.
7414 * configure.ac: Check if binutils supports TLS le relax.
7416 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7418 * config/riscv/iterators.md: Add rotate insn name.
7419 * config/riscv/riscv.md: Add new insns name for crypto vector.
7420 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
7421 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
7422 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
7424 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7426 PR target/113112
7427 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
7428 pointer type liveness count.
7429 \f
7430 Copyright (C) 2024 Free Software Foundation, Inc.
7432 Copying and distribution of this file, with or without modification,
7433 are permitted in any medium without royalty provided the copyright
7434 notice and this notice are preserved.