1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 struct target_reload default_target_reload
;
86 struct target_reload
*this_target_reload
= &default_target_reload
;
89 #define spill_indirect_levels \
90 (this_target_reload->x_spill_indirect_levels)
92 /* During reload_as_needed, element N contains a REG rtx for the hard reg
93 into which reg N has been reloaded (perhaps for a previous insn). */
94 static rtx
*reg_last_reload_reg
;
96 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
97 for an output reload that stores into reg N. */
98 static regset_head reg_has_output_reload
;
100 /* Indicates which hard regs are reload-registers for an output reload
101 in the current insn. */
102 static HARD_REG_SET reg_is_output_reload
;
104 /* Element N is the constant value to which pseudo reg N is equivalent,
105 or zero if pseudo reg N is not equivalent to a constant.
106 find_reloads looks at this in order to replace pseudo reg N
107 with the constant it stands for. */
108 rtx
*reg_equiv_constant
;
110 /* Element N is an invariant value to which pseudo reg N is equivalent.
111 eliminate_regs_in_insn uses this to replace pseudos in particular
113 rtx
*reg_equiv_invariant
;
115 /* Element N is a memory location to which pseudo reg N is equivalent,
116 prior to any register elimination (such as frame pointer to stack
117 pointer). Depending on whether or not it is a valid address, this value
118 is transferred to either reg_equiv_address or reg_equiv_mem. */
119 rtx
*reg_equiv_memory_loc
;
121 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
122 collector can keep track of what is inside. */
123 VEC(rtx
,gc
) *reg_equiv_memory_loc_vec
;
125 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
126 This is used when the address is not valid as a memory address
127 (because its displacement is too big for the machine.) */
128 rtx
*reg_equiv_address
;
130 /* Element N is the memory slot to which pseudo reg N is equivalent,
131 or zero if pseudo reg N is not equivalent to a memory slot. */
134 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
135 alternate representations of the location of pseudo reg N. */
136 rtx
*reg_equiv_alt_mem_list
;
138 /* Widest width in which each pseudo reg is referred to (via subreg). */
139 static unsigned int *reg_max_ref_width
;
141 /* Element N is the list of insns that initialized reg N from its equivalent
142 constant or memory slot. */
144 int reg_equiv_init_size
;
146 /* Vector to remember old contents of reg_renumber before spilling. */
147 static short *reg_old_renumber
;
149 /* During reload_as_needed, element N contains the last pseudo regno reloaded
150 into hard register N. If that pseudo reg occupied more than one register,
151 reg_reloaded_contents points to that pseudo for each spill register in
152 use; all of these must remain set for an inheritance to occur. */
153 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
155 /* During reload_as_needed, element N contains the insn for which
156 hard register N was last used. Its contents are significant only
157 when reg_reloaded_valid is set for this register. */
158 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
160 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
161 static HARD_REG_SET reg_reloaded_valid
;
162 /* Indicate if the register was dead at the end of the reload.
163 This is only valid if reg_reloaded_contents is set and valid. */
164 static HARD_REG_SET reg_reloaded_dead
;
166 /* Indicate whether the register's current value is one that is not
167 safe to retain across a call, even for registers that are normally
168 call-saved. This is only meaningful for members of reg_reloaded_valid. */
169 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
171 /* Number of spill-regs so far; number of valid elements of spill_regs. */
174 /* In parallel with spill_regs, contains REG rtx's for those regs.
175 Holds the last rtx used for any given reg, or 0 if it has never
176 been used for spilling yet. This rtx is reused, provided it has
178 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
180 /* In parallel with spill_regs, contains nonzero for a spill reg
181 that was stored after the last time it was used.
182 The precise value is the insn generated to do the store. */
183 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
185 /* This is the register that was stored with spill_reg_store. This is a
186 copy of reload_out / reload_out_reg when the value was stored; if
187 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
188 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
190 /* This table is the inverse mapping of spill_regs:
191 indexed by hard reg number,
192 it contains the position of that reg in spill_regs,
193 or -1 for something that is not in spill_regs.
195 ?!? This is no longer accurate. */
196 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
198 /* This reg set indicates registers that can't be used as spill registers for
199 the currently processed insn. These are the hard registers which are live
200 during the insn, but not allocated to pseudos, as well as fixed
202 static HARD_REG_SET bad_spill_regs
;
204 /* These are the hard registers that can't be used as spill register for any
205 insn. This includes registers used for user variables and registers that
206 we can't eliminate. A register that appears in this set also can't be used
207 to retry register allocation. */
208 static HARD_REG_SET bad_spill_regs_global
;
210 /* Describes order of use of registers for reloading
211 of spilled pseudo-registers. `n_spills' is the number of
212 elements that are actually valid; new ones are added at the end.
214 Both spill_regs and spill_reg_order are used on two occasions:
215 once during find_reload_regs, where they keep track of the spill registers
216 for a single insn, but also during reload_as_needed where they show all
217 the registers ever used by reload. For the latter case, the information
218 is calculated during finish_spills. */
219 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
221 /* This vector of reg sets indicates, for each pseudo, which hard registers
222 may not be used for retrying global allocation because the register was
223 formerly spilled from one of them. If we allowed reallocating a pseudo to
224 a register that it was already allocated to, reload might not
226 static HARD_REG_SET
*pseudo_previous_regs
;
228 /* This vector of reg sets indicates, for each pseudo, which hard
229 registers may not be used for retrying global allocation because they
230 are used as spill registers during one of the insns in which the
232 static HARD_REG_SET
*pseudo_forbidden_regs
;
234 /* All hard regs that have been used as spill registers for any insn are
235 marked in this set. */
236 static HARD_REG_SET used_spill_regs
;
238 /* Index of last register assigned as a spill register. We allocate in
239 a round-robin fashion. */
240 static int last_spill_reg
;
242 /* Record the stack slot for each spilled hard register. */
243 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
245 /* Width allocated so far for that stack slot. */
246 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
248 /* Record which pseudos needed to be spilled. */
249 static regset_head spilled_pseudos
;
251 /* Record which pseudos changed their allocation in finish_spills. */
252 static regset_head changed_allocation_pseudos
;
254 /* Used for communication between order_regs_for_reload and count_pseudo.
255 Used to avoid counting one pseudo twice. */
256 static regset_head pseudos_counted
;
258 /* First uid used by insns created by reload in this function.
259 Used in find_equiv_reg. */
260 int reload_first_uid
;
262 /* Flag set by local-alloc or global-alloc if anything is live in
263 a call-clobbered reg across calls. */
264 int caller_save_needed
;
266 /* Set to 1 while reload_as_needed is operating.
267 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress
= 0;
270 /* This obstack is used for allocation of rtl during register elimination.
271 The allocated storage can be freed once find_reloads has processed the
273 static struct obstack reload_obstack
;
275 /* Points to the beginning of the reload_obstack. All insn_chain structures
276 are allocated first. */
277 static char *reload_startobj
;
279 /* The point after all insn_chain structures. Used to quickly deallocate
280 memory allocated in copy_reloads during calculate_needs_all_insns. */
281 static char *reload_firstobj
;
283 /* This points before all local rtl generated by register elimination.
284 Used to quickly free all memory after processing one insn. */
285 static char *reload_insn_firstobj
;
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain
*reload_insn_chain
;
291 /* List of all insns needing reloads. */
292 static struct insn_chain
*insns_need_reload
;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from
; /* Register number to be eliminated. */
302 int to
; /* Register number used as replacement. */
303 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
304 int can_eliminate
; /* Nonzero if this elimination can be done. */
305 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
306 target hook in previous scan over insns
308 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
309 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
310 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
311 rtx from_rtx
; /* REG rtx for the register to be eliminated.
312 We cannot simply compare the number since
313 we might then spuriously replace a hard
314 register corresponding to a pseudo
315 assigned to the reg to be eliminated. */
316 rtx to_rtx
; /* REG rtx for the replacement. */
319 static struct elim_table
*reg_eliminate
= 0;
321 /* This is an intermediate structure to initialize the table. It has
322 exactly the members provided by ELIMINABLE_REGS. */
323 static const struct elim_table_1
327 } reg_eliminate_1
[] =
329 /* If a set of eliminable registers was specified, define the table from it.
330 Otherwise, default to the normal case of the frame pointer being
331 replaced by the stack pointer. */
333 #ifdef ELIMINABLE_REGS
336 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
339 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
341 /* Record the number of pending eliminations that have an offset not equal
342 to their initial offset. If nonzero, we use a new copy of each
343 replacement result in any insns encountered. */
344 int num_not_at_initial_offset
;
346 /* Count the number of registers that we may be able to eliminate. */
347 static int num_eliminable
;
348 /* And the number of registers that are equivalent to a constant that
349 can be eliminated to frame_pointer / arg_pointer + constant. */
350 static int num_eliminable_invariants
;
352 /* For each label, we record the offset of each elimination. If we reach
353 a label by more than one path and an offset differs, we cannot do the
354 elimination. This information is indexed by the difference of the
355 number of the label and the first label number. We can't offset the
356 pointer itself as this can cause problems on machines with segmented
357 memory. The first table is an array of flags that records whether we
358 have yet encountered a label and the second table is an array of arrays,
359 one entry in the latter array for each elimination. */
361 static int first_label_num
;
362 static char *offsets_known_at
;
363 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
365 /* Stack of addresses where an rtx has been changed. We can undo the
366 changes by popping items off the stack and restoring the original
367 value at each location.
369 We use this simplistic undo capability rather than copy_rtx as copy_rtx
370 will not make a deep copy of a normally sharable rtx, such as
371 (const (plus (symbol_ref) (const_int))). If such an expression appears
372 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
373 rtx expression would be changed. See PR 42431. */
377 DEF_VEC_ALLOC_P(rtx_p
,heap
);
378 static VEC(rtx_p
,heap
) *substitute_stack
;
380 /* Number of labels in the current function. */
382 static int num_labels
;
384 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain
*);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain
*, int);
389 static void find_reload_regs (struct insn_chain
*);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx
, enum reg_class
);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx
);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx
, rtx
, int);
398 static void check_eliminable_occurrences (rtx
);
399 static void elimination_effects (rtx
, enum machine_mode
);
400 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
401 static int eliminate_regs_in_insn (rtx
, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx
, const_rtx
, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx
);
408 static void init_eliminable_invariants (rtx
, bool);
409 static void init_elim_table (void);
410 static void free_reg_equiv (void);
411 static void update_eliminables (HARD_REG_SET
*);
412 static void elimination_costs_in_insn (rtx
);
413 static void spill_hard_reg (unsigned int, int);
414 static int finish_spills (int);
415 static void scan_paradoxical_subregs (rtx
);
416 static void count_pseudo (int);
417 static void order_regs_for_reload (struct insn_chain
*);
418 static void reload_as_needed (int);
419 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
420 static void forget_marked_reloads (regset
);
421 static int reload_reg_class_lower (const void *, const void *);
422 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
424 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
426 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
427 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
429 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
431 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
432 static int allocate_reload_reg (struct insn_chain
*, int, int);
433 static int conflicts_with_override (rtx
);
434 static void failed_reload (rtx
, int);
435 static int set_reload_reg (int, int);
436 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
437 static void choose_reload_regs (struct insn_chain
*);
438 static void merge_assigned_reloads (rtx
);
439 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
441 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
443 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
444 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
445 static void emit_reload_insns (struct insn_chain
*);
446 static void delete_output_reload (rtx
, int, int, rtx
);
447 static void delete_address_reloads (rtx
, rtx
);
448 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
449 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
451 static void add_auto_inc_notes (rtx
, rtx
);
453 static void substitute (rtx
*, const_rtx
, rtx
);
454 static bool gen_reload_chain_without_interm_reg_p (int, int);
455 static int reloads_conflict (int, int);
456 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
457 static rtx
emit_insn_if_valid_for_reload (rtx
);
459 /* Initialize the reload pass. This is called at the beginning of compilation
460 and may be called again if the target is reinitialized. */
467 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
468 Set spill_indirect_levels to the number of levels such addressing is
469 permitted, zero if it is not permitted at all. */
472 = gen_rtx_MEM (Pmode
,
475 LAST_VIRTUAL_REGISTER
+ 1),
477 spill_indirect_levels
= 0;
479 while (memory_address_p (QImode
, tem
))
481 spill_indirect_levels
++;
482 tem
= gen_rtx_MEM (Pmode
, tem
);
485 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
487 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
488 indirect_symref_ok
= memory_address_p (QImode
, tem
);
490 /* See if reg+reg is a valid (and offsettable) address. */
492 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
494 tem
= gen_rtx_PLUS (Pmode
,
495 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
496 gen_rtx_REG (Pmode
, i
));
498 /* This way, we make sure that reg+reg is an offsettable address. */
499 tem
= plus_constant (tem
, 4);
501 if (memory_address_p (QImode
, tem
))
503 double_reg_address_ok
= 1;
508 /* Initialize obstack for our rtl allocation. */
509 gcc_obstack_init (&reload_obstack
);
510 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
512 INIT_REG_SET (&spilled_pseudos
);
513 INIT_REG_SET (&changed_allocation_pseudos
);
514 INIT_REG_SET (&pseudos_counted
);
517 /* List of insn chains that are currently unused. */
518 static struct insn_chain
*unused_insn_chains
= 0;
520 /* Allocate an empty insn_chain structure. */
522 new_insn_chain (void)
524 struct insn_chain
*c
;
526 if (unused_insn_chains
== 0)
528 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
529 INIT_REG_SET (&c
->live_throughout
);
530 INIT_REG_SET (&c
->dead_or_set
);
534 c
= unused_insn_chains
;
535 unused_insn_chains
= c
->next
;
537 c
->is_caller_save_insn
= 0;
538 c
->need_operand_change
= 0;
544 /* Small utility function to set all regs in hard reg set TO which are
545 allocated to pseudos in regset FROM. */
548 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
551 reg_set_iterator rsi
;
553 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
555 int r
= reg_renumber
[regno
];
559 /* reload_combine uses the information from DF_LIVE_IN,
560 which might still contain registers that have not
561 actually been allocated since they have an
563 gcc_assert (ira_conflicts_p
|| reload_completed
);
566 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
570 /* Replace all pseudos found in LOC with their corresponding
574 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
587 unsigned int regno
= REGNO (x
);
589 if (regno
< FIRST_PSEUDO_REGISTER
)
592 x
= eliminate_regs (x
, mem_mode
, usage
);
596 replace_pseudos_in (loc
, mem_mode
, usage
);
600 if (reg_equiv_constant
[regno
])
601 *loc
= reg_equiv_constant
[regno
];
602 else if (reg_equiv_mem
[regno
])
603 *loc
= reg_equiv_mem
[regno
];
604 else if (reg_equiv_address
[regno
])
605 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
608 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
609 || REGNO (regno_reg_rtx
[regno
]) != regno
);
610 *loc
= regno_reg_rtx
[regno
];
615 else if (code
== MEM
)
617 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
621 /* Process each of our operands recursively. */
622 fmt
= GET_RTX_FORMAT (code
);
623 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
625 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
626 else if (*fmt
== 'E')
627 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
628 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
631 /* Determine if the current function has an exception receiver block
632 that reaches the exit block via non-exceptional edges */
635 has_nonexceptional_receiver (void)
639 basic_block
*tos
, *worklist
, bb
;
641 /* If we're not optimizing, then just err on the safe side. */
645 /* First determine which blocks can reach exit via normal paths. */
646 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
649 bb
->flags
&= ~BB_REACHABLE
;
651 /* Place the exit block on our worklist. */
652 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
653 *tos
++ = EXIT_BLOCK_PTR
;
655 /* Iterate: find everything reachable from what we've already seen. */
656 while (tos
!= worklist
)
660 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
661 if (!(e
->flags
& EDGE_ABNORMAL
))
663 basic_block src
= e
->src
;
665 if (!(src
->flags
& BB_REACHABLE
))
667 src
->flags
|= BB_REACHABLE
;
674 /* Now see if there's a reachable block with an exceptional incoming
677 if (bb
->flags
& BB_REACHABLE
)
678 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
679 if (e
->flags
& EDGE_ABNORMAL
)
682 /* No exceptional block reached exit unexceptionally. */
687 /* Global variables used by reload and its subroutines. */
689 /* The current basic block while in calculate_elim_costs_all_insns. */
690 static basic_block elim_bb
;
692 /* Set during calculate_needs if an insn needs register elimination. */
693 static int something_needs_elimination
;
694 /* Set during calculate_needs if an insn needs an operand changed. */
695 static int something_needs_operands_changed
;
696 /* Set by alter_regs if we spilled a register to the stack. */
697 static bool something_was_spilled
;
699 /* Nonzero means we couldn't get enough spill regs. */
702 /* Temporary array of pseudo-register number. */
703 static int *temp_pseudo_reg_arr
;
705 /* Main entry point for the reload pass.
707 FIRST is the first insn of the function being compiled.
709 GLOBAL nonzero means we were called from global_alloc
710 and should attempt to reallocate any pseudoregs that we
711 displace from hard regs we will use for reloads.
712 If GLOBAL is zero, we do not have enough information to do that,
713 so any pseudo reg that is spilled must go to the stack.
715 Return value is nonzero if reload failed
716 and we must not do any more for this function. */
719 reload (rtx first
, int global
)
723 struct elim_table
*ep
;
726 /* Make sure even insns with volatile mem refs are recognizable. */
731 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
733 /* Make sure that the last insn in the chain
734 is not something that needs reloading. */
735 emit_note (NOTE_INSN_DELETED
);
737 /* Enable find_equiv_reg to distinguish insns made by reload. */
738 reload_first_uid
= get_max_uid ();
740 #ifdef SECONDARY_MEMORY_NEEDED
741 /* Initialize the secondary memory table. */
742 clear_secondary_mem ();
745 /* We don't have a stack slot for any spill reg yet. */
746 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
747 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
749 /* Initialize the save area information for caller-save, in case some
753 /* Compute which hard registers are now in use
754 as homes for pseudo registers.
755 This is done here rather than (eg) in global_alloc
756 because this point is reached even if not optimizing. */
757 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
760 /* A function that has a nonlocal label that can reach the exit
761 block via non-exceptional paths must save all call-saved
763 if (cfun
->has_nonlocal_label
764 && has_nonexceptional_receiver ())
765 crtl
->saves_all_registers
= 1;
767 if (crtl
->saves_all_registers
)
768 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
769 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
770 df_set_regs_ever_live (i
, true);
772 reg_old_renumber
= XCNEWVEC (short, max_regno
);
773 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
774 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
775 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
777 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
779 init_eliminable_invariants (first
, true);
782 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
783 stack slots to the pseudos that lack hard regs or equivalents.
784 Do not touch virtual registers. */
786 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
787 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
788 temp_pseudo_reg_arr
[n
++] = i
;
791 /* Ask IRA to order pseudo-registers for better stack slot
793 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
795 for (i
= 0; i
< n
; i
++)
796 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
798 /* If we have some registers we think can be eliminated, scan all insns to
799 see if there is an insn that sets one of these registers to something
800 other than itself plus a constant. If so, the register cannot be
801 eliminated. Doing this scan here eliminates an extra pass through the
802 main reload loop in the most common case where register elimination
804 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
806 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
808 maybe_fix_stack_asms ();
810 insns_need_reload
= 0;
811 something_needs_elimination
= 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs
);
818 /* There can be multiple ways to eliminate a register;
819 they should be listed adjacently.
820 Elimination for any register fails only if all possible ways fail. */
821 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
824 int can_eliminate
= 0;
827 can_eliminate
|= ep
->can_eliminate
;
830 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
832 spill_hard_reg (from
, 1);
835 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
836 if (frame_pointer_needed
)
837 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
839 finish_spills (global
);
841 /* From now on, we may need to generate moves differently. We may also
842 allow modifications of insns which cause them to not be recognized.
843 Any such modifications will be cleaned up during reload itself. */
844 reload_in_progress
= 1;
846 /* This loop scans the entire function each go-round
847 and repeats until one repetition spills no additional hard regs. */
850 int something_changed
;
852 HOST_WIDE_INT starting_frame_size
;
854 starting_frame_size
= get_frame_size ();
855 something_was_spilled
= false;
857 set_initial_elim_offsets ();
858 set_initial_label_offsets ();
860 /* For each pseudo register that has an equivalent location defined,
861 try to eliminate any eliminable registers (such as the frame pointer)
862 assuming initial offsets for the replacement register, which
865 If the resulting location is directly addressable, substitute
866 the MEM we just got directly for the old REG.
868 If it is not addressable but is a constant or the sum of a hard reg
869 and constant, it is probably not addressable because the constant is
870 out of range, in that case record the address; we will generate
871 hairy code to compute the address in a register each time it is
872 needed. Similarly if it is a hard register, but one that is not
873 valid as an address register.
875 If the location is not addressable, but does not have one of the
876 above forms, assign a stack slot. We have to do this to avoid the
877 potential of producing lots of reloads if, e.g., a location involves
878 a pseudo that didn't get a hard register and has an equivalent memory
879 location that also involves a pseudo that didn't get a hard register.
881 Perhaps at some point we will improve reload_when_needed handling
882 so this problem goes away. But that's very hairy. */
884 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
885 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
887 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], VOIDmode
,
890 if (strict_memory_address_addr_space_p
891 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
893 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
894 else if (CONSTANT_P (XEXP (x
, 0))
895 || (REG_P (XEXP (x
, 0))
896 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
897 || (GET_CODE (XEXP (x
, 0)) == PLUS
898 && REG_P (XEXP (XEXP (x
, 0), 0))
899 && (REGNO (XEXP (XEXP (x
, 0), 0))
900 < FIRST_PSEUDO_REGISTER
)
901 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
902 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
905 /* Make a new stack slot. Then indicate that something
906 changed so we go back and recompute offsets for
907 eliminable registers because the allocation of memory
908 below might change some offset. reg_equiv_{mem,address}
909 will be set up for this pseudo on the next pass around
911 reg_equiv_memory_loc
[i
] = 0;
912 reg_equiv_init
[i
] = 0;
913 alter_reg (i
, -1, true);
917 if (caller_save_needed
)
920 /* If we allocated another stack slot, redo elimination bookkeeping. */
921 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
923 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
925 /* If we have a stack frame, we must align it now. The
926 stack size may be a part of the offset computation for
927 register elimination. So if this changes the stack size,
928 then repeat the elimination bookkeeping. We don't
929 realign when there is no stack, as that will cause a
930 stack frame when none is needed should
931 STARTING_FRAME_OFFSET not be already aligned to
933 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
934 if (starting_frame_size
!= get_frame_size ())
938 if (caller_save_needed
)
940 save_call_clobbered_regs ();
941 /* That might have allocated new insn_chain structures. */
942 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
945 calculate_needs_all_insns (global
);
947 if (! ira_conflicts_p
)
948 /* Don't do it for IRA. We need this info because we don't
949 change live_throughout and dead_or_set for chains when IRA
951 CLEAR_REG_SET (&spilled_pseudos
);
955 something_changed
= 0;
957 /* If we allocated any new memory locations, make another pass
958 since it might have changed elimination offsets. */
959 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
960 something_changed
= 1;
962 /* Even if the frame size remained the same, we might still have
963 changed elimination offsets, e.g. if find_reloads called
964 force_const_mem requiring the back end to allocate a constant
965 pool base register that needs to be saved on the stack. */
966 else if (!verify_initial_elim_offsets ())
967 something_changed
= 1;
970 HARD_REG_SET to_spill
;
971 CLEAR_HARD_REG_SET (to_spill
);
972 update_eliminables (&to_spill
);
973 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
975 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
976 if (TEST_HARD_REG_BIT (to_spill
, i
))
978 spill_hard_reg (i
, 1);
981 /* Regardless of the state of spills, if we previously had
982 a register that we thought we could eliminate, but now can
983 not eliminate, we must run another pass.
985 Consider pseudos which have an entry in reg_equiv_* which
986 reference an eliminable register. We must make another pass
987 to update reg_equiv_* so that we do not substitute in the
988 old value from when we thought the elimination could be
990 something_changed
= 1;
994 select_reload_regs ();
998 if (insns_need_reload
!= 0 || did_spill
)
999 something_changed
|= finish_spills (global
);
1001 if (! something_changed
)
1004 if (caller_save_needed
)
1005 delete_caller_save_insns ();
1007 obstack_free (&reload_obstack
, reload_firstobj
);
1010 /* If global-alloc was run, notify it of any register eliminations we have
1013 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1014 if (ep
->can_eliminate
)
1015 mark_elimination (ep
->from
, ep
->to
);
1017 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1018 If that insn didn't set the register (i.e., it copied the register to
1019 memory), just delete that insn instead of the equivalencing insn plus
1020 anything now dead. If we call delete_dead_insn on that insn, we may
1021 delete the insn that actually sets the register if the register dies
1022 there and that is incorrect. */
1024 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1026 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1029 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1031 rtx equiv_insn
= XEXP (list
, 0);
1033 /* If we already deleted the insn or if it may trap, we can't
1034 delete it. The latter case shouldn't happen, but can
1035 if an insn has a variable address, gets a REG_EH_REGION
1036 note added to it, and then gets converted into a load
1037 from a constant address. */
1038 if (NOTE_P (equiv_insn
)
1039 || can_throw_internal (equiv_insn
))
1041 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1042 delete_dead_insn (equiv_insn
);
1044 SET_INSN_DELETED (equiv_insn
);
1049 /* Use the reload registers where necessary
1050 by generating move instructions to move the must-be-register
1051 values into or out of the reload registers. */
1053 if (insns_need_reload
!= 0 || something_needs_elimination
1054 || something_needs_operands_changed
)
1056 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1058 reload_as_needed (global
);
1060 gcc_assert (old_frame_size
== get_frame_size ());
1062 gcc_assert (verify_initial_elim_offsets ());
1065 /* If we were able to eliminate the frame pointer, show that it is no
1066 longer live at the start of any basic block. If it ls live by
1067 virtue of being in a pseudo, that pseudo will be marked live
1068 and hence the frame pointer will be known to be live via that
1071 if (! frame_pointer_needed
)
1073 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1075 /* Come here (with failure set nonzero) if we can't get enough spill
1079 CLEAR_REG_SET (&changed_allocation_pseudos
);
1080 CLEAR_REG_SET (&spilled_pseudos
);
1081 reload_in_progress
= 0;
1083 /* Now eliminate all pseudo regs by modifying them into
1084 their equivalent memory references.
1085 The REG-rtx's for the pseudos are modified in place,
1086 so all insns that used to refer to them now refer to memory.
1088 For a reg that has a reg_equiv_address, all those insns
1089 were changed by reloading so that no insns refer to it any longer;
1090 but the DECL_RTL of a variable decl may refer to it,
1091 and if so this causes the debugging info to mention the variable. */
1093 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1097 if (reg_equiv_mem
[i
])
1098 addr
= XEXP (reg_equiv_mem
[i
], 0);
1100 if (reg_equiv_address
[i
])
1101 addr
= reg_equiv_address
[i
];
1105 if (reg_renumber
[i
] < 0)
1107 rtx reg
= regno_reg_rtx
[i
];
1109 REG_USERVAR_P (reg
) = 0;
1110 PUT_CODE (reg
, MEM
);
1111 XEXP (reg
, 0) = addr
;
1112 if (reg_equiv_memory_loc
[i
])
1113 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1116 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1117 MEM_ATTRS (reg
) = 0;
1119 MEM_NOTRAP_P (reg
) = 1;
1121 else if (reg_equiv_mem
[i
])
1122 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1125 /* We don't want complex addressing modes in debug insns
1126 if simpler ones will do, so delegitimize equivalences
1128 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1130 rtx reg
= regno_reg_rtx
[i
];
1134 if (reg_equiv_constant
[i
])
1135 equiv
= reg_equiv_constant
[i
];
1136 else if (reg_equiv_invariant
[i
])
1137 equiv
= reg_equiv_invariant
[i
];
1138 else if (reg
&& MEM_P (reg
))
1139 equiv
= targetm
.delegitimize_address (reg
);
1140 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1146 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1148 insn
= DF_REF_INSN (use
);
1150 /* Make sure the next ref is for a different instruction,
1151 so that we're not affected by the rescan. */
1152 next
= DF_REF_NEXT_REG (use
);
1153 while (next
&& DF_REF_INSN (next
) == insn
)
1154 next
= DF_REF_NEXT_REG (next
);
1156 if (DEBUG_INSN_P (insn
))
1160 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1161 df_insn_rescan_debug_internal (insn
);
1164 INSN_VAR_LOCATION_LOC (insn
)
1165 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1172 /* We must set reload_completed now since the cleanup_subreg_operands call
1173 below will re-recognize each insn and reload may have generated insns
1174 which are only valid during and after reload. */
1175 reload_completed
= 1;
1177 /* Make a pass over all the insns and delete all USEs which we inserted
1178 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1179 notes. Delete all CLOBBER insns, except those that refer to the return
1180 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1181 from misarranging variable-array code, and simplify (subreg (reg))
1182 operands. Strip and regenerate REG_INC notes that may have been moved
1185 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1191 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1192 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1194 if ((GET_CODE (PATTERN (insn
)) == USE
1195 /* We mark with QImode USEs introduced by reload itself. */
1196 && (GET_MODE (insn
) == QImode
1197 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1198 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1199 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1200 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1201 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1202 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1203 != stack_pointer_rtx
))
1204 && (!REG_P (XEXP (PATTERN (insn
), 0))
1205 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1211 /* Some CLOBBERs may survive until here and still reference unassigned
1212 pseudos with const equivalent, which may in turn cause ICE in later
1213 passes if the reference remains in place. */
1214 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1215 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1216 VOIDmode
, PATTERN (insn
));
1218 /* Discard obvious no-ops, even without -O. This optimization
1219 is fast and doesn't interfere with debugging. */
1220 if (NONJUMP_INSN_P (insn
)
1221 && GET_CODE (PATTERN (insn
)) == SET
1222 && REG_P (SET_SRC (PATTERN (insn
)))
1223 && REG_P (SET_DEST (PATTERN (insn
)))
1224 && (REGNO (SET_SRC (PATTERN (insn
)))
1225 == REGNO (SET_DEST (PATTERN (insn
)))))
1231 pnote
= ®_NOTES (insn
);
1234 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1235 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1236 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1237 *pnote
= XEXP (*pnote
, 1);
1239 pnote
= &XEXP (*pnote
, 1);
1243 add_auto_inc_notes (insn
, PATTERN (insn
));
1246 /* Simplify (subreg (reg)) if it appears as an operand. */
1247 cleanup_subreg_operands (insn
);
1249 /* Clean up invalid ASMs so that they don't confuse later passes.
1251 if (asm_noperands (PATTERN (insn
)) >= 0)
1253 extract_insn (insn
);
1254 if (!constrain_operands (1))
1256 error_for_asm (insn
,
1257 "%<asm%> operand has impossible constraints");
1264 /* If we are doing generic stack checking, give a warning if this
1265 function's frame size is larger than we expect. */
1266 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1268 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1269 static int verbose_warned
= 0;
1271 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1272 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1273 size
+= UNITS_PER_WORD
;
1275 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1277 warning (0, "frame size too large for reliable stack checking");
1278 if (! verbose_warned
)
1280 warning (0, "try reducing the number of local variables");
1286 free (temp_pseudo_reg_arr
);
1288 /* Indicate that we no longer have known memory locations or constants. */
1291 free (reg_max_ref_width
);
1292 free (reg_old_renumber
);
1293 free (pseudo_previous_regs
);
1294 free (pseudo_forbidden_regs
);
1296 CLEAR_HARD_REG_SET (used_spill_regs
);
1297 for (i
= 0; i
< n_spills
; i
++)
1298 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1300 /* Free all the insn_chain structures at once. */
1301 obstack_free (&reload_obstack
, reload_startobj
);
1302 unused_insn_chains
= 0;
1303 fixup_abnormal_edges ();
1305 /* Replacing pseudos with their memory equivalents might have
1306 created shared rtx. Subsequent passes would get confused
1307 by this, so unshare everything here. */
1308 unshare_all_rtl_again (first
);
1310 #ifdef STACK_BOUNDARY
1311 /* init_emit has set the alignment of the hard frame pointer
1312 to STACK_BOUNDARY. It is very likely no longer valid if
1313 the hard frame pointer was used for register allocation. */
1314 if (!frame_pointer_needed
)
1315 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1318 VEC_free (rtx_p
, heap
, substitute_stack
);
1323 /* Yet another special case. Unfortunately, reg-stack forces people to
1324 write incorrect clobbers in asm statements. These clobbers must not
1325 cause the register to appear in bad_spill_regs, otherwise we'll call
1326 fatal_insn later. We clear the corresponding regnos in the live
1327 register sets to avoid this.
1328 The whole thing is rather sick, I'm afraid. */
1331 maybe_fix_stack_asms (void)
1334 const char *constraints
[MAX_RECOG_OPERANDS
];
1335 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1336 struct insn_chain
*chain
;
1338 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1341 HARD_REG_SET clobbered
, allowed
;
1344 if (! INSN_P (chain
->insn
)
1345 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1347 pat
= PATTERN (chain
->insn
);
1348 if (GET_CODE (pat
) != PARALLEL
)
1351 CLEAR_HARD_REG_SET (clobbered
);
1352 CLEAR_HARD_REG_SET (allowed
);
1354 /* First, make a mask of all stack regs that are clobbered. */
1355 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1357 rtx t
= XVECEXP (pat
, 0, i
);
1358 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1359 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1362 /* Get the operand values and constraints out of the insn. */
1363 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1364 constraints
, operand_mode
, NULL
);
1366 /* For every operand, see what registers are allowed. */
1367 for (i
= 0; i
< noperands
; i
++)
1369 const char *p
= constraints
[i
];
1370 /* For every alternative, we compute the class of registers allowed
1371 for reloading in CLS, and merge its contents into the reg set
1373 int cls
= (int) NO_REGS
;
1379 if (c
== '\0' || c
== ',' || c
== '#')
1381 /* End of one alternative - mark the regs in the current
1382 class, and reset the class. */
1383 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1389 } while (c
!= '\0' && c
!= ',');
1397 case '=': case '+': case '*': case '%': case '?': case '!':
1398 case '0': case '1': case '2': case '3': case '4': case '<':
1399 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1400 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1401 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1402 case TARGET_MEM_CONSTRAINT
:
1406 cls
= (int) reg_class_subunion
[cls
]
1407 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1412 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1416 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1417 cls
= (int) reg_class_subunion
[cls
]
1418 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1420 cls
= (int) reg_class_subunion
[cls
]
1421 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1423 p
+= CONSTRAINT_LEN (c
, p
);
1426 /* Those of the registers which are clobbered, but allowed by the
1427 constraints, must be usable as reload registers. So clear them
1428 out of the life information. */
1429 AND_HARD_REG_SET (allowed
, clobbered
);
1430 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1431 if (TEST_HARD_REG_BIT (allowed
, i
))
1433 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1434 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1441 /* Copy the global variables n_reloads and rld into the corresponding elts
1444 copy_reloads (struct insn_chain
*chain
)
1446 chain
->n_reloads
= n_reloads
;
1447 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1448 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1449 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1452 /* Walk the chain of insns, and determine for each whether it needs reloads
1453 and/or eliminations. Build the corresponding insns_need_reload list, and
1454 set something_needs_elimination as appropriate. */
1456 calculate_needs_all_insns (int global
)
1458 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1459 struct insn_chain
*chain
, *next
= 0;
1461 something_needs_elimination
= 0;
1463 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1464 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1466 rtx insn
= chain
->insn
;
1470 /* Clear out the shortcuts. */
1471 chain
->n_reloads
= 0;
1472 chain
->need_elim
= 0;
1473 chain
->need_reload
= 0;
1474 chain
->need_operand_change
= 0;
1476 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1477 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1478 what effects this has on the known offsets at labels. */
1480 if (LABEL_P (insn
) || JUMP_P (insn
)
1481 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1482 set_label_offsets (insn
, insn
, 0);
1486 rtx old_body
= PATTERN (insn
);
1487 int old_code
= INSN_CODE (insn
);
1488 rtx old_notes
= REG_NOTES (insn
);
1489 int did_elimination
= 0;
1490 int operands_changed
= 0;
1491 rtx set
= single_set (insn
);
1493 /* Skip insns that only set an equivalence. */
1494 if (set
&& REG_P (SET_DEST (set
))
1495 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1496 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1497 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))]))
1498 && reg_equiv_init
[REGNO (SET_DEST (set
))])
1501 /* If needed, eliminate any eliminable registers. */
1502 if (num_eliminable
|| num_eliminable_invariants
)
1503 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1505 /* Analyze the instruction. */
1506 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1507 global
, spill_reg_order
);
1509 /* If a no-op set needs more than one reload, this is likely
1510 to be something that needs input address reloads. We
1511 can't get rid of this cleanly later, and it is of no use
1512 anyway, so discard it now.
1513 We only do this when expensive_optimizations is enabled,
1514 since this complements reload inheritance / output
1515 reload deletion, and it can make debugging harder. */
1516 if (flag_expensive_optimizations
&& n_reloads
> 1)
1518 rtx set
= single_set (insn
);
1521 ((SET_SRC (set
) == SET_DEST (set
)
1522 && REG_P (SET_SRC (set
))
1523 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1524 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1525 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1526 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1527 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))] != NULL
1528 && reg_equiv_memory_loc
[REGNO (SET_DEST (set
))] != NULL
1529 && rtx_equal_p (reg_equiv_memory_loc
1530 [REGNO (SET_SRC (set
))],
1531 reg_equiv_memory_loc
1532 [REGNO (SET_DEST (set
))]))))
1534 if (ira_conflicts_p
)
1535 /* Inform IRA about the insn deletion. */
1536 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1537 REGNO (SET_SRC (set
)));
1539 /* Delete it from the reload chain. */
1541 chain
->prev
->next
= next
;
1543 reload_insn_chain
= next
;
1545 next
->prev
= chain
->prev
;
1546 chain
->next
= unused_insn_chains
;
1547 unused_insn_chains
= chain
;
1552 update_eliminable_offsets ();
1554 /* Remember for later shortcuts which insns had any reloads or
1555 register eliminations. */
1556 chain
->need_elim
= did_elimination
;
1557 chain
->need_reload
= n_reloads
> 0;
1558 chain
->need_operand_change
= operands_changed
;
1560 /* Discard any register replacements done. */
1561 if (did_elimination
)
1563 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1564 PATTERN (insn
) = old_body
;
1565 INSN_CODE (insn
) = old_code
;
1566 REG_NOTES (insn
) = old_notes
;
1567 something_needs_elimination
= 1;
1570 something_needs_operands_changed
|= operands_changed
;
1574 copy_reloads (chain
);
1575 *pprev_reload
= chain
;
1576 pprev_reload
= &chain
->next_need_reload
;
1583 /* This function is called from the register allocator to set up estimates
1584 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1585 an invariant. The structure is similar to calculate_needs_all_insns. */
1588 calculate_elim_costs_all_insns (void)
1590 int *reg_equiv_init_cost
;
1594 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1596 init_eliminable_invariants (get_insns (), false);
1598 set_initial_elim_offsets ();
1599 set_initial_label_offsets ();
1606 FOR_BB_INSNS (bb
, insn
)
1608 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1609 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1610 what effects this has on the known offsets at labels. */
1612 if (LABEL_P (insn
) || JUMP_P (insn
)
1613 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1614 set_label_offsets (insn
, insn
, 0);
1618 rtx set
= single_set (insn
);
1620 /* Skip insns that only set an equivalence. */
1621 if (set
&& REG_P (SET_DEST (set
))
1622 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1623 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1624 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))])))
1626 unsigned regno
= REGNO (SET_DEST (set
));
1627 rtx init
= reg_equiv_init
[regno
];
1630 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1632 int cost
= rtx_cost (t
, SET
,
1633 optimize_bb_for_speed_p (bb
));
1634 int freq
= REG_FREQ_FROM_BB (bb
);
1636 reg_equiv_init_cost
[regno
] = cost
* freq
;
1640 /* If needed, eliminate any eliminable registers. */
1641 if (num_eliminable
|| num_eliminable_invariants
)
1642 elimination_costs_in_insn (insn
);
1645 update_eliminable_offsets ();
1649 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1651 if (reg_equiv_invariant
[i
])
1653 if (reg_equiv_init
[i
])
1655 int cost
= reg_equiv_init_cost
[i
];
1658 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1660 ira_adjust_equiv_reg_cost (i
, cost
);
1666 "Reg %d had equivalence, but can't be eliminated\n",
1668 ira_adjust_equiv_reg_cost (i
, 0);
1674 free (reg_equiv_init_cost
);
1677 /* Comparison function for qsort to decide which of two reloads
1678 should be handled first. *P1 and *P2 are the reload numbers. */
1681 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1683 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1686 /* Consider required reloads before optional ones. */
1687 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1691 /* Count all solitary classes before non-solitary ones. */
1692 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1693 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1697 /* Aside from solitaires, consider all multi-reg groups first. */
1698 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1702 /* Consider reloads in order of increasing reg-class number. */
1703 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1707 /* If reloads are equally urgent, sort by reload number,
1708 so that the results of qsort leave nothing to chance. */
1712 /* The cost of spilling each hard reg. */
1713 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1715 /* When spilling multiple hard registers, we use SPILL_COST for the first
1716 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1717 only the first hard reg for a multi-reg pseudo. */
1718 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1720 /* Map of hard regno to pseudo regno currently occupying the hard
1722 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1724 /* Update the spill cost arrays, considering that pseudo REG is live. */
1727 count_pseudo (int reg
)
1729 int freq
= REG_FREQ (reg
);
1730 int r
= reg_renumber
[reg
];
1733 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1734 || REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1735 /* Ignore spilled pseudo-registers which can be here only if IRA
1737 || (ira_conflicts_p
&& r
< 0))
1740 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1742 gcc_assert (r
>= 0);
1744 spill_add_cost
[r
] += freq
;
1745 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1748 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1749 spill_cost
[r
+ nregs
] += freq
;
1753 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1754 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1757 order_regs_for_reload (struct insn_chain
*chain
)
1760 HARD_REG_SET used_by_pseudos
;
1761 HARD_REG_SET used_by_pseudos2
;
1762 reg_set_iterator rsi
;
1764 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1766 memset (spill_cost
, 0, sizeof spill_cost
);
1767 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1768 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1769 hard_regno_to_pseudo_regno
[i
] = -1;
1771 /* Count number of uses of each hard reg by pseudo regs allocated to it
1772 and then order them by decreasing use. First exclude hard registers
1773 that are live in or across this insn. */
1775 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1776 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1777 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1778 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1780 /* Now find out which pseudos are allocated to it, and update
1782 CLEAR_REG_SET (&pseudos_counted
);
1784 EXECUTE_IF_SET_IN_REG_SET
1785 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1789 EXECUTE_IF_SET_IN_REG_SET
1790 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1794 CLEAR_REG_SET (&pseudos_counted
);
1797 /* Vector of reload-numbers showing the order in which the reloads should
1799 static short reload_order
[MAX_RELOADS
];
1801 /* This is used to keep track of the spill regs used in one insn. */
1802 static HARD_REG_SET used_spill_regs_local
;
1804 /* We decided to spill hard register SPILLED, which has a size of
1805 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1806 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1807 update SPILL_COST/SPILL_ADD_COST. */
1810 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1812 int freq
= REG_FREQ (reg
);
1813 int r
= reg_renumber
[reg
];
1814 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1816 /* Ignore spilled pseudo-registers which can be here only if IRA is
1818 if ((ira_conflicts_p
&& r
< 0)
1819 || REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1820 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1823 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1825 spill_add_cost
[r
] -= freq
;
1828 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1829 spill_cost
[r
+ nregs
] -= freq
;
1833 /* Find reload register to use for reload number ORDER. */
1836 find_reg (struct insn_chain
*chain
, int order
)
1838 int rnum
= reload_order
[order
];
1839 struct reload
*rl
= rld
+ rnum
;
1840 int best_cost
= INT_MAX
;
1842 unsigned int i
, j
, n
;
1844 HARD_REG_SET not_usable
;
1845 HARD_REG_SET used_by_other_reload
;
1846 reg_set_iterator rsi
;
1847 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1848 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1850 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1851 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1852 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1854 CLEAR_HARD_REG_SET (used_by_other_reload
);
1855 for (k
= 0; k
< order
; k
++)
1857 int other
= reload_order
[k
];
1859 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1860 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1861 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1864 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1866 #ifdef REG_ALLOC_ORDER
1867 unsigned int regno
= reg_alloc_order
[i
];
1869 unsigned int regno
= i
;
1872 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1873 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1874 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1876 int this_cost
= spill_cost
[regno
];
1878 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1880 for (j
= 1; j
< this_nregs
; j
++)
1882 this_cost
+= spill_add_cost
[regno
+ j
];
1883 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1884 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1890 if (ira_conflicts_p
)
1892 /* Ask IRA to find a better pseudo-register for
1894 for (n
= j
= 0; j
< this_nregs
; j
++)
1896 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1900 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1901 regno_pseudo_regs
[n
++] = r
;
1903 regno_pseudo_regs
[n
++] = -1;
1905 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1906 best_regno_pseudo_regs
,
1913 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1914 if (regno_pseudo_regs
[j
] < 0)
1921 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1923 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1925 if (this_cost
< best_cost
1926 /* Among registers with equal cost, prefer caller-saved ones, or
1927 use REG_ALLOC_ORDER if it is defined. */
1928 || (this_cost
== best_cost
1929 #ifdef REG_ALLOC_ORDER
1930 && (inv_reg_alloc_order
[regno
]
1931 < inv_reg_alloc_order
[best_reg
])
1933 && call_used_regs
[regno
]
1934 && ! call_used_regs
[best_reg
]
1939 best_cost
= this_cost
;
1947 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1949 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1950 rl
->regno
= best_reg
;
1952 EXECUTE_IF_SET_IN_REG_SET
1953 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1955 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1958 EXECUTE_IF_SET_IN_REG_SET
1959 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1961 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1964 for (i
= 0; i
< rl
->nregs
; i
++)
1966 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1967 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1968 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1969 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1974 /* Find more reload regs to satisfy the remaining need of an insn, which
1976 Do it by ascending class number, since otherwise a reg
1977 might be spilled for a big class and might fail to count
1978 for a smaller class even though it belongs to that class. */
1981 find_reload_regs (struct insn_chain
*chain
)
1985 /* In order to be certain of getting the registers we need,
1986 we must sort the reloads into order of increasing register class.
1987 Then our grabbing of reload registers will parallel the process
1988 that provided the reload registers. */
1989 for (i
= 0; i
< chain
->n_reloads
; i
++)
1991 /* Show whether this reload already has a hard reg. */
1992 if (chain
->rld
[i
].reg_rtx
)
1994 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1995 chain
->rld
[i
].regno
= regno
;
1997 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2000 chain
->rld
[i
].regno
= -1;
2001 reload_order
[i
] = i
;
2004 n_reloads
= chain
->n_reloads
;
2005 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2007 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2010 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2012 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2014 /* Compute the order of preference for hard registers to spill. */
2016 order_regs_for_reload (chain
);
2018 for (i
= 0; i
< n_reloads
; i
++)
2020 int r
= reload_order
[i
];
2022 /* Ignore reloads that got marked inoperative. */
2023 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2024 && ! rld
[r
].optional
2025 && rld
[r
].regno
== -1)
2026 if (! find_reg (chain
, i
))
2029 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2030 spill_failure (chain
->insn
, rld
[r
].rclass
);
2036 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2037 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2039 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2043 select_reload_regs (void)
2045 struct insn_chain
*chain
;
2047 /* Try to satisfy the needs for each insn. */
2048 for (chain
= insns_need_reload
; chain
!= 0;
2049 chain
= chain
->next_need_reload
)
2050 find_reload_regs (chain
);
2053 /* Delete all insns that were inserted by emit_caller_save_insns during
2056 delete_caller_save_insns (void)
2058 struct insn_chain
*c
= reload_insn_chain
;
2062 while (c
!= 0 && c
->is_caller_save_insn
)
2064 struct insn_chain
*next
= c
->next
;
2067 if (c
== reload_insn_chain
)
2068 reload_insn_chain
= next
;
2072 next
->prev
= c
->prev
;
2074 c
->prev
->next
= next
;
2075 c
->next
= unused_insn_chains
;
2076 unused_insn_chains
= c
;
2084 /* Handle the failure to find a register to spill.
2085 INSN should be one of the insns which needed this particular spill reg. */
2088 spill_failure (rtx insn
, enum reg_class rclass
)
2090 if (asm_noperands (PATTERN (insn
)) >= 0)
2091 error_for_asm (insn
, "can't find a register in class %qs while "
2092 "reloading %<asm%>",
2093 reg_class_names
[rclass
]);
2096 error ("unable to find a register to spill in class %qs",
2097 reg_class_names
[rclass
]);
2101 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2102 debug_reload_to_stream (dump_file
);
2104 fatal_insn ("this is the insn:", insn
);
2108 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2109 data that is dead in INSN. */
2112 delete_dead_insn (rtx insn
)
2114 rtx prev
= prev_real_insn (insn
);
2117 /* If the previous insn sets a register that dies in our insn, delete it
2119 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2120 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2121 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2122 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2123 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2124 delete_dead_insn (prev
);
2126 SET_INSN_DELETED (insn
);
2129 /* Modify the home of pseudo-reg I.
2130 The new home is present in reg_renumber[I].
2132 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2133 or it may be -1, meaning there is none or it is not relevant.
2134 This is used so that all pseudos spilled from a given hard reg
2135 can share one stack slot. */
2138 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2140 /* When outputting an inline function, this can happen
2141 for a reg that isn't actually used. */
2142 if (regno_reg_rtx
[i
] == 0)
2145 /* If the reg got changed to a MEM at rtl-generation time,
2147 if (!REG_P (regno_reg_rtx
[i
]))
2150 /* Modify the reg-rtx to contain the new hard reg
2151 number or else to contain its pseudo reg number. */
2152 SET_REGNO (regno_reg_rtx
[i
],
2153 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2155 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2156 allocate a stack slot for it. */
2158 if (reg_renumber
[i
] < 0
2159 && REG_N_REFS (i
) > 0
2160 && reg_equiv_constant
[i
] == 0
2161 && (reg_equiv_invariant
[i
] == 0 || reg_equiv_init
[i
] == 0)
2162 && reg_equiv_memory_loc
[i
] == 0)
2165 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2166 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2167 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2168 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2169 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2172 something_was_spilled
= true;
2174 if (ira_conflicts_p
)
2176 /* Mark the spill for IRA. */
2177 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2179 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2185 /* Each pseudo reg has an inherent size which comes from its own mode,
2186 and a total size which provides room for paradoxical subregs
2187 which refer to the pseudo reg in wider modes.
2189 We can use a slot already allocated if it provides both
2190 enough inherent space and enough total space.
2191 Otherwise, we allocate a new slot, making sure that it has no less
2192 inherent space, and no less total space, then the previous slot. */
2193 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2197 /* No known place to spill from => no slot to reuse. */
2198 x
= assign_stack_local (mode
, total_size
,
2199 min_align
> inherent_align
2200 || total_size
> inherent_size
? -1 : 0);
2204 /* Cancel the big-endian correction done in assign_stack_local.
2205 Get the address of the beginning of the slot. This is so we
2206 can do a big-endian correction unconditionally below. */
2207 if (BYTES_BIG_ENDIAN
)
2209 adjust
= inherent_size
- total_size
;
2212 = adjust_address_nv (x
, mode_for_size (total_size
2218 if (! dont_share_p
&& ira_conflicts_p
)
2219 /* Inform IRA about allocation a new stack slot. */
2220 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2223 /* Reuse a stack slot if possible. */
2224 else if (spill_stack_slot
[from_reg
] != 0
2225 && spill_stack_slot_width
[from_reg
] >= total_size
2226 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2228 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2229 x
= spill_stack_slot
[from_reg
];
2231 /* Allocate a bigger slot. */
2234 /* Compute maximum size needed, both for inherent size
2235 and for total size. */
2238 if (spill_stack_slot
[from_reg
])
2240 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2242 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2243 if (spill_stack_slot_width
[from_reg
] > total_size
)
2244 total_size
= spill_stack_slot_width
[from_reg
];
2245 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2246 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2249 /* Make a slot with that size. */
2250 x
= assign_stack_local (mode
, total_size
,
2251 min_align
> inherent_align
2252 || total_size
> inherent_size
? -1 : 0);
2255 /* Cancel the big-endian correction done in assign_stack_local.
2256 Get the address of the beginning of the slot. This is so we
2257 can do a big-endian correction unconditionally below. */
2258 if (BYTES_BIG_ENDIAN
)
2260 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2263 = adjust_address_nv (x
, mode_for_size (total_size
2269 spill_stack_slot
[from_reg
] = stack_slot
;
2270 spill_stack_slot_width
[from_reg
] = total_size
;
2273 /* On a big endian machine, the "address" of the slot
2274 is the address of the low part that fits its inherent mode. */
2275 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2276 adjust
+= (total_size
- inherent_size
);
2278 /* If we have any adjustment to make, or if the stack slot is the
2279 wrong mode, make a new stack slot. */
2280 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2282 /* Set all of the memory attributes as appropriate for a spill. */
2283 set_mem_attrs_for_spill (x
);
2285 /* Save the stack slot for later. */
2286 reg_equiv_memory_loc
[i
] = x
;
2290 /* Mark the slots in regs_ever_live for the hard regs used by
2291 pseudo-reg number REGNO, accessed in MODE. */
2294 mark_home_live_1 (int regno
, enum machine_mode mode
)
2298 i
= reg_renumber
[regno
];
2301 lim
= end_hard_regno (mode
, i
);
2303 df_set_regs_ever_live(i
++, true);
2306 /* Mark the slots in regs_ever_live for the hard regs
2307 used by pseudo-reg number REGNO. */
2310 mark_home_live (int regno
)
2312 if (reg_renumber
[regno
] >= 0)
2313 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2316 /* This function handles the tracking of elimination offsets around branches.
2318 X is a piece of RTL being scanned.
2320 INSN is the insn that it came from, if any.
2322 INITIAL_P is nonzero if we are to set the offset to be the initial
2323 offset and zero if we are setting the offset of the label to be the
2327 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2329 enum rtx_code code
= GET_CODE (x
);
2332 struct elim_table
*p
;
2337 if (LABEL_REF_NONLOCAL_P (x
))
2342 /* ... fall through ... */
2345 /* If we know nothing about this label, set the desired offsets. Note
2346 that this sets the offset at a label to be the offset before a label
2347 if we don't know anything about the label. This is not correct for
2348 the label after a BARRIER, but is the best guess we can make. If
2349 we guessed wrong, we will suppress an elimination that might have
2350 been possible had we been able to guess correctly. */
2352 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2354 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2355 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2356 = (initial_p
? reg_eliminate
[i
].initial_offset
2357 : reg_eliminate
[i
].offset
);
2358 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2361 /* Otherwise, if this is the definition of a label and it is
2362 preceded by a BARRIER, set our offsets to the known offset of
2366 && (tem
= prev_nonnote_insn (insn
)) != 0
2368 set_offsets_for_label (insn
);
2370 /* If neither of the above cases is true, compare each offset
2371 with those previously recorded and suppress any eliminations
2372 where the offsets disagree. */
2374 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2375 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2376 != (initial_p
? reg_eliminate
[i
].initial_offset
2377 : reg_eliminate
[i
].offset
))
2378 reg_eliminate
[i
].can_eliminate
= 0;
2383 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2385 /* ... fall through ... */
2389 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2390 to indirectly and hence must have all eliminations at their
2392 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2393 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2394 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2400 /* Each of the labels in the parallel or address vector must be
2401 at their initial offsets. We want the first field for PARALLEL
2402 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2404 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2405 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2410 /* We only care about setting PC. If the source is not RETURN,
2411 IF_THEN_ELSE, or a label, disable any eliminations not at
2412 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2413 isn't one of those possibilities. For branches to a label,
2414 call ourselves recursively.
2416 Note that this can disable elimination unnecessarily when we have
2417 a non-local goto since it will look like a non-constant jump to
2418 someplace in the current function. This isn't a significant
2419 problem since such jumps will normally be when all elimination
2420 pairs are back to their initial offsets. */
2422 if (SET_DEST (x
) != pc_rtx
)
2425 switch (GET_CODE (SET_SRC (x
)))
2432 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2436 tem
= XEXP (SET_SRC (x
), 1);
2437 if (GET_CODE (tem
) == LABEL_REF
)
2438 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2439 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2442 tem
= XEXP (SET_SRC (x
), 2);
2443 if (GET_CODE (tem
) == LABEL_REF
)
2444 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2445 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2453 /* If we reach here, all eliminations must be at their initial
2454 offset because we are doing a jump to a variable address. */
2455 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2456 if (p
->offset
!= p
->initial_offset
)
2457 p
->can_eliminate
= 0;
2465 /* Called through for_each_rtx, this function examines every reg that occurs
2466 in PX and adjusts the costs for its elimination which are gathered by IRA.
2467 DATA is the insn in which PX occurs. We do not recurse into MEM
2471 note_reg_elim_costly (rtx
*px
, void *data
)
2473 rtx insn
= (rtx
)data
;
2480 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2481 && reg_equiv_init
[REGNO (x
)]
2482 && reg_equiv_invariant
[REGNO (x
)])
2484 rtx t
= reg_equiv_invariant
[REGNO (x
)];
2485 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2486 int cost
= rtx_cost (new_rtx
, SET
, optimize_bb_for_speed_p (elim_bb
));
2487 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2490 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2495 /* Scan X and replace any eliminable registers (such as fp) with a
2496 replacement (such as sp), plus an offset.
2498 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2499 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2500 MEM, we are allowed to replace a sum of a register and the constant zero
2501 with the register, which we cannot do outside a MEM. In addition, we need
2502 to record the fact that a register is referenced outside a MEM.
2504 If INSN is an insn, it is the insn containing X. If we replace a REG
2505 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2506 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2507 the REG is being modified.
2509 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2510 That's used when we eliminate in expressions stored in notes.
2511 This means, do not set ref_outside_mem even if the reference
2514 If FOR_COSTS is true, we are being called before reload in order to
2515 estimate the costs of keeping registers with an equivalence unallocated.
2517 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2518 replacements done assuming all offsets are at their initial values. If
2519 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2520 encounter, return the actual location so that find_reloads will do
2521 the proper thing. */
2524 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2525 bool may_use_invariant
, bool for_costs
)
2527 enum rtx_code code
= GET_CODE (x
);
2528 struct elim_table
*ep
;
2535 if (! current_function_decl
)
2558 /* First handle the case where we encounter a bare register that
2559 is eliminable. Replace it with a PLUS. */
2560 if (regno
< FIRST_PSEUDO_REGISTER
)
2562 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2564 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2565 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2568 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2569 && reg_equiv_invariant
&& reg_equiv_invariant
[regno
])
2571 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2572 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant
[regno
]),
2573 mem_mode
, insn
, true, for_costs
);
2574 /* There exists at least one use of REGNO that cannot be
2575 eliminated. Prevent the defining insn from being deleted. */
2576 reg_equiv_init
[regno
] = NULL_RTX
;
2578 alter_reg (regno
, -1, true);
2582 /* You might think handling MINUS in a manner similar to PLUS is a
2583 good idea. It is not. It has been tried multiple times and every
2584 time the change has had to have been reverted.
2586 Other parts of reload know a PLUS is special (gen_reload for example)
2587 and require special code to handle code a reloaded PLUS operand.
2589 Also consider backends where the flags register is clobbered by a
2590 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2591 lea instruction comes to mind). If we try to reload a MINUS, we
2592 may kill the flags register that was holding a useful value.
2594 So, please before trying to handle MINUS, consider reload as a
2595 whole instead of this little section as well as the backend issues. */
2597 /* If this is the sum of an eliminable register and a constant, rework
2599 if (REG_P (XEXP (x
, 0))
2600 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2601 && CONSTANT_P (XEXP (x
, 1)))
2603 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2605 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2607 /* The only time we want to replace a PLUS with a REG (this
2608 occurs when the constant operand of the PLUS is the negative
2609 of the offset) is when we are inside a MEM. We won't want
2610 to do so at other times because that would change the
2611 structure of the insn in a way that reload can't handle.
2612 We special-case the commonest situation in
2613 eliminate_regs_in_insn, so just replace a PLUS with a
2614 PLUS here, unless inside a MEM. */
2615 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2616 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2619 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2620 plus_constant (XEXP (x
, 1),
2621 ep
->previous_offset
));
2624 /* If the register is not eliminable, we are done since the other
2625 operand is a constant. */
2629 /* If this is part of an address, we want to bring any constant to the
2630 outermost PLUS. We will do this by doing register replacement in
2631 our operands and seeing if a constant shows up in one of them.
2633 Note that there is no risk of modifying the structure of the insn,
2634 since we only get called for its operands, thus we are either
2635 modifying the address inside a MEM, or something like an address
2636 operand of a load-address insn. */
2639 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2641 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2644 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2646 /* If one side is a PLUS and the other side is a pseudo that
2647 didn't get a hard register but has a reg_equiv_constant,
2648 we must replace the constant here since it may no longer
2649 be in the position of any operand. */
2650 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2651 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2652 && reg_renumber
[REGNO (new1
)] < 0
2653 && reg_equiv_constant
!= 0
2654 && reg_equiv_constant
[REGNO (new1
)] != 0)
2655 new1
= reg_equiv_constant
[REGNO (new1
)];
2656 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2657 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2658 && reg_renumber
[REGNO (new0
)] < 0
2659 && reg_equiv_constant
[REGNO (new0
)] != 0)
2660 new0
= reg_equiv_constant
[REGNO (new0
)];
2662 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2664 /* As above, if we are not inside a MEM we do not want to
2665 turn a PLUS into something else. We might try to do so here
2666 for an addition of 0 if we aren't optimizing. */
2667 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2668 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2676 /* If this is the product of an eliminable register and a
2677 constant, apply the distribute law and move the constant out
2678 so that we have (plus (mult ..) ..). This is needed in order
2679 to keep load-address insns valid. This case is pathological.
2680 We ignore the possibility of overflow here. */
2681 if (REG_P (XEXP (x
, 0))
2682 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2683 && CONST_INT_P (XEXP (x
, 1)))
2684 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2686 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2689 /* Refs inside notes or in DEBUG_INSNs don't count for
2691 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2692 || GET_CODE (insn
) == INSN_LIST
2693 || DEBUG_INSN_P (insn
))))
2694 ep
->ref_outside_mem
= 1;
2697 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2698 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2701 /* ... fall through ... */
2705 /* See comments before PLUS about handling MINUS. */
2707 case DIV
: case UDIV
:
2708 case MOD
: case UMOD
:
2709 case AND
: case IOR
: case XOR
:
2710 case ROTATERT
: case ROTATE
:
2711 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2713 case GE
: case GT
: case GEU
: case GTU
:
2714 case LE
: case LT
: case LEU
: case LTU
:
2716 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2718 rtx new1
= XEXP (x
, 1)
2719 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2722 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2723 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2728 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2731 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2733 if (new_rtx
!= XEXP (x
, 0))
2735 /* If this is a REG_DEAD note, it is not valid anymore.
2736 Using the eliminated version could result in creating a
2737 REG_DEAD note for the stack or frame pointer. */
2738 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2740 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2744 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2748 /* ... fall through ... */
2751 /* Now do eliminations in the rest of the chain. If this was
2752 an EXPR_LIST, this might result in allocating more memory than is
2753 strictly needed, but it simplifies the code. */
2756 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2758 if (new_rtx
!= XEXP (x
, 1))
2760 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2768 /* We do not support elimination of a register that is modified.
2769 elimination_effects has already make sure that this does not
2775 /* We do not support elimination of a register that is modified.
2776 elimination_effects has already make sure that this does not
2777 happen. The only remaining case we need to consider here is
2778 that the increment value may be an eliminable register. */
2779 if (GET_CODE (XEXP (x
, 1)) == PLUS
2780 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2782 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2783 insn
, true, for_costs
);
2785 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2786 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2787 gen_rtx_PLUS (GET_MODE (x
),
2788 XEXP (x
, 0), new_rtx
));
2792 case STRICT_LOW_PART
:
2794 case SIGN_EXTEND
: case ZERO_EXTEND
:
2795 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2796 case FLOAT
: case FIX
:
2797 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2806 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2808 if (new_rtx
!= XEXP (x
, 0))
2809 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2813 /* Similar to above processing, but preserve SUBREG_BYTE.
2814 Convert (subreg (mem)) to (mem) if not paradoxical.
2815 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2816 pseudo didn't get a hard reg, we must replace this with the
2817 eliminated version of the memory location because push_reload
2818 may do the replacement in certain circumstances. */
2819 if (REG_P (SUBREG_REG (x
))
2820 && (GET_MODE_SIZE (GET_MODE (x
))
2821 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2822 && reg_equiv_memory_loc
!= 0
2823 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2825 new_rtx
= SUBREG_REG (x
);
2828 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false,
2831 if (new_rtx
!= SUBREG_REG (x
))
2833 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2834 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2837 && ((x_size
< new_size
2838 #ifdef WORD_REGISTER_OPERATIONS
2839 /* On these machines, combine can create rtl of the form
2840 (set (subreg:m1 (reg:m2 R) 0) ...)
2841 where m1 < m2, and expects something interesting to
2842 happen to the entire word. Moreover, it will use the
2843 (reg:m2 R) later, expecting all bits to be preserved.
2844 So if the number of words is the same, preserve the
2845 subreg so that push_reload can see it. */
2846 && ! ((x_size
- 1) / UNITS_PER_WORD
2847 == (new_size
-1 ) / UNITS_PER_WORD
)
2850 || x_size
== new_size
)
2852 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2854 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2860 /* Our only special processing is to pass the mode of the MEM to our
2861 recursive call and copy the flags. While we are here, handle this
2862 case more efficiently. */
2864 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2867 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2868 && !memory_address_p (GET_MODE (x
), new_rtx
))
2869 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2871 return replace_equiv_address_nv (x
, new_rtx
);
2874 /* Handle insn_list USE that a call to a pure function may generate. */
2875 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2877 if (new_rtx
!= XEXP (x
, 0))
2878 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2882 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2893 /* Process each of our operands recursively. If any have changed, make a
2895 fmt
= GET_RTX_FORMAT (code
);
2896 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2900 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2902 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2904 x
= shallow_copy_rtx (x
);
2907 XEXP (x
, i
) = new_rtx
;
2909 else if (*fmt
== 'E')
2912 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2914 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2916 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2918 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2922 x
= shallow_copy_rtx (x
);
2925 XVEC (x
, i
) = new_v
;
2928 XVECEXP (x
, i
, j
) = new_rtx
;
2937 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2939 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2942 /* Scan rtx X for modifications of elimination target registers. Update
2943 the table of eliminables to reflect the changed state. MEM_MODE is
2944 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2947 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2949 enum rtx_code code
= GET_CODE (x
);
2950 struct elim_table
*ep
;
2975 /* First handle the case where we encounter a bare register that
2976 is eliminable. Replace it with a PLUS. */
2977 if (regno
< FIRST_PSEUDO_REGISTER
)
2979 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2981 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2984 ep
->ref_outside_mem
= 1;
2989 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2990 && reg_equiv_constant
[regno
]
2991 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2992 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
3001 /* If we modify the source of an elimination rule, disable it. */
3002 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3003 if (ep
->from_rtx
== XEXP (x
, 0))
3004 ep
->can_eliminate
= 0;
3006 /* If we modify the target of an elimination rule by adding a constant,
3007 update its offset. If we modify the target in any other way, we'll
3008 have to disable the rule as well. */
3009 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3010 if (ep
->to_rtx
== XEXP (x
, 0))
3012 int size
= GET_MODE_SIZE (mem_mode
);
3014 /* If more bytes than MEM_MODE are pushed, account for them. */
3015 #ifdef PUSH_ROUNDING
3016 if (ep
->to_rtx
== stack_pointer_rtx
)
3017 size
= PUSH_ROUNDING (size
);
3019 if (code
== PRE_DEC
|| code
== POST_DEC
)
3021 else if (code
== PRE_INC
|| code
== POST_INC
)
3023 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3025 if (GET_CODE (XEXP (x
, 1)) == PLUS
3026 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3027 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3028 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3030 ep
->can_eliminate
= 0;
3034 /* These two aren't unary operators. */
3035 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3038 /* Fall through to generic unary operation case. */
3039 case STRICT_LOW_PART
:
3041 case SIGN_EXTEND
: case ZERO_EXTEND
:
3042 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3043 case FLOAT
: case FIX
:
3044 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3053 elimination_effects (XEXP (x
, 0), mem_mode
);
3057 if (REG_P (SUBREG_REG (x
))
3058 && (GET_MODE_SIZE (GET_MODE (x
))
3059 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3060 && reg_equiv_memory_loc
!= 0
3061 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
3064 elimination_effects (SUBREG_REG (x
), mem_mode
);
3068 /* If using a register that is the source of an eliminate we still
3069 think can be performed, note it cannot be performed since we don't
3070 know how this register is used. */
3071 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3072 if (ep
->from_rtx
== XEXP (x
, 0))
3073 ep
->can_eliminate
= 0;
3075 elimination_effects (XEXP (x
, 0), mem_mode
);
3079 /* If clobbering a register that is the replacement register for an
3080 elimination we still think can be performed, note that it cannot
3081 be performed. Otherwise, we need not be concerned about it. */
3082 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3083 if (ep
->to_rtx
== XEXP (x
, 0))
3084 ep
->can_eliminate
= 0;
3086 elimination_effects (XEXP (x
, 0), mem_mode
);
3090 /* Check for setting a register that we know about. */
3091 if (REG_P (SET_DEST (x
)))
3093 /* See if this is setting the replacement register for an
3096 If DEST is the hard frame pointer, we do nothing because we
3097 assume that all assignments to the frame pointer are for
3098 non-local gotos and are being done at a time when they are valid
3099 and do not disturb anything else. Some machines want to
3100 eliminate a fake argument pointer (or even a fake frame pointer)
3101 with either the real frame or the stack pointer. Assignments to
3102 the hard frame pointer must not prevent this elimination. */
3104 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3106 if (ep
->to_rtx
== SET_DEST (x
)
3107 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3109 /* If it is being incremented, adjust the offset. Otherwise,
3110 this elimination can't be done. */
3111 rtx src
= SET_SRC (x
);
3113 if (GET_CODE (src
) == PLUS
3114 && XEXP (src
, 0) == SET_DEST (x
)
3115 && CONST_INT_P (XEXP (src
, 1)))
3116 ep
->offset
-= INTVAL (XEXP (src
, 1));
3118 ep
->can_eliminate
= 0;
3122 elimination_effects (SET_DEST (x
), VOIDmode
);
3123 elimination_effects (SET_SRC (x
), VOIDmode
);
3127 /* Our only special processing is to pass the mode of the MEM to our
3129 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3136 fmt
= GET_RTX_FORMAT (code
);
3137 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3140 elimination_effects (XEXP (x
, i
), mem_mode
);
3141 else if (*fmt
== 'E')
3142 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3143 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3147 /* Descend through rtx X and verify that no references to eliminable registers
3148 remain. If any do remain, mark the involved register as not
3152 check_eliminable_occurrences (rtx x
)
3161 code
= GET_CODE (x
);
3163 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3165 struct elim_table
*ep
;
3167 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3168 if (ep
->from_rtx
== x
)
3169 ep
->can_eliminate
= 0;
3173 fmt
= GET_RTX_FORMAT (code
);
3174 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3177 check_eliminable_occurrences (XEXP (x
, i
));
3178 else if (*fmt
== 'E')
3181 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3182 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3187 /* Scan INSN and eliminate all eliminable registers in it.
3189 If REPLACE is nonzero, do the replacement destructively. Also
3190 delete the insn as dead it if it is setting an eliminable register.
3192 If REPLACE is zero, do all our allocations in reload_obstack.
3194 If no eliminations were done and this insn doesn't require any elimination
3195 processing (these are not identical conditions: it might be updating sp,
3196 but not referencing fp; this needs to be seen during reload_as_needed so
3197 that the offset between fp and sp can be taken into consideration), zero
3198 is returned. Otherwise, 1 is returned. */
3201 eliminate_regs_in_insn (rtx insn
, int replace
)
3203 int icode
= recog_memoized (insn
);
3204 rtx old_body
= PATTERN (insn
);
3205 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3206 rtx old_set
= single_set (insn
);
3210 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3211 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3212 struct elim_table
*ep
;
3213 rtx plus_src
, plus_cst_src
;
3215 if (! insn_is_asm
&& icode
< 0)
3217 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3218 || GET_CODE (PATTERN (insn
)) == CLOBBER
3219 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3220 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3221 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3222 || DEBUG_INSN_P (insn
));
3223 if (DEBUG_INSN_P (insn
))
3224 INSN_VAR_LOCATION_LOC (insn
)
3225 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3229 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3230 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3232 /* Check for setting an eliminable register. */
3233 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3234 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3236 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3237 /* If this is setting the frame pointer register to the
3238 hardware frame pointer register and this is an elimination
3239 that will be done (tested above), this insn is really
3240 adjusting the frame pointer downward to compensate for
3241 the adjustment done before a nonlocal goto. */
3242 if (ep
->from
== FRAME_POINTER_REGNUM
3243 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3245 rtx base
= SET_SRC (old_set
);
3246 rtx base_insn
= insn
;
3247 HOST_WIDE_INT offset
= 0;
3249 while (base
!= ep
->to_rtx
)
3251 rtx prev_insn
, prev_set
;
3253 if (GET_CODE (base
) == PLUS
3254 && CONST_INT_P (XEXP (base
, 1)))
3256 offset
+= INTVAL (XEXP (base
, 1));
3257 base
= XEXP (base
, 0);
3259 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3260 && (prev_set
= single_set (prev_insn
)) != 0
3261 && rtx_equal_p (SET_DEST (prev_set
), base
))
3263 base
= SET_SRC (prev_set
);
3264 base_insn
= prev_insn
;
3270 if (base
== ep
->to_rtx
)
3273 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3275 new_body
= old_body
;
3278 new_body
= copy_insn (old_body
);
3279 if (REG_NOTES (insn
))
3280 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3282 PATTERN (insn
) = new_body
;
3283 old_set
= single_set (insn
);
3285 /* First see if this insn remains valid when we
3286 make the change. If not, keep the INSN_CODE
3287 the same and let reload fit it up. */
3288 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3289 validate_change (insn
, &SET_DEST (old_set
),
3291 if (! apply_change_group ())
3293 SET_SRC (old_set
) = src
;
3294 SET_DEST (old_set
) = ep
->to_rtx
;
3303 /* In this case this insn isn't serving a useful purpose. We
3304 will delete it in reload_as_needed once we know that this
3305 elimination is, in fact, being done.
3307 If REPLACE isn't set, we can't delete this insn, but needn't
3308 process it since it won't be used unless something changes. */
3311 delete_dead_insn (insn
);
3319 /* We allow one special case which happens to work on all machines we
3320 currently support: a single set with the source or a REG_EQUAL
3321 note being a PLUS of an eliminable register and a constant. */
3322 plus_src
= plus_cst_src
= 0;
3323 if (old_set
&& REG_P (SET_DEST (old_set
)))
3325 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3326 plus_src
= SET_SRC (old_set
);
3327 /* First see if the source is of the form (plus (...) CST). */
3329 && CONST_INT_P (XEXP (plus_src
, 1)))
3330 plus_cst_src
= plus_src
;
3331 else if (REG_P (SET_SRC (old_set
))
3334 /* Otherwise, see if we have a REG_EQUAL note of the form
3335 (plus (...) CST). */
3337 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3339 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3340 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3341 && GET_CODE (XEXP (links
, 0)) == PLUS
3342 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3344 plus_cst_src
= XEXP (links
, 0);
3350 /* Check that the first operand of the PLUS is a hard reg or
3351 the lowpart subreg of one. */
3354 rtx reg
= XEXP (plus_cst_src
, 0);
3355 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3356 reg
= SUBREG_REG (reg
);
3358 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3364 rtx reg
= XEXP (plus_cst_src
, 0);
3365 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3367 if (GET_CODE (reg
) == SUBREG
)
3368 reg
= SUBREG_REG (reg
);
3370 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3371 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3373 rtx to_rtx
= ep
->to_rtx
;
3374 offset
+= ep
->offset
;
3375 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3377 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3378 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3380 /* If we have a nonzero offset, and the source is already
3381 a simple REG, the following transformation would
3382 increase the cost of the insn by replacing a simple REG
3383 with (plus (reg sp) CST). So try only when we already
3384 had a PLUS before. */
3385 if (offset
== 0 || plus_src
)
3387 rtx new_src
= plus_constant (to_rtx
, offset
);
3389 new_body
= old_body
;
3392 new_body
= copy_insn (old_body
);
3393 if (REG_NOTES (insn
))
3394 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3396 PATTERN (insn
) = new_body
;
3397 old_set
= single_set (insn
);
3399 /* First see if this insn remains valid when we make the
3400 change. If not, try to replace the whole pattern with
3401 a simple set (this may help if the original insn was a
3402 PARALLEL that was only recognized as single_set due to
3403 REG_UNUSED notes). If this isn't valid either, keep
3404 the INSN_CODE the same and let reload fix it up. */
3405 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3407 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3408 SET_DEST (old_set
), new_src
);
3410 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3411 SET_SRC (old_set
) = new_src
;
3418 /* This can't have an effect on elimination offsets, so skip right
3424 /* Determine the effects of this insn on elimination offsets. */
3425 elimination_effects (old_body
, VOIDmode
);
3427 /* Eliminate all eliminable registers occurring in operands that
3428 can be handled by reload. */
3429 extract_insn (insn
);
3430 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3432 orig_operand
[i
] = recog_data
.operand
[i
];
3433 substed_operand
[i
] = recog_data
.operand
[i
];
3435 /* For an asm statement, every operand is eliminable. */
3436 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3438 bool is_set_src
, in_plus
;
3440 /* Check for setting a register that we know about. */
3441 if (recog_data
.operand_type
[i
] != OP_IN
3442 && REG_P (orig_operand
[i
]))
3444 /* If we are assigning to a register that can be eliminated, it
3445 must be as part of a PARALLEL, since the code above handles
3446 single SETs. We must indicate that we can no longer
3447 eliminate this reg. */
3448 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3450 if (ep
->from_rtx
== orig_operand
[i
])
3451 ep
->can_eliminate
= 0;
3454 /* Companion to the above plus substitution, we can allow
3455 invariants as the source of a plain move. */
3458 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3462 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3463 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3467 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3468 replace
? insn
: NULL_RTX
,
3469 is_set_src
|| in_plus
, false);
3470 if (substed_operand
[i
] != orig_operand
[i
])
3472 /* Terminate the search in check_eliminable_occurrences at
3474 *recog_data
.operand_loc
[i
] = 0;
3476 /* If an output operand changed from a REG to a MEM and INSN is an
3477 insn, write a CLOBBER insn. */
3478 if (recog_data
.operand_type
[i
] != OP_IN
3479 && REG_P (orig_operand
[i
])
3480 && MEM_P (substed_operand
[i
])
3482 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3486 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3487 *recog_data
.dup_loc
[i
]
3488 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3490 /* If any eliminable remain, they aren't eliminable anymore. */
3491 check_eliminable_occurrences (old_body
);
3493 /* Substitute the operands; the new values are in the substed_operand
3495 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3496 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3497 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3498 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3500 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3501 re-recognize the insn. We do this in case we had a simple addition
3502 but now can do this as a load-address. This saves an insn in this
3504 If re-recognition fails, the old insn code number will still be used,
3505 and some register operands may have changed into PLUS expressions.
3506 These will be handled by find_reloads by loading them into a register
3511 /* If we aren't replacing things permanently and we changed something,
3512 make another copy to ensure that all the RTL is new. Otherwise
3513 things can go wrong if find_reload swaps commutative operands
3514 and one is inside RTL that has been copied while the other is not. */
3515 new_body
= old_body
;
3518 new_body
= copy_insn (old_body
);
3519 if (REG_NOTES (insn
))
3520 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3522 PATTERN (insn
) = new_body
;
3524 /* If we had a move insn but now we don't, rerecognize it. This will
3525 cause spurious re-recognition if the old move had a PARALLEL since
3526 the new one still will, but we can't call single_set without
3527 having put NEW_BODY into the insn and the re-recognition won't
3528 hurt in this rare case. */
3529 /* ??? Why this huge if statement - why don't we just rerecognize the
3533 && ((REG_P (SET_SRC (old_set
))
3534 && (GET_CODE (new_body
) != SET
3535 || !REG_P (SET_SRC (new_body
))))
3536 /* If this was a load from or store to memory, compare
3537 the MEM in recog_data.operand to the one in the insn.
3538 If they are not equal, then rerecognize the insn. */
3540 && ((MEM_P (SET_SRC (old_set
))
3541 && SET_SRC (old_set
) != recog_data
.operand
[1])
3542 || (MEM_P (SET_DEST (old_set
))
3543 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3544 /* If this was an add insn before, rerecognize. */
3545 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3547 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3549 INSN_CODE (insn
) = new_icode
;
3553 /* Restore the old body. If there were any changes to it, we made a copy
3554 of it while the changes were still in place, so we'll correctly return
3555 a modified insn below. */
3558 /* Restore the old body. */
3559 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3560 /* Restoring a top-level match_parallel would clobber the new_body
3561 we installed in the insn. */
3562 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3563 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3564 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3565 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3568 /* Update all elimination pairs to reflect the status after the current
3569 insn. The changes we make were determined by the earlier call to
3570 elimination_effects.
3572 We also detect cases where register elimination cannot be done,
3573 namely, if a register would be both changed and referenced outside a MEM
3574 in the resulting insn since such an insn is often undefined and, even if
3575 not, we cannot know what meaning will be given to it. Note that it is
3576 valid to have a register used in an address in an insn that changes it
3577 (presumably with a pre- or post-increment or decrement).
3579 If anything changes, return nonzero. */
3581 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3583 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3584 ep
->can_eliminate
= 0;
3586 ep
->ref_outside_mem
= 0;
3588 if (ep
->previous_offset
!= ep
->offset
)
3593 /* If we changed something, perform elimination in REG_NOTES. This is
3594 needed even when REPLACE is zero because a REG_DEAD note might refer
3595 to a register that we eliminate and could cause a different number
3596 of spill registers to be needed in the final reload pass than in
3598 if (val
&& REG_NOTES (insn
) != 0)
3600 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3606 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3607 register allocator. INSN is the instruction we need to examine, we perform
3608 eliminations in its operands and record cases where eliminating a reg with
3609 an invariant equivalence would add extra cost. */
3612 elimination_costs_in_insn (rtx insn
)
3614 int icode
= recog_memoized (insn
);
3615 rtx old_body
= PATTERN (insn
);
3616 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3617 rtx old_set
= single_set (insn
);
3619 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3620 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3621 struct elim_table
*ep
;
3622 rtx plus_src
, plus_cst_src
;
3625 if (! insn_is_asm
&& icode
< 0)
3627 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3628 || GET_CODE (PATTERN (insn
)) == CLOBBER
3629 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3630 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3631 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3632 || DEBUG_INSN_P (insn
));
3636 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3637 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3639 /* Check for setting an eliminable register. */
3640 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3641 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3645 /* We allow one special case which happens to work on all machines we
3646 currently support: a single set with the source or a REG_EQUAL
3647 note being a PLUS of an eliminable register and a constant. */
3648 plus_src
= plus_cst_src
= 0;
3650 if (old_set
&& REG_P (SET_DEST (old_set
)))
3653 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3654 plus_src
= SET_SRC (old_set
);
3655 /* First see if the source is of the form (plus (...) CST). */
3657 && CONST_INT_P (XEXP (plus_src
, 1)))
3658 plus_cst_src
= plus_src
;
3659 else if (REG_P (SET_SRC (old_set
))
3662 /* Otherwise, see if we have a REG_EQUAL note of the form
3663 (plus (...) CST). */
3665 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3667 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3668 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3669 && GET_CODE (XEXP (links
, 0)) == PLUS
3670 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3672 plus_cst_src
= XEXP (links
, 0);
3679 /* Determine the effects of this insn on elimination offsets. */
3680 elimination_effects (old_body
, VOIDmode
);
3682 /* Eliminate all eliminable registers occurring in operands that
3683 can be handled by reload. */
3684 extract_insn (insn
);
3685 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3686 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3688 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3690 orig_operand
[i
] = recog_data
.operand
[i
];
3692 /* For an asm statement, every operand is eliminable. */
3693 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3695 bool is_set_src
, in_plus
;
3697 /* Check for setting a register that we know about. */
3698 if (recog_data
.operand_type
[i
] != OP_IN
3699 && REG_P (orig_operand
[i
]))
3701 /* If we are assigning to a register that can be eliminated, it
3702 must be as part of a PARALLEL, since the code above handles
3703 single SETs. We must indicate that we can no longer
3704 eliminate this reg. */
3705 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3707 if (ep
->from_rtx
== orig_operand
[i
])
3708 ep
->can_eliminate
= 0;
3711 /* Companion to the above plus substitution, we can allow
3712 invariants as the source of a plain move. */
3714 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3716 if (is_set_src
&& !sets_reg_p
)
3717 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3719 if (plus_src
&& sets_reg_p
3720 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3721 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3724 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3726 is_set_src
|| in_plus
, true);
3727 /* Terminate the search in check_eliminable_occurrences at
3729 *recog_data
.operand_loc
[i
] = 0;
3733 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3734 *recog_data
.dup_loc
[i
]
3735 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3737 /* If any eliminable remain, they aren't eliminable anymore. */
3738 check_eliminable_occurrences (old_body
);
3740 /* Restore the old body. */
3741 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3742 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3743 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3744 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3746 /* Update all elimination pairs to reflect the status after the current
3747 insn. The changes we make were determined by the earlier call to
3748 elimination_effects. */
3750 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3752 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3753 ep
->can_eliminate
= 0;
3755 ep
->ref_outside_mem
= 0;
3761 /* Loop through all elimination pairs.
3762 Recalculate the number not at initial offset.
3764 Compute the maximum offset (minimum offset if the stack does not
3765 grow downward) for each elimination pair. */
3768 update_eliminable_offsets (void)
3770 struct elim_table
*ep
;
3772 num_not_at_initial_offset
= 0;
3773 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3775 ep
->previous_offset
= ep
->offset
;
3776 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3777 num_not_at_initial_offset
++;
3781 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3782 replacement we currently believe is valid, mark it as not eliminable if X
3783 modifies DEST in any way other than by adding a constant integer to it.
3785 If DEST is the frame pointer, we do nothing because we assume that
3786 all assignments to the hard frame pointer are nonlocal gotos and are being
3787 done at a time when they are valid and do not disturb anything else.
3788 Some machines want to eliminate a fake argument pointer with either the
3789 frame or stack pointer. Assignments to the hard frame pointer must not
3790 prevent this elimination.
3792 Called via note_stores from reload before starting its passes to scan
3793 the insns of the function. */
3796 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3800 /* A SUBREG of a hard register here is just changing its mode. We should
3801 not see a SUBREG of an eliminable hard register, but check just in
3803 if (GET_CODE (dest
) == SUBREG
)
3804 dest
= SUBREG_REG (dest
);
3806 if (dest
== hard_frame_pointer_rtx
)
3809 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3810 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3811 && (GET_CODE (x
) != SET
3812 || GET_CODE (SET_SRC (x
)) != PLUS
3813 || XEXP (SET_SRC (x
), 0) != dest
3814 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3816 reg_eliminate
[i
].can_eliminate_previous
3817 = reg_eliminate
[i
].can_eliminate
= 0;
3822 /* Verify that the initial elimination offsets did not change since the
3823 last call to set_initial_elim_offsets. This is used to catch cases
3824 where something illegal happened during reload_as_needed that could
3825 cause incorrect code to be generated if we did not check for it. */
3828 verify_initial_elim_offsets (void)
3832 if (!num_eliminable
)
3835 #ifdef ELIMINABLE_REGS
3837 struct elim_table
*ep
;
3839 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3841 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3842 if (t
!= ep
->initial_offset
)
3847 INITIAL_FRAME_POINTER_OFFSET (t
);
3848 if (t
!= reg_eliminate
[0].initial_offset
)
3855 /* Reset all offsets on eliminable registers to their initial values. */
3858 set_initial_elim_offsets (void)
3860 struct elim_table
*ep
= reg_eliminate
;
3862 #ifdef ELIMINABLE_REGS
3863 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3865 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3866 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3869 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3870 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3873 num_not_at_initial_offset
= 0;
3876 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3879 set_initial_eh_label_offset (rtx label
)
3881 set_label_offsets (label
, NULL_RTX
, 1);
3884 /* Initialize the known label offsets.
3885 Set a known offset for each forced label to be at the initial offset
3886 of each elimination. We do this because we assume that all
3887 computed jumps occur from a location where each elimination is
3888 at its initial offset.
3889 For all other labels, show that we don't know the offsets. */
3892 set_initial_label_offsets (void)
3895 memset (offsets_known_at
, 0, num_labels
);
3897 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3899 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3901 for_each_eh_label (set_initial_eh_label_offset
);
3904 /* Set all elimination offsets to the known values for the code label given
3908 set_offsets_for_label (rtx insn
)
3911 int label_nr
= CODE_LABEL_NUMBER (insn
);
3912 struct elim_table
*ep
;
3914 num_not_at_initial_offset
= 0;
3915 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3917 ep
->offset
= ep
->previous_offset
3918 = offsets_at
[label_nr
- first_label_num
][i
];
3919 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3920 num_not_at_initial_offset
++;
3924 /* See if anything that happened changes which eliminations are valid.
3925 For example, on the SPARC, whether or not the frame pointer can
3926 be eliminated can depend on what registers have been used. We need
3927 not check some conditions again (such as flag_omit_frame_pointer)
3928 since they can't have changed. */
3931 update_eliminables (HARD_REG_SET
*pset
)
3933 int previous_frame_pointer_needed
= frame_pointer_needed
;
3934 struct elim_table
*ep
;
3936 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3937 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3938 && targetm
.frame_pointer_required ())
3939 #ifdef ELIMINABLE_REGS
3940 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3943 ep
->can_eliminate
= 0;
3945 /* Look for the case where we have discovered that we can't replace
3946 register A with register B and that means that we will now be
3947 trying to replace register A with register C. This means we can
3948 no longer replace register C with register B and we need to disable
3949 such an elimination, if it exists. This occurs often with A == ap,
3950 B == sp, and C == fp. */
3952 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3954 struct elim_table
*op
;
3957 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3959 /* Find the current elimination for ep->from, if there is a
3961 for (op
= reg_eliminate
;
3962 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3963 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3969 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3971 for (op
= reg_eliminate
;
3972 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3973 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3974 op
->can_eliminate
= 0;
3978 /* See if any registers that we thought we could eliminate the previous
3979 time are no longer eliminable. If so, something has changed and we
3980 must spill the register. Also, recompute the number of eliminable
3981 registers and see if the frame pointer is needed; it is if there is
3982 no elimination of the frame pointer that we can perform. */
3984 frame_pointer_needed
= 1;
3985 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3987 if (ep
->can_eliminate
3988 && ep
->from
== FRAME_POINTER_REGNUM
3989 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3990 && (! SUPPORTS_STACK_ALIGNMENT
3991 || ! crtl
->stack_realign_needed
))
3992 frame_pointer_needed
= 0;
3994 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3996 ep
->can_eliminate_previous
= 0;
3997 SET_HARD_REG_BIT (*pset
, ep
->from
);
4002 /* If we didn't need a frame pointer last time, but we do now, spill
4003 the hard frame pointer. */
4004 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4005 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4008 /* Return true if X is used as the target register of an elimination. */
4011 elimination_target_reg_p (rtx x
)
4013 struct elim_table
*ep
;
4015 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4016 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4022 /* Initialize the table of registers to eliminate.
4023 Pre-condition: global flag frame_pointer_needed has been set before
4024 calling this function. */
4027 init_elim_table (void)
4029 struct elim_table
*ep
;
4030 #ifdef ELIMINABLE_REGS
4031 const struct elim_table_1
*ep1
;
4035 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4039 #ifdef ELIMINABLE_REGS
4040 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4041 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4043 ep
->from
= ep1
->from
;
4045 ep
->can_eliminate
= ep
->can_eliminate_previous
4046 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4047 && ! (ep
->to
== STACK_POINTER_REGNUM
4048 && frame_pointer_needed
4049 && (! SUPPORTS_STACK_ALIGNMENT
4050 || ! stack_realign_fp
)));
4053 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4054 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4055 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4056 = ! frame_pointer_needed
;
4059 /* Count the number of eliminable registers and build the FROM and TO
4060 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4061 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4062 We depend on this. */
4063 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4065 num_eliminable
+= ep
->can_eliminate
;
4066 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4067 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4071 /* Find all the pseudo registers that didn't get hard regs
4072 but do have known equivalent constants or memory slots.
4073 These include parameters (known equivalent to parameter slots)
4074 and cse'd or loop-moved constant memory addresses.
4076 Record constant equivalents in reg_equiv_constant
4077 so they will be substituted by find_reloads.
4078 Record memory equivalents in reg_mem_equiv so they can
4079 be substituted eventually by altering the REG-rtx's. */
4082 init_eliminable_invariants (rtx first
, bool do_subregs
)
4087 reg_equiv_constant
= XCNEWVEC (rtx
, max_regno
);
4088 reg_equiv_invariant
= XCNEWVEC (rtx
, max_regno
);
4089 reg_equiv_mem
= XCNEWVEC (rtx
, max_regno
);
4090 reg_equiv_alt_mem_list
= XCNEWVEC (rtx
, max_regno
);
4091 reg_equiv_address
= XCNEWVEC (rtx
, max_regno
);
4093 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4095 reg_max_ref_width
= NULL
;
4097 num_eliminable_invariants
= 0;
4099 first_label_num
= get_first_label_num ();
4100 num_labels
= max_label_num () - first_label_num
;
4102 /* Allocate the tables used to store offset information at labels. */
4103 offsets_known_at
= XNEWVEC (char, num_labels
);
4104 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4106 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4107 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4108 find largest such for each pseudo. FIRST is the head of the insn
4111 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4113 rtx set
= single_set (insn
);
4115 /* We may introduce USEs that we want to remove at the end, so
4116 we'll mark them with QImode. Make sure there are no
4117 previously-marked insns left by say regmove. */
4118 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4119 && GET_MODE (insn
) != VOIDmode
)
4120 PUT_MODE (insn
, VOIDmode
);
4122 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4123 scan_paradoxical_subregs (PATTERN (insn
));
4125 if (set
!= 0 && REG_P (SET_DEST (set
)))
4127 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4133 i
= REGNO (SET_DEST (set
));
4136 if (i
<= LAST_VIRTUAL_REGISTER
)
4139 /* If flag_pic and we have constant, verify it's legitimate. */
4141 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4143 /* It can happen that a REG_EQUIV note contains a MEM
4144 that is not a legitimate memory operand. As later
4145 stages of reload assume that all addresses found
4146 in the reg_equiv_* arrays were originally legitimate,
4147 we ignore such REG_EQUIV notes. */
4148 if (memory_operand (x
, VOIDmode
))
4150 /* Always unshare the equivalence, so we can
4151 substitute into this insn without touching the
4153 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
4155 else if (function_invariant_p (x
))
4157 if (GET_CODE (x
) == PLUS
)
4159 /* This is PLUS of frame pointer and a constant,
4160 and might be shared. Unshare it. */
4161 reg_equiv_invariant
[i
] = copy_rtx (x
);
4162 num_eliminable_invariants
++;
4164 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4166 reg_equiv_invariant
[i
] = x
;
4167 num_eliminable_invariants
++;
4169 else if (LEGITIMATE_CONSTANT_P (x
))
4170 reg_equiv_constant
[i
] = x
;
4173 reg_equiv_memory_loc
[i
]
4174 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
4175 if (! reg_equiv_memory_loc
[i
])
4176 reg_equiv_init
[i
] = NULL_RTX
;
4181 reg_equiv_init
[i
] = NULL_RTX
;
4186 reg_equiv_init
[i
] = NULL_RTX
;
4191 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4192 if (reg_equiv_init
[i
])
4194 fprintf (dump_file
, "init_insns for %u: ", i
);
4195 print_inline_rtx (dump_file
, reg_equiv_init
[i
], 20);
4196 fprintf (dump_file
, "\n");
4200 /* Indicate that we no longer have known memory locations or constants.
4201 Free all data involved in tracking these. */
4204 free_reg_equiv (void)
4208 if (reg_equiv_constant
)
4209 free (reg_equiv_constant
);
4210 if (reg_equiv_invariant
)
4211 free (reg_equiv_invariant
);
4212 reg_equiv_constant
= 0;
4213 reg_equiv_invariant
= 0;
4214 VEC_free (rtx
, gc
, reg_equiv_memory_loc_vec
);
4215 reg_equiv_memory_loc
= 0;
4217 if (offsets_known_at
)
4218 free (offsets_known_at
);
4222 offsets_known_at
= 0;
4224 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4225 if (reg_equiv_alt_mem_list
[i
])
4226 free_EXPR_LIST_list (®_equiv_alt_mem_list
[i
]);
4227 free (reg_equiv_alt_mem_list
);
4229 free (reg_equiv_mem
);
4230 free (reg_equiv_address
);
4233 /* Kick all pseudos out of hard register REGNO.
4235 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4236 because we found we can't eliminate some register. In the case, no pseudos
4237 are allowed to be in the register, even if they are only in a block that
4238 doesn't require spill registers, unlike the case when we are spilling this
4239 hard reg to produce another spill register.
4241 Return nonzero if any pseudos needed to be kicked out. */
4244 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4250 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4251 df_set_regs_ever_live (regno
, true);
4254 /* Spill every pseudo reg that was allocated to this reg
4255 or to something that overlaps this reg. */
4257 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4258 if (reg_renumber
[i
] >= 0
4259 && (unsigned int) reg_renumber
[i
] <= regno
4260 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4261 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4264 /* After find_reload_regs has been run for all insn that need reloads,
4265 and/or spill_hard_regs was called, this function is used to actually
4266 spill pseudo registers and try to reallocate them. It also sets up the
4267 spill_regs array for use by choose_reload_regs. */
4270 finish_spills (int global
)
4272 struct insn_chain
*chain
;
4273 int something_changed
= 0;
4275 reg_set_iterator rsi
;
4277 /* Build the spill_regs array for the function. */
4278 /* If there are some registers still to eliminate and one of the spill regs
4279 wasn't ever used before, additional stack space may have to be
4280 allocated to store this register. Thus, we may have changed the offset
4281 between the stack and frame pointers, so mark that something has changed.
4283 One might think that we need only set VAL to 1 if this is a call-used
4284 register. However, the set of registers that must be saved by the
4285 prologue is not identical to the call-used set. For example, the
4286 register used by the call insn for the return PC is a call-used register,
4287 but must be saved by the prologue. */
4290 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4291 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4293 spill_reg_order
[i
] = n_spills
;
4294 spill_regs
[n_spills
++] = i
;
4295 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4296 something_changed
= 1;
4297 df_set_regs_ever_live (i
, true);
4300 spill_reg_order
[i
] = -1;
4302 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4303 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4305 /* Record the current hard register the pseudo is allocated to
4306 in pseudo_previous_regs so we avoid reallocating it to the
4307 same hard reg in a later pass. */
4308 gcc_assert (reg_renumber
[i
] >= 0);
4310 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4311 /* Mark it as no longer having a hard register home. */
4312 reg_renumber
[i
] = -1;
4313 if (ira_conflicts_p
)
4314 /* Inform IRA about the change. */
4315 ira_mark_allocation_change (i
);
4316 /* We will need to scan everything again. */
4317 something_changed
= 1;
4320 /* Retry global register allocation if possible. */
4321 if (global
&& ira_conflicts_p
)
4325 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4326 /* For every insn that needs reloads, set the registers used as spill
4327 regs in pseudo_forbidden_regs for every pseudo live across the
4329 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4331 EXECUTE_IF_SET_IN_REG_SET
4332 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4334 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4335 chain
->used_spill_regs
);
4337 EXECUTE_IF_SET_IN_REG_SET
4338 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4340 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4341 chain
->used_spill_regs
);
4345 /* Retry allocating the pseudos spilled in IRA and the
4346 reload. For each reg, merge the various reg sets that
4347 indicate which hard regs can't be used, and call
4348 ira_reassign_pseudos. */
4349 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4350 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4352 if (reg_renumber
[i
] < 0)
4353 temp_pseudo_reg_arr
[n
++] = i
;
4355 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4357 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4358 bad_spill_regs_global
,
4359 pseudo_forbidden_regs
, pseudo_previous_regs
,
4361 something_changed
= 1;
4363 /* Fix up the register information in the insn chain.
4364 This involves deleting those of the spilled pseudos which did not get
4365 a new hard register home from the live_{before,after} sets. */
4366 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4368 HARD_REG_SET used_by_pseudos
;
4369 HARD_REG_SET used_by_pseudos2
;
4371 if (! ira_conflicts_p
)
4373 /* Don't do it for IRA because IRA and the reload still can
4374 assign hard registers to the spilled pseudos on next
4375 reload iterations. */
4376 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4377 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4379 /* Mark any unallocated hard regs as available for spills. That
4380 makes inheritance work somewhat better. */
4381 if (chain
->need_reload
)
4383 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4384 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4385 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4387 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4388 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4389 /* Value of chain->used_spill_regs from previous iteration
4390 may be not included in the value calculated here because
4391 of possible removing caller-saves insns (see function
4392 delete_caller_save_insns. */
4393 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4394 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4398 CLEAR_REG_SET (&changed_allocation_pseudos
);
4399 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4400 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4402 int regno
= reg_renumber
[i
];
4403 if (reg_old_renumber
[i
] == regno
)
4406 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4408 alter_reg (i
, reg_old_renumber
[i
], false);
4409 reg_old_renumber
[i
] = regno
;
4413 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4415 fprintf (dump_file
, " Register %d now in %d.\n\n",
4416 i
, reg_renumber
[i
]);
4420 return something_changed
;
4423 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4426 scan_paradoxical_subregs (rtx x
)
4430 enum rtx_code code
= GET_CODE (x
);
4441 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
4449 if (REG_P (SUBREG_REG (x
))
4450 && (GET_MODE_SIZE (GET_MODE (x
))
4451 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4453 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4454 = GET_MODE_SIZE (GET_MODE (x
));
4455 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4463 fmt
= GET_RTX_FORMAT (code
);
4464 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4467 scan_paradoxical_subregs (XEXP (x
, i
));
4468 else if (fmt
[i
] == 'E')
4471 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4472 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4477 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4478 examine all of the reload insns between PREV and NEXT exclusive, and
4479 annotate all that may trap. */
4482 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4484 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4487 if (!insn_could_throw_p (insn
))
4488 remove_note (insn
, note
);
4489 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4492 /* Reload pseudo-registers into hard regs around each insn as needed.
4493 Additional register load insns are output before the insn that needs it
4494 and perhaps store insns after insns that modify the reloaded pseudo reg.
4496 reg_last_reload_reg and reg_reloaded_contents keep track of
4497 which registers are already available in reload registers.
4498 We update these for the reloads that we perform,
4499 as the insns are scanned. */
4502 reload_as_needed (int live_known
)
4504 struct insn_chain
*chain
;
4505 #if defined (AUTO_INC_DEC)
4510 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4511 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4512 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4513 INIT_REG_SET (®_has_output_reload
);
4514 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4515 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4517 set_initial_elim_offsets ();
4519 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4522 rtx insn
= chain
->insn
;
4523 rtx old_next
= NEXT_INSN (insn
);
4525 rtx old_prev
= PREV_INSN (insn
);
4528 /* If we pass a label, copy the offsets from the label information
4529 into the current offsets of each elimination. */
4531 set_offsets_for_label (insn
);
4533 else if (INSN_P (insn
))
4535 regset_head regs_to_forget
;
4536 INIT_REG_SET (®s_to_forget
);
4537 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4539 /* If this is a USE and CLOBBER of a MEM, ensure that any
4540 references to eliminable registers have been removed. */
4542 if ((GET_CODE (PATTERN (insn
)) == USE
4543 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4544 && MEM_P (XEXP (PATTERN (insn
), 0)))
4545 XEXP (XEXP (PATTERN (insn
), 0), 0)
4546 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4547 GET_MODE (XEXP (PATTERN (insn
), 0)),
4550 /* If we need to do register elimination processing, do so.
4551 This might delete the insn, in which case we are done. */
4552 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4554 eliminate_regs_in_insn (insn
, 1);
4557 update_eliminable_offsets ();
4558 CLEAR_REG_SET (®s_to_forget
);
4563 /* If need_elim is nonzero but need_reload is zero, one might think
4564 that we could simply set n_reloads to 0. However, find_reloads
4565 could have done some manipulation of the insn (such as swapping
4566 commutative operands), and these manipulations are lost during
4567 the first pass for every insn that needs register elimination.
4568 So the actions of find_reloads must be redone here. */
4570 if (! chain
->need_elim
&& ! chain
->need_reload
4571 && ! chain
->need_operand_change
)
4573 /* First find the pseudo regs that must be reloaded for this insn.
4574 This info is returned in the tables reload_... (see reload.h).
4575 Also modify the body of INSN by substituting RELOAD
4576 rtx's for those pseudo regs. */
4579 CLEAR_REG_SET (®_has_output_reload
);
4580 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4582 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4588 rtx next
= NEXT_INSN (insn
);
4591 prev
= PREV_INSN (insn
);
4593 /* Now compute which reload regs to reload them into. Perhaps
4594 reusing reload regs from previous insns, or else output
4595 load insns to reload them. Maybe output store insns too.
4596 Record the choices of reload reg in reload_reg_rtx. */
4597 choose_reload_regs (chain
);
4599 /* Merge any reloads that we didn't combine for fear of
4600 increasing the number of spill registers needed but now
4601 discover can be safely merged. */
4602 if (targetm
.small_register_classes_for_mode_p (VOIDmode
))
4603 merge_assigned_reloads (insn
);
4605 /* Generate the insns to reload operands into or out of
4606 their reload regs. */
4607 emit_reload_insns (chain
);
4609 /* Substitute the chosen reload regs from reload_reg_rtx
4610 into the insn's body (or perhaps into the bodies of other
4611 load and store insn that we just made for reloading
4612 and that we moved the structure into). */
4613 subst_reloads (insn
);
4615 /* Adjust the exception region notes for loads and stores. */
4616 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4617 fixup_eh_region_note (insn
, prev
, next
);
4619 /* If this was an ASM, make sure that all the reload insns
4620 we have generated are valid. If not, give an error
4622 if (asm_noperands (PATTERN (insn
)) >= 0)
4623 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4624 if (p
!= insn
&& INSN_P (p
)
4625 && GET_CODE (PATTERN (p
)) != USE
4626 && (recog_memoized (p
) < 0
4627 || (extract_insn (p
), ! constrain_operands (1))))
4629 error_for_asm (insn
,
4630 "%<asm%> operand requires "
4631 "impossible reload");
4636 if (num_eliminable
&& chain
->need_elim
)
4637 update_eliminable_offsets ();
4639 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4640 is no longer validly lying around to save a future reload.
4641 Note that this does not detect pseudos that were reloaded
4642 for this insn in order to be stored in
4643 (obeying register constraints). That is correct; such reload
4644 registers ARE still valid. */
4645 forget_marked_reloads (®s_to_forget
);
4646 CLEAR_REG_SET (®s_to_forget
);
4648 /* There may have been CLOBBER insns placed after INSN. So scan
4649 between INSN and NEXT and use them to forget old reloads. */
4650 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4651 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4652 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4655 /* Likewise for regs altered by auto-increment in this insn.
4656 REG_INC notes have been changed by reloading:
4657 find_reloads_address_1 records substitutions for them,
4658 which have been performed by subst_reloads above. */
4659 for (i
= n_reloads
- 1; i
>= 0; i
--)
4661 rtx in_reg
= rld
[i
].in_reg
;
4664 enum rtx_code code
= GET_CODE (in_reg
);
4665 /* PRE_INC / PRE_DEC will have the reload register ending up
4666 with the same value as the stack slot, but that doesn't
4667 hold true for POST_INC / POST_DEC. Either we have to
4668 convert the memory access to a true POST_INC / POST_DEC,
4669 or we can't use the reload register for inheritance. */
4670 if ((code
== POST_INC
|| code
== POST_DEC
)
4671 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4672 REGNO (rld
[i
].reg_rtx
))
4673 /* Make sure it is the inc/dec pseudo, and not
4674 some other (e.g. output operand) pseudo. */
4675 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4676 == REGNO (XEXP (in_reg
, 0))))
4679 rtx reload_reg
= rld
[i
].reg_rtx
;
4680 enum machine_mode mode
= GET_MODE (reload_reg
);
4684 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4686 /* We really want to ignore REG_INC notes here, so
4687 use PATTERN (p) as argument to reg_set_p . */
4688 if (reg_set_p (reload_reg
, PATTERN (p
)))
4690 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4696 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4698 validate_replace_rtx_group (reload_reg
,
4700 n
= verify_changes (0);
4702 /* We must also verify that the constraints
4703 are met after the replacement. Make sure
4704 extract_insn is only called for an insn
4705 where the replacements were found to be
4710 n
= constrain_operands (1);
4713 /* If the constraints were not met, then
4714 undo the replacement, else confirm it. */
4718 confirm_change_group ();
4724 add_reg_note (p
, REG_INC
, reload_reg
);
4725 /* Mark this as having an output reload so that the
4726 REG_INC processing code below won't invalidate
4727 the reload for inheritance. */
4728 SET_HARD_REG_BIT (reg_is_output_reload
,
4729 REGNO (reload_reg
));
4730 SET_REGNO_REG_SET (®_has_output_reload
,
4731 REGNO (XEXP (in_reg
, 0)));
4734 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4737 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4738 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4739 REGNO (rld
[i
].reg_rtx
))
4740 /* Make sure it is the inc/dec pseudo, and not
4741 some other (e.g. output operand) pseudo. */
4742 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4743 == REGNO (XEXP (in_reg
, 0))))
4745 SET_HARD_REG_BIT (reg_is_output_reload
,
4746 REGNO (rld
[i
].reg_rtx
));
4747 SET_REGNO_REG_SET (®_has_output_reload
,
4748 REGNO (XEXP (in_reg
, 0)));
4750 else if (code
== PRE_INC
|| code
== PRE_DEC
4751 || code
== POST_INC
|| code
== POST_DEC
)
4753 int in_regno
= REGNO (XEXP (in_reg
, 0));
4755 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4758 bool forget_p
= true;
4760 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4761 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4764 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4767 if (x
== reg_reloaded_insn
[in_hard_regno
])
4773 /* If for some reasons, we didn't set up
4774 reg_last_reload_reg in this insn,
4775 invalidate inheritance from previous
4776 insns for the incremented/decremented
4777 register. Such registers will be not in
4778 reg_has_output_reload. Invalidate it
4779 also if the corresponding element in
4780 reg_reloaded_insn is also
4783 forget_old_reloads_1 (XEXP (in_reg
, 0),
4789 /* If a pseudo that got a hard register is auto-incremented,
4790 we must purge records of copying it into pseudos without
4792 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4793 if (REG_NOTE_KIND (x
) == REG_INC
)
4795 /* See if this pseudo reg was reloaded in this insn.
4796 If so, its last-reload info is still valid
4797 because it is based on this insn's reload. */
4798 for (i
= 0; i
< n_reloads
; i
++)
4799 if (rld
[i
].out
== XEXP (x
, 0))
4803 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4807 /* A reload reg's contents are unknown after a label. */
4809 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4811 /* Don't assume a reload reg is still good after a call insn
4812 if it is a call-used reg, or if it contains a value that will
4813 be partially clobbered by the call. */
4814 else if (CALL_P (insn
))
4816 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4817 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4822 free (reg_last_reload_reg
);
4823 CLEAR_REG_SET (®_has_output_reload
);
4826 /* Discard all record of any value reloaded from X,
4827 or reloaded in X from someplace else;
4828 unless X is an output reload reg of the current insn.
4830 X may be a hard reg (the reload reg)
4831 or it may be a pseudo reg that was reloaded from.
4833 When DATA is non-NULL just mark the registers in regset
4834 to be forgotten later. */
4837 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4842 regset regs
= (regset
) data
;
4844 /* note_stores does give us subregs of hard regs,
4845 subreg_regno_offset requires a hard reg. */
4846 while (GET_CODE (x
) == SUBREG
)
4848 /* We ignore the subreg offset when calculating the regno,
4849 because we are using the entire underlying hard register
4859 if (regno
>= FIRST_PSEUDO_REGISTER
)
4865 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4866 /* Storing into a spilled-reg invalidates its contents.
4867 This can happen if a block-local pseudo is allocated to that reg
4868 and it wasn't spilled because this block's total need is 0.
4869 Then some insn might have an optional reload and use this reg. */
4871 for (i
= 0; i
< nr
; i
++)
4872 /* But don't do this if the reg actually serves as an output
4873 reload reg in the current instruction. */
4875 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4877 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4878 spill_reg_store
[regno
+ i
] = 0;
4884 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4887 /* Since value of X has changed,
4888 forget any value previously copied from it. */
4891 /* But don't forget a copy if this is the output reload
4892 that establishes the copy's validity. */
4894 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4895 reg_last_reload_reg
[regno
+ nr
] = 0;
4899 /* Forget the reloads marked in regset by previous function. */
4901 forget_marked_reloads (regset regs
)
4904 reg_set_iterator rsi
;
4905 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4907 if (reg
< FIRST_PSEUDO_REGISTER
4908 /* But don't do this if the reg actually serves as an output
4909 reload reg in the current instruction. */
4911 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4913 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4914 spill_reg_store
[reg
] = 0;
4917 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4918 reg_last_reload_reg
[reg
] = 0;
4922 /* The following HARD_REG_SETs indicate when each hard register is
4923 used for a reload of various parts of the current insn. */
4925 /* If reg is unavailable for all reloads. */
4926 static HARD_REG_SET reload_reg_unavailable
;
4927 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4928 static HARD_REG_SET reload_reg_used
;
4929 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4930 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4931 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4932 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4933 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4934 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4935 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4936 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4937 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4938 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4939 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4940 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4941 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4942 static HARD_REG_SET reload_reg_used_in_op_addr
;
4943 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4944 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4945 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4946 static HARD_REG_SET reload_reg_used_in_insn
;
4947 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4948 static HARD_REG_SET reload_reg_used_in_other_addr
;
4950 /* If reg is in use as a reload reg for any sort of reload. */
4951 static HARD_REG_SET reload_reg_used_at_all
;
4953 /* If reg is use as an inherited reload. We just mark the first register
4955 static HARD_REG_SET reload_reg_used_for_inherit
;
4957 /* Records which hard regs are used in any way, either as explicit use or
4958 by being allocated to a pseudo during any point of the current insn. */
4959 static HARD_REG_SET reg_used_in_insn
;
4961 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4962 TYPE. MODE is used to indicate how many consecutive regs are
4966 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4967 enum machine_mode mode
)
4969 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4972 for (i
= regno
; i
< nregs
+ regno
; i
++)
4977 SET_HARD_REG_BIT (reload_reg_used
, i
);
4980 case RELOAD_FOR_INPUT_ADDRESS
:
4981 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4984 case RELOAD_FOR_INPADDR_ADDRESS
:
4985 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4988 case RELOAD_FOR_OUTPUT_ADDRESS
:
4989 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4992 case RELOAD_FOR_OUTADDR_ADDRESS
:
4993 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4996 case RELOAD_FOR_OPERAND_ADDRESS
:
4997 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
5000 case RELOAD_FOR_OPADDR_ADDR
:
5001 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
5004 case RELOAD_FOR_OTHER_ADDRESS
:
5005 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
5008 case RELOAD_FOR_INPUT
:
5009 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
5012 case RELOAD_FOR_OUTPUT
:
5013 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
5016 case RELOAD_FOR_INSN
:
5017 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
5021 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
5025 /* Similarly, but show REGNO is no longer in use for a reload. */
5028 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5029 enum reload_type type
, enum machine_mode mode
)
5031 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5032 unsigned int start_regno
, end_regno
, r
;
5034 /* A complication is that for some reload types, inheritance might
5035 allow multiple reloads of the same types to share a reload register.
5036 We set check_opnum if we have to check only reloads with the same
5037 operand number, and check_any if we have to check all reloads. */
5038 int check_opnum
= 0;
5040 HARD_REG_SET
*used_in_set
;
5045 used_in_set
= &reload_reg_used
;
5048 case RELOAD_FOR_INPUT_ADDRESS
:
5049 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5052 case RELOAD_FOR_INPADDR_ADDRESS
:
5054 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5057 case RELOAD_FOR_OUTPUT_ADDRESS
:
5058 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5061 case RELOAD_FOR_OUTADDR_ADDRESS
:
5063 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5066 case RELOAD_FOR_OPERAND_ADDRESS
:
5067 used_in_set
= &reload_reg_used_in_op_addr
;
5070 case RELOAD_FOR_OPADDR_ADDR
:
5072 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5075 case RELOAD_FOR_OTHER_ADDRESS
:
5076 used_in_set
= &reload_reg_used_in_other_addr
;
5080 case RELOAD_FOR_INPUT
:
5081 used_in_set
= &reload_reg_used_in_input
[opnum
];
5084 case RELOAD_FOR_OUTPUT
:
5085 used_in_set
= &reload_reg_used_in_output
[opnum
];
5088 case RELOAD_FOR_INSN
:
5089 used_in_set
= &reload_reg_used_in_insn
;
5094 /* We resolve conflicts with remaining reloads of the same type by
5095 excluding the intervals of reload registers by them from the
5096 interval of freed reload registers. Since we only keep track of
5097 one set of interval bounds, we might have to exclude somewhat
5098 more than what would be necessary if we used a HARD_REG_SET here.
5099 But this should only happen very infrequently, so there should
5100 be no reason to worry about it. */
5102 start_regno
= regno
;
5103 end_regno
= regno
+ nregs
;
5104 if (check_opnum
|| check_any
)
5106 for (i
= n_reloads
- 1; i
>= 0; i
--)
5108 if (rld
[i
].when_needed
== type
5109 && (check_any
|| rld
[i
].opnum
== opnum
)
5112 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5113 unsigned int conflict_end
5114 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5116 /* If there is an overlap with the first to-be-freed register,
5117 adjust the interval start. */
5118 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5119 start_regno
= conflict_end
;
5120 /* Otherwise, if there is a conflict with one of the other
5121 to-be-freed registers, adjust the interval end. */
5122 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5123 end_regno
= conflict_start
;
5128 for (r
= start_regno
; r
< end_regno
; r
++)
5129 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5132 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5133 specified by OPNUM and TYPE. */
5136 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5140 /* In use for a RELOAD_OTHER means it's not available for anything. */
5141 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5142 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5148 /* In use for anything means we can't use it for RELOAD_OTHER. */
5149 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5150 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5151 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5152 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5155 for (i
= 0; i
< reload_n_operands
; i
++)
5156 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5157 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5158 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5159 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5160 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5161 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5166 case RELOAD_FOR_INPUT
:
5167 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5168 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5171 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5174 /* If it is used for some other input, can't use it. */
5175 for (i
= 0; i
< reload_n_operands
; i
++)
5176 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5179 /* If it is used in a later operand's address, can't use it. */
5180 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5181 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5182 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5187 case RELOAD_FOR_INPUT_ADDRESS
:
5188 /* Can't use a register if it is used for an input address for this
5189 operand or used as an input in an earlier one. */
5190 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5191 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5194 for (i
= 0; i
< opnum
; i
++)
5195 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5200 case RELOAD_FOR_INPADDR_ADDRESS
:
5201 /* Can't use a register if it is used for an input address
5202 for this operand or used as an input in an earlier
5204 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5207 for (i
= 0; i
< opnum
; i
++)
5208 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5213 case RELOAD_FOR_OUTPUT_ADDRESS
:
5214 /* Can't use a register if it is used for an output address for this
5215 operand or used as an output in this or a later operand. Note
5216 that multiple output operands are emitted in reverse order, so
5217 the conflicting ones are those with lower indices. */
5218 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5221 for (i
= 0; i
<= opnum
; i
++)
5222 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5227 case RELOAD_FOR_OUTADDR_ADDRESS
:
5228 /* Can't use a register if it is used for an output address
5229 for this operand or used as an output in this or a
5230 later operand. Note that multiple output operands are
5231 emitted in reverse order, so the conflicting ones are
5232 those with lower indices. */
5233 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5236 for (i
= 0; i
<= opnum
; i
++)
5237 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5242 case RELOAD_FOR_OPERAND_ADDRESS
:
5243 for (i
= 0; i
< reload_n_operands
; i
++)
5244 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5247 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5248 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5250 case RELOAD_FOR_OPADDR_ADDR
:
5251 for (i
= 0; i
< reload_n_operands
; i
++)
5252 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5255 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5257 case RELOAD_FOR_OUTPUT
:
5258 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5259 outputs, or an operand address for this or an earlier output.
5260 Note that multiple output operands are emitted in reverse order,
5261 so the conflicting ones are those with higher indices. */
5262 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5265 for (i
= 0; i
< reload_n_operands
; i
++)
5266 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5269 for (i
= opnum
; i
< reload_n_operands
; i
++)
5270 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5271 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5276 case RELOAD_FOR_INSN
:
5277 for (i
= 0; i
< reload_n_operands
; i
++)
5278 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5279 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5282 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5283 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5285 case RELOAD_FOR_OTHER_ADDRESS
:
5286 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5293 /* Return 1 if the value in reload reg REGNO, as used by a reload
5294 needed for the part of the insn specified by OPNUM and TYPE,
5295 is still available in REGNO at the end of the insn.
5297 We can assume that the reload reg was already tested for availability
5298 at the time it is needed, and we should not check this again,
5299 in case the reg has already been marked in use. */
5302 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
5309 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5310 its value must reach the end. */
5313 /* If this use is for part of the insn,
5314 its value reaches if no subsequent part uses the same register.
5315 Just like the above function, don't try to do this with lots
5318 case RELOAD_FOR_OTHER_ADDRESS
:
5319 /* Here we check for everything else, since these don't conflict
5320 with anything else and everything comes later. */
5322 for (i
= 0; i
< reload_n_operands
; i
++)
5323 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5324 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5325 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5326 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5327 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5328 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5331 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5332 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5333 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5334 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5336 case RELOAD_FOR_INPUT_ADDRESS
:
5337 case RELOAD_FOR_INPADDR_ADDRESS
:
5338 /* Similar, except that we check only for this and subsequent inputs
5339 and the address of only subsequent inputs and we do not need
5340 to check for RELOAD_OTHER objects since they are known not to
5343 for (i
= opnum
; i
< reload_n_operands
; i
++)
5344 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5347 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5348 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5349 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5352 for (i
= 0; i
< reload_n_operands
; i
++)
5353 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5354 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5355 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5358 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5361 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5362 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5363 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5365 case RELOAD_FOR_INPUT
:
5366 /* Similar to input address, except we start at the next operand for
5367 both input and input address and we do not check for
5368 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5371 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5372 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5373 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5374 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5377 /* ... fall through ... */
5379 case RELOAD_FOR_OPERAND_ADDRESS
:
5380 /* Check outputs and their addresses. */
5382 for (i
= 0; i
< reload_n_operands
; i
++)
5383 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5384 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5385 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5388 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5390 case RELOAD_FOR_OPADDR_ADDR
:
5391 for (i
= 0; i
< reload_n_operands
; i
++)
5392 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5393 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5394 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5397 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5398 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5399 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5401 case RELOAD_FOR_INSN
:
5402 /* These conflict with other outputs with RELOAD_OTHER. So
5403 we need only check for output addresses. */
5405 opnum
= reload_n_operands
;
5407 /* ... fall through ... */
5409 case RELOAD_FOR_OUTPUT
:
5410 case RELOAD_FOR_OUTPUT_ADDRESS
:
5411 case RELOAD_FOR_OUTADDR_ADDRESS
:
5412 /* We already know these can't conflict with a later output. So the
5413 only thing to check are later output addresses.
5414 Note that multiple output operands are emitted in reverse order,
5415 so the conflicting ones are those with lower indices. */
5416 for (i
= 0; i
< opnum
; i
++)
5417 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5418 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5428 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5429 every register in the range [REGNO, REGNO + NREGS). */
5432 reload_regs_reach_end_p (unsigned int regno
, int nregs
,
5433 int opnum
, enum reload_type type
)
5437 for (i
= 0; i
< nregs
; i
++)
5438 if (!reload_reg_reaches_end_p (regno
+ i
, opnum
, type
))
5444 /* Returns whether R1 and R2 are uniquely chained: the value of one
5445 is used by the other, and that value is not used by any other
5446 reload for this insn. This is used to partially undo the decision
5447 made in find_reloads when in the case of multiple
5448 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5449 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5450 reloads. This code tries to avoid the conflict created by that
5451 change. It might be cleaner to explicitly keep track of which
5452 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5453 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5454 this after the fact. */
5456 reloads_unique_chain_p (int r1
, int r2
)
5460 /* We only check input reloads. */
5461 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5464 /* Avoid anything with output reloads. */
5465 if (rld
[r1
].out
|| rld
[r2
].out
)
5468 /* "chained" means one reload is a component of the other reload,
5469 not the same as the other reload. */
5470 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5471 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5472 || rld
[r1
].optional
|| rld
[r2
].optional
5473 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5474 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5477 for (i
= 0; i
< n_reloads
; i
++)
5478 /* Look for input reloads that aren't our two */
5479 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5481 /* If our reload is mentioned at all, it isn't a simple chain. */
5482 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5488 /* The recursive function change all occurrences of WHAT in *WHERE
5491 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5500 if (*where
== what
|| rtx_equal_p (*where
, what
))
5502 /* Record the location of the changed rtx. */
5503 VEC_safe_push (rtx_p
, heap
, substitute_stack
, where
);
5508 code
= GET_CODE (*where
);
5509 fmt
= GET_RTX_FORMAT (code
);
5510 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5516 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5517 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5519 else if (fmt
[i
] == 'e')
5520 substitute (&XEXP (*where
, i
), what
, repl
);
5524 /* The function returns TRUE if chain of reload R1 and R2 (in any
5525 order) can be evaluated without usage of intermediate register for
5526 the reload containing another reload. It is important to see
5527 gen_reload to understand what the function is trying to do. As an
5528 example, let us have reload chain
5531 r1: <something> + const
5533 and reload R2 got reload reg HR. The function returns true if
5534 there is a correct insn HR = HR + <something>. Otherwise,
5535 gen_reload will use intermediate register (and this is the reload
5536 reg for R1) to reload <something>.
5538 We need this function to find a conflict for chain reloads. In our
5539 example, if HR = HR + <something> is incorrect insn, then we cannot
5540 use HR as a reload register for R2. If we do use it then we get a
5549 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5551 /* Assume other cases in gen_reload are not possible for
5552 chain reloads or do need an intermediate hard registers. */
5555 rtx out
, in
, tem
, insn
;
5556 rtx last
= get_last_insn ();
5558 /* Make r2 a component of r1. */
5559 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5565 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5566 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5567 gcc_assert (regno
>= 0);
5568 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5570 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5572 /* If IN is a paradoxical SUBREG, remove it and try to put the
5573 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5574 if (GET_CODE (in
) == SUBREG
5575 && (GET_MODE_SIZE (GET_MODE (in
))
5576 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
5577 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
5578 in
= SUBREG_REG (in
), out
= tem
;
5580 if (GET_CODE (in
) == PLUS
5581 && (REG_P (XEXP (in
, 0))
5582 || GET_CODE (XEXP (in
, 0)) == SUBREG
5583 || MEM_P (XEXP (in
, 0)))
5584 && (REG_P (XEXP (in
, 1))
5585 || GET_CODE (XEXP (in
, 1)) == SUBREG
5586 || CONSTANT_P (XEXP (in
, 1))
5587 || MEM_P (XEXP (in
, 1))))
5589 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5590 code
= recog_memoized (insn
);
5595 extract_insn (insn
);
5596 /* We want constrain operands to treat this insn strictly in
5597 its validity determination, i.e., the way it would after
5598 reload has completed. */
5599 result
= constrain_operands (1);
5602 delete_insns_since (last
);
5605 /* Restore the original value at each changed address within R1. */
5606 while (!VEC_empty (rtx_p
, substitute_stack
))
5608 rtx
*where
= VEC_pop (rtx_p
, substitute_stack
);
5609 *where
= rld
[r2
].in
;
5615 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5618 This function uses the same algorithm as reload_reg_free_p above. */
5621 reloads_conflict (int r1
, int r2
)
5623 enum reload_type r1_type
= rld
[r1
].when_needed
;
5624 enum reload_type r2_type
= rld
[r2
].when_needed
;
5625 int r1_opnum
= rld
[r1
].opnum
;
5626 int r2_opnum
= rld
[r2
].opnum
;
5628 /* RELOAD_OTHER conflicts with everything. */
5629 if (r2_type
== RELOAD_OTHER
)
5632 /* Otherwise, check conflicts differently for each type. */
5636 case RELOAD_FOR_INPUT
:
5637 return (r2_type
== RELOAD_FOR_INSN
5638 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5639 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5640 || r2_type
== RELOAD_FOR_INPUT
5641 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5642 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5643 && r2_opnum
> r1_opnum
));
5645 case RELOAD_FOR_INPUT_ADDRESS
:
5646 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5647 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5649 case RELOAD_FOR_INPADDR_ADDRESS
:
5650 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5651 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5653 case RELOAD_FOR_OUTPUT_ADDRESS
:
5654 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5655 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5657 case RELOAD_FOR_OUTADDR_ADDRESS
:
5658 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5659 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5661 case RELOAD_FOR_OPERAND_ADDRESS
:
5662 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5663 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5664 && (!reloads_unique_chain_p (r1
, r2
)
5665 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5667 case RELOAD_FOR_OPADDR_ADDR
:
5668 return (r2_type
== RELOAD_FOR_INPUT
5669 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5671 case RELOAD_FOR_OUTPUT
:
5672 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5673 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5674 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5675 && r2_opnum
>= r1_opnum
));
5677 case RELOAD_FOR_INSN
:
5678 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5679 || r2_type
== RELOAD_FOR_INSN
5680 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5682 case RELOAD_FOR_OTHER_ADDRESS
:
5683 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5693 /* Indexed by reload number, 1 if incoming value
5694 inherited from previous insns. */
5695 static char reload_inherited
[MAX_RELOADS
];
5697 /* For an inherited reload, this is the insn the reload was inherited from,
5698 if we know it. Otherwise, this is 0. */
5699 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5701 /* If nonzero, this is a place to get the value of the reload,
5702 rather than using reload_in. */
5703 static rtx reload_override_in
[MAX_RELOADS
];
5705 /* For each reload, the hard register number of the register used,
5706 or -1 if we did not need a register for this reload. */
5707 static int reload_spill_index
[MAX_RELOADS
];
5709 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5710 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5712 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5713 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5715 /* Subroutine of free_for_value_p, used to check a single register.
5716 START_REGNO is the starting regno of the full reload register
5717 (possibly comprising multiple hard registers) that we are considering. */
5720 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5721 enum reload_type type
, rtx value
, rtx out
,
5722 int reloadnum
, int ignore_address_reloads
)
5725 /* Set if we see an input reload that must not share its reload register
5726 with any new earlyclobber, but might otherwise share the reload
5727 register with an output or input-output reload. */
5728 int check_earlyclobber
= 0;
5732 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5735 if (out
== const0_rtx
)
5741 /* We use some pseudo 'time' value to check if the lifetimes of the
5742 new register use would overlap with the one of a previous reload
5743 that is not read-only or uses a different value.
5744 The 'time' used doesn't have to be linear in any shape or form, just
5746 Some reload types use different 'buckets' for each operand.
5747 So there are MAX_RECOG_OPERANDS different time values for each
5749 We compute TIME1 as the time when the register for the prospective
5750 new reload ceases to be live, and TIME2 for each existing
5751 reload as the time when that the reload register of that reload
5753 Where there is little to be gained by exact lifetime calculations,
5754 we just make conservative assumptions, i.e. a longer lifetime;
5755 this is done in the 'default:' cases. */
5758 case RELOAD_FOR_OTHER_ADDRESS
:
5759 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5760 time1
= copy
? 0 : 1;
5763 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5765 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5766 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5767 respectively, to the time values for these, we get distinct time
5768 values. To get distinct time values for each operand, we have to
5769 multiply opnum by at least three. We round that up to four because
5770 multiply by four is often cheaper. */
5771 case RELOAD_FOR_INPADDR_ADDRESS
:
5772 time1
= opnum
* 4 + 2;
5774 case RELOAD_FOR_INPUT_ADDRESS
:
5775 time1
= opnum
* 4 + 3;
5777 case RELOAD_FOR_INPUT
:
5778 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5779 executes (inclusive). */
5780 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5782 case RELOAD_FOR_OPADDR_ADDR
:
5784 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5785 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5787 case RELOAD_FOR_OPERAND_ADDRESS
:
5788 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5790 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5792 case RELOAD_FOR_OUTADDR_ADDRESS
:
5793 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5795 case RELOAD_FOR_OUTPUT_ADDRESS
:
5796 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5799 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5802 for (i
= 0; i
< n_reloads
; i
++)
5804 rtx reg
= rld
[i
].reg_rtx
;
5805 if (reg
&& REG_P (reg
)
5806 && ((unsigned) regno
- true_regnum (reg
)
5807 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5810 rtx other_input
= rld
[i
].in
;
5812 /* If the other reload loads the same input value, that
5813 will not cause a conflict only if it's loading it into
5814 the same register. */
5815 if (true_regnum (reg
) != start_regno
)
5816 other_input
= NULL_RTX
;
5817 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5818 || rld
[i
].out
|| out
)
5821 switch (rld
[i
].when_needed
)
5823 case RELOAD_FOR_OTHER_ADDRESS
:
5826 case RELOAD_FOR_INPADDR_ADDRESS
:
5827 /* find_reloads makes sure that a
5828 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5829 by at most one - the first -
5830 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5831 address reload is inherited, the address address reload
5832 goes away, so we can ignore this conflict. */
5833 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5834 && ignore_address_reloads
5835 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5836 Then the address address is still needed to store
5837 back the new address. */
5838 && ! rld
[reloadnum
].out
)
5840 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5841 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5843 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5844 && ignore_address_reloads
5845 /* Unless we are reloading an auto_inc expression. */
5846 && ! rld
[reloadnum
].out
)
5848 time2
= rld
[i
].opnum
* 4 + 2;
5850 case RELOAD_FOR_INPUT_ADDRESS
:
5851 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5852 && ignore_address_reloads
5853 && ! rld
[reloadnum
].out
)
5855 time2
= rld
[i
].opnum
* 4 + 3;
5857 case RELOAD_FOR_INPUT
:
5858 time2
= rld
[i
].opnum
* 4 + 4;
5859 check_earlyclobber
= 1;
5861 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5862 == MAX_RECOG_OPERAND * 4 */
5863 case RELOAD_FOR_OPADDR_ADDR
:
5864 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5865 && ignore_address_reloads
5866 && ! rld
[reloadnum
].out
)
5868 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5870 case RELOAD_FOR_OPERAND_ADDRESS
:
5871 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5872 check_earlyclobber
= 1;
5874 case RELOAD_FOR_INSN
:
5875 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5877 case RELOAD_FOR_OUTPUT
:
5878 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5879 instruction is executed. */
5880 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5882 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5883 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5885 case RELOAD_FOR_OUTADDR_ADDRESS
:
5886 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5887 && ignore_address_reloads
5888 && ! rld
[reloadnum
].out
)
5890 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5892 case RELOAD_FOR_OUTPUT_ADDRESS
:
5893 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5896 /* If there is no conflict in the input part, handle this
5897 like an output reload. */
5898 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5900 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5901 /* Earlyclobbered outputs must conflict with inputs. */
5902 if (earlyclobber_operand_p (rld
[i
].out
))
5903 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5908 /* RELOAD_OTHER might be live beyond instruction execution,
5909 but this is not obvious when we set time2 = 1. So check
5910 here if there might be a problem with the new reload
5911 clobbering the register used by the RELOAD_OTHER. */
5919 && (! rld
[i
].in
|| rld
[i
].out
5920 || ! rtx_equal_p (other_input
, value
)))
5921 || (out
&& rld
[reloadnum
].out_reg
5922 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5928 /* Earlyclobbered outputs must conflict with inputs. */
5929 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5935 /* Return 1 if the value in reload reg REGNO, as used by a reload
5936 needed for the part of the insn specified by OPNUM and TYPE,
5937 may be used to load VALUE into it.
5939 MODE is the mode in which the register is used, this is needed to
5940 determine how many hard regs to test.
5942 Other read-only reloads with the same value do not conflict
5943 unless OUT is nonzero and these other reloads have to live while
5944 output reloads live.
5945 If OUT is CONST0_RTX, this is a special case: it means that the
5946 test should not be for using register REGNO as reload register, but
5947 for copying from register REGNO into the reload register.
5949 RELOADNUM is the number of the reload we want to load this value for;
5950 a reload does not conflict with itself.
5952 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5953 reloads that load an address for the very reload we are considering.
5955 The caller has to make sure that there is no conflict with the return
5959 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
5960 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5961 int ignore_address_reloads
)
5963 int nregs
= hard_regno_nregs
[regno
][mode
];
5965 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5966 value
, out
, reloadnum
,
5967 ignore_address_reloads
))
5972 /* Return nonzero if the rtx X is invariant over the current function. */
5973 /* ??? Actually, the places where we use this expect exactly what is
5974 tested here, and not everything that is function invariant. In
5975 particular, the frame pointer and arg pointer are special cased;
5976 pic_offset_table_rtx is not, and we must not spill these things to
5980 function_invariant_p (const_rtx x
)
5984 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5986 if (GET_CODE (x
) == PLUS
5987 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5988 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5993 /* Determine whether the reload reg X overlaps any rtx'es used for
5994 overriding inheritance. Return nonzero if so. */
5997 conflicts_with_override (rtx x
)
6000 for (i
= 0; i
< n_reloads
; i
++)
6001 if (reload_override_in
[i
]
6002 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6007 /* Give an error message saying we failed to find a reload for INSN,
6008 and clear out reload R. */
6010 failed_reload (rtx insn
, int r
)
6012 if (asm_noperands (PATTERN (insn
)) < 0)
6013 /* It's the compiler's fault. */
6014 fatal_insn ("could not find a spill register", insn
);
6016 /* It's the user's fault; the operand's mode and constraint
6017 don't match. Disable this reload so we don't crash in final. */
6018 error_for_asm (insn
,
6019 "%<asm%> operand constraint incompatible with operand size");
6023 rld
[r
].optional
= 1;
6024 rld
[r
].secondary_p
= 1;
6027 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6028 for reload R. If it's valid, get an rtx for it. Return nonzero if
6031 set_reload_reg (int i
, int r
)
6034 rtx reg
= spill_reg_rtx
[i
];
6036 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6037 spill_reg_rtx
[i
] = reg
6038 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6040 regno
= true_regnum (reg
);
6042 /* Detect when the reload reg can't hold the reload mode.
6043 This used to be one `if', but Sequent compiler can't handle that. */
6044 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6046 enum machine_mode test_mode
= VOIDmode
;
6048 test_mode
= GET_MODE (rld
[r
].in
);
6049 /* If rld[r].in has VOIDmode, it means we will load it
6050 in whatever mode the reload reg has: to wit, rld[r].mode.
6051 We have already tested that for validity. */
6052 /* Aside from that, we need to test that the expressions
6053 to reload from or into have modes which are valid for this
6054 reload register. Otherwise the reload insns would be invalid. */
6055 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6056 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6057 if (! (rld
[r
].out
!= 0
6058 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6060 /* The reg is OK. */
6063 /* Mark as in use for this insn the reload regs we use
6065 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6066 rld
[r
].when_needed
, rld
[r
].mode
);
6068 rld
[r
].reg_rtx
= reg
;
6069 reload_spill_index
[r
] = spill_regs
[i
];
6076 /* Find a spill register to use as a reload register for reload R.
6077 LAST_RELOAD is nonzero if this is the last reload for the insn being
6080 Set rld[R].reg_rtx to the register allocated.
6082 We return 1 if successful, or 0 if we couldn't find a spill reg and
6083 we didn't change anything. */
6086 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6091 /* If we put this reload ahead, thinking it is a group,
6092 then insist on finding a group. Otherwise we can grab a
6093 reg that some other reload needs.
6094 (That can happen when we have a 68000 DATA_OR_FP_REG
6095 which is a group of data regs or one fp reg.)
6096 We need not be so restrictive if there are no more reloads
6099 ??? Really it would be nicer to have smarter handling
6100 for that kind of reg class, where a problem like this is normal.
6101 Perhaps those classes should be avoided for reloading
6102 by use of more alternatives. */
6104 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6106 /* If we want a single register and haven't yet found one,
6107 take any reg in the right class and not in use.
6108 If we want a consecutive group, here is where we look for it.
6110 We use three passes so we can first look for reload regs to
6111 reuse, which are already in use for other reloads in this insn,
6112 and only then use additional registers which are not "bad", then
6113 finally any register.
6115 I think that maximizing reuse is needed to make sure we don't
6116 run out of reload regs. Suppose we have three reloads, and
6117 reloads A and B can share regs. These need two regs.
6118 Suppose A and B are given different regs.
6119 That leaves none for C. */
6120 for (pass
= 0; pass
< 3; pass
++)
6122 /* I is the index in spill_regs.
6123 We advance it round-robin between insns to use all spill regs
6124 equally, so that inherited reloads have a chance
6125 of leapfrogging each other. */
6129 for (count
= 0; count
< n_spills
; count
++)
6131 int rclass
= (int) rld
[r
].rclass
;
6137 regnum
= spill_regs
[i
];
6139 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6142 /* We check reload_reg_used to make sure we
6143 don't clobber the return register. */
6144 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6145 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6146 rld
[r
].when_needed
, rld
[r
].in
,
6148 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6149 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6150 /* Look first for regs to share, then for unshared. But
6151 don't share regs used for inherited reloads; they are
6152 the ones we want to preserve. */
6154 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6156 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6159 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6161 /* During the second pass we want to avoid reload registers
6162 which are "bad" for this reload. */
6164 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6167 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6168 (on 68000) got us two FP regs. If NR is 1,
6169 we would reject both of them. */
6172 /* If we need only one reg, we have already won. */
6175 /* But reject a single reg if we demand a group. */
6180 /* Otherwise check that as many consecutive regs as we need
6181 are available here. */
6184 int regno
= regnum
+ nr
- 1;
6185 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6186 && spill_reg_order
[regno
] >= 0
6187 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6188 rld
[r
].when_needed
)))
6197 /* If we found something on the current pass, omit later passes. */
6198 if (count
< n_spills
)
6202 /* We should have found a spill register by now. */
6203 if (count
>= n_spills
)
6206 /* I is the index in SPILL_REG_RTX of the reload register we are to
6207 allocate. Get an rtx for it and find its register number. */
6209 return set_reload_reg (i
, r
);
6212 /* Initialize all the tables needed to allocate reload registers.
6213 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6214 is the array we use to restore the reg_rtx field for every reload. */
6217 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6221 for (i
= 0; i
< n_reloads
; i
++)
6222 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6224 memset (reload_inherited
, 0, MAX_RELOADS
);
6225 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6226 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6228 CLEAR_HARD_REG_SET (reload_reg_used
);
6229 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6230 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6231 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6232 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6233 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6235 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6238 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6239 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6240 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6241 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6242 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6243 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6246 for (i
= 0; i
< reload_n_operands
; i
++)
6248 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6249 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6250 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6251 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6252 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6253 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6256 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6258 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6260 for (i
= 0; i
< n_reloads
; i
++)
6261 /* If we have already decided to use a certain register,
6262 don't use it in another way. */
6264 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6265 rld
[i
].when_needed
, rld
[i
].mode
);
6268 /* Assign hard reg targets for the pseudo-registers we must reload
6269 into hard regs for this insn.
6270 Also output the instructions to copy them in and out of the hard regs.
6272 For machines with register classes, we are responsible for
6273 finding a reload reg in the proper class. */
6276 choose_reload_regs (struct insn_chain
*chain
)
6278 rtx insn
= chain
->insn
;
6280 unsigned int max_group_size
= 1;
6281 enum reg_class group_class
= NO_REGS
;
6282 int pass
, win
, inheritance
;
6284 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6286 /* In order to be certain of getting the registers we need,
6287 we must sort the reloads into order of increasing register class.
6288 Then our grabbing of reload registers will parallel the process
6289 that provided the reload registers.
6291 Also note whether any of the reloads wants a consecutive group of regs.
6292 If so, record the maximum size of the group desired and what
6293 register class contains all the groups needed by this insn. */
6295 for (j
= 0; j
< n_reloads
; j
++)
6297 reload_order
[j
] = j
;
6298 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6300 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6301 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6302 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6305 reload_spill_index
[j
] = -1;
6307 if (rld
[j
].nregs
> 1)
6309 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6311 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6314 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6318 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6320 /* If -O, try first with inheritance, then turning it off.
6321 If not -O, don't do inheritance.
6322 Using inheritance when not optimizing leads to paradoxes
6323 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6324 because one side of the comparison might be inherited. */
6326 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6328 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6330 /* Process the reloads in order of preference just found.
6331 Beyond this point, subregs can be found in reload_reg_rtx.
6333 This used to look for an existing reloaded home for all of the
6334 reloads, and only then perform any new reloads. But that could lose
6335 if the reloads were done out of reg-class order because a later
6336 reload with a looser constraint might have an old home in a register
6337 needed by an earlier reload with a tighter constraint.
6339 To solve this, we make two passes over the reloads, in the order
6340 described above. In the first pass we try to inherit a reload
6341 from a previous insn. If there is a later reload that needs a
6342 class that is a proper subset of the class being processed, we must
6343 also allocate a spill register during the first pass.
6345 Then make a second pass over the reloads to allocate any reloads
6346 that haven't been given registers yet. */
6348 for (j
= 0; j
< n_reloads
; j
++)
6350 int r
= reload_order
[j
];
6351 rtx search_equiv
= NULL_RTX
;
6353 /* Ignore reloads that got marked inoperative. */
6354 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6355 && ! rld
[r
].secondary_p
)
6358 /* If find_reloads chose to use reload_in or reload_out as a reload
6359 register, we don't need to chose one. Otherwise, try even if it
6360 found one since we might save an insn if we find the value lying
6362 Try also when reload_in is a pseudo without a hard reg. */
6363 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6364 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6365 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6366 && !MEM_P (rld
[r
].in
)
6367 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6370 #if 0 /* No longer needed for correct operation.
6371 It might give better code, or might not; worth an experiment? */
6372 /* If this is an optional reload, we can't inherit from earlier insns
6373 until we are sure that any non-optional reloads have been allocated.
6374 The following code takes advantage of the fact that optional reloads
6375 are at the end of reload_order. */
6376 if (rld
[r
].optional
!= 0)
6377 for (i
= 0; i
< j
; i
++)
6378 if ((rld
[reload_order
[i
]].out
!= 0
6379 || rld
[reload_order
[i
]].in
!= 0
6380 || rld
[reload_order
[i
]].secondary_p
)
6381 && ! rld
[reload_order
[i
]].optional
6382 && rld
[reload_order
[i
]].reg_rtx
== 0)
6383 allocate_reload_reg (chain
, reload_order
[i
], 0);
6386 /* First see if this pseudo is already available as reloaded
6387 for a previous insn. We cannot try to inherit for reloads
6388 that are smaller than the maximum number of registers needed
6389 for groups unless the register we would allocate cannot be used
6392 We could check here to see if this is a secondary reload for
6393 an object that is already in a register of the desired class.
6394 This would avoid the need for the secondary reload register.
6395 But this is complex because we can't easily determine what
6396 objects might want to be loaded via this reload. So let a
6397 register be allocated here. In `emit_reload_insns' we suppress
6398 one of the loads in the case described above. */
6404 enum machine_mode mode
= VOIDmode
;
6408 else if (REG_P (rld
[r
].in
))
6410 regno
= REGNO (rld
[r
].in
);
6411 mode
= GET_MODE (rld
[r
].in
);
6413 else if (REG_P (rld
[r
].in_reg
))
6415 regno
= REGNO (rld
[r
].in_reg
);
6416 mode
= GET_MODE (rld
[r
].in_reg
);
6418 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6419 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6421 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6422 if (regno
< FIRST_PSEUDO_REGISTER
)
6423 regno
= subreg_regno (rld
[r
].in_reg
);
6425 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
6426 mode
= GET_MODE (rld
[r
].in_reg
);
6429 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6430 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6432 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6433 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6434 rld
[r
].out
= rld
[r
].in
;
6438 /* This won't work, since REGNO can be a pseudo reg number.
6439 Also, it takes much more hair to keep track of all the things
6440 that can invalidate an inherited reload of part of a pseudoreg. */
6441 else if (GET_CODE (rld
[r
].in
) == SUBREG
6442 && REG_P (SUBREG_REG (rld
[r
].in
)))
6443 regno
= subreg_regno (rld
[r
].in
);
6447 && reg_last_reload_reg
[regno
] != 0
6448 #ifdef CANNOT_CHANGE_MODE_CLASS
6449 /* Verify that the register it's in can be used in
6451 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6452 GET_MODE (reg_last_reload_reg
[regno
]),
6457 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6458 rtx last_reg
= reg_last_reload_reg
[regno
];
6459 enum machine_mode need_mode
;
6461 i
= REGNO (last_reg
);
6462 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6463 last_class
= REGNO_REG_CLASS (i
);
6469 = smallest_mode_for_size
6470 (GET_MODE_BITSIZE (mode
) + byte
* BITS_PER_UNIT
,
6471 GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
6472 ? MODE_INT
: GET_MODE_CLASS (mode
));
6474 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
6475 >= GET_MODE_SIZE (need_mode
))
6476 && reg_reloaded_contents
[i
] == regno
6477 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6478 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6479 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6480 /* Even if we can't use this register as a reload
6481 register, we might use it for reload_override_in,
6482 if copying it to the desired class is cheap
6484 || ((register_move_cost (mode
, last_class
, rclass
)
6485 < memory_move_cost (mode
, rclass
, true))
6486 && (secondary_reload_class (1, rclass
, mode
,
6489 #ifdef SECONDARY_MEMORY_NEEDED
6490 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6495 && (rld
[r
].nregs
== max_group_size
6496 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6498 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6499 rld
[r
].when_needed
, rld
[r
].in
,
6502 /* If a group is needed, verify that all the subsequent
6503 registers still have their values intact. */
6504 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6507 for (k
= 1; k
< nr
; k
++)
6508 if (reg_reloaded_contents
[i
+ k
] != regno
6509 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6517 last_reg
= (GET_MODE (last_reg
) == mode
6518 ? last_reg
: gen_rtx_REG (mode
, i
));
6521 for (k
= 0; k
< nr
; k
++)
6522 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6525 /* We found a register that contains the
6526 value we need. If this register is the
6527 same as an `earlyclobber' operand of the
6528 current insn, just mark it as a place to
6529 reload from since we can't use it as the
6530 reload register itself. */
6532 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6533 if (reg_overlap_mentioned_for_reload_p
6534 (reg_last_reload_reg
[regno
],
6535 reload_earlyclobbers
[i1
]))
6538 if (i1
!= n_earlyclobbers
6539 || ! (free_for_value_p (i
, rld
[r
].mode
,
6541 rld
[r
].when_needed
, rld
[r
].in
,
6543 /* Don't use it if we'd clobber a pseudo reg. */
6544 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6546 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6547 /* Don't clobber the frame pointer. */
6548 || (i
== HARD_FRAME_POINTER_REGNUM
6549 && frame_pointer_needed
6551 /* Don't really use the inherited spill reg
6552 if we need it wider than we've got it. */
6553 || (GET_MODE_SIZE (rld
[r
].mode
)
6554 > GET_MODE_SIZE (mode
))
6557 /* If find_reloads chose reload_out as reload
6558 register, stay with it - that leaves the
6559 inherited register for subsequent reloads. */
6560 || (rld
[r
].out
&& rld
[r
].reg_rtx
6561 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6563 if (! rld
[r
].optional
)
6565 reload_override_in
[r
] = last_reg
;
6566 reload_inheritance_insn
[r
]
6567 = reg_reloaded_insn
[i
];
6573 /* We can use this as a reload reg. */
6574 /* Mark the register as in use for this part of
6576 mark_reload_reg_in_use (i
,
6580 rld
[r
].reg_rtx
= last_reg
;
6581 reload_inherited
[r
] = 1;
6582 reload_inheritance_insn
[r
]
6583 = reg_reloaded_insn
[i
];
6584 reload_spill_index
[r
] = i
;
6585 for (k
= 0; k
< nr
; k
++)
6586 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6594 /* Here's another way to see if the value is already lying around. */
6597 && ! reload_inherited
[r
]
6599 && (CONSTANT_P (rld
[r
].in
)
6600 || GET_CODE (rld
[r
].in
) == PLUS
6601 || REG_P (rld
[r
].in
)
6602 || MEM_P (rld
[r
].in
))
6603 && (rld
[r
].nregs
== max_group_size
6604 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6605 search_equiv
= rld
[r
].in
;
6606 /* If this is an output reload from a simple move insn, look
6607 if an equivalence for the input is available. */
6608 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
6610 rtx set
= single_set (insn
);
6613 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
6614 && CONSTANT_P (SET_SRC (set
)))
6615 search_equiv
= SET_SRC (set
);
6621 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6622 -1, NULL
, 0, rld
[r
].mode
);
6628 regno
= REGNO (equiv
);
6631 /* This must be a SUBREG of a hard register.
6632 Make a new REG since this might be used in an
6633 address and not all machines support SUBREGs
6635 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6636 regno
= subreg_regno (equiv
);
6637 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6638 /* If we choose EQUIV as the reload register, but the
6639 loop below decides to cancel the inheritance, we'll
6640 end up reloading EQUIV in rld[r].mode, not the mode
6641 it had originally. That isn't safe when EQUIV isn't
6642 available as a spill register since its value might
6643 still be live at this point. */
6644 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6645 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6650 /* If we found a spill reg, reject it unless it is free
6651 and of the desired class. */
6655 int bad_for_class
= 0;
6656 int max_regno
= regno
+ rld
[r
].nregs
;
6658 for (i
= regno
; i
< max_regno
; i
++)
6660 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6662 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6667 && ! free_for_value_p (regno
, rld
[r
].mode
,
6668 rld
[r
].opnum
, rld
[r
].when_needed
,
6669 rld
[r
].in
, rld
[r
].out
, r
, 1))
6674 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6677 /* We found a register that contains the value we need.
6678 If this register is the same as an `earlyclobber' operand
6679 of the current insn, just mark it as a place to reload from
6680 since we can't use it as the reload register itself. */
6683 for (i
= 0; i
< n_earlyclobbers
; i
++)
6684 if (reg_overlap_mentioned_for_reload_p (equiv
,
6685 reload_earlyclobbers
[i
]))
6687 if (! rld
[r
].optional
)
6688 reload_override_in
[r
] = equiv
;
6693 /* If the equiv register we have found is explicitly clobbered
6694 in the current insn, it depends on the reload type if we
6695 can use it, use it for reload_override_in, or not at all.
6696 In particular, we then can't use EQUIV for a
6697 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6701 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6702 switch (rld
[r
].when_needed
)
6704 case RELOAD_FOR_OTHER_ADDRESS
:
6705 case RELOAD_FOR_INPADDR_ADDRESS
:
6706 case RELOAD_FOR_INPUT_ADDRESS
:
6707 case RELOAD_FOR_OPADDR_ADDR
:
6710 case RELOAD_FOR_INPUT
:
6711 case RELOAD_FOR_OPERAND_ADDRESS
:
6712 if (! rld
[r
].optional
)
6713 reload_override_in
[r
] = equiv
;
6719 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6720 switch (rld
[r
].when_needed
)
6722 case RELOAD_FOR_OTHER_ADDRESS
:
6723 case RELOAD_FOR_INPADDR_ADDRESS
:
6724 case RELOAD_FOR_INPUT_ADDRESS
:
6725 case RELOAD_FOR_OPADDR_ADDR
:
6726 case RELOAD_FOR_OPERAND_ADDRESS
:
6727 case RELOAD_FOR_INPUT
:
6730 if (! rld
[r
].optional
)
6731 reload_override_in
[r
] = equiv
;
6739 /* If we found an equivalent reg, say no code need be generated
6740 to load it, and use it as our reload reg. */
6742 && (regno
!= HARD_FRAME_POINTER_REGNUM
6743 || !frame_pointer_needed
))
6745 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6747 rld
[r
].reg_rtx
= equiv
;
6748 reload_spill_index
[r
] = regno
;
6749 reload_inherited
[r
] = 1;
6751 /* If reg_reloaded_valid is not set for this register,
6752 there might be a stale spill_reg_store lying around.
6753 We must clear it, since otherwise emit_reload_insns
6754 might delete the store. */
6755 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6756 spill_reg_store
[regno
] = NULL_RTX
;
6757 /* If any of the hard registers in EQUIV are spill
6758 registers, mark them as in use for this insn. */
6759 for (k
= 0; k
< nr
; k
++)
6761 i
= spill_reg_order
[regno
+ k
];
6764 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6767 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6774 /* If we found a register to use already, or if this is an optional
6775 reload, we are done. */
6776 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6780 /* No longer needed for correct operation. Might or might
6781 not give better code on the average. Want to experiment? */
6783 /* See if there is a later reload that has a class different from our
6784 class that intersects our class or that requires less register
6785 than our reload. If so, we must allocate a register to this
6786 reload now, since that reload might inherit a previous reload
6787 and take the only available register in our class. Don't do this
6788 for optional reloads since they will force all previous reloads
6789 to be allocated. Also don't do this for reloads that have been
6792 for (i
= j
+ 1; i
< n_reloads
; i
++)
6794 int s
= reload_order
[i
];
6796 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6797 && ! rld
[s
].secondary_p
)
6801 if ((rld
[s
].rclass
!= rld
[r
].rclass
6802 && reg_classes_intersect_p (rld
[r
].rclass
,
6804 || rld
[s
].nregs
< rld
[r
].nregs
)
6811 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6815 /* Now allocate reload registers for anything non-optional that
6816 didn't get one yet. */
6817 for (j
= 0; j
< n_reloads
; j
++)
6819 int r
= reload_order
[j
];
6821 /* Ignore reloads that got marked inoperative. */
6822 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6825 /* Skip reloads that already have a register allocated or are
6827 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6830 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6834 /* If that loop got all the way, we have won. */
6841 /* Loop around and try without any inheritance. */
6846 /* First undo everything done by the failed attempt
6847 to allocate with inheritance. */
6848 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6850 /* Some sanity tests to verify that the reloads found in the first
6851 pass are identical to the ones we have now. */
6852 gcc_assert (chain
->n_reloads
== n_reloads
);
6854 for (i
= 0; i
< n_reloads
; i
++)
6856 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6858 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6859 for (j
= 0; j
< n_spills
; j
++)
6860 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6861 if (! set_reload_reg (j
, i
))
6862 failed_reload (chain
->insn
, i
);
6866 /* If we thought we could inherit a reload, because it seemed that
6867 nothing else wanted the same reload register earlier in the insn,
6868 verify that assumption, now that all reloads have been assigned.
6869 Likewise for reloads where reload_override_in has been set. */
6871 /* If doing expensive optimizations, do one preliminary pass that doesn't
6872 cancel any inheritance, but removes reloads that have been needed only
6873 for reloads that we know can be inherited. */
6874 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6876 for (j
= 0; j
< n_reloads
; j
++)
6878 int r
= reload_order
[j
];
6880 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6881 check_reg
= rld
[r
].reg_rtx
;
6882 else if (reload_override_in
[r
]
6883 && (REG_P (reload_override_in
[r
])
6884 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6885 check_reg
= reload_override_in
[r
];
6888 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6889 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6890 (reload_inherited
[r
]
6891 ? rld
[r
].out
: const0_rtx
),
6896 reload_inherited
[r
] = 0;
6897 reload_override_in
[r
] = 0;
6899 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6900 reload_override_in, then we do not need its related
6901 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6902 likewise for other reload types.
6903 We handle this by removing a reload when its only replacement
6904 is mentioned in reload_in of the reload we are going to inherit.
6905 A special case are auto_inc expressions; even if the input is
6906 inherited, we still need the address for the output. We can
6907 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6908 If we succeeded removing some reload and we are doing a preliminary
6909 pass just to remove such reloads, make another pass, since the
6910 removal of one reload might allow us to inherit another one. */
6912 && rld
[r
].out
!= rld
[r
].in
6913 && remove_address_replacements (rld
[r
].in
) && pass
)
6918 /* Now that reload_override_in is known valid,
6919 actually override reload_in. */
6920 for (j
= 0; j
< n_reloads
; j
++)
6921 if (reload_override_in
[j
])
6922 rld
[j
].in
= reload_override_in
[j
];
6924 /* If this reload won't be done because it has been canceled or is
6925 optional and not inherited, clear reload_reg_rtx so other
6926 routines (such as subst_reloads) don't get confused. */
6927 for (j
= 0; j
< n_reloads
; j
++)
6928 if (rld
[j
].reg_rtx
!= 0
6929 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6930 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6931 && ! rld
[j
].secondary_p
)))
6933 int regno
= true_regnum (rld
[j
].reg_rtx
);
6935 if (spill_reg_order
[regno
] >= 0)
6936 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6937 rld
[j
].when_needed
, rld
[j
].mode
);
6939 reload_spill_index
[j
] = -1;
6942 /* Record which pseudos and which spill regs have output reloads. */
6943 for (j
= 0; j
< n_reloads
; j
++)
6945 int r
= reload_order
[j
];
6947 i
= reload_spill_index
[r
];
6949 /* I is nonneg if this reload uses a register.
6950 If rld[r].reg_rtx is 0, this is an optional reload
6951 that we opted to ignore. */
6952 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6953 && rld
[r
].reg_rtx
!= 0)
6955 int nregno
= REGNO (rld
[r
].out_reg
);
6958 if (nregno
< FIRST_PSEUDO_REGISTER
)
6959 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
6962 SET_REGNO_REG_SET (®_has_output_reload
,
6967 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6969 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6972 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
6973 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
6974 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
6979 /* Deallocate the reload register for reload R. This is called from
6980 remove_address_replacements. */
6983 deallocate_reload_reg (int r
)
6987 if (! rld
[r
].reg_rtx
)
6989 regno
= true_regnum (rld
[r
].reg_rtx
);
6991 if (spill_reg_order
[regno
] >= 0)
6992 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6994 reload_spill_index
[r
] = -1;
6997 /* If the small_register_classes_for_mode_p target hook returns true for
6998 some machine modes, we may not have merged two reloads of the same item
6999 for fear that we might not have enough reload registers. However,
7000 normally they will get the same reload register and hence actually need
7001 not be loaded twice.
7003 Here we check for the most common case of this phenomenon: when we have
7004 a number of reloads for the same object, each of which were allocated
7005 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
7006 reload, and is not modified in the insn itself. If we find such,
7007 merge all the reloads and set the resulting reload to RELOAD_OTHER.
7008 This will not increase the number of spill registers needed and will
7009 prevent redundant code. */
7012 merge_assigned_reloads (rtx insn
)
7016 /* Scan all the reloads looking for ones that only load values and
7017 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
7018 assigned and not modified by INSN. */
7020 for (i
= 0; i
< n_reloads
; i
++)
7022 int conflicting_input
= 0;
7023 int max_input_address_opnum
= -1;
7024 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
7026 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
7027 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
7028 || reg_set_p (rld
[i
].reg_rtx
, insn
))
7031 /* Look at all other reloads. Ensure that the only use of this
7032 reload_reg_rtx is in a reload that just loads the same value
7033 as we do. Note that any secondary reloads must be of the identical
7034 class since the values, modes, and result registers are the
7035 same, so we need not do anything with any secondary reloads. */
7037 for (j
= 0; j
< n_reloads
; j
++)
7039 if (i
== j
|| rld
[j
].reg_rtx
== 0
7040 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
7044 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
7045 && rld
[j
].opnum
> max_input_address_opnum
)
7046 max_input_address_opnum
= rld
[j
].opnum
;
7048 /* If the reload regs aren't exactly the same (e.g, different modes)
7049 or if the values are different, we can't merge this reload.
7050 But if it is an input reload, we might still merge
7051 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
7053 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
7054 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
7055 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
7057 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
7058 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
7059 || rld
[i
].opnum
> rld
[j
].opnum
)
7060 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
7062 conflicting_input
= 1;
7063 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
7064 min_conflicting_input_opnum
= rld
[j
].opnum
;
7068 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
7069 we, in fact, found any matching reloads. */
7072 && max_input_address_opnum
<= min_conflicting_input_opnum
)
7074 gcc_assert (rld
[i
].when_needed
!= RELOAD_FOR_OUTPUT
);
7076 for (j
= 0; j
< n_reloads
; j
++)
7077 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
7078 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
7079 && (! conflicting_input
7080 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
7081 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
7083 rld
[i
].when_needed
= RELOAD_OTHER
;
7085 reload_spill_index
[j
] = -1;
7086 transfer_replacements (i
, j
);
7089 /* If this is now RELOAD_OTHER, look for any reloads that
7090 load parts of this operand and set them to
7091 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
7092 RELOAD_OTHER for outputs. Note that this test is
7093 equivalent to looking for reloads for this operand
7096 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
7097 it may share registers with a RELOAD_FOR_INPUT, so we can
7098 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
7099 never need to, since we do not modify RELOAD_FOR_OUTPUT.
7101 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
7102 instruction is assigned the same register as the earlier
7103 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
7104 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
7105 instruction to be deleted later on. */
7107 if (rld
[i
].when_needed
== RELOAD_OTHER
)
7108 for (j
= 0; j
< n_reloads
; j
++)
7110 && rld
[j
].when_needed
!= RELOAD_OTHER
7111 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
7112 && rld
[j
].when_needed
!= RELOAD_FOR_OUTPUT_ADDRESS
7113 && rld
[j
].when_needed
!= RELOAD_FOR_OPERAND_ADDRESS
7114 && (! conflicting_input
7115 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
7116 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
7117 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
7123 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
7124 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
7125 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
7127 /* Check to see if we accidentally converted two
7128 reloads that use the same reload register with
7129 different inputs to the same type. If so, the
7130 resulting code won't work. */
7132 for (k
= 0; k
< j
; k
++)
7133 gcc_assert (rld
[k
].in
== 0 || rld
[k
].reg_rtx
== 0
7134 || rld
[k
].when_needed
!= rld
[j
].when_needed
7135 || !rtx_equal_p (rld
[k
].reg_rtx
,
7137 || rtx_equal_p (rld
[k
].in
,
7144 /* These arrays are filled by emit_reload_insns and its subroutines. */
7145 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
7146 static rtx other_input_address_reload_insns
= 0;
7147 static rtx other_input_reload_insns
= 0;
7148 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7149 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7150 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7151 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7152 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7153 static rtx operand_reload_insns
= 0;
7154 static rtx other_operand_reload_insns
= 0;
7155 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7157 /* Values to be put in spill_reg_store are put here first. */
7158 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7159 static HARD_REG_SET reg_reloaded_died
;
7161 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7162 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7163 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7164 adjusted register, and return true. Otherwise, return false. */
7166 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7167 enum reg_class new_class
,
7168 enum machine_mode new_mode
)
7173 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7175 unsigned regno
= REGNO (reg
);
7177 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7179 if (GET_MODE (reg
) != new_mode
)
7181 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7183 if (hard_regno_nregs
[regno
][new_mode
]
7184 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7186 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7194 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7195 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7196 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7197 adjusted register, and return true. Otherwise, return false. */
7199 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7200 enum insn_code icode
)
7203 enum reg_class new_class
= scratch_reload_class (icode
);
7204 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7206 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7207 new_class
, new_mode
);
7210 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7211 has the number J. OLD contains the value to be used as input. */
7214 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7217 rtx insn
= chain
->insn
;
7219 rtx oldequiv_reg
= 0;
7222 enum machine_mode mode
;
7225 /* delete_output_reload is only invoked properly if old contains
7226 the original pseudo register. Since this is replaced with a
7227 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7228 find the pseudo in RELOAD_IN_REG. */
7229 if (reload_override_in
[j
]
7230 && REG_P (rl
->in_reg
))
7237 else if (REG_P (oldequiv
))
7238 oldequiv_reg
= oldequiv
;
7239 else if (GET_CODE (oldequiv
) == SUBREG
)
7240 oldequiv_reg
= SUBREG_REG (oldequiv
);
7242 reloadreg
= reload_reg_rtx_for_input
[j
];
7243 mode
= GET_MODE (reloadreg
);
7245 /* If we are reloading from a register that was recently stored in
7246 with an output-reload, see if we can prove there was
7247 actually no need to store the old value in it. */
7249 if (optimize
&& REG_P (oldequiv
)
7250 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7251 && spill_reg_store
[REGNO (oldequiv
)]
7253 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7254 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7256 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7258 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7261 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7262 oldequiv
= SUBREG_REG (oldequiv
);
7263 if (GET_MODE (oldequiv
) != VOIDmode
7264 && mode
!= GET_MODE (oldequiv
))
7265 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7267 /* Switch to the right place to emit the reload insns. */
7268 switch (rl
->when_needed
)
7271 where
= &other_input_reload_insns
;
7273 case RELOAD_FOR_INPUT
:
7274 where
= &input_reload_insns
[rl
->opnum
];
7276 case RELOAD_FOR_INPUT_ADDRESS
:
7277 where
= &input_address_reload_insns
[rl
->opnum
];
7279 case RELOAD_FOR_INPADDR_ADDRESS
:
7280 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7282 case RELOAD_FOR_OUTPUT_ADDRESS
:
7283 where
= &output_address_reload_insns
[rl
->opnum
];
7285 case RELOAD_FOR_OUTADDR_ADDRESS
:
7286 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7288 case RELOAD_FOR_OPERAND_ADDRESS
:
7289 where
= &operand_reload_insns
;
7291 case RELOAD_FOR_OPADDR_ADDR
:
7292 where
= &other_operand_reload_insns
;
7294 case RELOAD_FOR_OTHER_ADDRESS
:
7295 where
= &other_input_address_reload_insns
;
7301 push_to_sequence (*where
);
7303 /* Auto-increment addresses must be reloaded in a special way. */
7304 if (rl
->out
&& ! rl
->out_reg
)
7306 /* We are not going to bother supporting the case where a
7307 incremented register can't be copied directly from
7308 OLDEQUIV since this seems highly unlikely. */
7309 gcc_assert (rl
->secondary_in_reload
< 0);
7311 if (reload_inherited
[j
])
7312 oldequiv
= reloadreg
;
7314 old
= XEXP (rl
->in_reg
, 0);
7316 if (optimize
&& REG_P (oldequiv
)
7317 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7318 && spill_reg_store
[REGNO (oldequiv
)]
7320 && (dead_or_set_p (insn
,
7321 spill_reg_stored_to
[REGNO (oldequiv
)])
7322 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7324 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7326 /* Prevent normal processing of this reload. */
7328 /* Output a special code sequence for this case. */
7329 new_spill_reg_store
[REGNO (reloadreg
)]
7330 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
7334 /* If we are reloading a pseudo-register that was set by the previous
7335 insn, see if we can get rid of that pseudo-register entirely
7336 by redirecting the previous insn into our reload register. */
7338 else if (optimize
&& REG_P (old
)
7339 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7340 && dead_or_set_p (insn
, old
)
7341 /* This is unsafe if some other reload
7342 uses the same reg first. */
7343 && ! conflicts_with_override (reloadreg
)
7344 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7345 rl
->when_needed
, old
, rl
->out
, j
, 0))
7347 rtx temp
= PREV_INSN (insn
);
7348 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7349 temp
= PREV_INSN (temp
);
7351 && NONJUMP_INSN_P (temp
)
7352 && GET_CODE (PATTERN (temp
)) == SET
7353 && SET_DEST (PATTERN (temp
)) == old
7354 /* Make sure we can access insn_operand_constraint. */
7355 && asm_noperands (PATTERN (temp
)) < 0
7356 /* This is unsafe if operand occurs more than once in current
7357 insn. Perhaps some occurrences aren't reloaded. */
7358 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7360 rtx old
= SET_DEST (PATTERN (temp
));
7361 /* Store into the reload register instead of the pseudo. */
7362 SET_DEST (PATTERN (temp
)) = reloadreg
;
7364 /* Verify that resulting insn is valid. */
7365 extract_insn (temp
);
7366 if (constrain_operands (1))
7368 /* If the previous insn is an output reload, the source is
7369 a reload register, and its spill_reg_store entry will
7370 contain the previous destination. This is now
7372 if (REG_P (SET_SRC (PATTERN (temp
)))
7373 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7375 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7376 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7379 /* If these are the only uses of the pseudo reg,
7380 pretend for GDB it lives in the reload reg we used. */
7381 if (REG_N_DEATHS (REGNO (old
)) == 1
7382 && REG_N_SETS (REGNO (old
)) == 1)
7384 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7385 if (ira_conflicts_p
)
7386 /* Inform IRA about the change. */
7387 ira_mark_allocation_change (REGNO (old
));
7388 alter_reg (REGNO (old
), -1, false);
7392 /* Adjust any debug insns between temp and insn. */
7393 while ((temp
= NEXT_INSN (temp
)) != insn
)
7394 if (DEBUG_INSN_P (temp
))
7395 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7397 gcc_assert (NOTE_P (temp
));
7401 SET_DEST (PATTERN (temp
)) = old
;
7406 /* We can't do that, so output an insn to load RELOADREG. */
7408 /* If we have a secondary reload, pick up the secondary register
7409 and icode, if any. If OLDEQUIV and OLD are different or
7410 if this is an in-out reload, recompute whether or not we
7411 still need a secondary register and what the icode should
7412 be. If we still need a secondary register and the class or
7413 icode is different, go back to reloading from OLD if using
7414 OLDEQUIV means that we got the wrong type of register. We
7415 cannot have different class or icode due to an in-out reload
7416 because we don't make such reloads when both the input and
7417 output need secondary reload registers. */
7419 if (! special
&& rl
->secondary_in_reload
>= 0)
7421 rtx second_reload_reg
= 0;
7422 rtx third_reload_reg
= 0;
7423 int secondary_reload
= rl
->secondary_in_reload
;
7424 rtx real_oldequiv
= oldequiv
;
7427 enum insn_code icode
;
7428 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7430 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7431 and similarly for OLD.
7432 See comments in get_secondary_reload in reload.c. */
7433 /* If it is a pseudo that cannot be replaced with its
7434 equivalent MEM, we must fall back to reload_in, which
7435 will have all the necessary substitutions registered.
7436 Likewise for a pseudo that can't be replaced with its
7437 equivalent constant.
7439 Take extra care for subregs of such pseudos. Note that
7440 we cannot use reg_equiv_mem in this case because it is
7441 not in the right mode. */
7444 if (GET_CODE (tmp
) == SUBREG
)
7445 tmp
= SUBREG_REG (tmp
);
7447 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7448 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
7449 || reg_equiv_constant
[REGNO (tmp
)] != 0))
7451 if (! reg_equiv_mem
[REGNO (tmp
)]
7452 || num_not_at_initial_offset
7453 || GET_CODE (oldequiv
) == SUBREG
)
7454 real_oldequiv
= rl
->in
;
7456 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
7460 if (GET_CODE (tmp
) == SUBREG
)
7461 tmp
= SUBREG_REG (tmp
);
7463 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7464 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
7465 || reg_equiv_constant
[REGNO (tmp
)] != 0))
7467 if (! reg_equiv_mem
[REGNO (tmp
)]
7468 || num_not_at_initial_offset
7469 || GET_CODE (old
) == SUBREG
)
7472 real_old
= reg_equiv_mem
[REGNO (tmp
)];
7475 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7476 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7478 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7480 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7481 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7482 /* We'd have to add more code for quartary reloads. */
7483 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7485 icode
= rl
->secondary_in_icode
;
7487 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7488 || (rl
->in
!= 0 && rl
->out
!= 0))
7490 secondary_reload_info sri
, sri2
;
7491 enum reg_class new_class
, new_t_class
;
7493 sri
.icode
= CODE_FOR_nothing
;
7494 sri
.prev_sri
= NULL
;
7496 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7500 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7501 second_reload_reg
= 0;
7502 else if (new_class
== NO_REGS
)
7504 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7506 (enum insn_code
) sri
.icode
))
7508 icode
= (enum insn_code
) sri
.icode
;
7509 third_reload_reg
= 0;
7514 real_oldequiv
= real_old
;
7517 else if (sri
.icode
!= CODE_FOR_nothing
)
7518 /* We currently lack a way to express this in reloads. */
7522 sri2
.icode
= CODE_FOR_nothing
;
7523 sri2
.prev_sri
= &sri
;
7525 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7528 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7530 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7534 third_reload_reg
= 0;
7535 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7540 real_oldequiv
= real_old
;
7543 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7545 rtx intermediate
= second_reload_reg
;
7547 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7549 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7553 second_reload_reg
= intermediate
;
7554 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7559 real_oldequiv
= real_old
;
7562 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7564 rtx intermediate
= second_reload_reg
;
7566 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7568 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7571 second_reload_reg
= intermediate
;
7572 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7577 real_oldequiv
= real_old
;
7582 /* This could be handled more intelligently too. */
7584 real_oldequiv
= real_old
;
7589 /* If we still need a secondary reload register, check
7590 to see if it is being used as a scratch or intermediate
7591 register and generate code appropriately. If we need
7592 a scratch register, use REAL_OLDEQUIV since the form of
7593 the insn may depend on the actual address if it is
7596 if (second_reload_reg
)
7598 if (icode
!= CODE_FOR_nothing
)
7600 /* We'd have to add extra code to handle this case. */
7601 gcc_assert (!third_reload_reg
);
7603 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7604 second_reload_reg
));
7609 /* See if we need a scratch register to load the
7610 intermediate register (a tertiary reload). */
7611 if (tertiary_icode
!= CODE_FOR_nothing
)
7613 emit_insn ((GEN_FCN (tertiary_icode
)
7614 (second_reload_reg
, real_oldequiv
,
7615 third_reload_reg
)));
7617 else if (third_reload_reg
)
7619 gen_reload (third_reload_reg
, real_oldequiv
,
7622 gen_reload (second_reload_reg
, third_reload_reg
,
7627 gen_reload (second_reload_reg
, real_oldequiv
,
7631 oldequiv
= second_reload_reg
;
7636 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7638 rtx real_oldequiv
= oldequiv
;
7640 if ((REG_P (oldequiv
)
7641 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7642 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
7643 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
7644 || (GET_CODE (oldequiv
) == SUBREG
7645 && REG_P (SUBREG_REG (oldequiv
))
7646 && (REGNO (SUBREG_REG (oldequiv
))
7647 >= FIRST_PSEUDO_REGISTER
)
7648 && ((reg_equiv_memory_loc
7649 [REGNO (SUBREG_REG (oldequiv
))] != 0)
7650 || (reg_equiv_constant
7651 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
7652 || (CONSTANT_P (oldequiv
)
7653 && (PREFERRED_RELOAD_CLASS (oldequiv
,
7654 REGNO_REG_CLASS (REGNO (reloadreg
)))
7656 real_oldequiv
= rl
->in
;
7657 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7661 if (cfun
->can_throw_non_call_exceptions
)
7662 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7664 /* End this sequence. */
7665 *where
= get_insns ();
7668 /* Update reload_override_in so that delete_address_reloads_1
7669 can see the actual register usage. */
7671 reload_override_in
[j
] = oldequiv
;
7674 /* Generate insns to for the output reload RL, which is for the insn described
7675 by CHAIN and has the number J. */
7677 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7681 rtx insn
= chain
->insn
;
7684 enum machine_mode mode
;
7688 if (rl
->when_needed
== RELOAD_OTHER
)
7691 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7693 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7694 mode
= GET_MODE (rl_reg_rtx
);
7696 reloadreg
= rl_reg_rtx
;
7698 /* If we need two reload regs, set RELOADREG to the intermediate
7699 one, since it will be stored into OLD. We might need a secondary
7700 register only for an input reload, so check again here. */
7702 if (rl
->secondary_out_reload
>= 0)
7705 int secondary_reload
= rl
->secondary_out_reload
;
7706 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7708 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7709 && reg_equiv_mem
[REGNO (old
)] != 0)
7710 real_old
= reg_equiv_mem
[REGNO (old
)];
7712 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7714 rtx second_reloadreg
= reloadreg
;
7715 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7717 /* See if RELOADREG is to be used as a scratch register
7718 or as an intermediate register. */
7719 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7721 /* We'd have to add extra code to handle this case. */
7722 gcc_assert (tertiary_reload
< 0);
7724 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7725 (real_old
, second_reloadreg
, reloadreg
)));
7730 /* See if we need both a scratch and intermediate reload
7733 enum insn_code tertiary_icode
7734 = rld
[secondary_reload
].secondary_out_icode
;
7736 /* We'd have to add more code for quartary reloads. */
7737 gcc_assert (tertiary_reload
< 0
7738 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7740 if (GET_MODE (reloadreg
) != mode
)
7741 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7743 if (tertiary_icode
!= CODE_FOR_nothing
)
7745 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7748 /* Copy primary reload reg to secondary reload reg.
7749 (Note that these have been swapped above, then
7750 secondary reload reg to OLD using our insn.) */
7752 /* If REAL_OLD is a paradoxical SUBREG, remove it
7753 and try to put the opposite SUBREG on
7755 if (GET_CODE (real_old
) == SUBREG
7756 && (GET_MODE_SIZE (GET_MODE (real_old
))
7757 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7758 && 0 != (tem
= gen_lowpart_common
7759 (GET_MODE (SUBREG_REG (real_old
)),
7761 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7763 gen_reload (reloadreg
, second_reloadreg
,
7764 rl
->opnum
, rl
->when_needed
);
7765 emit_insn ((GEN_FCN (tertiary_icode
)
7766 (real_old
, reloadreg
, third_reloadreg
)));
7772 /* Copy between the reload regs here and then to
7775 gen_reload (reloadreg
, second_reloadreg
,
7776 rl
->opnum
, rl
->when_needed
);
7777 if (tertiary_reload
>= 0)
7779 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7781 gen_reload (third_reloadreg
, reloadreg
,
7782 rl
->opnum
, rl
->when_needed
);
7783 reloadreg
= third_reloadreg
;
7790 /* Output the last reload insn. */
7795 /* Don't output the last reload if OLD is not the dest of
7796 INSN and is in the src and is clobbered by INSN. */
7797 if (! flag_expensive_optimizations
7799 || !(set
= single_set (insn
))
7800 || rtx_equal_p (old
, SET_DEST (set
))
7801 || !reg_mentioned_p (old
, SET_SRC (set
))
7802 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7803 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7804 gen_reload (old
, reloadreg
, rl
->opnum
,
7808 /* Look at all insns we emitted, just to be safe. */
7809 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7812 rtx pat
= PATTERN (p
);
7814 /* If this output reload doesn't come from a spill reg,
7815 clear any memory of reloaded copies of the pseudo reg.
7816 If this output reload comes from a spill reg,
7817 reg_has_output_reload will make this do nothing. */
7818 note_stores (pat
, forget_old_reloads_1
, NULL
);
7820 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7822 rtx set
= single_set (insn
);
7823 if (reload_spill_index
[j
] < 0
7825 && SET_SRC (set
) == rl_reg_rtx
)
7827 int src
= REGNO (SET_SRC (set
));
7829 reload_spill_index
[j
] = src
;
7830 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7831 if (find_regno_note (insn
, REG_DEAD
, src
))
7832 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7834 if (HARD_REGISTER_P (rl_reg_rtx
))
7836 int s
= rl
->secondary_out_reload
;
7837 set
= single_set (p
);
7838 /* If this reload copies only to the secondary reload
7839 register, the secondary reload does the actual
7841 if (s
>= 0 && set
== NULL_RTX
)
7842 /* We can't tell what function the secondary reload
7843 has and where the actual store to the pseudo is
7844 made; leave new_spill_reg_store alone. */
7847 && SET_SRC (set
) == rl_reg_rtx
7848 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7850 /* Usually the next instruction will be the
7851 secondary reload insn; if we can confirm
7852 that it is, setting new_spill_reg_store to
7853 that insn will allow an extra optimization. */
7854 rtx s_reg
= rld
[s
].reg_rtx
;
7855 rtx next
= NEXT_INSN (p
);
7856 rld
[s
].out
= rl
->out
;
7857 rld
[s
].out_reg
= rl
->out_reg
;
7858 set
= single_set (next
);
7859 if (set
&& SET_SRC (set
) == s_reg
7860 && ! new_spill_reg_store
[REGNO (s_reg
)])
7862 SET_HARD_REG_BIT (reg_is_output_reload
,
7864 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7868 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7873 if (rl
->when_needed
== RELOAD_OTHER
)
7875 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7876 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7879 output_reload_insns
[rl
->opnum
] = get_insns ();
7881 if (cfun
->can_throw_non_call_exceptions
)
7882 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7887 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7888 and has the number J. */
7890 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7892 rtx insn
= chain
->insn
;
7893 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7894 ? rl
->in_reg
: rl
->in
);
7895 rtx reg_rtx
= rl
->reg_rtx
;
7899 enum machine_mode mode
;
7901 /* Determine the mode to reload in.
7902 This is very tricky because we have three to choose from.
7903 There is the mode the insn operand wants (rl->inmode).
7904 There is the mode of the reload register RELOADREG.
7905 There is the intrinsic mode of the operand, which we could find
7906 by stripping some SUBREGs.
7907 It turns out that RELOADREG's mode is irrelevant:
7908 we can change that arbitrarily.
7910 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7911 then the reload reg may not support QImode moves, so use SImode.
7912 If foo is in memory due to spilling a pseudo reg, this is safe,
7913 because the QImode value is in the least significant part of a
7914 slot big enough for a SImode. If foo is some other sort of
7915 memory reference, then it is impossible to reload this case,
7916 so previous passes had better make sure this never happens.
7918 Then consider a one-word union which has SImode and one of its
7919 members is a float, being fetched as (SUBREG:SF union:SI).
7920 We must fetch that as SFmode because we could be loading into
7921 a float-only register. In this case OLD's mode is correct.
7923 Consider an immediate integer: it has VOIDmode. Here we need
7924 to get a mode from something else.
7926 In some cases, there is a fourth mode, the operand's
7927 containing mode. If the insn specifies a containing mode for
7928 this operand, it overrides all others.
7930 I am not sure whether the algorithm here is always right,
7931 but it does the right things in those cases. */
7933 mode
= GET_MODE (old
);
7934 if (mode
== VOIDmode
)
7937 /* We cannot use gen_lowpart_common since it can do the wrong thing
7938 when REG_RTX has a multi-word mode. Note that REG_RTX must
7939 always be a REG here. */
7940 if (GET_MODE (reg_rtx
) != mode
)
7941 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7943 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7946 /* AUTO_INC reloads need to be handled even if inherited. We got an
7947 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7948 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7949 && ! rtx_equal_p (reg_rtx
, old
)
7951 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7953 /* When inheriting a wider reload, we have a MEM in rl->in,
7954 e.g. inheriting a SImode output reload for
7955 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7956 if (optimize
&& reload_inherited
[j
] && rl
->in
7958 && MEM_P (rl
->in_reg
)
7959 && reload_spill_index
[j
] >= 0
7960 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7961 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7963 /* If we are reloading a register that was recently stored in with an
7964 output-reload, see if we can prove there was
7965 actually no need to store the old value in it. */
7968 && (reload_inherited
[j
] || reload_override_in
[j
])
7971 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7973 /* There doesn't seem to be any reason to restrict this to pseudos
7974 and doing so loses in the case where we are copying from a
7975 register of the wrong class. */
7976 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7978 /* The insn might have already some references to stackslots
7979 replaced by MEMs, while reload_out_reg still names the
7981 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7982 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7983 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7986 /* Do output reloading for reload RL, which is for the insn described by
7987 CHAIN and has the number J.
7988 ??? At some point we need to support handling output reloads of
7989 JUMP_INSNs or insns that set cc0. */
7991 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7994 rtx insn
= chain
->insn
;
7995 /* If this is an output reload that stores something that is
7996 not loaded in this same reload, see if we can eliminate a previous
7998 rtx pseudo
= rl
->out_reg
;
7999 rtx reg_rtx
= rl
->reg_rtx
;
8001 if (rl
->out
&& reg_rtx
)
8003 enum machine_mode mode
;
8005 /* Determine the mode to reload in.
8006 See comments above (for input reloading). */
8007 mode
= GET_MODE (rl
->out
);
8008 if (mode
== VOIDmode
)
8010 /* VOIDmode should never happen for an output. */
8011 if (asm_noperands (PATTERN (insn
)) < 0)
8012 /* It's the compiler's fault. */
8013 fatal_insn ("VOIDmode on an output", insn
);
8014 error_for_asm (insn
, "output operand is constant in %<asm%>");
8015 /* Prevent crash--use something we know is valid. */
8017 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
8019 if (GET_MODE (reg_rtx
) != mode
)
8020 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
8022 reload_reg_rtx_for_output
[j
] = reg_rtx
;
8027 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
8028 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
8029 && reg_last_reload_reg
[REGNO (pseudo
)])
8031 int pseudo_no
= REGNO (pseudo
);
8032 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
8034 /* We don't need to test full validity of last_regno for
8035 inherit here; we only want to know if the store actually
8036 matches the pseudo. */
8037 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8038 && reg_reloaded_contents
[last_regno
] == pseudo_no
8039 && spill_reg_store
[last_regno
]
8040 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8041 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8047 || rtx_equal_p (old
, reg_rtx
))
8050 /* An output operand that dies right away does need a reload,
8051 but need not be copied from it. Show the new location in the
8053 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8054 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8056 XEXP (note
, 0) = reg_rtx
;
8059 /* Likewise for a SUBREG of an operand that dies. */
8060 else if (GET_CODE (old
) == SUBREG
8061 && REG_P (SUBREG_REG (old
))
8062 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8065 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8068 else if (GET_CODE (old
) == SCRATCH
)
8069 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8070 but we don't want to make an output reload. */
8073 /* If is a JUMP_INSN, we can't support output reloads yet. */
8074 gcc_assert (NONJUMP_INSN_P (insn
));
8076 emit_output_reload_insns (chain
, rld
+ j
, j
);
8079 /* A reload copies values of MODE from register SRC to register DEST.
8080 Return true if it can be treated for inheritance purposes like a
8081 group of reloads, each one reloading a single hard register. The
8082 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8083 occupy the same number of hard registers. */
8086 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8087 int src ATTRIBUTE_UNUSED
,
8088 enum machine_mode mode ATTRIBUTE_UNUSED
)
8090 #ifdef CANNOT_CHANGE_MODE_CLASS
8091 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8092 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8098 /* Output insns to reload values in and out of the chosen reload regs. */
8101 emit_reload_insns (struct insn_chain
*chain
)
8103 rtx insn
= chain
->insn
;
8107 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8109 for (j
= 0; j
< reload_n_operands
; j
++)
8110 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8111 = inpaddr_address_reload_insns
[j
]
8112 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8113 = outaddr_address_reload_insns
[j
]
8114 = other_output_reload_insns
[j
] = 0;
8115 other_input_address_reload_insns
= 0;
8116 other_input_reload_insns
= 0;
8117 operand_reload_insns
= 0;
8118 other_operand_reload_insns
= 0;
8120 /* Dump reloads into the dump file. */
8123 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8124 debug_reload_to_stream (dump_file
);
8127 /* Now output the instructions to copy the data into and out of the
8128 reload registers. Do these in the order that the reloads were reported,
8129 since reloads of base and index registers precede reloads of operands
8130 and the operands may need the base and index registers reloaded. */
8132 for (j
= 0; j
< n_reloads
; j
++)
8134 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8138 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8139 new_spill_reg_store
[i
] = 0;
8142 do_input_reload (chain
, rld
+ j
, j
);
8143 do_output_reload (chain
, rld
+ j
, j
);
8146 /* Now write all the insns we made for reloads in the order expected by
8147 the allocation functions. Prior to the insn being reloaded, we write
8148 the following reloads:
8150 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8152 RELOAD_OTHER reloads.
8154 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8155 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8156 RELOAD_FOR_INPUT reload for the operand.
8158 RELOAD_FOR_OPADDR_ADDRS reloads.
8160 RELOAD_FOR_OPERAND_ADDRESS reloads.
8162 After the insn being reloaded, we write the following:
8164 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8165 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8166 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8167 reloads for the operand. The RELOAD_OTHER output reloads are
8168 output in descending order by reload number. */
8170 emit_insn_before (other_input_address_reload_insns
, insn
);
8171 emit_insn_before (other_input_reload_insns
, insn
);
8173 for (j
= 0; j
< reload_n_operands
; j
++)
8175 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8176 emit_insn_before (input_address_reload_insns
[j
], insn
);
8177 emit_insn_before (input_reload_insns
[j
], insn
);
8180 emit_insn_before (other_operand_reload_insns
, insn
);
8181 emit_insn_before (operand_reload_insns
, insn
);
8183 for (j
= 0; j
< reload_n_operands
; j
++)
8185 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8186 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8187 x
= emit_insn_after (output_reload_insns
[j
], x
);
8188 emit_insn_after (other_output_reload_insns
[j
], x
);
8191 /* For all the spill regs newly reloaded in this instruction,
8192 record what they were reloaded from, so subsequent instructions
8193 can inherit the reloads.
8195 Update spill_reg_store for the reloads of this insn.
8196 Copy the elements that were updated in the loop above. */
8198 for (j
= 0; j
< n_reloads
; j
++)
8200 int r
= reload_order
[j
];
8201 int i
= reload_spill_index
[r
];
8203 /* If this is a non-inherited input reload from a pseudo, we must
8204 clear any memory of a previous store to the same pseudo. Only do
8205 something if there will not be an output reload for the pseudo
8207 if (rld
[r
].in_reg
!= 0
8208 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8210 rtx reg
= rld
[r
].in_reg
;
8212 if (GET_CODE (reg
) == SUBREG
)
8213 reg
= SUBREG_REG (reg
);
8216 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8217 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8219 int nregno
= REGNO (reg
);
8221 if (reg_last_reload_reg
[nregno
])
8223 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8225 if (reg_reloaded_contents
[last_regno
] == nregno
)
8226 spill_reg_store
[last_regno
] = 0;
8231 /* I is nonneg if this reload used a register.
8232 If rld[r].reg_rtx is 0, this is an optional reload
8233 that we opted to ignore. */
8235 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8237 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8240 /* For a multi register reload, we need to check if all or part
8241 of the value lives to the end. */
8242 for (k
= 0; k
< nr
; k
++)
8243 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
8244 rld
[r
].when_needed
))
8245 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8247 /* Maybe the spill reg contains a copy of reload_out. */
8249 && (REG_P (rld
[r
].out
)
8253 || REG_P (rld
[r
].out_reg
)))
8256 enum machine_mode mode
;
8259 reg
= reload_reg_rtx_for_output
[r
];
8260 mode
= GET_MODE (reg
);
8261 regno
= REGNO (reg
);
8262 nregs
= hard_regno_nregs
[regno
][mode
];
8263 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
8264 rld
[r
].when_needed
))
8266 rtx out
= (REG_P (rld
[r
].out
)
8270 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8271 int out_regno
= REGNO (out
);
8272 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8273 : hard_regno_nregs
[out_regno
][mode
]);
8276 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8277 spill_reg_stored_to
[regno
] = out
;
8278 reg_last_reload_reg
[out_regno
] = reg
;
8280 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8281 && nregs
== out_nregs
8282 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8284 /* If OUT_REGNO is a hard register, it may occupy more than
8285 one register. If it does, say what is in the
8286 rest of the registers assuming that both registers
8287 agree on how many words the object takes. If not,
8288 invalidate the subsequent registers. */
8290 if (HARD_REGISTER_NUM_P (out_regno
))
8291 for (k
= 1; k
< out_nregs
; k
++)
8292 reg_last_reload_reg
[out_regno
+ k
]
8293 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8295 /* Now do the inverse operation. */
8296 for (k
= 0; k
< nregs
; k
++)
8298 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8299 reg_reloaded_contents
[regno
+ k
]
8300 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8303 reg_reloaded_insn
[regno
+ k
] = insn
;
8304 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8305 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8306 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8309 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8314 /* Maybe the spill reg contains a copy of reload_in. Only do
8315 something if there will not be an output reload for
8316 the register being reloaded. */
8317 else if (rld
[r
].out_reg
== 0
8319 && ((REG_P (rld
[r
].in
)
8320 && !HARD_REGISTER_P (rld
[r
].in
)
8321 && !REGNO_REG_SET_P (®_has_output_reload
,
8323 || (REG_P (rld
[r
].in_reg
)
8324 && !REGNO_REG_SET_P (®_has_output_reload
,
8325 REGNO (rld
[r
].in_reg
))))
8326 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8329 enum machine_mode mode
;
8332 reg
= reload_reg_rtx_for_input
[r
];
8333 mode
= GET_MODE (reg
);
8334 regno
= REGNO (reg
);
8335 nregs
= hard_regno_nregs
[regno
][mode
];
8336 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
8337 rld
[r
].when_needed
))
8344 if (REG_P (rld
[r
].in
)
8345 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8347 else if (REG_P (rld
[r
].in_reg
))
8350 in
= XEXP (rld
[r
].in_reg
, 0);
8351 in_regno
= REGNO (in
);
8353 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8354 : hard_regno_nregs
[in_regno
][mode
]);
8356 reg_last_reload_reg
[in_regno
] = reg
;
8358 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8359 && nregs
== in_nregs
8360 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8362 if (HARD_REGISTER_NUM_P (in_regno
))
8363 for (k
= 1; k
< in_nregs
; k
++)
8364 reg_last_reload_reg
[in_regno
+ k
]
8365 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8367 /* Unless we inherited this reload, show we haven't
8368 recently done a store.
8369 Previous stores of inherited auto_inc expressions
8370 also have to be discarded. */
8371 if (! reload_inherited
[r
]
8372 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8373 spill_reg_store
[regno
] = 0;
8375 for (k
= 0; k
< nregs
; k
++)
8377 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8378 reg_reloaded_contents
[regno
+ k
]
8379 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8382 reg_reloaded_insn
[regno
+ k
] = insn
;
8383 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8384 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8385 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8388 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8395 /* The following if-statement was #if 0'd in 1.34 (or before...).
8396 It's reenabled in 1.35 because supposedly nothing else
8397 deals with this problem. */
8399 /* If a register gets output-reloaded from a non-spill register,
8400 that invalidates any previous reloaded copy of it.
8401 But forget_old_reloads_1 won't get to see it, because
8402 it thinks only about the original insn. So invalidate it here.
8403 Also do the same thing for RELOAD_OTHER constraints where the
8404 output is discarded. */
8406 && ((rld
[r
].out
!= 0
8407 && (REG_P (rld
[r
].out
)
8408 || (MEM_P (rld
[r
].out
)
8409 && REG_P (rld
[r
].out_reg
))))
8410 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8411 && REG_P (rld
[r
].out_reg
))))
8413 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8414 ? rld
[r
].out
: rld
[r
].out_reg
);
8415 int out_regno
= REGNO (out
);
8416 enum machine_mode mode
= GET_MODE (out
);
8418 /* REG_RTX is now set or clobbered by the main instruction.
8419 As the comment above explains, forget_old_reloads_1 only
8420 sees the original instruction, and there is no guarantee
8421 that the original instruction also clobbered REG_RTX.
8422 For example, if find_reloads sees that the input side of
8423 a matched operand pair dies in this instruction, it may
8424 use the input register as the reload register.
8426 Calling forget_old_reloads_1 is a waste of effort if
8427 REG_RTX is also the output register.
8429 If we know that REG_RTX holds the value of a pseudo
8430 register, the code after the call will record that fact. */
8431 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8432 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8434 if (!HARD_REGISTER_NUM_P (out_regno
))
8436 rtx src_reg
, store_insn
= NULL_RTX
;
8438 reg_last_reload_reg
[out_regno
] = 0;
8440 /* If we can find a hard register that is stored, record
8441 the storing insn so that we may delete this insn with
8442 delete_output_reload. */
8443 src_reg
= reload_reg_rtx_for_output
[r
];
8445 /* If this is an optional reload, try to find the source reg
8446 from an input reload. */
8449 rtx set
= single_set (insn
);
8450 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8454 src_reg
= SET_SRC (set
);
8456 for (k
= 0; k
< n_reloads
; k
++)
8458 if (rld
[k
].in
== src_reg
)
8460 src_reg
= reload_reg_rtx_for_input
[k
];
8467 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8468 if (src_reg
&& REG_P (src_reg
)
8469 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8471 int src_regno
, src_nregs
, k
;
8474 gcc_assert (GET_MODE (src_reg
) == mode
);
8475 src_regno
= REGNO (src_reg
);
8476 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8477 /* The place where to find a death note varies with
8478 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8479 necessarily checked exactly in the code that moves
8480 notes, so just check both locations. */
8481 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8482 if (! note
&& store_insn
)
8483 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8484 for (k
= 0; k
< src_nregs
; k
++)
8486 spill_reg_store
[src_regno
+ k
] = store_insn
;
8487 spill_reg_stored_to
[src_regno
+ k
] = out
;
8488 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8489 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8490 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8491 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8492 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8494 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8497 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8499 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8501 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8503 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8505 reg_last_reload_reg
[out_regno
] = src_reg
;
8506 /* We have to set reg_has_output_reload here, or else
8507 forget_old_reloads_1 will clear reg_last_reload_reg
8509 SET_REGNO_REG_SET (®_has_output_reload
,
8515 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8517 for (k
= 0; k
< out_nregs
; k
++)
8518 reg_last_reload_reg
[out_regno
+ k
] = 0;
8522 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8525 /* Go through the motions to emit INSN and test if it is strictly valid.
8526 Return the emitted insn if valid, else return NULL. */
8529 emit_insn_if_valid_for_reload (rtx insn
)
8531 rtx last
= get_last_insn ();
8534 insn
= emit_insn (insn
);
8535 code
= recog_memoized (insn
);
8539 extract_insn (insn
);
8540 /* We want constrain operands to treat this insn strictly in its
8541 validity determination, i.e., the way it would after reload has
8543 if (constrain_operands (1))
8547 delete_insns_since (last
);
8551 /* Emit code to perform a reload from IN (which may be a reload register) to
8552 OUT (which may also be a reload register). IN or OUT is from operand
8553 OPNUM with reload type TYPE.
8555 Returns first insn emitted. */
8558 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8560 rtx last
= get_last_insn ();
8563 /* If IN is a paradoxical SUBREG, remove it and try to put the
8564 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8565 if (GET_CODE (in
) == SUBREG
8566 && (GET_MODE_SIZE (GET_MODE (in
))
8567 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
8568 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
8569 in
= SUBREG_REG (in
), out
= tem
;
8570 else if (GET_CODE (out
) == SUBREG
8571 && (GET_MODE_SIZE (GET_MODE (out
))
8572 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
8573 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
8574 out
= SUBREG_REG (out
), in
= tem
;
8576 /* How to do this reload can get quite tricky. Normally, we are being
8577 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8578 register that didn't get a hard register. In that case we can just
8579 call emit_move_insn.
8581 We can also be asked to reload a PLUS that adds a register or a MEM to
8582 another register, constant or MEM. This can occur during frame pointer
8583 elimination and while reloading addresses. This case is handled by
8584 trying to emit a single insn to perform the add. If it is not valid,
8585 we use a two insn sequence.
8587 Or we can be asked to reload an unary operand that was a fragment of
8588 an addressing mode, into a register. If it isn't recognized as-is,
8589 we try making the unop operand and the reload-register the same:
8590 (set reg:X (unop:X expr:Y))
8591 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8593 Finally, we could be called to handle an 'o' constraint by putting
8594 an address into a register. In that case, we first try to do this
8595 with a named pattern of "reload_load_address". If no such pattern
8596 exists, we just emit a SET insn and hope for the best (it will normally
8597 be valid on machines that use 'o').
8599 This entire process is made complex because reload will never
8600 process the insns we generate here and so we must ensure that
8601 they will fit their constraints and also by the fact that parts of
8602 IN might be being reloaded separately and replaced with spill registers.
8603 Because of this, we are, in some sense, just guessing the right approach
8604 here. The one listed above seems to work.
8606 ??? At some point, this whole thing needs to be rethought. */
8608 if (GET_CODE (in
) == PLUS
8609 && (REG_P (XEXP (in
, 0))
8610 || GET_CODE (XEXP (in
, 0)) == SUBREG
8611 || MEM_P (XEXP (in
, 0)))
8612 && (REG_P (XEXP (in
, 1))
8613 || GET_CODE (XEXP (in
, 1)) == SUBREG
8614 || CONSTANT_P (XEXP (in
, 1))
8615 || MEM_P (XEXP (in
, 1))))
8617 /* We need to compute the sum of a register or a MEM and another
8618 register, constant, or MEM, and put it into the reload
8619 register. The best possible way of doing this is if the machine
8620 has a three-operand ADD insn that accepts the required operands.
8622 The simplest approach is to try to generate such an insn and see if it
8623 is recognized and matches its constraints. If so, it can be used.
8625 It might be better not to actually emit the insn unless it is valid,
8626 but we need to pass the insn as an operand to `recog' and
8627 `extract_insn' and it is simpler to emit and then delete the insn if
8628 not valid than to dummy things up. */
8630 rtx op0
, op1
, tem
, insn
;
8633 op0
= find_replacement (&XEXP (in
, 0));
8634 op1
= find_replacement (&XEXP (in
, 1));
8636 /* Since constraint checking is strict, commutativity won't be
8637 checked, so we need to do that here to avoid spurious failure
8638 if the add instruction is two-address and the second operand
8639 of the add is the same as the reload reg, which is frequently
8640 the case. If the insn would be A = B + A, rearrange it so
8641 it will be A = A + B as constrain_operands expects. */
8643 if (REG_P (XEXP (in
, 1))
8644 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8645 tem
= op0
, op0
= op1
, op1
= tem
;
8647 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8648 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8650 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8654 /* If that failed, we must use a conservative two-insn sequence.
8656 Use a move to copy one operand into the reload register. Prefer
8657 to reload a constant, MEM or pseudo since the move patterns can
8658 handle an arbitrary operand. If OP1 is not a constant, MEM or
8659 pseudo and OP1 is not a valid operand for an add instruction, then
8662 After reloading one of the operands into the reload register, add
8663 the reload register to the output register.
8665 If there is another way to do this for a specific machine, a
8666 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8669 code
= (int) optab_handler (add_optab
, GET_MODE (out
));
8671 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8673 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8674 || (code
!= CODE_FOR_nothing
8675 && ! ((*insn_data
[code
].operand
[2].predicate
)
8676 (op1
, insn_data
[code
].operand
[2].mode
))))
8677 tem
= op0
, op0
= op1
, op1
= tem
;
8679 gen_reload (out
, op0
, opnum
, type
);
8681 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8682 This fixes a problem on the 32K where the stack pointer cannot
8683 be used as an operand of an add insn. */
8685 if (rtx_equal_p (op0
, op1
))
8688 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8691 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8692 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8696 /* If that failed, copy the address register to the reload register.
8697 Then add the constant to the reload register. */
8699 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8700 gen_reload (out
, op1
, opnum
, type
);
8701 insn
= emit_insn (gen_add2_insn (out
, op0
));
8702 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8705 #ifdef SECONDARY_MEMORY_NEEDED
8706 /* If we need a memory location to do the move, do it that way. */
8707 else if ((REG_P (in
)
8708 || (GET_CODE (in
) == SUBREG
&& REG_P (SUBREG_REG (in
))))
8709 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
8711 || (GET_CODE (out
) == SUBREG
&& REG_P (SUBREG_REG (out
))))
8712 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
8713 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
8714 REGNO_REG_CLASS (reg_or_subregno (out
)),
8717 /* Get the memory to use and rewrite both registers to its mode. */
8718 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8720 if (GET_MODE (loc
) != GET_MODE (out
))
8721 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
8723 if (GET_MODE (loc
) != GET_MODE (in
))
8724 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
8726 gen_reload (loc
, in
, opnum
, type
);
8727 gen_reload (out
, loc
, opnum
, type
);
8730 else if (REG_P (out
) && UNARY_P (in
))
8737 op1
= find_replacement (&XEXP (in
, 0));
8738 if (op1
!= XEXP (in
, 0))
8739 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8741 /* First, try a plain SET. */
8742 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8746 /* If that failed, move the inner operand to the reload
8747 register, and try the same unop with the inner expression
8748 replaced with the reload register. */
8750 if (GET_MODE (op1
) != GET_MODE (out
))
8751 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8755 gen_reload (out_moded
, op1
, opnum
, type
);
8758 = gen_rtx_SET (VOIDmode
, out
,
8759 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8761 insn
= emit_insn_if_valid_for_reload (insn
);
8764 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8768 fatal_insn ("Failure trying to reload:", set
);
8770 /* If IN is a simple operand, use gen_move_insn. */
8771 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8773 tem
= emit_insn (gen_move_insn (out
, in
));
8774 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8775 mark_jump_label (in
, tem
, 0);
8778 #ifdef HAVE_reload_load_address
8779 else if (HAVE_reload_load_address
)
8780 emit_insn (gen_reload_load_address (out
, in
));
8783 /* Otherwise, just write (set OUT IN) and hope for the best. */
8785 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8787 /* Return the first insn emitted.
8788 We can not just return get_last_insn, because there may have
8789 been multiple instructions emitted. Also note that gen_move_insn may
8790 emit more than one insn itself, so we can not assume that there is one
8791 insn emitted per emit_insn_before call. */
8793 return last
? NEXT_INSN (last
) : get_insns ();
8796 /* Delete a previously made output-reload whose result we now believe
8797 is not needed. First we double-check.
8799 INSN is the insn now being processed.
8800 LAST_RELOAD_REG is the hard register number for which we want to delete
8801 the last output reload.
8802 J is the reload-number that originally used REG. The caller has made
8803 certain that reload J doesn't use REG any longer for input.
8804 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8807 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8809 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8810 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8813 int n_inherited
= 0;
8817 /* It is possible that this reload has been only used to set another reload
8818 we eliminated earlier and thus deleted this instruction too. */
8819 if (INSN_DELETED_P (output_reload_insn
))
8822 /* Get the raw pseudo-register referred to. */
8824 while (GET_CODE (reg
) == SUBREG
)
8825 reg
= SUBREG_REG (reg
);
8826 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
8828 /* This is unsafe if the operand occurs more often in the current
8829 insn than it is inherited. */
8830 for (k
= n_reloads
- 1; k
>= 0; k
--)
8832 rtx reg2
= rld
[k
].in
;
8835 if (MEM_P (reg2
) || reload_override_in
[k
])
8836 reg2
= rld
[k
].in_reg
;
8838 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8839 reg2
= XEXP (rld
[k
].in_reg
, 0);
8841 while (GET_CODE (reg2
) == SUBREG
)
8842 reg2
= SUBREG_REG (reg2
);
8843 if (rtx_equal_p (reg2
, reg
))
8845 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8851 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8852 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8853 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8856 n_occurrences
+= count_occurrences (PATTERN (insn
),
8857 eliminate_regs (substed
, VOIDmode
,
8859 for (i1
= reg_equiv_alt_mem_list
[REGNO (reg
)]; i1
; i1
= XEXP (i1
, 1))
8861 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8862 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8864 if (n_occurrences
> n_inherited
)
8867 /* If the pseudo-reg we are reloading is no longer referenced
8868 anywhere between the store into it and here,
8869 and we're within the same basic block, then the value can only
8870 pass through the reload reg and end up here.
8871 Otherwise, give up--return. */
8872 for (i1
= NEXT_INSN (output_reload_insn
);
8873 i1
!= insn
; i1
= NEXT_INSN (i1
))
8875 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8877 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8878 && reg_mentioned_p (reg
, PATTERN (i1
)))
8880 /* If this is USE in front of INSN, we only have to check that
8881 there are no more references than accounted for by inheritance. */
8882 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8884 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8885 i1
= NEXT_INSN (i1
);
8887 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8893 /* We will be deleting the insn. Remove the spill reg information. */
8894 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8896 spill_reg_store
[last_reload_reg
+ k
] = 0;
8897 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8900 /* The caller has already checked that REG dies or is set in INSN.
8901 It has also checked that we are optimizing, and thus some
8902 inaccuracies in the debugging information are acceptable.
8903 So we could just delete output_reload_insn. But in some cases
8904 we can improve the debugging information without sacrificing
8905 optimization - maybe even improving the code: See if the pseudo
8906 reg has been completely replaced with reload regs. If so, delete
8907 the store insn and forget we had a stack slot for the pseudo. */
8908 if (rld
[j
].out
!= rld
[j
].in
8909 && REG_N_DEATHS (REGNO (reg
)) == 1
8910 && REG_N_SETS (REGNO (reg
)) == 1
8911 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8912 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8916 /* We know that it was used only between here and the beginning of
8917 the current basic block. (We also know that the last use before
8918 INSN was the output reload we are thinking of deleting, but never
8919 mind that.) Search that range; see if any ref remains. */
8920 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8922 rtx set
= single_set (i2
);
8924 /* Uses which just store in the pseudo don't count,
8925 since if they are the only uses, they are dead. */
8926 if (set
!= 0 && SET_DEST (set
) == reg
)
8931 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8932 && reg_mentioned_p (reg
, PATTERN (i2
)))
8934 /* Some other ref remains; just delete the output reload we
8936 delete_address_reloads (output_reload_insn
, insn
);
8937 delete_insn (output_reload_insn
);
8942 /* Delete the now-dead stores into this pseudo. Note that this
8943 loop also takes care of deleting output_reload_insn. */
8944 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8946 rtx set
= single_set (i2
);
8948 if (set
!= 0 && SET_DEST (set
) == reg
)
8950 delete_address_reloads (i2
, insn
);
8958 /* For the debugging info, say the pseudo lives in this reload reg. */
8959 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8960 if (ira_conflicts_p
)
8961 /* Inform IRA about the change. */
8962 ira_mark_allocation_change (REGNO (reg
));
8963 alter_reg (REGNO (reg
), -1, false);
8967 delete_address_reloads (output_reload_insn
, insn
);
8968 delete_insn (output_reload_insn
);
8972 /* We are going to delete DEAD_INSN. Recursively delete loads of
8973 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8974 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8976 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8978 rtx set
= single_set (dead_insn
);
8979 rtx set2
, dst
, prev
, next
;
8982 rtx dst
= SET_DEST (set
);
8984 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8986 /* If we deleted the store from a reloaded post_{in,de}c expression,
8987 we can delete the matching adds. */
8988 prev
= PREV_INSN (dead_insn
);
8989 next
= NEXT_INSN (dead_insn
);
8990 if (! prev
|| ! next
)
8992 set
= single_set (next
);
8993 set2
= single_set (prev
);
8995 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8996 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8997 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8999 dst
= SET_DEST (set
);
9000 if (! rtx_equal_p (dst
, SET_DEST (set2
))
9001 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
9002 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
9003 || (INTVAL (XEXP (SET_SRC (set
), 1))
9004 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
9006 delete_related_insns (prev
);
9007 delete_related_insns (next
);
9010 /* Subfunction of delete_address_reloads: process registers found in X. */
9012 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
9014 rtx prev
, set
, dst
, i2
;
9016 enum rtx_code code
= GET_CODE (x
);
9020 const char *fmt
= GET_RTX_FORMAT (code
);
9021 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9024 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9025 else if (fmt
[i
] == 'E')
9027 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9028 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9035 if (spill_reg_order
[REGNO (x
)] < 0)
9038 /* Scan backwards for the insn that sets x. This might be a way back due
9040 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9042 code
= GET_CODE (prev
);
9043 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9047 if (reg_set_p (x
, PATTERN (prev
)))
9049 if (reg_referenced_p (x
, PATTERN (prev
)))
9052 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9054 /* Check that PREV only sets the reload register. */
9055 set
= single_set (prev
);
9058 dst
= SET_DEST (set
);
9060 || ! rtx_equal_p (dst
, x
))
9062 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9064 /* Check if DST was used in a later insn -
9065 it might have been inherited. */
9066 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9072 if (reg_referenced_p (dst
, PATTERN (i2
)))
9074 /* If there is a reference to the register in the current insn,
9075 it might be loaded in a non-inherited reload. If no other
9076 reload uses it, that means the register is set before
9078 if (i2
== current_insn
)
9080 for (j
= n_reloads
- 1; j
>= 0; j
--)
9081 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9082 || reload_override_in
[j
] == dst
)
9084 for (j
= n_reloads
- 1; j
>= 0; j
--)
9085 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9094 /* If DST is still live at CURRENT_INSN, check if it is used for
9095 any reload. Note that even if CURRENT_INSN sets DST, we still
9096 have to check the reloads. */
9097 if (i2
== current_insn
)
9099 for (j
= n_reloads
- 1; j
>= 0; j
--)
9100 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9101 || reload_override_in
[j
] == dst
)
9103 /* ??? We can't finish the loop here, because dst might be
9104 allocated to a pseudo in this block if no reload in this
9105 block needs any of the classes containing DST - see
9106 spill_hard_reg. There is no easy way to tell this, so we
9107 have to scan till the end of the basic block. */
9109 if (reg_set_p (dst
, PATTERN (i2
)))
9113 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9114 reg_reloaded_contents
[REGNO (dst
)] = -1;
9118 /* Output reload-insns to reload VALUE into RELOADREG.
9119 VALUE is an autoincrement or autodecrement RTX whose operand
9120 is a register or memory location;
9121 so reloading involves incrementing that location.
9122 IN is either identical to VALUE, or some cheaper place to reload from.
9124 INC_AMOUNT is the number to increment or decrement by (always positive).
9125 This cannot be deduced from VALUE.
9127 Return the instruction that stores into RELOADREG. */
9130 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9132 /* REG or MEM to be copied and incremented. */
9133 rtx incloc
= find_replacement (&XEXP (value
, 0));
9134 /* Nonzero if increment after copying. */
9135 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9136 || GET_CODE (value
) == POST_MODIFY
);
9142 rtx real_in
= in
== value
? incloc
: in
;
9144 /* No hard register is equivalent to this register after
9145 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9146 we could inc/dec that register as well (maybe even using it for
9147 the source), but I'm not sure it's worth worrying about. */
9149 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9151 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9153 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9154 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9158 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9159 inc_amount
= -inc_amount
;
9161 inc
= GEN_INT (inc_amount
);
9164 /* If this is post-increment, first copy the location to the reload reg. */
9165 if (post
&& real_in
!= reloadreg
)
9166 emit_insn (gen_move_insn (reloadreg
, real_in
));
9170 /* See if we can directly increment INCLOC. Use a method similar to
9171 that in gen_reload. */
9173 last
= get_last_insn ();
9174 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9175 gen_rtx_PLUS (GET_MODE (incloc
),
9178 code
= recog_memoized (add_insn
);
9181 extract_insn (add_insn
);
9182 if (constrain_operands (1))
9184 /* If this is a pre-increment and we have incremented the value
9185 where it lives, copy the incremented value to RELOADREG to
9186 be used as an address. */
9189 emit_insn (gen_move_insn (reloadreg
, incloc
));
9194 delete_insns_since (last
);
9197 /* If couldn't do the increment directly, must increment in RELOADREG.
9198 The way we do this depends on whether this is pre- or post-increment.
9199 For pre-increment, copy INCLOC to the reload register, increment it
9200 there, then save back. */
9204 if (in
!= reloadreg
)
9205 emit_insn (gen_move_insn (reloadreg
, real_in
));
9206 emit_insn (gen_add2_insn (reloadreg
, inc
));
9207 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
9212 Because this might be a jump insn or a compare, and because RELOADREG
9213 may not be available after the insn in an input reload, we must do
9214 the incrementation before the insn being reloaded for.
9216 We have already copied IN to RELOADREG. Increment the copy in
9217 RELOADREG, save that back, then decrement RELOADREG so it has
9218 the original value. */
9220 emit_insn (gen_add2_insn (reloadreg
, inc
));
9221 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
9222 if (CONST_INT_P (inc
))
9223 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
9225 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9233 add_auto_inc_notes (rtx insn
, rtx x
)
9235 enum rtx_code code
= GET_CODE (x
);
9239 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9241 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9245 /* Scan all the operand sub-expressions. */
9246 fmt
= GET_RTX_FORMAT (code
);
9247 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9250 add_auto_inc_notes (insn
, XEXP (x
, i
));
9251 else if (fmt
[i
] == 'E')
9252 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9253 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
9258 /* This is used by reload pass, that does emit some instructions after
9259 abnormal calls moving basic block end, but in fact it wants to emit
9260 them on the edge. Looks for abnormal call edges, find backward the
9261 proper call and fix the damage.
9263 Similar handle instructions throwing exceptions internally. */
9265 fixup_abnormal_edges (void)
9267 bool inserted
= false;
9275 /* Look for cases we are interested in - calls or instructions causing
9277 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
9279 if (e
->flags
& EDGE_ABNORMAL_CALL
)
9281 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
9282 == (EDGE_ABNORMAL
| EDGE_EH
))
9285 if (e
&& !CALL_P (BB_END (bb
))
9286 && !can_throw_internal (BB_END (bb
)))
9290 /* Get past the new insns generated. Allow notes, as the insns
9291 may be already deleted. */
9293 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
9294 && !can_throw_internal (insn
)
9295 && insn
!= BB_HEAD (bb
))
9296 insn
= PREV_INSN (insn
);
9298 if (CALL_P (insn
) || can_throw_internal (insn
))
9302 stop
= NEXT_INSN (BB_END (bb
));
9304 insn
= NEXT_INSN (insn
);
9306 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
9307 if (e
->flags
& EDGE_FALLTHRU
)
9310 while (insn
&& insn
!= stop
)
9312 next
= NEXT_INSN (insn
);
9317 /* Sometimes there's still the return value USE.
9318 If it's placed after a trapping call (i.e. that
9319 call is the last insn anyway), we have no fallthru
9320 edge. Simply delete this use and don't try to insert
9321 on the non-existent edge. */
9322 if (GET_CODE (PATTERN (insn
)) != USE
)
9324 /* We're not deleting it, we're moving it. */
9325 INSN_DELETED_P (insn
) = 0;
9326 PREV_INSN (insn
) = NULL_RTX
;
9327 NEXT_INSN (insn
) = NULL_RTX
;
9329 insert_insn_on_edge (insn
, e
);
9333 else if (!BARRIER_P (insn
))
9334 set_block_for_insn (insn
, NULL
);
9339 /* It may be that we don't find any such trapping insn. In this
9340 case we discovered quite late that the insn that had been
9341 marked as can_throw_internal in fact couldn't trap at all.
9342 So we should in fact delete the EH edges out of the block. */
9344 purge_dead_edges (bb
);
9348 /* We've possibly turned single trapping insn into multiple ones. */
9349 if (cfun
->can_throw_non_call_exceptions
)
9352 blocks
= sbitmap_alloc (last_basic_block
);
9353 sbitmap_ones (blocks
);
9354 find_many_sub_basic_blocks (blocks
);
9355 sbitmap_free (blocks
);
9359 commit_edge_insertions ();
9361 #ifdef ENABLE_CHECKING
9362 /* Verify that we didn't turn one trapping insn into many, and that
9363 we found and corrected all of the problems wrt fixups on the
9365 verify_flow_info ();