1 ;; Machine description the Motorola MCore
2 ;; Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
3 ;; Contributed by Motorola.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; -------------------------------------------------------------------------
28 ;; -------------------------------------------------------------------------
32 (define_attr "type" "brcond,branch,jmp,load,store,move,alu,shift"
35 ;; If a branch destination is within -2048..2047 bytes away from the
36 ;; instruction it can be 2 bytes long. All other conditional branches
37 ;; are 10 bytes long, and all other unconditional branches are 8 bytes.
39 ;; the assembler handles the long-branch span case for us if we use
40 ;; the "jb*" mnemonics for jumps/branches. This pushes the span
41 ;; calculations and the literal table placement into the assembler,
42 ;; where their interactions can be managed in a single place.
44 ; All MCORE instructions are two bytes long.
46 (define_attr "length" "" (const_int 2))
48 ;; (define_function_unit {name} {num-units} {n-users} {test}
49 ;; {ready-delay} {issue-delay} [{conflict-list}])
52 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
54 ;; -------------------------------------------------------------------------
56 ;; -------------------------------------------------------------------------
60 (sign_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
62 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
65 [(set_attr "type" "shift")])
69 (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
71 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
74 [(set_attr "type" "shift")])
76 ;;; This is created by combine.
79 (ne:CC (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
81 (match_operand:SI 1 "mcore_literal_K_operand" "K"))
85 [(set_attr "type" "shift")])
88 ;; Created by combine from conditional patterns below (see sextb/btsti rx,31)
92 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
95 "GET_CODE(operands[0]) == SUBREG &&
96 GET_MODE(SUBREG_REG(operands[0])) == QImode"
98 [(set_attr "type" "shift")])
102 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
105 "GET_CODE(operands[0]) == SUBREG &&
106 GET_MODE(SUBREG_REG(operands[0])) == HImode"
108 [(set_attr "type" "shift")])
112 (if_then_else (ne (eq:CC (zero_extract:SI
113 (match_operand:SI 0 "mcore_arith_reg_operand" "")
115 (match_operand:SI 1 "mcore_literal_K_operand" ""))
118 (label_ref (match_operand 2 "" ""))
122 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
123 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
124 (label_ref (match_dup 2))
130 (if_then_else (eq (ne:CC (zero_extract:SI
131 (match_operand:SI 0 "mcore_arith_reg_operand" "")
133 (match_operand:SI 1 "mcore_literal_K_operand" ""))
136 (label_ref (match_operand 2 "" ""))
140 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
141 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
142 (label_ref (match_dup 2))
146 ;; XXX - disabled by nickc because it fails on libiberty/fnmatch.c
148 ;; ; Experimental - relax immediates for and, andn, or, and tst to allow
149 ;; ; any immediate value (or an immediate at all -- or, andn, & tst).
150 ;; ; This is done to allow bit field masks to fold together in combine.
151 ;; ; The reload phase will force the immediate into a register at the
152 ;; ; very end. This helps in some cases, but hurts in others: we'd
153 ;; ; really like to cse these immediates. However, there is a phase
154 ;; ; ordering problem here. cse picks up individual masks and cse's
155 ;; ; those, but not folded masks (cse happens before combine). It's
156 ;; ; not clear what the best solution is because we really want cse
157 ;; ; before combine (leaving the bit field masks alone). To pick up
158 ;; ; relaxed immediates use -mrelax-immediates. It might take some
159 ;; ; experimenting to see which does better (i.e. regular imms vs.
160 ;; ; arbitrary imms) for a particular code. BRC
164 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
165 ;; (match_operand:SI 1 "mcore_arith_any_imm_operand" "rI"))
167 ;; "TARGET_RELAX_IMM"
172 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
173 ;; (match_operand:SI 1 "mcore_arith_M_operand" "r"))
175 ;; "!TARGET_RELAX_IMM"
180 (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
181 (match_operand:SI 1 "mcore_arith_M_operand" "r"))
190 (ne:CC (ne:SI (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
191 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))
194 (clobber (match_operand:CC 2 "mcore_arith_reg_operand" "=r"))])]
196 [(set (reg:CC 17) (ne:SI (match_dup 0) (const_int 0)))
197 (set (reg:CC 17) (leu:CC (match_dup 0) (match_dup 1)))])
199 ;; -------------------------------------------------------------------------
200 ;; SImode signed integer comparisons
201 ;; -------------------------------------------------------------------------
203 (define_insn "decne_t"
204 [(set (reg:CC 17) (ne:CC (plus:SI (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
208 (plus:SI (match_dup 0)
213 ;; The combiner seems to prefer the following to the former.
216 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
219 (plus:SI (match_dup 0)
224 (define_insn "cmpnesi_t"
225 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
226 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
230 (define_insn "cmpneisi_t"
231 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
232 (match_operand:SI 1 "mcore_arith_K_operand" "K")))]
236 (define_insn "cmpgtsi_t"
237 [(set (reg:CC 17) (gt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
238 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
243 [(set (reg:CC 17) (gt:CC (plus:SI
244 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
247 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
251 (define_insn "cmpltsi_t"
252 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
253 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
258 (define_insn "cmpltisi_t"
259 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
260 (match_operand:SI 1 "mcore_arith_J_operand" "J")))]
266 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
272 [(set (reg:CC 17) (lt:CC (plus:SI
273 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
276 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
280 ;; -------------------------------------------------------------------------
281 ;; SImode unsigned integer comparisons
282 ;; -------------------------------------------------------------------------
284 (define_insn "cmpgeusi_t"
285 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
286 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
290 (define_insn "cmpgeusi_0"
291 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
296 (define_insn "cmpleusi_t"
297 [(set (reg:CC 17) (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
298 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
302 ;; We save the compare operands in the cmpxx patterns and use them when
303 ;; we generate the branch.
305 ;; We accept constants here, in case we can modify them to ones which
306 ;; are more efficient to load. E.g. change 'x <= 62' to 'x < 63'.
308 (define_expand "cmpsi"
309 [(set (reg:CC 17) (compare:CC (match_operand:SI 0 "mcore_compare_operand" "")
310 (match_operand:SI 1 "nonmemory_operand" "")))]
313 { arch_compare_op0 = operands[0];
314 arch_compare_op1 = operands[1];
318 ;; -------------------------------------------------------------------------
319 ;; Logical operations
320 ;; -------------------------------------------------------------------------
322 ;; Logical AND clearing a single bit. andsi3 knows that we have this
323 ;; pattern and allows the constant literal pass through.
326 ;; RBE 2/97: don't need this pattern any longer...
327 ;; RBE: I don't think we need both "S" and exact_log2() clauses.
329 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
330 ;; (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
331 ;; (match_operand:SI 2 "const_int_operand" "S")))]
332 ;; "mcore_arith_S_operand (operands[2])"
336 (define_insn "andnsi3"
337 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
338 (and:SI (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))
339 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
343 (define_expand "andsi3"
344 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
345 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
346 (match_operand:SI 2 "nonmemory_operand" "")))]
350 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0
351 && ! mcore_arith_S_operand (operands[2]))
353 int not_value = ~ INTVAL (operands[2]);
354 if ( CONST_OK_FOR_I (not_value)
355 || CONST_OK_FOR_M (not_value)
356 || CONST_OK_FOR_N (not_value))
358 operands[2] = copy_to_mode_reg (SImode, GEN_INT (not_value));
359 emit_insn (gen_andnsi3 (operands[0], operands[2], operands[1]));
364 if (! mcore_arith_K_S_operand (operands[2], SImode))
365 operands[2] = copy_to_mode_reg (SImode, operands[2]);
369 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
370 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
371 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,K,0,S")))]
375 switch (which_alternative)
377 case 0: return \"and %0,%2\";
378 case 1: return \"andi %0,%2\";
379 case 2: return \"and %0,%1\";
380 /* case -1: return \"bclri %0,%Q2\"; will not happen */
381 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
386 ;; This was the old "S" which was "!(2^n)" */
387 ;; case -1: return \"bclri %0,%Q2\"; will not happen */
390 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
391 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
392 (match_operand:SI 2 "mcore_arith_K_S_operand" "r,K,0,S")))]
396 switch (which_alternative)
398 case 0: return \"and %0,%2\";
399 case 1: return \"andi %0,%2\";
400 case 2: return \"and %0,%1\";
401 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
406 ;(define_insn "iorsi3"
407 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
408 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
409 ; (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
413 ; need an expand to resolve ambiguity betw. the two iors below.
414 (define_expand "iorsi3"
415 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
416 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
417 (match_operand:SI 2 "nonmemory_operand" "")))]
421 if (! mcore_arith_M_operand (operands[2], SImode))
422 operands[2] = copy_to_mode_reg (SImode, operands[2]);
426 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
427 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
428 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,M,T")))]
432 switch (which_alternative)
434 case 0: return \"or %0,%2\";
435 case 1: return \"bseti %0,%P2\";
436 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
442 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
443 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
444 (match_operand:SI 2 "mcore_arith_M_operand" "r,M,T")))]
448 switch (which_alternative)
450 case 0: return \"or %0,%2\";
451 case 1: return \"bseti %0,%P2\";
452 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
458 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
459 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
460 ; (match_operand:SI 2 "const_int_operand" "M")))]
461 ; "exact_log2 (INTVAL (operands[2])) >= 0"
465 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
466 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
467 ; (match_operand:SI 2 "const_int_operand" "i")))]
468 ; "mcore_num_ones (INTVAL (operands[2])) < 3"
469 ; "* return mcore_output_bseti (operands[0], INTVAL (operands[2]));")
471 (define_insn "xorsi3"
472 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
473 (xor:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
474 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
478 ; these patterns give better code then gcc invents if
479 ; left to its own devices
481 (define_insn "anddi3"
482 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
483 (and:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
484 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))]
486 "and %0,%2\;and %R0,%R2"
487 [(set_attr "length" "4")])
489 (define_insn "iordi3"
490 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
491 (ior:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
492 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))]
494 "or %0,%2\;or %R0,%R2"
495 [(set_attr "length" "4")])
497 (define_insn "xordi3"
498 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
499 (xor:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
500 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))]
502 "xor %0,%2\;xor %R0,%R2"
503 [(set_attr "length" "4")])
505 ;; -------------------------------------------------------------------------
506 ;; Shifts and rotates
507 ;; -------------------------------------------------------------------------
509 ;; Only allow these if the shift count is a convenient constant.
510 (define_expand "rotlsi3"
511 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
512 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
513 (match_operand:SI 2 "nonmemory_operand" "")))]
515 "if (! mcore_literal_K_operand (operands[2], SImode))
519 ;; We can only do constant rotates, which is what this pattern provides.
520 ;; The combiner will put it together for us when we do:
521 ;; (x << N) | (x >> (32 - N))
523 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
524 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
525 (match_operand:SI 2 "mcore_literal_K_operand" "K")))]
528 [(set_attr "type" "shift")])
530 (define_insn "ashlsi3"
531 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
532 (ashift:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
533 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
538 [(set_attr "type" "shift")])
541 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
542 (ashift:SI (const_int 1)
543 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
546 [(set_attr "type" "shift")])
548 (define_insn "ashrsi3"
549 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
550 (ashiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
551 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
556 [(set_attr "type" "shift")])
558 (define_insn "lshrsi3"
559 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
560 (lshiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
561 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
566 [(set_attr "type" "shift")])
568 ;(define_expand "ashldi3"
569 ; [(parallel[(set (match_operand:DI 0 "mcore_arith_reg_operand" "")
570 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "")
571 ; (match_operand:DI 2 "immediate_operand" "")))
573 ; (clobber (reg:CC 17))])]
578 ; if (GET_CODE (operands[2]) != CONST_INT
579 ; || INTVAL (operands[2]) != 1)
584 ; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
585 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
587 ; (clobber (reg:CC 17))]
589 ; "lsli %R0,0\;rotli %0,0"
590 ; [(set_attr "length" "4") (set_attr "type" "shift")])
592 ;; -------------------------------------------------------------------------
593 ;; Index instructions
594 ;; -------------------------------------------------------------------------
595 ;; The second of each set of patterns is borrowed from the alpha.md file.
596 ;; These variants of the above insns can occur if the second operand
597 ;; is the frame pointer. This is a kludge, but there doesn't
598 ;; seem to be a way around it. Only recognize them while reloading.
600 ;; We must use reload_operand for some operands in case frame pointer
601 ;; elimination put a MEM with invalid address there. Otherwise,
602 ;; the result of the substitution will not match this pattern, and reload
603 ;; will not be able to correctly fix the result.
605 ;; indexing longlongs or doubles (8 bytes)
607 (define_insn "indexdi_t"
608 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
609 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
611 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
614 if (! mcore_is_same_reg (operands[1], operands[2]))
616 output_asm_insn (\"ixw\\t%0,%1\", operands);
617 output_asm_insn (\"ixw\\t%0,%1\", operands);
621 output_asm_insn (\"ixh\\t%0,%1\", operands);
622 output_asm_insn (\"ixh\\t%0,%1\", operands);
626 ;; if operands[1] == operands[2], the first option above is wrong! -- dac
627 ;; was this... -- dac
628 ;; ixw %0,%1\;ixw %0,%1"
630 [(set_attr "length" "4")])
633 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
634 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
636 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
637 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
640 ixw %0,%1\;ixw %0,%1\;addu %0,%3
641 ixw %0,%1\;ixw %0,%1\;addi %0,%3
642 ixw %0,%1\;ixw %0,%1\;subi %0,%M3"
643 [(set_attr "length" "6")])
645 ;; indexing longs (4 bytes)
647 (define_insn "indexsi_t"
648 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
649 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
651 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
656 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
657 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
659 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
660 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
663 ixw %0,%1\;addu %0,%3
664 ixw %0,%1\;addi %0,%3
665 ixw %0,%1\;subi %0,%M3"
666 [(set_attr "length" "4")])
668 ;; indexing shorts (2 bytes)
670 (define_insn "indexhi_t"
671 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
672 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
674 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
679 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
680 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
682 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
683 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
686 ixh %0,%1\;addu %0,%3
687 ixh %0,%1\;addi %0,%3
688 ixh %0,%1\;subi %0,%M3"
689 [(set_attr "length" "4")])
692 ;; Other sizes may be handy for indexing.
693 ;; the tradeoffs to consider when adding these are
694 ;; codesize, execution time [vs. mul it is easy to win],
695 ;; and register pressure -- these patterns don't use an extra
696 ;; register to build the offset from the base
697 ;; and whether the compiler will not come up with some other idiom.
700 ;; -------------------------------------------------------------------------
701 ;; Addition, Subtraction instructions
702 ;; -------------------------------------------------------------------------
704 (define_expand "addsi3"
705 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
706 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
707 (match_operand:SI 2 "nonmemory_operand" "")))]
711 extern int flag_omit_frame_pointer;
713 /* If this is an add to the frame pointer, then accept it as is so
714 that we can later fold in the fp/sp offset from frame pointer
716 if (flag_omit_frame_pointer
717 && GET_CODE (operands[1]) == REG
718 && (REGNO (operands[1]) == VIRTUAL_STACK_VARS_REGNUM
719 || REGNO (operands[1]) == FRAME_POINTER_REGNUM))
721 emit_insn (gen_addsi3_fp (operands[0], operands[1], operands[2]));
725 /* Convert adds to subtracts if this makes loading the constant cheaper.
726 But only if we are allowed to generate new pseudos. */
727 if (! (reload_in_progress || reload_completed)
728 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < -32)
730 int neg_value = - INTVAL (operands[2]);
731 if ( CONST_OK_FOR_I (neg_value)
732 || CONST_OK_FOR_M (neg_value)
733 || CONST_OK_FOR_N (neg_value))
735 operands[2] = copy_to_mode_reg (SImode, GEN_INT (neg_value));
736 emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
741 if (! mcore_addsub_operand (operands[2], SImode))
742 operands[2] = copy_to_mode_reg (SImode, operands[2]);
745 ;; RBE: for some constants which are not in the range which allows
746 ;; us to do a single operation, we will try a paired addi/addi instead
747 ;; of a movi/addi. This relieves some register pressure at the expense
748 ;; of giving away some potential constant reuse.
750 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
751 ;; for later reference
753 ;; (define_insn "addsi3_i2"
754 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
755 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
756 ;; (match_operand:SI 2 "const_int_operand" "g")))]
757 ;; "GET_CODE(operands[2]) == CONST_INT
758 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
759 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
762 ;; int n = INTVAL(operands[2]);
765 ;; operands[2] = GEN_INT(n - 32);
766 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
771 ;; operands[2] = GEN_INT(n - 32);
772 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
775 ;; [(set_attr "length" "4")])
777 (define_insn "addsi3_i"
778 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
779 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
780 (match_operand:SI 2 "mcore_addsub_operand" "r,J,L")))]
787 ;; This exists so that address computations based on the frame pointer
788 ;; can be folded in when frame pointer elimination occurs. Ordinarily
789 ;; this would be bad because it allows insns which would require reloading,
790 ;; but without it, we get multiple adds where one would do.
792 (define_insn "addsi3_fp"
793 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
794 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
795 (match_operand:SI 2 "immediate_operand" "r,J,L")))]
796 "flag_omit_frame_pointer
797 && (reload_in_progress || reload_completed || REGNO (operands[1]) == FRAME_POINTER_REGNUM)"
803 ;; RBE: for some constants which are not in the range which allows
804 ;; us to do a single operation, we will try a paired addi/addi instead
805 ;; of a movi/addi. This relieves some register pressure at the expense
806 ;; of giving away some potential constant reuse.
808 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
809 ;; for later reference
811 ;; (define_insn "subsi3_i2"
812 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
813 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
814 ;; (match_operand:SI 2 "const_int_operand" "g")))]
815 ;; "TARGET_RBETEST && GET_CODE(operands[2]) == CONST_INT
816 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
817 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
820 ;; int n = INTVAL(operands[2]);
823 ;; operands[2] = GEN_INT( n - 32);
824 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
829 ;; operands[2] = GEN_INT(n - 32);
830 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
833 ;; [(set_attr "length" "4")])
835 ;(define_insn "subsi3"
836 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
837 ; (minus:SI (match_operand:SI 1 "mcore_arith_K_operand" "0,0,r,K")
838 ; (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0,0")))]
846 (define_insn "subsi3"
847 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
848 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r")
849 (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0")))]
857 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
858 (minus:SI (match_operand:SI 1 "mcore_literal_K_operand" "K")
859 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
863 (define_insn "adddi3"
864 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
865 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
866 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
867 (clobber (reg:CC 17))]
871 if (TARGET_LITTLE_END)
872 return \"cmplt %0,%0\;addc %0,%2\;addc %R0,%R2\";
873 return \"cmplt %R0,%R0\;addc %R0,%R2\;addc %0,%2\";
875 [(set_attr "length" "6")])
877 ;; special case for "longlong += 1"
879 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
880 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
882 (clobber (reg:CC 17))]
886 if (TARGET_LITTLE_END)
887 return \"addi %0,1\;cmpnei %0,0\;incf %R0\";
888 return \"addi %R0,1\;cmpnei %R0,0\;incf %0\";
890 [(set_attr "length" "6")])
892 ;; special case for "longlong -= 1"
894 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
895 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
897 (clobber (reg:CC 17))]
901 if (TARGET_LITTLE_END)
902 return \"cmpnei %0,0\;decf %R0\;subi %0,1\";
903 return \"cmpnei %R0,0\;decf %0\;subi %R0,1\";
905 [(set_attr "length" "6")])
907 ;; special case for "longlong += const_int"
908 ;; we have to use a register for the const_int because we don't
909 ;; have an unsigned compare immediate... only +/- 1 get to
910 ;; play the no-extra register game because they compare with 0.
911 ;; This winds up working out for any literal that is synthesized
912 ;; with a single instruction. The more complicated ones look
913 ;; like the get broken into subreg's to get initialized too soon
914 ;; for us to catch here. -- RBE 4/25/96
915 ;; only allow for-sure positive values.
918 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
919 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
920 (match_operand:SI 2 "const_int_operand" "r")))
921 (clobber (reg:CC 17))]
922 "GET_CODE (operands[2]) == CONST_INT
923 && INTVAL (operands[2]) > 0 && ! (INTVAL (operands[2]) & 0x80000000)"
926 if (GET_MODE (operands[2]) != SImode)
928 if (TARGET_LITTLE_END)
929 return \"addu %0,%2\;cmphs %0,%2\;incf %R0\";
930 return \"addu %R0,%2\;cmphs %R0,%2\;incf %0\";
932 [(set_attr "length" "6")])
934 ;; optimize "long long" + "unsigned long"
935 ;; won't trigger because of how the extension is expanded upstream.
937 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
938 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
939 ;; (zero_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
940 ;; (clobber (reg:CC 17))]
942 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0"
943 ;; [(set_attr "length" "6")])
945 ;; optimize "long long" + "signed long"
946 ;; won't trigger because of how the extension is expanded upstream.
948 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
949 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
950 ;; (sign_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
951 ;; (clobber (reg:CC 17))]
953 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0\;btsti %2,31\;dect %0"
954 ;; [(set_attr "length" "6")])
956 (define_insn "subdi3"
957 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
958 (minus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
959 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
960 (clobber (reg:CC 17))]
964 if (TARGET_LITTLE_END)
965 return \"cmphs %0,%0\;subc %0,%2\;subc %R0,%R2\";
966 return \"cmphs %R0,%R0\;subc %R0,%R2\;subc %0,%2\";
968 [(set_attr "length" "6")])
970 ;; -------------------------------------------------------------------------
971 ;; Multiplication instructions
972 ;; -------------------------------------------------------------------------
974 (define_insn "mulsi3"
975 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
976 (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
977 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
982 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
984 ;; Different constraints based on the architecture revision...
986 (define_expand "divsi3"
987 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
988 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
989 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
993 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
996 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
997 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
998 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
1003 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
1005 ;; Different constraints based on the architecture revision...
1007 (define_expand "udivsi3"
1008 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1009 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1010 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1014 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
1016 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1017 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1018 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
1022 ;; -------------------------------------------------------------------------
1024 ;; -------------------------------------------------------------------------
1026 (define_insn "negsi2"
1027 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1028 (neg:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1032 return \"rsubi %0,0\";
1036 (define_insn "abssi2"
1037 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1038 (abs:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1042 (define_insn "negdi2"
1043 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
1044 (neg:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")))
1045 (clobber (reg:CC 17))]
1049 if (TARGET_LITTLE_END)
1050 return \"cmpnei %0,0\\n\\trsubi %0,0\\n\\tnot %R0\\n\\tincf %R0\";
1051 return \"cmpnei %R0,0\\n\\trsubi %R0,0\\n\\tnot %0\\n\\tincf %0\";
1053 [(set_attr "length" "8")])
1055 (define_insn "one_cmplsi2"
1056 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1057 (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1061 ;; -------------------------------------------------------------------------
1062 ;; Zero extension instructions
1063 ;; -------------------------------------------------------------------------
1065 (define_expand "zero_extendhisi2"
1066 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1067 (zero_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "")))]
1072 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
1073 (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
1078 [(set_attr "type" "shift,load")])
1080 ;; ldh gives us a free zero-extension. The combiner picks up on this.
1082 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1083 (zero_extend:SI (mem:HI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1086 [(set_attr "type" "load")])
1089 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1090 (zero_extend:SI (mem:HI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1091 (match_operand:SI 2 "const_int_operand" "")))))]
1092 "(INTVAL (operands[2]) >= 0) &&
1093 (INTVAL (operands[2]) < 32) &&
1094 ((INTVAL (operands[2])&1) == 0)"
1096 [(set_attr "type" "load")])
1098 (define_expand "zero_extendqisi2"
1099 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1100 (zero_extend:SI (match_operand:QI 1 "general_operand" "")))]
1104 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1106 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b,r")
1107 (zero_extend:SI (match_operand:QI 1 "general_operand" "0,r,m")))]
1113 [(set_attr "type" "shift,shift,load")])
1115 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1117 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1118 (zero_extend:SI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1121 [(set_attr "type" "load")])
1124 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1125 (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1126 (match_operand:SI 2 "const_int_operand" "")))))]
1127 "(INTVAL (operands[2]) >= 0) &&
1128 (INTVAL (operands[2]) < 16)"
1130 [(set_attr "type" "load")])
1132 (define_expand "zero_extendqihi2"
1133 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "")
1134 (zero_extend:HI (match_operand:QI 1 "general_operand" "")))]
1138 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1140 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r,b,r")
1141 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,r,m")))]
1147 [(set_attr "type" "shift,shift,load")])
1149 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1150 ;; this doesn't catch references that are into a structure.
1151 ;; note that normally the compiler uses the above insn, unless it turns
1152 ;; out that we're dealing with a volatile...
1154 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1155 (zero_extend:HI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1158 [(set_attr "type" "load")])
1161 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1162 (zero_extend:HI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1163 (match_operand:SI 2 "const_int_operand" "")))))]
1164 "(INTVAL (operands[2]) >= 0) &&
1165 (INTVAL (operands[2]) < 16)"
1167 [(set_attr "type" "load")])
1170 ;; -------------------------------------------------------------------------
1171 ;; Sign extension instructions
1172 ;; -------------------------------------------------------------------------
1174 (define_expand "extendsidi2"
1175 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
1176 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
1182 if (TARGET_LITTLE_END)
1187 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], low),
1189 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], high),
1190 gen_rtx_ASHIFTRT (SImode,
1191 gen_rtx_SUBREG (SImode, operands[0], low),
1197 (define_insn "extendhisi2"
1198 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1199 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))]
1203 (define_insn "extendqisi2"
1204 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1205 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1209 (define_insn "extendqihi2"
1210 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1211 (sign_extend:HI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1215 ;; -------------------------------------------------------------------------
1216 ;; Move instructions
1217 ;; -------------------------------------------------------------------------
1221 (define_expand "movsi"
1222 [(set (match_operand:SI 0 "general_operand" "")
1223 (match_operand:SI 1 "general_operand" ""))]
1227 if (GET_CODE (operands[0]) == MEM)
1228 operands[1] = force_reg (SImode, operands[1]);
1229 else if (CONSTANT_P (operands[1])
1230 && (GET_CODE (operands[1]) != CONST_INT
1231 || ( ! CONST_OK_FOR_I (INTVAL (operands[1]))
1232 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1233 && ! CONST_OK_FOR_N (INTVAL (operands[1]))
1234 && (! TARGET_HARDLIT ||
1235 ! mcore_const_ok_for_inline (INTVAL (operands[1])))))
1236 && ! reload_completed
1237 && ! reload_in_progress
1238 && GET_CODE (operands[0]) == REG
1239 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
1240 && (REGNO (operands[0]) == STACK_POINTER_REGNUM
1241 || REGNO (operands[0]) == LK_REG))
1242 operands[1] = force_reg (SImode, operands[1]);
1245 ;;; Must put a/i before r/r so that it will be preferred when the dest is
1246 ;;; a hard register. Must put a/R before r/m.
1247 ;;; DO WE NEED a/i ANYMORE?
1250 [(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,r,a,r,r,a,r,m")
1251 (match_operand:SI 1 "mcore_general_movsrc_operand" "I,M,N,i,r,c,R,m,r"))]
1252 "(register_operand (operands[0], SImode)
1253 || register_operand (operands[1], SImode))
1254 && ! (CONSTANT_P (operands[1])
1255 && (GET_CODE (operands[1]) != CONST_INT
1256 || ( ! CONST_OK_FOR_I (INTVAL (operands[1]))
1257 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1258 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1259 && GET_CODE (operands[0]) == REG
1260 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
1261 && (REGNO (operands[0]) == STACK_POINTER_REGNUM
1262 || REGNO (operands[0]) == LK_REG))"
1263 "* return mcore_output_move (insn, operands, SImode);"
1264 [(set_attr "type" "move,move,move,move,move,move,load,load,store")])
1266 ;; This is to work around a bug in reload.
1268 [(set (match_operand:SI 0 "register_operand" "=r")
1269 (match_operand:SI 1 "immediate_operand" "i"))]
1270 "((reload_in_progress || reload_completed)
1271 && CONSTANT_P (operands[1])
1272 && GET_CODE (operands[1]) == CONST_INT
1273 && ! CONST_OK_FOR_I (INTVAL (operands[1]))
1274 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1275 && ! CONST_OK_FOR_N (INTVAL (operands[1]))
1276 && GET_CODE (operands[0]) == REG
1277 && REGNO (operands[0]) == LK_REG)"
1278 "* return mcore_output_inline_const_forced (insn, operands, SImode);"
1279 [(set_attr "type" "load")])
1281 ;; (define_expand "reload_insi"
1282 ;; [(parallel [(match_operand:SI 0 "register_operand" "=r")
1283 ;; (match_operand:SI 1 "general_operand" "")
1284 ;; (match_operand:DI 2 "register_operand" "=&r")])]
1288 ;; if (CONSTANT_P (operands[1])
1289 ;; && GET_CODE (operands[1]) == CONST_INT
1290 ;; && ! CONST_OK_FOR_I (INTVAL (operands[1]))
1291 ;; && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1292 ;; && ! CONST_OK_FOR_N (INTVAL (operands[1]))
1293 ;; && GET_CODE (operands[0]) == REG
1294 ;; && (REGNO (operands[0]) == STACK_POINTER_REGNUM
1295 ;; || REGNO (operands[0]) == LK_REG))
1299 ;; if ( REGNO (operands[2]) == REGNO (operands[0])
1300 ;; || REGNO (operands[2]) == STACK_POINTER_REGNUM
1301 ;; || REGNO (operands[2]) == LK_REG)
1302 ;; tmp = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
1304 ;; tmp = gen_rtx_REG (SImode, REGNO (operands[2]));
1306 ;; emit_insn (gen_movsi (tmp, operands[1]));
1307 ;; emit_insn (gen_movsi (operands[0], tmp));
1310 ;; emit_insn (gen_movsi (operands[0], operands[1]));
1321 ;;; ??? This isn't guaranteed to work. It should be more like the SImode
1324 (define_expand "movhi"
1325 [(set (match_operand:HI 0 "general_operand" "")
1326 (match_operand:HI 1 "general_operand" ""))]
1330 if (GET_CODE (operands[0]) == MEM)
1331 operands[1] = force_reg (HImode, operands[1]);
1332 else if (CONSTANT_P (operands[1])
1333 && (GET_CODE (operands[1]) != CONST_INT
1334 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1335 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1336 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1337 && ! reload_completed && ! reload_in_progress)
1339 rtx reg = gen_reg_rtx (SImode);
1340 emit_insn (gen_movsi (reg, operands[1]));
1341 operands[1] = gen_rtx (SUBREG, HImode, reg, 0);
1346 [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,r,r,r,r,m")
1347 (match_operand:HI 1 "mcore_general_movsrc_operand" "r,I,M,N,c,m,r"))]
1348 "(register_operand (operands[0], HImode)
1349 || register_operand (operands[1], HImode))
1350 && (GET_CODE (operands[1]) != CONST_INT
1351 || CONST_OK_FOR_M (INTVAL (operands[1]))
1352 || CONST_OK_FOR_N (INTVAL (operands[1]))
1353 || CONST_OK_FOR_I (INTVAL (operands[1])))"
1362 [(set_attr "type" "move,move,move,move,move,load,store")])
1364 ;; Like movhi, but the const_int source can't be synthesized in
1365 ;; a single-instruction. Fall back to the same things that
1366 ;; are done for movsi in such cases. Presumes that we can
1367 ;; modify any parts of the register that we wish.
1370 [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,a")
1371 (match_operand:HI 1 "const_int_operand" "P,i"))]
1372 "GET_CODE (operands[1]) == CONST_INT
1373 && INTVAL (operands[1]) > 127 && INTVAL (operands[1]) < 65536"
1376 if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
1377 && !mcore_const_ok_for_inline (INTVAL (operands[1])))
1379 /* mcore_output_move would generate lrw r15 -- a forbidden combo */
1380 return mcore_output_inline_const_forced (insn, operands, SImode);
1383 return mcore_output_move (insn, operands, SImode);
1385 [(set_attr "type" "move")])
1388 ;; if we're still looking around for things to use, here's a last
1389 ;; ditch effort that just calls the move. We only let this happen
1390 ;; if we're in the reload pass.
1393 [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,a")
1394 (match_operand:HI 1 "const_int_operand" "P,i"))]
1395 "reload_in_progress || reload_completed"
1398 if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
1399 && !mcore_const_ok_for_inline (INTVAL (operands[1])))
1401 /* mcore_output_move would generate lrw r15 -- a forbidden combo */
1402 return mcore_output_inline_const_forced (insn, operands, SImode);
1405 return mcore_output_move (insn, operands, HImode);
1407 [(set_attr "type" "move")])
1413 (define_expand "movqi"
1414 [(set (match_operand:QI 0 "general_operand" "")
1415 (match_operand:QI 1 "general_operand" ""))]
1419 if (GET_CODE (operands[0]) == MEM)
1420 operands[1] = force_reg (QImode, operands[1]);
1421 else if (CONSTANT_P (operands[1])
1422 && (GET_CODE (operands[1]) != CONST_INT
1423 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1424 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1425 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1426 && ! reload_completed && ! reload_in_progress)
1428 rtx reg = gen_reg_rtx (SImode);
1429 emit_insn (gen_movsi (reg, operands[1]));
1430 operands[1] = gen_rtx (SUBREG, QImode, reg, 0);
1435 [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,r,r,r,r,m")
1436 (match_operand:QI 1 "mcore_general_movsrc_operand" "r,I,M,N,c,m,r"))]
1437 "(register_operand (operands[0], QImode)
1438 || register_operand (operands[1], QImode))
1439 && (GET_CODE (operands[1]) != CONST_INT
1440 || CONST_OK_FOR_M (INTVAL (operands[1]))
1441 || CONST_OK_FOR_N (INTVAL (operands[1]))
1442 || CONST_OK_FOR_I (INTVAL (operands[1])))"
1451 [(set_attr "type" "move,move,move,move,move,load,store")])
1453 ;; cover the case where the constant is 128..255; this isn't handled
1454 ;; in the above case. We could if we wanted to mess with adding a
1455 ;; new constraint class like M,N,I.
1457 [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r")
1458 (match_operand:QI 1 "const_int_operand" ""))]
1459 "GET_CODE (operands[1]) == CONST_INT
1460 && INTVAL (operands[1]) > 127 && INTVAL (operands[1]) < 256"
1463 /* have a constant in range 128..255; have to do 2 insns; we can
1464 * do this with a movi followed by a bseti
1466 operands[2] = GEN_INT (INTVAL (operands[1]) & 0x7f);
1467 return \"movi\\t%0,%2\;bseti\\t%0,7\";
1469 [(set_attr "type" "move")])
1471 ;; if we're still looking around for things to use, here's a last
1472 ;; ditch effort that just calls the move. We only let this happen
1473 ;; if we're in the reload pass.
1476 [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,a")
1477 (match_operand:QI 1 "const_int_operand" "P,i"))]
1478 "(reload_in_progress || reload_completed)"
1481 if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
1482 && ! mcore_const_ok_for_inline (INTVAL (operands[1])))
1484 /* mcore_output_move would generate lrw r15 -- a forbidden combo */
1485 return mcore_output_inline_const_forced (insn, operands, SImode);
1488 return mcore_output_move (insn, operands, QImode);
1490 [(set_attr "type" "move")])
1494 (define_expand "movdi"
1495 [(set (match_operand:DI 0 "general_operand" "")
1496 (match_operand:DI 1 "general_operand" ""))]
1500 if (GET_CODE (operands[0]) == MEM)
1501 operands[1] = force_reg (DImode, operands[1]);
1502 else if (GET_CODE (operands[1]) == CONST_INT
1503 && ! CONST_OK_FOR_I (INTVAL (operands[1]))
1504 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1505 && ! CONST_OK_FOR_N (INTVAL (operands[1]))
1506 && ! reload_completed
1507 && ! reload_in_progress
1508 && GET_CODE (operands[0]) == REG)
1510 emit_move_insn (operand_subword (operands[0], 0, 1, DImode),
1511 operand_subword_force (operands[1], 0, DImode));
1512 emit_move_insn (operand_subword (operands[0], 1, 1, DImode),
1513 operand_subword_force (operands[1], 1, DImode));
1518 (define_insn "movdi_i"
1519 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,a,r,m")
1520 (match_operand:DI 1 "mcore_general_movsrc_operand" "I,M,N,r,R,m,r"))]
1522 "* return mcore_output_movedouble (operands, DImode);"
1523 [(set_attr "length" "4") (set_attr "type" "move,move,move,move,load,load,store")])
1527 (define_expand "movsf"
1528 [(set (match_operand:SF 0 "general_operand" "")
1529 (match_operand:SF 1 "general_operand" ""))]
1533 if (GET_CODE (operands[0]) == MEM)
1534 operands[1] = force_reg (SFmode, operands[1]);
1537 (define_insn "movsf_i"
1538 [(set (match_operand:SF 0 "general_operand" "=r,r,m")
1539 (match_operand:SF 1 "general_operand" "r,m,r"))]
1545 [(set_attr "type" "move,load,store")])
1549 (define_expand "movdf"
1550 [(set (match_operand:DF 0 "general_operand" "")
1551 (match_operand:DF 1 "general_operand" ""))]
1555 if (GET_CODE (operands[0]) == MEM)
1556 operands[1] = force_reg (DFmode, operands[1]);
1559 (define_insn "movdf_k"
1560 [(set (match_operand:DF 0 "general_operand" "=r,r,m")
1561 (match_operand:DF 1 "general_operand" "r,m,r"))]
1563 "* return mcore_output_movedouble (operands, DFmode);"
1564 [(set_attr "length" "4") (set_attr "type" "move,load,store")])
1567 ;; Load/store multiple
1569 ;; ??? This is not currently used.
1571 [(set (match_operand:TI 0 "mcore_arith_reg_operand" "=r")
1572 (mem:TI (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
1576 ;; ??? This is not currently used.
1578 [(set (mem:TI (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1579 (match_operand:TI 1 "mcore_arith_reg_operand" "r"))]
1583 (define_expand "load_multiple"
1584 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1585 (match_operand:SI 1 "" ""))
1586 (use (match_operand:SI 2 "" ""))])]
1590 int regno, count, i;
1592 /* Support only loading a constant number of registers from memory and
1593 only if at least two registers. The last register must be r15. */
1594 if (GET_CODE (operands[2]) != CONST_INT
1595 || INTVAL (operands[2]) < 2
1596 || GET_CODE (operands[1]) != MEM
1597 || XEXP (operands[1], 0) != stack_pointer_rtx
1598 || GET_CODE (operands[0]) != REG
1599 || REGNO (operands[0]) + INTVAL (operands[2]) != 16)
1602 count = INTVAL (operands[2]);
1603 regno = REGNO (operands[0]);
1605 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
1607 for (i = 0; i < count; i++)
1608 XVECEXP (operands[3], 0, i)
1609 = gen_rtx (SET, VOIDmode,
1610 gen_rtx (REG, SImode, regno + i),
1611 gen_rtx (MEM, SImode, plus_constant (stack_pointer_rtx,
1616 [(match_parallel 0 "mcore_load_multiple_operation"
1617 [(set (match_operand:SI 1 "mcore_arith_reg_operand" "=r")
1618 (mem:SI (match_operand:SI 2 "register_operand" "r")))])]
1619 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1622 (define_expand "store_multiple"
1623 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1624 (match_operand:SI 1 "" ""))
1625 (use (match_operand:SI 2 "" ""))])]
1629 int regno, count, i;
1631 /* Support only storing a constant number of registers to memory and
1632 only if at least two registers. The last register must be r15. */
1633 if (GET_CODE (operands[2]) != CONST_INT
1634 || INTVAL (operands[2]) < 2
1635 || GET_CODE (operands[0]) != MEM
1636 || XEXP (operands[0], 0) != stack_pointer_rtx
1637 || GET_CODE (operands[1]) != REG
1638 || REGNO (operands[1]) + INTVAL (operands[2]) != 16)
1641 count = INTVAL (operands[2]);
1642 regno = REGNO (operands[1]);
1644 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
1646 for (i = 0; i < count; i++)
1647 XVECEXP (operands[3], 0, i)
1648 = gen_rtx (SET, VOIDmode,
1649 gen_rtx (MEM, SImode, plus_constant (stack_pointer_rtx,
1651 gen_rtx (REG, SImode, regno + i));
1655 [(match_parallel 0 "mcore_store_multiple_operation"
1656 [(set (mem:SI (match_operand:SI 2 "register_operand" "r"))
1657 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))])]
1658 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1661 ;; ------------------------------------------------------------------------
1662 ;; Define the real conditional branch instructions.
1663 ;; ------------------------------------------------------------------------
1665 (define_insn "branch_true"
1666 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1667 (label_ref (match_operand 0 "" ""))
1671 [(set_attr "type" "brcond")])
1673 (define_insn "branch_false"
1674 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1675 (label_ref (match_operand 0 "" ""))
1679 [(set_attr "type" "brcond")])
1681 (define_insn "inverse_branch_true"
1682 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1684 (label_ref (match_operand 0 "" ""))))]
1687 [(set_attr "type" "brcond")])
1689 (define_insn "inverse_branch_false"
1690 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1692 (label_ref (match_operand 0 "" ""))))]
1695 [(set_attr "type" "brcond")])
1697 ;; Conditional branch insns
1699 ;; At top-level, condition test are eq/ne, because we
1700 ;; are comparing against the condition register (which
1701 ;; has the result of the true relational test
1703 ; There is no beq compare, so we reverse the branch arms.
1705 (define_expand "beq"
1706 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1708 (label_ref (match_operand 0 "" ""))))]
1712 operands[1] = mcore_gen_compare_reg (EQ);
1715 (define_expand "bne"
1716 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1717 (label_ref (match_operand 0 "" ""))
1722 operands[1] = mcore_gen_compare_reg (NE);
1725 ; check whether (GT A imm) can become (LE A imm) with the branch reversed.
1726 ; if so, emit a (LT A imm + 1) in place of the (LE A imm). BRC
1728 (define_expand "bgt"
1729 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1730 (label_ref (match_operand 0 "" ""))
1735 if (mcore_modify_comparison (LE))
1737 emit_jump_insn (gen_reverse_blt (operands[0]));
1740 operands[1] = mcore_gen_compare_reg (GT);
1743 ; There is no ble compare, so we reverse the branch arms.
1744 ; reversed the condition and branch arms for ble -- the check_dbra_loop()
1745 ; transformation assumes that ble uses a branch-true with the label as
1746 ; as the target. BRC
1748 ; check whether (LE A imm) can become (LT A imm + 1).
1750 (define_expand "ble"
1751 [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
1752 (label_ref (match_operand 0 "" ""))
1757 if (mcore_modify_comparison (LE))
1759 emit_jump_insn (gen_blt (operands[0]));
1762 operands[1] = mcore_gen_compare_reg (LE);
1765 ; make generating a reversed blt simple
1766 (define_expand "reverse_blt"
1767 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1769 (label_ref (match_operand 0 "" ""))))]
1773 operands[1] = mcore_gen_compare_reg (LT);
1776 (define_expand "blt"
1777 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1778 (label_ref (match_operand 0 "" ""))
1783 operands[1] = mcore_gen_compare_reg (LT);
1786 ; There is no bge compare, so we reverse the branch arms.
1788 (define_expand "bge"
1789 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1791 (label_ref (match_operand 0 "" ""))))]
1795 operands[1] = mcore_gen_compare_reg (GE);
1798 ; There is no gtu compare, so we reverse the branch arms
1800 ;(define_expand "bgtu"
1801 ; [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1803 ; (label_ref (match_operand 0 "" ""))))]
1807 ; if (GET_CODE (arch_compare_op1) == CONST_INT
1808 ; && INTVAL (arch_compare_op1) == 0)
1809 ; operands[1] = mcore_gen_compare_reg (NE);
1811 ; { if (mcore_modify_comparison (GTU))
1813 ; emit_jump_insn (gen_bgeu (operands[0]));
1816 ; operands[1] = mcore_gen_compare_reg (LEU);
1820 (define_expand "bgtu"
1821 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1823 (label_ref (match_operand 0 "" ""))))]
1827 if (GET_CODE (arch_compare_op1) == CONST_INT
1828 && INTVAL (arch_compare_op1) == 0)
1830 /* The inverse of '> 0' for an unsigned test is
1831 '== 0' but we do not have such an instruction available.
1832 Instead we must reverse the branch (back to the normal
1833 ordering) and test '!= 0'. */
1835 operands[1] = mcore_gen_compare_reg (NE);
1837 emit_jump_insn (gen_rtx_SET (VOIDmode,
1839 gen_rtx_IF_THEN_ELSE (VOIDmode,
1840 gen_rtx_NE (VOIDmode,
1843 gen_rtx_LABEL_REF (VOIDmode,operands[0]),
1847 operands[1] = mcore_gen_compare_reg (GTU);
1851 (define_expand "bleu"
1852 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1853 (label_ref (match_operand 0 "" ""))
1858 operands[1] = mcore_gen_compare_reg (LEU);
1861 ; There is no bltu compare, so we reverse the branch arms
1862 (define_expand "bltu"
1863 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1865 (label_ref (match_operand 0 "" ""))))]
1869 operands[1] = mcore_gen_compare_reg (LTU);
1872 (define_expand "bgeu"
1873 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1874 (label_ref (match_operand 0 "" ""))
1880 operands[1] = mcore_gen_compare_reg (GEU);
1883 ;; ------------------------------------------------------------------------
1884 ;; Jump and linkage insns
1885 ;; ------------------------------------------------------------------------
1887 (define_insn "jump_real"
1889 (label_ref (match_operand 0 "" "")))]
1892 [(set_attr "type" "branch")])
1894 (define_expand "jump"
1895 [(set (pc) (label_ref (match_operand 0 "" "")))]
1899 emit_insn (gen_jump_real (operand0));
1904 (define_insn "indirect_jump"
1906 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))]
1909 [(set_attr "type" "jmp")])
1911 (define_expand "call"
1912 [(parallel[(call (match_operand:SI 0 "" "")
1913 (match_operand 1 "" ""))
1914 (clobber (reg:SI 15))])]
1918 if (GET_CODE (operands[0]) == MEM
1919 && ! register_operand (XEXP (operands[0], 0), SImode)
1920 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1921 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1922 force_reg (Pmode, XEXP (operands[0], 0)));
1925 (define_insn "call_internal"
1926 [(call (mem:SI (match_operand:SI 0 "mcore_call_address_operand" "riR"))
1927 (match_operand 1 "" ""))
1928 (clobber (reg:SI 15))]
1930 "* return mcore_output_call (operands, 0);")
1932 (define_expand "call_value"
1933 [(parallel[(set (match_operand 0 "register_operand" "")
1934 (call (match_operand:SI 1 "" "")
1935 (match_operand 2 "" "")))
1936 (clobber (reg:SI 15))])]
1940 if (GET_CODE (operands[0]) == MEM
1941 && ! register_operand (XEXP (operands[0], 0), SImode)
1942 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1943 operands[1] = gen_rtx (MEM, GET_MODE (operands[1]),
1944 force_reg (Pmode, XEXP (operands[1], 0)));
1947 (define_insn "call_value_internal"
1948 [(set (match_operand 0 "register_operand" "=r")
1949 (call (mem:SI (match_operand:SI 1 "mcore_call_address_operand" "riR"))
1950 (match_operand 2 "" "")))
1951 (clobber (reg:SI 15))]
1953 "* return mcore_output_call (operands, 1);")
1955 (define_insn "call_value_struct"
1956 [(parallel [(set (match_parallel 0 ""
1957 [(expr_list (match_operand 3 "register_operand" "") (match_operand 4 "immediate_operand" ""))
1958 (expr_list (match_operand 5 "register_operand" "") (match_operand 6 "immediate_operand" ""))])
1959 (call (match_operand:SI 1 "" "")
1960 (match_operand 2 "" "")))
1961 (clobber (reg:SI 15))])]
1963 "* return mcore_output_call (operands, 1);"
1967 ;; ------------------------------------------------------------------------
1969 ;; ------------------------------------------------------------------------
1976 (define_insn "tablejump"
1978 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1979 (use (label_ref (match_operand 1 "" "")))]
1982 [(set_attr "type" "jmp")])
1984 (define_insn "*return"
1986 "reload_completed && ! mcore_naked_function_p ()"
1988 [(set_attr "type" "jmp")])
1990 (define_insn "*no_return"
1992 "reload_completed && mcore_naked_function_p ()"
1994 [(set_attr "length" "0")]
1997 (define_expand "prologue"
2000 "mcore_expand_prolog (); DONE;")
2002 (define_expand "epilogue"
2005 "mcore_expand_epilog ();")
2007 ;; ------------------------------------------------------------------------
2009 ;; ------------------------------------------------------------------------
2012 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2013 (ne:SI (reg:CC 17) (const_int 0)))]
2016 [(set_attr "type" "move")])
2019 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2020 (eq:SI (reg:CC 17) (const_int 0)))]
2023 [(set_attr "type" "move")])
2025 ; in 0.97 use (LE 0) with (LT 1) and complement c. BRC
2028 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2029 (ne:SI (gt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2032 (clobber (reg:SI 17))])]
2035 (lt:CC (match_dup 1) (const_int 1)))
2036 (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))])
2039 (define_expand "seq"
2040 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2041 (eq:SI (match_dup 1) (const_int 0)))]
2045 operands[1] = mcore_gen_compare_reg (NE);
2048 (define_expand "sne"
2049 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2050 (ne:SI (match_dup 1) (const_int 0)))]
2054 operands[1] = mcore_gen_compare_reg (NE);
2057 (define_expand "slt"
2058 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2059 (ne:SI (match_dup 1) (const_int 0)))]
2063 operands[1] = mcore_gen_compare_reg (LT);
2066 ; make generating a LT with the comparison reversed easy. BRC
2067 (define_expand "reverse_slt"
2068 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2069 (eq:SI (match_dup 1) (const_int 0)))]
2073 operands[1] = mcore_gen_compare_reg (LT);
2076 (define_expand "sge"
2077 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2078 (eq:SI (match_dup 1) (const_int 0)))]
2082 operands[1] = mcore_gen_compare_reg (LT);
2085 ; check whether (GT A imm) can become (LE A imm) with the comparison
2086 ; reversed. if so, emit a (LT A imm + 1) in place of the (LE A imm). BRC
2088 (define_expand "sgt"
2089 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2090 (ne:SI (match_dup 1) (const_int 0)))]
2094 if (mcore_modify_comparison (LE))
2096 emit_insn (gen_reverse_slt (operands[0]));
2100 operands[1] = mcore_gen_compare_reg (GT);
2103 (define_expand "sle"
2104 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2105 (eq:SI (match_dup 1) (const_int 0)))]
2109 if (mcore_modify_comparison (LE))
2111 emit_insn (gen_slt (operands[0]));
2114 operands[1] = mcore_gen_compare_reg (GT);
2117 (define_expand "sltu"
2118 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2119 (eq:SI (match_dup 1) (const_int 0)))]
2123 operands[1] = mcore_gen_compare_reg (GEU);
2126 (define_expand "sgeu"
2127 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2128 (ne:SI (match_dup 1) (const_int 0)))]
2132 operands[1] = mcore_gen_compare_reg (GEU);
2135 (define_expand "sgtu"
2136 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2137 (eq:SI (match_dup 1) (const_int 0)))]
2141 operands[1] = mcore_gen_compare_reg (LEU);
2144 (define_expand "sleu"
2145 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2146 (ne:SI (match_dup 1) (const_int 0)))]
2150 operands[1] = mcore_gen_compare_reg (LEU);
2153 (define_insn "incscc"
2154 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2155 (plus:SI (ne (reg:CC 17) (const_int 0))
2156 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
2160 (define_insn "incscc_false"
2161 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2162 (plus:SI (eq (reg:CC 17) (const_int 0))
2163 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
2167 (define_insn "decscc"
2168 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2169 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
2170 (ne (reg:CC 17) (const_int 0))))]
2174 (define_insn "decscc_false"
2175 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2176 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
2177 (eq (reg:CC 17) (const_int 0))))]
2181 ;; ------------------------------------------------------------------------
2182 ;; Conditional move patterns.
2183 ;; ------------------------------------------------------------------------
2185 (define_expand "smaxsi3"
2187 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2188 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2189 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2190 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2191 (match_dup 1) (match_dup 2)))]
2196 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2197 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2198 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2201 (lt:SI (match_dup 1) (match_dup 2)))
2203 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2204 (match_dup 1) (match_dup 2)))]
2207 ; no tstgt in 0.97, so just use cmplti (btsti x,31) and reverse move
2210 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2211 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2215 (lt:CC (match_dup 1) (const_int 0)))
2217 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2218 (match_dup 1) (const_int 0)))]
2221 (define_expand "sminsi3"
2223 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2224 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2225 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2226 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2227 (match_dup 1) (match_dup 2)))]
2232 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2233 (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2234 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2237 (lt:SI (match_dup 1) (match_dup 2)))
2239 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2240 (match_dup 1) (match_dup 2)))]
2244 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2245 ; (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2249 ; (gt:CC (match_dup 1) (const_int 0)))
2250 ; (set (match_dup 0)
2251 ; (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2252 ; (match_dup 1) (const_int 0)))]
2255 ; changed these unsigned patterns to use geu instead of ltu. it appears
2256 ; that the c-torture & ssrl test suites didn't catch these! only showed
2257 ; up in friedman's clib work. BRC 7/7/95
2259 (define_expand "umaxsi3"
2261 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2262 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2263 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2264 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2265 (match_dup 2) (match_dup 1)))]
2270 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2271 (umax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2272 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2275 (geu:SI (match_dup 1) (match_dup 2)))
2277 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2278 (match_dup 2) (match_dup 1)))]
2281 (define_expand "uminsi3"
2283 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2284 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2285 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2286 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2287 (match_dup 2) (match_dup 1)))]
2292 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2293 (umin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2294 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2297 (geu:SI (match_dup 1) (match_dup 2)))
2299 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2300 (match_dup 2) (match_dup 1)))]
2303 ;; ------------------------------------------------------------------------
2304 ;; conditional move patterns really start here
2305 ;; ------------------------------------------------------------------------
2307 ;; the "movtK" patterns are experimental. they are intended to account for
2308 ;; gcc's mucking on code such as:
2310 ;; free_ent = ((block_compress) ? 257 : 256 );
2312 ;; these patterns help to get a tstne/bgeni/inct (or equivalent) sequence
2313 ;; when both arms have constants that are +/- 1 of each other.
2315 ;; note in the following patterns that the "movtK" ones should be the first
2316 ;; one defined in each sequence. this is because the general pattern also
2317 ;; matches, so use ordering to determine priority (it's easier this way than
2318 ;; adding conditions to the general patterns). BRC
2320 ;; the U and Q constraints are necessary to ensure that reload does the
2321 ;; 'right thing'. U constrains the operand to 0 and Q to 1 for use in the
2322 ;; clrt & clrf and clrt/inct & clrf/incf patterns. BRC 6/26
2324 ;; ??? there appears to be some problems with these movtK patterns for ops
2325 ;; other than eq & ne. need to fix. 6/30 BRC
2327 ;; ------------------------------------------------------------------------
2329 ;; ------------------------------------------------------------------------
2331 ; experimental conditional move with two constants +/- 1 BRC
2333 (define_insn "movtK_1"
2334 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2336 (ne (reg:CC 17) (const_int 0))
2337 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2338 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2339 " GET_CODE (operands[1]) == CONST_INT
2340 && GET_CODE (operands[2]) == CONST_INT
2341 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
2342 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2343 "* return mcore_output_cmov (operands, 1, NULL);"
2344 [(set_attr "length" "4")])
2346 (define_insn "movt0"
2347 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2349 (ne (reg:CC 17) (const_int 0))
2350 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2351 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2359 ;; ------------------------------------------------------------------------
2361 ;; ------------------------------------------------------------------------
2363 ; experimental conditional move with two constants +/- 1 BRC
2364 (define_insn "movtK_2"
2365 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2367 (eq (reg:CC 17) (const_int 0))
2368 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2369 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2370 " GET_CODE (operands[1]) == CONST_INT
2371 && GET_CODE (operands[2]) == CONST_INT
2372 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
2373 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2374 "* return mcore_output_cmov (operands, 0, NULL);"
2375 [(set_attr "length" "4")])
2377 (define_insn "movf0"
2378 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2380 (eq (reg:CC 17) (const_int 0))
2381 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2382 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2390 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
2391 ; because the instructions are not adjacent (peepholes are related by posn -
2392 ; not by dataflow). BRC
2395 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2396 (if_then_else:SI (eq (zero_extract:SI
2397 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2399 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
2401 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
2402 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
2405 btsti %1,%2\;movf %0,%3
2406 btsti %1,%2\;movt %0,%4
2407 btsti %1,%2\;clrf %0
2408 btsti %1,%2\;clrt %0"
2409 [(set_attr "length" "4")])
2411 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
2414 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2415 (if_then_else:SI (eq (lshiftrt:SI
2416 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2419 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2420 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2421 "GET_CODE (operands[1]) == SUBREG &&
2422 GET_MODE (SUBREG_REG (operands[1])) == QImode"
2424 btsti %1,7\;movf %0,%2
2425 btsti %1,7\;movt %0,%3
2427 btsti %1,7\;clrt %0"
2428 [(set_attr "length" "4")])
2431 ;; ------------------------------------------------------------------------
2433 ;; ------------------------------------------------------------------------
2435 ;; Combine creates this from an andn instruction in a scc sequence.
2436 ;; We must recognize it to get conditional moves generated.
2438 ; experimental conditional move with two constants +/- 1 BRC
2439 (define_insn "movtK_3"
2440 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2442 (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2444 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2445 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2446 " GET_CODE (operands[2]) == CONST_INT
2447 && GET_CODE (operands[3]) == CONST_INT
2448 && ( (INTVAL (operands[2]) - INTVAL (operands[3]) == 1)
2449 || (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2452 rtx out_operands[4];
2453 out_operands[0] = operands[0];
2454 out_operands[1] = operands[2];
2455 out_operands[2] = operands[3];
2456 out_operands[3] = operands[1];
2458 return mcore_output_cmov (out_operands, 1, \"cmpnei %3,0\");
2461 [(set_attr "length" "6")])
2463 (define_insn "movt2"
2464 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2465 (if_then_else:SI (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2467 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2468 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2471 cmpnei %1,0\;movt %0,%2
2472 cmpnei %1,0\;movf %0,%3
2473 cmpnei %1,0\;clrt %0
2474 cmpnei %1,0\;clrf %0"
2475 [(set_attr "length" "4")])
2477 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
2478 ; because the instructions are not adjacent (peepholes are related by posn -
2479 ; not by dataflow). BRC
2482 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2483 (if_then_else:SI (ne (zero_extract:SI
2484 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2486 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
2488 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
2489 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
2492 btsti %1,%2\;movt %0,%3
2493 btsti %1,%2\;movf %0,%4
2494 btsti %1,%2\;clrt %0
2495 btsti %1,%2\;clrf %0"
2496 [(set_attr "length" "4")])
2498 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
2501 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2502 (if_then_else:SI (ne (lshiftrt:SI
2503 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2506 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2507 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2508 "GET_CODE (operands[1]) == SUBREG &&
2509 GET_MODE (SUBREG_REG (operands[1])) == QImode"
2511 btsti %1,7\;movt %0,%2
2512 btsti %1,7\;movf %0,%3
2514 btsti %1,7\;clrf %0"
2515 [(set_attr "length" "4")])
2517 ;; ------------------------------------------------------------------------
2519 ;; ------------------------------------------------------------------------
2521 ; experimental conditional move with two constants +/- 1 BRC
2522 (define_insn "movtK_4"
2523 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2525 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2526 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2527 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2528 "GET_CODE (operands[1]) == CONST_INT &&
2529 GET_CODE (operands[2]) == CONST_INT &&
2530 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2531 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2532 "* return mcore_output_cmov(operands, 1, NULL);"
2533 [(set_attr "length" "4")])
2535 (define_insn "movt3"
2536 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2538 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2539 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2540 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2548 ;; ------------------------------------------------------------------------
2550 ;; ------------------------------------------------------------------------
2552 ; experimental conditional move with two constants +/- 1 BRC
2553 (define_insn "movtK_5"
2554 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2556 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2557 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2558 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2559 "GET_CODE (operands[1]) == CONST_INT &&
2560 GET_CODE (operands[2]) == CONST_INT &&
2561 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2562 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2563 "* return mcore_output_cmov (operands, 0, NULL);"
2564 [(set_attr "length" "4")])
2566 (define_insn "movf1"
2567 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2569 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2570 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2571 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2579 ;; ------------------------------------------------------------------------
2581 ;; ------------------------------------------------------------------------
2583 ;; Combine creates this from an andn instruction in a scc sequence.
2584 ;; We must recognize it to get conditional moves generated.
2586 ; experimental conditional move with two constants +/- 1 BRC
2588 (define_insn "movtK_6"
2589 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2591 (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2593 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2594 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2595 "GET_CODE (operands[1]) == CONST_INT &&
2596 GET_CODE (operands[2]) == CONST_INT &&
2597 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2598 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2601 rtx out_operands[4];
2602 out_operands[0] = operands[0];
2603 out_operands[1] = operands[2];
2604 out_operands[2] = operands[3];
2605 out_operands[3] = operands[1];
2607 return mcore_output_cmov (out_operands, 0, \"cmpnei %3,0\");
2609 [(set_attr "length" "6")])
2611 (define_insn "movf3"
2612 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2613 (if_then_else:SI (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2615 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2616 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2619 cmpnei %1,0\;movf %0,%2
2620 cmpnei %1,0\;movt %0,%3
2621 cmpnei %1,0\;clrf %0
2622 cmpnei %1,0\;clrt %0"
2623 [(set_attr "length" "4")])
2625 ;; ------------------------------------------------------------------------
2627 ;; ------------------------------------------------------------------------
2629 ; experimental conditional move with two constants +/- 1 BRC
2630 (define_insn "movtK_7"
2631 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2633 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2634 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2635 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2636 "GET_CODE (operands[1]) == CONST_INT &&
2637 GET_CODE (operands[2]) == CONST_INT &&
2638 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2639 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2640 "* return mcore_output_cmov (operands, 0, NULL);"
2641 [(set_attr "length" "4")])
2643 (define_insn "movf4"
2644 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2646 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2647 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2648 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2656 ;; ------------------------------------------------------------------------
2658 ;; ------------------------------------------------------------------------
2660 ; experimental conditional move with two constants +/- 1 BRC
2661 (define_insn "movtK_8"
2662 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2664 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2665 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2666 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2667 "GET_CODE (operands[1]) == CONST_INT &&
2668 GET_CODE (operands[2]) == CONST_INT &&
2669 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2670 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2671 "* return mcore_output_cmov (operands, 1, NULL);"
2672 [(set_attr "length" "4")])
2674 (define_insn "movt4"
2675 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2677 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2678 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2679 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2687 ;; Also need patterns to recognize lt/ge, since otherwise the compiler will
2688 ;; try to output not/asri/tstne/movf.
2690 ;; ------------------------------------------------------------------------
2692 ;; ------------------------------------------------------------------------
2694 ; experimental conditional move with two constants +/- 1 BRC
2695 (define_insn "movtK_9"
2696 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2698 (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2700 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2701 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2702 "GET_CODE (operands[2]) == CONST_INT &&
2703 GET_CODE (operands[3]) == CONST_INT &&
2704 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2705 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2708 rtx out_operands[4];
2709 out_operands[0] = operands[0];
2710 out_operands[1] = operands[2];
2711 out_operands[2] = operands[3];
2712 out_operands[3] = operands[1];
2714 return mcore_output_cmov (out_operands, 1, \"btsti %3,31\");
2716 [(set_attr "length" "6")])
2718 (define_insn "movt5"
2719 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2720 (if_then_else:SI (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2722 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2723 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2726 btsti %1,31\;movt %0,%2
2727 btsti %1,31\;movf %0,%3
2728 btsti %1,31\;clrt %0
2729 btsti %1,31\;clrf %0"
2730 [(set_attr "length" "4")])
2733 ;; ------------------------------------------------------------------------
2735 ;; ------------------------------------------------------------------------
2737 ; experimental conditional move with two constants +/- 1 BRC
2738 (define_insn "movtK_10"
2739 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2741 (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2743 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2744 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2745 "GET_CODE (operands[2]) == CONST_INT &&
2746 GET_CODE (operands[3]) == CONST_INT &&
2747 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2748 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2751 rtx out_operands[4];
2752 out_operands[0] = operands[0];
2753 out_operands[1] = operands[2];
2754 out_operands[2] = operands[3];
2755 out_operands[3] = operands[1];
2757 return mcore_output_cmov (out_operands, 0, \"btsti %3,31\");
2759 [(set_attr "length" "6")])
2761 (define_insn "movf5"
2762 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2763 (if_then_else:SI (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2765 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2766 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2769 btsti %1,31\;movf %0,%2
2770 btsti %1,31\;movt %0,%3
2771 btsti %1,31\;clrf %0
2772 btsti %1,31\;clrt %0"
2773 [(set_attr "length" "4")])
2775 ;; ------------------------------------------------------------------------
2776 ;; Bitfield extract (xtrbN)
2777 ;; ------------------------------------------------------------------------
2779 ; sometimes we're better off using QI/HI mode and letting the machine indep.
2780 ; part expand insv and extv.
2782 ; e.g., sequences like:a [an insertion]
2785 ; movi r7,0x00ffffff
2787 ; stw r8,(r6) r8 dead
2792 ; stb r8,(r6) r8 dead
2794 ; it looks like always using SI mode is a win except in this type of code
2795 ; (when adjacent bit fields collapse on a byte or halfword boundary). when
2796 ; expanding with SI mode, non-adjacent bit field masks fold, but with QI/HI
2797 ; mode, they do not. one thought is to add some peepholes to cover cases
2798 ; like the above, but this is not a general solution.
2800 ; -mword-bitfields expands/inserts using SI mode. otherwise, do it with
2801 ; the smallest mode possible (using the machine indep. expansions). BRC
2803 ;(define_expand "extv"
2804 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2805 ; (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2806 ; (match_operand:SI 2 "const_int_operand" "")
2807 ; (match_operand:SI 3 "const_int_operand" "")))
2808 ; (clobber (reg:CC 17))]
2812 ; if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) % 8 != 0)
2814 ; if (TARGET_W_FIELD)
2816 ; rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2817 ; rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2819 ; emit_insn (gen_rtx (SET, SImode, operands[0], operands[1]));
2820 ; emit_insn (gen_rtx (SET, SImode, operands[0],
2821 ; gen_rtx (ASHIFT, SImode, operands[0], lshft)));
2822 ; emit_insn (gen_rtx (SET, SImode, operands[0],
2823 ; gen_rtx (ASHIFTRT, SImode, operands[0], rshft)));
2831 (define_expand "extv"
2832 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2833 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2834 (match_operand:SI 2 "const_int_operand" "")
2835 (match_operand:SI 3 "const_int_operand" "")))
2836 (clobber (reg:CC 17))]
2840 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2842 /* 8 bit field, aligned properly, use the xtrb[0123]+sext sequence */
2843 /* not DONE, not FAIL, but let the RTL get generated... */
2845 else if (TARGET_W_FIELD)
2847 /* Arbitrary placement; note that the tree->rtl generator will make
2848 something close to this if we return FAIL */
2849 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2850 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2851 rtx tmp1 = gen_reg_rtx (SImode);
2852 rtx tmp2 = gen_reg_rtx (SImode);
2854 emit_insn (gen_rtx (SET, SImode, tmp1, operands[1]));
2855 emit_insn (gen_rtx (SET, SImode, tmp2,
2856 gen_rtx (ASHIFT, SImode, tmp1, lshft)));
2857 emit_insn (gen_rtx (SET, SImode, operands[0],
2858 gen_rtx (ASHIFTRT, SImode, tmp2, rshft)));
2863 /* let the caller choose an alternate sequence */
2868 (define_expand "extzv"
2869 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2870 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2871 (match_operand:SI 2 "const_int_operand" "")
2872 (match_operand:SI 3 "const_int_operand" "")))
2873 (clobber (reg:CC 17))]
2877 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2879 /* 8 bit field, aligned properly, use the xtrb[0123] sequence */
2880 /* let the template generate some RTL.... */
2882 else if (CONST_OK_FOR_K ((1 << INTVAL (operands[2])) - 1))
2884 /* A narrow bit-field (<=5 bits) means we can do a shift to put
2885 it in place and then use an andi to extract it.
2886 This is as good as a shiftleft/shiftright. */
2889 rtx mask = GEN_INT ((1 << INTVAL (operands[2])) - 1);
2891 if (INTVAL (operands[3]) == 0)
2893 shifted = operands[1];
2897 rtx rshft = GEN_INT (INTVAL (operands[3]));
2898 shifted = gen_reg_rtx (SImode);
2899 emit_insn (gen_rtx (SET, SImode, shifted,
2900 gen_rtx (LSHIFTRT, SImode, operands[1], rshft)));
2902 emit_insn (gen_rtx (SET, SImode, operands[0],
2903 gen_rtx (AND, SImode, shifted, mask)));
2906 else if (TARGET_W_FIELD)
2908 /* Arbitrary pattern; play shift/shift games to get it.
2909 * this is pretty much what the caller will do if we say FAIL */
2910 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2911 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2912 rtx tmp1 = gen_reg_rtx (SImode);
2913 rtx tmp2 = gen_reg_rtx (SImode);
2915 emit_insn (gen_rtx (SET, SImode, tmp1, operands[1]));
2916 emit_insn (gen_rtx (SET, SImode, tmp2,
2917 gen_rtx (ASHIFT, SImode, tmp1, lshft)));
2918 emit_insn (gen_rtx (SET, SImode, operands[0],
2919 gen_rtx (LSHIFTRT, SImode, tmp2, rshft)));
2924 /* Make the compiler figure out some alternative mechanism. */
2928 /* Emit the RTL pattern; something will match it later. */
2931 (define_expand "insv"
2932 [(set (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "")
2933 (match_operand:SI 1 "const_int_operand" "")
2934 (match_operand:SI 2 "const_int_operand" ""))
2935 (match_operand:SI 3 "general_operand" ""))
2936 (clobber (reg:CC 17))]
2940 if (mcore_expand_insv (operands))
2951 ;; the xtrb[0123] instructions handily get at 8-bit fields on nice boundaries.
2952 ;; but then, they do force you through r1.
2954 ;; the combiner will build such patterns for us, so we'll make them available
2957 ;; Note that we have both SIGNED and UNSIGNED versions of these...
2961 ;; These no longer worry about the clobbering of CC bit; not sure this is
2964 ;; the SIGNED versions of these
2967 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2968 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
2972 xtrb0 %0,%1\;sextb %0"
2973 [(set_attr "type" "shift")])
2976 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2977 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
2979 "xtrb1 %0,%1\;sextb %0"
2980 [(set_attr "type" "shift")])
2983 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2984 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
2986 "xtrb2 %0,%1\;sextb %0"
2987 [(set_attr "type" "shift")])
2990 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2991 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0") (const_int 8) (const_int 0)))]
2994 [(set_attr "type" "shift")])
2996 ;; the UNSIGNED uses of xtrb[0123]
2999 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
3000 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
3005 [(set_attr "type" "shift")])
3008 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
3009 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
3012 [(set_attr "type" "shift")])
3015 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
3016 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
3019 [(set_attr "type" "shift")])
3021 ;; this can be peepholed if it follows a ldb ...
3023 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
3024 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 0)))]
3028 xtrb3 %0,%1\;zextb %0"
3029 [(set_attr "type" "shift")])
3032 ;; ------------------------------------------------------------------------
3033 ;; Block move - adapted from m88k.md
3034 ;; ------------------------------------------------------------------------
3036 (define_expand "movstrsi"
3037 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
3038 (mem:BLK (match_operand:BLK 1 "" "")))
3039 (use (match_operand:SI 2 "general_operand" ""))
3040 (use (match_operand:SI 3 "immediate_operand" ""))])]
3044 rtx dest_mem = operands[0];
3045 rtx src_mem = operands[1];
3046 operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
3047 operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
3048 mcore_expand_block_move (dest_mem, src_mem, operands);
3052 ;; ;;; ??? These patterns are meant to be generated from expand_block_move,
3053 ;; ;;; but they currently are not.
3056 ;; [(set (match_operand:QI 0 "mcore_arith_reg_operand" "=r")
3057 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
3060 ;; [(set_attr "type" "load")])
3063 ;; [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
3064 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
3067 ;; [(set_attr "type" "load")])
3070 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
3071 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
3074 ;; [(set_attr "type" "load")])
3077 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
3078 ;; (match_operand:QI 1 "mcore_arith_reg_operand" "r"))]
3081 ;; [(set_attr "type" "store")])
3084 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
3085 ;; (match_operand:HI 1 "mcore_arith_reg_operand" "r"))]
3088 ;; [(set_attr "type" "store")])
3091 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
3092 ;; (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
3095 ;; [(set_attr "type" "store")])
3097 ;; ------------------------------------------------------------------------
3098 ;; Misc Optimizing quirks
3099 ;; ------------------------------------------------------------------------
3101 ;; pair to catch constructs like: (int *)((p+=4)-4) which happen
3102 ;; in stdarg/varargs traversal. This changes a 3 insn sequence to a 2
3103 ;; insn sequence. -- RBE 11/30/95
3106 (set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
3107 (match_operand:SI 1 "mcore_arith_reg_operand" "+r"))
3108 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
3109 "GET_CODE(operands[2]) == CONST_INT"
3111 [(set_attr "length" "4")])
3115 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3116 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
3117 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
3118 "GET_CODE(operands[2]) == CONST_INT &&
3119 operands[0] != operands[1]"
3120 [(set (match_dup 0) (match_dup 1))
3121 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))])
3126 ; note: in the following patterns, use mcore_is_dead() to ensure that the
3127 ; reg we may be trashing really is dead. reload doesn't always mark
3128 ; deaths, so mcore_is_dead() (see mcore.c) scans forward to find its death. BRC
3130 ;;; A peephole to convert the 3 instruction sequence generated by reload
3131 ;;; to load a FP-offset address into a 2 instruction sequence.
3132 ;;; ??? This probably never matches anymore.
3134 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3135 (match_operand:SI 1 "const_int_operand" "J"))
3136 (set (match_dup 0) (neg:SI (match_dup 0)))
3138 (plus:SI (match_dup 0)
3139 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
3140 "CONST_OK_FOR_J (INTVAL (operands[1]))"
3141 "error\;mov %0,%2\;subi %0,%1")
3143 ;; Moves of inlinable constants are done late, so when a 'not' is generated
3144 ;; it is never combined with the following 'and' to generate an 'andn' b/c
3145 ;; the combiner never sees it. use a peephole to pick up this case (happens
3146 ;; mostly with bitfields) BRC
3149 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3150 (match_operand:SI 1 "const_int_operand" "i"))
3151 (set (match_operand:SI 2 "mcore_arith_reg_operand" "r")
3152 (and:SI (match_dup 2) (match_dup 0)))]
3153 "mcore_const_trick_uses_not (INTVAL (operands[1])) &&
3154 operands[0] != operands[2] &&
3155 mcore_is_dead (insn, operands[0])"
3156 "* return mcore_output_andn (insn, operands);")
3158 ; when setting or clearing just two bits, it's cheapest to use two bseti's
3159 ; or bclri's. only happens when relaxing immediates. BRC
3162 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3163 (match_operand:SI 1 "const_int_operand" ""))
3164 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3165 (ior:SI (match_dup 2) (match_dup 0)))]
3166 "TARGET_HARDLIT && mcore_num_ones (INTVAL (operands[1])) == 2 &&
3167 mcore_is_dead (insn, operands[0])"
3168 "* return mcore_output_bseti (operands[2], INTVAL (operands[1]));")
3171 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3172 (match_operand:SI 1 "const_int_operand" ""))
3173 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3174 (and:SI (match_dup 2) (match_dup 0)))]
3175 "TARGET_HARDLIT && mcore_num_zeros (INTVAL (operands[1])) == 2 &&
3176 mcore_is_dead (insn, operands[0])"
3177 "* return mcore_output_bclri (operands[2], INTVAL (operands[1]));")
3179 ; change an and with a mask that has a single cleared bit into a bclri. this
3180 ; handles QI and HI mode values using the knowledge that the most significant
3181 ; bits don't matter.
3184 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3185 (match_operand:SI 1 "const_int_operand" ""))
3186 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3187 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
3189 "GET_CODE (operands[3]) == SUBREG &&
3190 GET_MODE (SUBREG_REG (operands[3])) == QImode &&
3191 mcore_num_zeros (INTVAL (operands[1]) | 0xffffff00) == 1 &&
3192 mcore_is_dead (insn, operands[0])"
3194 if (! mcore_is_same_reg (operands[2], operands[3]))
3195 output_asm_insn (\"mov\\t%2,%3\", operands);
3196 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffffff00);")
3198 /* do not fold these together -- mode is lost at final output phase */
3201 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3202 (match_operand:SI 1 "const_int_operand" ""))
3203 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3204 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
3206 "GET_CODE (operands[3]) == SUBREG &&
3207 GET_MODE (SUBREG_REG (operands[3])) == HImode &&
3208 mcore_num_zeros (INTVAL (operands[1]) | 0xffff0000) == 1 &&
3209 operands[2] == operands[3] &&
3210 mcore_is_dead (insn, operands[0])"
3212 if (! mcore_is_same_reg (operands[2], operands[3]))
3213 output_asm_insn (\"mov\\t%2,%3\", operands);
3214 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffff0000);")
3216 ; This peephole helps when using -mwide-bitfields to widen fields so they
3217 ; collapse. This, however, has the effect that a narrower mode is not used
3220 ; e.g., sequences like:
3223 ; movi r7,0x00ffffff
3225 ; stw r8,(r6) r8 dead
3227 ; get peepholed to become:
3230 ; stb r8,(r6) r8 dead
3232 ; Do only easy addresses that have no offset. This peephole is also applied
3233 ; to halfwords. We need to check that the load is non-volatile before we get
3237 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3238 (match_operand:SI 1 "memory_operand" ""))
3239 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3240 (match_operand:SI 3 "const_int_operand" ""))
3241 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
3242 (set (match_operand:SI 4 "memory_operand" "") (match_dup 0))]
3243 "mcore_is_dead (insn, operands[0]) &&
3244 ! MEM_VOLATILE_P (operands[1]) &&
3245 mcore_is_dead (insn, operands[2]) &&
3246 (mcore_byte_offset (INTVAL (operands[3])) > -1 ||
3247 mcore_halfword_offset (INTVAL (operands[3])) > -1) &&
3248 ! MEM_VOLATILE_P (operands[4]) &&
3249 GET_CODE (XEXP (operands[4], 0)) == REG"
3253 enum machine_mode mode;
3254 rtx base_reg = XEXP (operands[4], 0);
3256 if ((ofs = mcore_byte_offset (INTVAL (operands[3]))) > -1)
3258 else if ((ofs = mcore_halfword_offset (INTVAL (operands[3]))) > -1)
3264 operands[4] = gen_rtx (MEM, mode,
3265 gen_rtx (PLUS, SImode, base_reg, GEN_INT(ofs)));
3267 operands[4] = gen_rtx (MEM, mode, base_reg);
3270 return \"movi %0,0\\n\\tst.b %0,%4\";
3272 return \"movi %0,0\\n\\tst.h %0,%4\";
3275 ; from sop11. get btsti's for (LT A 0) where A is a QI or HI value
3278 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3279 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))
3281 (lt:CC (match_dup 0)
3283 "mcore_is_dead (insn, operands[0])"
3287 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3288 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))
3290 (lt:CC (match_dup 0)
3292 "mcore_is_dead (insn, operands[0])"
3295 ; Pick up a tst. This combination happens because the immediate is not
3296 ; allowed to fold into one of the operands of the tst. Does not happen
3297 ; when relaxing immediates. BRC
3300 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3301 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
3303 (and:SI (match_dup 0)
3304 (match_operand:SI 2 "mcore_literal_K_operand" "")))
3305 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
3306 "mcore_is_dead (insn, operands[0])"
3307 "movi %0,%2\;tst %1,%0")
3310 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3311 (if_then_else:SI (ne (zero_extract:SI
3312 (match_operand:SI 1 "mcore_arith_reg_operand" "")
3314 (match_operand:SI 2 "mcore_literal_K_operand" ""))
3316 (match_operand:SI 3 "mcore_arith_imm_operand" "")
3317 (match_operand:SI 4 "mcore_arith_imm_operand" "")))
3318 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
3322 unsigned int op0 = REGNO (operands[0]);
3324 if (GET_CODE (operands[3]) == REG)
3326 if (REGNO (operands[3]) == op0 && GET_CODE (operands[4]) == CONST_INT
3327 && INTVAL (operands[4]) == 0)
3328 return \"btsti %1,%2\\n\\tclrf %0\";
3329 else if (GET_CODE (operands[4]) == REG)
3331 if (REGNO (operands[4]) == op0)
3332 return \"btsti %1,%2\\n\\tmovf %0,%3\";
3333 else if (REGNO (operands[3]) == op0)
3334 return \"btsti %1,%2\\n\\tmovt %0,%4\";
3339 else if (GET_CODE (operands[3]) == CONST_INT
3340 && INTVAL (operands[3]) == 0
3341 && GET_CODE (operands[4]) == REG)
3342 return \"btsti %1,%2\\n\\tclrt %0\";
3348 ; experimental - do the constant folding ourselves. note that this isn't
3349 ; re-applied like we'd really want. ie., four ands collapse into two
3350 ; instead of one. this is because peepholes are applied as a sliding
3351 ; window. the peephole does not generate new rtl's, but instead slides
3352 ; across the rtl's generating machine instructions. it would be nice
3353 ; if the peephole optimizer is changed to re-apply patterns and to gen
3354 ; new rtl's. this is more flexible. the pattern below helps when we're
3355 ; not using relaxed immediates. BRC
3358 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3359 ; (match_operand:SI 1 "const_int_operand" ""))
3360 ; (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3361 ; (and:SI (match_dup 2) (match_dup 0)))
3362 ; (set (match_dup 0)
3363 ; (match_operand:SI 3 "const_int_operand" ""))
3364 ; (set (match_dup 2)
3365 ; (and:SI (match_dup 2) (match_dup 0)))]
3366 ; "!TARGET_RELAX_IMM && mcore_is_dead (insn, operands[0]) &&
3367 ; mcore_const_ok_for_inline (INTVAL (operands[1]) & INTVAL (operands[3]))"
3370 ; rtx out_operands[2];
3371 ; out_operands[0] = operands[0];
3372 ; out_operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[3]));
3374 ; output_inline_const (SImode, out_operands);
3376 ; output_asm_insn (\"and %2,%0\", operands);
3381 ; BRC: for inlining get rid of extra test - experimental
3383 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3384 ; (ne:SI (reg:CC 17) (const_int 0)))
3385 ; (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))
3387 ; (if_then_else (eq (reg:CC 17) (const_int 0))
3388 ; (label_ref (match_operand 1 "" ""))
3393 ; if (get_attr_length (insn) == 10)
3395 ; output_asm_insn (\"bt 2f\\n\\tjmpi [1f]\", operands);
3396 ; output_asm_insn (\".align 2\\n1:\", operands);
3397 ; output_asm_insn (\".long %1\\n2:\", operands);
3400 ; return \"bf %l1\";
3404 ;;; Special patterns for dealing with the constant pool.
3406 ;;; 4 byte integer in line.
3408 (define_insn "consttable_4"
3409 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 0)]
3413 assemble_integer (operands[0], 4, BITS_PER_WORD, 1);
3416 [(set_attr "length" "4")])
3418 ;;; align to a four byte boundary.
3420 (define_insn "align_4"
3421 [(unspec_volatile [(const_int 0)] 1)]
3425 ;;; Handle extra constant pool entries created during final pass.
3427 (define_insn "consttable_end"
3428 [(unspec_volatile [(const_int 0)] 2)]
3430 "* return mcore_output_jump_label_table ();")
3433 ;; Stack allocation -- in particular, for alloca().
3434 ;; this is *not* what we use for entry into functions.
3436 ;; This is how we allocate stack space. If we are allocating a
3437 ;; constant amount of space and we know it is less than 4096
3438 ;; bytes, we need do nothing.
3440 ;; If it is more than 4096 bytes, we need to probe the stack
3443 ;; operands[1], the distance is a POSITIVE number indicating that we
3444 ;; are allocating stack space
3446 (define_expand "allocate_stack"
3449 (match_operand:SI 1 "general_operand" "")))
3450 (set (match_operand:SI 0 "register_operand" "=r")
3455 /* if he wants no probing, just do it for him. */
3456 if (mcore_stack_increment == 0)
3458 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,operands[1]));
3459 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3463 /* for small constant growth, we unroll the code */
3464 if (GET_CODE (operands[1]) == CONST_INT
3465 && INTVAL (operands[1]) < 8*STACK_UNITS_MAXSTEP)
3467 int left = INTVAL(operands[1]);
3469 /* if it's a long way, get close enough for a last shot */
3470 if (left >= STACK_UNITS_MAXSTEP)
3472 rtx tmp = gen_reg_rtx (Pmode);
3473 emit_insn (gen_movsi (tmp, GEN_INT(STACK_UNITS_MAXSTEP)));
3476 rtx memref = gen_rtx (MEM, SImode, stack_pointer_rtx);
3477 MEM_VOLATILE_P (memref) = 1;
3478 emit_insn(gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3479 emit_insn(gen_movsi (memref, stack_pointer_rtx));
3480 left -= STACK_UNITS_MAXSTEP;
3481 } while (left > STACK_UNITS_MAXSTEP);
3483 /* performs the final adjustment */
3484 emit_insn(gen_addsi3(stack_pointer_rtx,stack_pointer_rtx,GEN_INT(-left)));
3485 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3491 rtx loop_label = gen_label_rtx ();
3492 rtx step = gen_reg_rtx (Pmode);
3493 rtx tmp = gen_reg_rtx (Pmode);
3497 emit_insn(gen_movsi(tmp, operands[1]));
3498 emit_insn(gen_movsi(step, GEN_INT(STACK_UNITS_MAXSTEP)));
3500 if (GET_CODE (operands[1]) != CONST_INT)
3502 out_label = gen_label_rtx ();
3503 emit_insn (gen_cmpsi (step, tmp)); /* quick out */
3504 emit_jump_insn (gen_bgeu (out_label));
3507 /* run a loop that steps it incrementally */
3508 emit_label (loop_label);
3510 /* extend a step, probe, and adjust remaining count */
3511 emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx, step));
3512 memref = gen_rtx (MEM, SImode, stack_pointer_rtx);
3513 MEM_VOLATILE_P (memref) = 1;
3514 emit_insn(gen_movsi(memref, stack_pointer_rtx));
3515 emit_insn(gen_subsi3(tmp, tmp, step));
3517 /* loop condition -- going back up */
3518 emit_insn (gen_cmpsi (step, tmp));
3519 emit_jump_insn (gen_bltu (loop_label));
3522 emit_label (out_label);
3524 /* bump the residual */
3525 emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx, tmp));
3526 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3529 /* simple one-shot -- ensure register and do a subtract.
3530 * this does NOT comply with the ABI. */
3531 emit_insn(gen_movsi(tmp, operands[1]));
3532 emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx, tmp));
3533 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);