| blob | 77f7f34830fc71a9e8d7c70af981c2b14fa66919 |
1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
4 ;; David Mosberger <davidm@hpl.hp.com>.
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26 ;; reload. This will be fixed once scheduling support is turned on.
28 ;; ??? Optimize for post-increment addressing modes.
30 ;; ??? fselect is not supported, because there is no integer register
31 ;; equivalent.
33 ;; ??? fp abs/min/max instructions may also work for integer values.
35 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36 ;; it assumes the operand is a register and takes REGNO of it without checking.
38 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39 ;; it assumes the operand is a register and takes REGNO of it without checking.
41 ;; ??? Go through list of documented named patterns and look for more to
42 ;; implement.
44 ;; ??? Go through instruction manual and look for more instructions that
45 ;; can be emitted.
47 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
49 ;; ??? Need a better way to describe alternate fp status registers.
51 (define_constants
52 [; Relocations
53 (UNSPEC_LTOFF_DTPMOD 0)
54 (UNSPEC_LTOFF_DTPREL 1)
55 (UNSPEC_DTPREL 2)
56 (UNSPEC_LTOFF_TPREL 3)
57 (UNSPEC_TPREL 4)
59 (UNSPEC_LD_BASE 9)
60 (UNSPEC_GR_SPILL 10)
61 (UNSPEC_GR_RESTORE 11)
62 (UNSPEC_FR_SPILL 12)
63 (UNSPEC_FR_RESTORE 13)
64 (UNSPEC_FR_RECIP_APPROX 14)
65 (UNSPEC_PRED_REL_MUTEX 15)
66 (UNSPEC_GETF_EXP 16)
67 (UNSPEC_PIC_CALL 17)
68 (UNSPEC_MF 18)
69 (UNSPEC_CMPXCHG_ACQ 19)
70 (UNSPEC_FETCHADD_ACQ 20)
71 (UNSPEC_BSP_VALUE 21)
72 (UNSPEC_FLUSHRS 22)
73 (UNSPEC_BUNDLE_SELECTOR 23)
74 (UNSPEC_ADDP4 24)
75 (UNSPEC_PROLOGUE_USE 25)
76 ])
78 (define_constants
79 [(UNSPECV_ALLOC 0)
80 (UNSPECV_BLOCKAGE 1)
81 (UNSPECV_INSN_GROUP_BARRIER 2)
82 (UNSPECV_BREAK 3)
83 (UNSPECV_SET_BSP 4)
84 (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls
85 (UNSPECV_PSAC_NORMAL 6)
86 ])
87 \f
88 ;; ::::::::::::::::::::
89 ;; ::
90 ;; :: Attributes
91 ;; ::
92 ;; ::::::::::::::::::::
94 ;; Processor type. This attribute must exactly match the processor_type
95 ;; enumeration in ia64.h.
96 (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune")))
98 ;; Instruction type. This primarily determines how instructions can be
99 ;; packed in bundles, and secondarily affects scheduling to function units.
101 ;; A alu, can go in I or M syllable of a bundle
102 ;; I integer
103 ;; M memory
104 ;; F floating-point
105 ;; B branch
106 ;; L long immediate, takes two syllables
107 ;; S stop bit
109 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
110 ;; check this in md_reorg? Currently use unknown for patterns which emit
111 ;; multiple instructions, patterns which emit 0 instructions, and patterns
112 ;; which emit instruction that can go in any slot (e.g. nop).
114 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
115 fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
116 chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
117 syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f,
118 nop_i,nop_m,nop_x,lfetch,pre_cycle"
119 (const_string "unknown"))
121 ;; chk_s has an I and an M form; use type A for convenience.
122 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
123 (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M")
124 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
125 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
126 (eq_attr "itanium_class" "lfetch") (const_string "M")
127 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
128 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
129 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
130 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
131 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
132 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
133 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
134 (eq_attr "itanium_class" "stop_bit") (const_string "S")
135 (eq_attr "itanium_class" "nop_x") (const_string "X")
136 (eq_attr "itanium_class" "long_i") (const_string "L")]
137 (const_string "unknown")))
139 (define_attr "itanium_requires_unit0" "no,yes"
140 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
141 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
142 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
143 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
144 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
145 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
146 (const_string "no")))
148 ;; Predication. True iff this instruction can be predicated.
150 (define_attr "predicable" "no,yes" (const_string "yes"))
152 \f
154 ;; DFA descriptions of ia64 processors used for insn scheduling and
155 ;; bundling.
157 (automata_option "ndfa")
159 ;; Uncomment the following line to output automata for debugging.
160 ;; (automata_option "v")
162 (automata_option "w")
164 ;;(automata_option "no-minimization")
167 (include "itanium1.md")
168 (include "itanium2.md")
170 \f
171 ;; ::::::::::::::::::::
172 ;; ::
173 ;; :: Moves
174 ;; ::
175 ;; ::::::::::::::::::::
177 ;; Set of a single predicate register. This is only used to implement
178 ;; pr-to-pr move and complement.
180 (define_insn "*movcci"
181 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
182 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
183 ""
184 "@
185 cmp.ne %0, p0 = r0, r0
186 cmp.eq %0, p0 = r0, r0
187 (%1) cmp.eq.unc %0, p0 = r0, r0"
188 [(set_attr "itanium_class" "icmp")
189 (set_attr "predicable" "no")])
191 (define_insn "movbi"
192 [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
193 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
194 ""
195 "@
196 cmp.ne %0, %I0 = r0, r0
197 cmp.eq %0, %I0 = r0, r0
198 #
199 #
200 tbit.nz %0, %I0 = %1, 0
201 adds %0 = %1, r0
202 ld1%O1 %0 = %1%P1
203 st1%Q0 %0 = %1%P0
204 mov %0 = %1"
205 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
207 (define_split
208 [(set (match_operand:BI 0 "register_operand" "")
209 (match_operand:BI 1 "register_operand" ""))]
210 "reload_completed
211 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
212 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
213 [(cond_exec (ne (match_dup 1) (const_int 0))
214 (set (match_dup 0) (const_int 1)))
215 (cond_exec (eq (match_dup 1) (const_int 0))
216 (set (match_dup 0) (const_int 0)))]
217 "")
219 (define_split
220 [(set (match_operand:BI 0 "register_operand" "")
221 (match_operand:BI 1 "register_operand" ""))]
222 "reload_completed
223 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
224 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
225 [(set (match_dup 2) (match_dup 4))
226 (set (match_dup 3) (match_dup 5))
227 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
228 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
229 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
230 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
231 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
233 (define_expand "movqi"
234 [(set (match_operand:QI 0 "general_operand" "")
235 (match_operand:QI 1 "general_operand" ""))]
236 ""
237 {
238 rtx op1 = ia64_expand_move (operands[0], operands[1]);
239 if (!op1)
240 DONE;
241 operands[1] = op1;
242 })
244 (define_insn "*movqi_internal"
245 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
246 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
247 "ia64_move_ok (operands[0], operands[1])"
248 "@
249 mov %0 = %r1
250 addl %0 = %1, r0
251 ld1%O1 %0 = %1%P1
252 st1%Q0 %0 = %r1%P0
253 getf.sig %0 = %1
254 setf.sig %0 = %r1
255 mov %0 = %1"
256 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
258 (define_expand "movhi"
259 [(set (match_operand:HI 0 "general_operand" "")
260 (match_operand:HI 1 "general_operand" ""))]
261 ""
262 {
263 rtx op1 = ia64_expand_move (operands[0], operands[1]);
264 if (!op1)
265 DONE;
266 operands[1] = op1;
267 })
269 (define_insn "*movhi_internal"
270 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
271 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
272 "ia64_move_ok (operands[0], operands[1])"
273 "@
274 mov %0 = %r1
275 addl %0 = %1, r0
276 ld2%O1 %0 = %1%P1
277 st2%Q0 %0 = %r1%P0
278 getf.sig %0 = %1
279 setf.sig %0 = %r1
280 mov %0 = %1"
281 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
283 (define_expand "movsi"
284 [(set (match_operand:SI 0 "general_operand" "")
285 (match_operand:SI 1 "general_operand" ""))]
286 ""
287 {
288 rtx op1 = ia64_expand_move (operands[0], operands[1]);
289 if (!op1)
290 DONE;
291 operands[1] = op1;
292 })
294 ;; This is used during early compilation to delay the decision on
295 ;; how to refer to a variable as long as possible. This is especially
296 ;; important between initial rtl generation and optimization for
297 ;; deferred functions, since we may acquire additional information
298 ;; on the variables used in the meantime.
300 (define_insn_and_split "movsi_symbolic"
301 [(set (match_operand:SI 0 "register_operand" "=r")
302 (match_operand:SI 1 "symbolic_operand" "s"))
303 (clobber (match_scratch:DI 2 "=r"))
304 (use (reg:DI 1))]
305 ""
306 "* abort ();"
307 "!no_new_pseudos || reload_completed"
308 [(const_int 0)]
309 {
310 rtx scratch = operands[2];
311 if (!reload_completed)
312 scratch = gen_reg_rtx (Pmode);
313 ia64_expand_load_address (operands[0], operands[1], scratch);
314 DONE;
315 })
317 (define_insn "*movsi_internal"
318 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
319 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
320 "ia64_move_ok (operands[0], operands[1])"
321 "@
322 mov %0 = %r1
323 addl %0 = %1, r0
324 movl %0 = %1
325 ld4%O1 %0 = %1%P1
326 st4%Q0 %0 = %r1%P0
327 getf.sig %0 = %1
328 setf.sig %0 = %r1
329 mov %0 = %1
330 mov %0 = %1
331 mov %0 = %r1"
332 ;; frar_m, toar_m ??? why not frar_i and toar_i
333 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
335 (define_expand "movdi"
336 [(set (match_operand:DI 0 "general_operand" "")
337 (match_operand:DI 1 "general_operand" ""))]
338 ""
339 {
340 rtx op1 = ia64_expand_move (operands[0], operands[1]);
341 if (!op1)
342 DONE;
343 operands[1] = op1;
344 })
346 ;; This is used during early compilation to delay the decision on
347 ;; how to refer to a variable as long as possible. This is especially
348 ;; important between initial rtl generation and optimization for
349 ;; deferred functions, since we may acquire additional information
350 ;; on the variables used in the meantime.
352 (define_insn_and_split "movdi_symbolic"
353 [(set (match_operand:DI 0 "register_operand" "=r")
354 (match_operand:DI 1 "symbolic_operand" "s"))
355 (clobber (match_scratch:DI 2 "=r"))
356 (use (reg:DI 1))]
357 ""
358 "* abort ();"
359 "!no_new_pseudos || reload_completed"
360 [(const_int 0)]
361 {
362 rtx scratch = operands[2];
363 if (!reload_completed)
364 scratch = gen_reg_rtx (Pmode);
365 ia64_expand_load_address (operands[0], operands[1], scratch);
366 DONE;
367 })
369 (define_insn "*movdi_internal"
370 [(set (match_operand:DI 0 "destination_operand"
371 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
372 (match_operand:DI 1 "move_operand"
373 "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
374 "ia64_move_ok (operands[0], operands[1])"
375 {
376 static const char * const alt[] = {
377 "%,mov %0 = %r1",
378 "%,addl %0 = %1, r0",
379 "%,movl %0 = %1",
380 "%,ld8%O1 %0 = %1%P1",
381 "%,st8%Q0 %0 = %r1%P0",
382 "%,getf.sig %0 = %1",
383 "%,setf.sig %0 = %r1",
384 "%,mov %0 = %1",
385 "%,ldf8 %0 = %1%P1",
386 "%,stf8 %0 = %1%P0",
387 "%,mov %0 = %1",
388 "%,mov %0 = %r1",
389 "%,mov %0 = %1",
390 "%,mov %0 = %1",
391 "%,mov %0 = %1",
392 "%,mov %0 = %1",
393 "mov %0 = pr",
394 "mov pr = %1, -1"
395 };
397 if (which_alternative == 2 && ! TARGET_NO_PIC
398 && symbolic_operand (operands[1], VOIDmode))
399 abort ();
401 return alt[which_alternative];
402 }
403 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
405 (define_split
406 [(set (match_operand:DI 0 "register_operand" "")
407 (match_operand:DI 1 "symbolic_operand" ""))]
408 "reload_completed && ! TARGET_NO_PIC"
409 [(const_int 0)]
410 {
411 ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
412 DONE;
413 })
415 (define_expand "load_fptr"
416 [(set (match_dup 2)
417 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "")))
418 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
419 ""
420 {
421 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
422 operands[3] = gen_rtx_MEM (DImode, operands[2]);
423 RTX_UNCHANGING_P (operands[3]) = 1;
424 })
426 (define_insn "*load_fptr_internal1"
427 [(set (match_operand:DI 0 "register_operand" "=r")
428 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
429 ""
430 "addl %0 = @ltoff(@fptr(%1)), gp"
431 [(set_attr "itanium_class" "ialu")])
433 (define_insn "load_gprel"
434 [(set (match_operand:DI 0 "register_operand" "=r")
435 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
436 ""
437 "addl %0 = @gprel(%1), gp"
438 [(set_attr "itanium_class" "ialu")])
440 (define_insn "gprel64_offset"
441 [(set (match_operand:DI 0 "register_operand" "=r")
442 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
443 ""
444 "movl %0 = @gprel(%1)"
445 [(set_attr "itanium_class" "long_i")])
447 (define_expand "load_gprel64"
448 [(set (match_dup 2)
449 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3)))
450 (set (match_operand:DI 0 "register_operand" "")
451 (plus:DI (match_dup 3) (match_dup 2)))]
452 ""
453 {
454 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
455 operands[3] = pic_offset_table_rtx;
456 })
458 (define_expand "load_symptr"
459 [(set (match_operand:DI 2 "register_operand" "")
460 (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" "")))
461 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
462 ""
463 {
464 operands[3] = gen_rtx_MEM (DImode, operands[2]);
465 operands[4] = pic_offset_table_rtx;
466 RTX_UNCHANGING_P (operands[3]) = 1;
467 })
469 (define_insn "*load_symptr_internal1"
470 [(set (match_operand:DI 0 "register_operand" "=r")
471 (plus:DI (reg:DI 1) (match_operand 1 "got_symbolic_operand" "s")))]
472 ""
473 "addl %0 = @ltoff(%1), gp"
474 [(set_attr "itanium_class" "ialu")])
476 (define_insn "load_ltoff_dtpmod"
477 [(set (match_operand:DI 0 "register_operand" "=r")
478 (plus:DI (reg:DI 1)
479 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
480 UNSPEC_LTOFF_DTPMOD)))]
481 ""
482 "addl %0 = @ltoff(@dtpmod(%1)), gp"
483 [(set_attr "itanium_class" "ialu")])
485 (define_insn "load_ltoff_dtprel"
486 [(set (match_operand:DI 0 "register_operand" "=r")
487 (plus:DI (reg:DI 1)
488 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
489 UNSPEC_LTOFF_DTPREL)))]
490 ""
491 "addl %0 = @ltoff(@dtprel(%1)), gp"
492 [(set_attr "itanium_class" "ialu")])
494 (define_expand "load_dtprel"
495 [(set (match_operand:DI 0 "register_operand" "")
496 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
497 UNSPEC_DTPREL))]
498 ""
499 "")
501 (define_insn "*load_dtprel64"
502 [(set (match_operand:DI 0 "register_operand" "=r")
503 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
504 UNSPEC_DTPREL))]
505 "TARGET_TLS64"
506 "movl %0 = @dtprel(%1)"
507 [(set_attr "itanium_class" "long_i")])
509 (define_insn "*load_dtprel22"
510 [(set (match_operand:DI 0 "register_operand" "=r")
511 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
512 UNSPEC_DTPREL))]
513 ""
514 "addl %0 = @dtprel(%1), r0"
515 [(set_attr "itanium_class" "ialu")])
517 (define_expand "add_dtprel"
518 [(set (match_operand:DI 0 "register_operand" "")
519 (plus:DI (match_operand:DI 1 "register_operand" "")
520 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
521 UNSPEC_DTPREL)))]
522 "!TARGET_TLS64"
523 "")
525 (define_insn "*add_dtprel14"
526 [(set (match_operand:DI 0 "register_operand" "=r")
527 (plus:DI (match_operand:DI 1 "register_operand" "r")
528 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
529 UNSPEC_DTPREL)))]
530 "TARGET_TLS14"
531 "adds %0 = @dtprel(%2), %1"
532 [(set_attr "itanium_class" "ialu")])
534 (define_insn "*add_dtprel22"
535 [(set (match_operand:DI 0 "register_operand" "=r")
536 (plus:DI (match_operand:DI 1 "register_operand" "a")
537 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
538 UNSPEC_DTPREL)))]
539 "TARGET_TLS22"
540 "addl %0 = @dtprel(%2), %1"
541 [(set_attr "itanium_class" "ialu")])
543 (define_insn "load_ltoff_tprel"
544 [(set (match_operand:DI 0 "register_operand" "=r")
545 (plus:DI (reg:DI 1)
546 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
547 UNSPEC_LTOFF_TPREL)))]
548 ""
549 "addl %0 = @ltoff(@tprel(%1)), gp"
550 [(set_attr "itanium_class" "ialu")])
552 (define_expand "load_tprel"
553 [(set (match_operand:DI 0 "register_operand" "")
554 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
555 UNSPEC_TPREL))]
556 ""
557 "")
559 (define_insn "*load_tprel64"
560 [(set (match_operand:DI 0 "register_operand" "=r")
561 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
562 UNSPEC_TPREL))]
563 "TARGET_TLS64"
564 "movl %0 = @tprel(%1)"
565 [(set_attr "itanium_class" "long_i")])
567 (define_insn "*load_tprel22"
568 [(set (match_operand:DI 0 "register_operand" "=r")
569 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
570 UNSPEC_TPREL))]
571 ""
572 "addl %0 = @tprel(%1), r0"
573 [(set_attr "itanium_class" "ialu")])
575 (define_expand "add_tprel"
576 [(set (match_operand:DI 0 "register_operand" "")
577 (plus:DI (match_operand:DI 1 "register_operand" "")
578 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
579 UNSPEC_TPREL)))]
580 "!TARGET_TLS64"
581 "")
583 (define_insn "*add_tprel14"
584 [(set (match_operand:DI 0 "register_operand" "=r")
585 (plus:DI (match_operand:DI 1 "register_operand" "r")
586 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
587 UNSPEC_TPREL)))]
588 "TARGET_TLS14"
589 "adds %0 = @tprel(%2), %1"
590 [(set_attr "itanium_class" "ialu")])
592 (define_insn "*add_tprel22"
593 [(set (match_operand:DI 0 "register_operand" "=r")
594 (plus:DI (match_operand:DI 1 "register_operand" "a")
595 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
596 UNSPEC_TPREL)))]
597 "TARGET_TLS22"
598 "addl %0 = @tprel(%2), %1"
599 [(set_attr "itanium_class" "ialu")])
601 ;; With no offsettable memory references, we've got to have a scratch
602 ;; around to play with the second word.
603 (define_expand "movti"
604 [(parallel [(set (match_operand:TI 0 "general_operand" "")
605 (match_operand:TI 1 "general_operand" ""))
606 (clobber (match_scratch:DI 2 ""))])]
607 ""
608 {
609 rtx op1 = ia64_expand_move (operands[0], operands[1]);
610 if (!op1)
611 DONE;
612 operands[1] = op1;
613 })
615 (define_insn_and_split "*movti_internal"
616 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
617 (match_operand:TI 1 "general_operand" "ri,m,r"))
618 (clobber (match_scratch:DI 2 "=X,&r,&r"))]
619 "ia64_move_ok (operands[0], operands[1])"
620 "#"
621 "reload_completed"
622 [(const_int 0)]
623 {
624 rtx adj1, adj2, in[2], out[2], insn;
625 int first;
627 adj1 = ia64_split_timode (in, operands[1], operands[2]);
628 adj2 = ia64_split_timode (out, operands[0], operands[2]);
630 first = 0;
631 if (reg_overlap_mentioned_p (out[0], in[1]))
632 {
633 if (reg_overlap_mentioned_p (out[1], in[0]))
634 abort ();
635 first = 1;
636 }
638 if (adj1 && adj2)
639 abort ();
640 if (adj1)
641 emit_insn (adj1);
642 if (adj2)
643 emit_insn (adj2);
644 insn = emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
645 if (GET_CODE (out[first]) == MEM
646 && GET_CODE (XEXP (out[first], 0)) == POST_MODIFY)
647 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
648 XEXP (XEXP (out[first], 0), 0),
649 REG_NOTES (insn));
650 insn = emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
651 if (GET_CODE (out[!first]) == MEM
652 && GET_CODE (XEXP (out[!first], 0)) == POST_MODIFY)
653 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
654 XEXP (XEXP (out[!first], 0), 0),
655 REG_NOTES (insn));
656 DONE;
657 }
658 [(set_attr "itanium_class" "unknown")
659 (set_attr "predicable" "no")])
661 ;; ??? SSA creates these. Can't allow memories since we don't have
662 ;; the scratch register. Fortunately combine will know how to add
663 ;; the clobber and scratch.
664 (define_insn_and_split "*movti_internal_reg"
665 [(set (match_operand:TI 0 "register_operand" "=r")
666 (match_operand:TI 1 "nonmemory_operand" "ri"))]
667 ""
668 "#"
669 "reload_completed"
670 [(const_int 0)]
671 {
672 rtx in[2], out[2];
673 int first;
675 ia64_split_timode (in, operands[1], NULL_RTX);
676 ia64_split_timode (out, operands[0], NULL_RTX);
678 first = 0;
679 if (reg_overlap_mentioned_p (out[0], in[1]))
680 {
681 if (reg_overlap_mentioned_p (out[1], in[0]))
682 abort ();
683 first = 1;
684 }
686 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
687 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
688 DONE;
689 }
690 [(set_attr "itanium_class" "unknown")
691 (set_attr "predicable" "no")])
693 (define_expand "reload_inti"
694 [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
695 (match_operand:TI 1 "" "m"))
696 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
697 ""
698 {
699 unsigned int s_regno = REGNO (operands[2]);
700 if (s_regno == REGNO (operands[0]))
701 s_regno += 1;
702 operands[2] = gen_rtx_REG (DImode, s_regno);
703 })
705 (define_expand "reload_outti"
706 [(parallel [(set (match_operand:TI 0 "" "=m")
707 (match_operand:TI 1 "register_operand" "r"))
708 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
709 ""
710 {
711 unsigned int s_regno = REGNO (operands[2]);
712 if (s_regno == REGNO (operands[1]))
713 s_regno += 1;
714 operands[2] = gen_rtx_REG (DImode, s_regno);
715 })
717 ;; Floating Point Moves
718 ;;
719 ;; Note - Patterns for SF mode moves are compulsory, but
720 ;; patterns for DF are optional, as GCC can synthesize them.
722 (define_expand "movsf"
723 [(set (match_operand:SF 0 "general_operand" "")
724 (match_operand:SF 1 "general_operand" ""))]
725 ""
726 {
727 rtx op1 = ia64_expand_move (operands[0], operands[1]);
728 if (!op1)
729 DONE;
730 operands[1] = op1;
731 })
733 (define_insn "*movsf_internal"
734 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
735 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
736 "ia64_move_ok (operands[0], operands[1])"
737 "@
738 mov %0 = %F1
739 ldfs %0 = %1%P1
740 stfs %0 = %F1%P0
741 getf.s %0 = %F1
742 setf.s %0 = %1
743 mov %0 = %1
744 ld4%O1 %0 = %1%P1
745 st4%Q0 %0 = %1%P0"
746 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
748 (define_expand "movdf"
749 [(set (match_operand:DF 0 "general_operand" "")
750 (match_operand:DF 1 "general_operand" ""))]
751 ""
752 {
753 rtx op1 = ia64_expand_move (operands[0], operands[1]);
754 if (!op1)
755 DONE;
756 operands[1] = op1;
757 })
759 (define_insn "*movdf_internal"
760 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
761 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
762 "ia64_move_ok (operands[0], operands[1])"
763 "@
764 mov %0 = %F1
765 ldfd %0 = %1%P1
766 stfd %0 = %F1%P0
767 getf.d %0 = %F1
768 setf.d %0 = %1
769 mov %0 = %1
770 ld8%O1 %0 = %1%P1
771 st8%Q0 %0 = %1%P0"
772 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
774 ;; With no offsettable memory references, we've got to have a scratch
775 ;; around to play with the second word if the variable winds up in GRs.
776 (define_expand "movtf"
777 [(set (match_operand:TF 0 "general_operand" "")
778 (match_operand:TF 1 "general_operand" ""))]
779 "INTEL_EXTENDED_IEEE_FORMAT"
780 {
781 /* We must support TFmode loads into general registers for stdarg/vararg
782 and unprototyped calls. We split them into DImode loads for convenience.
783 We don't need TFmode stores from general regs, because a stdarg/vararg
784 routine does a block store to memory of unnamed arguments. */
785 if (GET_CODE (operands[0]) == REG
786 && GR_REGNO_P (REGNO (operands[0])))
787 {
788 /* We're hoping to transform everything that deals with TFmode
789 quantities and GR registers early in the compiler. */
790 if (no_new_pseudos)
791 abort ();
793 /* Struct to register can just use TImode instead. */
794 if ((GET_CODE (operands[1]) == SUBREG
795 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
796 || (GET_CODE (operands[1]) == REG
797 && GR_REGNO_P (REGNO (operands[1]))))
798 {
799 emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])),
800 SUBREG_REG (operands[1]));
801 DONE;
802 }
804 if (GET_CODE (operands[1]) == CONST_DOUBLE)
805 {
806 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])),
807 operand_subword (operands[1], 0, 0, TFmode));
808 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1),
809 operand_subword (operands[1], 1, 0, TFmode));
810 DONE;
811 }
813 /* If the quantity is in a register not known to be GR, spill it. */
814 if (register_operand (operands[1], TFmode))
815 operands[1] = spill_tfmode_operand (operands[1], 1);
817 if (GET_CODE (operands[1]) == MEM)
818 {
819 rtx out[2];
821 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0]));
822 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1);
824 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
825 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
826 DONE;
827 }
829 abort ();
830 }
832 if (! reload_in_progress && ! reload_completed)
833 {
834 operands[0] = spill_tfmode_operand (operands[0], 0);
835 operands[1] = spill_tfmode_operand (operands[1], 0);
837 if (! ia64_move_ok (operands[0], operands[1]))
838 operands[1] = force_reg (TFmode, operands[1]);
839 }
840 })
842 ;; ??? There's no easy way to mind volatile acquire/release semantics.
844 (define_insn "*movtf_internal"
845 [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
846 (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
847 "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])"
848 "@
849 mov %0 = %F1
850 ldfe %0 = %1%P1
851 stfe %0 = %F1%P0"
852 [(set_attr "itanium_class" "fmisc,fld,stf")])
853 \f
854 ;; ::::::::::::::::::::
855 ;; ::
856 ;; :: Conversions
857 ;; ::
858 ;; ::::::::::::::::::::
860 ;; Signed conversions from a smaller integer to a larger integer
862 (define_insn "extendqidi2"
863 [(set (match_operand:DI 0 "gr_register_operand" "=r")
864 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
865 ""
866 "sxt1 %0 = %1"
867 [(set_attr "itanium_class" "xtd")])
869 (define_insn "extendhidi2"
870 [(set (match_operand:DI 0 "gr_register_operand" "=r")
871 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
872 ""
873 "sxt2 %0 = %1"
874 [(set_attr "itanium_class" "xtd")])
876 (define_insn "extendsidi2"
877 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
878 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
879 ""
880 "@
881 sxt4 %0 = %1
882 fsxt.r %0 = %1, %1"
883 [(set_attr "itanium_class" "xtd,fmisc")])
885 ;; Unsigned conversions from a smaller integer to a larger integer
887 (define_insn "zero_extendqidi2"
888 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
889 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
890 ""
891 "@
892 zxt1 %0 = %1
893 ld1%O1 %0 = %1%P1"
894 [(set_attr "itanium_class" "xtd,ld")])
896 (define_insn "zero_extendhidi2"
897 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
898 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
899 ""
900 "@
901 zxt2 %0 = %1
902 ld2%O1 %0 = %1%P1"
903 [(set_attr "itanium_class" "xtd,ld")])
905 (define_insn "zero_extendsidi2"
906 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
907 (zero_extend:DI
908 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
909 ""
910 "@
911 zxt4 %0 = %1
912 ld4%O1 %0 = %1%P1
913 fmix.r %0 = f0, %1"
914 [(set_attr "itanium_class" "xtd,ld,fmisc")])
916 ;; Convert between floating point types of different sizes.
918 ;; At first glance, it would appear that emitting fnorm for an extending
919 ;; conversion is unnecessary. However, the stf and getf instructions work
920 ;; correctly only if the input is properly rounded for its type. In
921 ;; particular, we get the wrong result for getf.d/stfd if the input is a
922 ;; denorm single. Since we don't know what the next instruction will be, we
923 ;; have to emit an fnorm.
925 ;; ??? Optimization opportunity here. Get rid of the insn altogether
926 ;; when we can. Should probably use a scheme like has been proposed
927 ;; for ia32 in dealing with operands that match unary operators. This
928 ;; would let combine merge the thing into adjacent insns. See also how the
929 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
930 ;; se_register_operand.
932 (define_insn "extendsfdf2"
933 [(set (match_operand:DF 0 "fr_register_operand" "=f")
934 (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))]
935 ""
936 "fnorm.d %0 = %1"
937 [(set_attr "itanium_class" "fmac")])
939 (define_insn "extendsftf2"
940 [(set (match_operand:TF 0 "fr_register_operand" "=f")
941 (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))]
942 "INTEL_EXTENDED_IEEE_FORMAT"
943 "fnorm %0 = %1"
944 [(set_attr "itanium_class" "fmac")])
946 (define_insn "extenddftf2"
947 [(set (match_operand:TF 0 "fr_register_operand" "=f")
948 (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))]
949 "INTEL_EXTENDED_IEEE_FORMAT"
950 "fnorm %0 = %1"
951 [(set_attr "itanium_class" "fmac")])
953 (define_insn "truncdfsf2"
954 [(set (match_operand:SF 0 "fr_register_operand" "=f")
955 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
956 ""
957 "fnorm.s %0 = %1"
958 [(set_attr "itanium_class" "fmac")])
960 (define_insn "trunctfsf2"
961 [(set (match_operand:SF 0 "fr_register_operand" "=f")
962 (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
963 "INTEL_EXTENDED_IEEE_FORMAT"
964 "fnorm.s %0 = %1"
965 [(set_attr "itanium_class" "fmac")])
967 (define_insn "trunctfdf2"
968 [(set (match_operand:DF 0 "fr_register_operand" "=f")
969 (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
970 "INTEL_EXTENDED_IEEE_FORMAT"
971 "fnorm.d %0 = %1"
972 [(set_attr "itanium_class" "fmac")])
974 ;; Convert between signed integer types and floating point.
976 (define_insn "floatditf2"
977 [(set (match_operand:TF 0 "fr_register_operand" "=f")
978 (float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
979 "INTEL_EXTENDED_IEEE_FORMAT"
980 "fcvt.xf %0 = %1"
981 [(set_attr "itanium_class" "fcvtfx")])
983 ;; ??? Suboptimal. This should be split somehow.
984 (define_insn "floatdidf2"
985 [(set (match_operand:DF 0 "register_operand" "=f")
986 (float:DF (match_operand:DI 1 "register_operand" "f")))]
987 "!INTEL_EXTENDED_IEEE_FORMAT"
988 "fcvt.xf %0 = %1\;;;\;%,fnorm.d %0 = %0"
989 [(set_attr "itanium_class" "fcvtfx")])
991 ;; ??? Suboptimal. This should be split somehow.
992 (define_insn "floatdisf2"
993 [(set (match_operand:SF 0 "register_operand" "=f")
994 (float:SF (match_operand:DI 1 "register_operand" "f")))]
995 "!INTEL_EXTENDED_IEEE_FORMAT"
996 "fcvt.xf %0 = %1\;;;\;%,fnorm.s %0 = %0"
997 [(set_attr "itanium_class" "fcvtfx")])
999 (define_insn "fix_truncsfdi2"
1000 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1001 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1002 ""
1003 "fcvt.fx.trunc %0 = %1"
1004 [(set_attr "itanium_class" "fcvtfx")])
1006 (define_insn "fix_truncdfdi2"
1007 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1008 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1009 ""
1010 "fcvt.fx.trunc %0 = %1"
1011 [(set_attr "itanium_class" "fcvtfx")])
1013 (define_insn "fix_trunctfdi2"
1014 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1015 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
1016 "INTEL_EXTENDED_IEEE_FORMAT"
1017 "fcvt.fx.trunc %0 = %1"
1018 [(set_attr "itanium_class" "fcvtfx")])
1020 (define_insn "fix_trunctfdi2_alts"
1021 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1022 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1023 (use (match_operand:SI 2 "const_int_operand" ""))]
1024 "INTEL_EXTENDED_IEEE_FORMAT"
1025 "fcvt.fx.trunc.s%2 %0 = %1"
1026 [(set_attr "itanium_class" "fcvtfx")])
1028 ;; Convert between unsigned integer types and floating point.
1030 (define_insn "floatunsdisf2"
1031 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1032 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
1033 ""
1034 "fcvt.xuf.s %0 = %1"
1035 [(set_attr "itanium_class" "fcvtfx")])
1037 (define_insn "floatunsdidf2"
1038 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1039 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
1040 ""
1041 "fcvt.xuf.d %0 = %1"
1042 [(set_attr "itanium_class" "fcvtfx")])
1044 (define_insn "floatunsditf2"
1045 [(set (match_operand:TF 0 "fr_register_operand" "=f")
1046 (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
1047 "INTEL_EXTENDED_IEEE_FORMAT"
1048 "fcvt.xuf %0 = %1"
1049 [(set_attr "itanium_class" "fcvtfx")])
1051 (define_insn "fixuns_truncsfdi2"
1052 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1053 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1054 ""
1055 "fcvt.fxu.trunc %0 = %1"
1056 [(set_attr "itanium_class" "fcvtfx")])
1058 (define_insn "fixuns_truncdfdi2"
1059 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1060 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1061 ""
1062 "fcvt.fxu.trunc %0 = %1"
1063 [(set_attr "itanium_class" "fcvtfx")])
1065 (define_insn "fixuns_trunctfdi2"
1066 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1067 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
1068 "INTEL_EXTENDED_IEEE_FORMAT"
1069 "fcvt.fxu.trunc %0 = %1"
1070 [(set_attr "itanium_class" "fcvtfx")])
1072 (define_insn "fixuns_trunctfdi2_alts"
1073 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1074 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1075 (use (match_operand:SI 2 "const_int_operand" ""))]
1076 "INTEL_EXTENDED_IEEE_FORMAT"
1077 "fcvt.fxu.trunc.s%2 %0 = %1"
1078 [(set_attr "itanium_class" "fcvtfx")])
1079 \f
1080 ;; ::::::::::::::::::::
1081 ;; ::
1082 ;; :: Bit field extraction
1083 ;; ::
1084 ;; ::::::::::::::::::::
1086 (define_insn "extv"
1087 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1088 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1089 (match_operand:DI 2 "const_int_operand" "n")
1090 (match_operand:DI 3 "const_int_operand" "n")))]
1091 ""
1092 "extr %0 = %1, %3, %2"
1093 [(set_attr "itanium_class" "ishf")])
1095 (define_insn "extzv"
1096 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1097 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1098 (match_operand:DI 2 "const_int_operand" "n")
1099 (match_operand:DI 3 "const_int_operand" "n")))]
1100 ""
1101 "extr.u %0 = %1, %3, %2"
1102 [(set_attr "itanium_class" "ishf")])
1104 ;; Insert a bit field.
1105 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1106 ;; Source1 can be 0 or -1.
1107 ;; Source2 can be 0.
1109 ;; ??? Actual dep instruction is more powerful than what these insv
1110 ;; patterns support. Unfortunately, combine is unable to create patterns
1111 ;; where source2 != dest.
1113 (define_expand "insv"
1114 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1115 (match_operand:DI 1 "const_int_operand" "")
1116 (match_operand:DI 2 "const_int_operand" ""))
1117 (match_operand:DI 3 "nonmemory_operand" ""))]
1118 ""
1119 {
1120 int width = INTVAL (operands[1]);
1121 int shift = INTVAL (operands[2]);
1123 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1124 pseudo. */
1125 if (! register_operand (operands[3], DImode)
1126 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1127 operands[3] = force_reg (DImode, operands[3]);
1129 /* If this is a single dep instruction, we have nothing to do. */
1130 if (! ((register_operand (operands[3], DImode) && width <= 16)
1131 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1132 {
1133 /* Check for cases that can be implemented with a mix instruction. */
1134 if (width == 32 && shift == 0)
1135 {
1136 /* Directly generating the mix4left instruction confuses
1137 optimize_bit_field in function.c. Since this is performing
1138 a useful optimization, we defer generation of the complicated
1139 mix4left RTL to the first splitting phase. */
1140 rtx tmp = gen_reg_rtx (DImode);
1141 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1142 DONE;
1143 }
1144 else if (width == 32 && shift == 32)
1145 {
1146 emit_insn (gen_mix4right (operands[0], operands[3]));
1147 DONE;
1148 }
1150 /* We could handle remaining cases by emitting multiple dep
1151 instructions.
1153 If we need more than two dep instructions then we lose. A 6
1154 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1155 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1156 the latter is 6 cycles on an Itanium (TM) processor, because there is
1157 only one function unit that can execute dep and shr immed.
1159 If we only need two dep instruction, then we still lose.
1160 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1161 the unnecessary mov, this is still undesirable because it will be
1162 hard to optimize, and it creates unnecessary pressure on the I0
1163 function unit. */
1165 FAIL;
1167 #if 0
1168 /* This code may be useful for other IA-64 processors, so we leave it in
1169 for now. */
1170 while (width > 16)
1171 {
1172 rtx tmp;
1174 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1175 operands[3]));
1176 shift += 16;
1177 width -= 16;
1178 tmp = gen_reg_rtx (DImode);
1179 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1180 operands[3] = tmp;
1181 }
1182 operands[1] = GEN_INT (width);
1183 operands[2] = GEN_INT (shift);
1184 #endif
1185 }
1186 })
1188 (define_insn "*insv_internal"
1189 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1190 (match_operand:DI 1 "const_int_operand" "n")
1191 (match_operand:DI 2 "const_int_operand" "n"))
1192 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1193 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1194 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1195 "dep %0 = %3, %0, %2, %1"
1196 [(set_attr "itanium_class" "ishf")])
1198 ;; Combine doesn't like to create bit-field insertions into zero.
1199 (define_insn "*depz_internal"
1200 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1201 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1202 (match_operand:DI 2 "const_int_operand" "n"))
1203 (match_operand:DI 3 "const_int_operand" "n")))]
1204 "CONST_OK_FOR_M (INTVAL (operands[2]))
1205 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1206 {
1207 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1208 return "%,dep.z %0 = %1, %2, %3";
1209 }
1210 [(set_attr "itanium_class" "ishf")])
1212 (define_insn "shift_mix4left"
1213 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1214 (const_int 32) (const_int 0))
1215 (match_operand:DI 1 "gr_register_operand" "r"))
1216 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1217 ""
1218 "#"
1219 [(set_attr "itanium_class" "unknown")])
1221 (define_split
1222 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1223 (const_int 32) (const_int 0))
1224 (match_operand:DI 1 "register_operand" ""))
1225 (clobber (match_operand:DI 2 "register_operand" ""))]
1226 "reload_completed"
1227 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1228 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1229 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1230 "operands[3] = operands[2];")
1232 (define_split
1233 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1234 (const_int 32) (const_int 0))
1235 (match_operand:DI 1 "register_operand" ""))
1236 (clobber (match_operand:DI 2 "register_operand" ""))]
1237 "! reload_completed"
1238 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1239 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1240 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1241 "operands[3] = operands[2];")
1243 (define_insn "*mix4left"
1244 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1245 (const_int 32) (const_int 0))
1246 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1247 (const_int 32)))]
1248 ""
1249 "mix4.l %0 = %0, %r1"
1250 [(set_attr "itanium_class" "mmshf")])
1252 (define_insn "mix4right"
1253 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1254 (const_int 32) (const_int 32))
1255 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1256 ""
1257 "mix4.r %0 = %r1, %0"
1258 [(set_attr "itanium_class" "mmshf")])
1260 ;; This is used by the rotrsi3 pattern.
1262 (define_insn "*mix4right_3op"
1263 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1264 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1265 (ashift:DI (zero_extend:DI
1266 (match_operand:SI 2 "gr_register_operand" "r"))
1267 (const_int 32))))]
1268 ""
1269 "mix4.r %0 = %2, %1"
1270 [(set_attr "itanium_class" "mmshf")])
1272 \f
1273 ;; ::::::::::::::::::::
1274 ;; ::
1275 ;; :: 1 bit Integer arithmetic
1276 ;; ::
1277 ;; ::::::::::::::::::::
1279 (define_insn_and_split "andbi3"
1280 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1281 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1282 (match_operand:BI 2 "register_operand" "c,r,r")))]
1283 ""
1284 "@
1285 #
1286 tbit.nz.and.orcm %0, %I0 = %2, 0
1287 and %0 = %2, %1"
1288 "reload_completed
1289 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1290 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1291 [(cond_exec (eq (match_dup 2) (const_int 0))
1292 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1293 (match_dup 0))))]
1294 ""
1295 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1297 (define_insn_and_split "*andcmbi3"
1298 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1299 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1300 (match_operand:BI 2 "register_operand" "0,0,r")))]
1301 ""
1302 "@
1303 #
1304 tbit.z.and.orcm %0, %I0 = %1, 0
1305 andcm %0 = %2, %1"
1306 "reload_completed
1307 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1308 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1309 [(cond_exec (ne (match_dup 1) (const_int 0))
1310 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1311 (match_dup 0))))]
1312 ""
1313 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1315 (define_insn_and_split "iorbi3"
1316 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1317 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1318 (match_operand:BI 2 "register_operand" "c,r,r")))]
1319 ""
1320 "@
1321 #
1322 tbit.nz.or.andcm %0, %I0 = %2, 0
1323 or %0 = %2, %1"
1324 "reload_completed
1325 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1326 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1327 [(cond_exec (ne (match_dup 2) (const_int 0))
1328 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1329 (match_dup 0))))]
1330 ""
1331 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1333 (define_insn_and_split "*iorcmbi3"
1334 [(set (match_operand:BI 0 "register_operand" "=c,c")
1335 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1336 (match_operand:BI 2 "register_operand" "0,0")))]
1337 ""
1338 "@
1339 #
1340 tbit.z.or.andcm %0, %I0 = %1, 0"
1341 "reload_completed
1342 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1343 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1344 [(cond_exec (eq (match_dup 1) (const_int 0))
1345 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1346 (match_dup 0))))]
1347 ""
1348 [(set_attr "itanium_class" "unknown,tbit")])
1350 (define_insn "one_cmplbi2"
1351 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1352 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1353 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1354 ""
1355 "@
1356 tbit.z %0, %I0 = %1, 0
1357 xor %0 = 1, %1
1358 #
1359 #"
1360 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1362 (define_split
1363 [(set (match_operand:BI 0 "register_operand" "")
1364 (not:BI (match_operand:BI 1 "register_operand" "")))
1365 (clobber (match_scratch:BI 2 ""))]
1366 "reload_completed
1367 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1368 && rtx_equal_p (operands[0], operands[1])"
1369 [(set (match_dup 4) (match_dup 3))
1370 (set (match_dup 0) (const_int 1))
1371 (cond_exec (ne (match_dup 2) (const_int 0))
1372 (set (match_dup 0) (const_int 0)))
1373 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1374 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1375 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1377 (define_split
1378 [(set (match_operand:BI 0 "register_operand" "")
1379 (not:BI (match_operand:BI 1 "register_operand" "")))
1380 (clobber (match_scratch:BI 2 ""))]
1381 "reload_completed
1382 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1383 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1384 && ! rtx_equal_p (operands[0], operands[1])"
1385 [(cond_exec (ne (match_dup 1) (const_int 0))
1386 (set (match_dup 0) (const_int 0)))
1387 (cond_exec (eq (match_dup 1) (const_int 0))
1388 (set (match_dup 0) (const_int 1)))
1389 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1390 "")
1392 (define_insn "*cmpsi_and_0"
1393 [(set (match_operand:BI 0 "register_operand" "=c")
1394 (and:BI (match_operator:BI 4 "predicate_operator"
1395 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1396 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1397 (match_operand:BI 1 "register_operand" "0")))]
1398 ""
1399 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1400 [(set_attr "itanium_class" "icmp")])
1402 (define_insn "*cmpsi_and_1"
1403 [(set (match_operand:BI 0 "register_operand" "=c")
1404 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1405 [(match_operand:SI 2 "gr_register_operand" "r")
1406 (const_int 0)])
1407 (match_operand:BI 1 "register_operand" "0")))]
1408 ""
1409 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1410 [(set_attr "itanium_class" "icmp")])
1412 (define_insn "*cmpsi_andnot_0"
1413 [(set (match_operand:BI 0 "register_operand" "=c")
1414 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1415 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1416 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1417 (match_operand:BI 1 "register_operand" "0")))]
1418 ""
1419 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1420 [(set_attr "itanium_class" "icmp")])
1422 (define_insn "*cmpsi_andnot_1"
1423 [(set (match_operand:BI 0 "register_operand" "=c")
1424 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1425 [(match_operand:SI 2 "gr_register_operand" "r")
1426 (const_int 0)]))
1427 (match_operand:BI 1 "register_operand" "0")))]
1428 ""
1429 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1430 [(set_attr "itanium_class" "icmp")])
1432 (define_insn "*cmpdi_and_0"
1433 [(set (match_operand:BI 0 "register_operand" "=c")
1434 (and:BI (match_operator:BI 4 "predicate_operator"
1435 [(match_operand:DI 2 "gr_register_operand" "r")
1436 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1437 (match_operand:BI 1 "register_operand" "0")))]
1438 ""
1439 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1440 [(set_attr "itanium_class" "icmp")])
1442 (define_insn "*cmpdi_and_1"
1443 [(set (match_operand:BI 0 "register_operand" "=c")
1444 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1445 [(match_operand:DI 2 "gr_register_operand" "r")
1446 (const_int 0)])
1447 (match_operand:BI 1 "register_operand" "0")))]
1448 ""
1449 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1450 [(set_attr "itanium_class" "icmp")])
1452 (define_insn "*cmpdi_andnot_0"
1453 [(set (match_operand:BI 0 "register_operand" "=c")
1454 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1455 [(match_operand:DI 2 "gr_register_operand" "r")
1456 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1457 (match_operand:BI 1 "register_operand" "0")))]
1458 ""
1459 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1460 [(set_attr "itanium_class" "icmp")])
1462 (define_insn "*cmpdi_andnot_1"
1463 [(set (match_operand:BI 0 "register_operand" "=c")
1464 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1465 [(match_operand:DI 2 "gr_register_operand" "r")
1466 (const_int 0)]))
1467 (match_operand:BI 1 "register_operand" "0")))]
1468 ""
1469 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1470 [(set_attr "itanium_class" "icmp")])
1472 (define_insn "*tbit_and_0"
1473 [(set (match_operand:BI 0 "register_operand" "=c")
1474 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1475 (const_int 1))
1476 (const_int 0))
1477 (match_operand:BI 2 "register_operand" "0")))]
1478 ""
1479 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1480 [(set_attr "itanium_class" "tbit")])
1482 (define_insn "*tbit_and_1"
1483 [(set (match_operand:BI 0 "register_operand" "=c")
1484 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1485 (const_int 1))
1486 (const_int 0))
1487 (match_operand:BI 2 "register_operand" "0")))]
1488 ""
1489 "tbit.z.and.orcm %0, %I0 = %1, 0"
1490 [(set_attr "itanium_class" "tbit")])
1492 (define_insn "*tbit_and_2"
1493 [(set (match_operand:BI 0 "register_operand" "=c")
1494 (and:BI (ne:BI (zero_extract:DI
1495 (match_operand:DI 1 "gr_register_operand" "r")
1496 (const_int 1)
1497 (match_operand:DI 2 "const_int_operand" "n"))
1498 (const_int 0))
1499 (match_operand:BI 3 "register_operand" "0")))]
1500 ""
1501 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1502 [(set_attr "itanium_class" "tbit")])
1504 (define_insn "*tbit_and_3"
1505 [(set (match_operand:BI 0 "register_operand" "=c")
1506 (and:BI (eq:BI (zero_extract:DI
1507 (match_operand:DI 1 "gr_register_operand" "r")
1508 (const_int 1)
1509 (match_operand:DI 2 "const_int_operand" "n"))
1510 (const_int 0))
1511 (match_operand:BI 3 "register_operand" "0")))]
1512 ""
1513 "tbit.z.and.orcm %0, %I0 = %1, %2"
1514 [(set_attr "itanium_class" "tbit")])
1516 (define_insn "*cmpsi_or_0"
1517 [(set (match_operand:BI 0 "register_operand" "=c")
1518 (ior:BI (match_operator:BI 4 "predicate_operator"
1519 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1520 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1521 (match_operand:BI 1 "register_operand" "0")))]
1522 ""
1523 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1524 [(set_attr "itanium_class" "icmp")])
1526 (define_insn "*cmpsi_or_1"
1527 [(set (match_operand:BI 0 "register_operand" "=c")
1528 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1529 [(match_operand:SI 2 "gr_register_operand" "r")
1530 (const_int 0)])
1531 (match_operand:BI 1 "register_operand" "0")))]
1532 ""
1533 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1534 [(set_attr "itanium_class" "icmp")])
1536 (define_insn "*cmpsi_orcm_0"
1537 [(set (match_operand:BI 0 "register_operand" "=c")
1538 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1539 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1540 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1541 (match_operand:BI 1 "register_operand" "0")))]
1542 ""
1543 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1544 [(set_attr "itanium_class" "icmp")])
1546 (define_insn "*cmpsi_orcm_1"
1547 [(set (match_operand:BI 0 "register_operand" "=c")
1548 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1549 [(match_operand:SI 2 "gr_register_operand" "r")
1550 (const_int 0)]))
1551 (match_operand:BI 1 "register_operand" "0")))]
1552 ""
1553 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1554 [(set_attr "itanium_class" "icmp")])
1556 (define_insn "*cmpdi_or_0"
1557 [(set (match_operand:BI 0 "register_operand" "=c")
1558 (ior:BI (match_operator:BI 4 "predicate_operator"
1559 [(match_operand:DI 2 "gr_register_operand" "r")
1560 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1561 (match_operand:BI 1 "register_operand" "0")))]
1562 ""
1563 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1564 [(set_attr "itanium_class" "icmp")])
1566 (define_insn "*cmpdi_or_1"
1567 [(set (match_operand:BI 0 "register_operand" "=c")
1568 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1569 [(match_operand:DI 2 "gr_register_operand" "r")
1570 (const_int 0)])
1571 (match_operand:BI 1 "register_operand" "0")))]
1572 ""
1573 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1574 [(set_attr "itanium_class" "icmp")])
1576 (define_insn "*cmpdi_orcm_0"
1577 [(set (match_operand:BI 0 "register_operand" "=c")
1578 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1579 [(match_operand:DI 2 "gr_register_operand" "r")
1580 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1581 (match_operand:BI 1 "register_operand" "0")))]
1582 ""
1583 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1584 [(set_attr "itanium_class" "icmp")])
1586 (define_insn "*cmpdi_orcm_1"
1587 [(set (match_operand:BI 0 "register_operand" "=c")
1588 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1589 [(match_operand:DI 2 "gr_register_operand" "r")
1590 (const_int 0)]))
1591 (match_operand:BI 1 "register_operand" "0")))]
1592 ""
1593 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1594 [(set_attr "itanium_class" "icmp")])
1596 (define_insn "*tbit_or_0"
1597 [(set (match_operand:BI 0 "register_operand" "=c")
1598 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1599 (const_int 1))
1600 (const_int 0))
1601 (match_operand:BI 2 "register_operand" "0")))]
1602 ""
1603 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1604 [(set_attr "itanium_class" "tbit")])
1606 (define_insn "*tbit_or_1"
1607 [(set (match_operand:BI 0 "register_operand" "=c")
1608 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1609 (const_int 1))
1610 (const_int 0))
1611 (match_operand:BI 2 "register_operand" "0")))]
1612 ""
1613 "tbit.z.or.andcm %0, %I0 = %1, 0"
1614 [(set_attr "itanium_class" "tbit")])
1616 (define_insn "*tbit_or_2"
1617 [(set (match_operand:BI 0 "register_operand" "=c")
1618 (ior:BI (ne:BI (zero_extract:DI
1619 (match_operand:DI 1 "gr_register_operand" "r")
1620 (const_int 1)
1621 (match_operand:DI 2 "const_int_operand" "n"))
1622 (const_int 0))
1623 (match_operand:BI 3 "register_operand" "0")))]
1624 ""
1625 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1626 [(set_attr "itanium_class" "tbit")])
1628 (define_insn "*tbit_or_3"
1629 [(set (match_operand:BI 0 "register_operand" "=c")
1630 (ior:BI (eq:BI (zero_extract:DI
1631 (match_operand:DI 1 "gr_register_operand" "r")
1632 (const_int 1)
1633 (match_operand:DI 2 "const_int_operand" "n"))
1634 (const_int 0))
1635 (match_operand:BI 3 "register_operand" "0")))]
1636 ""
1637 "tbit.z.or.andcm %0, %I0 = %1, %2"
1638 [(set_attr "itanium_class" "tbit")])
1640 ;; Transform test of and/or of setcc into parallel comparisons.
1642 (define_split
1643 [(set (match_operand:BI 0 "register_operand" "")
1644 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1645 (const_int 0))
1646 (match_operand:DI 3 "register_operand" ""))
1647 (const_int 0)))]
1648 ""
1649 [(set (match_dup 0)
1650 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1651 (match_dup 2)))]
1652 "")
1654 (define_split
1655 [(set (match_operand:BI 0 "register_operand" "")
1656 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1657 (const_int 0))
1658 (match_operand:DI 3 "register_operand" ""))
1659 (const_int 0)))]
1660 ""
1661 [(set (match_dup 0)
1662 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1663 (match_dup 2)))
1664 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1665 (clobber (scratch))])]
1666 "")
1668 (define_split
1669 [(set (match_operand:BI 0 "register_operand" "")
1670 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1671 (const_int 0))
1672 (match_operand:DI 3 "register_operand" ""))
1673 (const_int 0)))]
1674 ""
1675 [(set (match_dup 0)
1676 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1677 (match_dup 2)))]
1678 "")
1680 (define_split
1681 [(set (match_operand:BI 0 "register_operand" "")
1682 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1683 (const_int 0))
1684 (match_operand:DI 3 "register_operand" ""))
1685 (const_int 0)))]
1686 ""
1687 [(set (match_dup 0)
1688 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1689 (match_dup 2)))
1690 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1691 (clobber (scratch))])]
1692 "")
1694 ;; ??? Incredibly hackish. Either need four proper patterns with all
1695 ;; the alternatives, or rely on sched1 to split the insn and hope that
1696 ;; nothing bad happens to the comparisons in the meantime.
1697 ;;
1698 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1699 ;; that we're doing height reduction.
1700 ;
1701 ;(define_insn_and_split ""
1702 ; [(set (match_operand:BI 0 "register_operand" "=c")
1703 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1704 ; [(match_operand 2 "" "")
1705 ; (match_operand 3 "" "")])
1706 ; (match_operator:BI 4 "comparison_operator"
1707 ; [(match_operand 5 "" "")
1708 ; (match_operand 6 "" "")]))
1709 ; (match_dup 0)))]
1710 ; "flag_schedule_insns"
1711 ; "#"
1712 ; ""
1713 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1714 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1715 ; "")
1716 ;
1717 ;(define_insn_and_split ""
1718 ; [(set (match_operand:BI 0 "register_operand" "=c")
1719 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1720 ; [(match_operand 2 "" "")
1721 ; (match_operand 3 "" "")])
1722 ; (match_operator:BI 4 "comparison_operator"
1723 ; [(match_operand 5 "" "")
1724 ; (match_operand 6 "" "")]))
1725 ; (match_dup 0)))]
1726 ; "flag_schedule_insns"
1727 ; "#"
1728 ; ""
1729 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1730 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1731 ; "")
1732 ;
1733 ;(define_split
1734 ; [(set (match_operand:BI 0 "register_operand" "")
1735 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1736 ; [(match_operand 2 "" "")
1737 ; (match_operand 3 "" "")])
1738 ; (match_operand:BI 7 "register_operand" ""))
1739 ; (and:BI (match_operator:BI 4 "comparison_operator"
1740 ; [(match_operand 5 "" "")
1741 ; (match_operand 6 "" "")])
1742 ; (match_operand:BI 8 "register_operand" ""))))]
1743 ; ""
1744 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
1745 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
1746 ; (match_dup 0)))]
1747 ; "")
1748 ;
1749 ;(define_split
1750 ; [(set (match_operand:BI 0 "register_operand" "")
1751 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1752 ; [(match_operand 2 "" "")
1753 ; (match_operand 3 "" "")])
1754 ; (match_operand:BI 7 "register_operand" ""))
1755 ; (ior:BI (match_operator:BI 4 "comparison_operator"
1756 ; [(match_operand 5 "" "")
1757 ; (match_operand 6 "" "")])
1758 ; (match_operand:BI 8 "register_operand" ""))))]
1759 ; ""
1760 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
1761 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
1762 ; (match_dup 0)))]
1763 ; "")
1765 ;; Try harder to avoid predicate copies by duplicating compares.
1766 ;; Note that we'll have already split the predicate copy, which
1767 ;; is kind of a pain, but oh well.
1769 (define_peephole2
1770 [(set (match_operand:BI 0 "register_operand" "")
1771 (match_operand:BI 1 "comparison_operator" ""))
1772 (set (match_operand:CCI 2 "register_operand" "")
1773 (match_operand:CCI 3 "register_operand" ""))
1774 (set (match_operand:CCI 4 "register_operand" "")
1775 (match_operand:CCI 5 "register_operand" ""))
1776 (set (match_operand:BI 6 "register_operand" "")
1777 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
1778 "REGNO (operands[3]) == REGNO (operands[0])
1779 && REGNO (operands[4]) == REGNO (operands[0]) + 1
1780 && REGNO (operands[4]) == REGNO (operands[2]) + 1
1781 && REGNO (operands[6]) == REGNO (operands[2])"
1782 [(set (match_dup 0) (match_dup 1))
1783 (set (match_dup 6) (match_dup 7))]
1784 "operands[7] = copy_rtx (operands[1]);")
1785 \f
1786 ;; ::::::::::::::::::::
1787 ;; ::
1788 ;; :: 16 bit Integer arithmetic
1789 ;; ::
1790 ;; ::::::::::::::::::::
1792 (define_insn "mulhi3"
1793 [(set (match_operand:HI 0 "gr_register_operand" "=r")
1794 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
1795 (match_operand:HI 2 "gr_register_operand" "r")))]
1796 ""
1797 "pmpy2.r %0 = %1, %2"
1798 [(set_attr "itanium_class" "mmmul")])
1800 \f
1801 ;; ::::::::::::::::::::
1802 ;; ::
1803 ;; :: 32 bit Integer arithmetic
1804 ;; ::
1805 ;; ::::::::::::::::::::
1807 (define_insn "addsi3"
1808 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
1809 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
1810 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
1811 ""
1812 "@
1813 add %0 = %1, %2
1814 adds %0 = %2, %1
1815 addl %0 = %2, %1"
1816 [(set_attr "itanium_class" "ialu")])
1818 (define_insn "*addsi3_plus1"
1819 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1820 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
1821 (match_operand:SI 2 "gr_register_operand" "r"))
1822 (const_int 1)))]
1823 ""
1824 "add %0 = %1, %2, 1"
1825 [(set_attr "itanium_class" "ialu")])
1827 (define_insn "*addsi3_plus1_alt"
1828 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1829 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1830 (const_int 2))
1831 (const_int 1)))]
1832 ""
1833 "add %0 = %1, %1, 1"
1834 [(set_attr "itanium_class" "ialu")])
1836 (define_insn "*addsi3_shladd"
1837 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1838 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1839 (match_operand:SI 2 "shladd_operand" "n"))
1840 (match_operand:SI 3 "gr_register_operand" "r")))]
1841 ""
1842 "shladd %0 = %1, %S2, %3"
1843 [(set_attr "itanium_class" "ialu")])
1845 (define_insn "subsi3"
1846 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1847 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
1848 (match_operand:SI 2 "gr_register_operand" "r")))]
1849 ""
1850 "sub %0 = %1, %2"
1851 [(set_attr "itanium_class" "ialu")])
1853 (define_insn "*subsi3_minus1"
1854 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1855 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
1856 (match_operand:SI 2 "gr_register_operand" "r")))]
1857 ""
1858 "sub %0 = %2, %1, 1"
1859 [(set_attr "itanium_class" "ialu")])
1861 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
1863 (define_insn "mulsi3"
1864 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1865 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1866 (match_operand:SI 2 "grfr_register_operand" "f")))]
1867 ""
1868 "xmpy.l %0 = %1, %2"
1869 [(set_attr "itanium_class" "xmpy")])
1871 (define_insn "maddsi4"
1872 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1873 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1874 (match_operand:SI 2 "grfr_register_operand" "f"))
1875 (match_operand:SI 3 "grfr_register_operand" "f")))]
1876 ""
1877 "xma.l %0 = %1, %2, %3"
1878 [(set_attr "itanium_class" "xmpy")])
1880 (define_insn "negsi2"
1881 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1882 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
1883 ""
1884 "sub %0 = r0, %1"
1885 [(set_attr "itanium_class" "ialu")])
1887 (define_expand "abssi2"
1888 [(set (match_dup 2)
1889 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
1890 (set (match_operand:SI 0 "gr_register_operand" "")
1891 (if_then_else:SI (eq (match_dup 2) (const_int 0))
1892 (neg:SI (match_dup 1))
1893 (match_dup 1)))]
1894 ""
1895 { operands[2] = gen_reg_rtx (BImode); })
1897 (define_expand "sminsi3"
1898 [(set (match_dup 3)
1899 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
1900 (match_operand:SI 2 "gr_register_operand" "")))
1901 (set (match_operand:SI 0 "gr_register_operand" "")
1902 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1903 (match_dup 2) (match_dup 1)))]
1904 ""
1905 { operands[3] = gen_reg_rtx (BImode); })
1907 (define_expand "smaxsi3"
1908 [(set (match_dup 3)
1909 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
1910 (match_operand:SI 2 "gr_register_operand" "")))
1911 (set (match_operand:SI 0 "gr_register_operand" "")
1912 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1913 (match_dup 1) (match_dup 2)))]
1914 ""
1915 { operands[3] = gen_reg_rtx (BImode); })
1917 (define_expand "uminsi3"
1918 [(set (match_dup 3)
1919 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
1920 (match_operand:SI 2 "gr_register_operand" "")))
1921 (set (match_operand:SI 0 "gr_register_operand" "")
1922 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1923 (match_dup 2) (match_dup 1)))]
1924 ""
1925 { operands[3] = gen_reg_rtx (BImode); })
1927 (define_expand "umaxsi3"
1928 [(set (match_dup 3)
1929 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
1930 (match_operand:SI 2 "gr_register_operand" "")))
1931 (set (match_operand:SI 0 "gr_register_operand" "")
1932 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1933 (match_dup 1) (match_dup 2)))]
1934 ""
1935 { operands[3] = gen_reg_rtx (BImode); })
1937 (define_expand "divsi3"
1938 [(set (match_operand:SI 0 "register_operand" "")
1939 (div:SI (match_operand:SI 1 "general_operand" "")
1940 (match_operand:SI 2 "general_operand" "")))]
1941 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
1942 {
1943 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
1944 REAL_VALUE_TYPE twon34_r;
1946 op0_tf = gen_reg_rtx (TFmode);
1947 op0_di = gen_reg_rtx (DImode);
1949 if (CONSTANT_P (operands[1]))
1950 operands[1] = force_reg (SImode, operands[1]);
1951 op1_tf = gen_reg_rtx (TFmode);
1952 expand_float (op1_tf, operands[1], 0);
1954 if (CONSTANT_P (operands[2]))
1955 operands[2] = force_reg (SImode, operands[2]);
1956 op2_tf = gen_reg_rtx (TFmode);
1957 expand_float (op2_tf, operands[2], 0);
1959 /* 2^-34 */
1960 real_2expN (&twon34_r, -34);
1961 twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
1962 twon34 = force_reg (TFmode, twon34);
1964 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
1966 emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
1967 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
1968 DONE;
1969 })
1971 (define_expand "modsi3"
1972 [(set (match_operand:SI 0 "register_operand" "")
1973 (mod:SI (match_operand:SI 1 "general_operand" "")
1974 (match_operand:SI 2 "general_operand" "")))]
1975 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
1976 {
1977 rtx op2_neg, op1_di, div;
1979 div = gen_reg_rtx (SImode);
1980 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
1982 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
1984 /* This is a trick to get us to reuse the value that we're sure to
1985 have already copied to the FP regs. */
1986 op1_di = gen_reg_rtx (DImode);
1987 convert_move (op1_di, operands[1], 0);
1989 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
1990 gen_lowpart (SImode, op1_di)));
1991 DONE;
1992 })
1994 (define_expand "udivsi3"
1995 [(set (match_operand:SI 0 "register_operand" "")
1996 (udiv:SI (match_operand:SI 1 "general_operand" "")
1997 (match_operand:SI 2 "general_operand" "")))]
1998 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
1999 {
2000 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
2001 REAL_VALUE_TYPE twon34_r;
2003 op0_tf = gen_reg_rtx (TFmode);
2004 op0_di = gen_reg_rtx (DImode);
2006 if (CONSTANT_P (operands[1]))
2007 operands[1] = force_reg (SImode, operands[1]);
2008 op1_tf = gen_reg_rtx (TFmode);
2009 expand_float (op1_tf, operands[1], 1);
2011 if (CONSTANT_P (operands[2]))
2012 operands[2] = force_reg (SImode, operands[2]);
2013 op2_tf = gen_reg_rtx (TFmode);
2014 expand_float (op2_tf, operands[2], 1);
2016 /* 2^-34 */
2017 real_2expN (&twon34_r, -34);
2018 twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
2019 twon34 = force_reg (TFmode, twon34);
2021 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
2023 emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
2024 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2025 DONE;
2026 })
2028 (define_expand "umodsi3"
2029 [(set (match_operand:SI 0 "register_operand" "")
2030 (umod:SI (match_operand:SI 1 "general_operand" "")
2031 (match_operand:SI 2 "general_operand" "")))]
2032 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2033 {
2034 rtx op2_neg, op1_di, div;
2036 div = gen_reg_rtx (SImode);
2037 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
2039 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2041 /* This is a trick to get us to reuse the value that we're sure to
2042 have already copied to the FP regs. */
2043 op1_di = gen_reg_rtx (DImode);
2044 convert_move (op1_di, operands[1], 1);
2046 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2047 gen_lowpart (SImode, op1_di)));
2048 DONE;
2049 })
2051 (define_insn_and_split "divsi3_internal"
2052 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2053 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2054 (match_operand:TF 2 "fr_register_operand" "f"))))
2055 (clobber (match_scratch:TF 4 "=&f"))
2056 (clobber (match_scratch:TF 5 "=&f"))
2057 (clobber (match_scratch:BI 6 "=c"))
2058 (use (match_operand:TF 3 "fr_register_operand" "f"))]
2059 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2060 "#"
2061 "&& reload_completed"
2062 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2063 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2064 UNSPEC_FR_RECIP_APPROX))
2065 (use (const_int 1))])
2066 (cond_exec (ne (match_dup 6) (const_int 0))
2067 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2068 (use (const_int 1))]))
2069 (cond_exec (ne (match_dup 6) (const_int 0))
2070 (parallel [(set (match_dup 5)
2071 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2072 (match_dup 7)))
2073 (use (const_int 1))]))
2074 (cond_exec (ne (match_dup 6) (const_int 0))
2075 (parallel [(set (match_dup 4)
2076 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2077 (match_dup 4)))
2078 (use (const_int 1))]))
2079 (cond_exec (ne (match_dup 6) (const_int 0))
2080 (parallel [(set (match_dup 5)
2081 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
2082 (match_dup 3)))
2083 (use (const_int 1))]))
2084 (cond_exec (ne (match_dup 6) (const_int 0))
2085 (parallel [(set (match_dup 0)
2086 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2087 (match_dup 4)))
2088 (use (const_int 1))]))
2089 ]
2090 "operands[7] = CONST1_RTX (TFmode);"
2091 [(set_attr "predicable" "no")])
2092 \f
2093 ;; ::::::::::::::::::::
2094 ;; ::
2095 ;; :: 64 bit Integer arithmetic
2096 ;; ::
2097 ;; ::::::::::::::::::::
2099 (define_insn "adddi3"
2100 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2101 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2102 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2103 ""
2104 "@
2105 add %0 = %1, %2
2106 adds %0 = %2, %1
2107 addl %0 = %2, %1"
2108 [(set_attr "itanium_class" "ialu")])
2110 (define_insn "*adddi3_plus1"
2111 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2112 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2113 (match_operand:DI 2 "gr_register_operand" "r"))
2114 (const_int 1)))]
2115 ""
2116 "add %0 = %1, %2, 1"
2117 [(set_attr "itanium_class" "ialu")])
2119 ;; This has some of the same problems as shladd. We let the shladd
2120 ;; eliminator hack handle it, which results in the 1 being forced into
2121 ;; a register, but not more ugliness here.
2122 (define_insn "*adddi3_plus1_alt"
2123 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2124 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2125 (const_int 2))
2126 (const_int 1)))]
2127 ""
2128 "add %0 = %1, %1, 1"
2129 [(set_attr "itanium_class" "ialu")])
2131 (define_insn "subdi3"
2132 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2133 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2134 (match_operand:DI 2 "gr_register_operand" "r")))]
2135 ""
2136 "sub %0 = %1, %2"
2137 [(set_attr "itanium_class" "ialu")])
2139 (define_insn "*subdi3_minus1"
2140 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2141 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2142 (match_operand:DI 2 "gr_register_operand" "r")))]
2143 ""
2144 "sub %0 = %2, %1, 1"
2145 [(set_attr "itanium_class" "ialu")])
2147 ;; ??? Use grfr instead of fr because of virtual register elimination
2148 ;; and silly test cases multiplying by the frame pointer.
2149 (define_insn "muldi3"
2150 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2151 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2152 (match_operand:DI 2 "grfr_register_operand" "f")))]
2153 ""
2154 "xmpy.l %0 = %1, %2"
2155 [(set_attr "itanium_class" "xmpy")])
2157 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2158 ;; same problem that we have with shladd below. Unfortunately, this case is
2159 ;; much harder to fix because the multiply puts the result in an FP register,
2160 ;; but the add needs inputs from a general register. We add a spurious clobber
2161 ;; here so that it will be present just in case register elimination gives us
2162 ;; the funny result.
2164 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2166 ;; ??? Maybe we should change how adds are canonicalized.
2168 (define_insn "madddi4"
2169 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2170 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2171 (match_operand:DI 2 "grfr_register_operand" "f"))
2172 (match_operand:DI 3 "grfr_register_operand" "f")))
2173 (clobber (match_scratch:DI 4 "=X"))]
2174 ""
2175 "xma.l %0 = %1, %2, %3"
2176 [(set_attr "itanium_class" "xmpy")])
2178 ;; This can be created by register elimination if operand3 of shladd is an
2179 ;; eliminable register or has reg_equiv_constant set.
2181 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2182 ;; validate_changes call inside eliminate_regs will always succeed. If it
2183 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2184 ;; incorrectly.
2186 (define_insn "*madddi4_elim"
2187 [(set (match_operand:DI 0 "register_operand" "=&r")
2188 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2189 (match_operand:DI 2 "register_operand" "f"))
2190 (match_operand:DI 3 "register_operand" "f"))
2191 (match_operand:DI 4 "nonmemory_operand" "rI")))
2192 (clobber (match_scratch:DI 5 "=f"))]
2193 "reload_in_progress"
2194 "#"
2195 [(set_attr "itanium_class" "unknown")])
2197 (define_split
2198 [(set (match_operand:DI 0 "register_operand" "")
2199 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2200 (match_operand:DI 2 "register_operand" ""))
2201 (match_operand:DI 3 "register_operand" ""))
2202 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2203 (clobber (match_scratch:DI 5 ""))]
2204 "reload_completed"
2205 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2206 (match_dup 3)))
2207 (clobber (match_dup 0))])
2208 (set (match_dup 0) (match_dup 5))
2209 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2210 "")
2212 ;; ??? There are highpart multiply and add instructions, but we have no way
2213 ;; to generate them.
2215 (define_insn "smuldi3_highpart"
2216 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2217 (truncate:DI
2218 (lshiftrt:TI
2219 (mult:TI (sign_extend:TI
2220 (match_operand:DI 1 "fr_register_operand" "f"))
2221 (sign_extend:TI
2222 (match_operand:DI 2 "fr_register_operand" "f")))
2223 (const_int 64))))]
2224 ""
2225 "xmpy.h %0 = %1, %2"
2226 [(set_attr "itanium_class" "xmpy")])
2228 (define_insn "umuldi3_highpart"
2229 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2230 (truncate:DI
2231 (lshiftrt:TI
2232 (mult:TI (zero_extend:TI
2233 (match_operand:DI 1 "fr_register_operand" "f"))
2234 (zero_extend:TI
2235 (match_operand:DI 2 "fr_register_operand" "f")))
2236 (const_int 64))))]
2237 ""
2238 "xmpy.hu %0 = %1, %2"
2239 [(set_attr "itanium_class" "xmpy")])
2241 (define_insn "negdi2"
2242 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2243 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2244 ""
2245 "sub %0 = r0, %1"
2246 [(set_attr "itanium_class" "ialu")])
2248 (define_expand "absdi2"
2249 [(set (match_dup 2)
2250 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2251 (set (match_operand:DI 0 "gr_register_operand" "")
2252 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2253 (neg:DI (match_dup 1))
2254 (match_dup 1)))]
2255 ""
2256 { operands[2] = gen_reg_rtx (BImode); })
2258 (define_expand "smindi3"
2259 [(set (match_dup 3)
2260 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2261 (match_operand:DI 2 "gr_register_operand" "")))
2262 (set (match_operand:DI 0 "gr_register_operand" "")
2263 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2264 (match_dup 2) (match_dup 1)))]
2265 ""
2266 { operands[3] = gen_reg_rtx (BImode); })
2268 (define_expand "smaxdi3"
2269 [(set (match_dup 3)
2270 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2271 (match_operand:DI 2 "gr_register_operand" "")))
2272 (set (match_operand:DI 0 "gr_register_operand" "")
2273 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2274 (match_dup 1) (match_dup 2)))]
2275 ""
2276 { operands[3] = gen_reg_rtx (BImode); })
2278 (define_expand "umindi3"
2279 [(set (match_dup 3)
2280 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2281 (match_operand:DI 2 "gr_register_operand" "")))
2282 (set (match_operand:DI 0 "gr_register_operand" "")
2283 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2284 (match_dup 2) (match_dup 1)))]
2285 ""
2286 { operands[3] = gen_reg_rtx (BImode); })
2288 (define_expand "umaxdi3"
2289 [(set (match_dup 3)
2290 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2291 (match_operand:DI 2 "gr_register_operand" "")))
2292 (set (match_operand:DI 0 "gr_register_operand" "")
2293 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2294 (match_dup 1) (match_dup 2)))]
2295 ""
2296 { operands[3] = gen_reg_rtx (BImode); })
2298 (define_expand "ffsdi2"
2299 [(set (match_dup 6)
2300 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2301 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2302 (set (match_dup 5) (const_int 0))
2303 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2304 (set (match_dup 4) (popcount:DI (match_dup 3)))
2305 (set (match_operand:DI 0 "gr_register_operand" "")
2306 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2307 (match_dup 5) (match_dup 4)))]
2308 ""
2309 {
2310 operands[2] = gen_reg_rtx (DImode);
2311 operands[3] = gen_reg_rtx (DImode);
2312 operands[4] = gen_reg_rtx (DImode);
2313 operands[5] = gen_reg_rtx (DImode);
2314 operands[6] = gen_reg_rtx (BImode);
2315 })
2317 (define_expand "ctzdi2"
2318 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2319 (const_int -1)))
2320 (set (match_dup 3) (not:DI (match_dup 1)))
2321 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2322 (set (match_operand:DI 0 "gr_register_operand" "")
2323 (popcount:DI (match_dup 4)))]
2324 ""
2325 {
2326 operands[2] = gen_reg_rtx (DImode);
2327 operands[3] = gen_reg_rtx (DImode);
2328 operands[4] = gen_reg_rtx (DImode);
2329 })
2331 ;; ??? Ought to invent some unspecs for !INTEL_EXTENDED_IEEE_FORMAT.
2332 ;; Note the computation here is op0 = 63 - (exp - 0xffff).
2333 (define_expand "clzdi2"
2334 [(set (match_dup 2)
2335 (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "")))
2336 (set (match_dup 3)
2337 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2338 (set (match_dup 4) (const_int 65598))
2339 (set (match_operand:DI 0 "gr_register_operand" "")
2340 (minus:DI (match_dup 4) (match_dup 3)))]
2341 "INTEL_EXTENDED_IEEE_FORMAT"
2342 {
2343 operands[2] = gen_reg_rtx (TFmode);
2344 operands[3] = gen_reg_rtx (DImode);
2345 operands[4] = gen_reg_rtx (DImode);
2346 })
2348 (define_insn "popcountdi2"
2349 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2350 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2351 ""
2352 "popcnt %0 = %1"
2353 [(set_attr "itanium_class" "mmmul")])
2355 (define_insn "*getf_exp_tf"
2356 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2357 (unspec:DI [(match_operand:TF 1 "fr_register_operand" "f")]
2358 UNSPEC_GETF_EXP))]
2359 "INTEL_EXTENDED_IEEE_FORMAT"
2360 "getf.exp %0 = %1"
2361 [(set_attr "itanium_class" "frfr")])
2363 (define_expand "divdi3"
2364 [(set (match_operand:DI 0 "register_operand" "")
2365 (div:DI (match_operand:DI 1 "general_operand" "")
2366 (match_operand:DI 2 "general_operand" "")))]
2367 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2368 {
2369 rtx op1_tf, op2_tf, op0_tf;
2371 op0_tf = gen_reg_rtx (TFmode);
2373 if (CONSTANT_P (operands[1]))
2374 operands[1] = force_reg (DImode, operands[1]);
2375 op1_tf = gen_reg_rtx (TFmode);
2376 expand_float (op1_tf, operands[1], 0);
2378 if (CONSTANT_P (operands[2]))
2379 operands[2] = force_reg (DImode, operands[2]);
2380 op2_tf = gen_reg_rtx (TFmode);
2381 expand_float (op2_tf, operands[2], 0);
2383 if (TARGET_INLINE_INT_DIV_LAT)
2384 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2385 else
2386 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2388 emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2389 DONE;
2390 })
2392 (define_expand "moddi3"
2393 [(set (match_operand:DI 0 "register_operand" "")
2394 (mod:SI (match_operand:DI 1 "general_operand" "")
2395 (match_operand:DI 2 "general_operand" "")))]
2396 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2397 {
2398 rtx op2_neg, div;
2400 div = gen_reg_rtx (DImode);
2401 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2403 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2405 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2406 DONE;
2407 })
2409 (define_expand "udivdi3"
2410 [(set (match_operand:DI 0 "register_operand" "")
2411 (udiv:DI (match_operand:DI 1 "general_operand" "")
2412 (match_operand:DI 2 "general_operand" "")))]
2413 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2414 {
2415 rtx op1_tf, op2_tf, op0_tf;
2417 op0_tf = gen_reg_rtx (TFmode);
2419 if (CONSTANT_P (operands[1]))
2420 operands[1] = force_reg (DImode, operands[1]);
2421 op1_tf = gen_reg_rtx (TFmode);
2422 expand_float (op1_tf, operands[1], 1);
2424 if (CONSTANT_P (operands[2]))
2425 operands[2] = force_reg (DImode, operands[2]);
2426 op2_tf = gen_reg_rtx (TFmode);
2427 expand_float (op2_tf, operands[2], 1);
2429 if (TARGET_INLINE_INT_DIV_LAT)
2430 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2431 else
2432 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2434 emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2435 DONE;
2436 })
2438 (define_expand "umoddi3"
2439 [(set (match_operand:DI 0 "register_operand" "")
2440 (umod:DI (match_operand:DI 1 "general_operand" "")
2441 (match_operand:DI 2 "general_operand" "")))]
2442 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
2443 {
2444 rtx op2_neg, div;
2446 div = gen_reg_rtx (DImode);
2447 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2449 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2451 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2452 DONE;
2453 })
2455 (define_insn_and_split "divdi3_internal_lat"
2456 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2457 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2458 (match_operand:TF 2 "fr_register_operand" "f"))))
2459 (clobber (match_scratch:TF 3 "=&f"))
2460 (clobber (match_scratch:TF 4 "=&f"))
2461 (clobber (match_scratch:TF 5 "=&f"))
2462 (clobber (match_scratch:BI 6 "=c"))]
2463 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_LAT"
2464 "#"
2465 "&& reload_completed"
2466 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2467 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2468 UNSPEC_FR_RECIP_APPROX))
2469 (use (const_int 1))])
2470 (cond_exec (ne (match_dup 6) (const_int 0))
2471 (parallel [(set (match_dup 3)
2472 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2473 (match_dup 7)))
2474 (use (const_int 1))]))
2475 (cond_exec (ne (match_dup 6) (const_int 0))
2476 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2477 (use (const_int 1))]))
2478 (cond_exec (ne (match_dup 6) (const_int 0))
2479 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
2480 (use (const_int 1))]))
2481 (cond_exec (ne (match_dup 6) (const_int 0))
2482 (parallel [(set (match_dup 4)
2483 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
2484 (match_dup 4)))
2485 (use (const_int 1))]))
2486 (cond_exec (ne (match_dup 6) (const_int 0))
2487 (parallel [(set (match_dup 0)
2488 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2489 (match_dup 0)))
2490 (use (const_int 1))]))
2491 (cond_exec (ne (match_dup 6) (const_int 0))
2492 (parallel [(set (match_dup 3)
2493 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2494 (match_dup 4)))
2495 (use (const_int 1))]))
2496 (cond_exec (ne (match_dup 6) (const_int 0))
2497 (parallel [(set (match_dup 0)
2498 (plus:TF (mult:TF (match_dup 5) (match_dup 0))
2499 (match_dup 0)))
2500 (use (const_int 1))]))
2501 (cond_exec (ne (match_dup 6) (const_int 0))
2502 (parallel [(set (match_dup 4)
2503 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2504 (match_dup 1)))
2505 (use (const_int 1))]))
2506 (cond_exec (ne (match_dup 6) (const_int 0))
2507 (parallel [(set (match_dup 0)
2508 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2509 (match_dup 3)))
2510 (use (const_int 1))]))
2511 ]
2512 "operands[7] = CONST1_RTX (TFmode);"
2513 [(set_attr "predicable" "no")])
2515 (define_insn_and_split "divdi3_internal_thr"
2516 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2517 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2518 (match_operand:TF 2 "fr_register_operand" "f"))))
2519 (clobber (match_scratch:TF 3 "=&f"))
2520 (clobber (match_scratch:TF 4 "=f"))
2521 (clobber (match_scratch:BI 5 "=c"))]
2522 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_THR"
2523 "#"
2524 "&& reload_completed"
2525 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2526 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
2527 UNSPEC_FR_RECIP_APPROX))
2528 (use (const_int 1))])
2529 (cond_exec (ne (match_dup 5) (const_int 0))
2530 (parallel [(set (match_dup 3)
2531 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2532 (match_dup 6)))
2533 (use (const_int 1))]))
2534 (cond_exec (ne (match_dup 5) (const_int 0))
2535 (parallel [(set (match_dup 0)
2536 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2537 (match_dup 0)))
2538 (use (const_int 1))]))
2539 (cond_exec (ne (match_dup 5) (const_int 0))
2540 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
2541 (use (const_int 1))]))
2542 (cond_exec (ne (match_dup 5) (const_int 0))
2543 (parallel [(set (match_dup 0)
2544 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2545 (match_dup 0)))
2546 (use (const_int 1))]))
2547 (cond_exec (ne (match_dup 5) (const_int 0))
2548 (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1)))
2549 (use (const_int 1))]))
2550 (cond_exec (ne (match_dup 5) (const_int 0))
2551 (parallel [(set (match_dup 4)
2552 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2553 (match_dup 1)))
2554 (use (const_int 1))]))
2555 (cond_exec (ne (match_dup 5) (const_int 0))
2556 (parallel [(set (match_dup 0)
2557 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2558 (match_dup 3)))
2559 (use (const_int 1))]))
2560 ]
2561 "operands[6] = CONST1_RTX (TFmode);"
2562 [(set_attr "predicable" "no")])
2563 \f
2564 ;; ::::::::::::::::::::
2565 ;; ::
2566 ;; :: 32 bit floating point arithmetic
2567 ;; ::
2568 ;; ::::::::::::::::::::
2570 (define_insn "addsf3"
2571 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2572 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2573 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2574 ""
2575 "fadd.s %0 = %1, %F2"
2576 [(set_attr "itanium_class" "fmac")])
2578 (define_insn "subsf3"
2579 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2580 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2581 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2582 ""
2583 "fsub.s %0 = %F1, %F2"
2584 [(set_attr "itanium_class" "fmac")])
2586 (define_insn "mulsf3"
2587 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2588 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2589 (match_operand:SF 2 "fr_register_operand" "f")))]
2590 ""
2591 "fmpy.s %0 = %1, %2"
2592 [(set_attr "itanium_class" "fmac")])
2594 (define_insn "abssf2"
2595 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2596 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2597 ""
2598 "fabs %0 = %1"
2599 [(set_attr "itanium_class" "fmisc")])
2601 (define_insn "negsf2"
2602 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2603 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2604 ""
2605 "fneg %0 = %1"
2606 [(set_attr "itanium_class" "fmisc")])
2608 (define_insn "*nabssf2"
2609 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2610 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
2611 ""
2612 "fnegabs %0 = %1"
2613 [(set_attr "itanium_class" "fmisc")])
2615 (define_insn "minsf3"
2616 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2617 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2618 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2619 ""
2620 "fmin %0 = %1, %F2"
2621 [(set_attr "itanium_class" "fmisc")])
2623 (define_insn "maxsf3"
2624 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2625 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2626 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2627 ""
2628 "fmax %0 = %1, %F2"
2629 [(set_attr "itanium_class" "fmisc")])
2631 (define_insn "*maddsf4"
2632 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2633 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2634 (match_operand:SF 2 "fr_register_operand" "f"))
2635 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2636 ""
2637 "fma.s %0 = %1, %2, %F3"
2638 [(set_attr "itanium_class" "fmac")])
2640 (define_insn "*msubsf4"
2641 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2642 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2643 (match_operand:SF 2 "fr_register_operand" "f"))
2644 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2645 ""
2646 "fms.s %0 = %1, %2, %F3"
2647 [(set_attr "itanium_class" "fmac")])
2649 (define_insn "*nmulsf3"
2650 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2651 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2652 (match_operand:SF 2 "fr_register_operand" "f"))))]
2653 ""
2654 "fnmpy.s %0 = %1, %2"
2655 [(set_attr "itanium_class" "fmac")])
2657 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2659 (define_insn "*nmaddsf4"
2660 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2661 (plus:SF (neg:SF (mult:SF
2662 (match_operand:SF 1 "fr_register_operand" "f")
2663 (match_operand:SF 2 "fr_register_operand" "f")))
2664 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2665 ""
2666 "fnma.s %0 = %1, %2, %F3"
2667 [(set_attr "itanium_class" "fmac")])
2669 (define_expand "divsf3"
2670 [(set (match_operand:SF 0 "fr_register_operand" "")
2671 (div:SF (match_operand:SF 1 "fr_register_operand" "")
2672 (match_operand:SF 2 "fr_register_operand" "")))]
2673 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
2674 {
2675 rtx insn;
2676 if (TARGET_INLINE_FLOAT_DIV_LAT)
2677 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
2678 else
2679 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
2680 emit_insn (insn);
2681 DONE;
2682 })
2684 (define_insn_and_split "divsf3_internal_lat"
2685 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2686 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2687 (match_operand:SF 2 "fr_register_operand" "f")))
2688 (clobber (match_scratch:TF 3 "=&f"))
2689 (clobber (match_scratch:TF 4 "=f"))
2690 (clobber (match_scratch:BI 5 "=c"))]
2691 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
2692 "#"
2693 "&& reload_completed"
2694 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2695 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
2696 UNSPEC_FR_RECIP_APPROX))
2697 (use (const_int 1))])
2698 (cond_exec (ne (match_dup 5) (const_int 0))
2699 (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
2700 (use (const_int 1))]))
2701 (cond_exec (ne (match_dup 5) (const_int 0))
2702 (parallel [(set (match_dup 4)
2703 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2704 (match_dup 10)))
2705 (use (const_int 1))]))
2706 (cond_exec (ne (match_dup 5) (const_int 0))
2707 (parallel [(set (match_dup 3)
2708 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2709 (match_dup 3)))
2710 (use (const_int 1))]))
2711 (cond_exec (ne (match_dup 5) (const_int 0))
2712 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2713 (use (const_int 1))]))
2714 (cond_exec (ne (match_dup 5) (const_int 0))
2715 (parallel [(set (match_dup 3)
2716 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2717 (match_dup 3)))
2718 (use (const_int 1))]))
2719 (cond_exec (ne (match_dup 5) (const_int 0))
2720 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2721 (use (const_int 1))]))
2722 (cond_exec (ne (match_dup 5) (const_int 0))
2723 (parallel [(set (match_dup 9)
2724 (float_truncate:DF
2725 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2726 (match_dup 3))))
2727 (use (const_int 1))]))
2728 (cond_exec (ne (match_dup 5) (const_int 0))
2729 (set (match_dup 0)
2730 (float_truncate:SF (match_dup 6))))
2731 ]
2732 {
2733 operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2734 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2735 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2736 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
2737 operands[10] = CONST1_RTX (TFmode);
2738 }
2739 [(set_attr "predicable" "no")])
2741 (define_insn_and_split "divsf3_internal_thr"
2742 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2743 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2744 (match_operand:SF 2 "fr_register_operand" "f")))
2745 (clobber (match_scratch:TF 3 "=&f"))
2746 (clobber (match_scratch:TF 4 "=f"))
2747 (clobber (match_scratch:BI 5 "=c"))]
2748 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
2749 "#"
2750 "&& reload_completed"
2751 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2752 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
2753 UNSPEC_FR_RECIP_APPROX))
2754 (use (const_int 1))])
2755 (cond_exec (ne (match_dup 5) (const_int 0))
2756 (parallel [(set (match_dup 3)
2757 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2758 (match_dup 10)))
2759 (use (const_int 1))]))
2760 (cond_exec (ne (match_dup 5) (const_int 0))
2761 (parallel [(set (match_dup 3)
2762 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
2763 (match_dup 3)))
2764 (use (const_int 1))]))
2765 (cond_exec (ne (match_dup 5) (const_int 0))
2766 (parallel [(set (match_dup 6)
2767 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
2768 (match_dup 6)))
2769 (use (const_int 1))]))
2770 (cond_exec (ne (match_dup 5) (const_int 0))
2771 (parallel [(set (match_dup 9)
2772 (float_truncate:SF
2773 (mult:TF (match_dup 7) (match_dup 6))))
2774 (use (const_int 1))]))
2775 (cond_exec (ne (match_dup 5) (const_int 0))
2776 (parallel [(set (match_dup 4)
2777 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3)))
2778 (match_dup 7)))
2779 (use (const_int 1))]))
2780 (cond_exec (ne (match_dup 5) (const_int 0))
2781 (set (match_dup 0)
2782 (float_truncate:SF
2783 (plus:TF (mult:TF (match_dup 4) (match_dup 6))
2784 (match_dup 3)))))
2785 ]
2786 {
2787 operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2788 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2789 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2790 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
2791 operands[10] = CONST1_RTX (TFmode);
2792 }
2793 [(set_attr "predicable" "no")])
2794 \f
2795 ;; ::::::::::::::::::::
2796 ;; ::
2797 ;; :: 64 bit floating point arithmetic
2798 ;; ::
2799 ;; ::::::::::::::::::::
2801 (define_insn "adddf3"
2802 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2803 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2804 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2805 ""
2806 "fadd.d %0 = %1, %F2"
2807 [(set_attr "itanium_class" "fmac")])
2809 (define_insn "*adddf3_trunc"
2810 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2811 (float_truncate:SF
2812 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2813 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2814 ""
2815 "fadd.s %0 = %1, %F2"
2816 [(set_attr "itanium_class" "fmac")])
2818 (define_insn "subdf3"
2819 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2820 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2821 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2822 ""
2823 "fsub.d %0 = %F1, %F2"
2824 [(set_attr "itanium_class" "fmac")])
2826 (define_insn "*subdf3_trunc"
2827 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2828 (float_truncate:SF
2829 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2830 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2831 ""
2832 "fsub.s %0 = %F1, %F2"
2833 [(set_attr "itanium_class" "fmac")])
2835 (define_insn "muldf3"
2836 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2837 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2838 (match_operand:DF 2 "fr_register_operand" "f")))]
2839 ""
2840 "fmpy.d %0 = %1, %2"
2841 [(set_attr "itanium_class" "fmac")])
2843 (define_insn "*muldf3_trunc"
2844 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2845 (float_truncate:SF
2846 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2847 (match_operand:DF 2 "fr_register_operand" "f"))))]
2848 ""
2849 "fmpy.s %0 = %1, %2"
2850 [(set_attr "itanium_class" "fmac")])
2852 (define_insn "absdf2"
2853 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2854 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
2855 ""
2856 "fabs %0 = %1"
2857 [(set_attr "itanium_class" "fmisc")])
2859 (define_insn "negdf2"
2860 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2861 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
2862 ""
2863 "fneg %0 = %1"
2864 [(set_attr "itanium_class" "fmisc")])
2866 (define_insn "*nabsdf2"
2867 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2868 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
2869 ""
2870 "fnegabs %0 = %1"
2871 [(set_attr "itanium_class" "fmisc")])
2873 (define_insn "mindf3"
2874 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2875 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
2876 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2877 ""
2878 "fmin %0 = %1, %F2"
2879 [(set_attr "itanium_class" "fmisc")])
2881 (define_insn "maxdf3"
2882 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2883 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
2884 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2885 ""
2886 "fmax %0 = %1, %F2"
2887 [(set_attr "itanium_class" "fmisc")])
2889 (define_insn "*madddf4"
2890 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2891 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2892 (match_operand:DF 2 "fr_register_operand" "f"))
2893 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2894 ""
2895 "fma.d %0 = %1, %2, %F3"
2896 [(set_attr "itanium_class" "fmac")])
2898 (define_insn "*madddf4_trunc"
2899 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2900 (float_truncate:SF
2901 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2902 (match_operand:DF 2 "fr_register_operand" "f"))
2903 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2904 ""
2905 "fma.s %0 = %1, %2, %F3"
2906 [(set_attr "itanium_class" "fmac")])
2908 (define_insn "*msubdf4"
2909 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2910 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2911 (match_operand:DF 2 "fr_register_operand" "f"))
2912 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2913 ""
2914 "fms.d %0 = %1, %2, %F3"
2915 [(set_attr "itanium_class" "fmac")])
2917 (define_insn "*msubdf4_trunc"
2918 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2919 (float_truncate:SF
2920 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2921 (match_operand:DF 2 "fr_register_operand" "f"))
2922 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2923 ""
2924 "fms.s %0 = %1, %2, %F3"
2925 [(set_attr "itanium_class" "fmac")])
2927 (define_insn "*nmuldf3"
2928 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2929 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2930 (match_operand:DF 2 "fr_register_operand" "f"))))]
2931 ""
2932 "fnmpy.d %0 = %1, %2"
2933 [(set_attr "itanium_class" "fmac")])
2935 (define_insn "*nmuldf3_trunc"
2936 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2937 (float_truncate:SF
2938 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2939 (match_operand:DF 2 "fr_register_operand" "f")))))]
2940 ""
2941 "fnmpy.s %0 = %1, %2"
2942 [(set_attr "itanium_class" "fmac")])
2944 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2946 (define_insn "*nmadddf4"
2947 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2948 (plus:DF (neg:DF (mult:DF
2949 (match_operand:DF 1 "fr_register_operand" "f")
2950 (match_operand:DF 2 "fr_register_operand" "f")))
2951 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2952 ""
2953 "fnma.d %0 = %1, %2, %F3"
2954 [(set_attr "itanium_class" "fmac")])
2956 (define_insn "*nmadddf4_alts"
2957 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2958 (plus:DF (neg:DF (mult:DF
2959 (match_operand:DF 1 "fr_register_operand" "f")
2960 (match_operand:DF 2 "fr_register_operand" "f")))
2961 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))
2962 (use (match_operand:SI 4 "const_int_operand" ""))]
2963 ""
2964 "fnma.d.s%4 %0 = %1, %2, %F3"
2965 [(set_attr "itanium_class" "fmac")])
2967 (define_insn "*nmadddf4_trunc"
2968 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2969 (float_truncate:SF
2970 (plus:DF (neg:DF (mult:DF
2971 (match_operand:DF 1 "fr_register_operand" "f")
2972 (match_operand:DF 2 "fr_register_operand" "f")))
2973 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2974 ""
2975 "fnma.s %0 = %1, %2, %F3"
2976 [(set_attr "itanium_class" "fmac")])
2978 (define_expand "divdf3"
2979 [(set (match_operand:DF 0 "fr_register_operand" "")
2980 (div:DF (match_operand:DF 1 "fr_register_operand" "")
2981 (match_operand:DF 2 "fr_register_operand" "")))]
2982 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
2983 {
2984 rtx insn;
2985 if (TARGET_INLINE_FLOAT_DIV_LAT)
2986 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
2987 else
2988 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
2989 emit_insn (insn);
2990 DONE;
2991 })
2993 (define_insn_and_split "divdf3_internal_lat"
2994 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
2995 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
2996 (match_operand:DF 2 "fr_register_operand" "f")))
2997 (clobber (match_scratch:TF 3 "=&f"))
2998 (clobber (match_scratch:TF 4 "=&f"))
2999 (clobber (match_scratch:TF 5 "=&f"))
3000 (clobber (match_scratch:BI 6 "=c"))]
3001 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
3002 "#"
3003 "&& reload_completed"
3004 [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
3005 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
3006 UNSPEC_FR_RECIP_APPROX))
3007 (use (const_int 1))])
3008 (cond_exec (ne (match_dup 6) (const_int 0))
3009 (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
3010 (use (const_int 1))]))
3011 (cond_exec (ne (match_dup 6) (const_int 0))
3012 (parallel [(set (match_dup 4)
3013 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7)))
3014 (match_dup 12)))
3015 (use (const_int 1))]))
3016 (cond_exec (ne (match_dup 6) (const_int 0))
3017 (parallel [(set (match_dup 3)
3018 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3019 (match_dup 3)))
3020 (use (const_int 1))]))
3021 (cond_exec (ne (match_dup 6) (const_int 0))
3022 (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4)))
3023 (use (const_int 1))]))
3024 (cond_exec (ne (match_dup 6) (const_int 0))
3025 (parallel [(set (match_dup 7)
3026 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3027 (match_dup 7)))
3028 (use (const_int 1))]))
3029 (cond_exec (ne (match_dup 6) (const_int 0))
3030 (parallel [(set (match_dup 3)
3031 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3032 (match_dup 3)))
3033 (use (const_int 1))]))
3034 (cond_exec (ne (match_dup 6) (const_int 0))
3035 (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5)))
3036 (use (const_int 1))]))
3037 (cond_exec (ne (match_dup 6) (const_int 0))
3038 (parallel [(set (match_dup 7)
3039 (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3040 (match_dup 7)))
3041 (use (const_int 1))]))
3042 (cond_exec (ne (match_dup 6) (const_int 0))
3043 (parallel [(set (match_dup 10)
3044 (float_truncate:DF
3045 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3046 (match_dup 3))))
3047 (use (const_int 1))]))
3048 (cond_exec (ne (match_dup 6) (const_int 0))
3049 (parallel [(set (match_dup 7)
3050 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3051 (match_dup 7)))
3052 (use (const_int 1))]))
3053 (cond_exec (ne (match_dup 6) (const_int 0))
3054 (parallel [(set (match_dup 11)
3055 (float_truncate:DF
3056 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3)))
3057 (match_dup 8))))
3058 (use (const_int 1))]))
3059 (cond_exec (ne (match_dup 6) (const_int 0))
3060 (set (match_dup 0)
3061 (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3062 (match_dup 3)))))
3063 ]
3064 {
3065 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3066 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3067 operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3068 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3069 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
3070 operands[12] = CONST1_RTX (TFmode);
3071 }
3072 [(set_attr "predicable" "no")])
3074 (define_insn_and_split "divdf3_internal_thr"
3075 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3076 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3077 (match_operand:DF 2 "fr_register_operand" "f")))
3078 (clobber (match_scratch:TF 3 "=&f"))
3079 (clobber (match_scratch:DF 4 "=f"))
3080 (clobber (match_scratch:BI 5 "=c"))]
3081 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
3082 "#"
3083 "&& reload_completed"
3084 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
3085 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3086 UNSPEC_FR_RECIP_APPROX))
3087 (use (const_int 1))])
3088 (cond_exec (ne (match_dup 5) (const_int 0))
3089 (parallel [(set (match_dup 3)
3090 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
3091 (match_dup 10)))
3092 (use (const_int 1))]))
3093 (cond_exec (ne (match_dup 5) (const_int 0))
3094 (parallel [(set (match_dup 6)
3095 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3096 (match_dup 6)))
3097 (use (const_int 1))]))
3098 (cond_exec (ne (match_dup 5) (const_int 0))
3099 (parallel [(set (match_dup 3)
3100 (mult:TF (match_dup 3) (match_dup 3)))
3101 (use (const_int 1))]))
3102 (cond_exec (ne (match_dup 5) (const_int 0))
3103 (parallel [(set (match_dup 6)
3104 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3105 (match_dup 6)))
3106 (use (const_int 1))]))
3107 (cond_exec (ne (match_dup 5) (const_int 0))
3108 (parallel [(set (match_dup 3)
3109 (mult:TF (match_dup 3) (match_dup 3)))
3110 (use (const_int 1))]))
3111 (cond_exec (ne (match_dup 5) (const_int 0))
3112 (parallel [(set (match_dup 6)
3113 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3114 (match_dup 6)))
3115 (use (const_int 1))]))
3116 (cond_exec (ne (match_dup 5) (const_int 0))
3117 (parallel [(set (match_dup 9)
3118 (float_truncate:DF
3119 (mult:TF (match_dup 7) (match_dup 3))))
3120 (use (const_int 1))]))
3121 (cond_exec (ne (match_dup 5) (const_int 0))
3122 (parallel [(set (match_dup 4)
3123 (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9)))
3124 (match_dup 1)))
3125 (use (const_int 1))]))
3126 (cond_exec (ne (match_dup 5) (const_int 0))
3127 (set (match_dup 0)
3128 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3129 (match_dup 9))))
3130 ]
3131 {
3132 operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3133 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3134 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3135 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3136 operands[10] = CONST1_RTX (TFmode);
3137 }
3138 [(set_attr "predicable" "no")])
3139 \f
3140 ;; ::::::::::::::::::::
3141 ;; ::
3142 ;; :: 80 bit floating point arithmetic
3143 ;; ::
3144 ;; ::::::::::::::::::::
3146 (define_insn "addtf3"
3147 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3148 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3149 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3150 "INTEL_EXTENDED_IEEE_FORMAT"
3151 "fadd %0 = %F1, %F2"
3152 [(set_attr "itanium_class" "fmac")])
3154 (define_insn "*addtf3_truncsf"
3155 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3156 (float_truncate:SF
3157 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3158 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3159 "INTEL_EXTENDED_IEEE_FORMAT"
3160 "fadd.s %0 = %F1, %F2"
3161 [(set_attr "itanium_class" "fmac")])
3163 (define_insn "*addtf3_truncdf"
3164 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3165 (float_truncate:DF
3166 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3167 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3168 "INTEL_EXTENDED_IEEE_FORMAT"
3169 "fadd.d %0 = %F1, %F2"
3170 [(set_attr "itanium_class" "fmac")])
3172 (define_insn "subtf3"
3173 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3174 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3175 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3176 "INTEL_EXTENDED_IEEE_FORMAT"
3177 "fsub %0 = %F1, %F2"
3178 [(set_attr "itanium_class" "fmac")])
3180 (define_insn "*subtf3_truncsf"
3181 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3182 (float_truncate:SF
3183 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3184 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3185 "INTEL_EXTENDED_IEEE_FORMAT"
3186 "fsub.s %0 = %F1, %F2"
3187 [(set_attr "itanium_class" "fmac")])
3189 (define_insn "*subtf3_truncdf"
3190 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3191 (float_truncate:DF
3192 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3193 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3194 "INTEL_EXTENDED_IEEE_FORMAT"
3195 "fsub.d %0 = %F1, %F2"
3196 [(set_attr "itanium_class" "fmac")])
3198 (define_insn "multf3"
3199 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3200 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3201 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3202 "INTEL_EXTENDED_IEEE_FORMAT"
3203 "fmpy %0 = %F1, %F2"
3204 [(set_attr "itanium_class" "fmac")])
3206 (define_insn "*multf3_truncsf"
3207 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3208 (float_truncate:SF
3209 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3210 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3211 "INTEL_EXTENDED_IEEE_FORMAT"
3212 "fmpy.s %0 = %F1, %F2"
3213 [(set_attr "itanium_class" "fmac")])
3215 (define_insn "*multf3_truncdf"
3216 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3217 (float_truncate:DF
3218 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3219 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3220 "INTEL_EXTENDED_IEEE_FORMAT"
3221 "fmpy.d %0 = %F1, %F2"
3222 [(set_attr "itanium_class" "fmac")])
3224 (define_insn "*multf3_alts"
3225 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3226 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3227 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3228 (use (match_operand:SI 3 "const_int_operand" ""))]
3229 "INTEL_EXTENDED_IEEE_FORMAT"
3230 "fmpy.s%3 %0 = %F1, %F2"
3231 [(set_attr "itanium_class" "fmac")])
3233 (define_insn "*multf3_truncsf_alts"
3234 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3235 (float_truncate:SF
3236 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3237 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3238 (use (match_operand:SI 3 "const_int_operand" ""))]
3239 "INTEL_EXTENDED_IEEE_FORMAT"
3240 "fmpy.s.s%3 %0 = %F1, %F2"
3241 [(set_attr "itanium_class" "fmac")])
3243 (define_insn "*multf3_truncdf_alts"
3244 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3245 (float_truncate:DF
3246 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3247 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3248 (use (match_operand:SI 3 "const_int_operand" ""))]
3249 "INTEL_EXTENDED_IEEE_FORMAT"
3250 "fmpy.d.s%3 %0 = %F1, %F2"
3251 [(set_attr "itanium_class" "fmac")])
3253 (define_insn "abstf2"
3254 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3255 (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3256 "INTEL_EXTENDED_IEEE_FORMAT"
3257 "fabs %0 = %F1"
3258 [(set_attr "itanium_class" "fmisc")])
3260 (define_insn "negtf2"
3261 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3262 (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3263 "INTEL_EXTENDED_IEEE_FORMAT"
3264 "fneg %0 = %F1"
3265 [(set_attr "itanium_class" "fmisc")])
3267 (define_insn "*nabstf2"
3268 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3269 (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
3270 "INTEL_EXTENDED_IEEE_FORMAT"
3271 "fnegabs %0 = %F1"
3272 [(set_attr "itanium_class" "fmisc")])
3274 (define_insn "mintf3"
3275 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3276 (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3277 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3278 "INTEL_EXTENDED_IEEE_FORMAT"
3279 "fmin %0 = %F1, %F2"
3280 [(set_attr "itanium_class" "fmisc")])
3282 (define_insn "maxtf3"
3283 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3284 (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3285 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3286 "INTEL_EXTENDED_IEEE_FORMAT"
3287 "fmax %0 = %F1, %F2"
3288 [(set_attr "itanium_class" "fmisc")])
3290 (define_insn "*maddtf4"
3291 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3292 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3293 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3294 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3295 "INTEL_EXTENDED_IEEE_FORMAT"
3296 "fma %0 = %F1, %F2, %F3"
3297 [(set_attr "itanium_class" "fmac")])
3299 (define_insn "*maddtf4_truncsf"
3300 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3301 (float_truncate:SF
3302 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3303 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3304 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3305 "INTEL_EXTENDED_IEEE_FORMAT"
3306 "fma.s %0 = %F1, %F2, %F3"
3307 [(set_attr "itanium_class" "fmac")])
3309 (define_insn "*maddtf4_truncdf"
3310 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3311 (float_truncate:DF
3312 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3313 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3314 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3315 "INTEL_EXTENDED_IEEE_FORMAT"
3316 "fma.d %0 = %F1, %F2, %F3"
3317 [(set_attr "itanium_class" "fmac")])
3319 (define_insn "*maddtf4_alts"
3320 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3321 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3322 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3323 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3324 (use (match_operand:SI 4 "const_int_operand" ""))]
3325 "INTEL_EXTENDED_IEEE_FORMAT"
3326 "fma.s%4 %0 = %F1, %F2, %F3"
3327 [(set_attr "itanium_class" "fmac")])
3329 (define_insn "*maddtf4_alts_truncdf"
3330 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3331 (float_truncate:DF
3332 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3333 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3334 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3335 (use (match_operand:SI 4 "const_int_operand" ""))]
3336 "INTEL_EXTENDED_IEEE_FORMAT"
3337 "fma.d.s%4 %0 = %F1, %F2, %F3"
3338 [(set_attr "itanium_class" "fmac")])
3340 (define_insn "*msubtf4"
3341 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3342 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3343 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3344 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3345 "INTEL_EXTENDED_IEEE_FORMAT"
3346 "fms %0 = %F1, %F2, %F3"
3347 [(set_attr "itanium_class" "fmac")])
3349 (define_insn "*msubtf4_truncsf"
3350 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3351 (float_truncate:SF
3352 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3353 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3354 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3355 "INTEL_EXTENDED_IEEE_FORMAT"
3356 "fms.s %0 = %F1, %F2, %F3"
3357 [(set_attr "itanium_class" "fmac")])
3359 (define_insn "*msubtf4_truncdf"
3360 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3361 (float_truncate:DF
3362 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3363 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3364 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3365 "INTEL_EXTENDED_IEEE_FORMAT"
3366 "fms.d %0 = %F1, %F2, %F3"
3367 [(set_attr "itanium_class" "fmac")])
3369 (define_insn "*nmultf3"
3370 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3371 (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3372 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3373 "INTEL_EXTENDED_IEEE_FORMAT"
3374 "fnmpy %0 = %F1, %F2"
3375 [(set_attr "itanium_class" "fmac")])
3377 (define_insn "*nmultf3_truncsf"
3378 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3379 (float_truncate:SF
3380 (neg:TF (mult:TF
3381 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3382 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3383 "INTEL_EXTENDED_IEEE_FORMAT"
3384 "fnmpy.s %0 = %F1, %F2"
3385 [(set_attr "itanium_class" "fmac")])
3387 (define_insn "*nmultf3_truncdf"
3388 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3389 (float_truncate:DF
3390 (neg:TF (mult:TF
3391 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3392 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3393 "INTEL_EXTENDED_IEEE_FORMAT"
3394 "fnmpy.d %0 = %F1, %F2"
3395 [(set_attr "itanium_class" "fmac")])
3397 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
3399 (define_insn "*nmaddtf4"
3400 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3401 (plus:TF (neg:TF (mult:TF
3402 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3403 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3404 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3405 "INTEL_EXTENDED_IEEE_FORMAT"
3406 "fnma %0 = %F1, %F2, %F3"
3407 [(set_attr "itanium_class" "fmac")])
3409 (define_insn "*nmaddtf4_truncsf"
3410 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3411 (float_truncate:SF
3412 (plus:TF (neg:TF (mult:TF
3413 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3414 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3415 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3416 "INTEL_EXTENDED_IEEE_FORMAT"
3417 "fnma.s %0 = %F1, %F2, %F3"
3418 [(set_attr "itanium_class" "fmac")])
3420 (define_insn "*nmaddtf4_truncdf"
3421 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3422 (float_truncate:DF
3423 (plus:TF (neg:TF (mult:TF
3424 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3425 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3426 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3427 "INTEL_EXTENDED_IEEE_FORMAT"
3428 "fnma.d %0 = %F1, %F2, %F3"
3429 [(set_attr "itanium_class" "fmac")])
3431 (define_insn "*nmaddtf4_alts"
3432 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3433 (plus:TF (neg:TF (mult:TF
3434 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3435 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3436 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3437 (use (match_operand:SI 4 "const_int_operand" ""))]
3438 "INTEL_EXTENDED_IEEE_FORMAT"
3439 "fnma.s%4 %0 = %F1, %F2, %F3"
3440 [(set_attr "itanium_class" "fmac")])
3442 (define_insn "*nmaddtf4_truncdf_alts"
3443 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3444 (float_truncate:DF
3445 (plus:TF (neg:TF
3446 (mult:TF
3447 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3448 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3449 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3450 (use (match_operand:SI 4 "const_int_operand" ""))]
3451 "INTEL_EXTENDED_IEEE_FORMAT"
3452 "fnma.d.s%4 %0 = %F1, %F2, %F3"
3453 [(set_attr "itanium_class" "fmac")])
3455 (define_expand "divtf3"
3456 [(set (match_operand:TF 0 "fr_register_operand" "")
3457 (div:TF (match_operand:TF 1 "fr_register_operand" "")
3458 (match_operand:TF 2 "fr_register_operand" "")))]
3459 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
3460 {
3461 rtx insn;
3462 if (TARGET_INLINE_FLOAT_DIV_LAT)
3463 insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
3464 else
3465 insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
3466 emit_insn (insn);
3467 DONE;
3468 })
3470 (define_insn_and_split "divtf3_internal_lat"
3471 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3472 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3473 (match_operand:TF 2 "fr_register_operand" "f")))
3474 (clobber (match_scratch:TF 3 "=&f"))
3475 (clobber (match_scratch:TF 4 "=&f"))
3476 (clobber (match_scratch:TF 5 "=&f"))
3477 (clobber (match_scratch:TF 6 "=&f"))
3478 (clobber (match_scratch:BI 7 "=c"))]
3479 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
3480 "#"
3481 "&& reload_completed"
3482 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3483 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
3484 UNSPEC_FR_RECIP_APPROX))
3485 (use (const_int 1))])
3486 (cond_exec (ne (match_dup 7) (const_int 0))
3487 (parallel [(set (match_dup 3)
3488 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3489 (match_dup 8)))
3490 (use (const_int 1))]))
3491 (cond_exec (ne (match_dup 7) (const_int 0))
3492 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3493 (use (const_int 1))]))
3494 (cond_exec (ne (match_dup 7) (const_int 0))
3495 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
3496 (use (const_int 1))]))
3497 (cond_exec (ne (match_dup 7) (const_int 0))
3498 (parallel [(set (match_dup 6)
3499 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
3500 (match_dup 3)))
3501 (use (const_int 1))]))
3502 (cond_exec (ne (match_dup 7) (const_int 0))
3503 (parallel [(set (match_dup 3)
3504 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
3505 (match_dup 3)))
3506 (use (const_int 1))]))
3507 (cond_exec (ne (match_dup 7) (const_int 0))
3508 (parallel [(set (match_dup 5)
3509 (plus:TF (mult:TF (match_dup 6) (match_dup 0))
3510 (match_dup 0)))
3511 (use (const_int 1))]))
3512 (cond_exec (ne (match_dup 7) (const_int 0))
3513 (parallel [(set (match_dup 0)
3514 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3515 (match_dup 0)))
3516 (use (const_int 1))]))
3517 (cond_exec (ne (match_dup 7) (const_int 0))
3518 (parallel [(set (match_dup 4)
3519 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3520 (match_dup 1)))
3521 (use (const_int 1))]))
3522 (cond_exec (ne (match_dup 7) (const_int 0))
3523 (parallel [(set (match_dup 3)
3524 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3525 (match_dup 4)))
3526 (use (const_int 1))]))
3527 (cond_exec (ne (match_dup 7) (const_int 0))
3528 (parallel [(set (match_dup 5)
3529 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3530 (match_dup 8)))
3531 (use (const_int 1))]))
3532 (cond_exec (ne (match_dup 7) (const_int 0))
3533 (parallel [(set (match_dup 0)
3534 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3535 (match_dup 0)))
3536 (use (const_int 1))]))
3537 (cond_exec (ne (match_dup 7) (const_int 0))
3538 (parallel [(set (match_dup 4)
3539 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3540 (match_dup 1)))
3541 (use (const_int 1))]))
3542 (cond_exec (ne (match_dup 7) (const_int 0))
3543 (set (match_dup 0)
3544 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3545 (match_dup 3))))
3546 ]
3547 "operands[8] = CONST1_RTX (TFmode);"
3548 [(set_attr "predicable" "no")])
3550 (define_insn_and_split "divtf3_internal_thr"
3551 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3552 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3553 (match_operand:TF 2 "fr_register_operand" "f")))
3554 (clobber (match_scratch:TF 3 "=&f"))
3555 (clobber (match_scratch:TF 4 "=&f"))
3556 (clobber (match_scratch:BI 5 "=c"))]
3557 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
3558 "#"
3559 "&& reload_completed"
3560 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3561 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
3562 UNSPEC_FR_RECIP_APPROX))
3563 (use (const_int 1))])
3564 (cond_exec (ne (match_dup 5) (const_int 0))
3565 (parallel [(set (match_dup 3)
3566 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3567 (match_dup 6)))
3568 (use (const_int 1))]))
3569 (cond_exec (ne (match_dup 5) (const_int 0))
3570 (parallel [(set (match_dup 4)
3571 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3572 (match_dup 0)))
3573 (use (const_int 1))]))
3574 (cond_exec (ne (match_dup 5) (const_int 0))
3575 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
3576 (use (const_int 1))]))
3577 (cond_exec (ne (match_dup 5) (const_int 0))
3578 (parallel [(set (match_dup 3)
3579 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
3580 (match_dup 4)))
3581 (use (const_int 1))]))
3582 (cond_exec (ne (match_dup 5) (const_int 0))
3583 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3584 (use (const_int 1))]))
3585 (cond_exec (ne (match_dup 5) (const_int 0))
3586 (parallel [(set (match_dup 0)
3587 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3588 (match_dup 6)))
3589 (use (const_int 1))]))
3590 (cond_exec (ne (match_dup 5) (const_int 0))
3591 (parallel [(set (match_dup 0)
3592 (plus:TF (mult:TF (match_dup 0) (match_dup 3))
3593 (match_dup 3)))
3594 (use (const_int 1))]))
3595 (cond_exec (ne (match_dup 5) (const_int 0))
3596 (parallel [(set (match_dup 3)
3597 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3598 (match_dup 1)))
3599 (use (const_int 1))]))
3600 (cond_exec (ne (match_dup 5) (const_int 0))
3601 (parallel [(set (match_dup 3)
3602 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3603 (match_dup 4)))
3604 (use (const_int 1))]))
3605 (cond_exec (ne (match_dup 5) (const_int 0))
3606 (parallel [(set (match_dup 4)
3607 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3608 (match_dup 6)))
3609 (use (const_int 1))]))
3610 (cond_exec (ne (match_dup 5) (const_int 0))
3611 (parallel [(set (match_dup 0)
3612 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3613 (match_dup 0)))
3614 (use (const_int 1))]))
3615 (cond_exec (ne (match_dup 5) (const_int 0))
3616 (parallel [(set (match_dup 4)
3617 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3618 (match_dup 1)))
3619 (use (const_int 1))]))
3620 (cond_exec (ne (match_dup 5) (const_int 0))
3621 (set (match_dup 0)
3622 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3623 (match_dup 3))))
3624 ]
3625 "operands[6] = CONST1_RTX (TFmode);"
3626 [(set_attr "predicable" "no")])
3628 ;; ??? frcpa works like cmp.foo.unc.
3630 (define_insn "*recip_approx"
3631 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3632 (div:TF (const_int 1)
3633 (match_operand:TF 3 "fr_register_operand" "f")))
3634 (set (match_operand:BI 1 "register_operand" "=c")
3635 (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
3636 (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
3637 (use (match_operand:SI 4 "const_int_operand" ""))]
3638 "INTEL_EXTENDED_IEEE_FORMAT"
3639 "frcpa.s%4 %0, %1 = %2, %3"
3640 [(set_attr "itanium_class" "fmisc")
3641 (set_attr "predicable" "no")])
3642 \f
3643 ;; ::::::::::::::::::::
3644 ;; ::
3645 ;; :: 32 bit Integer Shifts and Rotates
3646 ;; ::
3647 ;; ::::::::::::::::::::
3649 (define_expand "ashlsi3"
3650 [(set (match_operand:SI 0 "gr_register_operand" "")
3651 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3652 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3653 ""
3654 {
3655 if (GET_CODE (operands[2]) != CONST_INT)
3656 {
3657 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3658 we've got to get rid of stray bits outside the SImode register. */
3659 rtx subshift = gen_reg_rtx (DImode);
3660 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3661 operands[2] = subshift;
3662 }
3663 })
3665 (define_insn "*ashlsi3_internal"
3666 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3667 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3668 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
3669 ""
3670 "@
3671 shladd %0 = %1, %2, r0
3672 dep.z %0 = %1, %2, %E2
3673 shl %0 = %1, %2"
3674 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
3676 (define_expand "ashrsi3"
3677 [(set (match_operand:SI 0 "gr_register_operand" "")
3678 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3679 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3680 ""
3681 {
3682 rtx subtarget = gen_reg_rtx (DImode);
3683 if (GET_CODE (operands[2]) == CONST_INT)
3684 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3685 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3686 else
3687 {
3688 rtx subshift = gen_reg_rtx (DImode);
3689 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
3690 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3691 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
3692 }
3693 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3694 DONE;
3695 })
3697 (define_expand "lshrsi3"
3698 [(set (match_operand:SI 0 "gr_register_operand" "")
3699 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3700 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3701 ""
3702 {
3703 rtx subtarget = gen_reg_rtx (DImode);
3704 if (GET_CODE (operands[2]) == CONST_INT)
3705 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3706 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3707 else
3708 {
3709 rtx subshift = gen_reg_rtx (DImode);
3710 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
3711 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3712 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
3713 }
3714 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3715 DONE;
3716 })
3718 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
3719 ;; here, instead of 64 like the patterns above. Keep the pattern together
3720 ;; until after combine; otherwise it won't get matched often.
3722 (define_expand "rotrsi3"
3723 [(set (match_operand:SI 0 "gr_register_operand" "")
3724 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
3725 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3726 ""
3727 {
3728 if (GET_MODE (operands[2]) != VOIDmode)
3729 {
3730 rtx tmp = gen_reg_rtx (DImode);
3731 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
3732 operands[2] = tmp;
3733 }
3734 })
3736 (define_insn_and_split "*rotrsi3_internal"
3737 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
3738 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
3739 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
3740 ""
3741 "#"
3742 "reload_completed"
3743 [(set (match_dup 3)
3744 (ior:DI (zero_extend:DI (match_dup 1))
3745 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3746 (set (match_dup 3)
3747 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3748 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
3750 (define_expand "rotlsi3"
3751 [(set (match_operand:SI 0 "gr_register_operand" "")
3752 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
3753 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3754 ""
3755 {
3756 if (! shift_32bit_count_operand (operands[2], SImode))
3757 {
3758 rtx tmp = gen_reg_rtx (SImode);
3759 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
3760 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
3761 DONE;
3762 }
3763 })
3765 (define_insn_and_split "*rotlsi3_internal"
3766 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3767 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
3768 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
3769 ""
3770 "#"
3771 "reload_completed"
3772 [(set (match_dup 3)
3773 (ior:DI (zero_extend:DI (match_dup 1))
3774 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3775 (set (match_dup 3)
3776 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3777 {
3778 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
3779 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
3780 })
3781 \f
3782 ;; ::::::::::::::::::::
3783 ;; ::
3784 ;; :: 64 bit Integer Shifts and Rotates
3785 ;; ::
3786 ;; ::::::::::::::::::::
3788 (define_insn "ashldi3"
3789 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
3790 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
3791 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
3792 ""
3793 "@
3794 shladd %0 = %1, %2, r0
3795 shl %0 = %1, %2
3796 shl %0 = %1, %2"
3797 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
3799 ;; ??? Maybe combine this with the multiply and add instruction?
3801 (define_insn "*shladd"
3802 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3803 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3804 (match_operand:DI 2 "shladd_operand" "n"))
3805 (match_operand:DI 3 "gr_register_operand" "r")))]
3806 ""
3807 "shladd %0 = %1, %S2, %3"
3808 [(set_attr "itanium_class" "ialu")])
3810 ;; This can be created by register elimination if operand3 of shladd is an
3811 ;; eliminable register or has reg_equiv_constant set.
3813 ;; We have to use nonmemory_operand for operand 4, to ensure that the
3814 ;; validate_changes call inside eliminate_regs will always succeed. If it
3815 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
3816 ;; incorrectly.
3818 (define_insn_and_split "*shladd_elim"
3819 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
3820 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3821 (match_operand:DI 2 "shladd_operand" "n"))
3822 (match_operand:DI 3 "nonmemory_operand" "r"))
3823 (match_operand:DI 4 "nonmemory_operand" "rI")))]
3824 "reload_in_progress"
3825 "* abort ();"
3826 "reload_completed"
3827 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
3828 (match_dup 3)))
3829 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
3830 ""
3831 [(set_attr "itanium_class" "unknown")])
3833 (define_insn "ashrdi3"
3834 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3835 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3836 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3837 ""
3838 "@
3839 shr %0 = %1, %2
3840 shr %0 = %1, %2"
3841 [(set_attr "itanium_class" "mmshf,mmshfi")])
3843 (define_insn "lshrdi3"
3844 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3845 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3846 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3847 ""
3848 "@
3849 shr.u %0 = %1, %2
3850 shr.u %0 = %1, %2"
3851 [(set_attr "itanium_class" "mmshf,mmshfi")])
3853 ;; Using a predicate that accepts only constants doesn't work, because optabs
3854 ;; will load the operand into a register and call the pattern if the predicate
3855 ;; did not accept it on the first try. So we use nonmemory_operand and then
3856 ;; verify that we have an appropriate constant in the expander.
3858 (define_expand "rotrdi3"
3859 [(set (match_operand:DI 0 "gr_register_operand" "")
3860 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
3861 (match_operand:DI 2 "nonmemory_operand" "")))]
3862 ""
3863 {
3864 if (! shift_count_operand (operands[2], DImode))
3865 FAIL;
3866 })
3868 (define_insn "*rotrdi3_internal"
3869 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3870 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
3871 (match_operand:DI 2 "shift_count_operand" "M")))]
3872 ""
3873 "shrp %0 = %1, %1, %2"
3874 [(set_attr "itanium_class" "ishf")])
3876 (define_expand "rotldi3"
3877 [(set (match_operand:DI 0 "gr_register_operand" "")
3878 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
3879 (match_operand:DI 2 "nonmemory_operand" "")))]
3880 ""
3881 {
3882 if (! shift_count_operand (operands[2], DImode))
3883 FAIL;
3884 })
3886 (define_insn "*rotldi3_internal"
3887 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3888 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
3889 (match_operand:DI 2 "shift_count_operand" "M")))]
3890 ""
3891 "shrp %0 = %1, %1, %e2"
3892 [(set_attr "itanium_class" "ishf")])
3893 \f
3894 ;; ::::::::::::::::::::
3895 ;; ::
3896 ;; :: 32 bit Integer Logical operations
3897 ;; ::
3898 ;; ::::::::::::::::::::
3900 ;; We don't seem to need any other 32-bit logical operations, because gcc
3901 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
3902 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
3903 ;; This doesn't work for unary logical operations, because we don't call
3904 ;; apply_distributive_law for them.
3906 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
3907 ;; apply_distributive_law. We get inefficient code for
3908 ;; int sub4 (int i, int j) { return i & ~j; }
3909 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
3910 ;; (zero_extend (and (not A) B)) in combine.
3911 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
3912 ;; one_cmplsi2 pattern.
3914 (define_insn "one_cmplsi2"
3915 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3916 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
3917 ""
3918 "andcm %0 = -1, %1"
3919 [(set_attr "itanium_class" "ilog")])
3920 \f
3921 ;; ::::::::::::::::::::
3922 ;; ::
3923 ;; :: 64 bit Integer Logical operations
3924 ;; ::
3925 ;; ::::::::::::::::::::
3927 (define_insn "anddi3"
3928 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3929 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3930 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3931 ""
3932 "@
3933 and %0 = %2, %1
3934 fand %0 = %2, %1"
3935 [(set_attr "itanium_class" "ilog,fmisc")])
3937 (define_insn "*andnot"
3938 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3939 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
3940 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3941 ""
3942 "@
3943 andcm %0 = %2, %1
3944 fandcm %0 = %2, %1"
3945 [(set_attr "itanium_class" "ilog,fmisc")])
3947 (define_insn "iordi3"
3948 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3949 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3950 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3951 ""
3952 "@
3953 or %0 = %2, %1
3954 for %0 = %2, %1"
3955 [(set_attr "itanium_class" "ilog,fmisc")])
3957 (define_insn "xordi3"
3958 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3959 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3960 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3961 ""
3962 "@
3963 xor %0 = %2, %1
3964 fxor %0 = %2, %1"
3965 [(set_attr "itanium_class" "ilog,fmisc")])
3967 (define_insn "one_cmpldi2"
3968 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3969 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
3970 ""
3971 "andcm %0 = -1, %1"
3972 [(set_attr "itanium_class" "ilog")])
3973 \f
3974 ;; ::::::::::::::::::::
3975 ;; ::
3976 ;; :: Comparisons
3977 ;; ::
3978 ;; ::::::::::::::::::::
3980 (define_expand "cmpbi"
3981 [(set (cc0)
3982 (compare (match_operand:BI 0 "register_operand" "")
3983 (match_operand:BI 1 "const_int_operand" "")))]
3984 ""
3985 {
3986 ia64_compare_op0 = operands[0];
3987 ia64_compare_op1 = operands[1];
3988 DONE;
3989 })
3991 (define_expand "cmpsi"
3992 [(set (cc0)
3993 (compare (match_operand:SI 0 "gr_register_operand" "")
3994 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
3995 ""
3996 {
3997 ia64_compare_op0 = operands[0];
3998 ia64_compare_op1 = operands[1];
3999 DONE;
4000 })
4002 (define_expand "cmpdi"
4003 [(set (cc0)
4004 (compare (match_operand:DI 0 "gr_register_operand" "")
4005 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4006 ""
4007 {
4008 ia64_compare_op0 = operands[0];
4009 ia64_compare_op1 = operands[1];
4010 DONE;
4011 })
4013 (define_expand "cmpsf"
4014 [(set (cc0)
4015 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
4016 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
4017 ""
4018 {
4019 ia64_compare_op0 = operands[0];
4020 ia64_compare_op1 = operands[1];
4021 DONE;
4022 })
4024 (define_expand "cmpdf"
4025 [(set (cc0)
4026 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
4027 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
4028 ""
4029 {
4030 ia64_compare_op0 = operands[0];
4031 ia64_compare_op1 = operands[1];
4032 DONE;
4033 })
4035 (define_expand "cmptf"
4036 [(set (cc0)
4037 (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
4038 (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
4039 "INTEL_EXTENDED_IEEE_FORMAT"
4040 {
4041 ia64_compare_op0 = operands[0];
4042 ia64_compare_op1 = operands[1];
4043 DONE;
4044 })
4046 (define_insn "*cmpsi_normal"
4047 [(set (match_operand:BI 0 "register_operand" "=c")
4048 (match_operator:BI 1 "normal_comparison_operator"
4049 [(match_operand:SI 2 "gr_register_operand" "r")
4050 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
4051 ""
4052 "cmp4.%C1 %0, %I0 = %3, %2"
4053 [(set_attr "itanium_class" "icmp")])
4055 ;; We use %r3 because it is possible for us to match a 0, and two of the
4056 ;; unsigned comparisons don't accept immediate operands of zero.
4058 (define_insn "*cmpsi_adjusted"
4059 [(set (match_operand:BI 0 "register_operand" "=c")
4060 (match_operator:BI 1 "adjusted_comparison_operator"
4061 [(match_operand:SI 2 "gr_register_operand" "r")
4062 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4063 ""
4064 "cmp4.%C1 %0, %I0 = %r3, %2"
4065 [(set_attr "itanium_class" "icmp")])
4067 (define_insn "*cmpdi_normal"
4068 [(set (match_operand:BI 0 "register_operand" "=c")
4069 (match_operator:BI 1 "normal_comparison_operator"
4070 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
4071 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
4072 ""
4073 "cmp.%C1 %0, %I0 = %3, %r2"
4074 [(set_attr "itanium_class" "icmp")])
4076 ;; We use %r3 because it is possible for us to match a 0, and two of the
4077 ;; unsigned comparisons don't accept immediate operands of zero.
4079 (define_insn "*cmpdi_adjusted"
4080 [(set (match_operand:BI 0 "register_operand" "=c")
4081 (match_operator:BI 1 "adjusted_comparison_operator"
4082 [(match_operand:DI 2 "gr_register_operand" "r")
4083 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4084 ""
4085 "cmp.%C1 %0, %I0 = %r3, %2"
4086 [(set_attr "itanium_class" "icmp")])
4088 (define_insn "*cmpsf_internal"
4089 [(set (match_operand:BI 0 "register_operand" "=c")
4090 (match_operator:BI 1 "comparison_operator"
4091 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
4092 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
4093 ""
4094 "fcmp.%D1 %0, %I0 = %F2, %F3"
4095 [(set_attr "itanium_class" "fcmp")])
4097 (define_insn "*cmpdf_internal"
4098 [(set (match_operand:BI 0 "register_operand" "=c")
4099 (match_operator:BI 1 "comparison_operator"
4100 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
4101 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
4102 ""
4103 "fcmp.%D1 %0, %I0 = %F2, %F3"
4104 [(set_attr "itanium_class" "fcmp")])
4106 (define_insn "*cmptf_internal"
4107 [(set (match_operand:BI 0 "register_operand" "=c")
4108 (match_operator:BI 1 "comparison_operator"
4109 [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
4110 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
4111 "INTEL_EXTENDED_IEEE_FORMAT"
4112 "fcmp.%D1 %0, %I0 = %F2, %F3"
4113 [(set_attr "itanium_class" "fcmp")])
4115 ;; ??? Can this pattern be generated?
4117 (define_insn "*bit_zero"
4118 [(set (match_operand:BI 0 "register_operand" "=c")
4119 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4120 (const_int 1)
4121 (match_operand:DI 2 "immediate_operand" "n"))
4122 (const_int 0)))]
4123 ""
4124 "tbit.z %0, %I0 = %1, %2"
4125 [(set_attr "itanium_class" "tbit")])
4127 (define_insn "*bit_one"
4128 [(set (match_operand:BI 0 "register_operand" "=c")
4129 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4130 (const_int 1)
4131 (match_operand:DI 2 "immediate_operand" "n"))
4132 (const_int 0)))]
4133 ""
4134 "tbit.nz %0, %I0 = %1, %2"
4135 [(set_attr "itanium_class" "tbit")])
4136 \f
4137 ;; ::::::::::::::::::::
4138 ;; ::
4139 ;; :: Branches
4140 ;; ::
4141 ;; ::::::::::::::::::::
4143 (define_expand "beq"
4144 [(set (pc)
4145 (if_then_else (match_dup 1)
4146 (label_ref (match_operand 0 "" ""))
4147 (pc)))]
4148 ""
4149 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
4151 (define_expand "bne"
4152 [(set (pc)
4153 (if_then_else (match_dup 1)
4154 (label_ref (match_operand 0 "" ""))
4155 (pc)))]
4156 ""
4157 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
4159 (define_expand "blt"
4160 [(set (pc)
4161 (if_then_else (match_dup 1)
4162 (label_ref (match_operand 0 "" ""))
4163 (pc)))]
4164 ""
4165 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
4167 (define_expand "ble"
4168 [(set (pc)
4169 (if_then_else (match_dup 1)
4170 (label_ref (match_operand 0 "" ""))
4171 (pc)))]
4172 ""
4173 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
4175 (define_expand "bgt"
4176 [(set (pc)
4177 (if_then_else (match_dup 1)
4178 (label_ref (match_operand 0 "" ""))
4179 (pc)))]
4180 ""
4181 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
4183 (define_expand "bge"
4184 [(set (pc)
4185 (if_then_else (match_dup 1)
4186 (label_ref (match_operand 0 "" ""))
4187 (pc)))]
4188 ""
4189 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
4191 (define_expand "bltu"
4192 [(set (pc)
4193 (if_then_else (match_dup 1)
4194 (label_ref (match_operand 0 "" ""))
4195 (pc)))]
4196 ""
4197 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
4199 (define_expand "bleu"
4200 [(set (pc)
4201 (if_then_else (match_dup 1)
4202 (label_ref (match_operand 0 "" ""))
4203 (pc)))]
4204 ""
4205 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
4207 (define_expand "bgtu"
4208 [(set (pc)
4209 (if_then_else (match_dup 1)
4210 (label_ref (match_operand 0 "" ""))
4211 (pc)))]
4212 ""
4213 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
4215 (define_expand "bgeu"
4216 [(set (pc)
4217 (if_then_else (match_dup 1)
4218 (label_ref (match_operand 0 "" ""))
4219 (pc)))]
4220 ""
4221 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
4223 (define_expand "bunordered"
4224 [(set (pc)
4225 (if_then_else (match_dup 1)
4226 (label_ref (match_operand 0 "" ""))
4227 (pc)))]
4228 ""
4229 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
4231 (define_expand "bordered"
4232 [(set (pc)
4233 (if_then_else (match_dup 1)
4234 (label_ref (match_operand 0 "" ""))
4235 (pc)))]
4236 ""
4237 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
4239 (define_insn "*br_true"
4240 [(set (pc)
4241 (if_then_else (match_operator 0 "predicate_operator"
4242 [(match_operand:BI 1 "register_operand" "c")
4243 (const_int 0)])
4244 (label_ref (match_operand 2 "" ""))
4245 (pc)))]
4246 ""
4247 "(%J0) br.cond%+ %l2"
4248 [(set_attr "itanium_class" "br")
4249 (set_attr "predicable" "no")])
4251 (define_insn "*br_false"
4252 [(set (pc)
4253 (if_then_else (match_operator 0 "predicate_operator"
4254 [(match_operand:BI 1 "register_operand" "c")
4255 (const_int 0)])
4256 (pc)
4257 (label_ref (match_operand 2 "" ""))))]
4258 ""
4259 "(%j0) br.cond%+ %l2"
4260 [(set_attr "itanium_class" "br")
4261 (set_attr "predicable" "no")])
4262 \f
4263 ;; ::::::::::::::::::::
4264 ;; ::
4265 ;; :: Counted loop operations
4266 ;; ::
4267 ;; ::::::::::::::::::::
4269 (define_expand "doloop_end"
4270 [(use (match_operand 0 "" "")) ; loop pseudo
4271 (use (match_operand 1 "" "")) ; iterations; zero if unknown
4272 (use (match_operand 2 "" "")) ; max iterations
4273 (use (match_operand 3 "" "")) ; loop level
4274 (use (match_operand 4 "" ""))] ; label
4275 ""
4276 {
4277 /* Only use cloop on innermost loops. */
4278 if (INTVAL (operands[3]) > 1)
4279 FAIL;
4280 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
4281 operands[4]));
4282 DONE;
4283 })
4285 (define_insn "doloop_end_internal"
4286 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
4287 (const_int 0))
4288 (label_ref (match_operand 1 "" ""))
4289 (pc)))
4290 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
4291 (plus:DI (match_dup 0) (const_int -1))
4292 (match_dup 0)))]
4293 ""
4294 "br.cloop.sptk.few %l1"
4295 [(set_attr "itanium_class" "br")
4296 (set_attr "predicable" "no")])
4297 \f
4298 ;; ::::::::::::::::::::
4299 ;; ::
4300 ;; :: Set flag operations
4301 ;; ::
4302 ;; ::::::::::::::::::::
4304 (define_expand "seq"
4305 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4306 ""
4307 "operands[1] = ia64_expand_compare (EQ, DImode);")
4309 (define_expand "sne"
4310 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4311 ""
4312 "operands[1] = ia64_expand_compare (NE, DImode);")
4314 (define_expand "slt"
4315 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4316 ""
4317 "operands[1] = ia64_expand_compare (LT, DImode);")
4319 (define_expand "sle"
4320 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4321 ""
4322 "operands[1] = ia64_expand_compare (LE, DImode);")
4324 (define_expand "sgt"
4325 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4326 ""
4327 "operands[1] = ia64_expand_compare (GT, DImode);")
4329 (define_expand "sge"
4330 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4331 ""
4332 "operands[1] = ia64_expand_compare (GE, DImode);")
4334 (define_expand "sltu"
4335 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4336 ""
4337 "operands[1] = ia64_expand_compare (LTU, DImode);")
4339 (define_expand "sleu"
4340 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4341 ""
4342 "operands[1] = ia64_expand_compare (LEU, DImode);")
4344 (define_expand "sgtu"
4345 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4346 ""
4347 "operands[1] = ia64_expand_compare (GTU, DImode);")
4349 (define_expand "sgeu"
4350 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4351 ""
4352 "operands[1] = ia64_expand_compare (GEU, DImode);")
4354 (define_expand "sunordered"
4355 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4356 ""
4357 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
4359 (define_expand "sordered"
4360 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4361 ""
4362 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
4364 ;; Don't allow memory as destination here, because cmov/cmov/st is more
4365 ;; efficient than mov/mov/cst/cst.
4367 (define_insn_and_split "*sne_internal"
4368 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4369 (ne:DI (match_operand:BI 1 "register_operand" "c")
4370 (const_int 0)))]
4371 ""
4372 "#"
4373 "reload_completed"
4374 [(cond_exec (ne (match_dup 1) (const_int 0))
4375 (set (match_dup 0) (const_int 1)))
4376 (cond_exec (eq (match_dup 1) (const_int 0))
4377 (set (match_dup 0) (const_int 0)))]
4378 ""
4379 [(set_attr "itanium_class" "unknown")])
4381 (define_insn_and_split "*seq_internal"
4382 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4383 (eq:DI (match_operand:BI 1 "register_operand" "c")
4384 (const_int 0)))]
4385 ""
4386 "#"
4387 "reload_completed"
4388 [(cond_exec (ne (match_dup 1) (const_int 0))
4389 (set (match_dup 0) (const_int 0)))
4390 (cond_exec (eq (match_dup 1) (const_int 0))
4391 (set (match_dup 0) (const_int 1)))]
4392 ""
4393 [(set_attr "itanium_class" "unknown")])
4394 \f
4395 ;; ::::::::::::::::::::
4396 ;; ::
4397 ;; :: Conditional move instructions.
4398 ;; ::
4399 ;; ::::::::::::::::::::
4401 ;; ??? Add movXXcc patterns?
4403 ;;
4404 ;; DImode if_then_else patterns.
4405 ;;
4407 (define_insn "*cmovdi_internal"
4408 [(set (match_operand:DI 0 "destination_operand"
4409 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
4410 (if_then_else:DI
4411 (match_operator 4 "predicate_operator"
4412 [(match_operand:BI 1 "register_operand"
4413 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
4414 (const_int 0)])
4415 (match_operand:DI 2 "move_operand"
4416 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
4417 (match_operand:DI 3 "move_operand"
4418 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
4419 "ia64_move_ok (operands[0], operands[2])
4420 && ia64_move_ok (operands[0], operands[3])"
4421 { abort (); }
4422 [(set_attr "predicable" "no")])
4424 (define_split
4425 [(set (match_operand 0 "destination_operand" "")
4426 (if_then_else
4427 (match_operator 4 "predicate_operator"
4428 [(match_operand:BI 1 "register_operand" "")
4429 (const_int 0)])
4430 (match_operand 2 "move_operand" "")
4431 (match_operand 3 "move_operand" "")))]
4432 "reload_completed"
4433 [(const_int 0)]
4434 {
4435 rtx tmp;
4436 int emitted_something;
4438 emitted_something = 0;
4439 if (! rtx_equal_p (operands[0], operands[2]))
4440 {
4441 tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]);
4442 tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp);
4443 emit_insn (tmp);
4444 emitted_something = 1;
4445 }
4446 if (! rtx_equal_p (operands[0], operands[3]))
4447 {
4448 tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4449 VOIDmode, operands[1], const0_rtx);
4450 tmp = gen_rtx_COND_EXEC (VOIDmode, tmp,
4451 gen_rtx_SET (VOIDmode, operands[0],
4452 operands[3]));
4453 emit_insn (tmp);
4454 emitted_something = 1;
4455 }
4456 if (! emitted_something)
4457 emit_note (NULL, NOTE_INSN_DELETED);
4458 DONE;
4459 })
4461 ;; Absolute value pattern.
4463 (define_insn "*absdi2_internal"
4464 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4465 (if_then_else:DI
4466 (match_operator 4 "predicate_operator"
4467 [(match_operand:BI 1 "register_operand" "c,c")
4468 (const_int 0)])
4469 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4470 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
4471 ""
4472 "#"
4473 [(set_attr "itanium_class" "ialu,unknown")
4474 (set_attr "predicable" "no")])
4476 (define_split
4477 [(set (match_operand:DI 0 "register_operand" "")
4478 (if_then_else:DI
4479 (match_operator 4 "predicate_operator"
4480 [(match_operand:BI 1 "register_operand" "c,c")
4481 (const_int 0)])
4482 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4483 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4484 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4485 [(cond_exec
4486 (match_dup 4)
4487 (set (match_dup 0)
4488 (neg:DI (match_dup 2))))]
4489 "")
4491 (define_split
4492 [(set (match_operand:DI 0 "register_operand" "")
4493 (if_then_else:DI
4494 (match_operator 4 "predicate_operator"
4495 [(match_operand:BI 1 "register_operand" "c,c")
4496 (const_int 0)])
4497 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4498 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4499 "reload_completed"
4500 [(cond_exec
4501 (match_dup 4)
4502 (set (match_dup 0) (neg:DI (match_dup 2))))
4503 (cond_exec
4504 (match_dup 5)
4505 (set (match_dup 0) (match_dup 3)))]
4506 {
4507 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4508 VOIDmode, operands[1], const0_rtx);
4509 })
4511 ;;
4512 ;; SImode if_then_else patterns.
4513 ;;
4515 (define_insn "*cmovsi_internal"
4516 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
4517 (if_then_else:SI
4518 (match_operator 4 "predicate_operator"
4519 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
4520 (const_int 0)])
4521 (match_operand:SI 2 "move_operand"
4522 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
4523 (match_operand:SI 3 "move_operand"
4524 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
4525 "ia64_move_ok (operands[0], operands[2])
4526 && ia64_move_ok (operands[0], operands[3])"
4527 { abort (); }
4528 [(set_attr "predicable" "no")])
4530 (define_insn "*abssi2_internal"
4531 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
4532 (if_then_else:SI
4533 (match_operator 4 "predicate_operator"
4534 [(match_operand:BI 1 "register_operand" "c,c")
4535 (const_int 0)])
4536 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4537 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
4538 ""
4539 "#"
4540 [(set_attr "itanium_class" "ialu,unknown")
4541 (set_attr "predicable" "no")])
4543 (define_split
4544 [(set (match_operand:SI 0 "register_operand" "")
4545 (if_then_else:SI
4546 (match_operator 4 "predicate_operator"
4547 [(match_operand:BI 1 "register_operand" "c,c")
4548 (const_int 0)])
4549 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4550 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4551 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4552 [(cond_exec
4553 (match_dup 4)
4554 (set (match_dup 0)
4555 (neg:SI (match_dup 2))))]
4556 "")
4558 (define_split
4559 [(set (match_operand:SI 0 "register_operand" "")
4560 (if_then_else:SI
4561 (match_operator 4 "predicate_operator"
4562 [(match_operand:BI 1 "register_operand" "c,c")
4563 (const_int 0)])
4564 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4565 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4566 "reload_completed"
4567 [(cond_exec
4568 (match_dup 4)
4569 (set (match_dup 0) (neg:SI (match_dup 2))))
4570 (cond_exec
4571 (match_dup 5)
4572 (set (match_dup 0) (match_dup 3)))]
4573 {
4574 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4575 VOIDmode, operands[1], const0_rtx);
4576 })
4578 (define_insn_and_split "*cond_opsi2_internal"
4579 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4580 (match_operator:SI 5 "condop_operator"
4581 [(if_then_else:SI
4582 (match_operator 6 "predicate_operator"
4583 [(match_operand:BI 1 "register_operand" "c")
4584 (const_int 0)])
4585 (match_operand:SI 2 "gr_register_operand" "r")
4586 (match_operand:SI 3 "gr_register_operand" "r"))
4587 (match_operand:SI 4 "gr_register_operand" "r")]))]
4588 ""
4589 "#"
4590 "reload_completed"
4591 [(cond_exec
4592 (match_dup 6)
4593 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
4594 (cond_exec
4595 (match_dup 7)
4596 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
4597 {
4598 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4599 VOIDmode, operands[1], const0_rtx);
4600 }
4601 [(set_attr "itanium_class" "ialu")
4602 (set_attr "predicable" "no")])
4605 (define_insn_and_split "*cond_opsi2_internal_b"
4606 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4607 (match_operator:SI 5 "condop_operator"
4608 [(match_operand:SI 4 "gr_register_operand" "r")
4609 (if_then_else:SI
4610 (match_operator 6 "predicate_operator"
4611 [(match_operand:BI 1 "register_operand" "c")
4612 (const_int 0)])
4613 (match_operand:SI 2 "gr_register_operand" "r")
4614 (match_operand:SI 3 "gr_register_operand" "r"))]))]
4615 ""
4616 "#"
4617 "reload_completed"
4618 [(cond_exec
4619 (match_dup 6)
4620 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
4621 (cond_exec
4622 (match_dup 7)
4623 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
4624 {
4625 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4626 VOIDmode, operands[1], const0_rtx);
4627 }
4628 [(set_attr "itanium_class" "ialu")
4629 (set_attr "predicable" "no")])
4631 \f
4632 ;; ::::::::::::::::::::
4633 ;; ::
4634 ;; :: Call and branch instructions
4635 ;; ::
4636 ;; ::::::::::::::::::::
4638 ;; Subroutine call instruction returning no value. Operand 0 is the function
4639 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4640 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4641 ;; registers used as operands.
4643 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4644 ;; is supplied for the sake of some RISC machines which need to put this
4645 ;; information into the assembler code; they can put it in the RTL instead of
4646 ;; operand 1.
4648 (define_expand "call"
4649 [(use (match_operand:DI 0 "" ""))
4650 (use (match_operand 1 "" ""))
4651 (use (match_operand 2 "" ""))
4652 (use (match_operand 3 "" ""))]
4653 ""
4654 {
4655 ia64_expand_call (NULL_RTX, operands[0], operands[2], 0);
4656 DONE;
4657 })
4659 (define_expand "sibcall"
4660 [(use (match_operand:DI 0 "" ""))
4661 (use (match_operand 1 "" ""))
4662 (use (match_operand 2 "" ""))
4663 (use (match_operand 3 "" ""))]
4664 ""
4665 {
4666 ia64_expand_call (NULL_RTX, operands[0], operands[2], 1);
4667 DONE;
4668 })
4670 ;; Subroutine call instruction returning a value. Operand 0 is the hard
4671 ;; register in which the value is returned. There are three more operands,
4672 ;; the same as the three operands of the `call' instruction (but with numbers
4673 ;; increased by one).
4674 ;;
4675 ;; Subroutines that return `BLKmode' objects use the `call' insn.
4677 (define_expand "call_value"
4678 [(use (match_operand 0 "" ""))
4679 (use (match_operand:DI 1 "" ""))
4680 (use (match_operand 2 "" ""))
4681 (use (match_operand 3 "" ""))
4682 (use (match_operand 4 "" ""))]
4683 ""
4684 {
4685 ia64_expand_call (operands[0], operands[1], operands[3], 0);
4686 DONE;
4687 })
4689 (define_expand "sibcall_value"
4690 [(use (match_operand 0 "" ""))
4691 (use (match_operand:DI 1 "" ""))
4692 (use (match_operand 2 "" ""))
4693 (use (match_operand 3 "" ""))
4694 (use (match_operand 4 "" ""))]
4695 ""
4696 {
4697 ia64_expand_call (operands[0], operands[1], operands[3], 1);
4698 DONE;
4699 })
4701 ;; Call subroutine returning any type.
4703 (define_expand "untyped_call"
4704 [(parallel [(call (match_operand 0 "" "")
4705 (const_int 0))
4706 (match_operand 1 "" "")
4707 (match_operand 2 "" "")])]
4708 ""
4709 {
4710 int i;
4712 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4714 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4715 {
4716 rtx set = XVECEXP (operands[2], 0, i);
4717 emit_move_insn (SET_DEST (set), SET_SRC (set));
4718 }
4720 /* The optimizer does not know that the call sets the function value
4721 registers we stored in the result block. We avoid problems by
4722 claiming that all hard registers are used and clobbered at this
4723 point. */
4724 emit_insn (gen_blockage ());
4726 DONE;
4727 })
4729 (define_insn "call_nopic"
4730 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
4731 (match_operand 1 "" ""))
4732 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
4733 ""
4734 "br.call%+.many %2 = %0"
4735 [(set_attr "itanium_class" "br,scall")])
4737 (define_insn "call_value_nopic"
4738 [(set (match_operand 0 "" "")
4739 (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
4740 (match_operand 2 "" "")))
4741 (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
4742 ""
4743 "br.call%+.many %3 = %1"
4744 [(set_attr "itanium_class" "br,scall")])
4746 (define_insn "sibcall_nopic"
4747 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
4748 (match_operand 1 "" ""))
4749 (use (match_operand:DI 2 "register_operand" "=b,b"))
4750 (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))]
4751 ""
4752 "br%+.many %0"
4753 [(set_attr "itanium_class" "br,scall")])
4755 (define_insn "call_pic"
4756 [(call (mem (match_operand 0 "call_operand" "b,i"))
4757 (match_operand 1 "" ""))
4758 (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
4759 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
4760 ""
4761 "br.call%+.many %2 = %0"
4762 [(set_attr "itanium_class" "br,scall")])
4764 (define_insn "call_value_pic"
4765 [(set (match_operand 0 "" "")
4766 (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
4767 (match_operand 2 "" "")))
4768 (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
4769 (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
4770 ""
4771 "br.call%+.many %3 = %1"
4772 [(set_attr "itanium_class" "br,scall")])
4774 (define_insn "sibcall_pic"
4775 [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
4776 (match_operand 1 "" ""))
4777 (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
4778 (use (match_operand:DI 2 "register_operand" "=b"))
4779 (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))]
4780 ""
4781 "br%+.many %0"
4782 [(set_attr "itanium_class" "br")])
4784 (define_insn "return_internal"
4785 [(return)
4786 (use (match_operand:DI 0 "register_operand" "b"))]
4787 ""
4788 "br.ret.sptk.many %0"
4789 [(set_attr "itanium_class" "br")])
4791 (define_insn "return"
4792 [(return)]
4793 "ia64_direct_return ()"
4794 "br.ret.sptk.many rp"
4795 [(set_attr "itanium_class" "br")])
4797 (define_insn "*return_true"
4798 [(set (pc)
4799 (if_then_else (match_operator 0 "predicate_operator"
4800 [(match_operand:BI 1 "register_operand" "c")
4801 (const_int 0)])
4802 (return)
4803 (pc)))]
4804 "ia64_direct_return ()"
4805 "(%J0) br.ret%+.many rp"
4806 [(set_attr "itanium_class" "br")
4807 (set_attr "predicable" "no")])
4809 (define_insn "*return_false"
4810 [(set (pc)
4811 (if_then_else (match_operator 0 "predicate_operator"
4812 [(match_operand:BI 1 "register_operand" "c")
4813 (const_int 0)])
4814 (pc)
4815 (return)))]
4816 "ia64_direct_return ()"
4817 "(%j0) br.ret%+.many rp"
4818 [(set_attr "itanium_class" "br")
4819 (set_attr "predicable" "no")])
4821 (define_insn "jump"
4822 [(set (pc) (label_ref (match_operand 0 "" "")))]
4823 ""
4824 "br %l0"
4825 [(set_attr "itanium_class" "br")])
4827 (define_insn "indirect_jump"
4828 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
4829 ""
4830 "br %0"
4831 [(set_attr "itanium_class" "br")])
4833 (define_expand "tablejump"
4834 [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" ""))
4835 (use (label_ref (match_operand 1 "" "")))])]
4836 ""
4837 {
4838 rtx op0 = operands[0];
4839 rtx addr;
4841 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
4842 element into a register without bothering to see whether that
4843 is necessary given the operand predicate. Check for MEM just
4844 in case someone fixes this. */
4845 if (GET_CODE (op0) == MEM)
4846 addr = XEXP (op0, 0);
4847 else
4848 {
4849 /* Otherwise, cheat and guess that the previous insn in the
4850 stream was the memory load. Grab the address from that.
4851 Note we have to momentarily pop out of the sequence started
4852 by the insn-emit wrapper in order to grab the last insn. */
4853 rtx last, set;
4855 end_sequence ();
4856 last = get_last_insn ();
4857 start_sequence ();
4858 set = single_set (last);
4860 if (! rtx_equal_p (SET_DEST (set), op0)
4861 || GET_CODE (SET_SRC (set)) != MEM)
4862 abort ();
4863 addr = XEXP (SET_SRC (set), 0);
4864 if (rtx_equal_p (addr, op0))
4865 abort ();
4866 }
4868 /* Jump table elements are stored pc-relative. That is, a displacement
4869 from the entry to the label. Thus to convert to an absolute address
4870 we add the address of the memory from which the value is loaded. */
4871 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
4872 NULL_RTX, 1, OPTAB_DIRECT);
4873 })
4875 (define_insn "*tablejump_internal"
4876 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
4877 (use (label_ref (match_operand 1 "" "")))]
4878 ""
4879 "br %0"
4880 [(set_attr "itanium_class" "br")])
4882 \f
4883 ;; ::::::::::::::::::::
4884 ;; ::
4885 ;; :: Prologue and Epilogue instructions
4886 ;; ::
4887 ;; ::::::::::::::::::::
4889 (define_expand "prologue"
4890 [(const_int 1)]
4891 ""
4892 {
4893 ia64_expand_prologue ();
4894 DONE;
4895 })
4897 (define_expand "epilogue"
4898 [(return)]
4899 ""
4900 {
4901 ia64_expand_epilogue (0);
4902 DONE;
4903 })
4905 (define_expand "sibcall_epilogue"
4906 [(return)]
4907 ""
4908 {
4909 ia64_expand_epilogue (1);
4910 DONE;
4911 })
4913 ;; This prevents the scheduler from moving the SP decrement past FP-relative
4914 ;; stack accesses. This is the same as adddi3 plus the extra set.
4916 (define_insn "prologue_allocate_stack"
4917 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4918 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
4919 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
4920 (set (match_operand:DI 3 "register_operand" "+r,r,r")
4921 (match_dup 3))]
4922 ""
4923 "@
4924 add %0 = %1, %2
4925 adds %0 = %2, %1
4926 addl %0 = %2, %1"
4927 [(set_attr "itanium_class" "ialu")])
4929 ;; This prevents the scheduler from moving the SP restore past FP-relative
4930 ;; stack accesses. This is similar to movdi plus the extra set.
4932 (define_insn "epilogue_deallocate_stack"
4933 [(set (match_operand:DI 0 "register_operand" "=r")
4934 (match_operand:DI 1 "register_operand" "+r"))
4935 (set (match_dup 1) (match_dup 1))]
4936 ""
4937 "mov %0 = %1"
4938 [(set_attr "itanium_class" "ialu")])
4940 ;; As USE insns aren't meaningful after reload, this is used instead
4941 ;; to prevent deleting instructions setting registers for EH handling
4942 (define_insn "prologue_use"
4943 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
4944 UNSPEC_PROLOGUE_USE)]
4945 ""
4946 ""
4947 [(set_attr "itanium_class" "ignore")
4948 (set_attr "predicable" "no")])
4950 ;; Allocate a new register frame.
4952 (define_insn "alloc"
4953 [(set (match_operand:DI 0 "register_operand" "=r")
4954 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
4955 (use (match_operand:DI 1 "const_int_operand" "i"))
4956 (use (match_operand:DI 2 "const_int_operand" "i"))
4957 (use (match_operand:DI 3 "const_int_operand" "i"))
4958 (use (match_operand:DI 4 "const_int_operand" "i"))]
4959 ""
4960 "alloc %0 = ar.pfs, %1, %2, %3, %4"
4961 [(set_attr "itanium_class" "syst_m0")
4962 (set_attr "predicable" "no")])
4964 ;; Modifies ar.unat
4965 (define_expand "gr_spill"
4966 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
4967 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4968 (match_operand:DI 2 "const_int_operand" "")]
4969 UNSPEC_GR_SPILL))
4970 (clobber (match_dup 3))])]
4971 ""
4972 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
4974 (define_insn "gr_spill_internal"
4975 [(set (match_operand:DI 0 "memory_operand" "=m")
4976 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4977 (match_operand:DI 2 "const_int_operand" "")]
4978 UNSPEC_GR_SPILL))
4979 (clobber (match_operand:DI 3 "register_operand" ""))]
4980 ""
4981 {
4982 /* Note that we use a C output pattern here to avoid the predicate
4983 being automatically added before the .mem.offset directive. */
4984 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
4985 }
4986 [(set_attr "itanium_class" "st")])
4988 ;; Reads ar.unat
4989 (define_expand "gr_restore"
4990 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
4991 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
4992 (match_operand:DI 2 "const_int_operand" "")]
4993 UNSPEC_GR_RESTORE))
4994 (use (match_dup 3))])]
4995 ""
4996 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
4998 (define_insn "gr_restore_internal"
4999 [(set (match_operand:DI 0 "register_operand" "=r")
5000 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5001 (match_operand:DI 2 "const_int_operand" "")]
5002 UNSPEC_GR_RESTORE))
5003 (use (match_operand:DI 3 "register_operand" ""))]
5004 ""
5005 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
5006 [(set_attr "itanium_class" "ld")])
5008 (define_insn "fr_spill"
5009 [(set (match_operand:TF 0 "memory_operand" "=m")
5010 (unspec:TF [(match_operand:TF 1 "register_operand" "f")]
5011 UNSPEC_FR_SPILL))]
5012 ""
5013 "stf.spill %0 = %1%P0"
5014 [(set_attr "itanium_class" "stf")])
5016 (define_insn "fr_restore"
5017 [(set (match_operand:TF 0 "register_operand" "=f")
5018 (unspec:TF [(match_operand:TF 1 "memory_operand" "m")]
5019 UNSPEC_FR_RESTORE))]
5020 ""
5021 "ldf.fill %0 = %1%P1"
5022 [(set_attr "itanium_class" "fld")])
5024 ;; ??? The explicit stop is not ideal. It would be better if
5025 ;; rtx_needs_barrier took care of this, but this is something that can be
5026 ;; fixed later. This avoids an RSE DV.
5028 (define_insn "bsp_value"
5029 [(set (match_operand:DI 0 "register_operand" "=r")
5030 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
5031 ""
5032 "*
5033 {
5034 return \";;\;%,mov %0 = ar.bsp\";
5035 }"
5036 [(set_attr "itanium_class" "frar_i")])
5038 (define_insn "set_bsp"
5039 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
5040 UNSPECV_SET_BSP)]
5041 ""
5042 "flushrs
5043 mov r19=ar.rsc
5044 ;;
5045 and r19=0x1c,r19
5046 ;;
5047 mov ar.rsc=r19
5048 ;;
5049 mov ar.bspstore=%0
5050 ;;
5051 or r19=0x3,r19
5052 ;;
5053 loadrs
5054 invala
5055 ;;
5056 mov ar.rsc=r19"
5057 [(set_attr "itanium_class" "unknown")
5058 (set_attr "predicable" "no")])
5060 ;; ??? The explicit stops are not ideal. It would be better if
5061 ;; rtx_needs_barrier took care of this, but this is something that can be
5062 ;; fixed later. This avoids an RSE DV.
5064 (define_insn "flushrs"
5065 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
5066 ""
5067 ";;\;flushrs\;;;"
5068 [(set_attr "itanium_class" "rse_m")
5069 (set_attr "predicable" "no")])
5070 \f
5071 ;; ::::::::::::::::::::
5072 ;; ::
5073 ;; :: Miscellaneous instructions
5074 ;; ::
5075 ;; ::::::::::::::::::::
5077 ;; ??? Emiting a NOP instruction isn't very useful. This should probably
5078 ;; be emitting ";;" to force a break in the instruction packing.
5080 ;; No operation, needed in case the user uses -g but not -O.
5081 (define_insn "nop"
5082 [(const_int 0)]
5083 ""
5084 "nop 0"
5085 [(set_attr "itanium_class" "nop")])
5087 (define_insn "nop_m"
5088 [(const_int 1)]
5089 ""
5090 "nop.m 0"
5091 [(set_attr "itanium_class" "nop_m")])
5093 (define_insn "nop_i"
5094 [(const_int 2)]
5095 ""
5096 "nop.i 0"
5097 [(set_attr "itanium_class" "nop_i")])
5099 (define_insn "nop_f"
5100 [(const_int 3)]
5101 ""
5102 "nop.f 0"
5103 [(set_attr "itanium_class" "nop_f")])
5105 (define_insn "nop_b"
5106 [(const_int 4)]
5107 ""
5108 "nop.b 0"
5109 [(set_attr "itanium_class" "nop_b")])
5111 (define_insn "nop_x"
5112 [(const_int 5)]
5113 ""
5114 ""
5115 [(set_attr "itanium_class" "nop_x")])
5117 ;; The following insn will be never generated. It is used only by
5118 ;; insn scheduler to change state before advancing cycle.
5119 (define_insn "pre_cycle"
5120 [(const_int 6)]
5121 ""
5122 ""
5123 [(set_attr "itanium_class" "pre_cycle")])
5125 (define_insn "bundle_selector"
5126 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
5127 ""
5128 { return get_bundle_name (INTVAL (operands[0])); }
5129 [(set_attr "itanium_class" "ignore")
5130 (set_attr "predicable" "no")])
5132 ;; Pseudo instruction that prevents the scheduler from moving code above this
5133 ;; point.
5134 (define_insn "blockage"
5135 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5136 ""
5137 ""
5138 [(set_attr "itanium_class" "ignore")
5139 (set_attr "predicable" "no")])
5141 (define_insn "insn_group_barrier"
5142 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
5143 UNSPECV_INSN_GROUP_BARRIER)]
5144 ""
5145 ";;"
5146 [(set_attr "itanium_class" "stop_bit")
5147 (set_attr "predicable" "no")])
5149 (define_expand "trap"
5150 [(trap_if (const_int 1) (const_int 0))]
5151 ""
5152 "")
5154 ;; ??? We don't have a match-any slot type. Setting the type to unknown
5155 ;; produces worse code that setting the slot type to A.
5157 (define_insn "*trap"
5158 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
5159 ""
5160 "break %0"
5161 [(set_attr "itanium_class" "chk_s")])
5163 (define_expand "conditional_trap"
5164 [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
5165 ""
5166 {
5167 operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode);
5168 })
5170 (define_insn "*conditional_trap"
5171 [(trap_if (match_operator 0 "predicate_operator"
5172 [(match_operand:BI 1 "register_operand" "c")
5173 (const_int 0)])
5174 (match_operand 2 "const_int_operand" ""))]
5175 ""
5176 "(%J0) break %2"
5177 [(set_attr "itanium_class" "chk_s")
5178 (set_attr "predicable" "no")])
5180 (define_insn "break_f"
5181 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
5182 ""
5183 "break.f 0"
5184 [(set_attr "itanium_class" "nop_f")])
5186 (define_insn "prefetch"
5187 [(prefetch (match_operand:DI 0 "address_operand" "p")
5188 (match_operand:DI 1 "const_int_operand" "n")
5189 (match_operand:DI 2 "const_int_operand" "n"))]
5190 ""
5191 {
5192 static const char * const alt[2][4] = {
5193 {
5194 "lfetch.nta [%0]",
5195 "lfetch.nt1 [%0]",
5196 "lfetch.nt2 [%0]",
5197 "lfetch [%0]"
5198 },
5199 {
5200 "lfetch.excl.nta [%0]",
5201 "lfetch.excl.nt1 [%0]",
5202 "lfetch.excl.nt2 [%0]",
5203 "lfetch.excl [%0]"
5204 }
5205 };
5206 int i = (INTVAL (operands[1]));
5207 int j = (INTVAL (operands[2]));
5209 if (i != 0 && i != 1)
5210 abort ();
5211 if (j < 0 || j > 3)
5212 abort ();
5213 return alt[i][j];
5214 }
5215 [(set_attr "itanium_class" "lfetch")])
5216 \f
5217 ;; Non-local goto support.
5219 (define_expand "save_stack_nonlocal"
5220 [(use (match_operand:OI 0 "memory_operand" ""))
5221 (use (match_operand:DI 1 "register_operand" ""))]
5222 ""
5223 {
5224 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5225 \"__ia64_save_stack_nonlocal\"),
5226 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
5227 operands[1], Pmode);
5228 DONE;
5229 })
5231 (define_expand "nonlocal_goto"
5232 [(use (match_operand 0 "general_operand" ""))
5233 (use (match_operand 1 "general_operand" ""))
5234 (use (match_operand 2 "general_operand" ""))
5235 (use (match_operand 3 "general_operand" ""))]
5236 ""
5237 {
5238 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
5239 LCT_NORETURN, VOIDmode, 3,
5240 operands[1], Pmode,
5241 copy_to_reg (XEXP (operands[2], 0)), Pmode,
5242 operands[3], Pmode);
5243 emit_barrier ();
5244 DONE;
5245 })
5247 ;; The rest of the setjmp processing happens with the nonlocal_goto expander.
5248 ;; ??? This is not tested.
5249 (define_expand "builtin_setjmp_setup"
5250 [(use (match_operand:DI 0 "" ""))]
5251 ""
5252 {
5253 emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
5254 DONE;
5255 })
5257 (define_expand "builtin_setjmp_receiver"
5258 [(use (match_operand:DI 0 "" ""))]
5259 ""
5260 {
5261 emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
5262 DONE;
5263 })
5265 (define_expand "eh_epilogue"
5266 [(use (match_operand:DI 0 "register_operand" "r"))
5267 (use (match_operand:DI 1 "register_operand" "r"))
5268 (use (match_operand:DI 2 "register_operand" "r"))]
5269 ""
5270 {
5271 rtx bsp = gen_rtx_REG (Pmode, 10);
5272 rtx sp = gen_rtx_REG (Pmode, 9);
5274 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5275 {
5276 emit_move_insn (bsp, operands[0]);
5277 operands[0] = bsp;
5278 }
5279 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5280 {
5281 emit_move_insn (sp, operands[2]);
5282 operands[2] = sp;
5283 }
5284 emit_insn (gen_rtx_USE (VOIDmode, sp));
5285 emit_insn (gen_rtx_USE (VOIDmode, bsp));
5287 cfun->machine->ia64_eh_epilogue_sp = sp;
5288 cfun->machine->ia64_eh_epilogue_bsp = bsp;
5289 })
5290 \f
5291 ;; Builtin apply support.
5293 (define_expand "restore_stack_nonlocal"
5294 [(use (match_operand:DI 0 "register_operand" ""))
5295 (use (match_operand:OI 1 "memory_operand" ""))]
5296 ""
5297 {
5298 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5299 "__ia64_restore_stack_nonlocal"),
5300 0, VOIDmode, 1,
5301 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5302 DONE;
5303 })
5305 \f
5306 ;;; Intrinsics support.
5308 (define_expand "mf"
5309 [(set (mem:BLK (match_dup 0))
5310 (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
5311 ""
5312 {
5313 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
5314 MEM_VOLATILE_P (operands[0]) = 1;
5315 })
5317 (define_insn "*mf_internal"
5318 [(set (match_operand:BLK 0 "" "")
5319 (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
5320 ""
5321 "mf"
5322 [(set_attr "itanium_class" "syst_m")])
5324 (define_insn "fetchadd_acq_si"
5325 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5326 (match_dup 1))
5327 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5328 (unspec:SI [(match_dup 1)
5329 (match_operand:SI 2 "fetchadd_operand" "n")]
5330 UNSPEC_FETCHADD_ACQ))]
5331 ""
5332 "fetchadd4.acq %0 = %1, %2"
5333 [(set_attr "itanium_class" "sem")])
5335 (define_insn "fetchadd_acq_di"
5336 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5337 (match_dup 1))
5338 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5339 (unspec:DI [(match_dup 1)
5340 (match_operand:DI 2 "fetchadd_operand" "n")]
5341 UNSPEC_FETCHADD_ACQ))]
5342 ""
5343 "fetchadd8.acq %0 = %1, %2"
5344 [(set_attr "itanium_class" "sem")])
5346 (define_insn "cmpxchg_acq_si"
5347 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5348 (match_dup 1))
5349 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5350 (unspec:SI [(match_dup 1)
5351 (match_operand:SI 2 "gr_register_operand" "r")
5352 (match_operand:SI 3 "ar_ccv_reg_operand" "")]
5353 UNSPEC_CMPXCHG_ACQ))]
5354 ""
5355 "cmpxchg4.acq %0 = %1, %2, %3"
5356 [(set_attr "itanium_class" "sem")])
5358 (define_insn "cmpxchg_acq_di"
5359 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5360 (match_dup 1))
5361 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5362 (unspec:DI [(match_dup 1)
5363 (match_operand:DI 2 "gr_register_operand" "r")
5364 (match_operand:DI 3 "ar_ccv_reg_operand" "")]
5365 UNSPEC_CMPXCHG_ACQ))]
5366 ""
5367 "cmpxchg8.acq %0 = %1, %2, %3"
5368 [(set_attr "itanium_class" "sem")])
5370 (define_insn "xchgsi"
5371 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5372 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
5373 (set (match_dup 1)
5374 (match_operand:SI 2 "gr_register_operand" "r"))]
5375 ""
5376 "xchg4 %0 = %1, %2"
5377 [(set_attr "itanium_class" "sem")])
5379 (define_insn "xchgdi"
5380 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5381 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
5382 (set (match_dup 1)
5383 (match_operand:DI 2 "gr_register_operand" "r"))]
5384 ""
5385 "xchg8 %0 = %1, %2"
5386 [(set_attr "itanium_class" "sem")])
5387 \f
5388 ;; Predication.
5390 (define_cond_exec
5391 [(match_operator 0 "predicate_operator"
5392 [(match_operand:BI 1 "register_operand" "c")
5393 (const_int 0)])]
5394 ""
5395 "(%J0)")
5397 (define_insn "pred_rel_mutex"
5398 [(set (match_operand:BI 0 "register_operand" "+c")
5399 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
5400 ""
5401 ".pred.rel.mutex %0, %I0"
5402 [(set_attr "itanium_class" "ignore")
5403 (set_attr "predicable" "no")])
5405 (define_insn "safe_across_calls_all"
5406 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
5407 ""
5408 ".pred.safe_across_calls p1-p63"
5409 [(set_attr "itanium_class" "ignore")
5410 (set_attr "predicable" "no")])
5412 (define_insn "safe_across_calls_normal"
5413 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
5414 ""
5415 {
5416 emit_safe_across_calls (asm_out_file);
5417 return "";
5418 }
5419 [(set_attr "itanium_class" "ignore")
5420 (set_attr "predicable" "no")])
5422 ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
5423 ;; pointer. This is used by the HP-UX 32 bit mode.
5425 (define_insn "ptr_extend"
5426 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5427 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
5428 UNSPEC_ADDP4))]
5429 ""
5430 "addp4 %0 = 0,%1"
5431 [(set_attr "itanium_class" "ialu")])
5433 ;;
5434 ;; Optimizations for ptr_extend
5436 (define_insn "*ptr_extend_plus_1"
5437 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5438 (unspec:DI
5439 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
5440 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
5441 UNSPEC_ADDP4))]
5442 ""
5443 "addp4 %0 = %2, %1"
5444 [(set_attr "itanium_class" "ialu")])
5446 (define_insn "*ptr_extend_plus_2"
5447 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5448 (unspec:DI
5449 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
5450 (match_operand:SI 2 "basereg_operand" "r"))]
5451 UNSPEC_ADDP4))]
5452 ""
5453 "addp4 %0 = %1, %2"
5454 [(set_attr "itanium_class" "ialu")])