| blob | 2d5285a688b76c987202b58348abe91bc76dbe66 |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;;
6 ;; This file is part of GNU CC.
7 ;;
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
27 (define_constants
28 [(UNSPEC_ARG_HOME 0)
29 (UNSPEC_CTTZ 1)
30 (UNSPEC_INSXH 2)
31 (UNSPEC_MSKXH 3)
32 (UNSPEC_CVTQL 4)
33 (UNSPEC_NT_LDA 5)
34 (UNSPEC_UMK_LAUM 6)
35 (UNSPEC_UMK_LALM 7)
36 (UNSPEC_UMK_LAL 8)
37 (UNSPEC_UMK_LOAD_CIW 9)
38 (UNSPEC_LDGP2 10)
39 (UNSPEC_LITERAL 11)
40 (UNSPEC_LITUSE 12)
41 (UNSPEC_SIBCALL 13)
42 (UNSPEC_SYMBOL 14)
44 ;; TLS Support
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
47 (UNSPEC_TLSGD 17)
48 (UNSPEC_TLSLDM 18)
49 (UNSPEC_DTPREL 19)
50 (UNSPEC_TPREL 20)
51 (UNSPEC_TP 21)
53 ;; Builtins
54 (UNSPEC_CMPBGE 22)
55 (UNSPEC_ZAP 23)
56 (UNSPEC_AMASK 24)
57 (UNSPEC_IMPLVER 25)
58 (UNSPEC_PERR 26)
59 (UNSPEC_CTLZ 27)
60 (UNSPEC_CTPOP 28)
61 ])
63 ;; UNSPEC_VOLATILE:
65 (define_constants
66 [(UNSPECV_IMB 0)
67 (UNSPECV_BLOCKAGE 1)
68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
69 (UNSPECV_LONGJMP 3) ; builtin_longjmp
70 (UNSPECV_TRAPB 4)
71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
72 (UNSPECV_REALIGN 6)
73 (UNSPECV_EHR 7) ; exception_receiver
74 (UNSPECV_MCOUNT 8)
75 (UNSPECV_FORCE_MOV 9)
76 (UNSPECV_LDGP1 10)
77 (UNSPECV_PLDGP2 11) ; prologue ldgp
78 (UNSPECV_SET_TP 12)
79 (UNSPECV_RPCC 13)
80 ])
82 ;; Where necessary, the suffixes _le and _be are used to distinguish between
83 ;; little-endian and big-endian patterns.
84 ;;
85 ;; Note that the Unicos/Mk assembler does not support the following
86 ;; opcodes: mov, fmov, nop, fnop, unop.
87 \f
88 ;; Processor type -- this attribute must exactly match the processor_type
89 ;; enumeration in alpha.h.
91 (define_attr "cpu" "ev4,ev5,ev6"
92 (const (symbol_ref "alpha_cpu")))
94 ;; Define an insn type attribute. This is used in function unit delay
95 ;; computations, among other purposes. For the most part, we use the names
96 ;; defined in the EV4 documentation, but add a few that we have to know about
97 ;; separately.
99 (define_attr "type"
100 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
101 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
102 (const_string "iadd"))
104 ;; Describe a user's asm statement.
105 (define_asm_attributes
106 [(set_attr "type" "multi")])
108 ;; Define the operand size an insn operates on. Used primarily by mul
109 ;; and div operations that have size dependent timings.
111 (define_attr "opsize" "si,di,udi"
112 (const_string "di"))
114 ;; The TRAP attribute marks instructions that may generate traps
115 ;; (which are imprecise and may need a trapb if software completion
116 ;; is desired).
118 (define_attr "trap" "no,yes"
119 (const_string "no"))
121 ;; The ROUND_SUFFIX attribute marks which instructions require a
122 ;; rounding-mode suffix. The value NONE indicates no suffix,
123 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
125 (define_attr "round_suffix" "none,normal,c"
126 (const_string "none"))
128 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
129 ;; NONE no suffix
130 ;; SU accepts only /su (cmpt et al)
131 ;; SUI accepts only /sui (cvtqt and cvtqs)
132 ;; V_SV accepts /v and /sv (cvtql only)
133 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
134 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
135 ;;
136 ;; The actual suffix emitted is controled by alpha_fptm.
138 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
139 (const_string "none"))
141 ;; The length of an instruction sequence in bytes.
143 (define_attr "length" ""
144 (const_int 4))
146 ;; The USEGP attribute marks instructions that have relocations that use
147 ;; the GP.
149 (define_attr "usegp" "no,yes"
150 (cond [(eq_attr "type" "ldsym,jsr")
151 (const_string "yes")
152 (eq_attr "type" "ild,fld,ist,fst")
153 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
154 ]
155 (const_string "no")))
157 \f
158 ;; Include scheduling descriptions.
160 (include "ev4.md")
161 (include "ev5.md")
162 (include "ev6.md")
163 \f
164 ;; First define the arithmetic insns. Note that the 32-bit forms also
165 ;; sign-extend.
167 ;; Handle 32-64 bit extension from memory to a floating point register
168 ;; specially, since this occurs frequently in int->double conversions.
169 ;;
170 ;; Note that while we must retain the =f case in the insn for reload's
171 ;; benefit, it should be eliminated after reload, so we should never emit
172 ;; code for that case. But we don't reject the possibility.
174 (define_expand "extendsidi2"
175 [(set (match_operand:DI 0 "register_operand" "")
176 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
177 ""
178 "")
180 (define_insn "*extendsidi2_nofix"
181 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
182 (sign_extend:DI
183 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
184 "! TARGET_FIX"
185 "@
186 addl $31,%1,%0
187 ldl %0,%1
188 cvtlq %1,%0
189 lds %0,%1\;cvtlq %0,%0"
190 [(set_attr "type" "iadd,ild,fadd,fld")
191 (set_attr "length" "*,*,*,8")])
193 (define_insn "*extendsidi2_fix"
194 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
195 (sign_extend:DI
196 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
197 "TARGET_FIX"
198 "@
199 addl $31,%1,%0
200 ldl %0,%1
201 ftois %1,%0
202 cvtlq %1,%0
203 lds %0,%1\;cvtlq %0,%0"
204 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
205 (set_attr "length" "*,*,*,*,8")])
207 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
208 (define_split
209 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
210 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
211 "reload_completed"
212 [(set (match_dup 2) (match_dup 1))
213 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
214 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
216 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
217 ;; reload when converting fp->int.
219 (define_peephole2
220 [(set (match_operand:SI 0 "hard_int_register_operand" "")
221 (match_operand:SI 1 "memory_operand" ""))
222 (set (match_operand:DI 2 "hard_int_register_operand" "")
223 (sign_extend:DI (match_dup 0)))]
224 "true_regnum (operands[0]) == true_regnum (operands[2])
225 || peep2_reg_dead_p (2, operands[0])"
226 [(set (match_dup 2)
227 (sign_extend:DI (match_dup 1)))]
228 "")
230 (define_peephole2
231 [(set (match_operand:SI 0 "hard_int_register_operand" "")
232 (match_operand:SI 1 "hard_fp_register_operand" ""))
233 (set (match_operand:DI 2 "hard_int_register_operand" "")
234 (sign_extend:DI (match_dup 0)))]
235 "TARGET_FIX
236 && (true_regnum (operands[0]) == true_regnum (operands[2])
237 || peep2_reg_dead_p (2, operands[0]))"
238 [(set (match_dup 2)
239 (sign_extend:DI (match_dup 1)))]
240 "")
242 (define_peephole2
243 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
244 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
245 (set (match_operand:DI 2 "hard_int_register_operand" "")
246 (match_dup 0))]
247 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
248 [(set (match_dup 2)
249 (sign_extend:DI (match_dup 1)))]
250 "")
252 ;; Don't say we have addsi3 if optimizing. This generates better code. We
253 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
254 (define_expand "addsi3"
255 [(set (match_operand:SI 0 "register_operand" "")
256 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
257 (match_operand:SI 2 "add_operand" "")))]
258 "! optimize"
259 "")
261 (define_insn "*addsi_internal"
262 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
263 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
264 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
265 ""
266 "@
267 addl %r1,%2,%0
268 subl %r1,%n2,%0
269 lda %0,%2(%r1)
270 ldah %0,%h2(%r1)")
272 (define_split
273 [(set (match_operand:SI 0 "register_operand" "")
274 (plus:SI (match_operand:SI 1 "register_operand" "")
275 (match_operand:SI 2 "const_int_operand" "")))]
276 "! add_operand (operands[2], SImode)"
277 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
278 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
279 {
280 HOST_WIDE_INT val = INTVAL (operands[2]);
281 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
282 HOST_WIDE_INT rest = val - low;
284 operands[3] = GEN_INT (rest);
285 operands[4] = GEN_INT (low);
286 })
288 (define_insn "*addsi_se"
289 [(set (match_operand:DI 0 "register_operand" "=r,r")
290 (sign_extend:DI
291 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
292 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
293 ""
294 "@
295 addl %r1,%2,%0
296 subl %r1,%n2,%0")
298 (define_insn "*addsi_se2"
299 [(set (match_operand:DI 0 "register_operand" "=r,r")
300 (sign_extend:DI
301 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
302 (match_operand:DI 2 "sext_add_operand" "rI,O"))
303 0)))]
304 ""
305 "@
306 addl %r1,%2,%0
307 subl %r1,%n2,%0")
309 (define_split
310 [(set (match_operand:DI 0 "register_operand" "")
311 (sign_extend:DI
312 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
313 (match_operand:SI 2 "const_int_operand" ""))))
314 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
315 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
316 && INTVAL (operands[2]) % 4 == 0"
317 [(set (match_dup 3) (match_dup 4))
318 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
319 (match_dup 5))
320 (match_dup 1))))]
321 {
322 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
323 int mult = 4;
325 if (val % 2 == 0)
326 val /= 2, mult = 8;
328 operands[4] = GEN_INT (val);
329 operands[5] = GEN_INT (mult);
330 })
332 (define_split
333 [(set (match_operand:DI 0 "register_operand" "")
334 (sign_extend:DI
335 (plus:SI (match_operator:SI 1 "comparison_operator"
336 [(match_operand 2 "" "")
337 (match_operand 3 "" "")])
338 (match_operand:SI 4 "add_operand" ""))))
339 (clobber (match_operand:DI 5 "register_operand" ""))]
340 ""
341 [(set (match_dup 5) (match_dup 6))
342 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
343 {
344 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
345 operands[2], operands[3]);
346 operands[7] = gen_lowpart (SImode, operands[5]);
347 })
349 (define_insn "addvsi3"
350 [(set (match_operand:SI 0 "register_operand" "=r,r")
351 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
352 (match_operand:SI 2 "sext_add_operand" "rI,O")))
353 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
354 (sign_extend:DI (match_dup 2)))
355 (sign_extend:DI (plus:SI (match_dup 1)
356 (match_dup 2))))
357 (const_int 0))]
358 ""
359 "@
360 addlv %r1,%2,%0
361 sublv %r1,%n2,%0")
363 (define_expand "adddi3"
364 [(set (match_operand:DI 0 "register_operand" "")
365 (plus:DI (match_operand:DI 1 "register_operand" "")
366 (match_operand:DI 2 "add_operand" "")))]
367 ""
368 "")
370 (define_insn "*adddi_er_lo16_dtp"
371 [(set (match_operand:DI 0 "register_operand" "=r")
372 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
373 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
374 "HAVE_AS_TLS"
375 "lda %0,%2(%1)\t\t!dtprel")
377 (define_insn "*adddi_er_hi32_dtp"
378 [(set (match_operand:DI 0 "register_operand" "=r")
379 (plus:DI (match_operand:DI 1 "register_operand" "r")
380 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
381 "HAVE_AS_TLS"
382 "ldah %0,%2(%1)\t\t!dtprelhi")
384 (define_insn "*adddi_er_lo32_dtp"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
387 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
388 "HAVE_AS_TLS"
389 "lda %0,%2(%1)\t\t!dtprello")
391 (define_insn "*adddi_er_lo16_tp"
392 [(set (match_operand:DI 0 "register_operand" "=r")
393 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
394 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
395 "HAVE_AS_TLS"
396 "lda %0,%2(%1)\t\t!tprel")
398 (define_insn "*adddi_er_hi32_tp"
399 [(set (match_operand:DI 0 "register_operand" "=r")
400 (plus:DI (match_operand:DI 1 "register_operand" "r")
401 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
402 "HAVE_AS_TLS"
403 "ldah %0,%2(%1)\t\t!tprelhi")
405 (define_insn "*adddi_er_lo32_tp"
406 [(set (match_operand:DI 0 "register_operand" "=r")
407 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
408 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
409 "HAVE_AS_TLS"
410 "lda %0,%2(%1)\t\t!tprello")
412 (define_insn "*adddi_er_high_l"
413 [(set (match_operand:DI 0 "register_operand" "=r")
414 (plus:DI (match_operand:DI 1 "register_operand" "r")
415 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
416 "TARGET_EXPLICIT_RELOCS"
417 "ldah %0,%2(%1)\t\t!gprelhigh"
418 [(set_attr "usegp" "yes")])
420 (define_split
421 [(set (match_operand:DI 0 "register_operand" "")
422 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
423 "TARGET_EXPLICIT_RELOCS && reload_completed"
424 [(set (match_dup 0)
425 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
426 "operands[2] = pic_offset_table_rtx;")
428 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
429 ;; With complications like
430 ;;
431 ;; The NT stack unwind code can't handle a subq to adjust the stack
432 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
433 ;; the exception handling code will loop if a subq is used and an
434 ;; exception occurs.
435 ;;
436 ;; The 19980616 change to emit prologues as RTL also confused some
437 ;; versions of GDB, which also interprets prologues. This has been
438 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
439 ;; use lda here.
440 ;;
441 ;; and the fact that the three insns schedule exactly the same, it's
442 ;; just not worth the effort.
444 (define_insn "*adddi_internal"
445 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
446 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
447 (match_operand:DI 2 "add_operand" "r,K,L")))]
448 ""
449 "@
450 addq %1,%2,%0
451 lda %0,%2(%1)
452 ldah %0,%h2(%1)")
454 ;; ??? Allow large constants when basing off the frame pointer or some
455 ;; virtual register that may eliminate to the frame pointer. This is
456 ;; done because register elimination offsets will change the hi/lo split,
457 ;; and if we split before reload, we will require additional instructions.
459 (define_insn "*adddi_fp_hack"
460 [(set (match_operand:DI 0 "register_operand" "=r")
461 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
462 (match_operand:DI 2 "const_int_operand" "n")))]
463 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
464 && INTVAL (operands[2]) >= 0
465 /* This is the largest constant an lda+ldah pair can add, minus
466 an upper bound on the displacement between SP and AP during
467 register elimination. See INITIAL_ELIMINATION_OFFSET. */
468 && INTVAL (operands[2])
469 < (0x7fff8000
470 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
471 - ALPHA_ROUND(current_function_outgoing_args_size)
472 - (ALPHA_ROUND (get_frame_size ()
473 + max_reg_num () * UNITS_PER_WORD
474 + current_function_pretend_args_size)
475 - current_function_pretend_args_size))"
476 "#")
478 ;; Don't do this if we are adjusting SP since we don't want to do it
479 ;; in two steps. Don't split FP sources for the reason listed above.
480 (define_split
481 [(set (match_operand:DI 0 "register_operand" "")
482 (plus:DI (match_operand:DI 1 "register_operand" "")
483 (match_operand:DI 2 "const_int_operand" "")))]
484 "! add_operand (operands[2], DImode)
485 && operands[0] != stack_pointer_rtx
486 && operands[1] != frame_pointer_rtx
487 && operands[1] != arg_pointer_rtx"
488 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
489 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
490 {
491 HOST_WIDE_INT val = INTVAL (operands[2]);
492 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
493 HOST_WIDE_INT rest = val - low;
495 operands[4] = GEN_INT (low);
496 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
497 operands[3] = GEN_INT (rest);
498 else if (! no_new_pseudos)
499 {
500 operands[3] = gen_reg_rtx (DImode);
501 emit_move_insn (operands[3], operands[2]);
502 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
503 DONE;
504 }
505 else
506 FAIL;
507 })
509 (define_insn "*saddl"
510 [(set (match_operand:SI 0 "register_operand" "=r,r")
511 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
512 (match_operand:SI 2 "const48_operand" "I,I"))
513 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
514 ""
515 "@
516 s%2addl %1,%3,%0
517 s%2subl %1,%n3,%0")
519 (define_insn "*saddl_se"
520 [(set (match_operand:DI 0 "register_operand" "=r,r")
521 (sign_extend:DI
522 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
523 (match_operand:SI 2 "const48_operand" "I,I"))
524 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
525 ""
526 "@
527 s%2addl %1,%3,%0
528 s%2subl %1,%n3,%0")
530 (define_split
531 [(set (match_operand:DI 0 "register_operand" "")
532 (sign_extend:DI
533 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
534 [(match_operand 2 "" "")
535 (match_operand 3 "" "")])
536 (match_operand:SI 4 "const48_operand" ""))
537 (match_operand:SI 5 "sext_add_operand" ""))))
538 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
539 ""
540 [(set (match_dup 6) (match_dup 7))
541 (set (match_dup 0)
542 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
543 (match_dup 5))))]
544 {
545 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
546 operands[2], operands[3]);
547 operands[8] = gen_lowpart (SImode, operands[6]);
548 })
550 (define_insn "*saddq"
551 [(set (match_operand:DI 0 "register_operand" "=r,r")
552 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
553 (match_operand:DI 2 "const48_operand" "I,I"))
554 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
555 ""
556 "@
557 s%2addq %1,%3,%0
558 s%2subq %1,%n3,%0")
560 (define_insn "addvdi3"
561 [(set (match_operand:DI 0 "register_operand" "=r,r")
562 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
563 (match_operand:DI 2 "sext_add_operand" "rI,O")))
564 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
565 (sign_extend:TI (match_dup 2)))
566 (sign_extend:TI (plus:DI (match_dup 1)
567 (match_dup 2))))
568 (const_int 0))]
569 ""
570 "@
571 addqv %r1,%2,%0
572 subqv %r1,%n2,%0")
574 (define_insn "negsi2"
575 [(set (match_operand:SI 0 "register_operand" "=r")
576 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
577 ""
578 "subl $31,%1,%0")
580 (define_insn "*negsi_se"
581 [(set (match_operand:DI 0 "register_operand" "=r")
582 (sign_extend:DI (neg:SI
583 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
584 ""
585 "subl $31,%1,%0")
587 (define_insn "negvsi2"
588 [(set (match_operand:SI 0 "register_operand" "=r")
589 (neg:SI (match_operand:SI 1 "register_operand" "r")))
590 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
591 (sign_extend:DI (neg:SI (match_dup 1))))
592 (const_int 0))]
593 ""
594 "sublv $31,%1,%0")
596 (define_insn "negdi2"
597 [(set (match_operand:DI 0 "register_operand" "=r")
598 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
599 ""
600 "subq $31,%1,%0")
602 (define_insn "negvdi2"
603 [(set (match_operand:DI 0 "register_operand" "=r")
604 (neg:DI (match_operand:DI 1 "register_operand" "r")))
605 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
606 (sign_extend:TI (neg:DI (match_dup 1))))
607 (const_int 0))]
608 ""
609 "subqv $31,%1,%0")
611 (define_expand "subsi3"
612 [(set (match_operand:SI 0 "register_operand" "")
613 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
614 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
615 "! optimize"
616 "")
618 (define_insn "*subsi_internal"
619 [(set (match_operand:SI 0 "register_operand" "=r")
620 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
621 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
622 ""
623 "subl %r1,%2,%0")
625 (define_insn "*subsi_se"
626 [(set (match_operand:DI 0 "register_operand" "=r")
627 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
628 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
629 ""
630 "subl %r1,%2,%0")
632 (define_insn "*subsi_se2"
633 [(set (match_operand:DI 0 "register_operand" "=r")
634 (sign_extend:DI
635 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
636 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
637 0)))]
638 ""
639 "subl %r1,%2,%0")
641 (define_insn "subvsi3"
642 [(set (match_operand:SI 0 "register_operand" "=r")
643 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
644 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
645 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
646 (sign_extend:DI (match_dup 2)))
647 (sign_extend:DI (minus:SI (match_dup 1)
648 (match_dup 2))))
649 (const_int 0))]
650 ""
651 "sublv %r1,%2,%0")
653 (define_insn "subdi3"
654 [(set (match_operand:DI 0 "register_operand" "=r")
655 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
656 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
657 ""
658 "subq %r1,%2,%0")
660 (define_insn "*ssubl"
661 [(set (match_operand:SI 0 "register_operand" "=r")
662 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
663 (match_operand:SI 2 "const48_operand" "I"))
664 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
665 ""
666 "s%2subl %1,%3,%0")
668 (define_insn "*ssubl_se"
669 [(set (match_operand:DI 0 "register_operand" "=r")
670 (sign_extend:DI
671 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
672 (match_operand:SI 2 "const48_operand" "I"))
673 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
674 ""
675 "s%2subl %1,%3,%0")
677 (define_insn "*ssubq"
678 [(set (match_operand:DI 0 "register_operand" "=r")
679 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
680 (match_operand:DI 2 "const48_operand" "I"))
681 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
682 ""
683 "s%2subq %1,%3,%0")
685 (define_insn "subvdi3"
686 [(set (match_operand:DI 0 "register_operand" "=r")
687 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
688 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
689 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
690 (sign_extend:TI (match_dup 2)))
691 (sign_extend:TI (minus:DI (match_dup 1)
692 (match_dup 2))))
693 (const_int 0))]
694 ""
695 "subqv %r1,%2,%0")
697 ;; The Unicos/Mk assembler doesn't support mull.
699 (define_insn "mulsi3"
700 [(set (match_operand:SI 0 "register_operand" "=r")
701 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
702 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
703 "!TARGET_ABI_UNICOSMK"
704 "mull %r1,%2,%0"
705 [(set_attr "type" "imul")
706 (set_attr "opsize" "si")])
708 (define_insn "*mulsi_se"
709 [(set (match_operand:DI 0 "register_operand" "=r")
710 (sign_extend:DI
711 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
712 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
713 "!TARGET_ABI_UNICOSMK"
714 "mull %r1,%2,%0"
715 [(set_attr "type" "imul")
716 (set_attr "opsize" "si")])
718 (define_insn "mulvsi3"
719 [(set (match_operand:SI 0 "register_operand" "=r")
720 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
721 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
722 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
723 (sign_extend:DI (match_dup 2)))
724 (sign_extend:DI (mult:SI (match_dup 1)
725 (match_dup 2))))
726 (const_int 0))]
727 "!TARGET_ABI_UNICOSMK"
728 "mullv %r1,%2,%0"
729 [(set_attr "type" "imul")
730 (set_attr "opsize" "si")])
732 (define_insn "muldi3"
733 [(set (match_operand:DI 0 "register_operand" "=r")
734 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
735 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
736 ""
737 "mulq %r1,%2,%0"
738 [(set_attr "type" "imul")])
740 (define_insn "mulvdi3"
741 [(set (match_operand:DI 0 "register_operand" "=r")
742 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
743 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
744 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
745 (sign_extend:TI (match_dup 2)))
746 (sign_extend:TI (mult:DI (match_dup 1)
747 (match_dup 2))))
748 (const_int 0))]
749 ""
750 "mulqv %r1,%2,%0"
751 [(set_attr "type" "imul")])
753 (define_insn "umuldi3_highpart"
754 [(set (match_operand:DI 0 "register_operand" "=r")
755 (truncate:DI
756 (lshiftrt:TI
757 (mult:TI (zero_extend:TI
758 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
759 (zero_extend:TI
760 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
761 (const_int 64))))]
762 ""
763 "umulh %r1,%2,%0"
764 [(set_attr "type" "imul")
765 (set_attr "opsize" "udi")])
767 (define_insn "*umuldi3_highpart_const"
768 [(set (match_operand:DI 0 "register_operand" "=r")
769 (truncate:DI
770 (lshiftrt:TI
771 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
772 (match_operand:TI 2 "cint8_operand" "I"))
773 (const_int 64))))]
774 ""
775 "umulh %1,%2,%0"
776 [(set_attr "type" "imul")
777 (set_attr "opsize" "udi")])
778 \f
779 ;; The divide and remainder operations take their inputs from r24 and
780 ;; r25, put their output in r27, and clobber r23 and r28 on all
781 ;; systems except Unicos/Mk. On Unicos, the standard library provides
782 ;; subroutines which use the standard calling convention and work on
783 ;; DImode operands.
785 ;; ??? Force sign-extension here because some versions of OSF/1 and
786 ;; Interix/NT don't do the right thing if the inputs are not properly
787 ;; sign-extended. But Linux, for instance, does not have this
788 ;; problem. Is it worth the complication here to eliminate the sign
789 ;; extension?
791 (define_expand "divsi3"
792 [(set (match_dup 3)
793 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
794 (set (match_dup 4)
795 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
796 (parallel [(set (match_dup 5)
797 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
798 (clobber (reg:DI 23))
799 (clobber (reg:DI 28))])
800 (set (match_operand:SI 0 "nonimmediate_operand" "")
801 (subreg:SI (match_dup 5) 0))]
802 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
803 {
804 operands[3] = gen_reg_rtx (DImode);
805 operands[4] = gen_reg_rtx (DImode);
806 operands[5] = gen_reg_rtx (DImode);
807 })
809 (define_expand "udivsi3"
810 [(set (match_dup 3)
811 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
812 (set (match_dup 4)
813 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
814 (parallel [(set (match_dup 5)
815 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
816 (clobber (reg:DI 23))
817 (clobber (reg:DI 28))])
818 (set (match_operand:SI 0 "nonimmediate_operand" "")
819 (subreg:SI (match_dup 5) 0))]
820 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
821 {
822 operands[3] = gen_reg_rtx (DImode);
823 operands[4] = gen_reg_rtx (DImode);
824 operands[5] = gen_reg_rtx (DImode);
825 })
827 (define_expand "modsi3"
828 [(set (match_dup 3)
829 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
830 (set (match_dup 4)
831 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
832 (parallel [(set (match_dup 5)
833 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
834 (clobber (reg:DI 23))
835 (clobber (reg:DI 28))])
836 (set (match_operand:SI 0 "nonimmediate_operand" "")
837 (subreg:SI (match_dup 5) 0))]
838 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
839 {
840 operands[3] = gen_reg_rtx (DImode);
841 operands[4] = gen_reg_rtx (DImode);
842 operands[5] = gen_reg_rtx (DImode);
843 })
845 (define_expand "umodsi3"
846 [(set (match_dup 3)
847 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
848 (set (match_dup 4)
849 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
850 (parallel [(set (match_dup 5)
851 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
852 (clobber (reg:DI 23))
853 (clobber (reg:DI 28))])
854 (set (match_operand:SI 0 "nonimmediate_operand" "")
855 (subreg:SI (match_dup 5) 0))]
856 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
857 {
858 operands[3] = gen_reg_rtx (DImode);
859 operands[4] = gen_reg_rtx (DImode);
860 operands[5] = gen_reg_rtx (DImode);
861 })
863 (define_expand "divdi3"
864 [(parallel [(set (match_operand:DI 0 "register_operand" "")
865 (div:DI (match_operand:DI 1 "register_operand" "")
866 (match_operand:DI 2 "register_operand" "")))
867 (clobber (reg:DI 23))
868 (clobber (reg:DI 28))])]
869 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
870 "")
872 (define_expand "udivdi3"
873 [(parallel [(set (match_operand:DI 0 "register_operand" "")
874 (udiv:DI (match_operand:DI 1 "register_operand" "")
875 (match_operand:DI 2 "register_operand" "")))
876 (clobber (reg:DI 23))
877 (clobber (reg:DI 28))])]
878 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
879 "")
881 (define_expand "moddi3"
882 [(use (match_operand:DI 0 "register_operand" ""))
883 (use (match_operand:DI 1 "register_operand" ""))
884 (use (match_operand:DI 2 "register_operand" ""))]
885 "!TARGET_ABI_OPEN_VMS"
886 {
887 if (TARGET_ABI_UNICOSMK)
888 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
889 else
890 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
891 DONE;
892 })
894 (define_expand "moddi3_dft"
895 [(parallel [(set (match_operand:DI 0 "register_operand" "")
896 (mod:DI (match_operand:DI 1 "register_operand" "")
897 (match_operand:DI 2 "register_operand" "")))
898 (clobber (reg:DI 23))
899 (clobber (reg:DI 28))])]
900 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
901 "")
903 ;; On Unicos/Mk, we do as the system's C compiler does:
904 ;; compute the quotient, multiply and subtract.
906 (define_expand "moddi3_umk"
907 [(use (match_operand:DI 0 "register_operand" ""))
908 (use (match_operand:DI 1 "register_operand" ""))
909 (use (match_operand:DI 2 "register_operand" ""))]
910 "TARGET_ABI_UNICOSMK"
911 {
912 rtx div, mul = gen_reg_rtx (DImode);
914 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
915 NULL_RTX, 0, OPTAB_LIB);
916 div = force_reg (DImode, div);
917 emit_insn (gen_muldi3 (mul, operands[2], div));
918 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
919 DONE;
920 })
922 (define_expand "umoddi3"
923 [(use (match_operand:DI 0 "register_operand" ""))
924 (use (match_operand:DI 1 "register_operand" ""))
925 (use (match_operand:DI 2 "register_operand" ""))]
926 "! TARGET_ABI_OPEN_VMS"
927 {
928 if (TARGET_ABI_UNICOSMK)
929 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
930 else
931 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
932 DONE;
933 })
935 (define_expand "umoddi3_dft"
936 [(parallel [(set (match_operand:DI 0 "register_operand" "")
937 (umod:DI (match_operand:DI 1 "register_operand" "")
938 (match_operand:DI 2 "register_operand" "")))
939 (clobber (reg:DI 23))
940 (clobber (reg:DI 28))])]
941 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
942 "")
944 (define_expand "umoddi3_umk"
945 [(use (match_operand:DI 0 "register_operand" ""))
946 (use (match_operand:DI 1 "register_operand" ""))
947 (use (match_operand:DI 2 "register_operand" ""))]
948 "TARGET_ABI_UNICOSMK"
949 {
950 rtx div, mul = gen_reg_rtx (DImode);
952 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
953 NULL_RTX, 1, OPTAB_LIB);
954 div = force_reg (DImode, div);
955 emit_insn (gen_muldi3 (mul, operands[2], div));
956 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
957 DONE;
958 })
960 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
961 ;; expanded by the assembler.
963 (define_insn_and_split "*divmodsi_internal_er"
964 [(set (match_operand:DI 0 "register_operand" "=c")
965 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
966 [(match_operand:DI 1 "register_operand" "a")
967 (match_operand:DI 2 "register_operand" "b")])))
968 (clobber (reg:DI 23))
969 (clobber (reg:DI 28))]
970 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
971 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
972 "&& reload_completed"
973 [(parallel [(set (match_dup 0)
974 (sign_extend:DI (match_dup 3)))
975 (use (match_dup 0))
976 (use (match_dup 4))
977 (clobber (reg:DI 23))
978 (clobber (reg:DI 28))])]
979 {
980 const char *str;
981 switch (GET_CODE (operands[3]))
982 {
983 case DIV:
984 str = "__divl";
985 break;
986 case UDIV:
987 str = "__divlu";
988 break;
989 case MOD:
990 str = "__reml";
991 break;
992 case UMOD:
993 str = "__remlu";
994 break;
995 default:
996 abort ();
997 }
998 operands[4] = GEN_INT (alpha_next_sequence_number++);
999 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1000 gen_rtx_SYMBOL_REF (DImode, str),
1001 operands[4]));
1002 }
1003 [(set_attr "type" "jsr")
1004 (set_attr "length" "8")])
1006 (define_insn "*divmodsi_internal_er_1"
1007 [(set (match_operand:DI 0 "register_operand" "=c")
1008 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1009 [(match_operand:DI 1 "register_operand" "a")
1010 (match_operand:DI 2 "register_operand" "b")])))
1011 (use (match_operand:DI 4 "register_operand" "c"))
1012 (use (match_operand 5 "const_int_operand" ""))
1013 (clobber (reg:DI 23))
1014 (clobber (reg:DI 28))]
1015 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1016 "jsr $23,($27),__%E3%J5"
1017 [(set_attr "type" "jsr")
1018 (set_attr "length" "4")])
1020 (define_insn "*divmodsi_internal"
1021 [(set (match_operand:DI 0 "register_operand" "=c")
1022 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1023 [(match_operand:DI 1 "register_operand" "a")
1024 (match_operand:DI 2 "register_operand" "b")])))
1025 (clobber (reg:DI 23))
1026 (clobber (reg:DI 28))]
1027 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1028 "%E3 %1,%2,%0"
1029 [(set_attr "type" "jsr")
1030 (set_attr "length" "8")])
1032 (define_insn_and_split "*divmoddi_internal_er"
1033 [(set (match_operand:DI 0 "register_operand" "=c")
1034 (match_operator:DI 3 "divmod_operator"
1035 [(match_operand:DI 1 "register_operand" "a")
1036 (match_operand:DI 2 "register_operand" "b")]))
1037 (clobber (reg:DI 23))
1038 (clobber (reg:DI 28))]
1039 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1040 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1041 "&& reload_completed"
1042 [(parallel [(set (match_dup 0) (match_dup 3))
1043 (use (match_dup 0))
1044 (use (match_dup 4))
1045 (clobber (reg:DI 23))
1046 (clobber (reg:DI 28))])]
1047 {
1048 const char *str;
1049 switch (GET_CODE (operands[3]))
1050 {
1051 case DIV:
1052 str = "__divq";
1053 break;
1054 case UDIV:
1055 str = "__divqu";
1056 break;
1057 case MOD:
1058 str = "__remq";
1059 break;
1060 case UMOD:
1061 str = "__remqu";
1062 break;
1063 default:
1064 abort ();
1065 }
1066 operands[4] = GEN_INT (alpha_next_sequence_number++);
1067 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1068 gen_rtx_SYMBOL_REF (DImode, str),
1069 operands[4]));
1070 }
1071 [(set_attr "type" "jsr")
1072 (set_attr "length" "8")])
1074 (define_insn "*divmoddi_internal_er_1"
1075 [(set (match_operand:DI 0 "register_operand" "=c")
1076 (match_operator:DI 3 "divmod_operator"
1077 [(match_operand:DI 1 "register_operand" "a")
1078 (match_operand:DI 2 "register_operand" "b")]))
1079 (use (match_operand:DI 4 "register_operand" "c"))
1080 (use (match_operand 5 "const_int_operand" ""))
1081 (clobber (reg:DI 23))
1082 (clobber (reg:DI 28))]
1083 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1084 "jsr $23,($27),__%E3%J5"
1085 [(set_attr "type" "jsr")
1086 (set_attr "length" "4")])
1088 (define_insn "*divmoddi_internal"
1089 [(set (match_operand:DI 0 "register_operand" "=c")
1090 (match_operator:DI 3 "divmod_operator"
1091 [(match_operand:DI 1 "register_operand" "a")
1092 (match_operand:DI 2 "register_operand" "b")]))
1093 (clobber (reg:DI 23))
1094 (clobber (reg:DI 28))]
1095 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1096 "%E3 %1,%2,%0"
1097 [(set_attr "type" "jsr")
1098 (set_attr "length" "8")])
1099 \f
1100 ;; Next are the basic logical operations. These only exist in DImode.
1102 (define_insn "anddi3"
1103 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1104 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1105 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1106 ""
1107 "@
1108 and %r1,%2,%0
1109 bic %r1,%N2,%0
1110 zapnot %r1,%m2,%0"
1111 [(set_attr "type" "ilog,ilog,shift")])
1113 ;; There are times when we can split an AND into two AND insns. This occurs
1114 ;; when we can first clear any bytes and then clear anything else. For
1115 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1116 ;; Only do this when running on 64-bit host since the computations are
1117 ;; too messy otherwise.
1119 (define_split
1120 [(set (match_operand:DI 0 "register_operand" "")
1121 (and:DI (match_operand:DI 1 "register_operand" "")
1122 (match_operand:DI 2 "const_int_operand" "")))]
1123 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1124 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1125 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1126 {
1127 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1128 unsigned HOST_WIDE_INT mask2 = mask1;
1129 int i;
1131 /* For each byte that isn't all zeros, make it all ones. */
1132 for (i = 0; i < 64; i += 8)
1133 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1134 mask1 |= (HOST_WIDE_INT) 0xff << i;
1136 /* Now turn on any bits we've just turned off. */
1137 mask2 |= ~ mask1;
1139 operands[3] = GEN_INT (mask1);
1140 operands[4] = GEN_INT (mask2);
1141 })
1143 (define_expand "zero_extendqihi2"
1144 [(set (match_operand:HI 0 "register_operand" "")
1145 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1146 ""
1147 {
1148 if (! TARGET_BWX)
1149 operands[1] = force_reg (QImode, operands[1]);
1150 })
1152 (define_insn "*zero_extendqihi2_bwx"
1153 [(set (match_operand:HI 0 "register_operand" "=r,r")
1154 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1155 "TARGET_BWX"
1156 "@
1157 and %1,0xff,%0
1158 ldbu %0,%1"
1159 [(set_attr "type" "ilog,ild")])
1161 (define_insn "*zero_extendqihi2_nobwx"
1162 [(set (match_operand:HI 0 "register_operand" "=r")
1163 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1164 "! TARGET_BWX"
1165 "and %1,0xff,%0"
1166 [(set_attr "type" "ilog")])
1168 (define_expand "zero_extendqisi2"
1169 [(set (match_operand:SI 0 "register_operand" "")
1170 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1171 ""
1172 {
1173 if (! TARGET_BWX)
1174 operands[1] = force_reg (QImode, operands[1]);
1175 })
1177 (define_insn "*zero_extendqisi2_bwx"
1178 [(set (match_operand:SI 0 "register_operand" "=r,r")
1179 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1180 "TARGET_BWX"
1181 "@
1182 and %1,0xff,%0
1183 ldbu %0,%1"
1184 [(set_attr "type" "ilog,ild")])
1186 (define_insn "*zero_extendqisi2_nobwx"
1187 [(set (match_operand:SI 0 "register_operand" "=r")
1188 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1189 "! TARGET_BWX"
1190 "and %1,0xff,%0"
1191 [(set_attr "type" "ilog")])
1193 (define_expand "zero_extendqidi2"
1194 [(set (match_operand:DI 0 "register_operand" "")
1195 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1196 ""
1197 {
1198 if (! TARGET_BWX)
1199 operands[1] = force_reg (QImode, operands[1]);
1200 })
1202 (define_insn "*zero_extendqidi2_bwx"
1203 [(set (match_operand:DI 0 "register_operand" "=r,r")
1204 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1205 "TARGET_BWX"
1206 "@
1207 and %1,0xff,%0
1208 ldbu %0,%1"
1209 [(set_attr "type" "ilog,ild")])
1211 (define_insn "*zero_extendqidi2_nobwx"
1212 [(set (match_operand:DI 0 "register_operand" "=r")
1213 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1214 "! TARGET_BWX"
1215 "and %1,0xff,%0"
1216 [(set_attr "type" "ilog")])
1218 (define_expand "zero_extendhisi2"
1219 [(set (match_operand:SI 0 "register_operand" "")
1220 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1221 ""
1222 {
1223 if (! TARGET_BWX)
1224 operands[1] = force_reg (HImode, operands[1]);
1225 })
1227 (define_insn "*zero_extendhisi2_bwx"
1228 [(set (match_operand:SI 0 "register_operand" "=r,r")
1229 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1230 "TARGET_BWX"
1231 "@
1232 zapnot %1,3,%0
1233 ldwu %0,%1"
1234 [(set_attr "type" "shift,ild")])
1236 (define_insn "*zero_extendhisi2_nobwx"
1237 [(set (match_operand:SI 0 "register_operand" "=r")
1238 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1239 "! TARGET_BWX"
1240 "zapnot %1,3,%0"
1241 [(set_attr "type" "shift")])
1243 (define_expand "zero_extendhidi2"
1244 [(set (match_operand:DI 0 "register_operand" "")
1245 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1246 ""
1247 {
1248 if (! TARGET_BWX)
1249 operands[1] = force_reg (HImode, operands[1]);
1250 })
1252 (define_insn "*zero_extendhidi2_bwx"
1253 [(set (match_operand:DI 0 "register_operand" "=r,r")
1254 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1255 "TARGET_BWX"
1256 "@
1257 zapnot %1,3,%0
1258 ldwu %0,%1"
1259 [(set_attr "type" "shift,ild")])
1261 (define_insn "*zero_extendhidi2_nobwx"
1262 [(set (match_operand:DI 0 "register_operand" "=r")
1263 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1264 ""
1265 "zapnot %1,3,%0"
1266 [(set_attr "type" "shift")])
1268 (define_insn "zero_extendsidi2"
1269 [(set (match_operand:DI 0 "register_operand" "=r")
1270 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1271 ""
1272 "zapnot %1,15,%0"
1273 [(set_attr "type" "shift")])
1275 (define_insn "andnotdi3"
1276 [(set (match_operand:DI 0 "register_operand" "=r")
1277 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1278 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1279 ""
1280 "bic %r2,%1,%0"
1281 [(set_attr "type" "ilog")])
1283 (define_insn "iordi3"
1284 [(set (match_operand:DI 0 "register_operand" "=r,r")
1285 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1286 (match_operand:DI 2 "or_operand" "rI,N")))]
1287 ""
1288 "@
1289 bis %r1,%2,%0
1290 ornot %r1,%N2,%0"
1291 [(set_attr "type" "ilog")])
1293 (define_insn "one_cmpldi2"
1294 [(set (match_operand:DI 0 "register_operand" "=r")
1295 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1296 ""
1297 "ornot $31,%1,%0"
1298 [(set_attr "type" "ilog")])
1300 (define_insn "*iornot"
1301 [(set (match_operand:DI 0 "register_operand" "=r")
1302 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1303 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1304 ""
1305 "ornot %r2,%1,%0"
1306 [(set_attr "type" "ilog")])
1308 (define_insn "xordi3"
1309 [(set (match_operand:DI 0 "register_operand" "=r,r")
1310 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1311 (match_operand:DI 2 "or_operand" "rI,N")))]
1312 ""
1313 "@
1314 xor %r1,%2,%0
1315 eqv %r1,%N2,%0"
1316 [(set_attr "type" "ilog")])
1318 (define_insn "*xornot"
1319 [(set (match_operand:DI 0 "register_operand" "=r")
1320 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1321 (match_operand:DI 2 "register_operand" "rI"))))]
1322 ""
1323 "eqv %r1,%2,%0"
1324 [(set_attr "type" "ilog")])
1325 \f
1326 ;; Handle FFS and related insns iff we support CIX.
1328 (define_expand "ffsdi2"
1329 [(set (match_dup 2)
1330 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1331 (set (match_dup 3)
1332 (plus:DI (match_dup 2) (const_int 1)))
1333 (set (match_operand:DI 0 "register_operand" "")
1334 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1335 (const_int 0) (match_dup 3)))]
1336 "TARGET_CIX"
1337 {
1338 operands[2] = gen_reg_rtx (DImode);
1339 operands[3] = gen_reg_rtx (DImode);
1340 })
1342 (define_insn "*cttz"
1343 [(set (match_operand:DI 0 "register_operand" "=r")
1344 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1345 "TARGET_CIX"
1346 "cttz %1,%0"
1347 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1348 ; reuse the existing type name.
1349 [(set_attr "type" "mvi")])
1351 (define_insn "clzdi2"
1352 [(set (match_operand:DI 0 "register_operand" "=r")
1353 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1354 "TARGET_CIX"
1355 "ctlz %1,%0"
1356 [(set_attr "type" "mvi")])
1358 (define_insn "ctzdi2"
1359 [(set (match_operand:DI 0 "register_operand" "=r")
1360 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1361 "TARGET_CIX"
1362 "cttz %1,%0"
1363 [(set_attr "type" "mvi")])
1365 (define_insn "popcountdi2"
1366 [(set (match_operand:DI 0 "register_operand" "=r")
1367 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1368 "TARGET_CIX"
1369 "ctpop %1,%0"
1370 [(set_attr "type" "mvi")])
1371 \f
1372 ;; Next come the shifts and the various extract and insert operations.
1374 (define_insn "ashldi3"
1375 [(set (match_operand:DI 0 "register_operand" "=r,r")
1376 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1377 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1378 ""
1379 {
1380 switch (which_alternative)
1381 {
1382 case 0:
1383 if (operands[2] == const1_rtx)
1384 return "addq %r1,%r1,%0";
1385 else
1386 return "s%P2addq %r1,0,%0";
1387 case 1:
1388 return "sll %r1,%2,%0";
1389 default:
1390 abort();
1391 }
1392 }
1393 [(set_attr "type" "iadd,shift")])
1395 (define_insn "*ashldi_se"
1396 [(set (match_operand:DI 0 "register_operand" "=r")
1397 (sign_extend:DI
1398 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1399 (match_operand:DI 2 "const_int_operand" "P"))
1400 0)))]
1401 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1402 {
1403 if (operands[2] == const1_rtx)
1404 return "addl %r1,%r1,%0";
1405 else
1406 return "s%P2addl %r1,0,%0";
1407 }
1408 [(set_attr "type" "iadd")])
1410 (define_insn "lshrdi3"
1411 [(set (match_operand:DI 0 "register_operand" "=r")
1412 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1413 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1414 ""
1415 "srl %r1,%2,%0"
1416 [(set_attr "type" "shift")])
1418 (define_insn "ashrdi3"
1419 [(set (match_operand:DI 0 "register_operand" "=r")
1420 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1421 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1422 ""
1423 "sra %r1,%2,%0"
1424 [(set_attr "type" "shift")])
1426 (define_expand "extendqihi2"
1427 [(set (match_dup 2)
1428 (ashift:DI (match_operand:QI 1 "some_operand" "")
1429 (const_int 56)))
1430 (set (match_operand:HI 0 "register_operand" "")
1431 (ashiftrt:DI (match_dup 2)
1432 (const_int 56)))]
1433 ""
1434 {
1435 if (TARGET_BWX)
1436 {
1437 emit_insn (gen_extendqihi2x (operands[0],
1438 force_reg (QImode, operands[1])));
1439 DONE;
1440 }
1442 /* If we have an unaligned MEM, extend to DImode (which we do
1443 specially) and then copy to the result. */
1444 if (unaligned_memory_operand (operands[1], HImode))
1445 {
1446 rtx temp = gen_reg_rtx (DImode);
1448 emit_insn (gen_extendqidi2 (temp, operands[1]));
1449 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1450 DONE;
1451 }
1453 operands[0] = gen_lowpart (DImode, operands[0]);
1454 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1455 operands[2] = gen_reg_rtx (DImode);
1456 })
1458 (define_insn "extendqidi2x"
1459 [(set (match_operand:DI 0 "register_operand" "=r")
1460 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1461 "TARGET_BWX"
1462 "sextb %1,%0"
1463 [(set_attr "type" "shift")])
1465 (define_insn "extendhidi2x"
1466 [(set (match_operand:DI 0 "register_operand" "=r")
1467 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1468 "TARGET_BWX"
1469 "sextw %1,%0"
1470 [(set_attr "type" "shift")])
1472 (define_insn "extendqisi2x"
1473 [(set (match_operand:SI 0 "register_operand" "=r")
1474 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1475 "TARGET_BWX"
1476 "sextb %1,%0"
1477 [(set_attr "type" "shift")])
1479 (define_insn "extendhisi2x"
1480 [(set (match_operand:SI 0 "register_operand" "=r")
1481 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1482 "TARGET_BWX"
1483 "sextw %1,%0"
1484 [(set_attr "type" "shift")])
1486 (define_insn "extendqihi2x"
1487 [(set (match_operand:HI 0 "register_operand" "=r")
1488 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1489 "TARGET_BWX"
1490 "sextb %1,%0"
1491 [(set_attr "type" "shift")])
1493 (define_expand "extendqisi2"
1494 [(set (match_dup 2)
1495 (ashift:DI (match_operand:QI 1 "some_operand" "")
1496 (const_int 56)))
1497 (set (match_operand:SI 0 "register_operand" "")
1498 (ashiftrt:DI (match_dup 2)
1499 (const_int 56)))]
1500 ""
1501 {
1502 if (TARGET_BWX)
1503 {
1504 emit_insn (gen_extendqisi2x (operands[0],
1505 force_reg (QImode, operands[1])));
1506 DONE;
1507 }
1509 /* If we have an unaligned MEM, extend to a DImode form of
1510 the result (which we do specially). */
1511 if (unaligned_memory_operand (operands[1], QImode))
1512 {
1513 rtx temp = gen_reg_rtx (DImode);
1515 emit_insn (gen_extendqidi2 (temp, operands[1]));
1516 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1517 DONE;
1518 }
1520 operands[0] = gen_lowpart (DImode, operands[0]);
1521 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1522 operands[2] = gen_reg_rtx (DImode);
1523 })
1525 (define_expand "extendqidi2"
1526 [(set (match_dup 2)
1527 (ashift:DI (match_operand:QI 1 "some_operand" "")
1528 (const_int 56)))
1529 (set (match_operand:DI 0 "register_operand" "")
1530 (ashiftrt:DI (match_dup 2)
1531 (const_int 56)))]
1532 ""
1533 {
1534 if (TARGET_BWX)
1535 {
1536 emit_insn (gen_extendqidi2x (operands[0],
1537 force_reg (QImode, operands[1])));
1538 DONE;
1539 }
1541 if (unaligned_memory_operand (operands[1], QImode))
1542 {
1543 rtx seq
1544 = gen_unaligned_extendqidi (operands[0],
1545 get_unaligned_address (operands[1], 1));
1547 alpha_set_memflags (seq, operands[1]);
1548 emit_insn (seq);
1549 DONE;
1550 }
1552 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1553 operands[2] = gen_reg_rtx (DImode);
1554 })
1556 (define_expand "extendhisi2"
1557 [(set (match_dup 2)
1558 (ashift:DI (match_operand:HI 1 "some_operand" "")
1559 (const_int 48)))
1560 (set (match_operand:SI 0 "register_operand" "")
1561 (ashiftrt:DI (match_dup 2)
1562 (const_int 48)))]
1563 ""
1564 {
1565 if (TARGET_BWX)
1566 {
1567 emit_insn (gen_extendhisi2x (operands[0],
1568 force_reg (HImode, operands[1])));
1569 DONE;
1570 }
1572 /* If we have an unaligned MEM, extend to a DImode form of
1573 the result (which we do specially). */
1574 if (unaligned_memory_operand (operands[1], HImode))
1575 {
1576 rtx temp = gen_reg_rtx (DImode);
1578 emit_insn (gen_extendhidi2 (temp, operands[1]));
1579 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1580 DONE;
1581 }
1583 operands[0] = gen_lowpart (DImode, operands[0]);
1584 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1585 operands[2] = gen_reg_rtx (DImode);
1586 })
1588 (define_expand "extendhidi2"
1589 [(set (match_dup 2)
1590 (ashift:DI (match_operand:HI 1 "some_operand" "")
1591 (const_int 48)))
1592 (set (match_operand:DI 0 "register_operand" "")
1593 (ashiftrt:DI (match_dup 2)
1594 (const_int 48)))]
1595 ""
1596 {
1597 if (TARGET_BWX)
1598 {
1599 emit_insn (gen_extendhidi2x (operands[0],
1600 force_reg (HImode, operands[1])));
1601 DONE;
1602 }
1604 if (unaligned_memory_operand (operands[1], HImode))
1605 {
1606 rtx seq
1607 = gen_unaligned_extendhidi (operands[0],
1608 get_unaligned_address (operands[1], 2));
1610 alpha_set_memflags (seq, operands[1]);
1611 emit_insn (seq);
1612 DONE;
1613 }
1615 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1616 operands[2] = gen_reg_rtx (DImode);
1617 })
1619 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1620 ;; as a pattern saves one instruction. The code is similar to that for
1621 ;; the unaligned loads (see below).
1622 ;;
1623 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1624 (define_expand "unaligned_extendqidi"
1625 [(use (match_operand:QI 0 "register_operand" ""))
1626 (use (match_operand:DI 1 "address_operand" ""))]
1627 ""
1628 {
1629 if (WORDS_BIG_ENDIAN)
1630 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1631 else
1632 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1633 DONE;
1634 })
1636 (define_expand "unaligned_extendqidi_le"
1637 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1638 (set (match_dup 3)
1639 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1640 (const_int -8))))
1641 (set (match_dup 4)
1642 (ashift:DI (match_dup 3)
1643 (minus:DI (const_int 64)
1644 (ashift:DI
1645 (and:DI (match_dup 2) (const_int 7))
1646 (const_int 3)))))
1647 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1648 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1649 "! WORDS_BIG_ENDIAN"
1650 {
1651 operands[2] = gen_reg_rtx (DImode);
1652 operands[3] = gen_reg_rtx (DImode);
1653 operands[4] = gen_reg_rtx (DImode);
1654 })
1656 (define_expand "unaligned_extendqidi_be"
1657 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1658 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1659 (set (match_dup 4)
1660 (mem:DI (and:DI (match_dup 3)
1661 (const_int -8))))
1662 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1663 (set (match_dup 6)
1664 (ashift:DI (match_dup 4)
1665 (ashift:DI
1666 (and:DI
1667 (plus:DI (match_dup 5) (const_int 1))
1668 (const_int 7))
1669 (const_int 3))))
1670 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1671 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1672 "WORDS_BIG_ENDIAN"
1673 {
1674 operands[2] = gen_reg_rtx (DImode);
1675 operands[3] = gen_reg_rtx (DImode);
1676 operands[4] = gen_reg_rtx (DImode);
1677 operands[5] = gen_reg_rtx (DImode);
1678 operands[6] = gen_reg_rtx (DImode);
1679 })
1681 (define_expand "unaligned_extendhidi"
1682 [(use (match_operand:QI 0 "register_operand" ""))
1683 (use (match_operand:DI 1 "address_operand" ""))]
1684 ""
1685 {
1686 operands[0] = gen_lowpart (DImode, operands[0]);
1687 emit_insn ((WORDS_BIG_ENDIAN
1688 ? gen_unaligned_extendhidi_be
1689 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1690 DONE;
1691 })
1693 (define_expand "unaligned_extendhidi_le"
1694 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1695 (set (match_dup 3)
1696 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1697 (const_int -8))))
1698 (set (match_dup 4)
1699 (ashift:DI (match_dup 3)
1700 (minus:DI (const_int 64)
1701 (ashift:DI
1702 (and:DI (match_dup 2) (const_int 7))
1703 (const_int 3)))))
1704 (set (match_operand:DI 0 "register_operand" "")
1705 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1706 "! WORDS_BIG_ENDIAN"
1707 {
1708 operands[2] = gen_reg_rtx (DImode);
1709 operands[3] = gen_reg_rtx (DImode);
1710 operands[4] = gen_reg_rtx (DImode);
1711 })
1713 (define_expand "unaligned_extendhidi_be"
1714 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1715 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1716 (set (match_dup 4)
1717 (mem:DI (and:DI (match_dup 3)
1718 (const_int -8))))
1719 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1720 (set (match_dup 6)
1721 (ashift:DI (match_dup 4)
1722 (ashift:DI
1723 (and:DI
1724 (plus:DI (match_dup 5) (const_int 1))
1725 (const_int 7))
1726 (const_int 3))))
1727 (set (match_operand:DI 0 "register_operand" "")
1728 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1729 "WORDS_BIG_ENDIAN"
1730 {
1731 operands[2] = gen_reg_rtx (DImode);
1732 operands[3] = gen_reg_rtx (DImode);
1733 operands[4] = gen_reg_rtx (DImode);
1734 operands[5] = gen_reg_rtx (DImode);
1735 operands[6] = gen_reg_rtx (DImode);
1736 })
1738 (define_insn "*extxl_const"
1739 [(set (match_operand:DI 0 "register_operand" "=r")
1740 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1741 (match_operand:DI 2 "mode_width_operand" "n")
1742 (match_operand:DI 3 "mul8_operand" "I")))]
1743 ""
1744 "ext%M2l %r1,%s3,%0"
1745 [(set_attr "type" "shift")])
1747 (define_insn "extxl_le"
1748 [(set (match_operand:DI 0 "register_operand" "=r")
1749 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1750 (match_operand:DI 2 "mode_width_operand" "n")
1751 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1752 (const_int 3))))]
1753 "! WORDS_BIG_ENDIAN"
1754 "ext%M2l %r1,%3,%0"
1755 [(set_attr "type" "shift")])
1757 (define_insn "extxl_be"
1758 [(set (match_operand:DI 0 "register_operand" "=r")
1759 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1760 (match_operand:DI 2 "mode_width_operand" "n")
1761 (minus:DI
1762 (const_int 56)
1763 (ashift:DI
1764 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1765 (const_int 3)))))]
1766 "WORDS_BIG_ENDIAN"
1767 "ext%M2l %r1,%3,%0"
1768 [(set_attr "type" "shift")])
1770 ;; Combine has some strange notion of preserving existing undefined behavior
1771 ;; in shifts larger than a word size. So capture these patterns that it
1772 ;; should have turned into zero_extracts.
1774 (define_insn "*extxl_1_le"
1775 [(set (match_operand:DI 0 "register_operand" "=r")
1776 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1777 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1778 (const_int 3)))
1779 (match_operand:DI 3 "mode_mask_operand" "n")))]
1780 "! WORDS_BIG_ENDIAN"
1781 "ext%U3l %1,%2,%0"
1782 [(set_attr "type" "shift")])
1784 (define_insn "*extxl_1_be"
1785 [(set (match_operand:DI 0 "register_operand" "=r")
1786 (and:DI (lshiftrt:DI
1787 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1788 (minus:DI (const_int 56)
1789 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1790 (const_int 3))))
1791 (match_operand:DI 3 "mode_mask_operand" "n")))]
1792 "WORDS_BIG_ENDIAN"
1793 "ext%U3l %1,%2,%0"
1794 [(set_attr "type" "shift")])
1796 (define_insn "*extql_2_le"
1797 [(set (match_operand:DI 0 "register_operand" "=r")
1798 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1799 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1800 (const_int 3))))]
1801 "! WORDS_BIG_ENDIAN"
1802 "extql %1,%2,%0"
1803 [(set_attr "type" "shift")])
1805 (define_insn "*extql_2_be"
1806 [(set (match_operand:DI 0 "register_operand" "=r")
1807 (lshiftrt:DI
1808 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1809 (minus:DI (const_int 56)
1810 (ashift:DI
1811 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1812 (const_int 3)))))]
1813 "WORDS_BIG_ENDIAN"
1814 "extql %1,%2,%0"
1815 [(set_attr "type" "shift")])
1817 (define_insn "extqh_le"
1818 [(set (match_operand:DI 0 "register_operand" "=r")
1819 (ashift:DI
1820 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1821 (minus:DI (const_int 64)
1822 (ashift:DI
1823 (and:DI
1824 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1825 (const_int 7))
1826 (const_int 3)))))]
1827 "! WORDS_BIG_ENDIAN"
1828 "extqh %r1,%2,%0"
1829 [(set_attr "type" "shift")])
1831 (define_insn "extqh_be"
1832 [(set (match_operand:DI 0 "register_operand" "=r")
1833 (ashift:DI
1834 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1835 (ashift:DI
1836 (and:DI
1837 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1838 (const_int 1))
1839 (const_int 7))
1840 (const_int 3))))]
1841 "WORDS_BIG_ENDIAN"
1842 "extqh %r1,%2,%0"
1843 [(set_attr "type" "shift")])
1845 (define_insn "extlh_le"
1846 [(set (match_operand:DI 0 "register_operand" "=r")
1847 (ashift:DI
1848 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1849 (const_int 2147483647))
1850 (minus:DI (const_int 64)
1851 (ashift:DI
1852 (and:DI
1853 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1854 (const_int 7))
1855 (const_int 3)))))]
1856 "! WORDS_BIG_ENDIAN"
1857 "extlh %r1,%2,%0"
1858 [(set_attr "type" "shift")])
1860 (define_insn "extlh_be"
1861 [(set (match_operand:DI 0 "register_operand" "=r")
1862 (and:DI
1863 (ashift:DI
1864 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1865 (ashift:DI
1866 (and:DI
1867 (plus:DI
1868 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1869 (const_int 1))
1870 (const_int 7))
1871 (const_int 3)))
1872 (const_int 2147483647)))]
1873 "WORDS_BIG_ENDIAN"
1874 "extlh %r1,%2,%0"
1875 [(set_attr "type" "shift")])
1877 (define_insn "extwh_le"
1878 [(set (match_operand:DI 0 "register_operand" "=r")
1879 (ashift:DI
1880 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1881 (const_int 65535))
1882 (minus:DI (const_int 64)
1883 (ashift:DI
1884 (and:DI
1885 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1886 (const_int 7))
1887 (const_int 3)))))]
1888 "! WORDS_BIG_ENDIAN"
1889 "extwh %r1,%2,%0"
1890 [(set_attr "type" "shift")])
1892 (define_insn "extwh_be"
1893 [(set (match_operand:DI 0 "register_operand" "=r")
1894 (and:DI
1895 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1896 (ashift:DI
1897 (and:DI
1898 (plus:DI
1899 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1900 (const_int 1))
1901 (const_int 7))
1902 (const_int 3)))
1903 (const_int 65535)))]
1904 "WORDS_BIG_ENDIAN"
1905 "extwh %r1,%2,%0"
1906 [(set_attr "type" "shift")])
1908 ;; This converts an extXl into an extXh with an appropriate adjustment
1909 ;; to the address calculation.
1911 ;;(define_split
1912 ;; [(set (match_operand:DI 0 "register_operand" "")
1913 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1914 ;; (match_operand:DI 2 "mode_width_operand" "")
1915 ;; (ashift:DI (match_operand:DI 3 "" "")
1916 ;; (const_int 3)))
1917 ;; (match_operand:DI 4 "const_int_operand" "")))
1918 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1919 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1920 ;; [(set (match_dup 5) (match_dup 6))
1921 ;; (set (match_dup 0)
1922 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1923 ;; (ashift:DI (plus:DI (match_dup 5)
1924 ;; (match_dup 7))
1925 ;; (const_int 3)))
1926 ;; (match_dup 4)))]
1927 ;; "
1928 ;;{
1929 ;; operands[6] = plus_constant (operands[3],
1930 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1931 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1932 ;;}")
1934 (define_insn "*insbl_const"
1935 [(set (match_operand:DI 0 "register_operand" "=r")
1936 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1937 (match_operand:DI 2 "mul8_operand" "I")))]
1938 ""
1939 "insbl %1,%s2,%0"
1940 [(set_attr "type" "shift")])
1942 (define_insn "*inswl_const"
1943 [(set (match_operand:DI 0 "register_operand" "=r")
1944 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1945 (match_operand:DI 2 "mul8_operand" "I")))]
1946 ""
1947 "inswl %1,%s2,%0"
1948 [(set_attr "type" "shift")])
1950 (define_insn "*insll_const"
1951 [(set (match_operand:DI 0 "register_operand" "=r")
1952 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1953 (match_operand:DI 2 "mul8_operand" "I")))]
1954 ""
1955 "insll %1,%s2,%0"
1956 [(set_attr "type" "shift")])
1958 (define_insn "insbl_le"
1959 [(set (match_operand:DI 0 "register_operand" "=r")
1960 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1961 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1962 (const_int 3))))]
1963 "! WORDS_BIG_ENDIAN"
1964 "insbl %1,%2,%0"
1965 [(set_attr "type" "shift")])
1967 (define_insn "insbl_be"
1968 [(set (match_operand:DI 0 "register_operand" "=r")
1969 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1970 (minus:DI (const_int 56)
1971 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1972 (const_int 3)))))]
1973 "WORDS_BIG_ENDIAN"
1974 "insbl %1,%2,%0"
1975 [(set_attr "type" "shift")])
1977 (define_insn "inswl_le"
1978 [(set (match_operand:DI 0 "register_operand" "=r")
1979 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1980 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1981 (const_int 3))))]
1982 "! WORDS_BIG_ENDIAN"
1983 "inswl %1,%2,%0"
1984 [(set_attr "type" "shift")])
1986 (define_insn "inswl_be"
1987 [(set (match_operand:DI 0 "register_operand" "=r")
1988 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1989 (minus:DI (const_int 56)
1990 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1991 (const_int 3)))))]
1992 "WORDS_BIG_ENDIAN"
1993 "inswl %1,%2,%0"
1994 [(set_attr "type" "shift")])
1996 (define_insn "insll_le"
1997 [(set (match_operand:DI 0 "register_operand" "=r")
1998 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1999 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2000 (const_int 3))))]
2001 "! WORDS_BIG_ENDIAN"
2002 "insll %1,%2,%0"
2003 [(set_attr "type" "shift")])
2005 (define_insn "insll_be"
2006 [(set (match_operand:DI 0 "register_operand" "=r")
2007 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2008 (minus:DI (const_int 56)
2009 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2010 (const_int 3)))))]
2011 "WORDS_BIG_ENDIAN"
2012 "insll %1,%2,%0"
2013 [(set_attr "type" "shift")])
2015 (define_insn "insql_le"
2016 [(set (match_operand:DI 0 "register_operand" "=r")
2017 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2018 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2019 (const_int 3))))]
2020 "! WORDS_BIG_ENDIAN"
2021 "insql %1,%2,%0"
2022 [(set_attr "type" "shift")])
2024 (define_insn "insql_be"
2025 [(set (match_operand:DI 0 "register_operand" "=r")
2026 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2027 (minus:DI (const_int 56)
2028 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2029 (const_int 3)))))]
2030 "WORDS_BIG_ENDIAN"
2031 "insql %1,%2,%0"
2032 [(set_attr "type" "shift")])
2034 ;; Combine has this sometimes habit of moving the and outside of the
2035 ;; shift, making life more interesting.
2037 (define_insn "*insxl"
2038 [(set (match_operand:DI 0 "register_operand" "=r")
2039 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2040 (match_operand:DI 2 "mul8_operand" "I"))
2041 (match_operand:DI 3 "immediate_operand" "i")))]
2042 "HOST_BITS_PER_WIDE_INT == 64
2043 && GET_CODE (operands[3]) == CONST_INT
2044 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2045 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2046 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2047 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2048 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2049 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2050 {
2051 #if HOST_BITS_PER_WIDE_INT == 64
2052 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2053 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2054 return "insbl %1,%s2,%0";
2055 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2056 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2057 return "inswl %1,%s2,%0";
2058 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2059 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2060 return "insll %1,%s2,%0";
2061 #endif
2062 abort();
2063 }
2064 [(set_attr "type" "shift")])
2066 ;; We do not include the insXh insns because they are complex to express
2067 ;; and it does not appear that we would ever want to generate them.
2068 ;;
2069 ;; Since we need them for block moves, though, cop out and use unspec.
2071 (define_insn "insxh"
2072 [(set (match_operand:DI 0 "register_operand" "=r")
2073 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2074 (match_operand:DI 2 "mode_width_operand" "n")
2075 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2076 UNSPEC_INSXH))]
2077 ""
2078 "ins%M2h %1,%3,%0"
2079 [(set_attr "type" "shift")])
2081 (define_insn "mskxl_le"
2082 [(set (match_operand:DI 0 "register_operand" "=r")
2083 (and:DI (not:DI (ashift:DI
2084 (match_operand:DI 2 "mode_mask_operand" "n")
2085 (ashift:DI
2086 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2087 (const_int 3))))
2088 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2089 "! WORDS_BIG_ENDIAN"
2090 "msk%U2l %r1,%3,%0"
2091 [(set_attr "type" "shift")])
2093 (define_insn "mskxl_be"
2094 [(set (match_operand:DI 0 "register_operand" "=r")
2095 (and:DI (not:DI (ashift:DI
2096 (match_operand:DI 2 "mode_mask_operand" "n")
2097 (minus:DI (const_int 56)
2098 (ashift:DI
2099 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2100 (const_int 3)))))
2101 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2102 "WORDS_BIG_ENDIAN"
2103 "msk%U2l %r1,%3,%0"
2104 [(set_attr "type" "shift")])
2106 ;; We do not include the mskXh insns because it does not appear we would
2107 ;; ever generate one.
2108 ;;
2109 ;; Again, we do for block moves and we use unspec again.
2111 (define_insn "mskxh"
2112 [(set (match_operand:DI 0 "register_operand" "=r")
2113 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2114 (match_operand:DI 2 "mode_width_operand" "n")
2115 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2116 UNSPEC_MSKXH))]
2117 ""
2118 "msk%M2h %1,%3,%0"
2119 [(set_attr "type" "shift")])
2121 ;; Prefer AND + NE over LSHIFTRT + AND.
2123 (define_insn_and_split "*ze_and_ne"
2124 [(set (match_operand:DI 0 "register_operand" "=r")
2125 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2126 (const_int 1)
2127 (match_operand 2 "const_int_operand" "I")))]
2128 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2129 "#"
2130 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2131 [(set (match_dup 0)
2132 (and:DI (match_dup 1) (match_dup 3)))
2133 (set (match_dup 0)
2134 (ne:DI (match_dup 0) (const_int 0)))]
2135 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2136 \f
2137 ;; Floating-point operations. All the double-precision insns can extend
2138 ;; from single, so indicate that. The exception are the ones that simply
2139 ;; play with the sign bits; it's not clear what to do there.
2141 (define_insn "abssf2"
2142 [(set (match_operand:SF 0 "register_operand" "=f")
2143 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2144 "TARGET_FP"
2145 "cpys $f31,%R1,%0"
2146 [(set_attr "type" "fcpys")])
2148 (define_insn "*nabssf2"
2149 [(set (match_operand:SF 0 "register_operand" "=f")
2150 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2151 "TARGET_FP"
2152 "cpysn $f31,%R1,%0"
2153 [(set_attr "type" "fadd")])
2155 (define_insn "absdf2"
2156 [(set (match_operand:DF 0 "register_operand" "=f")
2157 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2158 "TARGET_FP"
2159 "cpys $f31,%R1,%0"
2160 [(set_attr "type" "fcpys")])
2162 (define_insn "*nabsdf2"
2163 [(set (match_operand:DF 0 "register_operand" "=f")
2164 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2165 "TARGET_FP"
2166 "cpysn $f31,%R1,%0"
2167 [(set_attr "type" "fadd")])
2169 (define_expand "abstf2"
2170 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2171 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2172 (use (match_dup 2))])]
2173 "TARGET_HAS_XFLOATING_LIBS"
2174 {
2175 #if HOST_BITS_PER_WIDE_INT >= 64
2176 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2177 #else
2178 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2179 #endif
2180 })
2182 (define_insn_and_split "*abstf_internal"
2183 [(set (match_operand:TF 0 "register_operand" "=r")
2184 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2185 (use (match_operand:DI 2 "register_operand" "r"))]
2186 "TARGET_HAS_XFLOATING_LIBS"
2187 "#"
2188 "&& reload_completed"
2189 [(const_int 0)]
2190 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2192 (define_insn "negsf2"
2193 [(set (match_operand:SF 0 "register_operand" "=f")
2194 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2195 "TARGET_FP"
2196 "cpysn %R1,%R1,%0"
2197 [(set_attr "type" "fadd")])
2199 (define_insn "negdf2"
2200 [(set (match_operand:DF 0 "register_operand" "=f")
2201 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2202 "TARGET_FP"
2203 "cpysn %R1,%R1,%0"
2204 [(set_attr "type" "fadd")])
2206 (define_expand "negtf2"
2207 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2208 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2209 (use (match_dup 2))])]
2210 "TARGET_HAS_XFLOATING_LIBS"
2211 {
2212 #if HOST_BITS_PER_WIDE_INT >= 64
2213 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2214 #else
2215 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2216 #endif
2217 })
2219 (define_insn_and_split "*negtf_internal"
2220 [(set (match_operand:TF 0 "register_operand" "=r")
2221 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2222 (use (match_operand:DI 2 "register_operand" "r"))]
2223 "TARGET_HAS_XFLOATING_LIBS"
2224 "#"
2225 "&& reload_completed"
2226 [(const_int 0)]
2227 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2229 (define_insn "*addsf_ieee"
2230 [(set (match_operand:SF 0 "register_operand" "=&f")
2231 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2232 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2233 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2234 "add%,%/ %R1,%R2,%0"
2235 [(set_attr "type" "fadd")
2236 (set_attr "trap" "yes")
2237 (set_attr "round_suffix" "normal")
2238 (set_attr "trap_suffix" "u_su_sui")])
2240 (define_insn "addsf3"
2241 [(set (match_operand:SF 0 "register_operand" "=f")
2242 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2243 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2244 "TARGET_FP"
2245 "add%,%/ %R1,%R2,%0"
2246 [(set_attr "type" "fadd")
2247 (set_attr "trap" "yes")
2248 (set_attr "round_suffix" "normal")
2249 (set_attr "trap_suffix" "u_su_sui")])
2251 (define_insn "*adddf_ieee"
2252 [(set (match_operand:DF 0 "register_operand" "=&f")
2253 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2254 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2255 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2256 "add%-%/ %R1,%R2,%0"
2257 [(set_attr "type" "fadd")
2258 (set_attr "trap" "yes")
2259 (set_attr "round_suffix" "normal")
2260 (set_attr "trap_suffix" "u_su_sui")])
2262 (define_insn "adddf3"
2263 [(set (match_operand:DF 0 "register_operand" "=f")
2264 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2265 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2266 "TARGET_FP"
2267 "add%-%/ %R1,%R2,%0"
2268 [(set_attr "type" "fadd")
2269 (set_attr "trap" "yes")
2270 (set_attr "round_suffix" "normal")
2271 (set_attr "trap_suffix" "u_su_sui")])
2273 (define_insn "*adddf_ext1"
2274 [(set (match_operand:DF 0 "register_operand" "=f")
2275 (plus:DF (float_extend:DF
2276 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2277 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2278 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2279 "add%-%/ %R1,%R2,%0"
2280 [(set_attr "type" "fadd")
2281 (set_attr "trap" "yes")
2282 (set_attr "round_suffix" "normal")
2283 (set_attr "trap_suffix" "u_su_sui")])
2285 (define_insn "*adddf_ext2"
2286 [(set (match_operand:DF 0 "register_operand" "=f")
2287 (plus:DF (float_extend:DF
2288 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2289 (float_extend:DF
2290 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2291 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2292 "add%-%/ %R1,%R2,%0"
2293 [(set_attr "type" "fadd")
2294 (set_attr "trap" "yes")
2295 (set_attr "round_suffix" "normal")
2296 (set_attr "trap_suffix" "u_su_sui")])
2298 (define_expand "addtf3"
2299 [(use (match_operand 0 "register_operand" ""))
2300 (use (match_operand 1 "general_operand" ""))
2301 (use (match_operand 2 "general_operand" ""))]
2302 "TARGET_HAS_XFLOATING_LIBS"
2303 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2305 ;; Define conversion operators between DFmode and SImode, using the cvtql
2306 ;; instruction. To allow combine et al to do useful things, we keep the
2307 ;; operation as a unit until after reload, at which point we split the
2308 ;; instructions.
2309 ;;
2310 ;; Note that we (attempt to) only consider this optimization when the
2311 ;; ultimate destination is memory. If we will be doing further integer
2312 ;; processing, it is cheaper to do the truncation in the int regs.
2314 (define_insn "*cvtql"
2315 [(set (match_operand:SI 0 "register_operand" "=f")
2316 (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2317 UNSPEC_CVTQL))]
2318 "TARGET_FP"
2319 "cvtql%/ %R1,%0"
2320 [(set_attr "type" "fadd")
2321 (set_attr "trap" "yes")
2322 (set_attr "trap_suffix" "v_sv")])
2324 (define_insn_and_split "*fix_truncdfsi_ieee"
2325 [(set (match_operand:SI 0 "memory_operand" "=m")
2326 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2327 (clobber (match_scratch:DI 2 "=&f"))
2328 (clobber (match_scratch:SI 3 "=&f"))]
2329 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2330 "#"
2331 "&& reload_completed"
2332 [(set (match_dup 2) (fix:DI (match_dup 1)))
2333 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2334 (set (match_dup 0) (match_dup 3))]
2335 ""
2336 [(set_attr "type" "fadd")
2337 (set_attr "trap" "yes")])
2339 (define_insn_and_split "*fix_truncdfsi_internal"
2340 [(set (match_operand:SI 0 "memory_operand" "=m")
2341 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2342 (clobber (match_scratch:DI 2 "=f"))]
2343 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2344 "#"
2345 "&& reload_completed"
2346 [(set (match_dup 2) (fix:DI (match_dup 1)))
2347 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2348 (set (match_dup 0) (match_dup 3))]
2349 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2350 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2351 [(set_attr "type" "fadd")
2352 (set_attr "trap" "yes")])
2354 (define_insn "*fix_truncdfdi_ieee"
2355 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2356 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2357 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2358 "cvt%-q%/ %R1,%0"
2359 [(set_attr "type" "fadd")
2360 (set_attr "trap" "yes")
2361 (set_attr "round_suffix" "c")
2362 (set_attr "trap_suffix" "v_sv_svi")])
2364 (define_insn "fix_truncdfdi2"
2365 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2366 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2367 "TARGET_FP"
2368 "cvt%-q%/ %R1,%0"
2369 [(set_attr "type" "fadd")
2370 (set_attr "trap" "yes")
2371 (set_attr "round_suffix" "c")
2372 (set_attr "trap_suffix" "v_sv_svi")])
2374 ;; Likewise between SFmode and SImode.
2376 (define_insn_and_split "*fix_truncsfsi_ieee"
2377 [(set (match_operand:SI 0 "memory_operand" "=m")
2378 (subreg:SI (fix:DI (float_extend:DF
2379 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2380 (clobber (match_scratch:DI 2 "=&f"))
2381 (clobber (match_scratch:SI 3 "=&f"))]
2382 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2383 "#"
2384 "&& reload_completed"
2385 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2386 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2387 (set (match_dup 0) (match_dup 3))]
2388 ""
2389 [(set_attr "type" "fadd")
2390 (set_attr "trap" "yes")])
2392 (define_insn_and_split "*fix_truncsfsi_internal"
2393 [(set (match_operand:SI 0 "memory_operand" "=m")
2394 (subreg:SI (fix:DI (float_extend:DF
2395 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2396 (clobber (match_scratch:DI 2 "=f"))]
2397 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2398 "#"
2399 "&& reload_completed"
2400 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2401 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2402 (set (match_dup 0) (match_dup 3))]
2403 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2404 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2405 [(set_attr "type" "fadd")
2406 (set_attr "trap" "yes")])
2408 (define_insn "*fix_truncsfdi_ieee"
2409 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2410 (fix:DI (float_extend:DF
2411 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2412 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2413 "cvt%-q%/ %R1,%0"
2414 [(set_attr "type" "fadd")
2415 (set_attr "trap" "yes")
2416 (set_attr "round_suffix" "c")
2417 (set_attr "trap_suffix" "v_sv_svi")])
2419 (define_insn "fix_truncsfdi2"
2420 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2421 (fix:DI (float_extend:DF
2422 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2423 "TARGET_FP"
2424 "cvt%-q%/ %R1,%0"
2425 [(set_attr "type" "fadd")
2426 (set_attr "trap" "yes")
2427 (set_attr "round_suffix" "c")
2428 (set_attr "trap_suffix" "v_sv_svi")])
2430 (define_expand "fix_trunctfdi2"
2431 [(use (match_operand:DI 0 "register_operand" ""))
2432 (use (match_operand:TF 1 "general_operand" ""))]
2433 "TARGET_HAS_XFLOATING_LIBS"
2434 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2436 (define_insn "*floatdisf_ieee"
2437 [(set (match_operand:SF 0 "register_operand" "=&f")
2438 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2439 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2440 "cvtq%,%/ %1,%0"
2441 [(set_attr "type" "fadd")
2442 (set_attr "trap" "yes")
2443 (set_attr "round_suffix" "normal")
2444 (set_attr "trap_suffix" "sui")])
2446 (define_insn "floatdisf2"
2447 [(set (match_operand:SF 0 "register_operand" "=f")
2448 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2449 "TARGET_FP"
2450 "cvtq%,%/ %1,%0"
2451 [(set_attr "type" "fadd")
2452 (set_attr "trap" "yes")
2453 (set_attr "round_suffix" "normal")
2454 (set_attr "trap_suffix" "sui")])
2456 (define_insn "*floatdidf_ieee"
2457 [(set (match_operand:DF 0 "register_operand" "=&f")
2458 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2459 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2460 "cvtq%-%/ %1,%0"
2461 [(set_attr "type" "fadd")
2462 (set_attr "trap" "yes")
2463 (set_attr "round_suffix" "normal")
2464 (set_attr "trap_suffix" "sui")])
2466 (define_insn "floatdidf2"
2467 [(set (match_operand:DF 0 "register_operand" "=f")
2468 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2469 "TARGET_FP"
2470 "cvtq%-%/ %1,%0"
2471 [(set_attr "type" "fadd")
2472 (set_attr "trap" "yes")
2473 (set_attr "round_suffix" "normal")
2474 (set_attr "trap_suffix" "sui")])
2476 (define_expand "floatditf2"
2477 [(use (match_operand:TF 0 "register_operand" ""))
2478 (use (match_operand:DI 1 "general_operand" ""))]
2479 "TARGET_HAS_XFLOATING_LIBS"
2480 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2482 (define_expand "floatunsdisf2"
2483 [(use (match_operand:SF 0 "register_operand" ""))
2484 (use (match_operand:DI 1 "register_operand" ""))]
2485 "TARGET_FP"
2486 "alpha_emit_floatuns (operands); DONE;")
2488 (define_expand "floatunsdidf2"
2489 [(use (match_operand:DF 0 "register_operand" ""))
2490 (use (match_operand:DI 1 "register_operand" ""))]
2491 "TARGET_FP"
2492 "alpha_emit_floatuns (operands); DONE;")
2494 (define_expand "floatunsditf2"
2495 [(use (match_operand:TF 0 "register_operand" ""))
2496 (use (match_operand:DI 1 "general_operand" ""))]
2497 "TARGET_HAS_XFLOATING_LIBS"
2498 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2500 (define_expand "extendsfdf2"
2501 [(set (match_operand:DF 0 "register_operand" "")
2502 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2503 "TARGET_FP"
2504 {
2505 if (alpha_fptm >= ALPHA_FPTM_SU)
2506 operands[1] = force_reg (SFmode, operands[1]);
2507 })
2509 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2510 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2512 (define_insn "*extendsfdf2_ieee"
2513 [(set (match_operand:DF 0 "register_operand" "=&f")
2514 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2515 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2516 "cvtsts %1,%0"
2517 [(set_attr "type" "fadd")
2518 (set_attr "trap" "yes")])
2520 (define_insn "*extendsfdf2_internal"
2521 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2522 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2523 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2524 "@
2525 cpys %1,%1,%0
2526 ld%, %0,%1
2527 st%- %1,%0"
2528 [(set_attr "type" "fcpys,fld,fst")])
2530 (define_expand "extendsftf2"
2531 [(use (match_operand:TF 0 "register_operand" ""))
2532 (use (match_operand:SF 1 "general_operand" ""))]
2533 "TARGET_HAS_XFLOATING_LIBS"
2534 {
2535 rtx tmp = gen_reg_rtx (DFmode);
2536 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2537 emit_insn (gen_extenddftf2 (operands[0], tmp));
2538 DONE;
2539 })
2541 (define_expand "extenddftf2"
2542 [(use (match_operand:TF 0 "register_operand" ""))
2543 (use (match_operand:DF 1 "general_operand" ""))]
2544 "TARGET_HAS_XFLOATING_LIBS"
2545 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2547 (define_insn "*truncdfsf2_ieee"
2548 [(set (match_operand:SF 0 "register_operand" "=&f")
2549 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2550 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2551 "cvt%-%,%/ %R1,%0"
2552 [(set_attr "type" "fadd")
2553 (set_attr "trap" "yes")
2554 (set_attr "round_suffix" "normal")
2555 (set_attr "trap_suffix" "u_su_sui")])
2557 (define_insn "truncdfsf2"
2558 [(set (match_operand:SF 0 "register_operand" "=f")
2559 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2560 "TARGET_FP"
2561 "cvt%-%,%/ %R1,%0"
2562 [(set_attr "type" "fadd")
2563 (set_attr "trap" "yes")
2564 (set_attr "round_suffix" "normal")
2565 (set_attr "trap_suffix" "u_su_sui")])
2567 (define_expand "trunctfdf2"
2568 [(use (match_operand:DF 0 "register_operand" ""))
2569 (use (match_operand:TF 1 "general_operand" ""))]
2570 "TARGET_HAS_XFLOATING_LIBS"
2571 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2573 (define_expand "trunctfsf2"
2574 [(use (match_operand:SF 0 "register_operand" ""))
2575 (use (match_operand:TF 1 "general_operand" ""))]
2576 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2577 {
2578 rtx tmpf, sticky, arg, lo, hi;
2580 tmpf = gen_reg_rtx (DFmode);
2581 sticky = gen_reg_rtx (DImode);
2582 arg = copy_to_mode_reg (TFmode, operands[1]);
2583 lo = gen_lowpart (DImode, arg);
2584 hi = gen_highpart (DImode, arg);
2586 /* Convert the low word of the TFmode value into a sticky rounding bit,
2587 then or it into the low bit of the high word. This leaves the sticky
2588 bit at bit 48 of the fraction, which is representable in DFmode,
2589 which prevents rounding error in the final conversion to SFmode. */
2591 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2592 gen_rtx_NE (DImode, lo, const0_rtx)));
2593 emit_insn (gen_iordi3 (hi, hi, sticky));
2594 emit_insn (gen_trunctfdf2 (tmpf, arg));
2595 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2596 DONE;
2597 })
2599 (define_insn "*divsf3_ieee"
2600 [(set (match_operand:SF 0 "register_operand" "=&f")
2601 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2602 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2603 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2604 "div%,%/ %R1,%R2,%0"
2605 [(set_attr "type" "fdiv")
2606 (set_attr "opsize" "si")
2607 (set_attr "trap" "yes")
2608 (set_attr "round_suffix" "normal")
2609 (set_attr "trap_suffix" "u_su_sui")])
2611 (define_insn "divsf3"
2612 [(set (match_operand:SF 0 "register_operand" "=f")
2613 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2614 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2615 "TARGET_FP"
2616 "div%,%/ %R1,%R2,%0"
2617 [(set_attr "type" "fdiv")
2618 (set_attr "opsize" "si")
2619 (set_attr "trap" "yes")
2620 (set_attr "round_suffix" "normal")
2621 (set_attr "trap_suffix" "u_su_sui")])
2623 (define_insn "*divdf3_ieee"
2624 [(set (match_operand:DF 0 "register_operand" "=&f")
2625 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2626 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2627 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2628 "div%-%/ %R1,%R2,%0"
2629 [(set_attr "type" "fdiv")
2630 (set_attr "trap" "yes")
2631 (set_attr "round_suffix" "normal")
2632 (set_attr "trap_suffix" "u_su_sui")])
2634 (define_insn "divdf3"
2635 [(set (match_operand:DF 0 "register_operand" "=f")
2636 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2637 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2638 "TARGET_FP"
2639 "div%-%/ %R1,%R2,%0"
2640 [(set_attr "type" "fdiv")
2641 (set_attr "trap" "yes")
2642 (set_attr "round_suffix" "normal")
2643 (set_attr "trap_suffix" "u_su_sui")])
2645 (define_insn "*divdf_ext1"
2646 [(set (match_operand:DF 0 "register_operand" "=f")
2647 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2648 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2649 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2650 "div%-%/ %R1,%R2,%0"
2651 [(set_attr "type" "fdiv")
2652 (set_attr "trap" "yes")
2653 (set_attr "round_suffix" "normal")
2654 (set_attr "trap_suffix" "u_su_sui")])
2656 (define_insn "*divdf_ext2"
2657 [(set (match_operand:DF 0 "register_operand" "=f")
2658 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2659 (float_extend:DF
2660 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2661 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2662 "div%-%/ %R1,%R2,%0"
2663 [(set_attr "type" "fdiv")
2664 (set_attr "trap" "yes")
2665 (set_attr "round_suffix" "normal")
2666 (set_attr "trap_suffix" "u_su_sui")])
2668 (define_insn "*divdf_ext3"
2669 [(set (match_operand:DF 0 "register_operand" "=f")
2670 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2671 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2672 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2673 "div%-%/ %R1,%R2,%0"
2674 [(set_attr "type" "fdiv")
2675 (set_attr "trap" "yes")
2676 (set_attr "round_suffix" "normal")
2677 (set_attr "trap_suffix" "u_su_sui")])
2679 (define_expand "divtf3"
2680 [(use (match_operand 0 "register_operand" ""))
2681 (use (match_operand 1 "general_operand" ""))
2682 (use (match_operand 2 "general_operand" ""))]
2683 "TARGET_HAS_XFLOATING_LIBS"
2684 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2686 (define_insn "*mulsf3_ieee"
2687 [(set (match_operand:SF 0 "register_operand" "=&f")
2688 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2689 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2690 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2691 "mul%,%/ %R1,%R2,%0"
2692 [(set_attr "type" "fmul")
2693 (set_attr "trap" "yes")
2694 (set_attr "round_suffix" "normal")
2695 (set_attr "trap_suffix" "u_su_sui")])
2697 (define_insn "mulsf3"
2698 [(set (match_operand:SF 0 "register_operand" "=f")
2699 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2700 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2701 "TARGET_FP"
2702 "mul%,%/ %R1,%R2,%0"
2703 [(set_attr "type" "fmul")
2704 (set_attr "trap" "yes")
2705 (set_attr "round_suffix" "normal")
2706 (set_attr "trap_suffix" "u_su_sui")])
2708 (define_insn "*muldf3_ieee"
2709 [(set (match_operand:DF 0 "register_operand" "=&f")
2710 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2711 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2712 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2713 "mul%-%/ %R1,%R2,%0"
2714 [(set_attr "type" "fmul")
2715 (set_attr "trap" "yes")
2716 (set_attr "round_suffix" "normal")
2717 (set_attr "trap_suffix" "u_su_sui")])
2719 (define_insn "muldf3"
2720 [(set (match_operand:DF 0 "register_operand" "=f")
2721 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2722 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2723 "TARGET_FP"
2724 "mul%-%/ %R1,%R2,%0"
2725 [(set_attr "type" "fmul")
2726 (set_attr "trap" "yes")
2727 (set_attr "round_suffix" "normal")
2728 (set_attr "trap_suffix" "u_su_sui")])
2730 (define_insn "*muldf_ext1"
2731 [(set (match_operand:DF 0 "register_operand" "=f")
2732 (mult:DF (float_extend:DF
2733 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2734 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2735 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2736 "mul%-%/ %R1,%R2,%0"
2737 [(set_attr "type" "fmul")
2738 (set_attr "trap" "yes")
2739 (set_attr "round_suffix" "normal")
2740 (set_attr "trap_suffix" "u_su_sui")])
2742 (define_insn "*muldf_ext2"
2743 [(set (match_operand:DF 0 "register_operand" "=f")
2744 (mult:DF (float_extend:DF
2745 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2746 (float_extend:DF
2747 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2748 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2749 "mul%-%/ %R1,%R2,%0"
2750 [(set_attr "type" "fmul")
2751 (set_attr "trap" "yes")
2752 (set_attr "round_suffix" "normal")
2753 (set_attr "trap_suffix" "u_su_sui")])
2755 (define_expand "multf3"
2756 [(use (match_operand 0 "register_operand" ""))
2757 (use (match_operand 1 "general_operand" ""))
2758 (use (match_operand 2 "general_operand" ""))]
2759 "TARGET_HAS_XFLOATING_LIBS"
2760 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2762 (define_insn "*subsf3_ieee"
2763 [(set (match_operand:SF 0 "register_operand" "=&f")
2764 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2765 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2766 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2767 "sub%,%/ %R1,%R2,%0"
2768 [(set_attr "type" "fadd")
2769 (set_attr "trap" "yes")
2770 (set_attr "round_suffix" "normal")
2771 (set_attr "trap_suffix" "u_su_sui")])
2773 (define_insn "subsf3"
2774 [(set (match_operand:SF 0 "register_operand" "=f")
2775 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2776 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2777 "TARGET_FP"
2778 "sub%,%/ %R1,%R2,%0"
2779 [(set_attr "type" "fadd")
2780 (set_attr "trap" "yes")
2781 (set_attr "round_suffix" "normal")
2782 (set_attr "trap_suffix" "u_su_sui")])
2784 (define_insn "*subdf3_ieee"
2785 [(set (match_operand:DF 0 "register_operand" "=&f")
2786 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2787 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2788 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2789 "sub%-%/ %R1,%R2,%0"
2790 [(set_attr "type" "fadd")
2791 (set_attr "trap" "yes")
2792 (set_attr "round_suffix" "normal")
2793 (set_attr "trap_suffix" "u_su_sui")])
2795 (define_insn "subdf3"
2796 [(set (match_operand:DF 0 "register_operand" "=f")
2797 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2798 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2799 "TARGET_FP"
2800 "sub%-%/ %R1,%R2,%0"
2801 [(set_attr "type" "fadd")
2802 (set_attr "trap" "yes")
2803 (set_attr "round_suffix" "normal")
2804 (set_attr "trap_suffix" "u_su_sui")])
2806 (define_insn "*subdf_ext1"
2807 [(set (match_operand:DF 0 "register_operand" "=f")
2808 (minus:DF (float_extend:DF
2809 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2810 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2811 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2812 "sub%-%/ %R1,%R2,%0"
2813 [(set_attr "type" "fadd")
2814 (set_attr "trap" "yes")
2815 (set_attr "round_suffix" "normal")
2816 (set_attr "trap_suffix" "u_su_sui")])
2818 (define_insn "*subdf_ext2"
2819 [(set (match_operand:DF 0 "register_operand" "=f")
2820 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2821 (float_extend:DF
2822 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2823 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2824 "sub%-%/ %R1,%R2,%0"
2825 [(set_attr "type" "fadd")
2826 (set_attr "trap" "yes")
2827 (set_attr "round_suffix" "normal")
2828 (set_attr "trap_suffix" "u_su_sui")])
2830 (define_insn "*subdf_ext3"
2831 [(set (match_operand:DF 0 "register_operand" "=f")
2832 (minus:DF (float_extend:DF
2833 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2834 (float_extend:DF
2835 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2836 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2837 "sub%-%/ %R1,%R2,%0"
2838 [(set_attr "type" "fadd")
2839 (set_attr "trap" "yes")
2840 (set_attr "round_suffix" "normal")
2841 (set_attr "trap_suffix" "u_su_sui")])
2843 (define_expand "subtf3"
2844 [(use (match_operand 0 "register_operand" ""))
2845 (use (match_operand 1 "general_operand" ""))
2846 (use (match_operand 2 "general_operand" ""))]
2847 "TARGET_HAS_XFLOATING_LIBS"
2848 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2850 (define_insn "*sqrtsf2_ieee"
2851 [(set (match_operand:SF 0 "register_operand" "=&f")
2852 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2853 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2854 "sqrt%,%/ %R1,%0"
2855 [(set_attr "type" "fsqrt")
2856 (set_attr "opsize" "si")
2857 (set_attr "trap" "yes")
2858 (set_attr "round_suffix" "normal")
2859 (set_attr "trap_suffix" "u_su_sui")])
2861 (define_insn "sqrtsf2"
2862 [(set (match_operand:SF 0 "register_operand" "=f")
2863 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2864 "TARGET_FP && TARGET_FIX"
2865 "sqrt%,%/ %R1,%0"
2866 [(set_attr "type" "fsqrt")
2867 (set_attr "opsize" "si")
2868 (set_attr "trap" "yes")
2869 (set_attr "round_suffix" "normal")
2870 (set_attr "trap_suffix" "u_su_sui")])
2872 (define_insn "*sqrtdf2_ieee"
2873 [(set (match_operand:DF 0 "register_operand" "=&f")
2874 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2875 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2876 "sqrt%-%/ %R1,%0"
2877 [(set_attr "type" "fsqrt")
2878 (set_attr "trap" "yes")
2879 (set_attr "round_suffix" "normal")
2880 (set_attr "trap_suffix" "u_su_sui")])
2882 (define_insn "sqrtdf2"
2883 [(set (match_operand:DF 0 "register_operand" "=f")
2884 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2885 "TARGET_FP && TARGET_FIX"
2886 "sqrt%-%/ %1,%0"
2887 [(set_attr "type" "fsqrt")
2888 (set_attr "trap" "yes")
2889 (set_attr "round_suffix" "normal")
2890 (set_attr "trap_suffix" "u_su_sui")])
2891 \f
2892 ;; Next are all the integer comparisons, and conditional moves and branches
2893 ;; and some of the related define_expand's and define_split's.
2895 (define_insn "*setcc_internal"
2896 [(set (match_operand 0 "register_operand" "=r")
2897 (match_operator 1 "alpha_comparison_operator"
2898 [(match_operand:DI 2 "register_operand" "r")
2899 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2900 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2901 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2902 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2903 "cmp%C1 %2,%3,%0"
2904 [(set_attr "type" "icmp")])
2906 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2907 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2908 ;; from cse on.
2909 (define_insn "*setcc_swapped_internal"
2910 [(set (match_operand 0 "register_operand" "=r")
2911 (match_operator 1 "alpha_swapped_comparison_operator"
2912 [(match_operand:DI 2 "register_operand" "r")
2913 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2914 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2915 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2916 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2917 "cmp%c1 %r3,%2,%0"
2918 [(set_attr "type" "icmp")])
2920 ;; Use match_operator rather than ne directly so that we can match
2921 ;; multiple integer modes.
2922 (define_insn "*setne_internal"
2923 [(set (match_operand 0 "register_operand" "=r")
2924 (match_operator 1 "signed_comparison_operator"
2925 [(match_operand:DI 2 "register_operand" "r")
2926 (const_int 0)]))]
2927 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2928 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2929 && GET_CODE (operands[1]) == NE
2930 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2931 "cmpult $31,%2,%0"
2932 [(set_attr "type" "icmp")])
2934 ;; The mode folding trick can't be used with const_int operands, since
2935 ;; reload needs to know the proper mode.
2936 ;;
2937 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2938 ;; in order to create more pairs of constants. As long as we're allowing
2939 ;; two constants at the same time, and will have to reload one of them...
2941 (define_insn "*movqicc_internal"
2942 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2943 (if_then_else:QI
2944 (match_operator 2 "signed_comparison_operator"
2945 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2946 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2947 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2948 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2949 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2950 "@
2951 cmov%C2 %r3,%1,%0
2952 cmov%D2 %r3,%5,%0
2953 cmov%c2 %r4,%1,%0
2954 cmov%d2 %r4,%5,%0"
2955 [(set_attr "type" "icmov")])
2957 (define_insn "*movhicc_internal"
2958 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2959 (if_then_else:HI
2960 (match_operator 2 "signed_comparison_operator"
2961 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2962 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2963 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2964 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2965 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2966 "@
2967 cmov%C2 %r3,%1,%0
2968 cmov%D2 %r3,%5,%0
2969 cmov%c2 %r4,%1,%0
2970 cmov%d2 %r4,%5,%0"
2971 [(set_attr "type" "icmov")])
2973 (define_insn "*movsicc_internal"
2974 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2975 (if_then_else:SI
2976 (match_operator 2 "signed_comparison_operator"
2977 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2978 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2979 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2980 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2981 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2982 "@
2983 cmov%C2 %r3,%1,%0
2984 cmov%D2 %r3,%5,%0
2985 cmov%c2 %r4,%1,%0
2986 cmov%d2 %r4,%5,%0"
2987 [(set_attr "type" "icmov")])
2989 (define_insn "*movdicc_internal"
2990 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2991 (if_then_else:DI
2992 (match_operator 2 "signed_comparison_operator"
2993 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2994 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2995 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2996 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2997 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2998 "@
2999 cmov%C2 %r3,%1,%0
3000 cmov%D2 %r3,%5,%0
3001 cmov%c2 %r4,%1,%0
3002 cmov%d2 %r4,%5,%0"
3003 [(set_attr "type" "icmov")])
3005 (define_insn "*movqicc_lbc"
3006 [(set (match_operand:QI 0 "register_operand" "=r,r")
3007 (if_then_else:QI
3008 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3009 (const_int 1)
3010 (const_int 0))
3011 (const_int 0))
3012 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3013 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3014 ""
3015 "@
3016 cmovlbc %r2,%1,%0
3017 cmovlbs %r2,%3,%0"
3018 [(set_attr "type" "icmov")])
3020 (define_insn "*movhicc_lbc"
3021 [(set (match_operand:HI 0 "register_operand" "=r,r")
3022 (if_then_else:HI
3023 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3024 (const_int 1)
3025 (const_int 0))
3026 (const_int 0))
3027 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3028 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3029 ""
3030 "@
3031 cmovlbc %r2,%1,%0
3032 cmovlbs %r2,%3,%0"
3033 [(set_attr "type" "icmov")])
3035 (define_insn "*movsicc_lbc"
3036 [(set (match_operand:SI 0 "register_operand" "=r,r")
3037 (if_then_else:SI
3038 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3039 (const_int 1)
3040 (const_int 0))
3041 (const_int 0))
3042 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3043 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3044 ""
3045 "@
3046 cmovlbc %r2,%1,%0
3047 cmovlbs %r2,%3,%0"
3048 [(set_attr "type" "icmov")])
3050 (define_insn "*movdicc_lbc"
3051 [(set (match_operand:DI 0 "register_operand" "=r,r")
3052 (if_then_else:DI
3053 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3054 (const_int 1)
3055 (const_int 0))
3056 (const_int 0))
3057 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3058 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3059 ""
3060 "@
3061 cmovlbc %r2,%1,%0
3062 cmovlbs %r2,%3,%0"
3063 [(set_attr "type" "icmov")])
3065 (define_insn "*movqicc_lbs"
3066 [(set (match_operand:QI 0 "register_operand" "=r,r")
3067 (if_then_else:QI
3068 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3069 (const_int 1)
3070 (const_int 0))
3071 (const_int 0))
3072 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3073 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3074 ""
3075 "@
3076 cmovlbs %r2,%1,%0
3077 cmovlbc %r2,%3,%0"
3078 [(set_attr "type" "icmov")])
3080 (define_insn "*movhicc_lbs"
3081 [(set (match_operand:HI 0 "register_operand" "=r,r")
3082 (if_then_else:HI
3083 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3084 (const_int 1)
3085 (const_int 0))
3086 (const_int 0))
3087 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3088 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3089 ""
3090 "@
3091 cmovlbs %r2,%1,%0
3092 cmovlbc %r2,%3,%0"
3093 [(set_attr "type" "icmov")])
3095 (define_insn "*movsicc_lbs"
3096 [(set (match_operand:SI 0 "register_operand" "=r,r")
3097 (if_then_else:SI
3098 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3099 (const_int 1)
3100 (const_int 0))
3101 (const_int 0))
3102 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3103 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3104 ""
3105 "@
3106 cmovlbs %r2,%1,%0
3107 cmovlbc %r2,%3,%0"
3108 [(set_attr "type" "icmov")])
3110 (define_insn "*movdicc_lbs"
3111 [(set (match_operand:DI 0 "register_operand" "=r,r")
3112 (if_then_else:DI
3113 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3114 (const_int 1)
3115 (const_int 0))
3116 (const_int 0))
3117 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3118 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3119 ""
3120 "@
3121 cmovlbs %r2,%1,%0
3122 cmovlbc %r2,%3,%0"
3123 [(set_attr "type" "icmov")])
3125 ;; For ABS, we have two choices, depending on whether the input and output
3126 ;; registers are the same or not.
3127 (define_expand "absdi2"
3128 [(set (match_operand:DI 0 "register_operand" "")
3129 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3130 ""
3131 {
3132 if (rtx_equal_p (operands[0], operands[1]))
3133 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3134 else
3135 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3136 DONE;
3137 })
3139 (define_expand "absdi2_same"
3140 [(set (match_operand:DI 1 "register_operand" "")
3141 (neg:DI (match_operand:DI 0 "register_operand" "")))
3142 (set (match_dup 0)
3143 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3144 (match_dup 0)
3145 (match_dup 1)))]
3146 ""
3147 "")
3149 (define_expand "absdi2_diff"
3150 [(set (match_operand:DI 0 "register_operand" "")
3151 (neg:DI (match_operand:DI 1 "register_operand" "")))
3152 (set (match_dup 0)
3153 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3154 (match_dup 0)
3155 (match_dup 1)))]
3156 ""
3157 "")
3159 (define_split
3160 [(set (match_operand:DI 0 "register_operand" "")
3161 (abs:DI (match_dup 0)))
3162 (clobber (match_operand:DI 1 "register_operand" ""))]
3163 ""
3164 [(set (match_dup 1) (neg:DI (match_dup 0)))
3165 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3166 (match_dup 0) (match_dup 1)))]
3167 "")
3169 (define_split
3170 [(set (match_operand:DI 0 "register_operand" "")
3171 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3172 "! rtx_equal_p (operands[0], operands[1])"
3173 [(set (match_dup 0) (neg:DI (match_dup 1)))
3174 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3175 (match_dup 0) (match_dup 1)))]
3176 "")
3178 (define_split
3179 [(set (match_operand:DI 0 "register_operand" "")
3180 (neg:DI (abs:DI (match_dup 0))))
3181 (clobber (match_operand:DI 1 "register_operand" ""))]
3182 ""
3183 [(set (match_dup 1) (neg:DI (match_dup 0)))
3184 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3185 (match_dup 0) (match_dup 1)))]
3186 "")
3188 (define_split
3189 [(set (match_operand:DI 0 "register_operand" "")
3190 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3191 "! rtx_equal_p (operands[0], operands[1])"
3192 [(set (match_dup 0) (neg:DI (match_dup 1)))
3193 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3194 (match_dup 0) (match_dup 1)))]
3195 "")
3197 (define_insn "sminqi3"
3198 [(set (match_operand:QI 0 "register_operand" "=r")
3199 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3200 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3201 "TARGET_MAX"
3202 "minsb8 %r1,%2,%0"
3203 [(set_attr "type" "mvi")])
3205 (define_insn "uminqi3"
3206 [(set (match_operand:QI 0 "register_operand" "=r")
3207 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3208 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3209 "TARGET_MAX"
3210 "minub8 %r1,%2,%0"
3211 [(set_attr "type" "mvi")])
3213 (define_insn "smaxqi3"
3214 [(set (match_operand:QI 0 "register_operand" "=r")
3215 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3216 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3217 "TARGET_MAX"
3218 "maxsb8 %r1,%2,%0"
3219 [(set_attr "type" "mvi")])
3221 (define_insn "umaxqi3"
3222 [(set (match_operand:QI 0 "register_operand" "=r")
3223 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3224 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3225 "TARGET_MAX"
3226 "maxub8 %r1,%2,%0"
3227 [(set_attr "type" "mvi")])
3229 (define_insn "sminhi3"
3230 [(set (match_operand:HI 0 "register_operand" "=r")
3231 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3232 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3233 "TARGET_MAX"
3234 "minsw4 %r1,%2,%0"
3235 [(set_attr "type" "mvi")])
3237 (define_insn "uminhi3"
3238 [(set (match_operand:HI 0 "register_operand" "=r")
3239 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3240 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3241 "TARGET_MAX"
3242 "minuw4 %r1,%2,%0"
3243 [(set_attr "type" "mvi")])
3245 (define_insn "smaxhi3"
3246 [(set (match_operand:HI 0 "register_operand" "=r")
3247 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3248 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3249 "TARGET_MAX"
3250 "maxsw4 %r1,%2,%0"
3251 [(set_attr "type" "mvi")])
3253 (define_insn "umaxhi3"
3254 [(set (match_operand:HI 0 "register_operand" "=r")
3255 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3256 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3257 "TARGET_MAX"
3258 "maxuw4 %r1,%2,%0"
3259 [(set_attr "type" "mvi")])
3261 (define_expand "smaxdi3"
3262 [(set (match_dup 3)
3263 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3264 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3265 (set (match_operand:DI 0 "register_operand" "")
3266 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3267 (match_dup 1) (match_dup 2)))]
3268 ""
3269 { operands[3] = gen_reg_rtx (DImode); })
3271 (define_split
3272 [(set (match_operand:DI 0 "register_operand" "")
3273 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3274 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3275 (clobber (match_operand:DI 3 "register_operand" ""))]
3276 "operands[2] != const0_rtx"
3277 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3278 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3279 (match_dup 1) (match_dup 2)))]
3280 "")
3282 (define_insn "*smax_const0"
3283 [(set (match_operand:DI 0 "register_operand" "=r")
3284 (smax:DI (match_operand:DI 1 "register_operand" "0")
3285 (const_int 0)))]
3286 ""
3287 "cmovlt %0,0,%0"
3288 [(set_attr "type" "icmov")])
3290 (define_expand "smindi3"
3291 [(set (match_dup 3)
3292 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3293 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3294 (set (match_operand:DI 0 "register_operand" "")
3295 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3296 (match_dup 1) (match_dup 2)))]
3297 ""
3298 { operands[3] = gen_reg_rtx (DImode); })
3300 (define_split
3301 [(set (match_operand:DI 0 "register_operand" "")
3302 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3303 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3304 (clobber (match_operand:DI 3 "register_operand" ""))]
3305 "operands[2] != const0_rtx"
3306 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3307 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3308 (match_dup 1) (match_dup 2)))]
3309 "")
3311 (define_insn "*smin_const0"
3312 [(set (match_operand:DI 0 "register_operand" "=r")
3313 (smin:DI (match_operand:DI 1 "register_operand" "0")
3314 (const_int 0)))]
3315 ""
3316 "cmovgt %0,0,%0"
3317 [(set_attr "type" "icmov")])
3319 (define_expand "umaxdi3"
3320 [(set (match_dup 3)
3321 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3322 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3323 (set (match_operand:DI 0 "register_operand" "")
3324 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3325 (match_dup 1) (match_dup 2)))]
3326 ""
3327 "operands[3] = gen_reg_rtx (DImode);")
3329 (define_split
3330 [(set (match_operand:DI 0 "register_operand" "")
3331 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3332 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3333 (clobber (match_operand:DI 3 "register_operand" ""))]
3334 "operands[2] != const0_rtx"
3335 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3336 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3337 (match_dup 1) (match_dup 2)))]
3338 "")
3340 (define_expand "umindi3"
3341 [(set (match_dup 3)
3342 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3343 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3344 (set (match_operand:DI 0 "register_operand" "")
3345 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3346 (match_dup 1) (match_dup 2)))]
3347 ""
3348 "operands[3] = gen_reg_rtx (DImode);")
3350 (define_split
3351 [(set (match_operand:DI 0 "register_operand" "")
3352 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3353 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3354 (clobber (match_operand:DI 3 "register_operand" ""))]
3355 "operands[2] != const0_rtx"
3356 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3357 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3358 (match_dup 1) (match_dup 2)))]
3359 "")
3361 (define_insn "*bcc_normal"
3362 [(set (pc)
3363 (if_then_else
3364 (match_operator 1 "signed_comparison_operator"
3365 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3366 (const_int 0)])
3367 (label_ref (match_operand 0 "" ""))
3368 (pc)))]
3369 ""
3370 "b%C1 %r2,%0"
3371 [(set_attr "type" "ibr")])
3373 (define_insn "*bcc_reverse"
3374 [(set (pc)
3375 (if_then_else
3376 (match_operator 1 "signed_comparison_operator"
3377 [(match_operand:DI 2 "register_operand" "r")
3378 (const_int 0)])
3380 (pc)
3381 (label_ref (match_operand 0 "" ""))))]
3382 ""
3383 "b%c1 %2,%0"
3384 [(set_attr "type" "ibr")])
3386 (define_insn "*blbs_normal"
3387 [(set (pc)
3388 (if_then_else
3389 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3390 (const_int 1)
3391 (const_int 0))
3392 (const_int 0))
3393 (label_ref (match_operand 0 "" ""))
3394 (pc)))]
3395 ""
3396 "blbs %r1,%0"
3397 [(set_attr "type" "ibr")])
3399 (define_insn "*blbc_normal"
3400 [(set (pc)
3401 (if_then_else
3402 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3403 (const_int 1)
3404 (const_int 0))
3405 (const_int 0))
3406 (label_ref (match_operand 0 "" ""))
3407 (pc)))]
3408 ""
3409 "blbc %r1,%0"
3410 [(set_attr "type" "ibr")])
3412 (define_split
3413 [(parallel
3414 [(set (pc)
3415 (if_then_else
3416 (match_operator 1 "comparison_operator"
3417 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3418 (const_int 1)
3419 (match_operand:DI 3 "const_int_operand" ""))
3420 (const_int 0)])
3421 (label_ref (match_operand 0 "" ""))
3422 (pc)))
3423 (clobber (match_operand:DI 4 "register_operand" ""))])]
3424 "INTVAL (operands[3]) != 0"
3425 [(set (match_dup 4)
3426 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3427 (set (pc)
3428 (if_then_else (match_op_dup 1
3429 [(zero_extract:DI (match_dup 4)
3430 (const_int 1)
3431 (const_int 0))
3432 (const_int 0)])
3433 (label_ref (match_dup 0))
3434 (pc)))]
3435 "")
3436 \f
3437 ;; The following are the corresponding floating-point insns. Recall
3438 ;; we need to have variants that expand the arguments from SFmode
3439 ;; to DFmode.
3441 (define_insn "*cmpdf_ieee"
3442 [(set (match_operand:DF 0 "register_operand" "=&f")
3443 (match_operator:DF 1 "alpha_fp_comparison_operator"
3444 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3445 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3446 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3447 "cmp%-%C1%/ %R2,%R3,%0"
3448 [(set_attr "type" "fadd")
3449 (set_attr "trap" "yes")
3450 (set_attr "trap_suffix" "su")])
3452 (define_insn "*cmpdf_internal"
3453 [(set (match_operand:DF 0 "register_operand" "=f")
3454 (match_operator:DF 1 "alpha_fp_comparison_operator"
3455 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3456 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3457 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3458 "cmp%-%C1%/ %R2,%R3,%0"
3459 [(set_attr "type" "fadd")
3460 (set_attr "trap" "yes")
3461 (set_attr "trap_suffix" "su")])
3463 (define_insn "*cmpdf_ieee_ext1"
3464 [(set (match_operand:DF 0 "register_operand" "=&f")
3465 (match_operator:DF 1 "alpha_fp_comparison_operator"
3466 [(float_extend:DF
3467 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3468 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3469 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3470 "cmp%-%C1%/ %R2,%R3,%0"
3471 [(set_attr "type" "fadd")
3472 (set_attr "trap" "yes")
3473 (set_attr "trap_suffix" "su")])
3475 (define_insn "*cmpdf_ext1"
3476 [(set (match_operand:DF 0 "register_operand" "=f")
3477 (match_operator:DF 1 "alpha_fp_comparison_operator"
3478 [(float_extend:DF
3479 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3480 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3481 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3482 "cmp%-%C1%/ %R2,%R3,%0"
3483 [(set_attr "type" "fadd")
3484 (set_attr "trap" "yes")
3485 (set_attr "trap_suffix" "su")])
3487 (define_insn "*cmpdf_ieee_ext2"
3488 [(set (match_operand:DF 0 "register_operand" "=&f")
3489 (match_operator:DF 1 "alpha_fp_comparison_operator"
3490 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3491 (float_extend:DF
3492 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3493 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3494 "cmp%-%C1%/ %R2,%R3,%0"
3495 [(set_attr "type" "fadd")
3496 (set_attr "trap" "yes")
3497 (set_attr "trap_suffix" "su")])
3499 (define_insn "*cmpdf_ext2"
3500 [(set (match_operand:DF 0 "register_operand" "=f")
3501 (match_operator:DF 1 "alpha_fp_comparison_operator"
3502 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3503 (float_extend:DF
3504 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3505 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3506 "cmp%-%C1%/ %R2,%R3,%0"
3507 [(set_attr "type" "fadd")
3508 (set_attr "trap" "yes")
3509 (set_attr "trap_suffix" "su")])
3511 (define_insn "*cmpdf_ieee_ext3"
3512 [(set (match_operand:DF 0 "register_operand" "=&f")
3513 (match_operator:DF 1 "alpha_fp_comparison_operator"
3514 [(float_extend:DF
3515 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3516 (float_extend:DF
3517 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3518 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3519 "cmp%-%C1%/ %R2,%R3,%0"
3520 [(set_attr "type" "fadd")
3521 (set_attr "trap" "yes")
3522 (set_attr "trap_suffix" "su")])
3524 (define_insn "*cmpdf_ext3"
3525 [(set (match_operand:DF 0 "register_operand" "=f")
3526 (match_operator:DF 1 "alpha_fp_comparison_operator"
3527 [(float_extend:DF
3528 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3529 (float_extend:DF
3530 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3531 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3532 "cmp%-%C1%/ %R2,%R3,%0"
3533 [(set_attr "type" "fadd")
3534 (set_attr "trap" "yes")
3535 (set_attr "trap_suffix" "su")])
3537 (define_insn "*movdfcc_internal"
3538 [(set (match_operand:DF 0 "register_operand" "=f,f")
3539 (if_then_else:DF
3540 (match_operator 3 "signed_comparison_operator"
3541 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3542 (match_operand:DF 2 "const0_operand" "G,G")])
3543 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3544 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3545 "TARGET_FP"
3546 "@
3547 fcmov%C3 %R4,%R1,%0
3548 fcmov%D3 %R4,%R5,%0"
3549 [(set_attr "type" "fcmov")])
3551 (define_insn "*movsfcc_internal"
3552 [(set (match_operand:SF 0 "register_operand" "=f,f")
3553 (if_then_else:SF
3554 (match_operator 3 "signed_comparison_operator"
3555 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3556 (match_operand:DF 2 "const0_operand" "G,G")])
3557 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3558 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3559 "TARGET_FP"
3560 "@
3561 fcmov%C3 %R4,%R1,%0
3562 fcmov%D3 %R4,%R5,%0"
3563 [(set_attr "type" "fcmov")])
3565 (define_insn "*movdfcc_ext1"
3566 [(set (match_operand:DF 0 "register_operand" "=f,f")
3567 (if_then_else:DF
3568 (match_operator 3 "signed_comparison_operator"
3569 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3570 (match_operand:DF 2 "const0_operand" "G,G")])
3571 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3572 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3573 "TARGET_FP"
3574 "@
3575 fcmov%C3 %R4,%R1,%0
3576 fcmov%D3 %R4,%R5,%0"
3577 [(set_attr "type" "fcmov")])
3579 (define_insn "*movdfcc_ext2"
3580 [(set (match_operand:DF 0 "register_operand" "=f,f")
3581 (if_then_else:DF
3582 (match_operator 3 "signed_comparison_operator"
3583 [(float_extend:DF
3584 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3585 (match_operand:DF 2 "const0_operand" "G,G")])
3586 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3587 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3588 "TARGET_FP"
3589 "@
3590 fcmov%C3 %R4,%R1,%0
3591 fcmov%D3 %R4,%R5,%0"
3592 [(set_attr "type" "fcmov")])
3594 (define_insn "*movdfcc_ext3"
3595 [(set (match_operand:SF 0 "register_operand" "=f,f")
3596 (if_then_else:SF
3597 (match_operator 3 "signed_comparison_operator"
3598 [(float_extend:DF
3599 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3600 (match_operand:DF 2 "const0_operand" "G,G")])
3601 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3602 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3603 "TARGET_FP"
3604 "@
3605 fcmov%C3 %R4,%R1,%0
3606 fcmov%D3 %R4,%R5,%0"
3607 [(set_attr "type" "fcmov")])
3609 (define_insn "*movdfcc_ext4"
3610 [(set (match_operand:DF 0 "register_operand" "=f,f")
3611 (if_then_else:DF
3612 (match_operator 3 "signed_comparison_operator"
3613 [(float_extend:DF
3614 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3615 (match_operand:DF 2 "const0_operand" "G,G")])
3616 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3617 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3618 "TARGET_FP"
3619 "@
3620 fcmov%C3 %R4,%R1,%0
3621 fcmov%D3 %R4,%R5,%0"
3622 [(set_attr "type" "fcmov")])
3624 (define_expand "maxdf3"
3625 [(set (match_dup 3)
3626 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3627 (match_operand:DF 2 "reg_or_0_operand" "")))
3628 (set (match_operand:DF 0 "register_operand" "")
3629 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3630 (match_dup 1) (match_dup 2)))]
3631 "TARGET_FP"
3632 {
3633 operands[3] = gen_reg_rtx (DFmode);
3634 operands[4] = CONST0_RTX (DFmode);
3635 })
3637 (define_expand "mindf3"
3638 [(set (match_dup 3)
3639 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3640 (match_operand:DF 2 "reg_or_0_operand" "")))
3641 (set (match_operand:DF 0 "register_operand" "")
3642 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3643 (match_dup 1) (match_dup 2)))]
3644 "TARGET_FP"
3645 {
3646 operands[3] = gen_reg_rtx (DFmode);
3647 operands[4] = CONST0_RTX (DFmode);
3648 })
3650 (define_expand "maxsf3"
3651 [(set (match_dup 3)
3652 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3653 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3654 (set (match_operand:SF 0 "register_operand" "")
3655 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3656 (match_dup 1) (match_dup 2)))]
3657 "TARGET_FP"
3658 {
3659 operands[3] = gen_reg_rtx (DFmode);
3660 operands[4] = CONST0_RTX (DFmode);
3661 })
3663 (define_expand "minsf3"
3664 [(set (match_dup 3)
3665 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3666 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3667 (set (match_operand:SF 0 "register_operand" "")
3668 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3669 (match_dup 1) (match_dup 2)))]
3670 "TARGET_FP"
3671 {
3672 operands[3] = gen_reg_rtx (DFmode);
3673 operands[4] = CONST0_RTX (DFmode);
3674 })
3676 (define_insn "*fbcc_normal"
3677 [(set (pc)
3678 (if_then_else
3679 (match_operator 1 "signed_comparison_operator"
3680 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3681 (match_operand:DF 3 "const0_operand" "G")])
3682 (label_ref (match_operand 0 "" ""))
3683 (pc)))]
3684 "TARGET_FP"
3685 "fb%C1 %R2,%0"
3686 [(set_attr "type" "fbr")])
3688 (define_insn "*fbcc_ext_normal"
3689 [(set (pc)
3690 (if_then_else
3691 (match_operator 1 "signed_comparison_operator"
3692 [(float_extend:DF
3693 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3694 (match_operand:DF 3 "const0_operand" "G")])
3695 (label_ref (match_operand 0 "" ""))
3696 (pc)))]
3697 "TARGET_FP"
3698 "fb%C1 %R2,%0"
3699 [(set_attr "type" "fbr")])
3700 \f
3701 ;; These are the main define_expand's used to make conditional branches
3702 ;; and compares.
3704 (define_expand "cmpdf"
3705 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3706 (match_operand:DF 1 "reg_or_0_operand" "")))]
3707 "TARGET_FP"
3708 {
3709 alpha_compare.op0 = operands[0];
3710 alpha_compare.op1 = operands[1];
3711 alpha_compare.fp_p = 1;
3712 DONE;
3713 })
3715 (define_expand "cmptf"
3716 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3717 (match_operand:TF 1 "general_operand" "")))]
3718 "TARGET_HAS_XFLOATING_LIBS"
3719 {
3720 alpha_compare.op0 = operands[0];
3721 alpha_compare.op1 = operands[1];
3722 alpha_compare.fp_p = 1;
3723 DONE;
3724 })
3726 (define_expand "cmpdi"
3727 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3728 (match_operand:DI 1 "general_operand" "")))]
3729 ""
3730 {
3731 alpha_compare.op0 = operands[0];
3732 alpha_compare.op1 = operands[1];
3733 alpha_compare.fp_p = 0;
3734 DONE;
3735 })
3737 (define_expand "beq"
3738 [(set (pc)
3739 (if_then_else (match_dup 1)
3740 (label_ref (match_operand 0 "" ""))
3741 (pc)))]
3742 ""
3743 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3745 (define_expand "bne"
3746 [(set (pc)
3747 (if_then_else (match_dup 1)
3748 (label_ref (match_operand 0 "" ""))
3749 (pc)))]
3750 ""
3751 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3753 (define_expand "blt"
3754 [(set (pc)
3755 (if_then_else (match_dup 1)
3756 (label_ref (match_operand 0 "" ""))
3757 (pc)))]
3758 ""
3759 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3761 (define_expand "ble"
3762 [(set (pc)
3763 (if_then_else (match_dup 1)
3764 (label_ref (match_operand 0 "" ""))
3765 (pc)))]
3766 ""
3767 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3769 (define_expand "bgt"
3770 [(set (pc)
3771 (if_then_else (match_dup 1)
3772 (label_ref (match_operand 0 "" ""))
3773 (pc)))]
3774 ""
3775 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3777 (define_expand "bge"
3778 [(set (pc)
3779 (if_then_else (match_dup 1)
3780 (label_ref (match_operand 0 "" ""))
3781 (pc)))]
3782 ""
3783 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3785 (define_expand "bltu"
3786 [(set (pc)
3787 (if_then_else (match_dup 1)
3788 (label_ref (match_operand 0 "" ""))
3789 (pc)))]
3790 ""
3791 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3793 (define_expand "bleu"
3794 [(set (pc)
3795 (if_then_else (match_dup 1)
3796 (label_ref (match_operand 0 "" ""))
3797 (pc)))]
3798 ""
3799 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3801 (define_expand "bgtu"
3802 [(set (pc)
3803 (if_then_else (match_dup 1)
3804 (label_ref (match_operand 0 "" ""))
3805 (pc)))]
3806 ""
3807 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3809 (define_expand "bgeu"
3810 [(set (pc)
3811 (if_then_else (match_dup 1)
3812 (label_ref (match_operand 0 "" ""))
3813 (pc)))]
3814 ""
3815 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3817 (define_expand "bunordered"
3818 [(set (pc)
3819 (if_then_else (match_dup 1)
3820 (label_ref (match_operand 0 "" ""))
3821 (pc)))]
3822 ""
3823 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3825 (define_expand "bordered"
3826 [(set (pc)
3827 (if_then_else (match_dup 1)
3828 (label_ref (match_operand 0 "" ""))
3829 (pc)))]
3830 ""
3831 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3833 (define_expand "seq"
3834 [(set (match_operand:DI 0 "register_operand" "")
3835 (match_dup 1))]
3836 ""
3837 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3839 (define_expand "sne"
3840 [(set (match_operand:DI 0 "register_operand" "")
3841 (match_dup 1))]
3842 ""
3843 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3845 (define_expand "slt"
3846 [(set (match_operand:DI 0 "register_operand" "")
3847 (match_dup 1))]
3848 ""
3849 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3851 (define_expand "sle"
3852 [(set (match_operand:DI 0 "register_operand" "")
3853 (match_dup 1))]
3854 ""
3855 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3857 (define_expand "sgt"
3858 [(set (match_operand:DI 0 "register_operand" "")
3859 (match_dup 1))]
3860 ""
3861 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3863 (define_expand "sge"
3864 [(set (match_operand:DI 0 "register_operand" "")
3865 (match_dup 1))]
3866 ""
3867 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3869 (define_expand "sltu"
3870 [(set (match_operand:DI 0 "register_operand" "")
3871 (match_dup 1))]
3872 ""
3873 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3875 (define_expand "sleu"
3876 [(set (match_operand:DI 0 "register_operand" "")
3877 (match_dup 1))]
3878 ""
3879 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3881 (define_expand "sgtu"
3882 [(set (match_operand:DI 0 "register_operand" "")
3883 (match_dup 1))]
3884 ""
3885 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3887 (define_expand "sgeu"
3888 [(set (match_operand:DI 0 "register_operand" "")
3889 (match_dup 1))]
3890 ""
3891 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3893 (define_expand "sunordered"
3894 [(set (match_operand:DI 0 "register_operand" "")
3895 (match_dup 1))]
3896 ""
3897 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3899 (define_expand "sordered"
3900 [(set (match_operand:DI 0 "register_operand" "")
3901 (match_dup 1))]
3902 ""
3903 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3904 \f
3905 ;; These are the main define_expand's used to make conditional moves.
3907 (define_expand "movsicc"
3908 [(set (match_operand:SI 0 "register_operand" "")
3909 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3910 (match_operand:SI 2 "reg_or_8bit_operand" "")
3911 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3912 ""
3913 {
3914 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3915 FAIL;
3916 })
3918 (define_expand "movdicc"
3919 [(set (match_operand:DI 0 "register_operand" "")
3920 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3921 (match_operand:DI 2 "reg_or_8bit_operand" "")
3922 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3923 ""
3924 {
3925 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3926 FAIL;
3927 })
3929 (define_expand "movsfcc"
3930 [(set (match_operand:SF 0 "register_operand" "")
3931 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3932 (match_operand:SF 2 "reg_or_8bit_operand" "")
3933 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3934 ""
3935 {
3936 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3937 FAIL;
3938 })
3940 (define_expand "movdfcc"
3941 [(set (match_operand:DF 0 "register_operand" "")
3942 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3943 (match_operand:DF 2 "reg_or_8bit_operand" "")
3944 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3945 ""
3946 {
3947 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3948 FAIL;
3949 })
3950 \f
3951 ;; These define_split definitions are used in cases when comparisons have
3952 ;; not be stated in the correct way and we need to reverse the second
3953 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3954 ;; comparison that tests the result being reversed. We have one define_split
3955 ;; for each use of a comparison. They do not match valid insns and need
3956 ;; not generate valid insns.
3957 ;;
3958 ;; We can also handle equality comparisons (and inequality comparisons in
3959 ;; cases where the resulting add cannot overflow) by doing an add followed by
3960 ;; a comparison with zero. This is faster since the addition takes one
3961 ;; less cycle than a compare when feeding into a conditional move.
3962 ;; For this case, we also have an SImode pattern since we can merge the add
3963 ;; and sign extend and the order doesn't matter.
3964 ;;
3965 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3966 ;; operation could have been generated.
3968 (define_split
3969 [(set (match_operand:DI 0 "register_operand" "")
3970 (if_then_else:DI
3971 (match_operator 1 "comparison_operator"
3972 [(match_operand:DI 2 "reg_or_0_operand" "")
3973 (match_operand:DI 3 "reg_or_cint_operand" "")])
3974 (match_operand:DI 4 "reg_or_cint_operand" "")
3975 (match_operand:DI 5 "reg_or_cint_operand" "")))
3976 (clobber (match_operand:DI 6 "register_operand" ""))]
3977 "operands[3] != const0_rtx"
3978 [(set (match_dup 6) (match_dup 7))
3979 (set (match_dup 0)
3980 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3981 {
3982 enum rtx_code code = GET_CODE (operands[1]);
3983 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3985 /* If we are comparing for equality with a constant and that constant
3986 appears in the arm when the register equals the constant, use the
3987 register since that is more likely to match (and to produce better code
3988 if both would). */
3990 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3991 && rtx_equal_p (operands[4], operands[3]))
3992 operands[4] = operands[2];
3994 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3995 && rtx_equal_p (operands[5], operands[3]))
3996 operands[5] = operands[2];
3998 if (code == NE || code == EQ
3999 || (extended_count (operands[2], DImode, unsignedp) >= 1
4000 && extended_count (operands[3], DImode, unsignedp) >= 1))
4001 {
4002 if (GET_CODE (operands[3]) == CONST_INT)
4003 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4004 GEN_INT (- INTVAL (operands[3])));
4005 else
4006 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4008 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4009 }
4011 else if (code == EQ || code == LE || code == LT
4012 || code == LEU || code == LTU)
4013 {
4014 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4015 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4016 }
4017 else
4018 {
4019 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4020 operands[2], operands[3]);
4021 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4022 }
4023 })
4025 (define_split
4026 [(set (match_operand:DI 0 "register_operand" "")
4027 (if_then_else:DI
4028 (match_operator 1 "comparison_operator"
4029 [(match_operand:SI 2 "reg_or_0_operand" "")
4030 (match_operand:SI 3 "reg_or_cint_operand" "")])
4031 (match_operand:DI 4 "reg_or_8bit_operand" "")
4032 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4033 (clobber (match_operand:DI 6 "register_operand" ""))]
4034 "operands[3] != const0_rtx
4035 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4036 [(set (match_dup 6) (match_dup 7))
4037 (set (match_dup 0)
4038 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4039 {
4040 enum rtx_code code = GET_CODE (operands[1]);
4041 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4042 rtx tem;
4044 if ((code != NE && code != EQ
4045 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4046 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4047 FAIL;
4049 if (GET_CODE (operands[3]) == CONST_INT)
4050 tem = gen_rtx_PLUS (SImode, operands[2],
4051 GEN_INT (- INTVAL (operands[3])));
4052 else
4053 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4055 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4056 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4057 operands[6], const0_rtx);
4058 })
4060 (define_split
4061 [(set (pc)
4062 (if_then_else
4063 (match_operator 1 "comparison_operator"
4064 [(match_operand:DI 2 "reg_or_0_operand" "")
4065 (match_operand:DI 3 "reg_or_cint_operand" "")])
4066 (label_ref (match_operand 0 "" ""))
4067 (pc)))
4068 (clobber (match_operand:DI 4 "register_operand" ""))]
4069 "operands[3] != const0_rtx"
4070 [(set (match_dup 4) (match_dup 5))
4071 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4072 {
4073 enum rtx_code code = GET_CODE (operands[1]);
4074 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4076 if (code == NE || code == EQ
4077 || (extended_count (operands[2], DImode, unsignedp) >= 1
4078 && extended_count (operands[3], DImode, unsignedp) >= 1))
4079 {
4080 if (GET_CODE (operands[3]) == CONST_INT)
4081 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4082 GEN_INT (- INTVAL (operands[3])));
4083 else
4084 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4086 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4087 }
4089 else if (code == EQ || code == LE || code == LT
4090 || code == LEU || code == LTU)
4091 {
4092 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4093 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4094 }
4095 else
4096 {
4097 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4098 operands[2], operands[3]);
4099 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4100 }
4101 })
4103 (define_split
4104 [(set (pc)
4105 (if_then_else
4106 (match_operator 1 "comparison_operator"
4107 [(match_operand:SI 2 "reg_or_0_operand" "")
4108 (match_operand:SI 3 "const_int_operand" "")])
4109 (label_ref (match_operand 0 "" ""))
4110 (pc)))
4111 (clobber (match_operand:DI 4 "register_operand" ""))]
4112 "operands[3] != const0_rtx
4113 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4114 [(set (match_dup 4) (match_dup 5))
4115 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4116 {
4117 rtx tem;
4119 if (GET_CODE (operands[3]) == CONST_INT)
4120 tem = gen_rtx_PLUS (SImode, operands[2],
4121 GEN_INT (- INTVAL (operands[3])));
4122 else
4123 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4125 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4126 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4127 operands[4], const0_rtx);
4128 })
4130 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4131 ;; This eliminates one, and sometimes two, insns when the AND can be done
4132 ;; with a ZAP.
4133 (define_split
4134 [(set (match_operand:DI 0 "register_operand" "")
4135 (match_operator:DI 1 "comparison_operator"
4136 [(match_operand:DI 2 "register_operand" "")
4137 (match_operand:DI 3 "const_int_operand" "")]))
4138 (clobber (match_operand:DI 4 "register_operand" ""))]
4139 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4140 && (GET_CODE (operands[1]) == GTU
4141 || GET_CODE (operands[1]) == LEU
4142 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4143 && extended_count (operands[2], DImode, 1) > 0))"
4144 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4145 (set (match_dup 0) (match_dup 6))]
4146 {
4147 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4148 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4149 || GET_CODE (operands[1]) == GT)
4150 ? NE : EQ),
4151 DImode, operands[4], const0_rtx);
4152 })
4154 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4156 (define_split
4157 [(set (match_operand 0 "register_operand" "")
4158 (if_then_else (match_operator 1 "signed_comparison_operator"
4159 [(match_operand:DI 2 "reg_or_0_operand" "")
4160 (const_int 0)])
4161 (match_operand 3 "const_int_operand" "")
4162 (match_operand 4 "const_int_operand" "")))]
4163 ""
4164 [(const_int 0)]
4165 {
4166 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4167 operands[2], operands[3], operands[4]))
4168 DONE;
4169 else
4170 FAIL;
4171 })
4173 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4174 ;; Oh well, we match it in movcc, so it must be partially our fault.
4175 (define_split
4176 [(set (match_operand 0 "register_operand" "")
4177 (if_then_else (match_operator 1 "signed_comparison_operator"
4178 [(const_int 0)
4179 (match_operand:DI 2 "reg_or_0_operand" "")])
4180 (match_operand 3 "const_int_operand" "")
4181 (match_operand 4 "const_int_operand" "")))]
4182 ""
4183 [(const_int 0)]
4184 {
4185 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4186 operands[0], operands[2], operands[3],
4187 operands[4]))
4188 DONE;
4189 else
4190 FAIL;
4191 })
4193 (define_insn_and_split "*cmp_sadd_di"
4194 [(set (match_operand:DI 0 "register_operand" "=r")
4195 (plus:DI (if_then_else:DI
4196 (match_operator 1 "alpha_zero_comparison_operator"
4197 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4198 (const_int 0)])
4199 (match_operand:DI 3 "const48_operand" "I")
4200 (const_int 0))
4201 (match_operand:DI 4 "sext_add_operand" "rIO")))
4202 (clobber (match_scratch:DI 5 "=r"))]
4203 ""
4204 "#"
4205 "! no_new_pseudos || reload_completed"
4206 [(set (match_dup 5)
4207 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4208 (set (match_dup 0)
4209 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4210 (match_dup 4)))]
4211 {
4212 if (! no_new_pseudos)
4213 operands[5] = gen_reg_rtx (DImode);
4214 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4215 operands[5] = operands[0];
4216 })
4218 (define_insn_and_split "*cmp_sadd_si"
4219 [(set (match_operand:SI 0 "register_operand" "=r")
4220 (plus:SI (if_then_else:SI
4221 (match_operator 1 "alpha_zero_comparison_operator"
4222 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4223 (const_int 0)])
4224 (match_operand:SI 3 "const48_operand" "I")
4225 (const_int 0))
4226 (match_operand:SI 4 "sext_add_operand" "rIO")))
4227 (clobber (match_scratch:SI 5 "=r"))]
4228 ""
4229 "#"
4230 "! no_new_pseudos || reload_completed"
4231 [(set (match_dup 5)
4232 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4233 (set (match_dup 0)
4234 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4235 (match_dup 4)))]
4236 {
4237 if (! no_new_pseudos)
4238 operands[5] = gen_reg_rtx (DImode);
4239 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4240 operands[5] = operands[0];
4241 })
4243 (define_insn_and_split "*cmp_sadd_sidi"
4244 [(set (match_operand:DI 0 "register_operand" "=r")
4245 (sign_extend:DI
4246 (plus:SI (if_then_else:SI
4247 (match_operator 1 "alpha_zero_comparison_operator"
4248 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4249 (const_int 0)])
4250 (match_operand:SI 3 "const48_operand" "I")
4251 (const_int 0))
4252 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4253 (clobber (match_scratch:SI 5 "=r"))]
4254 ""
4255 "#"
4256 "! no_new_pseudos || reload_completed"
4257 [(set (match_dup 5)
4258 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4259 (set (match_dup 0)
4260 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4261 (match_dup 4))))]
4262 {
4263 if (! no_new_pseudos)
4264 operands[5] = gen_reg_rtx (DImode);
4265 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4266 operands[5] = operands[0];
4267 })
4269 (define_insn_and_split "*cmp_ssub_di"
4270 [(set (match_operand:DI 0 "register_operand" "=r")
4271 (minus:DI (if_then_else:DI
4272 (match_operator 1 "alpha_zero_comparison_operator"
4273 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4274 (const_int 0)])
4275 (match_operand:DI 3 "const48_operand" "I")
4276 (const_int 0))
4277 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4278 (clobber (match_scratch:DI 5 "=r"))]
4279 ""
4280 "#"
4281 "! no_new_pseudos || reload_completed"
4282 [(set (match_dup 5)
4283 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4284 (set (match_dup 0)
4285 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4286 (match_dup 4)))]
4287 {
4288 if (! no_new_pseudos)
4289 operands[5] = gen_reg_rtx (DImode);
4290 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4291 operands[5] = operands[0];
4292 })
4294 (define_insn_and_split "*cmp_ssub_si"
4295 [(set (match_operand:SI 0 "register_operand" "=r")
4296 (minus:SI (if_then_else:SI
4297 (match_operator 1 "alpha_zero_comparison_operator"
4298 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4299 (const_int 0)])
4300 (match_operand:SI 3 "const48_operand" "I")
4301 (const_int 0))
4302 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4303 (clobber (match_scratch:SI 5 "=r"))]
4304 ""
4305 "#"
4306 "! no_new_pseudos || reload_completed"
4307 [(set (match_dup 5)
4308 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4309 (set (match_dup 0)
4310 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4311 (match_dup 4)))]
4312 {
4313 if (! no_new_pseudos)
4314 operands[5] = gen_reg_rtx (DImode);
4315 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4316 operands[5] = operands[0];
4317 })
4319 (define_insn_and_split "*cmp_ssub_sidi"
4320 [(set (match_operand:DI 0 "register_operand" "=r")
4321 (sign_extend:DI
4322 (minus:SI (if_then_else:SI
4323 (match_operator 1 "alpha_zero_comparison_operator"
4324 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4325 (const_int 0)])
4326 (match_operand:SI 3 "const48_operand" "I")
4327 (const_int 0))
4328 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4329 (clobber (match_scratch:SI 5 "=r"))]
4330 ""
4331 "#"
4332 "! no_new_pseudos || reload_completed"
4333 [(set (match_dup 5)
4334 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4335 (set (match_dup 0)
4336 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4337 (match_dup 4))))]
4338 {
4339 if (! no_new_pseudos)
4340 operands[5] = gen_reg_rtx (DImode);
4341 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4342 operands[5] = operands[0];
4343 })
4344 \f
4345 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4346 ;; work differently, so we have different patterns for each.
4348 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4349 ;; call. The CIW contains information about arguments passed in registers
4350 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4351 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4352 ;; in the presence of inlining since the CIWs for calls performed by the
4353 ;; inlined function must be stored in the SSIB of the function it is inlined
4354 ;; into as well. We encode the CIW in an unspec and append it to the list
4355 ;; of the CIWs for the current function only when the instruction for loading
4356 ;; $25 is generated.
4358 (define_expand "call"
4359 [(use (match_operand:DI 0 "" ""))
4360 (use (match_operand 1 "" ""))
4361 (use (match_operand 2 "" ""))
4362 (use (match_operand 3 "" ""))]
4363 ""
4364 {
4365 if (TARGET_ABI_WINDOWS_NT)
4366 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4367 else if (TARGET_ABI_OPEN_VMS)
4368 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4369 else if (TARGET_ABI_UNICOSMK)
4370 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4371 else
4372 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4373 DONE;
4374 })
4376 (define_expand "sibcall"
4377 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4378 (match_operand 1 "" ""))
4379 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4380 "TARGET_ABI_OSF"
4381 {
4382 if (GET_CODE (operands[0]) != MEM)
4383 abort ();
4384 operands[0] = XEXP (operands[0], 0);
4385 })
4387 (define_expand "call_osf"
4388 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4389 (match_operand 1 "" ""))
4390 (use (reg:DI 29))
4391 (clobber (reg:DI 26))])]
4392 ""
4393 {
4394 if (GET_CODE (operands[0]) != MEM)
4395 abort ();
4397 operands[0] = XEXP (operands[0], 0);
4398 if (! call_operand (operands[0], Pmode))
4399 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4400 })
4402 (define_expand "call_nt"
4403 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4404 (match_operand 1 "" ""))
4405 (clobber (reg:DI 26))])]
4406 ""
4407 {
4408 if (GET_CODE (operands[0]) != MEM)
4409 abort ();
4411 operands[0] = XEXP (operands[0], 0);
4412 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4413 operands[0] = force_reg (DImode, operands[0]);
4414 })
4416 ;; Calls on Unicos/Mk are always indirect.
4417 ;; op 0: symbol ref for called function
4418 ;; op 1: CIW for $25 represented by an unspec
4420 (define_expand "call_umk"
4421 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4422 (match_operand 1 "" ""))
4423 (use (reg:DI 25))
4424 (clobber (reg:DI 26))])]
4425 ""
4426 {
4427 if (GET_CODE (operands[0]) != MEM)
4428 abort ();
4430 /* Always load the address of the called function into a register;
4431 load the CIW in $25. */
4433 operands[0] = XEXP (operands[0], 0);
4434 if (GET_CODE (operands[0]) != REG)
4435 operands[0] = force_reg (DImode, operands[0]);
4437 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4438 })
4440 ;;
4441 ;; call openvms/alpha
4442 ;; op 0: symbol ref for called function
4443 ;; op 1: next_arg_reg (argument information value for R25)
4444 ;;
4445 (define_expand "call_vms"
4446 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4447 (match_operand 1 "" ""))
4448 (use (match_dup 2))
4449 (use (reg:DI 25))
4450 (use (reg:DI 26))
4451 (clobber (reg:DI 27))])]
4452 ""
4453 {
4454 if (GET_CODE (operands[0]) != MEM)
4455 abort ();
4457 operands[0] = XEXP (operands[0], 0);
4459 /* Always load AI with argument information, then handle symbolic and
4460 indirect call differently. Load RA and set operands[2] to PV in
4461 both cases. */
4463 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4464 if (GET_CODE (operands[0]) == SYMBOL_REF)
4465 {
4466 alpha_need_linkage (XSTR (operands[0], 0), 0);
4468 operands[2] = const0_rtx;
4469 }
4470 else
4471 {
4472 emit_move_insn (gen_rtx_REG (Pmode, 26),
4473 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4474 operands[2] = operands[0];
4475 }
4477 })
4479 (define_expand "call_value"
4480 [(use (match_operand 0 "" ""))
4481 (use (match_operand:DI 1 "" ""))
4482 (use (match_operand 2 "" ""))
4483 (use (match_operand 3 "" ""))
4484 (use (match_operand 4 "" ""))]
4485 ""
4486 {
4487 if (TARGET_ABI_WINDOWS_NT)
4488 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4489 else if (TARGET_ABI_OPEN_VMS)
4490 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4491 operands[3]));
4492 else if (TARGET_ABI_UNICOSMK)
4493 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4494 operands[3]));
4495 else
4496 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4497 operands[2]));
4498 DONE;
4499 })
4501 (define_expand "sibcall_value"
4502 [(parallel [(set (match_operand 0 "" "")
4503 (call (mem:DI (match_operand 1 "" ""))
4504 (match_operand 2 "" "")))
4505 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4506 "TARGET_ABI_OSF"
4507 {
4508 if (GET_CODE (operands[1]) != MEM)
4509 abort ();
4510 operands[1] = XEXP (operands[1], 0);
4511 })
4513 (define_expand "call_value_osf"
4514 [(parallel [(set (match_operand 0 "" "")
4515 (call (mem:DI (match_operand 1 "" ""))
4516 (match_operand 2 "" "")))
4517 (use (reg:DI 29))
4518 (clobber (reg:DI 26))])]
4519 ""
4520 {
4521 if (GET_CODE (operands[1]) != MEM)
4522 abort ();
4524 operands[1] = XEXP (operands[1], 0);
4525 if (! call_operand (operands[1], Pmode))
4526 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4527 })
4529 (define_expand "call_value_nt"
4530 [(parallel [(set (match_operand 0 "" "")
4531 (call (mem:DI (match_operand 1 "" ""))
4532 (match_operand 2 "" "")))
4533 (clobber (reg:DI 26))])]
4534 ""
4535 {
4536 if (GET_CODE (operands[1]) != MEM)
4537 abort ();
4539 operands[1] = XEXP (operands[1], 0);
4540 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4541 operands[1] = force_reg (DImode, operands[1]);
4542 })
4544 (define_expand "call_value_vms"
4545 [(parallel [(set (match_operand 0 "" "")
4546 (call (mem:DI (match_operand:DI 1 "" ""))
4547 (match_operand 2 "" "")))
4548 (use (match_dup 3))
4549 (use (reg:DI 25))
4550 (use (reg:DI 26))
4551 (clobber (reg:DI 27))])]
4552 ""
4553 {
4554 if (GET_CODE (operands[1]) != MEM)
4555 abort ();
4557 operands[1] = XEXP (operands[1], 0);
4559 /* Always load AI with argument information, then handle symbolic and
4560 indirect call differently. Load RA and set operands[3] to PV in
4561 both cases. */
4563 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4564 if (GET_CODE (operands[1]) == SYMBOL_REF)
4565 {
4566 alpha_need_linkage (XSTR (operands[1], 0), 0);
4568 operands[3] = const0_rtx;
4569 }
4570 else
4571 {
4572 emit_move_insn (gen_rtx_REG (Pmode, 26),
4573 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4574 operands[3] = operands[1];
4575 }
4576 })
4578 (define_expand "call_value_umk"
4579 [(parallel [(set (match_operand 0 "" "")
4580 (call (mem:DI (match_operand 1 "" ""))
4581 (match_operand 2 "" "")))
4582 (use (reg:DI 25))
4583 (clobber (reg:DI 26))])]
4584 ""
4585 {
4586 if (GET_CODE (operands[1]) != MEM)
4587 abort ();
4589 operands[1] = XEXP (operands[1], 0);
4590 if (GET_CODE (operands[1]) != REG)
4591 operands[1] = force_reg (DImode, operands[1]);
4593 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4594 })
4596 (define_insn "*call_osf_1_er"
4597 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4598 (match_operand 1 "" ""))
4599 (use (reg:DI 29))
4600 (clobber (reg:DI 26))]
4601 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4602 "@
4603 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4604 bsr $26,%0\t\t!samegp
4605 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4606 [(set_attr "type" "jsr")
4607 (set_attr "length" "12,*,16")])
4609 ;; We must use peep2 instead of a split because we need accurate life
4610 ;; information for $gp. Consider the case of { bar(); while (1); }.
4611 (define_peephole2
4612 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4613 (match_operand 1 "" ""))
4614 (use (reg:DI 29))
4615 (clobber (reg:DI 26))])]
4616 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4617 && ! samegp_function_operand (operands[0], Pmode)
4618 && peep2_regno_dead_p (1, 29)"
4619 [(parallel [(call (mem:DI (match_dup 2))
4620 (match_dup 1))
4621 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4622 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4623 (use (match_dup 0))
4624 (use (match_dup 3))])]
4625 {
4626 if (CONSTANT_P (operands[0]))
4627 {
4628 operands[2] = gen_rtx_REG (Pmode, 27);
4629 operands[3] = GEN_INT (alpha_next_sequence_number++);
4630 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4631 operands[0], operands[3]));
4632 }
4633 else
4634 {
4635 operands[2] = operands[0];
4636 operands[0] = const0_rtx;
4637 operands[3] = const0_rtx;
4638 }
4639 })
4641 (define_peephole2
4642 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4643 (match_operand 1 "" ""))
4644 (use (reg:DI 29))
4645 (clobber (reg:DI 26))])]
4646 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4647 && ! samegp_function_operand (operands[0], Pmode)
4648 && ! peep2_regno_dead_p (1, 29)"
4649 [(parallel [(call (mem:DI (match_dup 2))
4650 (match_dup 1))
4651 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4652 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4653 (use (match_dup 0))
4654 (use (match_dup 4))])
4655 (set (reg:DI 29)
4656 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4657 (set (reg:DI 29)
4658 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4659 {
4660 if (CONSTANT_P (operands[0]))
4661 {
4662 operands[2] = gen_rtx_REG (Pmode, 27);
4663 operands[4] = GEN_INT (alpha_next_sequence_number++);
4664 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4665 operands[0], operands[4]));
4666 }
4667 else
4668 {
4669 operands[2] = operands[0];
4670 operands[0] = const0_rtx;
4671 operands[4] = const0_rtx;
4672 }
4673 operands[3] = GEN_INT (alpha_next_sequence_number++);
4674 })
4676 ;; We add a blockage unspec_volatile to prevent insns from moving down
4677 ;; from above the call to in between the call and the ldah gpdisp.
4679 (define_insn "*call_osf_2_er"
4680 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4681 (match_operand 1 "" ""))
4682 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4683 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4684 (use (match_operand 2 "" ""))
4685 (use (match_operand 3 "const_int_operand" ""))]
4686 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4687 "jsr $26,(%0),%2%J3"
4688 [(set_attr "type" "jsr")])
4690 (define_insn "*call_osf_1_noreturn"
4691 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4692 (match_operand 1 "" ""))
4693 (use (reg:DI 29))
4694 (clobber (reg:DI 26))]
4695 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4696 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4697 "@
4698 jsr $26,($27),0
4699 bsr $26,$%0..ng
4700 jsr $26,%0"
4701 [(set_attr "type" "jsr")
4702 (set_attr "length" "*,*,8")])
4704 (define_insn "*call_osf_1"
4705 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4706 (match_operand 1 "" ""))
4707 (use (reg:DI 29))
4708 (clobber (reg:DI 26))]
4709 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4710 "@
4711 jsr $26,($27),0\;ldgp $29,0($26)
4712 bsr $26,$%0..ng
4713 jsr $26,%0\;ldgp $29,0($26)"
4714 [(set_attr "type" "jsr")
4715 (set_attr "length" "12,*,16")])
4717 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4718 ;; doesn't do what we want.
4719 (define_insn "*sibcall_osf_1_er"
4720 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4721 (match_operand 1 "" ""))
4722 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4723 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4724 "@
4725 br $31,%0\t\t!samegp
4726 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4727 [(set_attr "type" "jsr")
4728 (set_attr "length" "*,8")])
4730 (define_insn "*sibcall_osf_1"
4731 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4732 (match_operand 1 "" ""))
4733 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4734 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4735 "@
4736 br $31,$%0..ng
4737 lda $27,%0\;jmp $31,($27),%0"
4738 [(set_attr "type" "jsr")
4739 (set_attr "length" "*,8")])
4741 (define_insn "*call_nt_1"
4742 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4743 (match_operand 1 "" ""))
4744 (clobber (reg:DI 26))]
4745 "TARGET_ABI_WINDOWS_NT"
4746 "@
4747 jsr $26,(%0)
4748 bsr $26,%0
4749 jsr $26,%0"
4750 [(set_attr "type" "jsr")
4751 (set_attr "length" "*,*,12")])
4753 ; GAS relies on the order and position of instructions output below in order
4754 ; to generate relocs for VMS link to potentially optimize the call.
4755 ; Please do not molest.
4756 (define_insn "*call_vms_1"
4757 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4758 (match_operand 1 "" ""))
4759 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4760 (use (reg:DI 25))
4761 (use (reg:DI 26))
4762 (clobber (reg:DI 27))]
4763 "TARGET_ABI_OPEN_VMS"
4764 {
4765 switch (which_alternative)
4766 {
4767 case 0:
4768 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4769 case 1:
4770 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4771 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4772 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4773 default:
4774 abort();
4775 }
4776 }
4777 [(set_attr "type" "jsr")
4778 (set_attr "length" "12,16")])
4780 (define_insn "*call_umk_1"
4781 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4782 (match_operand 1 "" ""))
4783 (use (reg:DI 25))
4784 (clobber (reg:DI 26))]
4785 "TARGET_ABI_UNICOSMK"
4786 "jsr $26,(%0)"
4787 [(set_attr "type" "jsr")])
4789 ;; Call subroutine returning any type.
4791 (define_expand "untyped_call"
4792 [(parallel [(call (match_operand 0 "" "")
4793 (const_int 0))
4794 (match_operand 1 "" "")
4795 (match_operand 2 "" "")])]
4796 ""
4797 {
4798 int i;
4800 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4802 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4803 {
4804 rtx set = XVECEXP (operands[2], 0, i);
4805 emit_move_insn (SET_DEST (set), SET_SRC (set));
4806 }
4808 /* The optimizer does not know that the call sets the function value
4809 registers we stored in the result block. We avoid problems by
4810 claiming that all hard registers are used and clobbered at this
4811 point. */
4812 emit_insn (gen_blockage ());
4814 DONE;
4815 })
4817 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4818 ;; all of memory. This blocks insns from being moved across this point.
4820 (define_insn "blockage"
4821 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4822 ""
4823 ""
4824 [(set_attr "length" "0")
4825 (set_attr "type" "none")])
4827 (define_insn "jump"
4828 [(set (pc)
4829 (label_ref (match_operand 0 "" "")))]
4830 ""
4831 "br $31,%l0"
4832 [(set_attr "type" "ibr")])
4834 (define_expand "return"
4835 [(return)]
4836 "direct_return ()"
4837 "")
4839 (define_insn "*return_internal"
4840 [(return)]
4841 "reload_completed"
4842 "ret $31,($26),1"
4843 [(set_attr "type" "ibr")])
4845 (define_insn "indirect_jump"
4846 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4847 ""
4848 "jmp $31,(%0),0"
4849 [(set_attr "type" "ibr")])
4851 (define_expand "tablejump"
4852 [(parallel [(set (pc)
4853 (match_operand 0 "register_operand" ""))
4854 (use (label_ref:DI (match_operand 1 "" "")))])]
4855 ""
4856 {
4857 if (TARGET_ABI_WINDOWS_NT)
4858 {
4859 rtx dest = gen_reg_rtx (DImode);
4860 emit_insn (gen_extendsidi2 (dest, operands[0]));
4861 operands[0] = dest;
4862 }
4863 else if (TARGET_ABI_OSF)
4864 {
4865 rtx dest = gen_reg_rtx (DImode);
4866 emit_insn (gen_extendsidi2 (dest, operands[0]));
4867 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4868 operands[0] = dest;
4869 }
4870 })
4872 (define_insn "*tablejump_osf_nt_internal"
4873 [(set (pc)
4874 (match_operand:DI 0 "register_operand" "r"))
4875 (use (label_ref:DI (match_operand 1 "" "")))]
4876 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4877 && alpha_tablejump_addr_vec (insn)"
4878 {
4879 operands[2] = alpha_tablejump_best_label (insn);
4880 return "jmp $31,(%0),%2";
4881 }
4882 [(set_attr "type" "ibr")])
4884 (define_insn "*tablejump_internal"
4885 [(set (pc)
4886 (match_operand:DI 0 "register_operand" "r"))
4887 (use (label_ref (match_operand 1 "" "")))]
4888 ""
4889 "jmp $31,(%0),0"
4890 [(set_attr "type" "ibr")])
4892 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4893 ;; want to have to include pal.h in our .s file.
4894 ;;
4895 ;; Technically the type for call_pal is jsr, but we use that for determining
4896 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4897 ;; characteristics.
4898 (define_insn "imb"
4899 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4900 ""
4901 "call_pal 0x86"
4902 [(set_attr "type" "callpal")])
4904 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4905 ;; NT does not document anything at 0x81 -- presumably it would generate
4906 ;; the equivalent of SIGILL, but this isn't that important.
4907 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4908 (define_insn "trap"
4909 [(trap_if (const_int 1) (const_int 0))]
4910 "!TARGET_ABI_WINDOWS_NT"
4911 "call_pal 0x81"
4912 [(set_attr "type" "callpal")])
4914 ;; For userland, we load the thread pointer from the TCB.
4915 ;; For the kernel, we load the per-cpu private value.
4917 (define_insn "load_tp"
4918 [(set (match_operand:DI 0 "register_operand" "=v")
4919 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4920 "TARGET_ABI_OSF"
4921 {
4922 if (TARGET_TLS_KERNEL)
4923 return "call_pal 0x32";
4924 else
4925 return "call_pal 0x9e";
4926 }
4927 [(set_attr "type" "callpal")])
4929 ;; For completeness, and possibly a __builtin function, here's how to
4930 ;; set the thread pointer. Since we don't describe enough of this
4931 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4932 ;; not much point in creating an R16_REG register class.
4934 (define_expand "set_tp"
4935 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4936 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4937 "TARGET_ABI_OSF"
4938 "")
4940 (define_insn "*set_tp"
4941 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4942 "TARGET_ABI_OSF"
4943 {
4944 if (TARGET_TLS_KERNEL)
4945 return "call_pal 0x31";
4946 else
4947 return "call_pal 0x9f";
4948 }
4949 [(set_attr "type" "callpal")])
4950 \f
4951 ;; Finally, we have the basic data motion insns. The byte and word insns
4952 ;; are done via define_expand. Start with the floating-point insns, since
4953 ;; they are simpler.
4955 (define_insn "*movsf_nofix"
4956 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4957 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4958 "TARGET_FPREGS && ! TARGET_FIX
4959 && (register_operand (operands[0], SFmode)
4960 || reg_or_0_operand (operands[1], SFmode))"
4961 "@
4962 cpys %R1,%R1,%0
4963 ld%, %0,%1
4964 bis $31,%r1,%0
4965 ldl %0,%1
4966 st%, %R1,%0
4967 stl %r1,%0"
4968 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4970 (define_insn "*movsf_fix"
4971 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4972 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4973 "TARGET_FPREGS && TARGET_FIX
4974 && (register_operand (operands[0], SFmode)
4975 || reg_or_0_operand (operands[1], SFmode))"
4976 "@
4977 cpys %R1,%R1,%0
4978 ld%, %0,%1
4979 bis $31,%r1,%0
4980 ldl %0,%1
4981 st%, %R1,%0
4982 stl %r1,%0
4983 itofs %1,%0
4984 ftois %1,%0"
4985 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4987 (define_insn "*movsf_nofp"
4988 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4989 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4990 "! TARGET_FPREGS
4991 && (register_operand (operands[0], SFmode)
4992 || reg_or_0_operand (operands[1], SFmode))"
4993 "@
4994 bis $31,%r1,%0
4995 ldl %0,%1
4996 stl %r1,%0"
4997 [(set_attr "type" "ilog,ild,ist")])
4999 (define_insn "*movdf_nofix"
5000 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5001 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5002 "TARGET_FPREGS && ! TARGET_FIX
5003 && (register_operand (operands[0], DFmode)
5004 || reg_or_0_operand (operands[1], DFmode))"
5005 "@
5006 cpys %R1,%R1,%0
5007 ld%- %0,%1
5008 bis $31,%r1,%0
5009 ldq %0,%1
5010 st%- %R1,%0
5011 stq %r1,%0"
5012 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5014 (define_insn "*movdf_fix"
5015 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5016 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5017 "TARGET_FPREGS && TARGET_FIX
5018 && (register_operand (operands[0], DFmode)
5019 || reg_or_0_operand (operands[1], DFmode))"
5020 "@
5021 cpys %R1,%R1,%0
5022 ld%- %0,%1
5023 bis $31,%r1,%0
5024 ldq %0,%1
5025 st%- %R1,%0
5026 stq %r1,%0
5027 itoft %1,%0
5028 ftoit %1,%0"
5029 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5031 (define_insn "*movdf_nofp"
5032 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5033 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5034 "! TARGET_FPREGS
5035 && (register_operand (operands[0], DFmode)
5036 || reg_or_0_operand (operands[1], DFmode))"
5037 "@
5038 bis $31,%r1,%0
5039 ldq %0,%1
5040 stq %r1,%0"
5041 [(set_attr "type" "ilog,ild,ist")])
5043 ;; Subregs suck for register allocation. Pretend we can move TFmode
5044 ;; data between general registers until after reload.
5046 (define_insn_and_split "*movtf_internal"
5047 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5048 (match_operand:TF 1 "input_operand" "roG,rG"))]
5049 "register_operand (operands[0], TFmode)
5050 || reg_or_0_operand (operands[1], TFmode)"
5051 "#"
5052 "reload_completed"
5053 [(set (match_dup 0) (match_dup 2))
5054 (set (match_dup 1) (match_dup 3))]
5055 {
5056 alpha_split_tfmode_pair (operands);
5057 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5058 {
5059 rtx tmp;
5060 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5061 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5062 }
5063 })
5065 (define_expand "movsf"
5066 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5067 (match_operand:SF 1 "general_operand" ""))]
5068 ""
5069 {
5070 if (GET_CODE (operands[0]) == MEM
5071 && ! reg_or_0_operand (operands[1], SFmode))
5072 operands[1] = force_reg (SFmode, operands[1]);
5073 })
5075 (define_expand "movdf"
5076 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5077 (match_operand:DF 1 "general_operand" ""))]
5078 ""
5079 {
5080 if (GET_CODE (operands[0]) == MEM
5081 && ! reg_or_0_operand (operands[1], DFmode))
5082 operands[1] = force_reg (DFmode, operands[1]);
5083 })
5085 (define_expand "movtf"
5086 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5087 (match_operand:TF 1 "general_operand" ""))]
5088 ""
5089 {
5090 if (GET_CODE (operands[0]) == MEM
5091 && ! reg_or_0_operand (operands[1], TFmode))
5092 operands[1] = force_reg (TFmode, operands[1]);
5093 })
5095 (define_insn "*movsi_nofix"
5096 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5097 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5098 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5099 && (register_operand (operands[0], SImode)
5100 || reg_or_0_operand (operands[1], SImode))"
5101 "@
5102 bis $31,%r1,%0
5103 lda %0,%1($31)
5104 ldah %0,%h1($31)
5105 ldl %0,%1
5106 stl %r1,%0
5107 cpys %R1,%R1,%0
5108 ld%, %0,%1
5109 st%, %R1,%0"
5110 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5112 (define_insn "*movsi_fix"
5113 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5114 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5115 "TARGET_ABI_OSF && TARGET_FIX
5116 && (register_operand (operands[0], SImode)
5117 || reg_or_0_operand (operands[1], SImode))"
5118 "@
5119 bis $31,%r1,%0
5120 lda %0,%1($31)
5121 ldah %0,%h1($31)
5122 ldl %0,%1
5123 stl %r1,%0
5124 cpys %R1,%R1,%0
5125 ld%, %0,%1
5126 st%, %R1,%0
5127 ftois %1,%0
5128 itofs %1,%0"
5129 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5131 (define_insn "*movsi_nt_vms_nofix"
5132 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5133 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5134 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5135 && !TARGET_FIX
5136 && (register_operand (operands[0], SImode)
5137 || reg_or_0_operand (operands[1], SImode))"
5138 "@
5139 bis $31,%1,%0
5140 lda %0,%1
5141 ldah %0,%h1
5142 lda %0,%1
5143 ldl %0,%1
5144 stl %r1,%0
5145 cpys %R1,%R1,%0
5146 ld%, %0,%1
5147 st%, %R1,%0"
5148 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5150 (define_insn "*movsi_nt_vms_fix"
5151 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5152 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5153 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5154 && TARGET_FIX
5155 && (register_operand (operands[0], SImode)
5156 || reg_or_0_operand (operands[1], SImode))"
5157 "@
5158 bis $31,%1,%0
5159 lda %0,%1
5160 ldah %0,%h1
5161 lda %0,%1
5162 ldl %0,%1
5163 stl %r1,%0
5164 cpys %R1,%R1,%0
5165 ld%, %0,%1
5166 st%, %R1,%0
5167 ftois %1,%0
5168 itofs %1,%0"
5169 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5171 (define_insn "*movhi_nobwx"
5172 [(set (match_operand:HI 0 "register_operand" "=r,r")
5173 (match_operand:HI 1 "input_operand" "rJ,n"))]
5174 "! TARGET_BWX
5175 && (register_operand (operands[0], HImode)
5176 || register_operand (operands[1], HImode))"
5177 "@
5178 bis $31,%r1,%0
5179 lda %0,%L1($31)"
5180 [(set_attr "type" "ilog,iadd")])
5182 (define_insn "*movhi_bwx"
5183 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5184 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5185 "TARGET_BWX
5186 && (register_operand (operands[0], HImode)
5187 || reg_or_0_operand (operands[1], HImode))"
5188 "@
5189 bis $31,%r1,%0
5190 lda %0,%L1($31)
5191 ldwu %0,%1
5192 stw %r1,%0"
5193 [(set_attr "type" "ilog,iadd,ild,ist")])
5195 (define_insn "*movqi_nobwx"
5196 [(set (match_operand:QI 0 "register_operand" "=r,r")
5197 (match_operand:QI 1 "input_operand" "rJ,n"))]
5198 "! TARGET_BWX
5199 && (register_operand (operands[0], QImode)
5200 || register_operand (operands[1], QImode))"
5201 "@
5202 bis $31,%r1,%0
5203 lda %0,%L1($31)"
5204 [(set_attr "type" "ilog,iadd")])
5206 (define_insn "*movqi_bwx"
5207 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5208 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5209 "TARGET_BWX
5210 && (register_operand (operands[0], QImode)
5211 || reg_or_0_operand (operands[1], QImode))"
5212 "@
5213 bis $31,%r1,%0
5214 lda %0,%L1($31)
5215 ldbu %0,%1
5216 stb %r1,%0"
5217 [(set_attr "type" "ilog,iadd,ild,ist")])
5219 ;; We do two major things here: handle mem->mem and construct long
5220 ;; constants.
5222 (define_expand "movsi"
5223 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5224 (match_operand:SI 1 "general_operand" ""))]
5225 ""
5226 {
5227 if (alpha_expand_mov (SImode, operands))
5228 DONE;
5229 })
5231 ;; Split a load of a large constant into the appropriate two-insn
5232 ;; sequence.
5234 (define_split
5235 [(set (match_operand:SI 0 "register_operand" "")
5236 (match_operand:SI 1 "const_int_operand" ""))]
5237 "! add_operand (operands[1], SImode)"
5238 [(set (match_dup 0) (match_dup 2))
5239 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5240 {
5241 rtx tem
5242 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5244 if (tem == operands[0])
5245 DONE;
5246 else
5247 FAIL;
5248 })
5250 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5251 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5252 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5253 ;; notes and update LABEL_NUSES because this is not done automatically.
5254 ;; Labels may be incorrectly deleted if we don't do this.
5255 ;;
5256 ;; Describing what the individual instructions do correctly is too complicated
5257 ;; so use UNSPECs for each of the three parts of an address.
5259 (define_split
5260 [(set (match_operand:DI 0 "register_operand" "")
5261 (match_operand:DI 1 "symbolic_operand" ""))]
5262 "TARGET_ABI_UNICOSMK && reload_completed"
5263 [(const_int 0)]
5264 {
5265 rtx insn1, insn2, insn3;
5267 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5268 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5269 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5270 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5271 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5272 REG_NOTES (insn3));
5273 if (GET_CODE (operands[1]) == LABEL_REF)
5274 {
5275 rtx label;
5277 label = XEXP (operands[1], 0);
5278 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5279 REG_NOTES (insn1));
5280 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5281 REG_NOTES (insn2));
5282 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5283 REG_NOTES (insn3));
5284 LABEL_NUSES (label) += 3;
5285 }
5286 DONE;
5287 })
5289 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5291 (define_insn "umk_laum"
5292 [(set (match_operand:DI 0 "register_operand" "=r")
5293 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5294 UNSPEC_UMK_LAUM))]
5295 "TARGET_ABI_UNICOSMK"
5296 "laum %r0,%t1($31)"
5297 [(set_attr "type" "iadd")])
5299 (define_insn "umk_lalm"
5300 [(set (match_operand:DI 0 "register_operand" "=r")
5301 (plus:DI (match_operand:DI 1 "register_operand" "r")
5302 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5303 UNSPEC_UMK_LALM)))]
5304 "TARGET_ABI_UNICOSMK"
5305 "lalm %r0,%t2(%r1)"
5306 [(set_attr "type" "iadd")])
5308 (define_insn "umk_lal"
5309 [(set (match_operand:DI 0 "register_operand" "=r")
5310 (plus:DI (match_operand:DI 1 "register_operand" "r")
5311 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5312 UNSPEC_UMK_LAL)))]
5313 "TARGET_ABI_UNICOSMK"
5314 "lal %r0,%t2(%r1)"
5315 [(set_attr "type" "iadd")])
5317 ;; Add a new call information word to the current function's list of CIWs
5318 ;; and load its index into $25. Doing it here ensures that the CIW will be
5319 ;; associated with the correct function even in the presence of inlining.
5321 (define_insn "*umk_load_ciw"
5322 [(set (reg:DI 25)
5323 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5324 "TARGET_ABI_UNICOSMK"
5325 {
5326 operands[0] = unicosmk_add_call_info_word (operands[0]);
5327 return "lda $25,%0";
5328 }
5329 [(set_attr "type" "iadd")])
5331 (define_insn "*movdi_er_low_l"
5332 [(set (match_operand:DI 0 "register_operand" "=r")
5333 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5334 (match_operand:DI 2 "local_symbolic_operand" "")))]
5335 "TARGET_EXPLICIT_RELOCS"
5336 {
5337 if (true_regnum (operands[1]) == 29)
5338 return "lda %0,%2(%1)\t\t!gprel";
5339 else
5340 return "lda %0,%2(%1)\t\t!gprellow";
5341 }
5342 [(set_attr "usegp" "yes")])
5344 (define_split
5345 [(set (match_operand:DI 0 "register_operand" "")
5346 (match_operand:DI 1 "small_symbolic_operand" ""))]
5347 "TARGET_EXPLICIT_RELOCS && reload_completed"
5348 [(set (match_dup 0)
5349 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5350 "operands[2] = pic_offset_table_rtx;")
5352 (define_split
5353 [(set (match_operand:DI 0 "register_operand" "")
5354 (match_operand:DI 1 "local_symbolic_operand" ""))]
5355 "TARGET_EXPLICIT_RELOCS && reload_completed"
5356 [(set (match_dup 0)
5357 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5358 (set (match_dup 0)
5359 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5360 "operands[2] = pic_offset_table_rtx;")
5362 (define_split
5363 [(match_operand 0 "some_small_symbolic_operand" "")]
5364 "TARGET_EXPLICIT_RELOCS && reload_completed"
5365 [(match_dup 0)]
5366 "operands[0] = split_small_symbolic_operand (operands[0]);")
5368 ;; Accepts any symbolic, not just global, since function calls that
5369 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5370 (define_insn "movdi_er_high_g"
5371 [(set (match_operand:DI 0 "register_operand" "=r")
5372 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5373 (match_operand:DI 2 "symbolic_operand" "")
5374 (match_operand 3 "const_int_operand" "")]
5375 UNSPEC_LITERAL))]
5376 "TARGET_EXPLICIT_RELOCS"
5377 {
5378 if (INTVAL (operands[3]) == 0)
5379 return "ldq %0,%2(%1)\t\t!literal";
5380 else
5381 return "ldq %0,%2(%1)\t\t!literal!%3";
5382 }
5383 [(set_attr "type" "ldsym")])
5385 (define_split
5386 [(set (match_operand:DI 0 "register_operand" "")
5387 (match_operand:DI 1 "global_symbolic_operand" ""))]
5388 "TARGET_EXPLICIT_RELOCS && reload_completed"
5389 [(set (match_dup 0)
5390 (unspec:DI [(match_dup 2)
5391 (match_dup 1)
5392 (const_int 0)] UNSPEC_LITERAL))]
5393 "operands[2] = pic_offset_table_rtx;")
5395 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5396 ;; compiled at the end of compilation. In the meantime, someone can
5397 ;; re-encode-section-info on some symbol changing it e.g. from global
5398 ;; to local-not-small. If this happens, we'd have emitted a plain
5399 ;; load rather than a high+losum load and not recognize the insn.
5400 ;;
5401 ;; So if rtl inlining is in effect, we delay the global/not-global
5402 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5404 (define_insn_and_split "movdi_er_maybe_g"
5405 [(set (match_operand:DI 0 "register_operand" "=r")
5406 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5407 UNSPEC_SYMBOL))]
5408 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5409 "#"
5410 ""
5411 [(set (match_dup 0) (match_dup 1))]
5412 {
5413 if (local_symbolic_operand (operands[1], Pmode)
5414 && !small_symbolic_operand (operands[1], Pmode))
5415 {
5416 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5417 rtx tmp;
5419 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5420 if (reload_completed)
5421 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5422 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5424 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5425 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5426 DONE;
5427 }
5428 })
5430 (define_insn "movdi_er_tlsgd"
5431 [(set (match_operand:DI 0 "register_operand" "=r")
5432 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5433 (match_operand:DI 2 "symbolic_operand" "")
5434 (match_operand 3 "const_int_operand" "")]
5435 UNSPEC_TLSGD))]
5436 "HAVE_AS_TLS"
5437 {
5438 if (INTVAL (operands[3]) == 0)
5439 return "lda %0,%2(%1)\t\t!tlsgd";
5440 else
5441 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5442 })
5444 (define_insn "movdi_er_tlsldm"
5445 [(set (match_operand:DI 0 "register_operand" "=r")
5446 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5447 (match_operand 2 "const_int_operand" "")]
5448 UNSPEC_TLSLDM))]
5449 "HAVE_AS_TLS"
5450 {
5451 if (INTVAL (operands[2]) == 0)
5452 return "lda %0,%&(%1)\t\t!tlsldm";
5453 else
5454 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5455 })
5457 (define_insn "*movdi_er_gotdtp"
5458 [(set (match_operand:DI 0 "register_operand" "=r")
5459 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5460 (match_operand:DI 2 "symbolic_operand" "")]
5461 UNSPEC_DTPREL))]
5462 "HAVE_AS_TLS"
5463 "ldq %0,%2(%1)\t\t!gotdtprel"
5464 [(set_attr "type" "ild")
5465 (set_attr "usegp" "yes")])
5467 (define_split
5468 [(set (match_operand:DI 0 "register_operand" "")
5469 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5470 "HAVE_AS_TLS && reload_completed"
5471 [(set (match_dup 0)
5472 (unspec:DI [(match_dup 2)
5473 (match_dup 1)] UNSPEC_DTPREL))]
5474 {
5475 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5476 operands[2] = pic_offset_table_rtx;
5477 })
5479 (define_insn "*movdi_er_gottp"
5480 [(set (match_operand:DI 0 "register_operand" "=r")
5481 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5482 (match_operand:DI 2 "symbolic_operand" "")]
5483 UNSPEC_TPREL))]
5484 "HAVE_AS_TLS"
5485 "ldq %0,%2(%1)\t\t!gottprel"
5486 [(set_attr "type" "ild")
5487 (set_attr "usegp" "yes")])
5489 (define_split
5490 [(set (match_operand:DI 0 "register_operand" "")
5491 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5492 "HAVE_AS_TLS && reload_completed"
5493 [(set (match_dup 0)
5494 (unspec:DI [(match_dup 2)
5495 (match_dup 1)] UNSPEC_TPREL))]
5496 {
5497 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5498 operands[2] = pic_offset_table_rtx;
5499 })
5501 (define_insn "*movdi_er_nofix"
5502 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5503 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5504 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5505 && (register_operand (operands[0], DImode)
5506 || reg_or_0_operand (operands[1], DImode))"
5507 "@
5508 mov %r1,%0
5509 lda %0,%1($31)
5510 ldah %0,%h1($31)
5511 #
5512 #
5513 ldq%A1 %0,%1
5514 stq%A0 %r1,%0
5515 fmov %R1,%0
5516 ldt %0,%1
5517 stt %R1,%0"
5518 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")
5519 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")])
5521 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5522 ;; have been split up by the rules above but we shouldn't reject the
5523 ;; possibility of them getting through.
5525 (define_insn "*movdi_nofix"
5526 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5527 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5528 "! TARGET_FIX
5529 && (register_operand (operands[0], DImode)
5530 || reg_or_0_operand (operands[1], DImode))"
5531 "@
5532 bis $31,%r1,%0
5533 lda %0,%1($31)
5534 ldah %0,%h1($31)
5535 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5536 lda %0,%1
5537 ldq%A1 %0,%1
5538 stq%A0 %r1,%0
5539 cpys %R1,%R1,%0
5540 ldt %0,%1
5541 stt %R1,%0"
5542 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5543 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5545 (define_insn "*movdi_er_fix"
5546 [(set (match_operand:DI 0 "nonimmediate_operand"
5547 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5548 (match_operand:DI 1 "input_operand"
5549 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5550 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5551 && (register_operand (operands[0], DImode)
5552 || reg_or_0_operand (operands[1], DImode))"
5553 "@
5554 mov %r1,%0
5555 lda %0,%1($31)
5556 ldah %0,%h1($31)
5557 #
5558 #
5559 ldq%A1 %0,%1
5560 stq%A0 %r1,%0
5561 fmov %R1,%0
5562 ldt %0,%1
5563 stt %R1,%0
5564 ftoit %1,%0
5565 itoft %1,%0"
5566 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
5567 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")])
5569 (define_insn "*movdi_fix"
5570 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5571 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5572 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5573 && (register_operand (operands[0], DImode)
5574 || reg_or_0_operand (operands[1], DImode))"
5575 "@
5576 bis $31,%r1,%0
5577 lda %0,%1($31)
5578 ldah %0,%h1($31)
5579 lda %0,%1
5580 ldq%A1 %0,%1
5581 stq%A0 %r1,%0
5582 cpys %R1,%R1,%0
5583 ldt %0,%1
5584 stt %R1,%0
5585 ftoit %1,%0
5586 itoft %1,%0"
5587 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5589 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5590 ;; often appears dead to the life analysis code, at which point we
5591 ;; abort for emitting dead prologue instructions. Force this live.
5593 (define_insn "force_movdi"
5594 [(set (match_operand:DI 0 "register_operand" "=r")
5595 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5596 UNSPECV_FORCE_MOV))]
5597 ""
5598 "mov %1,%0"
5599 [(set_attr "type" "ilog")])
5601 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5602 ;; memory, and construct long 32-bit constants.
5604 (define_expand "movdi"
5605 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5606 (match_operand:DI 1 "general_operand" ""))]
5607 ""
5608 {
5609 if (alpha_expand_mov (DImode, operands))
5610 DONE;
5611 })
5613 ;; Split a load of a large constant into the appropriate two-insn
5614 ;; sequence.
5616 (define_split
5617 [(set (match_operand:DI 0 "register_operand" "")
5618 (match_operand:DI 1 "const_int_operand" ""))]
5619 "! add_operand (operands[1], DImode)"
5620 [(set (match_dup 0) (match_dup 2))
5621 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5622 {
5623 rtx tem
5624 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5626 if (tem == operands[0])
5627 DONE;
5628 else
5629 FAIL;
5630 })
5632 ;; These are the partial-word cases.
5633 ;;
5634 ;; First we have the code to load an aligned word. Operand 0 is the register
5635 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5636 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5637 ;; number of bits within the word that the value is. Operand 3 is an SImode
5638 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5639 ;; same register. It is allowed to conflict with operand 1 as well.
5641 (define_expand "aligned_loadqi"
5642 [(set (match_operand:SI 3 "register_operand" "")
5643 (match_operand:SI 1 "memory_operand" ""))
5644 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5645 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5646 (const_int 8)
5647 (match_operand:DI 2 "const_int_operand" "")))]
5649 ""
5650 "")
5652 (define_expand "aligned_loadhi"
5653 [(set (match_operand:SI 3 "register_operand" "")
5654 (match_operand:SI 1 "memory_operand" ""))
5655 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5656 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5657 (const_int 16)
5658 (match_operand:DI 2 "const_int_operand" "")))]
5660 ""
5661 "")
5663 ;; Similar for unaligned loads, where we use the sequence from the
5664 ;; Alpha Architecture manual. We have to distinguish between little-endian
5665 ;; and big-endian systems as the sequences are different.
5666 ;;
5667 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5668 ;; operand 3 can overlap the input and output registers.
5670 (define_expand "unaligned_loadqi"
5671 [(use (match_operand:QI 0 "register_operand" ""))
5672 (use (match_operand:DI 1 "address_operand" ""))
5673 (use (match_operand:DI 2 "register_operand" ""))
5674 (use (match_operand:DI 3 "register_operand" ""))]
5675 ""
5676 {
5677 if (WORDS_BIG_ENDIAN)
5678 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5679 operands[2], operands[3]));
5680 else
5681 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5682 operands[2], operands[3]));
5683 DONE;
5684 })
5686 (define_expand "unaligned_loadqi_le"
5687 [(set (match_operand:DI 2 "register_operand" "")
5688 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5689 (const_int -8))))
5690 (set (match_operand:DI 3 "register_operand" "")
5691 (match_dup 1))
5692 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5693 (zero_extract:DI (match_dup 2)
5694 (const_int 8)
5695 (ashift:DI (match_dup 3) (const_int 3))))]
5696 "! WORDS_BIG_ENDIAN"
5697 "")
5699 (define_expand "unaligned_loadqi_be"
5700 [(set (match_operand:DI 2 "register_operand" "")
5701 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5702 (const_int -8))))
5703 (set (match_operand:DI 3 "register_operand" "")
5704 (match_dup 1))
5705 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5706 (zero_extract:DI (match_dup 2)
5707 (const_int 8)
5708 (minus:DI
5709 (const_int 56)
5710 (ashift:DI (match_dup 3) (const_int 3)))))]
5711 "WORDS_BIG_ENDIAN"
5712 "")
5714 (define_expand "unaligned_loadhi"
5715 [(use (match_operand:QI 0 "register_operand" ""))
5716 (use (match_operand:DI 1 "address_operand" ""))
5717 (use (match_operand:DI 2 "register_operand" ""))
5718 (use (match_operand:DI 3 "register_operand" ""))]
5719 ""
5720 {
5721 if (WORDS_BIG_ENDIAN)
5722 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5723 operands[2], operands[3]));
5724 else
5725 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5726 operands[2], operands[3]));
5727 DONE;
5728 })
5730 (define_expand "unaligned_loadhi_le"
5731 [(set (match_operand:DI 2 "register_operand" "")
5732 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5733 (const_int -8))))
5734 (set (match_operand:DI 3 "register_operand" "")
5735 (match_dup 1))
5736 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5737 (zero_extract:DI (match_dup 2)
5738 (const_int 16)
5739 (ashift:DI (match_dup 3) (const_int 3))))]
5740 "! WORDS_BIG_ENDIAN"
5741 "")
5743 (define_expand "unaligned_loadhi_be"
5744 [(set (match_operand:DI 2 "register_operand" "")
5745 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5746 (const_int -8))))
5747 (set (match_operand:DI 3 "register_operand" "")
5748 (plus:DI (match_dup 1) (const_int 1)))
5749 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5750 (zero_extract:DI (match_dup 2)
5751 (const_int 16)
5752 (minus:DI
5753 (const_int 56)
5754 (ashift:DI (match_dup 3) (const_int 3)))))]
5755 "WORDS_BIG_ENDIAN"
5756 "")
5758 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5759 ;; aligned SImode MEM. Operand 1 is the register containing the
5760 ;; byte or word to store. Operand 2 is the number of bits within the word that
5761 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5763 (define_expand "aligned_store"
5764 [(set (match_operand:SI 3 "register_operand" "")
5765 (match_operand:SI 0 "memory_operand" ""))
5766 (set (subreg:DI (match_dup 3) 0)
5767 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5768 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5769 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5770 (match_operand:DI 2 "const_int_operand" "")))
5771 (set (subreg:DI (match_dup 4) 0)
5772 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5773 (set (match_dup 0) (match_dup 4))]
5774 ""
5775 {
5776 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5777 << INTVAL (operands[2])));
5778 })
5780 ;; For the unaligned byte and halfword cases, we use code similar to that
5781 ;; in the ;; Architecture book, but reordered to lower the number of registers
5782 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5783 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5784 ;; be the same temporary, if desired. If the address is in a register,
5785 ;; operand 2 can be that register.
5787 (define_expand "unaligned_storeqi"
5788 [(use (match_operand:DI 0 "address_operand" ""))
5789 (use (match_operand:QI 1 "register_operand" ""))
5790 (use (match_operand:DI 2 "register_operand" ""))
5791 (use (match_operand:DI 3 "register_operand" ""))
5792 (use (match_operand:DI 4 "register_operand" ""))]
5793 ""
5794 {
5795 if (WORDS_BIG_ENDIAN)
5796 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5797 operands[2], operands[3],
5798 operands[4]));
5799 else
5800 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5801 operands[2], operands[3],
5802 operands[4]));
5803 DONE;
5804 })
5806 (define_expand "unaligned_storeqi_le"
5807 [(set (match_operand:DI 3 "register_operand" "")
5808 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5809 (const_int -8))))
5810 (set (match_operand:DI 2 "register_operand" "")
5811 (match_dup 0))
5812 (set (match_dup 3)
5813 (and:DI (not:DI (ashift:DI (const_int 255)
5814 (ashift:DI (match_dup 2) (const_int 3))))
5815 (match_dup 3)))
5816 (set (match_operand:DI 4 "register_operand" "")
5817 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5818 (ashift:DI (match_dup 2) (const_int 3))))
5819 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5820 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5821 (match_dup 4))]
5822 "! WORDS_BIG_ENDIAN"
5823 "")
5825 (define_expand "unaligned_storeqi_be"
5826 [(set (match_operand:DI 3 "register_operand" "")
5827 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5828 (const_int -8))))
5829 (set (match_operand:DI 2 "register_operand" "")
5830 (match_dup 0))
5831 (set (match_dup 3)
5832 (and:DI (not:DI (ashift:DI (const_int 255)
5833 (minus:DI (const_int 56)
5834 (ashift:DI (match_dup 2) (const_int 3)))))
5835 (match_dup 3)))
5836 (set (match_operand:DI 4 "register_operand" "")
5837 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5838 (minus:DI (const_int 56)
5839 (ashift:DI (match_dup 2) (const_int 3)))))
5840 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5841 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5842 (match_dup 4))]
5843 "WORDS_BIG_ENDIAN"
5844 "")
5846 (define_expand "unaligned_storehi"
5847 [(use (match_operand:DI 0 "address_operand" ""))
5848 (use (match_operand:HI 1 "register_operand" ""))
5849 (use (match_operand:DI 2 "register_operand" ""))
5850 (use (match_operand:DI 3 "register_operand" ""))
5851 (use (match_operand:DI 4 "register_operand" ""))]
5852 ""
5853 {
5854 if (WORDS_BIG_ENDIAN)
5855 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5856 operands[2], operands[3],
5857 operands[4]));
5858 else
5859 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5860 operands[2], operands[3],
5861 operands[4]));
5862 DONE;
5863 })
5865 (define_expand "unaligned_storehi_le"
5866 [(set (match_operand:DI 3 "register_operand" "")
5867 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5868 (const_int -8))))
5869 (set (match_operand:DI 2 "register_operand" "")
5870 (match_dup 0))
5871 (set (match_dup 3)
5872 (and:DI (not:DI (ashift:DI (const_int 65535)
5873 (ashift:DI (match_dup 2) (const_int 3))))
5874 (match_dup 3)))
5875 (set (match_operand:DI 4 "register_operand" "")
5876 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5877 (ashift:DI (match_dup 2) (const_int 3))))
5878 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5879 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5880 (match_dup 4))]
5881 "! WORDS_BIG_ENDIAN"
5882 "")
5884 (define_expand "unaligned_storehi_be"
5885 [(set (match_operand:DI 3 "register_operand" "")
5886 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5887 (const_int -8))))
5888 (set (match_operand:DI 2 "register_operand" "")
5889 (plus:DI (match_dup 0) (const_int 1)))
5890 (set (match_dup 3)
5891 (and:DI (not:DI (ashift:DI
5892 (const_int 65535)
5893 (minus:DI (const_int 56)
5894 (ashift:DI (match_dup 2) (const_int 3)))))
5895 (match_dup 3)))
5896 (set (match_operand:DI 4 "register_operand" "")
5897 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5898 (minus:DI (const_int 56)
5899 (ashift:DI (match_dup 2) (const_int 3)))))
5900 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5901 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5902 (match_dup 4))]
5903 "WORDS_BIG_ENDIAN"
5904 "")
5905 \f
5906 ;; Here are the define_expand's for QI and HI moves that use the above
5907 ;; patterns. We have the normal sets, plus the ones that need scratch
5908 ;; registers for reload.
5910 (define_expand "movqi"
5911 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5912 (match_operand:QI 1 "general_operand" ""))]
5913 ""
5914 {
5915 if (TARGET_BWX
5916 ? alpha_expand_mov (QImode, operands)
5917 : alpha_expand_mov_nobwx (QImode, operands))
5918 DONE;
5919 })
5921 (define_expand "movhi"
5922 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5923 (match_operand:HI 1 "general_operand" ""))]
5924 ""
5925 {
5926 if (TARGET_BWX
5927 ? alpha_expand_mov (HImode, operands)
5928 : alpha_expand_mov_nobwx (HImode, operands))
5929 DONE;
5930 })
5932 ;; Here are the versions for reload. Note that in the unaligned cases
5933 ;; we know that the operand must not be a pseudo-register because stack
5934 ;; slots are always aligned references.
5936 (define_expand "reload_inqi"
5937 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5938 (match_operand:QI 1 "any_memory_operand" "m")
5939 (match_operand:TI 2 "register_operand" "=&r")])]
5940 "! TARGET_BWX"
5941 {
5942 rtx scratch, seq;
5944 if (GET_CODE (operands[1]) != MEM)
5945 abort ();
5947 if (aligned_memory_operand (operands[1], QImode))
5948 {
5949 seq = gen_reload_inqi_help (operands[0], operands[1],
5950 gen_rtx_REG (SImode, REGNO (operands[2])));
5951 }
5952 else
5953 {
5954 rtx addr;
5956 /* It is possible that one of the registers we got for operands[2]
5957 might coincide with that of operands[0] (which is why we made
5958 it TImode). Pick the other one to use as our scratch. */
5959 if (REGNO (operands[0]) == REGNO (operands[2]))
5960 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5961 else
5962 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5964 addr = get_unaligned_address (operands[1], 0);
5965 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5966 gen_rtx_REG (DImode, REGNO (operands[0])));
5967 alpha_set_memflags (seq, operands[1]);
5968 }
5969 emit_insn (seq);
5970 DONE;
5971 })
5973 (define_expand "reload_inhi"
5974 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5975 (match_operand:HI 1 "any_memory_operand" "m")
5976 (match_operand:TI 2 "register_operand" "=&r")])]
5977 "! TARGET_BWX"
5978 {
5979 rtx scratch, seq;
5981 if (GET_CODE (operands[1]) != MEM)
5982 abort ();
5984 if (aligned_memory_operand (operands[1], HImode))
5985 {
5986 seq = gen_reload_inhi_help (operands[0], operands[1],
5987 gen_rtx_REG (SImode, REGNO (operands[2])));
5988 }
5989 else
5990 {
5991 rtx addr;
5993 /* It is possible that one of the registers we got for operands[2]
5994 might coincide with that of operands[0] (which is why we made
5995 it TImode). Pick the other one to use as our scratch. */
5996 if (REGNO (operands[0]) == REGNO (operands[2]))
5997 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5998 else
5999 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6001 addr = get_unaligned_address (operands[1], 0);
6002 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
6003 gen_rtx_REG (DImode, REGNO (operands[0])));
6004 alpha_set_memflags (seq, operands[1]);
6005 }
6006 emit_insn (seq);
6007 DONE;
6008 })
6010 (define_expand "reload_outqi"
6011 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6012 (match_operand:QI 1 "register_operand" "r")
6013 (match_operand:TI 2 "register_operand" "=&r")])]
6014 "! TARGET_BWX"
6015 {
6016 if (GET_CODE (operands[0]) != MEM)
6017 abort ();
6019 if (aligned_memory_operand (operands[0], QImode))
6020 {
6021 emit_insn (gen_reload_outqi_help
6022 (operands[0], operands[1],
6023 gen_rtx_REG (SImode, REGNO (operands[2])),
6024 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6025 }
6026 else
6027 {
6028 rtx addr = get_unaligned_address (operands[0], 0);
6029 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6030 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6031 rtx scratch3 = scratch1;
6032 rtx seq;
6034 if (GET_CODE (addr) == REG)
6035 scratch1 = addr;
6037 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6038 scratch2, scratch3);
6039 alpha_set_memflags (seq, operands[0]);
6040 emit_insn (seq);
6041 }
6042 DONE;
6043 })
6045 (define_expand "reload_outhi"
6046 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6047 (match_operand:HI 1 "register_operand" "r")
6048 (match_operand:TI 2 "register_operand" "=&r")])]
6049 "! TARGET_BWX"
6050 {
6051 if (GET_CODE (operands[0]) != MEM)
6052 abort ();
6054 if (aligned_memory_operand (operands[0], HImode))
6055 {
6056 emit_insn (gen_reload_outhi_help
6057 (operands[0], operands[1],
6058 gen_rtx_REG (SImode, REGNO (operands[2])),
6059 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6060 }
6061 else
6062 {
6063 rtx addr = get_unaligned_address (operands[0], 0);
6064 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6065 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6066 rtx scratch3 = scratch1;
6067 rtx seq;
6069 if (GET_CODE (addr) == REG)
6070 scratch1 = addr;
6072 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6073 scratch2, scratch3);
6074 alpha_set_memflags (seq, operands[0]);
6075 emit_insn (seq);
6076 }
6077 DONE;
6078 })
6080 ;; Helpers for the above. The way reload is structured, we can't
6081 ;; always get a proper address for a stack slot during reload_foo
6082 ;; expansion, so we must delay our address manipulations until after.
6084 (define_insn "reload_inqi_help"
6085 [(set (match_operand:QI 0 "register_operand" "=r")
6086 (match_operand:QI 1 "memory_operand" "m"))
6087 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6088 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6089 "#")
6091 (define_insn "reload_inhi_help"
6092 [(set (match_operand:HI 0 "register_operand" "=r")
6093 (match_operand:HI 1 "memory_operand" "m"))
6094 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6095 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6096 "#")
6098 (define_insn "reload_outqi_help"
6099 [(set (match_operand:QI 0 "memory_operand" "=m")
6100 (match_operand:QI 1 "register_operand" "r"))
6101 (clobber (match_operand:SI 2 "register_operand" "=r"))
6102 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6103 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6104 "#")
6106 (define_insn "reload_outhi_help"
6107 [(set (match_operand:HI 0 "memory_operand" "=m")
6108 (match_operand:HI 1 "register_operand" "r"))
6109 (clobber (match_operand:SI 2 "register_operand" "=r"))
6110 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6111 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6112 "#")
6114 (define_split
6115 [(set (match_operand:QI 0 "register_operand" "")
6116 (match_operand:QI 1 "memory_operand" ""))
6117 (clobber (match_operand:SI 2 "register_operand" ""))]
6118 "! TARGET_BWX && reload_completed"
6119 [(const_int 0)]
6120 {
6121 rtx aligned_mem, bitnum;
6122 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6124 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6125 operands[2]));
6126 DONE;
6127 })
6129 (define_split
6130 [(set (match_operand:HI 0 "register_operand" "")
6131 (match_operand:HI 1 "memory_operand" ""))
6132 (clobber (match_operand:SI 2 "register_operand" ""))]
6133 "! TARGET_BWX && reload_completed"
6134 [(const_int 0)]
6135 {
6136 rtx aligned_mem, bitnum;
6137 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6139 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6140 operands[2]));
6141 DONE;
6142 })
6144 (define_split
6145 [(set (match_operand:QI 0 "memory_operand" "")
6146 (match_operand:QI 1 "register_operand" ""))
6147 (clobber (match_operand:SI 2 "register_operand" ""))
6148 (clobber (match_operand:SI 3 "register_operand" ""))]
6149 "! TARGET_BWX && reload_completed"
6150 [(const_int 0)]
6151 {
6152 rtx aligned_mem, bitnum;
6153 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6154 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6155 operands[2], operands[3]));
6156 DONE;
6157 })
6159 (define_split
6160 [(set (match_operand:HI 0 "memory_operand" "")
6161 (match_operand:HI 1 "register_operand" ""))
6162 (clobber (match_operand:SI 2 "register_operand" ""))
6163 (clobber (match_operand:SI 3 "register_operand" ""))]
6164 "! TARGET_BWX && reload_completed"
6165 [(const_int 0)]
6166 {
6167 rtx aligned_mem, bitnum;
6168 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6169 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6170 operands[2], operands[3]));
6171 DONE;
6172 })
6173 \f
6174 ;; Vector operations
6176 (define_expand "movv8qi"
6177 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
6178 (match_operand:V8QI 1 "general_operand" ""))]
6179 ""
6180 {
6181 if (alpha_expand_mov (V8QImode, operands))
6182 DONE;
6183 })
6185 (define_insn "*movv8qi_fix"
6186 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6187 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6188 "TARGET_FIX
6189 && (register_operand (operands[0], V8QImode)
6190 || reg_or_0_operand (operands[1], V8QImode))"
6191 "@
6192 bis $31,%r1,%0
6193 ldq %0,%1
6194 stq %r1,%0
6195 cpys %R1,%R1,%0
6196 ldt %0,%1
6197 stt %R1,%0
6198 ftoit %1,%0
6199 itoft %1,%0"
6200 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6202 (define_insn "*movv8qi_nofix"
6203 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6204 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6205 "! TARGET_FIX
6206 && (register_operand (operands[0], V8QImode)
6207 || reg_or_0_operand (operands[1], V8QImode))"
6208 "@
6209 bis $31,%r1,%0
6210 ldq %0,%1
6211 stq %r1,%0
6212 cpys %R1,%R1,%0
6213 ldt %0,%1
6214 stt %R1,%0"
6215 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6217 (define_expand "movv4hi"
6218 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
6219 (match_operand:V4HI 1 "general_operand" ""))]
6220 ""
6221 {
6222 if (alpha_expand_mov (V4HImode, operands))
6223 DONE;
6224 })
6226 (define_insn "*movv4hi_fix"
6227 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6228 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6229 "TARGET_FIX
6230 && (register_operand (operands[0], V4HImode)
6231 || reg_or_0_operand (operands[1], V4HImode))"
6232 "@
6233 bis $31,%r1,%0
6234 ldq %0,%1
6235 stq %r1,%0
6236 cpys %R1,%R1,%0
6237 ldt %0,%1
6238 stt %R1,%0
6239 ftoit %1,%0
6240 itoft %1,%0"
6241 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6243 (define_insn "*movv4hi_nofix"
6244 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6245 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6246 "! TARGET_FIX
6247 && (register_operand (operands[0], V4HImode)
6248 || reg_or_0_operand (operands[1], V4HImode))"
6249 "@
6250 bis $31,%r1,%0
6251 ldq %0,%1
6252 stq %r1,%0
6253 cpys %R1,%R1,%0
6254 ldt %0,%1
6255 stt %R1,%0"
6256 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6258 (define_expand "movv2si"
6259 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
6260 (match_operand:V2SI 1 "general_operand" ""))]
6261 ""
6262 {
6263 if (alpha_expand_mov (V2SImode, operands))
6264 DONE;
6265 })
6267 (define_insn "*movv2si_fix"
6268 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6269 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6270 "TARGET_FIX
6271 && (register_operand (operands[0], V2SImode)
6272 || reg_or_0_operand (operands[1], V2SImode))"
6273 "@
6274 bis $31,%r1,%0
6275 ldq %0,%1
6276 stq %r1,%0
6277 cpys %R1,%R1,%0
6278 ldt %0,%1
6279 stt %R1,%0
6280 ftoit %1,%0
6281 itoft %1,%0"
6282 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6284 (define_insn "*movv2si_nofix"
6285 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6286 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6287 "! TARGET_FIX
6288 && (register_operand (operands[0], V2SImode)
6289 || reg_or_0_operand (operands[1], V2SImode))"
6290 "@
6291 bis $31,%r1,%0
6292 ldq %0,%1
6293 stq %r1,%0
6294 cpys %R1,%R1,%0
6295 ldt %0,%1
6296 stt %R1,%0"
6297 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6299 (define_insn "uminv8qi3"
6300 [(set (match_operand:V8QI 0 "register_operand" "=r")
6301 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6302 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6303 "TARGET_MAX"
6304 "minub8 %r1,%r2,%0"
6305 [(set_attr "type" "mvi")])
6307 (define_insn "sminv8qi3"
6308 [(set (match_operand:V8QI 0 "register_operand" "=r")
6309 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6310 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6311 "TARGET_MAX"
6312 "minsb8 %r1,%r2,%0"
6313 [(set_attr "type" "mvi")])
6315 (define_insn "uminv4hi3"
6316 [(set (match_operand:V4HI 0 "register_operand" "=r")
6317 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6318 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6319 "TARGET_MAX"
6320 "minuw4 %r1,%r2,%0"
6321 [(set_attr "type" "mvi")])
6323 (define_insn "sminv4hi3"
6324 [(set (match_operand:V4HI 0 "register_operand" "=r")
6325 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6326 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6327 "TARGET_MAX"
6328 "minsw4 %r1,%r2,%0"
6329 [(set_attr "type" "mvi")])
6331 (define_insn "umaxv8qi3"
6332 [(set (match_operand:V8QI 0 "register_operand" "=r")
6333 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6334 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6335 "TARGET_MAX"
6336 "maxub8 %r1,%r2,%0"
6337 [(set_attr "type" "mvi")])
6339 (define_insn "smaxv8qi3"
6340 [(set (match_operand:V8QI 0 "register_operand" "=r")
6341 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6342 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6343 "TARGET_MAX"
6344 "maxsb8 %r1,%r2,%0"
6345 [(set_attr "type" "mvi")])
6347 (define_insn "umaxv4hi3"
6348 [(set (match_operand:V4HI 0 "register_operand" "=r")
6349 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6350 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6351 "TARGET_MAX"
6352 "maxuw4 %r1,%r2,%0"
6353 [(set_attr "type" "mvi")])
6355 (define_insn "smaxv4hi3"
6356 [(set (match_operand:V4HI 0 "register_operand" "=r")
6357 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6358 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6359 "TARGET_MAX"
6360 "maxsw4 %r1,%r2,%0"
6361 [(set_attr "type" "mvi")])
6362 \f
6363 ;; Bit field extract patterns which use ext[wlq][lh]
6365 (define_expand "extv"
6366 [(set (match_operand:DI 0 "register_operand" "")
6367 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6368 (match_operand:DI 2 "immediate_operand" "")
6369 (match_operand:DI 3 "immediate_operand" "")))]
6370 ""
6371 {
6372 int ofs;
6374 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6375 if (INTVAL (operands[3]) % 8 != 0
6376 || (INTVAL (operands[2]) != 16
6377 && INTVAL (operands[2]) != 32
6378 && INTVAL (operands[2]) != 64))
6379 FAIL;
6381 /* From mips.md: extract_bit_field doesn't verify that our source
6382 matches the predicate, so we force it to be a MEM here. */
6383 if (GET_CODE (operands[1]) != MEM)
6384 FAIL;
6386 /* The bit number is relative to the mode of operand 1 which is
6387 usually QImode (this might actually be a bug in expmed.c). Note
6388 that the bit number is negative in big-endian mode in this case.
6389 We have to convert that to the offset. */
6390 if (WORDS_BIG_ENDIAN)
6391 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6392 - INTVAL (operands[2]) - INTVAL (operands[3]);
6393 else
6394 ofs = INTVAL (operands[3]);
6396 ofs = ofs / 8;
6398 alpha_expand_unaligned_load (operands[0], operands[1],
6399 INTVAL (operands[2]) / 8,
6400 ofs, 1);
6401 DONE;
6402 })
6404 (define_expand "extzv"
6405 [(set (match_operand:DI 0 "register_operand" "")
6406 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6407 (match_operand:DI 2 "immediate_operand" "")
6408 (match_operand:DI 3 "immediate_operand" "")))]
6409 ""
6410 {
6411 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6412 if (INTVAL (operands[3]) % 8 != 0
6413 || (INTVAL (operands[2]) != 8
6414 && INTVAL (operands[2]) != 16
6415 && INTVAL (operands[2]) != 32
6416 && INTVAL (operands[2]) != 64))
6417 FAIL;
6419 if (GET_CODE (operands[1]) == MEM)
6420 {
6421 int ofs;
6423 /* Fail 8 bit fields, falling back on a simple byte load. */
6424 if (INTVAL (operands[2]) == 8)
6425 FAIL;
6427 /* The bit number is relative to the mode of operand 1 which is
6428 usually QImode (this might actually be a bug in expmed.c). Note
6429 that the bit number is negative in big-endian mode in this case.
6430 We have to convert that to the offset. */
6431 if (WORDS_BIG_ENDIAN)
6432 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6433 - INTVAL (operands[2]) - INTVAL (operands[3]);
6434 else
6435 ofs = INTVAL (operands[3]);
6437 ofs = ofs / 8;
6439 alpha_expand_unaligned_load (operands[0], operands[1],
6440 INTVAL (operands[2]) / 8,
6441 ofs, 0);
6442 DONE;
6443 }
6444 })
6446 (define_expand "insv"
6447 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6448 (match_operand:DI 1 "immediate_operand" "")
6449 (match_operand:DI 2 "immediate_operand" ""))
6450 (match_operand:DI 3 "register_operand" ""))]
6451 ""
6452 {
6453 int ofs;
6455 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6456 if (INTVAL (operands[2]) % 8 != 0
6457 || (INTVAL (operands[1]) != 16
6458 && INTVAL (operands[1]) != 32
6459 && INTVAL (operands[1]) != 64))
6460 FAIL;
6462 /* From mips.md: store_bit_field doesn't verify that our source
6463 matches the predicate, so we force it to be a MEM here. */
6464 if (GET_CODE (operands[0]) != MEM)
6465 FAIL;
6467 /* The bit number is relative to the mode of operand 1 which is
6468 usually QImode (this might actually be a bug in expmed.c). Note
6469 that the bit number is negative in big-endian mode in this case.
6470 We have to convert that to the offset. */
6471 if (WORDS_BIG_ENDIAN)
6472 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6473 - INTVAL (operands[1]) - INTVAL (operands[2]);
6474 else
6475 ofs = INTVAL (operands[2]);
6477 ofs = ofs / 8;
6479 alpha_expand_unaligned_store (operands[0], operands[3],
6480 INTVAL (operands[1]) / 8, ofs);
6481 DONE;
6482 })
6484 ;; Block move/clear, see alpha.c for more details.
6485 ;; Argument 0 is the destination
6486 ;; Argument 1 is the source
6487 ;; Argument 2 is the length
6488 ;; Argument 3 is the alignment
6490 (define_expand "movstrqi"
6491 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6492 (match_operand:BLK 1 "memory_operand" ""))
6493 (use (match_operand:DI 2 "immediate_operand" ""))
6494 (use (match_operand:DI 3 "immediate_operand" ""))])]
6495 ""
6496 {
6497 if (alpha_expand_block_move (operands))
6498 DONE;
6499 else
6500 FAIL;
6501 })
6503 (define_expand "movstrdi"
6504 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6505 (match_operand:BLK 1 "memory_operand" ""))
6506 (use (match_operand:DI 2 "immediate_operand" ""))
6507 (use (match_operand:DI 3 "immediate_operand" ""))
6508 (use (match_dup 4))
6509 (clobber (reg:DI 25))
6510 (clobber (reg:DI 16))
6511 (clobber (reg:DI 17))
6512 (clobber (reg:DI 18))
6513 (clobber (reg:DI 19))
6514 (clobber (reg:DI 20))
6515 (clobber (reg:DI 26))
6516 (clobber (reg:DI 27))])]
6517 "TARGET_ABI_OPEN_VMS"
6518 {
6519 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6520 alpha_need_linkage (XSTR (operands[4], 0), 0);
6521 })
6523 (define_insn "*movstrdi_1"
6524 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6525 (match_operand:BLK 1 "memory_operand" "m,m"))
6526 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6527 (use (match_operand:DI 3 "immediate_operand" ""))
6528 (use (match_operand:DI 4 "call_operand" "i,i"))
6529 (clobber (reg:DI 25))
6530 (clobber (reg:DI 16))
6531 (clobber (reg:DI 17))
6532 (clobber (reg:DI 18))
6533 (clobber (reg:DI 19))
6534 (clobber (reg:DI 20))
6535 (clobber (reg:DI 26))
6536 (clobber (reg:DI 27))]
6537 "TARGET_ABI_OPEN_VMS"
6538 {
6539 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6540 switch (which_alternative)
6541 {
6542 case 0:
6543 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6544 case 1:
6545 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6546 default:
6547 abort();
6548 }
6549 }
6550 [(set_attr "type" "multi")
6551 (set_attr "length" "28")])
6553 (define_expand "clrstrqi"
6554 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6555 (const_int 0))
6556 (use (match_operand:DI 1 "immediate_operand" ""))
6557 (use (match_operand:DI 2 "immediate_operand" ""))])]
6558 ""
6559 {
6560 if (alpha_expand_block_clear (operands))
6561 DONE;
6562 else
6563 FAIL;
6564 })
6566 (define_expand "clrstrdi"
6567 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6568 (const_int 0))
6569 (use (match_operand:DI 1 "immediate_operand" ""))
6570 (use (match_operand:DI 2 "immediate_operand" ""))
6571 (use (match_dup 3))
6572 (clobber (reg:DI 25))
6573 (clobber (reg:DI 16))
6574 (clobber (reg:DI 17))
6575 (clobber (reg:DI 26))
6576 (clobber (reg:DI 27))])]
6577 "TARGET_ABI_OPEN_VMS"
6578 {
6579 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6580 alpha_need_linkage (XSTR (operands[3], 0), 0);
6581 })
6583 (define_insn "*clrstrdi_1"
6584 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6585 (const_int 0))
6586 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6587 (use (match_operand:DI 2 "immediate_operand" ""))
6588 (use (match_operand:DI 3 "call_operand" "i,i"))
6589 (clobber (reg:DI 25))
6590 (clobber (reg:DI 16))
6591 (clobber (reg:DI 17))
6592 (clobber (reg:DI 26))
6593 (clobber (reg:DI 27))]
6594 "TARGET_ABI_OPEN_VMS"
6595 {
6596 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6597 switch (which_alternative)
6598 {
6599 case 0:
6600 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6601 case 1:
6602 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6603 default:
6604 abort();
6605 }
6606 }
6607 [(set_attr "type" "multi")
6608 (set_attr "length" "24")])
6610 \f
6611 ;; Subroutine of stack space allocation. Perform a stack probe.
6612 (define_expand "probe_stack"
6613 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6614 ""
6615 {
6616 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6617 INTVAL (operands[0])));
6618 MEM_VOLATILE_P (operands[1]) = 1;
6620 operands[0] = const0_rtx;
6621 })
6623 ;; This is how we allocate stack space. If we are allocating a
6624 ;; constant amount of space and we know it is less than 4096
6625 ;; bytes, we need do nothing.
6626 ;;
6627 ;; If it is more than 4096 bytes, we need to probe the stack
6628 ;; periodically.
6629 (define_expand "allocate_stack"
6630 [(set (reg:DI 30)
6631 (plus:DI (reg:DI 30)
6632 (match_operand:DI 1 "reg_or_cint_operand" "")))
6633 (set (match_operand:DI 0 "register_operand" "=r")
6634 (match_dup 2))]
6635 ""
6636 {
6637 if (GET_CODE (operands[1]) == CONST_INT
6638 && INTVAL (operands[1]) < 32768)
6639 {
6640 if (INTVAL (operands[1]) >= 4096)
6641 {
6642 /* We do this the same way as in the prologue and generate explicit
6643 probes. Then we update the stack by the constant. */
6645 int probed = 4096;
6647 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6648 while (probed + 8192 < INTVAL (operands[1]))
6649 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6651 if (probed + 4096 < INTVAL (operands[1]))
6652 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6653 }
6655 operands[1] = GEN_INT (- INTVAL (operands[1]));
6656 operands[2] = virtual_stack_dynamic_rtx;
6657 }
6658 else
6659 {
6660 rtx out_label = 0;
6661 rtx loop_label = gen_label_rtx ();
6662 rtx want = gen_reg_rtx (Pmode);
6663 rtx tmp = gen_reg_rtx (Pmode);
6664 rtx memref;
6666 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6667 force_reg (Pmode, operands[1])));
6668 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6670 if (GET_CODE (operands[1]) != CONST_INT)
6671 {
6672 out_label = gen_label_rtx ();
6673 emit_insn (gen_cmpdi (want, tmp));
6674 emit_jump_insn (gen_bgeu (out_label));
6675 }
6677 emit_label (loop_label);
6678 memref = gen_rtx_MEM (DImode, tmp);
6679 MEM_VOLATILE_P (memref) = 1;
6680 emit_move_insn (memref, const0_rtx);
6681 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6682 emit_insn (gen_cmpdi (tmp, want));
6683 emit_jump_insn (gen_bgtu (loop_label));
6685 memref = gen_rtx_MEM (DImode, want);
6686 MEM_VOLATILE_P (memref) = 1;
6687 emit_move_insn (memref, const0_rtx);
6689 if (out_label)
6690 emit_label (out_label);
6692 emit_move_insn (stack_pointer_rtx, want);
6693 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6694 DONE;
6695 }
6696 })
6698 ;; This is used by alpha_expand_prolog to do the same thing as above,
6699 ;; except we cannot at that time generate new basic blocks, so we hide
6700 ;; the loop in this one insn.
6702 (define_insn "prologue_stack_probe_loop"
6703 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6704 (match_operand:DI 1 "register_operand" "r")]
6705 UNSPECV_PSPL)]
6706 ""
6707 {
6708 operands[2] = gen_label_rtx ();
6709 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6710 CODE_LABEL_NUMBER (operands[2]));
6712 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6713 }
6714 [(set_attr "length" "16")
6715 (set_attr "type" "multi")])
6717 (define_expand "prologue"
6718 [(clobber (const_int 0))]
6719 ""
6720 {
6721 alpha_expand_prologue ();
6722 DONE;
6723 })
6725 ;; These take care of emitting the ldgp insn in the prologue. This will be
6726 ;; an lda/ldah pair and we want to align them properly. So we have two
6727 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6728 ;; and the second of which emits nothing. However, both are marked as type
6729 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6730 ;; with them.
6732 (define_expand "prologue_ldgp"
6733 [(set (match_dup 0)
6734 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6735 (set (match_dup 0)
6736 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6737 ""
6738 {
6739 operands[0] = pic_offset_table_rtx;
6740 operands[1] = gen_rtx_REG (Pmode, 27);
6741 operands[2] = (TARGET_EXPLICIT_RELOCS
6742 ? GEN_INT (alpha_next_sequence_number++)
6743 : const0_rtx);
6744 })
6746 (define_insn "*ldgp_er_1"
6747 [(set (match_operand:DI 0 "register_operand" "=r")
6748 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6749 (match_operand 2 "const_int_operand" "")]
6750 UNSPECV_LDGP1))]
6751 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6752 "ldah %0,0(%1)\t\t!gpdisp!%2")
6754 (define_insn "*ldgp_er_2"
6755 [(set (match_operand:DI 0 "register_operand" "=r")
6756 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6757 (match_operand 2 "const_int_operand" "")]
6758 UNSPEC_LDGP2))]
6759 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6760 "lda %0,0(%1)\t\t!gpdisp!%2")
6762 (define_insn "*prologue_ldgp_er_2"
6763 [(set (match_operand:DI 0 "register_operand" "=r")
6764 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6765 (match_operand 2 "const_int_operand" "")]
6766 UNSPECV_PLDGP2))]
6767 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6768 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6770 (define_insn "*prologue_ldgp_1"
6771 [(set (match_operand:DI 0 "register_operand" "=r")
6772 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6773 (match_operand 2 "const_int_operand" "")]
6774 UNSPECV_LDGP1))]
6775 ""
6776 "ldgp %0,0(%1)\n$%~..ng:")
6778 (define_insn "*prologue_ldgp_2"
6779 [(set (match_operand:DI 0 "register_operand" "=r")
6780 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6781 (match_operand 2 "const_int_operand" "")]
6782 UNSPECV_PLDGP2))]
6783 ""
6784 "")
6786 ;; The _mcount profiling hook has special calling conventions, and
6787 ;; does not clobber all the registers that a normal call would. So
6788 ;; hide the fact this is a call at all.
6790 (define_insn "prologue_mcount"
6791 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6792 ""
6793 {
6794 if (TARGET_EXPLICIT_RELOCS)
6795 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6796 cannot be called via the PLT. */
6797 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6798 else
6799 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6800 }
6801 [(set_attr "type" "multi")
6802 (set_attr "length" "8")])
6804 (define_insn "init_fp"
6805 [(set (match_operand:DI 0 "register_operand" "=r")
6806 (match_operand:DI 1 "register_operand" "r"))
6807 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6808 ""
6809 "bis $31,%1,%0")
6811 (define_expand "epilogue"
6812 [(return)]
6813 ""
6814 {
6815 alpha_expand_epilogue ();
6816 })
6818 (define_expand "sibcall_epilogue"
6819 [(return)]
6820 "TARGET_ABI_OSF"
6821 {
6822 alpha_expand_epilogue ();
6823 DONE;
6824 })
6826 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6827 ;; the frame size into a register. We use this pattern to ensure
6828 ;; we get lda instead of addq.
6829 (define_insn "nt_lda"
6830 [(set (match_operand:DI 0 "register_operand" "=r")
6831 (unspec:DI [(match_dup 0)
6832 (match_operand:DI 1 "const_int_operand" "n")]
6833 UNSPEC_NT_LDA))]
6834 ""
6835 "lda %0,%1(%0)")
6837 (define_expand "builtin_longjmp"
6838 [(use (match_operand:DI 0 "register_operand" "r"))]
6839 "TARGET_ABI_OSF"
6840 {
6841 /* The elements of the buffer are, in order: */
6842 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6843 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6844 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6845 rtx pv = gen_rtx_REG (Pmode, 27);
6847 /* This bit is the same as expand_builtin_longjmp. */
6848 emit_move_insn (hard_frame_pointer_rtx, fp);
6849 emit_move_insn (pv, lab);
6850 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6851 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6852 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6854 /* Load the label we are jumping through into $27 so that we know
6855 where to look for it when we get back to setjmp's function for
6856 restoring the gp. */
6857 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6858 emit_barrier ();
6859 DONE;
6860 })
6862 ;; This is effectively a copy of indirect_jump, but constrained such
6863 ;; that register renaming cannot foil our cunning plan with $27.
6864 (define_insn "builtin_longjmp_internal"
6865 [(set (pc)
6866 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6867 UNSPECV_LONGJMP))]
6868 ""
6869 "jmp $31,(%0),0"
6870 [(set_attr "type" "ibr")])
6872 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6873 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6874 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6875 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6877 (define_insn "*builtin_setjmp_receiver_er_1"
6878 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6879 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6880 "br $27,$LSJ%=\n$LSJ%=:"
6881 [(set_attr "type" "ibr")])
6883 (define_split
6884 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6885 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6886 && prev_nonnote_insn (insn) == operands[0]"
6887 [(const_int 0)]
6888 "
6889 {
6890 emit_note (NULL, NOTE_INSN_DELETED);
6891 DONE;
6892 }")
6894 (define_insn "*builtin_setjmp_receiver_1"
6895 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6896 "TARGET_ABI_OSF"
6897 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6898 [(set_attr "length" "12")
6899 (set_attr "type" "multi")])
6901 (define_expand "builtin_setjmp_receiver_er"
6902 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6903 (set (match_dup 1)
6904 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6905 (set (match_dup 1)
6906 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6907 ""
6908 {
6909 operands[1] = pic_offset_table_rtx;
6910 operands[2] = gen_rtx_REG (Pmode, 27);
6911 operands[3] = GEN_INT (alpha_next_sequence_number++);
6912 })
6914 (define_expand "builtin_setjmp_receiver"
6915 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6916 "TARGET_ABI_OSF"
6917 {
6918 if (TARGET_EXPLICIT_RELOCS)
6919 {
6920 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6921 DONE;
6922 }
6923 })
6925 (define_expand "exception_receiver_er"
6926 [(set (match_dup 0)
6927 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6928 (set (match_dup 0)
6929 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6930 ""
6931 {
6932 operands[0] = pic_offset_table_rtx;
6933 operands[1] = gen_rtx_REG (Pmode, 26);
6934 operands[2] = GEN_INT (alpha_next_sequence_number++);
6935 })
6937 (define_expand "exception_receiver"
6938 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6939 "TARGET_ABI_OSF"
6940 {
6941 if (TARGET_LD_BUGGY_LDGP)
6942 operands[0] = alpha_gp_save_rtx ();
6943 else if (TARGET_EXPLICIT_RELOCS)
6944 {
6945 emit_insn (gen_exception_receiver_er ());
6946 DONE;
6947 }
6948 else
6949 operands[0] = const0_rtx;
6950 })
6952 (define_insn "*exception_receiver_1"
6953 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6954 "! TARGET_LD_BUGGY_LDGP"
6955 "ldgp $29,0($26)"
6956 [(set_attr "length" "8")
6957 (set_attr "type" "multi")])
6959 (define_insn "*exception_receiver_2"
6960 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6961 "TARGET_LD_BUGGY_LDGP"
6962 "ldq $29,%0"
6963 [(set_attr "type" "ild")])
6965 (define_expand "nonlocal_goto_receiver"
6966 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6967 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6968 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6969 (use (reg:DI 27))]
6970 "TARGET_ABI_OPEN_VMS"
6971 "")
6973 (define_insn "arg_home"
6974 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6975 (use (reg:DI 1))
6976 (use (reg:DI 25))
6977 (use (reg:DI 16))
6978 (use (reg:DI 17))
6979 (use (reg:DI 18))
6980 (use (reg:DI 19))
6981 (use (reg:DI 20))
6982 (use (reg:DI 21))
6983 (use (reg:DI 48))
6984 (use (reg:DI 49))
6985 (use (reg:DI 50))
6986 (use (reg:DI 51))
6987 (use (reg:DI 52))
6988 (use (reg:DI 53))
6989 (clobber (mem:BLK (const_int 0)))
6990 (clobber (reg:DI 24))
6991 (clobber (reg:DI 25))
6992 (clobber (reg:DI 0))]
6993 "TARGET_ABI_OPEN_VMS"
6994 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6995 [(set_attr "length" "16")
6996 (set_attr "type" "multi")])
6998 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7000 (define_expand "umk_mismatch_args"
7001 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7002 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7003 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7004 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7005 (const_int 8))
7006 (match_dup 2)))
7007 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7008 "TARGET_ABI_UNICOSMK"
7009 {
7010 operands[1] = gen_reg_rtx (DImode);
7011 operands[2] = gen_reg_rtx (DImode);
7012 operands[3] = gen_reg_rtx (DImode);
7013 })
7015 (define_insn "arg_home_umk"
7016 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7017 (use (reg:DI 1))
7018 (use (reg:DI 2))
7019 (use (reg:DI 16))
7020 (use (reg:DI 17))
7021 (use (reg:DI 18))
7022 (use (reg:DI 19))
7023 (use (reg:DI 20))
7024 (use (reg:DI 21))
7025 (use (reg:DI 48))
7026 (use (reg:DI 49))
7027 (use (reg:DI 50))
7028 (use (reg:DI 51))
7029 (use (reg:DI 52))
7030 (use (reg:DI 53))
7031 (clobber (mem:BLK (const_int 0)))
7032 (parallel [
7033 (clobber (reg:DI 22))
7034 (clobber (reg:DI 23))
7035 (clobber (reg:DI 24))
7036 (clobber (reg:DI 0))
7037 (clobber (reg:DI 1))
7038 (clobber (reg:DI 2))
7039 (clobber (reg:DI 3))
7040 (clobber (reg:DI 4))
7041 (clobber (reg:DI 5))
7042 (clobber (reg:DI 6))
7043 (clobber (reg:DI 7))
7044 (clobber (reg:DI 8))])]
7045 "TARGET_ABI_UNICOSMK"
7046 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7047 [(set_attr "length" "16")
7048 (set_attr "type" "multi")])
7050 ;; Prefetch data.
7051 ;;
7052 ;; On EV4, these instructions are nops -- no load occurs.
7053 ;;
7054 ;; On EV5, these instructions act as a normal load, and thus can trap
7055 ;; if the address is invalid. The OS may (or may not) handle this in
7056 ;; the entMM fault handler and suppress the fault. If so, then this
7057 ;; has the effect of a read prefetch instruction.
7058 ;;
7059 ;; On EV6, these become official prefetch instructions.
7061 (define_insn "prefetch"
7062 [(prefetch (match_operand:DI 0 "address_operand" "p")
7063 (match_operand:DI 1 "const_int_operand" "n")
7064 (match_operand:DI 2 "const_int_operand" "n"))]
7065 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
7066 {
7067 /* Interpret "no temporal locality" as this data should be evicted once
7068 it is used. The "evict next" alternatives load the data into the cache
7069 and leave the LRU eviction counter pointing to that block. */
7070 static const char * const alt[2][2] = {
7071 {
7072 "ldq $31,%a0", /* read, evict next */
7073 "ldl $31,%a0", /* read, evict last */
7074 },
7075 {
7076 "ldt $f31,%a0", /* write, evict next */
7077 "lds $f31,%a0", /* write, evict last */
7078 }
7079 };
7081 bool write = INTVAL (operands[1]) != 0;
7082 bool lru = INTVAL (operands[2]) != 0;
7084 return alt[write][lru];
7085 }
7086 [(set_attr "type" "ild")])
7088 ;; Close the trap shadow of preceding instructions. This is generated
7089 ;; by alpha_reorg.
7091 (define_insn "trapb"
7092 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7093 ""
7094 "trapb"
7095 [(set_attr "type" "misc")])
7097 ;; No-op instructions used by machine-dependent reorg to preserve
7098 ;; alignment for instruction issue.
7099 ;; The Unicos/Mk assembler does not support these opcodes.
7101 (define_insn "nop"
7102 [(const_int 0)]
7103 ""
7104 "bis $31,$31,$31"
7105 [(set_attr "type" "ilog")])
7107 (define_insn "fnop"
7108 [(const_int 1)]
7109 "TARGET_FP"
7110 "cpys $f31,$f31,$f31"
7111 [(set_attr "type" "fcpys")])
7113 (define_insn "unop"
7114 [(const_int 2)]
7115 ""
7116 "ldq_u $31,0($30)")
7118 ;; On Unicos/Mk we use a macro for aligning code.
7120 (define_insn "realign"
7121 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7122 UNSPECV_REALIGN)]
7123 ""
7124 {
7125 if (TARGET_ABI_UNICOSMK)
7126 return "gcc@code@align %0";
7127 else
7128 return ".align %0 #realign";
7129 })
7130 \f
7131 ;; Instructions to be emitted from __builtins.
7133 (define_insn "builtin_cmpbge"
7134 [(set (match_operand:DI 0 "register_operand" "=r")
7135 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7136 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7137 UNSPEC_CMPBGE))]
7138 ""
7139 "cmpbge %r1,%2,%0"
7140 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7141 ;; actually differentiate between ILOG and ICMP in the schedule.
7142 [(set_attr "type" "icmp")])
7144 (define_expand "builtin_extbl"
7145 [(match_operand:DI 0 "register_operand" "")
7146 (match_operand:DI 1 "reg_or_0_operand" "")
7147 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7148 ""
7149 {
7150 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7151 if (WORDS_BIG_ENDIAN)
7152 gen = gen_extxl_be;
7153 else
7154 gen = gen_extxl_le;
7155 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7156 DONE;
7157 })
7159 (define_expand "builtin_extwl"
7160 [(match_operand:DI 0 "register_operand" "")
7161 (match_operand:DI 1 "reg_or_0_operand" "")
7162 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7163 ""
7164 {
7165 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7166 if (WORDS_BIG_ENDIAN)
7167 gen = gen_extxl_be;
7168 else
7169 gen = gen_extxl_le;
7170 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7171 DONE;
7172 })
7174 (define_expand "builtin_extll"
7175 [(match_operand:DI 0 "register_operand" "")
7176 (match_operand:DI 1 "reg_or_0_operand" "")
7177 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7178 ""
7179 {
7180 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7181 if (WORDS_BIG_ENDIAN)
7182 gen = gen_extxl_be;
7183 else
7184 gen = gen_extxl_le;
7185 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7186 DONE;
7187 })
7189 (define_expand "builtin_extql"
7190 [(match_operand:DI 0 "register_operand" "")
7191 (match_operand:DI 1 "reg_or_0_operand" "")
7192 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7193 ""
7194 {
7195 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7196 if (WORDS_BIG_ENDIAN)
7197 gen = gen_extxl_be;
7198 else
7199 gen = gen_extxl_le;
7200 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7201 DONE;
7202 })
7204 (define_expand "builtin_extwh"
7205 [(match_operand:DI 0 "register_operand" "")
7206 (match_operand:DI 1 "reg_or_0_operand" "")
7207 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7208 ""
7209 {
7210 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7211 if (WORDS_BIG_ENDIAN)
7212 gen = gen_extwh_be;
7213 else
7214 gen = gen_extwh_le;
7215 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7216 DONE;
7217 })
7219 (define_expand "builtin_extlh"
7220 [(match_operand:DI 0 "register_operand" "")
7221 (match_operand:DI 1 "reg_or_0_operand" "")
7222 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7223 ""
7224 {
7225 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7226 if (WORDS_BIG_ENDIAN)
7227 gen = gen_extlh_be;
7228 else
7229 gen = gen_extlh_le;
7230 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7231 DONE;
7232 })
7234 (define_expand "builtin_extqh"
7235 [(match_operand:DI 0 "register_operand" "")
7236 (match_operand:DI 1 "reg_or_0_operand" "")
7237 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7238 ""
7239 {
7240 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7241 if (WORDS_BIG_ENDIAN)
7242 gen = gen_extqh_be;
7243 else
7244 gen = gen_extqh_le;
7245 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7246 DONE;
7247 })
7249 (define_expand "builtin_insbl"
7250 [(match_operand:DI 0 "register_operand" "")
7251 (match_operand:DI 1 "reg_or_0_operand" "")
7252 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7253 ""
7254 {
7255 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7256 if (WORDS_BIG_ENDIAN)
7257 gen = gen_insbl_be;
7258 else
7259 gen = gen_insbl_le;
7260 operands[1] = gen_lowpart (QImode, operands[1]);
7261 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7262 DONE;
7263 })
7265 (define_expand "builtin_inswl"
7266 [(match_operand:DI 0 "register_operand" "")
7267 (match_operand:DI 1 "reg_or_0_operand" "")
7268 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7269 ""
7270 {
7271 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7272 if (WORDS_BIG_ENDIAN)
7273 gen = gen_inswl_be;
7274 else
7275 gen = gen_inswl_le;
7276 operands[1] = gen_lowpart (HImode, operands[1]);
7277 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7278 DONE;
7279 })
7281 (define_expand "builtin_insll"
7282 [(match_operand:DI 0 "register_operand" "")
7283 (match_operand:DI 1 "reg_or_0_operand" "")
7284 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7285 ""
7286 {
7287 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7288 if (WORDS_BIG_ENDIAN)
7289 gen = gen_insll_be;
7290 else
7291 gen = gen_insll_le;
7292 operands[1] = gen_lowpart (SImode, operands[1]);
7293 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7294 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7295 DONE;
7296 })
7298 (define_expand "builtin_insql"
7299 [(match_operand:DI 0 "register_operand" "")
7300 (match_operand:DI 1 "reg_or_0_operand" "")
7301 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7302 ""
7303 {
7304 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7305 if (WORDS_BIG_ENDIAN)
7306 gen = gen_insql_be;
7307 else
7308 gen = gen_insql_le;
7309 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7310 DONE;
7311 })
7313 (define_expand "builtin_inswh"
7314 [(match_operand:DI 0 "register_operand" "")
7315 (match_operand:DI 1 "register_operand" "")
7316 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7317 ""
7318 {
7319 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7320 DONE;
7321 })
7323 (define_expand "builtin_inslh"
7324 [(match_operand:DI 0 "register_operand" "")
7325 (match_operand:DI 1 "register_operand" "")
7326 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7327 ""
7328 {
7329 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7330 DONE;
7331 })
7333 (define_expand "builtin_insqh"
7334 [(match_operand:DI 0 "register_operand" "")
7335 (match_operand:DI 1 "register_operand" "")
7336 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7337 ""
7338 {
7339 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7340 DONE;
7341 })
7343 (define_expand "builtin_mskbl"
7344 [(match_operand:DI 0 "register_operand" "")
7345 (match_operand:DI 1 "reg_or_0_operand" "")
7346 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7347 ""
7348 {
7349 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7350 rtx mask;
7351 if (WORDS_BIG_ENDIAN)
7352 gen = gen_mskxl_be;
7353 else
7354 gen = gen_mskxl_le;
7355 mask = GEN_INT (0xff);
7356 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7357 DONE;
7358 })
7360 (define_expand "builtin_mskwl"
7361 [(match_operand:DI 0 "register_operand" "")
7362 (match_operand:DI 1 "reg_or_0_operand" "")
7363 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7364 ""
7365 {
7366 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7367 rtx mask;
7368 if (WORDS_BIG_ENDIAN)
7369 gen = gen_mskxl_be;
7370 else
7371 gen = gen_mskxl_le;
7372 mask = GEN_INT (0xffff);
7373 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7374 DONE;
7375 })
7377 (define_expand "builtin_mskll"
7378 [(match_operand:DI 0 "register_operand" "")
7379 (match_operand:DI 1 "reg_or_0_operand" "")
7380 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7381 ""
7382 {
7383 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7384 rtx mask;
7385 if (WORDS_BIG_ENDIAN)
7386 gen = gen_mskxl_be;
7387 else
7388 gen = gen_mskxl_le;
7389 mask = immed_double_const (0xffffffff, 0, DImode);
7390 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7391 DONE;
7392 })
7394 (define_expand "builtin_mskql"
7395 [(match_operand:DI 0 "register_operand" "")
7396 (match_operand:DI 1 "reg_or_0_operand" "")
7397 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7398 ""
7399 {
7400 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7401 rtx mask;
7402 if (WORDS_BIG_ENDIAN)
7403 gen = gen_mskxl_be;
7404 else
7405 gen = gen_mskxl_le;
7406 mask = constm1_rtx;
7407 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7408 DONE;
7409 })
7411 (define_expand "builtin_mskwh"
7412 [(match_operand:DI 0 "register_operand" "")
7413 (match_operand:DI 1 "register_operand" "")
7414 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7415 ""
7416 {
7417 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7418 DONE;
7419 })
7421 (define_expand "builtin_msklh"
7422 [(match_operand:DI 0 "register_operand" "")
7423 (match_operand:DI 1 "register_operand" "")
7424 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7425 ""
7426 {
7427 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7428 DONE;
7429 })
7431 (define_expand "builtin_mskqh"
7432 [(match_operand:DI 0 "register_operand" "")
7433 (match_operand:DI 1 "register_operand" "")
7434 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7435 ""
7436 {
7437 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7438 DONE;
7439 })
7441 (define_expand "builtin_zap"
7442 [(set (match_operand:DI 0 "register_operand" "")
7443 (and:DI (unspec:DI
7444 [(match_operand:DI 2 "reg_or_const_int_operand" "")]
7445 UNSPEC_ZAP)
7446 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7447 ""
7448 {
7449 if (GET_CODE (operands[2]) == CONST_INT)
7450 {
7451 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7453 if (mask == const0_rtx)
7454 {
7455 emit_move_insn (operands[0], const0_rtx);
7456 DONE;
7457 }
7458 if (mask == constm1_rtx)
7459 {
7460 emit_move_insn (operands[0], operands[1]);
7461 DONE;
7462 }
7464 operands[1] = force_reg (DImode, operands[1]);
7465 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7466 DONE;
7467 }
7469 operands[1] = force_reg (DImode, operands[1]);
7470 operands[2] = gen_lowpart (QImode, operands[2]);
7471 })
7473 (define_insn "*builtin_zap_1"
7474 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7475 (and:DI (unspec:DI
7476 [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")]
7477 UNSPEC_ZAP)
7478 (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))]
7479 ""
7480 "@
7481 #
7482 #
7483 bis $31,$31,%0
7484 zap %r1,%2,%0"
7485 [(set_attr "type" "shift,shift,ilog,shift")])
7487 (define_split
7488 [(set (match_operand:DI 0 "register_operand" "")
7489 (and:DI (unspec:DI
7490 [(match_operand:QI 2 "const_int_operand" "")]
7491 UNSPEC_ZAP)
7492 (match_operand:DI 1 "const_int_operand" "")))]
7493 ""
7494 [(const_int 0)]
7495 {
7496 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7497 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7498 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7499 else
7500 {
7501 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7502 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7503 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7504 c_hi & CONST_DOUBLE_HIGH (mask),
7505 DImode);
7506 }
7507 emit_move_insn (operands[0], operands[1]);
7508 DONE;
7509 })
7511 (define_split
7512 [(set (match_operand:DI 0 "register_operand" "")
7513 (and:DI (unspec:DI
7514 [(match_operand:QI 2 "const_int_operand" "")]
7515 UNSPEC_ZAP)
7516 (match_operand:DI 1 "register_operand" "")))]
7517 ""
7518 [(set (match_dup 0)
7519 (and:DI (match_dup 1) (match_dup 2)))]
7520 {
7521 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7522 if (operands[2] == const0_rtx)
7523 {
7524 emit_move_insn (operands[0], const0_rtx);
7525 DONE;
7526 }
7527 if (operands[2] == constm1_rtx)
7528 {
7529 emit_move_insn (operands[0], operands[1]);
7530 DONE;
7531 }
7532 })
7534 (define_expand "builtin_zapnot"
7535 [(set (match_operand:DI 0 "register_operand" "")
7536 (and:DI (unspec:DI
7537 [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))]
7538 UNSPEC_ZAP)
7539 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7540 ""
7541 {
7542 if (GET_CODE (operands[2]) == CONST_INT)
7543 {
7544 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7546 if (mask == const0_rtx)
7547 {
7548 emit_move_insn (operands[0], const0_rtx);
7549 DONE;
7550 }
7551 if (mask == constm1_rtx)
7552 {
7553 emit_move_insn (operands[0], operands[1]);
7554 DONE;
7555 }
7557 operands[1] = force_reg (DImode, operands[1]);
7558 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7559 DONE;
7560 }
7562 operands[1] = force_reg (DImode, operands[1]);
7563 operands[2] = gen_lowpart (QImode, operands[2]);
7564 })
7566 (define_insn "*builtin_zapnot_1"
7567 [(set (match_operand:DI 0 "register_operand" "=r")
7568 (and:DI (unspec:DI
7569 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7570 UNSPEC_ZAP)
7571 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7572 ""
7573 "zapnot %r1,%2,%0"
7574 [(set_attr "type" "shift")])
7576 (define_insn "builtin_amask"
7577 [(set (match_operand:DI 0 "register_operand" "=r")
7578 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7579 UNSPEC_AMASK))]
7580 ""
7581 "amask %1,%0"
7582 [(set_attr "type" "ilog")])
7584 (define_insn "builtin_implver"
7585 [(set (match_operand:DI 0 "register_operand" "=r")
7586 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7587 ""
7588 "implver %0"
7589 [(set_attr "type" "ilog")])
7591 (define_insn "builtin_rpcc"
7592 [(set (match_operand:DI 0 "register_operand" "=r")
7593 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7594 ""
7595 "rpcc %0"
7596 [(set_attr "type" "ilog")])
7598 (define_expand "builtin_minub8"
7599 [(match_operand:DI 0 "register_operand" "")
7600 (match_operand:DI 1 "reg_or_0_operand" "")
7601 (match_operand:DI 2 "reg_or_0_operand" "")]
7602 "TARGET_MAX"
7603 {
7604 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7605 operands[1], operands[2]);
7606 DONE;
7607 })
7609 (define_expand "builtin_minsb8"
7610 [(match_operand:DI 0 "register_operand" "")
7611 (match_operand:DI 1 "reg_or_0_operand" "")
7612 (match_operand:DI 2 "reg_or_0_operand" "")]
7613 "TARGET_MAX"
7614 {
7615 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7616 operands[1], operands[2]);
7617 DONE;
7618 })
7620 (define_expand "builtin_minuw4"
7621 [(match_operand:DI 0 "register_operand" "")
7622 (match_operand:DI 1 "reg_or_0_operand" "")
7623 (match_operand:DI 2 "reg_or_0_operand" "")]
7624 "TARGET_MAX"
7625 {
7626 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7627 operands[1], operands[2]);
7628 DONE;
7629 })
7631 (define_expand "builtin_minsw4"
7632 [(match_operand:DI 0 "register_operand" "")
7633 (match_operand:DI 1 "reg_or_0_operand" "")
7634 (match_operand:DI 2 "reg_or_0_operand" "")]
7635 "TARGET_MAX"
7636 {
7637 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7638 operands[1], operands[2]);
7639 DONE;
7640 })
7642 (define_expand "builtin_maxub8"
7643 [(match_operand:DI 0 "register_operand" "")
7644 (match_operand:DI 1 "reg_or_0_operand" "")
7645 (match_operand:DI 2 "reg_or_0_operand" "")]
7646 "TARGET_MAX"
7647 {
7648 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7649 operands[1], operands[2]);
7650 DONE;
7651 })
7653 (define_expand "builtin_maxsb8"
7654 [(match_operand:DI 0 "register_operand" "")
7655 (match_operand:DI 1 "reg_or_0_operand" "")
7656 (match_operand:DI 2 "reg_or_0_operand" "")]
7657 "TARGET_MAX"
7658 {
7659 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7660 operands[1], operands[2]);
7661 DONE;
7662 })
7664 (define_expand "builtin_maxuw4"
7665 [(match_operand:DI 0 "register_operand" "")
7666 (match_operand:DI 1 "reg_or_0_operand" "")
7667 (match_operand:DI 2 "reg_or_0_operand" "")]
7668 "TARGET_MAX"
7669 {
7670 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7671 operands[1], operands[2]);
7672 DONE;
7673 })
7675 (define_expand "builtin_maxsw4"
7676 [(match_operand:DI 0 "register_operand" "")
7677 (match_operand:DI 1 "reg_or_0_operand" "")
7678 (match_operand:DI 2 "reg_or_0_operand" "")]
7679 "TARGET_MAX"
7680 {
7681 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7682 operands[1], operands[2]);
7683 DONE;
7684 })
7686 (define_insn "builtin_perr"
7687 [(set (match_operand:DI 0 "register_operand" "=r")
7688 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7689 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7690 UNSPEC_PERR))]
7691 "TARGET_MAX"
7692 "perr %r1,%r2,%0"
7693 [(set_attr "type" "mvi")])
7695 (define_expand "builtin_pklb"
7696 [(set (match_operand:DI 0 "register_operand" "")
7697 (vec_concat:V8QI
7698 (vec_concat:V4QI
7699 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7700 (match_dup 2))
7701 (match_dup 3)))]
7702 "TARGET_MAX"
7703 {
7704 operands[0] = gen_lowpart (V8QImode, operands[0]);
7705 operands[1] = gen_lowpart (V2SImode, operands[1]);
7706 operands[2] = CONST0_RTX (V2QImode);
7707 operands[3] = CONST0_RTX (V4QImode);
7708 })
7710 (define_insn "*pklb"
7711 [(set (match_operand:V8QI 0 "register_operand" "=r")
7712 (vec_concat:V8QI
7713 (vec_concat:V4QI
7714 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7715 (match_operand:V2QI 2 "const0_operand" ""))
7716 (match_operand:V4QI 3 "const0_operand" "")))]
7717 "TARGET_MAX"
7718 "pklb %r1,%0"
7719 [(set_attr "type" "mvi")])
7721 (define_expand "builtin_pkwb"
7722 [(set (match_operand:DI 0 "register_operand" "")
7723 (vec_concat:V8QI
7724 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7725 (match_dup 2)))]
7726 "TARGET_MAX"
7727 {
7728 operands[0] = gen_lowpart (V8QImode, operands[0]);
7729 operands[1] = gen_lowpart (V4HImode, operands[1]);
7730 operands[2] = CONST0_RTX (V4QImode);
7731 })
7733 (define_insn "*pkwb"
7734 [(set (match_operand:V8QI 0 "register_operand" "=r")
7735 (vec_concat:V8QI
7736 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7737 (match_operand:V4QI 2 "const0_operand" "")))]
7738 "TARGET_MAX"
7739 "pkwb %r1,%0"
7740 [(set_attr "type" "mvi")])
7742 (define_expand "builtin_unpkbl"
7743 [(set (match_operand:DI 0 "register_operand" "")
7744 (zero_extend:V2SI
7745 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7746 (parallel [(const_int 0) (const_int 1)]))))]
7747 "TARGET_MAX"
7748 {
7749 operands[0] = gen_lowpart (V2SImode, operands[0]);
7750 operands[1] = gen_lowpart (V8QImode, operands[1]);
7751 })
7753 (define_insn "*unpkbl"
7754 [(set (match_operand:V2SI 0 "register_operand" "=r")
7755 (zero_extend:V2SI
7756 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7757 (parallel [(const_int 0) (const_int 1)]))))]
7758 "TARGET_MAX"
7759 "unpkbl %r1,%0"
7760 [(set_attr "type" "mvi")])
7762 (define_expand "builtin_unpkbw"
7763 [(set (match_operand:DI 0 "register_operand" "")
7764 (zero_extend:V4HI
7765 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7766 (parallel [(const_int 0)
7767 (const_int 1)
7768 (const_int 2)
7769 (const_int 3)]))))]
7770 "TARGET_MAX"
7771 {
7772 operands[0] = gen_lowpart (V4HImode, operands[0]);
7773 operands[1] = gen_lowpart (V8QImode, operands[1]);
7774 })
7776 (define_insn "*unpkbw"
7777 [(set (match_operand:V4HI 0 "register_operand" "=r")
7778 (zero_extend:V4HI
7779 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7780 (parallel [(const_int 0)
7781 (const_int 1)
7782 (const_int 2)
7783 (const_int 3)]))))]
7784 "TARGET_MAX"
7785 "unpkbw %r1,%0"
7786 [(set_attr "type" "mvi")])
7788 (define_expand "builtin_cttz"
7789 [(set (match_operand:DI 0 "register_operand" "")
7790 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7791 UNSPEC_CTTZ))]
7792 "TARGET_CIX"
7793 "")
7795 (define_insn "builtin_ctlz"
7796 [(set (match_operand:DI 0 "register_operand" "=r")
7797 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7798 UNSPEC_CTLZ))]
7799 "TARGET_CIX"
7800 "ctlz %1,%0"
7801 [(set_attr "type" "mvi")])
7803 (define_insn "builtin_ctpop"
7804 [(set (match_operand:DI 0 "register_operand" "=r")
7805 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7806 UNSPEC_CTPOP))]
7807 "TARGET_CIX"
7808 "ctpop %1,%0"
7809 [(set_attr "type" "mvi")])
7810 \f
7811 ;; The call patterns are at the end of the file because their
7812 ;; wildcard operand0 interferes with nice recognition.
7814 (define_insn "*call_value_osf_1_er"
7815 [(set (match_operand 0 "" "")
7816 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7817 (match_operand 2 "" "")))
7818 (use (reg:DI 29))
7819 (clobber (reg:DI 26))]
7820 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7821 "@
7822 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7823 bsr $26,%1\t\t!samegp
7824 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7825 [(set_attr "type" "jsr")
7826 (set_attr "length" "12,*,16")])
7828 ;; We must use peep2 instead of a split because we need accurate life
7829 ;; information for $gp. Consider the case of { bar(); while (1); }.
7830 (define_peephole2
7831 [(parallel [(set (match_operand 0 "" "")
7832 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7833 (match_operand 2 "" "")))
7834 (use (reg:DI 29))
7835 (clobber (reg:DI 26))])]
7836 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7837 && ! samegp_function_operand (operands[1], Pmode)
7838 && peep2_regno_dead_p (1, 29)"
7839 [(parallel [(set (match_dup 0)
7840 (call (mem:DI (match_dup 3))
7841 (match_dup 2)))
7842 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7843 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7844 (use (match_dup 1))
7845 (use (match_dup 4))])]
7846 {
7847 if (CONSTANT_P (operands[1]))
7848 {
7849 operands[3] = gen_rtx_REG (Pmode, 27);
7850 operands[4] = GEN_INT (alpha_next_sequence_number++);
7851 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7852 operands[1], operands[4]));
7853 }
7854 else
7855 {
7856 operands[3] = operands[1];
7857 operands[1] = const0_rtx;
7858 operands[4] = const0_rtx;
7859 }
7860 })
7862 (define_peephole2
7863 [(parallel [(set (match_operand 0 "" "")
7864 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7865 (match_operand 2 "" "")))
7866 (use (reg:DI 29))
7867 (clobber (reg:DI 26))])]
7868 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7869 && ! samegp_function_operand (operands[1], Pmode)
7870 && ! peep2_regno_dead_p (1, 29)"
7871 [(parallel [(set (match_dup 0)
7872 (call (mem:DI (match_dup 3))
7873 (match_dup 2)))
7874 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7875 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7876 (use (match_dup 1))
7877 (use (match_dup 5))])
7878 (set (reg:DI 29)
7879 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7880 (set (reg:DI 29)
7881 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7882 {
7883 if (CONSTANT_P (operands[1]))
7884 {
7885 operands[3] = gen_rtx_REG (Pmode, 27);
7886 operands[5] = GEN_INT (alpha_next_sequence_number++);
7887 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7888 operands[1], operands[5]));
7889 }
7890 else
7891 {
7892 operands[3] = operands[1];
7893 operands[1] = const0_rtx;
7894 operands[5] = const0_rtx;
7895 }
7896 operands[4] = GEN_INT (alpha_next_sequence_number++);
7897 })
7899 ;; We add a blockage unspec_volatile to prevent insns from moving down
7900 ;; from above the call to in between the call and the ldah gpdisp.
7901 (define_insn "*call_value_osf_2_er"
7902 [(set (match_operand 0 "" "")
7903 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7904 (match_operand 2 "" "")))
7905 (set (reg:DI 26)
7906 (plus:DI (pc) (const_int 4)))
7907 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7908 (use (match_operand 3 "" ""))
7909 (use (match_operand 4 "" ""))]
7910 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7911 "jsr $26,(%1),%3%J4"
7912 [(set_attr "type" "jsr")])
7914 (define_insn "*call_value_osf_1_noreturn"
7915 [(set (match_operand 0 "" "")
7916 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7917 (match_operand 2 "" "")))
7918 (use (reg:DI 29))
7919 (clobber (reg:DI 26))]
7920 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7921 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7922 "@
7923 jsr $26,($27),0
7924 bsr $26,$%1..ng
7925 jsr $26,%1"
7926 [(set_attr "type" "jsr")
7927 (set_attr "length" "*,*,8")])
7929 (define_insn_and_split "call_value_osf_tlsgd"
7930 [(set (match_operand 0 "" "")
7931 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7932 (const_int 0)))
7933 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7934 (use (reg:DI 29))
7935 (clobber (reg:DI 26))]
7936 "HAVE_AS_TLS"
7937 "#"
7938 "&& reload_completed"
7939 [(set (match_dup 3)
7940 (unspec:DI [(match_dup 5)
7941 (match_dup 1)
7942 (match_dup 2)] UNSPEC_LITERAL))
7943 (parallel [(set (match_dup 0)
7944 (call (mem:DI (match_dup 3))
7945 (const_int 0)))
7946 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7947 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7948 (use (match_dup 1))
7949 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7950 (set (match_dup 5)
7951 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7952 (set (match_dup 5)
7953 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7954 {
7955 operands[3] = gen_rtx_REG (Pmode, 27);
7956 operands[4] = GEN_INT (alpha_next_sequence_number++);
7957 operands[5] = pic_offset_table_rtx;
7958 }
7959 [(set_attr "type" "multi")])
7961 (define_insn_and_split "call_value_osf_tlsldm"
7962 [(set (match_operand 0 "" "")
7963 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7964 (const_int 0)))
7965 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7966 (use (reg:DI 29))
7967 (clobber (reg:DI 26))]
7968 "HAVE_AS_TLS"
7969 "#"
7970 "&& reload_completed"
7971 [(set (match_dup 3)
7972 (unspec:DI [(match_dup 5)
7973 (match_dup 1)
7974 (match_dup 2)] UNSPEC_LITERAL))
7975 (parallel [(set (match_dup 0)
7976 (call (mem:DI (match_dup 3))
7977 (const_int 0)))
7978 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7979 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7980 (use (match_dup 1))
7981 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7982 (set (reg:DI 29)
7983 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7984 (set (reg:DI 29)
7985 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7986 {
7987 operands[3] = gen_rtx_REG (Pmode, 27);
7988 operands[4] = GEN_INT (alpha_next_sequence_number++);
7989 operands[5] = pic_offset_table_rtx;
7990 }
7991 [(set_attr "type" "multi")])
7993 (define_insn "*call_value_osf_1"
7994 [(set (match_operand 0 "" "")
7995 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7996 (match_operand 2 "" "")))
7997 (use (reg:DI 29))
7998 (clobber (reg:DI 26))]
7999 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8000 "@
8001 jsr $26,($27),0\;ldgp $29,0($26)
8002 bsr $26,$%1..ng
8003 jsr $26,%1\;ldgp $29,0($26)"
8004 [(set_attr "type" "jsr")
8005 (set_attr "length" "12,*,16")])
8007 (define_insn "*sibcall_value_osf_1_er"
8008 [(set (match_operand 0 "" "")
8009 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8010 (match_operand 2 "" "")))
8011 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8012 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8013 "@
8014 br $31,%1\t\t!samegp
8015 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8016 [(set_attr "type" "jsr")
8017 (set_attr "length" "*,8")])
8019 (define_insn "*sibcall_value_osf_1"
8020 [(set (match_operand 0 "" "")
8021 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8022 (match_operand 2 "" "")))
8023 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8024 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8025 "@
8026 br $31,$%1..ng
8027 lda $27,%1\;jmp $31,($27),%1"
8028 [(set_attr "type" "jsr")
8029 (set_attr "length" "*,8")])
8031 (define_insn "*call_value_nt_1"
8032 [(set (match_operand 0 "" "")
8033 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8034 (match_operand 2 "" "")))
8035 (clobber (reg:DI 26))]
8036 "TARGET_ABI_WINDOWS_NT"
8037 "@
8038 jsr $26,(%1)
8039 bsr $26,%1
8040 jsr $26,%1"
8041 [(set_attr "type" "jsr")
8042 (set_attr "length" "*,*,12")])
8044 ; GAS relies on the order and position of instructions output below in order
8045 ; to generate relocs for VMS link to potentially optimize the call.
8046 ; Please do not molest.
8047 (define_insn "*call_value_vms_1"
8048 [(set (match_operand 0 "" "")
8049 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8050 (match_operand 2 "" "")))
8051 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8052 (use (reg:DI 25))
8053 (use (reg:DI 26))
8054 (clobber (reg:DI 27))]
8055 "TARGET_ABI_OPEN_VMS"
8056 {
8057 switch (which_alternative)
8058 {
8059 case 0:
8060 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8061 case 1:
8062 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8063 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8064 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8065 default:
8066 abort();
8067 }
8068 }
8069 [(set_attr "type" "jsr")
8070 (set_attr "length" "12,16")])
8072 (define_insn "*call_value_umk"
8073 [(set (match_operand 0 "" "")
8074 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8075 (match_operand 2 "" "")))
8076 (use (reg:DI 25))
8077 (clobber (reg:DI 26))]
8078 "TARGET_ABI_UNICOSMK"
8079 "jsr $26,(%1)"
8080 [(set_attr "type" "jsr")])