1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
55 /* Specify which cpu to schedule for. */
57 enum processor_type alpha_cpu
;
58 static const char * const alpha_cpu_name
[] =
63 /* Specify how accurate floating-point traps need to be. */
65 enum alpha_trap_precision alpha_tp
;
67 /* Specify the floating-point rounding mode. */
69 enum alpha_fp_rounding_mode alpha_fprm
;
71 /* Specify which things cause traps. */
73 enum alpha_fp_trap_mode alpha_fptm
;
75 /* Specify bit size of immediate TLS offsets. */
77 int alpha_tls_size
= 32;
79 /* Strings decoded into the above options. */
81 const char *alpha_cpu_string
; /* -mcpu= */
82 const char *alpha_tune_string
; /* -mtune= */
83 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
84 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
85 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
86 const char *alpha_mlat_string
; /* -mmemory-latency= */
87 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
89 /* Save information from a "cmpxx" operation until the branch or scc is
92 struct alpha_compare alpha_compare
;
94 /* Nonzero if inside of a function, because the Alpha asm can't
95 handle .files inside of functions. */
97 static int inside_function
= FALSE
;
99 /* The number of cycles of latency we should assume on memory reads. */
101 int alpha_memory_latency
= 3;
103 /* Whether the function needs the GP. */
105 static int alpha_function_needs_gp
;
107 /* The alias set for prologue/epilogue register save/restore. */
109 static GTY(()) int alpha_sr_alias_set
;
111 /* The assembler name of the current function. */
113 static const char *alpha_fnname
;
115 /* The next explicit relocation sequence number. */
116 extern GTY(()) int alpha_next_sequence_number
;
117 int alpha_next_sequence_number
= 1;
119 /* The literal and gpdisp sequence numbers for this insn, as printed
120 by %# and %* respectively. */
121 extern GTY(()) int alpha_this_literal_sequence_number
;
122 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
123 int alpha_this_literal_sequence_number
;
124 int alpha_this_gpdisp_sequence_number
;
126 /* Costs of various operations on the different architectures. */
128 struct alpha_rtx_cost_data
130 unsigned char fp_add
;
131 unsigned char fp_mult
;
132 unsigned char fp_div_sf
;
133 unsigned char fp_div_df
;
134 unsigned char int_mult_si
;
135 unsigned char int_mult_di
;
136 unsigned char int_shift
;
137 unsigned char int_cmov
;
140 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
143 COSTS_N_INSNS (6), /* fp_add */
144 COSTS_N_INSNS (6), /* fp_mult */
145 COSTS_N_INSNS (34), /* fp_div_sf */
146 COSTS_N_INSNS (63), /* fp_div_df */
147 COSTS_N_INSNS (23), /* int_mult_si */
148 COSTS_N_INSNS (23), /* int_mult_di */
149 COSTS_N_INSNS (2), /* int_shift */
150 COSTS_N_INSNS (2), /* int_cmov */
153 COSTS_N_INSNS (4), /* fp_add */
154 COSTS_N_INSNS (4), /* fp_mult */
155 COSTS_N_INSNS (15), /* fp_div_sf */
156 COSTS_N_INSNS (22), /* fp_div_df */
157 COSTS_N_INSNS (8), /* int_mult_si */
158 COSTS_N_INSNS (12), /* int_mult_di */
159 COSTS_N_INSNS (1) + 1, /* int_shift */
160 COSTS_N_INSNS (1), /* int_cmov */
163 COSTS_N_INSNS (4), /* fp_add */
164 COSTS_N_INSNS (4), /* fp_mult */
165 COSTS_N_INSNS (12), /* fp_div_sf */
166 COSTS_N_INSNS (15), /* fp_div_df */
167 COSTS_N_INSNS (7), /* int_mult_si */
168 COSTS_N_INSNS (7), /* int_mult_di */
169 COSTS_N_INSNS (1), /* int_shift */
170 COSTS_N_INSNS (2), /* int_cmov */
174 /* Declarations of static functions. */
175 static bool alpha_function_ok_for_sibcall
176 PARAMS ((tree
, tree
));
177 static int tls_symbolic_operand_1
178 PARAMS ((rtx
, enum machine_mode
, int, int));
179 static enum tls_model tls_symbolic_operand_type
181 static bool decl_in_text_section
183 static bool decl_has_samegp
185 static bool alpha_in_small_data_p
187 static void alpha_encode_section_info
188 PARAMS ((tree
, int));
189 static const char *alpha_strip_name_encoding
190 PARAMS ((const char *));
191 static int some_small_symbolic_operand_1
192 PARAMS ((rtx
*, void *));
193 static int split_small_symbolic_operand_1
194 PARAMS ((rtx
*, void *));
195 static bool alpha_cannot_copy_insn_p
197 static bool alpha_rtx_costs
198 PARAMS ((rtx
, int, int, int *));
199 static void alpha_set_memflags_1
200 PARAMS ((rtx
, int, int, int));
201 static rtx alpha_emit_set_const_1
202 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
203 static void alpha_expand_unaligned_load_words
204 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
205 static void alpha_expand_unaligned_store_words
206 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
207 static void alpha_init_builtins
209 static rtx alpha_expand_builtin
210 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
211 static void alpha_sa_mask
212 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
213 static int find_lo_sum_using_gp
214 PARAMS ((rtx
*, void *));
215 static int alpha_does_function_need_gp
217 static int alpha_ra_ever_killed
219 static const char *get_trap_mode_suffix
221 static const char *get_round_mode_suffix
223 static const char *get_some_local_dynamic_name
225 static int get_some_local_dynamic_name_1
226 PARAMS ((rtx
*, void *));
227 static rtx set_frame_related_p
229 static const char *alpha_lookup_xfloating_lib_func
230 PARAMS ((enum rtx_code
));
231 static int alpha_compute_xfloating_mode_arg
232 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
233 static void alpha_emit_xfloating_libcall
234 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
235 static rtx alpha_emit_xfloating_compare
236 PARAMS ((enum rtx_code
, rtx
, rtx
));
237 static void alpha_output_function_end_prologue
239 static int alpha_adjust_cost
240 PARAMS ((rtx
, rtx
, rtx
, int));
241 static int alpha_issue_rate
243 static int alpha_use_dfa_pipeline_interface
245 static int alpha_multipass_dfa_lookahead
248 #ifdef OBJECT_FORMAT_ELF
249 static void alpha_elf_select_rtx_section
250 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
253 #if TARGET_ABI_OPEN_VMS
254 static bool alpha_linkage_symbol_p
255 PARAMS ((const char *symname
));
256 static int alpha_write_one_linkage
257 PARAMS ((splay_tree_node
, void *));
258 static void alpha_write_linkage
259 PARAMS ((FILE *, const char *, tree
));
263 static void alpha_output_mi_thunk_osf
264 PARAMS ((FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
));
267 static struct machine_function
* alpha_init_machine_status
270 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
271 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
272 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
273 static int unicosmk_need_dex
PARAMS ((rtx
));
275 /* Get the number of args of a function in one of two ways. */
276 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
277 #define NUM_ARGS current_function_args_info.num_args
279 #define NUM_ARGS current_function_args_info
285 /* Initialize the GCC target structure. */
286 #if TARGET_ABI_OPEN_VMS
287 const struct attribute_spec vms_attribute_table
[];
288 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
289 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
290 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
291 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
292 # undef TARGET_ATTRIBUTE_TABLE
293 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
294 # undef TARGET_SECTION_TYPE_FLAGS
295 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
298 #undef TARGET_IN_SMALL_DATA_P
299 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
300 #undef TARGET_ENCODE_SECTION_INFO
301 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
302 #undef TARGET_STRIP_NAME_ENCODING
303 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
305 #if TARGET_ABI_UNICOSMK
306 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
307 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
308 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
310 static void unicosmk_unique_section
PARAMS ((tree
, int));
311 # undef TARGET_INSERT_ATTRIBUTES
312 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
313 # undef TARGET_SECTION_TYPE_FLAGS
314 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
315 # undef TARGET_ASM_UNIQUE_SECTION
316 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
317 # undef TARGET_ASM_GLOBALIZE_LABEL
318 # define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
321 #undef TARGET_ASM_ALIGNED_HI_OP
322 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
323 #undef TARGET_ASM_ALIGNED_DI_OP
324 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
326 /* Default unaligned ops are provided for ELF systems. To get unaligned
327 data for non-ELF systems, we have to turn off auto alignment. */
328 #ifndef OBJECT_FORMAT_ELF
329 #undef TARGET_ASM_UNALIGNED_HI_OP
330 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
331 #undef TARGET_ASM_UNALIGNED_SI_OP
332 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
333 #undef TARGET_ASM_UNALIGNED_DI_OP
334 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
337 #ifdef OBJECT_FORMAT_ELF
338 #undef TARGET_ASM_SELECT_RTX_SECTION
339 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
342 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
343 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
345 #undef TARGET_SCHED_ADJUST_COST
346 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
347 #undef TARGET_SCHED_ISSUE_RATE
348 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
349 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
350 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
351 alpha_use_dfa_pipeline_interface
352 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
353 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
354 alpha_multipass_dfa_lookahead
356 #undef TARGET_HAVE_TLS
357 #define TARGET_HAVE_TLS HAVE_AS_TLS
359 #undef TARGET_INIT_BUILTINS
360 #define TARGET_INIT_BUILTINS alpha_init_builtins
361 #undef TARGET_EXPAND_BUILTIN
362 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
364 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
365 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
366 #undef TARGET_CANNOT_COPY_INSN_P
367 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
370 #undef TARGET_ASM_OUTPUT_MI_THUNK
371 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
372 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
373 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
376 #undef TARGET_RTX_COSTS
377 #define TARGET_RTX_COSTS alpha_rtx_costs
378 #undef TARGET_ADDRESS_COST
379 #define TARGET_ADDRESS_COST hook_int_rtx_0
381 struct gcc_target targetm
= TARGET_INITIALIZER
;
383 /* Parse target option strings. */
389 static const struct cpu_table
{
390 const char *const name
;
391 const enum processor_type processor
;
394 #define EV5_MASK (MASK_CPU_EV5)
395 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
396 { "ev4", PROCESSOR_EV4
, 0 },
397 { "ev45", PROCESSOR_EV4
, 0 },
398 { "21064", PROCESSOR_EV4
, 0 },
399 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
400 { "21164", PROCESSOR_EV5
, EV5_MASK
},
401 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
402 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
403 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
404 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
405 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
406 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
407 { "21264", PROCESSOR_EV6
, EV6_MASK
},
408 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
409 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
413 /* Unicos/Mk doesn't have shared libraries. */
414 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
416 warning ("-f%s ignored for Unicos/Mk (not supported)",
417 (flag_pic
> 1) ? "PIC" : "pic");
421 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
422 floating-point instructions. Make that the default for this target. */
423 if (TARGET_ABI_UNICOSMK
)
424 alpha_fprm
= ALPHA_FPRM_DYN
;
426 alpha_fprm
= ALPHA_FPRM_NORM
;
428 alpha_tp
= ALPHA_TP_PROG
;
429 alpha_fptm
= ALPHA_FPTM_N
;
431 /* We cannot use su and sui qualifiers for conversion instructions on
432 Unicos/Mk. I'm not sure if this is due to assembler or hardware
433 limitations. Right now, we issue a warning if -mieee is specified
434 and then ignore it; eventually, we should either get it right or
435 disable the option altogether. */
439 if (TARGET_ABI_UNICOSMK
)
440 warning ("-mieee not supported on Unicos/Mk");
443 alpha_tp
= ALPHA_TP_INSN
;
444 alpha_fptm
= ALPHA_FPTM_SU
;
448 if (TARGET_IEEE_WITH_INEXACT
)
450 if (TARGET_ABI_UNICOSMK
)
451 warning ("-mieee-with-inexact not supported on Unicos/Mk");
454 alpha_tp
= ALPHA_TP_INSN
;
455 alpha_fptm
= ALPHA_FPTM_SUI
;
461 if (! strcmp (alpha_tp_string
, "p"))
462 alpha_tp
= ALPHA_TP_PROG
;
463 else if (! strcmp (alpha_tp_string
, "f"))
464 alpha_tp
= ALPHA_TP_FUNC
;
465 else if (! strcmp (alpha_tp_string
, "i"))
466 alpha_tp
= ALPHA_TP_INSN
;
468 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
471 if (alpha_fprm_string
)
473 if (! strcmp (alpha_fprm_string
, "n"))
474 alpha_fprm
= ALPHA_FPRM_NORM
;
475 else if (! strcmp (alpha_fprm_string
, "m"))
476 alpha_fprm
= ALPHA_FPRM_MINF
;
477 else if (! strcmp (alpha_fprm_string
, "c"))
478 alpha_fprm
= ALPHA_FPRM_CHOP
;
479 else if (! strcmp (alpha_fprm_string
,"d"))
480 alpha_fprm
= ALPHA_FPRM_DYN
;
482 error ("bad value `%s' for -mfp-rounding-mode switch",
486 if (alpha_fptm_string
)
488 if (strcmp (alpha_fptm_string
, "n") == 0)
489 alpha_fptm
= ALPHA_FPTM_N
;
490 else if (strcmp (alpha_fptm_string
, "u") == 0)
491 alpha_fptm
= ALPHA_FPTM_U
;
492 else if (strcmp (alpha_fptm_string
, "su") == 0)
493 alpha_fptm
= ALPHA_FPTM_SU
;
494 else if (strcmp (alpha_fptm_string
, "sui") == 0)
495 alpha_fptm
= ALPHA_FPTM_SUI
;
497 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
500 if (alpha_tls_size_string
)
502 if (strcmp (alpha_tls_size_string
, "16") == 0)
504 else if (strcmp (alpha_tls_size_string
, "32") == 0)
506 else if (strcmp (alpha_tls_size_string
, "64") == 0)
509 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
513 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
514 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
516 if (alpha_cpu_string
)
518 for (i
= 0; cpu_table
[i
].name
; i
++)
519 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
521 alpha_cpu
= cpu_table
[i
].processor
;
522 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
523 | MASK_CPU_EV5
| MASK_CPU_EV6
);
524 target_flags
|= cpu_table
[i
].flags
;
527 if (! cpu_table
[i
].name
)
528 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
531 if (alpha_tune_string
)
533 for (i
= 0; cpu_table
[i
].name
; i
++)
534 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
536 alpha_cpu
= cpu_table
[i
].processor
;
539 if (! cpu_table
[i
].name
)
540 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
543 /* Do some sanity checks on the above options. */
545 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
547 warning ("trap mode not supported on Unicos/Mk");
548 alpha_fptm
= ALPHA_FPTM_N
;
551 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
552 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
554 warning ("fp software completion requires -mtrap-precision=i");
555 alpha_tp
= ALPHA_TP_INSN
;
560 /* Except for EV6 pass 1 (not released), we always have precise
561 arithmetic traps. Which means we can do software completion
562 without minding trap shadows. */
563 alpha_tp
= ALPHA_TP_PROG
;
566 if (TARGET_FLOAT_VAX
)
568 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
570 warning ("rounding mode not supported for VAX floats");
571 alpha_fprm
= ALPHA_FPRM_NORM
;
573 if (alpha_fptm
== ALPHA_FPTM_SUI
)
575 warning ("trap mode not supported for VAX floats");
576 alpha_fptm
= ALPHA_FPTM_SU
;
584 if (!alpha_mlat_string
)
585 alpha_mlat_string
= "L1";
587 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
588 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
590 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
591 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
592 && alpha_mlat_string
[2] == '\0')
594 static int const cache_latency
[][4] =
596 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
597 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
598 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
601 lat
= alpha_mlat_string
[1] - '0';
602 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
604 warning ("L%d cache latency unknown for %s",
605 lat
, alpha_cpu_name
[alpha_cpu
]);
609 lat
= cache_latency
[alpha_cpu
][lat
-1];
611 else if (! strcmp (alpha_mlat_string
, "main"))
613 /* Most current memories have about 370ns latency. This is
614 a reasonable guess for a fast cpu. */
619 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
623 alpha_memory_latency
= lat
;
626 /* Default the definition of "small data" to 8 bytes. */
630 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
632 target_flags
|= MASK_SMALL_DATA
;
633 else if (flag_pic
== 2)
634 target_flags
&= ~MASK_SMALL_DATA
;
636 /* Align labels and loops for optimal branching. */
637 /* ??? Kludge these by not doing anything if we don't optimize and also if
638 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
639 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
641 if (align_loops
<= 0)
643 if (align_jumps
<= 0)
646 if (align_functions
<= 0)
647 align_functions
= 16;
649 /* Acquire a unique set number for our register saves and restores. */
650 alpha_sr_alias_set
= new_alias_set ();
652 /* Register variables and functions with the garbage collector. */
654 /* Set up function hooks. */
655 init_machine_status
= alpha_init_machine_status
;
657 /* Tell the compiler when we're using VAX floating point. */
658 if (TARGET_FLOAT_VAX
)
660 real_format_for_mode
[SFmode
- QFmode
] = &vax_f_format
;
661 real_format_for_mode
[DFmode
- QFmode
] = &vax_g_format
;
662 real_format_for_mode
[TFmode
- QFmode
] = NULL
;
666 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
674 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
676 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
682 /* Returns 1 if OP is either the constant zero or a register. If a
683 register, it must be in the proper mode unless MODE is VOIDmode. */
686 reg_or_0_operand (op
, mode
)
688 enum machine_mode mode
;
690 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
693 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
697 reg_or_6bit_operand (op
, mode
)
699 enum machine_mode mode
;
701 return ((GET_CODE (op
) == CONST_INT
702 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
703 || register_operand (op
, mode
));
707 /* Return 1 if OP is an 8-bit constant or any register. */
710 reg_or_8bit_operand (op
, mode
)
712 enum machine_mode mode
;
714 return ((GET_CODE (op
) == CONST_INT
715 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
716 || register_operand (op
, mode
));
719 /* Return 1 if OP is a constant or any register. */
722 reg_or_const_int_operand (op
, mode
)
724 enum machine_mode mode
;
726 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
729 /* Return 1 if OP is an 8-bit constant. */
732 cint8_operand (op
, mode
)
734 enum machine_mode mode ATTRIBUTE_UNUSED
;
736 return ((GET_CODE (op
) == CONST_INT
737 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
740 /* Return 1 if the operand is a valid second operand to an add insn. */
743 add_operand (op
, mode
)
745 enum machine_mode mode
;
747 if (GET_CODE (op
) == CONST_INT
)
748 /* Constraints I, J, O and P are covered by K. */
749 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
750 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
752 return register_operand (op
, mode
);
755 /* Return 1 if the operand is a valid second operand to a sign-extending
759 sext_add_operand (op
, mode
)
761 enum machine_mode mode
;
763 if (GET_CODE (op
) == CONST_INT
)
764 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
765 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
767 return reg_not_elim_operand (op
, mode
);
770 /* Return 1 if OP is the constant 4 or 8. */
773 const48_operand (op
, mode
)
775 enum machine_mode mode ATTRIBUTE_UNUSED
;
777 return (GET_CODE (op
) == CONST_INT
778 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
781 /* Return 1 if OP is a valid first operand to an AND insn. */
784 and_operand (op
, mode
)
786 enum machine_mode mode
;
788 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
789 return (zap_mask (CONST_DOUBLE_LOW (op
))
790 && zap_mask (CONST_DOUBLE_HIGH (op
)));
792 if (GET_CODE (op
) == CONST_INT
)
793 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
794 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
795 || zap_mask (INTVAL (op
)));
797 return register_operand (op
, mode
);
800 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
803 or_operand (op
, mode
)
805 enum machine_mode mode
;
807 if (GET_CODE (op
) == CONST_INT
)
808 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
809 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
811 return register_operand (op
, mode
);
814 /* Return 1 if OP is a constant that is the width, in bits, of an integral
815 mode smaller than DImode. */
818 mode_width_operand (op
, mode
)
820 enum machine_mode mode ATTRIBUTE_UNUSED
;
822 return (GET_CODE (op
) == CONST_INT
823 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
824 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
827 /* Return 1 if OP is a constant that is the width of an integral machine mode
828 smaller than an integer. */
831 mode_mask_operand (op
, mode
)
833 enum machine_mode mode ATTRIBUTE_UNUSED
;
835 if (GET_CODE (op
) == CONST_INT
)
837 HOST_WIDE_INT value
= INTVAL (op
);
843 if (value
== 0xffffffff)
848 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
850 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
857 /* Return 1 if OP is a multiple of 8 less than 64. */
860 mul8_operand (op
, mode
)
862 enum machine_mode mode ATTRIBUTE_UNUSED
;
864 return (GET_CODE (op
) == CONST_INT
865 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
866 && (INTVAL (op
) & 7) == 0);
869 /* Return 1 if OP is the zero constant for MODE. */
872 const0_operand (op
, mode
)
874 enum machine_mode mode
;
876 return op
== CONST0_RTX (mode
);
879 /* Return 1 if OP is a hard floating-point register. */
882 hard_fp_register_operand (op
, mode
)
884 enum machine_mode mode
;
886 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
889 if (GET_CODE (op
) == SUBREG
)
890 op
= SUBREG_REG (op
);
891 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
894 /* Return 1 if OP is a hard general register. */
897 hard_int_register_operand (op
, mode
)
899 enum machine_mode mode
;
901 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
904 if (GET_CODE (op
) == SUBREG
)
905 op
= SUBREG_REG (op
);
906 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
909 /* Return 1 if OP is a register or a constant integer. */
913 reg_or_cint_operand (op
, mode
)
915 enum machine_mode mode
;
917 return (GET_CODE (op
) == CONST_INT
918 || register_operand (op
, mode
));
921 /* Return 1 if OP is something that can be reloaded into a register;
922 if it is a MEM, it need not be valid. */
925 some_operand (op
, mode
)
927 enum machine_mode mode
;
929 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
932 switch (GET_CODE (op
))
946 return some_operand (SUBREG_REG (op
), VOIDmode
);
955 /* Likewise, but don't accept constants. */
958 some_ni_operand (op
, mode
)
960 enum machine_mode mode
;
962 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
965 if (GET_CODE (op
) == SUBREG
)
966 op
= SUBREG_REG (op
);
968 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
971 /* Return 1 if OP is a valid operand for the source of a move insn. */
974 input_operand (op
, mode
)
976 enum machine_mode mode
;
978 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
981 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
984 switch (GET_CODE (op
))
989 if (TARGET_EXPLICIT_RELOCS
)
991 /* We don't split symbolic operands into something unintelligable
992 until after reload, but we do not wish non-small, non-global
993 symbolic operands to be reconstructed from their high/lo_sum
995 return (small_symbolic_operand (op
, mode
)
996 || global_symbolic_operand (op
, mode
)
997 || gotdtp_symbolic_operand (op
, mode
)
998 || gottp_symbolic_operand (op
, mode
));
1001 /* This handles both the Windows/NT and OSF cases. */
1002 return mode
== ptr_mode
|| mode
== DImode
;
1005 return (TARGET_EXPLICIT_RELOCS
1006 && local_symbolic_operand (XEXP (op
, 0), mode
));
1013 if (register_operand (op
, mode
))
1015 /* ... fall through ... */
1017 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
1018 && general_operand (op
, mode
));
1022 return op
== CONST0_RTX (mode
);
1025 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
1027 case CONSTANT_P_RTX
:
1037 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
1038 file, and in the same section as the current function. */
1041 samegp_function_operand (op
, mode
)
1043 enum machine_mode mode ATTRIBUTE_UNUSED
;
1045 if (GET_CODE (op
) != SYMBOL_REF
)
1048 /* Easy test for recursion. */
1049 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
1052 /* Otherwise, encode_section_info recorded whether we are to treat
1053 this symbol as having the same GP. */
1054 return SYMBOL_REF_FLAG (op
);
1057 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
1060 direct_call_operand (op
, mode
)
1062 enum machine_mode mode
;
1064 /* Must share the same GP. */
1065 if (!samegp_function_operand (op
, mode
))
1068 /* If profiling is implemented via linker tricks, we can't jump
1069 to the nogp alternate entry point. Note that current_function_profile
1070 would not be correct, since that doesn't indicate if the target
1071 function uses profiling. */
1072 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
1073 but is approximately correct for the OSF ABIs. Don't know
1074 what to do for VMS, NT, or UMK. */
1075 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
1078 /* Must be "near" so that the branch is assumed to reach. With
1079 -msmall-text, this is true of all local symbols. */
1080 if (TARGET_SMALL_TEXT
)
1083 /* Otherwise, a decl is "near" if it is defined in the same section.
1084 See alpha_encode_section_info for commentary. */
1085 return op
->jump
&& decl_in_text_section (cfun
->decl
);
1088 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
1089 a (non-tls) variable known to be defined in this file. */
1092 local_symbolic_operand (op
, mode
)
1094 enum machine_mode mode
;
1098 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1101 if (GET_CODE (op
) == LABEL_REF
)
1104 if (GET_CODE (op
) == CONST
1105 && GET_CODE (XEXP (op
, 0)) == PLUS
1106 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1107 op
= XEXP (XEXP (op
, 0), 0);
1109 if (GET_CODE (op
) != SYMBOL_REF
)
1112 /* Easy pickings. */
1113 if (CONSTANT_POOL_ADDRESS_P (op
) || STRING_POOL_ADDRESS_P (op
))
1116 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1117 run into problems with the rtl inliner in that the symbol was
1118 once external, but is local after inlining, which results in
1119 unrecognizable insns. */
1123 /* If @[LS], then alpha_encode_section_info sez it's local. */
1124 if (str
[0] == '@' && (str
[1] == 'L' || str
[1] == 'S'))
1127 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1128 if (str
[0] == '*' && str
[1] == '$')
1134 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1135 known to be defined in this file in the small data area. */
1138 small_symbolic_operand (op
, mode
)
1140 enum machine_mode mode ATTRIBUTE_UNUSED
;
1144 if (! TARGET_SMALL_DATA
)
1147 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1150 if (GET_CODE (op
) == CONST
1151 && GET_CODE (XEXP (op
, 0)) == PLUS
1152 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1153 op
= XEXP (XEXP (op
, 0), 0);
1155 if (GET_CODE (op
) != SYMBOL_REF
)
1158 if (CONSTANT_POOL_ADDRESS_P (op
))
1159 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1163 return str
[0] == '@' && str
[1] == 'S';
1167 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1168 not known (or known not) to be defined in this file. */
1171 global_symbolic_operand (op
, mode
)
1173 enum machine_mode mode
;
1177 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1180 if (GET_CODE (op
) == CONST
1181 && GET_CODE (XEXP (op
, 0)) == PLUS
1182 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1183 op
= XEXP (XEXP (op
, 0), 0);
1185 if (GET_CODE (op
) != SYMBOL_REF
)
1188 if (local_symbolic_operand (op
, mode
))
1191 /* Also verify that it's not a TLS symbol. */
1193 return str
[0] != '%' && str
[0] != '@';
1196 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1199 call_operand (op
, mode
)
1201 enum machine_mode mode
;
1206 if (GET_CODE (op
) == REG
)
1210 /* Disallow virtual registers to cope with pathalogical test cases
1211 such as compile/930117-1.c in which the virtual reg decomposes
1212 to the frame pointer. Which is a hard reg that is not $27. */
1213 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1218 if (TARGET_ABI_UNICOSMK
)
1220 if (GET_CODE (op
) == SYMBOL_REF
)
1226 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1227 possibly with an offset. */
1230 symbolic_operand (op
, mode
)
1232 enum machine_mode mode
;
1234 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1236 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1238 if (GET_CODE (op
) == CONST
1239 && GET_CODE (XEXP (op
,0)) == PLUS
1240 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1241 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1246 /* Return true if OP is valid for a particular TLS relocation. */
1249 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1251 enum machine_mode mode
;
1256 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1259 if (GET_CODE (op
) != CONST
)
1263 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1265 op
= XVECEXP (op
, 0, 0);
1267 if (GET_CODE (op
) != SYMBOL_REF
)
1276 else if (str
[0] == '@')
1278 if (alpha_tls_size
> size
)
1287 return unspec
== UNSPEC_DTPREL
;
1289 return unspec
== UNSPEC_TPREL
&& size
== 64;
1291 return unspec
== UNSPEC_TPREL
&& size
< 64;
1297 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1300 dtp16_symbolic_operand (op
, mode
)
1302 enum machine_mode mode
;
1304 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1307 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1310 dtp32_symbolic_operand (op
, mode
)
1312 enum machine_mode mode
;
1314 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1317 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1320 gotdtp_symbolic_operand (op
, mode
)
1322 enum machine_mode mode
;
1324 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1327 /* Return true if OP is valid for 16-bit TP relative relocations. */
1330 tp16_symbolic_operand (op
, mode
)
1332 enum machine_mode mode
;
1334 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1337 /* Return true if OP is valid for 32-bit TP relative relocations. */
1340 tp32_symbolic_operand (op
, mode
)
1342 enum machine_mode mode
;
1344 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1347 /* Return true if OP is valid for 64-bit TP relative relocations. */
1350 gottp_symbolic_operand (op
, mode
)
1352 enum machine_mode mode
;
1354 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1357 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1358 comparisons are valid in which insn. */
1361 alpha_comparison_operator (op
, mode
)
1363 enum machine_mode mode
;
1365 enum rtx_code code
= GET_CODE (op
);
1367 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1370 return (code
== EQ
|| code
== LE
|| code
== LT
1371 || code
== LEU
|| code
== LTU
);
1374 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1375 Here we know which comparisons are valid in which insn. */
1378 alpha_zero_comparison_operator (op
, mode
)
1380 enum machine_mode mode
;
1382 enum rtx_code code
= GET_CODE (op
);
1384 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1387 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1388 || code
== LEU
|| code
== LTU
);
1391 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1394 alpha_swapped_comparison_operator (op
, mode
)
1396 enum machine_mode mode
;
1398 enum rtx_code code
= GET_CODE (op
);
1400 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1401 || GET_RTX_CLASS (code
) != '<')
1404 code
= swap_condition (code
);
1405 return (code
== EQ
|| code
== LE
|| code
== LT
1406 || code
== LEU
|| code
== LTU
);
1409 /* Return 1 if OP is a signed comparison operation. */
1412 signed_comparison_operator (op
, mode
)
1414 enum machine_mode mode ATTRIBUTE_UNUSED
;
1416 enum rtx_code code
= GET_CODE (op
);
1418 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1421 return (code
== EQ
|| code
== NE
1422 || code
== LE
|| code
== LT
1423 || code
== GE
|| code
== GT
);
1426 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1427 Here we know which comparisons are valid in which insn. */
1430 alpha_fp_comparison_operator (op
, mode
)
1432 enum machine_mode mode
;
1434 enum rtx_code code
= GET_CODE (op
);
1436 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1439 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1442 /* Return 1 if this is a divide or modulus operator. */
1445 divmod_operator (op
, mode
)
1447 enum machine_mode mode ATTRIBUTE_UNUSED
;
1449 switch (GET_CODE (op
))
1451 case DIV
: case MOD
: case UDIV
: case UMOD
:
1461 /* Return 1 if this memory address is a known aligned register plus
1462 a constant. It must be a valid address. This means that we can do
1463 this as an aligned reference plus some offset.
1465 Take into account what reload will do. */
1468 aligned_memory_operand (op
, mode
)
1470 enum machine_mode mode
;
1474 if (reload_in_progress
)
1477 if (GET_CODE (tmp
) == SUBREG
)
1478 tmp
= SUBREG_REG (tmp
);
1479 if (GET_CODE (tmp
) == REG
1480 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1482 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1488 if (GET_CODE (op
) != MEM
1489 || GET_MODE (op
) != mode
)
1493 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1494 sorts of constructs. Dig for the real base register. */
1495 if (reload_in_progress
1496 && GET_CODE (op
) == PLUS
1497 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1498 base
= XEXP (XEXP (op
, 0), 0);
1501 if (! memory_address_p (mode
, op
))
1503 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1506 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1509 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1512 unaligned_memory_operand (op
, mode
)
1514 enum machine_mode mode
;
1518 if (reload_in_progress
)
1521 if (GET_CODE (tmp
) == SUBREG
)
1522 tmp
= SUBREG_REG (tmp
);
1523 if (GET_CODE (tmp
) == REG
1524 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1526 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1532 if (GET_CODE (op
) != MEM
1533 || GET_MODE (op
) != mode
)
1537 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1538 sorts of constructs. Dig for the real base register. */
1539 if (reload_in_progress
1540 && GET_CODE (op
) == PLUS
1541 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1542 base
= XEXP (XEXP (op
, 0), 0);
1545 if (! memory_address_p (mode
, op
))
1547 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1550 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1553 /* Return 1 if OP is either a register or an unaligned memory location. */
1556 reg_or_unaligned_mem_operand (op
, mode
)
1558 enum machine_mode mode
;
1560 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1563 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1566 any_memory_operand (op
, mode
)
1568 enum machine_mode mode ATTRIBUTE_UNUSED
;
1570 return (GET_CODE (op
) == MEM
1571 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1572 || (reload_in_progress
&& GET_CODE (op
) == REG
1573 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1574 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1575 && GET_CODE (SUBREG_REG (op
)) == REG
1576 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1579 /* Returns 1 if OP is not an eliminable register.
1581 This exists to cure a pathological abort in the s8addq (et al) patterns,
1583 long foo () { long t; bar(); return (long) &t * 26107; }
1585 which run afoul of a hack in reload to cure a (presumably) similar
1586 problem with lea-type instructions on other targets. But there is
1587 one of us and many of them, so work around the problem by selectively
1588 preventing combine from making the optimization. */
1591 reg_not_elim_operand (op
, mode
)
1593 enum machine_mode mode
;
1596 if (GET_CODE (op
) == SUBREG
)
1597 inner
= SUBREG_REG (op
);
1598 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1601 return register_operand (op
, mode
);
1604 /* Return 1 is OP is a memory location that is not a reference (using
1605 an AND) to an unaligned location. Take into account what reload
1609 normal_memory_operand (op
, mode
)
1611 enum machine_mode mode ATTRIBUTE_UNUSED
;
1613 if (reload_in_progress
)
1616 if (GET_CODE (tmp
) == SUBREG
)
1617 tmp
= SUBREG_REG (tmp
);
1618 if (GET_CODE (tmp
) == REG
1619 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1621 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1623 /* This may not have been assigned an equivalent address if it will
1624 be eliminated. In that case, it doesn't matter what we do. */
1630 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1633 /* Accept a register, but not a subreg of any kind. This allows us to
1634 avoid pathological cases in reload wrt data movement common in
1635 int->fp conversion. */
1638 reg_no_subreg_operand (op
, mode
)
1640 enum machine_mode mode
;
1642 if (GET_CODE (op
) != REG
)
1644 return register_operand (op
, mode
);
1647 /* Recognize an addition operation that includes a constant. Used to
1648 convince reload to canonize (plus (plus reg c1) c2) during register
1652 addition_operation (op
, mode
)
1654 enum machine_mode mode
;
1656 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1658 if (GET_CODE (op
) == PLUS
1659 && register_operand (XEXP (op
, 0), mode
)
1660 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1661 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1666 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1667 the range defined for C in [I-P]. */
1670 alpha_const_ok_for_letter_p (value
, c
)
1671 HOST_WIDE_INT value
;
1677 /* An unsigned 8 bit constant. */
1678 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1680 /* The constant zero. */
1683 /* A signed 16 bit constant. */
1684 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1686 /* A shifted signed 16 bit constant appropriate for LDAH. */
1687 return ((value
& 0xffff) == 0
1688 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1690 /* A constant that can be AND'ed with using a ZAP insn. */
1691 return zap_mask (value
);
1693 /* A complemented unsigned 8 bit constant. */
1694 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1696 /* A negated unsigned 8 bit constant. */
1697 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1699 /* The constant 1, 2 or 3. */
1700 return value
== 1 || value
== 2 || value
== 3;
1707 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1708 matches for C in [GH]. */
1711 alpha_const_double_ok_for_letter_p (value
, c
)
1718 /* The floating point zero constant. */
1719 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1720 && value
== CONST0_RTX (GET_MODE (value
)));
1723 /* A valid operand of a ZAP insn. */
1724 return (GET_MODE (value
) == VOIDmode
1725 && zap_mask (CONST_DOUBLE_LOW (value
))
1726 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1733 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1737 alpha_extra_constraint (value
, c
)
1744 return normal_memory_operand (value
, VOIDmode
);
1746 return direct_call_operand (value
, Pmode
);
1748 return (GET_CODE (value
) == CONST_INT
1749 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1751 return GET_CODE (value
) == HIGH
;
1753 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1755 return (GET_CODE (value
) == CONST_VECTOR
1756 && value
== CONST0_RTX (GET_MODE (value
)));
1762 /* Return 1 if this function can directly return via $26. */
1767 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1769 && alpha_sa_size () == 0
1770 && get_frame_size () == 0
1771 && current_function_outgoing_args_size
== 0
1772 && current_function_pretend_args_size
== 0);
1775 /* Return the ADDR_VEC associated with a tablejump insn. */
1778 alpha_tablejump_addr_vec (insn
)
1783 tmp
= JUMP_LABEL (insn
);
1786 tmp
= NEXT_INSN (tmp
);
1789 if (GET_CODE (tmp
) == JUMP_INSN
1790 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1791 return PATTERN (tmp
);
1795 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1798 alpha_tablejump_best_label (insn
)
1801 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1802 rtx best_label
= NULL_RTX
;
1804 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1805 there for edge frequency counts from profile data. */
1809 int n_labels
= XVECLEN (jump_table
, 1);
1810 int best_count
= -1;
1813 for (i
= 0; i
< n_labels
; i
++)
1817 for (j
= i
+ 1; j
< n_labels
; j
++)
1818 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1819 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1822 if (count
> best_count
)
1823 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1827 return best_label
? best_label
: const0_rtx
;
1830 /* Return the TLS model to use for SYMBOL. */
1832 static enum tls_model
1833 tls_symbolic_operand_type (symbol
)
1838 if (GET_CODE (symbol
) != SYMBOL_REF
)
1840 str
= XSTR (symbol
, 0);
1844 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1845 have separately encoded local-ness. On well, maybe the user will use
1846 attribute visibility next time. At least we don't crash... */
1847 if (str
[1] == 'G' || str
[1] == 'D')
1848 return TLS_MODEL_GLOBAL_DYNAMIC
;
1850 return TLS_MODEL_INITIAL_EXEC
;
1852 else if (str
[0] == '@')
1856 /* Local dynamic is a waste if we're not going to combine
1857 the __tls_get_addr calls. So avoid it if not optimizing. */
1859 return TLS_MODEL_LOCAL_DYNAMIC
;
1861 return TLS_MODEL_GLOBAL_DYNAMIC
;
1864 return TLS_MODEL_INITIAL_EXEC
;
1866 return TLS_MODEL_LOCAL_EXEC
;
1873 /* Return true if the function DECL will be placed in the default text
1875 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1876 decl, as that would allow us to determine if two functions are in the
1877 same section, which is what we really want to know. */
1880 decl_in_text_section (decl
)
1883 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1884 && ! (flag_function_sections
1885 || (targetm
.have_named_sections
1886 && DECL_ONE_ONLY (decl
))));
1889 /* Return true if the function DECL will share the same GP as any
1890 function in the current unit of translation. */
1893 decl_has_samegp (decl
)
1896 /* Functions that are not local can be overridden, and thus may
1897 not share the same gp. */
1898 if (!(*targetm
.binds_local_p
) (decl
))
1901 /* If -msmall-data is in effect, assume that there is only one GP
1902 for the module, and so any local symbol has this property. We
1903 need explicit relocations to be able to enforce this for symbols
1904 not defined in this unit of translation, however. */
1905 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1908 /* Functions that are not external are defined in this UoT. */
1909 /* ??? Irritatingly, static functions not yet emitted are still
1910 marked "external". Apply this to non-static functions only. */
1911 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1914 /* Return true if EXP should be placed in the small data section. */
1917 alpha_in_small_data_p (exp
)
1920 /* We want to merge strings, so we never consider them small data. */
1921 if (TREE_CODE (exp
) == STRING_CST
)
1924 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1926 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1927 if (strcmp (section
, ".sdata") == 0
1928 || strcmp (section
, ".sbss") == 0)
1933 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1935 /* If this is an incomplete type with size 0, then we can't put it
1936 in sdata because it might be too big when completed. */
1937 if (size
> 0 && size
<= g_switch_value
)
1944 /* If we are referencing a function that is static, make the SYMBOL_REF
1945 special. We use this to see indicate we can branch to this function
1946 without setting PV or restoring GP.
1948 If this is a variable that is known to be defined locally, add "@v"
1949 to the name. If in addition the variable is to go in .sdata/.sbss,
1950 then add "@s" instead. */
1953 alpha_encode_section_info (decl
, first
)
1955 int first ATTRIBUTE_UNUSED
;
1957 const char *symbol_str
;
1962 rtl
= DECL_P (decl
) ? DECL_RTL (decl
) : TREE_CST_RTL (decl
);
1964 /* Careful not to prod global register variables. */
1965 if (GET_CODE (rtl
) != MEM
)
1967 symbol
= XEXP (rtl
, 0);
1968 if (GET_CODE (symbol
) != SYMBOL_REF
)
1971 /* A variable is considered "local" if it is defined in this module. */
1972 is_local
= (*targetm
.binds_local_p
) (decl
);
1974 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1976 /* Mark whether the decl is "near" in distance. If -msmall-text is
1977 in effect, this is trivially true of all local symbols. */
1978 if (TARGET_SMALL_TEXT
)
1985 /* Otherwise, a decl is "near" if it is defined in this same
1986 section. What we really need is to be able to access the
1987 target decl of a call from the call_insn pattern, so that
1988 we can determine if the call is from the same section. We
1989 can't do that at present, so handle the common case and
1990 match up .text with .text.
1992 Delay marking public functions until they are emitted; otherwise
1993 we don't know that they exist in this unit of translation. */
1994 if (!TREE_PUBLIC (decl
) && decl_in_text_section (decl
))
1998 /* Indicate whether the target function shares the same GP as any
1999 function emitted in this unit of translation. */
2000 if (decl_has_samegp (decl
))
2001 SYMBOL_REF_FLAG (symbol
) = 1;
2005 /* Early out if we're not going to do anything with this data. */
2006 if (! TARGET_EXPLICIT_RELOCS
)
2009 symbol_str
= XSTR (symbol
, 0);
2011 /* Care for TLS variables. */
2012 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL (decl
))
2014 switch (decl_tls_model (decl
))
2016 case TLS_MODEL_GLOBAL_DYNAMIC
:
2019 case TLS_MODEL_LOCAL_DYNAMIC
:
2022 case TLS_MODEL_INITIAL_EXEC
:
2025 case TLS_MODEL_LOCAL_EXEC
:
2026 encoding
= (alpha_tls_size
== 64 ? 'T' : 't');
2032 /* Determine if DECL will wind up in .sdata/.sbss. */
2033 if (alpha_in_small_data_p (decl
))
2039 /* Finally, encode this into the symbol string. */
2044 char want_prefix
= (is_local
? '@' : '%');
2045 char other_prefix
= (is_local
? '%' : '@');
2047 if (symbol_str
[0] == want_prefix
)
2049 if (symbol_str
[1] == encoding
)
2053 else if (symbol_str
[0] == other_prefix
)
2056 len
= strlen (symbol_str
) + 1;
2057 newstr
= alloca (len
+ 2);
2059 newstr
[0] = want_prefix
;
2060 newstr
[1] = encoding
;
2061 memcpy (newstr
+ 2, symbol_str
, len
);
2063 XSTR (symbol
, 0) = ggc_alloc_string (newstr
, len
+ 2 - 1);
2067 /* Undo the effects of the above. */
2070 alpha_strip_name_encoding (str
)
2073 if (str
[0] == '@' || str
[0] == '%')
2080 #if TARGET_ABI_OPEN_VMS
2082 alpha_linkage_symbol_p (symname
)
2083 const char *symname
;
2085 int symlen
= strlen (symname
);
2088 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
2093 #define LINKAGE_SYMBOL_REF_P(X) \
2094 ((GET_CODE (X) == SYMBOL_REF \
2095 && alpha_linkage_symbol_p (XSTR (X, 0))) \
2096 || (GET_CODE (X) == CONST \
2097 && GET_CODE (XEXP (X, 0)) == PLUS \
2098 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
2099 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
2102 /* legitimate_address_p recognizes an RTL expression that is a valid
2103 memory address for an instruction. The MODE argument is the
2104 machine mode for the MEM expression that wants to use this address.
2106 For Alpha, we have either a constant address or the sum of a
2107 register and a constant address, or just a register. For DImode,
2108 any of those forms can be surrounded with an AND that clear the
2109 low-order three bits; this is an "unaligned" access. */
2112 alpha_legitimate_address_p (mode
, x
, strict
)
2113 enum machine_mode mode
;
2117 /* If this is an ldq_u type address, discard the outer AND. */
2119 && GET_CODE (x
) == AND
2120 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2121 && INTVAL (XEXP (x
, 1)) == -8)
2124 /* Discard non-paradoxical subregs. */
2125 if (GET_CODE (x
) == SUBREG
2126 && (GET_MODE_SIZE (GET_MODE (x
))
2127 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2130 /* Unadorned general registers are valid. */
2133 ? STRICT_REG_OK_FOR_BASE_P (x
)
2134 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
2137 /* Constant addresses (i.e. +/- 32k) are valid. */
2138 if (CONSTANT_ADDRESS_P (x
))
2141 #if TARGET_ABI_OPEN_VMS
2142 if (LINKAGE_SYMBOL_REF_P (x
))
2146 /* Register plus a small constant offset is valid. */
2147 if (GET_CODE (x
) == PLUS
)
2149 rtx ofs
= XEXP (x
, 1);
2152 /* Discard non-paradoxical subregs. */
2153 if (GET_CODE (x
) == SUBREG
2154 && (GET_MODE_SIZE (GET_MODE (x
))
2155 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2161 && NONSTRICT_REG_OK_FP_BASE_P (x
)
2162 && GET_CODE (ofs
) == CONST_INT
)
2165 ? STRICT_REG_OK_FOR_BASE_P (x
)
2166 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
2167 && CONSTANT_ADDRESS_P (ofs
))
2170 else if (GET_CODE (x
) == ADDRESSOF
2171 && GET_CODE (ofs
) == CONST_INT
)
2175 /* If we're managing explicit relocations, LO_SUM is valid, as
2176 are small data symbols. */
2177 else if (TARGET_EXPLICIT_RELOCS
)
2179 if (small_symbolic_operand (x
, Pmode
))
2182 if (GET_CODE (x
) == LO_SUM
)
2184 rtx ofs
= XEXP (x
, 1);
2187 /* Discard non-paradoxical subregs. */
2188 if (GET_CODE (x
) == SUBREG
2189 && (GET_MODE_SIZE (GET_MODE (x
))
2190 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2193 /* Must have a valid base register. */
2196 ? STRICT_REG_OK_FOR_BASE_P (x
)
2197 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2200 /* The symbol must be local. */
2201 if (local_symbolic_operand (ofs
, Pmode
)
2202 || dtp32_symbolic_operand (ofs
, Pmode
)
2203 || tp32_symbolic_operand (ofs
, Pmode
))
2211 /* Try machine-dependent ways of modifying an illegitimate address
2212 to be legitimate. If we find one, return the new, valid address. */
2215 alpha_legitimize_address (x
, scratch
, mode
)
2218 enum machine_mode mode ATTRIBUTE_UNUSED
;
2220 HOST_WIDE_INT addend
;
2222 /* If the address is (plus reg const_int) and the CONST_INT is not a
2223 valid offset, compute the high part of the constant and add it to
2224 the register. Then our address is (plus temp low-part-const). */
2225 if (GET_CODE (x
) == PLUS
2226 && GET_CODE (XEXP (x
, 0)) == REG
2227 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2228 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2230 addend
= INTVAL (XEXP (x
, 1));
2235 /* If the address is (const (plus FOO const_int)), find the low-order
2236 part of the CONST_INT. Then load FOO plus any high-order part of the
2237 CONST_INT into a register. Our address is (plus reg low-part-const).
2238 This is done to reduce the number of GOT entries. */
2240 && GET_CODE (x
) == CONST
2241 && GET_CODE (XEXP (x
, 0)) == PLUS
2242 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2244 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2245 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2249 /* If we have a (plus reg const), emit the load as in (2), then add
2250 the two registers, and finally generate (plus reg low-part-const) as
2253 && GET_CODE (x
) == PLUS
2254 && GET_CODE (XEXP (x
, 0)) == REG
2255 && GET_CODE (XEXP (x
, 1)) == CONST
2256 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2257 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2259 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2260 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2261 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2262 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2266 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2267 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2269 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2271 switch (tls_symbolic_operand_type (x
))
2273 case TLS_MODEL_GLOBAL_DYNAMIC
:
2276 r0
= gen_rtx_REG (Pmode
, 0);
2277 r16
= gen_rtx_REG (Pmode
, 16);
2278 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2279 dest
= gen_reg_rtx (Pmode
);
2280 seq
= GEN_INT (alpha_next_sequence_number
++);
2282 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2283 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2284 insn
= emit_call_insn (insn
);
2285 CONST_OR_PURE_CALL_P (insn
) = 1;
2286 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2288 insn
= get_insns ();
2291 emit_libcall_block (insn
, dest
, r0
, x
);
2294 case TLS_MODEL_LOCAL_DYNAMIC
:
2297 r0
= gen_rtx_REG (Pmode
, 0);
2298 r16
= gen_rtx_REG (Pmode
, 16);
2299 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2300 scratch
= gen_reg_rtx (Pmode
);
2301 seq
= GEN_INT (alpha_next_sequence_number
++);
2303 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2304 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2305 insn
= emit_call_insn (insn
);
2306 CONST_OR_PURE_CALL_P (insn
) = 1;
2307 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2309 insn
= get_insns ();
2312 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2313 UNSPEC_TLSLDM_CALL
);
2314 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2316 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2317 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2319 if (alpha_tls_size
== 64)
2321 dest
= gen_reg_rtx (Pmode
);
2322 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2323 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2326 if (alpha_tls_size
== 32)
2328 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2329 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2330 scratch
= gen_reg_rtx (Pmode
);
2331 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2333 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2335 case TLS_MODEL_INITIAL_EXEC
:
2336 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2337 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2338 tp
= gen_reg_rtx (Pmode
);
2339 scratch
= gen_reg_rtx (Pmode
);
2340 dest
= gen_reg_rtx (Pmode
);
2342 emit_insn (gen_load_tp (tp
));
2343 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2344 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2347 case TLS_MODEL_LOCAL_EXEC
:
2348 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2349 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2350 tp
= gen_reg_rtx (Pmode
);
2352 emit_insn (gen_load_tp (tp
));
2353 if (alpha_tls_size
== 32)
2355 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2356 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2357 tp
= gen_reg_rtx (Pmode
);
2358 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2360 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2363 if (local_symbolic_operand (x
, Pmode
))
2365 if (small_symbolic_operand (x
, Pmode
))
2369 if (!no_new_pseudos
)
2370 scratch
= gen_reg_rtx (Pmode
);
2371 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2372 gen_rtx_HIGH (Pmode
, x
)));
2373 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2382 HOST_WIDE_INT low
, high
;
2384 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2386 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2390 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2391 (no_new_pseudos
? scratch
: NULL_RTX
),
2392 1, OPTAB_LIB_WIDEN
);
2394 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2395 (no_new_pseudos
? scratch
: NULL_RTX
),
2396 1, OPTAB_LIB_WIDEN
);
2398 return plus_constant (x
, low
);
2402 /* We do not allow indirect calls to be optimized into sibling calls, nor
2403 can we allow a call to a function with a different GP to be optimized
2407 alpha_function_ok_for_sibcall (decl
, exp
)
2409 tree exp ATTRIBUTE_UNUSED
;
2411 /* Can't do indirect tail calls, since we don't know if the target
2412 uses the same GP. */
2416 /* Otherwise, we can make a tail call if the target function shares
2418 return decl_has_samegp (decl
);
2421 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2422 small symbolic operand until after reload. At which point we need
2423 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2424 so that sched2 has the proper dependency information. */
2427 some_small_symbolic_operand (x
, mode
)
2429 enum machine_mode mode ATTRIBUTE_UNUSED
;
2431 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2435 some_small_symbolic_operand_1 (px
, data
)
2437 void *data ATTRIBUTE_UNUSED
;
2441 /* Don't re-split. */
2442 if (GET_CODE (x
) == LO_SUM
)
2445 return small_symbolic_operand (x
, Pmode
) != 0;
2449 split_small_symbolic_operand (x
)
2453 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2458 split_small_symbolic_operand_1 (px
, data
)
2460 void *data ATTRIBUTE_UNUSED
;
2464 /* Don't re-split. */
2465 if (GET_CODE (x
) == LO_SUM
)
2468 if (small_symbolic_operand (x
, Pmode
))
2470 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2478 /* Indicate that INSN cannot be duplicated. This is true for any insn
2479 that we've marked with gpdisp relocs, since those have to stay in
2480 1-1 correspondence with one another.
2482 Techinically we could copy them if we could set up a mapping from one
2483 sequence number to another, across the set of insns to be duplicated.
2484 This seems overly complicated and error-prone since interblock motion
2485 from sched-ebb could move one of the pair of insns to a different block. */
2488 alpha_cannot_copy_insn_p (insn
)
2493 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2496 if (GET_CODE (insn
) != INSN
)
2498 if (asm_noperands (insn
) >= 0)
2501 pat
= PATTERN (insn
);
2502 if (GET_CODE (pat
) != SET
)
2504 pat
= SET_SRC (pat
);
2505 if (GET_CODE (pat
) == UNSPEC_VOLATILE
)
2507 if (XINT (pat
, 1) == UNSPECV_LDGP1
2508 || XINT (pat
, 1) == UNSPECV_PLDGP2
)
2511 else if (GET_CODE (pat
) == UNSPEC
)
2513 if (XINT (pat
, 1) == UNSPEC_LDGP2
)
2521 /* Try a machine-dependent way of reloading an illegitimate address
2522 operand. If we find one, push the reload and return the new rtx. */
2525 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2527 enum machine_mode mode ATTRIBUTE_UNUSED
;
2530 int ind_levels ATTRIBUTE_UNUSED
;
2532 /* We must recognize output that we have already generated ourselves. */
2533 if (GET_CODE (x
) == PLUS
2534 && GET_CODE (XEXP (x
, 0)) == PLUS
2535 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2536 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2537 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2539 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2540 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2545 /* We wish to handle large displacements off a base register by
2546 splitting the addend across an ldah and the mem insn. This
2547 cuts number of extra insns needed from 3 to 1. */
2548 if (GET_CODE (x
) == PLUS
2549 && GET_CODE (XEXP (x
, 0)) == REG
2550 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2551 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2552 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2554 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2555 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2557 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2559 /* Check for 32-bit overflow. */
2560 if (high
+ low
!= val
)
2563 /* Reload the high part into a base reg; leave the low part
2564 in the mem directly. */
2565 x
= gen_rtx_PLUS (GET_MODE (x
),
2566 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2570 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2571 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2579 /* Compute a (partial) cost for rtx X. Return true if the complete
2580 cost has been computed, and false if subexpressions should be
2581 scanned. In either case, *TOTAL contains the cost result. */
2584 alpha_rtx_costs (x
, code
, outer_code
, total
)
2586 int code
, outer_code
;
2589 enum machine_mode mode
= GET_MODE (x
);
2590 bool float_mode_p
= FLOAT_MODE_P (mode
);
2594 /* If this is an 8-bit constant, return zero since it can be used
2595 nearly anywhere with no cost. If it is a valid operand for an
2596 ADD or AND, likewise return 0 if we know it will be used in that
2597 context. Otherwise, return 2 since it might be used there later.
2598 All other constants take at least two insns. */
2600 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2608 if (x
== CONST0_RTX (mode
))
2610 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2611 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2613 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2616 *total
= COSTS_N_INSNS (2);
2622 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2623 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2624 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2625 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2626 else if (tls_symbolic_operand_type (x
))
2627 /* Estimate of cost for call_pal rduniq. */
2628 *total
= COSTS_N_INSNS (15);
2630 /* Otherwise we do a load from the GOT. */
2631 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2637 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2638 else if (GET_CODE (XEXP (x
, 0)) == MULT
2639 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2641 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2642 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2649 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2650 else if (mode
== DImode
)
2651 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2653 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2657 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2658 && INTVAL (XEXP (x
, 1)) <= 3)
2660 *total
= COSTS_N_INSNS (1);
2667 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2672 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2674 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2682 *total
= COSTS_N_INSNS (70); /* ??? */
2683 else if (mode
== SFmode
)
2684 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2686 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2690 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2696 *total
= COSTS_N_INSNS (1);
2704 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2710 case UNSIGNED_FLOAT
:
2714 case FLOAT_TRUNCATE
:
2715 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2723 /* REF is an alignable memory location. Place an aligned SImode
2724 reference into *PALIGNED_MEM and the number of bits to shift into
2725 *PBITNUM. SCRATCH is a free register for use in reloading out
2726 of range stack slots. */
2729 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2731 rtx
*paligned_mem
, *pbitnum
;
2734 HOST_WIDE_INT offset
= 0;
2736 if (GET_CODE (ref
) != MEM
)
2739 if (reload_in_progress
2740 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2742 base
= find_replacement (&XEXP (ref
, 0));
2744 if (! memory_address_p (GET_MODE (ref
), base
))
2749 base
= XEXP (ref
, 0);
2752 if (GET_CODE (base
) == PLUS
)
2753 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2756 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2758 if (WORDS_BIG_ENDIAN
)
2759 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2760 + (offset
& 3) * 8));
2762 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2765 /* Similar, but just get the address. Handle the two reload cases.
2766 Add EXTRA_OFFSET to the address we return. */
2769 get_unaligned_address (ref
, extra_offset
)
2774 HOST_WIDE_INT offset
= 0;
2776 if (GET_CODE (ref
) != MEM
)
2779 if (reload_in_progress
2780 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2782 base
= find_replacement (&XEXP (ref
, 0));
2784 if (! memory_address_p (GET_MODE (ref
), base
))
2789 base
= XEXP (ref
, 0);
2792 if (GET_CODE (base
) == PLUS
)
2793 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2795 return plus_constant (base
, offset
+ extra_offset
);
2798 /* On the Alpha, all (non-symbolic) constants except zero go into
2799 a floating-point register via memory. Note that we cannot
2800 return anything that is not a subset of CLASS, and that some
2801 symbolic constants cannot be dropped to memory. */
2804 alpha_preferred_reload_class(x
, class)
2806 enum reg_class
class;
2808 /* Zero is present in any register class. */
2809 if (x
== CONST0_RTX (GET_MODE (x
)))
2812 /* These sorts of constants we can easily drop to memory. */
2813 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2815 if (class == FLOAT_REGS
)
2817 if (class == ALL_REGS
)
2818 return GENERAL_REGS
;
2822 /* All other kinds of constants should not (and in the case of HIGH
2823 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2824 secondary reload. */
2826 return (class == ALL_REGS
? GENERAL_REGS
: class);
2831 /* Loading and storing HImode or QImode values to and from memory
2832 usually requires a scratch register. The exceptions are loading
2833 QImode and HImode from an aligned address to a general register
2834 unless byte instructions are permitted.
2836 We also cannot load an unaligned address or a paradoxical SUBREG
2837 into an FP register.
2839 We also cannot do integral arithmetic into FP regs, as might result
2840 from register elimination into a DImode fp register. */
2843 secondary_reload_class (class, mode
, x
, in
)
2844 enum reg_class
class;
2845 enum machine_mode mode
;
2849 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2851 if (GET_CODE (x
) == MEM
2852 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2853 || (GET_CODE (x
) == SUBREG
2854 && (GET_CODE (SUBREG_REG (x
)) == MEM
2855 || (GET_CODE (SUBREG_REG (x
)) == REG
2856 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2858 if (!in
|| !aligned_memory_operand(x
, mode
))
2859 return GENERAL_REGS
;
2863 if (class == FLOAT_REGS
)
2865 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2866 return GENERAL_REGS
;
2868 if (GET_CODE (x
) == SUBREG
2869 && (GET_MODE_SIZE (GET_MODE (x
))
2870 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2871 return GENERAL_REGS
;
2873 if (in
&& INTEGRAL_MODE_P (mode
)
2874 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2875 return GENERAL_REGS
;
2881 /* Subfunction of the following function. Update the flags of any MEM
2882 found in part of X. */
2885 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2887 int in_struct_p
, volatile_p
, unchanging_p
;
2891 switch (GET_CODE (x
))
2897 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2898 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2903 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2908 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2910 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2915 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2916 MEM_VOLATILE_P (x
) = volatile_p
;
2917 RTX_UNCHANGING_P (x
) = unchanging_p
;
2918 /* Sadly, we cannot use alias sets because the extra aliasing
2919 produced by the AND interferes. Given that two-byte quantities
2920 are the only thing we would be able to differentiate anyway,
2921 there does not seem to be any point in convoluting the early
2922 out of the alias check. */
2930 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2931 generated to perform a memory operation, look for any MEMs in either
2932 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2933 volatile flags from REF into each of the MEMs found. If REF is not
2934 a MEM, don't do anything. */
2937 alpha_set_memflags (insn
, ref
)
2941 int in_struct_p
, volatile_p
, unchanging_p
;
2943 if (GET_CODE (ref
) != MEM
)
2946 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2947 volatile_p
= MEM_VOLATILE_P (ref
);
2948 unchanging_p
= RTX_UNCHANGING_P (ref
);
2950 /* This is only called from alpha.md, after having had something
2951 generated from one of the insn patterns. So if everything is
2952 zero, the pattern is already up-to-date. */
2953 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2956 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2959 /* Try to output insns to set TARGET equal to the constant C if it can be
2960 done in less than N insns. Do all computations in MODE. Returns the place
2961 where the output has been placed if it can be done and the insns have been
2962 emitted. If it would take more than N insns, zero is returned and no
2963 insns and emitted. */
2966 alpha_emit_set_const (target
, mode
, c
, n
)
2968 enum machine_mode mode
;
2973 rtx orig_target
= target
;
2976 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2977 can't load this constant in one insn, do this in DImode. */
2978 if (no_new_pseudos
&& mode
== SImode
2979 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2980 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2982 target
= gen_lowpart (DImode
, target
);
2986 /* Try 1 insn, then 2, then up to N. */
2987 for (i
= 1; i
<= n
; i
++)
2989 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2992 rtx insn
= get_last_insn ();
2993 rtx set
= single_set (insn
);
2994 if (! CONSTANT_P (SET_SRC (set
)))
2995 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
3000 /* Allow for the case where we changed the mode of TARGET. */
3001 if (result
== target
)
3002 result
= orig_target
;
3007 /* Internal routine for the above to check for N or below insns. */
3010 alpha_emit_set_const_1 (target
, mode
, c
, n
)
3012 enum machine_mode mode
;
3018 /* Use a pseudo if highly optimizing and still generating RTL. */
3020 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
3023 /* If this is a sign-extended 32-bit constant, we can do this in at most
3024 three insns, so do it if we have enough insns left. We always have
3025 a sign-extended 32-bit constant when compiling on a narrow machine. */
3027 if (HOST_BITS_PER_WIDE_INT
!= 64
3028 || c
>> 31 == -1 || c
>> 31 == 0)
3030 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
3031 HOST_WIDE_INT tmp1
= c
- low
;
3032 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
3033 HOST_WIDE_INT extra
= 0;
3035 /* If HIGH will be interpreted as negative but the constant is
3036 positive, we must adjust it to do two ldha insns. */
3038 if ((high
& 0x8000) != 0 && c
>= 0)
3042 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
3045 if (c
== low
|| (low
== 0 && extra
== 0))
3047 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
3048 but that meant that we can't handle INT_MIN on 32-bit machines
3049 (like NT/Alpha), because we recurse indefinitely through
3050 emit_move_insn to gen_movdi. So instead, since we know exactly
3051 what we want, create it explicitly. */
3054 target
= gen_reg_rtx (mode
);
3055 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
3058 else if (n
>= 2 + (extra
!= 0))
3060 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
3062 /* As of 2002-02-23, addsi3 is only available when not optimizing.
3063 This means that if we go through expand_binop, we'll try to
3064 generate extensions, etc, which will require new pseudos, which
3065 will fail during some split phases. The SImode add patterns
3066 still exist, but are not named. So build the insns by hand. */
3071 subtarget
= gen_reg_rtx (mode
);
3072 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
3073 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
3079 target
= gen_reg_rtx (mode
);
3080 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
3081 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
3087 /* If we couldn't do it that way, try some other methods. But if we have
3088 no instructions left, don't bother. Likewise, if this is SImode and
3089 we can't make pseudos, we can't do anything since the expand_binop
3090 and expand_unop calls will widen and try to make pseudos. */
3092 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
3095 /* Next, see if we can load a related constant and then shift and possibly
3096 negate it to get the constant we want. Try this once each increasing
3097 numbers of insns. */
3099 for (i
= 1; i
< n
; i
++)
3101 /* First, see if minus some low bits, we've an easy load of
3104 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
3106 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
3107 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
3108 target
, 0, OPTAB_WIDEN
);
3110 /* Next try complementing. */
3111 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
3112 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
3114 /* Next try to form a constant and do a left shift. We can do this
3115 if some low-order bits are zero; the exact_log2 call below tells
3116 us that information. The bits we are shifting out could be any
3117 value, but here we'll just try the 0- and sign-extended forms of
3118 the constant. To try to increase the chance of having the same
3119 constant in more than one insn, start at the highest number of
3120 bits to shift, but try all possibilities in case a ZAPNOT will
3123 if ((bits
= exact_log2 (c
& - c
)) > 0)
3124 for (; bits
> 0; bits
--)
3125 if ((temp
= (alpha_emit_set_const
3126 (subtarget
, mode
, c
>> bits
, i
))) != 0
3127 || ((temp
= (alpha_emit_set_const
3129 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
3131 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
3132 target
, 0, OPTAB_WIDEN
);
3134 /* Now try high-order zero bits. Here we try the shifted-in bits as
3135 all zero and all ones. Be careful to avoid shifting outside the
3136 mode and to avoid shifting outside the host wide int size. */
3137 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
3138 confuse the recursive call and set all of the high 32 bits. */
3140 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
3141 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
3142 for (; bits
> 0; bits
--)
3143 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
3145 || ((temp
= (alpha_emit_set_const
3147 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
3150 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
3151 target
, 1, OPTAB_WIDEN
);
3153 /* Now try high-order 1 bits. We get that with a sign-extension.
3154 But one bit isn't enough here. Be careful to avoid shifting outside
3155 the mode and to avoid shifting outside the host wide int size. */
3157 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
3158 - floor_log2 (~ c
) - 2)) > 0)
3159 for (; bits
> 0; bits
--)
3160 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
3162 || ((temp
= (alpha_emit_set_const
3164 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
3167 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
3168 target
, 0, OPTAB_WIDEN
);
3171 #if HOST_BITS_PER_WIDE_INT == 64
3172 /* Finally, see if can load a value into the target that is the same as the
3173 constant except that all bytes that are 0 are changed to be 0xff. If we
3174 can, then we can do a ZAPNOT to obtain the desired constant. */
3177 for (i
= 0; i
< 64; i
+= 8)
3178 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
3179 new |= (HOST_WIDE_INT
) 0xff << i
;
3181 /* We are only called for SImode and DImode. If this is SImode, ensure that
3182 we are sign extended to a full word. */
3185 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
3187 if (new != c
&& new != -1
3188 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
3189 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
3190 target
, 0, OPTAB_WIDEN
);
3196 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
3197 fall back to a straight forward decomposition. We do this to avoid
3198 exponential run times encountered when looking for longer sequences
3199 with alpha_emit_set_const. */
3202 alpha_emit_set_long_const (target
, c1
, c2
)
3204 HOST_WIDE_INT c1
, c2
;
3206 HOST_WIDE_INT d1
, d2
, d3
, d4
;
3208 /* Decompose the entire word */
3209 #if HOST_BITS_PER_WIDE_INT >= 64
3210 if (c2
!= -(c1
< 0))
3212 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3214 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3215 c1
= (c1
- d2
) >> 32;
3216 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3218 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3222 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3224 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3228 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
3230 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3235 /* Construct the high word */
3238 emit_move_insn (target
, GEN_INT (d4
));
3240 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
3243 emit_move_insn (target
, GEN_INT (d3
));
3245 /* Shift it into place */
3246 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
3248 /* Add in the low bits. */
3250 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
3252 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
3257 /* Expand a move instruction; return true if all work is done.
3258 We don't handle non-bwx subword loads here. */
3261 alpha_expand_mov (mode
, operands
)
3262 enum machine_mode mode
;
3265 /* If the output is not a register, the input must be. */
3266 if (GET_CODE (operands
[0]) == MEM
3267 && ! reg_or_0_operand (operands
[1], mode
))
3268 operands
[1] = force_reg (mode
, operands
[1]);
3270 /* Allow legitimize_address to perform some simplifications. */
3271 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
3275 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
3276 compiled at the end of compilation. In the meantime, someone can
3277 re-encode-section-info on some symbol changing it e.g. from global
3278 to local-not-small. If this happens, we'd have emitted a plain
3279 load rather than a high+losum load and not recognize the insn.
3281 So if rtl inlining is in effect, we delay the global/not-global
3282 decision until rest_of_compilation by wrapping it in an
3284 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
3285 && rtx_equal_function_value_matters
3286 && global_symbolic_operand (operands
[1], mode
))
3288 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
3292 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
3295 if (tmp
== operands
[0])
3302 /* Early out for non-constants and valid constants. */
3303 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
3306 /* Split large integers. */
3307 if (GET_CODE (operands
[1]) == CONST_INT
3308 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
3310 HOST_WIDE_INT i0
, i1
;
3311 rtx temp
= NULL_RTX
;
3313 if (GET_CODE (operands
[1]) == CONST_INT
)
3315 i0
= INTVAL (operands
[1]);
3318 else if (HOST_BITS_PER_WIDE_INT
>= 64)
3320 i0
= CONST_DOUBLE_LOW (operands
[1]);
3325 i0
= CONST_DOUBLE_LOW (operands
[1]);
3326 i1
= CONST_DOUBLE_HIGH (operands
[1]);
3329 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
3330 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
3332 if (!temp
&& TARGET_BUILD_CONSTANTS
)
3333 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
3337 if (rtx_equal_p (operands
[0], temp
))
3344 /* Otherwise we've nothing left but to drop the thing to memory. */
3345 operands
[1] = force_const_mem (mode
, operands
[1]);
3346 if (reload_in_progress
)
3348 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
3349 operands
[1] = copy_rtx (operands
[1]);
3350 XEXP (operands
[1], 0) = operands
[0];
3353 operands
[1] = validize_mem (operands
[1]);
3357 /* Expand a non-bwx QImode or HImode move instruction;
3358 return true if all work is done. */
3361 alpha_expand_mov_nobwx (mode
, operands
)
3362 enum machine_mode mode
;
3365 /* If the output is not a register, the input must be. */
3366 if (GET_CODE (operands
[0]) == MEM
)
3367 operands
[1] = force_reg (mode
, operands
[1]);
3369 /* Handle four memory cases, unaligned and aligned for either the input
3370 or the output. The only case where we can be called during reload is
3371 for aligned loads; all other cases require temporaries. */
3373 if (GET_CODE (operands
[1]) == MEM
3374 || (GET_CODE (operands
[1]) == SUBREG
3375 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3376 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3377 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3378 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3379 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3380 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3382 if (aligned_memory_operand (operands
[1], mode
))
3384 if (reload_in_progress
)
3386 emit_insn ((mode
== QImode
3387 ? gen_reload_inqi_help
3388 : gen_reload_inhi_help
)
3389 (operands
[0], operands
[1],
3390 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3394 rtx aligned_mem
, bitnum
;
3395 rtx scratch
= gen_reg_rtx (SImode
);
3397 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3399 emit_insn ((mode
== QImode
3400 ? gen_aligned_loadqi
3401 : gen_aligned_loadhi
)
3402 (operands
[0], aligned_mem
, bitnum
, scratch
));
3407 /* Don't pass these as parameters since that makes the generated
3408 code depend on parameter evaluation order which will cause
3409 bootstrap failures. */
3411 rtx temp1
= gen_reg_rtx (DImode
);
3412 rtx temp2
= gen_reg_rtx (DImode
);
3413 rtx seq
= ((mode
== QImode
3414 ? gen_unaligned_loadqi
3415 : gen_unaligned_loadhi
)
3416 (operands
[0], get_unaligned_address (operands
[1], 0),
3419 alpha_set_memflags (seq
, operands
[1]);
3425 if (GET_CODE (operands
[0]) == MEM
3426 || (GET_CODE (operands
[0]) == SUBREG
3427 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3428 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3429 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3430 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3431 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3432 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3434 if (aligned_memory_operand (operands
[0], mode
))
3436 rtx aligned_mem
, bitnum
;
3437 rtx temp1
= gen_reg_rtx (SImode
);
3438 rtx temp2
= gen_reg_rtx (SImode
);
3440 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3442 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3447 rtx temp1
= gen_reg_rtx (DImode
);
3448 rtx temp2
= gen_reg_rtx (DImode
);
3449 rtx temp3
= gen_reg_rtx (DImode
);
3450 rtx seq
= ((mode
== QImode
3451 ? gen_unaligned_storeqi
3452 : gen_unaligned_storehi
)
3453 (get_unaligned_address (operands
[0], 0),
3454 operands
[1], temp1
, temp2
, temp3
));
3456 alpha_set_memflags (seq
, operands
[0]);
3465 /* Generate an unsigned DImode to FP conversion. This is the same code
3466 optabs would emit if we didn't have TFmode patterns.
3468 For SFmode, this is the only construction I've found that can pass
3469 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3470 intermediates will work, because you'll get intermediate rounding
3471 that ruins the end result. Some of this could be fixed by turning
3472 on round-to-positive-infinity, but that requires diddling the fpsr,
3473 which kills performance. I tried turning this around and converting
3474 to a negative number, so that I could turn on /m, but either I did
3475 it wrong or there's something else cause I wound up with the exact
3476 same single-bit error. There is a branch-less form of this same code:
3487 fcmoveq $f10,$f11,$f0
3489 I'm not using it because it's the same number of instructions as
3490 this branch-full form, and it has more serialized long latency
3491 instructions on the critical path.
3493 For DFmode, we can avoid rounding errors by breaking up the word
3494 into two pieces, converting them separately, and adding them back:
3496 LC0: .long 0,0x5f800000
3501 cpyse $f11,$f31,$f10
3502 cpyse $f31,$f11,$f11
3510 This doesn't seem to be a clear-cut win over the optabs form.
3511 It probably all depends on the distribution of numbers being
3512 converted -- in the optabs form, all but high-bit-set has a
3513 much lower minimum execution time. */
3516 alpha_emit_floatuns (operands
)
3519 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3520 enum machine_mode mode
;
3523 in
= force_reg (DImode
, operands
[1]);
3524 mode
= GET_MODE (out
);
3525 neglab
= gen_label_rtx ();
3526 donelab
= gen_label_rtx ();
3527 i0
= gen_reg_rtx (DImode
);
3528 i1
= gen_reg_rtx (DImode
);
3529 f0
= gen_reg_rtx (mode
);
3531 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3533 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3534 emit_jump_insn (gen_jump (donelab
));
3537 emit_label (neglab
);
3539 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3540 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3541 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3542 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3543 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3545 emit_label (donelab
);
3548 /* Generate the comparison for a conditional branch. */
3551 alpha_emit_conditional_branch (code
)
3554 enum rtx_code cmp_code
, branch_code
;
3555 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3556 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3559 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3561 if (! TARGET_HAS_XFLOATING_LIBS
)
3564 /* X_floating library comparison functions return
3568 Convert the compare against the raw return value. */
3590 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3592 alpha_compare
.fp_p
= 0;
3595 /* The general case: fold the comparison code to the types of compares
3596 that we have, choosing the branch as necessary. */
3599 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3601 /* We have these compares: */
3602 cmp_code
= code
, branch_code
= NE
;
3607 /* These must be reversed. */
3608 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3611 case GE
: case GT
: case GEU
: case GTU
:
3612 /* For FP, we swap them, for INT, we reverse them. */
3613 if (alpha_compare
.fp_p
)
3615 cmp_code
= swap_condition (code
);
3617 tem
= op0
, op0
= op1
, op1
= tem
;
3621 cmp_code
= reverse_condition (code
);
3630 if (alpha_compare
.fp_p
)
3633 if (flag_unsafe_math_optimizations
)
3635 /* When we are not as concerned about non-finite values, and we
3636 are comparing against zero, we can branch directly. */
3637 if (op1
== CONST0_RTX (DFmode
))
3638 cmp_code
= NIL
, branch_code
= code
;
3639 else if (op0
== CONST0_RTX (DFmode
))
3641 /* Undo the swap we probably did just above. */
3642 tem
= op0
, op0
= op1
, op1
= tem
;
3643 branch_code
= swap_condition (cmp_code
);
3649 /* ??? We mark the branch mode to be CCmode to prevent the
3650 compare and branch from being combined, since the compare
3651 insn follows IEEE rules that the branch does not. */
3652 branch_mode
= CCmode
;
3659 /* The following optimizations are only for signed compares. */
3660 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3662 /* Whee. Compare and branch against 0 directly. */
3663 if (op1
== const0_rtx
)
3664 cmp_code
= NIL
, branch_code
= code
;
3666 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3667 bypass between logicals and br/cmov on EV5. But we don't want to
3668 force valid immediate constants into registers needlessly. */
3669 else if (GET_CODE (op1
) == CONST_INT
)
3671 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3673 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3674 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3675 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3677 cmp_code
= PLUS
, branch_code
= code
;
3683 if (!reg_or_0_operand (op0
, DImode
))
3684 op0
= force_reg (DImode
, op0
);
3685 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3686 op1
= force_reg (DImode
, op1
);
3689 /* Emit an initial compare instruction, if necessary. */
3691 if (cmp_code
!= NIL
)
3693 tem
= gen_reg_rtx (cmp_mode
);
3694 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3697 /* Zero the operands. */
3698 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3700 /* Return the branch comparison. */
3701 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3704 /* Certain simplifications can be done to make invalid setcc operations
3705 valid. Return the final comparison, or NULL if we can't work. */
3708 alpha_emit_setcc (code
)
3711 enum rtx_code cmp_code
;
3712 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3713 int fp_p
= alpha_compare
.fp_p
;
3716 /* Zero the operands. */
3717 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3719 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3721 if (! TARGET_HAS_XFLOATING_LIBS
)
3724 /* X_floating library comparison functions return
3728 Convert the compare against the raw return value. */
3730 if (code
== UNORDERED
|| code
== ORDERED
)
3735 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3739 if (code
== UNORDERED
)
3741 else if (code
== ORDERED
)
3747 if (fp_p
&& !TARGET_FIX
)
3750 /* The general case: fold the comparison code to the types of compares
3751 that we have, choosing the branch as necessary. */
3756 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3758 /* We have these compares. */
3760 cmp_code
= code
, code
= NE
;
3764 if (!fp_p
&& op1
== const0_rtx
)
3769 cmp_code
= reverse_condition (code
);
3773 case GE
: case GT
: case GEU
: case GTU
:
3774 /* These normally need swapping, but for integer zero we have
3775 special patterns that recognize swapped operands. */
3776 if (!fp_p
&& op1
== const0_rtx
)
3778 code
= swap_condition (code
);
3780 cmp_code
= code
, code
= NE
;
3781 tmp
= op0
, op0
= op1
, op1
= tmp
;
3790 if (!register_operand (op0
, DImode
))
3791 op0
= force_reg (DImode
, op0
);
3792 if (!reg_or_8bit_operand (op1
, DImode
))
3793 op1
= force_reg (DImode
, op1
);
3796 /* Emit an initial compare instruction, if necessary. */
3797 if (cmp_code
!= NIL
)
3799 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3801 tmp
= gen_reg_rtx (mode
);
3802 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3803 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3805 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3809 /* Return the setcc comparison. */
3810 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3814 /* Rewrite a comparison against zero CMP of the form
3815 (CODE (cc0) (const_int 0)) so it can be written validly in
3816 a conditional move (if_then_else CMP ...).
3817 If both of the operands that set cc0 are nonzero we must emit
3818 an insn to perform the compare (it can't be done within
3819 the conditional move). */
3821 alpha_emit_conditional_move (cmp
, mode
)
3823 enum machine_mode mode
;
3825 enum rtx_code code
= GET_CODE (cmp
);
3826 enum rtx_code cmov_code
= NE
;
3827 rtx op0
= alpha_compare
.op0
;
3828 rtx op1
= alpha_compare
.op1
;
3829 int fp_p
= alpha_compare
.fp_p
;
3830 enum machine_mode cmp_mode
3831 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3832 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3833 enum machine_mode cmov_mode
= VOIDmode
;
3834 int local_fast_math
= flag_unsafe_math_optimizations
;
3837 /* Zero the operands. */
3838 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3840 if (fp_p
!= FLOAT_MODE_P (mode
))
3842 enum rtx_code cmp_code
;
3847 /* If we have fp<->int register move instructions, do a cmov by
3848 performing the comparison in fp registers, and move the
3849 zero/nonzero value to integer registers, where we can then
3850 use a normal cmov, or vice-versa. */
3854 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3855 /* We have these compares. */
3856 cmp_code
= code
, code
= NE
;
3860 /* This must be reversed. */
3861 cmp_code
= EQ
, code
= EQ
;
3864 case GE
: case GT
: case GEU
: case GTU
:
3865 /* These normally need swapping, but for integer zero we have
3866 special patterns that recognize swapped operands. */
3867 if (!fp_p
&& op1
== const0_rtx
)
3868 cmp_code
= code
, code
= NE
;
3871 cmp_code
= swap_condition (code
);
3873 tem
= op0
, op0
= op1
, op1
= tem
;
3881 tem
= gen_reg_rtx (cmp_op_mode
);
3882 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3883 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3886 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3887 op0
= gen_lowpart (cmp_op_mode
, tem
);
3888 op1
= CONST0_RTX (cmp_op_mode
);
3890 local_fast_math
= 1;
3893 /* We may be able to use a conditional move directly.
3894 This avoids emitting spurious compares. */
3895 if (signed_comparison_operator (cmp
, VOIDmode
)
3896 && (!fp_p
|| local_fast_math
)
3897 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3898 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3900 /* We can't put the comparison inside the conditional move;
3901 emit a compare instruction and put that inside the
3902 conditional move. Make sure we emit only comparisons we have;
3903 swap or reverse as necessary. */
3910 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3911 /* We have these compares: */
3915 /* This must be reversed. */
3916 code
= reverse_condition (code
);
3920 case GE
: case GT
: case GEU
: case GTU
:
3921 /* These must be swapped. */
3922 if (op1
!= CONST0_RTX (cmp_mode
))
3924 code
= swap_condition (code
);
3925 tem
= op0
, op0
= op1
, op1
= tem
;
3935 if (!reg_or_0_operand (op0
, DImode
))
3936 op0
= force_reg (DImode
, op0
);
3937 if (!reg_or_8bit_operand (op1
, DImode
))
3938 op1
= force_reg (DImode
, op1
);
3941 /* ??? We mark the branch mode to be CCmode to prevent the compare
3942 and cmov from being combined, since the compare insn follows IEEE
3943 rules that the cmov does not. */
3944 if (fp_p
&& !local_fast_math
)
3947 tem
= gen_reg_rtx (cmp_op_mode
);
3948 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3949 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3952 /* Simplify a conditional move of two constants into a setcc with
3953 arithmetic. This is done with a splitter since combine would
3954 just undo the work if done during code generation. It also catches
3955 cases we wouldn't have before cse. */
3958 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3960 rtx dest
, cond
, t_rtx
, f_rtx
;
3962 HOST_WIDE_INT t
, f
, diff
;
3963 enum machine_mode mode
;
3964 rtx target
, subtarget
, tmp
;
3966 mode
= GET_MODE (dest
);
3971 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3972 || (code
== GE
|| code
== GT
))
3974 code
= reverse_condition (code
);
3975 diff
= t
, t
= f
, f
= diff
;
3979 subtarget
= target
= dest
;
3982 target
= gen_lowpart (DImode
, dest
);
3983 if (! no_new_pseudos
)
3984 subtarget
= gen_reg_rtx (DImode
);
3988 /* Below, we must be careful to use copy_rtx on target and subtarget
3989 in intermediate insns, as they may be a subreg rtx, which may not
3992 if (f
== 0 && exact_log2 (diff
) > 0
3993 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3994 viable over a longer latency cmove. On EV5, the E0 slot is a
3995 scarce resource, and on EV4 shift has the same latency as a cmove. */
3996 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3998 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3999 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
4001 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
4002 GEN_INT (exact_log2 (t
)));
4003 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
4005 else if (f
== 0 && t
== -1)
4007 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
4008 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
4010 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
4012 else if (diff
== 1 || diff
== 4 || diff
== 8)
4016 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
4017 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
4020 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
4023 add_op
= GEN_INT (f
);
4024 if (sext_add_operand (add_op
, mode
))
4026 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
4028 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
4029 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
4041 /* Look up the function X_floating library function name for the
4045 alpha_lookup_xfloating_lib_func (code
)
4050 const enum rtx_code code
;
4051 const char *const func
;
4054 static const struct xfloating_op vms_xfloating_ops
[] =
4056 { PLUS
, "OTS$ADD_X" },
4057 { MINUS
, "OTS$SUB_X" },
4058 { MULT
, "OTS$MUL_X" },
4059 { DIV
, "OTS$DIV_X" },
4060 { EQ
, "OTS$EQL_X" },
4061 { NE
, "OTS$NEQ_X" },
4062 { LT
, "OTS$LSS_X" },
4063 { LE
, "OTS$LEQ_X" },
4064 { GT
, "OTS$GTR_X" },
4065 { GE
, "OTS$GEQ_X" },
4066 { FIX
, "OTS$CVTXQ" },
4067 { FLOAT
, "OTS$CVTQX" },
4068 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
4069 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
4070 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
4073 static const struct xfloating_op osf_xfloating_ops
[] =
4075 { PLUS
, "_OtsAddX" },
4076 { MINUS
, "_OtsSubX" },
4077 { MULT
, "_OtsMulX" },
4078 { DIV
, "_OtsDivX" },
4085 { FIX
, "_OtsCvtXQ" },
4086 { FLOAT
, "_OtsCvtQX" },
4087 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
4088 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
4089 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
4092 const struct xfloating_op
*ops
;
4093 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
4096 /* How irritating. Nothing to key off for the table. Hardcode
4097 knowledge of the G_floating routines. */
4098 if (TARGET_FLOAT_VAX
)
4100 if (TARGET_ABI_OPEN_VMS
)
4102 if (code
== FLOAT_EXTEND
)
4103 return "OTS$CVT_FLOAT_G_X";
4104 if (code
== FLOAT_TRUNCATE
)
4105 return "OTS$CVT_FLOAT_X_G";
4109 if (code
== FLOAT_EXTEND
)
4110 return "_OtsConvertFloatGX";
4111 if (code
== FLOAT_TRUNCATE
)
4112 return "_OtsConvertFloatXG";
4116 if (TARGET_ABI_OPEN_VMS
)
4117 ops
= vms_xfloating_ops
;
4119 ops
= osf_xfloating_ops
;
4121 for (i
= 0; i
< n
; ++i
)
4122 if (ops
[i
].code
== code
)
4128 /* Most X_floating operations take the rounding mode as an argument.
4129 Compute that here. */
4132 alpha_compute_xfloating_mode_arg (code
, round
)
4134 enum alpha_fp_rounding_mode round
;
4140 case ALPHA_FPRM_NORM
:
4143 case ALPHA_FPRM_MINF
:
4146 case ALPHA_FPRM_CHOP
:
4149 case ALPHA_FPRM_DYN
:
4155 /* XXX For reference, round to +inf is mode = 3. */
4158 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
4164 /* Emit an X_floating library function call.
4166 Note that these functions do not follow normal calling conventions:
4167 TFmode arguments are passed in two integer registers (as opposed to
4168 indirect); TFmode return values appear in R16+R17.
4170 FUNC is the function name to call.
4171 TARGET is where the output belongs.
4172 OPERANDS are the inputs.
4173 NOPERANDS is the count of inputs.
4174 EQUIV is the expression equivalent for the function.
4178 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
4185 rtx usage
= NULL_RTX
, tmp
, reg
;
4190 for (i
= 0; i
< noperands
; ++i
)
4192 switch (GET_MODE (operands
[i
]))
4195 reg
= gen_rtx_REG (TFmode
, regno
);
4200 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
4205 if (GET_CODE (operands
[i
]) != CONST_INT
)
4209 reg
= gen_rtx_REG (DImode
, regno
);
4217 emit_move_insn (reg
, operands
[i
]);
4218 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
4221 switch (GET_MODE (target
))
4224 reg
= gen_rtx_REG (TFmode
, 16);
4227 reg
= gen_rtx_REG (DFmode
, 32);
4230 reg
= gen_rtx_REG (DImode
, 0);
4236 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
4237 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
4238 const0_rtx
, const0_rtx
));
4239 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
4244 emit_libcall_block (tmp
, target
, reg
, equiv
);
4247 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
4250 alpha_emit_xfloating_arith (code
, operands
)
4256 rtx out_operands
[3];
4258 func
= alpha_lookup_xfloating_lib_func (code
);
4259 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4261 out_operands
[0] = operands
[1];
4262 out_operands
[1] = operands
[2];
4263 out_operands
[2] = GEN_INT (mode
);
4264 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
4265 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
4269 /* Emit an X_floating library function call for a comparison. */
4272 alpha_emit_xfloating_compare (code
, op0
, op1
)
4277 rtx out
, operands
[2];
4279 func
= alpha_lookup_xfloating_lib_func (code
);
4283 out
= gen_reg_rtx (DImode
);
4285 /* ??? Strange mode for equiv because what's actually returned
4286 is -1,0,1, not a proper boolean value. */
4287 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
4288 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
4293 /* Emit an X_floating library function call for a conversion. */
4296 alpha_emit_xfloating_cvt (code
, operands
)
4300 int noperands
= 1, mode
;
4301 rtx out_operands
[2];
4304 func
= alpha_lookup_xfloating_lib_func (code
);
4306 out_operands
[0] = operands
[1];
4311 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
4312 out_operands
[1] = GEN_INT (mode
);
4315 case FLOAT_TRUNCATE
:
4316 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4317 out_operands
[1] = GEN_INT (mode
);
4324 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
4325 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
4329 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
4330 OP[0] into OP[0,1]. Naturally, output operand ordering is
4334 alpha_split_tfmode_pair (operands
)
4337 if (GET_CODE (operands
[1]) == REG
)
4339 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
4340 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
4342 else if (GET_CODE (operands
[1]) == MEM
)
4344 operands
[3] = adjust_address (operands
[1], DImode
, 8);
4345 operands
[2] = adjust_address (operands
[1], DImode
, 0);
4347 else if (operands
[1] == CONST0_RTX (TFmode
))
4348 operands
[2] = operands
[3] = const0_rtx
;
4352 if (GET_CODE (operands
[0]) == REG
)
4354 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
4355 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
4357 else if (GET_CODE (operands
[0]) == MEM
)
4359 operands
[1] = adjust_address (operands
[0], DImode
, 8);
4360 operands
[0] = adjust_address (operands
[0], DImode
, 0);
4366 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4367 op2 is a register containing the sign bit, operation is the
4368 logical operation to be performed. */
4371 alpha_split_tfmode_frobsign (operands
, operation
)
4373 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4375 rtx high_bit
= operands
[2];
4379 alpha_split_tfmode_pair (operands
);
4381 /* Detect three flavors of operand overlap. */
4383 if (rtx_equal_p (operands
[0], operands
[2]))
4385 else if (rtx_equal_p (operands
[1], operands
[2]))
4387 if (rtx_equal_p (operands
[0], high_bit
))
4394 emit_move_insn (operands
[0], operands
[2]);
4396 /* ??? If the destination overlaps both source tf and high_bit, then
4397 assume source tf is dead in its entirety and use the other half
4398 for a scratch register. Otherwise "scratch" is just the proper
4399 destination register. */
4400 scratch
= operands
[move
< 2 ? 1 : 3];
4402 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4406 emit_move_insn (operands
[0], operands
[2]);
4408 emit_move_insn (operands
[1], scratch
);
4412 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4416 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4417 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4418 lda r3,X(r11) lda r3,X+2(r11)
4419 extwl r1,r3,r1 extql r1,r3,r1
4420 extwh r2,r3,r2 extqh r2,r3,r2
4421 or r1.r2.r1 or r1,r2,r1
4424 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4425 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4426 lda r3,X(r11) lda r3,X(r11)
4427 extll r1,r3,r1 extll r1,r3,r1
4428 extlh r2,r3,r2 extlh r2,r3,r2
4429 or r1.r2.r1 addl r1,r2,r1
4431 quad: ldq_u r1,X(r11)
4440 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4442 HOST_WIDE_INT size
, ofs
;
4445 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4446 enum machine_mode mode
;
4448 meml
= gen_reg_rtx (DImode
);
4449 memh
= gen_reg_rtx (DImode
);
4450 addr
= gen_reg_rtx (DImode
);
4451 extl
= gen_reg_rtx (DImode
);
4452 exth
= gen_reg_rtx (DImode
);
4454 mema
= XEXP (mem
, 0);
4455 if (GET_CODE (mema
) == LO_SUM
)
4456 mema
= force_reg (Pmode
, mema
);
4458 /* AND addresses cannot be in any alias set, since they may implicitly
4459 alias surrounding code. Ideally we'd have some alias set that
4460 covered all types except those with alignment 8 or higher. */
4462 tmp
= change_address (mem
, DImode
,
4463 gen_rtx_AND (DImode
,
4464 plus_constant (mema
, ofs
),
4466 set_mem_alias_set (tmp
, 0);
4467 emit_move_insn (meml
, tmp
);
4469 tmp
= change_address (mem
, DImode
,
4470 gen_rtx_AND (DImode
,
4471 plus_constant (mema
, ofs
+ size
- 1),
4473 set_mem_alias_set (tmp
, 0);
4474 emit_move_insn (memh
, tmp
);
4476 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4478 emit_move_insn (addr
, plus_constant (mema
, -1));
4480 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4481 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4483 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4484 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4485 addr
, 1, OPTAB_WIDEN
);
4487 else if (sign
&& size
== 2)
4489 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4491 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4492 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4494 /* We must use tgt here for the target. Alpha-vms port fails if we use
4495 addr for the target, because addr is marked as a pointer and combine
4496 knows that pointers are always sign-extended 32 bit values. */
4497 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4498 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4499 addr
, 1, OPTAB_WIDEN
);
4503 if (WORDS_BIG_ENDIAN
)
4505 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4509 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4514 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4519 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4526 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4530 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4531 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4535 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4540 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4545 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4554 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4555 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4560 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4563 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4566 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4568 HOST_WIDE_INT size
, ofs
;
4570 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4572 dstl
= gen_reg_rtx (DImode
);
4573 dsth
= gen_reg_rtx (DImode
);
4574 insl
= gen_reg_rtx (DImode
);
4575 insh
= gen_reg_rtx (DImode
);
4577 dsta
= XEXP (dst
, 0);
4578 if (GET_CODE (dsta
) == LO_SUM
)
4579 dsta
= force_reg (Pmode
, dsta
);
4581 /* AND addresses cannot be in any alias set, since they may implicitly
4582 alias surrounding code. Ideally we'd have some alias set that
4583 covered all types except those with alignment 8 or higher. */
4585 meml
= change_address (dst
, DImode
,
4586 gen_rtx_AND (DImode
,
4587 plus_constant (dsta
, ofs
),
4589 set_mem_alias_set (meml
, 0);
4591 memh
= change_address (dst
, DImode
,
4592 gen_rtx_AND (DImode
,
4593 plus_constant (dsta
, ofs
+ size
- 1),
4595 set_mem_alias_set (memh
, 0);
4597 emit_move_insn (dsth
, memh
);
4598 emit_move_insn (dstl
, meml
);
4599 if (WORDS_BIG_ENDIAN
)
4601 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4603 if (src
!= const0_rtx
)
4608 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4611 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4614 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4617 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4618 GEN_INT (size
*8), addr
));
4624 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4628 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4629 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4633 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4637 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4641 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4643 if (src
!= const0_rtx
)
4645 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4646 GEN_INT (size
*8), addr
));
4651 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4654 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4657 emit_insn (gen_insql_le (insl
, src
, addr
));
4662 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4667 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4671 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4672 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4676 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4681 if (src
!= const0_rtx
)
4683 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4684 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4687 if (WORDS_BIG_ENDIAN
)
4689 emit_move_insn (meml
, dstl
);
4690 emit_move_insn (memh
, dsth
);
4694 /* Must store high before low for degenerate case of aligned. */
4695 emit_move_insn (memh
, dsth
);
4696 emit_move_insn (meml
, dstl
);
4700 /* The block move code tries to maximize speed by separating loads and
4701 stores at the expense of register pressure: we load all of the data
4702 before we store it back out. There are two secondary effects worth
4703 mentioning, that this speeds copying to/from aligned and unaligned
4704 buffers, and that it makes the code significantly easier to write. */
4706 #define MAX_MOVE_WORDS 8
4708 /* Load an integral number of consecutive unaligned quadwords. */
4711 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4714 HOST_WIDE_INT words
, ofs
;
4716 rtx
const im8
= GEN_INT (-8);
4717 rtx
const i64
= GEN_INT (64);
4718 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4719 rtx sreg
, areg
, tmp
, smema
;
4722 smema
= XEXP (smem
, 0);
4723 if (GET_CODE (smema
) == LO_SUM
)
4724 smema
= force_reg (Pmode
, smema
);
4726 /* Generate all the tmp registers we need. */
4727 for (i
= 0; i
< words
; ++i
)
4729 data_regs
[i
] = out_regs
[i
];
4730 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4732 data_regs
[words
] = gen_reg_rtx (DImode
);
4735 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4737 /* Load up all of the source data. */
4738 for (i
= 0; i
< words
; ++i
)
4740 tmp
= change_address (smem
, DImode
,
4741 gen_rtx_AND (DImode
,
4742 plus_constant (smema
, 8*i
),
4744 set_mem_alias_set (tmp
, 0);
4745 emit_move_insn (data_regs
[i
], tmp
);
4748 tmp
= change_address (smem
, DImode
,
4749 gen_rtx_AND (DImode
,
4750 plus_constant (smema
, 8*words
- 1),
4752 set_mem_alias_set (tmp
, 0);
4753 emit_move_insn (data_regs
[words
], tmp
);
4755 /* Extract the half-word fragments. Unfortunately DEC decided to make
4756 extxh with offset zero a noop instead of zeroing the register, so
4757 we must take care of that edge condition ourselves with cmov. */
4759 sreg
= copy_addr_to_reg (smema
);
4760 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4762 if (WORDS_BIG_ENDIAN
)
4763 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4764 for (i
= 0; i
< words
; ++i
)
4766 if (WORDS_BIG_ENDIAN
)
4768 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4769 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4773 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4774 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4776 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4777 gen_rtx_IF_THEN_ELSE (DImode
,
4778 gen_rtx_EQ (DImode
, areg
,
4780 const0_rtx
, ext_tmps
[i
])));
4783 /* Merge the half-words into whole words. */
4784 for (i
= 0; i
< words
; ++i
)
4786 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4787 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4791 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4792 may be NULL to store zeros. */
4795 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4798 HOST_WIDE_INT words
, ofs
;
4800 rtx
const im8
= GEN_INT (-8);
4801 rtx
const i64
= GEN_INT (64);
4802 rtx ins_tmps
[MAX_MOVE_WORDS
];
4803 rtx st_tmp_1
, st_tmp_2
, dreg
;
4804 rtx st_addr_1
, st_addr_2
, dmema
;
4807 dmema
= XEXP (dmem
, 0);
4808 if (GET_CODE (dmema
) == LO_SUM
)
4809 dmema
= force_reg (Pmode
, dmema
);
4811 /* Generate all the tmp registers we need. */
4812 if (data_regs
!= NULL
)
4813 for (i
= 0; i
< words
; ++i
)
4814 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4815 st_tmp_1
= gen_reg_rtx(DImode
);
4816 st_tmp_2
= gen_reg_rtx(DImode
);
4819 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4821 st_addr_2
= change_address (dmem
, DImode
,
4822 gen_rtx_AND (DImode
,
4823 plus_constant (dmema
, words
*8 - 1),
4825 set_mem_alias_set (st_addr_2
, 0);
4827 st_addr_1
= change_address (dmem
, DImode
,
4828 gen_rtx_AND (DImode
, dmema
, im8
));
4829 set_mem_alias_set (st_addr_1
, 0);
4831 /* Load up the destination end bits. */
4832 emit_move_insn (st_tmp_2
, st_addr_2
);
4833 emit_move_insn (st_tmp_1
, st_addr_1
);
4835 /* Shift the input data into place. */
4836 dreg
= copy_addr_to_reg (dmema
);
4837 if (WORDS_BIG_ENDIAN
)
4838 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4839 if (data_regs
!= NULL
)
4841 for (i
= words
-1; i
>= 0; --i
)
4843 if (WORDS_BIG_ENDIAN
)
4845 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4846 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4850 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4851 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4854 for (i
= words
-1; i
> 0; --i
)
4856 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4857 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4862 /* Split and merge the ends with the destination data. */
4863 if (WORDS_BIG_ENDIAN
)
4865 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4866 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4870 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4871 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4874 if (data_regs
!= NULL
)
4876 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4877 st_tmp_2
, 1, OPTAB_WIDEN
);
4878 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4879 st_tmp_1
, 1, OPTAB_WIDEN
);
4883 if (WORDS_BIG_ENDIAN
)
4884 emit_move_insn (st_addr_1
, st_tmp_1
);
4886 emit_move_insn (st_addr_2
, st_tmp_2
);
4887 for (i
= words
-1; i
> 0; --i
)
4889 rtx tmp
= change_address (dmem
, DImode
,
4890 gen_rtx_AND (DImode
,
4891 plus_constant(dmema
,
4892 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4894 set_mem_alias_set (tmp
, 0);
4895 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4897 if (WORDS_BIG_ENDIAN
)
4898 emit_move_insn (st_addr_2
, st_tmp_2
);
4900 emit_move_insn (st_addr_1
, st_tmp_1
);
4904 /* Expand string/block move operations.
4906 operands[0] is the pointer to the destination.
4907 operands[1] is the pointer to the source.
4908 operands[2] is the number of bytes to move.
4909 operands[3] is the alignment. */
4912 alpha_expand_block_move (operands
)
4915 rtx bytes_rtx
= operands
[2];
4916 rtx align_rtx
= operands
[3];
4917 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4918 HOST_WIDE_INT bytes
= orig_bytes
;
4919 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4920 HOST_WIDE_INT dst_align
= src_align
;
4921 rtx orig_src
= operands
[1];
4922 rtx orig_dst
= operands
[0];
4923 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4925 unsigned int i
, words
, ofs
, nregs
= 0;
4927 if (orig_bytes
<= 0)
4929 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4932 /* Look for additional alignment information from recorded register info. */
4934 tmp
= XEXP (orig_src
, 0);
4935 if (GET_CODE (tmp
) == REG
)
4936 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4937 else if (GET_CODE (tmp
) == PLUS
4938 && GET_CODE (XEXP (tmp
, 0)) == REG
4939 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4941 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4942 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4946 if (a
>= 64 && c
% 8 == 0)
4948 else if (a
>= 32 && c
% 4 == 0)
4950 else if (a
>= 16 && c
% 2 == 0)
4955 tmp
= XEXP (orig_dst
, 0);
4956 if (GET_CODE (tmp
) == REG
)
4957 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4958 else if (GET_CODE (tmp
) == PLUS
4959 && GET_CODE (XEXP (tmp
, 0)) == REG
4960 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4962 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4963 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4967 if (a
>= 64 && c
% 8 == 0)
4969 else if (a
>= 32 && c
% 4 == 0)
4971 else if (a
>= 16 && c
% 2 == 0)
4976 /* Load the entire block into registers. */
4977 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4979 enum machine_mode mode
;
4981 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4983 /* Don't use the existing register if we're reading more than
4984 is held in the register. Nor if there is not a mode that
4985 handles the exact size. */
4986 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4988 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4992 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4993 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4997 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
5002 /* No appropriate mode; fall back on memory. */
5003 orig_src
= replace_equiv_address (orig_src
,
5004 copy_addr_to_reg (XEXP (orig_src
, 0)));
5005 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
5009 if (src_align
>= 64 && bytes
>= 8)
5013 for (i
= 0; i
< words
; ++i
)
5014 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
5016 for (i
= 0; i
< words
; ++i
)
5017 emit_move_insn (data_regs
[nregs
+ i
],
5018 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
5025 if (src_align
>= 32 && bytes
>= 4)
5029 for (i
= 0; i
< words
; ++i
)
5030 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
5032 for (i
= 0; i
< words
; ++i
)
5033 emit_move_insn (data_regs
[nregs
+ i
],
5034 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
5045 for (i
= 0; i
< words
+1; ++i
)
5046 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
5048 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
5056 if (! TARGET_BWX
&& bytes
>= 4)
5058 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
5059 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
5066 if (src_align
>= 16)
5069 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
5070 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
5073 } while (bytes
>= 2);
5075 else if (! TARGET_BWX
)
5077 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
5078 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
5086 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
5087 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
5094 if (nregs
> ARRAY_SIZE (data_regs
))
5097 /* Now save it back out again. */
5101 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
5103 enum machine_mode mode
;
5104 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
5106 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
5107 if (GET_MODE (tmp
) == mode
)
5111 emit_move_insn (tmp
, data_regs
[0]);
5116 else if (nregs
== 2 && mode
== TImode
)
5118 /* Undo the subregging done above when copying between
5119 two TImode registers. */
5120 if (GET_CODE (data_regs
[0]) == SUBREG
5121 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
5122 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
5128 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
5129 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
5133 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
5134 data_regs
[1], NULL_RTX
);
5142 /* ??? If nregs > 1, consider reconstructing the word in regs. */
5143 /* ??? Optimize mode < dst_mode with strict_low_part. */
5145 /* No appropriate mode; fall back on memory. We can speed things
5146 up by recognizing extra alignment information. */
5147 orig_dst
= replace_equiv_address (orig_dst
,
5148 copy_addr_to_reg (XEXP (orig_dst
, 0)));
5149 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
5152 /* Write out the data in whatever chunks reading the source allowed. */
5153 if (dst_align
>= 64)
5155 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5157 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
5164 if (dst_align
>= 32)
5166 /* If the source has remaining DImode regs, write them out in
5168 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5170 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
5171 NULL_RTX
, 1, OPTAB_WIDEN
);
5173 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5174 gen_lowpart (SImode
, data_regs
[i
]));
5175 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
5176 gen_lowpart (SImode
, tmp
));
5181 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5183 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5190 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5192 /* Write out a remaining block of words using unaligned methods. */
5194 for (words
= 1; i
+ words
< nregs
; words
++)
5195 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
5199 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
5201 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
5208 /* Due to the above, this won't be aligned. */
5209 /* ??? If we have more than one of these, consider constructing full
5210 words in registers and using alpha_expand_unaligned_store_words. */
5211 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5213 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
5218 if (dst_align
>= 16)
5219 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5221 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
5226 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5228 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
5233 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
5235 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
5249 alpha_expand_block_clear (operands
)
5252 rtx bytes_rtx
= operands
[1];
5253 rtx align_rtx
= operands
[2];
5254 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
5255 HOST_WIDE_INT bytes
= orig_bytes
;
5256 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
5257 HOST_WIDE_INT alignofs
= 0;
5258 rtx orig_dst
= operands
[0];
5260 int i
, words
, ofs
= 0;
5262 if (orig_bytes
<= 0)
5264 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
5267 /* Look for stricter alignment. */
5268 tmp
= XEXP (orig_dst
, 0);
5269 if (GET_CODE (tmp
) == REG
)
5270 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
5271 else if (GET_CODE (tmp
) == PLUS
5272 && GET_CODE (XEXP (tmp
, 0)) == REG
5273 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
5275 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
5276 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
5281 align
= a
, alignofs
= 8 - c
% 8;
5283 align
= a
, alignofs
= 4 - c
% 4;
5285 align
= a
, alignofs
= 2 - c
% 2;
5288 else if (GET_CODE (tmp
) == ADDRESSOF
)
5290 enum machine_mode mode
;
5292 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
5293 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
5295 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
5299 /* No appropriate mode; fall back on memory. */
5300 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
5301 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
5304 /* Handle an unaligned prefix first. */
5308 #if HOST_BITS_PER_WIDE_INT >= 64
5309 /* Given that alignofs is bounded by align, the only time BWX could
5310 generate three stores is for a 7 byte fill. Prefer two individual
5311 stores over a load/mask/store sequence. */
5312 if ((!TARGET_BWX
|| alignofs
== 7)
5314 && !(alignofs
== 4 && bytes
>= 4))
5316 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
5317 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
5321 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
5322 set_mem_alias_set (mem
, 0);
5324 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
5325 if (bytes
< alignofs
)
5327 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
5338 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
5339 NULL_RTX
, 1, OPTAB_WIDEN
);
5341 emit_move_insn (mem
, tmp
);
5345 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
5347 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5352 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
5354 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
5359 if (alignofs
== 4 && bytes
>= 4)
5361 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5367 /* If we've not used the extra lead alignment information by now,
5368 we won't be able to. Downgrade align to match what's left over. */
5371 alignofs
= alignofs
& -alignofs
;
5372 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5376 /* Handle a block of contiguous long-words. */
5378 if (align
>= 64 && bytes
>= 8)
5382 for (i
= 0; i
< words
; ++i
)
5383 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5390 /* If the block is large and appropriately aligned, emit a single
5391 store followed by a sequence of stq_u insns. */
5393 if (align
>= 32 && bytes
> 16)
5397 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5401 orig_dsta
= XEXP (orig_dst
, 0);
5402 if (GET_CODE (orig_dsta
) == LO_SUM
)
5403 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5406 for (i
= 0; i
< words
; ++i
)
5409 = change_address (orig_dst
, DImode
,
5410 gen_rtx_AND (DImode
,
5411 plus_constant (orig_dsta
, ofs
+ i
*8),
5413 set_mem_alias_set (mem
, 0);
5414 emit_move_insn (mem
, const0_rtx
);
5417 /* Depending on the alignment, the first stq_u may have overlapped
5418 with the initial stl, which means that the last stq_u didn't
5419 write as much as it would appear. Leave those questionable bytes
5421 bytes
-= words
* 8 - 4;
5422 ofs
+= words
* 8 - 4;
5425 /* Handle a smaller block of aligned words. */
5427 if ((align
>= 64 && bytes
== 4)
5428 || (align
== 32 && bytes
>= 4))
5432 for (i
= 0; i
< words
; ++i
)
5433 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5440 /* An unaligned block uses stq_u stores for as many as possible. */
5446 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5452 /* Next clean up any trailing pieces. */
5454 #if HOST_BITS_PER_WIDE_INT >= 64
5455 /* Count the number of bits in BYTES for which aligned stores could
5458 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5462 /* If we have appropriate alignment (and it wouldn't take too many
5463 instructions otherwise), mask out the bytes we need. */
5464 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5471 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5472 set_mem_alias_set (mem
, 0);
5474 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5476 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5477 NULL_RTX
, 1, OPTAB_WIDEN
);
5479 emit_move_insn (mem
, tmp
);
5482 else if (align
>= 32 && bytes
< 4)
5487 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5488 set_mem_alias_set (mem
, 0);
5490 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5492 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5493 NULL_RTX
, 1, OPTAB_WIDEN
);
5495 emit_move_insn (mem
, tmp
);
5501 if (!TARGET_BWX
&& bytes
>= 4)
5503 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5513 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5517 } while (bytes
>= 2);
5519 else if (! TARGET_BWX
)
5521 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5529 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5537 /* Returns a mask so that zap(x, value) == x & mask. */
5540 alpha_expand_zap_mask (value
)
5541 HOST_WIDE_INT value
;
5546 if (HOST_BITS_PER_WIDE_INT
>= 64)
5548 HOST_WIDE_INT mask
= 0;
5550 for (i
= 7; i
>= 0; --i
)
5553 if (!((value
>> i
) & 1))
5557 result
= gen_int_mode (mask
, DImode
);
5559 else if (HOST_BITS_PER_WIDE_INT
== 32)
5561 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5563 for (i
= 7; i
>= 4; --i
)
5566 if (!((value
>> i
) & 1))
5570 for (i
= 3; i
>= 0; --i
)
5573 if (!((value
>> i
) & 1))
5577 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5586 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5587 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5588 enum machine_mode mode
;
5591 op0
= gen_lowpart (mode
, op0
);
5593 if (op1
== const0_rtx
)
5594 op1
= CONST0_RTX (mode
);
5596 op1
= gen_lowpart (mode
, op1
);
5598 if (op2
== const0_rtx
)
5599 op2
= CONST0_RTX (mode
);
5601 op2
= gen_lowpart (mode
, op2
);
5603 emit_insn ((*gen
) (op0
, op1
, op2
));
5606 /* Adjust the cost of a scheduling dependency. Return the new cost of
5607 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5610 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5616 enum attr_type insn_type
, dep_insn_type
;
5618 /* If the dependence is an anti-dependence, there is no cost. For an
5619 output dependence, there is sometimes a cost, but it doesn't seem
5620 worth handling those few cases. */
5621 if (REG_NOTE_KIND (link
) != 0)
5624 /* If we can't recognize the insns, we can't really do anything. */
5625 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5628 insn_type
= get_attr_type (insn
);
5629 dep_insn_type
= get_attr_type (dep_insn
);
5631 /* Bring in the user-defined memory latency. */
5632 if (dep_insn_type
== TYPE_ILD
5633 || dep_insn_type
== TYPE_FLD
5634 || dep_insn_type
== TYPE_LDSYM
)
5635 cost
+= alpha_memory_latency
-1;
5637 /* Everything else handled in DFA bypasses now. */
5642 /* The number of instructions that can be issued per cycle. */
5647 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5651 alpha_use_dfa_pipeline_interface ()
5656 /* How many alternative schedules to try. This should be as wide as the
5657 scheduling freedom in the DFA, but no wider. Making this value too
5658 large results extra work for the scheduler.
5660 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5661 alternative schedules. For EV5, we can choose between E0/E1 and
5662 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5665 alpha_multipass_dfa_lookahead ()
5667 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5670 /* Machine-specific function data. */
5672 struct machine_function
GTY(())
5675 /* List of call information words for calls from this function. */
5676 struct rtx_def
*first_ciw
;
5677 struct rtx_def
*last_ciw
;
5680 /* List of deferred case vectors. */
5681 struct rtx_def
*addr_list
;
5684 const char *some_ld_name
;
5687 /* How to allocate a 'struct machine_function'. */
5689 static struct machine_function
*
5690 alpha_init_machine_status ()
5692 return ((struct machine_function
*)
5693 ggc_alloc_cleared (sizeof (struct machine_function
)));
5696 /* Functions to save and restore alpha_return_addr_rtx. */
5698 /* Start the ball rolling with RETURN_ADDR_RTX. */
5701 alpha_return_addr (count
, frame
)
5703 rtx frame ATTRIBUTE_UNUSED
;
5708 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5711 /* Return or create a pseudo containing the gp value for the current
5712 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5715 alpha_gp_save_rtx ()
5717 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5718 if (GET_CODE (r
) != MEM
)
5719 r
= gen_mem_addressof (r
, NULL_TREE
);
5724 alpha_ra_ever_killed ()
5728 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5729 return regs_ever_live
[REG_RA
];
5731 push_topmost_sequence ();
5733 pop_topmost_sequence ();
5735 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5739 /* Return the trap mode suffix applicable to the current
5740 instruction, or NULL. */
5743 get_trap_mode_suffix ()
5745 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5749 case TRAP_SUFFIX_NONE
:
5752 case TRAP_SUFFIX_SU
:
5753 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5757 case TRAP_SUFFIX_SUI
:
5758 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5762 case TRAP_SUFFIX_V_SV
:
5770 case ALPHA_FPTM_SUI
:
5775 case TRAP_SUFFIX_V_SV_SVI
:
5784 case ALPHA_FPTM_SUI
:
5789 case TRAP_SUFFIX_U_SU_SUI
:
5798 case ALPHA_FPTM_SUI
:
5806 /* Return the rounding mode suffix applicable to the current
5807 instruction, or NULL. */
5810 get_round_mode_suffix ()
5812 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5816 case ROUND_SUFFIX_NONE
:
5818 case ROUND_SUFFIX_NORMAL
:
5821 case ALPHA_FPRM_NORM
:
5823 case ALPHA_FPRM_MINF
:
5825 case ALPHA_FPRM_CHOP
:
5827 case ALPHA_FPRM_DYN
:
5832 case ROUND_SUFFIX_C
:
5838 /* Locate some local-dynamic symbol still in use by this function
5839 so that we can print its name in some movdi_er_tlsldm pattern. */
5842 get_some_local_dynamic_name ()
5846 if (cfun
->machine
->some_ld_name
)
5847 return cfun
->machine
->some_ld_name
;
5849 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5851 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5852 return cfun
->machine
->some_ld_name
;
5858 get_some_local_dynamic_name_1 (px
, data
)
5860 void *data ATTRIBUTE_UNUSED
;
5864 if (GET_CODE (x
) == SYMBOL_REF
)
5866 const char *str
= XSTR (x
, 0);
5867 if (str
[0] == '@' && str
[1] == 'D')
5869 cfun
->machine
->some_ld_name
= str
;
5877 /* Print an operand. Recognize special options, documented below. */
5880 print_operand (file
, x
, code
)
5890 /* Print the assembler name of the current function. */
5891 assemble_name (file
, alpha_fnname
);
5895 assemble_name (file
, get_some_local_dynamic_name ());
5900 const char *trap
= get_trap_mode_suffix ();
5901 const char *round
= get_round_mode_suffix ();
5904 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5905 (trap
? trap
: ""), (round
? round
: ""));
5910 /* Generates single precision instruction suffix. */
5911 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5915 /* Generates double precision instruction suffix. */
5916 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5920 if (alpha_this_literal_sequence_number
== 0)
5921 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5922 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5926 if (alpha_this_gpdisp_sequence_number
== 0)
5927 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5928 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5932 if (GET_CODE (x
) == HIGH
)
5933 output_addr_const (file
, XEXP (x
, 0));
5935 output_operand_lossage ("invalid %%H value");
5942 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5944 x
= XVECEXP (x
, 0, 0);
5945 lituse
= "lituse_tlsgd";
5947 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5949 x
= XVECEXP (x
, 0, 0);
5950 lituse
= "lituse_tlsldm";
5952 else if (GET_CODE (x
) == CONST_INT
)
5953 lituse
= "lituse_jsr";
5956 output_operand_lossage ("invalid %%J value");
5960 if (x
!= const0_rtx
)
5961 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5966 /* If this operand is the constant zero, write it as "$31". */
5967 if (GET_CODE (x
) == REG
)
5968 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5969 else if (x
== CONST0_RTX (GET_MODE (x
)))
5970 fprintf (file
, "$31");
5972 output_operand_lossage ("invalid %%r value");
5976 /* Similar, but for floating-point. */
5977 if (GET_CODE (x
) == REG
)
5978 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5979 else if (x
== CONST0_RTX (GET_MODE (x
)))
5980 fprintf (file
, "$f31");
5982 output_operand_lossage ("invalid %%R value");
5986 /* Write the 1's complement of a constant. */
5987 if (GET_CODE (x
) != CONST_INT
)
5988 output_operand_lossage ("invalid %%N value");
5990 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5994 /* Write 1 << C, for a constant C. */
5995 if (GET_CODE (x
) != CONST_INT
)
5996 output_operand_lossage ("invalid %%P value");
5998 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
6002 /* Write the high-order 16 bits of a constant, sign-extended. */
6003 if (GET_CODE (x
) != CONST_INT
)
6004 output_operand_lossage ("invalid %%h value");
6006 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
6010 /* Write the low-order 16 bits of a constant, sign-extended. */
6011 if (GET_CODE (x
) != CONST_INT
)
6012 output_operand_lossage ("invalid %%L value");
6014 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6015 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
6019 /* Write mask for ZAP insn. */
6020 if (GET_CODE (x
) == CONST_DOUBLE
)
6022 HOST_WIDE_INT mask
= 0;
6023 HOST_WIDE_INT value
;
6025 value
= CONST_DOUBLE_LOW (x
);
6026 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
6031 value
= CONST_DOUBLE_HIGH (x
);
6032 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
6035 mask
|= (1 << (i
+ sizeof (int)));
6037 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
6040 else if (GET_CODE (x
) == CONST_INT
)
6042 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
6044 for (i
= 0; i
< 8; i
++, value
>>= 8)
6048 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
6051 output_operand_lossage ("invalid %%m value");
6055 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
6056 if (GET_CODE (x
) != CONST_INT
6057 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
6058 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
6059 output_operand_lossage ("invalid %%M value");
6061 fprintf (file
, "%s",
6062 (INTVAL (x
) == 8 ? "b"
6063 : INTVAL (x
) == 16 ? "w"
6064 : INTVAL (x
) == 32 ? "l"
6069 /* Similar, except do it from the mask. */
6070 if (GET_CODE (x
) == CONST_INT
)
6072 HOST_WIDE_INT value
= INTVAL (x
);
6079 if (value
== 0xffff)
6084 if (value
== 0xffffffff)
6095 else if (HOST_BITS_PER_WIDE_INT
== 32
6096 && GET_CODE (x
) == CONST_DOUBLE
6097 && CONST_DOUBLE_LOW (x
) == 0xffffffff
6098 && CONST_DOUBLE_HIGH (x
) == 0)
6103 output_operand_lossage ("invalid %%U value");
6107 /* Write the constant value divided by 8 for little-endian mode or
6108 (56 - value) / 8 for big-endian mode. */
6110 if (GET_CODE (x
) != CONST_INT
6111 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
6114 || (INTVAL (x
) & 7) != 0)
6115 output_operand_lossage ("invalid %%s value");
6117 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6119 ? (56 - INTVAL (x
)) / 8
6124 /* Same, except compute (64 - c) / 8 */
6126 if (GET_CODE (x
) != CONST_INT
6127 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
6128 && (INTVAL (x
) & 7) != 8)
6129 output_operand_lossage ("invalid %%s value");
6131 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
6136 /* On Unicos/Mk systems: use a DEX expression if the symbol
6137 clashes with a register name. */
6138 int dex
= unicosmk_need_dex (x
);
6140 fprintf (file
, "DEX(%d)", dex
);
6142 output_addr_const (file
, x
);
6146 case 'C': case 'D': case 'c': case 'd':
6147 /* Write out comparison name. */
6149 enum rtx_code c
= GET_CODE (x
);
6151 if (GET_RTX_CLASS (c
) != '<')
6152 output_operand_lossage ("invalid %%C value");
6154 else if (code
== 'D')
6155 c
= reverse_condition (c
);
6156 else if (code
== 'c')
6157 c
= swap_condition (c
);
6158 else if (code
== 'd')
6159 c
= swap_condition (reverse_condition (c
));
6162 fprintf (file
, "ule");
6164 fprintf (file
, "ult");
6165 else if (c
== UNORDERED
)
6166 fprintf (file
, "un");
6168 fprintf (file
, "%s", GET_RTX_NAME (c
));
6173 /* Write the divide or modulus operator. */
6174 switch (GET_CODE (x
))
6177 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
6180 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
6183 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
6186 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
6189 output_operand_lossage ("invalid %%E value");
6195 /* Write "_u" for unaligned access. */
6196 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
6197 fprintf (file
, "_u");
6201 if (GET_CODE (x
) == REG
)
6202 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
6203 else if (GET_CODE (x
) == MEM
)
6204 output_address (XEXP (x
, 0));
6205 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6207 switch (XINT (XEXP (x
, 0), 1))
6211 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
6214 output_operand_lossage ("unknown relocation unspec");
6219 output_addr_const (file
, x
);
6223 output_operand_lossage ("invalid %%xn code");
6228 print_operand_address (file
, addr
)
6233 HOST_WIDE_INT offset
= 0;
6235 if (GET_CODE (addr
) == AND
)
6236 addr
= XEXP (addr
, 0);
6238 if (GET_CODE (addr
) == PLUS
6239 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
6241 offset
= INTVAL (XEXP (addr
, 1));
6242 addr
= XEXP (addr
, 0);
6245 if (GET_CODE (addr
) == LO_SUM
)
6247 const char *reloc16
, *reloclo
;
6248 rtx op1
= XEXP (addr
, 1);
6250 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
6252 op1
= XEXP (op1
, 0);
6253 switch (XINT (op1
, 1))
6257 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
6261 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
6264 output_operand_lossage ("unknown relocation unspec");
6268 output_addr_const (file
, XVECEXP (op1
, 0, 0));
6273 reloclo
= "gprellow";
6274 output_addr_const (file
, op1
);
6280 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6283 addr
= XEXP (addr
, 0);
6284 if (GET_CODE (addr
) == REG
)
6285 basereg
= REGNO (addr
);
6286 else if (GET_CODE (addr
) == SUBREG
6287 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6288 basereg
= subreg_regno (addr
);
6292 fprintf (file
, "($%d)\t\t!%s", basereg
,
6293 (basereg
== 29 ? reloc16
: reloclo
));
6297 if (GET_CODE (addr
) == REG
)
6298 basereg
= REGNO (addr
);
6299 else if (GET_CODE (addr
) == SUBREG
6300 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6301 basereg
= subreg_regno (addr
);
6302 else if (GET_CODE (addr
) == CONST_INT
)
6303 offset
= INTVAL (addr
);
6305 #if TARGET_ABI_OPEN_VMS
6306 else if (GET_CODE (addr
) == SYMBOL_REF
)
6308 fprintf (file
, "%s", XSTR (addr
, 0));
6311 else if (GET_CODE (addr
) == CONST
6312 && GET_CODE (XEXP (addr
, 0)) == PLUS
6313 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
6315 fprintf (file
, "%s+%d",
6316 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
6317 INTVAL (XEXP (XEXP (addr
, 0), 1)));
6325 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6326 fprintf (file
, "($%d)", basereg
);
6329 /* Emit RTL insns to initialize the variable parts of a trampoline at
6330 TRAMP. FNADDR is an RTX for the address of the function's pure
6331 code. CXT is an RTX for the static chain value for the function.
6333 The three offset parameters are for the individual template's
6334 layout. A JMPOFS < 0 indicates that the trampoline does not
6335 contain instructions at all.
6337 We assume here that a function will be called many more times than
6338 its address is taken (e.g., it might be passed to qsort), so we
6339 take the trouble to initialize the "hint" field in the JMP insn.
6340 Note that the hint field is PC (new) + 4 * bits 13:0. */
6343 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
6344 rtx tramp
, fnaddr
, cxt
;
6345 int fnofs
, cxtofs
, jmpofs
;
6347 rtx temp
, temp1
, addr
;
6348 /* VMS really uses DImode pointers in memory at this point. */
6349 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
6351 #ifdef POINTERS_EXTEND_UNSIGNED
6352 fnaddr
= convert_memory_address (mode
, fnaddr
);
6353 cxt
= convert_memory_address (mode
, cxt
);
6356 /* Store function address and CXT. */
6357 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
6358 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
6359 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
6360 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
6362 /* This has been disabled since the hint only has a 32k range, and in
6363 no existing OS is the stack within 32k of the text segment. */
6364 if (0 && jmpofs
>= 0)
6366 /* Compute hint value. */
6367 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
6368 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
6370 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
6371 build_int_2 (2, 0), NULL_RTX
, 1);
6372 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
6373 GEN_INT (0x3fff), 0);
6375 /* Merge in the hint. */
6376 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
6377 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
6378 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
6379 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
6381 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
6384 #ifdef TRANSFER_FROM_TRAMPOLINE
6385 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
6386 0, VOIDmode
, 1, tramp
, Pmode
);
6390 emit_insn (gen_imb ());
6393 /* Determine where to put an argument to a function.
6394 Value is zero to push the argument on the stack,
6395 or a hard register in which to store the argument.
6397 MODE is the argument's machine mode.
6398 TYPE is the data type of the argument (as a tree).
6399 This is null for libcalls where that information may
6401 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6402 the preceding args and about the function being called.
6403 NAMED is nonzero if this argument is a named parameter
6404 (otherwise it is an extra parameter matching an ellipsis).
6406 On Alpha the first 6 words of args are normally in registers
6407 and the rest are pushed. */
6410 function_arg (cum
, mode
, type
, named
)
6411 CUMULATIVE_ARGS cum
;
6412 enum machine_mode mode
;
6414 int named ATTRIBUTE_UNUSED
;
6419 /* Set up defaults for FP operands passed in FP registers, and
6420 integral operands passed in integer registers. */
6422 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6423 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6428 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6429 the three platforms, so we can't avoid conditional compilation. */
6430 #if TARGET_ABI_OPEN_VMS
6432 if (mode
== VOIDmode
)
6433 return alpha_arg_info_reg_val (cum
);
6435 num_args
= cum
.num_args
;
6436 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6440 #if TARGET_ABI_UNICOSMK
6444 /* If this is the last argument, generate the call info word (CIW). */
6445 /* ??? We don't include the caller's line number in the CIW because
6446 I don't know how to determine it if debug infos are turned off. */
6447 if (mode
== VOIDmode
)
6456 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6457 if (cum
.reg_args_type
[i
])
6458 lo
|= (1 << (7 - i
));
6460 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6463 lo
|= cum
.num_reg_words
;
6465 #if HOST_BITS_PER_WIDE_INT == 32
6466 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6468 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6469 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6472 ciw
= immed_double_const (lo
, hi
, DImode
);
6474 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6475 UNSPEC_UMK_LOAD_CIW
);
6478 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6479 num_args
= cum
.num_reg_words
;
6480 if (MUST_PASS_IN_STACK (mode
, type
)
6481 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6483 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6487 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6488 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6490 /* The argument fits in two registers. Note that we still need to
6491 reserve a register for empty structures. */
6495 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6498 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6499 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6500 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6510 /* VOID is passed as a special flag for "last argument". */
6511 if (type
== void_type_node
)
6513 else if (MUST_PASS_IN_STACK (mode
, type
))
6515 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6518 #endif /* TARGET_ABI_UNICOSMK */
6519 #endif /* TARGET_ABI_OPEN_VMS */
6521 return gen_rtx_REG (mode
, num_args
+ basereg
);
6525 alpha_build_va_list ()
6527 tree base
, ofs
, record
, type_decl
;
6529 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6530 return ptr_type_node
;
6532 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6533 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6534 TREE_CHAIN (record
) = type_decl
;
6535 TYPE_NAME (record
) = type_decl
;
6537 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6539 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6541 DECL_FIELD_CONTEXT (ofs
) = record
;
6543 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6545 DECL_FIELD_CONTEXT (base
) = record
;
6546 TREE_CHAIN (base
) = ofs
;
6548 TYPE_FIELDS (record
) = base
;
6549 layout_type (record
);
6555 alpha_va_start (valist
, nextarg
)
6557 rtx nextarg ATTRIBUTE_UNUSED
;
6559 HOST_WIDE_INT offset
;
6560 tree t
, offset_field
, base_field
;
6562 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6565 if (TARGET_ABI_UNICOSMK
)
6566 std_expand_builtin_va_start (valist
, nextarg
);
6568 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6569 up by 48, storing fp arg registers in the first 48 bytes, and the
6570 integer arg registers in the next 48 bytes. This is only done,
6571 however, if any integer registers need to be stored.
6573 If no integer registers need be stored, then we must subtract 48
6574 in order to account for the integer arg registers which are counted
6575 in argsize above, but which are not actually stored on the stack. */
6578 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6580 offset
= -6 * UNITS_PER_WORD
;
6582 if (TARGET_ABI_OPEN_VMS
)
6584 nextarg
= plus_constant (nextarg
, offset
);
6585 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6586 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6587 make_tree (ptr_type_node
, nextarg
));
6588 TREE_SIDE_EFFECTS (t
) = 1;
6590 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6594 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6595 offset_field
= TREE_CHAIN (base_field
);
6597 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6598 valist
, base_field
);
6599 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6600 valist
, offset_field
);
6602 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6603 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6604 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6605 TREE_SIDE_EFFECTS (t
) = 1;
6606 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6608 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6609 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6610 TREE_SIDE_EFFECTS (t
) = 1;
6611 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6616 alpha_va_arg (valist
, type
)
6620 tree t
, type_size
, rounded_size
;
6621 tree offset_field
, base_field
, addr_tree
, addend
;
6622 tree wide_type
, wide_ofs
;
6625 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6626 return std_expand_builtin_va_arg (valist
, type
);
6628 if (type
== error_mark_node
6629 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6630 || TREE_OVERFLOW (type_size
))
6631 rounded_size
= size_zero_node
;
6633 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6634 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6635 fold (build (PLUS_EXPR
, sizetype
,
6641 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6642 offset_field
= TREE_CHAIN (base_field
);
6644 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6645 valist
, base_field
);
6646 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6647 valist
, offset_field
);
6649 /* If the type could not be passed in registers, skip the block
6650 reserved for the registers. */
6651 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6653 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6654 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6655 offset_field
, build_int_2 (6*8, 0)));
6656 TREE_SIDE_EFFECTS (t
) = 1;
6657 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6660 wide_type
= make_signed_type (64);
6661 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6665 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6668 rounded_size
= size_int (UNITS_PER_WORD
);
6670 else if (FLOAT_TYPE_P (type
))
6672 tree fpaddend
, cond
;
6674 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6675 addend
, build_int_2 (-6*8, 0)));
6677 cond
= fold (build (LT_EXPR
, integer_type_node
,
6678 wide_ofs
, build_int_2 (6*8, 0)));
6680 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6684 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6685 base_field
, addend
);
6687 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6688 addr
= copy_to_reg (addr
);
6690 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6691 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6692 offset_field
, rounded_size
));
6693 TREE_SIDE_EFFECTS (t
) = 1;
6694 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6698 addr
= force_reg (Pmode
, addr
);
6699 addr
= gen_rtx_MEM (Pmode
, addr
);
6709 ALPHA_BUILTIN_CMPBGE
,
6710 ALPHA_BUILTIN_EXTBL
,
6711 ALPHA_BUILTIN_EXTWL
,
6712 ALPHA_BUILTIN_EXTLL
,
6713 ALPHA_BUILTIN_EXTQL
,
6714 ALPHA_BUILTIN_EXTWH
,
6715 ALPHA_BUILTIN_EXTLH
,
6716 ALPHA_BUILTIN_EXTQH
,
6717 ALPHA_BUILTIN_INSBL
,
6718 ALPHA_BUILTIN_INSWL
,
6719 ALPHA_BUILTIN_INSLL
,
6720 ALPHA_BUILTIN_INSQL
,
6721 ALPHA_BUILTIN_INSWH
,
6722 ALPHA_BUILTIN_INSLH
,
6723 ALPHA_BUILTIN_INSQH
,
6724 ALPHA_BUILTIN_MSKBL
,
6725 ALPHA_BUILTIN_MSKWL
,
6726 ALPHA_BUILTIN_MSKLL
,
6727 ALPHA_BUILTIN_MSKQL
,
6728 ALPHA_BUILTIN_MSKWH
,
6729 ALPHA_BUILTIN_MSKLH
,
6730 ALPHA_BUILTIN_MSKQH
,
6731 ALPHA_BUILTIN_UMULH
,
6733 ALPHA_BUILTIN_ZAPNOT
,
6734 ALPHA_BUILTIN_AMASK
,
6735 ALPHA_BUILTIN_IMPLVER
,
6737 ALPHA_BUILTIN_THREAD_POINTER
,
6738 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6741 ALPHA_BUILTIN_MINUB8
,
6742 ALPHA_BUILTIN_MINSB8
,
6743 ALPHA_BUILTIN_MINUW4
,
6744 ALPHA_BUILTIN_MINSW4
,
6745 ALPHA_BUILTIN_MAXUB8
,
6746 ALPHA_BUILTIN_MAXSB8
,
6747 ALPHA_BUILTIN_MAXUW4
,
6748 ALPHA_BUILTIN_MAXSW4
,
6752 ALPHA_BUILTIN_UNPKBL
,
6753 ALPHA_BUILTIN_UNPKBW
,
6758 ALPHA_BUILTIN_CTPOP
,
6763 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6764 CODE_FOR_builtin_cmpbge
,
6765 CODE_FOR_builtin_extbl
,
6766 CODE_FOR_builtin_extwl
,
6767 CODE_FOR_builtin_extll
,
6768 CODE_FOR_builtin_extql
,
6769 CODE_FOR_builtin_extwh
,
6770 CODE_FOR_builtin_extlh
,
6771 CODE_FOR_builtin_extqh
,
6772 CODE_FOR_builtin_insbl
,
6773 CODE_FOR_builtin_inswl
,
6774 CODE_FOR_builtin_insll
,
6775 CODE_FOR_builtin_insql
,
6776 CODE_FOR_builtin_inswh
,
6777 CODE_FOR_builtin_inslh
,
6778 CODE_FOR_builtin_insqh
,
6779 CODE_FOR_builtin_mskbl
,
6780 CODE_FOR_builtin_mskwl
,
6781 CODE_FOR_builtin_mskll
,
6782 CODE_FOR_builtin_mskql
,
6783 CODE_FOR_builtin_mskwh
,
6784 CODE_FOR_builtin_msklh
,
6785 CODE_FOR_builtin_mskqh
,
6786 CODE_FOR_umuldi3_highpart
,
6787 CODE_FOR_builtin_zap
,
6788 CODE_FOR_builtin_zapnot
,
6789 CODE_FOR_builtin_amask
,
6790 CODE_FOR_builtin_implver
,
6791 CODE_FOR_builtin_rpcc
,
6796 CODE_FOR_builtin_minub8
,
6797 CODE_FOR_builtin_minsb8
,
6798 CODE_FOR_builtin_minuw4
,
6799 CODE_FOR_builtin_minsw4
,
6800 CODE_FOR_builtin_maxub8
,
6801 CODE_FOR_builtin_maxsb8
,
6802 CODE_FOR_builtin_maxuw4
,
6803 CODE_FOR_builtin_maxsw4
,
6804 CODE_FOR_builtin_perr
,
6805 CODE_FOR_builtin_pklb
,
6806 CODE_FOR_builtin_pkwb
,
6807 CODE_FOR_builtin_unpkbl
,
6808 CODE_FOR_builtin_unpkbw
,
6811 CODE_FOR_builtin_cttz
,
6812 CODE_FOR_builtin_ctlz
,
6813 CODE_FOR_builtin_ctpop
6816 struct alpha_builtin_def
6819 enum alpha_builtin code
;
6820 unsigned int target_mask
;
6823 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6824 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6825 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6828 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6829 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6830 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6831 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6832 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6833 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6834 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6835 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6836 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6839 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6840 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6841 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6842 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6843 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6844 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6845 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6846 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6847 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6848 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6849 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6850 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6851 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6852 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6853 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6854 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6855 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6856 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6857 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6858 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6859 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6860 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6861 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6862 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6863 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6864 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6865 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6866 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6867 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6868 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6869 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6870 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6871 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6872 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6873 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6877 alpha_init_builtins ()
6879 const struct alpha_builtin_def
*p
;
6883 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6885 p
= zero_arg_builtins
;
6886 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6887 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6888 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6891 ftype
= build_function_type_list (long_integer_type_node
,
6892 long_integer_type_node
, NULL_TREE
);
6894 p
= one_arg_builtins
;
6895 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6896 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6897 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6900 ftype
= build_function_type_list (long_integer_type_node
,
6901 long_integer_type_node
,
6902 long_integer_type_node
, NULL_TREE
);
6904 p
= two_arg_builtins
;
6905 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6906 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6907 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6910 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6911 builtin_function ("__builtin_thread_pointer", ftype
,
6912 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6915 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6916 builtin_function ("__builtin_set_thread_pointer", ftype
,
6917 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6921 /* Expand an expression EXP that calls a built-in function,
6922 with result going to TARGET if that's convenient
6923 (and in mode MODE if that's convenient).
6924 SUBTARGET may be used as the target for computing one of EXP's operands.
6925 IGNORE is nonzero if the value is to be ignored. */
6928 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6931 rtx subtarget ATTRIBUTE_UNUSED
;
6932 enum machine_mode mode ATTRIBUTE_UNUSED
;
6933 int ignore ATTRIBUTE_UNUSED
;
6937 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6938 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6939 tree arglist
= TREE_OPERAND (exp
, 1);
6940 enum insn_code icode
;
6941 rtx op
[MAX_ARGS
], pat
;
6945 if (fcode
>= ALPHA_BUILTIN_max
)
6946 internal_error ("bad builtin fcode");
6947 icode
= code_for_builtin
[fcode
];
6949 internal_error ("bad builtin fcode");
6951 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6953 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6955 arglist
= TREE_CHAIN (arglist
), arity
++)
6957 const struct insn_operand_data
*insn_op
;
6959 tree arg
= TREE_VALUE (arglist
);
6960 if (arg
== error_mark_node
)
6962 if (arity
> MAX_ARGS
)
6965 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6967 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6969 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6970 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6975 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6977 || GET_MODE (target
) != tmode
6978 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6979 target
= gen_reg_rtx (tmode
);
6985 pat
= GEN_FCN (icode
) (target
);
6989 pat
= GEN_FCN (icode
) (target
, op
[0]);
6991 pat
= GEN_FCN (icode
) (op
[0]);
6994 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
7009 /* This page contains routines that are used to determine what the function
7010 prologue and epilogue code will do and write them out. */
7012 /* Compute the size of the save area in the stack. */
7014 /* These variables are used for communication between the following functions.
7015 They indicate various things about the current function being compiled
7016 that are used to tell what kind of prologue, epilogue and procedure
7017 descriptior to generate. */
7019 /* Nonzero if we need a stack procedure. */
7020 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
7021 static enum alpha_procedure_types alpha_procedure_type
;
7023 /* Register number (either FP or SP) that is used to unwind the frame. */
7024 static int vms_unwind_regno
;
7026 /* Register number used to save FP. We need not have one for RA since
7027 we don't modify it for register procedures. This is only defined
7028 for register frame procedures. */
7029 static int vms_save_fp_regno
;
7031 /* Register number used to reference objects off our PV. */
7032 static int vms_base_regno
;
7034 /* Compute register masks for saved registers. */
7037 alpha_sa_mask (imaskP
, fmaskP
)
7038 unsigned long *imaskP
;
7039 unsigned long *fmaskP
;
7041 unsigned long imask
= 0;
7042 unsigned long fmask
= 0;
7045 /* Irritatingly, there are two kinds of thunks -- those created with
7046 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
7047 through the regular part of the compiler. In the
7048 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
7049 info, but assemble_start_function wants to output .frame and
7050 .mask directives. */
7051 if (current_function_is_thunk
&& !no_new_pseudos
)
7058 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7059 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
7061 /* One for every register we have to save. */
7062 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7063 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
7064 && regs_ever_live
[i
] && i
!= REG_RA
7065 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
7070 fmask
|= (1L << (i
- 32));
7073 /* We need to restore these for the handler. */
7074 if (current_function_calls_eh_return
)
7077 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
7078 if (regno
== INVALID_REGNUM
)
7080 imask
|= 1L << regno
;
7083 /* If any register spilled, then spill the return address also. */
7084 /* ??? This is required by the Digital stack unwind specification
7085 and isn't needed if we're doing Dwarf2 unwinding. */
7086 if (imask
|| fmask
|| alpha_ra_ever_killed ())
7087 imask
|= (1L << REG_RA
);
7096 unsigned long mask
[2];
7100 alpha_sa_mask (&mask
[0], &mask
[1]);
7102 if (TARGET_ABI_UNICOSMK
)
7104 if (mask
[0] || mask
[1])
7109 for (j
= 0; j
< 2; ++j
)
7110 for (i
= 0; i
< 32; ++i
)
7111 if ((mask
[j
] >> i
) & 1)
7115 if (TARGET_ABI_UNICOSMK
)
7117 /* We might not need to generate a frame if we don't make any calls
7118 (including calls to __T3E_MISMATCH if this is a vararg function),
7119 don't have any local variables which require stack slots, don't
7120 use alloca and have not determined that we need a frame for other
7123 alpha_procedure_type
7124 = (sa_size
|| get_frame_size() != 0
7125 || current_function_outgoing_args_size
7126 || current_function_stdarg
|| current_function_calls_alloca
7127 || frame_pointer_needed
)
7128 ? PT_STACK
: PT_REGISTER
;
7130 /* Always reserve space for saving callee-saved registers if we
7131 need a frame as required by the calling convention. */
7132 if (alpha_procedure_type
== PT_STACK
)
7135 else if (TARGET_ABI_OPEN_VMS
)
7137 /* Start by assuming we can use a register procedure if we don't
7138 make any calls (REG_RA not used) or need to save any
7139 registers and a stack procedure if we do. */
7140 if ((mask
[0] >> REG_RA
) & 1)
7141 alpha_procedure_type
= PT_STACK
;
7142 else if (get_frame_size() != 0)
7143 alpha_procedure_type
= PT_REGISTER
;
7145 alpha_procedure_type
= PT_NULL
;
7147 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7148 made the final decision on stack procedure vs register procedure. */
7149 if (alpha_procedure_type
== PT_STACK
)
7152 /* Decide whether to refer to objects off our PV via FP or PV.
7153 If we need FP for something else or if we receive a nonlocal
7154 goto (which expects PV to contain the value), we must use PV.
7155 Otherwise, start by assuming we can use FP. */
7158 = (frame_pointer_needed
7159 || current_function_has_nonlocal_label
7160 || alpha_procedure_type
== PT_STACK
7161 || current_function_outgoing_args_size
)
7162 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7164 /* If we want to copy PV into FP, we need to find some register
7165 in which to save FP. */
7167 vms_save_fp_regno
= -1;
7168 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7169 for (i
= 0; i
< 32; i
++)
7170 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
7171 vms_save_fp_regno
= i
;
7173 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7174 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7175 else if (alpha_procedure_type
== PT_NULL
)
7176 vms_base_regno
= REG_PV
;
7178 /* Stack unwinding should be done via FP unless we use it for PV. */
7179 vms_unwind_regno
= (vms_base_regno
== REG_PV
7180 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7182 /* If this is a stack procedure, allow space for saving FP and RA. */
7183 if (alpha_procedure_type
== PT_STACK
)
7188 /* Our size must be even (multiple of 16 bytes). */
7197 alpha_pv_save_size ()
7200 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7207 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7210 #if TARGET_ABI_OPEN_VMS
7212 const struct attribute_spec vms_attribute_table
[] =
7214 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7215 { "overlaid", 0, 0, true, false, false, NULL
},
7216 { "global", 0, 0, true, false, false, NULL
},
7217 { "initialize", 0, 0, true, false, false, NULL
},
7218 { NULL
, 0, 0, false, false, false, NULL
}
7224 find_lo_sum_using_gp (px
, data
)
7226 void *data ATTRIBUTE_UNUSED
;
7228 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7232 alpha_find_lo_sum_using_gp (insn
)
7235 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7239 alpha_does_function_need_gp ()
7243 /* The GP being variable is an OSF abi thing. */
7244 if (! TARGET_ABI_OSF
)
7247 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7250 if (current_function_is_thunk
)
7253 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7254 Even if we are a static function, we still need to do this in case
7255 our address is taken and passed to something like qsort. */
7257 push_topmost_sequence ();
7258 insn
= get_insns ();
7259 pop_topmost_sequence ();
7261 for (; insn
; insn
= NEXT_INSN (insn
))
7263 && GET_CODE (PATTERN (insn
)) != USE
7264 && GET_CODE (PATTERN (insn
)) != CLOBBER
7265 && get_attr_usegp (insn
))
7271 /* Write a version stamp. Don't write anything if we are running as a
7272 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
7279 alpha_write_verstamp (file
)
7280 FILE *file ATTRIBUTE_UNUSED
;
7283 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
7287 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7291 set_frame_related_p ()
7293 rtx seq
= get_insns ();
7304 while (insn
!= NULL_RTX
)
7306 RTX_FRAME_RELATED_P (insn
) = 1;
7307 insn
= NEXT_INSN (insn
);
7309 seq
= emit_insn (seq
);
7313 seq
= emit_insn (seq
);
7314 RTX_FRAME_RELATED_P (seq
) = 1;
7319 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7321 /* Write function prologue. */
7323 /* On vms we have two kinds of functions:
7325 - stack frame (PROC_STACK)
7326 these are 'normal' functions with local vars and which are
7327 calling other functions
7328 - register frame (PROC_REGISTER)
7329 keeps all data in registers, needs no stack
7331 We must pass this to the assembler so it can generate the
7332 proper pdsc (procedure descriptor)
7333 This is done with the '.pdesc' command.
7335 On not-vms, we don't really differentiate between the two, as we can
7336 simply allocate stack without saving registers. */
7339 alpha_expand_prologue ()
7341 /* Registers to save. */
7342 unsigned long imask
= 0;
7343 unsigned long fmask
= 0;
7344 /* Stack space needed for pushing registers clobbered by us. */
7345 HOST_WIDE_INT sa_size
;
7346 /* Complete stack size needed. */
7347 HOST_WIDE_INT frame_size
;
7348 /* Offset from base reg to register save area. */
7349 HOST_WIDE_INT reg_offset
;
7353 sa_size
= alpha_sa_size ();
7355 frame_size
= get_frame_size ();
7356 if (TARGET_ABI_OPEN_VMS
)
7357 frame_size
= ALPHA_ROUND (sa_size
7358 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7360 + current_function_pretend_args_size
);
7361 else if (TARGET_ABI_UNICOSMK
)
7362 /* We have to allocate space for the DSIB if we generate a frame. */
7363 frame_size
= ALPHA_ROUND (sa_size
7364 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7365 + ALPHA_ROUND (frame_size
7366 + current_function_outgoing_args_size
);
7368 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7370 + ALPHA_ROUND (frame_size
7371 + current_function_pretend_args_size
));
7373 if (TARGET_ABI_OPEN_VMS
)
7376 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7378 alpha_sa_mask (&imask
, &fmask
);
7380 /* Emit an insn to reload GP, if needed. */
7383 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7384 if (alpha_function_needs_gp
)
7385 emit_insn (gen_prologue_ldgp ());
7388 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7389 the call to mcount ourselves, rather than having the linker do it
7390 magically in response to -pg. Since _mcount has special linkage,
7391 don't represent the call as a call. */
7392 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7393 emit_insn (gen_prologue_mcount ());
7395 if (TARGET_ABI_UNICOSMK
)
7396 unicosmk_gen_dsib (&imask
);
7398 /* Adjust the stack by the frame size. If the frame size is > 4096
7399 bytes, we need to be sure we probe somewhere in the first and last
7400 4096 bytes (we can probably get away without the latter test) and
7401 every 8192 bytes in between. If the frame size is > 32768, we
7402 do this in a loop. Otherwise, we generate the explicit probe
7405 Note that we are only allowed to adjust sp once in the prologue. */
7407 if (frame_size
<= 32768)
7409 if (frame_size
> 4096)
7414 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7417 while ((probed
+= 8192) < frame_size
);
7419 /* We only have to do this probe if we aren't saving registers. */
7420 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7421 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7424 if (frame_size
!= 0)
7425 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7426 GEN_INT (TARGET_ABI_UNICOSMK
7432 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7433 number of 8192 byte blocks to probe. We then probe each block
7434 in the loop and then set SP to the proper location. If the
7435 amount remaining is > 4096, we have to do one more probe if we
7436 are not saving any registers. */
7438 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7439 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7440 rtx ptr
= gen_rtx_REG (DImode
, 22);
7441 rtx count
= gen_rtx_REG (DImode
, 23);
7444 emit_move_insn (count
, GEN_INT (blocks
));
7445 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7446 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7448 /* Because of the difficulty in emitting a new basic block this
7449 late in the compilation, generate the loop as a single insn. */
7450 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7452 if (leftover
> 4096 && sa_size
== 0)
7454 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7455 MEM_VOLATILE_P (last
) = 1;
7456 emit_move_insn (last
, const0_rtx
);
7459 if (TARGET_ABI_WINDOWS_NT
)
7461 /* For NT stack unwind (done by 'reverse execution'), it's
7462 not OK to take the result of a loop, even though the value
7463 is already in ptr, so we reload it via a single operation
7464 and subtract it to sp.
7466 Yes, that's correct -- we have to reload the whole constant
7467 into a temporary via ldah+lda then subtract from sp. To
7468 ensure we get ldah+lda, we use a special pattern. */
7470 HOST_WIDE_INT lo
, hi
;
7471 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7472 hi
= frame_size
- lo
;
7474 emit_move_insn (ptr
, GEN_INT (hi
));
7475 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7476 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7481 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7482 GEN_INT (-leftover
)));
7485 /* This alternative is special, because the DWARF code cannot
7486 possibly intuit through the loop above. So we invent this
7487 note it looks at instead. */
7488 RTX_FRAME_RELATED_P (seq
) = 1;
7490 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7491 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7492 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7493 GEN_INT (TARGET_ABI_UNICOSMK
7499 if (!TARGET_ABI_UNICOSMK
)
7501 /* Cope with very large offsets to the register save area. */
7502 sa_reg
= stack_pointer_rtx
;
7503 if (reg_offset
+ sa_size
> 0x8000)
7505 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7508 if (low
+ sa_size
<= 0x8000)
7509 bias
= reg_offset
- low
, reg_offset
= low
;
7511 bias
= reg_offset
, reg_offset
= 0;
7513 sa_reg
= gen_rtx_REG (DImode
, 24);
7514 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7518 /* Save regs in stack order. Beginning with VMS PV. */
7519 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7521 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7522 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7523 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7526 /* Save register RA next. */
7527 if (imask
& (1L << REG_RA
))
7529 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7530 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7531 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7532 imask
&= ~(1L << REG_RA
);
7536 /* Now save any other registers required to be saved. */
7537 for (i
= 0; i
< 32; i
++)
7538 if (imask
& (1L << i
))
7540 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7541 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7542 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7546 for (i
= 0; i
< 32; i
++)
7547 if (fmask
& (1L << i
))
7549 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7550 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7551 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7555 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7557 /* The standard frame on the T3E includes space for saving registers.
7558 We just have to use it. We don't have to save the return address and
7559 the old frame pointer here - they are saved in the DSIB. */
7562 for (i
= 9; i
< 15; i
++)
7563 if (imask
& (1L << i
))
7565 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7567 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7568 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7571 for (i
= 2; i
< 10; i
++)
7572 if (fmask
& (1L << i
))
7574 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7576 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7577 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7582 if (TARGET_ABI_OPEN_VMS
)
7584 if (alpha_procedure_type
== PT_REGISTER
)
7585 /* Register frame procedures save the fp.
7586 ?? Ought to have a dwarf2 save for this. */
7587 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7588 hard_frame_pointer_rtx
);
7590 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7591 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7592 gen_rtx_REG (DImode
, REG_PV
)));
7594 if (alpha_procedure_type
!= PT_NULL
7595 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7596 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7598 /* If we have to allocate space for outgoing args, do it now. */
7599 if (current_function_outgoing_args_size
!= 0)
7602 plus_constant (hard_frame_pointer_rtx
,
7604 (current_function_outgoing_args_size
)))));
7606 else if (!TARGET_ABI_UNICOSMK
)
7608 /* If we need a frame pointer, set it from the stack pointer. */
7609 if (frame_pointer_needed
)
7611 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7612 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7614 /* This must always be the last instruction in the
7615 prologue, thus we emit a special move + clobber. */
7616 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7617 stack_pointer_rtx
, sa_reg
)));
7621 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7622 the prologue, for exception handling reasons, we cannot do this for
7623 any insn that might fault. We could prevent this for mems with a
7624 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7625 have to prevent all such scheduling with a blockage.
7627 Linux, on the other hand, never bothered to implement OSF/1's
7628 exception handling, and so doesn't care about such things. Anyone
7629 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7631 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7632 emit_insn (gen_blockage ());
7635 /* Output the textual info surrounding the prologue. */
7638 alpha_start_function (file
, fnname
, decl
)
7641 tree decl ATTRIBUTE_UNUSED
;
7643 unsigned long imask
= 0;
7644 unsigned long fmask
= 0;
7645 /* Stack space needed for pushing registers clobbered by us. */
7646 HOST_WIDE_INT sa_size
;
7647 /* Complete stack size needed. */
7648 HOST_WIDE_INT frame_size
;
7649 /* Offset from base reg to register save area. */
7650 HOST_WIDE_INT reg_offset
;
7651 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7654 /* Don't emit an extern directive for functions defined in the same file. */
7655 if (TARGET_ABI_UNICOSMK
)
7658 name_tree
= get_identifier (fnname
);
7659 TREE_ASM_WRITTEN (name_tree
) = 1;
7662 alpha_fnname
= fnname
;
7663 sa_size
= alpha_sa_size ();
7665 frame_size
= get_frame_size ();
7666 if (TARGET_ABI_OPEN_VMS
)
7667 frame_size
= ALPHA_ROUND (sa_size
7668 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7670 + current_function_pretend_args_size
);
7671 else if (TARGET_ABI_UNICOSMK
)
7672 frame_size
= ALPHA_ROUND (sa_size
7673 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7674 + ALPHA_ROUND (frame_size
7675 + current_function_outgoing_args_size
);
7677 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7679 + ALPHA_ROUND (frame_size
7680 + current_function_pretend_args_size
));
7682 if (TARGET_ABI_OPEN_VMS
)
7685 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7687 alpha_sa_mask (&imask
, &fmask
);
7689 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7690 We have to do that before the .ent directive as we cannot switch
7691 files within procedures with native ecoff because line numbers are
7692 linked to procedure descriptors.
7693 Outputting the lineno helps debugging of one line functions as they
7694 would otherwise get no line number at all. Please note that we would
7695 like to put out last_linenum from final.c, but it is not accessible. */
7697 if (write_symbols
== SDB_DEBUG
)
7699 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7700 ASM_OUTPUT_SOURCE_FILENAME (file
,
7701 DECL_SOURCE_FILE (current_function_decl
));
7703 #ifdef ASM_OUTPUT_SOURCE_LINE
7704 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7705 ASM_OUTPUT_SOURCE_LINE (file
,
7706 DECL_SOURCE_LINE (current_function_decl
));
7710 /* Issue function start and label. */
7711 if (TARGET_ABI_OPEN_VMS
7712 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7714 fputs ("\t.ent ", file
);
7715 assemble_name (file
, fnname
);
7718 /* If the function needs GP, we'll write the "..ng" label there.
7719 Otherwise, do it here. */
7721 && ! alpha_function_needs_gp
7722 && ! current_function_is_thunk
)
7725 assemble_name (file
, fnname
);
7726 fputs ("..ng:\n", file
);
7730 strcpy (entry_label
, fnname
);
7731 if (TARGET_ABI_OPEN_VMS
)
7732 strcat (entry_label
, "..en");
7734 /* For public functions, the label must be globalized by appending an
7735 additional colon. */
7736 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7737 strcat (entry_label
, ":");
7739 ASM_OUTPUT_LABEL (file
, entry_label
);
7740 inside_function
= TRUE
;
7742 if (TARGET_ABI_OPEN_VMS
)
7743 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7745 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7746 && !flag_inhibit_size_directive
)
7748 /* Set flags in procedure descriptor to request IEEE-conformant
7749 math-library routines. The value we set it to is PDSC_EXC_IEEE
7750 (/usr/include/pdsc.h). */
7751 fputs ("\t.eflag 48\n", file
);
7754 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7755 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7756 alpha_arg_offset
= -frame_size
+ 48;
7758 /* Describe our frame. If the frame size is larger than an integer,
7759 print it as zero to avoid an assembler error. We won't be
7760 properly describing such a frame, but that's the best we can do. */
7761 if (TARGET_ABI_UNICOSMK
)
7763 else if (TARGET_ABI_OPEN_VMS
)
7765 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7766 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7767 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
7768 fputs (",$26,", file
);
7769 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7772 else if (!flag_inhibit_size_directive
)
7774 fprintf (file
, "\t.frame $%d,",
7775 (frame_pointer_needed
7776 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7777 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7778 frame_size
>= (1l << 31) ? 0 : frame_size
);
7779 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7782 /* Describe which registers were spilled. */
7783 if (TARGET_ABI_UNICOSMK
)
7785 else if (TARGET_ABI_OPEN_VMS
)
7788 /* ??? Does VMS care if mask contains ra? The old code didn't
7789 set it, so I don't here. */
7790 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
7792 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7793 if (alpha_procedure_type
== PT_REGISTER
)
7794 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7796 else if (!flag_inhibit_size_directive
)
7800 fprintf (file
, "\t.mask 0x%lx,", imask
);
7801 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7802 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7805 for (i
= 0; i
< 32; ++i
)
7806 if (imask
& (1L << i
))
7812 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7813 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7814 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7819 #if TARGET_ABI_OPEN_VMS
7820 /* Ifdef'ed cause link_section are only available then. */
7821 readonly_data_section ();
7822 fprintf (file
, "\t.align 3\n");
7823 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7824 fputs ("\t.ascii \"", file
);
7825 assemble_name (file
, fnname
);
7826 fputs ("\\0\"\n", file
);
7827 alpha_need_linkage (fnname
, 1);
7832 /* Emit the .prologue note at the scheduled end of the prologue. */
7835 alpha_output_function_end_prologue (file
)
7838 if (TARGET_ABI_UNICOSMK
)
7840 else if (TARGET_ABI_OPEN_VMS
)
7841 fputs ("\t.prologue\n", file
);
7842 else if (TARGET_ABI_WINDOWS_NT
)
7843 fputs ("\t.prologue 0\n", file
);
7844 else if (!flag_inhibit_size_directive
)
7845 fprintf (file
, "\t.prologue %d\n",
7846 alpha_function_needs_gp
|| current_function_is_thunk
);
7849 /* Write function epilogue. */
7851 /* ??? At some point we will want to support full unwind, and so will
7852 need to mark the epilogue as well. At the moment, we just confuse
7855 #define FRP(exp) exp
7858 alpha_expand_epilogue ()
7860 /* Registers to save. */
7861 unsigned long imask
= 0;
7862 unsigned long fmask
= 0;
7863 /* Stack space needed for pushing registers clobbered by us. */
7864 HOST_WIDE_INT sa_size
;
7865 /* Complete stack size needed. */
7866 HOST_WIDE_INT frame_size
;
7867 /* Offset from base reg to register save area. */
7868 HOST_WIDE_INT reg_offset
;
7869 int fp_is_frame_pointer
, fp_offset
;
7870 rtx sa_reg
, sa_reg_exp
= NULL
;
7871 rtx sp_adj1
, sp_adj2
, mem
;
7875 sa_size
= alpha_sa_size ();
7877 frame_size
= get_frame_size ();
7878 if (TARGET_ABI_OPEN_VMS
)
7879 frame_size
= ALPHA_ROUND (sa_size
7880 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7882 + current_function_pretend_args_size
);
7883 else if (TARGET_ABI_UNICOSMK
)
7884 frame_size
= ALPHA_ROUND (sa_size
7885 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7886 + ALPHA_ROUND (frame_size
7887 + current_function_outgoing_args_size
);
7889 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7891 + ALPHA_ROUND (frame_size
7892 + current_function_pretend_args_size
));
7894 if (TARGET_ABI_OPEN_VMS
)
7896 if (alpha_procedure_type
== PT_STACK
)
7902 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7904 alpha_sa_mask (&imask
, &fmask
);
7907 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7908 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7910 sa_reg
= stack_pointer_rtx
;
7912 if (current_function_calls_eh_return
)
7913 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7917 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7919 /* If we have a frame pointer, restore SP from it. */
7920 if ((TARGET_ABI_OPEN_VMS
7921 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7922 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7923 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7925 /* Cope with very large offsets to the register save area. */
7926 if (reg_offset
+ sa_size
> 0x8000)
7928 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7931 if (low
+ sa_size
<= 0x8000)
7932 bias
= reg_offset
- low
, reg_offset
= low
;
7934 bias
= reg_offset
, reg_offset
= 0;
7936 sa_reg
= gen_rtx_REG (DImode
, 22);
7937 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7939 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7942 /* Restore registers in order, excepting a true frame pointer. */
7944 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7946 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7947 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7950 imask
&= ~(1L << REG_RA
);
7952 for (i
= 0; i
< 32; ++i
)
7953 if (imask
& (1L << i
))
7955 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7956 fp_offset
= reg_offset
;
7959 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7960 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7961 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7966 for (i
= 0; i
< 32; ++i
)
7967 if (fmask
& (1L << i
))
7969 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7970 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7971 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7975 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7977 /* Restore callee-saved general-purpose registers. */
7981 for (i
= 9; i
< 15; i
++)
7982 if (imask
& (1L << i
))
7984 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7986 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7987 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7991 for (i
= 2; i
< 10; i
++)
7992 if (fmask
& (1L << i
))
7994 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7996 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7997 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
8001 /* Restore the return address from the DSIB. */
8003 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
8004 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8005 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
8008 if (frame_size
|| eh_ofs
)
8010 sp_adj1
= stack_pointer_rtx
;
8014 sp_adj1
= gen_rtx_REG (DImode
, 23);
8015 emit_move_insn (sp_adj1
,
8016 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
8019 /* If the stack size is large, begin computation into a temporary
8020 register so as not to interfere with a potential fp restore,
8021 which must be consecutive with an SP restore. */
8022 if (frame_size
< 32768
8023 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
8024 sp_adj2
= GEN_INT (frame_size
);
8025 else if (TARGET_ABI_UNICOSMK
)
8027 sp_adj1
= gen_rtx_REG (DImode
, 23);
8028 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
8029 sp_adj2
= const0_rtx
;
8031 else if (frame_size
< 0x40007fffL
)
8033 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
8035 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
8036 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
8040 sp_adj1
= gen_rtx_REG (DImode
, 23);
8041 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
8043 sp_adj2
= GEN_INT (low
);
8047 rtx tmp
= gen_rtx_REG (DImode
, 23);
8048 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
8051 /* We can't drop new things to memory this late, afaik,
8052 so build it up by pieces. */
8053 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
8054 -(frame_size
< 0)));
8060 /* From now on, things must be in order. So emit blockages. */
8062 /* Restore the frame pointer. */
8063 if (TARGET_ABI_UNICOSMK
)
8065 emit_insn (gen_blockage ());
8066 mem
= gen_rtx_MEM (DImode
,
8067 plus_constant (hard_frame_pointer_rtx
, -16));
8068 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8069 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8071 else if (fp_is_frame_pointer
)
8073 emit_insn (gen_blockage ());
8074 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
8075 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8076 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8078 else if (TARGET_ABI_OPEN_VMS
)
8080 emit_insn (gen_blockage ());
8081 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8082 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8085 /* Restore the stack pointer. */
8086 emit_insn (gen_blockage ());
8087 if (sp_adj2
== const0_rtx
)
8088 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
8090 FRP (emit_move_insn (stack_pointer_rtx
,
8091 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
8095 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8097 emit_insn (gen_blockage ());
8098 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8099 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8101 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8103 /* Decrement the frame pointer if the function does not have a
8106 emit_insn (gen_blockage ());
8107 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8108 hard_frame_pointer_rtx
, GEN_INT (-1))));
8113 /* Output the rest of the textual info surrounding the epilogue. */
8116 alpha_end_function (file
, fnname
, decl
)
8121 /* End the function. */
8122 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8124 fputs ("\t.end ", file
);
8125 assemble_name (file
, fnname
);
8128 inside_function
= FALSE
;
8130 #if TARGET_ABI_OPEN_VMS
8131 alpha_write_linkage (file
, fnname
, decl
);
8134 /* Show that we know this function if it is called again.
8135 This is only meaningful for symbols that bind locally. */
8136 if ((*targetm
.binds_local_p
) (decl
))
8138 rtx symbol
= XEXP (DECL_RTL (decl
), 0);
8140 /* Mark whether the decl is "near". See the commentary in
8141 alpha_encode_section_info wrt the .text section. */
8142 if (decl_in_text_section (decl
))
8145 /* Mark whether the decl shares a GP with other functions
8146 in this unit of translation. This is trivially true of
8148 SYMBOL_REF_FLAG (symbol
) = 1;
8151 /* Output jump tables and the static subroutine information block. */
8152 if (TARGET_ABI_UNICOSMK
)
8154 unicosmk_output_ssib (file
, fnname
);
8155 unicosmk_output_deferred_case_vectors (file
);
8160 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8162 In order to avoid the hordes of differences between generated code
8163 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8164 lots of code loading up large constants, generate rtl and emit it
8165 instead of going straight to text.
8167 Not sure why this idea hasn't been explored before... */
8170 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
8172 tree thunk_fndecl ATTRIBUTE_UNUSED
;
8173 HOST_WIDE_INT delta
;
8174 HOST_WIDE_INT vcall_offset
;
8177 HOST_WIDE_INT hi
, lo
;
8178 rtx
this, insn
, funexp
;
8180 /* We always require a valid GP. */
8181 emit_insn (gen_prologue_ldgp ());
8182 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
8184 /* Find the "this" pointer. If the function returns a structure,
8185 the structure return pointer is in $16. */
8186 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
8187 this = gen_rtx_REG (Pmode
, 17);
8189 this = gen_rtx_REG (Pmode
, 16);
8191 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8192 entire constant for the add. */
8193 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8194 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8195 if (hi
+ lo
== delta
)
8198 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
8200 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
8204 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8205 delta
, -(delta
< 0));
8206 emit_insn (gen_adddi3 (this, this, tmp
));
8209 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8214 tmp
= gen_rtx_REG (Pmode
, 0);
8215 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8217 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8218 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8219 if (hi
+ lo
== vcall_offset
)
8222 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8226 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8227 vcall_offset
, -(vcall_offset
< 0));
8228 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8232 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8235 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8237 emit_insn (gen_adddi3 (this, this, tmp
));
8240 /* Generate a tail call to the target function. */
8241 if (! TREE_USED (function
))
8243 assemble_external (function
);
8244 TREE_USED (function
) = 1;
8246 funexp
= XEXP (DECL_RTL (function
), 0);
8247 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8248 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8249 SIBLING_CALL_P (insn
) = 1;
8251 /* Run just enough of rest_of_compilation to get the insns emitted.
8252 There's not really enough bulk here to make other passes such as
8253 instruction scheduling worth while. Note that use_thunk calls
8254 assemble_start_function and assemble_end_function. */
8255 insn
= get_insns ();
8256 shorten_branches (insn
);
8257 final_start_function (insn
, file
, 1);
8258 final (insn
, file
, 1, 0);
8259 final_end_function ();
8261 #endif /* TARGET_ABI_OSF */
8263 /* Debugging support. */
8267 /* Count the number of sdb related labels are generated (to find block
8268 start and end boundaries). */
8270 int sdb_label_count
= 0;
8272 /* Next label # for each statement. */
8274 static int sym_lineno
= 0;
8276 /* Count the number of .file directives, so that .loc is up to date. */
8278 static int num_source_filenames
= 0;
8280 /* Name of the file containing the current function. */
8282 static const char *current_function_file
= "";
8284 /* Offsets to alpha virtual arg/local debugging pointers. */
8286 long alpha_arg_offset
;
8287 long alpha_auto_offset
;
8289 /* Emit a new filename to a stream. */
8292 alpha_output_filename (stream
, name
)
8296 static int first_time
= TRUE
;
8297 char ltext_label_name
[100];
8302 ++num_source_filenames
;
8303 current_function_file
= name
;
8304 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8305 output_quoted_string (stream
, name
);
8306 fprintf (stream
, "\n");
8307 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8308 fprintf (stream
, "\t#@stabs\n");
8311 else if (write_symbols
== DBX_DEBUG
)
8313 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
8314 fprintf (stream
, "%s", ASM_STABS_OP
);
8315 output_quoted_string (stream
, name
);
8316 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8319 else if (name
!= current_function_file
8320 && strcmp (name
, current_function_file
) != 0)
8322 if (inside_function
&& ! TARGET_GAS
)
8323 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8326 ++num_source_filenames
;
8327 current_function_file
= name
;
8328 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8331 output_quoted_string (stream
, name
);
8332 fprintf (stream
, "\n");
8336 /* Emit a linenumber to a stream. */
8339 alpha_output_lineno (stream
, line
)
8343 if (write_symbols
== DBX_DEBUG
)
8345 /* mips-tfile doesn't understand .stabd directives. */
8347 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8348 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8351 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8354 /* Structure to show the current status of registers and memory. */
8356 struct shadow_summary
8359 unsigned int i
: 31; /* Mask of int regs */
8360 unsigned int fp
: 31; /* Mask of fp regs */
8361 unsigned int mem
: 1; /* mem == imem | fpmem */
8365 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
8366 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
8368 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8369 to the summary structure. SET is nonzero if the insn is setting the
8370 object, otherwise zero. */
8373 summarize_insn (x
, sum
, set
)
8375 struct shadow_summary
*sum
;
8378 const char *format_ptr
;
8384 switch (GET_CODE (x
))
8386 /* ??? Note that this case would be incorrect if the Alpha had a
8387 ZERO_EXTRACT in SET_DEST. */
8389 summarize_insn (SET_SRC (x
), sum
, 0);
8390 summarize_insn (SET_DEST (x
), sum
, 1);
8394 summarize_insn (XEXP (x
, 0), sum
, 1);
8398 summarize_insn (XEXP (x
, 0), sum
, 0);
8402 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8403 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8407 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8408 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8412 summarize_insn (SUBREG_REG (x
), sum
, 0);
8417 int regno
= REGNO (x
);
8418 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8420 if (regno
== 31 || regno
== 63)
8426 sum
->defd
.i
|= mask
;
8428 sum
->defd
.fp
|= mask
;
8433 sum
->used
.i
|= mask
;
8435 sum
->used
.fp
|= mask
;
8446 /* Find the regs used in memory address computation: */
8447 summarize_insn (XEXP (x
, 0), sum
, 0);
8450 case CONST_INT
: case CONST_DOUBLE
:
8451 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8452 case SCRATCH
: case ASM_INPUT
:
8455 /* Handle common unary and binary ops for efficiency. */
8456 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8457 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8458 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8459 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8460 case NE
: case EQ
: case GE
: case GT
: case LE
:
8461 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8462 summarize_insn (XEXP (x
, 0), sum
, 0);
8463 summarize_insn (XEXP (x
, 1), sum
, 0);
8466 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8467 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8468 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8469 case SQRT
: case FFS
:
8470 summarize_insn (XEXP (x
, 0), sum
, 0);
8474 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8475 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8476 switch (format_ptr
[i
])
8479 summarize_insn (XEXP (x
, i
), sum
, 0);
8483 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8484 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8496 /* Ensure a sufficient number of `trapb' insns are in the code when
8497 the user requests code with a trap precision of functions or
8500 In naive mode, when the user requests a trap-precision of
8501 "instruction", a trapb is needed after every instruction that may
8502 generate a trap. This ensures that the code is resumption safe but
8505 When optimizations are turned on, we delay issuing a trapb as long
8506 as possible. In this context, a trap shadow is the sequence of
8507 instructions that starts with a (potentially) trap generating
8508 instruction and extends to the next trapb or call_pal instruction
8509 (but GCC never generates call_pal by itself). We can delay (and
8510 therefore sometimes omit) a trapb subject to the following
8513 (a) On entry to the trap shadow, if any Alpha register or memory
8514 location contains a value that is used as an operand value by some
8515 instruction in the trap shadow (live on entry), then no instruction
8516 in the trap shadow may modify the register or memory location.
8518 (b) Within the trap shadow, the computation of the base register
8519 for a memory load or store instruction may not involve using the
8520 result of an instruction that might generate an UNPREDICTABLE
8523 (c) Within the trap shadow, no register may be used more than once
8524 as a destination register. (This is to make life easier for the
8527 (d) The trap shadow may not include any branch instructions. */
8530 alpha_handle_trap_shadows (insns
)
8533 struct shadow_summary shadow
;
8534 int trap_pending
, exception_nesting
;
8538 exception_nesting
= 0;
8541 shadow
.used
.mem
= 0;
8542 shadow
.defd
= shadow
.used
;
8544 for (i
= insns
; i
; i
= NEXT_INSN (i
))
8546 if (GET_CODE (i
) == NOTE
)
8548 switch (NOTE_LINE_NUMBER (i
))
8550 case NOTE_INSN_EH_REGION_BEG
:
8551 exception_nesting
++;
8556 case NOTE_INSN_EH_REGION_END
:
8557 exception_nesting
--;
8562 case NOTE_INSN_EPILOGUE_BEG
:
8563 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8568 else if (trap_pending
)
8570 if (alpha_tp
== ALPHA_TP_FUNC
)
8572 if (GET_CODE (i
) == JUMP_INSN
8573 && GET_CODE (PATTERN (i
)) == RETURN
)
8576 else if (alpha_tp
== ALPHA_TP_INSN
)
8580 struct shadow_summary sum
;
8585 sum
.defd
= sum
.used
;
8587 switch (GET_CODE (i
))
8590 /* Annoyingly, get_attr_trap will abort on these. */
8591 if (GET_CODE (PATTERN (i
)) == USE
8592 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8595 summarize_insn (PATTERN (i
), &sum
, 0);
8597 if ((sum
.defd
.i
& shadow
.defd
.i
)
8598 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8600 /* (c) would be violated */
8604 /* Combine shadow with summary of current insn: */
8605 shadow
.used
.i
|= sum
.used
.i
;
8606 shadow
.used
.fp
|= sum
.used
.fp
;
8607 shadow
.used
.mem
|= sum
.used
.mem
;
8608 shadow
.defd
.i
|= sum
.defd
.i
;
8609 shadow
.defd
.fp
|= sum
.defd
.fp
;
8610 shadow
.defd
.mem
|= sum
.defd
.mem
;
8612 if ((sum
.defd
.i
& shadow
.used
.i
)
8613 || (sum
.defd
.fp
& shadow
.used
.fp
)
8614 || (sum
.defd
.mem
& shadow
.used
.mem
))
8616 /* (a) would be violated (also takes care of (b)) */
8617 if (get_attr_trap (i
) == TRAP_YES
8618 && ((sum
.defd
.i
& sum
.used
.i
)
8619 || (sum
.defd
.fp
& sum
.used
.fp
)))
8638 n
= emit_insn_before (gen_trapb (), i
);
8639 PUT_MODE (n
, TImode
);
8640 PUT_MODE (i
, TImode
);
8644 shadow
.used
.mem
= 0;
8645 shadow
.defd
= shadow
.used
;
8650 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8651 && GET_CODE (i
) == INSN
8652 && GET_CODE (PATTERN (i
)) != USE
8653 && GET_CODE (PATTERN (i
)) != CLOBBER
8654 && get_attr_trap (i
) == TRAP_YES
)
8656 if (optimize
&& !trap_pending
)
8657 summarize_insn (PATTERN (i
), &shadow
, 0);
8663 /* Alpha can only issue instruction groups simultaneously if they are
8664 suitibly aligned. This is very processor-specific. */
8666 enum alphaev4_pipe
{
8673 enum alphaev5_pipe
{
8684 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8685 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8686 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8687 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8688 static rtx alphaev4_next_nop
PARAMS ((int *));
8689 static rtx alphaev5_next_nop
PARAMS ((int *));
8691 static void alpha_align_insns
8692 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8694 static enum alphaev4_pipe
8695 alphaev4_insn_pipe (insn
)
8698 if (recog_memoized (insn
) < 0)
8700 if (get_attr_length (insn
) != 4)
8703 switch (get_attr_type (insn
))
8737 static enum alphaev5_pipe
8738 alphaev5_insn_pipe (insn
)
8741 if (recog_memoized (insn
) < 0)
8743 if (get_attr_length (insn
) != 4)
8746 switch (get_attr_type (insn
))
8787 /* IN_USE is a mask of the slots currently filled within the insn group.
8788 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8789 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8791 LEN is, of course, the length of the group in bytes. */
8794 alphaev4_next_group (insn
, pin_use
, plen
)
8796 int *pin_use
, *plen
;
8803 || GET_CODE (PATTERN (insn
)) == CLOBBER
8804 || GET_CODE (PATTERN (insn
)) == USE
)
8809 enum alphaev4_pipe pipe
;
8811 pipe
= alphaev4_insn_pipe (insn
);
8815 /* Force complex instructions to start new groups. */
8819 /* If this is a completely unrecognized insn, its an asm.
8820 We don't know how long it is, so record length as -1 to
8821 signal a needed realignment. */
8822 if (recog_memoized (insn
) < 0)
8825 len
= get_attr_length (insn
);
8829 if (in_use
& EV4_IB0
)
8831 if (in_use
& EV4_IB1
)
8836 in_use
|= EV4_IB0
| EV4_IBX
;
8840 if (in_use
& EV4_IB0
)
8842 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8850 if (in_use
& EV4_IB1
)
8860 /* Haifa doesn't do well scheduling branches. */
8861 if (GET_CODE (insn
) == JUMP_INSN
)
8865 insn
= next_nonnote_insn (insn
);
8867 if (!insn
|| ! INSN_P (insn
))
8870 /* Let Haifa tell us where it thinks insn group boundaries are. */
8871 if (GET_MODE (insn
) == TImode
)
8874 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8879 insn
= next_nonnote_insn (insn
);
8887 /* IN_USE is a mask of the slots currently filled within the insn group.
8888 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8889 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8891 LEN is, of course, the length of the group in bytes. */
8894 alphaev5_next_group (insn
, pin_use
, plen
)
8896 int *pin_use
, *plen
;
8903 || GET_CODE (PATTERN (insn
)) == CLOBBER
8904 || GET_CODE (PATTERN (insn
)) == USE
)
8909 enum alphaev5_pipe pipe
;
8911 pipe
= alphaev5_insn_pipe (insn
);
8915 /* Force complex instructions to start new groups. */
8919 /* If this is a completely unrecognized insn, its an asm.
8920 We don't know how long it is, so record length as -1 to
8921 signal a needed realignment. */
8922 if (recog_memoized (insn
) < 0)
8925 len
= get_attr_length (insn
);
8928 /* ??? Most of the places below, we would like to abort, as
8929 it would indicate an error either in Haifa, or in the
8930 scheduling description. Unfortunately, Haifa never
8931 schedules the last instruction of the BB, so we don't
8932 have an accurate TI bit to go off. */
8934 if (in_use
& EV5_E0
)
8936 if (in_use
& EV5_E1
)
8941 in_use
|= EV5_E0
| EV5_E01
;
8945 if (in_use
& EV5_E0
)
8947 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8955 if (in_use
& EV5_E1
)
8961 if (in_use
& EV5_FA
)
8963 if (in_use
& EV5_FM
)
8968 in_use
|= EV5_FA
| EV5_FAM
;
8972 if (in_use
& EV5_FA
)
8978 if (in_use
& EV5_FM
)
8991 /* Haifa doesn't do well scheduling branches. */
8992 /* ??? If this is predicted not-taken, slotting continues, except
8993 that no more IBR, FBR, or JSR insns may be slotted. */
8994 if (GET_CODE (insn
) == JUMP_INSN
)
8998 insn
= next_nonnote_insn (insn
);
9000 if (!insn
|| ! INSN_P (insn
))
9003 /* Let Haifa tell us where it thinks insn group boundaries are. */
9004 if (GET_MODE (insn
) == TImode
)
9007 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9012 insn
= next_nonnote_insn (insn
);
9021 alphaev4_next_nop (pin_use
)
9024 int in_use
= *pin_use
;
9027 if (!(in_use
& EV4_IB0
))
9032 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
9037 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
9050 alphaev5_next_nop (pin_use
)
9053 int in_use
= *pin_use
;
9056 if (!(in_use
& EV5_E1
))
9061 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
9066 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
9078 /* The instruction group alignment main loop. */
9081 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
9083 unsigned int max_align
;
9084 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
9085 rtx (*next_nop
) PARAMS ((int *));
9087 /* ALIGN is the known alignment for the insn group. */
9089 /* OFS is the offset of the current insn in the insn group. */
9091 int prev_in_use
, in_use
, len
;
9094 /* Let shorten branches care for assigning alignments to code labels. */
9095 shorten_branches (insns
);
9097 if (align_functions
< 4)
9099 else if ((unsigned int) align_functions
< max_align
)
9100 align
= align_functions
;
9104 ofs
= prev_in_use
= 0;
9106 if (GET_CODE (i
) == NOTE
)
9107 i
= next_nonnote_insn (i
);
9111 next
= (*next_group
) (i
, &in_use
, &len
);
9113 /* When we see a label, resync alignment etc. */
9114 if (GET_CODE (i
) == CODE_LABEL
)
9116 unsigned int new_align
= 1 << label_to_alignment (i
);
9118 if (new_align
>= align
)
9120 align
= new_align
< max_align
? new_align
: max_align
;
9124 else if (ofs
& (new_align
-1))
9125 ofs
= (ofs
| (new_align
-1)) + 1;
9130 /* Handle complex instructions special. */
9131 else if (in_use
== 0)
9133 /* Asms will have length < 0. This is a signal that we have
9134 lost alignment knowledge. Assume, however, that the asm
9135 will not mis-align instructions. */
9144 /* If the known alignment is smaller than the recognized insn group,
9145 realign the output. */
9146 else if ((int) align
< len
)
9148 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9151 where
= prev
= prev_nonnote_insn (i
);
9152 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
9155 /* Can't realign between a call and its gp reload. */
9156 if (! (TARGET_EXPLICIT_RELOCS
9157 && prev
&& GET_CODE (prev
) == CALL_INSN
))
9159 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9160 align
= 1 << new_log_align
;
9165 /* If the group won't fit in the same INT16 as the previous,
9166 we need to add padding to keep the group together. Rather
9167 than simply leaving the insn filling to the assembler, we
9168 can make use of the knowledge of what sorts of instructions
9169 were issued in the previous group to make sure that all of
9170 the added nops are really free. */
9171 else if (ofs
+ len
> (int) align
)
9173 int nop_count
= (align
- ofs
) / 4;
9176 /* Insert nops before labels, branches, and calls to truely merge
9177 the execution of the nops with the previous instruction group. */
9178 where
= prev_nonnote_insn (i
);
9181 if (GET_CODE (where
) == CODE_LABEL
)
9183 rtx where2
= prev_nonnote_insn (where
);
9184 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
9187 else if (GET_CODE (where
) == INSN
)
9194 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9195 while (--nop_count
);
9199 ofs
= (ofs
+ len
) & (align
- 1);
9200 prev_in_use
= in_use
;
9205 /* Machine dependent reorg pass. */
9211 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9212 alpha_handle_trap_shadows (insns
);
9214 /* Due to the number of extra trapb insns, don't bother fixing up
9215 alignment when trap precision is instruction. Moreover, we can
9216 only do our job when sched2 is run. */
9217 if (optimize
&& !optimize_size
9218 && alpha_tp
!= ALPHA_TP_INSN
9219 && flag_schedule_insns_after_reload
)
9221 if (alpha_cpu
== PROCESSOR_EV4
)
9222 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
9223 else if (alpha_cpu
== PROCESSOR_EV5
)
9224 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
9228 #ifdef OBJECT_FORMAT_ELF
9230 /* Switch to the section to which we should output X. The only thing
9231 special we do here is to honor small data. */
9234 alpha_elf_select_rtx_section (mode
, x
, align
)
9235 enum machine_mode mode
;
9237 unsigned HOST_WIDE_INT align
;
9239 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9240 /* ??? Consider using mergable sdata sections. */
9243 default_elf_select_rtx_section (mode
, x
, align
);
9246 #endif /* OBJECT_FORMAT_ELF */
9248 /* Structure to collect function names for final output in link section. */
9249 /* Note that items marked with GTY can't be ifdef'ed out. */
9251 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9252 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9254 struct alpha_links
GTY(())
9258 enum links_kind lkind
;
9259 enum reloc_kind rkind
;
9262 struct alpha_funcs
GTY(())
9265 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9269 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9270 splay_tree alpha_links_tree
;
9271 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9272 splay_tree alpha_funcs_tree
;
9274 static GTY(()) int alpha_funcs_num
;
9276 #if TARGET_ABI_OPEN_VMS
9278 /* Return the VMS argument type corresponding to MODE. */
9281 alpha_arg_type (mode
)
9282 enum machine_mode mode
;
9287 return TARGET_FLOAT_VAX
? FF
: FS
;
9289 return TARGET_FLOAT_VAX
? FD
: FT
;
9295 /* Return an rtx for an integer representing the VMS Argument Information
9299 alpha_arg_info_reg_val (cum
)
9300 CUMULATIVE_ARGS cum
;
9302 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9305 for (i
= 0; i
< 6; i
++)
9306 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9308 return GEN_INT (regval
);
9311 /* Make (or fake) .linkage entry for function call.
9313 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9315 Return an SYMBOL_REF rtx for the linkage. */
9318 alpha_need_linkage (name
, is_local
)
9322 splay_tree_node node
;
9323 struct alpha_links
*al
;
9330 struct alpha_funcs
*cfaf
;
9332 if (!alpha_funcs_tree
)
9333 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9334 splay_tree_compare_pointers
);
9336 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9339 cfaf
->num
= ++alpha_funcs_num
;
9341 splay_tree_insert (alpha_funcs_tree
,
9342 (splay_tree_key
) current_function_decl
,
9343 (splay_tree_value
) cfaf
);
9346 if (alpha_links_tree
)
9348 /* Is this name already defined? */
9350 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9353 al
= (struct alpha_links
*) node
->value
;
9356 /* Defined here but external assumed. */
9357 if (al
->lkind
== KIND_EXTERN
)
9358 al
->lkind
= KIND_LOCAL
;
9362 /* Used here but unused assumed. */
9363 if (al
->lkind
== KIND_UNUSED
)
9364 al
->lkind
= KIND_LOCAL
;
9370 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9372 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9373 name
= ggc_strdup (name
);
9375 /* Assume external if no definition. */
9376 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9378 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9379 get_identifier (name
);
9381 /* Construct a SYMBOL_REF for us to call. */
9383 size_t name_len
= strlen (name
);
9384 char *linksym
= alloca (name_len
+ 6);
9386 memcpy (linksym
+ 1, name
, name_len
);
9387 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9388 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9389 ggc_alloc_string (linksym
, name_len
+ 5));
9392 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9393 (splay_tree_value
) al
);
9399 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9405 splay_tree_node cfunnode
;
9406 struct alpha_funcs
*cfaf
;
9407 struct alpha_links
*al
;
9408 const char *name
= XSTR (linkage
, 0);
9410 cfaf
= (struct alpha_funcs
*) 0;
9411 al
= (struct alpha_links
*) 0;
9413 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9414 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9418 splay_tree_node lnode
;
9420 /* Is this name already defined? */
9422 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9424 al
= (struct alpha_links
*) lnode
->value
;
9427 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9435 splay_tree_node node
= 0;
9436 struct alpha_links
*anl
;
9441 name_len
= strlen (name
);
9443 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9444 al
->num
= cfaf
->num
;
9446 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9449 anl
= (struct alpha_links
*) node
->value
;
9450 al
->lkind
= anl
->lkind
;
9453 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9454 buflen
= strlen (buf
);
9455 linksym
= alloca (buflen
+ 1);
9456 memcpy (linksym
, buf
, buflen
+ 1);
9458 al
->linkage
= gen_rtx_SYMBOL_REF
9459 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9461 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9462 (splay_tree_value
) al
);
9466 al
->rkind
= KIND_CODEADDR
;
9468 al
->rkind
= KIND_LINKAGE
;
9471 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9477 alpha_write_one_linkage (node
, data
)
9478 splay_tree_node node
;
9481 const char *const name
= (const char *) node
->key
;
9482 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9483 FILE *stream
= (FILE *) data
;
9485 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9486 if (link
->rkind
== KIND_CODEADDR
)
9488 if (link
->lkind
== KIND_LOCAL
)
9490 /* Local and used */
9491 fprintf (stream
, "\t.quad %s..en\n", name
);
9495 /* External and used, request code address. */
9496 fprintf (stream
, "\t.code_address %s\n", name
);
9501 if (link
->lkind
== KIND_LOCAL
)
9503 /* Local and used, build linkage pair. */
9504 fprintf (stream
, "\t.quad %s..en\n", name
);
9505 fprintf (stream
, "\t.quad %s\n", name
);
9509 /* External and used, request linkage pair. */
9510 fprintf (stream
, "\t.linkage %s\n", name
);
9518 alpha_write_linkage (stream
, funname
, fundecl
)
9520 const char *funname
;
9523 splay_tree_node node
;
9524 struct alpha_funcs
*func
;
9527 fprintf (stream
, "\t.align 3\n");
9528 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9529 func
= (struct alpha_funcs
*) node
->value
;
9531 fputs ("\t.name ", stream
);
9532 assemble_name (stream
, funname
);
9533 fputs ("..na\n", stream
);
9534 ASM_OUTPUT_LABEL (stream
, funname
);
9535 fprintf (stream
, "\t.pdesc ");
9536 assemble_name (stream
, funname
);
9537 fprintf (stream
, "..en,%s\n",
9538 alpha_procedure_type
== PT_STACK
? "stack"
9539 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9543 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9544 /* splay_tree_delete (func->links); */
9548 /* Given a decl, a section name, and whether the decl initializer
9549 has relocs, choose attributes for the section. */
9551 #define SECTION_VMS_OVERLAY SECTION_FORGET
9552 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9553 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9556 vms_section_type_flags (decl
, name
, reloc
)
9561 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9563 if (decl
&& DECL_ATTRIBUTES (decl
)
9564 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9565 flags
|= SECTION_VMS_OVERLAY
;
9566 if (decl
&& DECL_ATTRIBUTES (decl
)
9567 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9568 flags
|= SECTION_VMS_GLOBAL
;
9569 if (decl
&& DECL_ATTRIBUTES (decl
)
9570 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9571 flags
|= SECTION_VMS_INITIALIZE
;
9576 /* Switch to an arbitrary section NAME with attributes as specified
9577 by FLAGS. ALIGN specifies any known alignment requirements for
9578 the section; 0 if the default should be used. */
9581 vms_asm_named_section (name
, flags
)
9585 fputc ('\n', asm_out_file
);
9586 fprintf (asm_out_file
, ".section\t%s", name
);
9588 if (flags
& SECTION_VMS_OVERLAY
)
9589 fprintf (asm_out_file
, ",OVR");
9590 if (flags
& SECTION_VMS_GLOBAL
)
9591 fprintf (asm_out_file
, ",GBL");
9592 if (flags
& SECTION_VMS_INITIALIZE
)
9593 fprintf (asm_out_file
, ",NOMOD");
9594 if (flags
& SECTION_DEBUG
)
9595 fprintf (asm_out_file
, ",NOWRT");
9597 fputc ('\n', asm_out_file
);
9600 /* Record an element in the table of global constructors. SYMBOL is
9601 a SYMBOL_REF of the function to be called; PRIORITY is a number
9602 between 0 and MAX_INIT_PRIORITY.
9604 Differs from default_ctors_section_asm_out_constructor in that the
9605 width of the .ctors entry is always 64 bits, rather than the 32 bits
9606 used by a normal pointer. */
9609 vms_asm_out_constructor (symbol
, priority
)
9611 int priority ATTRIBUTE_UNUSED
;
9614 assemble_align (BITS_PER_WORD
);
9615 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9619 vms_asm_out_destructor (symbol
, priority
)
9621 int priority ATTRIBUTE_UNUSED
;
9624 assemble_align (BITS_PER_WORD
);
9625 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9630 alpha_need_linkage (name
, is_local
)
9631 const char *name ATTRIBUTE_UNUSED
;
9632 int is_local ATTRIBUTE_UNUSED
;
9638 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9639 rtx linkage ATTRIBUTE_UNUSED
;
9640 tree cfundecl ATTRIBUTE_UNUSED
;
9641 int lflag ATTRIBUTE_UNUSED
;
9642 int rflag ATTRIBUTE_UNUSED
;
9647 #endif /* TARGET_ABI_OPEN_VMS */
9649 #if TARGET_ABI_UNICOSMK
9651 static void unicosmk_output_module_name
PARAMS ((FILE *));
9652 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9653 static void unicosmk_output_dex
PARAMS ((FILE *));
9654 static void unicosmk_output_externs
PARAMS ((FILE *));
9655 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9656 static const char *unicosmk_ssib_name
PARAMS ((void));
9657 static int unicosmk_special_name
PARAMS ((const char *));
9659 /* Define the offset between two registers, one to be eliminated, and the
9660 other its replacement, at the start of a routine. */
9663 unicosmk_initial_elimination_offset (from
, to
)
9669 fixed_size
= alpha_sa_size();
9670 if (fixed_size
!= 0)
9673 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9675 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9677 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9678 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9679 + ALPHA_ROUND (get_frame_size()));
9680 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9681 return (ALPHA_ROUND (fixed_size
)
9682 + ALPHA_ROUND (get_frame_size()
9683 + current_function_outgoing_args_size
));
9688 /* Output the module name for .ident and .end directives. We have to strip
9689 directories and add make sure that the module name starts with a letter
9693 unicosmk_output_module_name (file
)
9698 /* Strip directories. */
9700 name
= strrchr (main_input_filename
, '/');
9704 name
= main_input_filename
;
9706 /* CAM only accepts module names that start with a letter or '$'. We
9707 prefix the module name with a '$' if necessary. */
9709 if (!ISALPHA (*name
))
9711 output_clean_symbol_name (file
, name
);
9714 /* Output text that to appear at the beginning of an assembler file. */
9717 unicosmk_asm_file_start (file
)
9722 fputs ("\t.ident\t", file
);
9723 unicosmk_output_module_name (file
);
9724 fputs ("\n\n", file
);
9726 /* The Unicos/Mk assembler uses different register names. Instead of trying
9727 to support them, we simply use micro definitions. */
9729 /* CAM has different register names: rN for the integer register N and fN
9730 for the floating-point register N. Instead of trying to use these in
9731 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9734 for (i
= 0; i
< 32; ++i
)
9735 fprintf (file
, "$%d <- r%d\n", i
, i
);
9737 for (i
= 0; i
< 32; ++i
)
9738 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9742 /* The .align directive fill unused space with zeroes which does not work
9743 in code sections. We define the macro 'gcc@code@align' which uses nops
9744 instead. Note that it assumes that code sections always have the
9745 biggest possible alignment since . refers to the current offset from
9746 the beginning of the section. */
9748 fputs ("\t.macro gcc@code@align n\n", file
);
9749 fputs ("gcc@n@bytes = 1 << n\n", file
);
9750 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9751 fputs ("\t.if ne, gcc@here, 0\n", file
);
9752 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9753 fputs ("\tbis r31,r31,r31\n", file
);
9754 fputs ("\t.endr\n", file
);
9755 fputs ("\t.endif\n", file
);
9756 fputs ("\t.endm gcc@code@align\n\n", file
);
9758 /* Output extern declarations which should always be visible. */
9759 unicosmk_output_default_externs (file
);
9761 /* Open a dummy section. We always need to be inside a section for the
9762 section-switching code to work correctly.
9763 ??? This should be a module id or something like that. I still have to
9764 figure out what the rules for those are. */
9765 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9768 /* Output text to appear at the end of an assembler file. This includes all
9769 pending extern declarations and DEX expressions. */
9772 unicosmk_asm_file_end (file
)
9775 fputs ("\t.endp\n\n", file
);
9777 /* Output all pending externs. */
9779 unicosmk_output_externs (file
);
9781 /* Output dex definitions used for functions whose names conflict with
9784 unicosmk_output_dex (file
);
9786 fputs ("\t.end\t", file
);
9787 unicosmk_output_module_name (file
);
9791 /* Output the definition of a common variable. */
9794 unicosmk_output_common (file
, name
, size
, align
)
9801 printf ("T3E__: common %s\n", name
);
9804 fputs("\t.endp\n\n\t.psect ", file
);
9805 assemble_name(file
, name
);
9806 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9807 fprintf(file
, "\t.byte\t0:%d\n", size
);
9809 /* Mark the symbol as defined in this module. */
9810 name_tree
= get_identifier (name
);
9811 TREE_ASM_WRITTEN (name_tree
) = 1;
9814 #define SECTION_PUBLIC SECTION_MACH_DEP
9815 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9816 static int current_section_align
;
9819 unicosmk_section_type_flags (decl
, name
, reloc
)
9822 int reloc ATTRIBUTE_UNUSED
;
9824 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9829 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9831 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9832 if (align_functions_log
> current_section_align
)
9833 current_section_align
= align_functions_log
;
9835 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9836 flags
|= SECTION_MAIN
;
9839 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9841 if (TREE_PUBLIC (decl
))
9842 flags
|= SECTION_PUBLIC
;
9847 /* Generate a section name for decl and associate it with the
9851 unicosmk_unique_section (decl
, reloc
)
9853 int reloc ATTRIBUTE_UNUSED
;
9861 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9862 name
= alpha_strip_name_encoding (name
);
9863 len
= strlen (name
);
9865 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9869 /* It is essential that we prefix the section name here because
9870 otherwise the section names generated for constructors and
9871 destructors confuse collect2. */
9873 string
= alloca (len
+ 6);
9874 sprintf (string
, "code@%s", name
);
9875 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9877 else if (TREE_PUBLIC (decl
))
9878 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9883 string
= alloca (len
+ 6);
9884 sprintf (string
, "data@%s", name
);
9885 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9889 /* Switch to an arbitrary section NAME with attributes as specified
9890 by FLAGS. ALIGN specifies any known alignment requirements for
9891 the section; 0 if the default should be used. */
9894 unicosmk_asm_named_section (name
, flags
)
9900 /* Close the previous section. */
9902 fputs ("\t.endp\n\n", asm_out_file
);
9904 /* Find out what kind of section we are opening. */
9906 if (flags
& SECTION_MAIN
)
9907 fputs ("\t.start\tmain\n", asm_out_file
);
9909 if (flags
& SECTION_CODE
)
9911 else if (flags
& SECTION_PUBLIC
)
9916 if (current_section_align
!= 0)
9917 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9918 current_section_align
, kind
);
9920 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9924 unicosmk_insert_attributes (decl
, attr_ptr
)
9926 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9929 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9930 unicosmk_unique_section (decl
, 0);
9933 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9934 in code sections because .align fill unused space with zeroes. */
9937 unicosmk_output_align (file
, align
)
9941 if (inside_function
)
9942 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9944 fprintf (file
, "\t.align\t%d\n", align
);
9947 /* Add a case vector to the current function's list of deferred case
9948 vectors. Case vectors have to be put into a separate section because CAM
9949 does not allow data definitions in code sections. */
9952 unicosmk_defer_case_vector (lab
, vec
)
9956 struct machine_function
*machine
= cfun
->machine
;
9958 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9959 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9960 machine
->addr_list
);
9963 /* Output a case vector. */
9966 unicosmk_output_addr_vec (file
, vec
)
9970 rtx lab
= XEXP (vec
, 0);
9971 rtx body
= XEXP (vec
, 1);
9972 int vlen
= XVECLEN (body
, 0);
9975 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9977 for (idx
= 0; idx
< vlen
; idx
++)
9979 ASM_OUTPUT_ADDR_VEC_ELT
9980 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9984 /* Output current function's deferred case vectors. */
9987 unicosmk_output_deferred_case_vectors (file
)
9990 struct machine_function
*machine
= cfun
->machine
;
9993 if (machine
->addr_list
== NULL_RTX
)
9997 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9998 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
10001 /* Set up the dynamic subprogram information block (DSIB) and update the
10002 frame pointer register ($15) for subroutines which have a frame. If the
10003 subroutine doesn't have a frame, simply increment $15. */
10006 unicosmk_gen_dsib (imaskP
)
10007 unsigned long * imaskP
;
10009 if (alpha_procedure_type
== PT_STACK
)
10011 const char *ssib_name
;
10014 /* Allocate 64 bytes for the DSIB. */
10016 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10018 emit_insn (gen_blockage ());
10020 /* Save the return address. */
10022 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
10023 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10024 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
10025 (*imaskP
) &= ~(1L << REG_RA
);
10027 /* Save the old frame pointer. */
10029 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
10030 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10031 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
10032 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
10034 emit_insn (gen_blockage ());
10036 /* Store the SSIB pointer. */
10038 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
10039 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
10040 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10042 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
10043 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
10044 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
10046 /* Save the CIW index. */
10048 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
10049 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10050 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
10052 emit_insn (gen_blockage ());
10054 /* Set the new frame pointer. */
10056 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10057 stack_pointer_rtx
, GEN_INT (64))));
10062 /* Increment the frame pointer register to indicate that we do not
10065 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10066 hard_frame_pointer_rtx
, GEN_INT (1))));
10070 #define SSIB_PREFIX "__SSIB_"
10071 #define SSIB_PREFIX_LEN 7
10073 /* Generate the name of the SSIB section for the current function. */
10075 static const char *
10076 unicosmk_ssib_name ()
10078 /* This is ok since CAM won't be able to deal with names longer than that
10081 static char name
[256];
10084 const char *fnname
;
10087 x
= DECL_RTL (cfun
->decl
);
10088 if (GET_CODE (x
) != MEM
)
10091 if (GET_CODE (x
) != SYMBOL_REF
)
10093 fnname
= alpha_strip_name_encoding (XSTR (x
, 0));
10095 len
= strlen (fnname
);
10096 if (len
+ SSIB_PREFIX_LEN
> 255)
10097 len
= 255 - SSIB_PREFIX_LEN
;
10099 strcpy (name
, SSIB_PREFIX
);
10100 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
10101 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10106 /* Output the static subroutine information block for the current
10110 unicosmk_output_ssib (file
, fnname
)
10112 const char *fnname
;
10118 struct machine_function
*machine
= cfun
->machine
;
10121 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10122 unicosmk_ssib_name ());
10124 /* Some required stuff and the function name length. */
10126 len
= strlen (fnname
);
10127 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10130 ??? We don't do that yet. */
10132 fputs ("\t.quad\t0\n", file
);
10134 /* Function address. */
10136 fputs ("\t.quad\t", file
);
10137 assemble_name (file
, fnname
);
10140 fputs ("\t.quad\t0\n", file
);
10141 fputs ("\t.quad\t0\n", file
);
10144 ??? We do it the same way Cray CC does it but this could be
10147 for( i
= 0; i
< len
; i
++ )
10148 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10149 if( (len
% 8) == 0 )
10150 fputs ("\t.quad\t0\n", file
);
10152 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10154 /* All call information words used in the function. */
10156 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10159 fprintf (file
, "\t.quad\t");
10160 #if HOST_BITS_PER_WIDE_INT == 32
10161 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
10162 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10164 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
10166 fprintf (file
, "\n");
10170 /* Add a call information word (CIW) to the list of the current function's
10171 CIWs and return its index.
10173 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10176 unicosmk_add_call_info_word (x
)
10180 struct machine_function
*machine
= cfun
->machine
;
10182 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10183 if (machine
->first_ciw
== NULL_RTX
)
10184 machine
->first_ciw
= node
;
10186 XEXP (machine
->last_ciw
, 1) = node
;
10188 machine
->last_ciw
= node
;
10189 ++machine
->ciw_count
;
10191 return GEN_INT (machine
->ciw_count
10192 + strlen (current_function_name
)/8 + 5);
10195 static char unicosmk_section_buf
[100];
10198 unicosmk_text_section ()
10200 static int count
= 0;
10201 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
10203 return unicosmk_section_buf
;
10207 unicosmk_data_section ()
10209 static int count
= 1;
10210 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
10212 return unicosmk_section_buf
;
10215 /* The Cray assembler doesn't accept extern declarations for symbols which
10216 are defined in the same file. We have to keep track of all global
10217 symbols which are referenced and/or defined in a source file and output
10218 extern declarations for those which are referenced but not defined at
10219 the end of file. */
10221 /* List of identifiers for which an extern declaration might have to be
10223 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10225 struct unicosmk_extern_list
10227 struct unicosmk_extern_list
*next
;
10231 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10233 /* Output extern declarations which are required for every asm file. */
10236 unicosmk_output_default_externs (file
)
10239 static const char *const externs
[] =
10240 { "__T3E_MISMATCH" };
10245 n
= ARRAY_SIZE (externs
);
10247 for (i
= 0; i
< n
; i
++)
10248 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10251 /* Output extern declarations for global symbols which are have been
10252 referenced but not defined. */
10255 unicosmk_output_externs (file
)
10258 struct unicosmk_extern_list
*p
;
10259 const char *real_name
;
10263 len
= strlen (user_label_prefix
);
10264 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10266 /* We have to strip the encoding and possibly remove user_label_prefix
10267 from the identifier in order to handle -fleading-underscore and
10268 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10269 real_name
= alpha_strip_name_encoding (p
->name
);
10270 if (len
&& p
->name
[0] == '*'
10271 && !memcmp (real_name
, user_label_prefix
, len
))
10274 name_tree
= get_identifier (real_name
);
10275 if (! TREE_ASM_WRITTEN (name_tree
))
10277 TREE_ASM_WRITTEN (name_tree
) = 1;
10278 fputs ("\t.extern\t", file
);
10279 assemble_name (file
, p
->name
);
10285 /* Record an extern. */
10288 unicosmk_add_extern (name
)
10291 struct unicosmk_extern_list
*p
;
10293 p
= (struct unicosmk_extern_list
*)
10294 xmalloc (sizeof (struct unicosmk_extern_list
));
10295 p
->next
= unicosmk_extern_head
;
10297 unicosmk_extern_head
= p
;
10300 /* The Cray assembler generates incorrect code if identifiers which
10301 conflict with register names are used as instruction operands. We have
10302 to replace such identifiers with DEX expressions. */
10304 /* Structure to collect identifiers which have been replaced by DEX
10306 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10308 struct unicosmk_dex
{
10309 struct unicosmk_dex
*next
;
10313 /* List of identifiers which have been replaced by DEX expressions. The DEX
10314 number is determined by the position in the list. */
10316 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10318 /* The number of elements in the DEX list. */
10320 static int unicosmk_dex_count
= 0;
10322 /* Check if NAME must be replaced by a DEX expression. */
10325 unicosmk_special_name (name
)
10328 if (name
[0] == '*')
10331 if (name
[0] == '$')
10334 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10339 case '1': case '2':
10340 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10343 return (name
[2] == '\0'
10344 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10347 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10351 /* Return the DEX number if X must be replaced by a DEX expression and 0
10355 unicosmk_need_dex (x
)
10358 struct unicosmk_dex
*dex
;
10362 if (GET_CODE (x
) != SYMBOL_REF
)
10366 if (! unicosmk_special_name (name
))
10369 i
= unicosmk_dex_count
;
10370 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10372 if (! strcmp (name
, dex
->name
))
10377 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10379 dex
->next
= unicosmk_dex_list
;
10380 unicosmk_dex_list
= dex
;
10382 ++unicosmk_dex_count
;
10383 return unicosmk_dex_count
;
10386 /* Output the DEX definitions for this file. */
10389 unicosmk_output_dex (file
)
10392 struct unicosmk_dex
*dex
;
10395 if (unicosmk_dex_list
== NULL
)
10398 fprintf (file
, "\t.dexstart\n");
10400 i
= unicosmk_dex_count
;
10401 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10403 fprintf (file
, "\tDEX (%d) = ", i
);
10404 assemble_name (file
, dex
->name
);
10409 fprintf (file
, "\t.dexend\n");
10415 unicosmk_output_deferred_case_vectors (file
)
10416 FILE *file ATTRIBUTE_UNUSED
;
10420 unicosmk_gen_dsib (imaskP
)
10421 unsigned long * imaskP ATTRIBUTE_UNUSED
;
10425 unicosmk_output_ssib (file
, fnname
)
10426 FILE * file ATTRIBUTE_UNUSED
;
10427 const char * fnname ATTRIBUTE_UNUSED
;
10431 unicosmk_add_call_info_word (x
)
10432 rtx x ATTRIBUTE_UNUSED
;
10438 unicosmk_need_dex (x
)
10439 rtx x ATTRIBUTE_UNUSED
;
10444 #endif /* TARGET_ABI_UNICOSMK */
10446 #include "gt-alpha.h"