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Fix oinitialisation of frame pointer in interrupt functions.
[official-gcc.git] / gcc / config / arm / arm.h
blobed444db8029d230d896220d984ab95977dd4bc77
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 #define TARGET_CPU_arm2 0x0000
30 #define TARGET_CPU_arm250 0x0000
31 #define TARGET_CPU_arm3 0x0000
32 #define TARGET_CPU_arm6 0x0001
33 #define TARGET_CPU_arm600 0x0001
34 #define TARGET_CPU_arm610 0x0002
35 #define TARGET_CPU_arm7 0x0001
36 #define TARGET_CPU_arm7m 0x0004
37 #define TARGET_CPU_arm7dm 0x0004
38 #define TARGET_CPU_arm7dmi 0x0004
39 #define TARGET_CPU_arm700 0x0001
40 #define TARGET_CPU_arm710 0x0002
41 #define TARGET_CPU_arm7100 0x0002
42 #define TARGET_CPU_arm7500 0x0002
43 #define TARGET_CPU_arm7500fe 0x1001
44 #define TARGET_CPU_arm7tdmi 0x0008
45 #define TARGET_CPU_arm8 0x0010
46 #define TARGET_CPU_arm810 0x0020
47 #define TARGET_CPU_strongarm 0x0040
48 #define TARGET_CPU_strongarm110 0x0040
49 #define TARGET_CPU_strongarm1100 0x0040
50 #define TARGET_CPU_arm9 0x0080
51 #define TARGET_CPU_arm9tdmi 0x0080
52 #define TARGET_CPU_xscale 0x0100
53 /* Configure didn't specify. */
54 #define TARGET_CPU_generic 0x8000
55
56 typedef enum arm_cond_code
57 {
58 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
59 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
60 }
61 arm_cc;
62
63 extern arm_cc arm_current_cc;
64 extern const char * arm_condition_codes[];
65
66 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
67
68 extern int arm_target_label;
69 extern int arm_ccfsm_state;
70 extern struct rtx_def * arm_target_insn;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75 /* Define the information needed to generate branch insns. This is
76 stored from the compare operation. Note that we can't use "rtx" here
77 since it hasn't been defined! */
78 extern struct rtx_def * arm_compare_op0;
79 extern struct rtx_def * arm_compare_op1;
80 /* The label of the current constant pool. */
81 extern struct rtx_def * pool_vector_label;
82 /* Set to 1 when a return insn is output, this means that the epilogue
83 is not needed. */
84 extern int return_used_this_function;
85 /* Nonzero if the prologue must setup `fp'. */
86 extern int current_function_anonymous_args;
87 \f
88 /* Just in case configure has failed to define anything. */
89 #ifndef TARGET_CPU_DEFAULT
90 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
91 #endif
92
93 /* If the configuration file doesn't specify the cpu, the subtarget may
94 override it. If it doesn't, then default to an ARM6. */
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
96 #undef TARGET_CPU_DEFAULT
97
98 #ifdef SUBTARGET_CPU_DEFAULT
99 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
100 #else
101 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
102 #endif
103 #endif
104
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
107 #else
108 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
109 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
110 #else
111 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
112 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
113 #else
114 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
115 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
116 #else
117 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
118 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
119 #else
120 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
121 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
122 #else
123 Unrecognized value in TARGET_CPU_DEFAULT.
124 #endif
125 #endif
126 #endif
127 #endif
128 #endif
129 #endif
130
131 #ifndef CPP_PREDEFINES
132 #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm"
133 #endif
134
135 #define CPP_SPEC "\
136 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
137 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
138
139 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
140
141 /* Set the architecture define -- if -march= is set, then it overrides
142 the -mcpu= setting. */
143 #define CPP_CPU_ARCH_SPEC "\
144 %{march=arm2:-D__ARM_ARCH_2__} \
145 %{march=arm250:-D__ARM_ARCH_2__} \
146 %{march=arm3:-D__ARM_ARCH_2__} \
147 %{march=arm6:-D__ARM_ARCH_3__} \
148 %{march=arm600:-D__ARM_ARCH_3__} \
149 %{march=arm610:-D__ARM_ARCH_3__} \
150 %{march=arm7:-D__ARM_ARCH_3__} \
151 %{march=arm700:-D__ARM_ARCH_3__} \
152 %{march=arm710:-D__ARM_ARCH_3__} \
153 %{march=arm720:-D__ARM_ARCH_3__} \
154 %{march=arm7100:-D__ARM_ARCH_3__} \
155 %{march=arm7500:-D__ARM_ARCH_3__} \
156 %{march=arm7500fe:-D__ARM_ARCH_3__} \
157 %{march=arm7m:-D__ARM_ARCH_3M__} \
158 %{march=arm7dm:-D__ARM_ARCH_3M__} \
159 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
160 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
161 %{march=arm8:-D__ARM_ARCH_4__} \
162 %{march=arm810:-D__ARM_ARCH_4__} \
163 %{march=arm9:-D__ARM_ARCH_4T__} \
164 %{march=arm920:-D__ARM_ARCH_4__} \
165 %{march=arm920t:-D__ARM_ARCH_4T__} \
166 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
167 %{march=strongarm:-D__ARM_ARCH_4__} \
168 %{march=strongarm110:-D__ARM_ARCH_4__} \
169 %{march=strongarm1100:-D__ARM_ARCH_4__} \
170 %{march=xscale:-D__ARM_ARCH_5TE__} \
171 %{march=xscale:-D__XSCALE__} \
172 %{march=armv2:-D__ARM_ARCH_2__} \
173 %{march=armv2a:-D__ARM_ARCH_2__} \
174 %{march=armv3:-D__ARM_ARCH_3__} \
175 %{march=armv3m:-D__ARM_ARCH_3M__} \
176 %{march=armv4:-D__ARM_ARCH_4__} \
177 %{march=armv4t:-D__ARM_ARCH_4T__} \
178 %{march=armv5:-D__ARM_ARCH_5__} \
179 %{march=armv5t:-D__ARM_ARCH_5T__} \
180 %{march=armv5e:-D__ARM_ARCH_5E__} \
181 %{march=armv5te:-D__ARM_ARCH_5TE__} \
182 %{!march=*: \
183 %{mcpu=arm2:-D__ARM_ARCH_2__} \
184 %{mcpu=arm250:-D__ARM_ARCH_2__} \
185 %{mcpu=arm3:-D__ARM_ARCH_2__} \
186 %{mcpu=arm6:-D__ARM_ARCH_3__} \
187 %{mcpu=arm600:-D__ARM_ARCH_3__} \
188 %{mcpu=arm610:-D__ARM_ARCH_3__} \
189 %{mcpu=arm7:-D__ARM_ARCH_3__} \
190 %{mcpu=arm700:-D__ARM_ARCH_3__} \
191 %{mcpu=arm710:-D__ARM_ARCH_3__} \
192 %{mcpu=arm720:-D__ARM_ARCH_3__} \
193 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
194 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
195 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
196 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
197 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
198 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
199 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
200 %{mcpu=arm8:-D__ARM_ARCH_4__} \
201 %{mcpu=arm810:-D__ARM_ARCH_4__} \
202 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
203 %{mcpu=arm920:-D__ARM_ARCH_4__} \
204 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
205 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
206 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
207 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
208 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
209 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
210 %{mcpu=xscale:-D__XSCALE__} \
211 %{!mcpu*:%(cpp_cpu_arch_default)}} \
212 "
213
214 /* Define __APCS_26__ if the PC also contains the PSR */
215 #define CPP_APCS_PC_SPEC "\
216 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
217 -D__APCS_32__} \
218 %{mapcs-26:-D__APCS_26__} \
219 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
220 "
221
222 #ifndef CPP_APCS_PC_DEFAULT_SPEC
223 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
224 #endif
225
226 #define CPP_FLOAT_SPEC "\
227 %{msoft-float:\
228 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
229 -D__SOFTFP__} \
230 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
231 "
232
233 /* Default is hard float, which doesn't define anything */
234 #define CPP_FLOAT_DEFAULT_SPEC ""
235
236 #define CPP_ENDIAN_SPEC "\
237 %{mbig-endian: \
238 %{mlittle-endian: \
239 %e-mbig-endian and -mlittle-endian may not be used together} \
240 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
241 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
242 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
243 "
244
245 /* Default is little endian. */
246 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
247
248 /* Add a define for interworking. Needed when building libgcc.a.
249 This must define __THUMB_INTERWORK__ to the pre-processor if
250 interworking is enabled by default. */
251 #ifndef CPP_INTERWORK_DEFAULT_SPEC
252 #define CPP_INTERWORK_DEFAULT_SPEC ""
253 #endif
254
255 #define CPP_INTERWORK_SPEC " \
256 %{mthumb-interwork: \
257 %{mno-thumb-interwork: %eIncompatible interworking options} \
258 -D__THUMB_INTERWORK__} \
259 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
260 "
261
262 #define CC1_SPEC ""
263
264 /* This macro defines names of additional specifications to put in the specs
265 that can be used in various specifications like CC1_SPEC. Its definition
266 is an initializer with a subgrouping for each command option.
267
268 Each subgrouping contains a string constant, that defines the
269 specification name, and a string constant that used by the GNU CC driver
270 program.
271
272 Do not define this macro if it does not need to do anything. */
273 #define EXTRA_SPECS \
274 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
275 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
276 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
277 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
278 { "cpp_float", CPP_FLOAT_SPEC }, \
279 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
280 { "cpp_endian", CPP_ENDIAN_SPEC }, \
281 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
282 { "cpp_isa", CPP_ISA_SPEC }, \
283 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
284 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
285 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
286 SUBTARGET_EXTRA_SPECS
287
288 #ifndef SUBTARGET_EXTRA_SPECS
289 #define SUBTARGET_EXTRA_SPECS
290 #endif
291
292 #ifndef SUBTARGET_CPP_SPEC
293 #define SUBTARGET_CPP_SPEC ""
294 #endif
295 \f
296 /* Run-time Target Specification. */
297 #ifndef TARGET_VERSION
298 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
299 #endif
300
301 /* Nonzero if the function prologue (and epilogue) should obey
302 the ARM Procedure Call Standard. */
303 #define ARM_FLAG_APCS_FRAME (1 << 0)
304
305 /* Nonzero if the function prologue should output the function name to enable
306 the post mortem debugger to print a backtrace (very useful on RISCOS,
307 unused on RISCiX). Specifying this flag also enables
308 -fno-omit-frame-pointer.
309 XXX Must still be implemented in the prologue. */
310 #define ARM_FLAG_POKE (1 << 1)
311
312 /* Nonzero if floating point instructions are emulated by the FPE, in which
313 case instruction scheduling becomes very uninteresting. */
314 #define ARM_FLAG_FPE (1 << 2)
315
316 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
317 that assume restoration of the condition flags when returning from a
318 branch and link (ie a function). */
319 #define ARM_FLAG_APCS_32 (1 << 3)
320
321 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
322
323 /* Nonzero if stack checking should be performed on entry to each function
324 which allocates temporary variables on the stack. */
325 #define ARM_FLAG_APCS_STACK (1 << 4)
326
327 /* Nonzero if floating point parameters should be passed to functions in
328 floating point registers. */
329 #define ARM_FLAG_APCS_FLOAT (1 << 5)
330
331 /* Nonzero if re-entrant, position independent code should be generated.
332 This is equivalent to -fpic. */
333 #define ARM_FLAG_APCS_REENT (1 << 6)
334
335 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
336 be loaded using either LDRH or LDRB instructions. */
337 #define ARM_FLAG_MMU_TRAPS (1 << 7)
338
339 /* Nonzero if all floating point instructions are missing (and there is no
340 emulator either). Generate function calls for all ops in this case. */
341 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
342
343 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
344 #define ARM_FLAG_BIG_END (1 << 9)
345
346 /* Nonzero if we should compile for Thumb interworking. */
347 #define ARM_FLAG_INTERWORK (1 << 10)
348
349 /* Nonzero if we should have little-endian words even when compiling for
350 big-endian (for backwards compatibility with older versions of GCC). */
351 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
352
353 /* Nonzero if we need to protect the prolog from scheduling */
354 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
355
356 /* Nonzero if a call to abort should be generated if a noreturn
357 function tries to return. */
358 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
359
360 /* Nonzero if function prologues should not load the PIC register. */
361 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
362
363 /* Nonzero if all call instructions should be indirect. */
364 #define ARM_FLAG_LONG_CALLS (1 << 15)
365
366 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
367 #define ARM_FLAG_THUMB (1 << 16)
368
369 /* Set if a TPCS style stack frame should be generated, for non-leaf
370 functions, even if they do not need one. */
371 #define THUMB_FLAG_BACKTRACE (1 << 17)
372
373 /* Set if a TPCS style stack frame should be generated, for leaf
374 functions, even if they do not need one. */
375 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
376
377 /* Set if externally visible functions should assume that they
378 might be called in ARM mode, from a non-thumb aware code. */
379 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
380
381 /* Set if calls via function pointers should assume that their
382 destination is non-Thumb aware. */
383 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
384
385 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
386 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
387 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
388 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
389 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
390 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
391 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
392 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
393 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
394 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
395 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
396 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
397 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
398 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
399 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
400 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
401 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
402 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
403 #define TARGET_ARM (! TARGET_THUMB)
404 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
405 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
406 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
407 #define TARGET_BACKTRACE (leaf_function_p () \
408 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
409 : (target_flags & THUMB_FLAG_BACKTRACE))
410
411 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
412 Bit 31 is reserved. See riscix.h. */
413 #ifndef SUBTARGET_SWITCHES
414 #define SUBTARGET_SWITCHES
415 #endif
416
417 #define TARGET_SWITCHES \
418 { \
419 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
420 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
421 N_("Generate APCS conformant stack frames") }, \
422 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
423 {"poke-function-name", ARM_FLAG_POKE, \
424 N_("Store function names in object code") }, \
425 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
426 {"fpe", ARM_FLAG_FPE, "" }, \
427 {"apcs-32", ARM_FLAG_APCS_32, \
428 N_("Use the 32-bit version of the APCS") }, \
429 {"apcs-26", -ARM_FLAG_APCS_32, \
430 N_("Use the 26-bit version of the APCS") }, \
431 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
432 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
433 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
434 N_("Pass FP arguments in FP registers") }, \
435 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
436 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
437 N_("Generate re-entrant, PIC code") }, \
438 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
439 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
440 N_("The MMU will trap on unaligned accesses") }, \
441 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
442 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
443 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
444 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
445 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
446 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
447 N_("Use library calls to perform FP operations") }, \
448 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
449 N_("Use hardware floating point instructions") }, \
450 {"big-endian", ARM_FLAG_BIG_END, \
451 N_("Assume target CPU is configured as big endian") }, \
452 {"little-endian", -ARM_FLAG_BIG_END, \
453 N_("Assume target CPU is configured as little endian") }, \
454 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
455 N_("Assume big endian bytes, little endian words") }, \
456 {"thumb-interwork", ARM_FLAG_INTERWORK, \
457 N_("Support calls between Thumb and ARM instruction sets") }, \
458 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
459 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
460 N_("Generate a call to abort if a noreturn function returns")}, \
461 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
462 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
463 N_("Do not move instructions into a function's prologue") }, \
464 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
465 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
466 N_("Do not load the PIC register in function prologues") }, \
467 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
468 {"long-calls", ARM_FLAG_LONG_CALLS, \
469 N_("Generate call insns as indirect calls, if necessary") }, \
470 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
471 {"thumb", ARM_FLAG_THUMB, \
472 N_("Compile for the Thumb not the ARM") }, \
473 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
474 {"arm", -ARM_FLAG_THUMB, "" }, \
475 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
476 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
477 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
478 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
479 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
480 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
481 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
482 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
483 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
484 "" }, \
485 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
486 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
487 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
488 "" }, \
489 SUBTARGET_SWITCHES \
490 {"", TARGET_DEFAULT, "" } \
491 }
492
493 #define TARGET_OPTIONS \
494 { \
495 {"cpu=", & arm_select[0].string, \
496 N_("Specify the name of the target CPU") }, \
497 {"arch=", & arm_select[1].string, \
498 N_("Specify the name of the target architecture") }, \
499 {"tune=", & arm_select[2].string, "" }, \
500 {"fpe=", & target_fp_name, "" }, \
501 {"fp=", & target_fp_name, \
502 N_("Specify the version of the floating point emulator") }, \
503 {"structure-size-boundary=", & structure_size_string, \
504 N_("Specify the minimum bit alignment of structures") }, \
505 {"pic-register=", & arm_pic_register_string, \
506 N_("Specify the register to be used for PIC addressing") } \
507 }
508
509 struct arm_cpu_select
510 {
511 const char * string;
512 const char * name;
513 const struct processors * processors;
514 };
515
516 /* This is a magic array. If the user specifies a command line switch
517 which matches one of the entries in TARGET_OPTIONS then the corresponding
518 string pointer will be set to the value specified by the user. */
519 extern struct arm_cpu_select arm_select[];
520
521 enum prog_mode_type
522 {
523 prog_mode26,
524 prog_mode32
525 };
526
527 /* Recast the program mode class to be the prog_mode attribute */
528 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
529
530 extern enum prog_mode_type arm_prgmode;
531
532 /* What sort of floating point unit do we have? Hardware or software.
533 If software, is it issue 2 or issue 3? */
534 enum floating_point_type
535 {
536 FP_HARD,
537 FP_SOFT2,
538 FP_SOFT3
539 };
540
541 /* Recast the floating point class to be the floating point attribute. */
542 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
543
544 /* What type of floating point to tune for */
545 extern enum floating_point_type arm_fpu;
546
547 /* What type of floating point instructions are available */
548 extern enum floating_point_type arm_fpu_arch;
549
550 /* Default floating point architecture. Override in sub-target if
551 necessary. */
552 #define FP_DEFAULT FP_SOFT2
553
554 /* Nonzero if the processor has a fast multiply insn, and one that does
555 a 64-bit multiply of two 32-bit values. */
556 extern int arm_fast_multiply;
557
558 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
559 extern int arm_arch4;
560
561 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
562 extern int arm_arch5;
563
564 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
565 extern int arm_arch5e;
566
567 /* Nonzero if this chip can benefit from load scheduling. */
568 extern int arm_ld_sched;
569
570 /* Nonzero if generating thumb code. */
571 extern int thumb_code;
572
573 /* Nonzero if this chip is a StrongARM. */
574 extern int arm_is_strong;
575
576 /* Nonzero if this chip is an XScale. */
577 extern int arm_is_xscale;
578
579 /* Nonzero if this chip is a an ARM6 or an ARM7. */
580 extern int arm_is_6_or_7;
581
582 #ifndef TARGET_DEFAULT
583 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
584 #endif
585
586 /* The frame pointer register used in gcc has nothing to do with debugging;
587 that is controlled by the APCS-FRAME option. */
588 #define CAN_DEBUG_WITHOUT_FP
589
590 #define TARGET_MEM_FUNCTIONS 1
591
592 #define OVERRIDE_OPTIONS arm_override_options ()
593
594 /* Nonzero if PIC code requires explicit qualifiers to generate
595 PLT and GOT relocs rather than the assembler doing so implicitly.
596 Subtargets can override these if required. */
597 #ifndef NEED_GOT_RELOC
598 #define NEED_GOT_RELOC 0
599 #endif
600 #ifndef NEED_PLT_RELOC
601 #define NEED_PLT_RELOC 0
602 #endif
603
604 /* Nonzero if we need to refer to the GOT with a PC-relative
605 offset. In other words, generate
606
607 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
608
609 rather than
610
611 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
612
613 The default is true, which matches NetBSD. Subtargets can
614 override this if required. */
615 #ifndef GOT_PCREL
616 #define GOT_PCREL 1
617 #endif
618 \f
619 /* Target machine storage Layout. */
620
621
622 /* Define this macro if it is advisable to hold scalars in registers
623 in a wider mode than that declared by the program. In such cases,
624 the value is constrained to be within the bounds of the declared
625 type, but kept valid in the wider mode. The signedness of the
626 extension may differ from that of the type. */
627
628 /* It is far faster to zero extend chars than to sign extend them */
629
630 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
631 if (GET_MODE_CLASS (MODE) == MODE_INT \
632 && GET_MODE_SIZE (MODE) < 4) \
633 { \
634 if (MODE == QImode) \
635 UNSIGNEDP = 1; \
636 else if (MODE == HImode) \
637 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
638 (MODE) = SImode; \
639 }
640
641 /* Define this macro if the promotion described by `PROMOTE_MODE'
642 should also be done for outgoing function arguments. */
643 /* This is required to ensure that push insns always push a word. */
644 #define PROMOTE_FUNCTION_ARGS
645
646 /* Define for XFmode extended real floating point support.
647 This will automatically cause REAL_ARITHMETIC to be defined. */
648 /* For the ARM:
649 I think I have added all the code to make this work. Unfortunately,
650 early releases of the floating point emulation code on RISCiX used a
651 different format for extended precision numbers. On my RISCiX box there
652 is a bug somewhere which causes the machine to lock up when running enquire
653 with long doubles. There is the additional aspect that Norcroft C
654 treats long doubles as doubles and we ought to remain compatible.
655 Perhaps someone with an FPA coprocessor and not running RISCiX would like
656 to try this someday. */
657 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
658
659 /* Disable XFmode patterns in md file */
660 #define ENABLE_XF_PATTERNS 0
661
662 /* Define if you don't want extended real, but do want to use the
663 software floating point emulator for REAL_ARITHMETIC and
664 decimal <-> binary conversion. */
665 /* See comment above */
666 #define REAL_ARITHMETIC
667
668 /* Define this if most significant bit is lowest numbered
669 in instructions that operate on numbered bit-fields. */
670 #define BITS_BIG_ENDIAN 0
671
672 /* Define this if most significant byte of a word is the lowest numbered.
673 Most ARM processors are run in little endian mode, so that is the default.
674 If you want to have it run-time selectable, change the definition in a
675 cover file to be TARGET_BIG_ENDIAN. */
676 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
677
678 /* Define this if most significant word of a multiword number is the lowest
679 numbered.
680 This is always false, even when in big-endian mode. */
681 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
682
683 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
684 on processor pre-defineds when compiling libgcc2.c. */
685 #if defined(__ARMEB__) && !defined(__ARMWEL__)
686 #define LIBGCC2_WORDS_BIG_ENDIAN 1
687 #else
688 #define LIBGCC2_WORDS_BIG_ENDIAN 0
689 #endif
690
691 /* Define this if most significant word of doubles is the lowest numbered.
692 This is always true, even when in little-endian mode. */
693 #define FLOAT_WORDS_BIG_ENDIAN 1
694
695 /* Number of bits in an addressable storage unit */
696 #define BITS_PER_UNIT 8
697
698 #define BITS_PER_WORD 32
699
700 #define UNITS_PER_WORD 4
701
702 #define POINTER_SIZE 32
703
704 #define PARM_BOUNDARY 32
705
706 #define STACK_BOUNDARY 32
707
708 #define FUNCTION_BOUNDARY 32
709
710 /* The lowest bit is used to indicate Thumb-mode functions, so the
711 vbit must go into the delta field of pointers to member
712 functions. */
713 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
714
715 #define EMPTY_FIELD_BOUNDARY 32
716
717 #define BIGGEST_ALIGNMENT 32
718
719 /* Make strings word-aligned so strcpy from constants will be faster. */
720 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
721
722 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
723 ((TREE_CODE (EXP) == STRING_CST \
724 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
725 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
726
727 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
728 value set in previous versions of this toolchain was 8, which produces more
729 compact structures. The command line option -mstructure_size_boundary=<n>
730 can be used to change this value. For compatability with the ARM SDK
731 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
732 0020D) page 2-20 says "Structures are aligned on word boundaries". */
733 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
734 extern int arm_structure_size_boundary;
735
736 /* This is the value used to initialise arm_structure_size_boundary. If a
737 particular arm target wants to change the default value it should change
738 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
739 for an example of this. */
740 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
741 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
742 #endif
743
744 /* Used when parsing command line option -mstructure_size_boundary. */
745 extern const char * structure_size_string;
746
747 /* Non-zero if move instructions will actually fail to work
748 when given unaligned data. */
749 #define STRICT_ALIGNMENT 1
750
751 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
752
753 \f
754 /* Standard register usage. */
755
756 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
757 (S - saved over call).
758
759 r0 * argument word/integer result
760 r1-r3 argument word
761
762 r4-r8 S register variable
763 r9 S (rfp) register variable (real frame pointer)
764
765 r10 F S (sl) stack limit (used by -mapcs-stack-check)
766 r11 F S (fp) argument pointer
767 r12 (ip) temp workspace
768 r13 F S (sp) lower end of current stack frame
769 r14 (lr) link address/workspace
770 r15 F (pc) program counter
771
772 f0 floating point result
773 f1-f3 floating point scratch
774
775 f4-f7 S floating point variable
776
777 cc This is NOT a real register, but is used internally
778 to represent things that use or set the condition
779 codes.
780 sfp This isn't either. It is used during rtl generation
781 since the offset between the frame pointer and the
782 auto's isn't known until after register allocation.
783 afp Nor this, we only need this because of non-local
784 goto. Without it fp appears to be used and the
785 elimination code won't get rid of sfp. It tracks
786 fp exactly at all times.
787
788 *: See CONDITIONAL_REGISTER_USAGE */
789
790 /* The stack backtrace structure is as follows:
791 fp points to here: | save code pointer | [fp]
792 | return link value | [fp, #-4]
793 | return sp value | [fp, #-8]
794 | return fp value | [fp, #-12]
795 [| saved r10 value |]
796 [| saved r9 value |]
797 [| saved r8 value |]
798 [| saved r7 value |]
799 [| saved r6 value |]
800 [| saved r5 value |]
801 [| saved r4 value |]
802 [| saved r3 value |]
803 [| saved r2 value |]
804 [| saved r1 value |]
805 [| saved r0 value |]
806 [| saved f7 value |] three words
807 [| saved f6 value |] three words
808 [| saved f5 value |] three words
809 [| saved f4 value |] three words
810 r0-r3 are not normally saved in a C function. */
811
812 /* 1 for registers that have pervasive standard uses
813 and are not available for the register allocator. */
814 #define FIXED_REGISTERS \
815 { \
816 0,0,0,0,0,0,0,0, \
817 0,0,0,0,0,1,0,1, \
818 0,0,0,0,0,0,0,0, \
819 1,1,1 \
820 }
821
822 /* 1 for registers not available across function calls.
823 These must include the FIXED_REGISTERS and also any
824 registers that can be used without being saved.
825 The latter must include the registers where values are returned
826 and the register where structure-value addresses are passed.
827 Aside from that, you can include as many other registers as you like.
828 The CC is not preserved over function calls on the ARM 6, so it is
829 easier to assume this for all. SFP is preserved, since FP is. */
830 #define CALL_USED_REGISTERS \
831 { \
832 1,1,1,1,0,0,0,0, \
833 0,0,0,0,1,1,1,1, \
834 1,1,1,1,0,0,0,0, \
835 1,1,1 \
836 }
837
838 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
839 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
840 #endif
841
842 #define CONDITIONAL_REGISTER_USAGE \
843 { \
844 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
845 { \
846 int regno; \
847 for (regno = FIRST_ARM_FP_REGNUM; \
848 regno <= LAST_ARM_FP_REGNUM; ++regno) \
849 fixed_regs[regno] = call_used_regs[regno] = 1; \
850 } \
851 if (flag_pic) \
852 { \
853 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
854 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
855 } \
856 else if (TARGET_APCS_STACK) \
857 { \
858 fixed_regs[10] = 1; \
859 call_used_regs[10] = 1; \
860 } \
861 if (TARGET_APCS_FRAME) \
862 { \
863 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
864 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
865 } \
866 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
867 }
868
869 /* These are a couple of extensions to the formats accecpted
870 by asm_fprintf:
871 %@ prints out ASM_COMMENT_START
872 %r prints out REGISTER_PREFIX reg_names[arg] */
873 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
874 case '@': \
875 fputs (ASM_COMMENT_START, FILE); \
876 break; \
877 \
878 case 'r': \
879 fputs (REGISTER_PREFIX, FILE); \
880 fputs (reg_names [va_arg (ARGS, int)], FILE); \
881 break;
882
883 /* Round X up to the nearest word. */
884 #define ROUND_UP(X) (((X) + 3) & ~3)
885
886 /* Convert fron bytes to ints. */
887 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
888
889 /* The number of (integer) registers required to hold a quantity of type MODE. */
890 #define NUM_REGS(MODE) \
891 NUM_INTS (GET_MODE_SIZE (MODE))
892
893 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
894 #define NUM_REGS2(MODE, TYPE) \
895 NUM_INTS ((MODE) == BLKmode ? \
896 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
897
898 /* The number of (integer) argument register available. */
899 #define NUM_ARG_REGS 4
900
901 /* Return the regiser number of the N'th (integer) argument. */
902 #define ARG_REGISTER(N) (N - 1)
903
904 /* RTX for structure returns. NULL means use a hidden first argument. */
905 #define STRUCT_VALUE 0
906
907 /* Specify the registers used for certain standard purposes.
908 The values of these macros are register numbers. */
909
910 /* The number of the last argument register. */
911 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
912
913 /* The number of the last "lo" register (thumb). */
914 #define LAST_LO_REGNUM 7
915
916 /* The register that holds the return address in exception handlers. */
917 #define EXCEPTION_LR_REGNUM 2
918
919 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
920 as an invisible last argument (possible since varargs don't exist in
921 Pascal), so the following is not true. */
922 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
923
924 /* Define this to be where the real frame pointer is if it is not possible to
925 work out the offset between the frame pointer and the automatic variables
926 until after register allocation has taken place. FRAME_POINTER_REGNUM
927 should point to a special register that we will make sure is eliminated.
928
929 For the Thumb we have another problem. The TPCS defines the frame pointer
930 as r11, and GCC belives that it is always possible to use the frame pointer
931 as base register for addressing purposes. (See comments in
932 find_reloads_address()). But - the Thumb does not allow high registers,
933 including r11, to be used as base address registers. Hence our problem.
934
935 The solution used here, and in the old thumb port is to use r7 instead of
936 r11 as the hard frame pointer and to have special code to generate
937 backtrace structures on the stack (if required to do so via a command line
938 option) using r11. This is the only 'user visable' use of r11 as a frame
939 pointer. */
940 #define ARM_HARD_FRAME_POINTER_REGNUM 11
941 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
942
943 #define HARD_FRAME_POINTER_REGNUM \
944 (TARGET_ARM \
945 ? ARM_HARD_FRAME_POINTER_REGNUM \
946 : THUMB_HARD_FRAME_POINTER_REGNUM)
947
948 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
949
950 /* Register to use for pushing function arguments. */
951 #define STACK_POINTER_REGNUM SP_REGNUM
952
953 /* ARM floating pointer registers. */
954 #define FIRST_ARM_FP_REGNUM 16
955 #define LAST_ARM_FP_REGNUM 23
956
957 /* Base register for access to local variables of the function. */
958 #define FRAME_POINTER_REGNUM 25
959
960 /* Base register for access to arguments of the function. */
961 #define ARG_POINTER_REGNUM 26
962
963 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
964 #define FIRST_PSEUDO_REGISTER 27
965
966 /* Value should be nonzero if functions must have frame pointers.
967 Zero means the frame pointer need not be set up (and parms may be accessed
968 via the stack pointer) in functions that seem suitable.
969 If we have to have a frame pointer we might as well make use of it.
970 APCS says that the frame pointer does not need to be pushed in leaf
971 functions, or simple tail call functions. */
972 #define FRAME_POINTER_REQUIRED \
973 (current_function_has_nonlocal_label \
974 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
975
976 /* Return number of consecutive hard regs needed starting at reg REGNO
977 to hold something of mode MODE.
978 This is ordinarily the length in words of a value of mode MODE
979 but can be less for certain modes in special long registers.
980
981 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
982 mode. */
983 #define HARD_REGNO_NREGS(REGNO, MODE) \
984 ((TARGET_ARM \
985 && REGNO >= FIRST_ARM_FP_REGNUM \
986 && REGNO != FRAME_POINTER_REGNUM \
987 && REGNO != ARG_POINTER_REGNUM) \
988 ? 1 : NUM_REGS (MODE))
989
990 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
991 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
992 regs holding FP.
993 For the Thumb we only allow values bigger than SImode in registers 0 - 6,
994 so that there is always a second lo register available to hold the upper
995 part of the value. Probably we ought to ensure that the register is the
996 start of an even numbered register pair. */
997 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
998 (TARGET_ARM ? \
999 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1000 ( REGNO <= LAST_ARM_REGNUM \
1001 || REGNO == FRAME_POINTER_REGNUM \
1002 || REGNO == ARG_POINTER_REGNUM \
1003 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1004 : \
1005 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1006 (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM)))
1007
1008 /* Value is 1 if it is a good idea to tie two pseudo registers
1009 when one has mode MODE1 and one has mode MODE2.
1010 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1011 for any hard reg, then this must be 0 for correct output. */
1012 #define MODES_TIEABLE_P(MODE1, MODE2) \
1013 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1014
1015 /* The order in which register should be allocated. It is good to use ip
1016 since no saving is required (though calls clobber it) and it never contains
1017 function parameters. It is quite good to use lr since other calls may
1018 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1019 least likely to contain a function parameter; in addition results are
1020 returned in r0. */
1021 #define REG_ALLOC_ORDER \
1022 { \
1023 3, 2, 1, 0, 12, 14, 4, 5, \
1024 6, 7, 8, 10, 9, 11, 13, 15, \
1025 16, 17, 18, 19, 20, 21, 22, 23, \
1026 24, 25, 26 \
1027 }
1028 \f
1029 /* Register and constant classes. */
1030
1031 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1032 Now that the Thumb is involved it has become more compilcated. */
1033 enum reg_class
1034 {
1035 NO_REGS,
1036 FPU_REGS,
1037 LO_REGS,
1038 STACK_REG,
1039 BASE_REGS,
1040 HI_REGS,
1041 CC_REG,
1042 GENERAL_REGS,
1043 ALL_REGS,
1044 LIM_REG_CLASSES
1045 };
1046
1047 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1048
1049 /* Give names of register classes as strings for dump file. */
1050 #define REG_CLASS_NAMES \
1051 { \
1052 "NO_REGS", \
1053 "FPU_REGS", \
1054 "LO_REGS", \
1055 "STACK_REG", \
1056 "BASE_REGS", \
1057 "HI_REGS", \
1058 "CC_REG", \
1059 "GENERAL_REGS", \
1060 "ALL_REGS", \
1061 }
1062
1063 /* Define which registers fit in which classes.
1064 This is an initializer for a vector of HARD_REG_SET
1065 of length N_REG_CLASSES. */
1066 #define REG_CLASS_CONTENTS \
1067 { \
1068 { 0x0000000 }, /* NO_REGS */ \
1069 { 0x0FF0000 }, /* FPU_REGS */ \
1070 { 0x00000FF }, /* LO_REGS */ \
1071 { 0x0002000 }, /* STACK_REG */ \
1072 { 0x00020FF }, /* BASE_REGS */ \
1073 { 0x000FF00 }, /* HI_REGS */ \
1074 { 0x1000000 }, /* CC_REG */ \
1075 { 0x200FFFF }, /* GENERAL_REGS */ \
1076 { 0x2FFFFFF } /* ALL_REGS */ \
1077 }
1078
1079 /* The same information, inverted:
1080 Return the class number of the smallest class containing
1081 reg number REGNO. This could be a conditional expression
1082 or could index an array. */
1083 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1084
1085 /* The class value for index registers, and the one for base regs. */
1086 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1087 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1088
1089 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1090 registers explicitly used in the rtl to be used as spill registers
1091 but prevents the compiler from extending the lifetime of these
1092 registers. */
1093 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1094
1095 /* Get reg_class from a letter such as appears in the machine description.
1096 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1097 ARM, but several more letters for the Thumb. */
1098 #define REG_CLASS_FROM_LETTER(C) \
1099 ( (C) == 'f' ? FPU_REGS \
1100 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1101 : TARGET_ARM ? NO_REGS \
1102 : (C) == 'h' ? HI_REGS \
1103 : (C) == 'b' ? BASE_REGS \
1104 : (C) == 'k' ? STACK_REG \
1105 : (C) == 'c' ? CC_REG \
1106 : NO_REGS)
1107
1108 /* The letters I, J, K, L and M in a register constraint string
1109 can be used to stand for particular ranges of immediate operands.
1110 This macro defines what the ranges are.
1111 C is the letter, and VALUE is a constant value.
1112 Return 1 if VALUE is in the range specified by C.
1113 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1114 J: valid indexing constants.
1115 K: ~value ok in rhs argument of data operand.
1116 L: -value ok in rhs argument of data operand.
1117 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1118 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1119 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1120 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1121 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1122 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1123 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1124 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1125 : 0)
1126
1127 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1128 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1129 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1130 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1131 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1132 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1133 && ((VAL) & 3) == 0) : \
1134 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1135 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1136 : 0)
1137
1138 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1139 (TARGET_ARM ? \
1140 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1141
1142 /* Constant letter 'G' for the FPU immediate constants.
1143 'H' means the same constant negated. */
1144 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1145 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1146 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1147
1148 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1149 (TARGET_ARM ? \
1150 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1151
1152 /* For the ARM, `Q' means that this is a memory operand that is just
1153 an offset from a register.
1154 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1155 address. This means that the symbol is in the text segment and can be
1156 accessed without using a load. */
1157
1158 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1159 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1160 (C) == 'R' ? (GET_CODE (OP) == MEM \
1161 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1162 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1163 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1164 : 0)
1165
1166 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1167 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1168 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1169
1170 #define EXTRA_CONSTRAINT(X, C) \
1171 (TARGET_ARM ? \
1172 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1173
1174 /* Given an rtx X being reloaded into a reg required to be
1175 in class CLASS, return the class of reg to actually use.
1176 In general this is just CLASS, but for the Thumb we prefer
1177 a LO_REGS class or a subset. */
1178 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1179 (TARGET_ARM ? (CLASS) : \
1180 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1181
1182 /* Must leave BASE_REGS reloads alone */
1183 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1184 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1185 ? ((true_regnum (X) == -1 ? LO_REGS \
1186 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1187 : NO_REGS)) \
1188 : NO_REGS)
1189
1190 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1191 ((CLASS) != LO_REGS \
1192 ? ((true_regnum (X) == -1 ? LO_REGS \
1193 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1194 : NO_REGS)) \
1195 : NO_REGS)
1196
1197 /* Return the register class of a scratch register needed to copy IN into
1198 or out of a register in CLASS in MODE. If it can be done directly,
1199 NO_REGS is returned. */
1200 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1201 (TARGET_ARM ? \
1202 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1203 ? GENERAL_REGS : NO_REGS) \
1204 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1205
1206 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1207 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1208 (TARGET_ARM ? \
1209 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1210 && (GET_CODE (X) == MEM \
1211 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1212 && true_regnum (X) == -1))) \
1213 ? GENERAL_REGS : NO_REGS) \
1214 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1215
1216 /* Try a machine-dependent way of reloading an illegitimate address
1217 operand. If we find one, push the reload and jump to WIN. This
1218 macro is used in only one place: `find_reloads_address' in reload.c.
1219
1220 For the ARM, we wish to handle large displacements off a base
1221 register by splitting the addend across a MOV and the mem insn.
1222 This can cut the number of reloads needed. */
1223 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1224 do \
1225 { \
1226 if (GET_CODE (X) == PLUS \
1227 && GET_CODE (XEXP (X, 0)) == REG \
1228 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1229 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1230 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1231 { \
1232 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1233 HOST_WIDE_INT low, high; \
1234 \
1235 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1236 low = ((val & 0xf) ^ 0x8) - 0x8; \
1237 else if (MODE == SImode \
1238 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1239 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1240 /* Need to be careful, -4096 is not a valid offset. */ \
1241 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1242 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1243 /* Need to be careful, -256 is not a valid offset. */ \
1244 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1245 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1246 && TARGET_HARD_FLOAT) \
1247 /* Need to be careful, -1024 is not a valid offset. */ \
1248 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1249 else \
1250 break; \
1251 \
1252 high = ((((val - low) & HOST_UINT (0xffffffff)) \
1253 ^ HOST_UINT (0x80000000)) \
1254 - HOST_UINT (0x80000000)); \
1255 /* Check for overflow or zero */ \
1256 if (low == 0 || high == 0 || (high + low != val)) \
1257 break; \
1258 \
1259 /* Reload the high part into a base reg; leave the low part \
1260 in the mem. */ \
1261 X = gen_rtx_PLUS (GET_MODE (X), \
1262 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1263 GEN_INT (high)), \
1264 GEN_INT (low)); \
1265 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1266 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1267 OPNUM, TYPE); \
1268 goto WIN; \
1269 } \
1270 } \
1271 while (0)
1272
1273 /* ??? If an HImode FP+large_offset address is converted to an HImode
1274 SP+large_offset address, then reload won't know how to fix it. It sees
1275 only that SP isn't valid for HImode, and so reloads the SP into an index
1276 register, but the resulting address is still invalid because the offset
1277 is too big. We fix it here instead by reloading the entire address. */
1278 /* We could probably achieve better results by defining PROMOTE_MODE to help
1279 cope with the variances between the Thumb's signed and unsigned byte and
1280 halfword load instructions. */
1281 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1282 { \
1283 if (GET_CODE (X) == PLUS \
1284 && GET_MODE_SIZE (MODE) < 4 \
1285 && GET_CODE (XEXP (X, 0)) == REG \
1286 && XEXP (X, 0) == stack_pointer_rtx \
1287 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1288 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1289 { \
1290 rtx orig_X = X; \
1291 X = copy_rtx (X); \
1292 push_reload (orig_X, NULL_RTX, &X, NULL, \
1293 BASE_REG_CLASS, \
1294 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1295 goto WIN; \
1296 } \
1297 }
1298
1299 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1300 if (TARGET_ARM) \
1301 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1302 else \
1303 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1304
1305 /* Return the maximum number of consecutive registers
1306 needed to represent mode MODE in a register of class CLASS.
1307 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1308 #define CLASS_MAX_NREGS(CLASS, MODE) \
1309 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1310
1311 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1312 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1313 (TARGET_ARM ? \
1314 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1315 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1316 : \
1317 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1318 \f
1319 /* Stack layout; function entry, exit and calling. */
1320
1321 /* Define this if pushing a word on the stack
1322 makes the stack pointer a smaller address. */
1323 #define STACK_GROWS_DOWNWARD 1
1324
1325 /* Define this if the nominal address of the stack frame
1326 is at the high-address end of the local variables;
1327 that is, each additional local variable allocated
1328 goes at a more negative offset in the frame. */
1329 #define FRAME_GROWS_DOWNWARD 1
1330
1331 /* Offset within stack frame to start allocating local variables at.
1332 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1333 first local allocated. Otherwise, it is the offset to the BEGINNING
1334 of the first local allocated. */
1335 #define STARTING_FRAME_OFFSET 0
1336
1337 /* If we generate an insn to push BYTES bytes,
1338 this says how many the stack pointer really advances by. */
1339 /* The push insns do not do this rounding implicitly.
1340 So don't define this. */
1341 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1342
1343 /* Define this if the maximum size of all the outgoing args is to be
1344 accumulated and pushed during the prologue. The amount can be
1345 found in the variable current_function_outgoing_args_size. */
1346 #define ACCUMULATE_OUTGOING_ARGS 1
1347
1348 /* Offset of first parameter from the argument pointer register value. */
1349 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1350
1351 /* Value is the number of byte of arguments automatically
1352 popped when returning from a subroutine call.
1353 FUNDECL is the declaration node of the function (as a tree),
1354 FUNTYPE is the data type of the function (as a tree),
1355 or for a library call it is an identifier node for the subroutine name.
1356 SIZE is the number of bytes of arguments passed on the stack.
1357
1358 On the ARM, the caller does not pop any of its arguments that were passed
1359 on the stack. */
1360 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1361
1362 /* Define how to find the value returned by a library function
1363 assuming the value has mode MODE. */
1364 #define LIBCALL_VALUE(MODE) \
1365 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1366 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1367 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1368
1369 /* Define how to find the value returned by a function.
1370 VALTYPE is the data type of the value (as a tree).
1371 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1372 otherwise, FUNC is 0. */
1373 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1374 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1375
1376 /* 1 if N is a possible register number for a function value.
1377 On the ARM, only r0 and f0 can return results. */
1378 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1379 ((REGNO) == ARG_REGISTER (1) \
1380 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1381
1382 /* How large values are returned */
1383 /* A C expression which can inhibit the returning of certain function values
1384 in registers, based on the type of value. */
1385 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1386
1387 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1388 values must be in memory. On the ARM, they need only do so if larger
1389 than a word, or if they contain elements offset from zero in the struct. */
1390 #define DEFAULT_PCC_STRUCT_RETURN 0
1391
1392 /* Flags for the call/call_value rtl operations set up by function_arg. */
1393 #define CALL_NORMAL 0x00000000 /* No special processing. */
1394 #define CALL_LONG 0x00000001 /* Always call indirect. */
1395 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1396
1397 /* These bits describe the different types of function supported
1398 by the ARM backend. They are exclusive. ie a function cannot be both a
1399 normal function and an interworked function, for example. Knowing the
1400 type of a function is important for determining its prologue and
1401 epilogue sequences.
1402 Note value 7 is currently unassigned. Also note that the interrupt
1403 function types all have bit 2 set, so that they can be tested for easily.
1404 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1405 machine_function structure is initialised (to zero) func_type will
1406 default to unknown. This will force the first use of arm_current_func_type
1407 to call arm_compute_func_type. */
1408 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1409 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1410 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1411 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1412 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1413 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1414 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1415
1416 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1417
1418 /* In addition functions can have several type modifiers,
1419 outlined by these bit masks: */
1420 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1421 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1422 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1423 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1424
1425 /* Some macros to test these flags. */
1426 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1427 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1428 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1429 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1430 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1431
1432 /* A C structure for machine-specific, per-function data.
1433 This is added to the cfun structure. */
1434 typedef struct machine_function
1435 {
1436 /* Additionsl stack adjustment in __builtin_eh_throw. */
1437 struct rtx_def *eh_epilogue_sp_ofs;
1438 /* Records if LR has to be saved for far jumps. */
1439 int far_jump_used;
1440 /* Records if ARG_POINTER was ever live. */
1441 int arg_pointer_live;
1442 /* Records if the save of LR has been eliminated. */
1443 int lr_save_eliminated;
1444 /* Records the type of the current function. */
1445 unsigned long func_type;
1446 }
1447 machine_function;
1448
1449 /* A C type for declaring a variable that is used as the first argument of
1450 `FUNCTION_ARG' and other related values. For some target machines, the
1451 type `int' suffices and can hold the number of bytes of argument so far. */
1452 typedef struct
1453 {
1454 /* This is the number of registers of arguments scanned so far. */
1455 int nregs;
1456 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1457 int call_cookie;
1458 } CUMULATIVE_ARGS;
1459
1460 /* Define where to put the arguments to a function.
1461 Value is zero to push the argument on the stack,
1462 or a hard register in which to store the argument.
1463
1464 MODE is the argument's machine mode.
1465 TYPE is the data type of the argument (as a tree).
1466 This is null for libcalls where that information may
1467 not be available.
1468 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1469 the preceding args and about the function being called.
1470 NAMED is nonzero if this argument is a named parameter
1471 (otherwise it is an extra parameter matching an ellipsis).
1472
1473 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1474 other arguments are passed on the stack. If (NAMED == 0) (which happens
1475 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1476 passed in the stack (function_prologue will indeed make it pass in the
1477 stack if necessary). */
1478 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1479 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1480
1481 /* For an arg passed partly in registers and partly in memory,
1482 this is the number of registers used.
1483 For args passed entirely in registers or entirely in memory, zero. */
1484 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1485 ( NUM_ARG_REGS > (CUM).nregs \
1486 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1487 ? NUM_ARG_REGS - (CUM).nregs : 0)
1488
1489 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1490 for a call to a function whose data type is FNTYPE.
1491 For a library call, FNTYPE is 0.
1492 On the ARM, the offset starts at 0. */
1493 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1494 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1495
1496 /* Update the data in CUM to advance over an argument
1497 of mode MODE and data type TYPE.
1498 (TYPE is null for libcalls where that information may not be available.) */
1499 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1500 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1501
1502 /* 1 if N is a possible register number for function argument passing.
1503 On the ARM, r0-r3 are used to pass args. */
1504 #define FUNCTION_ARG_REGNO_P(REGNO) \
1505 ((REGNO) >= 0 && (REGNO) <= 3)
1506
1507 \f
1508 /* Tail calling. */
1509
1510 /* A C expression that evaluates to true if it is ok to perform a sibling
1511 call to DECL. */
1512 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1513
1514 /* Perform any actions needed for a function that is receiving a variable
1515 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1516 of the current parameter. PRETEND_SIZE is a variable that should be set to
1517 the amount of stack that must be pushed by the prolog to pretend that our
1518 caller pushed it.
1519
1520 Normally, this macro will push all remaining incoming registers on the
1521 stack and set PRETEND_SIZE to the length of the registers pushed.
1522
1523 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1524 named arg and all anonymous args onto the stack.
1525 XXX I know the prologue shouldn't be pushing registers, but it is faster
1526 that way. */
1527 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1528 { \
1529 extern int current_function_anonymous_args; \
1530 current_function_anonymous_args = 1; \
1531 if ((CUM).nregs < NUM_ARG_REGS) \
1532 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1533 }
1534
1535 /* Generate assembly output for the start of a function. */
1536 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1537 do \
1538 { \
1539 if (TARGET_ARM) \
1540 output_arm_prologue (STREAM, SIZE); \
1541 else \
1542 output_thumb_prologue (STREAM); \
1543 } \
1544 while (0)
1545
1546 /* If your target environment doesn't prefix user functions with an
1547 underscore, you may wish to re-define this to prevent any conflicts.
1548 e.g. AOF may prefix mcount with an underscore. */
1549 #ifndef ARM_MCOUNT_NAME
1550 #define ARM_MCOUNT_NAME "*mcount"
1551 #endif
1552
1553 /* Call the function profiler with a given profile label. The Acorn
1554 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1555 On the ARM the full profile code will look like:
1556 .data
1557 LP1
1558 .word 0
1559 .text
1560 mov ip, lr
1561 bl mcount
1562 .word LP1
1563
1564 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1565 will output the .text section.
1566
1567 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1568 ``prof'' doesn't seem to mind about this! */
1569 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1570 { \
1571 char temp[20]; \
1572 rtx sym; \
1573 \
1574 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1575 IP_REGNUM, LR_REGNUM); \
1576 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1577 fputc ('\n', STREAM); \
1578 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1579 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1580 ASM_OUTPUT_INT (STREAM, sym); \
1581 }
1582
1583 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1584 { \
1585 fprintf (STREAM, "\tmov\\tip, lr\n"); \
1586 fprintf (STREAM, "\tbl\tmcount\n"); \
1587 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1588 }
1589
1590 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1591 if (TARGET_ARM) \
1592 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1593 else \
1594 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1595
1596 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1597 the stack pointer does not matter. The value is tested only in
1598 functions that have frame pointers.
1599 No definition is equivalent to always zero.
1600
1601 On the ARM, the function epilogue recovers the stack pointer from the
1602 frame. */
1603 #define EXIT_IGNORE_STACK 1
1604
1605 /* Generate the assembly code for function exit. */
1606 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1607 output_func_epilogue (SIZE)
1608
1609 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1610
1611 /* Determine if the epilogue should be output as RTL.
1612 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1613 #define USE_RETURN_INSN(ISCOND) \
1614 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1615
1616 /* Definitions for register eliminations.
1617
1618 This is an array of structures. Each structure initializes one pair
1619 of eliminable registers. The "from" register number is given first,
1620 followed by "to". Eliminations of the same "from" register are listed
1621 in order of preference.
1622
1623 We have two registers that can be eliminated on the ARM. First, the
1624 arg pointer register can often be eliminated in favor of the stack
1625 pointer register. Secondly, the pseudo frame pointer register can always
1626 be eliminated; it is replaced with either the stack or the real frame
1627 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1628 because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */
1629
1630 #define ELIMINABLE_REGS \
1631 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1632 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1633 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1634 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1635 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1636 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1637 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1638
1639 /* Given FROM and TO register numbers, say whether this elimination is
1640 allowed. Frame pointer elimination is automatically handled.
1641
1642 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1643 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1644 pointer, we must eliminate FRAME_POINTER_REGNUM into
1645 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1646 ARG_POINTER_REGNUM. */
1647 #define CAN_ELIMINATE(FROM, TO) \
1648 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1649 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1650 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1651 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1652 1)
1653
1654 /* Define the offset between two registers, one to be eliminated, and the
1655 other its replacement, at the start of a routine. */
1656 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1657 { \
1658 int volatile_func = IS_VOLATILE (arm_current_func_type ()); \
1659 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1660 { \
1661 if (! current_function_needs_context || ! frame_pointer_needed) \
1662 (OFFSET) = 0; \
1663 else \
1664 (OFFSET) = 4; \
1665 } \
1666 else if ((FROM) == FRAME_POINTER_REGNUM \
1667 && (TO) == STACK_POINTER_REGNUM) \
1668 (OFFSET) = current_function_outgoing_args_size \
1669 + ROUND_UP (get_frame_size ()); \
1670 else \
1671 { \
1672 int regno; \
1673 int offset = 12; \
1674 int saved_hard_reg = 0; \
1675 \
1676 if (! volatile_func) \
1677 { \
1678 for (regno = 0; regno <= 10; regno++) \
1679 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1680 saved_hard_reg = 1, offset += 4; \
1681 if (! TARGET_APCS_FRAME \
1682 && ! frame_pointer_needed \
1683 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \
1684 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \
1685 saved_hard_reg = 1, offset += 4; \
1686 /* PIC register is a fixed reg, so call_used_regs set. */ \
1687 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1688 saved_hard_reg = 1, offset += 4; \
1689 for (regno = FIRST_ARM_FP_REGNUM; \
1690 regno <= LAST_ARM_FP_REGNUM; regno++) \
1691 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1692 offset += 12; \
1693 } \
1694 if ((FROM) == FRAME_POINTER_REGNUM) \
1695 (OFFSET) = - offset; \
1696 else \
1697 { \
1698 if (! frame_pointer_needed) \
1699 offset -= 16; \
1700 if (! volatile_func \
1701 && (regs_ever_live[LR_REGNUM] /*|| saved_hard_reg */)) \
1702 offset += 4; \
1703 offset += current_function_outgoing_args_size; \
1704 (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \
1705 } \
1706 } \
1707 }
1708
1709 /* Note: This macro must match the code in thumb_function_prologue(). */
1710 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1711 { \
1712 (OFFSET) = 0; \
1713 if ((FROM) == ARG_POINTER_REGNUM) \
1714 { \
1715 int count_regs = 0; \
1716 int regno; \
1717 for (regno = 8; regno < 13; regno ++) \
1718 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1719 count_regs ++; \
1720 if (count_regs) \
1721 (OFFSET) += 4 * count_regs; \
1722 count_regs = 0; \
1723 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1724 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1725 count_regs ++; \
1726 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1727 (OFFSET) += 4 * (count_regs + 1); \
1728 if (TARGET_BACKTRACE) \
1729 { \
1730 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1731 (OFFSET) += 20; \
1732 else \
1733 (OFFSET) += 16; \
1734 } \
1735 } \
1736 if ((TO) == STACK_POINTER_REGNUM) \
1737 { \
1738 (OFFSET) += current_function_outgoing_args_size; \
1739 (OFFSET) += ROUND_UP (get_frame_size ()); \
1740 } \
1741 }
1742
1743 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1744 if (TARGET_ARM) \
1745 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \
1746 else \
1747 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1748
1749 /* Special case handling of the location of arguments passed on the stack. */
1750 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1751
1752 /* Initialize data used by insn expanders. This is called from insn_emit,
1753 once for every function before code is generated. */
1754 #define INIT_EXPANDERS arm_init_expanders ()
1755
1756 /* Output assembler code for a block containing the constant parts
1757 of a trampoline, leaving space for the variable parts.
1758
1759 On the ARM, (if r8 is the static chain regnum, and remembering that
1760 referencing pc adds an offset of 8) the trampoline looks like:
1761 ldr r8, [pc, #0]
1762 ldr pc, [pc]
1763 .word static chain value
1764 .word function's address
1765 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1766 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1767 { \
1768 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1769 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1770 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1771 PC_REGNUM, PC_REGNUM); \
1772 ASM_OUTPUT_INT (FILE, const0_rtx); \
1773 ASM_OUTPUT_INT (FILE, const0_rtx); \
1774 }
1775
1776 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1777 Why - because it is easier. This code will always be branched to via
1778 a BX instruction and since the compiler magically generates the address
1779 of the function the linker has no opportunity to ensure that the
1780 bottom bit is set. Thus the processor will be in ARM mode when it
1781 reaches this code. So we duplicate the ARM trampoline code and add
1782 a switch into Thumb mode as well. */
1783 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1784 { \
1785 fprintf (FILE, "\t.code 32\n"); \
1786 fprintf (FILE, ".Ltrampoline_start:\n"); \
1787 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1788 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1789 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1790 IP_REGNUM, PC_REGNUM); \
1791 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1792 IP_REGNUM, IP_REGNUM); \
1793 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1794 fprintf (FILE, "\t.word\t0\n"); \
1795 fprintf (FILE, "\t.word\t0\n"); \
1796 fprintf (FILE, "\t.code 16\n"); \
1797 }
1798
1799 #define TRAMPOLINE_TEMPLATE(FILE) \
1800 if (TARGET_ARM) \
1801 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1802 else \
1803 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1804
1805 /* Length in units of the trampoline for entering a nested function. */
1806 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1807
1808 /* Alignment required for a trampoline in units. */
1809 #define TRAMPOLINE_ALIGN 4
1810
1811 /* Emit RTL insns to initialize the variable parts of a trampoline.
1812 FNADDR is an RTX for the address of the function's pure code.
1813 CXT is an RTX for the static chain value for the function. */
1814 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1815 { \
1816 emit_move_insn \
1817 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1818 emit_move_insn \
1819 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1820 }
1821
1822 \f
1823 /* Addressing modes, and classification of registers for them. */
1824 #define HAVE_POST_INCREMENT 1
1825 #define HAVE_PRE_INCREMENT TARGET_ARM
1826 #define HAVE_POST_DECREMENT TARGET_ARM
1827 #define HAVE_PRE_DECREMENT TARGET_ARM
1828
1829 /* Macros to check register numbers against specific register classes. */
1830
1831 /* These assume that REGNO is a hard or pseudo reg number.
1832 They give nonzero only if REGNO is a hard reg of the suitable class
1833 or a pseudo reg currently allocated to a suitable hard reg.
1834 Since they use reg_renumber, they are safe only once reg_renumber
1835 has been allocated, which happens in local-alloc.c. */
1836 #define TEST_REGNO(R, TEST, VALUE) \
1837 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1838
1839 /* On the ARM, don't allow the pc to be used. */
1840 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1841 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1842 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1843 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1844
1845 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1846 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1847 || (GET_MODE_SIZE (MODE) >= 4 \
1848 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1849
1850 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1851 (TARGET_THUMB \
1852 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1853 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1854
1855 /* For ARM code, we don't care about the mode, but for Thumb, the index
1856 must be suitable for use in a QImode load. */
1857 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1858 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1859
1860 /* Maximum number of registers that can appear in a valid memory address.
1861 Shifts in addresses can't be by a register. */
1862 #define MAX_REGS_PER_ADDRESS 2
1863
1864 /* Recognize any constant value that is a valid address. */
1865 /* XXX We can address any constant, eventually... */
1866
1867 #ifdef AOF_ASSEMBLER
1868
1869 #define CONSTANT_ADDRESS_P(X) \
1870 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1871
1872 #else
1873
1874 #define CONSTANT_ADDRESS_P(X) \
1875 (GET_CODE (X) == SYMBOL_REF \
1876 && (CONSTANT_POOL_ADDRESS_P (X) \
1877 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1878
1879 #endif /* AOF_ASSEMBLER */
1880
1881 /* Nonzero if the constant value X is a legitimate general operand.
1882 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1883
1884 On the ARM, allow any integer (invalid ones are removed later by insn
1885 patterns), nice doubles and symbol_refs which refer to the function's
1886 constant pool XXX.
1887
1888 When generating pic allow anything. */
1889 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1890
1891 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1892 ( GET_CODE (X) == CONST_INT \
1893 || GET_CODE (X) == CONST_DOUBLE \
1894 || CONSTANT_ADDRESS_P (X))
1895
1896 #define LEGITIMATE_CONSTANT_P(X) \
1897 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1898
1899 /* Special characters prefixed to function names
1900 in order to encode attribute like information.
1901 Note, '@' and '*' have already been taken. */
1902 #define SHORT_CALL_FLAG_CHAR '^'
1903 #define LONG_CALL_FLAG_CHAR '#'
1904
1905 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1906 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1907
1908 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1909 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1910
1911 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1912 #define SUBTARGET_NAME_ENCODING_LENGTHS
1913 #endif
1914
1915 /* This is a C fragement for the inside of a switch statement.
1916 Each case label should return the number of characters to
1917 be stripped from the start of a function's name, if that
1918 name starts with the indicated character. */
1919 #define ARM_NAME_ENCODING_LENGTHS \
1920 case SHORT_CALL_FLAG_CHAR: return 1; \
1921 case LONG_CALL_FLAG_CHAR: return 1; \
1922 case '*': return 1; \
1923 SUBTARGET_NAME_ENCODING_LENGTHS
1924
1925 /* This has to be handled by a function because more than part of the
1926 ARM backend uses function name prefixes to encode attributes. */
1927 #undef STRIP_NAME_ENCODING
1928 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1929 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1930
1931 /* This is how to output a reference to a user-level label named NAME.
1932 `assemble_name' uses this. */
1933 #undef ASM_OUTPUT_LABELREF
1934 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1935 asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME))
1936
1937 /* If we are referencing a function that is weak then encode a long call
1938 flag in the function name, otherwise if the function is static or
1939 or known to be defined in this file then encode a short call flag.
1940 This macro is used inside the ENCODE_SECTION macro. */
1941 #define ARM_ENCODE_CALL_TYPE(decl) \
1942 if (TREE_CODE (decl) == FUNCTION_DECL) \
1943 { \
1944 if (DECL_WEAK (decl)) \
1945 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1946 else if (! TREE_PUBLIC (decl)) \
1947 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1948 } \
1949
1950 /* Symbols in the text segment can be accessed without indirecting via the
1951 constant pool; it may take an extra binary operation, but this is still
1952 faster than indirecting via memory. Don't do this when not optimizing,
1953 since we won't be calculating al of the offsets necessary to do this
1954 simplification. */
1955 /* This doesn't work with AOF syntax, since the string table may be in
1956 a different AREA. */
1957 #ifndef AOF_ASSEMBLER
1958 #define ENCODE_SECTION_INFO(decl) \
1959 { \
1960 if (optimize > 0 && TREE_CONSTANT (decl) \
1961 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1962 { \
1963 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1964 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1965 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1966 } \
1967 ARM_ENCODE_CALL_TYPE (decl) \
1968 }
1969 #else
1970 #define ENCODE_SECTION_INFO(decl) \
1971 { \
1972 ARM_ENCODE_CALL_TYPE (decl) \
1973 }
1974 #endif
1975
1976 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1977 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1978
1979 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1980 and check its validity for a certain class.
1981 We have two alternate definitions for each of them.
1982 The usual definition accepts all pseudo regs; the other rejects
1983 them unless they have been allocated suitable hard regs.
1984 The symbol REG_OK_STRICT causes the latter definition to be used. */
1985 #ifndef REG_OK_STRICT
1986
1987 #define ARM_REG_OK_FOR_BASE_P(X) \
1988 (REGNO (X) <= LAST_ARM_REGNUM \
1989 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1990 || REGNO (X) == FRAME_POINTER_REGNUM \
1991 || REGNO (X) == ARG_POINTER_REGNUM)
1992
1993 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1994 (REGNO (X) <= LAST_LO_REGNUM \
1995 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1996 || (GET_MODE_SIZE (MODE) >= 4 \
1997 && (REGNO (X) == STACK_POINTER_REGNUM \
1998 || (X) == hard_frame_pointer_rtx \
1999 || (X) == arg_pointer_rtx)))
2000
2001 #else /* REG_OK_STRICT */
2002
2003 #define ARM_REG_OK_FOR_BASE_P(X) \
2004 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2005
2006 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2007 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2008
2009 #endif /* REG_OK_STRICT */
2010
2011 /* Now define some helpers in terms of the above. */
2012
2013 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2014 (TARGET_THUMB \
2015 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2016 : ARM_REG_OK_FOR_BASE_P (X))
2017
2018 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2019
2020 /* For Thumb, a valid index register is anything that can be used in
2021 a byte load instruction. */
2022 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2023
2024 /* Nonzero if X is a hard reg that can be used as an index
2025 or if it is a pseudo reg. On the Thumb, the stack pointer
2026 is not suitable. */
2027 #define REG_OK_FOR_INDEX_P(X) \
2028 (TARGET_THUMB \
2029 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2030 : ARM_REG_OK_FOR_INDEX_P (X))
2031
2032 \f
2033 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2034 that is a valid memory address for an instruction.
2035 The MODE argument is the machine mode for the MEM expression
2036 that wants to use this address.
2037
2038 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
2039
2040 /* --------------------------------arm version----------------------------- */
2041 #define ARM_BASE_REGISTER_RTX_P(X) \
2042 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2043
2044 #define ARM_INDEX_REGISTER_RTX_P(X) \
2045 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2046
2047 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
2048 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2049 only be small constants. */
2050 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2051 do \
2052 { \
2053 HOST_WIDE_INT range; \
2054 enum rtx_code code = GET_CODE (INDEX); \
2055 \
2056 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2057 { \
2058 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2059 && INTVAL (INDEX) > -1024 \
2060 && (INTVAL (INDEX) & 3) == 0) \
2061 goto LABEL; \
2062 } \
2063 else \
2064 { \
2065 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2066 && GET_MODE_SIZE (MODE) <= 4) \
2067 goto LABEL; \
2068 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2069 && (! arm_arch4 || (MODE) != HImode)) \
2070 { \
2071 rtx xiop0 = XEXP (INDEX, 0); \
2072 rtx xiop1 = XEXP (INDEX, 1); \
2073 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2074 && power_of_two_operand (xiop1, SImode)) \
2075 goto LABEL; \
2076 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2077 && power_of_two_operand (xiop0, SImode)) \
2078 goto LABEL; \
2079 } \
2080 if (GET_MODE_SIZE (MODE) <= 4 \
2081 && (code == LSHIFTRT || code == ASHIFTRT \
2082 || code == ASHIFT || code == ROTATERT) \
2083 && (! arm_arch4 || (MODE) != HImode)) \
2084 { \
2085 rtx op = XEXP (INDEX, 1); \
2086 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2087 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2088 && INTVAL (op) <= 31) \
2089 goto LABEL; \
2090 } \
2091 /* NASTY: Since this limits the addressing of unsigned \
2092 byte loads. */ \
2093 range = ((MODE) == HImode || (MODE) == QImode) \
2094 ? (arm_arch4 ? 256 : 4095) : 4096; \
2095 if (code == CONST_INT && INTVAL (INDEX) < range \
2096 && INTVAL (INDEX) > -range) \
2097 goto LABEL; \
2098 } \
2099 } \
2100 while (0)
2101
2102 /* Jump to LABEL if X is a valid address RTX. This must take
2103 REG_OK_STRICT into account when deciding about valid registers.
2104
2105 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2106 floating SYMBOL_REF to the constant pool. Allow REG-only and
2107 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2108 forced though a static cell to ensure addressability. */
2109 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2110 { \
2111 if (ARM_BASE_REGISTER_RTX_P (X)) \
2112 goto LABEL; \
2113 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2114 && GET_CODE (XEXP (X, 0)) == REG \
2115 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2116 goto LABEL; \
2117 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2118 && (GET_CODE (X) == LABEL_REF \
2119 || (GET_CODE (X) == CONST \
2120 && GET_CODE (XEXP ((X), 0)) == PLUS \
2121 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2122 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2123 goto LABEL; \
2124 else if ((MODE) == TImode) \
2125 ; \
2126 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2127 { \
2128 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2129 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2130 { \
2131 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2132 if (val == 4 || val == -4 || val == -8) \
2133 goto LABEL; \
2134 } \
2135 } \
2136 else if (GET_CODE (X) == PLUS) \
2137 { \
2138 rtx xop0 = XEXP (X, 0); \
2139 rtx xop1 = XEXP (X, 1); \
2140 \
2141 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2142 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2143 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2144 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2145 } \
2146 /* Reload currently can't handle MINUS, so disable this for now */ \
2147 /* else if (GET_CODE (X) == MINUS) \
2148 { \
2149 rtx xop0 = XEXP (X,0); \
2150 rtx xop1 = XEXP (X,1); \
2151 \
2152 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2153 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2154 } */ \
2155 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2156 && GET_CODE (X) == SYMBOL_REF \
2157 && CONSTANT_POOL_ADDRESS_P (X) \
2158 && ! (flag_pic \
2159 && symbol_mentioned_p (get_pool_constant (X)))) \
2160 goto LABEL; \
2161 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2162 && (GET_MODE_SIZE (MODE) <= 4) \
2163 && GET_CODE (XEXP (X, 0)) == REG \
2164 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2165 goto LABEL; \
2166 }
2167
2168 /* ---------------------thumb version----------------------------------*/
2169 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2170 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2171 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2172 && ((VAL) & 1) == 0) \
2173 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2174 && ((VAL) & 3) == 0))
2175
2176 /* The AP may be eliminated to either the SP or the FP, so we use the
2177 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2178
2179 /* ??? Verify whether the above is the right approach. */
2180
2181 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2182 needs special handling also. */
2183
2184 /* ??? Look at how the mips16 port solves this problem. It probably uses
2185 better ways to solve some of these problems. */
2186
2187 /* Although it is not incorrect, we don't accept QImode and HImode
2188 addresses based on the frame pointer or arg pointer until the
2189 reload pass starts. This is so that eliminating such addresses
2190 into stack based ones won't produce impossible code. */
2191 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2192 { \
2193 /* ??? Not clear if this is right. Experiment. */ \
2194 if (GET_MODE_SIZE (MODE) < 4 \
2195 && ! (reload_in_progress || reload_completed) \
2196 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2197 || reg_mentioned_p (arg_pointer_rtx, X) \
2198 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2199 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2200 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2201 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2202 ; \
2203 /* Accept any base register. SP only in SImode or larger. */ \
2204 else if (GET_CODE (X) == REG \
2205 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2206 goto WIN; \
2207 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2208 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2209 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2210 goto WIN; \
2211 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2212 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2213 && (GET_CODE (X) == LABEL_REF \
2214 || (GET_CODE (X) == CONST \
2215 && GET_CODE (XEXP (X, 0)) == PLUS \
2216 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2217 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2218 goto WIN; \
2219 /* Post-inc indexing only supported for SImode and larger. */ \
2220 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2221 && GET_CODE (XEXP (X, 0)) == REG \
2222 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2223 goto WIN; \
2224 else if (GET_CODE (X) == PLUS) \
2225 { \
2226 /* REG+REG address can be any two index registers. */ \
2227 /* We disallow FRAME+REG addressing since we know that FRAME \
2228 will be replaced with STACK, and SP relative addressing only \
2229 permits SP+OFFSET. */ \
2230 if (GET_MODE_SIZE (MODE) <= 4 \
2231 && GET_CODE (XEXP (X, 0)) == REG \
2232 && GET_CODE (XEXP (X, 1)) == REG \
2233 && XEXP (X, 0) != frame_pointer_rtx \
2234 && XEXP (X, 1) != frame_pointer_rtx \
2235 && XEXP (X, 0) != virtual_stack_vars_rtx \
2236 && XEXP (X, 1) != virtual_stack_vars_rtx \
2237 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2238 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2239 goto WIN; \
2240 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2241 else if (GET_CODE (XEXP (X, 0)) == REG \
2242 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2243 || XEXP (X, 0) == arg_pointer_rtx) \
2244 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2245 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2246 goto WIN; \
2247 /* REG+const has 10 bit offset for SP, but only SImode and \
2248 larger is supported. */ \
2249 /* ??? Should probably check for DI/DFmode overflow here \
2250 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2251 else if (GET_CODE (XEXP (X, 0)) == REG \
2252 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2253 && GET_MODE_SIZE (MODE) >= 4 \
2254 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2255 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2256 + GET_MODE_SIZE (MODE)) <= 1024 \
2257 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2258 goto WIN; \
2259 else if (GET_CODE (XEXP (X, 0)) == REG \
2260 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2261 && GET_MODE_SIZE (MODE) >= 4 \
2262 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2263 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2264 goto WIN; \
2265 } \
2266 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2267 && GET_CODE (X) == SYMBOL_REF \
2268 && CONSTANT_POOL_ADDRESS_P (X) \
2269 && ! (flag_pic \
2270 && symbol_mentioned_p (get_pool_constant (X)))) \
2271 goto WIN; \
2272 }
2273
2274 /* ------------------------------------------------------------------- */
2275 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2276 if (TARGET_ARM) \
2277 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2278 else /* if (TARGET_THUMB) */ \
2279 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2280 /* ------------------------------------------------------------------- */
2281 \f
2282 /* Try machine-dependent ways of modifying an illegitimate address
2283 to be legitimate. If we find one, return the new, valid address.
2284 This macro is used in only one place: `memory_address' in explow.c.
2285
2286 OLDX is the address as it was before break_out_memory_refs was called.
2287 In some cases it is useful to look at this to decide what needs to be done.
2288
2289 MODE and WIN are passed so that this macro can use
2290 GO_IF_LEGITIMATE_ADDRESS.
2291
2292 It is always safe for this macro to do nothing. It exists to recognize
2293 opportunities to optimize the output.
2294
2295 On the ARM, try to convert [REG, #BIGCONST]
2296 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2297 where VALIDCONST == 0 in case of TImode. */
2298 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2299 { \
2300 if (GET_CODE (X) == PLUS) \
2301 { \
2302 rtx xop0 = XEXP (X, 0); \
2303 rtx xop1 = XEXP (X, 1); \
2304 \
2305 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2306 xop0 = force_reg (SImode, xop0); \
2307 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2308 xop1 = force_reg (SImode, xop1); \
2309 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2310 && GET_CODE (xop1) == CONST_INT) \
2311 { \
2312 HOST_WIDE_INT n, low_n; \
2313 rtx base_reg, val; \
2314 n = INTVAL (xop1); \
2315 \
2316 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2317 { \
2318 low_n = n & 0x0f; \
2319 n &= ~0x0f; \
2320 if (low_n > 4) \
2321 { \
2322 n += 16; \
2323 low_n -= 16; \
2324 } \
2325 } \
2326 else \
2327 { \
2328 low_n = ((MODE) == TImode ? 0 \
2329 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2330 n -= low_n; \
2331 } \
2332 base_reg = gen_reg_rtx (SImode); \
2333 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2334 GEN_INT (n)), NULL_RTX); \
2335 emit_move_insn (base_reg, val); \
2336 (X) = (low_n == 0 ? base_reg \
2337 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2338 } \
2339 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2340 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2341 } \
2342 else if (GET_CODE (X) == MINUS) \
2343 { \
2344 rtx xop0 = XEXP (X, 0); \
2345 rtx xop1 = XEXP (X, 1); \
2346 \
2347 if (CONSTANT_P (xop0)) \
2348 xop0 = force_reg (SImode, xop0); \
2349 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2350 xop1 = force_reg (SImode, xop1); \
2351 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2352 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2353 } \
2354 if (flag_pic) \
2355 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2356 if (memory_address_p (MODE, X)) \
2357 goto WIN; \
2358 }
2359
2360 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2361 if (flag_pic) \
2362 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2363
2364 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2365 if (TARGET_ARM) \
2366 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2367 else \
2368 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2369
2370 /* Go to LABEL if ADDR (a legitimate address expression)
2371 has an effect that depends on the machine mode it is used for. */
2372 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2373 { \
2374 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2375 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2376 goto LABEL; \
2377 }
2378
2379 /* Nothing helpful to do for the Thumb */
2380 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2381 if (TARGET_ARM) \
2382 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2383 \f
2384
2385 /* Specify the machine mode that this machine uses
2386 for the index in the tablejump instruction. */
2387 #define CASE_VECTOR_MODE Pmode
2388
2389 /* Define as C expression which evaluates to nonzero if the tablejump
2390 instruction expects the table to contain offsets from the address of the
2391 table.
2392 Do not define this if the table should contain absolute addresses. */
2393 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2394
2395 /* Specify the tree operation to be used to convert reals to integers. */
2396 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2397
2398 /* This is the kind of divide that is easiest to do in the general case. */
2399 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2400
2401 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2402 unsigned is probably best, but may break some code. */
2403 #ifndef DEFAULT_SIGNED_CHAR
2404 #define DEFAULT_SIGNED_CHAR 0
2405 #endif
2406
2407 /* Don't cse the address of the function being compiled. */
2408 #define NO_RECURSIVE_FUNCTION_CSE 1
2409
2410 /* Max number of bytes we can move from memory to memory
2411 in one reasonably fast instruction. */
2412 #define MOVE_MAX 4
2413
2414 #undef MOVE_RATIO
2415 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2416
2417 /* Define if operations between registers always perform the operation
2418 on the full register even if a narrower mode is specified. */
2419 #define WORD_REGISTER_OPERATIONS
2420
2421 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2422 will either zero-extend or sign-extend. The value of this macro should
2423 be the code that says which one of the two operations is implicitly
2424 done, NIL if none. */
2425 #define LOAD_EXTEND_OP(MODE) \
2426 (TARGET_THUMB ? ZERO_EXTEND : \
2427 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2428 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2429
2430 /* Define this if zero-extension is slow (more than one real instruction).
2431 On the ARM, it is more than one instruction only if not fetching from
2432 memory. */
2433 /* #define SLOW_ZERO_EXTEND */
2434
2435 /* Nonzero if access to memory by bytes is slow and undesirable. */
2436 #define SLOW_BYTE_ACCESS 0
2437
2438 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2439
2440 /* Immediate shift counts are truncated by the output routines (or was it
2441 the assembler?). Shift counts in a register are truncated by ARM. Note
2442 that the native compiler puts too large (> 32) immediate shift counts
2443 into a register and shifts by the register, letting the ARM decide what
2444 to do instead of doing that itself. */
2445 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2446 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2447 On the arm, Y in a register is used modulo 256 for the shift. Only for
2448 rotates is modulo 32 used. */
2449 /* #define SHIFT_COUNT_TRUNCATED 1 */
2450
2451 /* All integers have the same format so truncation is easy. */
2452 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2453
2454 /* Calling from registers is a massive pain. */
2455 #define NO_FUNCTION_CSE 1
2456
2457 /* Chars and shorts should be passed as ints. */
2458 #define PROMOTE_PROTOTYPES 1
2459
2460 /* The machine modes of pointers and functions */
2461 #define Pmode SImode
2462 #define FUNCTION_MODE Pmode
2463
2464 #define ARM_FRAME_RTX(X) \
2465 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2466 || (X) == arg_pointer_rtx)
2467
2468 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2469 return arm_rtx_costs (X, CODE, OUTER_CODE);
2470
2471 /* Moves to and from memory are quite expensive */
2472 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2473 (TARGET_ARM ? 10 : \
2474 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2475 * (CLASS == LO_REGS ? 1 : 2)))
2476
2477 /* All address computations that can be done are free, but rtx cost returns
2478 the same for practically all of them. So we weight the different types
2479 of address here in the order (most pref first):
2480 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2481 #define ARM_ADDRESS_COST(X) \
2482 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2483 || GET_CODE (X) == SYMBOL_REF) \
2484 ? 0 \
2485 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2486 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2487 ? 10 \
2488 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2489 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2490 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2491 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2492 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2493 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2494 ? 1 : 0)) \
2495 : 4)))))
2496
2497 #define THUMB_ADDRESS_COST(X) \
2498 ((GET_CODE (X) == REG \
2499 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2500 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2501 ? 1 : 2)
2502
2503 #define ADDRESS_COST(X) \
2504 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2505
2506 /* Try to generate sequences that don't involve branches, we can then use
2507 conditional instructions */
2508 #define BRANCH_COST \
2509 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2510
2511 /* A C statement to update the variable COST based on the relationship
2512 between INSN that is dependent on DEP through dependence LINK. */
2513 #define ADJUST_COST(INSN, LINK, DEP, COST) \
2514 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
2515 \f
2516 /* Position Independent Code. */
2517 /* We decide which register to use based on the compilation options and
2518 the assembler in use; this is more general than the APCS restriction of
2519 using sb (r9) all the time. */
2520 extern int arm_pic_register;
2521
2522 /* Used when parsing command line option -mpic-register=. */
2523 extern const char * arm_pic_register_string;
2524
2525 /* The register number of the register used to address a table of static
2526 data addresses in memory. */
2527 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2528
2529 #define FINALIZE_PIC arm_finalize_pic (1)
2530
2531 /* We can't directly access anything that contains a symbol,
2532 nor can we indirect via the constant pool. */
2533 #define LEGITIMATE_PIC_OPERAND_P(X) \
2534 ( ! symbol_mentioned_p (X) \
2535 && ! label_mentioned_p (X) \
2536 && (! CONSTANT_POOL_ADDRESS_P (X) \
2537 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2538 && ! label_mentioned_p (get_pool_constant (X)))))
2539
2540 /* We need to know when we are making a constant pool; this determines
2541 whether data needs to be in the GOT or can be referenced via a GOT
2542 offset. */
2543 extern int making_const_table;
2544 \f
2545 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2546 with arguments ARGS is a valid machine specific attribute for TYPE.
2547 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2548 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2549 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2550
2551 /* If defined, a C expression whose value is zero if the attributes on
2552 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2553 two if they are nearly compatible (which causes a warning to be
2554 generated). */
2555 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2556 (arm_comp_type_attributes (TYPE1, TYPE2))
2557
2558 /* If defined, a C statement that assigns default attributes to newly
2559 defined TYPE. */
2560 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
2561 arm_set_default_type_attributes (TYPE)
2562
2563 /* Handle pragmas for compatibility with Intel's compilers. */
2564 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2565 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2566 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2567 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2568 } while (0)
2569
2570 /* Condition code information. */
2571 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2572 return the mode to be used for the comparison.
2573 CCFPEmode should be used with floating inequalities,
2574 CCFPmode should be used with floating equalities.
2575 CC_NOOVmode should be used with SImode integer equalities.
2576 CC_Zmode should be used if only the Z flag is set correctly
2577 CCmode should be used otherwise. */
2578
2579 #define EXTRA_CC_MODES \
2580 CC(CC_NOOVmode, "CC_NOOV") \
2581 CC(CC_Zmode, "CC_Z") \
2582 CC(CC_SWPmode, "CC_SWP") \
2583 CC(CCFPmode, "CCFP") \
2584 CC(CCFPEmode, "CCFPE") \
2585 CC(CC_DNEmode, "CC_DNE") \
2586 CC(CC_DEQmode, "CC_DEQ") \
2587 CC(CC_DLEmode, "CC_DLE") \
2588 CC(CC_DLTmode, "CC_DLT") \
2589 CC(CC_DGEmode, "CC_DGE") \
2590 CC(CC_DGTmode, "CC_DGT") \
2591 CC(CC_DLEUmode, "CC_DLEU") \
2592 CC(CC_DLTUmode, "CC_DLTU") \
2593 CC(CC_DGEUmode, "CC_DGEU") \
2594 CC(CC_DGTUmode, "CC_DGTU") \
2595 CC(CC_Cmode, "CC_C")
2596
2597 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2598
2599 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2600
2601 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2602 do \
2603 { \
2604 if (GET_CODE (OP1) == CONST_INT \
2605 && ! (const_ok_for_arm (INTVAL (OP1)) \
2606 || (const_ok_for_arm (- INTVAL (OP1))))) \
2607 { \
2608 rtx const_op = OP1; \
2609 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2610 OP1 = const_op; \
2611 } \
2612 } \
2613 while (0)
2614
2615 #define STORE_FLAG_VALUE 1
2616
2617 \f
2618
2619 /* Gcc puts the pool in the wrong place for ARM, since we can only
2620 load addresses a limited distance around the pc. We do some
2621 special munging to move the constant pool values to the correct
2622 point in the code. */
2623 #define MACHINE_DEPENDENT_REORG(INSN) \
2624 arm_reorg (INSN); \
2625
2626 #undef ASM_APP_OFF
2627 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2628
2629 /* Output an internal label definition. */
2630 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2631 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2632 do \
2633 { \
2634 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2635 \
2636 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2637 && !strcmp (PREFIX, "L")) \
2638 { \
2639 arm_ccfsm_state = 0; \
2640 arm_target_insn = NULL; \
2641 } \
2642 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2643 ASM_OUTPUT_LABEL (STREAM, s); \
2644 } \
2645 while (0)
2646 #endif
2647
2648 /* Output a push or a pop instruction (only used when profiling). */
2649 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2650 if (TARGET_ARM) \
2651 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2652 STACK_POINTER_REGNUM, REGNO); \
2653 else \
2654 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2655
2656
2657 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2658 if (TARGET_ARM) \
2659 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2660 STACK_POINTER_REGNUM, REGNO); \
2661 else \
2662 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2663
2664 /* This is how to output a label which precedes a jumptable. Since
2665 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2666 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2667 do \
2668 { \
2669 if (TARGET_THUMB) \
2670 ASM_OUTPUT_ALIGN (FILE, 2); \
2671 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2672 } \
2673 while (0)
2674
2675 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2676 do \
2677 { \
2678 if (TARGET_THUMB) \
2679 { \
2680 if (is_called_in_ARM_mode (DECL)) \
2681 fprintf (STREAM, "\t.code 32\n") ; \
2682 else \
2683 fprintf (STREAM, "\t.thumb_func\n") ; \
2684 } \
2685 if (TARGET_POKE_FUNCTION_NAME) \
2686 arm_poke_function_name (STREAM, (char *) NAME); \
2687 } \
2688 while (0)
2689
2690 /* For aliases of functions we use .thumb_set instead. */
2691 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2692 do \
2693 { \
2694 char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2695 char * LABEL2 = IDENTIFIER_POINTER (DECL2); \
2696 \
2697 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2698 { \
2699 fprintf (FILE, "\t.thumb_set "); \
2700 assemble_name (FILE, LABEL1); \
2701 fprintf (FILE, ","); \
2702 assemble_name (FILE, LABEL2); \
2703 fprintf (FILE, "\n"); \
2704 } \
2705 else \
2706 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2707 } \
2708 while (0)
2709
2710 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2711 /* To support -falign-* switches we need to use .p2align so
2712 that alignment directives in code sections will be padded
2713 with no-op instructions, rather than zeroes. */
2714 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2715 if ((LOG) != 0) \
2716 { \
2717 if ((MAX_SKIP) == 0) \
2718 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2719 else \
2720 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2721 (LOG), (MAX_SKIP)); \
2722 }
2723 #endif
2724
2725 /* Target characters. */
2726 #define TARGET_BELL 007
2727 #define TARGET_BS 010
2728 #define TARGET_TAB 011
2729 #define TARGET_NEWLINE 012
2730 #define TARGET_VT 013
2731 #define TARGET_FF 014
2732 #define TARGET_CR 015
2733 \f
2734 /* Only perform branch elimination (by making instructions conditional) if
2735 we're optimising. Otherwise it's of no use anyway. */
2736 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2737 if (TARGET_ARM && optimize) \
2738 arm_final_prescan_insn (INSN); \
2739 else if (TARGET_THUMB) \
2740 thumb_final_prescan_insn (INSN)
2741
2742 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2743 (CODE == '@' || CODE == '|' \
2744 || (TARGET_ARM && (CODE == '?')) \
2745 || (TARGET_THUMB && (CODE == '_')))
2746
2747 /* Output an operand of an instruction. */
2748 #define PRINT_OPERAND(STREAM, X, CODE) \
2749 arm_print_operand (STREAM, X, CODE)
2750
2751 /* Create an [unsigned] host sized integer declaration that
2752 avoids compiler warnings. */
2753 #ifdef __STDC__
2754 #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL)
2755 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL)
2756 #else
2757 #define HOST_INT(x) ((HOST_WIDE_INT) x)
2758 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x)
2759 #endif
2760
2761 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2762 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2763 : ((((unsigned HOST_WIDE_INT)(x)) & HOST_UINT (0xffffffff)) |\
2764 ((((unsigned HOST_WIDE_INT)(x)) & HOST_UINT (0x80000000)) \
2765 ? ((~ HOST_UINT (0)) \
2766 & ~ HOST_UINT(0xffffffff)) \
2767 : 0))))
2768
2769 /* Output the address of an operand. */
2770 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2771 { \
2772 int is_minus = GET_CODE (X) == MINUS; \
2773 \
2774 if (GET_CODE (X) == REG) \
2775 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2776 else if (GET_CODE (X) == PLUS || is_minus) \
2777 { \
2778 rtx base = XEXP (X, 0); \
2779 rtx index = XEXP (X, 1); \
2780 HOST_WIDE_INT offset = 0; \
2781 if (GET_CODE (base) != REG) \
2782 { \
2783 /* Ensure that BASE is a register */ \
2784 /* (one of them must be). */ \
2785 rtx temp = base; \
2786 base = index; \
2787 index = temp; \
2788 } \
2789 switch (GET_CODE (index)) \
2790 { \
2791 case CONST_INT: \
2792 offset = INTVAL (index); \
2793 if (is_minus) \
2794 offset = -offset; \
2795 asm_fprintf (STREAM, "[%r, #%d]", \
2796 REGNO (base), offset); \
2797 break; \
2798 \
2799 case REG: \
2800 asm_fprintf (STREAM, "[%r, %s%r]", \
2801 REGNO (base), is_minus ? "-" : "", \
2802 REGNO (index)); \
2803 break; \
2804 \
2805 case MULT: \
2806 case ASHIFTRT: \
2807 case LSHIFTRT: \
2808 case ASHIFT: \
2809 case ROTATERT: \
2810 { \
2811 asm_fprintf (STREAM, "[%r, %s%r", \
2812 REGNO (base), is_minus ? "-" : "", \
2813 REGNO (XEXP (index, 0))); \
2814 arm_print_operand (STREAM, index, 'S'); \
2815 fputs ("]", STREAM); \
2816 break; \
2817 } \
2818 \
2819 default: \
2820 abort(); \
2821 } \
2822 } \
2823 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2824 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2825 { \
2826 extern int output_memory_reference_mode; \
2827 \
2828 if (GET_CODE (XEXP (X, 0)) != REG) \
2829 abort (); \
2830 \
2831 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2832 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2833 REGNO (XEXP (X, 0)), \
2834 GET_CODE (X) == PRE_DEC ? "-" : "", \
2835 GET_MODE_SIZE (output_memory_reference_mode));\
2836 else \
2837 asm_fprintf (STREAM, "[%r], #%s%d", \
2838 REGNO (XEXP (X, 0)), \
2839 GET_CODE (X) == POST_DEC ? "-" : "", \
2840 GET_MODE_SIZE (output_memory_reference_mode));\
2841 } \
2842 else output_addr_const (STREAM, X); \
2843 }
2844
2845 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2846 { \
2847 if (GET_CODE (X) == REG) \
2848 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2849 else if (GET_CODE (X) == POST_INC) \
2850 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2851 else if (GET_CODE (X) == PLUS) \
2852 { \
2853 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2854 asm_fprintf (STREAM, "[%r, #%d]", \
2855 REGNO (XEXP (X, 0)), \
2856 (int) INTVAL (XEXP (X, 1))); \
2857 else \
2858 asm_fprintf (STREAM, "[%r, %r]", \
2859 REGNO (XEXP (X, 0)), \
2860 REGNO (XEXP (X, 1))); \
2861 } \
2862 else \
2863 output_addr_const (STREAM, X); \
2864 }
2865
2866 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2867 if (TARGET_ARM) \
2868 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2869 else \
2870 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2871
2872 #define OUTPUT_INT_ADDR_CONST(STREAM, X) \
2873 { \
2874 output_addr_const (STREAM, X); \
2875 \
2876 /* Mark symbols as position independent. We only do this in the \
2877 .text segment, not in the .data segment. */ \
2878 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2879 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2880 { \
2881 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2882 fprintf (STREAM, "(GOTOFF)"); \
2883 else if (GET_CODE (X) == LABEL_REF) \
2884 fprintf (STREAM, "(GOTOFF)"); \
2885 else \
2886 fprintf (STREAM, "(GOT)"); \
2887 } \
2888 }
2889
2890 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2891 Used for C++ multiple inheritance. */
2892 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2893 do \
2894 { \
2895 int mi_delta = (DELTA); \
2896 const char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2897 int shift = 0; \
2898 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2899 ? 1 : 0); \
2900 if (mi_delta < 0) \
2901 mi_delta = - mi_delta; \
2902 while (mi_delta != 0) \
2903 { \
2904 if ((mi_delta & (3 << shift)) == 0) \
2905 shift += 2; \
2906 else \
2907 { \
2908 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2909 mi_op, this_regno, this_regno, \
2910 mi_delta & (0xff << shift)); \
2911 mi_delta &= ~(0xff << shift); \
2912 shift += 8; \
2913 } \
2914 } \
2915 fputs ("\tb\t", FILE); \
2916 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2917 if (NEED_PLT_RELOC) \
2918 fputs ("(PLT)", FILE); \
2919 fputc ('\n', FILE); \
2920 } \
2921 while (0)
2922
2923 /* A C expression whose value is RTL representing the value of the return
2924 address for the frame COUNT steps up from the current frame. */
2925
2926 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2927 arm_return_addr (COUNT, FRAME)
2928
2929 /* Mask of the bits in the PC that contain the real return address
2930 when running in 26-bit mode. */
2931 #define RETURN_ADDR_MASK26 (0x03fffffc)
2932
2933 /* Pick up the return address upon entry to a procedure. Used for
2934 dwarf2 unwind information. This also enables the table driven
2935 mechanism. */
2936 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2937 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2938
2939 /* Used to mask out junk bits from the return address, such as
2940 processor state, interrupt status, condition codes and the like. */
2941 #define MASK_RETURN_ADDR \
2942 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2943 in 26 bit mode, the condition codes must be masked out of the \
2944 return address. This does not apply to ARM6 and later processors \
2945 when running in 32 bit mode. */ \
2946 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2947 : (GEN_INT ((unsigned long)0xffffffff)))
2948
2949 \f
2950 /* Define the codes that are matched by predicates in arm.c */
2951 #define PREDICATE_CODES \
2952 {"s_register_operand", {SUBREG, REG}}, \
2953 {"arm_hard_register_operand", {REG}}, \
2954 {"f_register_operand", {SUBREG, REG}}, \
2955 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2956 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2957 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2958 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2959 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2960 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2961 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2962 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2963 {"offsettable_memory_operand", {MEM}}, \
2964 {"bad_signed_byte_operand", {MEM}}, \
2965 {"alignable_memory_operand", {MEM}}, \
2966 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2967 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2968 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2969 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2970 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2971 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2972 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2973 {"load_multiple_operation", {PARALLEL}}, \
2974 {"store_multiple_operation", {PARALLEL}}, \
2975 {"equality_operator", {EQ, NE}}, \
2976 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2977 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2978 UNGE, UNGT}}, \
2979 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2980 {"const_shift_operand", {CONST_INT}}, \
2981 {"multi_register_push", {PARALLEL}}, \
2982 {"cc_register", {REG}}, \
2983 {"logical_binary_operator", {AND, IOR, XOR}}, \
2984 {"dominant_cc_register", {REG}},
2985
2986 /* Define this if you have special predicates that know special things
2987 about modes. Genrecog will warn about certain forms of
2988 match_operand without a mode; if the operand predicate is listed in
2989 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2990 #define SPECIAL_MODE_PREDICATES \
2991 "cc_register", "dominant_cc_register",
2992
2993 enum arm_builtins
2994 {
2995 ARM_BUILTIN_CLZ,
2996 ARM_BUILTIN_PREFETCH,
2997 ARM_BUILTIN_MAX
2998 };
2999
3000 #define MD_INIT_BUILTINS \
3001 do \
3002 { \
3003 arm_init_builtins (); \
3004 } \
3005 while (0)
3006
3007 #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
3008 arm_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE))
3009 #endif /* ! GCC_ARM_H */
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