gcc/testsuite/gcc.dg/vmx/unpack-be-order.c

   1 /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
   2
   3 #include "harness.h"
   4
   5 #define BIG 4294967295
   6
   7 static void test()
   8 {
   9   /* Input vectors.  */
  10   vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
  11   vector bool char vbc = {0,255,255,0,0,0,255,0,255,0,0,255,255,255,0,255};
  12   vector pixel vp = {(0<<15) + (1<<10)  + (2<<5)  + 3,
  13                      (1<<15) + (4<<10)  + (5<<5)  + 6,
  14                      (0<<15) + (7<<10)  + (8<<5)  + 9,
  15                      (1<<15) + (10<<10) + (11<<5) + 12,
  16                      (1<<15) + (13<<10) + (14<<5) + 15,
  17                      (0<<15) + (16<<10) + (17<<5) + 18,
  18                      (1<<15) + (19<<10) + (20<<5) + 21,
  19                      (0<<15) + (22<<10) + (23<<5) + 24};
  20   vector signed short vss = {-4,-3,-2,-1,0,1,2,3};
  21   vector bool short vbs = {0,65535,65535,0,0,0,65535,0};
  22
  23   /* Result vectors.  */
  24   vector signed short vsch, vscl;
  25   vector bool short vbsh, vbsl;
  26   vector unsigned int vuih, vuil;
  27   vector signed int vsih, vsil;
  28   vector bool int vbih, vbil;
  29
  30   /* Expected result vectors.  */
  31 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
  32   vector signed short vschr = {0,1,2,3,4,5,6,7};
  33   vector signed short vsclr = {-8,-7,-6,-5,-4,-3,-2,-1};
  34   vector bool short vbshr = {65535,0,0,65535,65535,65535,0,65535};
  35   vector bool short vbslr = {0,65535,65535,0,0,0,65535,0};
  36   vector unsigned int vuihr = {(65535<<24) + (13<<16) + (14<<8) + 15,
  37                                (0<<24)     + (16<<16) + (17<<8) + 18,
  38                                (65535<<24) + (19<<16) + (20<<8) + 21,
  39                                (0<<24)     + (22<<16) + (23<<8) + 24};
  40   vector unsigned int vuilr = {(0<<24)     + (1<<16)  + (2<<8)  + 3,
  41                                (65535<<24) + (4<<16)  + (5<<8)  + 6,
  42                                (0<<24)     + (7<<16)  + (8<<8)  + 9,
  43                                (65535<<24) + (10<<16) + (11<<8) + 12};
  44   vector signed int vsihr = {0,1,2,3};
  45   vector signed int vsilr = {-4,-3,-2,-1};
  46   vector bool int vbihr = {0,0,BIG,0};
  47   vector bool int vbilr = {0,BIG,BIG,0};
  48 #else
  49   vector signed short vschr = {-8,-7,-6,-5,-4,-3,-2,-1};
  50   vector signed short vsclr = {0,1,2,3,4,5,6,7};
  51   vector bool short vbshr = {0,65535,65535,0,0,0,65535,0};
  52   vector bool short vbslr = {65535,0,0,65535,65535,65535,0,65535};
  53   vector unsigned int vuihr = {(0<<24)     + (1<<16)  + (2<<8)  + 3,
  54                                (65535<<24) + (4<<16)  + (5<<8)  + 6,
  55                                (0<<24)     + (7<<16)  + (8<<8)  + 9,
  56                                (65535<<24) + (10<<16) + (11<<8) + 12};
  57   vector unsigned int vuilr = {(65535<<24) + (13<<16) + (14<<8) + 15,
  58                                (0<<24)     + (16<<16) + (17<<8) + 18,
  59                                (65535<<24) + (19<<16) + (20<<8) + 21,
  60                                (0<<24)     + (22<<16) + (23<<8) + 24};
  61   vector signed int vsihr = {-4,-3,-2,-1};
  62   vector signed int vsilr = {0,1,2,3};
  63   vector bool int vbihr = {0,BIG,BIG,0};
  64   vector bool int vbilr = {0,0,BIG,0};
  65 #endif
  66
  67   vsch = vec_unpackh (vsc);
  68   vscl = vec_unpackl (vsc);
  69   vbsh = vec_unpackh (vbc);
  70   vbsl = vec_unpackl (vbc);
  71   vuih = vec_unpackh (vp);
  72   vuil = vec_unpackl (vp);
  73   vsih = vec_unpackh (vss);
  74   vsil = vec_unpackl (vss);
  75   vbih = vec_unpackh (vbs);
  76   vbil = vec_unpackl (vbs);
  77
  78   check (vec_all_eq (vsch, vschr), "vsch");
  79   check (vec_all_eq (vscl, vsclr), "vscl");
  80   check (vec_all_eq (vbsh, vbshr), "vbsh");
  81   check (vec_all_eq (vbsl, vbslr), "vbsl");
  82   check (vec_all_eq (vuih, vuihr), "vuih");
  83   check (vec_all_eq (vuil, vuilr), "vuil");
  84   check (vec_all_eq (vsih, vsihr), "vsih");
  85   check (vec_all_eq (vsil, vsilr), "vsil");
  86   check (vec_all_eq (vbih, vbihr), "vbih");
  87   check (vec_all_eq (vbil, vbilr), "vbil");
  88 }