gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c

   1 /* { dg-do compile } */
   2 /* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
   3 /* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */
   4 /* { dg-options "-march=rv32gc_xtheadmemidx" { target { rv32 } } } */
   5
   6 #include "xtheadmemidx-helpers.h"
   7
   8 /* We have a simm5 shifted by a imm2.
   9    imm2  | range (simm5 << imm2)
  10      0   |  -16..-1,0..15
  11      1   |  -32..-2,0..30
  12      2   |  -64..-4,0..60
  13      3   | -128..-8,0..120  */
  14
  15 POST_INC_LOAD(int8_t, 1)
  16 /* { dg-final { scan-assembler {\mth.lbia[^\n\r]*1,0\M} } } */
  17 PRE_DEC_LOAD(int8_t, 32)
  18 /* { dg-final { scan-assembler {\mth.lbib[^\n\r]*-16,1\M} } } */
  19
  20 POST_DEC_LOAD(uint8_t, 1)
  21 /* { dg-final { scan-assembler {\mth.lbuia[^\n\r]*-1,0\M} } } */
  22 PRE_INC_LOAD(uint8_t, 32)
  23 /* { dg-final { scan-assembler {\mth.lbuib[^\n\r]*8,2\M} } } */
  24
  25 POST_INC_LOAD(int16_t, 1)
  26 /* { dg-final { scan-assembler {\mth.lhia[^\n\r]*2,0\M} } } */
  27 POST_DEC_LOAD(int16_t, 64)
  28 /* { dg-final { scan-assembler {\mth.lhia[^\n\r]*-16,3\M} } } */
  29
  30 POST_DEC_LOAD(uint16_t, 1)
  31 /* { dg-final { scan-assembler {\mth.lhuia[^\n\r]*-2,0\M} } } */
  32 POST_INC_LOAD(uint16_t, 60)
  33 /* { dg-final { scan-assembler {\mth.lhuia[^\n\r]*15,3\M} } } */
  34
  35 POST_INC_LOAD(int32_t, 1)
  36 /* { dg-final { scan-assembler {\mth.lwia[^\n\r]*4,0\M} } } */
  37 PRE_DEC_LOAD(int32_t, 32)
  38 /* { dg-final { scan-assembler {\mth.lwib[^\n\r]*-16,3\M} } } */
  39
  40 #if __riscv_xlen == 64
  41 POST_DEC_LOAD(uint32_t, 1)
  42 /* { dg-final { scan-assembler {\mth.lwuia[^\n\r]*-4,0\M} { target { rv64 } } } } */
  43 PRE_INC_LOAD(uint32_t, 15)
  44 /* { dg-final { scan-assembler {\mth.lwuib[^\n\r]*15,2\M} { target { rv64 } } } } */
  45
  46 POST_INC_LOAD(int64_t, 1)
  47 /* { dg-final { scan-assembler {\mth.ldia[^\n\r]*8,0\M} { target { rv64 } } } } */
  48 PRE_DEC_LOAD(int64_t, 16)
  49 /* { dg-final { scan-assembler {\mth.ldib[^\n\r]*-16,3\M} { target { rv64 } } } } */
  50 #endif
  51
  52 POST_DEC_STORE(int8_t, 1)
  53 /* { dg-final { scan-assembler {\mth.sbia[^\n\r]*-1,0\M} } } */
  54 PRE_INC_STORE(int8_t, 120)
  55 /* { dg-final { scan-assembler {\mth.sbib[^\n\r]*15,3\M} } } */
  56
  57 POST_INC_STORE(int16_t, 1)
  58 /* { dg-final { scan-assembler {\mth.shia[^\n\r]*2,0\M} } } */
  59 PRE_DEC_STORE(int16_t, 64)
  60 /* { dg-final { scan-assembler {\mth.shib[^\n\r]*-16,3\M} } } */
  61
  62 POST_DEC_STORE(int32_t, 1)
  63 /* { dg-final { scan-assembler {\mth.swia[^\n\r]*-4,0\M} } } */
  64 PRE_INC_STORE(int32_t, 2)
  65 /* { dg-final { scan-assembler {\mth.swib[^\n\r]*8,0\M} } } */
  66
  67 #if __riscv_xlen == 64
  68 POST_INC_STORE(int64_t, 1)
  69 /* { dg-final { scan-assembler {\mth.sdia[^\n\r]*8,0\M} { target { rv64 } } } } */
  70 PRE_DEC_STORE(int64_t, 8)
  71 /* { dg-final { scan-assembler {\mth.sdib[^\n\r]*-16,2\M} { target { rv64 } } } } */
  72 #endif
  73
  74 /* { dg-final { scan-assembler-not {\m\taddi\M} } } */