| blob | 6f0d0abf82c55720927e8cb0dc639e9f95d36e40 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
68 #ifndef CHECK_STACK_LIMIT
69 #define CHECK_STACK_LIMIT (-1)
70 #endif
72 /* Return index of given mode in mult and division cost tables. */
73 #define MODE_INDEX(mode) \
74 ((mode) == QImode ? 0 \
75 : (mode) == HImode ? 1 \
76 : (mode) == SImode ? 2 \
77 : (mode) == DImode ? 3 \
78 : 4)
80 /* Processor costs (relative to an add) */
81 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
82 #define COSTS_N_BYTES(N) ((N) * 2)
84 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
86 const
109 in QImode, HImode and SImode.
110 Relative to reg-reg move (2). */
114 in SFmode, DFmode and XFmode */
116 in SFmode, DFmode and XFmode */
119 in SImode and DImode */
121 in SImode and DImode */
124 in SImode, DImode and TImode */
126 in SImode, DImode and TImode */
154 };
156 /* Processor costs (relative to an add) */
157 static const
180 in QImode, HImode and SImode.
181 Relative to reg-reg move (2). */
185 in SFmode, DFmode and XFmode */
187 in SFmode, DFmode and XFmode */
190 in SImode and DImode */
192 in SImode and DImode */
195 in SImode, DImode and TImode */
197 in SImode, DImode and TImode */
211 DUMMY_STRINGOP_ALGS},
213 DUMMY_STRINGOP_ALGS},
225 };
227 static const
250 in QImode, HImode and SImode.
251 Relative to reg-reg move (2). */
255 in SFmode, DFmode and XFmode */
257 in SFmode, DFmode and XFmode */
260 in SImode and DImode */
262 in SImode and DImode */
265 in SImode, DImode and TImode */
267 in SImode, DImode and TImode */
270 shared for code and data, so 4kB is
271 not really precise. */
283 DUMMY_STRINGOP_ALGS},
285 DUMMY_STRINGOP_ALGS},
297 };
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
353 DUMMY_STRINGOP_ALGS},
355 DUMMY_STRINGOP_ALGS},
367 };
369 static const
392 in QImode, HImode and SImode.
393 Relative to reg-reg move (2). */
397 in SFmode, DFmode and XFmode */
399 in SFmode, DFmode and XFmode */
402 in SImode and DImode */
404 in SImode and DImode */
407 in SImode, DImode and TImode */
409 in SImode, DImode and TImode */
422 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
423 (we ensure the alignment). For small blocks inline loop is still a
424 noticeable win, for bigger blocks either rep movsl or rep movsb is
425 way to go. Rep movsb has apparently more expensive startup time in CPU,
426 but after 4K the difference is down in the noise. */
430 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
745 };
769 in QImode, HImode and SImode.
770 Relative to reg-reg move (2). */
774 in SFmode, DFmode and XFmode */
776 in SFmode, DFmode and XFmode */
779 in SImode and DImode */
781 in SImode and DImode */
784 in SImode, DImode and TImode */
786 in SImode, DImode and TImode */
788 /* On K8:
789 MOVD reg64, xmmreg Double FSTORE 4
790 MOVD reg32, xmmreg Double FSTORE 4
791 On AMDFAM10:
792 MOVD reg64, xmmreg Double FADD 3
793 1/1 1/1
794 MOVD reg32, xmmreg Double FADD 3
795 1/1 1/1 */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
835 };
859 in QImode, HImode and SImode.
860 Relative to reg-reg move (2). */
864 in SFmode, DFmode and XFmode */
866 in SFmode, DFmode and XFmode */
869 in SImode and DImode */
871 in SImode and DImode */
874 in SImode, DImode and TImode */
876 in SImode, DImode and TImode */
878 /* On K8:
879 MOVD reg64, xmmreg Double FSTORE 4
880 MOVD reg32, xmmreg Double FSTORE 4
881 On AMDFAM10:
882 MOVD reg64, xmmreg Double FADD 3
883 1/1 1/1
884 MOVD reg32, xmmreg Double FADD 3
885 1/1 1/1 */
889 /* New AMD processors never drop prefetches; if they cannot be performed
890 immediately, they are queued. We set number of simultaneous prefetches
891 to a large constant to reflect this (it probably is not a good idea not
892 to limit number of prefetches at all, as their execution also takes some
893 time). */
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
925 };
949 in QImode, HImode and SImode.
950 Relative to reg-reg move (2). */
954 in SFmode, DFmode and XFmode */
956 in SFmode, DFmode and XFmode */
959 in SImode and DImode */
961 in SImode and DImode */
964 in SImode, DImode and TImode */
966 in SImode, DImode and TImode */
968 /* On K8:
969 MOVD reg64, xmmreg Double FSTORE 4
970 MOVD reg32, xmmreg Double FSTORE 4
971 On AMDFAM10:
972 MOVD reg64, xmmreg Double FADD 3
973 1/1 1/1
974 MOVD reg32, xmmreg Double FADD 3
975 1/1 1/1 */
979 /* New AMD processors never drop prefetches; if they cannot be performed
980 immediately, they are queued. We set number of simultaneous prefetches
981 to a large constant to reflect this (it probably is not a good idea not
982 to limit number of prefetches at all, as their execution also takes some
983 time). */
993 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
994 very small blocks it is better to use loop. For large blocks, libcall
995 can do nontemporary accesses and beat inline considerably. */
1015 };
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1061 /* New AMD processors never drop prefetches; if they cannot be performed
1062 immediately, they are queued. We set number of simultaneous prefetches
1063 to a large constant to reflect this (it probably is not a good idea not
1064 to limit number of prefetches at all, as their execution also takes some
1065 time). */
1075 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1097 };
1121 in QImode, HImode and SImode.
1122 Relative to reg-reg move (2). */
1126 in SFmode, DFmode and XFmode */
1128 in SFmode, DFmode and XFmode */
1131 in SImode and DImode */
1133 in SImode and DImode */
1136 in SImode, DImode and TImode */
1138 in SImode, DImode and TImode */
1140 /* On K8:
1141 MOVD reg64, xmmreg Double FSTORE 4
1142 MOVD reg32, xmmreg Double FSTORE 4
1143 On AMDFAM10:
1144 MOVD reg64, xmmreg Double FADD 3
1145 1/1 1/1
1146 MOVD reg32, xmmreg Double FADD 3
1147 1/1 1/1 */
1160 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1161 very small blocks it is better to use loop. For large blocks, libcall can
1162 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1264 };
1266 static const
1289 in QImode, HImode and SImode.
1290 Relative to reg-reg move (2). */
1294 in SFmode, DFmode and XFmode */
1296 in SFmode, DFmode and XFmode */
1299 in SImode and DImode */
1301 in SImode and DImode */
1304 in SImode, DImode and TImode */
1306 in SImode, DImode and TImode */
1320 DUMMY_STRINGOP_ALGS},
1323 DUMMY_STRINGOP_ALGS},
1335 };
1337 static const
1360 in QImode, HImode and SImode.
1361 Relative to reg-reg move (2). */
1365 in SFmode, DFmode and XFmode */
1367 in SFmode, DFmode and XFmode */
1370 in SImode and DImode */
1372 in SImode and DImode */
1375 in SImode, DImode and TImode */
1377 in SImode, DImode and TImode */
1408 };
1410 static const
1433 in QImode, HImode and SImode.
1434 Relative to reg-reg move (2). */
1438 in SFmode, DFmode and XFmode */
1440 in SFmode, DFmode and XFmode */
1443 in SImode and DImode */
1445 in SImode and DImode */
1448 in SImode, DImode and TImode */
1450 in SImode, DImode and TImode */
1481 };
1483 /* Generic64 should produce code tuned for Nocona and K8. */
1484 static const
1487 /* On all chips taken into consideration lea is 2 cycles and more. With
1488 this cost however our current implementation of synth_mult results in
1489 use of unnecessary temporary registers causing regression on several
1490 SPECfp benchmarks. */
1511 in QImode, HImode and SImode.
1512 Relative to reg-reg move (2). */
1516 in SFmode, DFmode and XFmode */
1518 in SFmode, DFmode and XFmode */
1521 in SImode and DImode */
1523 in SImode and DImode */
1526 in SImode, DImode and TImode */
1528 in SImode, DImode and TImode */
1534 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1535 value is increased to perhaps more appropriate value of 5. */
1560 };
1562 /* core_cost should produce code tuned for Core familly of CPUs. */
1563 static const
1566 /* On all chips taken into consideration lea is 2 cycles and more. With
1567 this cost however our current implementation of synth_mult results in
1568 use of unnecessary temporary registers causing regression on several
1569 SPECfp benchmarks. */
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1613 /* FIXME perhaps more appropriate value is 5. */
1641 };
1643 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1644 Athlon and K8. */
1645 static const
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1700 DUMMY_STRINGOP_ALGS},
1703 DUMMY_STRINGOP_ALGS},
1715 };
1717 /* Set by -mtune. */
1720 /* Set by -mtune or -Os. */
1723 /* Processor feature/optimization bitmasks. */
1724 #define m_386 (1<<PROCESSOR_I386)
1725 #define m_486 (1<<PROCESSOR_I486)
1726 #define m_PENT (1<<PROCESSOR_PENTIUM)
1727 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1728 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1729 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1730 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1731 #define m_CORE2 (1<<PROCESSOR_CORE2)
1732 #define m_COREI7 (1<<PROCESSOR_COREI7)
1733 #define m_CORE2I7 (m_CORE2 | m_COREI7)
1734 #define m_ATOM (1<<PROCESSOR_ATOM)
1736 #define m_GEODE (1<<PROCESSOR_GEODE)
1737 #define m_K6 (1<<PROCESSOR_K6)
1738 #define m_K6_GEODE (m_K6 | m_GEODE)
1739 #define m_K8 (1<<PROCESSOR_K8)
1740 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1741 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1742 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1743 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1744 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1745 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1746 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1747 #define m_BTVER (m_BTVER1 | m_BTVER2)
1748 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1749 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1750 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1752 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1753 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1755 /* Generic instruction choice should be common subset of supported CPUs
1756 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1757 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1759 /* Feature tests against the various tunings. */
1762 /* Feature tests against the various tunings used to create ix86_tune_features
1763 based on the processor mask. */
1765 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1766 negatively, so enabling for Generic64 seems like good code size
1767 tradeoff. We can't enable it for 32bit generic because it does not
1768 work well with PPro base chips. */
1771 /* X86_TUNE_PUSH_MEMORY */
1774 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1777 /* X86_TUNE_UNROLL_STRLEN */
1780 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1781 on simulation result. But after P4 was made, no performance benefit
1782 was observed with branch hints. It also increases the code size.
1783 As a result, icc never generates branch hints. */
1786 /* X86_TUNE_DOUBLE_WITH_ADD */
1789 /* X86_TUNE_USE_SAHF */
1790 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1792 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1793 partial dependencies. */
1796 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1797 register stalls on Generic32 compilation setting as well. However
1798 in current implementation the partial register stalls are not eliminated
1799 very well - they can be introduced via subregs synthesized by combine
1800 and can happen in caller/callee saving sequences. Because this option
1801 pays back little on PPro based chips and is in conflict with partial reg
1802 dependencies used by Athlon/P4 based chips, it is better to leave it off
1803 for generic32 for now. */
1804 m_PPRO,
1806 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1809 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1810 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1813 /* X86_TUNE_USE_HIMODE_FIOP */
1816 /* X86_TUNE_USE_SIMODE_FIOP */
1819 /* X86_TUNE_USE_MOV0 */
1820 m_K6,
1822 /* X86_TUNE_USE_CLTD */
1825 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1826 m_PENT4,
1828 /* X86_TUNE_SPLIT_LONG_MOVES */
1829 m_PPRO,
1831 /* X86_TUNE_READ_MODIFY_WRITE */
1834 /* X86_TUNE_READ_MODIFY */
1837 /* X86_TUNE_PROMOTE_QIMODE */
1840 /* X86_TUNE_FAST_PREFIX */
1843 /* X86_TUNE_SINGLE_STRINGOP */
1846 /* X86_TUNE_QIMODE_MATH */
1849 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1850 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1851 might be considered for Generic32 if our scheme for avoiding partial
1852 stalls was more effective. */
1855 /* X86_TUNE_PROMOTE_QI_REGS */
1858 /* X86_TUNE_PROMOTE_HI_REGS */
1859 m_PPRO,
1861 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1862 over esp addition. */
1865 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1866 over esp addition. */
1867 m_PENT,
1869 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1870 over esp subtraction. */
1873 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1874 over esp subtraction. */
1877 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1878 for DFmode copies */
1881 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1884 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1885 conflict here in between PPro/Pentium4 based chips that thread 128bit
1886 SSE registers as single units versus K8 based chips that divide SSE
1887 registers to two 64bit halves. This knob promotes all store destinations
1888 to be 128bit to allow register renaming on 128bit SSE units, but usually
1889 results in one extra microop on 64bit SSE units. Experimental results
1890 shows that disabling this option on P4 brings over 20% SPECfp regression,
1891 while enabling it on K8 brings roughly 2.4% regression that can be partly
1892 masked by careful scheduling of moves. */
1895 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1898 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1901 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1902 m_BDVER ,
1904 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1905 are resolved on SSE register parts instead of whole registers, so we may
1906 maintain just lower part of scalar values in proper format leaving the
1907 upper part undefined. */
1908 m_ATHLON_K8,
1910 /* X86_TUNE_SSE_TYPELESS_STORES */
1911 m_AMD_MULTIPLE,
1913 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1916 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1919 /* X86_TUNE_PROLOGUE_USING_MOVE */
1922 /* X86_TUNE_EPILOGUE_USING_MOVE */
1925 /* X86_TUNE_SHIFT1 */
1928 /* X86_TUNE_USE_FFREEP */
1929 m_AMD_MULTIPLE,
1931 /* X86_TUNE_INTER_UNIT_MOVES */
1934 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1937 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1938 than 4 branch instructions in the 16 byte window. */
1941 /* X86_TUNE_SCHEDULE */
1944 /* X86_TUNE_USE_BT */
1947 /* X86_TUNE_USE_INCDEC */
1950 /* X86_TUNE_PAD_RETURNS */
1953 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1954 m_ATOM,
1956 /* X86_TUNE_EXT_80387_CONSTANTS */
1959 /* X86_TUNE_AVOID_VECTOR_DECODE */
1962 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1963 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1966 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1967 vector path on AMD machines. */
1970 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1971 machines. */
1974 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1975 than a MOV. */
1976 m_PENT,
1978 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1979 but one byte longer. */
1980 m_PENT,
1982 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1983 operand that cannot be represented using a modRM byte. The XOR
1984 replacement is long decoded, so this split helps here as well. */
1985 m_K6,
1987 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1988 from FP to FP. */
1991 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1992 from integer to FP. */
1993 m_AMDFAM10,
1995 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1996 with a subsequent conditional jump instruction into a single
1997 compare-and-branch uop. */
1998 m_BDVER,
2000 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2001 will impact LEA instruction selection. */
2002 m_ATOM,
2004 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2005 instructions. */
2008 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2009 at -O3. For the moment, the prefetching seems badly tuned for Intel
2010 chips. */
2013 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2014 the auto-vectorizer. */
2017 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2018 during reassociation of integer computation. */
2019 m_ATOM,
2021 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2022 during reassociation of fp computation. */
2023 m_ATOM,
2025 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2026 regs instead of memory. */
2029 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2030 a conditional move. */
2031 m_ATOM
2032 };
2034 /* Feature tests against the various architecture variations. */
2037 /* Feature tests against the various architecture variations, used to create
2038 ix86_arch_features based on the processor mask. */
2040 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2043 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2046 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2049 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2052 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2054 };
2056 static const unsigned int x86_accumulate_outgoing_args
2059 static const unsigned int x86_arch_always_fancy_math_387
2062 static const unsigned int x86_avx256_split_unaligned_load
2065 static const unsigned int x86_avx256_split_unaligned_store
2068 /* In case the average insn count for single function invocation is
2069 lower than this constant, emit fast (but longer) prologue and
2070 epilogue code. */
2071 #define FAST_PROLOGUE_INSN_COUNT 20
2073 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2078 /* Array of the smallest class containing reg number REGNO, indexed by
2079 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2082 {
2083 /* ax, dx, cx, bx */
2085 /* si, di, bp, sp */
2087 /* FP registers */
2090 /* arg pointer */
2091 NON_Q_REGS,
2092 /* flags, fpsr, fpcr, frame */
2094 /* SSE registers */
2097 /* MMX registers */
2100 /* REX registers */
2103 /* SSE REX registers */
2106 };
2108 /* The "default" register map used in 32bit mode. */
2111 {
2119 };
2121 /* The "default" register map used in 64bit mode. */
2124 {
2132 };
2134 /* Define the register numbers to be used in Dwarf debugging information.
2135 The SVR4 reference port C compiler uses the following register numbers
2136 in its Dwarf output code:
2137 0 for %eax (gcc regno = 0)
2138 1 for %ecx (gcc regno = 2)
2139 2 for %edx (gcc regno = 1)
2140 3 for %ebx (gcc regno = 3)
2141 4 for %esp (gcc regno = 7)
2142 5 for %ebp (gcc regno = 6)
2143 6 for %esi (gcc regno = 4)
2144 7 for %edi (gcc regno = 5)
2145 The following three DWARF register numbers are never generated by
2146 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2147 believes these numbers have these meanings.
2148 8 for %eip (no gcc equivalent)
2149 9 for %eflags (gcc regno = 17)
2150 10 for %trapno (no gcc equivalent)
2151 It is not at all clear how we should number the FP stack registers
2152 for the x86 architecture. If the version of SDB on x86/svr4 were
2153 a bit less brain dead with respect to floating-point then we would
2154 have a precedent to follow with respect to DWARF register numbers
2155 for x86 FP registers, but the SDB on x86/svr4 is so completely
2156 broken with respect to FP registers that it is hardly worth thinking
2157 of it as something to strive for compatibility with.
2158 The version of x86/svr4 SDB I have at the moment does (partially)
2159 seem to believe that DWARF register number 11 is associated with
2160 the x86 register %st(0), but that's about all. Higher DWARF
2161 register numbers don't seem to be associated with anything in
2162 particular, and even for DWARF regno 11, SDB only seems to under-
2163 stand that it should say that a variable lives in %st(0) (when
2164 asked via an `=' command) if we said it was in DWARF regno 11,
2165 but SDB still prints garbage when asked for the value of the
2166 variable in question (via a `/' command).
2167 (Also note that the labels SDB prints for various FP stack regs
2168 when doing an `x' command are all wrong.)
2169 Note that these problems generally don't affect the native SVR4
2170 C compiler because it doesn't allow the use of -O with -g and
2171 because when it is *not* optimizing, it allocates a memory
2172 location for each floating-point variable, and the memory
2173 location is what gets described in the DWARF AT_location
2174 attribute for the variable in question.
2175 Regardless of the severe mental illness of the x86/svr4 SDB, we
2176 do something sensible here and we use the following DWARF
2177 register numbers. Note that these are all stack-top-relative
2178 numbers.
2179 11 for %st(0) (gcc regno = 8)
2180 12 for %st(1) (gcc regno = 9)
2181 13 for %st(2) (gcc regno = 10)
2182 14 for %st(3) (gcc regno = 11)
2183 15 for %st(4) (gcc regno = 12)
2184 16 for %st(5) (gcc regno = 13)
2185 17 for %st(6) (gcc regno = 14)
2186 18 for %st(7) (gcc regno = 15)
2187 */
2189 {
2197 };
2199 /* Define parameter passing and return registers. */
2202 {
2204 };
2207 {
2209 };
2212 {
2214 };
2216 /* Define the structure for the machine field in struct function. */
2221 rtx rtl;
2223 };
2225 /* Structure describing stack frame layout.
2226 Stack grows downward:
2228 [arguments]
2229 <- ARG_POINTER
2230 saved pc
2232 saved static chain if ix86_static_chain_on_stack
2234 saved frame pointer if frame_pointer_needed
2235 <- HARD_FRAME_POINTER
2236 [saved regs]
2237 <- regs_save_offset
2238 [padding0]
2240 [saved SSE regs]
2241 <- sse_regs_save_offset
2242 [padding1] |
2243 | <- FRAME_POINTER
2244 [va_arg registers] |
2245 |
2246 [frame] |
2247 |
2248 [padding2] | = to_allocate
2249 <- STACK_POINTER
2250 */
2251 struct ix86_frame
2252 {
2259 /* The offsets relative to ARG_POINTER. */
2260 HOST_WIDE_INT frame_pointer_offset;
2261 HOST_WIDE_INT hard_frame_pointer_offset;
2262 HOST_WIDE_INT stack_pointer_offset;
2263 HOST_WIDE_INT hfp_save_offset;
2264 HOST_WIDE_INT reg_save_offset;
2265 HOST_WIDE_INT sse_reg_save_offset;
2267 /* When save_regs_using_mov is set, emit prologue using
2268 move instead of push instructions. */
2270 };
2272 /* Which cpu are we scheduling for. */
2275 /* Which cpu are we optimizing for. */
2278 /* Which instruction set architecture to use. */
2281 /* True if processor has SSE prefetch instruction. */
2284 /* -mstackrealign option */
2301 /* Preferred alignment for stack boundary in bits. */
2304 /* Alignment for incoming stack boundary in bits specified at
2305 command line. */
2308 /* Default alignment for incoming stack boundary in bits. */
2311 /* Alignment for incoming stack boundary in bits. */
2314 /* Calling abi specific va_list type nodes. */
2318 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2322 /* Fence to use after loop using movnt. */
2323 tree x86_mfence;
2325 /* Register class used for passing given 64bit part of the argument.
2326 These represent classes as documented by the PS ABI, with the exception
2327 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2328 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2330 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2331 whenever possible (upper half does contain padding). */
2332 enum x86_64_reg_class
2333 {
2334 X86_64_NO_CLASS,
2335 X86_64_INTEGER_CLASS,
2336 X86_64_INTEGERSI_CLASS,
2337 X86_64_SSE_CLASS,
2338 X86_64_SSESF_CLASS,
2339 X86_64_SSEDF_CLASS,
2340 X86_64_SSEUP_CLASS,
2341 X86_64_X87_CLASS,
2342 X86_64_X87UP_CLASS,
2343 X86_64_COMPLEX_X87_CLASS,
2344 X86_64_MEMORY_CLASS
2345 };
2347 #define MAX_CLASSES 4
2349 /* Table of constants used by fldpi, fldln2, etc.... */
2353 \f
2358 const_tree);
2370 enum ix86_function_specific_strings
2371 {
2372 IX86_FUNCTION_SPECIFIC_ARCH,
2373 IX86_FUNCTION_SPECIFIC_TUNE,
2374 IX86_FUNCTION_SPECIFIC_MAX
2375 };
2393 \f
2394 #ifndef SUBTARGET32_DEFAULT_CPU
2396 #endif
2398 /* Whether -mtune= or -march= were specified */
2402 /* Vectorization library interface and handlers. */
2408 /* Processor target table, indexed by processor number */
2409 struct ptt
2410 {
2417 };
2420 {
2431 /* Core 2 */
2433 /* Core i7 */
2444 };
2447 {
2475 "btver2"
2476 };
2477 \f
2478 static bool
2480 {
2482 }
2484 static unsigned int
2486 {
2489 /* vzeroupper instructions are inserted immediately after reload to
2490 account for possible spills from 256bit registers. The pass
2491 reuses mode switching infrastructure by re-running mode insertion
2492 pass, so disable entities that have already been processed. */
2498 /* Call optimize_mode_switching. */
2501 }
2504 {
2505 {
2506 RTL_PASS,
2521 }
2522 };
2524 /* Return true if a red-zone is in use. */
2528 {
2530 }
2531 \f
2532 /* Return a string that documents the current -m options. The caller is
2533 responsible for freeing the string. */
2539 {
2540 struct ix86_target_opts
2541 {
2544 };
2546 /* This table is ordered so that options like -msse4.2 that imply
2547 preceding options while match those first. */
2549 {
2585 };
2587 /* Flag options. */
2589 {
2617 };
2634 /* Add -march= option. */
2636 {
2639 }
2641 /* Add -mtune= option. */
2643 {
2646 }
2648 /* Add -m32/-m64/-mx32. */
2650 {
2653 else
2655 isa &= ~ (OPTION_MASK_ISA_64BIT
2656 | OPTION_MASK_ABI_64
2658 }
2659 else
2663 /* Pick out the options in isa options. */
2665 {
2667 {
2670 }
2671 }
2674 {
2677 isa);
2678 }
2680 /* Add flag options. */
2682 {
2684 {
2687 }
2688 }
2691 {
2694 }
2696 /* Add -fpmath= option. */
2698 {
2701 {
2716 }
2717 }
2719 /* Any options? */
2725 /* Size the string. */
2729 {
2734 }
2736 /* Build the string. */
2741 {
2748 {
2750 line_len++;
2753 {
2757 }
2758 }
2762 {
2766 }
2767 }
2773 }
2775 /* Return true, if profiling code should be emitted before
2776 prologue. Otherwise it returns false.
2777 Note: For x86 with "hotfix" it is sorried. */
2778 static bool
2780 {
2782 }
2784 /* Function that is callable from the debugger to print the current
2785 options. */
2786 void
2788 {
2794 {
2797 }
2798 else
2802 }
2803 \f
2804 /* Override various settings based on options. If MAIN_ARGS_P, the
2805 options are from the command line, otherwise they are from
2806 attributes. */
2808 static void
2810 {
2818 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2819 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2820 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2821 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2822 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2823 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2824 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2825 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2826 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2827 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2828 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2829 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2830 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2831 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2832 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2833 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2834 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2835 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2836 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2837 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2838 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2839 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2840 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2841 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2842 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2843 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2844 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2845 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2846 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2847 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2848 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2849 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2850 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2851 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2852 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2853 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2854 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2855 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2856 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2857 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2859 /* if this reaches 64, need to widen struct pta flags below */
2861 static struct pta
2862 {
2867 }
2869 {
2999 PTA_64BIT
3001 };
3003 /* -mrecip options. */
3004 static struct
3005 {
3008 }
3010 {
3017 };
3021 /* Set up prefix/suffix so the error messages refer to either the command
3022 line argument, or the attribute(target). */
3024 {
3028 }
3029 else
3030 {
3034 }
3036 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3037 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3040 #ifdef TARGET_BI_ARCH
3041 else
3042 {
3043 #if TARGET_BI_ARCH == 1
3044 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3045 is on and OPTION_MASK_ABI_X32 is off. We turn off
3046 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3047 -mx32. */
3050 #else
3051 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3052 on and OPTION_MASK_ABI_64 is off. We turn off
3053 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3054 -m64. */
3057 #endif
3058 }
3059 #endif
3062 {
3063 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3064 OPTION_MASK_ABI_64 for TARGET_X32. */
3067 }
3069 {
3070 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3071 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3074 }
3076 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3077 SUBTARGET_OVERRIDE_OPTIONS;
3078 #endif
3080 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3081 SUBSUBTARGET_OVERRIDE_OPTIONS;
3082 #endif
3084 /* -fPIC is the default for x86_64. */
3088 /* Need to check -mtune=generic first. */
3090 {
3093 /* As special support for cross compilers we read -mtune=native
3094 as -mtune=generic. With native compilers we won't see the
3095 -mtune=native, as it was changed by the driver. */
3097 {
3100 else
3102 }
3103 /* If this call is for setting the option attribute, allow the
3104 generic32/generic64 that was previously set. */
3108 ;
3116 }
3117 else
3118 {
3122 {
3125 }
3127 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3128 need to use a sensible tune option. */
3132 {
3135 else
3137 }
3138 }
3141 {
3142 /* rep; movq isn't available in 32-bit code. */
3145 }
3149 else
3153 {
3159 }
3160 else
3167 {
3169 {
3213 {
3216 }
3224 }
3225 }
3226 else
3227 {
3228 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3229 use of rip-relative addressing. This eliminates fixups that
3230 would otherwise be needed if this object is to be placed in a
3231 DLL, and is essentially just as efficient as direct addressing. */
3236 else
3238 }
3240 {
3243 }
3250 {
3253 /* Default cpu tuning to the architecture. */
3378 }
3393 {
3397 {
3399 {
3401 {
3409 }
3410 else
3413 }
3414 }
3415 else
3416 {
3417 /* Adjust tuning when compiling for 32-bit ABI. */
3419 {
3427 }
3428 }
3429 /* Intel CPUs have always interpreted SSE prefetch instructions as
3430 NOPs; so, we can enable SSE prefetch instructions even when
3431 -mtune (rather than -march) points us to a processor that has them.
3432 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3433 higher processors. */
3438 }
3448 #ifndef USE_IX86_FRAME_POINTER
3449 #define USE_IX86_FRAME_POINTER 0
3450 #endif
3452 #ifndef USE_X86_64_FRAME_POINTER
3453 #define USE_X86_64_FRAME_POINTER 0
3454 #endif
3456 /* Set the default values for switches whose default depends on TARGET_64BIT
3457 in case they weren't overwritten by command line options. */
3459 {
3466 }
3467 else
3468 {
3475 }
3480 else
3483 /* Arrange to set up i386_stack_locals for all functions. */
3486 /* Validate -mregparm= value. */
3488 {
3492 {
3496 }
3497 }
3501 /* Default align_* from the processor table. */
3503 {
3506 }
3508 {
3511 }
3513 {
3515 }
3517 /* Provide default for -mbranch-cost= value. */
3522 {
3525 /* Enable by default the SSE and MMX builtins. Do allow the user to
3526 explicitly disable any of these. In particular, disabling SSE and
3527 MMX for kernel code is extremely useful. */
3529 ix86_isa_flags
3535 }
3536 else
3537 {
3541 ix86_isa_flags
3544 /* i386 ABI does not specify red zone. It still makes sense to use it
3545 when programmer takes care to stack from being destroyed. */
3548 }
3550 /* Keep nonleaf frame pointers. */
3556 /* If we're doing fast math, we don't care about comparison order
3557 wrt NaNs. This lets us use a shorter comparison sequence. */
3561 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3562 since the insns won't need emulation. */
3566 /* Likewise, if the target doesn't have a 387, or we've specified
3567 software floating point, don't use 387 inline intrinsics. */
3571 /* Turn on MMX builtins for -msse. */
3575 /* Enable SSE prefetch. */
3579 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3583 /* Turn on lzcnt instruction for -mabm. */
3587 /* Validate -mpreferred-stack-boundary= value or default it to
3588 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3591 {
3597 {
3601 else
3604 }
3605 else
3606 ix86_preferred_stack_boundary
3608 }
3610 /* Set the default value for -mstackrealign. */
3616 /* Validate -mincoming-stack-boundary= value or default it to
3617 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3620 {
3625 else
3626 {
3627 ix86_user_incoming_stack_boundary
3629 ix86_incoming_stack_boundary
3631 }
3632 }
3634 /* Accept -msseregparm only if at least SSE support is enabled. */
3640 {
3642 {
3644 {
3647 }
3649 {
3652 }
3653 }
3654 }
3655 else
3658 /* If the i387 is disabled, then do not return values in it. */
3662 /* Use external vectorized library in vectorizing intrinsics. */
3665 {
3676 }
3684 /* ??? Unwind info is not correct around the CFG unless either a frame
3685 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3686 unwind info generation to be aware of the CFG and propagating states
3687 around edges. */
3690 && flag_omit_frame_pointer
3692 {
3698 }
3700 /* If stack probes are required, the space used for large function
3701 arguments on the stack must also be probed, so enable
3702 -maccumulate-outgoing-args so this happens in the prologue. */
3705 {
3710 }
3712 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3713 {
3719 }
3721 /* When scheduling description is not available, disable scheduler pass
3722 so it won't slow down the compilation and make x87 code slower. */
3743 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3745 && HAVE_prefetch
3750 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3751 can be optimized to ap = __builtin_next_arg (0). */
3756 {
3759 {
3762 ix86_gen_tls_local_dynamic_base_64
3764 }
3765 else
3766 {
3769 ix86_gen_tls_local_dynamic_base_64
3771 }
3772 }
3773 else
3774 {
3777 }
3780 {
3789 }
3790 else
3791 {
3800 }
3802 #ifdef USE_IX86_CLD
3803 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3806 #endif
3809 {
3814 }
3816 {
3820 }
3822 {
3823 #if defined(PROFILE_BEFORE_PROLOGUE)
3825 #else
3827 #endif
3828 }
3831 {
3832 /* When not optimize for size, enable vzeroupper optimization for
3833 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3834 AVX unaligned load/store. */
3836 {
3846 /* Enable 128-bit AVX instruction generation
3847 for the auto-vectorizer. */
3851 }
3852 }
3853 else
3854 {
3855 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3857 }
3860 {
3867 {
3870 {
3872 q++;
3873 }
3874 else
3879 else
3880 {
3883 {
3886 }
3889 {
3893 }
3894 }
3899 else
3901 }
3902 }
3909 /* Default long double to 64-bit for Bionic. */
3914 /* Save the initial options in case the user does function specific
3915 options. */
3917 target_option_default_node = target_option_current_node
3919 }
3921 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3923 static void
3925 {
3926 static struct register_pass_info insert_vzeroupper_info
3929 };
3934 /* This needs to be done at start up. It's convenient to do it here. */
3936 }
3938 /* Update register usage after having seen the compiler flags. */
3940 static void
3942 {
3946 /* The PIC register, if it exists, is fixed. */
3951 /* For 32-bit targets, squash the REX registers. */
3953 {
3958 }
3960 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3968 {
3969 /* Set/reset conditionally defined registers from
3970 CALL_USED_REGISTERS initializer. */
3974 /* Calculate registers of CLOBBERED_REGS register set
3975 as call used registers from GENERAL_REGS register set. */
3979 }
3981 /* If MMX is disabled, squash the registers. */
3987 /* If SSE is disabled, squash the registers. */
3993 /* If the FPU is disabled, squash the registers. */
3998 }
4000 \f
4001 /* Save the current options */
4003 static void
4005 {
4016 /* The fields are char but the variables are not; make sure the
4017 values fit in the fields. */
4022 }
4024 /* Restore the current options */
4026 static void
4028 {
4044 /* Recreate the arch feature tests if the arch changed */
4046 {
4051 }
4053 /* Recreate the tune optimization tests */
4055 {
4060 }
4061 }
4063 /* Print the current options */
4065 static void
4068 {
4090 {
4093 }
4094 }
4096 \f
4097 /* Inner function to process the attribute((target(...))), take an argument and
4098 set the current options from the argument. If we have a list, recursively go
4099 over the list. */
4101 static bool
4104 {
4108 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4109 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4110 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4111 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4112 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4114 enum ix86_opt_type
4115 {
4116 ix86_opt_unknown,
4117 ix86_opt_yes,
4118 ix86_opt_no,
4119 ix86_opt_str,
4120 ix86_opt_enum,
4121 ix86_opt_isa
4122 };
4124 static const struct
4125 {
4132 /* isa options */
4169 /* enum options */
4172 /* string options */
4176 /* flag options */
4178 OPT_mcld,
4179 MASK_CLD),
4182 OPT_mfancy_math_387,
4183 MASK_NO_FANCY_MATH_387),
4186 OPT_mieee_fp,
4187 MASK_IEEE_FP),
4190 OPT_minline_all_stringops,
4191 MASK_INLINE_ALL_STRINGOPS),
4194 OPT_minline_stringops_dynamically,
4195 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4198 OPT_mno_align_stringops,
4199 MASK_NO_ALIGN_STRINGOPS),
4202 OPT_mrecip,
4203 MASK_RECIP),
4205 };
4207 /* If this is a list, recurse to get the options. */
4209 {
4219 }
4224 /* Handle multiple arguments separated by commas. */
4228 {
4242 {
4246 }
4247 else
4248 {
4251 }
4253 /* Recognize no-xxx. */
4255 {
4259 }
4260 else
4263 /* Find the option. */
4267 {
4275 {
4280 }
4281 }
4283 /* Process the option. */
4285 {
4288 }
4291 {
4297 }
4300 {
4306 else
4308 }
4311 {
4313 {
4316 }
4317 else
4319 }
4322 {
4330 global_dc);
4331 else
4332 {
4335 }
4336 }
4338 else
4340 }
4343 }
4345 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4347 tree
4349 {
4364 /* Process each of the options on the chain. */
4369 /* If the changed options are different from the default, rerun
4370 ix86_option_override_internal, and then save the options away.
4371 The string options are are attribute options, and will be undone
4372 when we copy the save structure. */
4378 {
4379 /* If we are using the default tune= or arch=, undo the string assigned,
4380 and use the default. */
4391 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4395 {
4398 }
4400 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4403 /* Add any builtin functions with the new isa if any. */
4406 /* Save the current options unless we are validating options for
4407 #pragma. */
4414 /* Free up memory allocated to hold the strings */
4417 }
4420 }
4422 /* Hook to validate attribute((target("string"))). */
4424 static bool
4427 tree args,
4429 {
4436 /* If the function changed the optimization levels as well as setting target
4437 options, start with the optimizations specified. */
4442 /* The target attributes may also change some optimization flags, so update
4443 the optimization options if necessary. */
4452 {
4457 }
4466 }
4468 \f
4469 /* Hook to determine if one function can safely inline another. */
4471 static bool
4473 {
4478 /* If callee has no option attributes, then it is ok to inline. */
4482 /* If caller has no option attributes, but callee does then it is not ok to
4483 inline. */
4487 else
4488 {
4492 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4493 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4494 function. */
4499 /* See if we have the same non-isa options. */
4503 /* See if arch, tune, etc. are the same. */
4516 else
4518 }
4521 }
4523 \f
4524 /* Remember the last target of ix86_set_current_function. */
4527 /* Establish appropriate back-end context for processing the function
4528 FNDECL. The argument might be NULL to indicate processing at top
4529 level, outside of any function scope. */
4530 static void
4532 {
4533 /* Only change the context if the function changes. This hook is called
4534 several times in the course of compiling a function, and we don't want to
4535 slow things down too much or call target_reinit when it isn't safe. */
4537 {
4538 tree old_tree = (ix86_previous_fndecl
4542 tree new_tree = (fndecl
4548 ;
4551 {
4555 }
4558 {
4564 }
4565 }
4566 }
4568 \f
4569 /* Return true if this goes in large data/bss. */
4571 static bool
4573 {
4577 /* Functions are never large data. */
4582 {
4588 }
4589 else
4590 {
4593 /* If this is an incomplete type with size 0, then we can't put it
4594 in data because it might be too big when completed. */
4597 }
4600 }
4602 /* Switch to the appropriate section for output of DECL.
4603 DECL is either a `VAR_DECL' node or a constant of some sort.
4604 RELOC indicates whether forming the initial value of DECL requires
4605 link-time relocations. */
4608 ATTRIBUTE_UNUSED;
4613 {
4616 {
4620 {
4654 /* We don't split these for medium model. Place them into
4655 default sections and hope for best. */
4657 }
4659 {
4660 /* We might get called with string constants, but get_named_section
4661 doesn't like them as they are not DECLs. Also, we need to set
4662 flags in that case. */
4666 }
4667 }
4669 }
4671 /* Build up a unique section name, expressed as a
4672 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4673 RELOC indicates whether the initial value of EXP requires
4674 link-time relocations. */
4676 static void ATTRIBUTE_UNUSED
4678 {
4681 {
4683 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4687 {
4711 /* We don't split these for medium model. Place them into
4712 default sections and hope for best. */
4714 }
4716 {
4723 /* If we're using one_only, then there needs to be a .gnu.linkonce
4724 prefix to the section name. */
4731 }
4732 }
4734 }
4736 #ifdef COMMON_ASM_OP
4737 /* This says how to output assembler code to declare an
4738 uninitialized external linkage data object.
4740 For medium model x86-64 we need to use .largecomm opcode for
4741 large objects. */
4742 void
4746 {
4750 else
4755 }
4756 #endif
4758 /* Utility function for targets to use in implementing
4759 ASM_OUTPUT_ALIGNED_BSS. */
4761 void
4765 {
4769 else
4772 #ifdef ASM_DECLARE_OBJECT_NAME
4775 #else
4776 /* Standard thing is just output label for the object. */
4780 }
4781 \f
4782 /* Decide whether we must probe the stack before any space allocation
4783 on this target. It's essentially TARGET_STACK_PROBE except when
4784 -fstack-check causes the stack to be already probed differently. */
4786 bool
4788 {
4789 /* Do not probe the stack twice if static stack checking is enabled. */
4794 }
4795 \f
4796 /* Decide whether we can make a sibling call to a function. DECL is the
4797 declaration of the function being targeted by the call and EXP is the
4798 CALL_EXPR representing the call. */
4800 static bool
4802 {
4806 /* If we are generating position-independent code, we cannot sibcall
4807 optimize any indirect call, or a direct call to a global function,
4808 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4810 && !TARGET_64BIT
4811 && flag_pic
4815 /* If we need to align the outgoing stack, then sibcalling would
4816 unalign the stack, which may break the called function. */
4822 {
4825 }
4826 else
4827 {
4828 /* We're looking at the CALL_EXPR, we need the type of the function. */
4833 }
4835 /* Check that the return value locations are the same. Like
4836 if we are returning floats on the 80387 register stack, we cannot
4837 make a sibcall from a function that doesn't return a float to a
4838 function that does or, conversely, from a function that does return
4839 a float to a function that doesn't; the necessary stack adjustment
4840 would not be executed. This is also the place we notice
4841 differences in the return value ABI. Note that it is ok for one
4842 of the functions to have void return type as long as the return
4843 value of the other is passed in a register. */
4848 {
4851 }
4853 ;
4858 {
4859 /* The SYSV ABI has more call-clobbered registers;
4860 disallow sibcalls from MS to SYSV. */
4864 }
4865 else
4866 {
4867 /* If this call is indirect, we'll need to be able to use a
4868 call-clobbered register for the address of the target function.
4869 Make sure that all such registers are not used for passing
4870 parameters. Note that DLLIMPORT functions are indirect. */
4873 {
4875 {
4876 /* ??? Need to count the actual number of registers to be used,
4877 not the possible number of registers. Fix later. */
4879 }
4880 }
4881 }
4883 /* Otherwise okay. That also includes certain types of indirect calls. */
4885 }
4887 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4888 and "sseregparm" calling convention attributes;
4889 arguments as in struct attribute_spec.handler. */
4891 static tree
4893 tree args,
4896 {
4901 {
4903 name);
4906 }
4908 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4910 {
4911 tree cst;
4914 {
4916 }
4919 {
4921 }
4925 {
4928 name);
4930 }
4932 {
4936 }
4939 }
4942 {
4943 /* Do not warn when emulating the MS ABI. */
4948 name);
4951 }
4953 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4955 {
4957 {
4959 }
4961 {
4963 }
4965 {
4967 }
4969 {
4971 }
4972 }
4974 /* Can combine stdcall with fastcall (redundant), regparm and
4975 sseregparm. */
4977 {
4979 {
4981 }
4983 {
4985 }
4987 {
4989 }
4990 }
4992 /* Can combine cdecl with regparm and sseregparm. */
4994 {
4996 {
4998 }
5000 {
5002 }
5004 {
5006 }
5007 }
5009 {
5012 name);
5014 {
5016 }
5018 {
5020 }
5022 {
5024 }
5025 }
5027 /* Can combine sseregparm with all attributes. */
5030 }
5032 /* The transactional memory builtins are implicitly regparm or fastcall
5033 depending on the ABI. Override the generic do-nothing attribute that
5034 these builtins were declared with, and replace it with one of the two
5035 attributes that we expect elsewhere. */
5037 static tree
5039 tree args ATTRIBUTE_UNUSED,
5042 {
5043 tree alt;
5045 /* In no case do we want to add the placeholder attribute. */
5048 /* The 64-bit ABI is unchanged for transactional memory. */
5052 /* ??? Is there a better way to validate 32-bit windows? We have
5053 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5056 else
5057 {
5060 }
5064 }
5066 /* This function determines from TYPE the calling-convention. */
5068 unsigned int
5070 {
5073 tree attrs;
5080 {
5090 /* Regparam isn't allowed for thiscall and fastcall. */
5092 {
5097 }
5101 }
5108 || is_stdarg
5114 }
5116 /* Return 0 if the attributes for two types are incompatible, 1 if they
5117 are compatible, and 2 if they are nearly compatible (which causes a
5118 warning to be generated). */
5120 static int
5122 {
5138 }
5139 \f
5140 /* Return the regparm value for a function with the indicated TYPE and DECL.
5141 DECL may be NULL when calling function indirectly
5142 or considering a libcall. */
5144 static int
5146 {
5147 tree attr;
5158 {
5161 {
5164 }
5165 }
5171 /* Use register calling convention for local functions when possible. */
5174 && optimize
5176 {
5177 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5180 {
5183 /* Make sure no regparm register is taken by a
5184 fixed register variable. */
5189 /* We don't want to use regparm(3) for nested functions as
5190 these use a static chain pointer in the third argument. */
5194 /* In 32-bit mode save a register for the split stack. */
5198 /* Each fixed register usage increases register pressure,
5199 so less registers should be used for argument passing.
5200 This functionality can be overriden by an explicit
5201 regparm value. */
5204 globals++;
5206 local_regparm
5211 }
5212 }
5215 }
5217 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5218 DFmode (2) arguments in SSE registers for a function with the
5219 indicated TYPE and DECL. DECL may be NULL when calling function
5220 indirectly or considering a libcall. Otherwise return 0. */
5222 static int
5224 {
5227 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5228 by the sseregparm attribute. */
5231 {
5233 {
5235 {
5239 else
5242 }
5244 }
5247 }
5249 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5250 (and DFmode for SSE2) arguments in SSE registers. */
5253 {
5254 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5258 }
5261 }
5263 /* Return true if EAX is live at the start of the function. Used by
5264 ix86_expand_prologue to determine if we need special help before
5265 calling allocate_stack_worker. */
5267 static bool
5269 {
5270 /* Cheat. Don't bother working forward from ix86_function_regparm
5271 to the function type to whether an actual argument is located in
5272 eax. Instead just look at cfg info, which is still close enough
5273 to correct at this point. This gives false positives for broken
5274 functions that might use uninitialized data that happens to be
5275 allocated in eax, but who cares? */
5277 }
5279 static bool
5281 {
5282 tree attr;
5285 {
5291 /* For 32-bit MS-ABI the default is to keep aggregate
5292 return pointer. */
5295 }
5297 }
5299 /* Value is the number of bytes of arguments automatically
5300 popped when returning from a subroutine call.
5301 FUNDECL is the declaration node of the function (as a tree),
5302 FUNTYPE is the data type of the function (as a tree),
5303 or for a library call it is an identifier node for the subroutine name.
5304 SIZE is the number of bytes of arguments passed on the stack.
5306 On the 80386, the RTD insn may be used to pop them if the number
5307 of args is fixed, but if the number is variable then the caller
5308 must pop them all. RTD can't be used for library calls now
5309 because the library is compiled with the Unix compiler.
5310 Use of RTD is a selectable option, since it is incompatible with
5311 standard Unix calling sequences. If the option is not selected,
5312 the caller must always pop the args.
5314 The attribute stdcall is equivalent to RTD on a per module basis. */
5316 static int
5318 {
5321 /* None of the 64-bit ABIs pop arguments. */
5332 /* Lose any fake structure return argument if it is passed on the stack. */
5335 {
5339 }
5342 }
5344 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5346 static bool
5348 {
5349 /* Check operand constraints in case hard registers were propagated
5350 into insn pattern. This check prevents combine pass from
5351 generating insn patterns with invalid hard register operands.
5352 These invalid insns can eventually confuse reload to error out
5353 with a spill failure. See also PRs 46829 and 46843. */
5355 {
5362 {
5370 /* A unary operator may be accepted by the predicate, but it
5371 is irrelevant for matching constraints. */
5376 {
5384 }
5391 /* Operand has no constraints, anything is OK. */
5395 {
5398 && operands_match_p
5402 {
5405 }
5406 }
5410 }
5411 }
5414 }
5415 \f
5416 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5418 static unsigned HOST_WIDE_INT
5420 {
5422 }
5423 \f
5424 /* Argument support functions. */
5426 /* Return true when register may be used to pass function parameters. */
5427 bool
5429 {
5434 {
5438 else
5444 }
5447 {
5450 }
5451 else
5452 {
5456 }
5458 /* TODO: The function should depend on current function ABI but
5459 builtins.c would need updating then. Therefore we use the
5460 default ABI. */
5462 /* RAX is used as hidden argument to va_arg functions. */
5468 else
5475 }
5477 /* Return if we do not know how to pass TYPE solely in registers. */
5479 static bool
5481 {
5485 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5486 The layout_type routine is crafty and tries to trick us into passing
5487 currently unsupported vector types on the stack by using TImode. */
5490 }
5492 /* It returns the size, in bytes, of the area reserved for arguments passed
5493 in registers for the function represented by fndecl dependent to the used
5494 abi format. */
5495 int
5497 {
5501 else
5506 }
5508 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5509 call abi used. */
5510 enum calling_abi
5512 {
5514 {
5517 {
5520 }
5524 }
5526 }
5528 static bool
5530 {
5532 {
5536 else
5538 }
5540 }
5542 static enum calling_abi
5544 {
5548 }
5550 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5551 call abi used. */
5552 enum calling_abi
5554 {
5558 }
5560 /* Write the extra assembler code needed to declare a function properly. */
5562 void
5564 tree decl)
5565 {
5569 {
5575 }
5577 #ifdef SUBTARGET_ASM_UNWIND_INIT
5579 #endif
5583 /* Output magic byte marker, if hot-patch attribute is set. */
5585 {
5587 {
5588 /* leaq [%rsp + 0], %rsp */
5591 }
5592 else
5593 {
5594 /* movl.s %edi, %edi
5595 push %ebp
5596 movl.s %esp, %ebp */
5599 }
5600 }
5601 }
5603 /* regclass.c */
5606 /* Implementation of call abi switching target hook. Specific to FNDECL
5607 the specific call register sets are set. See also
5608 ix86_conditional_register_usage for more details. */
5609 void
5611 {
5614 else
5616 }
5618 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5619 expensive re-initialization of init_regs each time we switch function context
5620 since this is needed only during RTL expansion. */
5621 static void
5623 {
5627 }
5629 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5630 for a call to a function whose data type is FNTYPE.
5631 For a library call, FNTYPE is 0. */
5633 void
5637 tree fndecl,
5639 {
5645 {
5648 }
5649 else
5650 {
5653 }
5657 /* Set up the number of registers to use for passing arguments. */
5664 {
5666 ? X86_64_REGPARM_MAX
5668 }
5670 {
5673 {
5675 ? X86_64_SSE_REGPARM_MAX
5677 }
5678 }
5685 /* Because type might mismatch in between caller and callee, we need to
5686 use actual type of function for local calls.
5687 FIXME: cgraph_analyze can be told to actually record if function uses
5688 va_start so for local functions maybe_vaarg can be made aggressive
5689 helping K&R code.
5690 FIXME: once typesytem is fixed, we won't need this code anymore. */
5698 {
5699 /* If there are variable arguments, then we won't pass anything
5700 in registers in 32-bit mode. */
5702 {
5710 }
5712 /* Use ecx and edx registers if function has fastcall attribute,
5713 else look for regparm information. */
5715 {
5718 {
5721 }
5723 {
5726 }
5727 else
5729 }
5731 /* Set up the number of SSE registers used for passing SFmode
5732 and DFmode arguments. Warn for mismatching ABI. */
5734 }
5735 }
5737 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5738 But in the case of vector types, it is some vector mode.
5740 When we have only some of our vector isa extensions enabled, then there
5741 are some modes for which vector_mode_supported_p is false. For these
5742 modes, the generic vector support in gcc will choose some non-vector mode
5743 in order to implement the type. By computing the natural mode, we'll
5744 select the proper ABI location for the operand and not depend on whatever
5745 the middle-end decides to do with these vector types.
5747 The midde-end can't deal with the vector types > 16 bytes. In this
5748 case, we return the original mode and warn ABI change if CUM isn't
5749 NULL. */
5751 static enum machine_mode
5753 {
5757 {
5760 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5762 {
5767 else
5770 /* Get the mode which has this inner mode and number of units. */
5774 {
5776 {
5780 && !warnedavx
5782 {
5786 }
5788 }
5790 {
5794 && !warnedsse
5796 {
5800 }
5802 }
5803 else
5805 }
5808 }
5809 }
5812 }
5814 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5815 this may not agree with the mode that the type system has chosen for the
5816 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5817 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5819 static rtx
5822 {
5823 rtx tmp;
5827 else
5828 {
5832 }
5835 }
5837 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5838 of this code is to classify each 8bytes of incoming argument by the register
5839 class and assign registers accordingly. */
5841 /* Return the union class of CLASS1 and CLASS2.
5842 See the x86-64 PS ABI for details. */
5844 static enum x86_64_reg_class
5846 {
5847 /* Rule #1: If both classes are equal, this is the resulting class. */
5851 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5852 the other class. */
5858 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5862 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5870 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5871 MEMORY is used. */
5880 /* Rule #6: Otherwise class SSE is used. */
5882 }
5884 /* Classify the argument of type TYPE and mode MODE.
5885 CLASSES will be filled by the register class used to pass each word
5886 of the operand. The number of words is returned. In case the parameter
5887 should be passed in memory, 0 is returned. As a special case for zero
5888 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5890 BIT_OFFSET is used internally for handling records and specifies offset
5891 of the offset in bits modulo 256 to avoid overflow cases.
5893 See the x86-64 PS ABI for details.
5894 */
5896 static int
5899 {
5900 HOST_WIDE_INT bytes =
5902 int words
5905 /* Variable sized entities are always passed/returned in memory. */
5913 /* Special case check for pointer to shared, on 64-bit target. */
5917 {
5920 }
5923 {
5925 tree field;
5928 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5935 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5936 signalize memory class, so handle it as special case. */
5938 {
5941 }
5943 /* Classify each field of record and merge classes. */
5945 {
5947 /* And now merge the fields of structure. */
5949 {
5951 {
5957 /* Bitfields are always classified as integer. Handle them
5958 early, since later code would consider them to be
5959 misaligned integers. */
5961 {
5970 }
5971 else
5972 {
5977 /* Flexible array member is ignored. */
5984 {
5988 {
5991 "the ABI of passing struct with"
5992 " a flexible array member has"
5994 }
5996 }
5998 subclasses,
6008 }
6009 }
6010 }
6014 /* Arrays are handled as small records. */
6015 {
6022 /* The partial classes are now full classes. */
6033 }
6036 /* Unions are similar to RECORD_TYPE but offset is always 0.
6037 */
6039 {
6041 {
6049 bit_offset);
6054 }
6055 }
6060 }
6063 {
6064 /* When size > 16 bytes, if the first one isn't
6065 X86_64_SSE_CLASS or any other ones aren't
6066 X86_64_SSEUP_CLASS, everything should be passed in
6067 memory. */
6074 }
6076 /* Final merger cleanup. */
6078 {
6079 /* If one class is MEMORY, everything should be passed in
6080 memory. */
6084 /* The X86_64_SSEUP_CLASS should be always preceded by
6085 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6089 {
6090 /* The first one should never be X86_64_SSEUP_CLASS. */
6093 }
6095 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6096 everything should be passed in memory. */
6099 {
6102 /* The first one should never be X86_64_X87UP_CLASS. */
6105 {
6108 "the ABI of passing union with long double"
6110 }
6112 }
6113 }
6115 }
6117 /* Compute alignment needed. We align all types to natural boundaries with
6118 exception of XFmode that is aligned to 64bits. */
6120 {
6129 /* Misaligned fields are always returned in memory. */
6132 }
6134 /* for V1xx modes, just use the base mode */
6139 /* Classification of atomic types. */
6141 {
6157 {
6161 {
6164 }
6166 {
6169 }
6171 {
6175 }
6177 {
6180 }
6181 else
6183 }
6190 /* OImode shouldn't be used directly. */
6197 else
6215 else
6216 {
6220 {
6223 "the ABI of passing structure with complex float"
6225 }
6228 }
6237 /* This modes is larger than 16 bytes. */
6280 else
6284 }
6285 }
6287 /* Examine the argument and return set number of register required in each
6288 class. Return 0 iff parameter should be passed in memory. */
6289 static int
6292 {
6302 {
6324 }
6326 }
6328 /* Construct container for the argument used by GCC interface. See
6329 FUNCTION_ARG for the detailed description. */
6331 static rtx
6335 {
6336 /* The following variables hold the static issued_error state. */
6350 rtx ret;
6361 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6362 some less clueful developer tries to use floating-point anyway. */
6364 {
6366 {
6368 {
6371 }
6372 }
6374 {
6377 }
6379 }
6381 /* Likewise, error if the ABI requires us to return values in the
6382 x87 registers and the user specified -mno-80387. */
6388 {
6390 {
6393 }
6395 }
6397 /* First construct simple cases. Avoid SCmode, since we want to use
6398 single register to pass this type. */
6401 {
6416 /* Zero sized array, struct or class. */
6420 }
6447 /* Otherwise figure out the entries of the PARALLEL. */
6449 {
6453 {
6458 /* Merge TImodes on aligned occasions here too. */
6460 tmpmode
6464 else
6466 /* We've requested 24 bytes we
6467 don't have mode for. Use DImode. */
6474 intreg++;
6482 sse_regno++;
6490 sse_regno++;
6495 {
6501 {
6503 i++;
6504 }
6505 else
6518 }
6524 sse_regno++;
6528 }
6529 }
6531 /* Empty aligned struct, union or class. */
6539 }
6541 /* Update the data in CUM to advance over an argument of mode MODE
6542 and data type TYPE. (TYPE is null for libcalls where that information
6543 may not be available.) */
6545 static void
6548 HOST_WIDE_INT words)
6549 {
6551 {
6558 /* FALLTHRU */
6569 {
6572 }
6576 /* OImode shouldn't be used directly. */
6585 /* FALLTHRU */
6601 {
6606 {
6609 }
6610 }
6620 {
6625 {
6628 }
6629 }
6631 }
6632 }
6634 static void
6637 {
6640 /* Unnamed 256bit vector mode parameters are passed on stack. */
6646 {
6651 }
6652 else
6653 {
6657 }
6658 }
6660 static void
6662 HOST_WIDE_INT words)
6663 {
6664 /* Otherwise, this should be passed indirect. */
6669 {
6672 }
6673 }
6675 /* Update the data in CUM to advance over an argument of mode MODE and
6676 data type TYPE. (TYPE is null for libcalls where that information
6677 may not be available.) */
6679 static void
6682 {
6688 else
6699 else
6701 }
6703 /* Define where to put the arguments to a function.
6704 Value is zero to push the argument on the stack,
6705 or a hard register in which to store the argument.
6707 MODE is the argument's machine mode.
6708 TYPE is the data type of the argument (as a tree).
6709 This is null for libcalls where that information may
6710 not be available.
6711 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6712 the preceding args and about the function being called.
6713 NAMED is nonzero if this argument is a named parameter
6714 (otherwise it is an extra parameter matching an ellipsis). */
6716 static rtx
6720 {
6723 /* Avoid the AL settings for the Unix64 ABI. */
6728 {
6735 /* FALLTHRU */
6741 {
6744 /* Fastcall allocates the first two DWORD (SImode) or
6745 smaller arguments to ECX and EDX if it isn't an
6746 aggregate type . */
6748 {
6754 /* ECX not EAX is the first allocated register. */
6757 }
6759 }
6768 /* FALLTHRU */
6770 /* In 32bit, we pass TImode in xmm registers. */
6778 {
6780 {
6784 }
6788 }
6792 /* OImode shouldn't be used directly. */
6802 {
6806 }
6816 {
6818 {
6822 }
6826 }
6828 }
6831 }
6833 static rtx
6836 {
6837 /* Handle a hidden AL argument containing number of registers
6838 for varargs x86-64 functions. */
6842 ? X86_64_SSE_REGPARM_MAX
6847 {
6857 /* Unnamed 256bit vector mode parameters are passed on stack. */
6861 }
6867 }
6869 static rtx
6872 HOST_WIDE_INT bytes)
6873 {
6876 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6877 We use value of -2 to specify that current function call is MSABI. */
6881 /* If we've run out of registers, it goes on the stack. */
6887 /* Only floating point modes are passed in anything but integer regs. */
6889 {
6892 else
6893 {
6896 /* Unnamed floating parameters are passed in both the
6897 SSE and integer registers. */
6903 }
6904 }
6905 /* Handle aggregated types passed in register. */
6907 {
6912 }
6915 }
6917 /* Return where to put the arguments to a function.
6918 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6920 MODE is the argument's machine mode. TYPE is the data type of the
6921 argument. It is null for libcalls where that information may not be
6922 available. CUM gives information about the preceding args and about
6923 the function being called. NAMED is nonzero if this argument is a
6924 named parameter (otherwise it is an extra parameter matching an
6925 ellipsis). */
6927 static rtx
6930 {
6934 rtx arg;
6938 else
6942 /* To simplify the code below, represent vector types with a vector mode
6943 even if MMX/SSE are not active. */
6951 else
6955 }
6957 /* A C expression that indicates when an argument must be passed by
6958 reference. If nonzero for an argument, a copy of that argument is
6959 made in memory and a pointer to the argument is passed instead of
6960 the argument itself. The pointer is passed in whatever way is
6961 appropriate for passing a pointer to that type. */
6963 static bool
6967 {
6970 /* See Windows x64 Software Convention. */
6972 {
6975 {
6976 /* Arrays are passed by reference. */
6981 {
6982 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6983 are passed by reference. */
6985 }
6986 }
6988 /* __m128 is passed by reference. */
6994 }
6995 }
7000 }
7002 /* Return true when TYPE should be 128bit aligned for 32bit argument
7003 passing ABI. XXX: This function is obsolete and is only used for
7004 checking psABI compatibility with previous versions of GCC. */
7006 static bool
7008 {
7020 {
7021 /* Walk the aggregates recursively. */
7023 {
7027 {
7028 tree field;
7030 /* Walk all the structure fields. */
7032 {
7036 }
7038 }
7041 /* Just for use if some languages passes arrays by value. */
7048 }
7049 }
7051 }
7053 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7054 XXX: This function is obsolete and is only used for checking psABI
7055 compatibility with previous versions of GCC. */
7057 static unsigned int
7060 {
7061 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7062 natural boundaries. */
7064 {
7065 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7066 make an exception for SSE modes since these require 128bit
7067 alignment.
7069 The handling here differs from field_alignment. ICC aligns MMX
7070 arguments to 4 byte boundaries, while structure fields are aligned
7071 to 8 byte boundaries. */
7073 {
7076 }
7077 else
7078 {
7081 }
7082 }
7086 }
7088 /* Return true when TYPE should be 128bit aligned for 32bit argument
7089 passing ABI. */
7091 static bool
7093 {
7103 {
7104 /* Walk the aggregates recursively. */
7106 {
7110 {
7111 tree field;
7113 /* Walk all the structure fields. */
7115 field;
7117 {
7121 }
7123 }
7126 /* Just for use if some languages passes arrays by value. */
7133 }
7134 }
7135 else
7139 }
7141 /* Gives the alignment boundary, in bits, of an argument with the
7142 specified mode and type. */
7144 static unsigned int
7146 {
7149 {
7150 /* Since the main variant type is used for call, we convert it to
7151 the main variant type. */
7154 }
7155 else
7159 else
7160 {
7165 {
7166 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7168 {
7171 }
7177 }
7180 && !warned
7182 saved_align))
7183 {
7186 "The ABI for passing parameters with %d-byte"
7189 }
7190 }
7193 }
7195 /* Return true if N is a possible register number of function value. */
7197 static bool
7199 {
7201 {
7206 /* TODO: The function should depend on current function ABI but
7207 builtins.c would need updating then. Therefore we use the
7208 default ABI. */
7220 }
7223 }
7225 /* Define how to find the value returned by a function.
7226 VALTYPE is the data type of the value (as a tree).
7227 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7228 otherwise, FUNC is 0. */
7230 static rtx
7233 {
7236 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7237 we normally prevent this case when mmx is not available. However
7238 some ABIs may require the result to be returned like DImode. */
7242 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7243 we prevent this case when sse is not available. However some ABIs
7244 may require the result to be returned like integer TImode. */
7249 /* 32-byte vector modes in %ymm0. */
7253 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7256 else
7257 /* Most things go in %eax. */
7260 /* Override FP return register with %xmm0 for local functions when
7261 SSE math is enabled or for functions with sseregparm attribute. */
7263 {
7268 }
7270 /* OImode shouldn't be used directly. */
7274 }
7276 static rtx
7278 const_tree valtype)
7279 {
7280 rtx ret;
7282 /* Handle libcalls, which don't provide a type node. */
7284 {
7288 {
7307 }
7310 }
7313 {
7314 /* Pointers are always returned in word_mode. */
7316 }
7322 /* For zero sized structures, construct_container returns NULL, but we
7323 need to keep rest of compiler happy by returning meaningful value. */
7328 }
7330 static rtx
7332 {
7336 {
7338 {
7351 }
7352 }
7354 }
7356 static rtx
7359 {
7371 else
7373 }
7375 static rtx
7378 {
7384 }
7386 /* Pointer function arguments and return values are promoted to
7387 word_mode. */
7389 static enum machine_mode
7393 {
7395 {
7397 {
7400 }
7403 }
7405 for_return);
7406 }
7408 /* Return true if a structure, union or array with MODE containing FIELD
7409 should be accessed using BLKmode. */
7411 static bool
7413 {
7414 /* Union with XFmode must be in BLKmode. */
7418 }
7420 rtx
7422 {
7424 }
7426 /* Return true iff type is returned in memory. */
7428 static bool ATTRIBUTE_UNUSED
7430 {
7431 HOST_WIDE_INT size;
7442 {
7443 /* User-created vectors small enough to fit in EAX. */
7447 /* MMX/3dNow values are returned in MM0,
7448 except when it doesn't exits or the ABI prescribes otherwise. */
7452 /* SSE values are returned in XMM0, except when it doesn't exist. */
7456 /* AVX values are returned in YMM0, except when it doesn't exist. */
7459 }
7467 /* OImode shouldn't be used directly. */
7471 }
7473 static bool ATTRIBUTE_UNUSED
7475 {
7478 }
7480 static bool ATTRIBUTE_UNUSED
7482 {
7485 /* __m128 is returned in xmm0. */
7490 /* Otherwise, the size must be exactly in [1248]. */
7492 }
7494 static bool
7496 {
7497 #ifdef SUBTARGET_RETURN_IN_MEMORY
7499 #else
7503 {
7506 else
7508 }
7509 else
7511 #endif
7512 }
7514 /* When returning SSE vector types, we have a choice of either
7515 (1) being abi incompatible with a -march switch, or
7516 (2) generating an error.
7517 Given no good solution, I think the safest thing is one warning.
7518 The user won't be able to use -Werror, but....
7520 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7521 called in response to actually generating a caller or callee that
7522 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7523 via aggregate_value_p for general type probing from tree-ssa. */
7525 static rtx
7527 {
7531 {
7532 /* Look at the return type of the function, not the function type. */
7536 {
7539 {
7543 }
7544 }
7547 {
7549 {
7553 }
7554 }
7555 }
7558 }
7560 \f
7561 /* Create the va_list data type. */
7563 /* Returns the calling convention specific va_list date type.
7564 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7566 static tree
7568 {
7571 /* For i386 we use plain pointer to argument area. */
7581 unsigned_type_node);
7584 unsigned_type_node);
7587 ptr_type_node);
7590 ptr_type_node);
7609 /* The correct type is an array type of one element. */
7611 }
7613 /* Setup the builtin va_list data type and for 64-bit the additional
7614 calling convention specific va_list data types. */
7616 static tree
7618 {
7621 /* Initialize abi specific va_list builtin types. */
7623 {
7624 tree t;
7626 {
7631 }
7632 else
7633 {
7638 }
7640 {
7645 }
7646 else
7647 {
7652 }
7653 }
7656 }
7658 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7660 static void
7662 {
7664 alias_set_type set;
7667 /* GPR size of varargs save area. */
7670 else
7673 /* FPR size of varargs save area. We don't need it if we don't pass
7674 anything in SSE registers. */
7677 else
7691 {
7699 }
7702 {
7706 /* Now emit code to save SSE registers. The AX parameter contains number
7707 of SSE parameter registers used to call this function, though all we
7708 actually check here is the zero/non-zero status. */
7713 label));
7715 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7716 we used movdqa (i.e. TImode) instead? Perhaps even better would
7717 be if we could determine the real mode of the data, via a hook
7718 into pass_stdarg. Ignore all that for now. */
7728 {
7737 }
7740 }
7741 }
7743 static void
7745 {
7749 /* Reset to zero, as there might be a sysv vaarg used
7750 before. */
7755 {
7766 }
7767 }
7769 static void
7773 {
7775 CUMULATIVE_ARGS next_cum;
7776 tree fntype;
7778 /* This argument doesn't appear to be used anymore. Which is good,
7779 because the old code here didn't suppress rtl generation. */
7787 /* For varargs, we do not want to skip the dummy va_dcl argument.
7788 For stdargs, we do want to skip the last named argument. */
7796 else
7798 }
7800 /* Checks if TYPE is of kind va_list char *. */
7802 static bool
7804 {
7805 tree canonic;
7807 /* For 32-bit it is always true. */
7813 }
7815 /* Implement va_start. */
7817 static void
7819 {
7823 tree type;
7824 rtx ovf_rtx;
7828 {
7831 /* When we are splitting the stack, we can't refer to the stack
7832 arguments using internal_arg_pointer, because they may be on
7833 the old stack. The split stack prologue will arrange to
7834 leave a pointer to the old stack arguments in a scratch
7835 register, which we here copy to a pseudo-register. The split
7836 stack prologue can't set the pseudo-register directly because
7837 it (the prologue) runs before any registers have been saved. */
7841 {
7855 }
7856 }
7858 /* Only 64bit target needs something special. */
7860 {
7863 else
7864 {
7873 }
7875 }
7884 /* The following should be folded into the MEM_REF offset. */
7894 /* Count number of gp and fp argument registers used. */
7900 {
7906 }
7909 {
7915 }
7917 /* Find the overflow area. */
7921 else
7931 {
7932 /* Find the register save area.
7933 Prologue of the function save it right above stack frame. */
7941 }
7942 }
7944 /* Implement va_arg. */
7946 static tree
7949 {
7956 rtx container;
7958 tree ptrtype;
7962 /* Only 64bit target needs something special. */
7986 {
7993 /* Unnamed 256bit vector mode parameters are passed on stack. */
7995 {
7998 }
8006 }
8008 /* Pull the value out of the saved registers. */
8013 {
8027 /* In case we are passing structure, verify that it is consecutive block
8028 on the register save area. If not we need to do moves. */
8030 {
8031 /* Verify that all registers are strictly consecutive */
8033 {
8037 {
8042 }
8043 }
8044 else
8045 {
8049 {
8054 }
8055 }
8056 }
8058 {
8061 }
8062 else
8063 {
8066 }
8068 /* First ensure that we fit completely in registers. */
8070 {
8077 }
8079 {
8087 }
8089 /* Compute index to start of area used for integer regs. */
8091 {
8092 /* int_addr = gpr + sav; */
8095 }
8097 {
8098 /* sse_addr = fpr + sav; */
8101 }
8103 {
8107 /* addr = &temp; */
8112 {
8116 tree piece_type;
8117 tree addr_type;
8118 tree daddr_type;
8127 {
8132 }
8136 else
8143 {
8146 }
8147 else
8148 {
8151 }
8158 {
8163 }
8164 else
8165 {
8166 tree copy
8171 }
8173 }
8174 }
8177 {
8181 }
8184 {
8188 }
8193 }
8195 /* ... otherwise out of the overflow area. */
8197 /* When we align parameter on stack for caller, if the parameter
8198 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8199 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8200 here with caller. */
8205 /* Care for on-stack alignment if needed. */
8208 else
8209 {
8214 }
8231 }
8232 \f
8233 /* Return true if OPNUM's MEM should be matched
8234 in movabs* patterns. */
8236 bool
8238 {
8250 }
8251 \f
8252 /* Initialize the table of extra 80387 mathematical constants. */
8254 static void
8256 {
8258 {
8264 };
8268 {
8270 /* Ensure each constant is rounded to XFmode precision. */
8273 }
8276 }
8278 /* Return non-zero if the constant is something that
8279 can be loaded with a special instruction. */
8281 int
8283 {
8286 REAL_VALUE_TYPE r;
8298 /* For XFmode constants, try to find a special 80387 instruction when
8299 optimizing for size or on those CPUs that benefit from them. */
8302 {
8311 }
8313 /* Load of the constant -0.0 or -1.0 will be split as
8314 fldz;fchs or fld1;fchs sequence. */
8321 }
8323 /* Return the opcode of the special instruction to be used to load
8324 the constant X. */
8328 {
8330 {
8350 }
8351 }
8353 /* Return the CONST_DOUBLE representing the 80387 constant that is
8354 loaded by the specified special instruction. The argument IDX
8355 matches the return value from standard_80387_constant_p. */
8357 rtx
8359 {
8366 {
8377 }
8380 XFmode);
8381 }
8383 /* Return 1 if X is all 0s and 2 if x is all 1s
8384 in supported SSE/AVX vector mode. */
8386 int
8388 {
8395 {
8410 }
8413 }
8415 /* Return the opcode of the special instruction to be used to load
8416 the constant X. */
8420 {
8422 {
8425 {
8442 }
8447 else
8452 }
8454 }
8456 /* Returns true if OP contains a symbol reference */
8458 bool
8460 {
8469 {
8471 {
8477 }
8481 }
8484 }
8486 /* Return true if it is appropriate to emit `ret' instructions in the
8487 body of a function. Do this only if the epilogue is simple, needing a
8488 couple of insns. Prior to reloading, we can't tell how many registers
8489 must be saved, so return false then. Return false if there is no frame
8490 marker to de-allocate. */
8492 bool
8494 {
8500 /* Don't allow more than 32k pop, since that's all we can do
8501 with one instruction. */
8508 }
8509 \f
8510 /* Value should be nonzero if functions must have frame pointers.
8511 Zero means the frame pointer need not be set up (and parms may
8512 be accessed via the stack pointer) in functions that seem suitable. */
8514 static bool
8516 {
8517 /* If we accessed previous frames, then the generated code expects
8518 to be able to access the saved ebp value in our frame. */
8522 /* Several x86 os'es need a frame pointer for other reasons,
8523 usually pertaining to setjmp. */
8527 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8531 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8532 allocation is 4GB. */
8536 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8537 turns off the frame pointer by default. Turn it back on now if
8538 we've not got a leaf function. */
8548 }
8550 /* Record that the current function accesses previous call frames. */
8552 void
8554 {
8556 }
8557 \f
8558 #ifndef USE_HIDDEN_LINKONCE
8559 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8560 # define USE_HIDDEN_LINKONCE 1
8561 # else
8562 # define USE_HIDDEN_LINKONCE 0
8563 # endif
8564 #endif
8568 /* Fills in the label name that should be used for a pc thunk for
8569 the given register. */
8571 static void
8573 {
8578 else
8580 }
8583 /* This function generates code for -fpic that loads %ebx with
8584 the return address of the caller and then returns. */
8586 static void
8588 {
8593 {
8595 tree decl;
8611 #if TARGET_MACHO
8613 {
8622 }
8623 else
8624 #endif
8626 {
8637 }
8638 else
8639 {
8642 }
8648 /* Make sure unwind info is emitted for the thunk if needed. */
8651 /* Pad stack IP move with 4 instructions (two NOPs count
8652 as one instruction). */
8654 {
8659 }
8670 }
8674 }
8676 /* Emit code for the SET_GOT patterns. */
8680 {
8686 {
8687 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8692 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8693 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8694 an unadorned address. */
8699 }
8704 {
8709 #if TARGET_MACHO
8710 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8711 is what will be referenced by the Mach-O PIC subsystem. */
8714 #endif
8718 }
8719 else
8720 {
8728 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8729 is what will be referenced by the Mach-O PIC subsystem. */
8730 #if TARGET_MACHO
8733 else
8736 #endif
8737 }
8743 }
8745 /* Generate an "push" pattern for input ARG. */
8747 static rtx
8749 {
8762 stack_pointer_rtx)),
8763 arg);
8764 }
8766 /* Generate an "pop" pattern for input ARG. */
8768 static rtx
8770 {
8775 arg,
8778 stack_pointer_rtx)));
8779 }
8781 /* Return >= 0 if there is an unused call-clobbered register available
8782 for the entire function. */
8784 static unsigned int
8786 {
8790 {
8792 /* Can't use the same register for both PIC and DRAP. */
8795 else
8800 }
8803 }
8805 /* Return TRUE if we need to save REGNO. */
8807 static bool
8809 {
8819 {
8822 {
8828 }
8829 }
8838 }
8840 /* Return number of saved general prupose registers. */
8842 static int
8844 {
8850 nregs ++;
8852 }
8854 /* Return number of saved SSE registrers. */
8856 static int
8858 {
8866 nregs ++;
8868 }
8870 /* Given FROM and TO register numbers, say whether this elimination is
8871 allowed. If stack alignment is needed, we can only replace argument
8872 pointer with hard frame pointer, or replace frame pointer with stack
8873 pointer. Otherwise, frame pointer elimination is automatically
8874 handled and all other eliminations are valid. */
8876 static bool
8878 {
8884 else
8886 }
8888 /* Return the offset between two registers, one to be eliminated, and the other
8889 its replacement, at the start of a routine. */
8891 HOST_WIDE_INT
8893 {
8902 else
8903 {
8911 }
8912 }
8914 /* In a dynamically-aligned function, we can't know the offset from
8915 stack pointer to frame pointer, so we must ensure that setjmp
8916 eliminates fp against the hard fp (%ebp) rather than trying to
8917 index from %esp up to the top of the frame across a gap that is
8918 of unknown (at compile-time) size. */
8919 static rtx
8921 {
8923 }
8925 /* When using -fsplit-stack, the allocation routines set a field in
8926 the TCB to the bottom of the stack plus this much space, measured
8927 in bytes. */
8929 #define SPLIT_STACK_AVAILABLE 256
8931 /* Fill structure ix86_frame about frame of currently computed function. */
8933 static void
8935 {
8937 HOST_WIDE_INT offset;
8940 HOST_WIDE_INT to_allocate;
8948 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8949 function prologues and leaf. */
8953 {
8958 }
8964 /* For SEH we have to limit the amount of code movement into the prologue.
8965 At present we do this via a BLOCKAGE, at which point there's very little
8966 scheduling that can be done, which means that there's very little point
8967 in doing anything except PUSHs. */
8971 /* During reload iteration the amount of registers saved can change.
8972 Recompute the value as needed. Do not recompute when amount of registers
8973 didn't change as reload does multiple calls to the function and does not
8974 expect the decision to change within single iteration. */
8977 {
8983 /* The fast prologue uses move instead of push to save registers. This
8984 is significantly longer, but also executes faster as modern hardware
8985 can execute the moves in parallel, but can't do that for push/pop.
8987 Be careful about choosing what prologue to emit: When function takes
8988 many instructions to execute we may use slow version as well as in
8989 case function is known to be outside hot spot (this is known with
8990 feedback only). Weight the size of function by number of registers
8991 to save as it is cheap to use one or two push instructions but very
8992 slow to use many of them. */
8996 || (flag_branch_probabilities
8999 else
9002 }
9004 frame->save_regs_using_mov
9006 /* If static stack checking is enabled and done with probes,
9007 the registers need to be saved before allocating the frame. */
9010 /* Skip return address. */
9013 /* Skip pushed static chain. */
9017 /* Skip saved base pointer. */
9022 /* The traditional frame pointer location is at the top of the frame. */
9025 /* Register save area */
9029 /* On SEH target, registers are pushed just before the frame pointer
9030 location. */
9034 /* Align and set SSE register save area. */
9036 {
9037 /* The only ABI that has saved SSE registers (Win64) also has a
9038 16-byte aligned default stack, and thus we don't need to be
9039 within the re-aligned local stack frame to save them. */
9043 }
9046 /* The re-aligned stack starts here. Values before this point are not
9047 directly comparable with values below this point. In order to make
9048 sure that no value happens to be the same before and after, force
9049 the alignment computation below to add a non-zero value. */
9053 /* Va-arg area */
9057 /* Align start of frame for local function. */
9066 /* Frame pointer points here. */
9071 /* Add outgoing arguments area. Can be skipped if we eliminated
9072 all the function calls as dead code.
9073 Skipping is however impossible when function calls alloca. Alloca
9074 expander assumes that last crtl->outgoing_args_size
9075 of stack frame are unused. */
9079 {
9082 }
9083 else
9086 /* Align stack boundary. Only needed if we're calling another function
9087 or using alloca. */
9092 /* We've reached end of stack frame. */
9095 /* Size prologue needs to allocate. */
9106 {
9112 }
9113 else
9117 /* The SEH frame pointer location is near the bottom of the frame.
9118 This is enforced by the fact that the difference between the
9119 stack pointer and the frame pointer is limited to 240 bytes in
9120 the unwind data structure. */
9122 {
9123 HOST_WIDE_INT diff;
9125 /* If we can leave the frame pointer where it is, do so. Also, returns
9126 the establisher frame for __builtin_frame_address (0). */
9131 {
9132 /* Ideally we'd determine what portion of the local stack frame
9133 (within the constraint of the lowest 240) is most heavily used.
9134 But without that complication, simply bias the frame pointer
9135 by 128 bytes so as to maximize the amount of the local stack
9136 frame that is addressable with 8-bit offsets. */
9138 }
9139 }
9140 }
9142 /* This is semi-inlined memory_address_length, but simplified
9143 since we know that we're always dealing with reg+offset, and
9144 to avoid having to create and discard all that rtl. */
9148 {
9152 {
9153 /* EBP and R13 cannot be encoded without an offset. */
9155 }
9159 /* ESP and R12 must be encoded with a SIB byte. */
9161 len++;
9164 }
9166 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9167 The valid base registers are taken from CFUN->MACHINE->FS. */
9169 static rtx
9171 {
9177 {
9178 /* Choose the base register most likely to allow the most scheduling
9179 opportunities. Generally FP is valid throughout the function,
9180 while DRAP must be reloaded within the epilogue. But choose either
9181 over the SP due to increased encoding size. */
9184 {
9187 }
9189 {
9192 }
9194 {
9197 }
9198 }
9199 else
9200 {
9201 HOST_WIDE_INT toffset;
9204 /* Choose the base register with the smallest address encoding.
9205 With a tie, choose FP > DRAP > SP. */
9207 {
9211 }
9213 {
9217 {
9221 }
9222 }
9224 {
9228 {
9232 }
9233 }
9234 }
9238 }
9240 /* Emit code to save registers in the prologue. */
9242 static void
9244 {
9246 rtx insn;
9250 {
9253 }
9254 }
9256 /* Emit a single register save at CFA - CFA_OFFSET. */
9258 static void
9260 HOST_WIDE_INT cfa_offset)
9261 {
9269 /* For SSE saves, we need to indicate the 128-bit alignment. */
9280 /* When saving registers into a re-aligned local stack frame, avoid
9281 any tricky guessing by dwarf2out. */
9283 {
9287 {
9288 /* A bit of a hack. We force the DRAP register to be saved in
9289 the re-aligned stack frame, which provides us with a copy
9290 of the CFA that will last past the prologue. Install it. */
9296 }
9297 else
9298 {
9299 /* The frame pointer is a stable reference within the
9300 aligned frame. Use it. */
9307 }
9308 }
9310 /* The memory may not be relative to the current CFA register,
9311 which means that we may need to generate a new pattern for
9312 use by the unwind info. */
9314 {
9319 }
9320 }
9322 /* Emit code to save registers using MOV insns.
9323 First register is stored at CFA - CFA_OFFSET. */
9324 static void
9326 {
9331 {
9334 }
9335 }
9337 /* Emit code to save SSE registers using MOV insns.
9338 First register is stored at CFA - CFA_OFFSET. */
9339 static void
9341 {
9346 {
9349 }
9350 }
9354 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9355 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9356 Don't add the note if the previously saved value will be left untouched
9357 within stack red-zone till return, as unwinders can find the same value
9358 in the register and on the stack. */
9360 static void
9362 {
9368 {
9371 }
9372 else
9373 queued_cfa_restores
9375 }
9377 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9379 static void
9381 {
9382 rtx last;
9386 ;
9391 }
9393 /* Expand prologue or epilogue stack adjustment.
9394 The pattern exist to put a dependency on all ebp-based memory accesses.
9395 STYLE should be negative if instructions should be marked as frame related,
9396 zero if %r11 register is live and cannot be freely used and positive
9397 otherwise. */
9399 static void
9402 {
9404 rtx insn;
9411 else
9412 {
9413 rtx tmp;
9414 /* r11 is used by indirect sibcall return as well, set before the
9415 epilogue and used after the epilogue. */
9418 else
9419 {
9423 }
9429 }
9436 {
9437 rtx r;
9447 }
9449 {
9452 {
9456 }
9457 }
9460 {
9465 {
9468 }
9470 {
9473 }
9474 else
9475 {
9476 /* Else there are two possibilities: SP itself, which we set
9477 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9478 taken care of this by hand along the eh_return path. */
9481 }
9485 }
9486 }
9488 /* Find an available register to be used as dynamic realign argument
9489 pointer regsiter. Such a register will be written in prologue and
9490 used in begin of body, so it must not be
9491 1. parameter passing register.
9492 2. GOT pointer.
9493 We reuse static-chain register if it is available. Otherwise, we
9494 use DI for i386 and R13 for x86-64. We chose R13 since it has
9495 shorter encoding.
9497 Return: the regno of chosen register. */
9499 static unsigned int
9501 {
9505 {
9506 /* Use R13 for nested function or function need static chain.
9507 Since function with tail call may use any caller-saved
9508 registers in epilogue, DRAP must not use caller-saved
9509 register in such case. */
9514 }
9515 else
9516 {
9517 /* Use DI for nested function or function need static chain.
9518 Since function with tail call may use any caller-saved
9519 registers in epilogue, DRAP must not use caller-saved
9520 register in such case. */
9524 /* Reuse static chain register if it isn't used for parameter
9525 passing. */
9527 {
9531 }
9533 }
9534 }
9536 /* Return minimum incoming stack alignment. */
9538 static unsigned int
9540 {
9543 /* Prefer the one specified at command line. */
9546 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9547 if -mstackrealign is used, it isn't used for sibcall check and
9548 estimated stack alignment is 128bit. */
9550 && !TARGET_64BIT
9551 && ix86_force_align_arg_pointer
9554 else
9557 /* Incoming stack alignment can be changed on individual functions
9558 via force_align_arg_pointer attribute. We use the smallest
9559 incoming stack boundary. */
9565 /* The incoming stack frame has to be aligned at least at
9566 parm_stack_boundary. */
9570 /* Stack at entrance of main is aligned by runtime. We use the
9571 smallest incoming stack boundary. */
9579 }
9581 /* Update incoming stack boundary and estimated stack alignment. */
9583 static void
9585 {
9586 ix86_incoming_stack_boundary
9589 /* x86_64 vararg needs 16byte stack alignment for register save
9590 area. */
9595 }
9597 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9598 needed or an rtx for DRAP otherwise. */
9600 static rtx
9602 {
9607 {
9608 /* Assign DRAP to vDRAP and returns vDRAP */
9610 rtx drap_vreg;
9611 rtx arg_ptr;
9624 {
9627 }
9629 }
9630 else
9632 }
9634 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9636 static rtx
9638 {
9640 }
9643 rtx reg;
9645 };
9647 /* Return a short-lived scratch register for use on function entry.
9648 In 32-bit mode, it is valid only after the registers are saved
9649 in the prologue. This register must be released by means of
9650 release_scratch_register_on_entry once it is dead. */
9652 static void
9654 {
9660 {
9661 /* We always use R11 in 64-bit mode. */
9663 }
9664 else
9665 {
9667 bool fastcall_p
9669 bool thiscall_p
9673 int drap_regno
9676 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9677 for the static chain register. */
9681 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9682 for the static chain register. */
9687 /* ecx is the static chain register. */
9689 && !static_chain_p
9694 /* esi is the static chain register. */
9700 else
9701 {
9704 }
9705 }
9709 {
9712 }
9713 }
9715 /* Release a scratch register obtained from the preceding function. */
9717 static void
9719 {
9721 {
9725 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9731 }
9732 }
9734 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9736 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9738 static void
9740 {
9741 /* We skip the probe for the first interval + a small dope of 4 words and
9742 probe that many bytes past the specified size to maintain a protection
9743 area at the botton of the stack. */
9747 /* See if we have a constant small number of probes to generate. If so,
9748 that's the easy case. The run-time loop is made up of 11 insns in the
9749 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9750 for n # of intervals. */
9752 {
9756 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9757 values of N from 1 until it exceeds SIZE. If only one probe is
9758 needed, this will not generate any code. Then adjust and probe
9759 to PROBE_INTERVAL + SIZE. */
9761 {
9763 {
9766 }
9767 else
9774 }
9778 else
9786 /* Adjust back to account for the additional first interval. */
9790 }
9792 /* Otherwise, do the same as above, but in a loop. Note that we must be
9793 extra careful with variables wrapping around because we might be at
9794 the very top (or the very bottom) of the address space and we have
9795 to be able to handle this case properly; in particular, we use an
9796 equality test for the loop condition. */
9797 else
9798 {
9799 HOST_WIDE_INT rounded_size;
9805 /* Step 1: round SIZE to the previous multiple of the interval. */
9810 /* Step 2: compute initial and final value of the loop counter. */
9812 /* SP = SP_0 + PROBE_INTERVAL. */
9817 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9821 stack_pointer_rtx)));
9824 /* Step 3: the loop
9826 while (SP != LAST_ADDR)
9827 {
9828 SP = SP + PROBE_INTERVAL
9829 probe at SP
9830 }
9832 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9833 values of N from 1 until it is equal to ROUNDED_SIZE. */
9838 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9839 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9842 {
9847 }
9849 /* Adjust back to account for the additional first interval. */
9855 }
9859 /* Even if the stack pointer isn't the CFA register, we need to correctly
9860 describe the adjustments made to it, in particular differentiate the
9861 frame-related ones from the frame-unrelated ones. */
9863 {
9876 }
9878 /* Make sure nothing is scheduled before we are done. */
9880 }
9882 /* Adjust the stack pointer up to REG while probing it. */
9886 {
9896 /* Jump to END_LAB if SP == LAST_ADDR. */
9904 /* SP = SP + PROBE_INTERVAL. */
9908 /* Probe at SP. */
9919 }
9921 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9922 inclusive. These are offsets from the current stack pointer. */
9924 static void
9926 {
9927 /* See if we have a constant small number of probes to generate. If so,
9928 that's the easy case. The run-time loop is made up of 7 insns in the
9929 generic case while the compile-time loop is made up of n insns for n #
9930 of intervals. */
9932 {
9933 HOST_WIDE_INT i;
9935 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9936 it exceeds SIZE. If only one probe is needed, this will not
9937 generate any code. Then probe at FIRST + SIZE. */
9944 }
9946 /* Otherwise, do the same as above, but in a loop. Note that we must be
9947 extra careful with variables wrapping around because we might be at
9948 the very top (or the very bottom) of the address space and we have
9949 to be able to handle this case properly; in particular, we use an
9950 equality test for the loop condition. */
9951 else
9952 {
9959 /* Step 1: round SIZE to the previous multiple of the interval. */
9964 /* Step 2: compute initial and final value of the loop counter. */
9966 /* TEST_OFFSET = FIRST. */
9969 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9973 /* Step 3: the loop
9975 while (TEST_ADDR != LAST_ADDR)
9976 {
9977 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9978 probe at TEST_ADDR
9979 }
9981 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9982 until it is equal to ROUNDED_SIZE. */
9987 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
9988 that SIZE is equal to ROUNDED_SIZE. */
9993 stack_pointer_rtx,
9998 }
10000 /* Make sure nothing is scheduled before we are done. */
10002 }
10004 /* Probe a range of stack addresses from REG to END, inclusive. These are
10005 offsets from the current stack pointer. */
10009 {
10019 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10027 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10031 /* Probe at TEST_ADDR. */
10044 }
10046 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10047 to be generated in correct form. */
10048 static void
10050 {
10051 /* Check if stack realign is really needed after reload, and
10052 stores result in cfun */
10053 unsigned int incoming_stack_boundary
10062 {
10063 /* After stack_realign_needed is finalized, we can't no longer
10064 change it. */
10067 }
10069 /* If the only reason for frame_pointer_needed is that we conservatively
10070 assumed stack realignment might be needed, but in the end nothing that
10071 needed the stack alignment had been spilled, clear frame_pointer_needed
10072 and say we don't need stack realignment. */
10075 && frame_pointer_needed
10077 && flag_omit_frame_pointer
10079 && !ix86_current_function_calls_tls_descriptor
10088 {
10090 basic_block bb;
10097 HARD_FRAME_POINTER_REGNUM);
10099 {
10100 rtx insn;
10104 set_up_by_prologue))
10105 {
10109 }
10110 }
10124 }
10128 }
10130 /* Expand the prologue into a bunch of separate insns. */
10132 void
10134 {
10139 HOST_WIDE_INT allocate;
10145 /* DRAP should not coexist with stack_realign_fp */
10150 /* Initialize CFA state for before the prologue. */
10154 /* Track SP offset to the CFA. We continue tracking this after we've
10155 swapped the CFA register away from SP. In the case of re-alignment
10156 this is fudged; we're interested to offsets within the local frame. */
10163 {
10164 /* We should have already generated an error for any use of
10165 ms_hook on a nested function. */
10168 /* Check if profiling is active and we shall use profiling before
10169 prologue variant. If so sorry. */
10174 /* In ix86_asm_output_function_label we emitted:
10175 8b ff movl.s %edi,%edi
10176 55 push %ebp
10177 8b ec movl.s %esp,%ebp
10179 This matches the hookable function prologue in Win32 API
10180 functions in Microsoft Windows XP Service Pack 2 and newer.
10181 Wine uses this to enable Windows apps to hook the Win32 API
10182 functions provided by Wine.
10184 What that means is that we've already set up the frame pointer. */
10188 {
10191 /* We've decided to use the frame pointer already set up.
10192 Describe this to the unwinder by pretending that both
10193 push and mov insns happen right here.
10195 Putting the unwind info here at the end of the ms_hook
10196 is done so that we can make absolutely certain we get
10197 the required byte sequence at the start of the function,
10198 rather than relying on an assembler that can produce
10199 the exact encoding required.
10201 However it does mean (in the unpatched case) that we have
10202 a 1 insn window where the asynchronous unwind info is
10203 incorrect. However, if we placed the unwind info at
10204 its correct location we would have incorrect unwind info
10205 in the patched case. Which is probably all moot since
10206 I don't expect Wine generates dwarf2 unwind info for the
10207 system libraries that use this feature. */
10213 stack_pointer_rtx);
10221 /* Note that gen_push incremented m->fs.cfa_offset, even
10222 though we didn't emit the push insn here. */
10226 }
10227 else
10228 {
10229 /* The frame pointer is not needed so pop %ebp again.
10230 This leaves us with a pristine state. */
10232 }
10233 }
10235 /* The first insn of a function that accepts its static chain on the
10236 stack is to push the register that would be filled in by a direct
10237 call. This insn will be skipped by the trampoline. */
10239 {
10243 /* We don't want to interpret this push insn as a register save,
10244 only as a stack adjustment. The real copy of the register as
10245 a save will be done later, if needed. */
10250 }
10252 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10253 of DRAP is needed and stack realignment is really needed after reload */
10255 {
10258 /* Only need to push parameter pointer reg if it is caller saved. */
10260 {
10261 /* Push arg pointer reg */
10264 }
10266 /* Grab the argument pointer. */
10273 /* Align the stack. */
10275 stack_pointer_rtx,
10279 /* Replicate the return address on the stack so that return
10280 address can be reached via (argp - 1) slot. This is needed
10281 to implement macro RETURN_ADDR_RTX and intrinsic function
10282 expand_builtin_return_addr etc. */
10288 /* For the purposes of frame and register save area addressing,
10289 we've started over with a new frame. */
10292 }
10298 {
10299 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10300 slower on all targets. Also sdb doesn't like it. */
10304 /* Push registers now, before setting the frame pointer
10305 on SEH target. */
10307 && TARGET_SEH
10309 {
10313 }
10316 {
10324 }
10325 }
10328 {
10329 /* If saving registers via PUSH, do so now. */
10331 {
10335 }
10337 /* When using red zone we may start register saving before allocating
10338 the stack frame saving one cycle of the prologue. However, avoid
10339 doing this if we have to probe the stack; at least on x86_64 the
10340 stack probe can turn into a call that clobbers a red zone location. */
10342 && (! TARGET_STACK_PROBE
10344 {
10347 }
10348 }
10351 {
10355 /* The computation of the size of the re-aligned stack frame means
10356 that we must allocate the size of the register save area before
10357 performing the actual alignment. Otherwise we cannot guarantee
10358 that there's enough storage above the realignment point. */
10365 /* Align the stack. */
10367 stack_pointer_rtx,
10370 /* For the purposes of register save area addressing, the stack
10371 pointer is no longer valid. As for the value of sp_offset,
10372 see ix86_compute_frame_layout, which we need to match in order
10373 to pass verification of stack_pointer_offset at the end. */
10376 }
10381 {
10382 /* We start to count from ARG_POINTER. */
10385 /* If it was realigned, take into account the fake frame. */
10387 {
10394 /* This over-estimates by 1 minimal-stack-alignment-unit but
10395 mitigates that by counting in the new return address slot. */
10396 current_function_dynamic_stack_size
10398 }
10401 }
10403 /* On SEH target with very large frame size, allocate an area to save
10404 SSE registers (as the very large allocation won't be described). */
10408 {
10409 HOST_WIDE_INT sse_size =
10414 /* No need to do stack checking as the area will be immediately
10415 written. */
10422 }
10424 /* The stack has already been decremented by the instruction calling us
10425 so probe if the size is non-negative to preserve the protection area. */
10427 {
10428 /* We expect the registers to be saved when probes are used. */
10432 {
10435 }
10436 else
10437 {
10445 else
10447 }
10448 }
10451 ;
10454 {
10458 }
10459 else
10460 {
10473 /* Note that SEH directives need to continue tracking the stack
10474 pointer even after the frame pointer has been set up. */
10476 {
10480 {
10484 }
10485 }
10488 {
10493 {
10497 }
10498 }
10503 /* Use the fact that AX still contains ALLOCATE. */
10505 ? gen_pro_epilogue_adjust_stack_di_sub
10512 {
10520 }
10524 {
10531 }
10533 {
10538 }
10539 }
10542 /* If we havn't already set up the frame pointer, do so now. */
10544 {
10556 }
10567 {
10574 }
10577 {
10579 {
10581 {
10591 label));
10595 }
10596 else
10598 }
10599 else
10600 {
10604 }
10605 }
10607 /* In the pic_reg_used case, make sure that the got load isn't deleted
10608 when mcount needs it. Blockage to avoid call movement across mcount
10609 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10610 note. */
10615 {
10616 /* vDRAP is setup but after reload it turns out stack realign
10617 isn't necessary, here we will emit prologue to setup DRAP
10618 without stack realign adjustment */
10621 }
10623 /* Prevent instructions from being scheduled into register save push
10624 sequence when access to the redzone area is done through frame pointer.
10625 The offset between the frame pointer and the stack pointer is calculated
10626 relative to the value of the stack pointer at the end of the function
10627 prologue, and moving instructions that access redzone area via frame
10628 pointer inside push sequence violates this assumption. */
10632 /* Emit cld instruction if stringops are used in the function. */
10636 /* SEH requires that the prologue end within 256 bytes of the start of
10637 the function. Prevent instruction schedules that would extend that.
10638 Further, prevent alloca modifications to the stack pointer from being
10639 combined with prologue modifications. */
10642 }
10644 /* Emit code to restore REG using a POP insn. */
10646 static void
10648 {
10657 {
10658 /* Previously we'd represented the CFA as an expression
10659 like *(%ebp - 8). We've just popped that value from
10660 the stack, which means we need to reset the CFA to
10661 the drap register. This will remain until we restore
10662 the stack pointer. */
10666 /* This means that the DRAP register is valid for addressing too. */
10669 }
10672 {
10679 }
10681 /* When the frame pointer is the CFA, and we pop it, we are
10682 swapping back to the stack pointer as the CFA. This happens
10683 for stack frames that don't allocate other data, so we assume
10684 the stack pointer is now pointing at the return address, i.e.
10685 the function entry state, which makes the offset be 1 word. */
10687 {
10690 {
10698 }
10699 }
10700 }
10702 /* Emit code to restore saved registers using POP insns. */
10704 static void
10706 {
10712 }
10714 /* Emit code and notes for the LEAVE instruction. */
10716 static void
10718 {
10730 {
10738 }
10741 }
10743 /* Emit code to restore saved registers using MOV insns.
10744 First register is restored from CFA - CFA_OFFSET. */
10745 static void
10748 {
10754 {
10763 {
10764 /* Previously we'd represented the CFA as an expression
10765 like *(%ebp - 8). We've just popped that value from
10766 the stack, which means we need to reset the CFA to
10767 the drap register. This will remain until we restore
10768 the stack pointer. */
10772 /* This means that the DRAP register is valid for addressing. */
10774 }
10775 else
10779 }
10780 }
10782 /* Emit code to restore saved registers using MOV insns.
10783 First register is restored from CFA - CFA_OFFSET. */
10784 static void
10787 {
10792 {
10794 rtx mem;
10804 }
10805 }
10807 /* Restore function stack, frame, and registers. */
10809 void
10811 {
10827 /* The FP must be valid if the frame pointer is present. */
10832 /* We must have *some* valid pointer to the stack frame. */
10835 /* The DRAP is never valid at this point. */
10838 /* See the comment about red zone and frame
10839 pointer usage in ix86_expand_prologue. */
10846 /* Determine the CFA offset of the end of the red-zone. */
10849 {
10850 /* The red-zone begins below the return address. */
10853 /* When the register save area is in the aligned portion of
10854 the stack, determine the maximum runtime displacement that
10855 matches up with the aligned frame. */
10859 }
10861 /* Special care must be taken for the normal return case of a function
10862 using eh_return: the eax and edx registers are marked as saved, but
10863 not restored along this path. Adjust the save location to match. */
10867 /* EH_RETURN requires the use of moves to function properly. */
10870 /* SEH requires the use of pops to identify the epilogue. */
10873 /* If we're only restoring one register and sp is not valid then
10874 using a move instruction to restore the register since it's
10875 less work than reloading sp and popping the register. */
10888 && TARGET_USE_LEAVE
10892 else
10896 {
10897 /* Ensure that the entire register save area is addressable via
10898 the stack pointer, if we will restore via sp. */
10903 {
10907 style,
10909 }
10910 }
10912 /* If there are any SSE registers to restore, then we have to do it
10913 via moves, since there's obviously no pop for SSE regs. */
10919 {
10920 rtx t;
10925 /* eh_return epilogues need %ecx added to the stack pointer. */
10927 {
10930 /* Stack align doesn't work with eh_return. */
10932 /* Neither does regparm nested functions. */
10936 {
10944 /* Note that we use SA as a temporary CFA, as the return
10945 address is at the proper place relative to it. We
10946 pretend this happens at the FP restore insn because
10947 prior to this insn the FP would be stored at the wrong
10948 offset relative to SA, and after this insn we have no
10949 other reasonable register to use for the CFA. We don't
10950 bother resetting the CFA to the SP for the duration of
10951 the return insn. */
10964 }
10965 else
10966 {
10974 {
10978 UNITS_PER_WORD));
10980 }
10981 }
10984 }
10985 }
10986 else
10987 {
10988 /* SEH requires that the function end with (1) a stack adjustment
10989 if necessary, (2) a sequence of pops, and (3) a return or
10990 jump instruction. Prevent insns from the function body from
10991 being scheduled into this sequence. */
10993 {
10994 /* Prevent a catch region from being adjacent to the standard
10995 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
10996 several other flags that would be interesting to test are
10997 not yet set up. */
11000 else
11002 }
11004 /* First step is to deallocate the stack frame so that we can
11005 pop the registers. Also do it on SEH target for very large
11006 frame as the emitted instructions aren't allowed by the ABI in
11007 epilogues. */
11009 || (TARGET_SEH
11012 {
11017 }
11019 {
11023 style,
11025 }
11028 }
11030 /* If we used a stack pointer and haven't already got rid of it,
11031 then do so now. */
11033 {
11034 /* If the stack pointer is valid and pointing at the frame
11035 pointer store address, then we only need a pop. */
11038 /* Leave results in shorter dependency chains on CPUs that are
11039 able to grok it fast. */
11044 else
11045 {
11047 hard_frame_pointer_rtx,
11050 }
11051 }
11054 {
11056 rtx insn;
11082 }
11084 /* At this point the stack pointer must be valid, and we must have
11085 restored all of the registers. We may not have deallocated the
11086 entire stack frame. We've delayed this until now because it may
11087 be possible to merge the local stack deallocation with the
11088 deallocation forced by ix86_static_chain_on_stack. */
11093 {
11097 }
11098 else
11101 /* Sibcall epilogues don't want a return instruction. */
11103 {
11106 }
11109 {
11112 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11113 address, do explicit add, and jump indirectly to the caller. */
11116 {
11118 rtx insn;
11120 /* There is no "pascal" calling convention in any 64bit ABI. */
11136 }
11137 else
11139 }
11140 else
11143 /* Restore the state back to the state from the prologue,
11144 so that it's correct for the next epilogue. */
11146 }
11148 /* Reset from the function's potential modifications. */
11150 static void
11152 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11153 {
11156 #if TARGET_MACHO
11157 /* Mach-O doesn't support labels at the end of objects, so if
11158 it looks like we might want one, insert a NOP. */
11159 {
11165 {
11166 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11167 notes only, instead set their CODE_LABEL_NUMBER to -1,
11168 otherwise there would be code generation differences
11169 in between -g and -g0. */
11173 }
11183 }
11184 #endif
11186 }
11188 /* Return a scratch register to use in the split stack prologue. The
11189 split stack prologue is used for -fsplit-stack. It is the first
11190 instructions in the function, even before the regular prologue.
11191 The scratch register can be any caller-saved register which is not
11192 used for parameters or for the static chain. */
11194 static unsigned int
11196 {
11199 else
11200 {
11213 {
11215 {
11219 }
11221 }
11223 {
11227 }
11229 {
11232 else
11233 {
11235 {
11239 }
11241 }
11242 }
11243 else
11244 {
11245 /* FIXME: We could make this work by pushing a register
11246 around the addition and comparison. */
11249 }
11250 }
11251 }
11253 /* A SYMBOL_REF for the function which allocates new stackspace for
11254 -fsplit-stack. */
11258 /* A SYMBOL_REF for the more stack function when using the large
11259 model. */
11263 /* Handle -fsplit-stack. These are the first instructions in the
11264 function, even before the regular prologue. */
11266 void
11268 {
11270 HOST_WIDE_INT allocate;
11275 rtx fn;
11283 /* This is the label we will branch to if we have enough stack
11284 space. We expect the basic block reordering pass to reverse this
11285 branch if optimizing, so that we branch in the unlikely case. */
11288 /* We need to compare the stack pointer minus the frame size with
11289 the stack boundary in the TCB. The stack boundary always gives
11290 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11291 can compare directly. Otherwise we need to do an addition. */
11294 UNSPEC_STACK_CHECK);
11299 else
11300 {
11302 rtx offset;
11304 /* We need a scratch register to hold the stack pointer minus
11305 the required frame size. Since this is the very start of the
11306 function, the scratch register can be any caller-saved
11307 register which is not used for parameters. */
11314 {
11315 /* We don't use ix86_gen_add3 in this case because it will
11316 want to split to lea, but when not optimizing the insn
11317 will not be split after this point. */
11320 offset)));
11321 }
11322 else
11323 {
11326 stack_pointer_rtx));
11327 }
11329 }
11335 /* Mark the jump as very likely to be taken. */
11343 /* Get more stack space. We pass in the desired stack space and the
11344 size of the arguments to copy to the new stack. In 32-bit mode
11345 we push the parameters; __morestack will return on a new stack
11346 anyhow. In 64-bit mode we pass the parameters in r10 and
11347 r11. */
11352 {
11358 /* If this function uses a static chain, it will be in %r10.
11359 Preserve it across the call to __morestack. */
11361 {
11362 rtx rax;
11367 }
11370 {
11371 HOST_WIDE_INT argval;
11374 /* When using the large model we need to load the address
11375 into a register, and we've run out of registers. So we
11376 switch to a different calling convention, and we call a
11377 different function: __morestack_large. We pass the
11378 argument size in the upper 32 bits of r10 and pass the
11379 frame size in the lower 32 bits. */
11384 split_stack_fn_large =
11388 {
11398 UNSPEC_GOT);
11404 }
11405 else
11412 }
11413 else
11414 {
11418 }
11421 }
11422 else
11423 {
11426 }
11432 /* In order to make call/return prediction work right, we now need
11433 to execute a return instruction. See
11434 libgcc/config/i386/morestack.S for the details on how this works.
11436 For flow purposes gcc must not see this as a return
11437 instruction--we need control flow to continue at the subsequent
11438 label. Therefore, we use an unspec. */
11442 /* If we are in 64-bit mode and this function uses a static chain,
11443 we saved %r10 in %rax before calling _morestack. */
11448 /* If this function calls va_start, we need to store a pointer to
11449 the arguments on the old stack, because they may not have been
11450 all copied to the new stack. At this point the old stack can be
11451 found at the frame pointer value used by __morestack, because
11452 __morestack has set that up before calling back to us. Here we
11453 store that pointer in a scratch register, and in
11454 ix86_expand_prologue we store the scratch register in a stack
11455 slot. */
11457 {
11459 rtx frame_reg;
11466 /* 64-bit:
11467 fp -> old fp value
11468 return address within this function
11469 return address of caller of this function
11470 stack arguments
11471 So we add three words to get to the stack arguments.
11473 32-bit:
11474 fp -> old fp value
11475 return address within this function
11476 first argument to __morestack
11477 second argument to __morestack
11478 return address of caller of this function
11479 stack arguments
11480 So we add five words to get to the stack arguments.
11481 */
11492 }
11497 /* If this function calls va_start, we now have to set the scratch
11498 register for the case where we do not call __morestack. In this
11499 case we need to set it based on the stack pointer. */
11501 {
11508 }
11509 }
11511 /* We may have to tell the dataflow pass that the split stack prologue
11512 is initializing a scratch register. */
11514 static void
11516 {
11518 {
11521 }
11522 }
11523 \f
11524 /* Determine if op is suitable SUBREG RTX for address. */
11526 static bool
11528 {
11539 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11540 failures when the register is one word out of a two word structure. */
11544 /* Allow only SUBREGs of non-eliminable hard registers. */
11546 }
11548 /* Extract the parts of an RTL expression that is a valid memory address
11549 for an instruction. Return 0 if the structure of the address is
11550 grossly off. Return -1 if the address contains ASHIFT, so it is not
11551 strictly valid, but still used for computing length of lea instruction. */
11553 int
11555 {
11560 rtx tmp;
11564 /* Allow zero-extended SImode addresses,
11565 they will be emitted with addr32 prefix. */
11567 {
11570 {
11574 }
11577 {
11584 }
11585 }
11587 /* Allow SImode subregs of DImode addresses,
11588 they will be emitted with addr32 prefix. */
11590 {
11593 {
11597 }
11598 }
11603 {
11606 else
11608 }
11610 {
11615 do
11616 {
11621 }
11628 {
11631 {
11656 /* FALLTHRU */
11660 && TARGET_TLS_DIRECT_SEG_REFS
11663 else
11670 /* FALLTHRU */
11677 else
11692 }
11693 }
11694 }
11696 {
11699 }
11701 {
11702 /* We're called for lea too, which implements ashift on occasion. */
11712 }
11714 {
11718 /* Constant addresses are sign extended to 64bit, we have to
11719 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11725 }
11726 else
11730 {
11732 ;
11735 ;
11736 else
11738 }
11740 /* Address override works only on the (%reg) part of %fs:(%reg). */
11746 /* Extract the integral value of scale. */
11748 {
11752 }
11757 /* Avoid useless 0 displacement. */
11761 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11766 {
11767 rtx tmp;
11770 }
11772 /* Special case: %ebp cannot be encoded as a base without a displacement.
11773 Similarly %r13. */
11775 && base_reg
11784 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11785 Avoid this by transforming to [%esi+0].
11786 Reload calls address legitimization without cfun defined, so we need
11787 to test cfun for being non-NULL. */
11793 /* Special case: encode reg+reg instead of reg*2. */
11797 /* Special case: scaling cannot be encoded without base or displacement. */
11808 }
11809 \f
11810 /* Return cost of the memory address x.
11811 For i386, it is better to use a complex address than let gcc copy
11812 the address into a reg and make a new pseudo. But not if the address
11813 requires to two regs - that would mean more pseudos with longer
11814 lifetimes. */
11815 static int
11817 addr_space_t as ATTRIBUTE_UNUSED,
11819 {
11831 /* Attempt to minimize number of registers in the address. */
11837 cost++;
11844 cost++;
11846 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11847 since it's predecode logic can't detect the length of instructions
11848 and it degenerates to vector decoded. Increase cost of such
11849 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11850 to split such addresses or even refuse such addresses at all.
11852 Following addressing modes are affected:
11853 [base+scale*index]
11854 [scale*index+disp]
11855 [base+index]
11857 The first and last case may be avoidable by explicitly coding the zero in
11858 memory address, but I don't have AMD-K6 machine handy to check this
11859 theory. */
11868 }
11869 \f
11870 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11871 this is used for to form addresses to local data when -fPIC is in
11872 use. */
11874 static bool
11876 {
11879 }
11881 /* Determine if a given RTX is a valid constant. We already know this
11882 satisfies CONSTANT_P. */
11884 static bool
11886 {
11888 {
11893 {
11897 }
11902 /* Only some unspecs are valid as "constants". */
11905 {
11921 }
11923 /* We must have drilled down to a symbol. */
11928 /* FALLTHRU */
11931 /* TLS symbols are never valid. */
11935 /* DLLIMPORT symbols are never valid. */
11940 #if TARGET_MACHO
11941 /* mdynamic-no-pic */
11944 #endif
11960 }
11962 /* Otherwise we handle everything else in the move patterns. */
11964 }
11966 /* Determine if it's legal to put X into the constant pool. This
11967 is not possible for the address of thread-local symbols, which
11968 is checked above. */
11970 static bool
11972 {
11973 /* We can always put integral constants and vectors in memory. */
11975 {
11983 }
11985 }
11988 /* Nonzero if the constant value X is a legitimate general operand
11989 when generating PIC code. It is given that flag_pic is on and
11990 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11992 bool
11994 {
11995 rtx inner;
11998 {
12005 /* Only some unspecs are valid as "constants". */
12008 {
12021 }
12022 /* FALLTHRU */
12030 }
12031 }
12033 /* Determine if a given CONST RTX is a valid memory displacement
12034 in PIC mode. */
12036 bool
12038 {
12041 /* In 64bit mode we can allow direct addresses of symbols and labels
12042 when they are not dynamic symbols. */
12044 {
12048 {
12072 /* FALLTHRU */
12075 /* TLS references should always be enclosed in UNSPEC. */
12085 }
12086 }
12092 {
12093 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12094 of GOT tables. We should not need these anyway. */
12106 }
12110 {
12115 }
12124 {
12128 /* We need to check for both symbols and labels because VxWorks loads
12129 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12130 details. */
12134 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12135 While ABI specify also 32bit relocation but we don't produce it in
12136 small PIC model at all. */
12158 }
12161 }
12163 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12164 replace the input X, or the original X if no replacement is called for.
12165 The output parameter *WIN is 1 if the calling macro should goto WIN,
12166 0 if it should not. */
12168 bool
12173 {
12174 /* Reload can generate:
12176 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12177 (reg:DI 97))
12178 (reg:DI 2 cx))
12180 This RTX is rejected from ix86_legitimate_address_p due to
12181 non-strictness of base register 97. Following this rejection,
12182 reload pushes all three components into separate registers,
12183 creating invalid memory address RTX.
12185 Following code reloads only the invalid part of the
12186 memory address RTX. */
12192 {
12198 {
12203 }
12207 {
12212 }
12216 }
12219 }
12221 /* Recognizes RTL expressions that are valid memory addresses for an
12222 instruction. The MODE argument is the machine mode for the MEM
12223 expression that wants to use this address.
12225 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12226 convert common non-canonical forms to canonical form so that they will
12227 be recognized. */
12229 static bool
12232 {
12235 HOST_WIDE_INT scale;
12238 /* Decomposition failed. */
12246 /* Validate base register. */
12248 {
12249 rtx reg;
12255 else
12256 /* Base is not a register. */
12264 /* Base is not valid. */
12266 }
12268 /* Validate index register. */
12270 {
12271 rtx reg;
12277 else
12278 /* Index is not a register. */
12286 /* Index is not valid. */
12288 }
12290 /* Index and base should have the same mode. */
12295 /* Validate scale factor. */
12297 {
12299 /* Scale without index. */
12303 /* Scale is not a valid multiplier. */
12305 }
12307 /* Validate displacement. */
12309 {
12314 {
12315 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12316 used. While ABI specify also 32bit relocations, we don't produce
12317 them at all and use IP relative instead. */
12324 /* 64bit address unspec. */
12344 /* Invalid address unspec. */
12346 }
12349 && (flag_pic
12350 || (TARGET_MACHO
12351 #if TARGET_MACHO
12352 && MACHOPIC_INDIRECT
12354 #endif
12355 )))
12356 {
12358 is_legitimate_pic:
12360 {
12361 /* foo@dtpoff(%rX) is ok. */
12368 /* Non-constant pic memory reference. */
12370 }
12373 /* Displacement is an invalid pic construct. */
12375 #if TARGET_MACHO
12378 /* displacment must be referenced via non_lazy_pointer */
12380 #endif
12382 /* This code used to verify that a symbolic pic displacement
12383 includes the pic_offset_table_rtx register.
12385 While this is good idea, unfortunately these constructs may
12386 be created by "adds using lea" optimization for incorrect
12387 code like:
12389 int a;
12390 int foo(int i)
12391 {
12392 return *(&a+i);
12393 }
12395 This code is nonsensical, but results in addressing
12396 GOT table with pic_offset_table_rtx base. We can't
12397 just refuse it easily, since it gets matched by
12398 "addsi3" pattern, that later gets split to lea in the
12399 case output register differs from input. While this
12400 can be handled by separate addsi pattern for this case
12401 that never results in lea, this seems to be easier and
12402 correct fix for crash to disable this test. */
12403 }
12410 /* Displacement is not constant. */
12414 /* Displacement is out of range. */
12416 }
12418 /* Everything looks valid. */
12420 }
12422 /* Determine if a given RTX is a valid constant address. */
12424 bool
12426 {
12428 }
12429 \f
12430 /* Return a unique alias set for the GOT. */
12432 static alias_set_type
12434 {
12439 }
12441 /* Return a legitimate reference for ORIG (an address) using the
12442 register REG. If REG is 0, a new pseudo is generated.
12444 There are two types of references that must be handled:
12446 1. Global data references must load the address from the GOT, via
12447 the PIC reg. An insn is emitted to do this load, and the reg is
12448 returned.
12450 2. Static data references, constant pool addresses, and code labels
12451 compute the address as an offset from the GOT, whose base is in
12452 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12453 differentiate them from global data objects. The returned
12454 address is the PIC reg + an unspec constant.
12456 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12457 reg also appears in the address. */
12459 static rtx
12461 {
12465 #if TARGET_MACHO
12467 {
12470 /* Use the generic Mach-O PIC machinery. */
12472 }
12473 #endif
12480 {
12481 rtx tmpreg;
12482 /* This symbol may be referenced via a displacement from the PIC
12483 base address (@GOTOFF). */
12490 {
12492 UNSPEC_GOTOFF);
12494 }
12495 else
12500 else
12505 {
12509 }
12511 }
12513 {
12514 /* This symbol may be referenced via a displacement from the PIC
12515 base address (@GOTOFF). */
12522 {
12524 UNSPEC_GOTOFF);
12526 }
12527 else
12533 {
12536 }
12537 }
12539 /* We can't use @GOTOFF for text labels on VxWorks;
12540 see gotoff_operand. */
12542 {
12544 {
12550 {
12553 }
12554 }
12556 /* For x64 PE-COFF there is no GOT table. So we use address
12557 directly. */
12559 {
12567 }
12569 {
12577 /* Use directly gen_movsi, otherwise the address is loaded
12578 into register for CSE. We don't want to CSE this addresses,
12579 instead we CSE addresses from the GOT table, so skip this. */
12582 }
12583 else
12584 {
12585 /* This symbol must be referenced via a load from the
12586 Global Offset Table (@GOT). */
12602 }
12603 }
12604 else
12605 {
12608 {
12610 {
12613 }
12614 else
12616 }
12618 {
12621 /* We must match stuff we generate before. Assume the only
12622 unspecs that can get here are ours. Not that we could do
12623 anything with them anyway.... */
12629 }
12631 {
12634 /* Check first to see if this is a constant offset from a @GOTOFF
12635 symbol reference. */
12638 {
12640 {
12644 UNSPEC_GOTOFF);
12650 {
12653 }
12654 }
12655 else
12656 {
12659 {
12663 }
12664 }
12665 }
12666 else
12667 {
12670 new_rtx
12674 {
12677 {
12680 new_rtx
12682 }
12683 else
12685 }
12686 else
12687 {
12690 {
12693 }
12695 }
12696 }
12697 }
12698 }
12700 }
12701 \f
12702 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12704 static rtx
12706 {
12710 {
12715 }
12721 }
12723 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12727 static rtx
12729 {
12731 {
12737 }
12740 }
12742 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12746 rtx
12748 {
12750 {
12751 ix86_tls_module_base_symbol
12756 }
12759 }
12761 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12762 false if we expect this to be used for a memory address and true if
12763 we expect to load the address into a register. */
12765 static rtx
12767 {
12774 {
12779 {
12782 else
12783 {
12786 }
12787 }
12790 {
12793 else
12803 }
12804 else
12805 {
12809 {
12811 rtx insns;
12814 emit_call_insn
12824 }
12825 else
12827 }
12834 {
12837 else
12838 {
12841 }
12842 }
12845 {
12850 else
12856 }
12857 else
12858 {
12862 {
12867 emit_call_insn
12872 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12873 share the LD_BASE result with other LD model accesses. */
12875 UNSPEC_TLS_LD_BASE);
12879 }
12880 else
12882 }
12890 {
12897 }
12902 {
12904 {
12905 /* The Sun linker took the AMD64 TLS spec literally
12906 and can only handle %rax as destination of the
12907 initial executable code sequence. */
12912 }
12914 /* Generate DImode references to avoid %fs:(%reg32)
12915 problems and linker IE->LE relaxation bug. */
12919 }
12921 {
12926 }
12928 {
12932 }
12933 else
12934 {
12937 }
12947 {
12952 }
12953 else
12954 {
12958 }
12968 {
12972 }
12973 else
12974 {
12978 }
12983 }
12986 }
12988 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12989 to symbol DECL. */
12992 htab_t dllimport_map;
12994 static tree
12996 {
13003 tree to;
13004 rtx rtl;
13048 }
13050 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13051 true if we require the result be a register. */
13053 static rtx
13055 {
13056 tree imp_decl;
13057 rtx x;
13066 }
13068 /* Try machine-dependent ways of modifying an illegitimate address
13069 to be legitimate. If we find one, return the new, valid address.
13070 This macro is used in only one place: `memory_address' in explow.c.
13072 OLDX is the address as it was before break_out_memory_refs was called.
13073 In some cases it is useful to look at this to decide what needs to be done.
13075 It is always safe for this macro to do nothing. It exists to recognize
13076 opportunities to optimize the output.
13078 For the 80386, we handle X+REG by loading X into a register R and
13079 using R+REG. R will go in a general reg and indexing will be used.
13080 However, if REG is a broken-out memory address or multiplication,
13081 nothing needs to be done because REG can certainly go in a general reg.
13083 When -fpic is used, special handling is needed for symbolic references.
13084 See comments by legitimize_pic_address in i386.c for details. */
13086 static rtx
13089 {
13100 {
13104 }
13107 {
13114 {
13117 }
13118 }
13123 #if TARGET_MACHO
13126 #endif
13128 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13132 {
13137 }
13140 {
13141 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13146 {
13152 }
13157 {
13163 }
13165 /* Put multiply first if it isn't already. */
13167 {
13172 }
13174 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13175 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13176 created by virtual register instantiation, register elimination, and
13177 similar optimizations. */
13179 {
13185 }
13187 /* Canonicalize
13188 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13189 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13194 {
13195 rtx constant;
13199 {
13202 }
13204 {
13207 }
13208 else
13212 {
13219 }
13220 }
13226 {
13229 }
13232 {
13235 }
13243 {
13246 }
13252 {
13256 {
13259 }
13263 }
13266 {
13270 {
13273 }
13277 }
13278 }
13281 }
13282 \f
13283 /* Print an integer constant expression in assembler syntax. Addition
13284 and subtraction are the only arithmetic that may appear in these
13285 expressions. FILE is the stdio stream to write to, X is the rtx, and
13286 CODE is the operand print code from the output string. */
13288 static void
13290 {
13294 {
13303 else
13304 {
13307 /* Mark the decl as referenced so that cgraph will
13308 output the function. */
13312 #if TARGET_MACHO
13316 #endif
13318 }
13326 /* FALLTHRU */
13337 /* This used to output parentheses around the expression,
13338 but that does not work on the 386 (either ATT or BSD assembler). */
13344 {
13345 /* We can use %d if the number is <32 bits and positive. */
13350 else
13352 }
13353 else
13354 /* We can't handle floating point constants;
13355 TARGET_PRINT_OPERAND must handle them. */
13360 /* Some assemblers need integer constants to appear first. */
13362 {
13366 }
13367 else
13368 {
13373 }
13388 {
13392 }
13397 {
13416 /* FIXME: This might be @TPOFF in Sun ld too. */
13425 else
13435 else
13441 #if TARGET_MACHO
13446 #endif
13450 }
13455 }
13456 }
13458 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13459 We need to emit DTP-relative relocations. */
13461 static void ATTRIBUTE_UNUSED
13463 {
13468 {
13476 }
13477 }
13479 /* Return true if X is a representation of the PIC register. This copes
13480 with calls from ix86_find_base_term, where the register might have
13481 been replaced by a cselib value. */
13483 static bool
13485 {
13489 else
13491 }
13493 /* Helper function for ix86_delegitimize_address.
13494 Attempt to delegitimize TLS local-exec accesses. */
13496 static rtx
13498 {
13523 {
13528 }
13534 }
13536 /* In the name of slightly smaller debug output, and to cater to
13537 general assembler lossage, recognize PIC+GOTOFF and turn it back
13538 into a direct symbol reference.
13540 On Darwin, this is necessary to avoid a crash, because Darwin
13541 has a different PIC label for each routine but the DWARF debugging
13542 information is not associated with any particular routine, so it's
13543 necessary to remove references to the PIC label from RTL stored by
13544 the DWARF output code. */
13546 static rtx
13548 {
13550 /* addend is NULL or some rtx if x is something+GOTOFF where
13551 something doesn't include the PIC register. */
13553 /* reg_addend is NULL or a multiple of some register. */
13555 /* const_addend is NULL or a const_int. */
13557 /* This is the result, or NULL. */
13566 {
13573 {
13579 }
13588 {
13593 }
13595 }
13602 /* %ebx + GOT/GOTOFF */
13603 ;
13605 {
13606 /* %ebx + %reg * scale + GOT/GOTOFF */
13612 else
13613 {
13616 }
13617 }
13618 else
13624 {
13627 }
13646 {
13647 /* If the rest of original X doesn't involve the PIC register, add
13648 addend and subtract pic_offset_table_rtx. This can happen e.g.
13649 for code like:
13650 leal (%ebx, %ecx, 4), %ecx
13651 ...
13652 movl foo@GOTOFF(%ecx), %edx
13653 in which case we return (%ecx - %ebx) + foo. */
13656 pic_offset_table_rtx),
13657 result);
13658 else
13660 }
13662 {
13666 }
13668 }
13670 /* If X is a machine specific address (i.e. a symbol or label being
13671 referenced as a displacement from the GOT implemented using an
13672 UNSPEC), then return the base term. Otherwise return X. */
13674 rtx
13676 {
13677 rtx term;
13680 {
13694 }
13697 }
13698 \f
13699 static void
13702 {
13706 {
13709 }
13714 {
13717 {
13736 }
13740 {
13759 }
13766 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13767 Those same assemblers have the same but opposite lossage on cmov. */
13772 else
13777 {
13790 }
13798 {
13811 }
13814 /* ??? As above. */
13823 /* ??? As above. */
13828 else
13839 }
13841 }
13843 /* Print the name of register X to FILE based on its machine mode and number.
13844 If CODE is 'w', pretend the mode is HImode.
13845 If CODE is 'b', pretend the mode is QImode.
13846 If CODE is 'k', pretend the mode is SImode.
13847 If CODE is 'q', pretend the mode is DImode.
13848 If CODE is 'x', pretend the mode is V4SFmode.
13849 If CODE is 't', pretend the mode is V8SFmode.
13850 If CODE is 'h', pretend the reg is the 'high' byte register.
13851 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13852 If CODE is 'd', duplicate the operand for AVX instruction.
13853 */
13855 void
13857 {
13866 {
13870 }
13895 else
13898 /* Irritatingly, AMD extended registers use different naming convention
13899 from the normal registers: "r%d[bwd]" */
13901 {
13906 {
13920 /* no suffix */
13925 }
13927 }
13931 {
13934 {
13937 }
13938 /* FALLTHRU */
13944 /* FALLTHRU */
13947 normal:
13962 {
13967 }
13971 }
13975 {
13978 else
13980 }
13981 }
13983 /* Locate some local-dynamic symbol still in use by this function
13984 so that we can print its name in some tls_local_dynamic_base
13985 pattern. */
13987 static int
13989 {
13994 {
13997 }
14000 }
14004 {
14005 rtx insn;
14016 }
14018 /* Meaning of CODE:
14019 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14020 C -- print opcode suffix for set/cmov insn.
14021 c -- like C, but print reversed condition
14022 F,f -- likewise, but for floating-point.
14023 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14024 otherwise nothing
14025 R -- print the prefix for register names.
14026 z -- print the opcode suffix for the size of the current operand.
14027 Z -- likewise, with special suffixes for x87 instructions.
14028 * -- print a star (in certain assembler syntax)
14029 A -- print an absolute memory reference.
14030 E -- print address with DImode register names if TARGET_64BIT.
14031 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14032 s -- print a shift double count, followed by the assemblers argument
14033 delimiter.
14034 b -- print the QImode name of the register for the indicated operand.
14035 %b0 would print %al if operands[0] is reg 0.
14036 w -- likewise, print the HImode name of the register.
14037 k -- likewise, print the SImode name of the register.
14038 q -- likewise, print the DImode name of the register.
14039 x -- likewise, print the V4SFmode name of the register.
14040 t -- likewise, print the V8SFmode name of the register.
14041 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14042 y -- print "st(0)" instead of "st" as a register.
14043 d -- print duplicated register operand for AVX instruction.
14044 D -- print condition for SSE cmp instruction.
14045 P -- if PIC, print an @PLT suffix.
14046 p -- print raw symbol name.
14047 X -- don't print any sort of PIC '@' suffix for a symbol.
14048 & -- print some in-use local-dynamic symbol name.
14049 H -- print a memory address offset by 8; used for sse high-parts
14050 Y -- print condition for XOP pcom* instruction.
14051 + -- print a branch hint as 'cs' or 'ds' prefix
14052 ; -- print a semicolon (after prefixes due to bug in older gas).
14053 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14054 @ -- print a segment register of thread base pointer load
14055 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14056 */
14058 void
14060 {
14062 {
14064 {
14067 {
14073 /* Intel syntax. For absolute addresses, registers should not
14074 be surrounded by braces. */
14076 {
14081 }
14086 }
14092 /* Wrap address in an UNSPEC to declare special handling. */
14130 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14135 {
14149 output_operand_lossage
14152 }
14155 #endif
14160 {
14161 /* Opcodes don't get size suffixes if using Intel opcodes. */
14166 {
14184 output_operand_lossage
14187 }
14188 }
14191 warning
14193 /* FALLTHRU */
14196 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14201 {
14203 {
14205 #ifdef HAVE_AS_IX86_FILDS
14207 #endif
14215 #ifdef HAVE_AS_IX86_FILDQ
14217 #else
14219 #endif
14224 }
14225 }
14227 {
14228 /* 387 opcodes don't get size suffixes
14229 if the operands are registers. */
14234 {
14250 }
14251 }
14252 else
14253 {
14254 output_operand_lossage
14257 }
14259 output_operand_lossage
14279 {
14282 }
14287 {
14338 }
14342 /* Little bit of braindamage here. The SSE compare instructions
14343 does use completely different names for the comparisons that the
14344 fp conditional moves. */
14346 {
14349 {
14352 }
14358 {
14361 }
14367 {
14370 }
14379 {
14382 }
14388 {
14391 }
14397 {
14400 }
14411 }
14416 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14419 #endif
14424 {
14428 }
14432 file);
14437 {
14441 }
14442 /* It doesn't actually matter what mode we use here, as we're
14443 only going to use this for printing. */
14451 #ifdef HAVE_AS_IX86_HLE
14453 #else
14455 #endif
14457 #ifdef HAVE_AS_IX86_HLE
14459 #else
14461 #endif
14462 /* We do not want to print value of the operand. */
14471 {
14476 else
14479 }
14482 {
14483 rtx x;
14492 {
14497 {
14499 bool cputaken
14502 /* Emit hints only in the case default branch prediction
14503 heuristics would fail. */
14505 {
14506 /* We use 3e (DS) prefix for taken branches and
14507 2e (CS) prefix for not taken branches. */
14510 else
14512 }
14513 }
14514 }
14516 }
14519 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14521 #endif
14528 /* The kernel uses a different segment register for performance
14529 reasons; a system call would not have to trash the userspace
14530 segment register, which would be expensive. */
14533 else
14548 }
14549 }
14555 {
14556 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14559 {
14562 {
14571 else
14577 }
14579 /* Check for explicit size override (codes 'b', 'w', 'k',
14580 'q' and 'x') */
14594 }
14597 /* Avoid (%rip) for call operands. */
14603 else
14605 }
14608 {
14609 REAL_VALUE_TYPE r;
14617 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14620 else
14622 }
14625 {
14626 REAL_VALUE_TYPE r;
14635 }
14637 /* These float cases don't actually occur as immediate operands. */
14639 {
14644 }
14646 else
14647 {
14648 /* We have patterns that allow zero sets of memory, for instance.
14649 In 64-bit mode, we should probably support all 8-byte vectors,
14650 since we can in fact encode that into an immediate. */
14652 {
14655 }
14658 {
14660 {
14663 }
14666 {
14669 else
14671 }
14672 }
14677 else
14679 }
14680 }
14682 static bool
14684 {
14687 }
14688 \f
14689 /* Print a memory operand whose address is ADDR. */
14691 static void
14693 {
14702 {
14709 }
14711 {
14715 }
14716 else
14727 {
14738 }
14740 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14742 {
14754 }
14756 {
14757 /* Displacement only requires special attention. */
14760 {
14764 }
14767 else
14769 }
14770 else
14771 {
14772 /* Print SImode register names to force addr32 prefix. */
14774 {
14775 #ifdef ENABLE_CHECKING
14778 {
14789 }
14790 #endif
14793 }
14795 && TARGET_X32
14796 && disp
14799 {
14800 /* X32 runs in 64-bit mode, where displacement, DISP, in
14801 address DISP(%r64), is encoded as 32-bit immediate sign-
14802 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14803 address is %r64 + 0xffffffffbffffd00. When %r64 <
14804 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14805 which is invalid for x32. The correct address is %r64
14806 - 0x40000300 == 0xf7ffdd64. To properly encode
14807 -0x40000300(%r64) for x32, we zero-extend negative
14808 displacement by forcing addr32 prefix which truncates
14809 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14810 zero-extend all negative displacements, including -1(%rsp).
14811 However, for small negative displacements, sign-extension
14812 won't cause overflow. We only zero-extend negative
14813 displacements if they < -16*1024*1024, which is also used
14814 to check legitimate address displacements for PIC. */
14816 }
14819 {
14821 {
14826 else
14828 }
14834 {
14839 }
14841 }
14842 else
14843 {
14847 {
14848 /* Pull out the offset of a symbol; print any symbol itself. */
14852 {
14856 }
14864 else
14866 }
14870 {
14873 {
14877 }
14878 }
14881 else
14885 {
14890 }
14892 }
14893 }
14894 }
14896 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14898 static bool
14900 {
14901 rtx op;
14908 {
14911 /* FIXME: This might be @TPOFF in Sun ld. */
14922 else
14934 else
14941 #if TARGET_MACHO
14947 #endif
14950 {
14955 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14957 #else
14959 #endif
14962 }
14967 }
14970 }
14971 \f
14972 /* Split one or more double-mode RTL references into pairs of half-mode
14973 references. The RTL can be REG, offsettable MEM, integer constant, or
14974 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14975 split and "num" is its length. lo_half and hi_half are output arrays
14976 that parallel "operands". */
14978 void
14981 {
14986 {
14995 }
15000 {
15003 /* simplify_subreg refuse to split volatile memory addresses,
15004 but we still have to handle it. */
15006 {
15009 }
15010 else
15011 {
15018 }
15019 }
15020 }
15021 \f
15022 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15023 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15024 is the expression of the binary operation. The output may either be
15025 emitted here, or returned to the caller, like all output_* functions.
15027 There is no guarantee that the operands are the same mode, as they
15028 might be within FLOAT or FLOAT_EXTEND expressions. */
15030 #ifndef SYSV386_COMPAT
15031 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15032 wants to fix the assemblers because that causes incompatibility
15033 with gcc. No-one wants to fix gcc because that causes
15034 incompatibility with assemblers... You can use the option of
15035 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15036 #define SYSV386_COMPAT 1
15037 #endif
15041 {
15047 #ifdef ENABLE_CHECKING
15048 /* Even if we do not want to check the inputs, this documents input
15049 constraints. Which helps in understanding the following code. */
15059 else
15061 #endif
15064 {
15069 else
15078 else
15087 else
15096 else
15103 }
15106 {
15108 {
15112 else
15114 }
15115 else
15116 {
15120 else
15122 }
15124 }
15128 {
15132 {
15136 }
15138 /* know operands[0] == operands[1]. */
15141 {
15144 }
15147 {
15149 /* How is it that we are storing to a dead operand[2]?
15150 Well, presumably operands[1] is dead too. We can't
15151 store the result to st(0) as st(0) gets popped on this
15152 instruction. Instead store to operands[2] (which I
15153 think has to be st(1)). st(1) will be popped later.
15154 gcc <= 2.8.1 didn't have this check and generated
15155 assembly code that the Unixware assembler rejected. */
15157 else
15160 }
15164 else
15171 {
15174 }
15177 {
15180 }
15183 {
15184 #if SYSV386_COMPAT
15185 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15186 derived assemblers, confusingly reverse the direction of
15187 the operation for fsub{r} and fdiv{r} when the
15188 destination register is not st(0). The Intel assembler
15189 doesn't have this brain damage. Read !SYSV386_COMPAT to
15190 figure out what the hardware really does. */
15193 else
15195 #else
15197 /* As above for fmul/fadd, we can't store to st(0). */
15199 else
15201 #endif
15203 }
15206 {
15207 #if SYSV386_COMPAT
15210 else
15212 #else
15215 else
15217 #endif
15219 }
15222 {
15225 else
15228 }
15230 {
15231 #if SYSV386_COMPAT
15233 #else
15235 #endif
15236 }
15237 else
15238 {
15239 #if SYSV386_COMPAT
15241 #else
15243 #endif
15244 }
15249 }
15253 }
15255 /* Check if a 256bit AVX register is referenced inside of EXP. */
15257 static int
15259 {
15270 }
15272 /* Return needed mode for entity in optimize_mode_switching pass. */
15274 static int
15276 {
15278 {
15279 rtx link;
15281 /* Needed mode is set to AVX_U128_CLEAN if there are
15282 no 256bit modes used in function arguments. */
15284 link;
15286 {
15288 {
15293 }
15294 }
15297 }
15299 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15300 changes state only when a 256bit register is written to, but we need
15301 to prevent the compiler from moving optimal insertion point above
15302 eventual read from 256bit register. */
15307 }
15309 /* Return mode that i387 must be switched into
15310 prior to the execution of insn. */
15312 static int
15314 {
15317 /* The mode UNINITIALIZED is used to store control word after a
15318 function call or ASM pattern. The mode ANY specify that function
15319 has no requirements on the control word and make no changes in the
15320 bits we are interested in. */
15334 {
15357 }
15360 }
15362 /* Return mode that entity must be switched into
15363 prior to the execution of insn. */
15365 int
15367 {
15369 {
15379 }
15381 }
15383 /* Check if a 256bit AVX register is referenced in stores. */
15385 static void
15387 {
15389 {
15392 }
15393 }
15395 /* Calculate mode of upper 128bit AVX registers after the insn. */
15397 static int
15399 {
15406 /* We know that state is clean after CALL insn if there are no
15407 256bit registers used in the function return register. */
15409 {
15414 }
15416 /* Otherwise, return current mode. Remember that if insn
15417 references AVX 256bit registers, the mode was already changed
15418 to DIRTY from MODE_NEEDED. */
15420 }
15422 /* Return the mode that an insn results in. */
15424 int
15426 {
15428 {
15438 }
15439 }
15441 static int
15443 {
15444 tree arg;
15446 /* Entry mode is set to AVX_U128_DIRTY if there are
15447 256bit modes used in function arguments. */
15450 {
15455 }
15458 }
15460 /* Return a mode that ENTITY is assumed to be
15461 switched to at function entry. */
15463 int
15465 {
15467 {
15477 }
15478 }
15480 static int
15482 {
15485 /* Exit mode is set to AVX_U128_DIRTY if there are
15486 256bit modes used in the function return register. */
15491 }
15493 /* Return a mode that ENTITY is assumed to be
15494 switched to at function exit. */
15496 int
15498 {
15500 {
15510 }
15511 }
15513 /* Output code to initialize control word copies used by trunc?f?i and
15514 rounding patterns. CURRENT_MODE is set to current control word,
15515 while NEW_MODE is set to new control word. */
15517 static void
15519 {
15521 rtx new_mode;
15532 {
15534 {
15536 /* round toward zero (truncate) */
15542 /* round down toward -oo */
15549 /* round up toward +oo */
15556 /* mask precision exception for nearbyint() */
15563 }
15564 }
15565 else
15566 {
15568 {
15570 /* round toward zero (truncate) */
15576 /* round down toward -oo */
15582 /* round up toward +oo */
15588 /* mask precision exception for nearbyint() */
15595 }
15596 }
15602 }
15604 /* Emit vzeroupper. */
15606 void
15608 {
15611 /* Cancel automatic vzeroupper insertion if there are
15612 live call-saved SSE registers at the insertion point. */
15624 }
15626 /* Generate one or more insns to set ENTITY to MODE. */
15628 void
15630 {
15632 {
15647 }
15648 }
15650 /* Output code for INSN to convert a float to a signed int. OPERANDS
15651 are the insn operands. The output may be [HSD]Imode and the input
15652 operand may be [SDX]Fmode. */
15656 {
15661 /* Jump through a hoop or two for DImode, since the hardware has no
15662 non-popping instruction. We used to do this a different way, but
15663 that was somewhat fragile and broke with post-reload splitters. */
15673 else
15674 {
15679 else
15683 }
15686 }
15688 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15689 have the values zero or one, indicates the ffreep insn's operand
15690 from the OPERANDS array. */
15694 {
15696 #ifdef HAVE_AS_IX86_FFREEP
15698 #else
15699 {
15709 }
15710 #endif
15713 }
15716 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15717 should be used. UNORDERED_P is true when fucom should be used. */
15721 {
15727 {
15730 }
15731 else
15732 {
15735 }
15738 {
15742 else
15744 else
15747 else
15749 }
15756 {
15758 {
15761 }
15762 else
15764 }
15767 && stack_top_dies
15770 {
15771 /* If both the top of the 387 stack dies, and the other operand
15772 is also a stack register that dies, then this must be a
15773 `fcompp' float compare */
15776 {
15777 /* There is no double popping fcomi variant. Fortunately,
15778 eflags is immune from the fstp's cc clobbering. */
15781 else
15784 }
15785 else
15786 {
15789 else
15791 }
15792 }
15793 else
15794 {
15795 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15798 {
15806 NULL,
15807 NULL,
15814 NULL,
15815 NULL,
15816 NULL,
15817 NULL
15818 };
15833 }
15834 }
15836 void
15838 {
15841 #ifdef ASM_QUAD
15844 #else
15846 #endif
15849 }
15851 void
15853 {
15856 #ifdef ASM_QUAD
15859 #else
15861 #endif
15862 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15868 #if TARGET_MACHO
15870 {
15874 }
15875 #endif
15876 else
15879 }
15880 \f
15881 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15882 for the target. */
15884 void
15886 {
15887 rtx tmp;
15889 /* We play register width games, which are only valid after reload. */
15892 /* Avoid HImode and its attendant prefix byte. */
15897 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15899 {
15902 }
15905 }
15907 /* X is an unchanging MEM. If it is a constant pool reference, return
15908 the constant pool rtx, else NULL. */
15910 rtx
15912 {
15919 }
15921 void
15923 {
15931 {
15934 {
15940 }
15944 }
15948 {
15961 {
15968 }
15969 }
15973 {
15975 {
15976 #if TARGET_MACHO
15977 /* dynamic-no-pic */
15979 {
15980 rtx temp = ((reload_in_progress
15988 }
15990 {
15994 }
15997 else
15998 {
16006 }
16007 /* dynamic-no-pic */
16008 #endif
16009 }
16010 else
16011 {
16015 {
16021 }
16022 }
16023 }
16024 else
16025 {
16036 /* Force large constants in 64bit compilation into register
16037 to get them CSEed. */
16049 {
16050 /* If we are loading a floating point constant to a register,
16051 force the value to memory now, since we'll get better code
16052 out the back end. */
16056 {
16061 }
16062 }
16063 }
16066 }
16068 void
16070 {
16074 /* Force constants other than zero into memory. We do not know how
16075 the instructions used to build constants modify the upper 64 bits
16076 of the register, once we have that information we may be able
16077 to handle some of them more efficiently. */
16086 /* We need to check memory alignment for SSE mode since attribute
16087 can make operands unaligned. */
16092 {
16095 /* ix86_expand_vector_move_misalign() does not like constants ... */
16101 /* ... nor both arguments in memory. */
16109 }
16111 /* Make operand1 a register if it isn't already. */
16115 {
16118 }
16121 }
16123 /* Split 32-byte AVX unaligned load and store if needed. */
16125 static void
16127 {
16128 rtx m;
16135 {
16156 }
16159 {
16161 {
16168 }
16169 else
16171 }
16173 {
16175 {
16180 }
16181 else
16183 }
16184 else
16186 }
16188 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16189 straight to ix86_expand_vector_move. */
16190 /* Code generation for scalar reg-reg moves of single and double precision data:
16191 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16192 movaps reg, reg
16193 else
16194 movss reg, reg
16195 if (x86_sse_partial_reg_dependency == true)
16196 movapd reg, reg
16197 else
16198 movsd reg, reg
16200 Code generation for scalar loads of double precision data:
16201 if (x86_sse_split_regs == true)
16202 movlpd mem, reg (gas syntax)
16203 else
16204 movsd mem, reg
16206 Code generation for unaligned packed loads of single precision data
16207 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16208 if (x86_sse_unaligned_move_optimal)
16209 movups mem, reg
16211 if (x86_sse_partial_reg_dependency == true)
16212 {
16213 xorps reg, reg
16214 movlps mem, reg
16215 movhps mem+8, reg
16216 }
16217 else
16218 {
16219 movlps mem, reg
16220 movhps mem+8, reg
16221 }
16223 Code generation for unaligned packed loads of double precision data
16224 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16225 if (x86_sse_unaligned_move_optimal)
16226 movupd mem, reg
16228 if (x86_sse_split_regs == true)
16229 {
16230 movlpd mem, reg
16231 movhpd mem+8, reg
16232 }
16233 else
16234 {
16235 movsd mem, reg
16236 movhpd mem+8, reg
16237 }
16238 */
16240 void
16242 {
16250 {
16252 {
16257 /* FALLTHRU */
16265 }
16268 }
16271 {
16272 /* ??? If we have typed data, then it would appear that using
16273 movdqu is the only way to get unaligned data loaded with
16274 integer type. */
16276 {
16279 /* We will eventually emit movups based on insn attributes. */
16281 }
16283 {
16284 rtx zero;
16287 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16288 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16290 {
16291 /* We will eventually emit movups based on insn attributes. */
16294 }
16296 /* When SSE registers are split into halves, we can avoid
16297 writing to the top half twice. */
16299 {
16302 }
16303 else
16304 {
16305 /* ??? Not sure about the best option for the Intel chips.
16306 The following would seem to satisfy; the register is
16307 entirely cleared, breaking the dependency chain. We
16308 then store to the upper half, with a dependency depth
16309 of one. A rumor has it that Intel recommends two movsd
16310 followed by an unpacklpd, but this is unconfirmed. And
16311 given that the dependency depth of the unpacklpd would
16312 still be one, I'm not sure why this would be better. */
16314 }
16320 }
16321 else
16322 {
16324 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16325 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16327 {
16332 }
16336 else
16346 }
16347 }
16349 {
16351 {
16354 /* We will eventually emit movups based on insn attributes. */
16356 }
16358 {
16360 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16361 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16363 /* We will eventually emit movups based on insn attributes. */
16365 else
16366 {
16371 }
16372 }
16373 else
16374 {
16379 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16380 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16382 {
16385 }
16386 else
16387 {
16392 }
16393 }
16394 }
16395 else
16397 }
16399 /* Expand a push in MODE. This is some mode for which we do not support
16400 proper push instructions, at least from the registers that we expect
16401 the value to live in. */
16403 void
16405 {
16406 rtx tmp;
16416 /* When we push an operand onto stack, it has to be aligned at least
16417 at the function argument boundary. However since we don't have
16418 the argument type, we can't determine the actual argument
16419 boundary. */
16421 }
16423 /* Helper function of ix86_fixup_binary_operands to canonicalize
16424 operand order. Returns true if the operands should be swapped. */
16426 static bool
16428 rtx operands[])
16429 {
16434 /* If the operation is not commutative, we can't do anything. */
16438 /* Highest priority is that src1 should match dst. */
16444 /* Next highest priority is that immediate constants come second. */
16450 /* Lowest priority is that memory references should come second. */
16457 }
16460 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16461 destination to use for the operation. If different from the true
16462 destination in operands[0], a copy operation will be required. */
16464 rtx
16466 rtx operands[])
16467 {
16472 /* Canonicalize operand order. */
16474 {
16475 rtx temp;
16477 /* It is invalid to swap operands of different modes. */
16483 }
16485 /* Both source operands cannot be in memory. */
16487 {
16488 /* Optimization: Only read from memory once. */
16490 {
16493 }
16494 else
16496 }
16498 /* If the destination is memory, and we do not have matching source
16499 operands, do things in registers. */
16503 /* Source 1 cannot be a constant. */
16507 /* Source 1 cannot be a non-matching memory. */
16511 /* Improve address combine. */
16520 }
16522 /* Similarly, but assume that the destination has already been
16523 set up properly. */
16525 void
16528 {
16531 }
16533 /* Attempt to expand a binary operator. Make the expansion closer to the
16534 actual machine, then just general_operand, which will allow 3 separate
16535 memory references (one output, two input) in a single insn. */
16537 void
16539 rtx operands[])
16540 {
16547 /* Emit the instruction. */
16551 {
16552 /* Reload doesn't know about the flags register, and doesn't know that
16553 it doesn't want to clobber it. We can only do this with PLUS. */
16556 }
16560 {
16561 /* This is going to be an LEA; avoid splitting it later. */
16563 }
16564 else
16565 {
16568 }
16570 /* Fix up the destination if needed. */
16573 }
16575 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16576 the given OPERANDS. */
16578 void
16580 rtx operands[])
16581 {
16584 {
16587 }
16589 {
16592 }
16593 /* Optimize (__m128i) d | (__m128i) e and similar code
16594 when d and e are float vectors into float vector logical
16595 insn. In C/C++ without using intrinsics there is no other way
16596 to express vector logical operation on float vectors than
16597 to cast them temporarily to integer vectors. */
16599 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16608 {
16609 rtx dst;
16611 {
16618 {
16621 }
16622 else
16623 {
16628 }
16639 }
16640 }
16649 }
16651 /* Return TRUE or FALSE depending on whether the binary operator meets the
16652 appropriate constraints. */
16654 bool
16657 {
16662 /* Both source operands cannot be in memory. */
16666 /* Canonicalize operand order for commutative operators. */
16668 {
16672 }
16674 /* If the destination is memory, we must have a matching source operand. */
16678 /* Source 1 cannot be a constant. */
16682 /* Source 1 cannot be a non-matching memory. */
16684 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16692 }
16694 /* Attempt to expand a unary operator. Make the expansion closer to the
16695 actual machine, then just general_operand, which will allow 2 separate
16696 memory references (one output, one input) in a single insn. */
16698 void
16700 rtx operands[])
16701 {
16708 /* If the destination is memory, and we do not have matching source
16709 operands, do things in registers. */
16712 {
16715 else
16717 }
16719 /* When source operand is memory, destination must match. */
16723 /* Emit the instruction. */
16727 {
16728 /* Reload doesn't know about the flags register, and doesn't know that
16729 it doesn't want to clobber it. */
16732 }
16733 else
16734 {
16737 }
16739 /* Fix up the destination if needed. */
16742 }
16744 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16745 divisor are within the range [0-255]. */
16747 void
16750 {
16759 {
16772 }
16779 /* Use 8bit unsigned divimod if dividend and divisor are within
16780 the range [0-255]. */
16789 pc_rtx);
16794 /* Generate original signed/unsigned divimod. */
16799 /* Branch to the end. */
16803 /* Generate 8bit unsigned divide. */
16805 /* Don't use operands[0] for result of 8bit divide since not all
16806 registers support QImode ZERO_EXTRACT. */
16813 {
16816 }
16817 else
16818 {
16821 }
16823 /* Extract remainder from AH. */
16827 else
16828 {
16829 /* Need a new scratch register since the old one has result
16830 of 8bit divide. */
16834 }
16837 /* Zero extend quotient from AL. */
16843 }
16845 #define LEA_MAX_STALL (3)
16846 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16848 /* Increase given DISTANCE in half-cycles according to
16849 dependencies between PREV and NEXT instructions.
16850 Add 1 half-cycle if there is no dependency and
16851 go to next cycle if there is some dependecy. */
16853 static unsigned int
16855 {
16872 }
16874 /* Function checks if instruction INSN defines register number
16875 REGNO1 or REGNO2. */
16877 static bool
16879 rtx insn)
16880 {
16888 {
16890 }
16893 }
16895 /* Function checks if instruction INSN uses register number
16896 REGNO as a part of address expression. */
16898 static bool
16900 {
16908 }
16910 /* Search backward for non-agu definition of register number REGNO1
16911 or register number REGNO2 in basic block starting from instruction
16912 START up to head of basic block or instruction INSN.
16914 Function puts true value into *FOUND var if definition was found
16915 and false otherwise.
16917 Distance in half-cycles between START and found instruction or head
16918 of BB is added to DISTANCE and returned. */
16920 static int
16924 {
16934 {
16936 {
16939 {
16942 {
16945 }
16946 }
16949 }
16954 }
16957 }
16959 /* Search backward for non-agu definition of register number REGNO1
16960 or register number REGNO2 in INSN's basic block until
16961 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16962 2. Reach neighbour BBs boundary, or
16963 3. Reach agu definition.
16964 Returns the distance between the non-agu definition point and INSN.
16965 If no definition point, returns -1. */
16967 static int
16969 rtx insn)
16970 {
16981 {
16982 edge e;
16983 edge_iterator ei;
16988 {
16991 }
16997 else
16998 {
17003 {
17004 int bb_dist
17010 {
17017 }
17018 }
17021 }
17022 }
17024 /* get_attr_type may modify recog data. We want to make sure
17025 that recog data is valid for instruction INSN, on which
17026 distance_non_agu_define is called. INSN is unchanged here. */
17033 }
17035 /* Return the distance in half-cycles between INSN and the next
17036 insn that uses register number REGNO in memory address added
17037 to DISTANCE. Return -1 if REGNO0 is set.
17039 Put true value into *FOUND if register usage was found and
17040 false otherwise.
17041 Put true value into *REDEFINED if register redefinition was
17042 found and false otherwise. */
17044 static int
17048 {
17059 {
17061 {
17064 {
17065 /* Return DISTANCE if OP0 is used in memory
17066 address in NEXT. */
17069 }
17072 {
17073 /* Return -1 if OP0 is set in NEXT. */
17076 }
17079 }
17085 }
17088 }
17090 /* Return the distance between INSN and the next insn that uses
17091 register number REGNO0 in memory address. Return -1 if no such
17092 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17094 static int
17096 {
17108 {
17109 edge e;
17110 edge_iterator ei;
17115 {
17118 }
17124 else
17125 {
17131 {
17132 int bb_dist
17137 {
17144 }
17145 }
17148 }
17149 }
17155 }
17157 /* Define this macro to tune LEA priority vs ADD, it take effect when
17158 there is a dilemma of choicing LEA or ADD
17159 Negative value: ADD is more preferred than LEA
17160 Zero: Netrual
17161 Positive value: LEA is more preferred than ADD*/
17162 #define IX86_LEA_PRIORITY 0
17164 /* Return true if usage of lea INSN has performance advantage
17165 over a sequence of instructions. Instructions sequence has
17166 SPLIT_COST cycles higher latency than lea latency. */
17168 static bool
17171 {
17178 {
17179 /* If there is no non AGU operand definition, no AGU
17180 operand usage and split cost is 0 then both lea
17181 and non lea variants have same priority. Currently
17182 we prefer lea for 64 bit code and non lea on 32 bit
17183 code. */
17186 else
17188 }
17190 /* With longer definitions distance lea is more preferable.
17191 Here we change it to take into account splitting cost and
17192 lea priority. */
17195 /* If there is no use in memory addess then we just check
17196 that split cost exceeds AGU stall. */
17200 /* If this insn has both backward non-agu dependence and forward
17201 agu dependence, the one with short distance takes effect. */
17203 }
17205 /* Return true if it is legal to clobber flags by INSN and
17206 false otherwise. */
17208 static bool
17210 {
17213 bitmap live;
17216 {
17218 {
17225 }
17231 }
17235 }
17237 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17238 move and add to avoid AGU stalls. */
17240 bool
17242 {
17245 /* Check if we need to optimize. */
17249 /* Check it is correct to split here. */
17257 /* We need to split only adds with non destructive
17258 destination operand. */
17261 else
17263 }
17265 /* Return true if we should emit lea instruction instead of mov
17266 instruction. */
17268 bool
17270 {
17273 /* Check if we need to optimize. */
17277 /* Use lea for reg to reg moves only. */
17285 }
17287 /* Return true if we need to split lea into a sequence of
17288 instructions to avoid AGU stalls. */
17290 bool
17292 {
17298 /* Check we need to optimize. */
17302 /* Check it is correct to split here. */
17309 /* There should be at least two components in the address. */
17314 /* We should not split into add if non legitimate pic
17315 operand is used as displacement. */
17330 /* Compute how many cycles we will add to execution time
17331 if split lea into a sequence of instructions. */
17333 {
17334 /* Have to use mov instruction if non desctructive
17335 destination form is used. */
17339 /* Have to add index to base if both exist. */
17343 /* Have to use shift and adds if scale is 2 or greater. */
17345 {
17350 else
17352 }
17354 /* Have to use add instruction with immediate if
17355 disp is non zero. */
17359 /* Subtract the price of lea. */
17361 }
17364 }
17366 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17367 matches destination. RTX includes clobber of FLAGS_REG. */
17369 static void
17372 {
17379 }
17381 /* Return true if regno1 def is nearest to the insn. */
17383 static bool
17385 {
17392 {
17394 {
17397 }
17403 }
17405 /* None of the regs is defined in the bb. */
17407 }
17409 /* Split lea instructions into a sequence of instructions
17410 which are executed on ALU to avoid AGU stalls.
17411 It is assumed that it is allowed to clobber flags register
17412 at lea position. */
17414 void
17416 {
17432 {
17435 }
17438 {
17441 }
17447 {
17448 /* Case r1 = r1 + ... */
17450 {
17451 /* If we have a case r1 = r1 + C * r1 then we
17452 should use multiplication which is very
17453 expensive. Assume cost model is wrong if we
17454 have such case here. */
17459 }
17460 else
17461 {
17462 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17466 /* Use shift for scaling. */
17475 }
17476 }
17478 {
17481 }
17482 else
17483 {
17485 {
17488 }
17490 {
17493 }
17494 else
17495 {
17500 else
17501 {
17502 rtx tmp1;
17504 /* Find better operand for SET instruction, depending
17505 on which definition is farther from the insn. */
17508 else
17518 }
17521 }
17525 }
17526 }
17528 /* Return true if it is ok to optimize an ADD operation to LEA
17529 operation to avoid flag register consumation. For most processors,
17530 ADD is faster than LEA. For the processors like ATOM, if the
17531 destination register of LEA holds an actual address which will be
17532 used soon, LEA is better and otherwise ADD is better. */
17534 bool
17536 {
17541 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17549 }
17551 /* Return true if destination reg of SET_BODY is shift count of
17552 USE_BODY. */
17554 static bool
17556 {
17557 rtx set_dest;
17558 rtx shift_rtx;
17561 /* Retrieve destination of SET_BODY. */
17563 {
17572 use_body))
17577 }
17579 /* Retrieve shift count of USE_BODY. */
17581 {
17593 }
17601 {
17604 /* Return true if shift count is dest of SET_BODY. */
17606 {
17607 /* Add check since it can be invoked before register
17608 allocation in pre-reload schedule. */
17614 }
17615 }
17618 }
17620 /* Return true if destination reg of SET_INSN is shift count of
17621 USE_INSN. */
17623 bool
17625 {
17628 }
17630 /* Return TRUE or FALSE depending on whether the unary operator meets the
17631 appropriate constraints. */
17633 bool
17637 {
17638 /* If one of operands is memory, source and destination must match. */
17644 }
17646 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17647 are ok, keeping in mind the possible movddup alternative. */
17649 bool
17651 {
17657 }
17659 /* Post-reload splitter for converting an SF or DFmode value in an
17660 SSE register into an unsigned SImode. */
17662 void
17664 {
17675 /* Load up the value into the low element. We must ensure that the other
17676 elements are valid floats -- zero is the easiest such value. */
17678 {
17681 else
17683 }
17684 else
17685 {
17690 else
17692 }
17712 else
17717 }
17719 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17720 Expects the 64-bit DImode to be supplied in a pair of integral
17721 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17722 -mfpmath=sse, !optimize_size only. */
17724 void
17726 {
17730 rtx x;
17736 {
17739 }
17740 else
17741 {
17745 }
17753 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17756 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17757 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17758 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17759 (0x1.0p84 + double(fp_value_hi_xmm)).
17760 Note these exponents differ by 32. */
17764 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17765 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17774 /* Add the upper and lower DFmode values together. */
17777 else
17778 {
17782 }
17785 }
17787 /* Not used, but eases macroization of patterns. */
17788 void
17790 rtx input ATTRIBUTE_UNUSED)
17791 {
17793 }
17795 /* Convert an unsigned SImode value into a DFmode. Only currently used
17796 for SSE, but applicable anywhere. */
17798 void
17800 {
17801 REAL_VALUE_TYPE TWO31r;
17816 }
17818 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17819 32-bit mode; otherwise we have a direct convert instruction. */
17821 void
17823 {
17824 REAL_VALUE_TYPE TWO32r;
17842 }
17844 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17845 For x86_32, -mfpmath=sse, !optimize_size only. */
17846 void
17848 {
17849 REAL_VALUE_TYPE ONE16r;
17868 }
17870 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17871 a vector of unsigned ints VAL to vector of floats TARGET. */
17873 void
17875 {
17877 REAL_VALUE_TYPE TWO16r;
17884 else
17889 OPTAB_DIRECT);
17900 OPTAB_DIRECT);
17902 OPTAB_DIRECT);
17905 }
17907 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17908 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17909 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17910 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17912 rtx
17914 {
17915 REAL_VALUE_TYPE TWO31r;
17930 {
17936 }
17945 OPTAB_DIRECT);
17946 else
17947 {
17953 OPTAB_DIRECT);
17954 }
17957 }
17959 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17960 then replicate the value for all elements of the vector
17961 register. */
17963 rtx
17965 {
17967 rtvec v;
17971 {
17998 }
17999 }
18001 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18002 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18003 for an SSE register. If VECT is true, then replicate the mask for
18004 all elements of the vector register. If INVERT is true, then create
18005 a mask excluding the sign bit. */
18007 rtx
18009 {
18013 rtx v;
18014 rtx mask;
18016 /* Find the sign bit, sign extended to 2*HWI. */
18018 {
18038 else
18046 {
18049 }
18050 else
18051 {
18052 rtvec vec;
18058 {
18061 }
18062 else
18072 }
18077 }
18082 /* Force this value into the low part of a fp vector constant. */
18091 }
18093 /* Generate code for floating point ABS or NEG. */
18095 void
18097 rtx operands[])
18098 {
18109 {
18115 }
18117 /* NEG and ABS performed with SSE use bitwise mask operations.
18118 Create the appropriate mask now. */
18121 else
18131 {
18133 rtvec par;
18138 else
18139 {
18142 }
18144 }
18145 else
18147 }
18149 /* Expand a copysign operation. Special case operand 0 being a constant. */
18151 void
18153 {
18167 else
18171 {
18178 {
18181 else
18182 {
18186 }
18187 }
18197 else
18201 }
18202 else
18203 {
18213 else
18217 }
18218 }
18220 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18221 be a constant, and so has already been expanded into a vector constant. */
18223 void
18225 {
18241 {
18244 }
18245 }
18247 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18248 so we have to do two masks. */
18250 void
18252 {
18267 {
18268 /* Shouldn't happen often (it's useless, obviously), but when it does
18269 we'd generate incorrect code if we continue below. */
18272 }
18275 {
18286 }
18287 else
18288 {
18290 {
18292 }
18294 {
18298 }
18302 {
18305 }
18307 {
18312 }
18314 }
18318 }
18320 /* Return TRUE or FALSE depending on whether the first SET in INSN
18321 has source and destination with matching CC modes, and that the
18322 CC mode is at least as constrained as REQ_MODE. */
18324 bool
18326 {
18327 rtx set;
18338 {
18348 /* FALLTHRU */
18352 /* FALLTHRU */
18356 /* FALLTHRU */
18370 }
18373 }
18375 /* Generate insn patterns to do an integer compare of OPERANDS. */
18377 static rtx
18379 {
18386 /* This is very simple, but making the interface the same as in the
18387 FP case makes the rest of the code easier. */
18391 /* Return the test that should be put into the flags user, i.e.
18392 the bcc, scc, or cmov instruction. */
18394 }
18396 /* Figure out whether to use ordered or unordered fp comparisons.
18397 Return the appropriate mode to use. */
18399 enum machine_mode
18401 {
18402 /* ??? In order to make all comparisons reversible, we do all comparisons
18403 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18404 all forms trapping and nontrapping comparisons, we can make inequality
18405 comparisons trapping again, since it results in better code when using
18406 FCOM based compares. */
18408 }
18410 enum machine_mode
18412 {
18416 {
18419 }
18422 {
18423 /* Only zero flag is needed. */
18427 /* Codes needing carry flag. */
18430 /* Detect overflow checks. They need just the carry flag. */
18434 else
18438 /* Detect overflow checks. They need just the carry flag. */
18442 else
18444 /* Codes possibly doable only with sign flag when
18445 comparing against zero. */
18450 else
18451 /* For other cases Carry flag is not required. */
18453 /* Codes doable only with sign flag when comparing
18454 against zero, but we miss jump instruction for it
18455 so we need to use relational tests against overflow
18456 that thus needs to be zero. */
18461 else
18463 /* strcmp pattern do (use flags) and combine may ask us for proper
18464 mode. */
18469 }
18470 }
18472 /* Return the fixed registers used for condition codes. */
18474 static bool
18476 {
18480 }
18482 /* If two condition code modes are compatible, return a condition code
18483 mode which is compatible with both. Otherwise, return
18484 VOIDmode. */
18486 static enum machine_mode
18488 {
18505 {
18519 {
18533 }
18537 /* These are only compatible with themselves, which we already
18538 checked above. */
18540 }
18541 }
18544 /* Return a comparison we can do and that it is equivalent to
18545 swap_condition (code) apart possibly from orderedness.
18546 But, never change orderedness if TARGET_IEEE_FP, returning
18547 UNKNOWN in that case if necessary. */
18549 static enum rtx_code
18551 {
18553 {
18564 }
18565 }
18567 /* Return cost of comparison CODE using the best strategy for performance.
18568 All following functions do use number of instructions as a cost metrics.
18569 In future this should be tweaked to compute bytes for optimize_size and
18570 take into account performance of various instructions on various CPUs. */
18572 static int
18574 {
18577 /* The cost of code using bit-twiddling on %ah. */
18579 {
18602 }
18605 {
18612 }
18613 }
18615 /* Return strategy to use for floating-point. We assume that fcomi is always
18616 preferrable where available, since that is also true when looking at size
18617 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18619 enum ix86_fpcmp_strategy
18621 {
18622 /* Do fcomi/sahf based test when profitable. */
18631 }
18633 /* Swap, force into registers, or otherwise massage the two operands
18634 to a fp comparison. The operands are updated in place; the new
18635 comparison code is returned. */
18637 static enum rtx_code
18639 {
18645 /* All of the unordered compare instructions only work on registers.
18646 The same is true of the fcomi compare instructions. The XFmode
18647 compare instructions require registers except when comparing
18648 against zero or when converting operand 1 from fixed point to
18649 floating point. */
18658 {
18661 }
18662 else
18663 {
18664 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18665 things around if they appear profitable, otherwise force op0
18666 into a register. */
18672 {
18675 {
18676 rtx tmp;
18679 }
18680 }
18686 {
18691 {
18694 }
18695 else
18697 }
18698 }
18700 /* Try to rearrange the comparison to make it cheaper. */
18704 {
18705 rtx tmp;
18710 }
18715 }
18717 /* Convert comparison codes we use to represent FP comparison to integer
18718 code that will result in proper branch. Return UNKNOWN if no such code
18719 is available. */
18721 enum rtx_code
18723 {
18725 {
18748 }
18749 }
18751 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18753 static rtx
18755 {
18762 /* Do fcomi/sahf based test when profitable. */
18764 {
18769 tmp);
18777 tmp);
18786 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18793 /* In the unordered case, we have to check C2 for NaN's, which
18794 doesn't happen to work out to anything nice combination-wise.
18795 So do some bit twiddling on the value we've got in AH to come
18796 up with an appropriate set of condition codes. */
18800 {
18804 {
18807 }
18808 else
18809 {
18815 }
18820 {
18825 }
18826 else
18827 {
18830 }
18835 {
18838 }
18839 else
18840 {
18844 }
18849 {
18855 }
18856 else
18857 {
18860 }
18865 {
18870 }
18871 else
18872 {
18875 }
18880 {
18885 }
18886 else
18887 {
18890 }
18904 }
18909 }
18911 /* Return the test that should be put into the flags user, i.e.
18912 the bcc, scc, or cmov instruction. */
18915 const0_rtx);
18916 }
18918 static rtx
18920 {
18921 rtx ret;
18927 {
18930 }
18931 else
18935 }
18937 void
18939 {
18941 rtx tmp;
18944 {
18951 simple:
18955 pc_rtx);
18963 /* Expand DImode branch into multiple compare+branch. */
18964 {
18970 {
18973 }
18980 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18981 avoid two branches. This costs one extra insn, so disable when
18982 optimizing for size. */
18987 {
19005 }
19007 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19008 op1 is a constant and the low word is zero, then we can just
19009 examine the high word. Similarly for low word -1 and
19010 less-or-equal-than or greater-than. */
19014 {
19017 {
19020 }
19024 {
19027 }
19031 }
19033 /* Otherwise, we need two or three jumps. */
19042 {
19056 }
19058 /*
19059 * a < b =>
19060 * if (hi(a) < hi(b)) goto true;
19061 * if (hi(a) > hi(b)) goto false;
19062 * if (lo(a) < lo(b)) goto true;
19063 * false:
19064 */
19076 }
19081 }
19082 }
19084 /* Split branch based on floating point condition. */
19085 void
19088 {
19089 rtx condition;
19090 rtx i;
19093 {
19098 }
19101 tmp);
19103 /* Remove pushed operand from stack. */
19113 }
19115 void
19117 {
19118 rtx ret;
19125 }
19127 /* Expand comparison setting or clearing carry flag. Return true when
19128 successful and set pop for the operation. */
19129 static bool
19131 {
19135 /* Do not handle double-mode compares that go through special path. */
19140 {
19145 /* Shortcut: following common codes never translate
19146 into carry flag compares. */
19151 /* These comparisons require zero flag; swap operands so they won't. */
19154 {
19159 }
19161 /* Try to expand the comparison and verify that we end up with
19162 carry flag based comparison. This fails to be true only when
19163 we decide to expand comparison using arithmetic that is not
19164 too common scenario. */
19173 else
19182 }
19188 {
19193 /* Convert a==0 into (unsigned)a<1. */
19202 /* Convert a>b into b<a or a>=b-1. */
19206 {
19208 /* Bail out on overflow. We still can swap operands but that
19209 would force loading of the constant into register. */
19214 }
19215 else
19216 {
19221 }
19224 /* Convert a>=0 into (unsigned)a<0x80000000. */
19242 }
19243 /* Swapping operands may cause constant to appear as first operand. */
19245 {
19249 }
19253 }
19255 bool
19257 {
19281 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19282 HImode insns, we'd be swallowed in word prefix ops. */
19288 {
19292 HOST_WIDE_INT diff;
19295 /* Sign bit compares are better done using shifts than we do by using
19296 sbb. */
19299 {
19300 /* Detect overlap between destination and compare sources. */
19304 {
19305 rtx flags;
19314 {
19316 compare_code
19318 }
19320 /* To simplify rest of code, restrict to the GEU case. */
19322 {
19328 }
19329 else
19330 {
19333 reverse_condition_maybe_unordered
19335 else
19338 }
19347 else
19350 }
19351 else
19352 {
19355 else
19356 {
19361 }
19363 }
19366 {
19367 /*
19368 * cmpl op0,op1
19369 * sbbl dest,dest
19370 * [addl dest, ct]
19371 *
19372 * Size 5 - 8.
19373 */
19378 }
19380 {
19381 /*
19382 * cmpl op0,op1
19383 * sbbl dest,dest
19384 * orl $ct, dest
19385 *
19386 * Size 8.
19387 */
19391 }
19393 {
19394 /*
19395 * cmpl op0,op1
19396 * sbbl dest,dest
19397 * notl dest
19398 * [addl dest, cf]
19399 *
19400 * Size 8 - 11.
19401 */
19407 }
19408 else
19409 {
19410 /*
19411 * cmpl op0,op1
19412 * sbbl dest,dest
19413 * [notl dest]
19414 * andl cf - ct, dest
19415 * [addl dest, ct]
19416 *
19417 * Size 8 - 11.
19418 */
19421 {
19425 }
19435 }
19441 }
19444 {
19447 HOST_WIDE_INT tmp;
19452 {
19455 /* We may be reversing unordered compare to normal compare, that
19456 is not valid in general (we may convert non-trapping condition
19457 to trapping one), however on i386 we currently emit all
19458 comparisons unordered. */
19461 }
19462 else
19463 {
19466 }
19467 }
19472 {
19477 {
19482 }
19483 }
19485 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19489 {
19490 /* If lea code below could be used, only optimize
19491 if it results in a 2 insn sequence. */
19497 {
19498 /*
19499 * notl op1 (if necessary)
19500 * sarl $31, op1
19501 * orl cf, op1
19502 */
19504 {
19508 }
19519 }
19520 }
19528 {
19529 /*
19530 * xorl dest,dest
19531 * cmpl op1,op2
19532 * setcc dest
19533 * lea cf(dest*(ct-cf)),dest
19534 *
19535 * Size 14.
19536 *
19537 * This also catches the degenerate setcc-only case.
19538 */
19540 rtx tmp;
19546 /* On x86_64 the lea instruction operates on Pmode, so we need
19547 to get arithmetics done in proper mode to match. */
19550 else
19551 {
19552 rtx out1;
19555 nops++;
19557 {
19559 nops++;
19560 }
19561 }
19563 {
19565 nops++;
19566 }
19568 {
19571 else
19573 }
19578 }
19580 /*
19581 * General case: Jumpful:
19582 * xorl dest,dest cmpl op1, op2
19583 * cmpl op1, op2 movl ct, dest
19584 * setcc dest jcc 1f
19585 * decl dest movl cf, dest
19586 * andl (cf-ct),dest 1:
19587 * addl ct,dest
19588 *
19589 * Size 20. Size 14.
19590 *
19591 * This is reasonably steep, but branch mispredict costs are
19592 * high on modern cpus, so consider failing only if optimizing
19593 * for space.
19594 */
19599 {
19601 {
19608 {
19611 /* We may be reversing unordered compare to normal compare,
19612 that is not valid in general (we may convert non-trapping
19613 condition to trapping one), however on i386 we currently
19614 emit all comparisons unordered. */
19616 }
19617 else
19618 {
19622 }
19623 }
19626 {
19627 /* notl op1 (if needed)
19628 sarl $31, op1
19629 andl (cf-ct), op1
19630 addl ct, op1
19632 For x < 0 (resp. x <= -1) there will be no notl,
19633 so if possible swap the constants to get rid of the
19634 complement.
19635 True/false will be -1/0 while code below (store flag
19636 followed by decrement) is 0/-1, so the constants need
19637 to be exchanged once more. */
19640 {
19643 }
19644 else
19645 {
19649 }
19652 }
19653 else
19654 {
19658 constm1_rtx,
19660 }
19672 }
19673 }
19676 {
19677 /* Try a few things more with specific constants and a variable. */
19679 optab op;
19685 /* If one of the two operands is an interesting constant, load a
19686 constant with the above and mask it in with a logical operation. */
19689 {
19695 else
19697 }
19699 {
19705 else
19707 }
19708 else
19715 /* Recurse to get the constant loaded. */
19719 /* Mask in the interesting variable. */
19721 OPTAB_WIDEN);
19726 }
19728 /*
19729 * For comparison with above,
19730 *
19731 * movl cf,dest
19732 * movl ct,tmp
19733 * cmpl op1,op2
19734 * cmovcc tmp,dest
19735 *
19736 * Size 15.
19737 */
19759 }
19761 /* Swap, force into registers, or otherwise massage the two operands
19762 to an sse comparison with a mask result. Thus we differ a bit from
19763 ix86_prepare_fp_compare_args which expects to produce a flags result.
19765 The DEST operand exists to help determine whether to commute commutative
19766 operators. The POP0/POP1 operands are updated in place. The new
19767 comparison code is returned, or UNKNOWN if not implementable. */
19769 static enum rtx_code
19772 {
19773 rtx tmp;
19776 {
19779 /* AVX supports all the needed comparisons. */
19782 /* We have no LTGT as an operator. We could implement it with
19783 NE & ORDERED, but this requires an extra temporary. It's
19784 not clear that it's worth it. */
19791 /* These are supported directly. */
19798 /* AVX has 3 operand comparisons, no need to swap anything. */
19801 /* For commutative operators, try to canonicalize the destination
19802 operand to be first in the comparison - this helps reload to
19803 avoid extra moves. */
19806 /* FALLTHRU */
19812 /* These are not supported directly before AVX, and furthermore
19813 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19814 comparison operands to transform into something that is
19815 supported. */
19824 }
19827 }
19829 /* Detect conditional moves that exactly match min/max operational
19830 semantics. Note that this is IEEE safe, as long as we don't
19831 interchange the operands.
19833 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19834 and TRUE if the operation is successful and instructions are emitted. */
19836 static bool
19839 {
19842 rtx tmp;
19845 ;
19847 {
19851 }
19852 else
19859 else
19864 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19865 but MODE may be a vector mode and thus not appropriate. */
19867 {
19869 rtvec v;
19874 }
19875 else
19876 {
19879 }
19883 }
19885 /* Expand an sse vector comparison. Return the register with the result. */
19887 static rtx
19890 {
19893 rtx x;
19906 {
19909 }
19910 else
19914 }
19916 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19917 operations. This is used for both scalar and vector conditional moves. */
19919 static void
19921 {
19927 {
19929 }
19931 {
19935 }
19937 {
19942 }
19944 {
19948 }
19950 {
19958 op_true,
19959 op_false)));
19960 }
19961 else
19962 {
19971 {
19985 {
19991 }
20006 {
20012 }
20016 }
20020 else
20021 {
20027 else
20039 }
20040 }
20041 }
20043 /* Expand a floating-point conditional move. Return true if successful. */
20045 bool
20047 {
20055 {
20058 /* Since we've no cmove for sse registers, don't force bad register
20059 allocation just to gain access to it. Deny movcc when the
20060 comparison mode doesn't match the move mode. */
20079 }
20086 /* The floating point conditional move instructions don't directly
20087 support conditions resulting from a signed integer comparison. */
20091 {
20096 }
20103 }
20105 /* Expand a floating-point vector conditional move; a vcond operation
20106 rather than a movcc operation. */
20108 bool
20110 {
20112 rtx cmp;
20117 {
20118 rtx temp;
20120 {
20137 }
20139 OPTAB_DIRECT);
20142 }
20152 }
20154 /* Expand a signed/unsigned integral vector conditional move. */
20156 bool
20158 {
20168 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20169 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20178 {
20182 {
20188 }
20191 {
20197 }
20198 }
20207 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20211 ;
20212 else
20213 {
20214 /* Canonicalize the comparison to EQ, GT, GTU. */
20216 {
20233 /* FALLTHRU */
20243 }
20245 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20247 {
20249 {
20251 /* SSE4.1 supports EQ. */
20258 /* SSE4.2 supports GT/GTU. */
20265 }
20266 }
20268 /* Unsigned parallel compare is not supported by the hardware.
20269 Play some tricks to turn this into a signed comparison
20270 against 0. */
20272 {
20276 {
20281 {
20286 {
20293 }
20294 /* Subtract (-(INT MAX) - 1) from both operands to make
20295 them signed. */
20306 }
20313 /* Perform a parallel unsigned saturating subtraction. */
20326 }
20327 }
20328 }
20330 /* Allow the comparison to be done in one mode, but the movcc to
20331 happen in another mode. */
20333 {
20336 }
20337 else
20338 {
20344 }
20349 }
20351 /* Expand a variable vector permutation. */
20353 void
20355 {
20366 /* Number of elements in the vector. */
20372 {
20374 {
20375 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20376 an constant shuffle operand. With a tiny bit of effort we can
20377 use VPERMD instead. A re-interpretation stall for V4DFmode is
20378 unfortunate but there's no avoiding it.
20379 Similarly for V16HImode we don't have instructions for variable
20380 shuffling, while for V32QImode we can use after preparing suitable
20381 masks vpshufb; vpshufb; vpermq; vpor. */
20384 {
20388 }
20389 else
20390 {
20394 }
20397 /* Replicate the low bits of the V4DImode mask into V8SImode:
20398 mask = { A B C D }
20399 t1 = { A A B B C C D D }. */
20407 else
20410 /* Multiply the shuffle indicies by two. */
20412 OPTAB_DIRECT);
20414 /* Add one to the odd shuffle indicies:
20415 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20417 {
20420 }
20424 OPTAB_DIRECT);
20426 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20431 }
20434 {
20436 /* The VPERMD and VPERMPS instructions already properly ignore
20437 the high bits of the shuffle elements. No need for us to
20438 perform an AND ourselves. */
20441 else
20442 {
20448 }
20455 else
20456 {
20462 }
20466 /* By combining the two 128-bit input vectors into one 256-bit
20467 input vector, we can use VPERMD and VPERMPS for the full
20468 two-operand shuffle. */
20500 /* From mask create two adjusted masks, which contain the same
20501 bits as mask in the low 7 bits of each vector element.
20502 The first mask will have the most significant bit clear
20503 if it requests element from the same 128-bit lane
20504 and MSB set if it requests element from the other 128-bit lane.
20505 The second mask will have the opposite values of the MSB,
20506 and additionally will have its 128-bit lanes swapped.
20507 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20508 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20509 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20510 stands for other 12 bytes. */
20511 /* The bit whether element is from the same lane or the other
20512 lane is bit 4, so shift it up by 3 to the MSB position. */
20516 /* Clear MSB bits from the mask just in case it had them set. */
20518 /* After this t1 will have MSB set for elements from other lane. */
20520 /* Clear bits other than MSB. */
20522 /* Or in the lower bits from mask into t3. */
20524 /* And invert MSB bits in t1, so MSB is set for elements from the same
20525 lane. */
20527 /* Swap 128-bit lanes in t3. */
20532 /* And or in the lower bits from mask into t1. */
20535 {
20536 /* Each of these shuffles will put 0s in places where
20537 element from the other 128-bit lane is needed, otherwise
20538 will shuffle in the requested value. */
20541 /* For t3 the 128-bit lanes are swapped again. */
20546 /* And oring both together leads to the result. */
20549 }
20552 /* Similarly to the above one_operand_shuffle code,
20553 just for repeated twice for each operand. merge_two:
20554 code will merge the two results together. */
20576 }
20577 }
20580 {
20581 /* The XOP VPPERM insn supports three inputs. By ignoring the
20582 one_operand_shuffle special case, we avoid creating another
20583 set of constant vectors in memory. */
20586 /* mask = mask & {2*w-1, ...} */
20588 }
20589 else
20590 {
20591 /* mask = mask & {w-1, ...} */
20593 }
20601 /* For non-QImode operations, convert the word permutation control
20602 into a byte permutation control. */
20604 {
20609 /* Convert mask to vector of chars. */
20612 /* Replicate each of the input bytes into byte positions:
20613 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20614 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20615 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20622 else
20625 /* Convert it into the byte positions by doing
20626 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20632 }
20634 /* The actual shuffle operations all operate on V16QImode. */
20640 {
20642 }
20644 {
20646 }
20647 else
20648 {
20652 /* Shuffle the two input vectors independently. */
20658 merge_two:
20659 /* Then merge them together. The key is whether any given control
20660 element contained a bit set that indicates the second word. */
20664 {
20665 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20666 more shuffle to convert the V2DI input mask into a V4SI
20667 input mask. At which point the masking that expand_int_vcond
20668 will work as desired. */
20676 }
20693 }
20694 }
20696 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20697 true if we should do zero extension, else sign extension. HIGH_P is
20698 true if we want the N/2 high elements, else the low elements. */
20700 void
20702 {
20704 rtx tmp;
20707 {
20713 {
20717 else
20720 extract
20726 else
20729 extract
20735 else
20738 extract
20744 else
20750 else
20756 else
20761 }
20764 {
20767 }
20769 {
20770 /* Shift higher 8 bytes to lower 8 bytes. */
20775 }
20776 else
20780 }
20781 else
20782 {
20786 {
20790 else
20796 else
20802 else
20807 }
20811 else
20816 }
20817 }
20819 /* Expand conditional increment or decrement using adb/sbb instructions.
20820 The default case using setcc followed by the conditional move can be
20821 done by generic code. */
20822 bool
20824 {
20826 rtx flags;
20828 rtx compare_op;
20846 {
20849 }
20852 {
20856 reverse_condition_maybe_unordered
20858 else
20860 }
20864 /* Construct either adc or sbb insn. */
20866 {
20868 {
20883 }
20884 }
20885 else
20886 {
20888 {
20903 }
20904 }
20908 }
20911 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20912 but works for floating pointer parameters and nonoffsetable memories.
20913 For pushes, it returns just stack offsets; the values will be saved
20914 in the right order. Maximally three parts are generated. */
20916 static int
20918 {
20923 else
20929 /* Optimize constant pool reference to immediates. This is used by fp
20930 moves, that force all constants to memory to allow combining. */
20932 {
20936 }
20939 {
20940 /* The only non-offsetable memories we handle are pushes. */
20949 }
20952 {
20954 /* Caution: if we looked through a constant pool memory above,
20955 the operand may actually have a different mode now. That's
20956 ok, since we want to pun this all the way back to an integer. */
20960 }
20963 {
20966 else
20967 {
20971 {
20975 }
20977 {
20982 }
20984 {
20985 REAL_VALUE_TYPE r;
20990 {
20997 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
20998 long double may not be 80-bit. */
21007 }
21010 }
21011 else
21013 }
21014 }
21015 else
21016 {
21020 {
21023 {
21027 }
21029 {
21033 }
21035 {
21036 REAL_VALUE_TYPE r;
21042 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21045 = gen_int_mode
21048 DImode);
21049 else
21056 = gen_int_mode
21059 DImode);
21060 else
21062 }
21063 else
21065 }
21066 }
21069 }
21071 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21072 Return false when normal moves are needed; true when all required
21073 insns have been emitted. Operands 2-4 contain the input values
21074 int the correct order; operands 5-7 contain the output values. */
21076 void
21078 {
21086 /* The DFmode expanders may ask us to move double.
21087 For 64bit target this is single move. By hiding the fact
21088 here we simplify i386.md splitters. */
21090 {
21091 /* Optimize constant pool reference to immediates. This is used by
21092 fp moves, that force all constants to memory to allow combining. */
21099 {
21102 }
21103 else
21108 }
21110 /* The only non-offsettable memory we handle is push. */
21113 else
21120 /* When emitting push, take care for source operands on the stack. */
21123 {
21126 /* Compensate for the stack decrement by 4. */
21131 /* src_base refers to the stack pointer and is
21132 automatically decreased by emitted push. */
21136 }
21138 /* We need to do copy in the right order in case an address register
21139 of the source overlaps the destination. */
21141 {
21142 rtx tmp;
21145 {
21149 collisions++;
21150 }
21152 /* Collision in the middle part can be handled by reordering. */
21154 {
21157 }
21161 {
21163 {
21166 }
21167 else
21168 {
21171 }
21172 }
21174 /* If there are more collisions, we can't handle it by reordering.
21175 Do an lea to the last part and use only one colliding move. */
21177 {
21178 rtx base;
21184 /* Handle the case when the last part isn't valid for lea.
21185 Happens in 64-bit mode storing the 12-byte XFmode. */
21192 {
21195 }
21196 }
21197 }
21200 {
21202 {
21204 {
21209 }
21211 {
21214 }
21215 }
21216 else
21217 {
21218 /* In 64bit mode we don't have 32bit push available. In case this is
21219 register, it is OK - we will just use larger counterpart. We also
21220 retype memory - these comes from attempt to avoid REX prefix on
21221 moving of second half of TFmode value. */
21223 {
21225 {
21236 }
21240 }
21241 }
21245 }
21247 /* Choose correct order to not overwrite the source before it is copied. */
21257 {
21259 {
21262 }
21263 }
21264 else
21265 {
21267 {
21270 }
21271 }
21273 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21275 {
21284 }
21290 }
21292 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21293 left shift by a constant, either using a single shift or
21294 a sequence of add instructions. */
21296 static void
21298 {
21304 {
21308 }
21309 else
21310 {
21313 }
21314 }
21316 void
21318 {
21327 {
21332 {
21338 }
21339 else
21340 {
21348 }
21350 }
21357 {
21358 /* Assuming we've chosen a QImode capable registers, then 1 << N
21359 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21361 {
21377 }
21379 /* Otherwise, we can get the same results by manually performing
21380 a bit extract operation on bit 5/6, and then performing the two
21381 shifts. The two methods of getting 0/1 into low/high are exactly
21382 the same size. Avoiding the shift in the bit extract case helps
21383 pentium4 a bit; no one else seems to care much either way. */
21384 else
21385 {
21390 HOST_WIDE_INT bits;
21391 rtx x;
21394 {
21400 }
21401 else
21402 {
21408 }
21412 else
21420 }
21425 }
21428 {
21429 /* For -1 << N, we can avoid the shld instruction, because we
21430 know that we're shifting 0...31/63 ones into a -1. */
21434 else
21436 }
21437 else
21438 {
21446 }
21451 {
21457 }
21458 else
21459 {
21464 }
21465 }
21467 void
21469 {
21479 {
21484 {
21490 }
21492 {
21501 }
21502 else
21503 {
21511 }
21512 }
21513 else
21514 {
21526 {
21534 scratch));
21535 }
21536 else
21537 {
21542 }
21543 }
21544 }
21546 void
21548 {
21558 {
21563 {
21570 }
21571 else
21572 {
21580 }
21581 }
21582 else
21583 {
21595 {
21601 scratch));
21602 }
21603 else
21604 {
21609 }
21610 }
21611 }
21613 /* Predict just emitted jump instruction to be taken with probability PROB. */
21614 static void
21616 {
21620 }
21622 /* Helper function for the string operations below. Dest VARIABLE whether
21623 it is aligned to VALUE bytes. If true, jump to the label. */
21624 static rtx
21626 {
21631 else
21637 else
21640 }
21642 /* Adjust COUNTER by the VALUE. */
21643 static void
21645 {
21650 }
21652 /* Zero extend possibly SImode EXP to Pmode register. */
21653 rtx
21655 {
21657 }
21659 /* Divide COUNTREG by SCALE. */
21660 static rtx
21662 {
21663 rtx sc;
21675 }
21677 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21678 DImode for constant loop counts. */
21680 static enum machine_mode
21682 {
21690 }
21692 /* When SRCPTR is non-NULL, output simple loop to move memory
21693 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21694 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21695 equivalent loop to set memory by VALUE (supposed to be in MODE).
21697 The size is rounded down to whole number of chunk size moved at once.
21698 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21701 static void
21706 {
21711 rtx size;
21712 rtx x_addr;
21713 rtx y_addr;
21722 /* Those two should combine. */
21724 {
21728 }
21738 {
21742 /* When unrolling for chips that reorder memory reads and writes,
21743 we can save registers by using single temporary.
21744 Also using 4 temporaries is overkill in 32bit mode. */
21746 {
21748 {
21750 {
21751 destmem =
21753 srcmem =
21755 }
21757 }
21758 }
21759 else
21760 {
21764 {
21767 {
21768 srcmem =
21770 }
21772 }
21774 {
21776 {
21777 destmem =
21779 }
21781 }
21782 }
21783 }
21784 else
21786 {
21788 destmem =
21791 }
21801 {
21807 else
21809 }
21810 else
21818 {
21823 }
21825 }
21827 /* Output "rep; mov" instruction.
21828 Arguments have same meaning as for previous function */
21829 static void
21832 rtx count,
21834 {
21835 rtx destexp;
21836 rtx srcexp;
21837 rtx countreg;
21838 HOST_WIDE_INT rounded_count;
21840 /* If the size is known, it is shorter to use rep movs. */
21851 {
21858 }
21859 else
21860 {
21863 }
21865 {
21872 }
21873 else
21874 {
21879 }
21882 }
21884 /* Output "rep; stos" instruction.
21885 Arguments have same meaning as for previous function */
21886 static void
21889 rtx orig_value)
21890 {
21891 rtx destexp;
21892 rtx countreg;
21893 HOST_WIDE_INT rounded_count;
21900 {
21904 }
21905 else
21908 {
21913 }
21917 }
21919 static void
21922 {
21926 }
21928 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21929 static void
21932 {
21935 {
21940 {
21942 {
21945 }
21946 else
21949 }
21951 {
21954 else
21955 {
21958 }
21960 }
21962 {
21965 }
21967 {
21970 }
21972 {
21975 }
21977 }
21979 {
21985 }
21987 /* When there are stringops, we can cheaply increase dest and src pointers.
21988 Otherwise we save code size by maintaining offset (zero is readily
21989 available from preceding rep operation) and using x86 addressing modes.
21990 */
21992 {
21994 {
22001 }
22003 {
22010 }
22012 {
22019 }
22020 }
22021 else
22022 {
22024 rtx tmp;
22027 {
22038 }
22040 {
22053 }
22055 {
22064 }
22065 }
22066 }
22068 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22069 static void
22072 {
22073 count =
22079 }
22081 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22082 static void
22084 {
22085 rtx dest;
22088 {
22093 {
22095 {
22100 }
22101 else
22104 }
22106 {
22108 {
22111 }
22112 else
22113 {
22118 }
22120 }
22122 {
22126 }
22128 {
22132 }
22134 {
22138 }
22140 }
22142 {
22145 }
22147 {
22150 {
22154 }
22155 else
22156 {
22162 }
22165 }
22167 {
22170 {
22173 }
22174 else
22175 {
22179 }
22182 }
22184 {
22190 }
22192 {
22198 }
22200 {
22206 }
22207 }
22209 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22210 DESIRED_ALIGNMENT. */
22211 static void
22215 {
22217 {
22225 }
22227 {
22235 }
22237 {
22245 }
22247 }
22249 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22250 ALIGN_BYTES is how many bytes need to be copied. */
22251 static rtx
22254 {
22263 {
22268 }
22270 {
22281 }
22283 {
22289 {
22297 }
22300 }
22306 {
22318 }
22325 }
22327 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22328 DESIRED_ALIGNMENT. */
22329 static void
22332 {
22334 {
22341 }
22343 {
22350 }
22352 {
22359 }
22361 }
22363 /* Set enough from DST to align DST known to by aligned by ALIGN to
22364 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22365 static rtx
22368 {
22372 {
22377 }
22379 {
22386 }
22388 {
22395 }
22402 }
22404 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22405 static enum stringop_alg
22408 {
22411 /* Algorithms using the rep prefix want at least edi and ecx;
22412 additionally, memset wants eax and memcpy wants esi. Don't
22413 consider such algorithms if the user has appropriated those
22414 registers for their own purposes. */
22416 || (memset
22420 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22421 || (alg != rep_prefix_1_byte \
22422 && alg != rep_prefix_4_byte \
22423 && alg != rep_prefix_8_byte))
22426 /* Even if the string operation call is cold, we still might spend a lot
22427 of time processing large blocks. */
22432 else
22440 else
22444 /* rep; movq or rep; movl is the smallest variant. */
22446 {
22449 else
22451 }
22452 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22453 */
22457 {
22461 {
22462 /* We get here if the algorithms that were not libcall-based
22463 were rep-prefix based and we are unable to use rep prefixes
22464 based on global register usage. Break out of the loop and
22465 use the heuristic below. */
22469 {
22474 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22475 last non-libcall inline algorithm. */
22477 {
22478 /* When the current size is best to be copied by a libcall,
22479 but we are still forced to inline, run the heuristic below
22480 that will pick code for medium sized blocks. */
22484 }
22486 {
22489 }
22490 }
22491 }
22493 }
22494 /* When asked to inline the call anyway, try to pick meaningful choice.
22495 We look for maximal size of block that is faster to copy by hand and
22496 take blocks of at most of that size guessing that average size will
22497 be roughly half of the block.
22499 If this turns out to be bad, we might simply specify the preferred
22500 choice in ix86_costs. */
22503 {
22510 {
22517 }
22518 /* If there aren't any usable algorithms, then recursing on
22519 smaller sizes isn't going to find anything. Just return the
22520 simple byte-at-a-time copy loop. */
22522 {
22523 /* Pick something reasonable. */
22527 }
22536 }
22538 #undef ALG_USABLE_P
22539 }
22541 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22542 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22543 static int
22547 {
22550 {
22561 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22562 copying whole cacheline at once. */
22565 else
22569 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22570 copying whole cacheline at once. */
22573 else
22581 }
22590 }
22592 /* Return the smallest power of 2 greater than VAL. */
22593 static int
22595 {
22600 }
22602 /* Expand string move (memcpy) operation. Use i386 string operations
22603 when profitable. expand_setmem contains similar code. The code
22604 depends upon architecture, block size and alignment, but always has
22605 the same overall structure:
22607 1) Prologue guard: Conditional that jumps up to epilogues for small
22608 blocks that can be handled by epilogue alone. This is faster
22609 but also needed for correctness, since prologue assume the block
22610 is larger than the desired alignment.
22612 Optional dynamic check for size and libcall for large
22613 blocks is emitted here too, with -minline-stringops-dynamically.
22615 2) Prologue: copy first few bytes in order to get destination
22616 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22617 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22618 copied. We emit either a jump tree on power of two sized
22619 blocks, or a byte loop.
22621 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22622 with specified algorithm.
22624 4) Epilogue: code copying tail of the block that is too small to be
22625 handled by main body (or up to size guarded by prologue guard). */
22627 bool
22630 {
22631 rtx destreg;
22632 rtx srcreg;
22634 rtx tmp;
22648 /* i386 can do misaligned access on reasonably increased cost. */
22652 /* ALIGN is the minimum of destination and source alignment, but we care here
22653 just about destination alignment. */
22662 /* Make sure we don't need to care about overflow later on. */
22666 /* Step 0: Decide on preferred algorithm, desired alignment and
22667 size of chunks to be copied by main loop. */
22683 {
22708 }
22712 /* Step 1: Prologue guard. */
22714 /* Alignment code needs count to be in register. */
22716 {
22719 {
22720 align_bytes
22724 else
22726 }
22729 }
22732 /* Ensure that alignment prologue won't copy past end of block. */
22734 {
22736 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22737 Make sure it is power of 2. */
22741 {
22743 {
22744 /* If main algorithm works on QImode, no epilogue is needed.
22745 For small sizes just don't align anything. */
22748 else
22750 }
22751 }
22752 else
22753 {
22760 else
22762 }
22763 }
22765 /* Emit code to decide on runtime whether library call or inline should be
22766 used. */
22768 {
22770 {
22772 {
22776 }
22777 }
22778 else
22779 {
22788 }
22789 }
22791 /* Step 2: Alignment prologue. */
22794 {
22796 {
22797 /* Except for the first move in epilogue, we no longer know
22798 constant offset in aliasing info. It don't seems to worth
22799 the pain to maintain it for the first move, so throw away
22800 the info early. */
22804 desired_align);
22805 }
22806 else
22807 {
22808 /* If we know how many bytes need to be stored before dst is
22809 sufficiently aligned, maintain aliasing info accurately. */
22815 }
22821 {
22822 /* It is possible that we copied enough so the main loop will not
22823 execute. */
22833 else
22835 }
22836 }
22838 {
22843 }
22847 /* Step 3: Main loop. */
22850 {
22863 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22864 registers for 4 temporaries anyway. */
22867 expected_size);
22871 DImode);
22875 SImode);
22879 QImode);
22881 }
22882 /* Adjust properly the offset of src and dest memory for aliasing. */
22884 {
22889 }
22890 else
22891 {
22894 }
22896 /* Step 4: Epilogue to copy the remaining bytes. */
22897 epilogue:
22899 {
22900 /* When the main loop is done, COUNT_EXP might hold original count,
22901 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22902 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22903 bytes. Compensate if needed. */
22906 {
22907 tmp =
22910 OPTAB_DIRECT);
22913 }
22916 }
22920 epilogue_size_needed);
22924 }
22926 /* Helper function for memcpy. For QImode value 0xXY produce
22927 0xXYXYXYXY of wide specified by MODE. This is essentially
22928 a * 0x10101010, but we can do slightly better than
22929 synth_mult by unwinding the sequence by hand on CPUs with
22930 slow multiply. */
22931 static rtx
22933 {
22935 rtx tmp;
22942 {
22950 }
22959 nops--;
22964 {
22968 OPTAB_DIRECT);
22969 }
22970 else
22971 {
22977 else
22979 else
22980 {
22983 reg =
22985 }
22995 }
22996 }
22998 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
22999 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23000 alignment from ALIGN to DESIRED_ALIGN. */
23001 static rtx
23003 {
23004 rtx promoted_val;
23013 else
23017 }
23019 /* Expand string clear operation (bzero). Use i386 string operations when
23020 profitable. See expand_movmem comment for explanation of individual
23021 steps performed. */
23022 bool
23025 {
23026 rtx destreg;
23028 rtx tmp;
23044 /* i386 can do misaligned access on reasonably increased cost. */
23053 /* Make sure we don't need to care about overflow later on. */
23057 /* Step 0: Decide on preferred algorithm, desired alignment and
23058 size of chunks to be copied by main loop. */
23073 {
23098 }
23101 /* Step 1: Prologue guard. */
23103 /* Alignment code needs count to be in register. */
23105 {
23108 {
23109 align_bytes
23113 else
23115 }
23117 {
23122 }
23123 }
23124 /* Do the cheap promotion to allow better CSE across the
23125 main loop and epilogue (ie one load of the big constant in the
23126 front of all code. */
23130 /* Ensure that alignment prologue won't copy past end of block. */
23132 {
23134 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23135 Make sure it is power of 2. */
23138 /* To improve performance of small blocks, we jump around the VAL
23139 promoting mode. This mean that if the promoted VAL is not constant,
23140 we might not use it in the epilogue and have to use byte
23141 loop variant. */
23145 {
23147 {
23148 /* If main algorithm works on QImode, no epilogue is needed.
23149 For small sizes just don't align anything. */
23152 else
23154 }
23155 }
23156 else
23157 {
23164 else
23166 }
23167 }
23169 {
23178 }
23180 /* Step 2: Alignment prologue. */
23182 /* Do the expensive promotion once we branched off the small blocks. */
23189 {
23191 {
23192 /* Except for the first move in epilogue, we no longer know
23193 constant offset in aliasing info. It don't seems to worth
23194 the pain to maintain it for the first move, so throw away
23195 the info early. */
23198 desired_align);
23199 }
23200 else
23201 {
23202 /* If we know how many bytes need to be stored before dst is
23203 sufficiently aligned, maintain aliasing info accurately. */
23209 }
23215 {
23216 /* It is possible that we copied enough so the main loop will not
23217 execute. */
23227 else
23229 }
23230 }
23232 {
23238 }
23242 /* Step 3: Main loop. */
23245 {
23273 }
23274 /* Adjust properly the offset of src and dest memory for aliasing. */
23278 else
23281 /* Step 4: Epilogue to copy the remaining bytes. */
23284 {
23285 /* When the main loop is done, COUNT_EXP might hold original count,
23286 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23287 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23288 bytes. Compensate if needed. */
23291 {
23292 tmp =
23295 OPTAB_DIRECT);
23298 }
23301 }
23302 epilogue:
23304 {
23307 epilogue_size_needed);
23308 else
23310 epilogue_size_needed);
23311 }
23315 }
23317 /* Expand the appropriate insns for doing strlen if not just doing
23318 repnz; scasb
23320 out = result, initialized with the start address
23321 align_rtx = alignment of the address.
23322 scratch = scratch register, initialized with the startaddress when
23323 not aligned, otherwise undefined
23325 This is just the body. It needs the initializations mentioned above and
23326 some address computing at the end. These things are done in i386.md. */
23328 static void
23330 {
23332 rtx tmp;
23337 rtx mem;
23340 rtx cmp;
23346 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23348 /* Is there a known alignment and is it less than 4? */
23350 {
23353 /* Is there a known alignment and is it not 2? */
23355 {
23359 /* Leave just the 3 lower bits. */
23369 }
23370 else
23371 {
23372 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23373 check if is aligned to 4 - byte. */
23380 }
23384 /* Now compare the bytes. */
23386 /* Compare the first n unaligned byte on a byte per byte basis. */
23390 /* Increment the address. */
23393 /* Not needed with an alignment of 2 */
23395 {
23399 end_0_label);
23404 }
23407 end_0_label);
23410 }
23412 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23413 align this loop. It gives only huge programs, but does not help to
23414 speed up. */
23421 /* This formula yields a nonzero result iff one of the bytes is zero.
23422 This saves three branches inside loop and many cycles. */
23430 align_4_label);
23433 {
23439 /* If zero is not in the first two bytes, move two bytes forward. */
23445 reg,
23446 tmpreg)));
23447 /* Emit lea manually to avoid clobbering of flags. */
23455 reg2,
23456 out)));
23457 }
23458 else
23459 {
23461 /* Is zero in the first two bytes? */
23468 pc_rtx);
23472 /* Not in the first two. Move two bytes forward. */
23478 }
23480 /* Avoid branch in fixing the byte. */
23488 }
23490 /* Expand strlen. */
23492 bool
23494 {
23497 /* The generic case of strlen expander is long. Avoid it's
23498 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23501 && !TARGET_INLINE_ALL_STRINGOPS
23511 {
23512 /* Well it seems that some optimizer does not combine a call like
23513 foo(strlen(bar), strlen(bar));
23514 when the move and the subtraction is done here. It does calculate
23515 the length just once when these instructions are done inside of
23516 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23517 often used and I use one fewer register for the lifetime of
23518 output_strlen_unroll() this is better. */
23524 /* strlensi_unroll_1 returns the address of the zero at the end of
23525 the string, like memchr(), so compute the length by subtracting
23526 the start address. */
23528 }
23529 else
23530 {
23531 rtx unspec;
23533 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23546 /* If .md starts supporting :P, this can be done in .md. */
23552 }
23554 }
23556 /* For given symbol (function) construct code to compute address of it's PLT
23557 entry in large x86-64 PIC model. */
23558 static rtx
23560 {
23573 }
23575 rtx
23577 rtx callarg2,
23579 {
23580 /* We need to represent that SI and DI registers are clobbered
23581 by SYSV calls. */
23587 };
23597 {
23598 #if TARGET_MACHO
23601 #endif
23602 }
23603 else
23604 {
23605 /* Static functions and indirect calls don't need the pic register. */
23610 }
23613 {
23617 }
23627 {
23630 }
23639 {
23643 }
23647 {
23651 UNSPEC_MS_TO_SYSV_CALL);
23659 }
23668 }
23670 /* Output the assembly for a call instruction. */
23674 {
23680 {
23683 /* SEH epilogue detection requires the indirect branch case
23684 to include REX.W. */
23687 else
23692 }
23694 /* SEH unwinding can require an extra nop to be emitted in several
23695 circumstances. Determine if we have one of those. */
23697 {
23698 rtx i;
23701 {
23702 /* If we get to another real insn, we don't need the nop. */
23706 /* If we get to the epilogue note, prevent a catch region from
23707 being adjacent to the standard epilogue sequence. If non-
23708 call-exceptions, we'll have done this during epilogue emission. */
23710 && !flag_non_call_exceptions
23712 {
23715 }
23716 }
23718 /* If we didn't find a real insn following the call, prevent the
23719 unwinder from looking into the next function. */
23722 }
23726 else
23735 }
23736 \f
23737 /* Clear stack slot assignments remembered from previous functions.
23738 This is called from INIT_EXPANDERS once before RTL is emitted for each
23739 function. */
23743 {
23751 }
23753 /* Return a MEM corresponding to a stack slot with mode MODE.
23754 Allocate a new slot if necessary.
23756 The RTL for a function can have several slots available: N is
23757 which slot to use. */
23759 rtx
23761 {
23778 }
23780 static void
23782 {
23788 }
23789 \f
23790 /* Calculate the length of the memory address in the instruction encoding.
23791 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23792 or other prefixes. We never generate addr32 prefix for LEA insn. */
23794 int
23796 {
23813 /* If this is not LEA instruction, add the length of addr32 prefix. */
23818 len++;
23832 /* Rule of thumb:
23833 - esp as the base always wants an index,
23834 - ebp as the base always wants a displacement,
23835 - r12 as the base always wants an index,
23836 - r13 as the base always wants a displacement. */
23838 /* Register Indirect. */
23840 {
23841 /* esp (for its index) and ebp (for its displacement) need
23842 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23843 code. */
23850 len++;
23851 }
23853 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23854 is not disp32, but disp32(%rip), so for disp32
23855 SIB byte is needed, unless print_operand_address
23856 optimizes it into disp32(%rip) or (%rip) is implied
23857 by UNSPEC. */
23859 {
23862 {
23878 len++;
23879 }
23880 }
23881 else
23882 {
23883 /* Find the length of the displacement constant. */
23885 {
23888 else
23890 }
23891 /* ebp always wants a displacement. Similarly r13. */
23893 len++;
23895 /* An index requires the two-byte modrm form.... */
23897 /* ...like esp (or r12), which always wants an index. */
23901 len++;
23902 }
23905 }
23907 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23908 is set, expect that insn have 8bit immediate alternative. */
23909 int
23911 {
23917 {
23922 {
23925 {
23937 }
23939 {
23942 }
23943 }
23945 {
23955 /* Immediates for DImode instructions are encoded
23956 as 32bit sign extended values. */
23962 }
23963 }
23965 }
23967 /* Compute default value for "length_address" attribute. */
23968 int
23970 {
23974 {
23985 }
23990 {
23993 {
23998 constraints++;
24001 ;
24002 /* Skip ignored operands. */
24005 }
24007 }
24009 }
24011 /* Compute default value for "length_vex" attribute. It includes
24012 2 or 3 byte VEX prefix and 1 opcode byte. */
24014 int
24016 {
24019 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24020 byte VEX prefix. */
24024 /* We can always use 2 byte VEX prefix in 32bit. */
24032 {
24033 /* REX.W bit uses 3 byte VEX prefix. */
24037 }
24038 else
24039 {
24040 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24044 }
24047 }
24048 \f
24049 /* Return the maximum number of instructions a cpu can issue. */
24051 static int
24053 {
24055 {
24080 }
24081 }
24083 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24084 by DEP_INSN and nothing set by DEP_INSN. */
24086 static bool
24088 {
24091 /* Simplify the test for uninteresting insns. */
24099 {
24102 }
24107 {
24110 }
24111 else
24117 /* This test is true if the dependent insn reads the flags but
24118 not any other potentially set register. */
24126 }
24128 /* Return true iff USE_INSN has a memory address with operands set by
24129 SET_INSN. */
24131 bool
24133 {
24138 {
24141 }
24143 }
24145 static int
24147 {
24153 /* Anti and output dependencies have zero cost on all CPUs. */
24159 /* If we can't recognize the insns, we can't really do anything. */
24167 {
24169 /* Address Generation Interlock adds a cycle of latency. */
24171 {
24182 }
24186 /* ??? Compares pair with jump/setcc. */
24190 /* Floating point stores require value to be ready one cycle earlier. */
24200 /* INT->FP conversion is expensive. */
24204 /* There is one cycle extra latency between an FP op and a store. */
24212 /* Show ability of reorder buffer to hide latency of load by executing
24213 in parallel with previous instruction in case
24214 previous instruction is not needed to compute the address. */
24217 {
24218 /* Claim moves to take one cycle, as core can issue one load
24219 at time and the next load can start cycle later. */
24224 cost--;
24225 }
24231 /* The esp dependency is resolved before the instruction is really
24232 finished. */
24237 /* INT->FP conversion is expensive. */
24241 /* Show ability of reorder buffer to hide latency of load by executing
24242 in parallel with previous instruction in case
24243 previous instruction is not needed to compute the address. */
24246 {
24247 /* Claim moves to take one cycle, as core can issue one load
24248 at time and the next load can start cycle later. */
24254 else
24256 }
24272 /* Show ability of reorder buffer to hide latency of load by executing
24273 in parallel with previous instruction in case
24274 previous instruction is not needed to compute the address. */
24277 {
24281 /* Because of the difference between the length of integer and
24282 floating unit pipeline preparation stages, the memory operands
24283 for floating point are cheaper.
24285 ??? For Athlon it the difference is most probably 2. */
24288 else
24293 else
24295 }
24299 }
24302 }
24304 /* How many alternative schedules to try. This should be as wide as the
24305 scheduling freedom in the DFA, but no wider. Making this value too
24306 large results extra work for the scheduler. */
24308 static int
24310 {
24312 {
24323 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24324 as many instructions can be executed on a cycle, i.e.,
24325 issue_rate. I wonder why tuning for many CPUs does not do this. */
24328 /* Don't use lookahead for pre-reload schedule to save compile time. */
24333 }
24334 }
24336 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24337 execution. It is applied if
24338 (1) IMUL instruction is on the top of list;
24339 (2) There exists the only producer of independent IMUL instruction in
24340 ready list;
24341 (3) Put found producer on the top of ready list.
24342 Returns issue rate. */
24344 static int
24347 {
24352 sd_iterator_def sd_it;
24353 dep_t dep;
24356 /* Set up issue rate. */
24359 /* Do reodering for Atom only. */
24362 /* Do not perform ready list reodering for pre-reload schedule pass. */
24365 /* Nothing to do if ready list contains only 1 instruction. */
24369 /* Check that IMUL instruction is on the top of ready list. */
24382 /* Search for producer of independent IMUL instruction. */
24384 {
24388 /* Skip IMUL instruction. */
24398 {
24399 rtx con;
24410 {
24411 sd_iterator_def sd_it1;
24412 dep_t dep1;
24413 /* Check if there is no other dependee for IMUL. */
24416 {
24417 rtx pro;
24423 }
24426 }
24427 }
24430 }
24438 /* Put IMUL producer (ready[index]) at the top of ready list. */
24445 }
24447 static bool
24450 /* Returns true if lhs of insn is HW function argument register and set up
24451 is_spilled to true if it is likely spilled HW register. */
24452 static bool
24454 {
24455 rtx dst;
24459 /* Call instructions are not movable, ignore it. */
24470 {
24471 /* Is it likely spilled HW register? */
24476 }
24478 }
24480 /* Add output dependencies for chain of function adjacent arguments if only
24481 there is a move to likely spilled HW register. Return first argument
24482 if at least one dependence was added or NULL otherwise. */
24483 static rtx
24485 {
24486 rtx insn;
24493 /* Find nearest to call argument passing instruction. */
24495 {
24504 }
24508 {
24515 {
24518 }
24520 {
24521 /* Add output depdendence between two function arguments if chain
24522 of output arguments contains likely spilled HW registers. */
24526 }
24527 else
24529 }
24533 }
24535 /* Add output or anti dependency from insn to first_arg to restrict its code
24536 motion. */
24537 static void
24539 {
24540 rtx set;
24541 rtx tmp;
24548 {
24549 /* Add output dependency to the first function argument. */
24552 }
24553 /* Add anti dependency. */
24555 }
24557 /* Avoid cross block motion of function argument through adding dependency
24558 from the first non-jump instruction in bb. */
24559 static void
24561 {
24565 {
24567 {
24570 {
24573 }
24574 }
24578 }
24579 }
24581 /* Hook for pre-reload schedule - avoid motion of function arguments
24582 passed in likely spilled HW registers. */
24583 static void
24585 {
24586 rtx insn;
24594 {
24597 {
24598 /* Add dependee for first argument to predecessors if only
24599 region contains more than one block. */
24603 /* Skip trivial regions and region head blocks that can have
24604 predecessors outside of region. */
24606 {
24607 edge e;
24608 edge_iterator ei;
24609 /* Assume that region is SCC, i.e. all immediate predecessors
24610 of non-head block are in the same region. */
24612 {
24613 /* Avoid creating of loop-carried dependencies through
24614 using topological odering in region. */
24617 }
24618 }
24622 }
24623 }
24626 }
24628 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24629 HW registers to maximum, to schedule them at soon as possible. These are
24630 moves from function argument registers at the top of the function entry
24631 and moves from function return value registers after call. */
24632 static int
24634 {
24635 rtx set;
24645 {
24652 }
24655 }
24657 /* Model decoder of Core 2/i7.
24658 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24659 track the instruction fetch block boundaries and make sure that long
24660 (9+ bytes) instructions are assigned to D0. */
24662 /* Maximum length of an insn that can be handled by
24663 a secondary decoder unit. '8' for Core 2/i7. */
24666 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24667 '16' for Core 2/i7. */
24670 /* Maximum number of instructions decoder can handle per cycle.
24671 '6' for Core 2/i7. */
24675 ix86_first_cycle_multipass_data_t;
24677 const_ix86_first_cycle_multipass_data_t;
24679 /* A variable to store target state across calls to max_issue within
24680 one cycle. */
24684 /* Initialize DATA. */
24685 static void
24687 {
24688 ix86_first_cycle_multipass_data_t data
24695 }
24697 /* Advancing the cycle; reset ifetch block counts. */
24698 static void
24700 {
24707 }
24711 /* Filter out insns from ready_try that the core will not be able to issue
24712 on current cycle due to decoder. */
24713 static void
24714 core2i7_first_cycle_multipass_filter_ready_try
24717 {
24719 {
24720 rtx insn;
24730 (!first_cycle_insn_p
24732 /* ... or it would not fit into the ifetch block ... */
24734 /* ... or the decoder is full already ... */
24736 /* ... mask the insn out. */
24737 {
24742 }
24743 }
24744 }
24746 /* Prepare for a new round of multipass lookahead scheduling. */
24747 static void
24750 {
24751 ix86_first_cycle_multipass_data_t data
24753 const_ix86_first_cycle_multipass_data_t prev_data
24756 /* Restore the state from the end of the previous round. */
24760 /* Filter instructions that cannot be issued on current cycle due to
24761 decoder restrictions. */
24763 first_cycle_insn_p);
24764 }
24766 /* INSN is being issued in current solution. Account for its impact on
24767 the decoder model. */
24768 static void
24771 {
24772 ix86_first_cycle_multipass_data_t data
24774 const_ix86_first_cycle_multipass_data_t prev_data
24784 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24786 {
24789 }
24791 {
24795 }
24798 /* Filter out insns from ready_try that the core will not be able to issue
24799 on current cycle due to decoder. */
24802 }
24804 /* Revert the effect on ready_try. */
24805 static void
24809 {
24810 const_ix86_first_cycle_multipass_data_t data
24813 sbitmap_iterator sbi;
24817 {
24819 }
24820 }
24822 /* Save the result of multipass lookahead scheduling for the next round. */
24823 static void
24825 {
24826 const_ix86_first_cycle_multipass_data_t data
24828 ix86_first_cycle_multipass_data_t next_data
24832 {
24835 }
24836 }
24838 /* Deallocate target data. */
24839 static void
24841 {
24842 ix86_first_cycle_multipass_data_t data
24846 {
24850 }
24851 }
24853 /* Prepare for scheduling pass. */
24854 static void
24858 {
24859 /* Install scheduling hooks for current CPU. Some of these hooks are used
24860 in time-critical parts of the scheduler, so we only set them up when
24861 they are actually used. */
24863 {
24866 /* Do not perform multipass scheduling for pre-reload schedule
24867 to save compile time. */
24869 {
24885 /* Set decoder parameters. */
24890 }
24891 /* ... Fall through ... */
24901 }
24902 }
24904 \f
24905 /* Compute the alignment given to a constant that is being placed in memory.
24906 EXP is the constant and ALIGN is the alignment that the object would
24907 ordinarily have.
24908 The value of this function is used instead of that alignment to align
24909 the object. */
24911 int
24913 {
24916 {
24921 }
24927 }
24929 /* Compute the alignment for a static variable.
24930 TYPE is the data type, and ALIGN is the alignment that
24931 the object would ordinarily have. The value of this function is used
24932 instead of that alignment to align the object. */
24934 int
24936 {
24947 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24948 to 16byte boundary. */
24950 {
24957 }
24960 {
24965 }
24967 {
24974 }
24979 {
24984 }
24987 {
24992 }
24995 }
24997 /* Compute the alignment for a local variable or a stack slot. EXP is
24998 the data type or decl itself, MODE is the widest mode available and
24999 ALIGN is the alignment that the object would ordinarily have. The
25000 value of this macro is used instead of that alignment to align the
25001 object. */
25003 unsigned int
25006 {
25010 {
25013 }
25014 else
25015 {
25018 }
25020 /* Don't do dynamic stack realignment for long long objects with
25021 -mpreferred-stack-boundary=2. */
25030 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25031 register in MODE. We will return the largest alignment of XF
25032 and DF. */
25034 {
25038 }
25040 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25041 to 16byte boundary. Exact wording is:
25043 An array uses the same alignment as its elements, except that a local or
25044 global array variable of length at least 16 bytes or
25045 a C99 variable-length array variable always has alignment of at least 16 bytes.
25047 This was added to allow use of aligned SSE instructions at arrays. This
25048 rule is meant for static storage (where compiler can not do the analysis
25049 by itself). We follow it for automatic variables only when convenient.
25050 We fully control everything in the function compiled and functions from
25051 other unit can not rely on the alignment.
25053 Exclude va_list type. It is the common case of local array where
25054 we can not benefit from the alignment. */
25057 {
25067 }
25069 {
25074 }
25076 {
25082 }
25087 {
25092 }
25095 {
25101 }
25103 }
25105 /* Compute the minimum required alignment for dynamic stack realignment
25106 purposes for a local variable, parameter or a stack slot. EXP is
25107 the data type or decl itself, MODE is its mode and ALIGN is the
25108 alignment that the object would ordinarily have. */
25110 unsigned int
25113 {
25117 {
25120 }
25121 else
25122 {
25125 }
25130 /* Don't do dynamic stack realignment for long long objects with
25131 -mpreferred-stack-boundary=2. */
25138 }
25139 \f
25140 /* Find a location for the static chain incoming to a nested function.
25141 This is a register, unless all free registers are used by arguments. */
25143 static rtx
25145 {
25152 {
25153 /* We always use R10 in 64-bit mode. */
25155 }
25156 else
25157 {
25158 tree fntype;
25161 /* By default in 32-bit mode we use ECX to pass the static chain. */
25167 {
25168 /* Fastcall functions use ecx/edx for arguments, which leaves
25169 us with EAX for the static chain.
25170 Thiscall functions use ecx for arguments, which also
25171 leaves us with EAX for the static chain. */
25173 }
25175 {
25176 /* Thiscall functions use ecx for arguments, which leaves
25177 us with EAX and EDX for the static chain.
25178 We are using for abi-compatibility EAX. */
25180 }
25182 {
25183 /* For regparm 3, we have no free call-clobbered registers in
25184 which to store the static chain. In order to implement this,
25185 we have the trampoline push the static chain to the stack.
25186 However, we can't push a value below the return address when
25187 we call the nested function directly, so we have to use an
25188 alternate entry point. For this we use ESI, and have the
25189 alternate entry point push ESI, so that things appear the
25190 same once we're executing the nested function. */
25192 {
25198 }
25200 }
25201 }
25204 }
25206 /* Emit RTL insns to initialize the variable parts of a trampoline.
25207 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25208 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25209 to be passed to the target function. */
25211 static void
25213 {
25221 {
25224 /* Load the function address to r11. Try to load address using
25225 the shorter movl instead of movabs. We may want to support
25226 movq for kernel mode, but kernel does not use trampolines at
25227 the moment. FNADDR is a 32bit address and may not be in
25228 DImode when ptr_mode == SImode. Always use movl in this
25229 case. */
25232 {
25241 }
25242 else
25243 {
25250 }
25252 /* Load static chain using movabs to r10. Use the shorter movl
25253 instead of movabs when ptr_mode == SImode. */
25255 {
25258 }
25259 else
25260 {
25263 }
25272 /* Jump to r11; the last (unused) byte is a nop, only there to
25273 pad the write out to a single 32-bit store. */
25277 }
25278 else
25279 {
25282 /* Depending on the static chain location, either load a register
25283 with a constant, or push the constant to the stack. All of the
25284 instructions are the same size. */
25287 {
25289 {
25296 }
25297 }
25298 else
25313 /* Compute offset from the end of the jmp to the target function.
25314 In the case in which the trampoline stores the static chain on
25315 the stack, we need to skip the first insn which pushes the
25316 (call-saved) register static chain; this push is 1 byte. */
25323 }
25327 #ifdef HAVE_ENABLE_EXECUTE_STACK
25328 #ifdef CHECK_EXECUTE_STACK_ENABLED
25330 #endif
25333 #endif
25334 }
25335 \f
25336 /* The following file contains several enumerations and data structures
25337 built from the definitions in i386-builtin-types.def. */
25341 /* Table for the ix86 builtin non-function types. */
25344 /* Retrieve an element from the above table, building some of
25345 the types lazily. */
25347 static tree
25349 {
25361 {
25369 }
25370 else
25371 {
25377 else
25385 }
25389 }
25391 /* Table for the ix86 builtin function types. */
25394 /* Retrieve an element from the above table, building some of
25395 the types lazily. */
25397 static tree
25399 {
25400 tree type;
25409 {
25417 {
25420 }
25423 }
25424 else
25425 {
25431 }
25435 }
25438 /* Codes for all the SSE/MMX builtins. */
25439 enum ix86_builtins
25440 {
25441 IX86_BUILTIN_ADDPS,
25442 IX86_BUILTIN_ADDSS,
25443 IX86_BUILTIN_DIVPS,
25444 IX86_BUILTIN_DIVSS,
25445 IX86_BUILTIN_MULPS,
25446 IX86_BUILTIN_MULSS,
25447 IX86_BUILTIN_SUBPS,
25448 IX86_BUILTIN_SUBSS,
25450 IX86_BUILTIN_CMPEQPS,
25451 IX86_BUILTIN_CMPLTPS,
25452 IX86_BUILTIN_CMPLEPS,
25453 IX86_BUILTIN_CMPGTPS,
25454 IX86_BUILTIN_CMPGEPS,
25455 IX86_BUILTIN_CMPNEQPS,
25456 IX86_BUILTIN_CMPNLTPS,
25457 IX86_BUILTIN_CMPNLEPS,
25458 IX86_BUILTIN_CMPNGTPS,
25459 IX86_BUILTIN_CMPNGEPS,
25460 IX86_BUILTIN_CMPORDPS,
25461 IX86_BUILTIN_CMPUNORDPS,
25462 IX86_BUILTIN_CMPEQSS,
25463 IX86_BUILTIN_CMPLTSS,
25464 IX86_BUILTIN_CMPLESS,
25465 IX86_BUILTIN_CMPNEQSS,
25466 IX86_BUILTIN_CMPNLTSS,
25467 IX86_BUILTIN_CMPNLESS,
25468 IX86_BUILTIN_CMPNGTSS,
25469 IX86_BUILTIN_CMPNGESS,
25470 IX86_BUILTIN_CMPORDSS,
25471 IX86_BUILTIN_CMPUNORDSS,
25473 IX86_BUILTIN_COMIEQSS,
25474 IX86_BUILTIN_COMILTSS,
25475 IX86_BUILTIN_COMILESS,
25476 IX86_BUILTIN_COMIGTSS,
25477 IX86_BUILTIN_COMIGESS,
25478 IX86_BUILTIN_COMINEQSS,
25479 IX86_BUILTIN_UCOMIEQSS,
25480 IX86_BUILTIN_UCOMILTSS,
25481 IX86_BUILTIN_UCOMILESS,
25482 IX86_BUILTIN_UCOMIGTSS,
25483 IX86_BUILTIN_UCOMIGESS,
25484 IX86_BUILTIN_UCOMINEQSS,
25486 IX86_BUILTIN_CVTPI2PS,
25487 IX86_BUILTIN_CVTPS2PI,
25488 IX86_BUILTIN_CVTSI2SS,
25489 IX86_BUILTIN_CVTSI642SS,
25490 IX86_BUILTIN_CVTSS2SI,
25491 IX86_BUILTIN_CVTSS2SI64,
25492 IX86_BUILTIN_CVTTPS2PI,
25493 IX86_BUILTIN_CVTTSS2SI,
25494 IX86_BUILTIN_CVTTSS2SI64,
25496 IX86_BUILTIN_MAXPS,
25497 IX86_BUILTIN_MAXSS,
25498 IX86_BUILTIN_MINPS,
25499 IX86_BUILTIN_MINSS,
25501 IX86_BUILTIN_LOADUPS,
25502 IX86_BUILTIN_STOREUPS,
25503 IX86_BUILTIN_MOVSS,
25505 IX86_BUILTIN_MOVHLPS,
25506 IX86_BUILTIN_MOVLHPS,
25507 IX86_BUILTIN_LOADHPS,
25508 IX86_BUILTIN_LOADLPS,
25509 IX86_BUILTIN_STOREHPS,
25510 IX86_BUILTIN_STORELPS,
25512 IX86_BUILTIN_MASKMOVQ,
25513 IX86_BUILTIN_MOVMSKPS,
25514 IX86_BUILTIN_PMOVMSKB,
25516 IX86_BUILTIN_MOVNTPS,
25517 IX86_BUILTIN_MOVNTQ,
25519 IX86_BUILTIN_LOADDQU,
25520 IX86_BUILTIN_STOREDQU,
25522 IX86_BUILTIN_PACKSSWB,
25523 IX86_BUILTIN_PACKSSDW,
25524 IX86_BUILTIN_PACKUSWB,
25526 IX86_BUILTIN_PADDB,
25527 IX86_BUILTIN_PADDW,
25528 IX86_BUILTIN_PADDD,
25529 IX86_BUILTIN_PADDQ,
25530 IX86_BUILTIN_PADDSB,
25531 IX86_BUILTIN_PADDSW,
25532 IX86_BUILTIN_PADDUSB,
25533 IX86_BUILTIN_PADDUSW,
25534 IX86_BUILTIN_PSUBB,
25535 IX86_BUILTIN_PSUBW,
25536 IX86_BUILTIN_PSUBD,
25537 IX86_BUILTIN_PSUBQ,
25538 IX86_BUILTIN_PSUBSB,
25539 IX86_BUILTIN_PSUBSW,
25540 IX86_BUILTIN_PSUBUSB,
25541 IX86_BUILTIN_PSUBUSW,
25543 IX86_BUILTIN_PAND,
25544 IX86_BUILTIN_PANDN,
25545 IX86_BUILTIN_POR,
25546 IX86_BUILTIN_PXOR,
25548 IX86_BUILTIN_PAVGB,
25549 IX86_BUILTIN_PAVGW,
25551 IX86_BUILTIN_PCMPEQB,
25552 IX86_BUILTIN_PCMPEQW,
25553 IX86_BUILTIN_PCMPEQD,
25554 IX86_BUILTIN_PCMPGTB,
25555 IX86_BUILTIN_PCMPGTW,
25556 IX86_BUILTIN_PCMPGTD,
25558 IX86_BUILTIN_PMADDWD,
25560 IX86_BUILTIN_PMAXSW,
25561 IX86_BUILTIN_PMAXUB,
25562 IX86_BUILTIN_PMINSW,
25563 IX86_BUILTIN_PMINUB,
25565 IX86_BUILTIN_PMULHUW,
25566 IX86_BUILTIN_PMULHW,
25567 IX86_BUILTIN_PMULLW,
25569 IX86_BUILTIN_PSADBW,
25570 IX86_BUILTIN_PSHUFW,
25572 IX86_BUILTIN_PSLLW,
25573 IX86_BUILTIN_PSLLD,
25574 IX86_BUILTIN_PSLLQ,
25575 IX86_BUILTIN_PSRAW,
25576 IX86_BUILTIN_PSRAD,
25577 IX86_BUILTIN_PSRLW,
25578 IX86_BUILTIN_PSRLD,
25579 IX86_BUILTIN_PSRLQ,
25580 IX86_BUILTIN_PSLLWI,
25581 IX86_BUILTIN_PSLLDI,
25582 IX86_BUILTIN_PSLLQI,
25583 IX86_BUILTIN_PSRAWI,
25584 IX86_BUILTIN_PSRADI,
25585 IX86_BUILTIN_PSRLWI,
25586 IX86_BUILTIN_PSRLDI,
25587 IX86_BUILTIN_PSRLQI,
25589 IX86_BUILTIN_PUNPCKHBW,
25590 IX86_BUILTIN_PUNPCKHWD,
25591 IX86_BUILTIN_PUNPCKHDQ,
25592 IX86_BUILTIN_PUNPCKLBW,
25593 IX86_BUILTIN_PUNPCKLWD,
25594 IX86_BUILTIN_PUNPCKLDQ,
25596 IX86_BUILTIN_SHUFPS,
25598 IX86_BUILTIN_RCPPS,
25599 IX86_BUILTIN_RCPSS,
25600 IX86_BUILTIN_RSQRTPS,
25601 IX86_BUILTIN_RSQRTPS_NR,
25602 IX86_BUILTIN_RSQRTSS,
25603 IX86_BUILTIN_RSQRTF,
25604 IX86_BUILTIN_SQRTPS,
25605 IX86_BUILTIN_SQRTPS_NR,
25606 IX86_BUILTIN_SQRTSS,
25608 IX86_BUILTIN_UNPCKHPS,
25609 IX86_BUILTIN_UNPCKLPS,
25611 IX86_BUILTIN_ANDPS,
25612 IX86_BUILTIN_ANDNPS,
25613 IX86_BUILTIN_ORPS,
25614 IX86_BUILTIN_XORPS,
25616 IX86_BUILTIN_EMMS,
25617 IX86_BUILTIN_LDMXCSR,
25618 IX86_BUILTIN_STMXCSR,
25619 IX86_BUILTIN_SFENCE,
25621 IX86_BUILTIN_FXSAVE,
25622 IX86_BUILTIN_FXRSTOR,
25623 IX86_BUILTIN_FXSAVE64,
25624 IX86_BUILTIN_FXRSTOR64,
25626 IX86_BUILTIN_XSAVE,
25627 IX86_BUILTIN_XRSTOR,
25628 IX86_BUILTIN_XSAVE64,
25629 IX86_BUILTIN_XRSTOR64,
25631 IX86_BUILTIN_XSAVEOPT,
25632 IX86_BUILTIN_XSAVEOPT64,
25634 /* 3DNow! Original */
25635 IX86_BUILTIN_FEMMS,
25636 IX86_BUILTIN_PAVGUSB,
25637 IX86_BUILTIN_PF2ID,
25638 IX86_BUILTIN_PFACC,
25639 IX86_BUILTIN_PFADD,
25640 IX86_BUILTIN_PFCMPEQ,
25641 IX86_BUILTIN_PFCMPGE,
25642 IX86_BUILTIN_PFCMPGT,
25643 IX86_BUILTIN_PFMAX,
25644 IX86_BUILTIN_PFMIN,
25645 IX86_BUILTIN_PFMUL,
25646 IX86_BUILTIN_PFRCP,
25647 IX86_BUILTIN_PFRCPIT1,
25648 IX86_BUILTIN_PFRCPIT2,
25649 IX86_BUILTIN_PFRSQIT1,
25650 IX86_BUILTIN_PFRSQRT,
25651 IX86_BUILTIN_PFSUB,
25652 IX86_BUILTIN_PFSUBR,
25653 IX86_BUILTIN_PI2FD,
25654 IX86_BUILTIN_PMULHRW,
25656 /* 3DNow! Athlon Extensions */
25657 IX86_BUILTIN_PF2IW,
25658 IX86_BUILTIN_PFNACC,
25659 IX86_BUILTIN_PFPNACC,
25660 IX86_BUILTIN_PI2FW,
25661 IX86_BUILTIN_PSWAPDSI,
25662 IX86_BUILTIN_PSWAPDSF,
25664 /* SSE2 */
25665 IX86_BUILTIN_ADDPD,
25666 IX86_BUILTIN_ADDSD,
25667 IX86_BUILTIN_DIVPD,
25668 IX86_BUILTIN_DIVSD,
25669 IX86_BUILTIN_MULPD,
25670 IX86_BUILTIN_MULSD,
25671 IX86_BUILTIN_SUBPD,
25672 IX86_BUILTIN_SUBSD,
25674 IX86_BUILTIN_CMPEQPD,
25675 IX86_BUILTIN_CMPLTPD,
25676 IX86_BUILTIN_CMPLEPD,
25677 IX86_BUILTIN_CMPGTPD,
25678 IX86_BUILTIN_CMPGEPD,
25679 IX86_BUILTIN_CMPNEQPD,
25680 IX86_BUILTIN_CMPNLTPD,
25681 IX86_BUILTIN_CMPNLEPD,
25682 IX86_BUILTIN_CMPNGTPD,
25683 IX86_BUILTIN_CMPNGEPD,
25684 IX86_BUILTIN_CMPORDPD,
25685 IX86_BUILTIN_CMPUNORDPD,
25686 IX86_BUILTIN_CMPEQSD,
25687 IX86_BUILTIN_CMPLTSD,
25688 IX86_BUILTIN_CMPLESD,
25689 IX86_BUILTIN_CMPNEQSD,
25690 IX86_BUILTIN_CMPNLTSD,
25691 IX86_BUILTIN_CMPNLESD,
25692 IX86_BUILTIN_CMPORDSD,
25693 IX86_BUILTIN_CMPUNORDSD,
25695 IX86_BUILTIN_COMIEQSD,
25696 IX86_BUILTIN_COMILTSD,
25697 IX86_BUILTIN_COMILESD,
25698 IX86_BUILTIN_COMIGTSD,
25699 IX86_BUILTIN_COMIGESD,
25700 IX86_BUILTIN_COMINEQSD,
25701 IX86_BUILTIN_UCOMIEQSD,
25702 IX86_BUILTIN_UCOMILTSD,
25703 IX86_BUILTIN_UCOMILESD,
25704 IX86_BUILTIN_UCOMIGTSD,
25705 IX86_BUILTIN_UCOMIGESD,
25706 IX86_BUILTIN_UCOMINEQSD,
25708 IX86_BUILTIN_MAXPD,
25709 IX86_BUILTIN_MAXSD,
25710 IX86_BUILTIN_MINPD,
25711 IX86_BUILTIN_MINSD,
25713 IX86_BUILTIN_ANDPD,
25714 IX86_BUILTIN_ANDNPD,
25715 IX86_BUILTIN_ORPD,
25716 IX86_BUILTIN_XORPD,
25718 IX86_BUILTIN_SQRTPD,
25719 IX86_BUILTIN_SQRTSD,
25721 IX86_BUILTIN_UNPCKHPD,
25722 IX86_BUILTIN_UNPCKLPD,
25724 IX86_BUILTIN_SHUFPD,
25726 IX86_BUILTIN_LOADUPD,
25727 IX86_BUILTIN_STOREUPD,
25728 IX86_BUILTIN_MOVSD,
25730 IX86_BUILTIN_LOADHPD,
25731 IX86_BUILTIN_LOADLPD,
25733 IX86_BUILTIN_CVTDQ2PD,
25734 IX86_BUILTIN_CVTDQ2PS,
25736 IX86_BUILTIN_CVTPD2DQ,
25737 IX86_BUILTIN_CVTPD2PI,
25738 IX86_BUILTIN_CVTPD2PS,
25739 IX86_BUILTIN_CVTTPD2DQ,
25740 IX86_BUILTIN_CVTTPD2PI,
25742 IX86_BUILTIN_CVTPI2PD,
25743 IX86_BUILTIN_CVTSI2SD,
25744 IX86_BUILTIN_CVTSI642SD,
25746 IX86_BUILTIN_CVTSD2SI,
25747 IX86_BUILTIN_CVTSD2SI64,
25748 IX86_BUILTIN_CVTSD2SS,
25749 IX86_BUILTIN_CVTSS2SD,
25750 IX86_BUILTIN_CVTTSD2SI,
25751 IX86_BUILTIN_CVTTSD2SI64,
25753 IX86_BUILTIN_CVTPS2DQ,
25754 IX86_BUILTIN_CVTPS2PD,
25755 IX86_BUILTIN_CVTTPS2DQ,
25757 IX86_BUILTIN_MOVNTI,
25758 IX86_BUILTIN_MOVNTI64,
25759 IX86_BUILTIN_MOVNTPD,
25760 IX86_BUILTIN_MOVNTDQ,
25762 IX86_BUILTIN_MOVQ128,
25764 /* SSE2 MMX */
25765 IX86_BUILTIN_MASKMOVDQU,
25766 IX86_BUILTIN_MOVMSKPD,
25767 IX86_BUILTIN_PMOVMSKB128,
25769 IX86_BUILTIN_PACKSSWB128,
25770 IX86_BUILTIN_PACKSSDW128,
25771 IX86_BUILTIN_PACKUSWB128,
25773 IX86_BUILTIN_PADDB128,
25774 IX86_BUILTIN_PADDW128,
25775 IX86_BUILTIN_PADDD128,
25776 IX86_BUILTIN_PADDQ128,
25777 IX86_BUILTIN_PADDSB128,
25778 IX86_BUILTIN_PADDSW128,
25779 IX86_BUILTIN_PADDUSB128,
25780 IX86_BUILTIN_PADDUSW128,
25781 IX86_BUILTIN_PSUBB128,
25782 IX86_BUILTIN_PSUBW128,
25783 IX86_BUILTIN_PSUBD128,
25784 IX86_BUILTIN_PSUBQ128,
25785 IX86_BUILTIN_PSUBSB128,
25786 IX86_BUILTIN_PSUBSW128,
25787 IX86_BUILTIN_PSUBUSB128,
25788 IX86_BUILTIN_PSUBUSW128,
25790 IX86_BUILTIN_PAND128,
25791 IX86_BUILTIN_PANDN128,
25792 IX86_BUILTIN_POR128,
25793 IX86_BUILTIN_PXOR128,
25795 IX86_BUILTIN_PAVGB128,
25796 IX86_BUILTIN_PAVGW128,
25798 IX86_BUILTIN_PCMPEQB128,
25799 IX86_BUILTIN_PCMPEQW128,
25800 IX86_BUILTIN_PCMPEQD128,
25801 IX86_BUILTIN_PCMPGTB128,
25802 IX86_BUILTIN_PCMPGTW128,
25803 IX86_BUILTIN_PCMPGTD128,
25805 IX86_BUILTIN_PMADDWD128,
25807 IX86_BUILTIN_PMAXSW128,
25808 IX86_BUILTIN_PMAXUB128,
25809 IX86_BUILTIN_PMINSW128,
25810 IX86_BUILTIN_PMINUB128,
25812 IX86_BUILTIN_PMULUDQ,
25813 IX86_BUILTIN_PMULUDQ128,
25814 IX86_BUILTIN_PMULHUW128,
25815 IX86_BUILTIN_PMULHW128,
25816 IX86_BUILTIN_PMULLW128,
25818 IX86_BUILTIN_PSADBW128,
25819 IX86_BUILTIN_PSHUFHW,
25820 IX86_BUILTIN_PSHUFLW,
25821 IX86_BUILTIN_PSHUFD,
25823 IX86_BUILTIN_PSLLDQI128,
25824 IX86_BUILTIN_PSLLWI128,
25825 IX86_BUILTIN_PSLLDI128,
25826 IX86_BUILTIN_PSLLQI128,
25827 IX86_BUILTIN_PSRAWI128,
25828 IX86_BUILTIN_PSRADI128,
25829 IX86_BUILTIN_PSRLDQI128,
25830 IX86_BUILTIN_PSRLWI128,
25831 IX86_BUILTIN_PSRLDI128,
25832 IX86_BUILTIN_PSRLQI128,
25834 IX86_BUILTIN_PSLLDQ128,
25835 IX86_BUILTIN_PSLLW128,
25836 IX86_BUILTIN_PSLLD128,
25837 IX86_BUILTIN_PSLLQ128,
25838 IX86_BUILTIN_PSRAW128,
25839 IX86_BUILTIN_PSRAD128,
25840 IX86_BUILTIN_PSRLW128,
25841 IX86_BUILTIN_PSRLD128,
25842 IX86_BUILTIN_PSRLQ128,
25844 IX86_BUILTIN_PUNPCKHBW128,
25845 IX86_BUILTIN_PUNPCKHWD128,
25846 IX86_BUILTIN_PUNPCKHDQ128,
25847 IX86_BUILTIN_PUNPCKHQDQ128,
25848 IX86_BUILTIN_PUNPCKLBW128,
25849 IX86_BUILTIN_PUNPCKLWD128,
25850 IX86_BUILTIN_PUNPCKLDQ128,
25851 IX86_BUILTIN_PUNPCKLQDQ128,
25853 IX86_BUILTIN_CLFLUSH,
25854 IX86_BUILTIN_MFENCE,
25855 IX86_BUILTIN_LFENCE,
25856 IX86_BUILTIN_PAUSE,
25858 IX86_BUILTIN_BSRSI,
25859 IX86_BUILTIN_BSRDI,
25860 IX86_BUILTIN_RDPMC,
25861 IX86_BUILTIN_RDTSC,
25862 IX86_BUILTIN_RDTSCP,
25863 IX86_BUILTIN_ROLQI,
25864 IX86_BUILTIN_ROLHI,
25865 IX86_BUILTIN_RORQI,
25866 IX86_BUILTIN_RORHI,
25868 /* SSE3. */
25869 IX86_BUILTIN_ADDSUBPS,
25870 IX86_BUILTIN_HADDPS,
25871 IX86_BUILTIN_HSUBPS,
25872 IX86_BUILTIN_MOVSHDUP,
25873 IX86_BUILTIN_MOVSLDUP,
25874 IX86_BUILTIN_ADDSUBPD,
25875 IX86_BUILTIN_HADDPD,
25876 IX86_BUILTIN_HSUBPD,
25877 IX86_BUILTIN_LDDQU,
25879 IX86_BUILTIN_MONITOR,
25880 IX86_BUILTIN_MWAIT,
25882 /* SSSE3. */
25883 IX86_BUILTIN_PHADDW,
25884 IX86_BUILTIN_PHADDD,
25885 IX86_BUILTIN_PHADDSW,
25886 IX86_BUILTIN_PHSUBW,
25887 IX86_BUILTIN_PHSUBD,
25888 IX86_BUILTIN_PHSUBSW,
25889 IX86_BUILTIN_PMADDUBSW,
25890 IX86_BUILTIN_PMULHRSW,
25891 IX86_BUILTIN_PSHUFB,
25892 IX86_BUILTIN_PSIGNB,
25893 IX86_BUILTIN_PSIGNW,
25894 IX86_BUILTIN_PSIGND,
25895 IX86_BUILTIN_PALIGNR,
25896 IX86_BUILTIN_PABSB,
25897 IX86_BUILTIN_PABSW,
25898 IX86_BUILTIN_PABSD,
25900 IX86_BUILTIN_PHADDW128,
25901 IX86_BUILTIN_PHADDD128,
25902 IX86_BUILTIN_PHADDSW128,
25903 IX86_BUILTIN_PHSUBW128,
25904 IX86_BUILTIN_PHSUBD128,
25905 IX86_BUILTIN_PHSUBSW128,
25906 IX86_BUILTIN_PMADDUBSW128,
25907 IX86_BUILTIN_PMULHRSW128,
25908 IX86_BUILTIN_PSHUFB128,
25909 IX86_BUILTIN_PSIGNB128,
25910 IX86_BUILTIN_PSIGNW128,
25911 IX86_BUILTIN_PSIGND128,
25912 IX86_BUILTIN_PALIGNR128,
25913 IX86_BUILTIN_PABSB128,
25914 IX86_BUILTIN_PABSW128,
25915 IX86_BUILTIN_PABSD128,
25917 /* AMDFAM10 - SSE4A New Instructions. */
25918 IX86_BUILTIN_MOVNTSD,
25919 IX86_BUILTIN_MOVNTSS,
25920 IX86_BUILTIN_EXTRQI,
25921 IX86_BUILTIN_EXTRQ,
25922 IX86_BUILTIN_INSERTQI,
25923 IX86_BUILTIN_INSERTQ,
25925 /* SSE4.1. */
25926 IX86_BUILTIN_BLENDPD,
25927 IX86_BUILTIN_BLENDPS,
25928 IX86_BUILTIN_BLENDVPD,
25929 IX86_BUILTIN_BLENDVPS,
25930 IX86_BUILTIN_PBLENDVB128,
25931 IX86_BUILTIN_PBLENDW128,
25933 IX86_BUILTIN_DPPD,
25934 IX86_BUILTIN_DPPS,
25936 IX86_BUILTIN_INSERTPS128,
25938 IX86_BUILTIN_MOVNTDQA,
25939 IX86_BUILTIN_MPSADBW128,
25940 IX86_BUILTIN_PACKUSDW128,
25941 IX86_BUILTIN_PCMPEQQ,
25942 IX86_BUILTIN_PHMINPOSUW128,
25944 IX86_BUILTIN_PMAXSB128,
25945 IX86_BUILTIN_PMAXSD128,
25946 IX86_BUILTIN_PMAXUD128,
25947 IX86_BUILTIN_PMAXUW128,
25949 IX86_BUILTIN_PMINSB128,
25950 IX86_BUILTIN_PMINSD128,
25951 IX86_BUILTIN_PMINUD128,
25952 IX86_BUILTIN_PMINUW128,
25954 IX86_BUILTIN_PMOVSXBW128,
25955 IX86_BUILTIN_PMOVSXBD128,
25956 IX86_BUILTIN_PMOVSXBQ128,
25957 IX86_BUILTIN_PMOVSXWD128,
25958 IX86_BUILTIN_PMOVSXWQ128,
25959 IX86_BUILTIN_PMOVSXDQ128,
25961 IX86_BUILTIN_PMOVZXBW128,
25962 IX86_BUILTIN_PMOVZXBD128,
25963 IX86_BUILTIN_PMOVZXBQ128,
25964 IX86_BUILTIN_PMOVZXWD128,
25965 IX86_BUILTIN_PMOVZXWQ128,
25966 IX86_BUILTIN_PMOVZXDQ128,
25968 IX86_BUILTIN_PMULDQ128,
25969 IX86_BUILTIN_PMULLD128,
25971 IX86_BUILTIN_ROUNDSD,
25972 IX86_BUILTIN_ROUNDSS,
25974 IX86_BUILTIN_ROUNDPD,
25975 IX86_BUILTIN_ROUNDPS,
25977 IX86_BUILTIN_FLOORPD,
25978 IX86_BUILTIN_CEILPD,
25979 IX86_BUILTIN_TRUNCPD,
25980 IX86_BUILTIN_RINTPD,
25981 IX86_BUILTIN_ROUNDPD_AZ,
25983 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
25984 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
25985 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
25987 IX86_BUILTIN_FLOORPS,
25988 IX86_BUILTIN_CEILPS,
25989 IX86_BUILTIN_TRUNCPS,
25990 IX86_BUILTIN_RINTPS,
25991 IX86_BUILTIN_ROUNDPS_AZ,
25993 IX86_BUILTIN_FLOORPS_SFIX,
25994 IX86_BUILTIN_CEILPS_SFIX,
25995 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
25997 IX86_BUILTIN_PTESTZ,
25998 IX86_BUILTIN_PTESTC,
25999 IX86_BUILTIN_PTESTNZC,
26001 IX86_BUILTIN_VEC_INIT_V2SI,
26002 IX86_BUILTIN_VEC_INIT_V4HI,
26003 IX86_BUILTIN_VEC_INIT_V8QI,
26004 IX86_BUILTIN_VEC_EXT_V2DF,
26005 IX86_BUILTIN_VEC_EXT_V2DI,
26006 IX86_BUILTIN_VEC_EXT_V4SF,
26007 IX86_BUILTIN_VEC_EXT_V4SI,
26008 IX86_BUILTIN_VEC_EXT_V8HI,
26009 IX86_BUILTIN_VEC_EXT_V2SI,
26010 IX86_BUILTIN_VEC_EXT_V4HI,
26011 IX86_BUILTIN_VEC_EXT_V16QI,
26012 IX86_BUILTIN_VEC_SET_V2DI,
26013 IX86_BUILTIN_VEC_SET_V4SF,
26014 IX86_BUILTIN_VEC_SET_V4SI,
26015 IX86_BUILTIN_VEC_SET_V8HI,
26016 IX86_BUILTIN_VEC_SET_V4HI,
26017 IX86_BUILTIN_VEC_SET_V16QI,
26019 IX86_BUILTIN_VEC_PACK_SFIX,
26020 IX86_BUILTIN_VEC_PACK_SFIX256,
26022 /* SSE4.2. */
26023 IX86_BUILTIN_CRC32QI,
26024 IX86_BUILTIN_CRC32HI,
26025 IX86_BUILTIN_CRC32SI,
26026 IX86_BUILTIN_CRC32DI,
26028 IX86_BUILTIN_PCMPESTRI128,
26029 IX86_BUILTIN_PCMPESTRM128,
26030 IX86_BUILTIN_PCMPESTRA128,
26031 IX86_BUILTIN_PCMPESTRC128,
26032 IX86_BUILTIN_PCMPESTRO128,
26033 IX86_BUILTIN_PCMPESTRS128,
26034 IX86_BUILTIN_PCMPESTRZ128,
26035 IX86_BUILTIN_PCMPISTRI128,
26036 IX86_BUILTIN_PCMPISTRM128,
26037 IX86_BUILTIN_PCMPISTRA128,
26038 IX86_BUILTIN_PCMPISTRC128,
26039 IX86_BUILTIN_PCMPISTRO128,
26040 IX86_BUILTIN_PCMPISTRS128,
26041 IX86_BUILTIN_PCMPISTRZ128,
26043 IX86_BUILTIN_PCMPGTQ,
26045 /* AES instructions */
26046 IX86_BUILTIN_AESENC128,
26047 IX86_BUILTIN_AESENCLAST128,
26048 IX86_BUILTIN_AESDEC128,
26049 IX86_BUILTIN_AESDECLAST128,
26050 IX86_BUILTIN_AESIMC128,
26051 IX86_BUILTIN_AESKEYGENASSIST128,
26053 /* PCLMUL instruction */
26054 IX86_BUILTIN_PCLMULQDQ128,
26056 /* AVX */
26057 IX86_BUILTIN_ADDPD256,
26058 IX86_BUILTIN_ADDPS256,
26059 IX86_BUILTIN_ADDSUBPD256,
26060 IX86_BUILTIN_ADDSUBPS256,
26061 IX86_BUILTIN_ANDPD256,
26062 IX86_BUILTIN_ANDPS256,
26063 IX86_BUILTIN_ANDNPD256,
26064 IX86_BUILTIN_ANDNPS256,
26065 IX86_BUILTIN_BLENDPD256,
26066 IX86_BUILTIN_BLENDPS256,
26067 IX86_BUILTIN_BLENDVPD256,
26068 IX86_BUILTIN_BLENDVPS256,
26069 IX86_BUILTIN_DIVPD256,
26070 IX86_BUILTIN_DIVPS256,
26071 IX86_BUILTIN_DPPS256,
26072 IX86_BUILTIN_HADDPD256,
26073 IX86_BUILTIN_HADDPS256,
26074 IX86_BUILTIN_HSUBPD256,
26075 IX86_BUILTIN_HSUBPS256,
26076 IX86_BUILTIN_MAXPD256,
26077 IX86_BUILTIN_MAXPS256,
26078 IX86_BUILTIN_MINPD256,
26079 IX86_BUILTIN_MINPS256,
26080 IX86_BUILTIN_MULPD256,
26081 IX86_BUILTIN_MULPS256,
26082 IX86_BUILTIN_ORPD256,
26083 IX86_BUILTIN_ORPS256,
26084 IX86_BUILTIN_SHUFPD256,
26085 IX86_BUILTIN_SHUFPS256,
26086 IX86_BUILTIN_SUBPD256,
26087 IX86_BUILTIN_SUBPS256,
26088 IX86_BUILTIN_XORPD256,
26089 IX86_BUILTIN_XORPS256,
26090 IX86_BUILTIN_CMPSD,
26091 IX86_BUILTIN_CMPSS,
26092 IX86_BUILTIN_CMPPD,
26093 IX86_BUILTIN_CMPPS,
26094 IX86_BUILTIN_CMPPD256,
26095 IX86_BUILTIN_CMPPS256,
26096 IX86_BUILTIN_CVTDQ2PD256,
26097 IX86_BUILTIN_CVTDQ2PS256,
26098 IX86_BUILTIN_CVTPD2PS256,
26099 IX86_BUILTIN_CVTPS2DQ256,
26100 IX86_BUILTIN_CVTPS2PD256,
26101 IX86_BUILTIN_CVTTPD2DQ256,
26102 IX86_BUILTIN_CVTPD2DQ256,
26103 IX86_BUILTIN_CVTTPS2DQ256,
26104 IX86_BUILTIN_EXTRACTF128PD256,
26105 IX86_BUILTIN_EXTRACTF128PS256,
26106 IX86_BUILTIN_EXTRACTF128SI256,
26107 IX86_BUILTIN_VZEROALL,
26108 IX86_BUILTIN_VZEROUPPER,
26109 IX86_BUILTIN_VPERMILVARPD,
26110 IX86_BUILTIN_VPERMILVARPS,
26111 IX86_BUILTIN_VPERMILVARPD256,
26112 IX86_BUILTIN_VPERMILVARPS256,
26113 IX86_BUILTIN_VPERMILPD,
26114 IX86_BUILTIN_VPERMILPS,
26115 IX86_BUILTIN_VPERMILPD256,
26116 IX86_BUILTIN_VPERMILPS256,
26117 IX86_BUILTIN_VPERMIL2PD,
26118 IX86_BUILTIN_VPERMIL2PS,
26119 IX86_BUILTIN_VPERMIL2PD256,
26120 IX86_BUILTIN_VPERMIL2PS256,
26121 IX86_BUILTIN_VPERM2F128PD256,
26122 IX86_BUILTIN_VPERM2F128PS256,
26123 IX86_BUILTIN_VPERM2F128SI256,
26124 IX86_BUILTIN_VBROADCASTSS,
26125 IX86_BUILTIN_VBROADCASTSD256,
26126 IX86_BUILTIN_VBROADCASTSS256,
26127 IX86_BUILTIN_VBROADCASTPD256,
26128 IX86_BUILTIN_VBROADCASTPS256,
26129 IX86_BUILTIN_VINSERTF128PD256,
26130 IX86_BUILTIN_VINSERTF128PS256,
26131 IX86_BUILTIN_VINSERTF128SI256,
26132 IX86_BUILTIN_LOADUPD256,
26133 IX86_BUILTIN_LOADUPS256,
26134 IX86_BUILTIN_STOREUPD256,
26135 IX86_BUILTIN_STOREUPS256,
26136 IX86_BUILTIN_LDDQU256,
26137 IX86_BUILTIN_MOVNTDQ256,
26138 IX86_BUILTIN_MOVNTPD256,
26139 IX86_BUILTIN_MOVNTPS256,
26140 IX86_BUILTIN_LOADDQU256,
26141 IX86_BUILTIN_STOREDQU256,
26142 IX86_BUILTIN_MASKLOADPD,
26143 IX86_BUILTIN_MASKLOADPS,
26144 IX86_BUILTIN_MASKSTOREPD,
26145 IX86_BUILTIN_MASKSTOREPS,
26146 IX86_BUILTIN_MASKLOADPD256,
26147 IX86_BUILTIN_MASKLOADPS256,
26148 IX86_BUILTIN_MASKSTOREPD256,
26149 IX86_BUILTIN_MASKSTOREPS256,
26150 IX86_BUILTIN_MOVSHDUP256,
26151 IX86_BUILTIN_MOVSLDUP256,
26152 IX86_BUILTIN_MOVDDUP256,
26154 IX86_BUILTIN_SQRTPD256,
26155 IX86_BUILTIN_SQRTPS256,
26156 IX86_BUILTIN_SQRTPS_NR256,
26157 IX86_BUILTIN_RSQRTPS256,
26158 IX86_BUILTIN_RSQRTPS_NR256,
26160 IX86_BUILTIN_RCPPS256,
26162 IX86_BUILTIN_ROUNDPD256,
26163 IX86_BUILTIN_ROUNDPS256,
26165 IX86_BUILTIN_FLOORPD256,
26166 IX86_BUILTIN_CEILPD256,
26167 IX86_BUILTIN_TRUNCPD256,
26168 IX86_BUILTIN_RINTPD256,
26169 IX86_BUILTIN_ROUNDPD_AZ256,
26171 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26172 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26173 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26175 IX86_BUILTIN_FLOORPS256,
26176 IX86_BUILTIN_CEILPS256,
26177 IX86_BUILTIN_TRUNCPS256,
26178 IX86_BUILTIN_RINTPS256,
26179 IX86_BUILTIN_ROUNDPS_AZ256,
26181 IX86_BUILTIN_FLOORPS_SFIX256,
26182 IX86_BUILTIN_CEILPS_SFIX256,
26183 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26185 IX86_BUILTIN_UNPCKHPD256,
26186 IX86_BUILTIN_UNPCKLPD256,
26187 IX86_BUILTIN_UNPCKHPS256,
26188 IX86_BUILTIN_UNPCKLPS256,
26190 IX86_BUILTIN_SI256_SI,
26191 IX86_BUILTIN_PS256_PS,
26192 IX86_BUILTIN_PD256_PD,
26193 IX86_BUILTIN_SI_SI256,
26194 IX86_BUILTIN_PS_PS256,
26195 IX86_BUILTIN_PD_PD256,
26197 IX86_BUILTIN_VTESTZPD,
26198 IX86_BUILTIN_VTESTCPD,
26199 IX86_BUILTIN_VTESTNZCPD,
26200 IX86_BUILTIN_VTESTZPS,
26201 IX86_BUILTIN_VTESTCPS,
26202 IX86_BUILTIN_VTESTNZCPS,
26203 IX86_BUILTIN_VTESTZPD256,
26204 IX86_BUILTIN_VTESTCPD256,
26205 IX86_BUILTIN_VTESTNZCPD256,
26206 IX86_BUILTIN_VTESTZPS256,
26207 IX86_BUILTIN_VTESTCPS256,
26208 IX86_BUILTIN_VTESTNZCPS256,
26209 IX86_BUILTIN_PTESTZ256,
26210 IX86_BUILTIN_PTESTC256,
26211 IX86_BUILTIN_PTESTNZC256,
26213 IX86_BUILTIN_MOVMSKPD256,
26214 IX86_BUILTIN_MOVMSKPS256,
26216 /* AVX2 */
26217 IX86_BUILTIN_MPSADBW256,
26218 IX86_BUILTIN_PABSB256,
26219 IX86_BUILTIN_PABSW256,
26220 IX86_BUILTIN_PABSD256,
26221 IX86_BUILTIN_PACKSSDW256,
26222 IX86_BUILTIN_PACKSSWB256,
26223 IX86_BUILTIN_PACKUSDW256,
26224 IX86_BUILTIN_PACKUSWB256,
26225 IX86_BUILTIN_PADDB256,
26226 IX86_BUILTIN_PADDW256,
26227 IX86_BUILTIN_PADDD256,
26228 IX86_BUILTIN_PADDQ256,
26229 IX86_BUILTIN_PADDSB256,
26230 IX86_BUILTIN_PADDSW256,
26231 IX86_BUILTIN_PADDUSB256,
26232 IX86_BUILTIN_PADDUSW256,
26233 IX86_BUILTIN_PALIGNR256,
26234 IX86_BUILTIN_AND256I,
26235 IX86_BUILTIN_ANDNOT256I,
26236 IX86_BUILTIN_PAVGB256,
26237 IX86_BUILTIN_PAVGW256,
26238 IX86_BUILTIN_PBLENDVB256,
26239 IX86_BUILTIN_PBLENDVW256,
26240 IX86_BUILTIN_PCMPEQB256,
26241 IX86_BUILTIN_PCMPEQW256,
26242 IX86_BUILTIN_PCMPEQD256,
26243 IX86_BUILTIN_PCMPEQQ256,
26244 IX86_BUILTIN_PCMPGTB256,
26245 IX86_BUILTIN_PCMPGTW256,
26246 IX86_BUILTIN_PCMPGTD256,
26247 IX86_BUILTIN_PCMPGTQ256,
26248 IX86_BUILTIN_PHADDW256,
26249 IX86_BUILTIN_PHADDD256,
26250 IX86_BUILTIN_PHADDSW256,
26251 IX86_BUILTIN_PHSUBW256,
26252 IX86_BUILTIN_PHSUBD256,
26253 IX86_BUILTIN_PHSUBSW256,
26254 IX86_BUILTIN_PMADDUBSW256,
26255 IX86_BUILTIN_PMADDWD256,
26256 IX86_BUILTIN_PMAXSB256,
26257 IX86_BUILTIN_PMAXSW256,
26258 IX86_BUILTIN_PMAXSD256,
26259 IX86_BUILTIN_PMAXUB256,
26260 IX86_BUILTIN_PMAXUW256,
26261 IX86_BUILTIN_PMAXUD256,
26262 IX86_BUILTIN_PMINSB256,
26263 IX86_BUILTIN_PMINSW256,
26264 IX86_BUILTIN_PMINSD256,
26265 IX86_BUILTIN_PMINUB256,
26266 IX86_BUILTIN_PMINUW256,
26267 IX86_BUILTIN_PMINUD256,
26268 IX86_BUILTIN_PMOVMSKB256,
26269 IX86_BUILTIN_PMOVSXBW256,
26270 IX86_BUILTIN_PMOVSXBD256,
26271 IX86_BUILTIN_PMOVSXBQ256,
26272 IX86_BUILTIN_PMOVSXWD256,
26273 IX86_BUILTIN_PMOVSXWQ256,
26274 IX86_BUILTIN_PMOVSXDQ256,
26275 IX86_BUILTIN_PMOVZXBW256,
26276 IX86_BUILTIN_PMOVZXBD256,
26277 IX86_BUILTIN_PMOVZXBQ256,
26278 IX86_BUILTIN_PMOVZXWD256,
26279 IX86_BUILTIN_PMOVZXWQ256,
26280 IX86_BUILTIN_PMOVZXDQ256,
26281 IX86_BUILTIN_PMULDQ256,
26282 IX86_BUILTIN_PMULHRSW256,
26283 IX86_BUILTIN_PMULHUW256,
26284 IX86_BUILTIN_PMULHW256,
26285 IX86_BUILTIN_PMULLW256,
26286 IX86_BUILTIN_PMULLD256,
26287 IX86_BUILTIN_PMULUDQ256,
26288 IX86_BUILTIN_POR256,
26289 IX86_BUILTIN_PSADBW256,
26290 IX86_BUILTIN_PSHUFB256,
26291 IX86_BUILTIN_PSHUFD256,
26292 IX86_BUILTIN_PSHUFHW256,
26293 IX86_BUILTIN_PSHUFLW256,
26294 IX86_BUILTIN_PSIGNB256,
26295 IX86_BUILTIN_PSIGNW256,
26296 IX86_BUILTIN_PSIGND256,
26297 IX86_BUILTIN_PSLLDQI256,
26298 IX86_BUILTIN_PSLLWI256,
26299 IX86_BUILTIN_PSLLW256,
26300 IX86_BUILTIN_PSLLDI256,
26301 IX86_BUILTIN_PSLLD256,
26302 IX86_BUILTIN_PSLLQI256,
26303 IX86_BUILTIN_PSLLQ256,
26304 IX86_BUILTIN_PSRAWI256,
26305 IX86_BUILTIN_PSRAW256,
26306 IX86_BUILTIN_PSRADI256,
26307 IX86_BUILTIN_PSRAD256,
26308 IX86_BUILTIN_PSRLDQI256,
26309 IX86_BUILTIN_PSRLWI256,
26310 IX86_BUILTIN_PSRLW256,
26311 IX86_BUILTIN_PSRLDI256,
26312 IX86_BUILTIN_PSRLD256,
26313 IX86_BUILTIN_PSRLQI256,
26314 IX86_BUILTIN_PSRLQ256,
26315 IX86_BUILTIN_PSUBB256,
26316 IX86_BUILTIN_PSUBW256,
26317 IX86_BUILTIN_PSUBD256,
26318 IX86_BUILTIN_PSUBQ256,
26319 IX86_BUILTIN_PSUBSB256,
26320 IX86_BUILTIN_PSUBSW256,
26321 IX86_BUILTIN_PSUBUSB256,
26322 IX86_BUILTIN_PSUBUSW256,
26323 IX86_BUILTIN_PUNPCKHBW256,
26324 IX86_BUILTIN_PUNPCKHWD256,
26325 IX86_BUILTIN_PUNPCKHDQ256,
26326 IX86_BUILTIN_PUNPCKHQDQ256,
26327 IX86_BUILTIN_PUNPCKLBW256,
26328 IX86_BUILTIN_PUNPCKLWD256,
26329 IX86_BUILTIN_PUNPCKLDQ256,
26330 IX86_BUILTIN_PUNPCKLQDQ256,
26331 IX86_BUILTIN_PXOR256,
26332 IX86_BUILTIN_MOVNTDQA256,
26333 IX86_BUILTIN_VBROADCASTSS_PS,
26334 IX86_BUILTIN_VBROADCASTSS_PS256,
26335 IX86_BUILTIN_VBROADCASTSD_PD256,
26336 IX86_BUILTIN_VBROADCASTSI256,
26337 IX86_BUILTIN_PBLENDD256,
26338 IX86_BUILTIN_PBLENDD128,
26339 IX86_BUILTIN_PBROADCASTB256,
26340 IX86_BUILTIN_PBROADCASTW256,
26341 IX86_BUILTIN_PBROADCASTD256,
26342 IX86_BUILTIN_PBROADCASTQ256,
26343 IX86_BUILTIN_PBROADCASTB128,
26344 IX86_BUILTIN_PBROADCASTW128,
26345 IX86_BUILTIN_PBROADCASTD128,
26346 IX86_BUILTIN_PBROADCASTQ128,
26347 IX86_BUILTIN_VPERMVARSI256,
26348 IX86_BUILTIN_VPERMDF256,
26349 IX86_BUILTIN_VPERMVARSF256,
26350 IX86_BUILTIN_VPERMDI256,
26351 IX86_BUILTIN_VPERMTI256,
26352 IX86_BUILTIN_VEXTRACT128I256,
26353 IX86_BUILTIN_VINSERT128I256,
26354 IX86_BUILTIN_MASKLOADD,
26355 IX86_BUILTIN_MASKLOADQ,
26356 IX86_BUILTIN_MASKLOADD256,
26357 IX86_BUILTIN_MASKLOADQ256,
26358 IX86_BUILTIN_MASKSTORED,
26359 IX86_BUILTIN_MASKSTOREQ,
26360 IX86_BUILTIN_MASKSTORED256,
26361 IX86_BUILTIN_MASKSTOREQ256,
26362 IX86_BUILTIN_PSLLVV4DI,
26363 IX86_BUILTIN_PSLLVV2DI,
26364 IX86_BUILTIN_PSLLVV8SI,
26365 IX86_BUILTIN_PSLLVV4SI,
26366 IX86_BUILTIN_PSRAVV8SI,
26367 IX86_BUILTIN_PSRAVV4SI,
26368 IX86_BUILTIN_PSRLVV4DI,
26369 IX86_BUILTIN_PSRLVV2DI,
26370 IX86_BUILTIN_PSRLVV8SI,
26371 IX86_BUILTIN_PSRLVV4SI,
26373 IX86_BUILTIN_GATHERSIV2DF,
26374 IX86_BUILTIN_GATHERSIV4DF,
26375 IX86_BUILTIN_GATHERDIV2DF,
26376 IX86_BUILTIN_GATHERDIV4DF,
26377 IX86_BUILTIN_GATHERSIV4SF,
26378 IX86_BUILTIN_GATHERSIV8SF,
26379 IX86_BUILTIN_GATHERDIV4SF,
26380 IX86_BUILTIN_GATHERDIV8SF,
26381 IX86_BUILTIN_GATHERSIV2DI,
26382 IX86_BUILTIN_GATHERSIV4DI,
26383 IX86_BUILTIN_GATHERDIV2DI,
26384 IX86_BUILTIN_GATHERDIV4DI,
26385 IX86_BUILTIN_GATHERSIV4SI,
26386 IX86_BUILTIN_GATHERSIV8SI,
26387 IX86_BUILTIN_GATHERDIV4SI,
26388 IX86_BUILTIN_GATHERDIV8SI,
26390 /* Alternate 4 element gather for the vectorizer where
26391 all operands are 32-byte wide. */
26392 IX86_BUILTIN_GATHERALTSIV4DF,
26393 IX86_BUILTIN_GATHERALTDIV8SF,
26394 IX86_BUILTIN_GATHERALTSIV4DI,
26395 IX86_BUILTIN_GATHERALTDIV8SI,
26397 /* TFmode support builtins. */
26398 IX86_BUILTIN_INFQ,
26399 IX86_BUILTIN_HUGE_VALQ,
26400 IX86_BUILTIN_FABSQ,
26401 IX86_BUILTIN_COPYSIGNQ,
26403 /* Vectorizer support builtins. */
26404 IX86_BUILTIN_CPYSGNPS,
26405 IX86_BUILTIN_CPYSGNPD,
26406 IX86_BUILTIN_CPYSGNPS256,
26407 IX86_BUILTIN_CPYSGNPD256,
26409 /* FMA4 instructions. */
26410 IX86_BUILTIN_VFMADDSS,
26411 IX86_BUILTIN_VFMADDSD,
26412 IX86_BUILTIN_VFMADDPS,
26413 IX86_BUILTIN_VFMADDPD,
26414 IX86_BUILTIN_VFMADDPS256,
26415 IX86_BUILTIN_VFMADDPD256,
26416 IX86_BUILTIN_VFMADDSUBPS,
26417 IX86_BUILTIN_VFMADDSUBPD,
26418 IX86_BUILTIN_VFMADDSUBPS256,
26419 IX86_BUILTIN_VFMADDSUBPD256,
26421 /* FMA3 instructions. */
26422 IX86_BUILTIN_VFMADDSS3,
26423 IX86_BUILTIN_VFMADDSD3,
26425 /* XOP instructions. */
26426 IX86_BUILTIN_VPCMOV,
26427 IX86_BUILTIN_VPCMOV_V2DI,
26428 IX86_BUILTIN_VPCMOV_V4SI,
26429 IX86_BUILTIN_VPCMOV_V8HI,
26430 IX86_BUILTIN_VPCMOV_V16QI,
26431 IX86_BUILTIN_VPCMOV_V4SF,
26432 IX86_BUILTIN_VPCMOV_V2DF,
26433 IX86_BUILTIN_VPCMOV256,
26434 IX86_BUILTIN_VPCMOV_V4DI256,
26435 IX86_BUILTIN_VPCMOV_V8SI256,
26436 IX86_BUILTIN_VPCMOV_V16HI256,
26437 IX86_BUILTIN_VPCMOV_V32QI256,
26438 IX86_BUILTIN_VPCMOV_V8SF256,
26439 IX86_BUILTIN_VPCMOV_V4DF256,
26441 IX86_BUILTIN_VPPERM,
26443 IX86_BUILTIN_VPMACSSWW,
26444 IX86_BUILTIN_VPMACSWW,
26445 IX86_BUILTIN_VPMACSSWD,
26446 IX86_BUILTIN_VPMACSWD,
26447 IX86_BUILTIN_VPMACSSDD,
26448 IX86_BUILTIN_VPMACSDD,
26449 IX86_BUILTIN_VPMACSSDQL,
26450 IX86_BUILTIN_VPMACSSDQH,
26451 IX86_BUILTIN_VPMACSDQL,
26452 IX86_BUILTIN_VPMACSDQH,
26453 IX86_BUILTIN_VPMADCSSWD,
26454 IX86_BUILTIN_VPMADCSWD,
26456 IX86_BUILTIN_VPHADDBW,
26457 IX86_BUILTIN_VPHADDBD,
26458 IX86_BUILTIN_VPHADDBQ,
26459 IX86_BUILTIN_VPHADDWD,
26460 IX86_BUILTIN_VPHADDWQ,
26461 IX86_BUILTIN_VPHADDDQ,
26462 IX86_BUILTIN_VPHADDUBW,
26463 IX86_BUILTIN_VPHADDUBD,
26464 IX86_BUILTIN_VPHADDUBQ,
26465 IX86_BUILTIN_VPHADDUWD,
26466 IX86_BUILTIN_VPHADDUWQ,
26467 IX86_BUILTIN_VPHADDUDQ,
26468 IX86_BUILTIN_VPHSUBBW,
26469 IX86_BUILTIN_VPHSUBWD,
26470 IX86_BUILTIN_VPHSUBDQ,
26472 IX86_BUILTIN_VPROTB,
26473 IX86_BUILTIN_VPROTW,
26474 IX86_BUILTIN_VPROTD,
26475 IX86_BUILTIN_VPROTQ,
26476 IX86_BUILTIN_VPROTB_IMM,
26477 IX86_BUILTIN_VPROTW_IMM,
26478 IX86_BUILTIN_VPROTD_IMM,
26479 IX86_BUILTIN_VPROTQ_IMM,
26481 IX86_BUILTIN_VPSHLB,
26482 IX86_BUILTIN_VPSHLW,
26483 IX86_BUILTIN_VPSHLD,
26484 IX86_BUILTIN_VPSHLQ,
26485 IX86_BUILTIN_VPSHAB,
26486 IX86_BUILTIN_VPSHAW,
26487 IX86_BUILTIN_VPSHAD,
26488 IX86_BUILTIN_VPSHAQ,
26490 IX86_BUILTIN_VFRCZSS,
26491 IX86_BUILTIN_VFRCZSD,
26492 IX86_BUILTIN_VFRCZPS,
26493 IX86_BUILTIN_VFRCZPD,
26494 IX86_BUILTIN_VFRCZPS256,
26495 IX86_BUILTIN_VFRCZPD256,
26497 IX86_BUILTIN_VPCOMEQUB,
26498 IX86_BUILTIN_VPCOMNEUB,
26499 IX86_BUILTIN_VPCOMLTUB,
26500 IX86_BUILTIN_VPCOMLEUB,
26501 IX86_BUILTIN_VPCOMGTUB,
26502 IX86_BUILTIN_VPCOMGEUB,
26503 IX86_BUILTIN_VPCOMFALSEUB,
26504 IX86_BUILTIN_VPCOMTRUEUB,
26506 IX86_BUILTIN_VPCOMEQUW,
26507 IX86_BUILTIN_VPCOMNEUW,
26508 IX86_BUILTIN_VPCOMLTUW,
26509 IX86_BUILTIN_VPCOMLEUW,
26510 IX86_BUILTIN_VPCOMGTUW,
26511 IX86_BUILTIN_VPCOMGEUW,
26512 IX86_BUILTIN_VPCOMFALSEUW,
26513 IX86_BUILTIN_VPCOMTRUEUW,
26515 IX86_BUILTIN_VPCOMEQUD,
26516 IX86_BUILTIN_VPCOMNEUD,
26517 IX86_BUILTIN_VPCOMLTUD,
26518 IX86_BUILTIN_VPCOMLEUD,
26519 IX86_BUILTIN_VPCOMGTUD,
26520 IX86_BUILTIN_VPCOMGEUD,
26521 IX86_BUILTIN_VPCOMFALSEUD,
26522 IX86_BUILTIN_VPCOMTRUEUD,
26524 IX86_BUILTIN_VPCOMEQUQ,
26525 IX86_BUILTIN_VPCOMNEUQ,
26526 IX86_BUILTIN_VPCOMLTUQ,
26527 IX86_BUILTIN_VPCOMLEUQ,
26528 IX86_BUILTIN_VPCOMGTUQ,
26529 IX86_BUILTIN_VPCOMGEUQ,
26530 IX86_BUILTIN_VPCOMFALSEUQ,
26531 IX86_BUILTIN_VPCOMTRUEUQ,
26533 IX86_BUILTIN_VPCOMEQB,
26534 IX86_BUILTIN_VPCOMNEB,
26535 IX86_BUILTIN_VPCOMLTB,
26536 IX86_BUILTIN_VPCOMLEB,
26537 IX86_BUILTIN_VPCOMGTB,
26538 IX86_BUILTIN_VPCOMGEB,
26539 IX86_BUILTIN_VPCOMFALSEB,
26540 IX86_BUILTIN_VPCOMTRUEB,
26542 IX86_BUILTIN_VPCOMEQW,
26543 IX86_BUILTIN_VPCOMNEW,
26544 IX86_BUILTIN_VPCOMLTW,
26545 IX86_BUILTIN_VPCOMLEW,
26546 IX86_BUILTIN_VPCOMGTW,
26547 IX86_BUILTIN_VPCOMGEW,
26548 IX86_BUILTIN_VPCOMFALSEW,
26549 IX86_BUILTIN_VPCOMTRUEW,
26551 IX86_BUILTIN_VPCOMEQD,
26552 IX86_BUILTIN_VPCOMNED,
26553 IX86_BUILTIN_VPCOMLTD,
26554 IX86_BUILTIN_VPCOMLED,
26555 IX86_BUILTIN_VPCOMGTD,
26556 IX86_BUILTIN_VPCOMGED,
26557 IX86_BUILTIN_VPCOMFALSED,
26558 IX86_BUILTIN_VPCOMTRUED,
26560 IX86_BUILTIN_VPCOMEQQ,
26561 IX86_BUILTIN_VPCOMNEQ,
26562 IX86_BUILTIN_VPCOMLTQ,
26563 IX86_BUILTIN_VPCOMLEQ,
26564 IX86_BUILTIN_VPCOMGTQ,
26565 IX86_BUILTIN_VPCOMGEQ,
26566 IX86_BUILTIN_VPCOMFALSEQ,
26567 IX86_BUILTIN_VPCOMTRUEQ,
26569 /* LWP instructions. */
26570 IX86_BUILTIN_LLWPCB,
26571 IX86_BUILTIN_SLWPCB,
26572 IX86_BUILTIN_LWPVAL32,
26573 IX86_BUILTIN_LWPVAL64,
26574 IX86_BUILTIN_LWPINS32,
26575 IX86_BUILTIN_LWPINS64,
26577 IX86_BUILTIN_CLZS,
26579 /* RTM */
26580 IX86_BUILTIN_XBEGIN,
26581 IX86_BUILTIN_XEND,
26582 IX86_BUILTIN_XABORT,
26583 IX86_BUILTIN_XTEST,
26585 /* BMI instructions. */
26586 IX86_BUILTIN_BEXTR32,
26587 IX86_BUILTIN_BEXTR64,
26588 IX86_BUILTIN_CTZS,
26590 /* TBM instructions. */
26591 IX86_BUILTIN_BEXTRI32,
26592 IX86_BUILTIN_BEXTRI64,
26594 /* BMI2 instructions. */
26595 IX86_BUILTIN_BZHI32,
26596 IX86_BUILTIN_BZHI64,
26597 IX86_BUILTIN_PDEP32,
26598 IX86_BUILTIN_PDEP64,
26599 IX86_BUILTIN_PEXT32,
26600 IX86_BUILTIN_PEXT64,
26602 /* ADX instructions. */
26603 IX86_BUILTIN_ADDCARRYX32,
26604 IX86_BUILTIN_ADDCARRYX64,
26606 /* FSGSBASE instructions. */
26607 IX86_BUILTIN_RDFSBASE32,
26608 IX86_BUILTIN_RDFSBASE64,
26609 IX86_BUILTIN_RDGSBASE32,
26610 IX86_BUILTIN_RDGSBASE64,
26611 IX86_BUILTIN_WRFSBASE32,
26612 IX86_BUILTIN_WRFSBASE64,
26613 IX86_BUILTIN_WRGSBASE32,
26614 IX86_BUILTIN_WRGSBASE64,
26616 /* RDRND instructions. */
26617 IX86_BUILTIN_RDRAND16_STEP,
26618 IX86_BUILTIN_RDRAND32_STEP,
26619 IX86_BUILTIN_RDRAND64_STEP,
26621 /* RDSEED instructions. */
26622 IX86_BUILTIN_RDSEED16_STEP,
26623 IX86_BUILTIN_RDSEED32_STEP,
26624 IX86_BUILTIN_RDSEED64_STEP,
26626 /* F16C instructions. */
26627 IX86_BUILTIN_CVTPH2PS,
26628 IX86_BUILTIN_CVTPH2PS256,
26629 IX86_BUILTIN_CVTPS2PH,
26630 IX86_BUILTIN_CVTPS2PH256,
26632 /* CFString built-in for darwin */
26633 IX86_BUILTIN_CFSTRING,
26635 /* Builtins to get CPU type and supported features. */
26636 IX86_BUILTIN_CPU_INIT,
26637 IX86_BUILTIN_CPU_IS,
26638 IX86_BUILTIN_CPU_SUPPORTS,
26640 IX86_BUILTIN_MAX
26641 };
26643 /* Table for the ix86 builtin decls. */
26646 /* Table of all of the builtin functions that are possible with different ISA's
26647 but are waiting to be built until a function is declared to use that
26648 ISA. */
26655 };
26660 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26661 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26662 function decl in the ix86_builtins array. Returns the function decl or
26663 NULL_TREE, if the builtin was not added.
26665 If the front end has a special hook for builtin functions, delay adding
26666 builtin functions that aren't in the current ISA until the ISA is changed
26667 with function specific optimization. Doing so, can save about 300K for the
26668 default compiler. When the builtin is expanded, check at that time whether
26669 it is valid.
26671 If the front end doesn't have a special hook, record all builtins, even if
26672 it isn't an instruction set in the current ISA in case the user uses
26673 function specific options for a different ISA, so that we don't get scope
26674 errors if a builtin is added in the middle of a function scope. */
26680 {
26684 {
26693 {
26699 }
26700 else
26701 {
26707 }
26708 }
26711 }
26713 /* Like def_builtin, but also marks the function decl "const". */
26718 {
26722 else
26726 }
26728 /* Add any new builtin functions for a given ISA that may not have been
26729 declared. This saves a bit of space compared to adding all of the
26730 declarations to the tree, even if we didn't use them. */
26732 static void
26734 {
26738 {
26741 {
26744 /* Don't define the builtin again. */
26750 NULL_TREE);
26755 }
26756 }
26757 }
26759 /* Bits for builtin_description.flag. */
26761 /* Set when we don't support the comparison natively, and should
26762 swap_comparison in order to support it. */
26763 #define BUILTIN_DESC_SWAP_OPERANDS 1
26765 struct builtin_description
26766 {
26773 };
26776 {
26777 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26778 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26779 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26780 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26782 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26783 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26784 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26785 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26786 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26787 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26788 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26789 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26790 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26791 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26792 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26793 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26794 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26795 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26796 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26797 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26798 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26799 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26800 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26801 };
26804 {
26805 /* SSE4.2 */
26806 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26807 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26808 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26809 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26810 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26811 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26812 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26813 };
26816 {
26817 /* SSE4.2 */
26818 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26819 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26820 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26821 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26822 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26823 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26824 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26825 };
26827 /* Special builtins with variable number of arguments. */
26829 {
26830 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26831 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26832 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26834 /* MMX */
26835 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26837 /* 3DNow! */
26838 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26840 /* FXSR, XSAVE and XSAVEOPT */
26841 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26842 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26843 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26844 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26845 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26847 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26848 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26849 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26850 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26851 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26853 /* SSE */
26854 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26855 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26856 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26858 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26859 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26860 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26861 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26863 /* SSE or 3DNow!A */
26864 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26865 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26867 /* SSE2 */
26868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26875 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26876 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26879 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26880 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26882 /* SSE3 */
26883 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26885 /* SSE4.1 */
26886 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26888 /* SSE4A */
26889 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26890 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26892 /* AVX */
26893 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26894 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26896 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26897 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26898 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26899 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26907 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26919 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26920 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26923 /* AVX2 */
26924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26926 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26931 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26934 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26935 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26936 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26937 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26938 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26939 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26941 /* FSGSBASE */
26942 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26943 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26944 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26945 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26946 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26947 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26948 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26949 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26951 /* RTM */
26952 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26953 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26954 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26955 };
26957 /* Builtins with variable number of arguments. */
26959 {
26960 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26961 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26962 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26963 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26964 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26965 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26966 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26968 /* MMX */
26969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26971 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26974 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26976 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26978 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26979 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26980 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26982 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26983 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26985 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26988 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27028 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27032 /* 3DNow! */
27033 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27034 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27035 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27036 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27038 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27039 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27040 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27041 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27042 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27043 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27044 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27045 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27046 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27047 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27048 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27049 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27050 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27051 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27052 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27054 /* 3DNow!A */
27055 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27056 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27057 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27058 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27059 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27060 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27062 /* SSE */
27063 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27064 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27065 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27066 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27067 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27068 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27069 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27070 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27071 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27072 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27074 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27076 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27078 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27079 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27080 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27092 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27095 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27096 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27098 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27103 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27107 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27110 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27111 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27117 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27125 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27130 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27132 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27135 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27136 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27138 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27139 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27141 /* SSE MMX or 3Dnow!A */
27142 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27143 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27144 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27146 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27147 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27148 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27149 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27151 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27152 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27154 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27156 /* SSE2 */
27157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27163 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27168 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27169 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27171 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27173 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27175 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27176 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27180 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27182 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27183 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27184 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27185 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27208 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27213 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27217 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27219 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27225 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27226 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27228 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27232 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27233 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27234 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27236 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27237 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27246 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27248 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27252 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27253 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27254 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27256 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27266 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27267 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27268 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27271 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27272 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27273 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27274 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27275 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27276 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27277 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27278 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27284 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27288 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27293 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27300 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27301 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27302 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27306 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27307 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27309 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27310 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27314 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27326 /* SSE2 MMX */
27327 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27330 /* SSE3 */
27331 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27332 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27334 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27335 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27336 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27337 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27338 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27339 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27341 /* SSSE3 */
27342 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27343 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27344 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27345 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27346 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27347 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27349 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27350 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27351 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27352 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27353 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27354 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27355 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27356 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27357 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27358 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27359 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27360 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27361 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27362 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27363 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27364 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27365 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27366 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27367 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27368 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27369 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27371 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27372 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27374 /* SSSE3. */
27375 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27378 /* SSE4.1 */
27379 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27380 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27381 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27382 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27383 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27384 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27385 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27386 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27387 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27388 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27390 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27391 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27392 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27393 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27394 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27395 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27396 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27397 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27398 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27399 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27400 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27401 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27402 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27404 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27405 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27406 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27407 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27414 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27417 /* SSE4.1 */
27418 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27419 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27420 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27421 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27423 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27424 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27425 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27426 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27428 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27429 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27431 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27432 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27434 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27435 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27436 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27437 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27439 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27440 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27442 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27443 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27445 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27446 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27447 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27449 /* SSE4.2 */
27450 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27451 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27452 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27453 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27454 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27456 /* SSE4A */
27457 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27458 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27459 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27460 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27462 /* AES */
27463 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27464 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27466 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27467 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27468 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27469 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27471 /* PCLMUL */
27472 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27474 /* AVX */
27475 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27476 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27477 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27478 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27479 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27480 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27481 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27482 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27483 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27484 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27485 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27486 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27487 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27488 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27489 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27490 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27491 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27492 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27493 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27494 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27495 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27496 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27497 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27498 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27499 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27500 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27523 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27524 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27562 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27576 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27577 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27587 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27588 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27589 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27610 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27611 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27613 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27615 /* AVX2 */
27616 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27617 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27618 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27619 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27620 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27621 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27622 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27623 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27624 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27625 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27626 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27627 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27628 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27629 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27630 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27631 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27632 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27633 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27634 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27635 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27636 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27637 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27640 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27642 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27643 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27644 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27649 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27650 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27651 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27763 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27765 /* BMI */
27766 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27767 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27768 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27770 /* TBM */
27771 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27772 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27774 /* F16C */
27775 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27776 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27777 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27778 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27780 /* BMI2 */
27781 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27782 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27783 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27784 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27785 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27786 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27787 };
27789 /* FMA4 and XOP. */
27790 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27791 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27792 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27793 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27794 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27795 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27796 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27797 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27798 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27799 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27800 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27801 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27802 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27803 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27804 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27805 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27806 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27807 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27808 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27809 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27810 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27811 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27812 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27813 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27814 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27815 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27816 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27817 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27818 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27819 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27820 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27821 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27822 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27823 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27824 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27825 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27826 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27827 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27828 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27829 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27830 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27831 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27832 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27833 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27834 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27835 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27836 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27837 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27838 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27839 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27840 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27841 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27844 {
27885 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27886 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27887 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27888 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27889 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27890 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27891 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27893 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27894 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27895 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27896 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27897 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27898 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27899 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27901 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27903 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27904 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27905 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27908 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27909 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27910 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27911 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27913 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27918 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27919 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
27980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
27984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
27985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
27986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
27988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
27989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
27992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
27993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
27994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
27996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
27997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28043 };
28044 \f
28045 /* TM vector builtins. */
28047 /* Reuse the existing x86-specific `struct builtin_description' cause
28048 we're lazy. Add casts to make them fit. */
28050 {
28051 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28052 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28053 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28054 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28055 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28056 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28057 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28059 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28060 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28061 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28062 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28063 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28064 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28065 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28067 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28068 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28069 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28070 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28071 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28072 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28073 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28075 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28076 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28077 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28078 };
28080 /* TM callbacks. */
28082 /* Return the builtin decl needed to load a vector of TYPE. */
28084 static tree
28086 {
28088 {
28090 {
28097 }
28098 }
28100 }
28102 /* Return the builtin decl needed to store a vector of TYPE. */
28104 static tree
28106 {
28108 {
28110 {
28117 }
28118 }
28120 }
28121 \f
28122 /* Initialize the transactional memory vector load/store builtins. */
28124 static void
28126 {
28130 tree decl;
28137 /* If there are no builtins defined, we must be compiling in a
28138 language without trans-mem support. */
28142 /* Use whatever attributes a normal TM load has. */
28146 /* Use whatever attributes a normal TM store has. */
28150 /* Use whatever attributes a normal TM log has. */
28158 {
28162 {
28170 {
28173 }
28175 {
28178 }
28179 else
28180 {
28183 }
28185 /* The builtin without the prefix for
28186 calling it directly. */
28188 attrs);
28189 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28190 set the TYPE_ATTRIBUTES. */
28194 }
28195 }
28196 }
28198 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28199 in the current target ISA to allow the user to compile particular modules
28200 with different target specific options that differ from the command line
28201 options. */
28202 static void
28204 {
28209 /* Add all special builtins with variable number of operands. */
28213 {
28219 }
28221 /* Add all builtins with variable number of operands. */
28225 {
28231 }
28233 /* pcmpestr[im] insns. */
28237 {
28240 else
28243 }
28245 /* pcmpistr[im] insns. */
28249 {
28252 else
28255 }
28257 /* comi/ucomi insns. */
28259 {
28262 else
28265 }
28267 /* SSE */
28273 /* SSE or 3DNow!A */
28276 IX86_BUILTIN_MASKMOVQ);
28278 /* SSE2 */
28287 /* SSE3. */
28293 /* AES */
28307 /* PCLMUL */
28311 /* RDRND */
28318 IX86_BUILTIN_RDRAND64_STEP);
28320 /* AVX2 */
28322 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28323 IX86_BUILTIN_GATHERSIV2DF);
28326 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28327 IX86_BUILTIN_GATHERSIV4DF);
28330 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28331 IX86_BUILTIN_GATHERDIV2DF);
28334 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28335 IX86_BUILTIN_GATHERDIV4DF);
28338 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28339 IX86_BUILTIN_GATHERSIV4SF);
28342 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28343 IX86_BUILTIN_GATHERSIV8SF);
28346 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28347 IX86_BUILTIN_GATHERDIV4SF);
28350 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28351 IX86_BUILTIN_GATHERDIV8SF);
28354 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28355 IX86_BUILTIN_GATHERSIV2DI);
28358 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28359 IX86_BUILTIN_GATHERSIV4DI);
28362 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28363 IX86_BUILTIN_GATHERDIV2DI);
28366 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28367 IX86_BUILTIN_GATHERDIV4DI);
28370 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28371 IX86_BUILTIN_GATHERSIV4SI);
28374 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28375 IX86_BUILTIN_GATHERSIV8SI);
28378 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28379 IX86_BUILTIN_GATHERDIV4SI);
28382 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28383 IX86_BUILTIN_GATHERDIV8SI);
28386 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28387 IX86_BUILTIN_GATHERALTSIV4DF);
28390 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28391 IX86_BUILTIN_GATHERALTDIV8SF);
28394 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28395 IX86_BUILTIN_GATHERALTSIV4DI);
28398 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28399 IX86_BUILTIN_GATHERALTDIV8SI);
28401 /* RTM. */
28405 /* MMX access to the vec_init patterns. */
28410 V4HI_FTYPE_HI_HI_HI_HI,
28411 IX86_BUILTIN_VEC_INIT_V4HI);
28414 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28415 IX86_BUILTIN_VEC_INIT_V8QI);
28417 /* Access to the vec_extract patterns. */
28439 /* Access to the vec_set patterns. */
28460 /* RDSEED */
28469 /* ADCX */
28474 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28475 IX86_BUILTIN_ADDCARRYX64);
28477 /* Add FMA4 multi-arg argument instructions */
28479 {
28485 }
28486 }
28488 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28489 to return a pointer to VERSION_DECL if the outcome of the expression
28490 formed by PREDICATE_CHAIN is true. This function will be called during
28491 version dispatch to decide which function version to execute. It returns
28492 the basic block at the end, to which more conditions can be added. */
28494 static basic_block
28497 {
28498 gimple return_stmt;
28500 gimple convert_stmt;
28501 gimple call_cond_stmt;
28502 gimple if_else_stmt;
28508 gimple_seq gseq;
28525 {
28533 }
28536 {
28551 else
28552 {
28553 gimple assign_stmt;
28554 /* Use MIN_EXPR to check if any integer is zero?.
28555 and_expr_var = min_expr <cond_var, and_expr_var> */
28563 }
28564 }
28567 integer_zero_node,
28597 }
28599 /* This parses the attribute arguments to target in DECL and determines
28600 the right builtin to use to match the platform specification.
28601 It returns the priority value for this version decl. If PREDICATE_LIST
28602 is not NULL, it stores the list of cpu features that need to be checked
28603 before dispatching this function. */
28605 static unsigned int
28607 {
28608 tree attrs;
28610 tree target_node;
28617 /* Priority of i386 features, greater value is higher priority. This is
28618 used to decide the order in which function dispatch must happen. For
28619 instance, a version specialized for SSE4.2 should be checked for dispatch
28620 before a version for SSE3, as SSE4.2 implies SSE3. */
28621 enum feature_priority
28622 {
28624 P_MMX,
28625 P_SSE,
28626 P_SSE2,
28627 P_SSE3,
28628 P_SSSE3,
28629 P_PROC_SSSE3,
28630 P_SSE4_a,
28631 P_PROC_SSE4_a,
28632 P_SSE4_1,
28633 P_SSE4_2,
28634 P_PROC_SSE4_2,
28635 P_POPCNT,
28636 P_AVX,
28637 P_AVX2,
28638 P_FMA,
28639 P_PROC_FMA
28640 };
28644 /* These are the target attribute strings for which a dispatcher is
28645 available, from fold_builtin_cpu. */
28647 static struct _feature_list
28648 {
28651 }
28653 {
28664 };
28667 static unsigned int NUM_FEATURES
28684 /* Handle arch= if specified. For priority, set it to be 1 more than
28685 the best instruction set the processor can handle. For instance, if
28686 there is a version for atom and a version for ssse3 (the highest ISA
28687 priority for atom), the atom version must be checked for dispatch
28688 before the ssse3 version. */
28690 {
28699 {
28701 {
28726 }
28727 }
28732 {
28736 }
28739 {
28741 /* For a C string literal the length includes the trailing NULL. */
28744 predicate_chain);
28745 }
28746 }
28748 /* Process feature name. */
28755 {
28756 /* Do not process "arch=" */
28758 {
28761 }
28763 {
28765 {
28767 {
28772 predicate_chain);
28773 }
28774 /* Find the maximum priority feature. */
28779 }
28780 }
28782 {
28786 }
28788 }
28792 {
28795 attrs_str);
28797 }
28799 {
28802 }
28805 }
28807 /* This compares the priority of target features in function DECL1
28808 and DECL2. It returns positive value if DECL1 is higher priority,
28809 negative value if DECL2 is higher priority and 0 if they are the
28810 same. */
28812 static int
28814 {
28825 }
28827 /* V1 and V2 point to function versions with different priorities
28828 based on the target ISA. This function compares their priorities. */
28830 static int
28832 {
28834 {
28835 tree version_decl;
28836 tree predicate_chain;
28843 }
28845 /* This function generates the dispatch function for
28846 multi-versioned functions. DISPATCH_DECL is the function which will
28847 contain the dispatch logic. FNDECLS are the function choices for
28848 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28849 in DISPATCH_DECL in which the dispatch code is generated. */
28851 static int
28855 {
28856 tree default_decl;
28857 gimple ifunc_cpu_init_stmt;
28858 gimple_seq gseq;
28860 tree ele;
28866 struct _function_version_info
28867 {
28868 tree version_decl;
28869 tree predicate_chain;
28877 /*fndecls_p is actually a vector. */
28880 /* At least one more version other than the default. */
28887 /* The first version in the vector is the default decl. */
28893 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28894 constructors, so explicity call __builtin_cpu_init here. */
28905 {
28909 /* Get attribute string, parse it and find the right predicate decl.
28910 The predicate function could be a lengthy combination of many
28911 features, like arch-type and various isa-variants. */
28918 actual_versions++;
28922 }
28924 /* Sort the versions according to descending order of dispatch priority. The
28925 priority is based on the ISA. This is not a perfect solution. There
28926 could still be ambiguity. If more than one function version is suitable
28927 to execute, which one should be dispatched? In future, allow the user
28928 to specify a dispatch priority next to the version. */
28938 /* dispatch default version at the end. */
28944 }
28946 /* Comparator function to be used in qsort routine to sort attribute
28947 specification strings to "target". */
28949 static int
28951 {
28955 }
28957 /* STR is the argument to target attribute. This function tokenizes
28958 the comma separated arguments, sorts them and returns a string which
28959 is a unique identifier for the comma separated arguments. It also
28960 replaces non-identifier characters "=,-" with "_". */
28964 {
28973 argnum++;
28978 /* Replace "=,-" with "_". */
28991 {
28993 i++;
28995 }
29002 {
29005 }
29010 }
29012 /* This function changes the assembler name for functions that are
29013 versions. If DECL is a function version and has a "target"
29014 attribute, it appends the attribute string to its assembler name. */
29016 static tree
29018 {
29019 tree version_attr;
29027 "Function versions cannot be marked as gnu_inline,"
29037 /* target attribute string is NULL for default functions. */
29042 version_string
29051 /* Allow assembler name to be modified if already set. */
29056 }
29058 /* This function returns true if FN1 and FN2 are versions of the same function,
29059 that is, the target strings of the function decls are different. This assumes
29060 that FN1 and FN2 have the same signature. */
29062 static bool
29064 {
29077 /* At least one function decl should have the target attribute specified. */
29081 /* If one function does not have a target attribute, these are versions. */
29091 /* The sorted target strings must be different for fn1 and fn2
29092 to be versions. */
29095 else
29102 }
29104 /* This target supports function multiversioning. */
29106 static bool
29108 {
29110 }
29112 static tree
29114 {
29115 /* For function version, add the target suffix to the assembler name. */
29119 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29121 #endif
29124 }
29126 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29127 is true, append the full path name of the source file. */
29131 {
29139 /* Get a unique name that can be used globally without any chances
29140 of collision at link time. */
29150 /* Use '.' to concatenate names as it is demangler friendly. */
29154 else
29158 }
29160 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29162 /* Make a dispatcher declaration for the multi-versioned function DECL.
29163 Calls to DECL function will be replaced with calls to the dispatcher
29164 by the front-end. Return the decl created. */
29166 static tree
29168 {
29169 tree func_decl;
29190 /* Mark this func as external, the resolver will flip it again if
29191 it gets generated. */
29193 /* This will be of type IFUNCs have to be externally visible. */
29197 }
29199 #endif
29201 /* Returns true if decl is multi-versioned and DECL is the default function,
29202 that is it is not tagged with target specific optimization. */
29204 static bool
29206 {
29210 }
29212 /* Make a dispatcher declaration for the multi-versioned function DECL.
29213 Calls to DECL function will be replaced with calls to the dispatcher
29214 by the front-end. Returns the decl of the dispatcher function. */
29216 static tree
29218 {
29227 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29231 #endif
29246 /* Find the default version and make it the first node. */
29248 /* Go to the beginnig of the chain. */
29253 {
29258 }
29260 /* If there is no default node, just return NULL. */
29264 /* Make default info the first node. */
29266 {
29273 }
29277 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29278 /* Right now, the dispatching is done via ifunc. */
29284 dispatcher_version_info
29289 /* Set the dispatcher for all the versions. */
29292 {
29295 }
29296 #else
29298 "multiversioning needs ifunc which is not supported "
29300 #endif
29302 }
29304 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29305 it to CHAIN. */
29307 static tree
29309 {
29310 tree attr_name;
29311 tree attr_arg_name;
29312 tree attr_args;
29313 tree attr;
29320 }
29322 /* Make the resolver function decl to dispatch the versions of
29323 a multi-versioned function, DEFAULT_DECL. Create an
29324 empty basic block in the resolver and store the pointer in
29325 EMPTY_BB. Return the decl of the resolver function. */
29327 static tree
29331 {
29336 /* IFUNC's have to be globally visible. So, if the default_decl is
29337 not, then the name of the IFUNC should be made unique. */
29341 /* Append the filename to the resolver function if the versions are
29342 not externally visible. This is because the resolver function has
29343 to be externally visible for the loader to find it. So, appending
29344 the filename will prevent conflicts with a resolver function from
29345 another module which is based on the same version name. */
29348 /* The resolver function should return a (void *). */
29359 /* IFUNC resolvers have to be externally visible. */
29363 /* Resolver is not external, body is generated. */
29373 {
29374 /* In this case, each translation unit with a call to this
29375 versioned function will put out a resolver. Ensure it
29376 is comdat to keep just one copy. */
29379 }
29380 /* Build result decl and add to function_decl. */
29396 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29400 /* Create the alias for dispatch to resolver here. */
29401 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29404 }
29406 /* Generate the dispatching code body to dispatch multi-versioned function
29407 DECL. The target hook is called to process the "target" attributes and
29408 provide the code to dispatch the right function at run-time. NODE points
29409 to the dispatcher decl whose body will be created. */
29411 static tree
29413 {
29414 tree resolver_decl;
29415 basic_block empty_bb;
29417 tree default_ver_decl;
29433 /* The first version in the chain corresponds to the default version. */
29436 /* node is going to be an alias, so remove the finalized bit. */
29450 {
29452 /* Check for virtual functions here again, as by this time it should
29453 have been determined if this function needs a vtable index or
29454 not. This happens for methods in derived classes that override
29455 virtual methods in base classes but are not explicitly marked as
29456 virtual. */
29461 }
29468 }
29469 /* This builds the processor_model struct type defined in
29470 libgcc/config/i386/cpuinfo.c */
29472 static tree
29474 {
29481 /* The first 3 fields are unsigned int. */
29483 {
29489 }
29491 /* The last field is an array of unsigned integers of size one. */
29502 }
29504 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29506 static tree
29508 {
29509 tree new_decl;
29512 VAR_DECL,
29514 type);
29527 }
29529 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29530 into an integer defined in libgcc/config/i386/cpuinfo.c */
29532 static tree
29534 {
29540 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29541 enum processor_features
29542 {
29544 F_MMX,
29545 F_POPCNT,
29546 F_SSE,
29547 F_SSE2,
29548 F_SSE3,
29549 F_SSSE3,
29550 F_SSE4_1,
29551 F_SSE4_2,
29552 F_AVX,
29553 F_AVX2,
29554 F_MAX
29555 };
29557 /* These are the values for vendor types and cpu types and subtypes
29558 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29559 the corresponding start value. */
29560 enum processor_model
29561 {
29563 M_AMD,
29564 M_CPU_TYPE_START,
29565 M_INTEL_ATOM,
29566 M_INTEL_CORE2,
29567 M_INTEL_COREI7,
29568 M_AMDFAM10H,
29569 M_AMDFAM15H,
29570 M_CPU_SUBTYPE_START,
29571 M_INTEL_COREI7_NEHALEM,
29572 M_INTEL_COREI7_WESTMERE,
29573 M_INTEL_COREI7_SANDYBRIDGE,
29574 M_AMDFAM10H_BARCELONA,
29575 M_AMDFAM10H_SHANGHAI,
29576 M_AMDFAM10H_ISTANBUL,
29577 M_AMDFAM15H_BDVER1,
29578 M_AMDFAM15H_BDVER2,
29579 M_AMDFAM15H_BDVER3
29580 };
29582 static struct _arch_names_table
29583 {
29586 }
29588 {
29605 };
29607 static struct _isa_names_table
29608 {
29611 }
29613 {
29625 };
29636 {
29637 /* *args must be a expr that can contain other EXPRS leading to a
29638 STRING_CST. */
29640 {
29643 }
29645 }
29650 {
29651 tree ref;
29652 tree field;
29653 tree final;
29656 unsigned int NUM_ARCH_NAMES
29665 {
29669 }
29674 /* CPU types are stored in the next field. */
29677 {
29680 }
29682 /* CPU subtypes are stored in the next field. */
29684 {
29687 }
29689 /* Get the appropriate field in __cpu_model. */
29693 /* Check the value. */
29697 }
29699 {
29700 tree ref;
29701 tree array_elt;
29702 tree field;
29703 tree final;
29706 unsigned int NUM_ISA_NAMES
29715 {
29719 }
29722 /* Get the last field, which is __cpu_features. */
29726 /* Get the appropriate field: __cpu_model.__cpu_features */
29730 /* Access the 0th element of __cpu_features array. */
29735 /* Return __cpu_model.__cpu_features[0] & field_val */
29739 }
29741 }
29743 static tree
29746 {
29748 {
29753 {
29756 }
29757 }
29759 #ifdef SUBTARGET_FOLD_BUILTIN
29761 #endif
29764 }
29766 /* Make builtins to detect cpu type and features supported. NAME is
29767 the builtin name, CODE is the builtin code, and FTYPE is the function
29768 type of the builtin. */
29770 static void
29773 {
29774 tree decl;
29775 tree type;
29783 }
29785 /* Make builtins to get CPU type and features supported. The created
29786 builtins are :
29788 __builtin_cpu_init (), to detect cpu type and features,
29789 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29790 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29791 */
29793 static void
29795 {
29802 }
29804 /* Internal method for ix86_init_builtins. */
29806 static void
29808 {
29820 sysv_va_ref =
29823 fnvoid_va_end_ms =
29825 fnvoid_va_start_ms =
29827 fnvoid_va_end_sysv =
29829 fnvoid_va_start_sysv =
29831 NULL_TREE);
29832 fnvoid_va_copy_ms =
29834 NULL_TREE);
29835 fnvoid_va_copy_sysv =
29851 }
29853 static void
29855 {
29858 /* The __float80 type. */
29861 {
29862 /* The __float80 type. */
29867 }
29870 /* The __float128 type. */
29876 /* This macro is built by i386-builtin-types.awk. */
29877 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29878 }
29880 static void
29882 {
29883 tree t;
29887 /* Builtins to get CPU type and features. */
29890 /* TFmode support builtins. */
29896 /* We will expand them to normal call if SSE isn't available since
29897 they are used by libgcc. */
29916 #ifdef SUBTARGET_INIT_BUILTINS
29917 SUBTARGET_INIT_BUILTINS;
29918 #endif
29919 }
29921 /* Return the ix86 builtin for CODE. */
29923 static tree
29925 {
29930 }
29932 /* Errors in the source file can cause expand_expr to return const0_rtx
29933 where we expect a vector. To avoid crashing, use one of the vector
29934 clear instructions. */
29935 static rtx
29937 {
29941 }
29943 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
29945 static rtx
29947 {
29948 rtx pat;
29968 {
29972 }
29986 }
29988 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
29990 static rtx
29994 {
29995 rtx pat;
30003 rtx op;
30010 {
30090 }
30100 {
30107 {
30109 {
30112 {
30130 xop_rotl:
30132 {
30135 gcc_checking_assert
30137 }
30138 else
30139 {
30140 gcc_checking_assert
30151 }
30155 }
30156 }
30157 }
30158 else
30159 {
30160 non_constant:
30164 /* If we aren't optimizing, only allow one memory operand to be
30165 generated. */
30167 num_memory++;
30175 }
30179 }
30182 {
30193 else
30194 {
30200 }
30213 }
30220 }
30222 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30223 insns with vec_merge. */
30225 static rtx
30227 rtx target)
30228 {
30229 rtx pat;
30256 }
30258 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30260 static rtx
30263 {
30264 rtx pat;
30269 rtx op2;
30280 /* Swap operands if we have a comparison that isn't available in
30281 hardware. */
30283 {
30288 }
30308 }
30310 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30312 static rtx
30314 rtx target)
30315 {
30316 rtx pat;
30330 /* Swap operands if we have a comparison that isn't available in
30331 hardware. */
30333 {
30337 }
30358 const0_rtx)));
30361 }
30363 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30365 static rtx
30367 rtx target)
30368 {
30369 rtx pat;
30394 }
30396 static rtx
30399 {
30400 rtx pat;
30405 rtx op2;
30432 }
30434 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30436 static rtx
30438 rtx target)
30439 {
30440 rtx pat;
30473 const0_rtx)));
30476 }
30478 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30480 static rtx
30483 {
30484 rtx pat;
30522 {
30525 }
30528 {
30537 }
30539 {
30548 }
30549 else
30550 {
30557 }
30565 {
30570 emit_insn
30574 FLAGS_REG),
30575 const0_rtx)));
30577 }
30578 else
30580 }
30583 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30585 static rtx
30588 {
30589 rtx pat;
30617 {
30620 }
30623 {
30632 }
30634 {
30643 }
30644 else
30645 {
30652 }
30660 {
30665 emit_insn
30669 FLAGS_REG),
30670 const0_rtx)));
30672 }
30673 else
30675 }
30677 /* Subroutine of ix86_expand_builtin to take care of insns with
30678 variable number of operands. */
30680 static rtx
30683 {
30688 struct
30689 {
30690 rtx op;
30702 {
30981 }
30986 {
30989 }
30992 {
30999 }
31000 else
31001 {
31004 }
31007 {
31014 {
31015 /* SIMD shift insns take either an 8-bit immediate or
31016 register as count. But builtin functions take int as
31017 count. If count doesn't match, we put it in register. */
31019 {
31023 }
31024 }
31026 {
31029 {
31083 {
31086 {
31089 }
31095 }
31097 }
31098 }
31099 else
31100 {
31104 /* If we aren't optimizing, only allow one memory operand to
31105 be generated. */
31107 num_memory++;
31110 {
31113 }
31114 else
31115 {
31118 }
31119 }
31123 }
31126 {
31143 }
31150 }
31152 /* Subroutine of ix86_expand_builtin to take care of special insns
31153 with variable number of operands. */
31155 static rtx
31158 {
31159 tree arg;
31162 struct
31163 {
31164 rtx op;
31174 {
31222 /* Reserve memory operand for target. */
31253 /* Reserve memory operand for target. */
31267 }
31272 {
31277 {
31280 }
31281 else
31284 }
31285 else
31286 {
31293 }
31296 {
31305 {
31307 {
31313 else
31316 }
31317 }
31318 else
31319 {
31321 {
31322 /* This must be the memory operand. */
31327 }
31328 else
31329 {
31330 /* This must be register. */
31337 }
31338 }
31342 }
31345 {
31360 }
31366 }
31368 /* Return the integer constant in ARG. Constrain it to be in the range
31369 of the subparts of VEC_TYPE; issue an error if not. */
31371 static int
31373 {
31378 {
31381 }
31384 }
31386 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31387 ix86_expand_vector_init. We DO have language-level syntax for this, in
31388 the form of (type){ init-list }. Except that since we can't place emms
31389 instructions from inside the compiler, we can't allow the use of MMX
31390 registers unless the user explicitly asks for it. So we do *not* define
31391 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31392 we have builtins invoked by mmintrin.h that gives us license to emit
31393 these sorts of instructions. */
31395 static rtx
31397 {
31407 {
31410 }
31417 }
31419 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31420 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31421 had a language-level syntax for referencing vector elements. */
31423 static rtx
31425 {
31429 rtx op0;
31449 }
31451 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31452 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31453 a language-level syntax for referencing vector elements. */
31455 static rtx
31457 {
31481 /* OP0 is the source of these builtin functions and shouldn't be
31482 modified. Create a copy, use it and return it as target. */
31488 }
31490 /* Expand an expression EXP that calls a built-in function,
31491 with result going to TARGET if that's convenient
31492 (and in mode MODE if that's convenient).
31493 SUBTARGET may be used as the target for computing one of EXP's operands.
31494 IGNORE is nonzero if the value is to be ignored. */
31496 static rtx
31500 {
31510 /* For CPU builtins that can be folded, fold first and expand the fold. */
31512 {
31514 {
31515 /* Make it call __cpu_indicator_init in libgcc. */
31521 }
31524 {
31529 }
31530 }
31532 /* Determine whether the builtin function is available under the current ISA.
31533 Originally the builtin was not created if it wasn't applicable to the
31534 current ISA based on the command line switches. With function specific
31535 options, we need to check in the context of the function making the call
31536 whether it is supported. */
31539 {
31545 else
31546 {
31550 }
31552 }
31555 {
31559 ? CODE_FOR_mmx_maskmovq
31561 /* Note the arg order is different from the operand order. */
31662 {
31663 REAL_VALUE_TYPE inf;
31664 rtx tmp;
31676 }
31686 {
31692 insn = (TARGET_64BIT
31696 }
31698 {
31699 insn = (TARGET_64BIT
31703 }
31704 else
31705 {
31708 insn = (TARGET_64BIT
31716 {
31719 }
31721 }
31727 {
31732 }
31742 {
31757 }
31763 {
31766 }
31786 {
31789 }
31795 {
31799 {
31820 }
31825 }
31826 else
31827 {
31829 {
31841 }
31843 }
31873 ? CODE_FOR_tbm_bextri_si
31876 {
31879 }
31880 else
31881 {
31890 }
31906 rdrand_step:
31913 {
31916 }
31922 /* Emit SImode conditional move. */
31924 {
31927 }
31930 else
31937 const0_rtx);
31956 rdseed_step:
31963 {
31966 }
31972 const0_rtx);
31990 addcarryx:
31998 /* Generate CF from input operand. */
32003 /* Gen ADCX instruction to compute X+Y+CF. */
32018 /* Store the result. */
32021 {
32024 }
32027 /* Return current CF value. */
32096 gather_gen:
32107 /* Note the arg order is different from the operand order. */
32116 else
32121 {
32127 }
32130 {
32135 else
32145 }
32147 /* Force memory operand only with base register here. But we
32148 don't want to do it on memory operand for other builtin
32149 functions. */
32161 {
32164 }
32166 /* Optimize. If mask is known to have all high bits set,
32167 replace op0 with pc_rtx to signal that the instruction
32168 overwrites the whole destination and doesn't use its
32169 previous contents. */
32171 {
32173 {
32176 {
32180 negative++;
32183 negative++;
32184 }
32187 }
32189 {
32190 /* Recognize also when mask is like:
32191 __v2df src = _mm_setzero_pd ();
32192 __v2df mask = _mm_cmpeq_pd (src, src);
32193 or
32194 __v8sf src = _mm256_setzero_ps ();
32195 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32196 as that is a cheaper way to load all ones into
32197 a register than having to load a constant from
32198 memory. */
32201 {
32206 {
32213 /* FALLTHRU */
32223 }
32224 }
32225 }
32226 }
32235 {
32242 else
32244 }
32245 else
32256 {
32259 }
32265 }
32278 {
32282 /* Emit a normal call if SSE isn't available. */
32286 }
32311 }
32313 /* Returns a function decl for a vectorized version of the builtin function
32314 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32315 if it is not available. */
32317 static tree
32319 tree type_in)
32320 {
32336 {
32339 {
32344 }
32349 {
32354 }
32360 /* The round insn does not trap on denormals. */
32365 {
32370 }
32376 /* The round insn does not trap on denormals. */
32381 {
32386 }
32392 /* The round insn does not trap on denormals. */
32397 {
32402 }
32408 /* The round insn does not trap on denormals. */
32413 {
32418 }
32425 {
32430 }
32437 {
32442 }
32448 /* The round insn does not trap on denormals. */
32453 {
32458 }
32464 /* The round insn does not trap on denormals. */
32469 {
32474 }
32479 {
32484 }
32489 {
32494 }
32498 /* The round insn does not trap on denormals. */
32503 {
32508 }
32512 /* The round insn does not trap on denormals. */
32517 {
32522 }
32526 /* The round insn does not trap on denormals. */
32531 {
32536 }
32540 /* The round insn does not trap on denormals. */
32545 {
32550 }
32554 /* The round insn does not trap on denormals. */
32559 {
32564 }
32568 /* The round insn does not trap on denormals. */
32573 {
32578 }
32582 /* The round insn does not trap on denormals. */
32587 {
32592 }
32596 /* The round insn does not trap on denormals. */
32601 {
32606 }
32610 /* The round insn does not trap on denormals. */
32615 {
32620 }
32624 /* The round insn does not trap on denormals. */
32629 {
32634 }
32639 {
32644 }
32649 {
32654 }
32659 }
32661 /* Dispatch to a handler for a vectorization library. */
32664 type_in);
32667 }
32669 /* Handler for an SVML-style interface to
32670 a library with vectorized intrinsics. */
32672 static tree
32674 {
32682 /* The SVML is suitable for unsafe math only. */
32695 {
32742 }
32751 {
32754 }
32755 else
32758 /* Convert to uppercase. */
32763 args;
32765 arity++;
32769 else
32772 /* Build a function declaration for the vectorized function. */
32781 }
32783 /* Handler for an ACML-style interface to
32784 a library with vectorized intrinsics. */
32786 static tree
32788 {
32796 /* The ACML is 64bits only and suitable for unsafe math only as
32797 it does not correctly support parts of IEEE with the required
32798 precision such as denormals. */
32812 {
32842 }
32849 args;
32851 arity++;
32855 else
32858 /* Build a function declaration for the vectorized function. */
32867 }
32869 /* Returns a decl of a function that implements gather load with
32870 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32871 Return NULL_TREE if it is not available. */
32873 static tree
32876 {
32892 /* v*gather* insn sign extends index to pointer mode. */
32904 {
32931 }
32934 }
32936 /* Returns a code for a target-specific builtin that implements
32937 reciprocal of the function, or NULL_TREE if not available. */
32939 static tree
32942 {
32949 /* Machine dependent builtins. */
32951 {
32952 /* Vectorized version of sqrt to rsqrt conversion. */
32961 }
32962 else
32963 /* Normal builtins. */
32965 {
32966 /* Sqrt to rsqrt conversion. */
32972 }
32973 }
32974 \f
32975 /* Helper for avx_vpermilps256_operand et al. This is also used by
32976 the expansion functions to turn the parallel back into a mask.
32977 The return value is 0 for no match and the imm8+1 for a match. */
32979 int
32981 {
32989 /* Validate that all of the elements are constants, and not totally
32990 out of range. Copy the data into an integral array to make the
32991 subsequent checks easier. */
32993 {
33003 }
33006 {
33008 /* In the 256-bit DFmode case, we can only move elements within
33009 a 128-bit lane. */
33011 {
33015 }
33017 {
33021 }
33025 /* In the 256-bit SFmode case, we have full freedom of movement
33026 within the low 128-bit lane, but the high 128-bit lane must
33027 mirror the exact same pattern. */
33032 /* FALLTHRU */
33036 /* In the 128-bit case, we've full freedom in the placement of
33037 the elements from the source operand. */
33044 }
33046 /* Make sure success has a non-zero value by adding one. */
33048 }
33050 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33051 the expansion functions to turn the parallel back into a mask.
33052 The return value is 0 for no match and the imm8+1 for a match. */
33054 int
33056 {
33064 /* Validate that all of the elements are constants, and not totally
33065 out of range. Copy the data into an integral array to make the
33066 subsequent checks easier. */
33068 {
33078 }
33080 /* Validate that the halves of the permute are halves. */
33088 /* Reconstruct the mask. */
33090 {
33096 }
33098 /* Make sure success has a non-zero value by adding one. */
33100 }
33101 \f
33102 /* Store OPERAND to the memory after reload is completed. This means
33103 that we can't easily use assign_stack_local. */
33104 rtx
33106 {
33107 rtx result;
33111 {
33114 stack_pointer_rtx,
33117 }
33119 {
33121 {
33125 /* FALLTHRU */
33131 stack_pointer_rtx)),
33132 operand));
33136 }
33138 }
33139 else
33140 {
33142 {
33144 {
33151 stack_pointer_rtx)),
33157 stack_pointer_rtx)),
33159 }
33162 /* Store HImodes as SImodes. */
33164 /* FALLTHRU */
33170 stack_pointer_rtx)),
33171 operand));
33175 }
33177 }
33179 }
33181 /* Free operand from the memory. */
33182 void
33184 {
33186 {
33191 else
33193 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33194 to pop or add instruction if registers are available. */
33198 }
33199 }
33201 /* Return a register priority for hard reg REGNO. */
33202 static int
33204 {
33205 /* ebp and r13 as the base always wants a displacement, r12 as the
33206 base always wants an index. So discourage their usage in an
33207 address. */
33212 /* New x86-64 int registers result in bigger code size. Discourage
33213 them. */
33216 /* New x86-64 SSE registers result in bigger code size. Discourage
33217 them. */
33220 /* Usage of AX register results in smaller code. Prefer it. */
33224 }
33226 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33228 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33229 QImode must go into class Q_REGS.
33230 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33231 movdf to do mem-to-mem moves through integer regs. */
33233 static reg_class_t
33235 {
33238 /* We're only allowed to return a subclass of CLASS. Many of the
33239 following checks fail for NO_REGS, so eliminate that early. */
33243 /* All classes can load zeros. */
33247 /* Force constants into memory if we are loading a (nonzero) constant into
33248 an MMX or SSE register. This is because there are no MMX/SSE instructions
33249 to load from a constant. */
33254 /* Prefer SSE regs only, if we can use them for math. */
33258 /* Floating-point constants need more complex checks. */
33260 {
33261 /* General regs can load everything. */
33265 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33266 zero above. We only want to wind up preferring 80387 registers if
33267 we plan on doing computation with them. */
33270 {
33271 /* Limit class to non-sse. */
33280 }
33283 }
33285 /* Generally when we see PLUS here, it's the function invariant
33286 (plus soft-fp const_int). Which can only be computed into general
33287 regs. */
33291 /* QImode constants are easy to load, but non-constant QImode data
33292 must go into Q_REGS. */
33294 {
33300 }
33303 }
33305 /* Discourage putting floating-point values in SSE registers unless
33306 SSE math is being used, and likewise for the 387 registers. */
33307 static reg_class_t
33309 {
33312 /* Restrict the output reload class to the register bank that we are doing
33313 math on. If we would like not to return a subset of CLASS, reject this
33314 alternative: if reload cannot do this, it will still use its choice. */
33320 {
33325 else
33327 }
33330 }
33332 static reg_class_t
33335 {
33336 /* Double-word spills from general registers to non-offsettable memory
33337 references (zero-extended addresses) require special handling. */
33343 {
33345 ? CODE_FOR_reload_noff_load
33347 /* Add the cost of moving address to a temporary. */
33351 }
33353 /* QImode spills from non-QI registers require
33354 intermediate register on 32bit targets. */
33363 {
33368 else
33374 /* Return Q_REGS if the operand is in memory. */
33377 }
33379 /* This condition handles corner case where an expression involving
33380 pointers gets vectorized. We're trying to use the address of a
33381 stack slot as a vector initializer.
33383 (set (reg:V2DI 74 [ vect_cst_.2 ])
33384 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33386 Eventually frame gets turned into sp+offset like this:
33388 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33389 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33390 (const_int 392 [0x188]))))
33392 That later gets turned into:
33394 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33395 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33396 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33398 We'll have the following reload recorded:
33400 Reload 0: reload_in (DI) =
33401 (plus:DI (reg/f:DI 7 sp)
33402 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33403 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33404 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33405 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33406 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33407 reload_reg_rtx: (reg:V2DI 22 xmm1)
33409 Which isn't going to work since SSE instructions can't handle scalar
33410 additions. Returning GENERAL_REGS forces the addition into integer
33411 register and reload can handle subsequent reloads without problems. */
33419 }
33421 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33423 static bool
33425 {
33427 {
33442 }
33445 }
33447 /* If we are copying between general and FP registers, we need a memory
33448 location. The same is true for SSE and MMX registers.
33450 To optimize register_move_cost performance, allow inline variant.
33452 The macro can't work reliably when one of the CLASSES is class containing
33453 registers from multiple units (SSE, MMX, integer). We avoid this by never
33454 combining those units in single alternative in the machine description.
33455 Ensure that this constraint holds to avoid unexpected surprises.
33457 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33458 enforce these sanity checks. */
33463 {
33470 {
33473 }
33478 /* ??? This is a lie. We do have moves between mmx/general, and for
33479 mmx/sse2. But by saying we need secondary memory we discourage the
33480 register allocator from using the mmx registers unless needed. */
33485 {
33486 /* SSE1 doesn't have any direct moves from other classes. */
33490 /* If the target says that inter-unit moves are more expensive
33491 than moving through memory, then don't generate them. */
33495 /* Between SSE and general, we have moves no larger than word size. */
33498 }
33501 }
33503 bool
33506 {
33508 }
33510 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33512 On the 80386, this is the size of MODE in words,
33513 except in the FP regs, where a single reg is always enough. */
33515 static unsigned char
33517 {
33519 {
33524 else
33526 }
33527 else
33528 {
33531 else
33533 }
33534 }
33536 /* Return true if the registers in CLASS cannot represent the change from
33537 modes FROM to TO. */
33539 bool
33542 {
33546 /* x87 registers can't do subreg at all, as all values are reformatted
33547 to extended precision. */
33552 {
33553 /* Vector registers do not support QI or HImode loads. If we don't
33554 disallow a change to these modes, reload will assume it's ok to
33555 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33556 the vec_dupv4hi pattern. */
33560 /* Vector registers do not support subreg with nonzero offsets, which
33561 are otherwise valid for integer registers. Since we can't see
33562 whether we have a nonzero offset from here, prohibit all
33563 nonparadoxical subregs changing size. */
33566 }
33569 }
33571 /* Return the cost of moving data of mode M between a
33572 register and memory. A value of 2 is the default; this cost is
33573 relative to those in `REGISTER_MOVE_COST'.
33575 This function is used extensively by register_move_cost that is used to
33576 build tables at startup. Make it inline in this case.
33577 When IN is 2, return maximum of in and out move cost.
33579 If moving between registers and memory is more expensive than
33580 between two registers, you should define this macro to express the
33581 relative cost.
33583 Model also increased moving costs of QImode registers in non
33584 Q_REGS classes.
33585 */
33589 {
33592 {
33595 {
33607 }
33611 }
33613 {
33616 {
33628 }
33632 }
33634 {
33637 {
33646 }
33650 }
33652 {
33655 {
33661 else
33666 }
33667 else
33668 {
33673 else
33675 }
33682 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33689 else
33693 }
33694 }
33696 static int
33699 {
33701 }
33704 /* Return the cost of moving data from a register in class CLASS1 to
33705 one in class CLASS2.
33707 It is not required that the cost always equal 2 when FROM is the same as TO;
33708 on some machines it is expensive to move between registers if they are not
33709 general registers. */
33711 static int
33713 reg_class_t class2_i)
33714 {
33718 /* In case we require secondary memory, compute cost of the store followed
33719 by load. In order to avoid bad register allocation choices, we need
33720 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33723 {
33729 /* In case of copying from general_purpose_register we may emit multiple
33730 stores followed by single load causing memory size mismatch stall.
33731 Count this as arbitrarily high cost of 20. */
33736 /* In the case of FP/MMX moves, the registers actually overlap, and we
33737 have to switch modes in order to treat them differently. */
33743 }
33745 /* Moves between SSE/MMX and integer unit are expensive. */
33749 /* ??? By keeping returned value relatively high, we limit the number
33750 of moves between integer and MMX/SSE registers for all targets.
33751 Additionally, high value prevents problem with x86_modes_tieable_p(),
33752 where integer modes in MMX/SSE registers are not tieable
33753 because of missing QImode and HImode moves to, from or between
33754 MMX/SSE registers. */
33764 }
33766 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33767 MODE. */
33769 bool
33771 {
33772 /* Flags and only flags can only hold CCmode values. */
33782 {
33783 /* We implement the move patterns for all vector modes into and
33784 out of SSE registers, even when no operation instructions
33785 are available. OImode move is available only when AVX is
33786 enabled. */
33793 }
33795 {
33796 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33797 so if the register is available at all, then we can move data of
33798 the given mode into or out of it. */
33801 }
33804 {
33805 /* Take care for QImode values - they can be in non-QI regs,
33806 but then they do cause partial register stalls. */
33812 }
33813 /* We handle both integer and floats in the general purpose registers. */
33820 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33821 on to use that value in smaller contexts, this can easily force a
33822 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33823 supporting DImode, allow it. */
33828 }
33830 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33831 tieable integer mode. */
33833 static bool
33835 {
33837 {
33850 }
33851 }
33853 /* Return true if MODE1 is accessible in a register that can hold MODE2
33854 without copying. That is, all register classes that can hold MODE2
33855 can also hold MODE1. */
33857 bool
33859 {
33867 /* MODE2 being XFmode implies fp stack or general regs, which means we
33868 can tie any smaller floating point modes to it. Note that we do not
33869 tie this with TFmode. */
33873 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33874 that we can tie it with SFmode. */
33878 /* If MODE2 is only appropriate for an SSE register, then tie with
33879 any other mode acceptable to SSE registers. */
33889 /* If MODE2 is appropriate for an MMX register, then tie
33890 with any other mode acceptable to MMX registers. */
33897 }
33899 /* Return the cost of moving between two registers of mode MODE. */
33901 static int
33903 {
33907 {
33938 }
33940 /* Return the cost of moving between two registers of mode MODE,
33941 assuming that the move will be in pieces of at most UNITS bytes. */
33943 }
33945 /* Compute a (partial) cost for rtx X. Return true if the complete
33946 cost has been computed, and false if subexpressions should be
33947 scanned. In either case, *TOTAL contains the cost result. */
33949 static bool
33952 {
33959 {
33963 {
33966 }
33978 && (!TARGET_64BIT
33983 else
33989 {
33992 }
33994 {
34004 }
34006 {
34009 {
34018 }
34019 }
34020 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34021 it'll probably end up. Add a penalty for size. */
34028 /* The zero extensions is often completely free on x86_64, so make
34029 it as cheap as possible. */
34035 else
34047 {
34050 {
34053 }
34056 {
34059 }
34060 }
34061 /* FALLTHRU */
34068 {
34069 /* ??? Should be SSE vector operation cost. */
34070 /* At least for published AMD latencies, this really is the same
34071 as the latency for a simple fpu operation like fabs. */
34072 /* V*QImode is emulated with 1-11 insns. */
34074 {
34077 {
34078 /* For XOP we use vpshab, which requires a broadcast of the
34079 value to the variable shift insn. For constants this
34080 means a V16Q const in mem; even when we can perform the
34081 shift with one insn set the cost to prefer paddb. */
34083 {
34088 }
34090 }
34094 }
34095 else
34097 }
34099 {
34101 {
34104 else
34106 }
34107 else
34108 {
34111 else
34113 }
34114 }
34115 else
34116 {
34119 else
34121 }
34125 {
34126 rtx sub;
34131 /* ??? SSE scalar/vector cost should be used here. */
34132 /* ??? Bald assumption that fma has the same cost as fmul. */
34136 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34147 }
34151 {
34152 /* ??? SSE scalar cost should be used here. */
34155 }
34157 {
34160 }
34162 {
34163 /* ??? SSE vector cost should be used here. */
34166 }
34168 {
34169 /* V*QImode is emulated with 7-13 insns. */
34171 {
34178 }
34179 /* V*DImode is emulated with 5-8 insns. */
34181 {
34184 else
34186 }
34187 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34188 insns, including two PMULUDQ. */
34191 else
34194 }
34195 else
34196 {
34201 {
34204 nbits++;
34205 }
34206 else
34207 /* This is arbitrary. */
34210 /* Compute costs correctly for widening multiplication. */
34214 {
34221 {
34225 else
34227 }
34231 }
34239 }
34246 /* ??? SSE cost should be used here. */
34251 /* ??? SSE vector cost should be used here. */
34253 else
34260 {
34265 {
34268 {
34276 }
34277 }
34280 {
34283 {
34289 }
34290 }
34292 {
34300 }
34301 }
34302 /* FALLTHRU */
34306 {
34307 /* ??? SSE cost should be used here. */
34310 }
34312 {
34315 }
34317 {
34318 /* ??? SSE vector cost should be used here. */
34321 }
34322 /* FALLTHRU */
34329 {
34336 }
34337 /* FALLTHRU */
34341 {
34342 /* ??? SSE cost should be used here. */
34345 }
34347 {
34350 }
34352 {
34353 /* ??? SSE vector cost should be used here. */
34356 }
34357 /* FALLTHRU */
34361 {
34362 /* ??? Should be SSE vector operation cost. */
34363 /* At least for published AMD latencies, this really is the same
34364 as the latency for a simple fpu operation like fabs. */
34366 }
34369 else
34378 {
34379 /* This kind of construct is implemented using test[bwl].
34380 Treat it as if we had an AND. */
34385 }
34395 /* ??? SSE cost should be used here. */
34400 /* ??? SSE vector cost should be used here. */
34406 /* ??? SSE cost should be used here. */
34411 /* ??? SSE vector cost should be used here. */
34424 /* ??? Assume all of these vector manipulation patterns are
34425 recognizable. In which case they all pretty much have the
34426 same cost. */
34432 }
34433 }
34435 #if TARGET_MACHO
34439 /* Given a symbol name and its associated stub, write out the
34440 definition of the stub. */
34442 void
34444 {
34449 /* For 64-bit we shouldn't get here. */
34452 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34469 else
34476 {
34478 }
34480 {
34481 /* PIC stub. */
34482 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34488 }
34489 else
34492 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34493 it needs no stub-binding-helper. */
34500 {
34503 }
34504 else
34509 /* N.B. Keep the correspondence of these
34510 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34511 old-pic/new-pic/non-pic stubs; altering this will break
34512 compatibility with existing dylibs. */
34514 {
34515 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34517 }
34518 else
34519 /* 16-byte -mdynamic-no-pic stub. */
34525 }
34528 /* Order the registers for register allocator. */
34530 void
34532 {
34536 /* First allocate the local general purpose registers. */
34541 /* Global general purpose registers. */
34546 /* x87 registers come first in case we are doing FP math
34547 using them. */
34552 /* SSE registers. */
34558 /* x87 registers. */
34566 /* Initialize the rest of array as we do not allocate some registers
34567 at all. */
34570 }
34572 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34573 in struct attribute_spec handler. */
34574 static tree
34576 tree args,
34579 {
34584 {
34586 name);
34589 }
34591 {
34593 name);
34596 }
34598 {
34599 tree cst;
34603 {
34606 name);
34608 }
34611 {
34614 name);
34616 }
34619 }
34622 }
34624 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34625 struct attribute_spec.handler. */
34626 static tree
34628 tree args ATTRIBUTE_UNUSED,
34630 {
34635 {
34637 name);
34640 }
34642 /* Can combine regparm with all attributes but fastcall. */
34644 {
34646 {
34648 }
34651 }
34653 {
34655 {
34657 }
34660 }
34663 }
34665 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34666 struct attribute_spec.handler. */
34667 static tree
34669 tree args ATTRIBUTE_UNUSED,
34671 {
34674 {
34677 }
34678 else
34682 {
34684 name);
34686 }
34692 {
34694 name);
34696 }
34699 }
34701 static tree
34703 tree args ATTRIBUTE_UNUSED,
34705 {
34707 {
34709 name);
34711 }
34713 }
34715 static bool
34717 {
34721 }
34723 /* Returns an expression indicating where the this parameter is
34724 located on entry to the FUNCTION. */
34726 static rtx
34728 {
34734 {
34739 else
34742 }
34747 {
34754 {
34759 }
34760 else
34761 {
34764 {
34770 }
34771 }
34773 }
34777 }
34779 /* Determine whether x86_output_mi_thunk can succeed. */
34781 static bool
34783 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34785 {
34786 /* 64-bit can handle anything. */
34790 /* For 32-bit, everything's fine if we have one free register. */
34794 /* Need a free register for vcall_offset. */
34798 /* Need a free register for GOT references. */
34802 /* Otherwise ok. */
34804 }
34806 /* Output the assembler code for a thunk function. THUNK_DECL is the
34807 declaration for the thunk function itself, FUNCTION is the decl for
34808 the target function. DELTA is an immediate constant offset to be
34809 added to THIS. If VCALL_OFFSET is nonzero, the word at
34810 *(*this + vcall_offset) should be added to THIS. */
34812 static void
34816 {
34823 else
34824 {
34830 else
34832 }
34836 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34837 pull it in now and let DELTA benefit. */
34841 {
34842 /* Put the this parameter into %eax. */
34845 }
34846 else
34849 /* Adjust the this parameter by a fixed constant. */
34851 {
34856 {
34858 {
34862 }
34863 }
34866 }
34868 /* Adjust the this parameter by a value stored in the vtable. */
34870 {
34880 /* Adjust the this parameter. */
34884 {
34888 }
34895 vcall_mem));
34896 else
34898 }
34900 /* If necessary, drop THIS back to its stack slot. */
34906 {
34909 ;
34910 else
34911 {
34915 }
34916 }
34917 else
34918 {
34920 ;
34921 #if TARGET_MACHO
34923 {
34926 }
34928 else
34929 {
34936 }
34937 }
34939 /* Our sibling call patterns do not allow memories, because we have no
34940 predicate that can distinguish between frame and non-frame memory.
34941 For our purposes here, we can get away with (ab)using a jump pattern,
34942 because we're going to do no optimization. */
34945 else
34946 {
34952 {
34958 }
34964 }
34967 /* Emit just enough of rest_of_compilation to get the insns emitted.
34968 Note that use_thunk calls assemble_start_function et al. */
34974 }
34976 static void
34978 {
34980 #if TARGET_MACHO
34982 #endif
34989 }
34991 int
34993 {
35005 }
35007 /* Output assembler code to FILE to increment profiler label # LABELNO
35008 for profiling a function entry. */
35009 void
35011 {
35016 {
35017 #ifndef NO_PROFILE_COUNTERS
35019 #endif
35023 else
35025 }
35027 {
35028 #ifndef NO_PROFILE_COUNTERS
35031 #endif
35033 }
35034 else
35035 {
35036 #ifndef NO_PROFILE_COUNTERS
35039 #endif
35041 }
35042 }
35044 /* We don't have exact information about the insn sizes, but we may assume
35045 quite safely that we are informed about all 1 byte insns and memory
35046 address sizes. This is enough to eliminate unnecessary padding in
35047 99% of cases. */
35049 static int
35051 {
35057 /* Discard alignments we've emit and jump instructions. */
35064 /* Important case - calls are always 5 bytes.
35065 It is common to have many calls in the row. */
35074 /* For normal instructions we rely on get_attr_length being exact,
35075 with a few exceptions. */
35077 {
35081 {
35091 /* Otherwise trust get_attr_length. */
35093 }
35098 }
35101 else
35103 }
35105 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35107 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35108 window. */
35110 static void
35112 {
35117 /* Look for all minimal intervals of instructions containing 4 jumps.
35118 The intervals are bounded by START and INSN. NBYTES is the total
35119 size of instructions in the interval including INSN and not including
35120 START. When the NBYTES is smaller than 16 bytes, it is possible
35121 that the end of START and INSN ends up in the same 16byte page.
35123 The smallest offset in the page INSN can start is the case where START
35124 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35125 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35126 */
35128 {
35132 {
35138 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35139 already in the current 16 byte page, because otherwise
35140 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35141 bytes to reach 16 byte boundary. */
35149 {
35151 {
35158 else
35161 }
35162 }
35164 }
35175 njumps++;
35176 else
35180 {
35187 else
35190 }
35197 {
35204 }
35205 }
35206 }
35207 #endif
35209 /* AMD Athlon works faster
35210 when RET is not destination of conditional jump or directly preceded
35211 by other jump instruction. We avoid the penalty by inserting NOP just
35212 before the RET instructions in such cases. */
35213 static void
35215 {
35216 edge e;
35217 edge_iterator ei;
35220 {
35223 rtx prev;
35233 {
35234 edge e;
35235 edge_iterator ei;
35241 }
35243 {
35249 /* Empty functions get branch mispredict even when
35250 the jump destination is not visible to us. */
35253 }
35255 {
35258 }
35259 }
35260 }
35262 /* Count the minimum number of instructions in BB. Return 4 if the
35263 number of instructions >= 4. */
35265 static int
35267 {
35268 rtx insn;
35271 /* Count number of instructions in this block. Return 4 if the number
35272 of instructions >= 4. */
35274 {
35275 /* Only happen in exit blocks. */
35283 {
35284 insn_count++;
35287 }
35288 }
35291 }
35294 /* Count the minimum number of instructions in code path in BB.
35295 Return 4 if the number of instructions >= 4. */
35297 static int
35299 {
35300 edge e;
35301 edge_iterator ei;
35304 /* Only bother counting instructions along paths with no
35305 more than 2 basic blocks between entry and exit. Given
35306 that BB has an edge to exit, determine if a predecessor
35307 of BB has an edge from entry. If so, compute the number
35308 of instructions in the predecessor block. If there
35309 happen to be multiple such blocks, compute the minimum. */
35312 {
35313 edge prev_e;
35314 edge_iterator prev_ei;
35317 {
35320 }
35322 {
35324 {
35329 }
35330 }
35331 }
35337 }
35339 /* Pad short function to 4 instructions. */
35341 static void
35343 {
35344 edge e;
35345 edge_iterator ei;
35348 {
35351 {
35354 /* Pad short function. */
35356 {
35359 /* Find epilogue. */
35368 /* Two NOPs count as one instruction. */
35371 }
35372 }
35373 }
35374 }
35376 /* Implement machine specific optimizations. We implement padding of returns
35377 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35378 static void
35380 {
35381 /* We are freeing block_for_insn in the toplev to keep compatibility
35382 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35386 {
35391 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35394 #endif
35395 }
35396 }
35398 /* Return nonzero when QImode register that must be represented via REX prefix
35399 is used. */
35400 bool
35402 {
35410 }
35412 /* Return nonzero when P points to register encoded via REX prefix.
35413 Called via for_each_rtx. */
35414 static int
35416 {
35422 }
35424 /* Return true when INSN mentions register that must be encoded using REX
35425 prefix. */
35426 bool
35428 {
35431 }
35433 /* If profitable, negate (without causing overflow) integer constant
35434 of mode MODE at location LOC. Return true in this case. */
35435 bool
35437 {
35438 HOST_WIDE_INT val;
35444 {
35446 /* DImode x86_64 constants must fit in 32 bits. */
35459 }
35461 /* Avoid overflows. */
35467 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35468 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35471 {
35474 }
35477 }
35479 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35480 optabs would emit if we didn't have TFmode patterns. */
35482 void
35484 {
35518 }
35519 \f
35520 /* AVX2 does support 32-byte integer vector operations,
35521 thus the longest vector we are faced with is V32QImode. */
35522 #define MAX_VECT_LEN 32
35524 struct expand_vec_perm_d
35525 {
35532 };
35538 /* Get a vector mode of the same size as the original but with elements
35539 twice as wide. This is only guaranteed to apply to integral vectors. */
35543 {
35544 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35549 }
35551 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35552 with all elements equal to VAR. Return true if successful. */
35554 static bool
35557 {
35561 {
35566 /* FALLTHRU */
35576 {
35579 /* First attempt to recognize VAL as-is. */
35583 {
35584 rtx seq;
35585 /* If that fails, force VAL into a register. */
35596 }
35597 }
35604 {
35605 rtx x;
35612 }
35622 {
35626 permute:
35634 /* Extend to SImode using a paradoxical SUBREG. */
35638 /* Insert the SImode value as low element of a V4SImode vector. */
35646 }
35654 widen:
35655 /* Replicate the value once into the next wider mode and recurse. */
35656 {
35658 rtx x;
35674 }
35678 {
35687 }
35692 }
35693 }
35695 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35696 whose ONE_VAR element is VAR, and other elements are zero. Return true
35697 if successful. */
35699 static bool
35702 {
35704 rtx new_target;
35709 {
35711 /* For SSE4.1, we normally use vector set. But if the second
35712 element is zero and inter-unit moves are OK, we use movq
35713 instead. */
35714 use_vector_set = (TARGET_64BIT
35715 && TARGET_SSE4_1
35716 && !(TARGET_INTER_UNIT_MOVES
35738 /* Use ix86_expand_vector_set in 64bit mode only. */
35743 }
35746 {
35751 }
35754 {
35759 /* FALLTHRU */
35774 else
35781 {
35782 /* We need to shuffle the value to the correct position, so
35783 create a new pseudo to store the intermediate result. */
35785 /* With SSE2, we can use the integer shuffle insns. */
35787 {
35789 const1_rtx,
35796 }
35798 /* Otherwise convert the intermediate result to V4SFmode and
35799 use the SSE1 shuffle instructions. */
35801 {
35804 }
35805 else
35809 const1_rtx,
35818 }
35833 widen:
35837 /* Zero extend the variable element to SImode and recurse. */
35850 }
35851 }
35853 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35854 consisting of the values in VALS. It is known that all elements
35855 except ONE_VAR are constants. Return true if successful. */
35857 static bool
35860 {
35870 {
35875 /* For the two element vectors, it's just as easy to use
35876 the general case. */
35880 /* Use ix86_expand_vector_set in 64bit mode only. */
35902 widen:
35903 /* There's no way to set one QImode entry easily. Combine
35904 the variable value with its adjacent constant value, and
35905 promote to an HImode set. */
35908 {
35913 }
35914 else
35915 {
35918 }
35932 }
35937 }
35939 /* A subroutine of ix86_expand_vector_init_general. Use vector
35940 concatenate to handle the most general case: all values variable,
35941 and none identical. */
35943 static void
35946 {
35949 rtvec v;
35953 {
35956 {
35989 }
36002 {
36017 }
36022 {
36033 }
36036 half:
36037 /* FIXME: We process inputs backward to help RA. PR 36222. */
36041 {
36046 }
36050 {
36053 {
36057 }
36060 }
36061 else
36067 }
36068 }
36070 /* A subroutine of ix86_expand_vector_init_general. Use vector
36071 interleave to handle the most general case: all values variable,
36072 and none identical. */
36074 static void
36077 {
36086 {
36107 }
36110 {
36111 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36115 /* Insert the SImode value as low element of V4SImode vector. */
36119 op0),
36121 const1_rtx);
36124 /* Cast the V4SImode vector back to a vector in orignal mode. */
36128 /* Load even elements into the second positon. */
36132 const1_rtx));
36134 /* Cast vector to FIRST_IMODE vector. */
36137 }
36139 /* Interleave low FIRST_IMODE vectors. */
36141 {
36145 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36148 }
36150 /* Interleave low SECOND_IMODE vectors. */
36152 {
36155 {
36160 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36161 vector. */
36164 }
36167 /* FALLTHRU */
36174 /* Cast the SECOND_IMODE vector back to a vector on original
36175 mode. */
36182 }
36183 }
36185 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36186 all values variable, and none identical. */
36188 static void
36191 {
36197 {
36202 /* FALLTHRU */
36226 half:
36243 /* FALLTHRU */
36249 /* Don't use ix86_expand_vector_init_interleave if we can't
36250 move from GPR to SSE register directly. */
36266 }
36268 {
36280 {
36284 {
36290 else
36291 {
36296 }
36297 }
36300 }
36305 {
36311 }
36313 {
36319 }
36320 else
36322 }
36323 }
36325 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36326 instructions unless MMX_OK is true. */
36328 void
36330 {
36337 rtx x;
36340 {
36350 }
36352 /* Constants are best loaded from the constant pool. */
36354 {
36357 }
36359 /* If all values are identical, broadcast the value. */
36365 /* Values where only one field is non-constant are best loaded from
36366 the pool and overwritten via move later. */
36368 {
36372 one_var))
36377 }
36380 }
36382 void
36384 {
36389 rtx tmp;
36391 = {
36398 };
36400 = {
36407 };
36411 {
36415 {
36420 else
36424 }
36436 else
36442 {
36445 /* For the two element vectors, we implement a VEC_CONCAT with
36446 the extraction of the other element. */
36453 else
36458 }
36467 {
36473 /* tmp = target = A B C D */
36475 /* target = A A B B */
36477 /* target = X A B B */
36479 /* target = A X C D */
36486 /* tmp = target = A B C D */
36488 /* tmp = X B C D */
36490 /* target = A B X D */
36497 /* tmp = target = A B C D */
36499 /* tmp = X B C D */
36501 /* target = A B X D */
36509 }
36517 /* Element 0 handled by vec_merge below. */
36519 {
36522 }
36525 {
36526 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36527 store into element 0, then shuffle them back. */
36544 }
36545 else
36546 {
36547 /* For SSE1, we have to reuse the V4SF code. */
36550 }
36603 half:
36604 /* Compute offset. */
36610 /* Extract the half. */
36614 /* Put val in tmp at elt. */
36617 /* Put it back. */
36623 }
36626 {
36630 }
36631 else
36632 {
36641 }
36642 }
36644 void
36646 {
36650 rtx tmp;
36653 {
36658 /* FALLTHRU */
36671 {
36691 }
36703 {
36705 {
36725 }
36729 }
36730 else
36731 {
36732 /* For SSE1, we have to reuse the V4SF code. */
36736 }
36752 {
36756 else
36760 }
36765 {
36769 else
36773 }
36778 {
36782 else
36786 }
36791 {
36795 else
36799 }
36804 {
36808 else
36812 }
36817 {
36821 else
36825 }
36829 /* ??? Could extract the appropriate HImode element and shift. */
36832 }
36835 {
36839 /* Let the rtl optimizers know about the zero extension performed. */
36841 {
36844 }
36847 }
36848 else
36849 {
36856 }
36857 }
36859 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36860 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36861 The upper bits of DEST are undefined, though they shouldn't cause
36862 exceptions (some bits from src or all zeros are ok). */
36864 static void
36866 {
36867 rtx tem;
36869 {
36873 else
36891 else
36898 else
36909 const1_rtx);
36910 else
36917 }
36919 }
36921 /* Expand a vector reduction. FN is the binary pattern to reduce;
36922 DEST is the destination; IN is the input vector. */
36924 void
36926 {
36931 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
36935 {
36938 }
36943 {
36948 else
36952 }
36953 }
36954 \f
36955 /* Target hook for scalar_mode_supported_p. */
36956 static bool
36958 {
36963 else
36965 }
36967 /* Implements target hook vector_mode_supported_p. */
36968 static bool
36970 {
36982 }
36984 /* Target hook for c_mode_for_suffix. */
36985 static enum machine_mode
36987 {
36994 }
36996 /* Worker function for TARGET_MD_ASM_CLOBBERS.
36998 We do this in the new i386 backend to maintain source compatibility
36999 with the old cc0-based compiler. */
37001 static tree
37003 tree inputs ATTRIBUTE_UNUSED,
37004 tree clobbers)
37005 {
37007 clobbers);
37009 clobbers);
37011 }
37013 /* Implements target vector targetm.asm.encode_section_info. */
37015 static void ATTRIBUTE_UNUSED
37017 {
37024 }
37026 /* Worker function for REVERSE_CONDITION. */
37028 enum rtx_code
37030 {
37034 }
37036 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37037 to OPERANDS[0]. */
37041 {
37043 {
37046 {
37050 }
37054 }
37056 {
37060 else
37061 {
37062 /* There is no non-popping store to memory for XFmode.
37063 So if we need one, follow the store with a load. */
37066 else
37068 }
37069 }
37070 else
37072 }
37074 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37075 FP status register is set. */
37077 void
37079 {
37081 rtx temp;
37086 {
37091 }
37092 else
37093 {
37098 }
37102 pc_rtx);
37107 }
37109 /* Output code to perform a log1p XFmode calculation. */
37112 {
37118 rtx test;
37124 XFmode));
37138 }
37140 /* Emit code for round calculation. */
37142 {
37149 rtx insn;
37154 {
37166 }
37169 {
37190 }
37198 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37200 /* scratch = fxam(op1) */
37203 UNSPEC_FXAM)));
37204 /* e1 = fabs(op1) */
37207 /* e2 = e1 + 0.5 */
37212 /* res = floor(e2) */
37214 {
37219 }
37220 else
37224 {
37227 {
37234 UNSPEC_TRUNC_NOOP)));
37235 }
37251 }
37253 /* flags = signbit(a) */
37256 /* if (flags) then res = -res */
37260 pc_rtx);
37271 }
37273 /* Output code to perform a Newton-Rhapson approximation of a single precision
37274 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37277 {
37285 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37289 /* x0 = rcp(b) estimate */
37292 UNSPEC_RCP)));
37293 /* e0 = x0 * b */
37297 /* e0 = x0 * e0 */
37301 /* e1 = x0 + x0 */
37305 /* x1 = e1 - e0 */
37309 /* res = a * x1 */
37312 }
37314 /* Output code to perform a Newton-Rhapson approximation of a
37315 single precision floating point [reciprocal] square root. */
37319 {
37321 REAL_VALUE_TYPE r;
37336 {
37339 }
37341 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37342 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37346 /* x0 = rsqrt(a) estimate */
37349 UNSPEC_RSQRT)));
37351 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37353 {
37365 }
37367 /* e0 = x0 * a */
37370 /* e1 = e0 * x0 */
37374 /* e2 = e1 - 3. */
37381 /* e3 = -.5 * x0 */
37384 else
37385 /* e3 = -.5 * e0 */
37388 /* ret = e2 * e3 */
37391 }
37393 #ifdef TARGET_SOLARIS
37394 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37396 static void
37398 tree decl)
37399 {
37400 /* With Binutils 2.15, the "@unwind" marker must be specified on
37401 every occurrence of the ".eh_frame" section, not just the first
37402 one. */
37405 {
37409 }
37411 #ifndef USE_GAS
37413 {
37416 }
37417 #endif
37420 }
37423 /* Return the mangling of TYPE if it is an extended fundamental type. */
37427 {
37435 {
37437 /* __float128 is "g". */
37440 /* "long double" or __float80 is "e". */
37444 }
37445 }
37447 /* For 32-bit code we can save PIC register setup by using
37448 __stack_chk_fail_local hidden function instead of calling
37449 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37450 register, so it is better to call __stack_chk_fail directly. */
37452 static tree ATTRIBUTE_UNUSED
37454 {
37455 return TARGET_64BIT
37458 }
37460 /* Select a format to encode pointers in exception handling data. CODE
37461 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37462 true if the symbol may be affected by dynamic relocations.
37464 ??? All x86 object file formats are capable of representing this.
37465 After all, the relocation needed is the same as for the call insn.
37466 Whether or not a particular assembler allows us to enter such, I
37467 guess we'll have to see. */
37468 int
37470 {
37472 {
37479 }
37484 }
37485 \f
37486 /* Expand copysign from SIGN to the positive value ABS_VALUE
37487 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37488 the sign-bit. */
37489 static void
37491 {
37495 {
37502 else
37507 {
37508 /* We need to generate a scalar mode mask in this case. */
37513 }
37514 }
37515 else
37521 }
37523 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37524 mask for masking out the sign-bit is stored in *SMASK, if that is
37525 non-null. */
37526 static rtx
37528 {
37537 else
37541 {
37542 /* We need to generate a scalar mode mask in this case. */
37547 }
37555 }
37557 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37558 swapping the operands if SWAP_OPERANDS is true. The expanded
37559 code is a forward jump to a newly created label in case the
37560 comparison is true. The generated label rtx is returned. */
37561 static rtx
37564 {
37568 {
37572 }
37585 }
37587 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37588 using comparison code CODE. Operands are swapped for the comparison if
37589 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37590 static rtx
37593 {
37599 {
37603 }
37610 }
37612 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37613 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37614 static rtx
37616 {
37617 REAL_VALUE_TYPE TWO52r;
37618 rtx TWO52;
37625 }
37627 /* Expand SSE sequence for computing lround from OP1 storing
37628 into OP0. */
37629 void
37631 {
37632 /* C code for the stuff we're doing below:
37633 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37634 return (long)tmp;
37635 */
37639 rtx adj;
37641 /* load nextafter (0.5, 0.0) */
37646 /* adj = copysign (0.5, op1) */
37650 /* adj = op1 + adj */
37653 /* op0 = (imode)adj */
37655 }
37657 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37658 into OPERAND0. */
37659 void
37661 {
37662 /* C code for the stuff we're doing below (for do_floor):
37663 xi = (long)op1;
37664 xi -= (double)xi > op1 ? 1 : 0;
37665 return xi;
37666 */
37671 /* reg = (long)op1 */
37675 /* freg = (double)reg */
37679 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37690 }
37692 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37693 result in OPERAND0. */
37694 void
37696 {
37697 /* C code for the stuff we're doing below:
37698 xa = fabs (operand1);
37699 if (!isless (xa, 2**52))
37700 return operand1;
37701 xa = xa + 2**52 - 2**52;
37702 return copysign (xa, operand1);
37703 */
37710 /* xa = abs (operand1) */
37713 /* if (!isless (xa, TWO52)) goto label; */
37726 }
37728 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37729 into OPERAND0. */
37730 void
37732 {
37733 /* C code for the stuff we expand below.
37734 double xa = fabs (x), x2;
37735 if (!isless (xa, TWO52))
37736 return x;
37737 xa = xa + TWO52 - TWO52;
37738 x2 = copysign (xa, x);
37739 Compensate. Floor:
37740 if (x2 > x)
37741 x2 -= 1;
37742 Compensate. Ceil:
37743 if (x2 < x)
37744 x2 -= -1;
37745 return x2;
37746 */
37752 /* Temporary for holding the result, initialized to the input
37753 operand to ease control flow. */
37757 /* xa = abs (operand1) */
37760 /* if (!isless (xa, TWO52)) goto label; */
37763 /* xa = xa + TWO52 - TWO52; */
37767 /* xa = copysign (xa, operand1) */
37770 /* generate 1.0 or -1.0 */
37775 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37779 /* We always need to subtract here to preserve signed zero. */
37788 }
37790 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37791 into OPERAND0. */
37792 void
37794 {
37795 /* C code for the stuff we expand below.
37796 double xa = fabs (x), x2;
37797 if (!isless (xa, TWO52))
37798 return x;
37799 x2 = (double)(long)x;
37800 Compensate. Floor:
37801 if (x2 > x)
37802 x2 -= 1;
37803 Compensate. Ceil:
37804 if (x2 < x)
37805 x2 += 1;
37806 if (HONOR_SIGNED_ZEROS (mode))
37807 return copysign (x2, x);
37808 return x2;
37809 */
37815 /* Temporary for holding the result, initialized to the input
37816 operand to ease control flow. */
37820 /* xa = abs (operand1) */
37823 /* if (!isless (xa, TWO52)) goto label; */
37826 /* xa = (double)(long)x */
37831 /* generate 1.0 */
37834 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37849 }
37851 /* Expand SSE sequence for computing round from OPERAND1 storing
37852 into OPERAND0. Sequence that works without relying on DImode truncation
37853 via cvttsd2siq that is only available on 64bit targets. */
37854 void
37856 {
37857 /* C code for the stuff we expand below.
37858 double xa = fabs (x), xa2, x2;
37859 if (!isless (xa, TWO52))
37860 return x;
37861 Using the absolute value and copying back sign makes
37862 -0.0 -> -0.0 correct.
37863 xa2 = xa + TWO52 - TWO52;
37864 Compensate.
37865 dxa = xa2 - xa;
37866 if (dxa <= -0.5)
37867 xa2 += 1;
37868 else if (dxa > 0.5)
37869 xa2 -= 1;
37870 x2 = copysign (xa2, x);
37871 return x2;
37872 */
37878 /* Temporary for holding the result, initialized to the input
37879 operand to ease control flow. */
37883 /* xa = abs (operand1) */
37886 /* if (!isless (xa, TWO52)) goto label; */
37889 /* xa2 = xa + TWO52 - TWO52; */
37893 /* dxa = xa2 - xa; */
37896 /* generate 0.5, 1.0 and -0.5 */
37902 /* Compensate. */
37904 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37909 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37915 /* res = copysign (xa2, operand1) */
37922 }
37924 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37925 into OPERAND0. */
37926 void
37928 {
37929 /* C code for SSE variant we expand below.
37930 double xa = fabs (x), x2;
37931 if (!isless (xa, TWO52))
37932 return x;
37933 x2 = (double)(long)x;
37934 if (HONOR_SIGNED_ZEROS (mode))
37935 return copysign (x2, x);
37936 return x2;
37937 */
37943 /* Temporary for holding the result, initialized to the input
37944 operand to ease control flow. */
37948 /* xa = abs (operand1) */
37951 /* if (!isless (xa, TWO52)) goto label; */
37954 /* x = (double)(long)x */
37966 }
37968 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37969 into OPERAND0. */
37970 void
37972 {
37976 /* C code for SSE variant we expand below.
37977 double xa = fabs (x), x2;
37978 if (!isless (xa, TWO52))
37979 return x;
37980 xa2 = xa + TWO52 - TWO52;
37981 Compensate:
37982 if (xa2 > xa)
37983 xa2 -= 1.0;
37984 x2 = copysign (xa2, x);
37985 return x2;
37986 */
37990 /* Temporary for holding the result, initialized to the input
37991 operand to ease control flow. */
37995 /* xa = abs (operand1) */
37998 /* if (!isless (xa, TWO52)) goto label; */
38001 /* res = xa + TWO52 - TWO52; */
38006 /* generate 1.0 */
38009 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38017 /* res = copysign (res, operand1) */
38024 }
38026 /* Expand SSE sequence for computing round from OPERAND1 storing
38027 into OPERAND0. */
38028 void
38030 {
38031 /* C code for the stuff we're doing below:
38032 double xa = fabs (x);
38033 if (!isless (xa, TWO52))
38034 return x;
38035 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38036 return copysign (xa, x);
38037 */
38043 /* Temporary for holding the result, initialized to the input
38044 operand to ease control flow. */
38052 /* load nextafter (0.5, 0.0) */
38057 /* xa = xa + 0.5 */
38061 /* xa = (double)(int64_t)xa */
38066 /* res = copysign (xa, operand1) */
38073 }
38075 /* Expand SSE sequence for computing round
38076 from OP1 storing into OP0 using sse4 round insn. */
38077 void
38079 {
38088 {
38099 }
38101 /* round (a) = trunc (a + copysign (0.5, a)) */
38103 /* load nextafter (0.5, 0.0) */
38109 /* e1 = copysign (0.5, op1) */
38113 /* e2 = op1 + e1 */
38116 /* res = trunc (e2) */
38121 }
38122 \f
38124 /* Table of valid machine attributes. */
38126 {
38127 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38128 affects_type_identity } */
38129 /* Stdcall attribute says callee is responsible for popping arguments
38130 if they are not variable. */
38133 /* Fastcall attribute says callee is responsible for popping arguments
38134 if they are not variable. */
38137 /* Thiscall attribute says callee is responsible for popping arguments
38138 if they are not variable. */
38141 /* Cdecl attribute says the callee is a normal C declaration */
38144 /* Regparm attribute specifies how many integer arguments are to be
38145 passed in registers. */
38148 /* Sseregparm attribute says we are using x86_64 calling conventions
38149 for FP arguments. */
38152 /* The transactional memory builtins are implicitly regparm or fastcall
38153 depending on the ABI. Override the generic do-nothing attribute that
38154 these builtins were declared with. */
38157 /* force_align_arg_pointer says this function realigns the stack at entry. */
38160 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38165 #endif
38170 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38171 SUBTARGET_ATTRIBUTE_TABLE,
38172 #endif
38173 /* ms_abi and sysv_abi calling convention function attributes. */
38180 /* End element. */
38182 };
38184 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38185 static int
38187 tree vectype,
38189 {
38193 {
38238 }
38239 }
38241 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38242 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38243 insn every time. */
38247 /* Initialize vselect_insn. */
38249 static void
38251 {
38253 rtx x;
38264 }
38266 /* Construct (set target (vec_select op0 (parallel perm))) and
38267 return true if that's a valid instruction in the active ISA. */
38269 static bool
38272 {
38298 }
38300 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38302 static bool
38306 {
38308 rtx x;
38323 }
38325 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38326 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38328 static bool
38330 {
38339 ;
38341 ;
38343 ;
38344 else
38347 /* This is a blend, not a permute. Elements must stay in their
38348 respective lanes. */
38350 {
38354 }
38359 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38360 decision should be extracted elsewhere, so that we only try that
38361 sequence once all budget==3 options have been tried. */
38368 {
38392 /* See if bytes move in pairs so we can use pblendw with
38393 an immediate argument, rather than pblendvb with a vector
38394 argument. */
38397 {
38398 use_pblendvb:
38402 finish_pblendvb:
38408 else
38411 }
38416 /* FALLTHRU */
38418 do_subreg:
38425 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38429 /* See if bytes move in quadruplets. If yes, vpblendd
38430 with immediate can be used. */
38435 {
38436 /* See if bytes move the same in both lanes. If yes,
38437 vpblendw with immediate can be used. */
38442 /* Use vpblendw. */
38447 }
38449 /* Use vpblendd. */
38456 /* See if words move in pairs. If yes, vpblendd can be used. */
38461 {
38462 /* See if words move the same in both lanes. If not,
38463 vpblendvb must be used. */
38466 {
38467 /* Use vpblendvb. */
38477 }
38479 /* Use vpblendw. */
38483 }
38485 /* Use vpblendd. */
38492 /* Use vpblendd. */
38500 }
38502 /* This matches five different patterns with the different modes. */
38508 }
38510 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38511 in terms of the variable form of vpermilps.
38513 Note that we will have already failed the immediate input vpermilps,
38514 which requires that the high and low part shuffle be identical; the
38515 variable form doesn't require that. */
38517 static bool
38519 {
38526 /* We can only permute within the 128-bit lane. */
38528 {
38532 }
38538 {
38541 /* Within each 128-bit lane, the elements of op0 are numbered
38542 from 0 and the elements of op1 are numbered from 4. */
38549 }
38556 }
38558 /* Return true if permutation D can be performed as VMODE permutation
38559 instead. */
38561 static bool
38563 {
38578 else
38584 }
38586 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38587 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38589 static bool
38591 {
38600 {
38602 {
38605 {
38609 /* Use vperm2i128 insn. The pattern uses
38610 V4DImode instead of V2TImode. */
38619 }
38621 }
38622 }
38623 else
38624 {
38626 {
38629 }
38631 {
38635 /* V4DImode should be already handled through
38636 expand_vselect by vpermq instruction. */
38643 {
38644 /* First see if vpermq can be used for
38645 V8SImode/V16HImode/V32QImode. */
38647 {
38655 }
38657 /* Next see if vpermd can be used. */
38660 }
38661 /* Or if vpermps can be used. */
38666 {
38667 /* vpshufb only works intra lanes, it is not
38668 possible to shuffle bytes in between the lanes. */
38672 }
38673 }
38674 else
38676 }
38684 else
38685 {
38691 else
38695 {
38699 }
38700 }
38709 {
38716 else
38718 }
38719 else
38720 {
38723 }
38726 }
38728 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38729 in a single instruction. */
38731 static bool
38733 {
38737 /* Check plain VEC_SELECT first, because AVX has instructions that could
38738 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38739 input where SEL+CONCAT may not. */
38741 {
38747 {
38753 }
38756 {
38760 }
38762 {
38763 /* Use vpbroadcast{b,w,d}. */
38766 {
38785 /* For other modes prefer other shuffles this function creates. */
38787 }
38789 {
38793 }
38794 }
38799 /* There are plenty of patterns in sse.md that are written for
38800 SEL+CONCAT and are not replicated for a single op. Perhaps
38801 that should be changed, to avoid the nastiness here. */
38803 /* Recognize interleave style patterns, which means incrementing
38804 every other permutation operand. */
38806 {
38809 }
38814 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38816 {
38818 {
38823 }
38828 }
38829 }
38831 /* Finally, try the fully general two operand permute. */
38836 /* Recognize interleave style patterns with reversed operands. */
38838 {
38840 {
38844 else
38847 }
38852 }
38854 /* Try the SSE4.1 blend variable merge instructions. */
38858 /* Try one of the AVX vpermil variable permutations. */
38862 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38863 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38868 }
38870 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38871 in terms of a pair of pshuflw + pshufhw instructions. */
38873 static bool
38875 {
38883 /* The two permutations only operate in 64-bit lanes. */
38894 /* Emit the pshuflw. */
38901 /* Emit the pshufhw. */
38909 }
38911 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38912 the permutation using the SSSE3 palignr instruction. This succeeds
38913 when all of the elements in PERM fit within one vector and we merely
38914 need to shift them down so that a single vector permutation has a
38915 chance to succeed. */
38917 static bool
38919 {
38923 rtx shift;
38925 /* Even with AVX, palignr only operates on 128-bit vectors. */
38931 {
38937 }
38941 /* Given that we have SSSE3, we know we'll be able to implement the
38942 single operand permutation after the palignr with pshufb. */
38956 {
38961 }
38963 /* Test for the degenerate case where the alignment by itself
38964 produces the desired permutation. */
38972 }
38976 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38977 a two vector permutation into a single vector permutation by using
38978 an interleave operation to merge the vectors. */
38980 static bool
38982 {
38987 rtx seq;
38991 {
38994 }
38996 {
38999 /* For 32-byte modes allow even d->one_operand_p.
39000 The lack of cross-lane shuffling in some instructions
39001 might prevent a single insn shuffle. */
39004 /* If expand_vec_perm_interleave3 can expand this into
39005 a 3 insn sequence, give up and let it be expanded as
39006 3 insn sequence. While that is one insn longer,
39007 it doesn't need a memory operand and in the common
39008 case that both interleave low and high permutations
39009 with the same operands are adjacent needs 4 insns
39010 for both after CSE. */
39013 }
39014 else
39017 /* Examine from whence the elements come. */
39026 {
39029 /* Split the two input vectors into 4 halves. */
39035 /* If the elements from the low halves use interleave low, and similarly
39036 for interleave high. If the elements are from mis-matched halves, we
39037 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39039 {
39040 /* punpckl* */
39042 {
39047 }
39050 }
39052 {
39053 /* punpckh* */
39055 {
39060 }
39063 }
39065 {
39066 /* shufps */
39068 {
39073 }
39075 {
39076 /* shufpd */
39081 }
39082 }
39084 {
39085 /* shufps */
39087 {
39092 }
39094 {
39095 /* shufpd */
39100 }
39101 }
39102 else
39104 }
39105 else
39106 {
39111 /* Split the two input vectors into 8 quarters. */
39117 {
39120 }
39123 {
39127 }
39129 {
39132 }
39135 {
39137 {
39138 /* Attempt to increase the likelihood that dfinal
39139 shuffle will be intra-lane. */
39143 }
39145 /* vperm2f128 or vperm2i128. */
39147 {
39152 }
39157 {
39161 {
39164 }
39165 }
39166 }
39171 {
39172 /* vpunpckl* */
39174 {
39183 }
39184 }
39187 {
39188 /* vpunpckh* */
39190 {
39199 }
39200 }
39201 else
39203 }
39205 /* Use the remapping array set up above to move the elements from their
39206 swizzled locations into their final destinations. */
39209 {
39212 /* If same_halves is true, both halves of the remapped vector are the
39213 same. Avoid cross-lane accesses if possible. */
39215 {
39218 }
39219 else
39221 }
39227 /* Test if the final remap can be done with a single insn. For V4SFmode or
39228 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39241 {
39245 }
39252 }
39254 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39255 a single vector cross-lane permutation into vpermq followed
39256 by any of the single insn permutations. */
39258 static bool
39260 {
39274 {
39277 }
39280 {
39285 }
39298 {
39305 }
39312 {
39317 ;
39320 else
39322 }
39331 }
39333 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39334 a vector permutation using two instructions, vperm2f128 resp.
39335 vperm2i128 followed by any single in-lane permutation. */
39337 static bool
39339 {
39353 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39354 immediate. For perm < 16 the second permutation uses
39355 d->op0 as first operand, for perm >= 16 it uses d->op1
39356 as first operand. The second operand is the result of
39357 vperm2[fi]128. */
39359 {
39360 /* Ignore permutations which do not move anything cross-lane. */
39362 {
39363 /* The second shuffle for e.g. V4DFmode has
39364 0123 and ABCD operands.
39365 Ignore AB23, as 23 is already in the second lane
39366 of the first operand. */
39368 /* And 01CD, as 01 is in the first lane of the first
39369 operand. */
39371 /* And 4567, as then the vperm2[fi]128 doesn't change
39372 anything on the original 4567 second operand. */
39374 }
39375 else
39376 {
39377 /* The second shuffle for e.g. V4DFmode has
39378 4567 and ABCD operands.
39379 Ignore AB67, as 67 is already in the second lane
39380 of the first operand. */
39382 /* And 45CD, as 45 is in the first lane of the first
39383 operand. */
39385 /* And 0123, as then the vperm2[fi]128 doesn't change
39386 anything on the original 0123 first operand. */
39388 }
39391 {
39397 else
39399 }
39402 {
39406 }
39407 else
39411 {
39415 /* Found a usable second shuffle. dfirst will be
39416 vperm2f128 on d->op0 and d->op1. */
39427 /* And dsecond is some single insn shuffle, taking
39428 d->op0 and result of vperm2f128 (if perm < 16) or
39429 d->op1 and result of vperm2f128 (otherwise). */
39438 }
39440 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39443 }
39446 }
39448 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39449 a two vector permutation using 2 intra-lane interleave insns
39450 and cross-lane shuffle for 32-byte vectors. */
39452 static bool
39454 {
39461 ;
39463 ;
39464 else
39479 {
39483 else
39489 else
39495 else
39501 else
39507 else
39513 else
39518 }
39522 }
39524 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39525 a single vector permutation using a single intra-lane vector
39526 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39527 the non-swapped and swapped vectors together. */
39529 static bool
39531 {
39534 rtx seq;
39539 || TARGET_AVX2
39548 {
39555 }
39590 }
39592 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39593 permutation using two vperm2f128, followed by a vshufpd insn blending
39594 the two vectors together. */
39596 static bool
39598 {
39641 }
39643 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39644 permutation with two pshufb insns and an ior. We should have already
39645 failed all two instruction sequences. */
39647 static bool
39649 {
39660 /* Generate two permutation masks. If the required element is within
39661 the given vector it is shuffled into the proper lane. If the required
39662 element is in the other vector, force a zero into the lane by setting
39663 bit 7 in the permutation mask. */
39666 {
39673 {
39676 }
39677 }
39697 }
39699 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39700 with two vpshufb insns, vpermq and vpor. We should have already failed
39701 all two or three instruction sequences. */
39703 static bool
39705 {
39720 /* Generate two permutation masks. If the required element is within
39721 the same lane, it is shuffled in. If the required element from the
39722 other lane, force a zero by setting bit 7 in the permutation mask.
39723 In the other mask the mask has non-negative elements if element
39724 is requested from the other lane, but also moved to the other lane,
39725 so that the result of vpshufb can have the two V2TImode halves
39726 swapped. */
39729 {
39734 {
39737 }
39738 }
39747 /* Swap the 128-byte lanes of h into hp. */
39751 const1_rtx));
39764 }
39766 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39767 and extract-odd permutations of two V32QImode and V16QImode operand
39768 with two vpshufb insns, vpor and vpermq. We should have already
39769 failed all two or three instruction sequences. */
39771 static bool
39773 {
39792 /* Generate two permutation masks. In the first permutation mask
39793 the first quarter will contain indexes for the first half
39794 of the op0, the second quarter will contain bit 7 set, third quarter
39795 will contain indexes for the second half of the op0 and the
39796 last quarter bit 7 set. In the second permutation mask
39797 the first quarter will contain bit 7 set, the second quarter
39798 indexes for the first half of the op1, the third quarter bit 7 set
39799 and last quarter indexes for the second half of the op1.
39800 I.e. the first mask e.g. for V32QImode extract even will be:
39801 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39802 (all values masked with 0xf except for -128) and second mask
39803 for extract even will be
39804 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39807 {
39813 {
39816 }
39817 }
39836 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39843 }
39845 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39846 and extract-odd permutations. */
39848 static bool
39850 {
39854 {
39859 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39863 /* Now an unpck[lh]pd will produce the result required. */
39866 else
39872 {
39879 /* Shuffle within the 128-bit lanes to produce:
39880 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39884 /* Shuffle the lanes around to produce:
39885 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39889 /* Shuffle within the 128-bit lanes to produce:
39890 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39893 /* Shuffle within the 128-bit lanes to produce:
39894 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39897 /* Shuffle the lanes around to produce:
39898 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39901 }
39908 /* These are always directly implementable by expand_vec_perm_1. */
39914 else
39915 {
39916 /* We need 2*log2(N)-1 operations to achieve odd/even
39917 with interleave. */
39926 else
39929 }
39935 else
39936 {
39948 else
39951 }
39960 {
39967 }
39972 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39976 /* Now an vpunpck[lh]qdq will produce the result required. */
39979 else
39986 {
39993 }
39998 /* Shuffle the lanes around into
39999 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40009 /* Swap the 2nd and 3rd position in each lane into
40010 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40016 /* Now an vpunpck[lh]qdq will produce
40017 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40022 else
40031 }
40034 }
40036 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40037 extract-even and extract-odd permutations. */
40039 static bool
40041 {
40053 }
40055 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40056 permutations. We assume that expand_vec_perm_1 has already failed. */
40058 static bool
40060 {
40068 {
40071 /* These are special-cased in sse.md so that we can optionally
40072 use the vbroadcast instruction. They expand to two insns
40073 if the input happens to be in a register. */
40080 /* These are always implementable using standard shuffle patterns. */
40085 /* These can be implemented via interleave. We save one insn by
40086 stopping once we have promoted to V4SImode and then use pshufd. */
40087 do
40088 {
40089 rtx dest;
40095 {
40099 }
40106 }
40119 /* For AVX2 broadcasts of the first element vpbroadcast* or
40120 vpermq should be used by expand_vec_perm_1. */
40126 }
40127 }
40129 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40130 broadcast permutations. */
40132 static bool
40134 {
40146 }
40148 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40149 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40150 all the shorter instruction sequences. */
40152 static bool
40154 {
40170 /* Generate 4 permutation masks. If the required element is within
40171 the same lane, it is shuffled in. If the required element from the
40172 other lane, force a zero by setting bit 7 in the permutation mask.
40173 In the other mask the mask has non-negative elements if element
40174 is requested from the other lane, but also moved to the other lane,
40175 so that the result of vpshufb can have the two V2TImode halves
40176 swapped. */
40179 {
40184 }
40190 {
40198 }
40201 {
40203 {
40206 }
40213 }
40215 /* Swap the 128-byte lanes of h[X]. */
40217 {
40223 const1_rtx));
40225 }
40228 {
40230 {
40233 }
40239 }
40242 {
40244 {
40248 }
40251 }
40257 }
40259 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40260 With all of the interface bits taken care of, perform the expansion
40261 in D and return true on success. */
40263 static bool
40265 {
40266 /* Try a single instruction expansion. */
40270 /* Try sequences of two instructions. */
40290 /* Try sequences of three instructions. */
40304 /* Try sequences of four instructions. */
40312 /* ??? Look for narrow permutations whose element orderings would
40313 allow the promotion to a wider mode. */
40315 /* ??? Look for sequences of interleave or a wider permute that place
40316 the data into the correct lanes for a half-vector shuffle like
40317 pshuf[lh]w or vpermilps. */
40319 /* ??? Look for sequences of interleave that produce the desired results.
40320 The combinatorics of punpck[lh] get pretty ugly... */
40325 /* Even longer sequences. */
40330 }
40332 /* If a permutation only uses one operand, make it clear. Returns true
40333 if the permutation references both operands. */
40335 static bool
40337 {
40345 {
40351 {
40354 }
40355 /* The elements of PERM do not suggest that only the first operand
40356 is used, but both operands are identical. Allow easier matching
40357 of the permutation by folding the permutation into the single
40358 input vector. */
40359 /* FALLTHRU */
40370 }
40373 }
40375 bool
40377 {
40382 rtx sel;
40399 {
40404 }
40411 /* If the selector says both arguments are needed, but the operands are the
40412 same, the above tried to expand with one_operand_p and flattened selector.
40413 If that didn't work, retry without one_operand_p; we succeeded with that
40414 during testing. */
40416 {
40420 }
40423 }
40425 /* Implement targetm.vectorize.vec_perm_const_ok. */
40427 static bool
40430 {
40439 /* Given sufficient ISA support we can just return true here
40440 for selected vector modes. */
40442 {
40443 /* All implementable with a single vpperm insn. */
40446 /* All implementable with 2 pshufb + 1 ior. */
40449 /* All implementable with shufpd or unpck[lh]pd. */
40452 }
40454 /* Extract the values from the vector CST into the permutation
40455 array in D. */
40458 {
40462 }
40464 /* For all elements from second vector, fold the elements to first. */
40469 /* Check whether the mask can be applied to the vector type. */
40472 /* Implementable with shufps or pshufd. */
40476 /* Otherwise we have to go through the motions and see if we can
40477 figure out how to generate the requested permutation. */
40488 }
40490 void
40492 {
40507 /* We'll either be able to implement the permutation directly... */
40511 /* ... or we use the special-case patterns. */
40513 }
40515 static void
40517 {
40532 {
40535 }
40537 /* Note that for AVX this isn't one instruction. */
40540 }
40543 /* Expand a vector operation CODE for a V*QImode in terms of the
40544 same operation on V*HImode. */
40546 void
40548 {
40560 {
40573 }
40577 {
40579 /* Unpack data such that we've got a source byte in each low byte of
40580 each word. We don't care what goes into the high byte of each word.
40581 Rather than trying to get zero in there, most convenient is to let
40582 it be a copy of the low byte. */
40587 /* FALLTHRU */
40599 /* FALLTHRU */
40609 }
40611 /* Perform the operation. */
40618 /* Merge the data back into the right place. */
40628 {
40629 /* For SSE2, we used an full interleave, so the desired
40630 results are in the even elements. */
40633 }
40634 else
40635 {
40636 /* For AVX, the interleave used above was not cross-lane. So the
40637 extraction is evens but with the second and third quarter swapped.
40638 Happily, that is even one insn shorter than even extraction. */
40641 }
40648 }
40650 void
40653 {
40656 rtx x;
40658 /* We only play even/odd games with vectors of SImode. */
40661 /* If we're looking for the odd results, shift those members down to
40662 the even slots. For some cpus this is faster than a PSHUFD. */
40664 {
40666 {
40670 }
40679 }
40682 {
40685 else
40687 }
40692 else
40693 {
40696 /* The easiest way to implement this without PMULDQ is to go through
40697 the motions as if we are performing a full 64-bit multiply. With
40698 the exception that we need to do less shuffling of the elements. */
40700 /* Compute the sign-extension, aka highparts, of the two operands. */
40706 /* Multiply LO(A) * HI(B), and vice-versa. */
40712 /* Multiply LO(A) * LO(B). */
40716 /* Combine and shift the highparts into place. */
40721 /* Combine high and low parts. */
40724 }
40726 }
40728 void
40731 {
40737 {
40742 {
40743 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40744 shuffle the elements once so that all elements are in the right
40745 place for immediate use: { A C B D }. */
40750 }
40751 else
40752 {
40753 /* Put the elements into place for the multiply. */
40757 }
40762 /* Shuffle the elements between the lanes. After this we
40763 have { A B E F | C D G H } for each operand. */
40773 /* Shuffle the elements within the lanes. After this we
40774 have { A A B B | C C D D } or { E E F F | G G H H }. */
40810 }
40811 }
40813 void
40815 {
40825 /* Move the results in element 2 down to element 1; we don't care
40826 what goes in elements 2 and 3. Then we can merge the parts
40827 back together with an interleave.
40829 Note that two other sequences were tried:
40830 (1) Use interleaves at the start instead of psrldq, which allows
40831 us to use a single shufps to merge things back at the end.
40832 (2) Use shufps here to combine the two vectors, then pshufd to
40833 put the elements in the correct order.
40834 In both cases the cost of the reformatting stall was too high
40835 and the overall sequence slower. */
40844 }
40846 void
40848 {
40853 {
40854 /* op1: A,B,C,D, op2: E,F,G,H */
40863 /* t1: B,A,D,C */
40870 /* t2: (B*E),(A*F),(D*G),(C*H) */
40873 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40876 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40879 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40881 }
40882 else
40883 {
40888 {
40891 }
40893 {
40896 }
40897 else
40901 /* Multiply low parts. */
40905 /* Shift input vectors right 32 bits so we can multiply high parts. */
40910 /* Multiply high parts by low parts. */
40916 /* Combine and shift the highparts back. */
40920 /* Combine high and low parts. */
40922 }
40926 }
40928 /* Expand an insert into a vector register through pinsr insn.
40929 Return true if successful. */
40931 bool
40933 {
40941 {
40944 }
40950 {
40955 {
40962 {
40994 }
41003 }
41007 }
41008 }
41009 \f
41010 /* This function returns the calling abi specific va_list type node.
41011 It returns the FNDECL specific va_list type. */
41013 static tree
41015 {
41022 else
41024 }
41026 /* Returns the canonical va_list type specified by TYPE. If there
41027 is no valid TYPE provided, it return NULL_TREE. */
41029 static tree
41031 {
41034 /* Resolve references and pointers to va_list type. */
41043 {
41048 {
41049 /* If va_list is an array type, the argument may have decayed
41050 to a pointer type, e.g. by being passed to another function.
41051 In that case, unwrap both types so that we can compare the
41052 underlying records. */
41055 {
41058 }
41059 }
41066 {
41067 /* If va_list is an array type, the argument may have decayed
41068 to a pointer type, e.g. by being passed to another function.
41069 In that case, unwrap both types so that we can compare the
41070 underlying records. */
41073 {
41076 }
41077 }
41084 {
41085 /* If va_list is an array type, the argument may have decayed
41086 to a pointer type, e.g. by being passed to another function.
41087 In that case, unwrap both types so that we can compare the
41088 underlying records. */
41091 {
41094 }
41095 }
41099 }
41101 }
41103 /* Iterate through the target-specific builtin types for va_list.
41104 IDX denotes the iterator, *PTREE is set to the result type of
41105 the va_list builtin, and *PNAME to its internal type.
41106 Returns zero if there is no element for this index, otherwise
41107 IDX should be increased upon the next call.
41108 Note, do not iterate a base builtin's name like __builtin_va_list.
41109 Used from c_common_nodes_and_builtins. */
41111 static int
41113 {
41115 {
41117 {
41130 }
41131 }
41134 }
41136 #undef TARGET_SCHED_DISPATCH
41137 #define TARGET_SCHED_DISPATCH has_dispatch
41138 #undef TARGET_SCHED_DISPATCH_DO
41139 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41140 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41141 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41142 #undef TARGET_SCHED_REORDER
41143 #define TARGET_SCHED_REORDER ix86_sched_reorder
41144 #undef TARGET_SCHED_ADJUST_PRIORITY
41145 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41146 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41147 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41149 /* The size of the dispatch window is the total number of bytes of
41150 object code allowed in a window. */
41151 #define DISPATCH_WINDOW_SIZE 16
41153 /* Number of dispatch windows considered for scheduling. */
41154 #define MAX_DISPATCH_WINDOWS 3
41156 /* Maximum number of instructions in a window. */
41157 #define MAX_INSN 4
41159 /* Maximum number of immediate operands in a window. */
41160 #define MAX_IMM 4
41162 /* Maximum number of immediate bits allowed in a window. */
41163 #define MAX_IMM_SIZE 128
41165 /* Maximum number of 32 bit immediates allowed in a window. */
41166 #define MAX_IMM_32 4
41168 /* Maximum number of 64 bit immediates allowed in a window. */
41169 #define MAX_IMM_64 2
41171 /* Maximum total of loads or prefetches allowed in a window. */
41172 #define MAX_LOAD 2
41174 /* Maximum total of stores allowed in a window. */
41175 #define MAX_STORE 1
41177 #undef BIG
41178 #define BIG 100
41181 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41184 disp_load,
41185 disp_store,
41186 disp_load_store,
41187 disp_prefetch,
41188 disp_imm,
41189 disp_imm_32,
41190 disp_imm_64,
41191 disp_branch,
41192 disp_cmp,
41193 disp_jcc,
41194 disp_last
41195 };
41197 /* Number of allowable groups in a dispatch window. It is an array
41198 indexed by dispatch_group enum. 100 is used as a big number,
41199 because the number of these kind of operations does not have any
41200 effect in dispatch window, but we need them for other reasons in
41201 the table. */
41204 };
41210 };
41212 /* Instruction path. */
41218 last_path
41219 };
41221 /* sched_insn_info defines a window to the instructions scheduled in
41222 the basic block. It contains a pointer to the insn_info table and
41223 the instruction scheduled.
41225 Windows are allocated for each basic block and are linked
41226 together. */
41228 rtx insn;
41235 /* Linked list of dispatch windows. This is a two way list of
41236 dispatch windows of a basic block. It contains information about
41237 the number of uops in the window and the total number of
41238 instructions and of bytes in the object code for this dispatch
41239 window. */
41257 /* Immediate valuse used in an insn. */
41259 {
41268 /* Get dispatch group of insn. */
41270 static enum dispatch_group
41272 {
41288 }
41290 /* Return true if insn is a compare instruction. */
41292 static bool
41294 {
41302 }
41304 /* Return true if a dispatch violation encountered. */
41306 static bool
41308 {
41312 }
41314 /* Return true if insn is a branch instruction. */
41316 static bool
41318 {
41320 }
41322 /* Return true if insn is a prefetch instruction. */
41324 static bool
41326 {
41328 }
41330 /* This function initializes a dispatch window and the list container holding a
41331 pointer to the window. */
41333 static void
41335 {
41341 else
41359 {
41365 }
41367 }
41369 /* This function allocates and initializes a dispatch window and the
41370 list container holding a pointer to the window. */
41374 {
41379 }
41381 /* This routine initializes the dispatch scheduling information. It
41382 initiates building dispatch scheduler tables and constructs the
41383 first dispatch window. */
41385 static void
41387 {
41388 /* Allocate a dispatch list and a window. */
41393 }
41395 /* This function returns true if a branch is detected. End of a basic block
41396 does not have to be a branch, but here we assume only branches end a
41397 window. */
41399 static bool
41401 {
41403 }
41405 /* This function is called when the end of a window processing is reached. */
41407 static void
41409 {
41412 {
41417 }
41419 }
41421 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41422 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41423 for 48 bytes of instructions. Note that these windows are not dispatch
41424 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41428 {
41430 {
41435 }
41441 }
41443 /* Increment the number of immediate operands of an instruction. */
41445 static int
41447 {
41452 {
41459 else
41470 {
41473 }
41478 }
41481 }
41483 /* Compute number of immediate operands of an instruction. */
41485 static void
41487 {
41490 }
41492 /* Return total size of immediate operands of an instruction along with number
41493 of corresponding immediate-operands. It initializes its parameters to zero
41494 befor calling FIND_CONSTANT.
41495 INSN is the input instruction. IMM is the total of immediates.
41496 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41497 bit immediates. */
41499 static int
41501 {
41509 }
41511 /* This function indicates if an operand of an instruction is an
41512 immediate. */
41514 static bool
41516 {
41525 }
41527 /* Return single or double path for instructions. */
41529 static enum insn_path
41531 {
41541 }
41543 /* Return insn dispatch group. */
41545 static enum dispatch_group
41547 {
41565 }
41567 /* Count number of GROUP restricted instructions in a dispatch
41568 window WINDOW_LIST. */
41570 static int
41572 {
41583 {
41602 }
41615 }
41617 /* This function returns true if insn satisfies dispatch rules on the
41618 last window scheduled. */
41620 static bool
41622 {
41630 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41631 instructions should be given the lowest priority in the
41632 scheduling process in Haifa scheduler to make sure they will be
41633 scheduled in the same dispatch window as the reference to them. */
41637 /* Check nonrestricted. */
41641 /* Get last dispatch window. */
41646 {
41651 /* Window 1 is full. Go for next window. */
41653 }
41660 /* See if it fits in the first window. */
41662 {
41663 /* The first widow should have only single and double path
41664 uops. */
41670 }
41672 }
41674 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41675 dispatch window WINDOW_LIST. */
41677 static void
41679 {
41697 /* Initialize window with new instruction. */
41718 {
41721 }
41722 }
41724 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41725 If the total bytes of instructions or the number of instructions in
41726 the window exceed allowable, it allocates a new window. */
41728 static void
41730 {
41753 /* Get the last dispatch window. */
41761 else
41764 /* If current window is full, get a new window.
41765 Window number zero is full, if MAX_INSN uops are scheduled in it.
41766 Window number one is full, if window zero's bytes plus window
41767 one's bytes is 32, or if the bytes of the new instruction added
41768 to the total makes it greater than 48, or it has already MAX_INSN
41769 instructions in it. */
41778 {
41781 }
41784 {
41788 {
41791 }
41792 }
41794 {
41799 {
41802 }
41805 }
41806 else
41810 {
41811 /* End of basic block is reached do end-basic-block process. */
41814 }
41815 }
41817 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41819 DEBUG_FUNCTION static void
41821 {
41827 else
41841 {
41844 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41850 }
41851 }
41853 /* Print to stdout a dispatch window. */
41855 DEBUG_FUNCTION void
41857 {
41859 }
41861 /* Print INSN dispatch information to FILE. */
41863 DEBUG_FUNCTION static void
41865 {
41888 }
41890 /* Print to STDERR the status of the ready list with respect to
41891 dispatch windows. */
41893 DEBUG_FUNCTION void
41895 {
41903 }
41905 /* This routine is the driver of the dispatch scheduler. */
41907 static void
41909 {
41914 }
41916 /* Return TRUE if Dispatch Scheduling is supported. */
41918 static bool
41920 {
41924 {
41940 }
41943 }
41945 /* Implementation of reassociation_width target hook used by
41946 reassoc phase to identify parallelism level in reassociated
41947 tree. Statements tree_code is passed in OPC. Arguments type
41948 is passed in MODE.
41950 Currently parallel reassociation is enabled for Atom
41951 processors only and we set reassociation width to be 2
41952 because Atom may issue up to 2 instructions per cycle.
41954 Return value should be fixed if parallel reassociation is
41955 enabled for other processors. */
41957 static int
41960 {
41969 }
41971 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
41972 place emms and femms instructions. */
41974 static enum machine_mode
41976 {
41981 {
41994 else
42004 /* FALLTHRU */
42008 }
42009 }
42011 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42012 vectors. */
42014 static unsigned int
42016 {
42018 }
42020 \f
42022 /* Return class of registers which could be used for pseudo of MODE
42023 and of class RCLASS for spilling instead of memory. Return NO_REGS
42024 if it is not possible or non-profitable. */
42025 static reg_class_t
42027 {
42034 }
42036 /* Implement targetm.vectorize.init_cost. */
42040 {
42044 }
42046 /* Implement targetm.vectorize.add_stmt_cost. */
42048 static unsigned
42052 {
42057 {
42061 /* Statements in an inner loop relative to the loop being
42062 vectorized are weighted more heavily. The value here is
42063 arbitrary and could potentially be improved with analysis. */
42069 }
42072 }
42074 /* Implement targetm.vectorize.finish_cost. */
42076 static void
42079 {
42084 }
42086 /* Implement targetm.vectorize.destroy_cost_data. */
42088 static void
42090 {
42092 }
42094 /* Validate target specific memory model bits in VAL. */
42096 static unsigned HOST_WIDE_INT
42098 {
42105 {
42109 }
42112 {
42116 }
42118 {
42122 }
42124 }
42126 /* Initialize the GCC target structure. */
42127 #undef TARGET_RETURN_IN_MEMORY
42128 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42130 #undef TARGET_LEGITIMIZE_ADDRESS
42131 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42133 #undef TARGET_ATTRIBUTE_TABLE
42134 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42135 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42136 # undef TARGET_MERGE_DECL_ATTRIBUTES
42137 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42138 #endif
42140 #undef TARGET_COMP_TYPE_ATTRIBUTES
42141 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42143 #undef TARGET_INIT_BUILTINS
42144 #define TARGET_INIT_BUILTINS ix86_init_builtins
42145 #undef TARGET_BUILTIN_DECL
42146 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42147 #undef TARGET_EXPAND_BUILTIN
42148 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42150 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42151 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42152 ix86_builtin_vectorized_function
42154 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42155 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42157 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42158 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42160 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42161 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42163 #undef TARGET_BUILTIN_RECIPROCAL
42164 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42166 #undef TARGET_ASM_FUNCTION_EPILOGUE
42167 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42169 #undef TARGET_ENCODE_SECTION_INFO
42170 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42171 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42172 #else
42173 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42174 #endif
42176 #undef TARGET_ASM_OPEN_PAREN
42178 #undef TARGET_ASM_CLOSE_PAREN
42181 #undef TARGET_ASM_BYTE_OP
42182 #define TARGET_ASM_BYTE_OP ASM_BYTE
42184 #undef TARGET_ASM_ALIGNED_HI_OP
42185 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42186 #undef TARGET_ASM_ALIGNED_SI_OP
42187 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42188 #ifdef ASM_QUAD
42189 #undef TARGET_ASM_ALIGNED_DI_OP
42190 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42191 #endif
42193 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42194 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42196 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42197 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42199 #undef TARGET_ASM_UNALIGNED_HI_OP
42200 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42201 #undef TARGET_ASM_UNALIGNED_SI_OP
42202 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42203 #undef TARGET_ASM_UNALIGNED_DI_OP
42204 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42206 #undef TARGET_PRINT_OPERAND
42207 #define TARGET_PRINT_OPERAND ix86_print_operand
42208 #undef TARGET_PRINT_OPERAND_ADDRESS
42209 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42210 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42211 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42212 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42213 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42215 #undef TARGET_SCHED_INIT_GLOBAL
42216 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42217 #undef TARGET_SCHED_ADJUST_COST
42218 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42219 #undef TARGET_SCHED_ISSUE_RATE
42220 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42221 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42222 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42223 ia32_multipass_dfa_lookahead
42225 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42226 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42228 #undef TARGET_MEMMODEL_CHECK
42229 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42231 #ifdef HAVE_AS_TLS
42232 #undef TARGET_HAVE_TLS
42233 #define TARGET_HAVE_TLS true
42234 #endif
42235 #undef TARGET_CANNOT_FORCE_CONST_MEM
42236 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42237 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42238 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42240 #undef TARGET_DELEGITIMIZE_ADDRESS
42241 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42243 #undef TARGET_MS_BITFIELD_LAYOUT_P
42244 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42246 #if TARGET_MACHO
42247 #undef TARGET_BINDS_LOCAL_P
42248 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42249 #endif
42250 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42251 #undef TARGET_BINDS_LOCAL_P
42252 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42253 #endif
42255 #undef TARGET_ASM_OUTPUT_MI_THUNK
42256 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42257 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42258 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42260 #undef TARGET_ASM_FILE_START
42261 #define TARGET_ASM_FILE_START x86_file_start
42263 #undef TARGET_OPTION_OVERRIDE
42264 #define TARGET_OPTION_OVERRIDE ix86_option_override
42266 #undef TARGET_REGISTER_MOVE_COST
42267 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42268 #undef TARGET_MEMORY_MOVE_COST
42269 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42270 #undef TARGET_RTX_COSTS
42271 #define TARGET_RTX_COSTS ix86_rtx_costs
42272 #undef TARGET_ADDRESS_COST
42273 #define TARGET_ADDRESS_COST ix86_address_cost
42275 #undef TARGET_FIXED_CONDITION_CODE_REGS
42276 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42277 #undef TARGET_CC_MODES_COMPATIBLE
42278 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42280 #undef TARGET_MACHINE_DEPENDENT_REORG
42281 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42283 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42284 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42286 #undef TARGET_BUILD_BUILTIN_VA_LIST
42287 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42289 #undef TARGET_FOLD_BUILTIN
42290 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42292 #undef TARGET_COMPARE_VERSION_PRIORITY
42293 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42295 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42296 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42297 ix86_generate_version_dispatcher_body
42299 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42300 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42301 ix86_get_function_versions_dispatcher
42303 #undef TARGET_ENUM_VA_LIST_P
42304 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42306 #undef TARGET_FN_ABI_VA_LIST
42307 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42309 #undef TARGET_CANONICAL_VA_LIST_TYPE
42310 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42312 #undef TARGET_EXPAND_BUILTIN_VA_START
42313 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42315 #undef TARGET_MD_ASM_CLOBBERS
42316 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42318 #undef TARGET_PROMOTE_PROTOTYPES
42319 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42320 #undef TARGET_STRUCT_VALUE_RTX
42321 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42322 #undef TARGET_SETUP_INCOMING_VARARGS
42323 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42324 #undef TARGET_MUST_PASS_IN_STACK
42325 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42326 #undef TARGET_FUNCTION_ARG_ADVANCE
42327 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42328 #undef TARGET_FUNCTION_ARG
42329 #define TARGET_FUNCTION_ARG ix86_function_arg
42330 #undef TARGET_FUNCTION_ARG_BOUNDARY
42331 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42332 #undef TARGET_PASS_BY_REFERENCE
42333 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42334 #undef TARGET_INTERNAL_ARG_POINTER
42335 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42336 #undef TARGET_UPDATE_STACK_BOUNDARY
42337 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42338 #undef TARGET_GET_DRAP_RTX
42339 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42340 #undef TARGET_STRICT_ARGUMENT_NAMING
42341 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42342 #undef TARGET_STATIC_CHAIN
42343 #define TARGET_STATIC_CHAIN ix86_static_chain
42344 #undef TARGET_TRAMPOLINE_INIT
42345 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42346 #undef TARGET_RETURN_POPS_ARGS
42347 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42349 #undef TARGET_LEGITIMATE_COMBINED_INSN
42350 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42352 #undef TARGET_ASAN_SHADOW_OFFSET
42353 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42355 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42356 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42358 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42359 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42361 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42362 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42364 #undef TARGET_C_MODE_FOR_SUFFIX
42365 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42367 #ifdef HAVE_AS_TLS
42368 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42369 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42370 #endif
42372 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42373 #undef TARGET_INSERT_ATTRIBUTES
42374 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42375 #endif
42377 #undef TARGET_MANGLE_TYPE
42378 #define TARGET_MANGLE_TYPE ix86_mangle_type
42380 #if !TARGET_MACHO
42381 #undef TARGET_STACK_PROTECT_FAIL
42382 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42383 #endif
42385 #undef TARGET_FUNCTION_VALUE
42386 #define TARGET_FUNCTION_VALUE ix86_function_value
42388 #undef TARGET_FUNCTION_VALUE_REGNO_P
42389 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42391 #undef TARGET_PROMOTE_FUNCTION_MODE
42392 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42394 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42395 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42397 #undef TARGET_INSTANTIATE_DECLS
42398 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42400 #undef TARGET_SECONDARY_RELOAD
42401 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42403 #undef TARGET_CLASS_MAX_NREGS
42404 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42406 #undef TARGET_PREFERRED_RELOAD_CLASS
42407 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42408 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42409 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42410 #undef TARGET_CLASS_LIKELY_SPILLED_P
42411 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42413 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42414 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42415 ix86_builtin_vectorization_cost
42416 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42417 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42418 ix86_vectorize_vec_perm_const_ok
42419 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42420 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42421 ix86_preferred_simd_mode
42422 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42423 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42424 ix86_autovectorize_vector_sizes
42425 #undef TARGET_VECTORIZE_INIT_COST
42426 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42427 #undef TARGET_VECTORIZE_ADD_STMT_COST
42428 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42429 #undef TARGET_VECTORIZE_FINISH_COST
42430 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42431 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42432 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42434 #undef TARGET_SET_CURRENT_FUNCTION
42435 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42437 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42438 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42440 #undef TARGET_OPTION_SAVE
42441 #define TARGET_OPTION_SAVE ix86_function_specific_save
42443 #undef TARGET_OPTION_RESTORE
42444 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42446 #undef TARGET_OPTION_PRINT
42447 #define TARGET_OPTION_PRINT ix86_function_specific_print
42449 #undef TARGET_OPTION_FUNCTION_VERSIONS
42450 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42452 #undef TARGET_OPTION_SUPPORTS_FUNCTION_VERSIONS
42453 #define TARGET_OPTION_SUPPORTS_FUNCTION_VERSIONS \
42454 ix86_supports_function_versions
42456 #undef TARGET_CAN_INLINE_P
42457 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42459 #undef TARGET_EXPAND_TO_RTL_HOOK
42460 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42462 #undef TARGET_LEGITIMATE_ADDRESS_P
42463 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42465 #undef TARGET_LRA_P
42466 #define TARGET_LRA_P hook_bool_void_true
42468 #undef TARGET_REGISTER_PRIORITY
42469 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42471 #undef TARGET_LEGITIMATE_CONSTANT_P
42472 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42474 #undef TARGET_FRAME_POINTER_REQUIRED
42475 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42477 #undef TARGET_CAN_ELIMINATE
42478 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42480 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42481 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42483 #undef TARGET_ASM_CODE_END
42484 #define TARGET_ASM_CODE_END ix86_code_end
42486 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42487 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42489 #if TARGET_MACHO
42490 #undef TARGET_INIT_LIBFUNCS
42491 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42492 #endif
42494 #undef TARGET_SPILL_CLASS
42495 #define TARGET_SPILL_CLASS ix86_spill_class
42498 \f