1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static rtx
emit_set_insn (rtx
, rtx
);
146 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
149 #ifdef OBJECT_FORMAT_ELF
150 static void arm_elf_asm_constructor (rtx
, int);
153 static void arm_encode_section_info (tree
, rtx
, int);
156 static void arm_file_end (void);
159 static void aof_globalize_label (FILE *, const char *);
160 static void aof_dump_imports (FILE *);
161 static void aof_dump_pic_table (FILE *);
162 static void aof_file_start (void);
163 static void aof_file_end (void);
164 static void aof_asm_init_sections (void);
166 static rtx
arm_struct_value_rtx (tree
, int);
167 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
169 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
170 enum machine_mode
, tree
, bool);
171 static bool arm_promote_prototypes (tree
);
172 static bool arm_default_short_enums (void);
173 static bool arm_align_anon_bitfield (void);
174 static bool arm_return_in_msb (tree
);
175 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
176 #ifdef TARGET_UNWIND_INFO
177 static void arm_unwind_emit (FILE *, rtx
);
178 static bool arm_output_ttype (rtx
);
181 static tree
arm_cxx_guard_type (void);
182 static bool arm_cxx_guard_mask_bit (void);
183 static tree
arm_get_cookie_size (tree
);
184 static bool arm_cookie_has_size (void);
185 static bool arm_cxx_cdtor_returns_this (void);
186 static bool arm_cxx_key_method_may_be_inline (void);
187 static void arm_cxx_determine_class_data_visibility (tree
);
188 static bool arm_cxx_class_data_always_comdat (void);
189 static bool arm_cxx_use_aeabi_atexit (void);
190 static void arm_init_libfuncs (void);
191 static bool arm_handle_option (size_t, const char *, int);
192 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
193 static bool arm_cannot_copy_insn_p (rtx
);
194 static bool arm_tls_symbol_p (rtx x
);
197 /* Initialize the GCC target structure. */
198 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
199 #undef TARGET_MERGE_DECL_ATTRIBUTES
200 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
203 #undef TARGET_ATTRIBUTE_TABLE
204 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
206 #undef TARGET_ASM_FILE_END
207 #define TARGET_ASM_FILE_END arm_file_end
210 #undef TARGET_ASM_BYTE_OP
211 #define TARGET_ASM_BYTE_OP "\tDCB\t"
212 #undef TARGET_ASM_ALIGNED_HI_OP
213 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
214 #undef TARGET_ASM_ALIGNED_SI_OP
215 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
216 #undef TARGET_ASM_GLOBALIZE_LABEL
217 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
218 #undef TARGET_ASM_FILE_START
219 #define TARGET_ASM_FILE_START aof_file_start
220 #undef TARGET_ASM_FILE_END
221 #define TARGET_ASM_FILE_END aof_file_end
223 #undef TARGET_ASM_ALIGNED_SI_OP
224 #define TARGET_ASM_ALIGNED_SI_OP NULL
225 #undef TARGET_ASM_INTEGER
226 #define TARGET_ASM_INTEGER arm_assemble_integer
229 #undef TARGET_ASM_FUNCTION_PROLOGUE
230 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
232 #undef TARGET_ASM_FUNCTION_EPILOGUE
233 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
235 #undef TARGET_DEFAULT_TARGET_FLAGS
236 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
237 #undef TARGET_HANDLE_OPTION
238 #define TARGET_HANDLE_OPTION arm_handle_option
240 #undef TARGET_COMP_TYPE_ATTRIBUTES
241 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
243 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
244 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
246 #undef TARGET_SCHED_ADJUST_COST
247 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
249 #undef TARGET_ENCODE_SECTION_INFO
251 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
253 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
256 #undef TARGET_STRIP_NAME_ENCODING
257 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
259 #undef TARGET_ASM_INTERNAL_LABEL
260 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
262 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
263 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
265 #undef TARGET_ASM_OUTPUT_MI_THUNK
266 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
267 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
268 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
270 /* This will be overridden in arm_override_options. */
271 #undef TARGET_RTX_COSTS
272 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
273 #undef TARGET_ADDRESS_COST
274 #define TARGET_ADDRESS_COST arm_address_cost
276 #undef TARGET_SHIFT_TRUNCATION_MASK
277 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
278 #undef TARGET_VECTOR_MODE_SUPPORTED_P
279 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
281 #undef TARGET_MACHINE_DEPENDENT_REORG
282 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
284 #undef TARGET_INIT_BUILTINS
285 #define TARGET_INIT_BUILTINS arm_init_builtins
286 #undef TARGET_EXPAND_BUILTIN
287 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
289 #undef TARGET_INIT_LIBFUNCS
290 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
292 #undef TARGET_PROMOTE_FUNCTION_ARGS
293 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
294 #undef TARGET_PROMOTE_FUNCTION_RETURN
295 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
296 #undef TARGET_PROMOTE_PROTOTYPES
297 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
298 #undef TARGET_PASS_BY_REFERENCE
299 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
300 #undef TARGET_ARG_PARTIAL_BYTES
301 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
303 #undef TARGET_STRUCT_VALUE_RTX
304 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
306 #undef TARGET_SETUP_INCOMING_VARARGS
307 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
309 #undef TARGET_DEFAULT_SHORT_ENUMS
310 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
312 #undef TARGET_ALIGN_ANON_BITFIELD
313 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
315 #undef TARGET_CXX_GUARD_TYPE
316 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
318 #undef TARGET_CXX_GUARD_MASK_BIT
319 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
321 #undef TARGET_CXX_GET_COOKIE_SIZE
322 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
324 #undef TARGET_CXX_COOKIE_HAS_SIZE
325 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
327 #undef TARGET_CXX_CDTOR_RETURNS_THIS
328 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
330 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
331 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
333 #undef TARGET_CXX_USE_AEABI_ATEXIT
334 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
336 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
337 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
338 arm_cxx_determine_class_data_visibility
340 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
341 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
343 #undef TARGET_RETURN_IN_MSB
344 #define TARGET_RETURN_IN_MSB arm_return_in_msb
346 #undef TARGET_MUST_PASS_IN_STACK
347 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
349 #ifdef TARGET_UNWIND_INFO
350 #undef TARGET_UNWIND_EMIT
351 #define TARGET_UNWIND_EMIT arm_unwind_emit
353 /* EABI unwinding tables use a different format for the typeinfo tables. */
354 #undef TARGET_ASM_TTYPE
355 #define TARGET_ASM_TTYPE arm_output_ttype
357 #undef TARGET_ARM_EABI_UNWINDER
358 #define TARGET_ARM_EABI_UNWINDER true
359 #endif /* TARGET_UNWIND_INFO */
361 #undef TARGET_CANNOT_COPY_INSN_P
362 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
365 #undef TARGET_HAVE_TLS
366 #define TARGET_HAVE_TLS true
369 #undef TARGET_CANNOT_FORCE_CONST_MEM
370 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
372 struct gcc_target targetm
= TARGET_INITIALIZER
;
374 /* Obstack for minipool constant handling. */
375 static struct obstack minipool_obstack
;
376 static char * minipool_startobj
;
378 /* The maximum number of insns skipped which
379 will be conditionalised if possible. */
380 static int max_insns_skipped
= 5;
382 extern FILE * asm_out_file
;
384 /* True if we are currently building a constant table. */
385 int making_const_table
;
387 /* Define the information needed to generate branch insns. This is
388 stored from the compare operation. */
389 rtx arm_compare_op0
, arm_compare_op1
;
391 /* The processor for which instructions should be scheduled. */
392 enum processor_type arm_tune
= arm_none
;
394 /* Which floating point model to use. */
395 enum arm_fp_model arm_fp_model
;
397 /* Which floating point hardware is available. */
398 enum fputype arm_fpu_arch
;
400 /* Which floating point hardware to schedule for. */
401 enum fputype arm_fpu_tune
;
403 /* Whether to use floating point hardware. */
404 enum float_abi_type arm_float_abi
;
406 /* Which ABI to use. */
407 enum arm_abi_type arm_abi
;
409 /* Which thread pointer model to use. */
410 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
412 /* Used to parse -mstructure_size_boundary command line option. */
413 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
415 /* Used for Thumb call_via trampolines. */
416 rtx thumb_call_via_label
[14];
417 static int thumb_call_reg_needed
;
419 /* Bit values used to identify processor capabilities. */
420 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
421 #define FL_ARCH3M (1 << 1) /* Extended multiply */
422 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
423 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
424 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
425 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
426 #define FL_THUMB (1 << 6) /* Thumb aware */
427 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
428 #define FL_STRONG (1 << 8) /* StrongARM */
429 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
430 #define FL_XSCALE (1 << 10) /* XScale */
431 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
432 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
433 media instructions. */
434 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
435 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
436 Note: ARM6 & 7 derivatives only. */
437 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
439 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
441 #define FL_FOR_ARCH2 0
442 #define FL_FOR_ARCH3 FL_MODE32
443 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
444 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
445 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
446 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
447 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
448 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
449 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
450 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
451 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
452 #define FL_FOR_ARCH6J FL_FOR_ARCH6
453 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
454 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
455 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
457 /* The bits in this mask specify which
458 instructions we are allowed to generate. */
459 static unsigned long insn_flags
= 0;
461 /* The bits in this mask specify which instruction scheduling options should
463 static unsigned long tune_flags
= 0;
465 /* The following are used in the arm.md file as equivalents to bits
466 in the above two flag variables. */
468 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
471 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
474 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
477 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
480 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
483 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
486 /* Nonzero if this chip supports the ARM 6K extensions. */
489 /* Nonzero if this chip can benefit from load scheduling. */
490 int arm_ld_sched
= 0;
492 /* Nonzero if this chip is a StrongARM. */
493 int arm_tune_strongarm
= 0;
495 /* Nonzero if this chip is a Cirrus variant. */
496 int arm_arch_cirrus
= 0;
498 /* Nonzero if this chip supports Intel Wireless MMX technology. */
499 int arm_arch_iwmmxt
= 0;
501 /* Nonzero if this chip is an XScale. */
502 int arm_arch_xscale
= 0;
504 /* Nonzero if tuning for XScale */
505 int arm_tune_xscale
= 0;
507 /* Nonzero if we want to tune for stores that access the write-buffer.
508 This typically means an ARM6 or ARM7 with MMU or MPU. */
509 int arm_tune_wbuf
= 0;
511 /* Nonzero if generating Thumb instructions. */
514 /* Nonzero if we should define __THUMB_INTERWORK__ in the
516 XXX This is a bit of a hack, it's intended to help work around
517 problems in GLD which doesn't understand that armv5t code is
518 interworking clean. */
519 int arm_cpp_interwork
= 0;
521 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
522 must report the mode of the memory reference from PRINT_OPERAND to
523 PRINT_OPERAND_ADDRESS. */
524 enum machine_mode output_memory_reference_mode
;
526 /* The register number to be used for the PIC offset register. */
527 unsigned arm_pic_register
= INVALID_REGNUM
;
529 /* Set to 1 when a return insn is output, this means that the epilogue
531 int return_used_this_function
;
533 /* Set to 1 after arm_reorg has started. Reset to start at the start of
534 the next function. */
535 static int after_arm_reorg
= 0;
537 /* The maximum number of insns to be used when loading a constant. */
538 static int arm_constant_limit
= 3;
540 /* For an explanation of these variables, see final_prescan_insn below. */
542 enum arm_cond_code arm_current_cc
;
544 int arm_target_label
;
546 /* The condition codes of the ARM, and the inverse function. */
547 static const char * const arm_condition_codes
[] =
549 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
550 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
553 #define streq(string1, string2) (strcmp (string1, string2) == 0)
555 /* Initialization code. */
559 const char *const name
;
560 enum processor_type core
;
562 const unsigned long flags
;
563 bool (* rtx_costs
) (rtx
, int, int, int *);
566 /* Not all of these give usefully different compilation alternatives,
567 but there is no simple way of generalizing them. */
568 static const struct processors all_cores
[] =
571 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
572 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
573 #include "arm-cores.def"
575 {NULL
, arm_none
, NULL
, 0, NULL
}
578 static const struct processors all_architectures
[] =
580 /* ARM Architectures */
581 /* We don't specify rtx_costs here as it will be figured out
584 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
585 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
586 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
587 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
588 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
589 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
590 implementations that support it, so we will leave it out for now. */
591 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
592 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
593 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
594 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
595 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
596 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
597 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
598 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
599 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
600 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
601 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
602 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
603 {NULL
, arm_none
, NULL
, 0 , NULL
}
606 struct arm_cpu_select
610 const struct processors
* processors
;
613 /* This is a magic structure. The 'string' field is magically filled in
614 with a pointer to the value specified by the user on the command line
615 assuming that the user has specified such a value. */
617 static struct arm_cpu_select arm_select
[] =
619 /* string name processors */
620 { NULL
, "-mcpu=", all_cores
},
621 { NULL
, "-march=", all_architectures
},
622 { NULL
, "-mtune=", all_cores
}
625 /* Defines representing the indexes into the above table. */
626 #define ARM_OPT_SET_CPU 0
627 #define ARM_OPT_SET_ARCH 1
628 #define ARM_OPT_SET_TUNE 2
630 /* The name of the proprocessor macro to define for this architecture. */
632 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
641 /* Available values for -mfpu=. */
643 static const struct fpu_desc all_fpus
[] =
645 {"fpa", FPUTYPE_FPA
},
646 {"fpe2", FPUTYPE_FPA_EMU2
},
647 {"fpe3", FPUTYPE_FPA_EMU2
},
648 {"maverick", FPUTYPE_MAVERICK
},
653 /* Floating point models used by the different hardware.
654 See fputype in arm.h. */
656 static const enum fputype fp_model_for_fpu
[] =
658 /* No FP hardware. */
659 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
660 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
661 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
662 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
663 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
664 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
671 enum float_abi_type abi_type
;
675 /* Available values for -mfloat-abi=. */
677 static const struct float_abi all_float_abis
[] =
679 {"soft", ARM_FLOAT_ABI_SOFT
},
680 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
681 {"hard", ARM_FLOAT_ABI_HARD
}
688 enum arm_abi_type abi_type
;
692 /* Available values for -mabi=. */
694 static const struct abi_name arm_all_abis
[] =
696 {"apcs-gnu", ARM_ABI_APCS
},
697 {"atpcs", ARM_ABI_ATPCS
},
698 {"aapcs", ARM_ABI_AAPCS
},
699 {"iwmmxt", ARM_ABI_IWMMXT
},
700 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
703 /* Supported TLS relocations. */
713 /* Emit an insn that's a simple single-set. Both the operands must be known
716 emit_set_insn (rtx x
, rtx y
)
718 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
721 /* Return the number of bits set in VALUE. */
723 bit_count (unsigned long value
)
725 unsigned long count
= 0;
730 value
&= value
- 1; /* Clear the least-significant set bit. */
736 /* Set up library functions unique to ARM. */
739 arm_init_libfuncs (void)
741 /* There are no special library functions unless we are using the
746 /* The functions below are described in Section 4 of the "Run-Time
747 ABI for the ARM architecture", Version 1.0. */
749 /* Double-precision floating-point arithmetic. Table 2. */
750 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
751 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
752 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
753 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
754 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
756 /* Double-precision comparisons. Table 3. */
757 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
758 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
759 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
760 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
761 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
762 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
763 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
765 /* Single-precision floating-point arithmetic. Table 4. */
766 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
767 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
768 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
769 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
770 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
772 /* Single-precision comparisons. Table 5. */
773 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
774 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
775 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
776 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
777 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
778 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
779 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
781 /* Floating-point to integer conversions. Table 6. */
782 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
783 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
784 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
785 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
786 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
787 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
788 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
789 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
791 /* Conversions between floating types. Table 7. */
792 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
793 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
795 /* Integer to floating-point conversions. Table 8. */
796 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
797 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
798 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
799 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
800 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
801 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
802 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
803 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
805 /* Long long. Table 9. */
806 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
807 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
808 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
809 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
810 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
811 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
812 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
813 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
815 /* Integer (32/32->32) division. \S 4.3.1. */
816 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
817 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
819 /* The divmod functions are designed so that they can be used for
820 plain division, even though they return both the quotient and the
821 remainder. The quotient is returned in the usual location (i.e.,
822 r0 for SImode, {r0, r1} for DImode), just as would be expected
823 for an ordinary division routine. Because the AAPCS calling
824 conventions specify that all of { r0, r1, r2, r3 } are
825 callee-saved registers, there is no need to tell the compiler
826 explicitly that those registers are clobbered by these
828 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
829 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
831 /* For SImode division the ABI provides div-without-mod routines,
833 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
834 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
836 /* We don't have mod libcalls. Fortunately gcc knows how to use the
837 divmod libcalls instead. */
838 set_optab_libfunc (smod_optab
, DImode
, NULL
);
839 set_optab_libfunc (umod_optab
, DImode
, NULL
);
840 set_optab_libfunc (smod_optab
, SImode
, NULL
);
841 set_optab_libfunc (umod_optab
, SImode
, NULL
);
844 /* Implement TARGET_HANDLE_OPTION. */
847 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
852 arm_select
[1].string
= arg
;
856 arm_select
[0].string
= arg
;
859 case OPT_mhard_float
:
860 target_float_abi_name
= "hard";
863 case OPT_msoft_float
:
864 target_float_abi_name
= "soft";
868 arm_select
[2].string
= arg
;
876 /* Fix up any incompatible options that the user has specified.
877 This has now turned into a maze. */
879 arm_override_options (void)
882 enum processor_type target_arch_cpu
= arm_none
;
884 /* Set up the flags based on the cpu/architecture selected by the user. */
885 for (i
= ARRAY_SIZE (arm_select
); i
--;)
887 struct arm_cpu_select
* ptr
= arm_select
+ i
;
889 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
891 const struct processors
* sel
;
893 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
894 if (streq (ptr
->string
, sel
->name
))
896 /* Set the architecture define. */
897 if (i
!= ARM_OPT_SET_TUNE
)
898 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
900 /* Determine the processor core for which we should
901 tune code-generation. */
902 if (/* -mcpu= is a sensible default. */
904 /* -mtune= overrides -mcpu= and -march=. */
905 || i
== ARM_OPT_SET_TUNE
)
906 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
908 /* Remember the CPU associated with this architecture.
909 If no other option is used to set the CPU type,
910 we'll use this to guess the most suitable tuning
912 if (i
== ARM_OPT_SET_ARCH
)
913 target_arch_cpu
= sel
->core
;
915 if (i
!= ARM_OPT_SET_TUNE
)
917 /* If we have been given an architecture and a processor
918 make sure that they are compatible. We only generate
919 a warning though, and we prefer the CPU over the
921 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
922 warning (0, "switch -mcpu=%s conflicts with -march= switch",
925 insn_flags
= sel
->flags
;
931 if (sel
->name
== NULL
)
932 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
936 /* Guess the tuning options from the architecture if necessary. */
937 if (arm_tune
== arm_none
)
938 arm_tune
= target_arch_cpu
;
940 /* If the user did not specify a processor, choose one for them. */
943 const struct processors
* sel
;
945 enum processor_type cpu
;
947 cpu
= TARGET_CPU_DEFAULT
;
950 #ifdef SUBTARGET_CPU_DEFAULT
951 /* Use the subtarget default CPU if none was specified by
953 cpu
= SUBTARGET_CPU_DEFAULT
;
955 /* Default to ARM6. */
959 sel
= &all_cores
[cpu
];
961 insn_flags
= sel
->flags
;
963 /* Now check to see if the user has specified some command line
964 switch that require certain abilities from the cpu. */
967 if (TARGET_INTERWORK
|| TARGET_THUMB
)
969 sought
|= (FL_THUMB
| FL_MODE32
);
971 /* There are no ARM processors that support both APCS-26 and
972 interworking. Therefore we force FL_MODE26 to be removed
973 from insn_flags here (if it was set), so that the search
974 below will always be able to find a compatible processor. */
975 insn_flags
&= ~FL_MODE26
;
978 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
980 /* Try to locate a CPU type that supports all of the abilities
981 of the default CPU, plus the extra abilities requested by
983 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
984 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
987 if (sel
->name
== NULL
)
989 unsigned current_bit_count
= 0;
990 const struct processors
* best_fit
= NULL
;
992 /* Ideally we would like to issue an error message here
993 saying that it was not possible to find a CPU compatible
994 with the default CPU, but which also supports the command
995 line options specified by the programmer, and so they
996 ought to use the -mcpu=<name> command line option to
997 override the default CPU type.
999 If we cannot find a cpu that has both the
1000 characteristics of the default cpu and the given
1001 command line options we scan the array again looking
1002 for a best match. */
1003 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1004 if ((sel
->flags
& sought
) == sought
)
1008 count
= bit_count (sel
->flags
& insn_flags
);
1010 if (count
>= current_bit_count
)
1013 current_bit_count
= count
;
1017 gcc_assert (best_fit
);
1021 insn_flags
= sel
->flags
;
1023 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1024 if (arm_tune
== arm_none
)
1025 arm_tune
= (enum processor_type
) (sel
- all_cores
);
1028 /* The processor for which we should tune should now have been
1030 gcc_assert (arm_tune
!= arm_none
);
1032 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1034 targetm
.rtx_costs
= arm_size_rtx_costs
;
1036 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1038 /* Make sure that the processor choice does not conflict with any of the
1039 other command line choices. */
1040 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1042 warning (0, "target CPU does not support interworking" );
1043 target_flags
&= ~MASK_INTERWORK
;
1046 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1048 warning (0, "target CPU does not support THUMB instructions");
1049 target_flags
&= ~MASK_THUMB
;
1052 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1054 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1055 target_flags
&= ~MASK_APCS_FRAME
;
1058 /* Callee super interworking implies thumb interworking. Adding
1059 this to the flags here simplifies the logic elsewhere. */
1060 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1061 target_flags
|= MASK_INTERWORK
;
1063 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1064 from here where no function is being compiled currently. */
1065 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1066 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1068 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1069 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1071 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1072 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1074 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1076 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1077 target_flags
|= MASK_APCS_FRAME
;
1080 if (TARGET_POKE_FUNCTION_NAME
)
1081 target_flags
|= MASK_APCS_FRAME
;
1083 if (TARGET_APCS_REENT
&& flag_pic
)
1084 error ("-fpic and -mapcs-reent are incompatible");
1086 if (TARGET_APCS_REENT
)
1087 warning (0, "APCS reentrant code not supported. Ignored");
1089 /* If this target is normally configured to use APCS frames, warn if they
1090 are turned off and debugging is turned on. */
1092 && write_symbols
!= NO_DEBUG
1093 && !TARGET_APCS_FRAME
1094 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1095 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1097 /* If stack checking is disabled, we can use r10 as the PIC register,
1098 which keeps r9 available. */
1099 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
1100 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1102 if (TARGET_APCS_FLOAT
)
1103 warning (0, "passing floating point arguments in fp regs not yet supported");
1105 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1106 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1107 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1108 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1109 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1110 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1111 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1112 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1113 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1114 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1116 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1117 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1118 thumb_code
= (TARGET_ARM
== 0);
1119 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1120 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1121 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1123 /* V5 code we generate is completely interworking capable, so we turn off
1124 TARGET_INTERWORK here to avoid many tests later on. */
1126 /* XXX However, we must pass the right pre-processor defines to CPP
1127 or GLD can get confused. This is a hack. */
1128 if (TARGET_INTERWORK
)
1129 arm_cpp_interwork
= 1;
1132 target_flags
&= ~MASK_INTERWORK
;
1134 if (target_abi_name
)
1136 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1138 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1140 arm_abi
= arm_all_abis
[i
].abi_type
;
1144 if (i
== ARRAY_SIZE (arm_all_abis
))
1145 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1148 arm_abi
= ARM_DEFAULT_ABI
;
1150 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1151 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1153 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1154 error ("iwmmxt abi requires an iwmmxt capable cpu");
1156 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1157 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1159 if (streq (target_fpe_name
, "2"))
1160 target_fpu_name
= "fpe2";
1161 else if (streq (target_fpe_name
, "3"))
1162 target_fpu_name
= "fpe3";
1164 error ("invalid floating point emulation option: -mfpe=%s",
1167 if (target_fpu_name
!= NULL
)
1169 /* The user specified a FPU. */
1170 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1172 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1174 arm_fpu_arch
= all_fpus
[i
].fpu
;
1175 arm_fpu_tune
= arm_fpu_arch
;
1176 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1180 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1181 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1185 #ifdef FPUTYPE_DEFAULT
1186 /* Use the default if it is specified for this platform. */
1187 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1188 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1190 /* Pick one based on CPU type. */
1191 /* ??? Some targets assume FPA is the default.
1192 if ((insn_flags & FL_VFP) != 0)
1193 arm_fpu_arch = FPUTYPE_VFP;
1196 if (arm_arch_cirrus
)
1197 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1199 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1201 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1202 arm_fpu_tune
= FPUTYPE_FPA
;
1204 arm_fpu_tune
= arm_fpu_arch
;
1205 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1206 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1209 if (target_float_abi_name
!= NULL
)
1211 /* The user specified a FP ABI. */
1212 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1214 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1216 arm_float_abi
= all_float_abis
[i
].abi_type
;
1220 if (i
== ARRAY_SIZE (all_float_abis
))
1221 error ("invalid floating point abi: -mfloat-abi=%s",
1222 target_float_abi_name
);
1225 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1227 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1228 sorry ("-mfloat-abi=hard and VFP");
1230 /* If soft-float is specified then don't use FPU. */
1231 if (TARGET_SOFT_FLOAT
)
1232 arm_fpu_arch
= FPUTYPE_NONE
;
1234 /* For arm2/3 there is no need to do any scheduling if there is only
1235 a floating point emulator, or we are doing software floating-point. */
1236 if ((TARGET_SOFT_FLOAT
1237 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1238 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1239 && (tune_flags
& FL_MODE32
) == 0)
1240 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1242 if (target_thread_switch
)
1244 if (strcmp (target_thread_switch
, "soft") == 0)
1245 target_thread_pointer
= TP_SOFT
;
1246 else if (strcmp (target_thread_switch
, "auto") == 0)
1247 target_thread_pointer
= TP_AUTO
;
1248 else if (strcmp (target_thread_switch
, "cp15") == 0)
1249 target_thread_pointer
= TP_CP15
;
1251 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1254 /* Use the cp15 method if it is available. */
1255 if (target_thread_pointer
== TP_AUTO
)
1257 if (arm_arch6k
&& !TARGET_THUMB
)
1258 target_thread_pointer
= TP_CP15
;
1260 target_thread_pointer
= TP_SOFT
;
1263 if (TARGET_HARD_TP
&& TARGET_THUMB
)
1264 error ("can not use -mtp=cp15 with -mthumb");
1266 /* Override the default structure alignment for AAPCS ABI. */
1267 if (TARGET_AAPCS_BASED
)
1268 arm_structure_size_boundary
= 8;
1270 if (structure_size_string
!= NULL
)
1272 int size
= strtol (structure_size_string
, NULL
, 0);
1274 if (size
== 8 || size
== 32
1275 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1276 arm_structure_size_boundary
= size
;
1278 warning (0, "structure size boundary can only be set to %s",
1279 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1282 if (arm_pic_register_string
!= NULL
)
1284 int pic_register
= decode_reg_name (arm_pic_register_string
);
1287 warning (0, "-mpic-register= is useless without -fpic");
1289 /* Prevent the user from choosing an obviously stupid PIC register. */
1290 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1291 || pic_register
== HARD_FRAME_POINTER_REGNUM
1292 || pic_register
== STACK_POINTER_REGNUM
1293 || pic_register
>= PC_REGNUM
)
1294 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1296 arm_pic_register
= pic_register
;
1299 if (TARGET_THUMB
&& flag_schedule_insns
)
1301 /* Don't warn since it's on by default in -O2. */
1302 flag_schedule_insns
= 0;
1307 arm_constant_limit
= 1;
1309 /* If optimizing for size, bump the number of instructions that we
1310 are prepared to conditionally execute (even on a StrongARM). */
1311 max_insns_skipped
= 6;
1315 /* For processors with load scheduling, it never costs more than
1316 2 cycles to load a constant, and the load scheduler may well
1317 reduce that to 1. */
1319 arm_constant_limit
= 1;
1321 /* On XScale the longer latency of a load makes it more difficult
1322 to achieve a good schedule, so it's faster to synthesize
1323 constants that can be done in two insns. */
1324 if (arm_tune_xscale
)
1325 arm_constant_limit
= 2;
1327 /* StrongARM has early execution of branches, so a sequence
1328 that is worth skipping is shorter. */
1329 if (arm_tune_strongarm
)
1330 max_insns_skipped
= 3;
1333 /* Register global variables with the garbage collector. */
1334 arm_add_gc_roots ();
1338 arm_add_gc_roots (void)
1340 gcc_obstack_init(&minipool_obstack
);
1341 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1344 /* A table of known ARM exception types.
1345 For use with the interrupt function attribute. */
1349 const char *const arg
;
1350 const unsigned long return_value
;
1354 static const isr_attribute_arg isr_attribute_args
[] =
1356 { "IRQ", ARM_FT_ISR
},
1357 { "irq", ARM_FT_ISR
},
1358 { "FIQ", ARM_FT_FIQ
},
1359 { "fiq", ARM_FT_FIQ
},
1360 { "ABORT", ARM_FT_ISR
},
1361 { "abort", ARM_FT_ISR
},
1362 { "ABORT", ARM_FT_ISR
},
1363 { "abort", ARM_FT_ISR
},
1364 { "UNDEF", ARM_FT_EXCEPTION
},
1365 { "undef", ARM_FT_EXCEPTION
},
1366 { "SWI", ARM_FT_EXCEPTION
},
1367 { "swi", ARM_FT_EXCEPTION
},
1368 { NULL
, ARM_FT_NORMAL
}
1371 /* Returns the (interrupt) function type of the current
1372 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1374 static unsigned long
1375 arm_isr_value (tree argument
)
1377 const isr_attribute_arg
* ptr
;
1380 /* No argument - default to IRQ. */
1381 if (argument
== NULL_TREE
)
1384 /* Get the value of the argument. */
1385 if (TREE_VALUE (argument
) == NULL_TREE
1386 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1387 return ARM_FT_UNKNOWN
;
1389 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1391 /* Check it against the list of known arguments. */
1392 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1393 if (streq (arg
, ptr
->arg
))
1394 return ptr
->return_value
;
1396 /* An unrecognized interrupt type. */
1397 return ARM_FT_UNKNOWN
;
1400 /* Computes the type of the current function. */
1402 static unsigned long
1403 arm_compute_func_type (void)
1405 unsigned long type
= ARM_FT_UNKNOWN
;
1409 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1411 /* Decide if the current function is volatile. Such functions
1412 never return, and many memory cycles can be saved by not storing
1413 register values that will never be needed again. This optimization
1414 was added to speed up context switching in a kernel application. */
1416 && TREE_NOTHROW (current_function_decl
)
1417 && TREE_THIS_VOLATILE (current_function_decl
))
1418 type
|= ARM_FT_VOLATILE
;
1420 if (cfun
->static_chain_decl
!= NULL
)
1421 type
|= ARM_FT_NESTED
;
1423 attr
= DECL_ATTRIBUTES (current_function_decl
);
1425 a
= lookup_attribute ("naked", attr
);
1427 type
|= ARM_FT_NAKED
;
1429 a
= lookup_attribute ("isr", attr
);
1431 a
= lookup_attribute ("interrupt", attr
);
1434 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1436 type
|= arm_isr_value (TREE_VALUE (a
));
1441 /* Returns the type of the current function. */
1444 arm_current_func_type (void)
1446 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1447 cfun
->machine
->func_type
= arm_compute_func_type ();
1449 return cfun
->machine
->func_type
;
1452 /* Return 1 if it is possible to return using a single instruction.
1453 If SIBLING is non-null, this is a test for a return before a sibling
1454 call. SIBLING is the call insn, so we can examine its register usage. */
1457 use_return_insn (int iscond
, rtx sibling
)
1460 unsigned int func_type
;
1461 unsigned long saved_int_regs
;
1462 unsigned HOST_WIDE_INT stack_adjust
;
1463 arm_stack_offsets
*offsets
;
1465 /* Never use a return instruction before reload has run. */
1466 if (!reload_completed
)
1469 func_type
= arm_current_func_type ();
1471 /* Naked functions and volatile functions need special
1473 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1476 /* So do interrupt functions that use the frame pointer. */
1477 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1480 offsets
= arm_get_frame_offsets ();
1481 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1483 /* As do variadic functions. */
1484 if (current_function_pretend_args_size
1485 || cfun
->machine
->uses_anonymous_args
1486 /* Or if the function calls __builtin_eh_return () */
1487 || current_function_calls_eh_return
1488 /* Or if the function calls alloca */
1489 || current_function_calls_alloca
1490 /* Or if there is a stack adjustment. However, if the stack pointer
1491 is saved on the stack, we can use a pre-incrementing stack load. */
1492 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1495 saved_int_regs
= arm_compute_save_reg_mask ();
1497 /* Unfortunately, the insn
1499 ldmib sp, {..., sp, ...}
1501 triggers a bug on most SA-110 based devices, such that the stack
1502 pointer won't be correctly restored if the instruction takes a
1503 page fault. We work around this problem by popping r3 along with
1504 the other registers, since that is never slower than executing
1505 another instruction.
1507 We test for !arm_arch5 here, because code for any architecture
1508 less than this could potentially be run on one of the buggy
1510 if (stack_adjust
== 4 && !arm_arch5
)
1512 /* Validate that r3 is a call-clobbered register (always true in
1513 the default abi) ... */
1514 if (!call_used_regs
[3])
1517 /* ... that it isn't being used for a return value ... */
1518 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1521 /* ... or for a tail-call argument ... */
1524 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1526 if (find_regno_fusage (sibling
, USE
, 3))
1530 /* ... and that there are no call-saved registers in r0-r2
1531 (always true in the default ABI). */
1532 if (saved_int_regs
& 0x7)
1536 /* Can't be done if interworking with Thumb, and any registers have been
1538 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1541 /* On StrongARM, conditional returns are expensive if they aren't
1542 taken and multiple registers have been stacked. */
1543 if (iscond
&& arm_tune_strongarm
)
1545 /* Conditional return when just the LR is stored is a simple
1546 conditional-load instruction, that's not expensive. */
1547 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1551 && arm_pic_register
!= INVALID_REGNUM
1552 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1556 /* If there are saved registers but the LR isn't saved, then we need
1557 two instructions for the return. */
1558 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1561 /* Can't be done if any of the FPA regs are pushed,
1562 since this also requires an insn. */
1563 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1564 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1565 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1568 /* Likewise VFP regs. */
1569 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1570 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1571 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1574 if (TARGET_REALLY_IWMMXT
)
1575 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1576 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1582 /* Return TRUE if int I is a valid immediate ARM constant. */
1585 const_ok_for_arm (HOST_WIDE_INT i
)
1589 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1590 be all zero, or all one. */
1591 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1592 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1593 != ((~(unsigned HOST_WIDE_INT
) 0)
1594 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1597 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1599 /* Fast return for 0 and small values. We must do this for zero, since
1600 the code below can't handle that one case. */
1601 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1604 /* Get the number of trailing zeros, rounded down to the nearest even
1606 lowbit
= (ffs ((int) i
) - 1) & ~1;
1608 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1610 else if (lowbit
<= 4
1611 && ((i
& ~0xc000003f) == 0
1612 || (i
& ~0xf000000f) == 0
1613 || (i
& ~0xfc000003) == 0))
1619 /* Return true if I is a valid constant for the operation CODE. */
1621 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1623 if (const_ok_for_arm (i
))
1629 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1631 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1637 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1644 /* Emit a sequence of insns to handle a large constant.
1645 CODE is the code of the operation required, it can be any of SET, PLUS,
1646 IOR, AND, XOR, MINUS;
1647 MODE is the mode in which the operation is being performed;
1648 VAL is the integer to operate on;
1649 SOURCE is the other operand (a register, or a null-pointer for SET);
1650 SUBTARGETS means it is safe to create scratch registers if that will
1651 either produce a simpler sequence, or we will want to cse the values.
1652 Return value is the number of insns emitted. */
1655 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1656 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1660 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1661 cond
= COND_EXEC_TEST (PATTERN (insn
));
1665 if (subtargets
|| code
== SET
1666 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1667 && REGNO (target
) != REGNO (source
)))
1669 /* After arm_reorg has been called, we can't fix up expensive
1670 constants by pushing them into memory so we must synthesize
1671 them in-line, regardless of the cost. This is only likely to
1672 be more costly on chips that have load delay slots and we are
1673 compiling without running the scheduler (so no splitting
1674 occurred before the final instruction emission).
1676 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1678 if (!after_arm_reorg
1680 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1682 > arm_constant_limit
+ (code
!= SET
)))
1686 /* Currently SET is the only monadic value for CODE, all
1687 the rest are diadic. */
1688 emit_set_insn (target
, GEN_INT (val
));
1693 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1695 emit_set_insn (temp
, GEN_INT (val
));
1696 /* For MINUS, the value is subtracted from, since we never
1697 have subtraction of a constant. */
1699 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
1701 emit_set_insn (target
,
1702 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
1708 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1713 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1715 HOST_WIDE_INT temp1
;
1723 if (remainder
& (3 << (i
- 2)))
1728 temp1
= remainder
& ((0x0ff << end
)
1729 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1730 remainder
&= ~temp1
;
1735 } while (remainder
);
1739 /* Emit an instruction with the indicated PATTERN. If COND is
1740 non-NULL, conditionalize the execution of the instruction on COND
1744 emit_constant_insn (rtx cond
, rtx pattern
)
1747 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1748 emit_insn (pattern
);
1751 /* As above, but extra parameter GENERATE which, if clear, suppresses
1755 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1756 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1761 int can_negate_initial
= 0;
1764 int num_bits_set
= 0;
1765 int set_sign_bit_copies
= 0;
1766 int clear_sign_bit_copies
= 0;
1767 int clear_zero_bit_copies
= 0;
1768 int set_zero_bit_copies
= 0;
1770 unsigned HOST_WIDE_INT temp1
, temp2
;
1771 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1773 /* Find out which operations are safe for a given CODE. Also do a quick
1774 check for degenerate cases; these can occur when DImode operations
1786 can_negate_initial
= 1;
1790 if (remainder
== 0xffffffff)
1793 emit_constant_insn (cond
,
1794 gen_rtx_SET (VOIDmode
, target
,
1795 GEN_INT (ARM_SIGN_EXTEND (val
))));
1800 if (reload_completed
&& rtx_equal_p (target
, source
))
1803 emit_constant_insn (cond
,
1804 gen_rtx_SET (VOIDmode
, target
, source
));
1813 emit_constant_insn (cond
,
1814 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1817 if (remainder
== 0xffffffff)
1819 if (reload_completed
&& rtx_equal_p (target
, source
))
1822 emit_constant_insn (cond
,
1823 gen_rtx_SET (VOIDmode
, target
, source
));
1832 if (reload_completed
&& rtx_equal_p (target
, source
))
1835 emit_constant_insn (cond
,
1836 gen_rtx_SET (VOIDmode
, target
, source
));
1840 /* We don't know how to handle other cases yet. */
1841 gcc_assert (remainder
== 0xffffffff);
1844 emit_constant_insn (cond
,
1845 gen_rtx_SET (VOIDmode
, target
,
1846 gen_rtx_NOT (mode
, source
)));
1850 /* We treat MINUS as (val - source), since (source - val) is always
1851 passed as (source + (-val)). */
1855 emit_constant_insn (cond
,
1856 gen_rtx_SET (VOIDmode
, target
,
1857 gen_rtx_NEG (mode
, source
)));
1860 if (const_ok_for_arm (val
))
1863 emit_constant_insn (cond
,
1864 gen_rtx_SET (VOIDmode
, target
,
1865 gen_rtx_MINUS (mode
, GEN_INT (val
),
1877 /* If we can do it in one insn get out quickly. */
1878 if (const_ok_for_arm (val
)
1879 || (can_negate_initial
&& const_ok_for_arm (-val
))
1880 || (can_invert
&& const_ok_for_arm (~val
)))
1883 emit_constant_insn (cond
,
1884 gen_rtx_SET (VOIDmode
, target
,
1886 ? gen_rtx_fmt_ee (code
, mode
, source
,
1892 /* Calculate a few attributes that may be useful for specific
1894 for (i
= 31; i
>= 0; i
--)
1896 if ((remainder
& (1 << i
)) == 0)
1897 clear_sign_bit_copies
++;
1902 for (i
= 31; i
>= 0; i
--)
1904 if ((remainder
& (1 << i
)) != 0)
1905 set_sign_bit_copies
++;
1910 for (i
= 0; i
<= 31; i
++)
1912 if ((remainder
& (1 << i
)) == 0)
1913 clear_zero_bit_copies
++;
1918 for (i
= 0; i
<= 31; i
++)
1920 if ((remainder
& (1 << i
)) != 0)
1921 set_zero_bit_copies
++;
1929 /* See if we can do this by sign_extending a constant that is known
1930 to be negative. This is a good, way of doing it, since the shift
1931 may well merge into a subsequent insn. */
1932 if (set_sign_bit_copies
> 1)
1934 if (const_ok_for_arm
1935 (temp1
= ARM_SIGN_EXTEND (remainder
1936 << (set_sign_bit_copies
- 1))))
1940 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1941 emit_constant_insn (cond
,
1942 gen_rtx_SET (VOIDmode
, new_src
,
1944 emit_constant_insn (cond
,
1945 gen_ashrsi3 (target
, new_src
,
1946 GEN_INT (set_sign_bit_copies
- 1)));
1950 /* For an inverted constant, we will need to set the low bits,
1951 these will be shifted out of harm's way. */
1952 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1953 if (const_ok_for_arm (~temp1
))
1957 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1958 emit_constant_insn (cond
,
1959 gen_rtx_SET (VOIDmode
, new_src
,
1961 emit_constant_insn (cond
,
1962 gen_ashrsi3 (target
, new_src
,
1963 GEN_INT (set_sign_bit_copies
- 1)));
1969 /* See if we can calculate the value as the difference between two
1970 valid immediates. */
1971 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1973 int topshift
= clear_sign_bit_copies
& ~1;
1975 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1976 & (0xff000000 >> topshift
));
1978 /* If temp1 is zero, then that means the 9 most significant
1979 bits of remainder were 1 and we've caused it to overflow.
1980 When topshift is 0 we don't need to do anything since we
1981 can borrow from 'bit 32'. */
1982 if (temp1
== 0 && topshift
!= 0)
1983 temp1
= 0x80000000 >> (topshift
- 1);
1985 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1987 if (const_ok_for_arm (temp2
))
1991 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1992 emit_constant_insn (cond
,
1993 gen_rtx_SET (VOIDmode
, new_src
,
1995 emit_constant_insn (cond
,
1996 gen_addsi3 (target
, new_src
,
2004 /* See if we can generate this by setting the bottom (or the top)
2005 16 bits, and then shifting these into the other half of the
2006 word. We only look for the simplest cases, to do more would cost
2007 too much. Be careful, however, not to generate this when the
2008 alternative would take fewer insns. */
2009 if (val
& 0xffff0000)
2011 temp1
= remainder
& 0xffff0000;
2012 temp2
= remainder
& 0x0000ffff;
2014 /* Overlaps outside this range are best done using other methods. */
2015 for (i
= 9; i
< 24; i
++)
2017 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2018 && !const_ok_for_arm (temp2
))
2020 rtx new_src
= (subtargets
2021 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2023 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2024 source
, subtargets
, generate
);
2032 gen_rtx_ASHIFT (mode
, source
,
2039 /* Don't duplicate cases already considered. */
2040 for (i
= 17; i
< 24; i
++)
2042 if (((temp1
| (temp1
>> i
)) == remainder
)
2043 && !const_ok_for_arm (temp1
))
2045 rtx new_src
= (subtargets
2046 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2048 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2049 source
, subtargets
, generate
);
2054 gen_rtx_SET (VOIDmode
, target
,
2057 gen_rtx_LSHIFTRT (mode
, source
,
2068 /* If we have IOR or XOR, and the constant can be loaded in a
2069 single instruction, and we can find a temporary to put it in,
2070 then this can be done in two instructions instead of 3-4. */
2072 /* TARGET can't be NULL if SUBTARGETS is 0 */
2073 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2075 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2079 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2081 emit_constant_insn (cond
,
2082 gen_rtx_SET (VOIDmode
, sub
,
2084 emit_constant_insn (cond
,
2085 gen_rtx_SET (VOIDmode
, target
,
2086 gen_rtx_fmt_ee (code
, mode
,
2096 if (set_sign_bit_copies
> 8
2097 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2101 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2102 rtx shift
= GEN_INT (set_sign_bit_copies
);
2106 gen_rtx_SET (VOIDmode
, sub
,
2108 gen_rtx_ASHIFT (mode
,
2113 gen_rtx_SET (VOIDmode
, target
,
2115 gen_rtx_LSHIFTRT (mode
, sub
,
2121 if (set_zero_bit_copies
> 8
2122 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2126 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2127 rtx shift
= GEN_INT (set_zero_bit_copies
);
2131 gen_rtx_SET (VOIDmode
, sub
,
2133 gen_rtx_LSHIFTRT (mode
,
2138 gen_rtx_SET (VOIDmode
, target
,
2140 gen_rtx_ASHIFT (mode
, sub
,
2146 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2150 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2151 emit_constant_insn (cond
,
2152 gen_rtx_SET (VOIDmode
, sub
,
2153 gen_rtx_NOT (mode
, source
)));
2156 sub
= gen_reg_rtx (mode
);
2157 emit_constant_insn (cond
,
2158 gen_rtx_SET (VOIDmode
, sub
,
2159 gen_rtx_AND (mode
, source
,
2161 emit_constant_insn (cond
,
2162 gen_rtx_SET (VOIDmode
, target
,
2163 gen_rtx_NOT (mode
, sub
)));
2170 /* See if two shifts will do 2 or more insn's worth of work. */
2171 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2173 HOST_WIDE_INT shift_mask
= ((0xffffffff
2174 << (32 - clear_sign_bit_copies
))
2177 if ((remainder
| shift_mask
) != 0xffffffff)
2181 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2182 insns
= arm_gen_constant (AND
, mode
, cond
,
2183 remainder
| shift_mask
,
2184 new_src
, source
, subtargets
, 1);
2189 rtx targ
= subtargets
? NULL_RTX
: target
;
2190 insns
= arm_gen_constant (AND
, mode
, cond
,
2191 remainder
| shift_mask
,
2192 targ
, source
, subtargets
, 0);
2198 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2199 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2201 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2202 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2208 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2210 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2212 if ((remainder
| shift_mask
) != 0xffffffff)
2216 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2218 insns
= arm_gen_constant (AND
, mode
, cond
,
2219 remainder
| shift_mask
,
2220 new_src
, source
, subtargets
, 1);
2225 rtx targ
= subtargets
? NULL_RTX
: target
;
2227 insns
= arm_gen_constant (AND
, mode
, cond
,
2228 remainder
| shift_mask
,
2229 targ
, source
, subtargets
, 0);
2235 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2236 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2238 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2239 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2251 for (i
= 0; i
< 32; i
++)
2252 if (remainder
& (1 << i
))
2255 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2256 remainder
= (~remainder
) & 0xffffffff;
2257 else if (code
== PLUS
&& num_bits_set
> 16)
2258 remainder
= (-remainder
) & 0xffffffff;
2265 /* Now try and find a way of doing the job in either two or three
2267 We start by looking for the largest block of zeros that are aligned on
2268 a 2-bit boundary, we then fill up the temps, wrapping around to the
2269 top of the word when we drop off the bottom.
2270 In the worst case this code should produce no more than four insns. */
2273 int best_consecutive_zeros
= 0;
2275 for (i
= 0; i
< 32; i
+= 2)
2277 int consecutive_zeros
= 0;
2279 if (!(remainder
& (3 << i
)))
2281 while ((i
< 32) && !(remainder
& (3 << i
)))
2283 consecutive_zeros
+= 2;
2286 if (consecutive_zeros
> best_consecutive_zeros
)
2288 best_consecutive_zeros
= consecutive_zeros
;
2289 best_start
= i
- consecutive_zeros
;
2295 /* So long as it won't require any more insns to do so, it's
2296 desirable to emit a small constant (in bits 0...9) in the last
2297 insn. This way there is more chance that it can be combined with
2298 a later addressing insn to form a pre-indexed load or store
2299 operation. Consider:
2301 *((volatile int *)0xe0000100) = 1;
2302 *((volatile int *)0xe0000110) = 2;
2304 We want this to wind up as:
2308 str rB, [rA, #0x100]
2310 str rB, [rA, #0x110]
2312 rather than having to synthesize both large constants from scratch.
2314 Therefore, we calculate how many insns would be required to emit
2315 the constant starting from `best_start', and also starting from
2316 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2317 yield a shorter sequence, we may as well use zero. */
2319 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2320 && (count_insns_for_constant (remainder
, 0) <=
2321 count_insns_for_constant (remainder
, best_start
)))
2324 /* Now start emitting the insns. */
2332 if (remainder
& (3 << (i
- 2)))
2337 temp1
= remainder
& ((0x0ff << end
)
2338 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2339 remainder
&= ~temp1
;
2343 rtx new_src
, temp1_rtx
;
2345 if (code
== SET
|| code
== MINUS
)
2347 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2348 if (can_invert
&& code
!= MINUS
)
2353 if (remainder
&& subtargets
)
2354 new_src
= gen_reg_rtx (mode
);
2359 else if (can_negate
)
2363 temp1
= trunc_int_for_mode (temp1
, mode
);
2364 temp1_rtx
= GEN_INT (temp1
);
2368 else if (code
== MINUS
)
2369 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2371 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2373 emit_constant_insn (cond
,
2374 gen_rtx_SET (VOIDmode
, new_src
,
2384 else if (code
== MINUS
)
2398 /* Canonicalize a comparison so that we are more likely to recognize it.
2399 This can be done for a few constant compares, where we can make the
2400 immediate value easier to load. */
2403 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2406 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2407 unsigned HOST_WIDE_INT maxval
;
2408 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2419 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2421 *op1
= GEN_INT (i
+ 1);
2422 return code
== GT
? GE
: LT
;
2429 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2431 *op1
= GEN_INT (i
- 1);
2432 return code
== GE
? GT
: LE
;
2438 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2439 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2441 *op1
= GEN_INT (i
+ 1);
2442 return code
== GTU
? GEU
: LTU
;
2449 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2451 *op1
= GEN_INT (i
- 1);
2452 return code
== GEU
? GTU
: LEU
;
2464 /* Define how to find the value returned by a function. */
2467 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2469 enum machine_mode mode
;
2470 int unsignedp ATTRIBUTE_UNUSED
;
2471 rtx r ATTRIBUTE_UNUSED
;
2473 mode
= TYPE_MODE (type
);
2474 /* Promote integer types. */
2475 if (INTEGRAL_TYPE_P (type
))
2476 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2478 /* Promotes small structs returned in a register to full-word size
2479 for big-endian AAPCS. */
2480 if (arm_return_in_msb (type
))
2482 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2483 if (size
% UNITS_PER_WORD
!= 0)
2485 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2486 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2490 return LIBCALL_VALUE(mode
);
2493 /* Determine the amount of memory needed to store the possible return
2494 registers of an untyped call. */
2496 arm_apply_result_size (void)
2502 if (TARGET_HARD_FLOAT_ABI
)
2506 if (TARGET_MAVERICK
)
2509 if (TARGET_IWMMXT_ABI
)
2516 /* Decide whether a type should be returned in memory (true)
2517 or in a register (false). This is called by the macro
2518 RETURN_IN_MEMORY. */
2520 arm_return_in_memory (tree type
)
2524 if (!AGGREGATE_TYPE_P (type
) &&
2525 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2526 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2527 /* All simple types are returned in registers.
2528 For AAPCS, complex types are treated the same as aggregates. */
2531 size
= int_size_in_bytes (type
);
2533 if (arm_abi
!= ARM_ABI_APCS
)
2535 /* ATPCS and later return aggregate types in memory only if they are
2536 larger than a word (or are variable size). */
2537 return (size
< 0 || size
> UNITS_PER_WORD
);
2540 /* To maximize backwards compatibility with previous versions of gcc,
2541 return vectors up to 4 words in registers. */
2542 if (TREE_CODE (type
) == VECTOR_TYPE
)
2543 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2545 /* For the arm-wince targets we choose to be compatible with Microsoft's
2546 ARM and Thumb compilers, which always return aggregates in memory. */
2548 /* All structures/unions bigger than one word are returned in memory.
2549 Also catch the case where int_size_in_bytes returns -1. In this case
2550 the aggregate is either huge or of variable size, and in either case
2551 we will want to return it via memory and not in a register. */
2552 if (size
< 0 || size
> UNITS_PER_WORD
)
2555 if (TREE_CODE (type
) == RECORD_TYPE
)
2559 /* For a struct the APCS says that we only return in a register
2560 if the type is 'integer like' and every addressable element
2561 has an offset of zero. For practical purposes this means
2562 that the structure can have at most one non bit-field element
2563 and that this element must be the first one in the structure. */
2565 /* Find the first field, ignoring non FIELD_DECL things which will
2566 have been created by C++. */
2567 for (field
= TYPE_FIELDS (type
);
2568 field
&& TREE_CODE (field
) != FIELD_DECL
;
2569 field
= TREE_CHAIN (field
))
2573 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2575 /* Check that the first field is valid for returning in a register. */
2577 /* ... Floats are not allowed */
2578 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2581 /* ... Aggregates that are not themselves valid for returning in
2582 a register are not allowed. */
2583 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2586 /* Now check the remaining fields, if any. Only bitfields are allowed,
2587 since they are not addressable. */
2588 for (field
= TREE_CHAIN (field
);
2590 field
= TREE_CHAIN (field
))
2592 if (TREE_CODE (field
) != FIELD_DECL
)
2595 if (!DECL_BIT_FIELD_TYPE (field
))
2602 if (TREE_CODE (type
) == UNION_TYPE
)
2606 /* Unions can be returned in registers if every element is
2607 integral, or can be returned in an integer register. */
2608 for (field
= TYPE_FIELDS (type
);
2610 field
= TREE_CHAIN (field
))
2612 if (TREE_CODE (field
) != FIELD_DECL
)
2615 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2618 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2624 #endif /* not ARM_WINCE */
2626 /* Return all other types in memory. */
2630 /* Indicate whether or not words of a double are in big-endian order. */
2633 arm_float_words_big_endian (void)
2635 if (TARGET_MAVERICK
)
2638 /* For FPA, float words are always big-endian. For VFP, floats words
2639 follow the memory system mode. */
2647 return (TARGET_BIG_END
? 1 : 0);
2652 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2653 for a call to a function whose data type is FNTYPE.
2654 For a library call, FNTYPE is NULL. */
2656 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2657 rtx libname ATTRIBUTE_UNUSED
,
2658 tree fndecl ATTRIBUTE_UNUSED
)
2660 /* On the ARM, the offset starts at 0. */
2661 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2662 pcum
->iwmmxt_nregs
= 0;
2663 pcum
->can_split
= true;
2665 pcum
->call_cookie
= CALL_NORMAL
;
2667 if (TARGET_LONG_CALLS
)
2668 pcum
->call_cookie
= CALL_LONG
;
2670 /* Check for long call/short call attributes. The attributes
2671 override any command line option. */
2674 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2675 pcum
->call_cookie
= CALL_SHORT
;
2676 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2677 pcum
->call_cookie
= CALL_LONG
;
2680 /* Varargs vectors are treated the same as long long.
2681 named_count avoids having to change the way arm handles 'named' */
2682 pcum
->named_count
= 0;
2685 if (TARGET_REALLY_IWMMXT
&& fntype
)
2689 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2691 fn_arg
= TREE_CHAIN (fn_arg
))
2692 pcum
->named_count
+= 1;
2694 if (! pcum
->named_count
)
2695 pcum
->named_count
= INT_MAX
;
2700 /* Return true if mode/type need doubleword alignment. */
2702 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2704 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2705 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2709 /* Determine where to put an argument to a function.
2710 Value is zero to push the argument on the stack,
2711 or a hard register in which to store the argument.
2713 MODE is the argument's machine mode.
2714 TYPE is the data type of the argument (as a tree).
2715 This is null for libcalls where that information may
2717 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2718 the preceding args and about the function being called.
2719 NAMED is nonzero if this argument is a named parameter
2720 (otherwise it is an extra parameter matching an ellipsis). */
2723 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2724 tree type
, int named
)
2728 /* Varargs vectors are treated the same as long long.
2729 named_count avoids having to change the way arm handles 'named' */
2730 if (TARGET_IWMMXT_ABI
2731 && arm_vector_mode_supported_p (mode
)
2732 && pcum
->named_count
> pcum
->nargs
+ 1)
2734 if (pcum
->iwmmxt_nregs
<= 9)
2735 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2738 pcum
->can_split
= false;
2743 /* Put doubleword aligned quantities in even register pairs. */
2745 && ARM_DOUBLEWORD_ALIGN
2746 && arm_needs_doubleword_align (mode
, type
))
2749 if (mode
== VOIDmode
)
2750 /* Compute operand 2 of the call insn. */
2751 return GEN_INT (pcum
->call_cookie
);
2753 /* Only allow splitting an arg between regs and memory if all preceding
2754 args were allocated to regs. For args passed by reference we only count
2755 the reference pointer. */
2756 if (pcum
->can_split
)
2759 nregs
= ARM_NUM_REGS2 (mode
, type
);
2761 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2764 return gen_rtx_REG (mode
, pcum
->nregs
);
2768 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2769 tree type
, bool named ATTRIBUTE_UNUSED
)
2771 int nregs
= pcum
->nregs
;
2773 if (arm_vector_mode_supported_p (mode
))
2776 if (NUM_ARG_REGS
> nregs
2777 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2779 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2784 /* Variable sized types are passed by reference. This is a GCC
2785 extension to the ARM ABI. */
2788 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2789 enum machine_mode mode ATTRIBUTE_UNUSED
,
2790 tree type
, bool named ATTRIBUTE_UNUSED
)
2792 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2795 /* Encode the current state of the #pragma [no_]long_calls. */
2798 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2799 LONG
, /* #pragma long_calls is in effect. */
2800 SHORT
/* #pragma no_long_calls is in effect. */
2803 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2806 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2808 arm_pragma_long_calls
= LONG
;
2812 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2814 arm_pragma_long_calls
= SHORT
;
2818 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2820 arm_pragma_long_calls
= OFF
;
2823 /* Table of machine attributes. */
2824 const struct attribute_spec arm_attribute_table
[] =
2826 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2827 /* Function calls made to this symbol must be done indirectly, because
2828 it may lie outside of the 26 bit addressing range of a normal function
2830 { "long_call", 0, 0, false, true, true, NULL
},
2831 /* Whereas these functions are always known to reside within the 26 bit
2832 addressing range. */
2833 { "short_call", 0, 0, false, true, true, NULL
},
2834 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2835 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2836 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2837 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2839 /* ARM/PE has three new attributes:
2841 dllexport - for exporting a function/variable that will live in a dll
2842 dllimport - for importing a function/variable from a dll
2844 Microsoft allows multiple declspecs in one __declspec, separating
2845 them with spaces. We do NOT support this. Instead, use __declspec
2848 { "dllimport", 0, 0, true, false, false, NULL
},
2849 { "dllexport", 0, 0, true, false, false, NULL
},
2850 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2851 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2852 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2853 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2854 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2856 { NULL
, 0, 0, false, false, false, NULL
}
2859 /* Handle an attribute requiring a FUNCTION_DECL;
2860 arguments as in struct attribute_spec.handler. */
2862 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2863 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2865 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2867 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2868 IDENTIFIER_POINTER (name
));
2869 *no_add_attrs
= true;
2875 /* Handle an "interrupt" or "isr" attribute;
2876 arguments as in struct attribute_spec.handler. */
2878 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2883 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2885 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2886 IDENTIFIER_POINTER (name
));
2887 *no_add_attrs
= true;
2889 /* FIXME: the argument if any is checked for type attributes;
2890 should it be checked for decl ones? */
2894 if (TREE_CODE (*node
) == FUNCTION_TYPE
2895 || TREE_CODE (*node
) == METHOD_TYPE
)
2897 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2899 warning (OPT_Wattributes
, "%qs attribute ignored",
2900 IDENTIFIER_POINTER (name
));
2901 *no_add_attrs
= true;
2904 else if (TREE_CODE (*node
) == POINTER_TYPE
2905 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2906 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2907 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2909 *node
= build_variant_type_copy (*node
);
2910 TREE_TYPE (*node
) = build_type_attribute_variant
2912 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2913 *no_add_attrs
= true;
2917 /* Possibly pass this attribute on from the type to a decl. */
2918 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2919 | (int) ATTR_FLAG_FUNCTION_NEXT
2920 | (int) ATTR_FLAG_ARRAY_NEXT
))
2922 *no_add_attrs
= true;
2923 return tree_cons (name
, args
, NULL_TREE
);
2927 warning (OPT_Wattributes
, "%qs attribute ignored",
2928 IDENTIFIER_POINTER (name
));
2936 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2937 /* Handle the "notshared" attribute. This attribute is another way of
2938 requesting hidden visibility. ARM's compiler supports
2939 "__declspec(notshared)"; we support the same thing via an
2943 arm_handle_notshared_attribute (tree
*node
,
2944 tree name ATTRIBUTE_UNUSED
,
2945 tree args ATTRIBUTE_UNUSED
,
2946 int flags ATTRIBUTE_UNUSED
,
2949 tree decl
= TYPE_NAME (*node
);
2953 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2954 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2955 *no_add_attrs
= false;
2961 /* Return 0 if the attributes for two types are incompatible, 1 if they
2962 are compatible, and 2 if they are nearly compatible (which causes a
2963 warning to be generated). */
2965 arm_comp_type_attributes (tree type1
, tree type2
)
2969 /* Check for mismatch of non-default calling convention. */
2970 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2973 /* Check for mismatched call attributes. */
2974 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2975 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2976 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2977 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2979 /* Only bother to check if an attribute is defined. */
2980 if (l1
| l2
| s1
| s2
)
2982 /* If one type has an attribute, the other must have the same attribute. */
2983 if ((l1
!= l2
) || (s1
!= s2
))
2986 /* Disallow mixed attributes. */
2987 if ((l1
& s2
) || (l2
& s1
))
2991 /* Check for mismatched ISR attribute. */
2992 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2994 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2995 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2997 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
3004 /* Encode long_call or short_call attribute by prefixing
3005 symbol name in DECL with a special character FLAG. */
3007 arm_encode_call_attribute (tree decl
, int flag
)
3009 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
3010 int len
= strlen (str
);
3013 /* Do not allow weak functions to be treated as short call. */
3014 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3017 newstr
= alloca (len
+ 2);
3019 strcpy (newstr
+ 1, str
);
3021 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3022 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3025 /* Assigns default attributes to newly defined type. This is used to
3026 set short_call/long_call attributes for function types of
3027 functions defined inside corresponding #pragma scopes. */
3029 arm_set_default_type_attributes (tree type
)
3031 /* Add __attribute__ ((long_call)) to all functions, when
3032 inside #pragma long_calls or __attribute__ ((short_call)),
3033 when inside #pragma no_long_calls. */
3034 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3036 tree type_attr_list
, attr_name
;
3037 type_attr_list
= TYPE_ATTRIBUTES (type
);
3039 if (arm_pragma_long_calls
== LONG
)
3040 attr_name
= get_identifier ("long_call");
3041 else if (arm_pragma_long_calls
== SHORT
)
3042 attr_name
= get_identifier ("short_call");
3046 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3047 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3051 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3052 defined within the current compilation unit. If this cannot be
3053 determined, then 0 is returned. */
3055 current_file_function_operand (rtx sym_ref
)
3057 /* This is a bit of a fib. A function will have a short call flag
3058 applied to its name if it has the short call attribute, or it has
3059 already been defined within the current compilation unit. */
3060 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3063 /* The current function is always defined within the current compilation
3064 unit. If it s a weak definition however, then this may not be the real
3065 definition of the function, and so we have to say no. */
3066 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3067 && !DECL_WEAK (current_function_decl
))
3070 /* We cannot make the determination - default to returning 0. */
3074 /* Return nonzero if a 32 bit "long_call" should be generated for
3075 this call. We generate a long_call if the function:
3077 a. has an __attribute__((long call))
3078 or b. is within the scope of a #pragma long_calls
3079 or c. the -mlong-calls command line switch has been specified
3081 1. -ffunction-sections is in effect
3082 or 2. the current function has __attribute__ ((section))
3083 or 3. the target function has __attribute__ ((section))
3085 However we do not generate a long call if the function:
3087 d. has an __attribute__ ((short_call))
3088 or e. is inside the scope of a #pragma no_long_calls
3089 or f. is defined within the current compilation unit.
3091 This function will be called by C fragments contained in the machine
3092 description file. SYM_REF and CALL_COOKIE correspond to the matched
3093 rtl operands. CALL_SYMBOL is used to distinguish between
3094 two different callers of the function. It is set to 1 in the
3095 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3096 and "call_value" patterns. This is because of the difference in the
3097 SYM_REFs passed by these patterns. */
3099 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3103 if (GET_CODE (sym_ref
) != MEM
)
3106 sym_ref
= XEXP (sym_ref
, 0);
3109 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3112 if (call_cookie
& CALL_SHORT
)
3115 if (TARGET_LONG_CALLS
)
3117 if (flag_function_sections
3118 || DECL_SECTION_NAME (current_function_decl
))
3119 /* c.3 is handled by the definition of the
3120 ARM_DECLARE_FUNCTION_SIZE macro. */
3124 if (current_file_function_operand (sym_ref
))
3127 return (call_cookie
& CALL_LONG
)
3128 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3129 || TARGET_LONG_CALLS
;
3132 /* Return nonzero if it is ok to make a tail-call to DECL. */
3134 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3136 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3138 if (cfun
->machine
->sibcall_blocked
)
3141 /* Never tailcall something for which we have no decl, or if we
3142 are in Thumb mode. */
3143 if (decl
== NULL
|| TARGET_THUMB
)
3146 /* Get the calling method. */
3147 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3148 call_type
= CALL_SHORT
;
3149 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3150 call_type
= CALL_LONG
;
3152 /* Cannot tail-call to long calls, since these are out of range of
3153 a branch instruction. However, if not compiling PIC, we know
3154 we can reach the symbol if it is in this compilation unit. */
3155 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3158 /* If we are interworking and the function is not declared static
3159 then we can't tail-call it unless we know that it exists in this
3160 compilation unit (since it might be a Thumb routine). */
3161 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3164 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3165 if (IS_INTERRUPT (arm_current_func_type ()))
3168 /* Everything else is ok. */
3173 /* Addressing mode support functions. */
3175 /* Return nonzero if X is a legitimate immediate operand when compiling
3176 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3178 legitimate_pic_operand_p (rtx x
)
3180 if (GET_CODE (x
) == SYMBOL_REF
3181 || (GET_CODE (x
) == CONST
3182 && GET_CODE (XEXP (x
, 0)) == PLUS
3183 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3190 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3192 if (GET_CODE (orig
) == SYMBOL_REF
3193 || GET_CODE (orig
) == LABEL_REF
)
3195 #ifndef AOF_ASSEMBLER
3196 rtx pic_ref
, address
;
3201 /* If this function doesn't have a pic register, create one now.
3202 A lot of the logic here is made obscure by the fact that this
3203 routine gets called as part of the rtx cost estimation
3204 process. We don't want those calls to affect any assumptions
3205 about the real function; and further, we can't call
3206 entry_of_function() until we start the real expansion
3208 if (!current_function_uses_pic_offset_table
)
3210 gcc_assert (!no_new_pseudos
);
3211 if (arm_pic_register
!= INVALID_REGNUM
)
3213 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
3215 /* Play games to avoid marking the function as needing pic
3216 if we are being called as part of the cost-estimation
3219 current_function_uses_pic_offset_table
= 1;
3225 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
3227 /* Play games to avoid marking the function as needing pic
3228 if we are being called as part of the cost-estimation
3232 current_function_uses_pic_offset_table
= 1;
3235 arm_load_pic_register (0UL);
3239 emit_insn_after (seq
, entry_of_function ());
3246 gcc_assert (!no_new_pseudos
);
3247 reg
= gen_reg_rtx (Pmode
);
3252 #ifdef AOF_ASSEMBLER
3253 /* The AOF assembler can generate relocations for these directly, and
3254 understands that the PIC register has to be added into the offset. */
3255 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3258 address
= gen_reg_rtx (Pmode
);
3263 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3265 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3267 if ((GET_CODE (orig
) == LABEL_REF
3268 || (GET_CODE (orig
) == SYMBOL_REF
&&
3269 SYMBOL_REF_LOCAL_P (orig
)))
3271 pic_ref
= gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
, address
);
3274 pic_ref
= gen_const_mem (Pmode
,
3275 gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
,
3279 insn
= emit_move_insn (reg
, pic_ref
);
3281 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3283 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3287 else if (GET_CODE (orig
) == CONST
)
3291 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3292 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
3295 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3296 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3301 gcc_assert (!no_new_pseudos
);
3302 reg
= gen_reg_rtx (Pmode
);
3305 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3307 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3308 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3309 base
== reg
? 0 : reg
);
3311 if (GET_CODE (offset
) == CONST_INT
)
3313 /* The base register doesn't really matter, we only want to
3314 test the index for the appropriate mode. */
3315 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3317 gcc_assert (!no_new_pseudos
);
3318 offset
= force_reg (Pmode
, offset
);
3321 if (GET_CODE (offset
) == CONST_INT
)
3322 return plus_constant (base
, INTVAL (offset
));
3325 if (GET_MODE_SIZE (mode
) > 4
3326 && (GET_MODE_CLASS (mode
) == MODE_INT
3327 || TARGET_SOFT_FLOAT
))
3329 emit_insn (gen_addsi3 (reg
, base
, offset
));
3333 return gen_rtx_PLUS (Pmode
, base
, offset
);
3340 /* Find a spare low register to use during the prolog of a function. */
3343 thumb_find_work_register (unsigned long pushed_regs_mask
)
3347 /* Check the argument registers first as these are call-used. The
3348 register allocation order means that sometimes r3 might be used
3349 but earlier argument registers might not, so check them all. */
3350 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3351 if (!regs_ever_live
[reg
])
3354 /* Before going on to check the call-saved registers we can try a couple
3355 more ways of deducing that r3 is available. The first is when we are
3356 pushing anonymous arguments onto the stack and we have less than 4
3357 registers worth of fixed arguments(*). In this case r3 will be part of
3358 the variable argument list and so we can be sure that it will be
3359 pushed right at the start of the function. Hence it will be available
3360 for the rest of the prologue.
3361 (*): ie current_function_pretend_args_size is greater than 0. */
3362 if (cfun
->machine
->uses_anonymous_args
3363 && current_function_pretend_args_size
> 0)
3364 return LAST_ARG_REGNUM
;
3366 /* The other case is when we have fixed arguments but less than 4 registers
3367 worth. In this case r3 might be used in the body of the function, but
3368 it is not being used to convey an argument into the function. In theory
3369 we could just check current_function_args_size to see how many bytes are
3370 being passed in argument registers, but it seems that it is unreliable.
3371 Sometimes it will have the value 0 when in fact arguments are being
3372 passed. (See testcase execute/20021111-1.c for an example). So we also
3373 check the args_info.nregs field as well. The problem with this field is
3374 that it makes no allowances for arguments that are passed to the
3375 function but which are not used. Hence we could miss an opportunity
3376 when a function has an unused argument in r3. But it is better to be
3377 safe than to be sorry. */
3378 if (! cfun
->machine
->uses_anonymous_args
3379 && current_function_args_size
>= 0
3380 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3381 && cfun
->args_info
.nregs
< 4)
3382 return LAST_ARG_REGNUM
;
3384 /* Otherwise look for a call-saved register that is going to be pushed. */
3385 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3386 if (pushed_regs_mask
& (1 << reg
))
3389 /* Something went wrong - thumb_compute_save_reg_mask()
3390 should have arranged for a suitable register to be pushed. */
3394 static GTY(()) int pic_labelno
;
3396 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3400 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3402 #ifndef AOF_ASSEMBLER
3403 rtx l1
, labelno
, pic_tmp
, pic_tmp2
, pic_rtx
;
3404 rtx global_offset_table
;
3406 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3409 gcc_assert (flag_pic
);
3411 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3412 in the code stream. */
3414 labelno
= GEN_INT (pic_labelno
++);
3415 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3416 l1
= gen_rtx_CONST (VOIDmode
, l1
);
3418 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3419 /* On the ARM the PC register contains 'dot + 8' at the time of the
3420 addition, on the Thumb it is 'dot + 4'. */
3421 pic_tmp
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
3423 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3424 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3426 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3428 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3432 emit_insn (gen_pic_load_addr_arm (cfun
->machine
->pic_reg
, pic_rtx
));
3433 emit_insn (gen_pic_add_dot_plus_eight (cfun
->machine
->pic_reg
,
3434 cfun
->machine
->pic_reg
, labelno
));
3438 if (arm_pic_register
!= INVALID_REGNUM
3439 && REGNO (cfun
->machine
->pic_reg
) > LAST_LO_REGNUM
)
3441 /* We will have pushed the pic register, so we should always be
3442 able to find a work register. */
3443 pic_tmp
= gen_rtx_REG (SImode
,
3444 thumb_find_work_register (saved_regs
));
3445 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3446 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3449 emit_insn (gen_pic_load_addr_thumb (cfun
->machine
->pic_reg
, pic_rtx
));
3450 emit_insn (gen_pic_add_dot_plus_four (cfun
->machine
->pic_reg
,
3451 cfun
->machine
->pic_reg
, labelno
));
3454 /* Need to emit this whether or not we obey regdecls,
3455 since setjmp/longjmp can cause life info to screw up. */
3456 emit_insn (gen_rtx_USE (VOIDmode
, cfun
->machine
->pic_reg
));
3457 #endif /* AOF_ASSEMBLER */
3461 /* Return nonzero if X is valid as an ARM state addressing register. */
3463 arm_address_register_rtx_p (rtx x
, int strict_p
)
3467 if (GET_CODE (x
) != REG
)
3473 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3475 return (regno
<= LAST_ARM_REGNUM
3476 || regno
>= FIRST_PSEUDO_REGISTER
3477 || regno
== FRAME_POINTER_REGNUM
3478 || regno
== ARG_POINTER_REGNUM
);
3481 /* Return TRUE if this rtx is the difference of a symbol and a label,
3482 and will reduce to a PC-relative relocation in the object file.
3483 Expressions like this can be left alone when generating PIC, rather
3484 than forced through the GOT. */
3486 pcrel_constant_p (rtx x
)
3488 if (GET_CODE (x
) == MINUS
)
3489 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3494 /* Return nonzero if X is a valid ARM state address operand. */
3496 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3500 enum rtx_code code
= GET_CODE (x
);
3502 if (arm_address_register_rtx_p (x
, strict_p
))
3505 use_ldrd
= (TARGET_LDRD
3507 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3509 if (code
== POST_INC
|| code
== PRE_DEC
3510 || ((code
== PRE_INC
|| code
== POST_DEC
)
3511 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3512 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3514 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3515 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3516 && GET_CODE (XEXP (x
, 1)) == PLUS
3517 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3519 rtx addend
= XEXP (XEXP (x
, 1), 1);
3521 /* Don't allow ldrd post increment by register because it's hard
3522 to fixup invalid register choices. */
3524 && GET_CODE (x
) == POST_MODIFY
3525 && GET_CODE (addend
) == REG
)
3528 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3529 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3532 /* After reload constants split into minipools will have addresses
3533 from a LABEL_REF. */
3534 else if (reload_completed
3535 && (code
== LABEL_REF
3537 && GET_CODE (XEXP (x
, 0)) == PLUS
3538 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3539 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3542 else if (mode
== TImode
)
3545 else if (code
== PLUS
)
3547 rtx xop0
= XEXP (x
, 0);
3548 rtx xop1
= XEXP (x
, 1);
3550 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3551 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3552 || (arm_address_register_rtx_p (xop1
, strict_p
)
3553 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3557 /* Reload currently can't handle MINUS, so disable this for now */
3558 else if (GET_CODE (x
) == MINUS
)
3560 rtx xop0
= XEXP (x
, 0);
3561 rtx xop1
= XEXP (x
, 1);
3563 return (arm_address_register_rtx_p (xop0
, strict_p
)
3564 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3568 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3569 && code
== SYMBOL_REF
3570 && CONSTANT_POOL_ADDRESS_P (x
)
3572 && symbol_mentioned_p (get_pool_constant (x
))
3573 && ! pcrel_constant_p (get_pool_constant (x
))))
3579 /* Return nonzero if INDEX is valid for an address index operand in
3582 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3585 HOST_WIDE_INT range
;
3586 enum rtx_code code
= GET_CODE (index
);
3588 /* Standard coprocessor addressing modes. */
3589 if (TARGET_HARD_FLOAT
3590 && (TARGET_FPA
|| TARGET_MAVERICK
)
3591 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3592 || (TARGET_MAVERICK
&& mode
== DImode
)))
3593 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3594 && INTVAL (index
) > -1024
3595 && (INTVAL (index
) & 3) == 0);
3597 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3598 return (code
== CONST_INT
3599 && INTVAL (index
) < 1024
3600 && INTVAL (index
) > -1024
3601 && (INTVAL (index
) & 3) == 0);
3603 if (arm_address_register_rtx_p (index
, strict_p
)
3604 && (GET_MODE_SIZE (mode
) <= 4))
3607 if (mode
== DImode
|| mode
== DFmode
)
3609 if (code
== CONST_INT
)
3611 HOST_WIDE_INT val
= INTVAL (index
);
3614 return val
> -256 && val
< 256;
3616 return val
> -4096 && val
< 4092;
3619 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3622 if (GET_MODE_SIZE (mode
) <= 4
3625 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3629 rtx xiop0
= XEXP (index
, 0);
3630 rtx xiop1
= XEXP (index
, 1);
3632 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3633 && power_of_two_operand (xiop1
, SImode
))
3634 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3635 && power_of_two_operand (xiop0
, SImode
)));
3637 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3638 || code
== ASHIFT
|| code
== ROTATERT
)
3640 rtx op
= XEXP (index
, 1);
3642 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3643 && GET_CODE (op
) == CONST_INT
3645 && INTVAL (op
) <= 31);
3649 /* For ARM v4 we may be doing a sign-extend operation during the
3653 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3659 range
= (mode
== HImode
) ? 4095 : 4096;
3661 return (code
== CONST_INT
3662 && INTVAL (index
) < range
3663 && INTVAL (index
) > -range
);
3666 /* Return nonzero if X is valid as a Thumb state base register. */
3668 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3672 if (GET_CODE (x
) != REG
)
3678 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3680 return (regno
<= LAST_LO_REGNUM
3681 || regno
> LAST_VIRTUAL_REGISTER
3682 || regno
== FRAME_POINTER_REGNUM
3683 || (GET_MODE_SIZE (mode
) >= 4
3684 && (regno
== STACK_POINTER_REGNUM
3685 || regno
>= FIRST_PSEUDO_REGISTER
3686 || x
== hard_frame_pointer_rtx
3687 || x
== arg_pointer_rtx
)));
3690 /* Return nonzero if x is a legitimate index register. This is the case
3691 for any base register that can access a QImode object. */
3693 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3695 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3698 /* Return nonzero if x is a legitimate Thumb-state address.
3700 The AP may be eliminated to either the SP or the FP, so we use the
3701 least common denominator, e.g. SImode, and offsets from 0 to 64.
3703 ??? Verify whether the above is the right approach.
3705 ??? Also, the FP may be eliminated to the SP, so perhaps that
3706 needs special handling also.
3708 ??? Look at how the mips16 port solves this problem. It probably uses
3709 better ways to solve some of these problems.
3711 Although it is not incorrect, we don't accept QImode and HImode
3712 addresses based on the frame pointer or arg pointer until the
3713 reload pass starts. This is so that eliminating such addresses
3714 into stack based ones won't produce impossible code. */
3716 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3718 /* ??? Not clear if this is right. Experiment. */
3719 if (GET_MODE_SIZE (mode
) < 4
3720 && !(reload_in_progress
|| reload_completed
)
3721 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3722 || reg_mentioned_p (arg_pointer_rtx
, x
)
3723 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3724 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3725 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3726 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3729 /* Accept any base register. SP only in SImode or larger. */
3730 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3733 /* This is PC relative data before arm_reorg runs. */
3734 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3735 && GET_CODE (x
) == SYMBOL_REF
3736 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
3739 /* This is PC relative data after arm_reorg runs. */
3740 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3741 && (GET_CODE (x
) == LABEL_REF
3742 || (GET_CODE (x
) == CONST
3743 && GET_CODE (XEXP (x
, 0)) == PLUS
3744 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3745 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3748 /* Post-inc indexing only supported for SImode and larger. */
3749 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3750 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3753 else if (GET_CODE (x
) == PLUS
)
3755 /* REG+REG address can be any two index registers. */
3756 /* We disallow FRAME+REG addressing since we know that FRAME
3757 will be replaced with STACK, and SP relative addressing only
3758 permits SP+OFFSET. */
3759 if (GET_MODE_SIZE (mode
) <= 4
3760 && XEXP (x
, 0) != frame_pointer_rtx
3761 && XEXP (x
, 1) != frame_pointer_rtx
3762 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3763 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3766 /* REG+const has 5-7 bit offset for non-SP registers. */
3767 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3768 || XEXP (x
, 0) == arg_pointer_rtx
)
3769 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3770 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3773 /* REG+const has 10 bit offset for SP, but only SImode and
3774 larger is supported. */
3775 /* ??? Should probably check for DI/DFmode overflow here
3776 just like GO_IF_LEGITIMATE_OFFSET does. */
3777 else if (GET_CODE (XEXP (x
, 0)) == REG
3778 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3779 && GET_MODE_SIZE (mode
) >= 4
3780 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3781 && INTVAL (XEXP (x
, 1)) >= 0
3782 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3783 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3786 else if (GET_CODE (XEXP (x
, 0)) == REG
3787 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3788 && GET_MODE_SIZE (mode
) >= 4
3789 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3790 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3794 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3795 && GET_MODE_SIZE (mode
) == 4
3796 && GET_CODE (x
) == SYMBOL_REF
3797 && CONSTANT_POOL_ADDRESS_P (x
)
3799 && symbol_mentioned_p (get_pool_constant (x
))
3800 && ! pcrel_constant_p (get_pool_constant (x
))))
3806 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3807 instruction of mode MODE. */
3809 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3811 switch (GET_MODE_SIZE (mode
))
3814 return val
>= 0 && val
< 32;
3817 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3821 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3826 /* Build the SYMBOL_REF for __tls_get_addr. */
3828 static GTY(()) rtx tls_get_addr_libfunc
;
3831 get_tls_get_addr (void)
3833 if (!tls_get_addr_libfunc
)
3834 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
3835 return tls_get_addr_libfunc
;
3839 arm_load_tp (rtx target
)
3842 target
= gen_reg_rtx (SImode
);
3846 /* Can return in any reg. */
3847 emit_insn (gen_load_tp_hard (target
));
3851 /* Always returned in r0. Immediately copy the result into a pseudo,
3852 otherwise other uses of r0 (e.g. setting up function arguments) may
3853 clobber the value. */
3857 emit_insn (gen_load_tp_soft ());
3859 tmp
= gen_rtx_REG (SImode
, 0);
3860 emit_move_insn (target
, tmp
);
3866 load_tls_operand (rtx x
, rtx reg
)
3870 if (reg
== NULL_RTX
)
3871 reg
= gen_reg_rtx (SImode
);
3873 tmp
= gen_rtx_CONST (SImode
, x
);
3875 emit_move_insn (reg
, tmp
);
3881 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
3883 rtx insns
, label
, labelno
, sum
;
3887 labelno
= GEN_INT (pic_labelno
++);
3888 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3889 label
= gen_rtx_CONST (VOIDmode
, label
);
3891 sum
= gen_rtx_UNSPEC (Pmode
,
3892 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
3893 GEN_INT (TARGET_ARM
? 8 : 4)),
3895 reg
= load_tls_operand (sum
, reg
);
3898 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
3900 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3902 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
3903 Pmode
, 1, reg
, Pmode
);
3905 insns
= get_insns ();
3912 legitimize_tls_address (rtx x
, rtx reg
)
3914 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
3915 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
3919 case TLS_MODEL_GLOBAL_DYNAMIC
:
3920 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
3921 dest
= gen_reg_rtx (Pmode
);
3922 emit_libcall_block (insns
, dest
, ret
, x
);
3925 case TLS_MODEL_LOCAL_DYNAMIC
:
3926 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
3928 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3929 share the LDM result with other LD model accesses. */
3930 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
3932 dest
= gen_reg_rtx (Pmode
);
3933 emit_libcall_block (insns
, dest
, ret
, eqv
);
3935 /* Load the addend. */
3936 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
3938 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
3939 return gen_rtx_PLUS (Pmode
, dest
, addend
);
3941 case TLS_MODEL_INITIAL_EXEC
:
3942 labelno
= GEN_INT (pic_labelno
++);
3943 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3944 label
= gen_rtx_CONST (VOIDmode
, label
);
3945 sum
= gen_rtx_UNSPEC (Pmode
,
3946 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
3947 GEN_INT (TARGET_ARM
? 8 : 4)),
3949 reg
= load_tls_operand (sum
, reg
);
3952 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
3955 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3956 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
3959 tp
= arm_load_tp (NULL_RTX
);
3961 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3963 case TLS_MODEL_LOCAL_EXEC
:
3964 tp
= arm_load_tp (NULL_RTX
);
3966 reg
= gen_rtx_UNSPEC (Pmode
,
3967 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
3969 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
3971 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3978 /* Try machine-dependent ways of modifying an illegitimate address
3979 to be legitimate. If we find one, return the new, valid address. */
3981 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3983 if (arm_tls_symbol_p (x
))
3984 return legitimize_tls_address (x
, NULL_RTX
);
3986 if (GET_CODE (x
) == PLUS
)
3988 rtx xop0
= XEXP (x
, 0);
3989 rtx xop1
= XEXP (x
, 1);
3991 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3992 xop0
= force_reg (SImode
, xop0
);
3994 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3995 xop1
= force_reg (SImode
, xop1
);
3997 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3998 && GET_CODE (xop1
) == CONST_INT
)
4000 HOST_WIDE_INT n
, low_n
;
4004 /* VFP addressing modes actually allow greater offsets, but for
4005 now we just stick with the lowest common denominator. */
4007 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
4019 low_n
= ((mode
) == TImode
? 0
4020 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
4024 base_reg
= gen_reg_rtx (SImode
);
4025 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
4026 emit_move_insn (base_reg
, val
);
4027 x
= plus_constant (base_reg
, low_n
);
4029 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4030 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4033 /* XXX We don't allow MINUS any more -- see comment in
4034 arm_legitimate_address_p (). */
4035 else if (GET_CODE (x
) == MINUS
)
4037 rtx xop0
= XEXP (x
, 0);
4038 rtx xop1
= XEXP (x
, 1);
4040 if (CONSTANT_P (xop0
))
4041 xop0
= force_reg (SImode
, xop0
);
4043 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
4044 xop1
= force_reg (SImode
, xop1
);
4046 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4047 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
4050 /* Make sure to take full advantage of the pre-indexed addressing mode
4051 with absolute addresses which often allows for the base register to
4052 be factorized for multiple adjacent memory references, and it might
4053 even allows for the mini pool to be avoided entirely. */
4054 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
4057 HOST_WIDE_INT mask
, base
, index
;
4060 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4061 use a 8 bit index. So let's use a 12 bit index for SImode only and
4062 hope that arm_gen_constant will enable ldrb to use more bits. */
4063 bits
= (mode
== SImode
) ? 12 : 8;
4064 mask
= (1 << bits
) - 1;
4065 base
= INTVAL (x
) & ~mask
;
4066 index
= INTVAL (x
) & mask
;
4067 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4069 /* It'll most probably be more efficient to generate the base
4070 with more bits set and use a negative index instead. */
4074 base_reg
= force_reg (SImode
, GEN_INT (base
));
4075 x
= plus_constant (base_reg
, index
);
4080 /* We need to find and carefully transform any SYMBOL and LABEL
4081 references; so go back to the original address expression. */
4082 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4084 if (new_x
!= orig_x
)
4092 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4093 to be legitimate. If we find one, return the new, valid address. */
4095 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4097 if (arm_tls_symbol_p (x
))
4098 return legitimize_tls_address (x
, NULL_RTX
);
4100 if (GET_CODE (x
) == PLUS
4101 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4102 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4103 || INTVAL (XEXP (x
, 1)) < 0))
4105 rtx xop0
= XEXP (x
, 0);
4106 rtx xop1
= XEXP (x
, 1);
4107 HOST_WIDE_INT offset
= INTVAL (xop1
);
4109 /* Try and fold the offset into a biasing of the base register and
4110 then offsetting that. Don't do this when optimizing for space
4111 since it can cause too many CSEs. */
4112 if (optimize_size
&& offset
>= 0
4113 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4115 HOST_WIDE_INT delta
;
4118 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4119 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4120 delta
= 31 * GET_MODE_SIZE (mode
);
4122 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4124 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4126 x
= plus_constant (xop0
, delta
);
4128 else if (offset
< 0 && offset
> -256)
4129 /* Small negative offsets are best done with a subtract before the
4130 dereference, forcing these into a register normally takes two
4132 x
= force_operand (x
, NULL_RTX
);
4135 /* For the remaining cases, force the constant into a register. */
4136 xop1
= force_reg (SImode
, xop1
);
4137 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4140 else if (GET_CODE (x
) == PLUS
4141 && s_register_operand (XEXP (x
, 1), SImode
)
4142 && !s_register_operand (XEXP (x
, 0), SImode
))
4144 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4146 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4151 /* We need to find and carefully transform any SYMBOL and LABEL
4152 references; so go back to the original address expression. */
4153 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4155 if (new_x
!= orig_x
)
4163 thumb_legitimize_reload_address (rtx
*x_p
,
4164 enum machine_mode mode
,
4165 int opnum
, int type
,
4166 int ind_levels ATTRIBUTE_UNUSED
)
4170 if (GET_CODE (x
) == PLUS
4171 && GET_MODE_SIZE (mode
) < 4
4172 && REG_P (XEXP (x
, 0))
4173 && XEXP (x
, 0) == stack_pointer_rtx
4174 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4175 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4180 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4181 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4185 /* If both registers are hi-regs, then it's better to reload the
4186 entire expression rather than each register individually. That
4187 only requires one reload register rather than two. */
4188 if (GET_CODE (x
) == PLUS
4189 && REG_P (XEXP (x
, 0))
4190 && REG_P (XEXP (x
, 1))
4191 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4192 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4197 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4198 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4205 /* Test for various thread-local symbols. */
4207 /* Return TRUE if X is a thread-local symbol. */
4210 arm_tls_symbol_p (rtx x
)
4212 if (! TARGET_HAVE_TLS
)
4215 if (GET_CODE (x
) != SYMBOL_REF
)
4218 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4221 /* Helper for arm_tls_referenced_p. */
4224 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4226 if (GET_CODE (*x
) == SYMBOL_REF
)
4227 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4229 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4230 TLS offsets, not real symbol references. */
4231 if (GET_CODE (*x
) == UNSPEC
4232 && XINT (*x
, 1) == UNSPEC_TLS
)
4238 /* Return TRUE if X contains any TLS symbol references. */
4241 arm_tls_referenced_p (rtx x
)
4243 if (! TARGET_HAVE_TLS
)
4246 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4249 #define REG_OR_SUBREG_REG(X) \
4250 (GET_CODE (X) == REG \
4251 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4253 #define REG_OR_SUBREG_RTX(X) \
4254 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4256 #ifndef COSTS_N_INSNS
4257 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4260 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4262 enum machine_mode mode
= GET_MODE (x
);
4275 return COSTS_N_INSNS (1);
4278 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4281 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4288 return COSTS_N_INSNS (2) + cycles
;
4290 return COSTS_N_INSNS (1) + 16;
4293 return (COSTS_N_INSNS (1)
4294 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4295 + GET_CODE (SET_DEST (x
)) == MEM
));
4300 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4302 if (thumb_shiftable_const (INTVAL (x
)))
4303 return COSTS_N_INSNS (2);
4304 return COSTS_N_INSNS (3);
4306 else if ((outer
== PLUS
|| outer
== COMPARE
)
4307 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4309 else if (outer
== AND
4310 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4311 return COSTS_N_INSNS (1);
4312 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4313 || outer
== LSHIFTRT
)
4315 return COSTS_N_INSNS (2);
4321 return COSTS_N_INSNS (3);
4339 /* XXX another guess. */
4340 /* Memory costs quite a lot for the first word, but subsequent words
4341 load at the equivalent of a single insn each. */
4342 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4343 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4348 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4353 /* XXX still guessing. */
4354 switch (GET_MODE (XEXP (x
, 0)))
4357 return (1 + (mode
== DImode
? 4 : 0)
4358 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4361 return (4 + (mode
== DImode
? 4 : 0)
4362 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4365 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4377 /* Worker routine for arm_rtx_costs. */
4379 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4381 enum machine_mode mode
= GET_MODE (x
);
4382 enum rtx_code subcode
;
4388 /* Memory costs quite a lot for the first word, but subsequent words
4389 load at the equivalent of a single insn each. */
4390 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4391 + (GET_CODE (x
) == SYMBOL_REF
4392 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4398 return optimize_size
? COSTS_N_INSNS (2) : 100;
4401 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4408 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4410 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4411 + ((GET_CODE (XEXP (x
, 0)) == REG
4412 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4413 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4415 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4416 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4417 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4419 + ((GET_CODE (XEXP (x
, 1)) == REG
4420 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4421 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4422 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4427 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4428 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4429 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4430 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4433 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4434 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4435 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4436 && arm_const_double_rtx (XEXP (x
, 1))))
4438 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4439 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4440 && arm_const_double_rtx (XEXP (x
, 0))))
4443 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4444 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4445 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4446 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4447 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4448 || subcode
== ROTATE
|| subcode
== ROTATERT
4450 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4451 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4452 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4453 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4454 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4455 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4456 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4461 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4462 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4463 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4464 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4465 && arm_const_double_rtx (XEXP (x
, 1))))
4469 case AND
: case XOR
: case IOR
:
4472 /* Normally the frame registers will be spilt into reg+const during
4473 reload, so it is a bad idea to combine them with other instructions,
4474 since then they might not be moved outside of loops. As a compromise
4475 we allow integration with ops that have a constant as their second
4477 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4478 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4479 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4480 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4481 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4485 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4486 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4487 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4488 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4491 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4492 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4493 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4494 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4495 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4498 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4499 return (1 + extra_cost
4500 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4501 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4502 || subcode
== ROTATE
|| subcode
== ROTATERT
4504 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4505 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4506 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4507 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4508 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4509 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4515 /* This should have been handled by the CPU specific routines. */
4519 if (arm_arch3m
&& mode
== SImode
4520 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4521 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4522 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4523 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4524 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4525 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4530 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4531 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4535 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4537 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4540 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4548 return 4 + (mode
== DImode
? 4 : 0);
4551 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4552 return (4 + (mode
== DImode
? 4 : 0)
4553 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4556 switch (GET_MODE (XEXP (x
, 0)))
4559 return (1 + (mode
== DImode
? 4 : 0)
4560 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4563 return (4 + (mode
== DImode
? 4 : 0)
4564 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4567 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4582 if (const_ok_for_arm (INTVAL (x
)))
4583 return outer
== SET
? 2 : -1;
4584 else if (outer
== AND
4585 && const_ok_for_arm (~INTVAL (x
)))
4587 else if ((outer
== COMPARE
4588 || outer
== PLUS
|| outer
== MINUS
)
4589 && const_ok_for_arm (-INTVAL (x
)))
4600 if (arm_const_double_rtx (x
))
4601 return outer
== SET
? 2 : -1;
4602 else if ((outer
== COMPARE
|| outer
== PLUS
)
4603 && neg_const_double_rtx_ok_for_fpa (x
))
4612 /* RTX costs when optimizing for size. */
4614 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4616 enum machine_mode mode
= GET_MODE (x
);
4620 /* XXX TBD. For now, use the standard costs. */
4621 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4628 /* A memory access costs 1 insn if the mode is small, or the address is
4629 a single register, otherwise it costs one insn per word. */
4630 if (REG_P (XEXP (x
, 0)))
4631 *total
= COSTS_N_INSNS (1);
4633 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4640 /* Needs a libcall, so it costs about this. */
4641 *total
= COSTS_N_INSNS (2);
4645 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4647 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4655 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4657 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4660 else if (mode
== SImode
)
4662 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4663 /* Slightly disparage register shifts, but not by much. */
4664 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4665 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4669 /* Needs a libcall. */
4670 *total
= COSTS_N_INSNS (2);
4674 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4676 *total
= COSTS_N_INSNS (1);
4682 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4683 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4685 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4686 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4687 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4688 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4689 || subcode1
== ASHIFTRT
)
4691 /* It's just the cost of the two operands. */
4696 *total
= COSTS_N_INSNS (1);
4700 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4704 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4706 *total
= COSTS_N_INSNS (1);
4711 case AND
: case XOR
: case IOR
:
4714 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4716 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4717 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4718 || (code
== AND
&& subcode
== NOT
))
4720 /* It's just the cost of the two operands. */
4726 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4730 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4734 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4735 *total
= COSTS_N_INSNS (1);
4738 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4747 if (cc_register (XEXP (x
, 0), VOIDmode
))
4750 *total
= COSTS_N_INSNS (1);
4754 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4755 *total
= COSTS_N_INSNS (1);
4757 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4762 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4764 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4765 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4768 *total
+= COSTS_N_INSNS (1);
4773 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4775 switch (GET_MODE (XEXP (x
, 0)))
4778 *total
+= COSTS_N_INSNS (1);
4782 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4788 *total
+= COSTS_N_INSNS (2);
4793 *total
+= COSTS_N_INSNS (1);
4798 if (const_ok_for_arm (INTVAL (x
)))
4799 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4800 else if (const_ok_for_arm (~INTVAL (x
)))
4801 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4802 else if (const_ok_for_arm (-INTVAL (x
)))
4804 if (outer_code
== COMPARE
|| outer_code
== PLUS
4805 || outer_code
== MINUS
)
4808 *total
= COSTS_N_INSNS (1);
4811 *total
= COSTS_N_INSNS (2);
4817 *total
= COSTS_N_INSNS (2);
4821 *total
= COSTS_N_INSNS (4);
4825 if (mode
!= VOIDmode
)
4826 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4828 *total
= COSTS_N_INSNS (4); /* How knows? */
4833 /* RTX costs for cores with a slow MUL implementation. */
4836 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4838 enum machine_mode mode
= GET_MODE (x
);
4842 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4849 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4856 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4858 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4859 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4860 int cost
, const_ok
= const_ok_for_arm (i
);
4861 int j
, booth_unit_size
;
4863 /* Tune as appropriate. */
4864 cost
= const_ok
? 4 : 8;
4865 booth_unit_size
= 2;
4866 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4868 i
>>= booth_unit_size
;
4876 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4877 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4881 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4887 /* RTX cost for cores with a fast multiply unit (M variants). */
4890 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4892 enum machine_mode mode
= GET_MODE (x
);
4896 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4903 /* There is no point basing this on the tuning, since it is always the
4904 fast variant if it exists at all. */
4906 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4907 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4908 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4915 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4922 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4924 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4925 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4926 int cost
, const_ok
= const_ok_for_arm (i
);
4927 int j
, booth_unit_size
;
4929 /* Tune as appropriate. */
4930 cost
= const_ok
? 4 : 8;
4931 booth_unit_size
= 8;
4932 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4934 i
>>= booth_unit_size
;
4942 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4943 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4947 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4953 /* RTX cost for XScale CPUs. */
4956 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4958 enum machine_mode mode
= GET_MODE (x
);
4962 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4969 /* There is no point basing this on the tuning, since it is always the
4970 fast variant if it exists at all. */
4972 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4973 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4974 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4981 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4988 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4990 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4991 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4992 int cost
, const_ok
= const_ok_for_arm (i
);
4993 unsigned HOST_WIDE_INT masked_const
;
4995 /* The cost will be related to two insns.
4996 First a load of the constant (MOV or LDR), then a multiply. */
4999 cost
+= 1; /* LDR is probably more expensive because
5000 of longer result latency. */
5001 masked_const
= i
& 0xffff8000;
5002 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
5004 masked_const
= i
& 0xf8000000;
5005 if (masked_const
== 0 || masked_const
== 0xf8000000)
5014 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5015 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5019 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5020 will stall until the multiplication is complete. */
5021 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5022 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
5024 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5028 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5034 /* RTX costs for 9e (and later) cores. */
5037 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5039 enum machine_mode mode
= GET_MODE (x
);
5048 *total
= COSTS_N_INSNS (3);
5052 *total
= thumb_rtx_costs (x
, code
, outer_code
);
5060 /* There is no point basing this on the tuning, since it is always the
5061 fast variant if it exists at all. */
5063 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5064 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5065 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5072 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5089 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5090 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5094 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5098 /* All address computations that can be done are free, but rtx cost returns
5099 the same for practically all of them. So we weight the different types
5100 of address here in the order (most pref first):
5101 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5103 arm_arm_address_cost (rtx x
)
5105 enum rtx_code c
= GET_CODE (x
);
5107 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5109 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5112 if (c
== PLUS
|| c
== MINUS
)
5114 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5117 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5127 arm_thumb_address_cost (rtx x
)
5129 enum rtx_code c
= GET_CODE (x
);
5134 && GET_CODE (XEXP (x
, 0)) == REG
5135 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5142 arm_address_cost (rtx x
)
5144 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5148 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5152 /* Some true dependencies can have a higher cost depending
5153 on precisely how certain input operands are used. */
5155 && REG_NOTE_KIND (link
) == 0
5156 && recog_memoized (insn
) >= 0
5157 && recog_memoized (dep
) >= 0)
5159 int shift_opnum
= get_attr_shift (insn
);
5160 enum attr_type attr_type
= get_attr_type (dep
);
5162 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5163 operand for INSN. If we have a shifted input operand and the
5164 instruction we depend on is another ALU instruction, then we may
5165 have to account for an additional stall. */
5166 if (shift_opnum
!= 0
5167 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5169 rtx shifted_operand
;
5172 /* Get the shifted operand. */
5173 extract_insn (insn
);
5174 shifted_operand
= recog_data
.operand
[shift_opnum
];
5176 /* Iterate over all the operands in DEP. If we write an operand
5177 that overlaps with SHIFTED_OPERAND, then we have increase the
5178 cost of this dependency. */
5180 preprocess_constraints ();
5181 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5183 /* We can ignore strict inputs. */
5184 if (recog_data
.operand_type
[opno
] == OP_IN
)
5187 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5194 /* XXX This is not strictly true for the FPA. */
5195 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5196 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5199 /* Call insns don't incur a stall, even if they follow a load. */
5200 if (REG_NOTE_KIND (link
) == 0
5201 && GET_CODE (insn
) == CALL_INSN
)
5204 if ((i_pat
= single_set (insn
)) != NULL
5205 && GET_CODE (SET_SRC (i_pat
)) == MEM
5206 && (d_pat
= single_set (dep
)) != NULL
5207 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5209 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5210 /* This is a load after a store, there is no conflict if the load reads
5211 from a cached area. Assume that loads from the stack, and from the
5212 constant pool are cached, and that others will miss. This is a
5215 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5216 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5217 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5218 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5225 static int fp_consts_inited
= 0;
5227 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5228 static const char * const strings_fp
[8] =
5231 "4", "5", "0.5", "10"
5234 static REAL_VALUE_TYPE values_fp
[8];
5237 init_fp_table (void)
5243 fp_consts_inited
= 1;
5245 fp_consts_inited
= 8;
5247 for (i
= 0; i
< fp_consts_inited
; i
++)
5249 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5254 /* Return TRUE if rtx X is a valid immediate FP constant. */
5256 arm_const_double_rtx (rtx x
)
5261 if (!fp_consts_inited
)
5264 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5265 if (REAL_VALUE_MINUS_ZERO (r
))
5268 for (i
= 0; i
< fp_consts_inited
; i
++)
5269 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5275 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5277 neg_const_double_rtx_ok_for_fpa (rtx x
)
5282 if (!fp_consts_inited
)
5285 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5286 r
= REAL_VALUE_NEGATE (r
);
5287 if (REAL_VALUE_MINUS_ZERO (r
))
5290 for (i
= 0; i
< 8; i
++)
5291 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5297 /* Predicates for `match_operand' and `match_operator'. */
5299 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5301 cirrus_memory_offset (rtx op
)
5303 /* Reject eliminable registers. */
5304 if (! (reload_in_progress
|| reload_completed
)
5305 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5306 || reg_mentioned_p (arg_pointer_rtx
, op
)
5307 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5308 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5309 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5310 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5313 if (GET_CODE (op
) == MEM
)
5319 /* Match: (mem (reg)). */
5320 if (GET_CODE (ind
) == REG
)
5326 if (GET_CODE (ind
) == PLUS
5327 && GET_CODE (XEXP (ind
, 0)) == REG
5328 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5329 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5336 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5337 WB if true if writeback address modes are allowed. */
5340 arm_coproc_mem_operand (rtx op
, bool wb
)
5344 /* Reject eliminable registers. */
5345 if (! (reload_in_progress
|| reload_completed
)
5346 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5347 || reg_mentioned_p (arg_pointer_rtx
, op
)
5348 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5349 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5350 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5351 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5354 /* Constants are converted into offsets from labels. */
5355 if (GET_CODE (op
) != MEM
)
5360 if (reload_completed
5361 && (GET_CODE (ind
) == LABEL_REF
5362 || (GET_CODE (ind
) == CONST
5363 && GET_CODE (XEXP (ind
, 0)) == PLUS
5364 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5365 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5368 /* Match: (mem (reg)). */
5369 if (GET_CODE (ind
) == REG
)
5370 return arm_address_register_rtx_p (ind
, 0);
5372 /* Autoincremment addressing modes. */
5374 && (GET_CODE (ind
) == PRE_INC
5375 || GET_CODE (ind
) == POST_INC
5376 || GET_CODE (ind
) == PRE_DEC
5377 || GET_CODE (ind
) == POST_DEC
))
5378 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5381 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5382 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5383 && GET_CODE (XEXP (ind
, 1)) == PLUS
5384 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5385 ind
= XEXP (ind
, 1);
5390 if (GET_CODE (ind
) == PLUS
5391 && GET_CODE (XEXP (ind
, 0)) == REG
5392 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5393 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5394 && INTVAL (XEXP (ind
, 1)) > -1024
5395 && INTVAL (XEXP (ind
, 1)) < 1024
5396 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5402 /* Return true if X is a register that will be eliminated later on. */
5404 arm_eliminable_register (rtx x
)
5406 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5407 || REGNO (x
) == ARG_POINTER_REGNUM
5408 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5409 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5412 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5413 VFP registers. Otherwise return NO_REGS. */
5416 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5418 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5421 return GENERAL_REGS
;
5424 /* Values which must be returned in the most-significant end of the return
5428 arm_return_in_msb (tree valtype
)
5430 return (TARGET_AAPCS_BASED
5432 && (AGGREGATE_TYPE_P (valtype
)
5433 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5436 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5437 Use by the Cirrus Maverick code which has to workaround
5438 a hardware bug triggered by such instructions. */
5440 arm_memory_load_p (rtx insn
)
5442 rtx body
, lhs
, rhs
;;
5444 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5447 body
= PATTERN (insn
);
5449 if (GET_CODE (body
) != SET
)
5452 lhs
= XEXP (body
, 0);
5453 rhs
= XEXP (body
, 1);
5455 lhs
= REG_OR_SUBREG_RTX (lhs
);
5457 /* If the destination is not a general purpose
5458 register we do not have to worry. */
5459 if (GET_CODE (lhs
) != REG
5460 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5463 /* As well as loads from memory we also have to react
5464 to loads of invalid constants which will be turned
5465 into loads from the minipool. */
5466 return (GET_CODE (rhs
) == MEM
5467 || GET_CODE (rhs
) == SYMBOL_REF
5468 || note_invalid_constants (insn
, -1, false));
5471 /* Return TRUE if INSN is a Cirrus instruction. */
5473 arm_cirrus_insn_p (rtx insn
)
5475 enum attr_cirrus attr
;
5477 /* get_attr cannot accept USE or CLOBBER. */
5479 || GET_CODE (insn
) != INSN
5480 || GET_CODE (PATTERN (insn
)) == USE
5481 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5484 attr
= get_attr_cirrus (insn
);
5486 return attr
!= CIRRUS_NOT
;
5489 /* Cirrus reorg for invalid instruction combinations. */
5491 cirrus_reorg (rtx first
)
5493 enum attr_cirrus attr
;
5494 rtx body
= PATTERN (first
);
5498 /* Any branch must be followed by 2 non Cirrus instructions. */
5499 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5502 t
= next_nonnote_insn (first
);
5504 if (arm_cirrus_insn_p (t
))
5507 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5511 emit_insn_after (gen_nop (), first
);
5516 /* (float (blah)) is in parallel with a clobber. */
5517 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5518 body
= XVECEXP (body
, 0, 0);
5520 if (GET_CODE (body
) == SET
)
5522 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5524 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5525 be followed by a non Cirrus insn. */
5526 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5528 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5529 emit_insn_after (gen_nop (), first
);
5533 else if (arm_memory_load_p (first
))
5535 unsigned int arm_regno
;
5537 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5538 ldr/cfmv64hr combination where the Rd field is the same
5539 in both instructions must be split with a non Cirrus
5546 /* Get Arm register number for ldr insn. */
5547 if (GET_CODE (lhs
) == REG
)
5548 arm_regno
= REGNO (lhs
);
5551 gcc_assert (GET_CODE (rhs
) == REG
);
5552 arm_regno
= REGNO (rhs
);
5556 first
= next_nonnote_insn (first
);
5558 if (! arm_cirrus_insn_p (first
))
5561 body
= PATTERN (first
);
5563 /* (float (blah)) is in parallel with a clobber. */
5564 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5565 body
= XVECEXP (body
, 0, 0);
5567 if (GET_CODE (body
) == FLOAT
)
5568 body
= XEXP (body
, 0);
5570 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5571 && GET_CODE (XEXP (body
, 1)) == REG
5572 && arm_regno
== REGNO (XEXP (body
, 1)))
5573 emit_insn_after (gen_nop (), first
);
5579 /* get_attr cannot accept USE or CLOBBER. */
5581 || GET_CODE (first
) != INSN
5582 || GET_CODE (PATTERN (first
)) == USE
5583 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5586 attr
= get_attr_cirrus (first
);
5588 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5589 must be followed by a non-coprocessor instruction. */
5590 if (attr
== CIRRUS_COMPARE
)
5594 t
= next_nonnote_insn (first
);
5596 if (arm_cirrus_insn_p (t
))
5599 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5603 emit_insn_after (gen_nop (), first
);
5609 /* Return TRUE if X references a SYMBOL_REF. */
5611 symbol_mentioned_p (rtx x
)
5616 if (GET_CODE (x
) == SYMBOL_REF
)
5619 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5620 are constant offsets, not symbols. */
5621 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5624 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5626 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5632 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5633 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5636 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5643 /* Return TRUE if X references a LABEL_REF. */
5645 label_mentioned_p (rtx x
)
5650 if (GET_CODE (x
) == LABEL_REF
)
5653 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5654 instruction, but they are constant offsets, not symbols. */
5655 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5658 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5659 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5665 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5666 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5669 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5677 tls_mentioned_p (rtx x
)
5679 switch (GET_CODE (x
))
5682 return tls_mentioned_p (XEXP (x
, 0));
5685 if (XINT (x
, 1) == UNSPEC_TLS
)
5693 /* Must not copy a SET whose source operand is PC-relative. */
5696 arm_cannot_copy_insn_p (rtx insn
)
5698 rtx pat
= PATTERN (insn
);
5700 if (GET_CODE (pat
) == PARALLEL
5701 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
5703 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
5705 if (GET_CODE (rhs
) == UNSPEC
5706 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
5709 if (GET_CODE (rhs
) == MEM
5710 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
5711 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
5721 enum rtx_code code
= GET_CODE (x
);
5738 /* Return 1 if memory locations are adjacent. */
5740 adjacent_mem_locations (rtx a
, rtx b
)
5742 /* We don't guarantee to preserve the order of these memory refs. */
5743 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5746 if ((GET_CODE (XEXP (a
, 0)) == REG
5747 || (GET_CODE (XEXP (a
, 0)) == PLUS
5748 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5749 && (GET_CODE (XEXP (b
, 0)) == REG
5750 || (GET_CODE (XEXP (b
, 0)) == PLUS
5751 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5753 HOST_WIDE_INT val0
= 0, val1
= 0;
5757 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5759 reg0
= XEXP (XEXP (a
, 0), 0);
5760 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5765 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5767 reg1
= XEXP (XEXP (b
, 0), 0);
5768 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5773 /* Don't accept any offset that will require multiple
5774 instructions to handle, since this would cause the
5775 arith_adjacentmem pattern to output an overlong sequence. */
5776 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5779 /* Don't allow an eliminable register: register elimination can make
5780 the offset too large. */
5781 if (arm_eliminable_register (reg0
))
5784 val_diff
= val1
- val0
;
5788 /* If the target has load delay slots, then there's no benefit
5789 to using an ldm instruction unless the offset is zero and
5790 we are optimizing for size. */
5791 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5792 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5793 && (val_diff
== 4 || val_diff
== -4));
5796 return ((REGNO (reg0
) == REGNO (reg1
))
5797 && (val_diff
== 4 || val_diff
== -4));
5804 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5805 HOST_WIDE_INT
*load_offset
)
5807 int unsorted_regs
[4];
5808 HOST_WIDE_INT unsorted_offsets
[4];
5813 /* Can only handle 2, 3, or 4 insns at present,
5814 though could be easily extended if required. */
5815 gcc_assert (nops
>= 2 && nops
<= 4);
5817 /* Loop over the operands and check that the memory references are
5818 suitable (i.e. immediate offsets from the same base register). At
5819 the same time, extract the target register, and the memory
5821 for (i
= 0; i
< nops
; i
++)
5826 /* Convert a subreg of a mem into the mem itself. */
5827 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5828 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5830 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5832 /* Don't reorder volatile memory references; it doesn't seem worth
5833 looking for the case where the order is ok anyway. */
5834 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5837 offset
= const0_rtx
;
5839 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5840 || (GET_CODE (reg
) == SUBREG
5841 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5842 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5843 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5845 || (GET_CODE (reg
) == SUBREG
5846 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5847 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5852 base_reg
= REGNO (reg
);
5853 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5854 ? REGNO (operands
[i
])
5855 : REGNO (SUBREG_REG (operands
[i
])));
5860 if (base_reg
!= (int) REGNO (reg
))
5861 /* Not addressed from the same base register. */
5864 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5865 ? REGNO (operands
[i
])
5866 : REGNO (SUBREG_REG (operands
[i
])));
5867 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5871 /* If it isn't an integer register, or if it overwrites the
5872 base register but isn't the last insn in the list, then
5873 we can't do this. */
5874 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5875 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5878 unsorted_offsets
[i
] = INTVAL (offset
);
5881 /* Not a suitable memory address. */
5885 /* All the useful information has now been extracted from the
5886 operands into unsorted_regs and unsorted_offsets; additionally,
5887 order[0] has been set to the lowest numbered register in the
5888 list. Sort the registers into order, and check that the memory
5889 offsets are ascending and adjacent. */
5891 for (i
= 1; i
< nops
; i
++)
5895 order
[i
] = order
[i
- 1];
5896 for (j
= 0; j
< nops
; j
++)
5897 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5898 && (order
[i
] == order
[i
- 1]
5899 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5902 /* Have we found a suitable register? if not, one must be used more
5904 if (order
[i
] == order
[i
- 1])
5907 /* Is the memory address adjacent and ascending? */
5908 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5916 for (i
= 0; i
< nops
; i
++)
5917 regs
[i
] = unsorted_regs
[order
[i
]];
5919 *load_offset
= unsorted_offsets
[order
[0]];
5922 if (unsorted_offsets
[order
[0]] == 0)
5923 return 1; /* ldmia */
5925 if (unsorted_offsets
[order
[0]] == 4)
5926 return 2; /* ldmib */
5928 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5929 return 3; /* ldmda */
5931 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5932 return 4; /* ldmdb */
5934 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5935 if the offset isn't small enough. The reason 2 ldrs are faster
5936 is because these ARMs are able to do more than one cache access
5937 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5938 whilst the ARM8 has a double bandwidth cache. This means that
5939 these cores can do both an instruction fetch and a data fetch in
5940 a single cycle, so the trick of calculating the address into a
5941 scratch register (one of the result regs) and then doing a load
5942 multiple actually becomes slower (and no smaller in code size).
5943 That is the transformation
5945 ldr rd1, [rbase + offset]
5946 ldr rd2, [rbase + offset + 4]
5950 add rd1, rbase, offset
5951 ldmia rd1, {rd1, rd2}
5953 produces worse code -- '3 cycles + any stalls on rd2' instead of
5954 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5955 access per cycle, the first sequence could never complete in less
5956 than 6 cycles, whereas the ldm sequence would only take 5 and
5957 would make better use of sequential accesses if not hitting the
5960 We cheat here and test 'arm_ld_sched' which we currently know to
5961 only be true for the ARM8, ARM9 and StrongARM. If this ever
5962 changes, then the test below needs to be reworked. */
5963 if (nops
== 2 && arm_ld_sched
)
5966 /* Can't do it without setting up the offset, only do this if it takes
5967 no more than one insn. */
5968 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5969 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5973 emit_ldm_seq (rtx
*operands
, int nops
)
5977 HOST_WIDE_INT offset
;
5981 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5984 strcpy (buf
, "ldm%?ia\t");
5988 strcpy (buf
, "ldm%?ib\t");
5992 strcpy (buf
, "ldm%?da\t");
5996 strcpy (buf
, "ldm%?db\t");
6001 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6002 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6005 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6006 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6008 output_asm_insn (buf
, operands
);
6010 strcpy (buf
, "ldm%?ia\t");
6017 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6018 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6020 for (i
= 1; i
< nops
; i
++)
6021 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6022 reg_names
[regs
[i
]]);
6024 strcat (buf
, "}\t%@ phole ldm");
6026 output_asm_insn (buf
, operands
);
6031 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
6032 HOST_WIDE_INT
* load_offset
)
6034 int unsorted_regs
[4];
6035 HOST_WIDE_INT unsorted_offsets
[4];
6040 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6041 extended if required. */
6042 gcc_assert (nops
>= 2 && nops
<= 4);
6044 /* Loop over the operands and check that the memory references are
6045 suitable (i.e. immediate offsets from the same base register). At
6046 the same time, extract the target register, and the memory
6048 for (i
= 0; i
< nops
; i
++)
6053 /* Convert a subreg of a mem into the mem itself. */
6054 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6055 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6057 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6059 /* Don't reorder volatile memory references; it doesn't seem worth
6060 looking for the case where the order is ok anyway. */
6061 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6064 offset
= const0_rtx
;
6066 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6067 || (GET_CODE (reg
) == SUBREG
6068 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6069 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6070 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6072 || (GET_CODE (reg
) == SUBREG
6073 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6074 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6079 base_reg
= REGNO (reg
);
6080 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6081 ? REGNO (operands
[i
])
6082 : REGNO (SUBREG_REG (operands
[i
])));
6087 if (base_reg
!= (int) REGNO (reg
))
6088 /* Not addressed from the same base register. */
6091 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6092 ? REGNO (operands
[i
])
6093 : REGNO (SUBREG_REG (operands
[i
])));
6094 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6098 /* If it isn't an integer register, then we can't do this. */
6099 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6102 unsorted_offsets
[i
] = INTVAL (offset
);
6105 /* Not a suitable memory address. */
6109 /* All the useful information has now been extracted from the
6110 operands into unsorted_regs and unsorted_offsets; additionally,
6111 order[0] has been set to the lowest numbered register in the
6112 list. Sort the registers into order, and check that the memory
6113 offsets are ascending and adjacent. */
6115 for (i
= 1; i
< nops
; i
++)
6119 order
[i
] = order
[i
- 1];
6120 for (j
= 0; j
< nops
; j
++)
6121 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6122 && (order
[i
] == order
[i
- 1]
6123 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6126 /* Have we found a suitable register? if not, one must be used more
6128 if (order
[i
] == order
[i
- 1])
6131 /* Is the memory address adjacent and ascending? */
6132 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6140 for (i
= 0; i
< nops
; i
++)
6141 regs
[i
] = unsorted_regs
[order
[i
]];
6143 *load_offset
= unsorted_offsets
[order
[0]];
6146 if (unsorted_offsets
[order
[0]] == 0)
6147 return 1; /* stmia */
6149 if (unsorted_offsets
[order
[0]] == 4)
6150 return 2; /* stmib */
6152 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6153 return 3; /* stmda */
6155 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6156 return 4; /* stmdb */
6162 emit_stm_seq (rtx
*operands
, int nops
)
6166 HOST_WIDE_INT offset
;
6170 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6173 strcpy (buf
, "stm%?ia\t");
6177 strcpy (buf
, "stm%?ib\t");
6181 strcpy (buf
, "stm%?da\t");
6185 strcpy (buf
, "stm%?db\t");
6192 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6193 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6195 for (i
= 1; i
< nops
; i
++)
6196 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6197 reg_names
[regs
[i
]]);
6199 strcat (buf
, "}\t%@ phole stm");
6201 output_asm_insn (buf
, operands
);
6205 /* Routines for use in generating RTL. */
6208 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6209 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6211 HOST_WIDE_INT offset
= *offsetp
;
6214 int sign
= up
? 1 : -1;
6217 /* XScale has load-store double instructions, but they have stricter
6218 alignment requirements than load-store multiple, so we cannot
6221 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6222 the pipeline until completion.
6230 An ldr instruction takes 1-3 cycles, but does not block the
6239 Best case ldr will always win. However, the more ldr instructions
6240 we issue, the less likely we are to be able to schedule them well.
6241 Using ldr instructions also increases code size.
6243 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6244 for counts of 3 or 4 regs. */
6245 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6251 for (i
= 0; i
< count
; i
++)
6253 addr
= plus_constant (from
, i
* 4 * sign
);
6254 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6255 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6261 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6271 result
= gen_rtx_PARALLEL (VOIDmode
,
6272 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6275 XVECEXP (result
, 0, 0)
6276 = gen_rtx_SET (VOIDmode
, from
, plus_constant (from
, count
* 4 * sign
));
6281 for (j
= 0; i
< count
; i
++, j
++)
6283 addr
= plus_constant (from
, j
* 4 * sign
);
6284 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6285 XVECEXP (result
, 0, i
)
6286 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6297 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6298 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6300 HOST_WIDE_INT offset
= *offsetp
;
6303 int sign
= up
? 1 : -1;
6306 /* See arm_gen_load_multiple for discussion of
6307 the pros/cons of ldm/stm usage for XScale. */
6308 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6314 for (i
= 0; i
< count
; i
++)
6316 addr
= plus_constant (to
, i
* 4 * sign
);
6317 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6318 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6324 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6334 result
= gen_rtx_PARALLEL (VOIDmode
,
6335 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6338 XVECEXP (result
, 0, 0)
6339 = gen_rtx_SET (VOIDmode
, to
,
6340 plus_constant (to
, count
* 4 * sign
));
6345 for (j
= 0; i
< count
; i
++, j
++)
6347 addr
= plus_constant (to
, j
* 4 * sign
);
6348 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6349 XVECEXP (result
, 0, i
)
6350 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6361 arm_gen_movmemqi (rtx
*operands
)
6363 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6364 HOST_WIDE_INT srcoffset
, dstoffset
;
6366 rtx src
, dst
, srcbase
, dstbase
;
6367 rtx part_bytes_reg
= NULL
;
6370 if (GET_CODE (operands
[2]) != CONST_INT
6371 || GET_CODE (operands
[3]) != CONST_INT
6372 || INTVAL (operands
[2]) > 64
6373 || INTVAL (operands
[3]) & 3)
6376 dstbase
= operands
[0];
6377 srcbase
= operands
[1];
6379 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6380 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6382 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6383 out_words_to_go
= INTVAL (operands
[2]) / 4;
6384 last_bytes
= INTVAL (operands
[2]) & 3;
6385 dstoffset
= srcoffset
= 0;
6387 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6388 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6390 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6392 if (in_words_to_go
> 4)
6393 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6394 srcbase
, &srcoffset
));
6396 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6397 FALSE
, srcbase
, &srcoffset
));
6399 if (out_words_to_go
)
6401 if (out_words_to_go
> 4)
6402 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6403 dstbase
, &dstoffset
));
6404 else if (out_words_to_go
!= 1)
6405 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6409 dstbase
, &dstoffset
));
6412 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6413 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6414 if (last_bytes
!= 0)
6416 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6422 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6423 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6426 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6427 if (out_words_to_go
)
6431 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6432 sreg
= copy_to_reg (mem
);
6434 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6435 emit_move_insn (mem
, sreg
);
6438 gcc_assert (!in_words_to_go
); /* Sanity check */
6443 gcc_assert (in_words_to_go
> 0);
6445 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6446 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6449 gcc_assert (!last_bytes
|| part_bytes_reg
);
6451 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6453 rtx tmp
= gen_reg_rtx (SImode
);
6455 /* The bytes we want are in the top end of the word. */
6456 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6457 GEN_INT (8 * (4 - last_bytes
))));
6458 part_bytes_reg
= tmp
;
6462 mem
= adjust_automodify_address (dstbase
, QImode
,
6463 plus_constant (dst
, last_bytes
- 1),
6464 dstoffset
+ last_bytes
- 1);
6465 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6469 tmp
= gen_reg_rtx (SImode
);
6470 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6471 part_bytes_reg
= tmp
;
6480 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6481 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6485 rtx tmp
= gen_reg_rtx (SImode
);
6486 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6487 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6488 part_bytes_reg
= tmp
;
6495 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6496 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6503 /* Select a dominance comparison mode if possible for a test of the general
6504 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6505 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6506 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6507 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6508 In all cases OP will be either EQ or NE, but we don't need to know which
6509 here. If we are unable to support a dominance comparison we return
6510 CC mode. This will then fail to match for the RTL expressions that
6511 generate this call. */
6513 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6515 enum rtx_code cond1
, cond2
;
6518 /* Currently we will probably get the wrong result if the individual
6519 comparisons are not simple. This also ensures that it is safe to
6520 reverse a comparison if necessary. */
6521 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6523 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6527 /* The if_then_else variant of this tests the second condition if the
6528 first passes, but is true if the first fails. Reverse the first
6529 condition to get a true "inclusive-or" expression. */
6530 if (cond_or
== DOM_CC_NX_OR_Y
)
6531 cond1
= reverse_condition (cond1
);
6533 /* If the comparisons are not equal, and one doesn't dominate the other,
6534 then we can't do this. */
6536 && !comparison_dominates_p (cond1
, cond2
)
6537 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6542 enum rtx_code temp
= cond1
;
6550 if (cond_or
== DOM_CC_X_AND_Y
)
6555 case EQ
: return CC_DEQmode
;
6556 case LE
: return CC_DLEmode
;
6557 case LEU
: return CC_DLEUmode
;
6558 case GE
: return CC_DGEmode
;
6559 case GEU
: return CC_DGEUmode
;
6560 default: gcc_unreachable ();
6564 if (cond_or
== DOM_CC_X_AND_Y
)
6580 if (cond_or
== DOM_CC_X_AND_Y
)
6596 if (cond_or
== DOM_CC_X_AND_Y
)
6612 if (cond_or
== DOM_CC_X_AND_Y
)
6627 /* The remaining cases only occur when both comparisons are the
6630 gcc_assert (cond1
== cond2
);
6634 gcc_assert (cond1
== cond2
);
6638 gcc_assert (cond1
== cond2
);
6642 gcc_assert (cond1
== cond2
);
6646 gcc_assert (cond1
== cond2
);
6655 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6657 /* All floating point compares return CCFP if it is an equality
6658 comparison, and CCFPE otherwise. */
6659 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6679 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6688 /* A compare with a shifted operand. Because of canonicalization, the
6689 comparison will have to be swapped when we emit the assembler. */
6690 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6691 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6692 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6693 || GET_CODE (x
) == ROTATERT
))
6696 /* This operation is performed swapped, but since we only rely on the Z
6697 flag we don't need an additional mode. */
6698 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6699 && GET_CODE (x
) == NEG
6700 && (op
== EQ
|| op
== NE
))
6703 /* This is a special case that is used by combine to allow a
6704 comparison of a shifted byte load to be split into a zero-extend
6705 followed by a comparison of the shifted integer (only valid for
6706 equalities and unsigned inequalities). */
6707 if (GET_MODE (x
) == SImode
6708 && GET_CODE (x
) == ASHIFT
6709 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6710 && GET_CODE (XEXP (x
, 0)) == SUBREG
6711 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6712 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6713 && (op
== EQ
|| op
== NE
6714 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6715 && GET_CODE (y
) == CONST_INT
)
6718 /* A construct for a conditional compare, if the false arm contains
6719 0, then both conditions must be true, otherwise either condition
6720 must be true. Not all conditions are possible, so CCmode is
6721 returned if it can't be done. */
6722 if (GET_CODE (x
) == IF_THEN_ELSE
6723 && (XEXP (x
, 2) == const0_rtx
6724 || XEXP (x
, 2) == const1_rtx
)
6725 && COMPARISON_P (XEXP (x
, 0))
6726 && COMPARISON_P (XEXP (x
, 1)))
6727 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6728 INTVAL (XEXP (x
, 2)));
6730 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6731 if (GET_CODE (x
) == AND
6732 && COMPARISON_P (XEXP (x
, 0))
6733 && COMPARISON_P (XEXP (x
, 1)))
6734 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6737 if (GET_CODE (x
) == IOR
6738 && COMPARISON_P (XEXP (x
, 0))
6739 && COMPARISON_P (XEXP (x
, 1)))
6740 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6743 /* An operation (on Thumb) where we want to test for a single bit.
6744 This is done by shifting that bit up into the top bit of a
6745 scratch register; we can then branch on the sign bit. */
6747 && GET_MODE (x
) == SImode
6748 && (op
== EQ
|| op
== NE
)
6749 && (GET_CODE (x
) == ZERO_EXTRACT
))
6752 /* An operation that sets the condition codes as a side-effect, the
6753 V flag is not set correctly, so we can only use comparisons where
6754 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6756 if (GET_MODE (x
) == SImode
6758 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6759 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6760 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6761 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6762 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6763 || GET_CODE (x
) == LSHIFTRT
6764 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6765 || GET_CODE (x
) == ROTATERT
6766 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6769 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6772 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6773 && GET_CODE (x
) == PLUS
6774 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6780 /* X and Y are two things to compare using CODE. Emit the compare insn and
6781 return the rtx for register 0 in the proper mode. FP means this is a
6782 floating point compare: I don't think that it is needed on the arm. */
6784 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6786 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6787 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6789 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
6794 /* Generate a sequence of insns that will generate the correct return
6795 address mask depending on the physical architecture that the program
6798 arm_gen_return_addr_mask (void)
6800 rtx reg
= gen_reg_rtx (Pmode
);
6802 emit_insn (gen_return_addr_mask (reg
));
6807 arm_reload_in_hi (rtx
*operands
)
6809 rtx ref
= operands
[1];
6811 HOST_WIDE_INT offset
= 0;
6813 if (GET_CODE (ref
) == SUBREG
)
6815 offset
= SUBREG_BYTE (ref
);
6816 ref
= SUBREG_REG (ref
);
6819 if (GET_CODE (ref
) == REG
)
6821 /* We have a pseudo which has been spilt onto the stack; there
6822 are two cases here: the first where there is a simple
6823 stack-slot replacement and a second where the stack-slot is
6824 out of range, or is used as a subreg. */
6825 if (reg_equiv_mem
[REGNO (ref
)])
6827 ref
= reg_equiv_mem
[REGNO (ref
)];
6828 base
= find_replacement (&XEXP (ref
, 0));
6831 /* The slot is out of range, or was dressed up in a SUBREG. */
6832 base
= reg_equiv_address
[REGNO (ref
)];
6835 base
= find_replacement (&XEXP (ref
, 0));
6837 /* Handle the case where the address is too complex to be offset by 1. */
6838 if (GET_CODE (base
) == MINUS
6839 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6841 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6843 emit_set_insn (base_plus
, base
);
6846 else if (GET_CODE (base
) == PLUS
)
6848 /* The addend must be CONST_INT, or we would have dealt with it above. */
6849 HOST_WIDE_INT hi
, lo
;
6851 offset
+= INTVAL (XEXP (base
, 1));
6852 base
= XEXP (base
, 0);
6854 /* Rework the address into a legal sequence of insns. */
6855 /* Valid range for lo is -4095 -> 4095 */
6858 : -((-offset
) & 0xfff));
6860 /* Corner case, if lo is the max offset then we would be out of range
6861 once we have added the additional 1 below, so bump the msb into the
6862 pre-loading insn(s). */
6866 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6867 ^ (HOST_WIDE_INT
) 0x80000000)
6868 - (HOST_WIDE_INT
) 0x80000000);
6870 gcc_assert (hi
+ lo
== offset
);
6874 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6876 /* Get the base address; addsi3 knows how to handle constants
6877 that require more than one insn. */
6878 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6884 /* Operands[2] may overlap operands[0] (though it won't overlap
6885 operands[1]), that's why we asked for a DImode reg -- so we can
6886 use the bit that does not overlap. */
6887 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6888 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6890 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6892 emit_insn (gen_zero_extendqisi2 (scratch
,
6893 gen_rtx_MEM (QImode
,
6894 plus_constant (base
,
6896 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6897 gen_rtx_MEM (QImode
,
6898 plus_constant (base
,
6900 if (!BYTES_BIG_ENDIAN
)
6901 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6902 gen_rtx_IOR (SImode
,
6905 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6909 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6910 gen_rtx_IOR (SImode
,
6911 gen_rtx_ASHIFT (SImode
, scratch
,
6913 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
6916 /* Handle storing a half-word to memory during reload by synthesizing as two
6917 byte stores. Take care not to clobber the input values until after we
6918 have moved them somewhere safe. This code assumes that if the DImode
6919 scratch in operands[2] overlaps either the input value or output address
6920 in some way, then that value must die in this insn (we absolutely need
6921 two scratch registers for some corner cases). */
6923 arm_reload_out_hi (rtx
*operands
)
6925 rtx ref
= operands
[0];
6926 rtx outval
= operands
[1];
6928 HOST_WIDE_INT offset
= 0;
6930 if (GET_CODE (ref
) == SUBREG
)
6932 offset
= SUBREG_BYTE (ref
);
6933 ref
= SUBREG_REG (ref
);
6936 if (GET_CODE (ref
) == REG
)
6938 /* We have a pseudo which has been spilt onto the stack; there
6939 are two cases here: the first where there is a simple
6940 stack-slot replacement and a second where the stack-slot is
6941 out of range, or is used as a subreg. */
6942 if (reg_equiv_mem
[REGNO (ref
)])
6944 ref
= reg_equiv_mem
[REGNO (ref
)];
6945 base
= find_replacement (&XEXP (ref
, 0));
6948 /* The slot is out of range, or was dressed up in a SUBREG. */
6949 base
= reg_equiv_address
[REGNO (ref
)];
6952 base
= find_replacement (&XEXP (ref
, 0));
6954 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6956 /* Handle the case where the address is too complex to be offset by 1. */
6957 if (GET_CODE (base
) == MINUS
6958 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6960 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6962 /* Be careful not to destroy OUTVAL. */
6963 if (reg_overlap_mentioned_p (base_plus
, outval
))
6965 /* Updating base_plus might destroy outval, see if we can
6966 swap the scratch and base_plus. */
6967 if (!reg_overlap_mentioned_p (scratch
, outval
))
6970 scratch
= base_plus
;
6975 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6977 /* Be conservative and copy OUTVAL into the scratch now,
6978 this should only be necessary if outval is a subreg
6979 of something larger than a word. */
6980 /* XXX Might this clobber base? I can't see how it can,
6981 since scratch is known to overlap with OUTVAL, and
6982 must be wider than a word. */
6983 emit_insn (gen_movhi (scratch_hi
, outval
));
6984 outval
= scratch_hi
;
6988 emit_set_insn (base_plus
, base
);
6991 else if (GET_CODE (base
) == PLUS
)
6993 /* The addend must be CONST_INT, or we would have dealt with it above. */
6994 HOST_WIDE_INT hi
, lo
;
6996 offset
+= INTVAL (XEXP (base
, 1));
6997 base
= XEXP (base
, 0);
6999 /* Rework the address into a legal sequence of insns. */
7000 /* Valid range for lo is -4095 -> 4095 */
7003 : -((-offset
) & 0xfff));
7005 /* Corner case, if lo is the max offset then we would be out of range
7006 once we have added the additional 1 below, so bump the msb into the
7007 pre-loading insn(s). */
7011 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
7012 ^ (HOST_WIDE_INT
) 0x80000000)
7013 - (HOST_WIDE_INT
) 0x80000000);
7015 gcc_assert (hi
+ lo
== offset
);
7019 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7021 /* Be careful not to destroy OUTVAL. */
7022 if (reg_overlap_mentioned_p (base_plus
, outval
))
7024 /* Updating base_plus might destroy outval, see if we
7025 can swap the scratch and base_plus. */
7026 if (!reg_overlap_mentioned_p (scratch
, outval
))
7029 scratch
= base_plus
;
7034 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7036 /* Be conservative and copy outval into scratch now,
7037 this should only be necessary if outval is a
7038 subreg of something larger than a word. */
7039 /* XXX Might this clobber base? I can't see how it
7040 can, since scratch is known to overlap with
7042 emit_insn (gen_movhi (scratch_hi
, outval
));
7043 outval
= scratch_hi
;
7047 /* Get the base address; addsi3 knows how to handle constants
7048 that require more than one insn. */
7049 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7055 if (BYTES_BIG_ENDIAN
)
7057 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7058 plus_constant (base
, offset
+ 1)),
7059 gen_lowpart (QImode
, outval
)));
7060 emit_insn (gen_lshrsi3 (scratch
,
7061 gen_rtx_SUBREG (SImode
, outval
, 0),
7063 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7064 gen_lowpart (QImode
, scratch
)));
7068 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7069 gen_lowpart (QImode
, outval
)));
7070 emit_insn (gen_lshrsi3 (scratch
,
7071 gen_rtx_SUBREG (SImode
, outval
, 0),
7073 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7074 plus_constant (base
, offset
+ 1)),
7075 gen_lowpart (QImode
, scratch
)));
7079 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7080 (padded to the size of a word) should be passed in a register. */
7083 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7085 if (TARGET_AAPCS_BASED
)
7086 return must_pass_in_stack_var_size (mode
, type
);
7088 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7092 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7093 Return true if an argument passed on the stack should be padded upwards,
7094 i.e. if the least-significant byte has useful data.
7095 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7096 aggregate types are placed in the lowest memory address. */
7099 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7101 if (!TARGET_AAPCS_BASED
)
7102 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7104 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7111 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7112 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7113 byte of the register has useful data, and return the opposite if the
7114 most significant byte does.
7115 For AAPCS, small aggregates and small complex types are always padded
7119 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7120 tree type
, int first ATTRIBUTE_UNUSED
)
7122 if (TARGET_AAPCS_BASED
7124 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7125 && int_size_in_bytes (type
) <= 4)
7128 /* Otherwise, use default padding. */
7129 return !BYTES_BIG_ENDIAN
;
7133 /* Print a symbolic form of X to the debug file, F. */
7135 arm_print_value (FILE *f
, rtx x
)
7137 switch (GET_CODE (x
))
7140 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7144 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7152 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7154 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7155 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7163 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7167 fprintf (f
, "`%s'", XSTR (x
, 0));
7171 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7175 arm_print_value (f
, XEXP (x
, 0));
7179 arm_print_value (f
, XEXP (x
, 0));
7181 arm_print_value (f
, XEXP (x
, 1));
7189 fprintf (f
, "????");
7194 /* Routines for manipulation of the constant pool. */
7196 /* Arm instructions cannot load a large constant directly into a
7197 register; they have to come from a pc relative load. The constant
7198 must therefore be placed in the addressable range of the pc
7199 relative load. Depending on the precise pc relative load
7200 instruction the range is somewhere between 256 bytes and 4k. This
7201 means that we often have to dump a constant inside a function, and
7202 generate code to branch around it.
7204 It is important to minimize this, since the branches will slow
7205 things down and make the code larger.
7207 Normally we can hide the table after an existing unconditional
7208 branch so that there is no interruption of the flow, but in the
7209 worst case the code looks like this:
7227 We fix this by performing a scan after scheduling, which notices
7228 which instructions need to have their operands fetched from the
7229 constant table and builds the table.
7231 The algorithm starts by building a table of all the constants that
7232 need fixing up and all the natural barriers in the function (places
7233 where a constant table can be dropped without breaking the flow).
7234 For each fixup we note how far the pc-relative replacement will be
7235 able to reach and the offset of the instruction into the function.
7237 Having built the table we then group the fixes together to form
7238 tables that are as large as possible (subject to addressing
7239 constraints) and emit each table of constants after the last
7240 barrier that is within range of all the instructions in the group.
7241 If a group does not contain a barrier, then we forcibly create one
7242 by inserting a jump instruction into the flow. Once the table has
7243 been inserted, the insns are then modified to reference the
7244 relevant entry in the pool.
7246 Possible enhancements to the algorithm (not implemented) are:
7248 1) For some processors and object formats, there may be benefit in
7249 aligning the pools to the start of cache lines; this alignment
7250 would need to be taken into account when calculating addressability
7253 /* These typedefs are located at the start of this file, so that
7254 they can be used in the prototypes there. This comment is to
7255 remind readers of that fact so that the following structures
7256 can be understood more easily.
7258 typedef struct minipool_node Mnode;
7259 typedef struct minipool_fixup Mfix; */
7261 struct minipool_node
7263 /* Doubly linked chain of entries. */
7266 /* The maximum offset into the code that this entry can be placed. While
7267 pushing fixes for forward references, all entries are sorted in order
7268 of increasing max_address. */
7269 HOST_WIDE_INT max_address
;
7270 /* Similarly for an entry inserted for a backwards ref. */
7271 HOST_WIDE_INT min_address
;
7272 /* The number of fixes referencing this entry. This can become zero
7273 if we "unpush" an entry. In this case we ignore the entry when we
7274 come to emit the code. */
7276 /* The offset from the start of the minipool. */
7277 HOST_WIDE_INT offset
;
7278 /* The value in table. */
7280 /* The mode of value. */
7281 enum machine_mode mode
;
7282 /* The size of the value. With iWMMXt enabled
7283 sizes > 4 also imply an alignment of 8-bytes. */
7287 struct minipool_fixup
7291 HOST_WIDE_INT address
;
7293 enum machine_mode mode
;
7297 HOST_WIDE_INT forwards
;
7298 HOST_WIDE_INT backwards
;
7301 /* Fixes less than a word need padding out to a word boundary. */
7302 #define MINIPOOL_FIX_SIZE(mode) \
7303 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7305 static Mnode
* minipool_vector_head
;
7306 static Mnode
* minipool_vector_tail
;
7307 static rtx minipool_vector_label
;
7309 /* The linked list of all minipool fixes required for this function. */
7310 Mfix
* minipool_fix_head
;
7311 Mfix
* minipool_fix_tail
;
7312 /* The fix entry for the current minipool, once it has been placed. */
7313 Mfix
* minipool_barrier
;
7315 /* Determines if INSN is the start of a jump table. Returns the end
7316 of the TABLE or NULL_RTX. */
7318 is_jump_table (rtx insn
)
7322 if (GET_CODE (insn
) == JUMP_INSN
7323 && JUMP_LABEL (insn
) != NULL
7324 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7325 == next_real_insn (insn
))
7327 && GET_CODE (table
) == JUMP_INSN
7328 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7329 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7335 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7336 #define JUMP_TABLES_IN_TEXT_SECTION 0
7339 static HOST_WIDE_INT
7340 get_jump_table_size (rtx insn
)
7342 /* ADDR_VECs only take room if read-only data does into the text
7344 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
7346 rtx body
= PATTERN (insn
);
7347 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7349 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7355 /* Move a minipool fix MP from its current location to before MAX_MP.
7356 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7357 constraints may need updating. */
7359 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7360 HOST_WIDE_INT max_address
)
7362 /* The code below assumes these are different. */
7363 gcc_assert (mp
!= max_mp
);
7367 if (max_address
< mp
->max_address
)
7368 mp
->max_address
= max_address
;
7372 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7373 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7375 mp
->max_address
= max_address
;
7377 /* Unlink MP from its current position. Since max_mp is non-null,
7378 mp->prev must be non-null. */
7379 mp
->prev
->next
= mp
->next
;
7380 if (mp
->next
!= NULL
)
7381 mp
->next
->prev
= mp
->prev
;
7383 minipool_vector_tail
= mp
->prev
;
7385 /* Re-insert it before MAX_MP. */
7387 mp
->prev
= max_mp
->prev
;
7390 if (mp
->prev
!= NULL
)
7391 mp
->prev
->next
= mp
;
7393 minipool_vector_head
= mp
;
7396 /* Save the new entry. */
7399 /* Scan over the preceding entries and adjust their addresses as
7401 while (mp
->prev
!= NULL
7402 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7404 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7411 /* Add a constant to the minipool for a forward reference. Returns the
7412 node added or NULL if the constant will not fit in this pool. */
7414 add_minipool_forward_ref (Mfix
*fix
)
7416 /* If set, max_mp is the first pool_entry that has a lower
7417 constraint than the one we are trying to add. */
7418 Mnode
* max_mp
= NULL
;
7419 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7422 /* If this fix's address is greater than the address of the first
7423 entry, then we can't put the fix in this pool. We subtract the
7424 size of the current fix to ensure that if the table is fully
7425 packed we still have enough room to insert this value by shuffling
7426 the other fixes forwards. */
7427 if (minipool_vector_head
&&
7428 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7431 /* Scan the pool to see if a constant with the same value has
7432 already been added. While we are doing this, also note the
7433 location where we must insert the constant if it doesn't already
7435 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7437 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7438 && fix
->mode
== mp
->mode
7439 && (GET_CODE (fix
->value
) != CODE_LABEL
7440 || (CODE_LABEL_NUMBER (fix
->value
)
7441 == CODE_LABEL_NUMBER (mp
->value
)))
7442 && rtx_equal_p (fix
->value
, mp
->value
))
7444 /* More than one fix references this entry. */
7446 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7449 /* Note the insertion point if necessary. */
7451 && mp
->max_address
> max_address
)
7454 /* If we are inserting an 8-bytes aligned quantity and
7455 we have not already found an insertion point, then
7456 make sure that all such 8-byte aligned quantities are
7457 placed at the start of the pool. */
7458 if (ARM_DOUBLEWORD_ALIGN
7460 && fix
->fix_size
== 8
7461 && mp
->fix_size
!= 8)
7464 max_address
= mp
->max_address
;
7468 /* The value is not currently in the minipool, so we need to create
7469 a new entry for it. If MAX_MP is NULL, the entry will be put on
7470 the end of the list since the placement is less constrained than
7471 any existing entry. Otherwise, we insert the new fix before
7472 MAX_MP and, if necessary, adjust the constraints on the other
7474 mp
= xmalloc (sizeof (* mp
));
7475 mp
->fix_size
= fix
->fix_size
;
7476 mp
->mode
= fix
->mode
;
7477 mp
->value
= fix
->value
;
7479 /* Not yet required for a backwards ref. */
7480 mp
->min_address
= -65536;
7484 mp
->max_address
= max_address
;
7486 mp
->prev
= minipool_vector_tail
;
7488 if (mp
->prev
== NULL
)
7490 minipool_vector_head
= mp
;
7491 minipool_vector_label
= gen_label_rtx ();
7494 mp
->prev
->next
= mp
;
7496 minipool_vector_tail
= mp
;
7500 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7501 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7503 mp
->max_address
= max_address
;
7506 mp
->prev
= max_mp
->prev
;
7508 if (mp
->prev
!= NULL
)
7509 mp
->prev
->next
= mp
;
7511 minipool_vector_head
= mp
;
7514 /* Save the new entry. */
7517 /* Scan over the preceding entries and adjust their addresses as
7519 while (mp
->prev
!= NULL
7520 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7522 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7530 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7531 HOST_WIDE_INT min_address
)
7533 HOST_WIDE_INT offset
;
7535 /* The code below assumes these are different. */
7536 gcc_assert (mp
!= min_mp
);
7540 if (min_address
> mp
->min_address
)
7541 mp
->min_address
= min_address
;
7545 /* We will adjust this below if it is too loose. */
7546 mp
->min_address
= min_address
;
7548 /* Unlink MP from its current position. Since min_mp is non-null,
7549 mp->next must be non-null. */
7550 mp
->next
->prev
= mp
->prev
;
7551 if (mp
->prev
!= NULL
)
7552 mp
->prev
->next
= mp
->next
;
7554 minipool_vector_head
= mp
->next
;
7556 /* Reinsert it after MIN_MP. */
7558 mp
->next
= min_mp
->next
;
7560 if (mp
->next
!= NULL
)
7561 mp
->next
->prev
= mp
;
7563 minipool_vector_tail
= mp
;
7569 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7571 mp
->offset
= offset
;
7572 if (mp
->refcount
> 0)
7573 offset
+= mp
->fix_size
;
7575 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7576 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7582 /* Add a constant to the minipool for a backward reference. Returns the
7583 node added or NULL if the constant will not fit in this pool.
7585 Note that the code for insertion for a backwards reference can be
7586 somewhat confusing because the calculated offsets for each fix do
7587 not take into account the size of the pool (which is still under
7590 add_minipool_backward_ref (Mfix
*fix
)
7592 /* If set, min_mp is the last pool_entry that has a lower constraint
7593 than the one we are trying to add. */
7594 Mnode
*min_mp
= NULL
;
7595 /* This can be negative, since it is only a constraint. */
7596 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7599 /* If we can't reach the current pool from this insn, or if we can't
7600 insert this entry at the end of the pool without pushing other
7601 fixes out of range, then we don't try. This ensures that we
7602 can't fail later on. */
7603 if (min_address
>= minipool_barrier
->address
7604 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7605 >= minipool_barrier
->address
))
7608 /* Scan the pool to see if a constant with the same value has
7609 already been added. While we are doing this, also note the
7610 location where we must insert the constant if it doesn't already
7612 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7614 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7615 && fix
->mode
== mp
->mode
7616 && (GET_CODE (fix
->value
) != CODE_LABEL
7617 || (CODE_LABEL_NUMBER (fix
->value
)
7618 == CODE_LABEL_NUMBER (mp
->value
)))
7619 && rtx_equal_p (fix
->value
, mp
->value
)
7620 /* Check that there is enough slack to move this entry to the
7621 end of the table (this is conservative). */
7623 > (minipool_barrier
->address
7624 + minipool_vector_tail
->offset
7625 + minipool_vector_tail
->fix_size
)))
7628 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7632 mp
->min_address
+= fix
->fix_size
;
7635 /* Note the insertion point if necessary. */
7636 if (mp
->min_address
< min_address
)
7638 /* For now, we do not allow the insertion of 8-byte alignment
7639 requiring nodes anywhere but at the start of the pool. */
7640 if (ARM_DOUBLEWORD_ALIGN
7641 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7646 else if (mp
->max_address
7647 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7649 /* Inserting before this entry would push the fix beyond
7650 its maximum address (which can happen if we have
7651 re-located a forwards fix); force the new fix to come
7654 min_address
= mp
->min_address
+ fix
->fix_size
;
7656 /* If we are inserting an 8-bytes aligned quantity and
7657 we have not already found an insertion point, then
7658 make sure that all such 8-byte aligned quantities are
7659 placed at the start of the pool. */
7660 else if (ARM_DOUBLEWORD_ALIGN
7662 && fix
->fix_size
== 8
7663 && mp
->fix_size
< 8)
7666 min_address
= mp
->min_address
+ fix
->fix_size
;
7671 /* We need to create a new entry. */
7672 mp
= xmalloc (sizeof (* mp
));
7673 mp
->fix_size
= fix
->fix_size
;
7674 mp
->mode
= fix
->mode
;
7675 mp
->value
= fix
->value
;
7677 mp
->max_address
= minipool_barrier
->address
+ 65536;
7679 mp
->min_address
= min_address
;
7684 mp
->next
= minipool_vector_head
;
7686 if (mp
->next
== NULL
)
7688 minipool_vector_tail
= mp
;
7689 minipool_vector_label
= gen_label_rtx ();
7692 mp
->next
->prev
= mp
;
7694 minipool_vector_head
= mp
;
7698 mp
->next
= min_mp
->next
;
7702 if (mp
->next
!= NULL
)
7703 mp
->next
->prev
= mp
;
7705 minipool_vector_tail
= mp
;
7708 /* Save the new entry. */
7716 /* Scan over the following entries and adjust their offsets. */
7717 while (mp
->next
!= NULL
)
7719 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7720 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7723 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7725 mp
->next
->offset
= mp
->offset
;
7734 assign_minipool_offsets (Mfix
*barrier
)
7736 HOST_WIDE_INT offset
= 0;
7739 minipool_barrier
= barrier
;
7741 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7743 mp
->offset
= offset
;
7745 if (mp
->refcount
> 0)
7746 offset
+= mp
->fix_size
;
7750 /* Output the literal table */
7752 dump_minipool (rtx scan
)
7758 if (ARM_DOUBLEWORD_ALIGN
)
7759 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7760 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7768 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7769 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7771 scan
= emit_label_after (gen_label_rtx (), scan
);
7772 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7773 scan
= emit_label_after (minipool_vector_label
, scan
);
7775 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7777 if (mp
->refcount
> 0)
7782 ";; Offset %u, min %ld, max %ld ",
7783 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7784 (unsigned long) mp
->max_address
);
7785 arm_print_value (dump_file
, mp
->value
);
7786 fputc ('\n', dump_file
);
7789 switch (mp
->fix_size
)
7791 #ifdef HAVE_consttable_1
7793 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7797 #ifdef HAVE_consttable_2
7799 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7803 #ifdef HAVE_consttable_4
7805 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7809 #ifdef HAVE_consttable_8
7811 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7824 minipool_vector_head
= minipool_vector_tail
= NULL
;
7825 scan
= emit_insn_after (gen_consttable_end (), scan
);
7826 scan
= emit_barrier_after (scan
);
7829 /* Return the cost of forcibly inserting a barrier after INSN. */
7831 arm_barrier_cost (rtx insn
)
7833 /* Basing the location of the pool on the loop depth is preferable,
7834 but at the moment, the basic block information seems to be
7835 corrupt by this stage of the compilation. */
7837 rtx next
= next_nonnote_insn (insn
);
7839 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7842 switch (GET_CODE (insn
))
7845 /* It will always be better to place the table before the label, rather
7854 return base_cost
- 10;
7857 return base_cost
+ 10;
7861 /* Find the best place in the insn stream in the range
7862 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7863 Create the barrier by inserting a jump and add a new fix entry for
7866 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7868 HOST_WIDE_INT count
= 0;
7870 rtx from
= fix
->insn
;
7871 rtx selected
= from
;
7873 HOST_WIDE_INT selected_address
;
7875 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7876 rtx label
= gen_label_rtx ();
7878 selected_cost
= arm_barrier_cost (from
);
7879 selected_address
= fix
->address
;
7881 while (from
&& count
< max_count
)
7886 /* This code shouldn't have been called if there was a natural barrier
7888 gcc_assert (GET_CODE (from
) != BARRIER
);
7890 /* Count the length of this insn. */
7891 count
+= get_attr_length (from
);
7893 /* If there is a jump table, add its length. */
7894 tmp
= is_jump_table (from
);
7897 count
+= get_jump_table_size (tmp
);
7899 /* Jump tables aren't in a basic block, so base the cost on
7900 the dispatch insn. If we select this location, we will
7901 still put the pool after the table. */
7902 new_cost
= arm_barrier_cost (from
);
7904 if (count
< max_count
&& new_cost
<= selected_cost
)
7907 selected_cost
= new_cost
;
7908 selected_address
= fix
->address
+ count
;
7911 /* Continue after the dispatch table. */
7912 from
= NEXT_INSN (tmp
);
7916 new_cost
= arm_barrier_cost (from
);
7918 if (count
< max_count
&& new_cost
<= selected_cost
)
7921 selected_cost
= new_cost
;
7922 selected_address
= fix
->address
+ count
;
7925 from
= NEXT_INSN (from
);
7928 /* Create a new JUMP_INSN that branches around a barrier. */
7929 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7930 JUMP_LABEL (from
) = label
;
7931 barrier
= emit_barrier_after (from
);
7932 emit_label_after (label
, barrier
);
7934 /* Create a minipool barrier entry for the new barrier. */
7935 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7936 new_fix
->insn
= barrier
;
7937 new_fix
->address
= selected_address
;
7938 new_fix
->next
= fix
->next
;
7939 fix
->next
= new_fix
;
7944 /* Record that there is a natural barrier in the insn stream at
7947 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7949 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7952 fix
->address
= address
;
7955 if (minipool_fix_head
!= NULL
)
7956 minipool_fix_tail
->next
= fix
;
7958 minipool_fix_head
= fix
;
7960 minipool_fix_tail
= fix
;
7963 /* Record INSN, which will need fixing up to load a value from the
7964 minipool. ADDRESS is the offset of the insn since the start of the
7965 function; LOC is a pointer to the part of the insn which requires
7966 fixing; VALUE is the constant that must be loaded, which is of type
7969 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7970 enum machine_mode mode
, rtx value
)
7972 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7974 #ifdef AOF_ASSEMBLER
7975 /* PIC symbol references need to be converted into offsets into the
7977 /* XXX This shouldn't be done here. */
7978 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7979 value
= aof_pic_entry (value
);
7980 #endif /* AOF_ASSEMBLER */
7983 fix
->address
= address
;
7986 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7988 fix
->forwards
= get_attr_pool_range (insn
);
7989 fix
->backwards
= get_attr_neg_pool_range (insn
);
7990 fix
->minipool
= NULL
;
7992 /* If an insn doesn't have a range defined for it, then it isn't
7993 expecting to be reworked by this code. Better to stop now than
7994 to generate duff assembly code. */
7995 gcc_assert (fix
->forwards
|| fix
->backwards
);
7997 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7998 So there might be an empty word before the start of the pool.
7999 Hence we reduce the forward range by 4 to allow for this
8001 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
8007 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8008 GET_MODE_NAME (mode
),
8009 INSN_UID (insn
), (unsigned long) address
,
8010 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
8011 arm_print_value (dump_file
, fix
->value
);
8012 fprintf (dump_file
, "\n");
8015 /* Add it to the chain of fixes. */
8018 if (minipool_fix_head
!= NULL
)
8019 minipool_fix_tail
->next
= fix
;
8021 minipool_fix_head
= fix
;
8023 minipool_fix_tail
= fix
;
8026 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8027 Returns the number of insns needed, or 99 if we don't know how to
8030 arm_const_double_inline_cost (rtx val
)
8032 rtx lowpart
, highpart
;
8033 enum machine_mode mode
;
8035 mode
= GET_MODE (val
);
8037 if (mode
== VOIDmode
)
8040 gcc_assert (GET_MODE_SIZE (mode
) == 8);
8042 lowpart
= gen_lowpart (SImode
, val
);
8043 highpart
= gen_highpart_mode (SImode
, mode
, val
);
8045 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
8046 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
8048 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
8049 NULL_RTX
, NULL_RTX
, 0, 0)
8050 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
8051 NULL_RTX
, NULL_RTX
, 0, 0));
8054 /* Return true if it is worthwhile to split a 64-bit constant into two
8055 32-bit operations. This is the case if optimizing for size, or
8056 if we have load delay slots, or if one 32-bit part can be done with
8057 a single data operation. */
8059 arm_const_double_by_parts (rtx val
)
8061 enum machine_mode mode
= GET_MODE (val
);
8064 if (optimize_size
|| arm_ld_sched
)
8067 if (mode
== VOIDmode
)
8070 part
= gen_highpart_mode (SImode
, mode
, val
);
8072 gcc_assert (GET_CODE (part
) == CONST_INT
);
8074 if (const_ok_for_arm (INTVAL (part
))
8075 || const_ok_for_arm (~INTVAL (part
)))
8078 part
= gen_lowpart (SImode
, val
);
8080 gcc_assert (GET_CODE (part
) == CONST_INT
);
8082 if (const_ok_for_arm (INTVAL (part
))
8083 || const_ok_for_arm (~INTVAL (part
)))
8089 /* Scan INSN and note any of its operands that need fixing.
8090 If DO_PUSHES is false we do not actually push any of the fixups
8091 needed. The function returns TRUE if any fixups were needed/pushed.
8092 This is used by arm_memory_load_p() which needs to know about loads
8093 of constants that will be converted into minipool loads. */
8095 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8097 bool result
= false;
8100 extract_insn (insn
);
8102 if (!constrain_operands (1))
8103 fatal_insn_not_found (insn
);
8105 if (recog_data
.n_alternatives
== 0)
8108 /* Fill in recog_op_alt with information about the constraints of
8110 preprocess_constraints ();
8112 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8114 /* Things we need to fix can only occur in inputs. */
8115 if (recog_data
.operand_type
[opno
] != OP_IN
)
8118 /* If this alternative is a memory reference, then any mention
8119 of constants in this alternative is really to fool reload
8120 into allowing us to accept one there. We need to fix them up
8121 now so that we output the right code. */
8122 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8124 rtx op
= recog_data
.operand
[opno
];
8126 if (CONSTANT_P (op
))
8129 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8130 recog_data
.operand_mode
[opno
], op
);
8133 else if (GET_CODE (op
) == MEM
8134 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8135 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8139 rtx cop
= avoid_constant_pool_reference (op
);
8141 /* Casting the address of something to a mode narrower
8142 than a word can cause avoid_constant_pool_reference()
8143 to return the pool reference itself. That's no good to
8144 us here. Lets just hope that we can use the
8145 constant pool value directly. */
8147 cop
= get_pool_constant (XEXP (op
, 0));
8149 push_minipool_fix (insn
, address
,
8150 recog_data
.operand_loc
[opno
],
8151 recog_data
.operand_mode
[opno
], cop
);
8162 /* Gcc puts the pool in the wrong place for ARM, since we can only
8163 load addresses a limited distance around the pc. We do some
8164 special munging to move the constant pool values to the correct
8165 point in the code. */
8170 HOST_WIDE_INT address
= 0;
8173 minipool_fix_head
= minipool_fix_tail
= NULL
;
8175 /* The first insn must always be a note, or the code below won't
8176 scan it properly. */
8177 insn
= get_insns ();
8178 gcc_assert (GET_CODE (insn
) == NOTE
);
8180 /* Scan all the insns and record the operands that will need fixing. */
8181 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8183 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8184 && (arm_cirrus_insn_p (insn
)
8185 || GET_CODE (insn
) == JUMP_INSN
8186 || arm_memory_load_p (insn
)))
8187 cirrus_reorg (insn
);
8189 if (GET_CODE (insn
) == BARRIER
)
8190 push_minipool_barrier (insn
, address
);
8191 else if (INSN_P (insn
))
8195 note_invalid_constants (insn
, address
, true);
8196 address
+= get_attr_length (insn
);
8198 /* If the insn is a vector jump, add the size of the table
8199 and skip the table. */
8200 if ((table
= is_jump_table (insn
)) != NULL
)
8202 address
+= get_jump_table_size (table
);
8208 fix
= minipool_fix_head
;
8210 /* Now scan the fixups and perform the required changes. */
8215 Mfix
* last_added_fix
;
8216 Mfix
* last_barrier
= NULL
;
8219 /* Skip any further barriers before the next fix. */
8220 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8223 /* No more fixes. */
8227 last_added_fix
= NULL
;
8229 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8231 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8233 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8236 last_barrier
= ftmp
;
8238 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8241 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8244 /* If we found a barrier, drop back to that; any fixes that we
8245 could have reached but come after the barrier will now go in
8246 the next mini-pool. */
8247 if (last_barrier
!= NULL
)
8249 /* Reduce the refcount for those fixes that won't go into this
8251 for (fdel
= last_barrier
->next
;
8252 fdel
&& fdel
!= ftmp
;
8255 fdel
->minipool
->refcount
--;
8256 fdel
->minipool
= NULL
;
8259 ftmp
= last_barrier
;
8263 /* ftmp is first fix that we can't fit into this pool and
8264 there no natural barriers that we could use. Insert a
8265 new barrier in the code somewhere between the previous
8266 fix and this one, and arrange to jump around it. */
8267 HOST_WIDE_INT max_address
;
8269 /* The last item on the list of fixes must be a barrier, so
8270 we can never run off the end of the list of fixes without
8271 last_barrier being set. */
8274 max_address
= minipool_vector_head
->max_address
;
8275 /* Check that there isn't another fix that is in range that
8276 we couldn't fit into this pool because the pool was
8277 already too large: we need to put the pool before such an
8279 if (ftmp
->address
< max_address
)
8280 max_address
= ftmp
->address
;
8282 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8285 assign_minipool_offsets (last_barrier
);
8289 if (GET_CODE (ftmp
->insn
) != BARRIER
8290 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8297 /* Scan over the fixes we have identified for this pool, fixing them
8298 up and adding the constants to the pool itself. */
8299 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8300 this_fix
= this_fix
->next
)
8301 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8304 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8305 minipool_vector_label
),
8306 this_fix
->minipool
->offset
);
8307 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8310 dump_minipool (last_barrier
->insn
);
8314 /* From now on we must synthesize any constants that we can't handle
8315 directly. This can happen if the RTL gets split during final
8316 instruction generation. */
8317 after_arm_reorg
= 1;
8319 /* Free the minipool memory. */
8320 obstack_free (&minipool_obstack
, minipool_startobj
);
8323 /* Routines to output assembly language. */
8325 /* If the rtx is the correct value then return the string of the number.
8326 In this way we can ensure that valid double constants are generated even
8327 when cross compiling. */
8329 fp_immediate_constant (rtx x
)
8334 if (!fp_consts_inited
)
8337 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8338 for (i
= 0; i
< 8; i
++)
8339 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8340 return strings_fp
[i
];
8345 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8347 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8351 if (!fp_consts_inited
)
8354 for (i
= 0; i
< 8; i
++)
8355 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8356 return strings_fp
[i
];
8361 /* Output the operands of a LDM/STM instruction to STREAM.
8362 MASK is the ARM register set mask of which only bits 0-15 are important.
8363 REG is the base register, either the frame pointer or the stack pointer,
8364 INSTR is the possibly suffixed load or store instruction. */
8367 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8371 bool not_first
= FALSE
;
8373 fputc ('\t', stream
);
8374 asm_fprintf (stream
, instr
, reg
);
8375 fputs (", {", stream
);
8377 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8378 if (mask
& (1 << i
))
8381 fprintf (stream
, ", ");
8383 asm_fprintf (stream
, "%r", i
);
8387 fprintf (stream
, "}\n");
8391 /* Output a FLDMX instruction to STREAM.
8392 BASE if the register containing the address.
8393 REG and COUNT specify the register range.
8394 Extra registers may be added to avoid hardware bugs. */
8397 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8401 /* Workaround ARM10 VFPr1 bug. */
8402 if (count
== 2 && !arm_arch6
)
8409 fputc ('\t', stream
);
8410 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8412 for (i
= reg
; i
< reg
+ count
; i
++)
8415 fputs (", ", stream
);
8416 asm_fprintf (stream
, "d%d", i
);
8418 fputs ("}\n", stream
);
8423 /* Output the assembly for a store multiple. */
8426 vfp_output_fstmx (rtx
* operands
)
8433 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8434 p
= strlen (pattern
);
8436 gcc_assert (GET_CODE (operands
[1]) == REG
);
8438 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8439 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8441 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8443 strcpy (&pattern
[p
], "}");
8445 output_asm_insn (pattern
, operands
);
8450 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8451 number of bytes pushed. */
8454 vfp_emit_fstmx (int base_reg
, int count
)
8461 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8462 register pairs are stored by a store multiple insn. We avoid this
8463 by pushing an extra pair. */
8464 if (count
== 2 && !arm_arch6
)
8466 if (base_reg
== LAST_VFP_REGNUM
- 3)
8471 /* ??? The frame layout is implementation defined. We describe
8472 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8473 We really need some way of representing the whole block so that the
8474 unwinder can figure it out at runtime. */
8475 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8476 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8478 reg
= gen_rtx_REG (DFmode
, base_reg
);
8482 = gen_rtx_SET (VOIDmode
,
8483 gen_frame_mem (BLKmode
,
8484 gen_rtx_PRE_DEC (BLKmode
,
8485 stack_pointer_rtx
)),
8486 gen_rtx_UNSPEC (BLKmode
,
8490 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8491 plus_constant (stack_pointer_rtx
, -(count
* 8 + 4)));
8492 RTX_FRAME_RELATED_P (tmp
) = 1;
8493 XVECEXP (dwarf
, 0, 0) = tmp
;
8495 tmp
= gen_rtx_SET (VOIDmode
,
8496 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8498 RTX_FRAME_RELATED_P (tmp
) = 1;
8499 XVECEXP (dwarf
, 0, 1) = tmp
;
8501 for (i
= 1; i
< count
; i
++)
8503 reg
= gen_rtx_REG (DFmode
, base_reg
);
8505 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8507 tmp
= gen_rtx_SET (VOIDmode
,
8508 gen_frame_mem (DFmode
,
8509 plus_constant (stack_pointer_rtx
,
8512 RTX_FRAME_RELATED_P (tmp
) = 1;
8513 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8516 par
= emit_insn (par
);
8517 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8519 RTX_FRAME_RELATED_P (par
) = 1;
8521 return count
* 8 + 4;
8525 /* Output a 'call' insn. */
8527 output_call (rtx
*operands
)
8529 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8531 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8532 if (REGNO (operands
[0]) == LR_REGNUM
)
8534 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8535 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8538 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8540 if (TARGET_INTERWORK
|| arm_arch4t
)
8541 output_asm_insn ("bx%?\t%0", operands
);
8543 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8548 /* Output a 'call' insn that is a reference in memory. */
8550 output_call_mem (rtx
*operands
)
8552 if (TARGET_INTERWORK
&& !arm_arch5
)
8554 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8555 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8556 output_asm_insn ("bx%?\t%|ip", operands
);
8558 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8560 /* LR is used in the memory address. We load the address in the
8561 first instruction. It's safe to use IP as the target of the
8562 load since the call will kill it anyway. */
8563 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8565 output_asm_insn ("blx%?\t%|ip", operands
);
8568 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8570 output_asm_insn ("bx%?\t%|ip", operands
);
8572 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8577 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8578 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8585 /* Output a move from arm registers to an fpa registers.
8586 OPERANDS[0] is an fpa register.
8587 OPERANDS[1] is the first registers of an arm register pair. */
8589 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8591 int arm_reg0
= REGNO (operands
[1]);
8594 gcc_assert (arm_reg0
!= IP_REGNUM
);
8596 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8597 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8598 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8600 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8601 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8606 /* Output a move from an fpa register to arm registers.
8607 OPERANDS[0] is the first registers of an arm register pair.
8608 OPERANDS[1] is an fpa register. */
8610 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8612 int arm_reg0
= REGNO (operands
[0]);
8615 gcc_assert (arm_reg0
!= IP_REGNUM
);
8617 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8618 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8619 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8621 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8622 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8626 /* Output a move from arm registers to arm registers of a long double
8627 OPERANDS[0] is the destination.
8628 OPERANDS[1] is the source. */
8630 output_mov_long_double_arm_from_arm (rtx
*operands
)
8632 /* We have to be careful here because the two might overlap. */
8633 int dest_start
= REGNO (operands
[0]);
8634 int src_start
= REGNO (operands
[1]);
8638 if (dest_start
< src_start
)
8640 for (i
= 0; i
< 3; i
++)
8642 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8643 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8644 output_asm_insn ("mov%?\t%0, %1", ops
);
8649 for (i
= 2; i
>= 0; i
--)
8651 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8652 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8653 output_asm_insn ("mov%?\t%0, %1", ops
);
8661 /* Output a move from arm registers to an fpa registers.
8662 OPERANDS[0] is an fpa register.
8663 OPERANDS[1] is the first registers of an arm register pair. */
8665 output_mov_double_fpa_from_arm (rtx
*operands
)
8667 int arm_reg0
= REGNO (operands
[1]);
8670 gcc_assert (arm_reg0
!= IP_REGNUM
);
8672 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8673 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8674 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8675 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8679 /* Output a move from an fpa register to arm registers.
8680 OPERANDS[0] is the first registers of an arm register pair.
8681 OPERANDS[1] is an fpa register. */
8683 output_mov_double_arm_from_fpa (rtx
*operands
)
8685 int arm_reg0
= REGNO (operands
[0]);
8688 gcc_assert (arm_reg0
!= IP_REGNUM
);
8690 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8691 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8692 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8693 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8697 /* Output a move between double words.
8698 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8699 or MEM<-REG and all MEMs must be offsettable addresses. */
8701 output_move_double (rtx
*operands
)
8703 enum rtx_code code0
= GET_CODE (operands
[0]);
8704 enum rtx_code code1
= GET_CODE (operands
[1]);
8709 int reg0
= REGNO (operands
[0]);
8711 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8713 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8715 switch (GET_CODE (XEXP (operands
[1], 0)))
8718 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8722 gcc_assert (TARGET_LDRD
);
8723 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8727 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8731 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8735 gcc_assert (TARGET_LDRD
);
8736 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8741 otherops
[0] = operands
[0];
8742 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8743 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8745 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8747 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8749 /* Registers overlap so split out the increment. */
8750 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8751 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8754 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8758 /* We only allow constant increments, so this is safe. */
8759 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8765 output_asm_insn ("adr%?\t%0, %1", operands
);
8766 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8770 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8771 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8773 otherops
[0] = operands
[0];
8774 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8775 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8777 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8779 if (GET_CODE (otherops
[2]) == CONST_INT
)
8781 switch ((int) INTVAL (otherops
[2]))
8784 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8787 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8790 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8795 && (GET_CODE (otherops
[2]) == REG
8796 || (GET_CODE (otherops
[2]) == CONST_INT
8797 && INTVAL (otherops
[2]) > -256
8798 && INTVAL (otherops
[2]) < 256)))
8800 if (reg_overlap_mentioned_p (otherops
[0],
8803 /* Swap base and index registers over to
8804 avoid a conflict. */
8805 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8806 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8808 /* If both registers conflict, it will usually
8809 have been fixed by a splitter. */
8810 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8812 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8813 output_asm_insn ("ldr%?d\t%0, [%1]",
8817 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8821 if (GET_CODE (otherops
[2]) == CONST_INT
)
8823 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8824 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8826 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8829 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8832 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8834 return "ldm%?ia\t%0, %M0";
8838 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8839 /* Take care of overlapping base/data reg. */
8840 if (reg_mentioned_p (operands
[0], operands
[1]))
8842 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8843 output_asm_insn ("ldr%?\t%0, %1", operands
);
8847 output_asm_insn ("ldr%?\t%0, %1", operands
);
8848 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8855 /* Constraints should ensure this. */
8856 gcc_assert (code0
== MEM
&& code1
== REG
);
8857 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8859 switch (GET_CODE (XEXP (operands
[0], 0)))
8862 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8866 gcc_assert (TARGET_LDRD
);
8867 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8871 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8875 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8879 gcc_assert (TARGET_LDRD
);
8880 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8885 otherops
[0] = operands
[1];
8886 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8887 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8889 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8890 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8892 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8896 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8897 if (GET_CODE (otherops
[2]) == CONST_INT
)
8899 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8902 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8906 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8910 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8915 && (GET_CODE (otherops
[2]) == REG
8916 || (GET_CODE (otherops
[2]) == CONST_INT
8917 && INTVAL (otherops
[2]) > -256
8918 && INTVAL (otherops
[2]) < 256)))
8920 otherops
[0] = operands
[1];
8921 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8922 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8928 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8929 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8930 output_asm_insn ("str%?\t%1, %0", operands
);
8931 output_asm_insn ("str%?\t%1, %0", otherops
);
8938 /* Output an ADD r, s, #n where n may be too big for one instruction.
8939 If adding zero to one register, output nothing. */
8941 output_add_immediate (rtx
*operands
)
8943 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8945 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8948 output_multi_immediate (operands
,
8949 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8952 output_multi_immediate (operands
,
8953 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8960 /* Output a multiple immediate operation.
8961 OPERANDS is the vector of operands referred to in the output patterns.
8962 INSTR1 is the output pattern to use for the first constant.
8963 INSTR2 is the output pattern to use for subsequent constants.
8964 IMMED_OP is the index of the constant slot in OPERANDS.
8965 N is the constant value. */
8967 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8968 int immed_op
, HOST_WIDE_INT n
)
8970 #if HOST_BITS_PER_WIDE_INT > 32
8976 /* Quick and easy output. */
8977 operands
[immed_op
] = const0_rtx
;
8978 output_asm_insn (instr1
, operands
);
8983 const char * instr
= instr1
;
8985 /* Note that n is never zero here (which would give no output). */
8986 for (i
= 0; i
< 32; i
+= 2)
8990 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8991 output_asm_insn (instr
, operands
);
9001 /* Return the appropriate ARM instruction for the operation code.
9002 The returned result should not be overwritten. OP is the rtx of the
9003 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9006 arithmetic_instr (rtx op
, int shift_first_arg
)
9008 switch (GET_CODE (op
))
9014 return shift_first_arg
? "rsb" : "sub";
9030 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9031 for the operation code. The returned result should not be overwritten.
9032 OP is the rtx code of the shift.
9033 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9036 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
9039 enum rtx_code code
= GET_CODE (op
);
9041 switch (GET_CODE (XEXP (op
, 1)))
9049 *amountp
= INTVAL (XEXP (op
, 1));
9071 gcc_assert (*amountp
!= -1);
9072 *amountp
= 32 - *amountp
;
9081 /* We never have to worry about the amount being other than a
9082 power of 2, since this case can never be reloaded from a reg. */
9083 gcc_assert (*amountp
!= -1);
9084 *amountp
= int_log2 (*amountp
);
9093 /* This is not 100% correct, but follows from the desire to merge
9094 multiplication by a power of 2 with the recognizer for a
9095 shift. >=32 is not a valid shift for "asl", so we must try and
9096 output a shift that produces the correct arithmetical result.
9097 Using lsr #32 is identical except for the fact that the carry bit
9098 is not set correctly if we set the flags; but we never use the
9099 carry bit from such an operation, so we can ignore that. */
9100 if (code
== ROTATERT
)
9101 /* Rotate is just modulo 32. */
9103 else if (*amountp
!= (*amountp
& 31))
9110 /* Shifts of 0 are no-ops. */
9118 /* Obtain the shift from the POWER of two. */
9120 static HOST_WIDE_INT
9121 int_log2 (HOST_WIDE_INT power
)
9123 HOST_WIDE_INT shift
= 0;
9125 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9127 gcc_assert (shift
<= 31);
9134 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9135 because /bin/as is horribly restrictive. The judgement about
9136 whether or not each character is 'printable' (and can be output as
9137 is) or not (and must be printed with an octal escape) must be made
9138 with reference to the *host* character set -- the situation is
9139 similar to that discussed in the comments above pp_c_char in
9140 c-pretty-print.c. */
9142 #define MAX_ASCII_LEN 51
9145 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9150 fputs ("\t.ascii\t\"", stream
);
9152 for (i
= 0; i
< len
; i
++)
9156 if (len_so_far
>= MAX_ASCII_LEN
)
9158 fputs ("\"\n\t.ascii\t\"", stream
);
9164 if (c
== '\\' || c
== '\"')
9166 putc ('\\', stream
);
9174 fprintf (stream
, "\\%03o", c
);
9179 fputs ("\"\n", stream
);
9182 /* Compute the register save mask for registers 0 through 12
9183 inclusive. This code is used by arm_compute_save_reg_mask. */
9185 static unsigned long
9186 arm_compute_save_reg0_reg12_mask (void)
9188 unsigned long func_type
= arm_current_func_type ();
9189 unsigned long save_reg_mask
= 0;
9192 if (IS_INTERRUPT (func_type
))
9194 unsigned int max_reg
;
9195 /* Interrupt functions must not corrupt any registers,
9196 even call clobbered ones. If this is a leaf function
9197 we can just examine the registers used by the RTL, but
9198 otherwise we have to assume that whatever function is
9199 called might clobber anything, and so we have to save
9200 all the call-clobbered registers as well. */
9201 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9202 /* FIQ handlers have registers r8 - r12 banked, so
9203 we only need to check r0 - r7, Normal ISRs only
9204 bank r14 and r15, so we must check up to r12.
9205 r13 is the stack pointer which is always preserved,
9206 so we do not need to consider it here. */
9211 for (reg
= 0; reg
<= max_reg
; reg
++)
9212 if (regs_ever_live
[reg
]
9213 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9214 save_reg_mask
|= (1 << reg
);
9216 /* Also save the pic base register if necessary. */
9218 && !TARGET_SINGLE_PIC_BASE
9219 && arm_pic_register
!= INVALID_REGNUM
9220 && current_function_uses_pic_offset_table
)
9221 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9225 /* In the normal case we only need to save those registers
9226 which are call saved and which are used by this function. */
9227 for (reg
= 0; reg
<= 10; reg
++)
9228 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9229 save_reg_mask
|= (1 << reg
);
9231 /* Handle the frame pointer as a special case. */
9232 if (! TARGET_APCS_FRAME
9233 && ! frame_pointer_needed
9234 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9235 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9236 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9238 /* If we aren't loading the PIC register,
9239 don't stack it even though it may be live. */
9241 && !TARGET_SINGLE_PIC_BASE
9242 && arm_pic_register
!= INVALID_REGNUM
9243 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9244 || current_function_uses_pic_offset_table
))
9245 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9248 /* Save registers so the exception handler can modify them. */
9249 if (current_function_calls_eh_return
)
9255 reg
= EH_RETURN_DATA_REGNO (i
);
9256 if (reg
== INVALID_REGNUM
)
9258 save_reg_mask
|= 1 << reg
;
9262 return save_reg_mask
;
9265 /* Compute a bit mask of which registers need to be
9266 saved on the stack for the current function. */
9268 static unsigned long
9269 arm_compute_save_reg_mask (void)
9271 unsigned int save_reg_mask
= 0;
9272 unsigned long func_type
= arm_current_func_type ();
9274 if (IS_NAKED (func_type
))
9275 /* This should never really happen. */
9278 /* If we are creating a stack frame, then we must save the frame pointer,
9279 IP (which will hold the old stack pointer), LR and the PC. */
9280 if (frame_pointer_needed
)
9282 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9287 /* Volatile functions do not return, so there
9288 is no need to save any other registers. */
9289 if (IS_VOLATILE (func_type
))
9290 return save_reg_mask
;
9292 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9294 /* Decide if we need to save the link register.
9295 Interrupt routines have their own banked link register,
9296 so they never need to save it.
9297 Otherwise if we do not use the link register we do not need to save
9298 it. If we are pushing other registers onto the stack however, we
9299 can save an instruction in the epilogue by pushing the link register
9300 now and then popping it back into the PC. This incurs extra memory
9301 accesses though, so we only do it when optimizing for size, and only
9302 if we know that we will not need a fancy return sequence. */
9303 if (regs_ever_live
[LR_REGNUM
]
9306 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9307 && !current_function_calls_eh_return
))
9308 save_reg_mask
|= 1 << LR_REGNUM
;
9310 if (cfun
->machine
->lr_save_eliminated
)
9311 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9313 if (TARGET_REALLY_IWMMXT
9314 && ((bit_count (save_reg_mask
)
9315 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9319 /* The total number of registers that are going to be pushed
9320 onto the stack is odd. We need to ensure that the stack
9321 is 64-bit aligned before we start to save iWMMXt registers,
9322 and also before we start to create locals. (A local variable
9323 might be a double or long long which we will load/store using
9324 an iWMMXt instruction). Therefore we need to push another
9325 ARM register, so that the stack will be 64-bit aligned. We
9326 try to avoid using the arg registers (r0 -r3) as they might be
9327 used to pass values in a tail call. */
9328 for (reg
= 4; reg
<= 12; reg
++)
9329 if ((save_reg_mask
& (1 << reg
)) == 0)
9333 save_reg_mask
|= (1 << reg
);
9336 cfun
->machine
->sibcall_blocked
= 1;
9337 save_reg_mask
|= (1 << 3);
9341 return save_reg_mask
;
9345 /* Compute a bit mask of which registers need to be
9346 saved on the stack for the current function. */
9347 static unsigned long
9348 thumb_compute_save_reg_mask (void)
9354 for (reg
= 0; reg
< 12; reg
++)
9355 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9359 && !TARGET_SINGLE_PIC_BASE
9360 && arm_pic_register
!= INVALID_REGNUM
9361 && current_function_uses_pic_offset_table
)
9362 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9364 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9365 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9366 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9368 /* LR will also be pushed if any lo regs are pushed. */
9369 if (mask
& 0xff || thumb_force_lr_save ())
9370 mask
|= (1 << LR_REGNUM
);
9372 /* Make sure we have a low work register if we need one.
9373 We will need one if we are going to push a high register,
9374 but we are not currently intending to push a low register. */
9375 if ((mask
& 0xff) == 0
9376 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9378 /* Use thumb_find_work_register to choose which register
9379 we will use. If the register is live then we will
9380 have to push it. Use LAST_LO_REGNUM as our fallback
9381 choice for the register to select. */
9382 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9384 if (! call_used_regs
[reg
])
9392 /* Return the number of bytes required to save VFP registers. */
9394 arm_get_vfp_saved_size (void)
9401 /* Space for saved VFP registers. */
9402 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9405 for (regno
= FIRST_VFP_REGNUM
;
9406 regno
< LAST_VFP_REGNUM
;
9409 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9410 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9414 /* Workaround ARM10 VFPr1 bug. */
9415 if (count
== 2 && !arm_arch6
)
9417 saved
+= count
* 8 + 4;
9426 if (count
== 2 && !arm_arch6
)
9428 saved
+= count
* 8 + 4;
9435 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9436 everything bar the final return instruction. */
9438 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9440 char conditional
[10];
9443 unsigned long live_regs_mask
;
9444 unsigned long func_type
;
9445 arm_stack_offsets
*offsets
;
9447 func_type
= arm_current_func_type ();
9449 if (IS_NAKED (func_type
))
9452 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9454 /* If this function was declared non-returning, and we have
9455 found a tail call, then we have to trust that the called
9456 function won't return. */
9461 /* Otherwise, trap an attempted return by aborting. */
9463 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9465 assemble_external_libcall (ops
[1]);
9466 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9472 gcc_assert (!current_function_calls_alloca
|| really_return
);
9474 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9476 return_used_this_function
= 1;
9478 live_regs_mask
= arm_compute_save_reg_mask ();
9482 const char * return_reg
;
9484 /* If we do not have any special requirements for function exit
9485 (e.g. interworking, or ISR) then we can load the return address
9486 directly into the PC. Otherwise we must load it into LR. */
9488 && ! TARGET_INTERWORK
)
9489 return_reg
= reg_names
[PC_REGNUM
];
9491 return_reg
= reg_names
[LR_REGNUM
];
9493 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9495 /* There are three possible reasons for the IP register
9496 being saved. 1) a stack frame was created, in which case
9497 IP contains the old stack pointer, or 2) an ISR routine
9498 corrupted it, or 3) it was saved to align the stack on
9499 iWMMXt. In case 1, restore IP into SP, otherwise just
9501 if (frame_pointer_needed
)
9503 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9504 live_regs_mask
|= (1 << SP_REGNUM
);
9507 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9510 /* On some ARM architectures it is faster to use LDR rather than
9511 LDM to load a single register. On other architectures, the
9512 cost is the same. In 26 bit mode, or for exception handlers,
9513 we have to use LDM to load the PC so that the CPSR is also
9515 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9516 if (live_regs_mask
== (1U << reg
))
9519 if (reg
<= LAST_ARM_REGNUM
9520 && (reg
!= LR_REGNUM
9522 || ! IS_INTERRUPT (func_type
)))
9524 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9525 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9532 /* Generate the load multiple instruction to restore the
9533 registers. Note we can get here, even if
9534 frame_pointer_needed is true, but only if sp already
9535 points to the base of the saved core registers. */
9536 if (live_regs_mask
& (1 << SP_REGNUM
))
9538 unsigned HOST_WIDE_INT stack_adjust
;
9540 offsets
= arm_get_frame_offsets ();
9541 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9542 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9544 if (stack_adjust
&& arm_arch5
)
9545 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9548 /* If we can't use ldmib (SA110 bug),
9549 then try to pop r3 instead. */
9551 live_regs_mask
|= 1 << 3;
9552 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9556 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9558 p
= instr
+ strlen (instr
);
9560 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9561 if (live_regs_mask
& (1 << reg
))
9563 int l
= strlen (reg_names
[reg
]);
9569 memcpy (p
, ", ", 2);
9573 memcpy (p
, "%|", 2);
9574 memcpy (p
+ 2, reg_names
[reg
], l
);
9578 if (live_regs_mask
& (1 << LR_REGNUM
))
9580 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9581 /* If returning from an interrupt, restore the CPSR. */
9582 if (IS_INTERRUPT (func_type
))
9589 output_asm_insn (instr
, & operand
);
9591 /* See if we need to generate an extra instruction to
9592 perform the actual function return. */
9594 && func_type
!= ARM_FT_INTERWORKED
9595 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9597 /* The return has already been handled
9598 by loading the LR into the PC. */
9605 switch ((int) ARM_FUNC_TYPE (func_type
))
9609 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9612 case ARM_FT_INTERWORKED
:
9613 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9616 case ARM_FT_EXCEPTION
:
9617 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9621 /* Use bx if it's available. */
9622 if (arm_arch5
|| arm_arch4t
)
9623 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9625 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9629 output_asm_insn (instr
, & operand
);
9635 /* Write the function name into the code section, directly preceding
9636 the function prologue.
9638 Code will be output similar to this:
9640 .ascii "arm_poke_function_name", 0
9643 .word 0xff000000 + (t1 - t0)
9644 arm_poke_function_name
9646 stmfd sp!, {fp, ip, lr, pc}
9649 When performing a stack backtrace, code can inspect the value
9650 of 'pc' stored at 'fp' + 0. If the trace function then looks
9651 at location pc - 12 and the top 8 bits are set, then we know
9652 that there is a function name embedded immediately preceding this
9653 location and has length ((pc[-3]) & 0xff000000).
9655 We assume that pc is declared as a pointer to an unsigned long.
9657 It is of no benefit to output the function name if we are assembling
9658 a leaf function. These function types will not contain a stack
9659 backtrace structure, therefore it is not possible to determine the
9662 arm_poke_function_name (FILE *stream
, const char *name
)
9664 unsigned long alignlength
;
9665 unsigned long length
;
9668 length
= strlen (name
) + 1;
9669 alignlength
= ROUND_UP_WORD (length
);
9671 ASM_OUTPUT_ASCII (stream
, name
, length
);
9672 ASM_OUTPUT_ALIGN (stream
, 2);
9673 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9674 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9677 /* Place some comments into the assembler stream
9678 describing the current function. */
9680 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9682 unsigned long func_type
;
9686 thumb_output_function_prologue (f
, frame_size
);
9691 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9693 func_type
= arm_current_func_type ();
9695 switch ((int) ARM_FUNC_TYPE (func_type
))
9700 case ARM_FT_INTERWORKED
:
9701 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9704 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9707 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9709 case ARM_FT_EXCEPTION
:
9710 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9714 if (IS_NAKED (func_type
))
9715 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9717 if (IS_VOLATILE (func_type
))
9718 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9720 if (IS_NESTED (func_type
))
9721 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9723 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9724 current_function_args_size
,
9725 current_function_pretend_args_size
, frame_size
);
9727 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9728 frame_pointer_needed
,
9729 cfun
->machine
->uses_anonymous_args
);
9731 if (cfun
->machine
->lr_save_eliminated
)
9732 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9734 if (current_function_calls_eh_return
)
9735 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9737 #ifdef AOF_ASSEMBLER
9739 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9742 return_used_this_function
= 0;
9746 arm_output_epilogue (rtx sibling
)
9749 unsigned long saved_regs_mask
;
9750 unsigned long func_type
;
9751 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9752 frame that is $fp + 4 for a non-variadic function. */
9753 int floats_offset
= 0;
9755 FILE * f
= asm_out_file
;
9756 unsigned int lrm_count
= 0;
9757 int really_return
= (sibling
== NULL
);
9759 arm_stack_offsets
*offsets
;
9761 /* If we have already generated the return instruction
9762 then it is futile to generate anything else. */
9763 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9766 func_type
= arm_current_func_type ();
9768 if (IS_NAKED (func_type
))
9769 /* Naked functions don't have epilogues. */
9772 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9776 /* A volatile function should never return. Call abort. */
9777 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9778 assemble_external_libcall (op
);
9779 output_asm_insn ("bl\t%a0", &op
);
9784 /* If we are throwing an exception, then we really must be doing a
9785 return, so we can't tail-call. */
9786 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9788 offsets
= arm_get_frame_offsets ();
9789 saved_regs_mask
= arm_compute_save_reg_mask ();
9792 lrm_count
= bit_count (saved_regs_mask
);
9794 floats_offset
= offsets
->saved_args
;
9795 /* Compute how far away the floats will be. */
9796 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9797 if (saved_regs_mask
& (1 << reg
))
9800 if (frame_pointer_needed
)
9802 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9803 int vfp_offset
= offsets
->frame
;
9805 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9807 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9808 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9810 floats_offset
+= 12;
9811 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9812 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9817 start_reg
= LAST_FPA_REGNUM
;
9819 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9821 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9823 floats_offset
+= 12;
9825 /* We can't unstack more than four registers at once. */
9826 if (start_reg
- reg
== 3)
9828 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9829 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9830 start_reg
= reg
- 1;
9835 if (reg
!= start_reg
)
9836 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9837 reg
+ 1, start_reg
- reg
,
9838 FP_REGNUM
, floats_offset
- vfp_offset
);
9839 start_reg
= reg
- 1;
9843 /* Just in case the last register checked also needs unstacking. */
9844 if (reg
!= start_reg
)
9845 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9846 reg
+ 1, start_reg
- reg
,
9847 FP_REGNUM
, floats_offset
- vfp_offset
);
9850 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9854 /* The fldmx insn does not have base+offset addressing modes,
9855 so we use IP to hold the address. */
9856 saved_size
= arm_get_vfp_saved_size ();
9860 floats_offset
+= saved_size
;
9861 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9862 FP_REGNUM
, floats_offset
- vfp_offset
);
9864 start_reg
= FIRST_VFP_REGNUM
;
9865 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9867 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9868 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9870 if (start_reg
!= reg
)
9871 arm_output_fldmx (f
, IP_REGNUM
,
9872 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9873 (reg
- start_reg
) / 2);
9874 start_reg
= reg
+ 2;
9877 if (start_reg
!= reg
)
9878 arm_output_fldmx (f
, IP_REGNUM
,
9879 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9880 (reg
- start_reg
) / 2);
9885 /* The frame pointer is guaranteed to be non-double-word aligned.
9886 This is because it is set to (old_stack_pointer - 4) and the
9887 old_stack_pointer was double word aligned. Thus the offset to
9888 the iWMMXt registers to be loaded must also be non-double-word
9889 sized, so that the resultant address *is* double-word aligned.
9890 We can ignore floats_offset since that was already included in
9891 the live_regs_mask. */
9892 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9894 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9895 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9897 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9898 reg
, FP_REGNUM
, lrm_count
* 4);
9903 /* saved_regs_mask should contain the IP, which at the time of stack
9904 frame generation actually contains the old stack pointer. So a
9905 quick way to unwind the stack is just pop the IP register directly
9906 into the stack pointer. */
9907 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9908 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9909 saved_regs_mask
|= (1 << SP_REGNUM
);
9911 /* There are two registers left in saved_regs_mask - LR and PC. We
9912 only need to restore the LR register (the return address), but to
9913 save time we can load it directly into the PC, unless we need a
9914 special function exit sequence, or we are not really returning. */
9916 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9917 && !current_function_calls_eh_return
)
9918 /* Delete the LR from the register mask, so that the LR on
9919 the stack is loaded into the PC in the register mask. */
9920 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9922 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9924 /* We must use SP as the base register, because SP is one of the
9925 registers being restored. If an interrupt or page fault
9926 happens in the ldm instruction, the SP might or might not
9927 have been restored. That would be bad, as then SP will no
9928 longer indicate the safe area of stack, and we can get stack
9929 corruption. Using SP as the base register means that it will
9930 be reset correctly to the original value, should an interrupt
9931 occur. If the stack pointer already points at the right
9932 place, then omit the subtraction. */
9933 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9934 || current_function_calls_alloca
)
9935 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9936 4 * bit_count (saved_regs_mask
));
9937 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9939 if (IS_INTERRUPT (func_type
))
9940 /* Interrupt handlers will have pushed the
9941 IP onto the stack, so restore it now. */
9942 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9946 /* Restore stack pointer if necessary. */
9947 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9949 operands
[0] = operands
[1] = stack_pointer_rtx
;
9950 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9951 output_add_immediate (operands
);
9954 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9956 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9957 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9958 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9963 start_reg
= FIRST_FPA_REGNUM
;
9965 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9967 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9969 if (reg
- start_reg
== 3)
9971 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9972 start_reg
, SP_REGNUM
);
9973 start_reg
= reg
+ 1;
9978 if (reg
!= start_reg
)
9979 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9980 start_reg
, reg
- start_reg
,
9983 start_reg
= reg
+ 1;
9987 /* Just in case the last register checked also needs unstacking. */
9988 if (reg
!= start_reg
)
9989 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9990 start_reg
, reg
- start_reg
, SP_REGNUM
);
9993 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9995 start_reg
= FIRST_VFP_REGNUM
;
9996 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9998 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9999 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10001 if (start_reg
!= reg
)
10002 arm_output_fldmx (f
, SP_REGNUM
,
10003 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10004 (reg
- start_reg
) / 2);
10005 start_reg
= reg
+ 2;
10008 if (start_reg
!= reg
)
10009 arm_output_fldmx (f
, SP_REGNUM
,
10010 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10011 (reg
- start_reg
) / 2);
10014 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
10015 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10016 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
10018 /* If we can, restore the LR into the PC. */
10019 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
10021 && current_function_pretend_args_size
== 0
10022 && saved_regs_mask
& (1 << LR_REGNUM
)
10023 && !current_function_calls_eh_return
)
10025 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
10026 saved_regs_mask
|= (1 << PC_REGNUM
);
10029 /* Load the registers off the stack. If we only have one register
10030 to load use the LDR instruction - it is faster. */
10031 if (saved_regs_mask
== (1 << LR_REGNUM
))
10033 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
10035 else if (saved_regs_mask
)
10037 if (saved_regs_mask
& (1 << SP_REGNUM
))
10038 /* Note - write back to the stack register is not enabled
10039 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10040 in the list of registers and if we add writeback the
10041 instruction becomes UNPREDICTABLE. */
10042 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
10044 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
10047 if (current_function_pretend_args_size
)
10049 /* Unwind the pre-pushed regs. */
10050 operands
[0] = operands
[1] = stack_pointer_rtx
;
10051 operands
[2] = GEN_INT (current_function_pretend_args_size
);
10052 output_add_immediate (operands
);
10056 /* We may have already restored PC directly from the stack. */
10057 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10060 /* Stack adjustment for exception handler. */
10061 if (current_function_calls_eh_return
)
10062 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10063 ARM_EH_STACKADJ_REGNUM
);
10065 /* Generate the return instruction. */
10066 switch ((int) ARM_FUNC_TYPE (func_type
))
10070 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10073 case ARM_FT_EXCEPTION
:
10074 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10077 case ARM_FT_INTERWORKED
:
10078 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10082 if (arm_arch5
|| arm_arch4t
)
10083 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10085 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10093 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10094 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10096 arm_stack_offsets
*offsets
;
10102 /* Emit any call-via-reg trampolines that are needed for v4t support
10103 of call_reg and call_value_reg type insns. */
10104 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10106 rtx label
= cfun
->machine
->call_via
[regno
];
10110 switch_to_section (function_section (current_function_decl
));
10111 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10112 CODE_LABEL_NUMBER (label
));
10113 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10117 /* ??? Probably not safe to set this here, since it assumes that a
10118 function will be emitted as assembly immediately after we generate
10119 RTL for it. This does not happen for inline functions. */
10120 return_used_this_function
= 0;
10124 /* We need to take into account any stack-frame rounding. */
10125 offsets
= arm_get_frame_offsets ();
10127 gcc_assert (!use_return_insn (FALSE
, NULL
)
10128 || !return_used_this_function
10129 || offsets
->saved_regs
== offsets
->outgoing_args
10130 || frame_pointer_needed
);
10132 /* Reset the ARM-specific per-function variables. */
10133 after_arm_reorg
= 0;
10137 /* Generate and emit an insn that we will recognize as a push_multi.
10138 Unfortunately, since this insn does not reflect very well the actual
10139 semantics of the operation, we need to annotate the insn for the benefit
10140 of DWARF2 frame unwind information. */
10142 emit_multi_reg_push (unsigned long mask
)
10145 int num_dwarf_regs
;
10149 int dwarf_par_index
;
10152 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10153 if (mask
& (1 << i
))
10156 gcc_assert (num_regs
&& num_regs
<= 16);
10158 /* We don't record the PC in the dwarf frame information. */
10159 num_dwarf_regs
= num_regs
;
10160 if (mask
& (1 << PC_REGNUM
))
10163 /* For the body of the insn we are going to generate an UNSPEC in
10164 parallel with several USEs. This allows the insn to be recognized
10165 by the push_multi pattern in the arm.md file. The insn looks
10166 something like this:
10169 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10170 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10171 (use (reg:SI 11 fp))
10172 (use (reg:SI 12 ip))
10173 (use (reg:SI 14 lr))
10174 (use (reg:SI 15 pc))
10177 For the frame note however, we try to be more explicit and actually
10178 show each register being stored into the stack frame, plus a (single)
10179 decrement of the stack pointer. We do it this way in order to be
10180 friendly to the stack unwinding code, which only wants to see a single
10181 stack decrement per instruction. The RTL we generate for the note looks
10182 something like this:
10185 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10186 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10187 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10188 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10189 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10192 This sequence is used both by the code to support stack unwinding for
10193 exceptions handlers and the code to generate dwarf2 frame debugging. */
10195 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10196 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10197 dwarf_par_index
= 1;
10199 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10201 if (mask
& (1 << i
))
10203 reg
= gen_rtx_REG (SImode
, i
);
10205 XVECEXP (par
, 0, 0)
10206 = gen_rtx_SET (VOIDmode
,
10207 gen_frame_mem (BLKmode
,
10208 gen_rtx_PRE_DEC (BLKmode
,
10209 stack_pointer_rtx
)),
10210 gen_rtx_UNSPEC (BLKmode
,
10211 gen_rtvec (1, reg
),
10212 UNSPEC_PUSH_MULT
));
10214 if (i
!= PC_REGNUM
)
10216 tmp
= gen_rtx_SET (VOIDmode
,
10217 gen_frame_mem (SImode
, stack_pointer_rtx
),
10219 RTX_FRAME_RELATED_P (tmp
) = 1;
10220 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10228 for (j
= 1, i
++; j
< num_regs
; i
++)
10230 if (mask
& (1 << i
))
10232 reg
= gen_rtx_REG (SImode
, i
);
10234 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10236 if (i
!= PC_REGNUM
)
10239 = gen_rtx_SET (VOIDmode
,
10240 gen_frame_mem (SImode
,
10241 plus_constant (stack_pointer_rtx
,
10244 RTX_FRAME_RELATED_P (tmp
) = 1;
10245 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10252 par
= emit_insn (par
);
10254 tmp
= gen_rtx_SET (VOIDmode
,
10256 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
10257 RTX_FRAME_RELATED_P (tmp
) = 1;
10258 XVECEXP (dwarf
, 0, 0) = tmp
;
10260 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10265 /* Calculate the size of the return value that is passed in registers. */
10267 arm_size_return_regs (void)
10269 enum machine_mode mode
;
10271 if (current_function_return_rtx
!= 0)
10272 mode
= GET_MODE (current_function_return_rtx
);
10274 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10276 return GET_MODE_SIZE (mode
);
10280 emit_sfm (int base_reg
, int count
)
10287 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10288 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10290 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10292 XVECEXP (par
, 0, 0)
10293 = gen_rtx_SET (VOIDmode
,
10294 gen_frame_mem (BLKmode
,
10295 gen_rtx_PRE_DEC (BLKmode
,
10296 stack_pointer_rtx
)),
10297 gen_rtx_UNSPEC (BLKmode
,
10298 gen_rtvec (1, reg
),
10299 UNSPEC_PUSH_MULT
));
10300 tmp
= gen_rtx_SET (VOIDmode
,
10301 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10302 RTX_FRAME_RELATED_P (tmp
) = 1;
10303 XVECEXP (dwarf
, 0, 1) = tmp
;
10305 for (i
= 1; i
< count
; i
++)
10307 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10308 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10310 tmp
= gen_rtx_SET (VOIDmode
,
10311 gen_frame_mem (XFmode
,
10312 plus_constant (stack_pointer_rtx
,
10315 RTX_FRAME_RELATED_P (tmp
) = 1;
10316 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10319 tmp
= gen_rtx_SET (VOIDmode
,
10321 plus_constant (stack_pointer_rtx
, -12 * count
));
10323 RTX_FRAME_RELATED_P (tmp
) = 1;
10324 XVECEXP (dwarf
, 0, 0) = tmp
;
10326 par
= emit_insn (par
);
10327 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10333 /* Return true if the current function needs to save/restore LR. */
10336 thumb_force_lr_save (void)
10338 return !cfun
->machine
->lr_save_eliminated
10339 && (!leaf_function_p ()
10340 || thumb_far_jump_used_p ()
10341 || regs_ever_live
[LR_REGNUM
]);
10345 /* Compute the distance from register FROM to register TO.
10346 These can be the arg pointer (26), the soft frame pointer (25),
10347 the stack pointer (13) or the hard frame pointer (11).
10348 In thumb mode r7 is used as the soft frame pointer, if needed.
10349 Typical stack layout looks like this:
10351 old stack pointer -> | |
10354 | | saved arguments for
10355 | | vararg functions
10358 hard FP & arg pointer -> | | \
10366 soft frame pointer -> | | /
10371 locals base pointer -> | | /
10376 current stack pointer -> | | /
10379 For a given function some or all of these stack components
10380 may not be needed, giving rise to the possibility of
10381 eliminating some of the registers.
10383 The values returned by this function must reflect the behavior
10384 of arm_expand_prologue() and arm_compute_save_reg_mask().
10386 The sign of the number returned reflects the direction of stack
10387 growth, so the values are positive for all eliminations except
10388 from the soft frame pointer to the hard frame pointer.
10390 SFP may point just inside the local variables block to ensure correct
10394 /* Calculate stack offsets. These are used to calculate register elimination
10395 offsets and in prologue/epilogue code. */
10397 static arm_stack_offsets
*
10398 arm_get_frame_offsets (void)
10400 struct arm_stack_offsets
*offsets
;
10401 unsigned long func_type
;
10404 HOST_WIDE_INT frame_size
;
10406 offsets
= &cfun
->machine
->stack_offsets
;
10408 /* We need to know if we are a leaf function. Unfortunately, it
10409 is possible to be called after start_sequence has been called,
10410 which causes get_insns to return the insns for the sequence,
10411 not the function, which will cause leaf_function_p to return
10412 the incorrect result.
10414 to know about leaf functions once reload has completed, and the
10415 frame size cannot be changed after that time, so we can safely
10416 use the cached value. */
10418 if (reload_completed
)
10421 /* Initially this is the size of the local variables. It will translated
10422 into an offset once we have determined the size of preceding data. */
10423 frame_size
= ROUND_UP_WORD (get_frame_size ());
10425 leaf
= leaf_function_p ();
10427 /* Space for variadic functions. */
10428 offsets
->saved_args
= current_function_pretend_args_size
;
10430 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10434 unsigned int regno
;
10436 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10438 /* We know that SP will be doubleword aligned on entry, and we must
10439 preserve that condition at any subroutine call. We also require the
10440 soft frame pointer to be doubleword aligned. */
10442 if (TARGET_REALLY_IWMMXT
)
10444 /* Check for the call-saved iWMMXt registers. */
10445 for (regno
= FIRST_IWMMXT_REGNUM
;
10446 regno
<= LAST_IWMMXT_REGNUM
;
10448 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10452 func_type
= arm_current_func_type ();
10453 if (! IS_VOLATILE (func_type
))
10455 /* Space for saved FPA registers. */
10456 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10457 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10460 /* Space for saved VFP registers. */
10461 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10462 saved
+= arm_get_vfp_saved_size ();
10465 else /* TARGET_THUMB */
10467 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10468 if (TARGET_BACKTRACE
)
10472 /* Saved registers include the stack frame. */
10473 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10474 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10475 /* A leaf function does not need any stack alignment if it has nothing
10477 if (leaf
&& frame_size
== 0)
10479 offsets
->outgoing_args
= offsets
->soft_frame
;
10483 /* Ensure SFP has the correct alignment. */
10484 if (ARM_DOUBLEWORD_ALIGN
10485 && (offsets
->soft_frame
& 7))
10486 offsets
->soft_frame
+= 4;
10488 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10489 offsets
->outgoing_args
= (offsets
->locals_base
10490 + current_function_outgoing_args_size
);
10492 if (ARM_DOUBLEWORD_ALIGN
)
10494 /* Ensure SP remains doubleword aligned. */
10495 if (offsets
->outgoing_args
& 7)
10496 offsets
->outgoing_args
+= 4;
10497 gcc_assert (!(offsets
->outgoing_args
& 7));
10504 /* Calculate the relative offsets for the different stack pointers. Positive
10505 offsets are in the direction of stack growth. */
10508 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10510 arm_stack_offsets
*offsets
;
10512 offsets
= arm_get_frame_offsets ();
10514 /* OK, now we have enough information to compute the distances.
10515 There must be an entry in these switch tables for each pair
10516 of registers in ELIMINABLE_REGS, even if some of the entries
10517 seem to be redundant or useless. */
10520 case ARG_POINTER_REGNUM
:
10523 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10526 case FRAME_POINTER_REGNUM
:
10527 /* This is the reverse of the soft frame pointer
10528 to hard frame pointer elimination below. */
10529 return offsets
->soft_frame
- offsets
->saved_args
;
10531 case ARM_HARD_FRAME_POINTER_REGNUM
:
10532 /* If there is no stack frame then the hard
10533 frame pointer and the arg pointer coincide. */
10534 if (offsets
->frame
== offsets
->saved_regs
)
10536 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10537 return (frame_pointer_needed
10538 && cfun
->static_chain_decl
!= NULL
10539 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10541 case STACK_POINTER_REGNUM
:
10542 /* If nothing has been pushed on the stack at all
10543 then this will return -4. This *is* correct! */
10544 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10547 gcc_unreachable ();
10549 gcc_unreachable ();
10551 case FRAME_POINTER_REGNUM
:
10554 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10557 case ARM_HARD_FRAME_POINTER_REGNUM
:
10558 /* The hard frame pointer points to the top entry in the
10559 stack frame. The soft frame pointer to the bottom entry
10560 in the stack frame. If there is no stack frame at all,
10561 then they are identical. */
10563 return offsets
->frame
- offsets
->soft_frame
;
10565 case STACK_POINTER_REGNUM
:
10566 return offsets
->outgoing_args
- offsets
->soft_frame
;
10569 gcc_unreachable ();
10571 gcc_unreachable ();
10574 /* You cannot eliminate from the stack pointer.
10575 In theory you could eliminate from the hard frame
10576 pointer to the stack pointer, but this will never
10577 happen, since if a stack frame is not needed the
10578 hard frame pointer will never be used. */
10579 gcc_unreachable ();
10584 /* Generate the prologue instructions for entry into an ARM function. */
10586 arm_expand_prologue (void)
10592 unsigned long live_regs_mask
;
10593 unsigned long func_type
;
10595 int saved_pretend_args
= 0;
10596 int saved_regs
= 0;
10597 unsigned HOST_WIDE_INT args_to_push
;
10598 arm_stack_offsets
*offsets
;
10600 func_type
= arm_current_func_type ();
10602 /* Naked functions don't have prologues. */
10603 if (IS_NAKED (func_type
))
10606 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10607 args_to_push
= current_function_pretend_args_size
;
10609 /* Compute which register we will have to save onto the stack. */
10610 live_regs_mask
= arm_compute_save_reg_mask ();
10612 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10614 if (frame_pointer_needed
)
10616 if (IS_INTERRUPT (func_type
))
10618 /* Interrupt functions must not corrupt any registers.
10619 Creating a frame pointer however, corrupts the IP
10620 register, so we must push it first. */
10621 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10623 /* Do not set RTX_FRAME_RELATED_P on this insn.
10624 The dwarf stack unwinding code only wants to see one
10625 stack decrement per function, and this is not it. If
10626 this instruction is labeled as being part of the frame
10627 creation sequence then dwarf2out_frame_debug_expr will
10628 die when it encounters the assignment of IP to FP
10629 later on, since the use of SP here establishes SP as
10630 the CFA register and not IP.
10632 Anyway this instruction is not really part of the stack
10633 frame creation although it is part of the prologue. */
10635 else if (IS_NESTED (func_type
))
10637 /* The Static chain register is the same as the IP register
10638 used as a scratch register during stack frame creation.
10639 To get around this need to find somewhere to store IP
10640 whilst the frame is being created. We try the following
10643 1. The last argument register.
10644 2. A slot on the stack above the frame. (This only
10645 works if the function is not a varargs function).
10646 3. Register r3, after pushing the argument registers
10649 Note - we only need to tell the dwarf2 backend about the SP
10650 adjustment in the second variant; the static chain register
10651 doesn't need to be unwound, as it doesn't contain a value
10652 inherited from the caller. */
10654 if (regs_ever_live
[3] == 0)
10655 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10656 else if (args_to_push
== 0)
10660 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10661 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
10664 /* Just tell the dwarf backend that we adjusted SP. */
10665 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10666 plus_constant (stack_pointer_rtx
,
10668 RTX_FRAME_RELATED_P (insn
) = 1;
10669 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10670 dwarf
, REG_NOTES (insn
));
10674 /* Store the args on the stack. */
10675 if (cfun
->machine
->uses_anonymous_args
)
10676 insn
= emit_multi_reg_push
10677 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10680 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10681 GEN_INT (- args_to_push
)));
10683 RTX_FRAME_RELATED_P (insn
) = 1;
10685 saved_pretend_args
= 1;
10686 fp_offset
= args_to_push
;
10689 /* Now reuse r3 to preserve IP. */
10690 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10694 insn
= emit_set_insn (ip_rtx
,
10695 plus_constant (stack_pointer_rtx
, fp_offset
));
10696 RTX_FRAME_RELATED_P (insn
) = 1;
10701 /* Push the argument registers, or reserve space for them. */
10702 if (cfun
->machine
->uses_anonymous_args
)
10703 insn
= emit_multi_reg_push
10704 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10707 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10708 GEN_INT (- args_to_push
)));
10709 RTX_FRAME_RELATED_P (insn
) = 1;
10712 /* If this is an interrupt service routine, and the link register
10713 is going to be pushed, and we are not creating a stack frame,
10714 (which would involve an extra push of IP and a pop in the epilogue)
10715 subtracting four from LR now will mean that the function return
10716 can be done with a single instruction. */
10717 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10718 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10719 && ! frame_pointer_needed
)
10721 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
10723 emit_set_insn (lr
, plus_constant (lr
, -4));
10726 if (live_regs_mask
)
10728 insn
= emit_multi_reg_push (live_regs_mask
);
10729 saved_regs
+= bit_count (live_regs_mask
) * 4;
10730 RTX_FRAME_RELATED_P (insn
) = 1;
10734 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10735 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10737 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10738 insn
= gen_frame_mem (V2SImode
, insn
);
10739 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
10740 RTX_FRAME_RELATED_P (insn
) = 1;
10744 if (! IS_VOLATILE (func_type
))
10748 /* Save any floating point call-saved registers used by this
10750 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10752 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10753 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10755 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10756 insn
= gen_frame_mem (XFmode
, insn
);
10757 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
10758 RTX_FRAME_RELATED_P (insn
) = 1;
10764 start_reg
= LAST_FPA_REGNUM
;
10766 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10768 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10770 if (start_reg
- reg
== 3)
10772 insn
= emit_sfm (reg
, 4);
10773 RTX_FRAME_RELATED_P (insn
) = 1;
10775 start_reg
= reg
- 1;
10780 if (start_reg
!= reg
)
10782 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10783 RTX_FRAME_RELATED_P (insn
) = 1;
10784 saved_regs
+= (start_reg
- reg
) * 12;
10786 start_reg
= reg
- 1;
10790 if (start_reg
!= reg
)
10792 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10793 saved_regs
+= (start_reg
- reg
) * 12;
10794 RTX_FRAME_RELATED_P (insn
) = 1;
10797 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10799 start_reg
= FIRST_VFP_REGNUM
;
10801 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10803 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10804 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10806 if (start_reg
!= reg
)
10807 saved_regs
+= vfp_emit_fstmx (start_reg
,
10808 (reg
- start_reg
) / 2);
10809 start_reg
= reg
+ 2;
10812 if (start_reg
!= reg
)
10813 saved_regs
+= vfp_emit_fstmx (start_reg
,
10814 (reg
- start_reg
) / 2);
10818 if (frame_pointer_needed
)
10820 /* Create the new frame pointer. */
10821 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10822 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10823 RTX_FRAME_RELATED_P (insn
) = 1;
10825 if (IS_NESTED (func_type
))
10827 /* Recover the static chain register. */
10828 if (regs_ever_live
[3] == 0
10829 || saved_pretend_args
)
10830 insn
= gen_rtx_REG (SImode
, 3);
10831 else /* if (current_function_pretend_args_size == 0) */
10833 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
10834 insn
= gen_frame_mem (SImode
, insn
);
10837 emit_set_insn (ip_rtx
, insn
);
10838 /* Add a USE to stop propagate_one_insn() from barfing. */
10839 emit_insn (gen_prologue_use (ip_rtx
));
10843 offsets
= arm_get_frame_offsets ();
10844 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10846 /* This add can produce multiple insns for a large constant, so we
10847 need to get tricky. */
10848 rtx last
= get_last_insn ();
10850 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10851 - offsets
->outgoing_args
);
10853 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10857 last
= last
? NEXT_INSN (last
) : get_insns ();
10858 RTX_FRAME_RELATED_P (last
) = 1;
10860 while (last
!= insn
);
10862 /* If the frame pointer is needed, emit a special barrier that
10863 will prevent the scheduler from moving stores to the frame
10864 before the stack adjustment. */
10865 if (frame_pointer_needed
)
10866 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10867 hard_frame_pointer_rtx
));
10871 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
10872 arm_load_pic_register (0UL);
10874 /* If we are profiling, make sure no instructions are scheduled before
10875 the call to mcount. Similarly if the user has requested no
10876 scheduling in the prolog. Similarly if we want non-call exceptions
10877 using the EABI unwinder, to prevent faulting instructions from being
10878 swapped with a stack adjustment. */
10879 if (current_function_profile
|| !TARGET_SCHED_PROLOG
10880 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
10881 emit_insn (gen_blockage ());
10883 /* If the link register is being kept alive, with the return address in it,
10884 then make sure that it does not get reused by the ce2 pass. */
10885 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10887 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10888 cfun
->machine
->lr_save_eliminated
= 1;
10892 /* If CODE is 'd', then the X is a condition operand and the instruction
10893 should only be executed if the condition is true.
10894 if CODE is 'D', then the X is a condition operand and the instruction
10895 should only be executed if the condition is false: however, if the mode
10896 of the comparison is CCFPEmode, then always execute the instruction -- we
10897 do this because in these circumstances !GE does not necessarily imply LT;
10898 in these cases the instruction pattern will take care to make sure that
10899 an instruction containing %d will follow, thereby undoing the effects of
10900 doing this instruction unconditionally.
10901 If CODE is 'N' then X is a floating point operand that must be negated
10903 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10904 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10906 arm_print_operand (FILE *stream
, rtx x
, int code
)
10911 fputs (ASM_COMMENT_START
, stream
);
10915 fputs (user_label_prefix
, stream
);
10919 fputs (REGISTER_PREFIX
, stream
);
10923 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10927 output_operand_lossage ("predicated Thumb instruction");
10930 if (current_insn_predicate
!= NULL
)
10932 output_operand_lossage
10933 ("predicated instruction in conditional sequence");
10937 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10939 else if (current_insn_predicate
)
10941 enum arm_cond_code code
;
10945 output_operand_lossage ("predicated Thumb instruction");
10949 code
= get_arm_condition_code (current_insn_predicate
);
10950 fputs (arm_condition_codes
[code
], stream
);
10957 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10958 r
= REAL_VALUE_NEGATE (r
);
10959 fprintf (stream
, "%s", fp_const_from_val (&r
));
10964 if (GET_CODE (x
) == CONST_INT
)
10967 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10968 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10972 putc ('~', stream
);
10973 output_addr_const (stream
, x
);
10978 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10981 /* Truncate Cirrus shift counts. */
10983 if (GET_CODE (x
) == CONST_INT
)
10985 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10988 arm_print_operand (stream
, x
, 0);
10992 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10998 const char * shift
= shift_op (x
, &val
);
11002 fprintf (stream
, ", %s ", shift_op (x
, &val
));
11004 arm_print_operand (stream
, XEXP (x
, 1), 0);
11006 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
11011 /* An explanation of the 'Q', 'R' and 'H' register operands:
11013 In a pair of registers containing a DI or DF value the 'Q'
11014 operand returns the register number of the register containing
11015 the least significant part of the value. The 'R' operand returns
11016 the register number of the register containing the most
11017 significant part of the value.
11019 The 'H' operand returns the higher of the two register numbers.
11020 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11021 same as the 'Q' operand, since the most significant part of the
11022 value is held in the lower number register. The reverse is true
11023 on systems where WORDS_BIG_ENDIAN is false.
11025 The purpose of these operands is to distinguish between cases
11026 where the endian-ness of the values is important (for example
11027 when they are added together), and cases where the endian-ness
11028 is irrelevant, but the order of register operations is important.
11029 For example when loading a value from memory into a register
11030 pair, the endian-ness does not matter. Provided that the value
11031 from the lower memory address is put into the lower numbered
11032 register, and the value from the higher address is put into the
11033 higher numbered register, the load will work regardless of whether
11034 the value being loaded is big-wordian or little-wordian. The
11035 order of the two register loads can matter however, if the address
11036 of the memory location is actually held in one of the registers
11037 being overwritten by the load. */
11039 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11041 output_operand_lossage ("invalid operand for code '%c'", code
);
11045 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11049 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11051 output_operand_lossage ("invalid operand for code '%c'", code
);
11055 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11059 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11061 output_operand_lossage ("invalid operand for code '%c'", code
);
11065 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11069 asm_fprintf (stream
, "%r",
11070 GET_CODE (XEXP (x
, 0)) == REG
11071 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11075 asm_fprintf (stream
, "{%r-%r}",
11077 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11081 /* CONST_TRUE_RTX means always -- that's the default. */
11082 if (x
== const_true_rtx
)
11085 if (!COMPARISON_P (x
))
11087 output_operand_lossage ("invalid operand for code '%c'", code
);
11091 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11096 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11097 want to do that. */
11098 if (x
== const_true_rtx
)
11100 output_operand_lossage ("instruction never exectued");
11103 if (!COMPARISON_P (x
))
11105 output_operand_lossage ("invalid operand for code '%c'", code
);
11109 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11110 (get_arm_condition_code (x
))],
11114 /* Cirrus registers can be accessed in a variety of ways:
11115 single floating point (f)
11116 double floating point (d)
11118 64bit integer (dx). */
11119 case 'W': /* Cirrus register in F mode. */
11120 case 'X': /* Cirrus register in D mode. */
11121 case 'Y': /* Cirrus register in FX mode. */
11122 case 'Z': /* Cirrus register in DX mode. */
11123 gcc_assert (GET_CODE (x
) == REG
11124 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11126 fprintf (stream
, "mv%s%s",
11128 : code
== 'X' ? "d"
11129 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11133 /* Print cirrus register in the mode specified by the register's mode. */
11136 int mode
= GET_MODE (x
);
11138 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11140 output_operand_lossage ("invalid operand for code '%c'", code
);
11144 fprintf (stream
, "mv%s%s",
11145 mode
== DFmode
? "d"
11146 : mode
== SImode
? "fx"
11147 : mode
== DImode
? "dx"
11148 : "f", reg_names
[REGNO (x
)] + 2);
11154 if (GET_CODE (x
) != REG
11155 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11156 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11157 /* Bad value for wCG register number. */
11159 output_operand_lossage ("invalid operand for code '%c'", code
);
11164 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11167 /* Print an iWMMXt control register name. */
11169 if (GET_CODE (x
) != CONST_INT
11171 || INTVAL (x
) >= 16)
11172 /* Bad value for wC register number. */
11174 output_operand_lossage ("invalid operand for code '%c'", code
);
11180 static const char * wc_reg_names
[16] =
11182 "wCID", "wCon", "wCSSF", "wCASF",
11183 "wC4", "wC5", "wC6", "wC7",
11184 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11185 "wC12", "wC13", "wC14", "wC15"
11188 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11192 /* Print a VFP double precision register name. */
11195 int mode
= GET_MODE (x
);
11198 if (mode
!= DImode
&& mode
!= DFmode
)
11200 output_operand_lossage ("invalid operand for code '%c'", code
);
11204 if (GET_CODE (x
) != REG
11205 || !IS_VFP_REGNUM (REGNO (x
)))
11207 output_operand_lossage ("invalid operand for code '%c'", code
);
11211 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11214 output_operand_lossage ("invalid operand for code '%c'", code
);
11218 fprintf (stream
, "d%d", num
>> 1);
11225 output_operand_lossage ("missing operand");
11229 switch (GET_CODE (x
))
11232 asm_fprintf (stream
, "%r", REGNO (x
));
11236 output_memory_reference_mode
= GET_MODE (x
);
11237 output_address (XEXP (x
, 0));
11241 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11245 gcc_assert (GET_CODE (x
) != NEG
);
11246 fputc ('#', stream
);
11247 output_addr_const (stream
, x
);
11253 #ifndef AOF_ASSEMBLER
11254 /* Target hook for assembling integer objects. The ARM version needs to
11255 handle word-sized values specially. */
11257 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11259 if (size
== UNITS_PER_WORD
&& aligned_p
)
11261 fputs ("\t.word\t", asm_out_file
);
11262 output_addr_const (asm_out_file
, x
);
11264 /* Mark symbols as position independent. We only do this in the
11265 .text segment, not in the .data segment. */
11266 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11267 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11269 if (GET_CODE (x
) == SYMBOL_REF
11270 && (CONSTANT_POOL_ADDRESS_P (x
)
11271 || SYMBOL_REF_LOCAL_P (x
)))
11272 fputs ("(GOTOFF)", asm_out_file
);
11273 else if (GET_CODE (x
) == LABEL_REF
)
11274 fputs ("(GOTOFF)", asm_out_file
);
11276 fputs ("(GOT)", asm_out_file
);
11278 fputc ('\n', asm_out_file
);
11282 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11286 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11288 units
= CONST_VECTOR_NUNITS (x
);
11290 switch (GET_MODE (x
))
11292 case V2SImode
: size
= 4; break;
11293 case V4HImode
: size
= 2; break;
11294 case V8QImode
: size
= 1; break;
11296 gcc_unreachable ();
11299 for (i
= 0; i
< units
; i
++)
11303 elt
= CONST_VECTOR_ELT (x
, i
);
11305 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11311 return default_assemble_integer (x
, size
, aligned_p
);
11315 /* Add a function to the list of static constructors. */
11318 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
11320 if (!TARGET_AAPCS_BASED
)
11322 default_named_section_asm_out_constructor (symbol
, priority
);
11326 /* Put these in the .init_array section, using a special relocation. */
11327 switch_to_section (ctors_section
);
11328 assemble_align (POINTER_SIZE
);
11329 fputs ("\t.word\t", asm_out_file
);
11330 output_addr_const (asm_out_file
, symbol
);
11331 fputs ("(target1)\n", asm_out_file
);
11335 /* A finite state machine takes care of noticing whether or not instructions
11336 can be conditionally executed, and thus decrease execution time and code
11337 size by deleting branch instructions. The fsm is controlled by
11338 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11340 /* The state of the fsm controlling condition codes are:
11341 0: normal, do nothing special
11342 1: make ASM_OUTPUT_OPCODE not output this instruction
11343 2: make ASM_OUTPUT_OPCODE not output this instruction
11344 3: make instructions conditional
11345 4: make instructions conditional
11347 State transitions (state->state by whom under condition):
11348 0 -> 1 final_prescan_insn if the `target' is a label
11349 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11350 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11351 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11352 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11353 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11354 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11355 (the target insn is arm_target_insn).
11357 If the jump clobbers the conditions then we use states 2 and 4.
11359 A similar thing can be done with conditional return insns.
11361 XXX In case the `target' is an unconditional branch, this conditionalising
11362 of the instructions always reduces code size, but not always execution
11363 time. But then, I want to reduce the code size to somewhere near what
11364 /bin/cc produces. */
11366 /* Returns the index of the ARM condition code string in
11367 `arm_condition_codes'. COMPARISON should be an rtx like
11368 `(eq (...) (...))'. */
11369 static enum arm_cond_code
11370 get_arm_condition_code (rtx comparison
)
11372 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11374 enum rtx_code comp_code
= GET_CODE (comparison
);
11376 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11377 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11378 XEXP (comparison
, 1));
11382 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11383 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11384 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11385 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11386 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11387 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11388 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11389 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11390 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11391 case CC_DLTUmode
: code
= ARM_CC
;
11394 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11396 if (comp_code
== EQ
)
11397 return ARM_INVERSE_CONDITION_CODE (code
);
11403 case NE
: return ARM_NE
;
11404 case EQ
: return ARM_EQ
;
11405 case GE
: return ARM_PL
;
11406 case LT
: return ARM_MI
;
11407 default: gcc_unreachable ();
11413 case NE
: return ARM_NE
;
11414 case EQ
: return ARM_EQ
;
11415 default: gcc_unreachable ();
11421 case NE
: return ARM_MI
;
11422 case EQ
: return ARM_PL
;
11423 default: gcc_unreachable ();
11428 /* These encodings assume that AC=1 in the FPA system control
11429 byte. This allows us to handle all cases except UNEQ and
11433 case GE
: return ARM_GE
;
11434 case GT
: return ARM_GT
;
11435 case LE
: return ARM_LS
;
11436 case LT
: return ARM_MI
;
11437 case NE
: return ARM_NE
;
11438 case EQ
: return ARM_EQ
;
11439 case ORDERED
: return ARM_VC
;
11440 case UNORDERED
: return ARM_VS
;
11441 case UNLT
: return ARM_LT
;
11442 case UNLE
: return ARM_LE
;
11443 case UNGT
: return ARM_HI
;
11444 case UNGE
: return ARM_PL
;
11445 /* UNEQ and LTGT do not have a representation. */
11446 case UNEQ
: /* Fall through. */
11447 case LTGT
: /* Fall through. */
11448 default: gcc_unreachable ();
11454 case NE
: return ARM_NE
;
11455 case EQ
: return ARM_EQ
;
11456 case GE
: return ARM_LE
;
11457 case GT
: return ARM_LT
;
11458 case LE
: return ARM_GE
;
11459 case LT
: return ARM_GT
;
11460 case GEU
: return ARM_LS
;
11461 case GTU
: return ARM_CC
;
11462 case LEU
: return ARM_CS
;
11463 case LTU
: return ARM_HI
;
11464 default: gcc_unreachable ();
11470 case LTU
: return ARM_CS
;
11471 case GEU
: return ARM_CC
;
11472 default: gcc_unreachable ();
11478 case NE
: return ARM_NE
;
11479 case EQ
: return ARM_EQ
;
11480 case GE
: return ARM_GE
;
11481 case GT
: return ARM_GT
;
11482 case LE
: return ARM_LE
;
11483 case LT
: return ARM_LT
;
11484 case GEU
: return ARM_CS
;
11485 case GTU
: return ARM_HI
;
11486 case LEU
: return ARM_LS
;
11487 case LTU
: return ARM_CC
;
11488 default: gcc_unreachable ();
11491 default: gcc_unreachable ();
11496 arm_final_prescan_insn (rtx insn
)
11498 /* BODY will hold the body of INSN. */
11499 rtx body
= PATTERN (insn
);
11501 /* This will be 1 if trying to repeat the trick, and things need to be
11502 reversed if it appears to fail. */
11505 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11506 taken are clobbered, even if the rtl suggests otherwise. It also
11507 means that we have to grub around within the jump expression to find
11508 out what the conditions are when the jump isn't taken. */
11509 int jump_clobbers
= 0;
11511 /* If we start with a return insn, we only succeed if we find another one. */
11512 int seeking_return
= 0;
11514 /* START_INSN will hold the insn from where we start looking. This is the
11515 first insn after the following code_label if REVERSE is true. */
11516 rtx start_insn
= insn
;
11518 /* If in state 4, check if the target branch is reached, in order to
11519 change back to state 0. */
11520 if (arm_ccfsm_state
== 4)
11522 if (insn
== arm_target_insn
)
11524 arm_target_insn
= NULL
;
11525 arm_ccfsm_state
= 0;
11530 /* If in state 3, it is possible to repeat the trick, if this insn is an
11531 unconditional branch to a label, and immediately following this branch
11532 is the previous target label which is only used once, and the label this
11533 branch jumps to is not too far off. */
11534 if (arm_ccfsm_state
== 3)
11536 if (simplejump_p (insn
))
11538 start_insn
= next_nonnote_insn (start_insn
);
11539 if (GET_CODE (start_insn
) == BARRIER
)
11541 /* XXX Isn't this always a barrier? */
11542 start_insn
= next_nonnote_insn (start_insn
);
11544 if (GET_CODE (start_insn
) == CODE_LABEL
11545 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11546 && LABEL_NUSES (start_insn
) == 1)
11551 else if (GET_CODE (body
) == RETURN
)
11553 start_insn
= next_nonnote_insn (start_insn
);
11554 if (GET_CODE (start_insn
) == BARRIER
)
11555 start_insn
= next_nonnote_insn (start_insn
);
11556 if (GET_CODE (start_insn
) == CODE_LABEL
11557 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11558 && LABEL_NUSES (start_insn
) == 1)
11561 seeking_return
= 1;
11570 gcc_assert (!arm_ccfsm_state
|| reverse
);
11571 if (GET_CODE (insn
) != JUMP_INSN
)
11574 /* This jump might be paralleled with a clobber of the condition codes
11575 the jump should always come first */
11576 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11577 body
= XVECEXP (body
, 0, 0);
11580 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11581 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11584 int fail
= FALSE
, succeed
= FALSE
;
11585 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11586 int then_not_else
= TRUE
;
11587 rtx this_insn
= start_insn
, label
= 0;
11589 /* If the jump cannot be done with one instruction, we cannot
11590 conditionally execute the instruction in the inverse case. */
11591 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11597 /* Register the insn jumped to. */
11600 if (!seeking_return
)
11601 label
= XEXP (SET_SRC (body
), 0);
11603 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11604 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11605 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11607 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11608 then_not_else
= FALSE
;
11610 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11611 seeking_return
= 1;
11612 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11614 seeking_return
= 1;
11615 then_not_else
= FALSE
;
11618 gcc_unreachable ();
11620 /* See how many insns this branch skips, and what kind of insns. If all
11621 insns are okay, and the label or unconditional branch to the same
11622 label is not too far away, succeed. */
11623 for (insns_skipped
= 0;
11624 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11628 this_insn
= next_nonnote_insn (this_insn
);
11632 switch (GET_CODE (this_insn
))
11635 /* Succeed if it is the target label, otherwise fail since
11636 control falls in from somewhere else. */
11637 if (this_insn
== label
)
11641 arm_ccfsm_state
= 2;
11642 this_insn
= next_nonnote_insn (this_insn
);
11645 arm_ccfsm_state
= 1;
11653 /* Succeed if the following insn is the target label.
11655 If return insns are used then the last insn in a function
11656 will be a barrier. */
11657 this_insn
= next_nonnote_insn (this_insn
);
11658 if (this_insn
&& this_insn
== label
)
11662 arm_ccfsm_state
= 2;
11663 this_insn
= next_nonnote_insn (this_insn
);
11666 arm_ccfsm_state
= 1;
11674 /* The AAPCS says that conditional calls should not be
11675 used since they make interworking inefficient (the
11676 linker can't transform BL<cond> into BLX). That's
11677 only a problem if the machine has BLX. */
11684 /* Succeed if the following insn is the target label, or
11685 if the following two insns are a barrier and the
11687 this_insn
= next_nonnote_insn (this_insn
);
11688 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11689 this_insn
= next_nonnote_insn (this_insn
);
11691 if (this_insn
&& this_insn
== label
11692 && insns_skipped
< max_insns_skipped
)
11696 arm_ccfsm_state
= 2;
11697 this_insn
= next_nonnote_insn (this_insn
);
11700 arm_ccfsm_state
= 1;
11708 /* If this is an unconditional branch to the same label, succeed.
11709 If it is to another label, do nothing. If it is conditional,
11711 /* XXX Probably, the tests for SET and the PC are
11714 scanbody
= PATTERN (this_insn
);
11715 if (GET_CODE (scanbody
) == SET
11716 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11718 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11719 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11721 arm_ccfsm_state
= 2;
11724 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11727 /* Fail if a conditional return is undesirable (e.g. on a
11728 StrongARM), but still allow this if optimizing for size. */
11729 else if (GET_CODE (scanbody
) == RETURN
11730 && !use_return_insn (TRUE
, NULL
)
11733 else if (GET_CODE (scanbody
) == RETURN
11736 arm_ccfsm_state
= 2;
11739 else if (GET_CODE (scanbody
) == PARALLEL
)
11741 switch (get_attr_conds (this_insn
))
11751 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11756 /* Instructions using or affecting the condition codes make it
11758 scanbody
= PATTERN (this_insn
);
11759 if (!(GET_CODE (scanbody
) == SET
11760 || GET_CODE (scanbody
) == PARALLEL
)
11761 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11764 /* A conditional cirrus instruction must be followed by
11765 a non Cirrus instruction. However, since we
11766 conditionalize instructions in this function and by
11767 the time we get here we can't add instructions
11768 (nops), because shorten_branches() has already been
11769 called, we will disable conditionalizing Cirrus
11770 instructions to be safe. */
11771 if (GET_CODE (scanbody
) != USE
11772 && GET_CODE (scanbody
) != CLOBBER
11773 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11783 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11784 arm_target_label
= CODE_LABEL_NUMBER (label
);
11787 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11789 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11791 this_insn
= next_nonnote_insn (this_insn
);
11792 gcc_assert (!this_insn
11793 || (GET_CODE (this_insn
) != BARRIER
11794 && GET_CODE (this_insn
) != CODE_LABEL
));
11798 /* Oh, dear! we ran off the end.. give up. */
11799 recog (PATTERN (insn
), insn
, NULL
);
11800 arm_ccfsm_state
= 0;
11801 arm_target_insn
= NULL
;
11804 arm_target_insn
= this_insn
;
11808 gcc_assert (!reverse
);
11810 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11812 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11813 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11814 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11815 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11819 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11822 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11826 if (reverse
|| then_not_else
)
11827 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11830 /* Restore recog_data (getting the attributes of other insns can
11831 destroy this array, but final.c assumes that it remains intact
11832 across this call; since the insn has been recognized already we
11833 call recog direct). */
11834 recog (PATTERN (insn
), insn
, NULL
);
11838 /* Returns true if REGNO is a valid register
11839 for holding a quantity of type MODE. */
11841 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11843 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11844 return (regno
== CC_REGNUM
11845 || (TARGET_HARD_FLOAT
&& TARGET_VFP
11846 && regno
== VFPCC_REGNUM
));
11849 /* For the Thumb we only allow values bigger than SImode in
11850 registers 0 - 6, so that there is always a second low
11851 register available to hold the upper part of the value.
11852 We probably we ought to ensure that the register is the
11853 start of an even numbered register pair. */
11854 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11856 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
11857 && IS_CIRRUS_REGNUM (regno
))
11858 /* We have outlawed SI values in Cirrus registers because they
11859 reside in the lower 32 bits, but SF values reside in the
11860 upper 32 bits. This causes gcc all sorts of grief. We can't
11861 even split the registers into pairs because Cirrus SI values
11862 get sign extended to 64bits-- aldyh. */
11863 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11865 if (TARGET_HARD_FLOAT
&& TARGET_VFP
11866 && IS_VFP_REGNUM (regno
))
11868 if (mode
== SFmode
|| mode
== SImode
)
11871 /* DFmode values are only valid in even register pairs. */
11872 if (mode
== DFmode
)
11873 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11877 if (TARGET_REALLY_IWMMXT
)
11879 if (IS_IWMMXT_GR_REGNUM (regno
))
11880 return mode
== SImode
;
11882 if (IS_IWMMXT_REGNUM (regno
))
11883 return VALID_IWMMXT_REG_MODE (mode
);
11886 /* We allow any value to be stored in the general registers.
11887 Restrict doubleword quantities to even register pairs so that we can
11889 if (regno
<= LAST_ARM_REGNUM
)
11890 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11892 if (regno
== FRAME_POINTER_REGNUM
11893 || regno
== ARG_POINTER_REGNUM
)
11894 /* We only allow integers in the fake hard registers. */
11895 return GET_MODE_CLASS (mode
) == MODE_INT
;
11897 /* The only registers left are the FPA registers
11898 which we only allow to hold FP values. */
11899 return (TARGET_HARD_FLOAT
&& TARGET_FPA
11900 && GET_MODE_CLASS (mode
) == MODE_FLOAT
11901 && regno
>= FIRST_FPA_REGNUM
11902 && regno
<= LAST_FPA_REGNUM
);
11906 arm_regno_class (int regno
)
11910 if (regno
== STACK_POINTER_REGNUM
)
11912 if (regno
== CC_REGNUM
)
11919 if ( regno
<= LAST_ARM_REGNUM
11920 || regno
== FRAME_POINTER_REGNUM
11921 || regno
== ARG_POINTER_REGNUM
)
11922 return GENERAL_REGS
;
11924 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11927 if (IS_CIRRUS_REGNUM (regno
))
11928 return CIRRUS_REGS
;
11930 if (IS_VFP_REGNUM (regno
))
11933 if (IS_IWMMXT_REGNUM (regno
))
11934 return IWMMXT_REGS
;
11936 if (IS_IWMMXT_GR_REGNUM (regno
))
11937 return IWMMXT_GR_REGS
;
11942 /* Handle a special case when computing the offset
11943 of an argument from the frame pointer. */
11945 arm_debugger_arg_offset (int value
, rtx addr
)
11949 /* We are only interested if dbxout_parms() failed to compute the offset. */
11953 /* We can only cope with the case where the address is held in a register. */
11954 if (GET_CODE (addr
) != REG
)
11957 /* If we are using the frame pointer to point at the argument, then
11958 an offset of 0 is correct. */
11959 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11962 /* If we are using the stack pointer to point at the
11963 argument, then an offset of 0 is correct. */
11964 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11965 && REGNO (addr
) == SP_REGNUM
)
11968 /* Oh dear. The argument is pointed to by a register rather
11969 than being held in a register, or being stored at a known
11970 offset from the frame pointer. Since GDB only understands
11971 those two kinds of argument we must translate the address
11972 held in the register into an offset from the frame pointer.
11973 We do this by searching through the insns for the function
11974 looking to see where this register gets its value. If the
11975 register is initialized from the frame pointer plus an offset
11976 then we are in luck and we can continue, otherwise we give up.
11978 This code is exercised by producing debugging information
11979 for a function with arguments like this:
11981 double func (double a, double b, int c, double d) {return d;}
11983 Without this code the stab for parameter 'd' will be set to
11984 an offset of 0 from the frame pointer, rather than 8. */
11986 /* The if() statement says:
11988 If the insn is a normal instruction
11989 and if the insn is setting the value in a register
11990 and if the register being set is the register holding the address of the argument
11991 and if the address is computing by an addition
11992 that involves adding to a register
11993 which is the frame pointer
11998 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12000 if ( GET_CODE (insn
) == INSN
12001 && GET_CODE (PATTERN (insn
)) == SET
12002 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
12003 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
12004 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
12005 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12006 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
12009 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
12018 warning (0, "unable to compute real location of stacked parameter");
12019 value
= 8; /* XXX magic hack */
12025 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12028 if ((MASK) & insn_flags) \
12029 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
12030 BUILT_IN_MD, NULL, NULL_TREE); \
12034 struct builtin_description
12036 const unsigned int mask
;
12037 const enum insn_code icode
;
12038 const char * const name
;
12039 const enum arm_builtins code
;
12040 const enum rtx_code comparison
;
12041 const unsigned int flag
;
12044 static const struct builtin_description bdesc_2arg
[] =
12046 #define IWMMXT_BUILTIN(code, string, builtin) \
12047 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12048 ARM_BUILTIN_##builtin, 0, 0 },
12050 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12051 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12052 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12053 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12054 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12055 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12056 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12057 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12058 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12059 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12060 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12061 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12062 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12063 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12064 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12065 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12066 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12067 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12068 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12069 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12070 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12071 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12072 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12073 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12074 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12075 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12076 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12077 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12078 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12079 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12080 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12081 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12082 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12083 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12084 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12085 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12086 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12087 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12088 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12089 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12090 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12091 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12092 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12093 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12094 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12095 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12096 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12097 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12098 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12099 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12100 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12101 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12102 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12103 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12104 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12105 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12106 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12107 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12109 #define IWMMXT_BUILTIN2(code, builtin) \
12110 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12112 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12113 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12114 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12115 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12116 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12117 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12118 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12119 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12120 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12121 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12122 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12123 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12124 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12125 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12126 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12127 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12128 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12129 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12130 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12131 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12132 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12133 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12134 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12135 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12136 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12137 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12138 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12139 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12140 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12141 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12142 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12143 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12146 static const struct builtin_description bdesc_1arg
[] =
12148 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12149 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12150 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12151 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12152 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12153 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12154 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12155 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12156 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12157 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12158 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12159 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12160 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12161 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12162 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12163 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12164 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12165 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12168 /* Set up all the iWMMXt builtins. This is
12169 not called if TARGET_IWMMXT is zero. */
12172 arm_init_iwmmxt_builtins (void)
12174 const struct builtin_description
* d
;
12176 tree endlink
= void_list_node
;
12178 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12179 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12180 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12183 = build_function_type (integer_type_node
,
12184 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12185 tree v8qi_ftype_v8qi_v8qi_int
12186 = build_function_type (V8QI_type_node
,
12187 tree_cons (NULL_TREE
, V8QI_type_node
,
12188 tree_cons (NULL_TREE
, V8QI_type_node
,
12189 tree_cons (NULL_TREE
,
12192 tree v4hi_ftype_v4hi_int
12193 = build_function_type (V4HI_type_node
,
12194 tree_cons (NULL_TREE
, V4HI_type_node
,
12195 tree_cons (NULL_TREE
, integer_type_node
,
12197 tree v2si_ftype_v2si_int
12198 = build_function_type (V2SI_type_node
,
12199 tree_cons (NULL_TREE
, V2SI_type_node
,
12200 tree_cons (NULL_TREE
, integer_type_node
,
12202 tree v2si_ftype_di_di
12203 = build_function_type (V2SI_type_node
,
12204 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12205 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12207 tree di_ftype_di_int
12208 = build_function_type (long_long_integer_type_node
,
12209 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12210 tree_cons (NULL_TREE
, integer_type_node
,
12212 tree di_ftype_di_int_int
12213 = build_function_type (long_long_integer_type_node
,
12214 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12215 tree_cons (NULL_TREE
, integer_type_node
,
12216 tree_cons (NULL_TREE
,
12219 tree int_ftype_v8qi
12220 = build_function_type (integer_type_node
,
12221 tree_cons (NULL_TREE
, V8QI_type_node
,
12223 tree int_ftype_v4hi
12224 = build_function_type (integer_type_node
,
12225 tree_cons (NULL_TREE
, V4HI_type_node
,
12227 tree int_ftype_v2si
12228 = build_function_type (integer_type_node
,
12229 tree_cons (NULL_TREE
, V2SI_type_node
,
12231 tree int_ftype_v8qi_int
12232 = build_function_type (integer_type_node
,
12233 tree_cons (NULL_TREE
, V8QI_type_node
,
12234 tree_cons (NULL_TREE
, integer_type_node
,
12236 tree int_ftype_v4hi_int
12237 = build_function_type (integer_type_node
,
12238 tree_cons (NULL_TREE
, V4HI_type_node
,
12239 tree_cons (NULL_TREE
, integer_type_node
,
12241 tree int_ftype_v2si_int
12242 = build_function_type (integer_type_node
,
12243 tree_cons (NULL_TREE
, V2SI_type_node
,
12244 tree_cons (NULL_TREE
, integer_type_node
,
12246 tree v8qi_ftype_v8qi_int_int
12247 = build_function_type (V8QI_type_node
,
12248 tree_cons (NULL_TREE
, V8QI_type_node
,
12249 tree_cons (NULL_TREE
, integer_type_node
,
12250 tree_cons (NULL_TREE
,
12253 tree v4hi_ftype_v4hi_int_int
12254 = build_function_type (V4HI_type_node
,
12255 tree_cons (NULL_TREE
, V4HI_type_node
,
12256 tree_cons (NULL_TREE
, integer_type_node
,
12257 tree_cons (NULL_TREE
,
12260 tree v2si_ftype_v2si_int_int
12261 = build_function_type (V2SI_type_node
,
12262 tree_cons (NULL_TREE
, V2SI_type_node
,
12263 tree_cons (NULL_TREE
, integer_type_node
,
12264 tree_cons (NULL_TREE
,
12267 /* Miscellaneous. */
12268 tree v8qi_ftype_v4hi_v4hi
12269 = build_function_type (V8QI_type_node
,
12270 tree_cons (NULL_TREE
, V4HI_type_node
,
12271 tree_cons (NULL_TREE
, V4HI_type_node
,
12273 tree v4hi_ftype_v2si_v2si
12274 = build_function_type (V4HI_type_node
,
12275 tree_cons (NULL_TREE
, V2SI_type_node
,
12276 tree_cons (NULL_TREE
, V2SI_type_node
,
12278 tree v2si_ftype_v4hi_v4hi
12279 = build_function_type (V2SI_type_node
,
12280 tree_cons (NULL_TREE
, V4HI_type_node
,
12281 tree_cons (NULL_TREE
, V4HI_type_node
,
12283 tree v2si_ftype_v8qi_v8qi
12284 = build_function_type (V2SI_type_node
,
12285 tree_cons (NULL_TREE
, V8QI_type_node
,
12286 tree_cons (NULL_TREE
, V8QI_type_node
,
12288 tree v4hi_ftype_v4hi_di
12289 = build_function_type (V4HI_type_node
,
12290 tree_cons (NULL_TREE
, V4HI_type_node
,
12291 tree_cons (NULL_TREE
,
12292 long_long_integer_type_node
,
12294 tree v2si_ftype_v2si_di
12295 = build_function_type (V2SI_type_node
,
12296 tree_cons (NULL_TREE
, V2SI_type_node
,
12297 tree_cons (NULL_TREE
,
12298 long_long_integer_type_node
,
12300 tree void_ftype_int_int
12301 = build_function_type (void_type_node
,
12302 tree_cons (NULL_TREE
, integer_type_node
,
12303 tree_cons (NULL_TREE
, integer_type_node
,
12306 = build_function_type (long_long_unsigned_type_node
, endlink
);
12308 = build_function_type (long_long_integer_type_node
,
12309 tree_cons (NULL_TREE
, V8QI_type_node
,
12312 = build_function_type (long_long_integer_type_node
,
12313 tree_cons (NULL_TREE
, V4HI_type_node
,
12316 = build_function_type (long_long_integer_type_node
,
12317 tree_cons (NULL_TREE
, V2SI_type_node
,
12319 tree v2si_ftype_v4hi
12320 = build_function_type (V2SI_type_node
,
12321 tree_cons (NULL_TREE
, V4HI_type_node
,
12323 tree v4hi_ftype_v8qi
12324 = build_function_type (V4HI_type_node
,
12325 tree_cons (NULL_TREE
, V8QI_type_node
,
12328 tree di_ftype_di_v4hi_v4hi
12329 = build_function_type (long_long_unsigned_type_node
,
12330 tree_cons (NULL_TREE
,
12331 long_long_unsigned_type_node
,
12332 tree_cons (NULL_TREE
, V4HI_type_node
,
12333 tree_cons (NULL_TREE
,
12337 tree di_ftype_v4hi_v4hi
12338 = build_function_type (long_long_unsigned_type_node
,
12339 tree_cons (NULL_TREE
, V4HI_type_node
,
12340 tree_cons (NULL_TREE
, V4HI_type_node
,
12343 /* Normal vector binops. */
12344 tree v8qi_ftype_v8qi_v8qi
12345 = build_function_type (V8QI_type_node
,
12346 tree_cons (NULL_TREE
, V8QI_type_node
,
12347 tree_cons (NULL_TREE
, V8QI_type_node
,
12349 tree v4hi_ftype_v4hi_v4hi
12350 = build_function_type (V4HI_type_node
,
12351 tree_cons (NULL_TREE
, V4HI_type_node
,
12352 tree_cons (NULL_TREE
, V4HI_type_node
,
12354 tree v2si_ftype_v2si_v2si
12355 = build_function_type (V2SI_type_node
,
12356 tree_cons (NULL_TREE
, V2SI_type_node
,
12357 tree_cons (NULL_TREE
, V2SI_type_node
,
12359 tree di_ftype_di_di
12360 = build_function_type (long_long_unsigned_type_node
,
12361 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12362 tree_cons (NULL_TREE
,
12363 long_long_unsigned_type_node
,
12366 /* Add all builtins that are more or less simple operations on two
12368 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12370 /* Use one of the operands; the target can have a different mode for
12371 mask-generating compares. */
12372 enum machine_mode mode
;
12378 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12383 type
= v8qi_ftype_v8qi_v8qi
;
12386 type
= v4hi_ftype_v4hi_v4hi
;
12389 type
= v2si_ftype_v2si_v2si
;
12392 type
= di_ftype_di_di
;
12396 gcc_unreachable ();
12399 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12402 /* Add the remaining MMX insns with somewhat more complicated types. */
12403 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12404 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12405 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12407 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12408 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12409 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12410 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12411 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12412 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12414 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12415 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12416 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12417 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12418 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12419 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12421 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12422 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12423 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12424 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12425 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12426 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12428 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12429 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12430 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12431 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12432 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12433 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12435 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12437 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12438 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12439 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12440 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12442 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12443 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12444 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12445 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12446 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12447 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12448 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12449 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12450 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12452 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12453 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12454 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12456 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12457 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12458 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12460 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12461 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12462 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12463 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12464 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12465 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12467 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12468 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12469 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12470 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12471 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12472 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12473 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12474 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12475 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12476 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12477 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12478 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12480 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12481 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12482 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12483 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12485 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12486 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12487 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12488 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12489 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12490 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12491 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12495 arm_init_tls_builtins (void)
12498 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
12499 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
12501 ftype
= build_function_type (ptr_type_node
, void_list_node
);
12502 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
12503 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
12504 NULL
, const_nothrow
);
12508 arm_init_builtins (void)
12510 arm_init_tls_builtins ();
12512 if (TARGET_REALLY_IWMMXT
)
12513 arm_init_iwmmxt_builtins ();
12516 /* Errors in the source file can cause expand_expr to return const0_rtx
12517 where we expect a vector. To avoid crashing, use one of the vector
12518 clear instructions. */
12521 safe_vector_operand (rtx x
, enum machine_mode mode
)
12523 if (x
!= const0_rtx
)
12525 x
= gen_reg_rtx (mode
);
12527 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12528 : gen_rtx_SUBREG (DImode
, x
, 0)));
12532 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12535 arm_expand_binop_builtin (enum insn_code icode
,
12536 tree arglist
, rtx target
)
12539 tree arg0
= TREE_VALUE (arglist
);
12540 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12541 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12542 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12543 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12544 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12545 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12547 if (VECTOR_MODE_P (mode0
))
12548 op0
= safe_vector_operand (op0
, mode0
);
12549 if (VECTOR_MODE_P (mode1
))
12550 op1
= safe_vector_operand (op1
, mode1
);
12553 || GET_MODE (target
) != tmode
12554 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12555 target
= gen_reg_rtx (tmode
);
12557 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12559 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12560 op0
= copy_to_mode_reg (mode0
, op0
);
12561 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12562 op1
= copy_to_mode_reg (mode1
, op1
);
12564 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12571 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12574 arm_expand_unop_builtin (enum insn_code icode
,
12575 tree arglist
, rtx target
, int do_load
)
12578 tree arg0
= TREE_VALUE (arglist
);
12579 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12580 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12581 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12584 || GET_MODE (target
) != tmode
12585 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12586 target
= gen_reg_rtx (tmode
);
12588 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12591 if (VECTOR_MODE_P (mode0
))
12592 op0
= safe_vector_operand (op0
, mode0
);
12594 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12595 op0
= copy_to_mode_reg (mode0
, op0
);
12598 pat
= GEN_FCN (icode
) (target
, op0
);
12605 /* Expand an expression EXP that calls a built-in function,
12606 with result going to TARGET if that's convenient
12607 (and in mode MODE if that's convenient).
12608 SUBTARGET may be used as the target for computing one of EXP's operands.
12609 IGNORE is nonzero if the value is to be ignored. */
12612 arm_expand_builtin (tree exp
,
12614 rtx subtarget ATTRIBUTE_UNUSED
,
12615 enum machine_mode mode ATTRIBUTE_UNUSED
,
12616 int ignore ATTRIBUTE_UNUSED
)
12618 const struct builtin_description
* d
;
12619 enum insn_code icode
;
12620 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12621 tree arglist
= TREE_OPERAND (exp
, 1);
12629 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12631 enum machine_mode tmode
;
12632 enum machine_mode mode0
;
12633 enum machine_mode mode1
;
12634 enum machine_mode mode2
;
12638 case ARM_BUILTIN_TEXTRMSB
:
12639 case ARM_BUILTIN_TEXTRMUB
:
12640 case ARM_BUILTIN_TEXTRMSH
:
12641 case ARM_BUILTIN_TEXTRMUH
:
12642 case ARM_BUILTIN_TEXTRMSW
:
12643 case ARM_BUILTIN_TEXTRMUW
:
12644 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12645 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12646 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12647 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12648 : CODE_FOR_iwmmxt_textrmw
);
12650 arg0
= TREE_VALUE (arglist
);
12651 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12652 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12653 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12654 tmode
= insn_data
[icode
].operand
[0].mode
;
12655 mode0
= insn_data
[icode
].operand
[1].mode
;
12656 mode1
= insn_data
[icode
].operand
[2].mode
;
12658 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12659 op0
= copy_to_mode_reg (mode0
, op0
);
12660 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12662 /* @@@ better error message */
12663 error ("selector must be an immediate");
12664 return gen_reg_rtx (tmode
);
12667 || GET_MODE (target
) != tmode
12668 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12669 target
= gen_reg_rtx (tmode
);
12670 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12676 case ARM_BUILTIN_TINSRB
:
12677 case ARM_BUILTIN_TINSRH
:
12678 case ARM_BUILTIN_TINSRW
:
12679 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12680 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12681 : CODE_FOR_iwmmxt_tinsrw
);
12682 arg0
= TREE_VALUE (arglist
);
12683 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12684 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12685 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12686 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12687 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12688 tmode
= insn_data
[icode
].operand
[0].mode
;
12689 mode0
= insn_data
[icode
].operand
[1].mode
;
12690 mode1
= insn_data
[icode
].operand
[2].mode
;
12691 mode2
= insn_data
[icode
].operand
[3].mode
;
12693 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12694 op0
= copy_to_mode_reg (mode0
, op0
);
12695 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12696 op1
= copy_to_mode_reg (mode1
, op1
);
12697 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12699 /* @@@ better error message */
12700 error ("selector must be an immediate");
12704 || GET_MODE (target
) != tmode
12705 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12706 target
= gen_reg_rtx (tmode
);
12707 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12713 case ARM_BUILTIN_SETWCX
:
12714 arg0
= TREE_VALUE (arglist
);
12715 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12716 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12717 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12718 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12721 case ARM_BUILTIN_GETWCX
:
12722 arg0
= TREE_VALUE (arglist
);
12723 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12724 target
= gen_reg_rtx (SImode
);
12725 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12728 case ARM_BUILTIN_WSHUFH
:
12729 icode
= CODE_FOR_iwmmxt_wshufh
;
12730 arg0
= TREE_VALUE (arglist
);
12731 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12732 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12733 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12734 tmode
= insn_data
[icode
].operand
[0].mode
;
12735 mode1
= insn_data
[icode
].operand
[1].mode
;
12736 mode2
= insn_data
[icode
].operand
[2].mode
;
12738 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12739 op0
= copy_to_mode_reg (mode1
, op0
);
12740 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12742 /* @@@ better error message */
12743 error ("mask must be an immediate");
12747 || GET_MODE (target
) != tmode
12748 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12749 target
= gen_reg_rtx (tmode
);
12750 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12756 case ARM_BUILTIN_WSADB
:
12757 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12758 case ARM_BUILTIN_WSADH
:
12759 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12760 case ARM_BUILTIN_WSADBZ
:
12761 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12762 case ARM_BUILTIN_WSADHZ
:
12763 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12765 /* Several three-argument builtins. */
12766 case ARM_BUILTIN_WMACS
:
12767 case ARM_BUILTIN_WMACU
:
12768 case ARM_BUILTIN_WALIGN
:
12769 case ARM_BUILTIN_TMIA
:
12770 case ARM_BUILTIN_TMIAPH
:
12771 case ARM_BUILTIN_TMIATT
:
12772 case ARM_BUILTIN_TMIATB
:
12773 case ARM_BUILTIN_TMIABT
:
12774 case ARM_BUILTIN_TMIABB
:
12775 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12776 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12777 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12778 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12779 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12780 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12781 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12782 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12783 : CODE_FOR_iwmmxt_walign
);
12784 arg0
= TREE_VALUE (arglist
);
12785 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12786 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12787 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12788 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12789 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12790 tmode
= insn_data
[icode
].operand
[0].mode
;
12791 mode0
= insn_data
[icode
].operand
[1].mode
;
12792 mode1
= insn_data
[icode
].operand
[2].mode
;
12793 mode2
= insn_data
[icode
].operand
[3].mode
;
12795 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12796 op0
= copy_to_mode_reg (mode0
, op0
);
12797 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12798 op1
= copy_to_mode_reg (mode1
, op1
);
12799 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12800 op2
= copy_to_mode_reg (mode2
, op2
);
12802 || GET_MODE (target
) != tmode
12803 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12804 target
= gen_reg_rtx (tmode
);
12805 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12811 case ARM_BUILTIN_WZERO
:
12812 target
= gen_reg_rtx (DImode
);
12813 emit_insn (gen_iwmmxt_clrdi (target
));
12816 case ARM_BUILTIN_THREAD_POINTER
:
12817 return arm_load_tp (target
);
12823 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12824 if (d
->code
== (const enum arm_builtins
) fcode
)
12825 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12827 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12828 if (d
->code
== (const enum arm_builtins
) fcode
)
12829 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12831 /* @@@ Should really do something sensible here. */
12835 /* Return the number (counting from 0) of
12836 the least significant set bit in MASK. */
12839 number_of_first_bit_set (unsigned mask
)
12844 (mask
& (1 << bit
)) == 0;
12851 /* Emit code to push or pop registers to or from the stack. F is the
12852 assembly file. MASK is the registers to push or pop. PUSH is
12853 nonzero if we should push, and zero if we should pop. For debugging
12854 output, if pushing, adjust CFA_OFFSET by the amount of space added
12855 to the stack. REAL_REGS should have the same number of bits set as
12856 MASK, and will be used instead (in the same order) to describe which
12857 registers were saved - this is used to mark the save slots when we
12858 push high registers after moving them to low registers. */
12860 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12861 unsigned long real_regs
)
12864 int lo_mask
= mask
& 0xFF;
12865 int pushed_words
= 0;
12869 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12871 /* Special case. Do not generate a POP PC statement here, do it in
12873 thumb_exit (f
, -1);
12877 if (ARM_EABI_UNWIND_TABLES
&& push
)
12879 fprintf (f
, "\t.save\t{");
12880 for (regno
= 0; regno
< 15; regno
++)
12882 if (real_regs
& (1 << regno
))
12884 if (real_regs
& ((1 << regno
) -1))
12886 asm_fprintf (f
, "%r", regno
);
12889 fprintf (f
, "}\n");
12892 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12894 /* Look at the low registers first. */
12895 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12899 asm_fprintf (f
, "%r", regno
);
12901 if ((lo_mask
& ~1) != 0)
12908 if (push
&& (mask
& (1 << LR_REGNUM
)))
12910 /* Catch pushing the LR. */
12914 asm_fprintf (f
, "%r", LR_REGNUM
);
12918 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12920 /* Catch popping the PC. */
12921 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12922 || current_function_calls_eh_return
)
12924 /* The PC is never poped directly, instead
12925 it is popped into r3 and then BX is used. */
12926 fprintf (f
, "}\n");
12928 thumb_exit (f
, -1);
12937 asm_fprintf (f
, "%r", PC_REGNUM
);
12941 fprintf (f
, "}\n");
12943 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12945 char *l
= dwarf2out_cfi_label ();
12946 int pushed_mask
= real_regs
;
12948 *cfa_offset
+= pushed_words
* 4;
12949 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12952 pushed_mask
= real_regs
;
12953 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12955 if (pushed_mask
& 1)
12956 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12961 /* Generate code to return from a thumb function.
12962 If 'reg_containing_return_addr' is -1, then the return address is
12963 actually on the stack, at the stack pointer. */
12965 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12967 unsigned regs_available_for_popping
;
12968 unsigned regs_to_pop
;
12970 unsigned available
;
12974 int restore_a4
= FALSE
;
12976 /* Compute the registers we need to pop. */
12980 if (reg_containing_return_addr
== -1)
12982 regs_to_pop
|= 1 << LR_REGNUM
;
12986 if (TARGET_BACKTRACE
)
12988 /* Restore the (ARM) frame pointer and stack pointer. */
12989 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12993 /* If there is nothing to pop then just emit the BX instruction and
12995 if (pops_needed
== 0)
12997 if (current_function_calls_eh_return
)
12998 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13000 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13003 /* Otherwise if we are not supporting interworking and we have not created
13004 a backtrace structure and the function was not entered in ARM mode then
13005 just pop the return address straight into the PC. */
13006 else if (!TARGET_INTERWORK
13007 && !TARGET_BACKTRACE
13008 && !is_called_in_ARM_mode (current_function_decl
)
13009 && !current_function_calls_eh_return
)
13011 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
13015 /* Find out how many of the (return) argument registers we can corrupt. */
13016 regs_available_for_popping
= 0;
13018 /* If returning via __builtin_eh_return, the bottom three registers
13019 all contain information needed for the return. */
13020 if (current_function_calls_eh_return
)
13024 /* If we can deduce the registers used from the function's
13025 return value. This is more reliable that examining
13026 regs_ever_live[] because that will be set if the register is
13027 ever used in the function, not just if the register is used
13028 to hold a return value. */
13030 if (current_function_return_rtx
!= 0)
13031 mode
= GET_MODE (current_function_return_rtx
);
13033 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13035 size
= GET_MODE_SIZE (mode
);
13039 /* In a void function we can use any argument register.
13040 In a function that returns a structure on the stack
13041 we can use the second and third argument registers. */
13042 if (mode
== VOIDmode
)
13043 regs_available_for_popping
=
13044 (1 << ARG_REGISTER (1))
13045 | (1 << ARG_REGISTER (2))
13046 | (1 << ARG_REGISTER (3));
13048 regs_available_for_popping
=
13049 (1 << ARG_REGISTER (2))
13050 | (1 << ARG_REGISTER (3));
13052 else if (size
<= 4)
13053 regs_available_for_popping
=
13054 (1 << ARG_REGISTER (2))
13055 | (1 << ARG_REGISTER (3));
13056 else if (size
<= 8)
13057 regs_available_for_popping
=
13058 (1 << ARG_REGISTER (3));
13061 /* Match registers to be popped with registers into which we pop them. */
13062 for (available
= regs_available_for_popping
,
13063 required
= regs_to_pop
;
13064 required
!= 0 && available
!= 0;
13065 available
&= ~(available
& - available
),
13066 required
&= ~(required
& - required
))
13069 /* If we have any popping registers left over, remove them. */
13071 regs_available_for_popping
&= ~available
;
13073 /* Otherwise if we need another popping register we can use
13074 the fourth argument register. */
13075 else if (pops_needed
)
13077 /* If we have not found any free argument registers and
13078 reg a4 contains the return address, we must move it. */
13079 if (regs_available_for_popping
== 0
13080 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13082 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13083 reg_containing_return_addr
= LR_REGNUM
;
13085 else if (size
> 12)
13087 /* Register a4 is being used to hold part of the return value,
13088 but we have dire need of a free, low register. */
13091 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13094 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13096 /* The fourth argument register is available. */
13097 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13103 /* Pop as many registers as we can. */
13104 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13105 regs_available_for_popping
);
13107 /* Process the registers we popped. */
13108 if (reg_containing_return_addr
== -1)
13110 /* The return address was popped into the lowest numbered register. */
13111 regs_to_pop
&= ~(1 << LR_REGNUM
);
13113 reg_containing_return_addr
=
13114 number_of_first_bit_set (regs_available_for_popping
);
13116 /* Remove this register for the mask of available registers, so that
13117 the return address will not be corrupted by further pops. */
13118 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13121 /* If we popped other registers then handle them here. */
13122 if (regs_available_for_popping
)
13126 /* Work out which register currently contains the frame pointer. */
13127 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13129 /* Move it into the correct place. */
13130 asm_fprintf (f
, "\tmov\t%r, %r\n",
13131 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13133 /* (Temporarily) remove it from the mask of popped registers. */
13134 regs_available_for_popping
&= ~(1 << frame_pointer
);
13135 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13137 if (regs_available_for_popping
)
13141 /* We popped the stack pointer as well,
13142 find the register that contains it. */
13143 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13145 /* Move it into the stack register. */
13146 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13148 /* At this point we have popped all necessary registers, so
13149 do not worry about restoring regs_available_for_popping
13150 to its correct value:
13152 assert (pops_needed == 0)
13153 assert (regs_available_for_popping == (1 << frame_pointer))
13154 assert (regs_to_pop == (1 << STACK_POINTER)) */
13158 /* Since we have just move the popped value into the frame
13159 pointer, the popping register is available for reuse, and
13160 we know that we still have the stack pointer left to pop. */
13161 regs_available_for_popping
|= (1 << frame_pointer
);
13165 /* If we still have registers left on the stack, but we no longer have
13166 any registers into which we can pop them, then we must move the return
13167 address into the link register and make available the register that
13169 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13171 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13173 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13174 reg_containing_return_addr
);
13176 reg_containing_return_addr
= LR_REGNUM
;
13179 /* If we have registers left on the stack then pop some more.
13180 We know that at most we will want to pop FP and SP. */
13181 if (pops_needed
> 0)
13186 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13187 regs_available_for_popping
);
13189 /* We have popped either FP or SP.
13190 Move whichever one it is into the correct register. */
13191 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13192 move_to
= number_of_first_bit_set (regs_to_pop
);
13194 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13196 regs_to_pop
&= ~(1 << move_to
);
13201 /* If we still have not popped everything then we must have only
13202 had one register available to us and we are now popping the SP. */
13203 if (pops_needed
> 0)
13207 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13208 regs_available_for_popping
);
13210 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13212 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13214 assert (regs_to_pop == (1 << STACK_POINTER))
13215 assert (pops_needed == 1)
13219 /* If necessary restore the a4 register. */
13222 if (reg_containing_return_addr
!= LR_REGNUM
)
13224 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13225 reg_containing_return_addr
= LR_REGNUM
;
13228 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13231 if (current_function_calls_eh_return
)
13232 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13234 /* Return to caller. */
13235 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13240 thumb_final_prescan_insn (rtx insn
)
13242 if (flag_print_asm_name
)
13243 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
13244 INSN_ADDRESSES (INSN_UID (insn
)));
13248 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
13250 unsigned HOST_WIDE_INT mask
= 0xff;
13253 if (val
== 0) /* XXX */
13256 for (i
= 0; i
< 25; i
++)
13257 if ((val
& (mask
<< i
)) == val
)
13263 /* Returns nonzero if the current function contains,
13264 or might contain a far jump. */
13266 thumb_far_jump_used_p (void)
13270 /* This test is only important for leaf functions. */
13271 /* assert (!leaf_function_p ()); */
13273 /* If we have already decided that far jumps may be used,
13274 do not bother checking again, and always return true even if
13275 it turns out that they are not being used. Once we have made
13276 the decision that far jumps are present (and that hence the link
13277 register will be pushed onto the stack) we cannot go back on it. */
13278 if (cfun
->machine
->far_jump_used
)
13281 /* If this function is not being called from the prologue/epilogue
13282 generation code then it must be being called from the
13283 INITIAL_ELIMINATION_OFFSET macro. */
13284 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13286 /* In this case we know that we are being asked about the elimination
13287 of the arg pointer register. If that register is not being used,
13288 then there are no arguments on the stack, and we do not have to
13289 worry that a far jump might force the prologue to push the link
13290 register, changing the stack offsets. In this case we can just
13291 return false, since the presence of far jumps in the function will
13292 not affect stack offsets.
13294 If the arg pointer is live (or if it was live, but has now been
13295 eliminated and so set to dead) then we do have to test to see if
13296 the function might contain a far jump. This test can lead to some
13297 false negatives, since before reload is completed, then length of
13298 branch instructions is not known, so gcc defaults to returning their
13299 longest length, which in turn sets the far jump attribute to true.
13301 A false negative will not result in bad code being generated, but it
13302 will result in a needless push and pop of the link register. We
13303 hope that this does not occur too often.
13305 If we need doubleword stack alignment this could affect the other
13306 elimination offsets so we can't risk getting it wrong. */
13307 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13308 cfun
->machine
->arg_pointer_live
= 1;
13309 else if (!cfun
->machine
->arg_pointer_live
)
13313 /* Check to see if the function contains a branch
13314 insn with the far jump attribute set. */
13315 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13317 if (GET_CODE (insn
) == JUMP_INSN
13318 /* Ignore tablejump patterns. */
13319 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13320 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13321 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13324 /* Record the fact that we have decided that
13325 the function does use far jumps. */
13326 cfun
->machine
->far_jump_used
= 1;
13334 /* Return nonzero if FUNC must be entered in ARM mode. */
13336 is_called_in_ARM_mode (tree func
)
13338 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
13340 /* Ignore the problem about functions whose address is taken. */
13341 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13345 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13351 /* The bits which aren't usefully expanded as rtl. */
13353 thumb_unexpanded_epilogue (void)
13356 unsigned long live_regs_mask
= 0;
13357 int high_regs_pushed
= 0;
13358 int had_to_push_lr
;
13361 if (return_used_this_function
)
13364 if (IS_NAKED (arm_current_func_type ()))
13367 live_regs_mask
= thumb_compute_save_reg_mask ();
13368 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13370 /* If we can deduce the registers used from the function's return value.
13371 This is more reliable that examining regs_ever_live[] because that
13372 will be set if the register is ever used in the function, not just if
13373 the register is used to hold a return value. */
13374 size
= arm_size_return_regs ();
13376 /* The prolog may have pushed some high registers to use as
13377 work registers. e.g. the testsuite file:
13378 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13379 compiles to produce:
13380 push {r4, r5, r6, r7, lr}
13384 as part of the prolog. We have to undo that pushing here. */
13386 if (high_regs_pushed
)
13388 unsigned long mask
= live_regs_mask
& 0xff;
13391 /* The available low registers depend on the size of the value we are
13399 /* Oh dear! We have no low registers into which we can pop
13402 ("no low registers available for popping high registers");
13404 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13405 if (live_regs_mask
& (1 << next_hi_reg
))
13408 while (high_regs_pushed
)
13410 /* Find lo register(s) into which the high register(s) can
13412 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13414 if (mask
& (1 << regno
))
13415 high_regs_pushed
--;
13416 if (high_regs_pushed
== 0)
13420 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13422 /* Pop the values into the low register(s). */
13423 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13425 /* Move the value(s) into the high registers. */
13426 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13428 if (mask
& (1 << regno
))
13430 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13433 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13434 if (live_regs_mask
& (1 << next_hi_reg
))
13439 live_regs_mask
&= ~0x0f00;
13442 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13443 live_regs_mask
&= 0xff;
13445 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13447 /* Pop the return address into the PC. */
13448 if (had_to_push_lr
)
13449 live_regs_mask
|= 1 << PC_REGNUM
;
13451 /* Either no argument registers were pushed or a backtrace
13452 structure was created which includes an adjusted stack
13453 pointer, so just pop everything. */
13454 if (live_regs_mask
)
13455 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13458 /* We have either just popped the return address into the
13459 PC or it is was kept in LR for the entire function. */
13460 if (!had_to_push_lr
)
13461 thumb_exit (asm_out_file
, LR_REGNUM
);
13465 /* Pop everything but the return address. */
13466 if (live_regs_mask
)
13467 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13470 if (had_to_push_lr
)
13474 /* We have no free low regs, so save one. */
13475 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13479 /* Get the return address into a temporary register. */
13480 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13481 1 << LAST_ARG_REGNUM
);
13485 /* Move the return address to lr. */
13486 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13488 /* Restore the low register. */
13489 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13494 regno
= LAST_ARG_REGNUM
;
13499 /* Remove the argument registers that were pushed onto the stack. */
13500 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13501 SP_REGNUM
, SP_REGNUM
,
13502 current_function_pretend_args_size
);
13504 thumb_exit (asm_out_file
, regno
);
13510 /* Functions to save and restore machine-specific function data. */
13511 static struct machine_function
*
13512 arm_init_machine_status (void)
13514 struct machine_function
*machine
;
13515 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13517 #if ARM_FT_UNKNOWN != 0
13518 machine
->func_type
= ARM_FT_UNKNOWN
;
13523 /* Return an RTX indicating where the return address to the
13524 calling function can be found. */
13526 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13531 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13534 /* Do anything needed before RTL is emitted for each function. */
13536 arm_init_expanders (void)
13538 /* Arrange to initialize and mark the machine per-function status. */
13539 init_machine_status
= arm_init_machine_status
;
13541 /* This is to stop the combine pass optimizing away the alignment
13542 adjustment of va_arg. */
13543 /* ??? It is claimed that this should not be necessary. */
13545 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13549 /* Like arm_compute_initial_elimination offset. Simpler because there
13550 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13551 to point at the base of the local variables after static stack
13552 space for a function has been allocated. */
13555 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13557 arm_stack_offsets
*offsets
;
13559 offsets
= arm_get_frame_offsets ();
13563 case ARG_POINTER_REGNUM
:
13566 case STACK_POINTER_REGNUM
:
13567 return offsets
->outgoing_args
- offsets
->saved_args
;
13569 case FRAME_POINTER_REGNUM
:
13570 return offsets
->soft_frame
- offsets
->saved_args
;
13572 case ARM_HARD_FRAME_POINTER_REGNUM
:
13573 return offsets
->saved_regs
- offsets
->saved_args
;
13575 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13576 return offsets
->locals_base
- offsets
->saved_args
;
13579 gcc_unreachable ();
13583 case FRAME_POINTER_REGNUM
:
13586 case STACK_POINTER_REGNUM
:
13587 return offsets
->outgoing_args
- offsets
->soft_frame
;
13589 case ARM_HARD_FRAME_POINTER_REGNUM
:
13590 return offsets
->saved_regs
- offsets
->soft_frame
;
13592 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13593 return offsets
->locals_base
- offsets
->soft_frame
;
13596 gcc_unreachable ();
13601 gcc_unreachable ();
13606 /* Generate the rest of a function's prologue. */
13608 thumb_expand_prologue (void)
13612 HOST_WIDE_INT amount
;
13613 arm_stack_offsets
*offsets
;
13614 unsigned long func_type
;
13616 unsigned long live_regs_mask
;
13618 func_type
= arm_current_func_type ();
13620 /* Naked functions don't have prologues. */
13621 if (IS_NAKED (func_type
))
13624 if (IS_INTERRUPT (func_type
))
13626 error ("interrupt Service Routines cannot be coded in Thumb mode");
13630 live_regs_mask
= thumb_compute_save_reg_mask ();
13631 /* Load the pic register before setting the frame pointer,
13632 so we can use r7 as a temporary work register. */
13633 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
13634 arm_load_pic_register (live_regs_mask
);
13636 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13637 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13638 stack_pointer_rtx
);
13640 offsets
= arm_get_frame_offsets ();
13641 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13646 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13647 GEN_INT (- amount
)));
13648 RTX_FRAME_RELATED_P (insn
) = 1;
13654 /* The stack decrement is too big for an immediate value in a single
13655 insn. In theory we could issue multiple subtracts, but after
13656 three of them it becomes more space efficient to place the full
13657 value in the constant pool and load into a register. (Also the
13658 ARM debugger really likes to see only one stack decrement per
13659 function). So instead we look for a scratch register into which
13660 we can load the decrement, and then we subtract this from the
13661 stack pointer. Unfortunately on the thumb the only available
13662 scratch registers are the argument registers, and we cannot use
13663 these as they may hold arguments to the function. Instead we
13664 attempt to locate a call preserved register which is used by this
13665 function. If we can find one, then we know that it will have
13666 been pushed at the start of the prologue and so we can corrupt
13668 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13669 if (live_regs_mask
& (1 << regno
)
13670 && !(frame_pointer_needed
13671 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13674 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13676 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13678 /* Choose an arbitrary, non-argument low register. */
13679 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13681 /* Save it by copying it into a high, scratch register. */
13682 emit_insn (gen_movsi (spare
, reg
));
13683 /* Add a USE to stop propagate_one_insn() from barfing. */
13684 emit_insn (gen_prologue_use (spare
));
13686 /* Decrement the stack. */
13687 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13688 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13689 stack_pointer_rtx
, reg
));
13690 RTX_FRAME_RELATED_P (insn
) = 1;
13691 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13692 plus_constant (stack_pointer_rtx
,
13694 RTX_FRAME_RELATED_P (dwarf
) = 1;
13696 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13699 /* Restore the low register's original value. */
13700 emit_insn (gen_movsi (reg
, spare
));
13702 /* Emit a USE of the restored scratch register, so that flow
13703 analysis will not consider the restore redundant. The
13704 register won't be used again in this function and isn't
13705 restored by the epilogue. */
13706 emit_insn (gen_prologue_use (reg
));
13710 reg
= gen_rtx_REG (SImode
, regno
);
13712 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13714 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13715 stack_pointer_rtx
, reg
));
13716 RTX_FRAME_RELATED_P (insn
) = 1;
13717 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13718 plus_constant (stack_pointer_rtx
,
13720 RTX_FRAME_RELATED_P (dwarf
) = 1;
13722 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13728 if (frame_pointer_needed
)
13730 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13733 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13734 stack_pointer_rtx
, GEN_INT (amount
)));
13737 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13738 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13739 hard_frame_pointer_rtx
,
13740 stack_pointer_rtx
));
13741 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
13742 plus_constant (stack_pointer_rtx
, amount
));
13743 RTX_FRAME_RELATED_P (dwarf
) = 1;
13744 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13748 RTX_FRAME_RELATED_P (insn
) = 1;
13751 /* If we are profiling, make sure no instructions are scheduled before
13752 the call to mcount. Similarly if the user has requested no
13753 scheduling in the prolog. Similarly if we want non-call exceptions
13754 using the EABI unwinder, to prevent faulting instructions from being
13755 swapped with a stack adjustment. */
13756 if (current_function_profile
|| !TARGET_SCHED_PROLOG
13757 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
13758 emit_insn (gen_blockage ());
13760 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13761 if (live_regs_mask
& 0xff)
13762 cfun
->machine
->lr_save_eliminated
= 0;
13764 /* If the link register is being kept alive, with the return address in it,
13765 then make sure that it does not get reused by the ce2 pass. */
13766 if (cfun
->machine
->lr_save_eliminated
)
13767 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13772 thumb_expand_epilogue (void)
13774 HOST_WIDE_INT amount
;
13775 arm_stack_offsets
*offsets
;
13778 /* Naked functions don't have prologues. */
13779 if (IS_NAKED (arm_current_func_type ()))
13782 offsets
= arm_get_frame_offsets ();
13783 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13785 if (frame_pointer_needed
)
13787 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13788 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13794 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13795 GEN_INT (amount
)));
13798 /* r3 is always free in the epilogue. */
13799 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13801 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13802 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13806 /* Emit a USE (stack_pointer_rtx), so that
13807 the stack adjustment will not be deleted. */
13808 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13810 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13811 emit_insn (gen_blockage ());
13813 /* Emit a clobber for each insn that will be restored in the epilogue,
13814 so that flow2 will get register lifetimes correct. */
13815 for (regno
= 0; regno
< 13; regno
++)
13816 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13817 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13819 if (! regs_ever_live
[LR_REGNUM
])
13820 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13824 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13826 unsigned long live_regs_mask
= 0;
13827 unsigned long l_mask
;
13828 unsigned high_regs_pushed
= 0;
13829 int cfa_offset
= 0;
13832 if (IS_NAKED (arm_current_func_type ()))
13835 if (is_called_in_ARM_mode (current_function_decl
))
13839 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13840 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13842 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13844 /* Generate code sequence to switch us into Thumb mode. */
13845 /* The .code 32 directive has already been emitted by
13846 ASM_DECLARE_FUNCTION_NAME. */
13847 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13848 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13850 /* Generate a label, so that the debugger will notice the
13851 change in instruction sets. This label is also used by
13852 the assembler to bypass the ARM code when this function
13853 is called from a Thumb encoded function elsewhere in the
13854 same file. Hence the definition of STUB_NAME here must
13855 agree with the definition in gas/config/tc-arm.c. */
13857 #define STUB_NAME ".real_start_of"
13859 fprintf (f
, "\t.code\t16\n");
13861 if (arm_dllexport_name_p (name
))
13862 name
= arm_strip_name_encoding (name
);
13864 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13865 fprintf (f
, "\t.thumb_func\n");
13866 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13869 if (current_function_pretend_args_size
)
13871 /* Output unwind directive for the stack adjustment. */
13872 if (ARM_EABI_UNWIND_TABLES
)
13873 fprintf (f
, "\t.pad #%d\n",
13874 current_function_pretend_args_size
);
13876 if (cfun
->machine
->uses_anonymous_args
)
13880 fprintf (f
, "\tpush\t{");
13882 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13884 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13885 regno
<= LAST_ARG_REGNUM
;
13887 asm_fprintf (f
, "%r%s", regno
,
13888 regno
== LAST_ARG_REGNUM
? "" : ", ");
13890 fprintf (f
, "}\n");
13893 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13894 SP_REGNUM
, SP_REGNUM
,
13895 current_function_pretend_args_size
);
13897 /* We don't need to record the stores for unwinding (would it
13898 help the debugger any if we did?), but record the change in
13899 the stack pointer. */
13900 if (dwarf2out_do_frame ())
13902 char *l
= dwarf2out_cfi_label ();
13904 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13905 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13909 /* Get the registers we are going to push. */
13910 live_regs_mask
= thumb_compute_save_reg_mask ();
13911 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13912 l_mask
= live_regs_mask
& 0x40ff;
13913 /* Then count how many other high registers will need to be pushed. */
13914 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13916 if (TARGET_BACKTRACE
)
13919 unsigned work_register
;
13921 /* We have been asked to create a stack backtrace structure.
13922 The code looks like this:
13926 0 sub SP, #16 Reserve space for 4 registers.
13927 2 push {R7} Push low registers.
13928 4 add R7, SP, #20 Get the stack pointer before the push.
13929 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13930 8 mov R7, PC Get hold of the start of this code plus 12.
13931 10 str R7, [SP, #16] Store it.
13932 12 mov R7, FP Get hold of the current frame pointer.
13933 14 str R7, [SP, #4] Store it.
13934 16 mov R7, LR Get hold of the current return address.
13935 18 str R7, [SP, #12] Store it.
13936 20 add R7, SP, #16 Point at the start of the backtrace structure.
13937 22 mov FP, R7 Put this value into the frame pointer. */
13939 work_register
= thumb_find_work_register (live_regs_mask
);
13941 if (ARM_EABI_UNWIND_TABLES
)
13942 asm_fprintf (f
, "\t.pad #16\n");
13945 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13946 SP_REGNUM
, SP_REGNUM
);
13948 if (dwarf2out_do_frame ())
13950 char *l
= dwarf2out_cfi_label ();
13952 cfa_offset
= cfa_offset
+ 16;
13953 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13958 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13959 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13964 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13965 offset
+ 16 + current_function_pretend_args_size
);
13967 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13970 /* Make sure that the instruction fetching the PC is in the right place
13971 to calculate "start of backtrace creation code + 12". */
13974 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13975 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13977 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13978 ARM_HARD_FRAME_POINTER_REGNUM
);
13979 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13984 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13985 ARM_HARD_FRAME_POINTER_REGNUM
);
13986 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13988 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13989 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13993 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13994 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13996 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13998 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13999 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
14001 /* Optimization: If we are not pushing any low registers but we are going
14002 to push some high registers then delay our first push. This will just
14003 be a push of LR and we can combine it with the push of the first high
14005 else if ((l_mask
& 0xff) != 0
14006 || (high_regs_pushed
== 0 && l_mask
))
14007 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14009 if (high_regs_pushed
)
14011 unsigned pushable_regs
;
14012 unsigned next_hi_reg
;
14014 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
14015 if (live_regs_mask
& (1 << next_hi_reg
))
14018 pushable_regs
= l_mask
& 0xff;
14020 if (pushable_regs
== 0)
14021 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
14023 while (high_regs_pushed
> 0)
14025 unsigned long real_regs_mask
= 0;
14027 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
14029 if (pushable_regs
& (1 << regno
))
14031 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
14033 high_regs_pushed
--;
14034 real_regs_mask
|= (1 << next_hi_reg
);
14036 if (high_regs_pushed
)
14038 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
14040 if (live_regs_mask
& (1 << next_hi_reg
))
14045 pushable_regs
&= ~((1 << regno
) - 1);
14051 /* If we had to find a work register and we have not yet
14052 saved the LR then add it to the list of regs to push. */
14053 if (l_mask
== (1 << LR_REGNUM
))
14055 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14057 real_regs_mask
| (1 << LR_REGNUM
));
14061 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14066 /* Handle the case of a double word load into a low register from
14067 a computed memory address. The computed address may involve a
14068 register which is overwritten by the load. */
14070 thumb_load_double_from_address (rtx
*operands
)
14078 gcc_assert (GET_CODE (operands
[0]) == REG
);
14079 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14081 /* Get the memory address. */
14082 addr
= XEXP (operands
[1], 0);
14084 /* Work out how the memory address is computed. */
14085 switch (GET_CODE (addr
))
14088 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14090 if (REGNO (operands
[0]) == REGNO (addr
))
14092 output_asm_insn ("ldr\t%H0, %2", operands
);
14093 output_asm_insn ("ldr\t%0, %1", operands
);
14097 output_asm_insn ("ldr\t%0, %1", operands
);
14098 output_asm_insn ("ldr\t%H0, %2", operands
);
14103 /* Compute <address> + 4 for the high order load. */
14104 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14106 output_asm_insn ("ldr\t%0, %1", operands
);
14107 output_asm_insn ("ldr\t%H0, %2", operands
);
14111 arg1
= XEXP (addr
, 0);
14112 arg2
= XEXP (addr
, 1);
14114 if (CONSTANT_P (arg1
))
14115 base
= arg2
, offset
= arg1
;
14117 base
= arg1
, offset
= arg2
;
14119 gcc_assert (GET_CODE (base
) == REG
);
14121 /* Catch the case of <address> = <reg> + <reg> */
14122 if (GET_CODE (offset
) == REG
)
14124 int reg_offset
= REGNO (offset
);
14125 int reg_base
= REGNO (base
);
14126 int reg_dest
= REGNO (operands
[0]);
14128 /* Add the base and offset registers together into the
14129 higher destination register. */
14130 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14131 reg_dest
+ 1, reg_base
, reg_offset
);
14133 /* Load the lower destination register from the address in
14134 the higher destination register. */
14135 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14136 reg_dest
, reg_dest
+ 1);
14138 /* Load the higher destination register from its own address
14140 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14141 reg_dest
+ 1, reg_dest
+ 1);
14145 /* Compute <address> + 4 for the high order load. */
14146 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14148 /* If the computed address is held in the low order register
14149 then load the high order register first, otherwise always
14150 load the low order register first. */
14151 if (REGNO (operands
[0]) == REGNO (base
))
14153 output_asm_insn ("ldr\t%H0, %2", operands
);
14154 output_asm_insn ("ldr\t%0, %1", operands
);
14158 output_asm_insn ("ldr\t%0, %1", operands
);
14159 output_asm_insn ("ldr\t%H0, %2", operands
);
14165 /* With no registers to worry about we can just load the value
14167 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14169 output_asm_insn ("ldr\t%H0, %2", operands
);
14170 output_asm_insn ("ldr\t%0, %1", operands
);
14174 gcc_unreachable ();
14181 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14188 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14191 operands
[4] = operands
[5];
14194 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14195 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14199 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14202 operands
[4] = operands
[5];
14205 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14208 operands
[5] = operands
[6];
14211 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14214 operands
[4] = operands
[5];
14218 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14219 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14223 gcc_unreachable ();
14229 /* Output a call-via instruction for thumb state. */
14231 thumb_call_via_reg (rtx reg
)
14233 int regno
= REGNO (reg
);
14236 gcc_assert (regno
< LR_REGNUM
);
14238 /* If we are in the normal text section we can use a single instance
14239 per compilation unit. If we are doing function sections, then we need
14240 an entry per section, since we can't rely on reachability. */
14241 if (in_section
== text_section
)
14243 thumb_call_reg_needed
= 1;
14245 if (thumb_call_via_label
[regno
] == NULL
)
14246 thumb_call_via_label
[regno
] = gen_label_rtx ();
14247 labelp
= thumb_call_via_label
+ regno
;
14251 if (cfun
->machine
->call_via
[regno
] == NULL
)
14252 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
14253 labelp
= cfun
->machine
->call_via
+ regno
;
14256 output_asm_insn ("bl\t%a0", labelp
);
14260 /* Routines for generating rtl. */
14262 thumb_expand_movmemqi (rtx
*operands
)
14264 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
14265 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
14266 HOST_WIDE_INT len
= INTVAL (operands
[2]);
14267 HOST_WIDE_INT offset
= 0;
14271 emit_insn (gen_movmem12b (out
, in
, out
, in
));
14277 emit_insn (gen_movmem8b (out
, in
, out
, in
));
14283 rtx reg
= gen_reg_rtx (SImode
);
14284 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
14285 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
14292 rtx reg
= gen_reg_rtx (HImode
);
14293 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
14294 plus_constant (in
, offset
))));
14295 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
14303 rtx reg
= gen_reg_rtx (QImode
);
14304 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
14305 plus_constant (in
, offset
))));
14306 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
14312 thumb_reload_out_hi (rtx
*operands
)
14314 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14317 /* Handle reading a half-word from memory during reload. */
14319 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14321 gcc_unreachable ();
14324 /* Return the length of a function name prefix
14325 that starts with the character 'c'. */
14327 arm_get_strip_length (int c
)
14331 ARM_NAME_ENCODING_LENGTHS
14336 /* Return a pointer to a function's name with any
14337 and all prefix encodings stripped from it. */
14339 arm_strip_name_encoding (const char *name
)
14343 while ((skip
= arm_get_strip_length (* name
)))
14349 /* If there is a '*' anywhere in the name's prefix, then
14350 emit the stripped name verbatim, otherwise prepend an
14351 underscore if leading underscores are being used. */
14353 arm_asm_output_labelref (FILE *stream
, const char *name
)
14358 while ((skip
= arm_get_strip_length (* name
)))
14360 verbatim
|= (*name
== '*');
14365 fputs (name
, stream
);
14367 asm_fprintf (stream
, "%U%s", name
);
14371 arm_file_end (void)
14375 if (! thumb_call_reg_needed
)
14378 switch_to_section (text_section
);
14379 asm_fprintf (asm_out_file
, "\t.code 16\n");
14380 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
14382 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14384 rtx label
= thumb_call_via_label
[regno
];
14388 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14389 CODE_LABEL_NUMBER (label
));
14390 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14397 #ifdef AOF_ASSEMBLER
14398 /* Special functions only needed when producing AOF syntax assembler. */
14402 struct pic_chain
* next
;
14403 const char * symname
;
14406 static struct pic_chain
* aof_pic_chain
= NULL
;
14409 aof_pic_entry (rtx x
)
14411 struct pic_chain
** chainp
;
14414 if (aof_pic_label
== NULL_RTX
)
14416 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14419 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14420 offset
+= 4, chainp
= &(*chainp
)->next
)
14421 if ((*chainp
)->symname
== XSTR (x
, 0))
14422 return plus_constant (aof_pic_label
, offset
);
14424 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14425 (*chainp
)->next
= NULL
;
14426 (*chainp
)->symname
= XSTR (x
, 0);
14427 return plus_constant (aof_pic_label
, offset
);
14431 aof_dump_pic_table (FILE *f
)
14433 struct pic_chain
* chain
;
14435 if (aof_pic_chain
== NULL
)
14438 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14439 PIC_OFFSET_TABLE_REGNUM
,
14440 PIC_OFFSET_TABLE_REGNUM
);
14441 fputs ("|x$adcons|\n", f
);
14443 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14445 fputs ("\tDCD\t", f
);
14446 assemble_name (f
, chain
->symname
);
14451 int arm_text_section_count
= 1;
14453 /* A get_unnamed_section callback for switching to the text section. */
14456 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
14458 fprintf (asm_out_file
, "\tAREA |C$$code%d|, CODE, READONLY",
14459 arm_text_section_count
++);
14461 fprintf (asm_out_file
, ", PIC, REENTRANT");
14462 fprintf (asm_out_file
, "\n");
14465 static int arm_data_section_count
= 1;
14467 /* A get_unnamed_section callback for switching to the data section. */
14470 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
14472 fprintf (asm_out_file
, "\tAREA |C$$data%d|, DATA\n",
14473 arm_data_section_count
++);
14476 /* Implement TARGET_ASM_INIT_SECTIONS.
14478 AOF Assembler syntax is a nightmare when it comes to areas, since once
14479 we change from one area to another, we can't go back again. Instead,
14480 we must create a new area with the same attributes and add the new output
14481 to that. Unfortunately, there is nothing we can do here to guarantee that
14482 two areas with the same attributes will be linked adjacently in the
14483 resulting executable, so we have to be careful not to do pc-relative
14484 addressing across such boundaries. */
14487 aof_asm_init_sections (void)
14489 text_section
= get_unnamed_section (SECTION_CODE
,
14490 aof_output_text_section_asm_op
, NULL
);
14491 data_section
= get_unnamed_section (SECTION_WRITE
,
14492 aof_output_data_section_asm_op
, NULL
);
14493 readonly_data_section
= text_section
;
14497 zero_init_section (void)
14499 static int zero_init_count
= 1;
14501 fprintf (asm_out_file
, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count
++);
14505 /* The AOF assembler is religiously strict about declarations of
14506 imported and exported symbols, so that it is impossible to declare
14507 a function as imported near the beginning of the file, and then to
14508 export it later on. It is, however, possible to delay the decision
14509 until all the functions in the file have been compiled. To get
14510 around this, we maintain a list of the imports and exports, and
14511 delete from it any that are subsequently defined. At the end of
14512 compilation we spit the remainder of the list out before the END
14517 struct import
* next
;
14521 static struct import
* imports_list
= NULL
;
14524 aof_add_import (const char *name
)
14526 struct import
* new;
14528 for (new = imports_list
; new; new = new->next
)
14529 if (new->name
== name
)
14532 new = (struct import
*) xmalloc (sizeof (struct import
));
14533 new->next
= imports_list
;
14534 imports_list
= new;
14539 aof_delete_import (const char *name
)
14541 struct import
** old
;
14543 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14545 if ((*old
)->name
== name
)
14547 *old
= (*old
)->next
;
14553 int arm_main_function
= 0;
14556 aof_dump_imports (FILE *f
)
14558 /* The AOF assembler needs this to cause the startup code to be extracted
14559 from the library. Brining in __main causes the whole thing to work
14561 if (arm_main_function
)
14563 switch_to_section (text_section
);
14564 fputs ("\tIMPORT __main\n", f
);
14565 fputs ("\tDCD __main\n", f
);
14568 /* Now dump the remaining imports. */
14569 while (imports_list
)
14571 fprintf (f
, "\tIMPORT\t");
14572 assemble_name (f
, imports_list
->name
);
14574 imports_list
= imports_list
->next
;
14579 aof_globalize_label (FILE *stream
, const char *name
)
14581 default_globalize_label (stream
, name
);
14582 if (! strcmp (name
, "main"))
14583 arm_main_function
= 1;
14587 aof_file_start (void)
14589 fputs ("__r0\tRN\t0\n", asm_out_file
);
14590 fputs ("__a1\tRN\t0\n", asm_out_file
);
14591 fputs ("__a2\tRN\t1\n", asm_out_file
);
14592 fputs ("__a3\tRN\t2\n", asm_out_file
);
14593 fputs ("__a4\tRN\t3\n", asm_out_file
);
14594 fputs ("__v1\tRN\t4\n", asm_out_file
);
14595 fputs ("__v2\tRN\t5\n", asm_out_file
);
14596 fputs ("__v3\tRN\t6\n", asm_out_file
);
14597 fputs ("__v4\tRN\t7\n", asm_out_file
);
14598 fputs ("__v5\tRN\t8\n", asm_out_file
);
14599 fputs ("__v6\tRN\t9\n", asm_out_file
);
14600 fputs ("__sl\tRN\t10\n", asm_out_file
);
14601 fputs ("__fp\tRN\t11\n", asm_out_file
);
14602 fputs ("__ip\tRN\t12\n", asm_out_file
);
14603 fputs ("__sp\tRN\t13\n", asm_out_file
);
14604 fputs ("__lr\tRN\t14\n", asm_out_file
);
14605 fputs ("__pc\tRN\t15\n", asm_out_file
);
14606 fputs ("__f0\tFN\t0\n", asm_out_file
);
14607 fputs ("__f1\tFN\t1\n", asm_out_file
);
14608 fputs ("__f2\tFN\t2\n", asm_out_file
);
14609 fputs ("__f3\tFN\t3\n", asm_out_file
);
14610 fputs ("__f4\tFN\t4\n", asm_out_file
);
14611 fputs ("__f5\tFN\t5\n", asm_out_file
);
14612 fputs ("__f6\tFN\t6\n", asm_out_file
);
14613 fputs ("__f7\tFN\t7\n", asm_out_file
);
14614 switch_to_section (text_section
);
14618 aof_file_end (void)
14621 aof_dump_pic_table (asm_out_file
);
14623 aof_dump_imports (asm_out_file
);
14624 fputs ("\tEND\n", asm_out_file
);
14626 #endif /* AOF_ASSEMBLER */
14629 /* Symbols in the text segment can be accessed without indirecting via the
14630 constant pool; it may take an extra binary operation, but this is still
14631 faster than indirecting via memory. Don't do this when not optimizing,
14632 since we won't be calculating al of the offsets necessary to do this
14636 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14638 /* This doesn't work with AOF syntax, since the string table may be in
14639 a different AREA. */
14640 #ifndef AOF_ASSEMBLER
14641 if (optimize
> 0 && TREE_CONSTANT (decl
))
14642 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14645 /* If we are referencing a function that is weak then encode a long call
14646 flag in the function name, otherwise if the function is static or
14647 or known to be defined in this file then encode a short call flag. */
14648 if (first
&& DECL_P (decl
))
14650 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14651 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14652 else if (! TREE_PUBLIC (decl
))
14653 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14656 default_encode_section_info (decl
, rtl
, first
);
14658 #endif /* !ARM_PE */
14661 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14663 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14664 && !strcmp (prefix
, "L"))
14666 arm_ccfsm_state
= 0;
14667 arm_target_insn
= NULL
;
14669 default_internal_label (stream
, prefix
, labelno
);
14672 /* Output code to add DELTA to the first argument, and then jump
14673 to FUNCTION. Used for C++ multiple inheritance. */
14675 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14676 HOST_WIDE_INT delta
,
14677 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14680 static int thunk_label
= 0;
14682 int mi_delta
= delta
;
14683 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14685 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14688 mi_delta
= - mi_delta
;
14691 int labelno
= thunk_label
++;
14692 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14693 fputs ("\tldr\tr12, ", file
);
14694 assemble_name (file
, label
);
14695 fputc ('\n', file
);
14697 while (mi_delta
!= 0)
14699 if ((mi_delta
& (3 << shift
)) == 0)
14703 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14704 mi_op
, this_regno
, this_regno
,
14705 mi_delta
& (0xff << shift
));
14706 mi_delta
&= ~(0xff << shift
);
14712 fprintf (file
, "\tbx\tr12\n");
14713 ASM_OUTPUT_ALIGN (file
, 2);
14714 assemble_name (file
, label
);
14715 fputs (":\n", file
);
14716 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14720 fputs ("\tb\t", file
);
14721 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14722 if (NEED_PLT_RELOC
)
14723 fputs ("(PLT)", file
);
14724 fputc ('\n', file
);
14729 arm_emit_vector_const (FILE *file
, rtx x
)
14732 const char * pattern
;
14734 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14736 switch (GET_MODE (x
))
14738 case V2SImode
: pattern
= "%08x"; break;
14739 case V4HImode
: pattern
= "%04x"; break;
14740 case V8QImode
: pattern
= "%02x"; break;
14741 default: gcc_unreachable ();
14744 fprintf (file
, "0x");
14745 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14749 element
= CONST_VECTOR_ELT (x
, i
);
14750 fprintf (file
, pattern
, INTVAL (element
));
14757 arm_output_load_gr (rtx
*operands
)
14764 if (GET_CODE (operands
[1]) != MEM
14765 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14766 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14767 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14768 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14769 return "wldrw%?\t%0, %1";
14771 /* Fix up an out-of-range load of a GR register. */
14772 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14773 wcgr
= operands
[0];
14775 output_asm_insn ("ldr%?\t%0, %1", operands
);
14777 operands
[0] = wcgr
;
14779 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14780 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14786 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14787 int incoming ATTRIBUTE_UNUSED
)
14790 /* FIXME: The ARM backend has special code to handle structure
14791 returns, and will reserve its own hidden first argument. So
14792 if this macro is enabled a *second* hidden argument will be
14793 reserved, which will break binary compatibility with old
14794 toolchains and also thunk handling. One day this should be
14798 /* Register in which address to store a structure value
14799 is passed to a function. */
14800 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14804 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14806 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14807 named arg and all anonymous args onto the stack.
14808 XXX I know the prologue shouldn't be pushing registers, but it is faster
14812 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14813 enum machine_mode mode ATTRIBUTE_UNUSED
,
14814 tree type ATTRIBUTE_UNUSED
,
14816 int second_time ATTRIBUTE_UNUSED
)
14818 cfun
->machine
->uses_anonymous_args
= 1;
14819 if (cum
->nregs
< NUM_ARG_REGS
)
14820 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14823 /* Return nonzero if the CONSUMER instruction (a store) does not need
14824 PRODUCER's value to calculate the address. */
14827 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14829 rtx value
= PATTERN (producer
);
14830 rtx addr
= PATTERN (consumer
);
14832 if (GET_CODE (value
) == COND_EXEC
)
14833 value
= COND_EXEC_CODE (value
);
14834 if (GET_CODE (value
) == PARALLEL
)
14835 value
= XVECEXP (value
, 0, 0);
14836 value
= XEXP (value
, 0);
14837 if (GET_CODE (addr
) == COND_EXEC
)
14838 addr
= COND_EXEC_CODE (addr
);
14839 if (GET_CODE (addr
) == PARALLEL
)
14840 addr
= XVECEXP (addr
, 0, 0);
14841 addr
= XEXP (addr
, 0);
14843 return !reg_overlap_mentioned_p (value
, addr
);
14846 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14847 have an early register shift value or amount dependency on the
14848 result of PRODUCER. */
14851 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14853 rtx value
= PATTERN (producer
);
14854 rtx op
= PATTERN (consumer
);
14857 if (GET_CODE (value
) == COND_EXEC
)
14858 value
= COND_EXEC_CODE (value
);
14859 if (GET_CODE (value
) == PARALLEL
)
14860 value
= XVECEXP (value
, 0, 0);
14861 value
= XEXP (value
, 0);
14862 if (GET_CODE (op
) == COND_EXEC
)
14863 op
= COND_EXEC_CODE (op
);
14864 if (GET_CODE (op
) == PARALLEL
)
14865 op
= XVECEXP (op
, 0, 0);
14868 early_op
= XEXP (op
, 0);
14869 /* This is either an actual independent shift, or a shift applied to
14870 the first operand of another operation. We want the whole shift
14872 if (GET_CODE (early_op
) == REG
)
14875 return !reg_overlap_mentioned_p (value
, early_op
);
14878 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14879 have an early register shift value dependency on the result of
14883 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14885 rtx value
= PATTERN (producer
);
14886 rtx op
= PATTERN (consumer
);
14889 if (GET_CODE (value
) == COND_EXEC
)
14890 value
= COND_EXEC_CODE (value
);
14891 if (GET_CODE (value
) == PARALLEL
)
14892 value
= XVECEXP (value
, 0, 0);
14893 value
= XEXP (value
, 0);
14894 if (GET_CODE (op
) == COND_EXEC
)
14895 op
= COND_EXEC_CODE (op
);
14896 if (GET_CODE (op
) == PARALLEL
)
14897 op
= XVECEXP (op
, 0, 0);
14900 early_op
= XEXP (op
, 0);
14902 /* This is either an actual independent shift, or a shift applied to
14903 the first operand of another operation. We want the value being
14904 shifted, in either case. */
14905 if (GET_CODE (early_op
) != REG
)
14906 early_op
= XEXP (early_op
, 0);
14908 return !reg_overlap_mentioned_p (value
, early_op
);
14911 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14912 have an early register mult dependency on the result of
14916 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14918 rtx value
= PATTERN (producer
);
14919 rtx op
= PATTERN (consumer
);
14921 if (GET_CODE (value
) == COND_EXEC
)
14922 value
= COND_EXEC_CODE (value
);
14923 if (GET_CODE (value
) == PARALLEL
)
14924 value
= XVECEXP (value
, 0, 0);
14925 value
= XEXP (value
, 0);
14926 if (GET_CODE (op
) == COND_EXEC
)
14927 op
= COND_EXEC_CODE (op
);
14928 if (GET_CODE (op
) == PARALLEL
)
14929 op
= XVECEXP (op
, 0, 0);
14932 return (GET_CODE (op
) == PLUS
14933 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14937 /* We can't rely on the caller doing the proper promotion when
14938 using APCS or ATPCS. */
14941 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14943 return !TARGET_AAPCS_BASED
;
14947 /* AAPCS based ABIs use short enums by default. */
14950 arm_default_short_enums (void)
14952 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
14956 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14959 arm_align_anon_bitfield (void)
14961 return TARGET_AAPCS_BASED
;
14965 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14968 arm_cxx_guard_type (void)
14970 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14974 /* The EABI says test the least significant bit of a guard variable. */
14977 arm_cxx_guard_mask_bit (void)
14979 return TARGET_AAPCS_BASED
;
14983 /* The EABI specifies that all array cookies are 8 bytes long. */
14986 arm_get_cookie_size (tree type
)
14990 if (!TARGET_AAPCS_BASED
)
14991 return default_cxx_get_cookie_size (type
);
14993 size
= build_int_cst (sizetype
, 8);
14998 /* The EABI says that array cookies should also contain the element size. */
15001 arm_cookie_has_size (void)
15003 return TARGET_AAPCS_BASED
;
15007 /* The EABI says constructors and destructors should return a pointer to
15008 the object constructed/destroyed. */
15011 arm_cxx_cdtor_returns_this (void)
15013 return TARGET_AAPCS_BASED
;
15016 /* The EABI says that an inline function may never be the key
15020 arm_cxx_key_method_may_be_inline (void)
15022 return !TARGET_AAPCS_BASED
;
15026 arm_cxx_determine_class_data_visibility (tree decl
)
15028 if (!TARGET_AAPCS_BASED
)
15031 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15032 is exported. However, on systems without dynamic vague linkage,
15033 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15034 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
15035 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
15037 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
15038 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
15042 arm_cxx_class_data_always_comdat (void)
15044 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15045 vague linkage if the class has no key function. */
15046 return !TARGET_AAPCS_BASED
;
15050 /* The EABI says __aeabi_atexit should be used to register static
15054 arm_cxx_use_aeabi_atexit (void)
15056 return TARGET_AAPCS_BASED
;
15061 arm_set_return_address (rtx source
, rtx scratch
)
15063 arm_stack_offsets
*offsets
;
15064 HOST_WIDE_INT delta
;
15066 unsigned long saved_regs
;
15068 saved_regs
= arm_compute_save_reg_mask ();
15070 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
15071 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15074 if (frame_pointer_needed
)
15075 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
15078 /* LR will be the first saved register. */
15079 offsets
= arm_get_frame_offsets ();
15080 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15085 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15086 GEN_INT (delta
& ~4095)));
15091 addr
= stack_pointer_rtx
;
15093 addr
= plus_constant (addr
, delta
);
15095 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15101 thumb_set_return_address (rtx source
, rtx scratch
)
15103 arm_stack_offsets
*offsets
;
15104 HOST_WIDE_INT delta
;
15107 unsigned long mask
;
15109 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15111 mask
= thumb_compute_save_reg_mask ();
15112 if (mask
& (1 << LR_REGNUM
))
15114 offsets
= arm_get_frame_offsets ();
15116 /* Find the saved regs. */
15117 if (frame_pointer_needed
)
15119 delta
= offsets
->soft_frame
- offsets
->saved_args
;
15120 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
15124 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
15127 /* Allow for the stack frame. */
15128 if (TARGET_BACKTRACE
)
15130 /* The link register is always the first saved register. */
15133 /* Construct the address. */
15134 addr
= gen_rtx_REG (SImode
, reg
);
15135 if ((reg
!= SP_REGNUM
&& delta
>= 128)
15138 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
15139 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
15143 addr
= plus_constant (addr
, delta
);
15145 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15148 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15151 /* Implements target hook vector_mode_supported_p. */
15153 arm_vector_mode_supported_p (enum machine_mode mode
)
15155 if ((mode
== V2SImode
)
15156 || (mode
== V4HImode
)
15157 || (mode
== V8QImode
))
15163 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15164 ARM insns and therefore guarantee that the shift count is modulo 256.
15165 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15166 guarantee no particular behavior for out-of-range counts. */
15168 static unsigned HOST_WIDE_INT
15169 arm_shift_truncation_mask (enum machine_mode mode
)
15171 return mode
== SImode
? 255 : 0;
15175 /* Map internal gcc register numbers to DWARF2 register numbers. */
15178 arm_dbx_register_number (unsigned int regno
)
15183 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15184 compatibility. The EABI defines them as registers 96-103. */
15185 if (IS_FPA_REGNUM (regno
))
15186 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
15188 if (IS_VFP_REGNUM (regno
))
15189 return 64 + regno
- FIRST_VFP_REGNUM
;
15191 if (IS_IWMMXT_GR_REGNUM (regno
))
15192 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
15194 if (IS_IWMMXT_REGNUM (regno
))
15195 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
15197 gcc_unreachable ();
15201 #ifdef TARGET_UNWIND_INFO
15202 /* Emit unwind directives for a store-multiple instruction. This should
15203 only ever be generated by the function prologue code, so we expect it
15204 to have a particular form. */
15207 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
15210 HOST_WIDE_INT offset
;
15211 HOST_WIDE_INT nregs
;
15217 /* First insn will adjust the stack pointer. */
15218 e
= XVECEXP (p
, 0, 0);
15219 if (GET_CODE (e
) != SET
15220 || GET_CODE (XEXP (e
, 0)) != REG
15221 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15222 || GET_CODE (XEXP (e
, 1)) != PLUS
)
15225 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
15226 nregs
= XVECLEN (p
, 0) - 1;
15228 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
15231 /* The function prologue may also push pc, but not annotate it as it is
15232 never restored. We turn this into a stack pointer adjustment. */
15233 if (nregs
* 4 == offset
- 4)
15235 fprintf (asm_out_file
, "\t.pad #4\n");
15240 else if (IS_VFP_REGNUM (reg
))
15242 /* FPA register saves use an additional word. */
15246 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
15248 /* FPA registers are done differently. */
15249 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
15253 /* Unknown register type. */
15256 /* If the stack increment doesn't match the size of the saved registers,
15257 something has gone horribly wrong. */
15258 if (offset
!= nregs
* reg_size
)
15261 fprintf (asm_out_file
, "\t.save {");
15265 /* The remaining insns will describe the stores. */
15266 for (i
= 1; i
<= nregs
; i
++)
15268 /* Expect (set (mem <addr>) (reg)).
15269 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15270 e
= XVECEXP (p
, 0, i
);
15271 if (GET_CODE (e
) != SET
15272 || GET_CODE (XEXP (e
, 0)) != MEM
15273 || GET_CODE (XEXP (e
, 1)) != REG
)
15276 reg
= REGNO (XEXP (e
, 1));
15281 fprintf (asm_out_file
, ", ");
15282 /* We can't use %r for vfp because we need to use the
15283 double precision register names. */
15284 if (IS_VFP_REGNUM (reg
))
15285 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
15287 asm_fprintf (asm_out_file
, "%r", reg
);
15289 #ifdef ENABLE_CHECKING
15290 /* Check that the addresses are consecutive. */
15291 e
= XEXP (XEXP (e
, 0), 0);
15292 if (GET_CODE (e
) == PLUS
)
15294 offset
+= reg_size
;
15295 if (GET_CODE (XEXP (e
, 0)) != REG
15296 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15297 || GET_CODE (XEXP (e
, 1)) != CONST_INT
15298 || offset
!= INTVAL (XEXP (e
, 1)))
15302 || GET_CODE (e
) != REG
15303 || REGNO (e
) != SP_REGNUM
)
15307 fprintf (asm_out_file
, "}\n");
15310 /* Emit unwind directives for a SET. */
15313 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
15320 switch (GET_CODE (e0
))
15323 /* Pushing a single register. */
15324 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
15325 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
15326 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
15329 asm_fprintf (asm_out_file
, "\t.save ");
15330 if (IS_VFP_REGNUM (REGNO (e1
)))
15331 asm_fprintf(asm_out_file
, "{d%d}\n",
15332 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
15334 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
15338 if (REGNO (e0
) == SP_REGNUM
)
15340 /* A stack increment. */
15341 if (GET_CODE (e1
) != PLUS
15342 || GET_CODE (XEXP (e1
, 0)) != REG
15343 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
15344 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15347 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
15348 -INTVAL (XEXP (e1
, 1)));
15350 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
15352 HOST_WIDE_INT offset
;
15355 if (GET_CODE (e1
) == PLUS
)
15357 if (GET_CODE (XEXP (e1
, 0)) != REG
15358 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15360 reg
= REGNO (XEXP (e1
, 0));
15361 offset
= INTVAL (XEXP (e1
, 1));
15362 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
15363 HARD_FRAME_POINTER_REGNUM
, reg
,
15364 INTVAL (XEXP (e1
, 1)));
15366 else if (GET_CODE (e1
) == REG
)
15369 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
15370 HARD_FRAME_POINTER_REGNUM
, reg
);
15375 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
15377 /* Move from sp to reg. */
15378 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
15390 /* Emit unwind directives for the given insn. */
15393 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
15397 if (!ARM_EABI_UNWIND_TABLES
)
15400 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
15403 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
15405 pat
= XEXP (pat
, 0);
15407 pat
= PATTERN (insn
);
15409 switch (GET_CODE (pat
))
15412 arm_unwind_emit_set (asm_out_file
, pat
);
15416 /* Store multiple. */
15417 arm_unwind_emit_stm (asm_out_file
, pat
);
15426 /* Output a reference from a function exception table to the type_info
15427 object X. The EABI specifies that the symbol should be relocated by
15428 an R_ARM_TARGET2 relocation. */
15431 arm_output_ttype (rtx x
)
15433 fputs ("\t.word\t", asm_out_file
);
15434 output_addr_const (asm_out_file
, x
);
15435 /* Use special relocations for symbol references. */
15436 if (GET_CODE (x
) != CONST_INT
)
15437 fputs ("(TARGET2)", asm_out_file
);
15438 fputc ('\n', asm_out_file
);
15442 #endif /* TARGET_UNWIND_INFO */
15445 /* Output unwind directives for the start/end of a function. */
15448 arm_output_fn_unwind (FILE * f
, bool prologue
)
15450 if (!ARM_EABI_UNWIND_TABLES
)
15454 fputs ("\t.fnstart\n", f
);
15456 fputs ("\t.fnend\n", f
);
15460 arm_emit_tls_decoration (FILE *fp
, rtx x
)
15462 enum tls_reloc reloc
;
15465 val
= XVECEXP (x
, 0, 0);
15466 reloc
= INTVAL (XVECEXP (x
, 0, 1));
15468 output_addr_const (fp
, val
);
15473 fputs ("(tlsgd)", fp
);
15476 fputs ("(tlsldm)", fp
);
15479 fputs ("(tlsldo)", fp
);
15482 fputs ("(gottpoff)", fp
);
15485 fputs ("(tpoff)", fp
);
15488 gcc_unreachable ();
15496 fputs (" + (. - ", fp
);
15497 output_addr_const (fp
, XVECEXP (x
, 0, 2));
15499 output_addr_const (fp
, XVECEXP (x
, 0, 3));
15510 arm_output_addr_const_extra (FILE *fp
, rtx x
)
15512 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
15513 return arm_emit_tls_decoration (fp
, x
);
15514 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
15517 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
15519 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
15520 assemble_name_raw (fp
, label
);
15524 else if (GET_CODE (x
) == CONST_VECTOR
)
15525 return arm_emit_vector_const (fp
, x
);
15530 #include "gt-arm.h"