| blob | 73ef7e5a554cbfdf9f87c1554de7ab5d3724c482 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
67 /* This file should be included last. */
70 /* Defined for convenience. */
71 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
73 /* Classifies an address.
75 ADDRESS_REG_IMM
76 A simple base register plus immediate offset.
78 ADDRESS_REG_WB
79 A base register indexed by immediate offset with writeback.
81 ADDRESS_REG_REG
82 A base register indexed by (optionally scaled) register.
84 ADDRESS_REG_UXTW
85 A base register indexed by (optionally scaled) zero-extended register.
87 ADDRESS_REG_SXTW
88 A base register indexed by (optionally scaled) sign-extended register.
90 ADDRESS_LO_SUM
91 A LO_SUM rtx with a base register and "LO12" symbol relocation.
93 ADDRESS_SYMBOLIC:
94 A constant symbolic address, in pc-relative literal pool. */
97 ADDRESS_REG_IMM,
98 ADDRESS_REG_WB,
99 ADDRESS_REG_REG,
100 ADDRESS_REG_UXTW,
101 ADDRESS_REG_SXTW,
102 ADDRESS_LO_SUM,
103 ADDRESS_SYMBOLIC
104 };
108 rtx base;
109 rtx offset;
112 };
114 struct simd_immediate_info
115 {
116 rtx value;
121 };
123 /* The current code model. */
126 #ifdef HAVE_AS_TLS
127 #undef TARGET_HAVE_TLS
128 #define TARGET_HAVE_TLS 1
129 #endif
133 const_tree,
144 /* Major revision number of the ARM Architecture implemented by the target. */
147 /* The processor for which instructions should be scheduled. */
150 /* Mask to specify which instruction scheduling options should be used. */
153 /* Global flag for PC relative loads. */
156 /* Support for command line parsing of boolean flags in the tuning
157 structures. */
158 struct aarch64_flag_desc
159 {
162 };
164 #define AARCH64_FUSION_PAIR(name, internal_name) \
165 { name, AARCH64_FUSE_##internal_name },
167 {
172 };
173 #undef AARCH64_FUION_PAIR
175 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
176 { name, AARCH64_EXTRA_TUNE_##internal_name },
178 {
183 };
184 #undef AARCH64_EXTRA_TUNING_OPTION
186 /* Tuning parameters. */
189 {
190 {
195 },
202 };
205 {
206 {
211 },
218 };
221 {
222 {
227 },
234 };
237 {
238 {
243 },
250 };
253 {
255 /* Avoid the use of slow int<->fp moves for spilling by setting
256 their cost higher than memmov_cost. */
260 };
263 {
265 /* Avoid the use of slow int<->fp moves for spilling by setting
266 their cost higher than memmov_cost. */
270 };
273 {
275 /* Avoid the use of slow int<->fp moves for spilling by setting
276 their cost higher than memmov_cost. */
280 };
283 {
285 /* Avoid the use of slow int<->fp moves for spilling by setting
286 their cost higher than memmov_cost (actual, 4 and 9). */
290 };
293 {
298 };
301 {
303 /* Avoid the use of slow int<->fp moves for spilling by setting
304 their cost higher than memmov_cost. */
308 };
310 /* Generic costs for vector insn classes. */
312 {
325 };
327 /* Generic costs for vector insn classes. */
329 {
342 };
345 {
358 };
360 /* Generic costs for vector insn classes. */
362 {
375 };
377 /* Generic costs for branch instructions. */
379 {
382 };
384 /* Branch costs for Cortex-A57. */
386 {
389 };
392 {
413 };
416 {
438 };
441 {
463 };
466 {
487 (AARCH64_EXTRA_TUNE_RENAME_FMA_REGS
489 };
492 {
514 };
517 {
538 };
541 {
562 };
565 {
586 };
588 /* Support for fine-grained override of the tuning structures. */
589 struct aarch64_tuning_override_function
590 {
593 };
598 static const struct aarch64_tuning_override_function
599 aarch64_tuning_override_functions[] =
600 {
604 };
606 /* A processor implementing AArch64. */
607 struct processor
608 {
616 };
618 /* Architectures implementing AArch64. */
620 {
621 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
622 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
624 #undef AARCH64_ARCH
626 };
628 /* Processor cores implementing AArch64. */
630 {
631 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
632 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
633 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
634 FLAGS, &COSTS##_tunings},
636 #undef AARCH64_CORE
640 };
643 /* Target specification. These are populated by the -march, -mtune, -mcpu
644 handling code or by target attributes. */
649 /* The current tuning set. */
652 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
654 /* An ISA extension in the co-processor and main instruction set space. */
655 struct aarch64_option_extension
656 {
660 };
662 /* ISA extensions in AArch64. */
664 {
665 #define AARCH64_OPT_EXTENSION(NAME, FLAGS_ON, FLAGS_OFF, FEATURE_STRING) \
666 {NAME, FLAGS_ON, FLAGS_OFF},
668 #undef AARCH64_OPT_EXTENSION
670 };
673 {
677 }
678 aarch64_cc;
680 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
682 /* The condition codes of the processor, and the inverse function. */
684 {
687 };
689 /* Generate code to enable conditional branches in functions over 1 MiB. */
693 {
710 }
712 void
714 {
718 else
720 }
722 static unsigned int
724 {
728 }
730 static int
733 {
741 }
743 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
744 unsigned
746 {
754 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
755 equivalent DWARF register. */
757 }
759 /* Return TRUE if MODE is any of the large INT modes. */
760 static bool
762 {
764 }
766 /* Return TRUE if MODE is any of the vector modes. */
767 static bool
769 {
772 }
774 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
775 static bool
778 {
786 }
788 /* Implement HARD_REGNO_NREGS. */
790 int
792 {
794 {
800 }
802 }
804 /* Implement HARD_REGNO_MODE_OK. */
806 int
808 {
813 /* The purpose of comparing with ptr_mode is to support the
814 global register variable associated with the stack pointer
815 register via the syntax of asm ("wsp") in ILP32. */
825 {
827 return
829 else
831 }
834 }
836 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
837 machine_mode
839 machine_mode mode)
840 {
841 /* Handle modes that fit within single registers. */
843 {
846 else
848 }
849 /* Fall back to generic for multi-reg and very large modes. */
850 else
852 }
854 /* Return true if calls to DECL should be treated as
855 long-calls (ie called via a register). */
856 static bool
858 {
860 }
862 /* Return true if calls to symbol-ref SYM should be treated as
863 long-calls (ie called via a register). */
864 bool
866 {
868 }
870 /* Return true if calls to symbol-ref SYM should not go through
871 plt stubs. */
873 bool
875 {
879 && decl
880 && (!flag_plt
886 }
888 /* Return true if the offsets to a zero/sign-extract operation
889 represent an expression that matches an extend operation. The
890 operands represent the paramters from
892 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
893 bool
895 rtx extract_imm)
896 {
913 }
915 /* Emit an insn that's a simple single-set. Both the operands must be
916 known to be valid. */
919 {
921 }
923 /* X and Y are two things to compare using CODE. Emit the compare insn and
924 return the rtx for register 0 in the proper mode. */
925 rtx
927 {
933 }
935 /* Build the SYMBOL_REF for __tls_get_addr. */
939 rtx
941 {
945 }
947 /* Return the TLS model to use for ADDR. */
949 static enum tls_model
951 {
956 {
960 }
965 }
967 /* We'll allow lo_sum's in addresses in our legitimate addresses
968 so that combine would take care of combining addresses where
969 necessary, but for generation purposes, we'll generate the address
970 as :
971 RTL Absolute
972 tmp = hi (symbol_ref); adrp x1, foo
973 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
974 nop
976 PIC TLS
977 adrp x1, :got:foo adrp tmp, :tlsgd:foo
978 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
979 bl __tls_get_addr
980 nop
982 Load TLS symbol, depending on TLS mechanism and TLS access model.
984 Global Dynamic - Traditional TLS:
985 adrp tmp, :tlsgd:imm
986 add dest, tmp, #:tlsgd_lo12:imm
987 bl __tls_get_addr
989 Global Dynamic - TLS Descriptors:
990 adrp dest, :tlsdesc:imm
991 ldr tmp, [dest, #:tlsdesc_lo12:imm]
992 add dest, dest, #:tlsdesc_lo12:imm
993 blr tmp
994 mrs tp, tpidr_el0
995 add dest, dest, tp
997 Initial Exec:
998 mrs tp, tpidr_el0
999 adrp tmp, :gottprel:imm
1000 ldr dest, [tmp, #:gottprel_lo12:imm]
1001 add dest, dest, tp
1003 Local Exec:
1004 mrs tp, tpidr_el0
1005 add t0, tp, #:tprel_hi12:imm, lsl #12
1006 add t0, t0, #:tprel_lo12_nc:imm
1007 */
1009 static void
1012 {
1014 {
1016 {
1017 /* In ILP32, the mode of dest can be either SImode or DImode. */
1029 }
1036 {
1039 rtx insn;
1040 rtx mem;
1042 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1043 here before rtl expand. Tree IVOPT will generate rtl pattern to
1044 decide rtx costs, in which case pic_offset_table_rtx is not
1045 initialized. For that case no need to generate the first adrp
1046 instruction as the final cost for global variable access is
1047 one instruction. */
1049 {
1050 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1051 using the page base as GOT base, the first page may be wasted,
1052 in the worst scenario, there is only 28K space for GOT).
1054 The generate instruction sequence for accessing global variable
1055 is:
1057 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1059 Only one instruction needed. But we must initialize
1060 pic_offset_table_rtx properly. We generate initialize insn for
1061 every global access, and allow CSE to remove all redundant.
1063 The final instruction sequences will look like the following
1064 for multiply global variables access.
1066 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1068 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1069 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1070 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1071 ... */
1079 }
1082 {
1085 else
1089 }
1090 else
1091 {
1096 }
1098 /* The operand is expected to be MEM. Whenever the related insn
1099 pattern changed, above code which calculate mem should be
1100 updated. */
1106 }
1109 {
1110 /* In ILP32, the mode of dest can be either SImode or DImode,
1111 while the got entry is always of SImode size. The mode of
1112 dest depends on how dest is used: if dest is assigned to a
1113 pointer (e.g. in the memory), it has SImode; it may have
1114 DImode if dest is dereferenced to access the memeory.
1115 This is why we have to handle three different ldr_got_small
1116 patterns here (two patterns for ILP32). */
1118 rtx insn;
1119 rtx mem;
1128 {
1131 else
1135 }
1136 else
1137 {
1142 }
1149 }
1152 {
1164 }
1167 {
1170 rtx tp;
1174 /* In ILP32, the got entry is always of SImode size. Unlike
1175 small GOT, the dest is fixed at reg 0. */
1178 else
1188 }
1191 {
1192 /* In ILP32, the mode of dest can be either SImode or DImode,
1193 while the got entry is always of SImode size. The mode of
1194 dest depends on how dest is used: if dest is assigned to a
1195 pointer (e.g. in the memory), it has SImode; it may have
1196 DImode if dest is dereferenced to access the memeory.
1197 This is why we have to handle three different tlsie_small
1198 patterns here (two patterns for ILP32). */
1204 {
1207 else
1208 {
1211 }
1212 }
1213 else
1214 {
1217 }
1222 }
1228 {
1236 {
1259 }
1263 }
1270 {
1275 {
1278 else
1279 {
1282 }
1283 }
1284 else
1285 {
1288 }
1292 }
1296 }
1297 }
1299 /* Emit a move from SRC to DEST. Assume that the move expanders can
1300 handle all moves if !can_create_pseudo_p (). The distinction is
1301 important because, unlike emit_move_insn, the move expanders know
1302 how to force Pmode objects into the constant pool even when the
1303 constant pool address is not itself legitimate. */
1304 static rtx
1306 {
1310 }
1312 /* Split a 128-bit move operation into two 64-bit move operations,
1313 taking care to handle partial overlap of register to register
1314 copies. Special cases are needed when moving between GP regs and
1315 FP regs. SRC can be a register, constant or memory; DST a register
1316 or memory. If either operand is memory it must not have any side
1317 effects. */
1318 void
1320 {
1331 {
1335 /* Handle FP <-> GP regs. */
1337 {
1342 {
1345 }
1346 else
1347 {
1350 }
1352 }
1354 {
1359 {
1362 }
1363 else
1364 {
1367 }
1369 }
1370 }
1377 /* At most one pairing may overlap. */
1379 {
1382 }
1383 else
1384 {
1387 }
1388 }
1390 bool
1392 {
1395 }
1397 /* Split a complex SIMD combine. */
1399 void
1401 {
1408 {
1412 {
1436 }
1440 }
1441 }
1443 /* Split a complex SIMD move. */
1445 void
1447 {
1454 {
1460 {
1484 }
1488 }
1489 }
1491 static rtx
1493 {
1496 else
1497 {
1500 }
1501 }
1504 static rtx
1506 {
1508 {
1509 rtx high;
1510 /* Load the full offset into a register. This
1511 might be improvable in the future. */
1517 }
1519 }
1521 static int
1523 machine_mode mode)
1524 {
1533 {
1537 }
1540 {
1542 {
1547 else
1550 }
1552 }
1554 /* Remaining cases are all for DImode. */
1563 {
1564 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1565 For a 64-bit bitmask try whether changing 16 bits to all ones or
1566 zeroes creates a valid bitmask. To check any repeated bitmask,
1567 try using 16 bits from the other 32-bit half of val. */
1570 {
1581 }
1583 {
1585 {
1589 }
1590 }
1591 }
1593 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1594 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1595 otherwise skip zero bits. */
1607 {
1613 num_insns ++;
1614 }
1617 }
1620 void
1622 {
1627 /* Check on what type of symbol it is. */
1631 {
1635 /* If we have (const (plus symbol offset)), separate out the offset
1636 before we start classifying the symbol. */
1641 {
1645 {
1651 }
1656 /* If we aren't generating PC relative literals, then
1657 we need to expand the literal pool access carefully.
1658 This is something that needs to be done in a number
1659 of places, so could well live as a separate function. */
1661 {
1666 }
1683 {
1689 }
1690 /* FALLTHRU */
1703 }
1704 }
1707 {
1710 else
1711 {
1715 }
1718 }
1721 }
1723 static bool
1725 tree exp ATTRIBUTE_UNUSED)
1726 {
1727 /* Currently, always true. */
1729 }
1731 /* Implement TARGET_PASS_BY_REFERENCE. */
1733 static bool
1735 machine_mode mode,
1736 const_tree type,
1738 {
1739 HOST_WIDE_INT size;
1740 machine_mode dummymode;
1743 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
1747 /* Aggregates are passed by reference based on their size. */
1749 {
1751 }
1753 /* Variable sized arguments are always returned by reference. */
1757 /* Can this be a candidate to be passed in fp/simd register(s)? */
1760 NULL))
1763 /* Arguments which are variable sized or larger than 2 registers are
1764 passed by reference unless they are a homogenous floating point
1765 aggregate. */
1767 }
1769 /* Return TRUE if VALTYPE is padded to its least significant bits. */
1770 static bool
1772 {
1773 machine_mode dummy_mode;
1776 /* Never happens in little-endian mode. */
1780 /* Only composite types smaller than or equal to 16 bytes can
1781 be potentially returned in registers. */
1787 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
1788 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
1789 is always passed/returned in the least significant bits of fp/simd
1790 register(s). */
1796 }
1798 /* Implement TARGET_FUNCTION_VALUE.
1799 Define how to find the value returned by a function. */
1801 static rtx
1804 {
1805 machine_mode mode;
1808 machine_mode ag_mode;
1815 {
1819 {
1822 }
1823 }
1827 {
1829 {
1832 }
1833 else
1834 {
1836 rtx par;
1840 {
1845 }
1847 }
1848 }
1849 else
1851 }
1853 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
1854 Return true if REGNO is the number of a hard register in which the values
1855 of called function may come back. */
1857 static bool
1859 {
1860 /* Maximum of 16 bytes can be returned in the general registers. Examples
1861 of 16-byte return values are: 128-bit integers and 16-byte small
1862 structures (excluding homogeneous floating-point aggregates). */
1866 /* Up to four fp/simd registers can return a function value, e.g. a
1867 homogeneous floating-point aggregate having four members. */
1872 }
1874 /* Implement TARGET_RETURN_IN_MEMORY.
1876 If the type T of the result of a function is such that
1877 void func (T arg)
1878 would require that arg be passed as a value in a register (or set of
1879 registers) according to the parameter passing rules, then the result
1880 is returned in the same registers as would be used for such an
1881 argument. */
1883 static bool
1885 {
1886 HOST_WIDE_INT size;
1887 machine_mode ag_mode;
1893 /* Simple scalar types always returned in registers. */
1897 type,
1900 NULL))
1903 /* Types larger than 2 registers returned in memory. */
1906 }
1908 static bool
1911 {
1914 type,
1916 nregs,
1917 NULL);
1918 }
1920 /* Given MODE and TYPE of a function argument, return the alignment in
1921 bits. The idea is to suppress any stronger alignment requested by
1922 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
1923 This is a helper function for local use only. */
1925 static unsigned int
1927 {
1931 {
1933 {
1936 else
1938 }
1939 else
1941 }
1942 else
1946 }
1948 /* Layout a function argument according to the AAPCS64 rules. The rule
1949 numbers refer to the rule numbers in the AAPCS64. */
1951 static void
1953 const_tree type,
1955 {
1959 HOST_WIDE_INT size;
1961 /* We need to do this once per argument. */
1967 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
1968 size
1970 UNITS_PER_WORD);
1974 mode,
1975 type,
1978 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
1979 The following code thus handles passing by SIMD/FP registers first. */
1983 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
1984 and homogenous short-vector aggregates (HVA). */
1986 {
1991 {
1994 {
1997 }
1998 else
1999 {
2000 rtx par;
2004 {
2007 tmp = gen_rtx_EXPR_LIST
2011 }
2013 }
2015 }
2016 else
2017 {
2018 /* C.3 NSRN is set to 8. */
2021 }
2022 }
2027 /* C6 - C9. though the sign and zero extension semantics are
2028 handled elsewhere. This is the case where the argument fits
2029 entirely general registers. */
2031 {
2036 /* C.8 if the argument has an alignment of 16 then the NGRN is
2037 rounded up to the next even number. */
2039 {
2042 }
2043 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2044 A reg is still generated for it, but the caller should be smart
2045 enough not to use it. */
2047 {
2049 }
2050 else
2051 {
2052 rtx par;
2057 {
2062 }
2064 }
2068 }
2070 /* C.11 */
2073 /* The argument is passed on stack; record the needed number of words for
2074 this argument and align the total size if necessary. */
2075 on_stack:
2081 }
2083 /* Implement TARGET_FUNCTION_ARG. */
2085 static rtx
2088 {
2097 }
2099 void
2101 const_tree fntype ATTRIBUTE_UNUSED,
2102 rtx libname ATTRIBUTE_UNUSED,
2103 const_tree fndecl ATTRIBUTE_UNUSED,
2105 {
2119 {
2126 }
2128 }
2130 static void
2132 machine_mode mode,
2133 const_tree type,
2135 {
2138 {
2148 }
2149 }
2151 bool
2153 {
2156 }
2158 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2159 PARM_BOUNDARY bits of alignment, but will be given anything up
2160 to STACK_BOUNDARY bits if the type requires it. This makes sure
2161 that both before and after the layout of each argument, the Next
2162 Stacked Argument Address (NSAA) will have a minimum alignment of
2163 8 bytes. */
2165 static unsigned int
2167 {
2175 }
2177 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2179 Return true if an argument passed on the stack should be padded upwards,
2180 i.e. if the least-significant byte of the stack slot has useful data.
2182 Small aggregate types are placed in the lowest memory address.
2184 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2186 bool
2188 {
2189 /* On little-endian targets, the least significant byte of every stack
2190 argument is passed at the lowest byte address of the stack slot. */
2194 /* Otherwise, integral, floating-point and pointer types are padded downward:
2195 the least significant byte of a stack argument is passed at the highest
2196 byte address of the stack slot. */
2203 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2205 }
2207 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2209 It specifies padding for the last (may also be the only)
2210 element of a block move between registers and memory. If
2211 assuming the block is in the memory, padding upward means that
2212 the last element is padded after its highest significant byte,
2213 while in downward padding, the last element is padded at the
2214 its least significant byte side.
2216 Small aggregates and small complex types are always padded
2217 upwards.
2219 We don't need to worry about homogeneous floating-point or
2220 short-vector aggregates; their move is not affected by the
2221 padding direction determined here. Regardless of endianness,
2222 each element of such an aggregate is put in the least
2223 significant bits of a fp/simd register.
2225 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2226 register has useful data, and return the opposite if the most
2227 significant byte does. */
2229 bool
2232 {
2234 /* Small composite types are always padded upward. */
2236 {
2241 }
2243 /* Otherwise, use the default padding. */
2245 }
2247 static machine_mode
2249 {
2251 }
2253 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2255 /* We use the 12-bit shifted immediate arithmetic instructions so values
2256 must be multiple of (1 << 12), i.e. 4096. */
2257 #define ARITH_FACTOR 4096
2259 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2260 #error Cannot use simple address calculation for stack probing
2261 #endif
2263 /* The pair of scratch registers used for stack probing. */
2264 #define PROBE_STACK_FIRST_REG 9
2265 #define PROBE_STACK_SECOND_REG 10
2267 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2268 inclusive. These are offsets from the current stack pointer. */
2270 static void
2272 {
2275 /* See the same assertion on PROBE_INTERVAL above. */
2278 /* See if we have a constant small number of probes to generate. If so,
2279 that's the easy case. */
2281 {
2288 }
2290 /* The run-time loop is made up of 8 insns in the generic case while the
2291 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2293 {
2298 stack_pointer_rtx,
2302 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2303 it exceeds SIZE. If only two probes are needed, this will not
2304 generate any code. Then probe at FIRST + SIZE. */
2306 {
2310 }
2314 {
2319 }
2320 else
2322 }
2324 /* Otherwise, do the same as above, but in a loop. Note that we must be
2325 extra careful with variables wrapping around because we might be at
2326 the very top (or the very bottom) of the address space and we have
2327 to be able to handle this case properly; in particular, we use an
2328 equality test for the loop condition. */
2329 else
2330 {
2333 /* Step 1: round SIZE to the previous multiple of the interval. */
2338 /* Step 2: compute initial and final value of the loop counter. */
2340 /* TEST_ADDR = SP + FIRST. */
2344 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2350 /* Step 3: the loop
2352 do
2353 {
2354 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2355 probe at TEST_ADDR
2356 }
2357 while (TEST_ADDR != LAST_ADDR)
2359 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2360 until it is equal to ROUNDED_SIZE. */
2364 else
2368 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2369 that SIZE is equal to ROUNDED_SIZE. */
2372 {
2376 {
2381 }
2382 else
2384 }
2385 }
2387 /* Make sure nothing is scheduled before we are done. */
2389 }
2391 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2392 absolute addresses. */
2396 {
2403 /* Loop. */
2406 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2411 /* Probe at TEST_ADDR. */
2414 /* Test if TEST_ADDR == LAST_ADDR. */
2418 /* Branch. */
2424 }
2426 static bool
2428 {
2429 /* In aarch64_override_options_after_change
2430 flag_omit_leaf_frame_pointer turns off the frame pointer by
2431 default. Turn it back on now if we've not got a leaf
2432 function. */
2438 }
2440 /* Mark the registers that need to be saved by the callee and calculate
2441 the size of the callee-saved registers area and frame record (both FP
2442 and LR may be omitted). */
2443 static void
2445 {
2452 #define SLOT_NOT_REQUIRED (-2)
2453 #define SLOT_REQUIRED (-1)
2458 /* First mark all the registers that really need to be saved... */
2465 /* ... that includes the eh data registers (if needed)... */
2471 /* ... and any callee saved register that dataflow says is live. */
2484 {
2485 /* FP and LR are placed in the linkage record. */
2492 }
2494 /* Now assign stack slots for them. */
2497 {
2504 }
2508 {
2516 }
2536 }
2538 static bool
2540 {
2542 }
2544 static unsigned
2546 {
2548 regno ++;
2550 }
2552 static void
2554 HOST_WIDE_INT adjustment)
2555 {
2566 }
2568 static rtx
2570 HOST_WIDE_INT adjustment)
2571 {
2573 {
2584 }
2585 }
2587 static void
2590 {
2600 }
2602 static rtx
2604 HOST_WIDE_INT adjustment)
2605 {
2607 {
2616 }
2617 }
2619 static rtx
2621 rtx reg2)
2622 {
2624 {
2633 }
2634 }
2636 static rtx
2638 rtx mem2)
2639 {
2641 {
2650 }
2651 }
2654 static void
2657 {
2667 {
2669 HOST_WIDE_INT offset;
2679 offset));
2687 {
2689 rtx mem2;
2693 offset));
2695 reg2));
2697 /* The first part of a frame-related parallel insn is
2698 always assumed to be relevant to the frame
2699 calculations; subsequent parts, are only
2700 frame-related if explicitly marked. */
2703 }
2704 else
2708 }
2709 }
2711 static void
2715 {
2721 HOST_WIDE_INT offset;
2726 {
2743 {
2745 rtx mem2;
2753 }
2754 else
2757 }
2758 }
2760 /* AArch64 stack frames generated by this compiler look like:
2762 +-------------------------------+
2763 | |
2764 | incoming stack arguments |
2765 | |
2766 +-------------------------------+
2767 | | <-- incoming stack pointer (aligned)
2768 | callee-allocated save area |
2769 | for register varargs |
2770 | |
2771 +-------------------------------+
2772 | local variables | <-- frame_pointer_rtx
2773 | |
2774 +-------------------------------+
2775 | padding0 | \
2776 +-------------------------------+ |
2777 | callee-saved registers | | frame.saved_regs_size
2778 +-------------------------------+ |
2779 | LR' | |
2780 +-------------------------------+ |
2781 | FP' | / <- hard_frame_pointer_rtx (aligned)
2782 +-------------------------------+
2783 | dynamic allocation |
2784 +-------------------------------+
2785 | padding |
2786 +-------------------------------+
2787 | outgoing stack arguments | <-- arg_pointer
2788 | |
2789 +-------------------------------+
2790 | | <-- stack_pointer_rtx (aligned)
2792 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
2793 but leave frame_pointer_rtx and hard_frame_pointer_rtx
2794 unchanged. */
2796 /* Generate the prologue instructions for entry into a function.
2797 Establish the stack frame by decreasing the stack pointer with a
2798 properly calculated size and, if necessary, create a frame record
2799 filled with the values of LR and previous frame pointer. The
2800 current FP is also set up if it is in use. */
2802 void
2804 {
2805 /* sub sp, sp, #<frame_size>
2806 stp {fp, lr}, [sp, #<frame_size> - 16]
2807 add fp, sp, #<frame_size> - hardfp_offset
2808 stp {cs_reg}, [fp, #-16] etc.
2810 sub sp, sp, <final_adjustment_if_any>
2811 */
2814 HOST_WIDE_INT hard_fp_offset;
2827 {
2829 {
2833 }
2836 }
2838 /* Store pairs and load pairs have a range only -512 to 504. */
2840 {
2841 /* When the frame has a large size, an initial decrease is done on
2842 the stack pointer to jump over the callee-allocated save area for
2843 register varargs, the local variable area and/or the callee-saved
2844 register area. This will allow the pre-index write-back
2845 store pair instructions to be used for setting up the stack frame
2846 efficiently. */
2855 {
2865 }
2867 {
2872 {
2876 }
2878 {
2882 }
2883 }
2884 }
2885 else
2889 {
2893 {
2897 {
2904 }
2905 else
2908 /* Set up frame pointer to point to the location of the
2909 previous frame pointer on the stack. */
2911 stack_pointer_rtx,
2915 }
2916 else
2917 {
2925 {
2929 }
2930 else
2931 {
2938 else
2940 }
2941 }
2944 skip_wb);
2946 skip_wb);
2947 }
2949 /* when offset >= 512,
2950 sub sp, sp, #<outgoing_args_size> */
2952 {
2954 {
2959 }
2960 }
2961 }
2963 /* Return TRUE if we can use a simple_return insn.
2965 This function checks whether the callee saved stack is empty, which
2966 means no restore actions are need. The pro_and_epilogue will use
2967 this to check whether shrink-wrapping opt is feasible. */
2969 bool
2971 {
2981 }
2983 /* Generate the epilogue instructions for returning from a function. */
2984 void
2986 {
2988 HOST_WIDE_INT fp_offset;
2989 HOST_WIDE_INT hard_fp_offset;
2991 /* We need to add memory barrier to prevent read from deallocated stack. */
3001 /* Store pairs and load pairs have a range only -512 to 504. */
3003 {
3011 {
3016 }
3017 }
3018 else
3021 /* If there were outgoing arguments or we've done dynamic stack
3022 allocation, then restore the stack pointer from the frame
3023 pointer. This is at most one insn and more efficient than using
3024 GCC's internal mechanism. */
3027 {
3032 hard_frame_pointer_rtx,
3035 }
3038 {
3061 {
3067 {
3072 }
3073 else
3074 {
3081 }
3082 }
3083 else
3084 {
3087 }
3089 /* Reset the CFA to be SP + FRAME_SIZE. */
3096 }
3099 {
3104 {
3108 }
3109 else
3110 {
3115 {
3120 }
3123 }
3125 /* Reset the CFA to be SP + 0. */
3128 }
3130 /* Stack adjustment for exception handler. */
3132 {
3133 /* We need to unwind the stack by the offset computed by
3134 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3135 to be SP; letting the CFA move during this adjustment
3136 is just as correct as retaining the CFA from the body
3137 of the function. Therefore, do nothing special. */
3139 }
3144 }
3146 /* Return the place to copy the exception unwinding return address to.
3147 This will probably be a stack slot, but could (in theory be the
3148 return register). */
3149 rtx
3151 {
3152 HOST_WIDE_INT fp_offset;
3162 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
3163 result in a store to save LR introduced by builtin_eh_return () being
3164 incorrectly deleted because the alias is not detected.
3165 So in the calculation of the address to copy the exception unwinding
3166 return address to, we note 2 cases.
3167 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
3168 we return a SP-relative location since all the addresses are SP-relative
3169 in this case. This prevents the store from being optimized away.
3170 If the fp_offset is not 0, then the addresses will be FP-relative and
3171 therefore we return a FP-relative location. */
3174 {
3178 else
3181 }
3183 /* If FP is not needed, we calculate the location of LR, which would be
3184 at the top of the saved registers block. */
3188 stack_pointer_rtx,
3189 fp_offset
3192 }
3194 /* Possibly output code to build up a constant in a register. For
3195 the benefit of the costs infrastructure, returns the number of
3196 instructions which would be emitted. GENERATE inhibits or
3197 enables code generation. */
3199 static int
3201 {
3205 {
3209 }
3210 else
3211 {
3216 HOST_WIDE_INT valm;
3217 HOST_WIDE_INT tval;
3220 {
3230 }
3232 /* zcount contains the number of additional MOVK instructions
3233 required if the constant is built up with an initial MOVZ instruction,
3234 while ncount is the number of MOVK instructions required if starting
3235 with a MOVN instruction. Choose the sequence that yields the fewest
3236 number of instructions, preferring MOVZ instructions when they are both
3237 the same. */
3239 {
3244 insns++;
3245 }
3246 else
3247 {
3252 insns++;
3253 }
3258 {
3260 {
3265 insns++;
3266 }
3268 }
3269 }
3271 }
3273 static void
3275 {
3284 {
3287 }
3289 {
3291 {
3297 else
3300 }
3302 {
3306 }
3307 }
3308 }
3310 /* Output code to add DELTA to the first argument, and then jump
3311 to FUNCTION. Used for C++ multiple inheritance. */
3312 static void
3314 HOST_WIDE_INT delta,
3315 HOST_WIDE_INT vcall_offset,
3316 tree function)
3317 {
3318 /* The this pointer is always in x0. Note that this differs from
3319 Arm where the this pointer maybe bumped to r1 if r0 is required
3320 to return a pointer to an aggregate. On AArch64 a result value
3321 pointer will be in x8. */
3331 else
3332 {
3341 {
3345 else
3347 }
3351 else
3358 else
3359 {
3362 }
3366 else
3372 }
3374 /* Generate a tail call to the target function. */
3376 {
3379 }
3391 /* Stop pretending to be a post-reload pass. */
3393 }
3395 static bool
3397 {
3402 {
3406 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3407 TLS offsets, not real symbol references. */
3410 }
3412 }
3415 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3416 a left shift of 0 or 12 bits. */
3417 bool
3419 {
3422 );
3423 }
3426 /* Return true if val is an immediate that can be loaded into a
3427 register by a MOVZ instruction. */
3428 static bool
3430 {
3432 {
3436 }
3437 else
3438 {
3439 /* Ignore sign extension. */
3441 }
3444 }
3446 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3449 {
3455 };
3458 /* Return true if val is a valid bitmask immediate. */
3460 bool
3462 {
3466 /* Check for a single sequence of one bits and return quickly if so.
3467 The special cases of all ones and all zeroes returns false. */
3474 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3478 /* Invert if the immediate doesn't start with a zero bit - this means we
3479 only need to search for sequences of one bits. */
3483 /* Find the first set bit and set tmp to val with the first sequence of one
3484 bits removed. Return success if there is a single sequence of ones. */
3491 /* Find the next set bit and compute the difference in bit position. */
3496 /* Check the bit position difference is a power of 2, and that the first
3497 sequence of one bits fits within 'bits' bits. */
3501 /* Check the sequence of one bits is repeated 64/bits times. */
3503 }
3506 /* Return true if val is an immediate that can be loaded into a
3507 register in a single instruction. */
3508 bool
3510 {
3514 }
3516 static bool
3518 {
3526 {
3530 else
3531 /* Avoid generating a 64-bit relocation in ILP32; leave
3532 to aarch64_expand_mov_immediate to handle it properly. */
3534 }
3537 }
3539 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
3541 static unsigned int
3543 {
3544 /* Use the specified limit for the number of cases before using jump
3545 tables at higher optimization levels. */
3549 else
3551 }
3553 /* Return true if register REGNO is a valid index register.
3554 STRICT_P is true if REG_OK_STRICT is in effect. */
3556 bool
3558 {
3560 {
3568 }
3570 }
3572 /* Return true if register REGNO is a valid base register for mode MODE.
3573 STRICT_P is true if REG_OK_STRICT is in effect. */
3575 bool
3577 {
3579 {
3587 }
3589 /* The fake registers will be eliminated to either the stack or
3590 hard frame pointer, both of which are usually valid base registers.
3591 Reload deals with the cases where the eliminated form isn't valid. */
3596 }
3598 /* Return true if X is a valid base register for mode MODE.
3599 STRICT_P is true if REG_OK_STRICT is in effect. */
3601 static bool
3603 {
3608 }
3610 /* Return true if address offset is a valid index. If it is, fill in INFO
3611 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3613 static bool
3616 {
3618 rtx index;
3621 /* (reg:P) */
3624 {
3628 }
3629 /* (sign_extend:DI (reg:SI)) */
3634 {
3639 }
3640 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3647 {
3652 }
3653 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3660 {
3665 }
3666 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3673 {
3681 }
3682 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3683 (const_int 0xffffffff<<shift)) */
3690 {
3696 }
3697 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3704 {
3712 }
3713 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3714 (const_int 0xffffffff<<shift)) */
3721 {
3727 }
3728 /* (mult:P (reg:P) (const_int scale)) */
3733 {
3737 }
3738 /* (ashift:P (reg:P) (const_int shift)) */
3743 {
3747 }
3748 else
3759 {
3764 }
3767 }
3769 bool
3771 {
3775 }
3779 HOST_WIDE_INT offset)
3780 {
3782 }
3786 {
3790 }
3792 /* Return true if MODE is one of the modes for which we
3793 support LDP/STP operations. */
3795 static bool
3797 {
3802 }
3804 /* Return true if X is a valid address for machine mode MODE. If it is,
3805 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3806 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3808 static bool
3812 {
3816 /* On BE, we use load/store pair for all large int mode load/stores. */
3818 || (BYTES_BIG_ENDIAN
3822 !load_store_pair_p
3826 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3827 REG addressing. */
3833 {
3851 {
3857 }
3862 {
3869 /* TImode and TFmode values are allowed in both pairs of X
3870 registers and individual Q registers. The available
3871 address modes are:
3872 X,X: 7-bit signed scaled offset
3873 Q: 9-bit signed offset
3874 We conservatively require an offset representable in either mode.
3875 */
3880 /* A 7bit offset check because OImode will emit a ldp/stp
3881 instruction (only big endian will get here).
3882 For ldp/stp instructions, the offset is scaled for the size of a
3883 single element of the pair. */
3887 /* Three 9/12 bit offsets checks because CImode will emit three
3888 ldr/str instructions (only big endian will get here). */
3895 /* Two 7bit offsets checks because XImode will emit two ldp/stp
3896 instructions (only big endian will get here). */
3905 else
3908 }
3911 {
3912 /* Look for base + (scaled/extended) index register. */
3915 {
3918 }
3921 {
3924 }
3925 }
3946 {
3947 HOST_WIDE_INT offset;
3951 /* TImode and TFmode values are allowed in both pairs of X
3952 registers and individual Q registers. The available
3953 address modes are:
3954 X,X: 7-bit signed scaled offset
3955 Q: 9-bit signed offset
3956 We conservatively require an offset representable in either mode.
3957 */
3965 else
3967 }
3973 /* load literal: pc-relative constant pool entry. Only supported
3974 for SI mode or larger. */
3978 {
3986 }
3995 {
4000 {
4001 /* The symbol and offset must be aligned to the access size. */
4008 {
4012 }
4018 else
4027 }
4028 }
4033 }
4034 }
4036 bool
4038 {
4039 rtx offset;
4043 }
4045 /* Classify the base of symbolic expression X. */
4047 enum aarch64_symbol_type
4049 {
4050 rtx offset;
4054 }
4057 /* Return TRUE if X is a legitimate address for accessing memory in
4058 mode MODE. */
4059 static bool
4061 {
4065 }
4067 /* Return TRUE if X is a legitimate address for accessing memory in
4068 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4069 pair operation. */
4070 bool
4073 {
4077 }
4079 /* Return TRUE if rtx X is immediate constant 0.0 */
4080 bool
4082 {
4089 }
4091 /* Return the fixed registers used for condition codes. */
4093 static bool
4095 {
4099 }
4101 /* Emit call insn with PAT and do aarch64-specific handling. */
4103 void
4105 {
4111 }
4113 machine_mode
4115 {
4116 /* All floating point compares return CCFP if it is an equality
4117 comparison, and CCFPE otherwise. */
4119 {
4121 {
4142 }
4143 }
4145 /* Equality comparisons of short modes against zero can be performed
4146 using the TST instruction with the appropriate bitmask. */
4161 /* A compare with a shifted operand. Because of canonicalization,
4162 the comparison will have to be swapped when we emit the assembly
4163 code. */
4171 /* Similarly for a negated operand, but we can only do this for
4172 equalities. */
4179 /* A compare of a mode narrower than SI mode against zero can be done
4180 by extending the value in the comparison. */
4183 /* Only use sign-extension if we really need it. */
4187 /* For everything else, return CCmode. */
4189 }
4191 static int
4194 int
4196 {
4203 }
4205 static int
4207 {
4210 {
4214 {
4228 }
4283 {
4295 }
4302 {
4314 }
4319 {
4325 }
4330 {
4334 }
4340 }
4349 }
4351 bool
4353 HOST_WIDE_INT minval,
4354 HOST_WIDE_INT maxval)
4355 {
4356 HOST_WIDE_INT firstval;
4373 }
4375 bool
4377 {
4379 }
4382 /* N Z C V. */
4383 #define AARCH64_CC_V 1
4384 #define AARCH64_CC_C (1 << 1)
4385 #define AARCH64_CC_Z (1 << 2)
4386 #define AARCH64_CC_N (1 << 3)
4388 /* N Z C V flags for ccmp. The first code is for AND op and the other
4389 is for IOR op. Indexed by AARCH64_COND_CODE. */
4391 {
4408 };
4410 int
4412 {
4414 {
4447 }
4448 }
4451 static void
4453 {
4455 {
4456 /* An integer or symbol address without a preceding # sign. */
4459 {
4471 {
4474 }
4475 /* Fall through. */
4479 }
4483 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4484 {
4489 {
4492 }
4495 {
4508 }
4509 }
4513 {
4516 /* Print N such that 2^N == X. */
4518 {
4521 }
4524 }
4528 /* Print the number of non-zero bits in X (a const_int). */
4530 {
4533 }
4539 /* Print the higher numbered register of a pair (TImode) of regs. */
4541 {
4544 }
4550 {
4552 /* Print a condition (eq, ne, etc). */
4554 /* CONST_TRUE_RTX means always -- that's the default. */
4559 {
4562 }
4567 }
4571 {
4573 /* Print the inverse of a condition (eq <-> ne, etc). */
4575 /* CONST_TRUE_RTX means never -- that's the default. */
4577 {
4580 }
4583 {
4586 }
4591 }
4599 /* Print a scalar FP/SIMD register name. */
4601 {
4602 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4604 }
4612 /* Print the first FP/SIMD register name in a list. */
4614 {
4615 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4617 }
4622 /* Print a scalar FP/SIMD register name + 1. */
4624 {
4625 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4627 }
4632 /* Print bottom 16 bits of integer constant in hex. */
4634 {
4637 }
4643 /* Print a general register name or the zero register (32-bit or
4644 64-bit). */
4647 {
4650 }
4653 {
4656 }
4659 {
4662 }
4664 /* Fall through */
4667 /* Print a normal operand, if it's a general register, then we
4668 assume DImode. */
4670 {
4673 }
4676 {
4697 {
4700 HOST_WIDE_INT_MIN,
4701 HOST_WIDE_INT_MAX));
4703 }
4705 {
4707 }
4708 else
4713 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
4714 be getting CONST_DOUBLEs holding integers. */
4717 {
4720 }
4722 {
4723 #define buf_size 20
4731 #undef buf_size
4732 }
4738 }
4746 {
4773 }
4779 {
4814 }
4821 {
4827 }
4832 {
4834 /* Print nzcv. */
4837 {
4840 }
4845 }
4849 {
4851 /* Print nzcv. */
4854 {
4857 }
4862 }
4868 }
4869 }
4871 static void
4873 {
4878 {
4882 else
4891 else
4900 else
4909 else
4916 {
4943 }
4954 }
4957 }
4959 bool
4961 {
4968 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4969 referencing instruction, but they are constant offsets, not
4970 symbols. */
4976 {
4978 {
4984 }
4987 }
4990 }
4992 /* Implement REGNO_REG_CLASS. */
4994 enum reg_class
4996 {
5011 }
5013 static rtx
5015 {
5016 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5017 where mask is selected by alignment and size of the offset.
5018 We try to pick as large a range for the offset as possible to
5019 maximize the chance of a CSE. However, for aligned addresses
5020 we limit the range to 4k so that structures with different sized
5021 elements are likely to use the same base. We need to be careful
5022 not to split a CONST for some forms of address expression, otherwise
5023 it will generate sub-optimal code. */
5026 {
5028 HOST_WIDE_INT base_offset;
5031 {
5035 /* Address expressions of the form Ra + Rb + CONST.
5037 If CONST is within the range supported by the addressing
5038 mode "reg+offset", do not split CONST and use the
5039 sequence
5040 Rt = Ra + Rb;
5041 addr = Rt + CONST. */
5043 {
5049 {
5052 }
5053 }
5054 /* Address expressions of the form Ra + Rb<<SCALE + CONST.
5056 If Reg + Rb<<SCALE is a valid address expression, do not
5057 split CONST and use the sequence
5058 Rc = CONST;
5059 Rt = Ra + Rc;
5060 addr = Rt + Rb<<SCALE.
5062 Here we split CONST out of memory referece because:
5063 a) We depend on GIMPLE optimizers to pick up common sub
5064 expression involving the scaling operation.
5065 b) The index Rb is likely a loop iv, it's better to split
5066 the CONST so that computation of new base Rt is a loop
5067 invariant and can be moved out of loop. This is more
5068 important when the original base Ra is sfp related. */
5070 {
5074 /* Switch to make sure that register is in op0. */
5081 {
5084 NULL_RTX);
5086 }
5087 }
5088 }
5090 /* Does it look like we'll need a load/store-pair operation? */
5095 /* For offsets aren't a multiple of the access size, the limit is
5096 -256...255. */
5099 else
5108 NULL_RTX);
5111 }
5114 }
5116 /* Try a machine-dependent way of reloading an illegitimate address
5117 operand. If we find one, push the reload and return the new rtx. */
5119 rtx
5121 machine_mode mode,
5124 {
5127 /* Do not allow mem (plus (reg, const)) if vector struct mode. */
5132 {
5139 }
5141 /* We must recognize output that we have already generated ourselves. */
5147 {
5152 }
5154 /* We wish to handle large displacements off a base register by splitting
5155 the addend across an add and the mem insn. This can cut the number of
5156 extra insns needed from 3 to 1. It is only useful for load/store of a
5157 single register with 12 bit offset field. */
5165 {
5169 HOST_WIDE_INT offs;
5170 rtx cst;
5173 /* In ILP32, xmode can be either DImode or SImode. */
5176 /* Reload non-zero BLKmode offsets. This is because we cannot ascertain
5177 BLKmode alignment. */
5183 /* Align misaligned offset by adjusting high part to compensate. */
5185 {
5187 {
5188 /* Align down. */
5191 }
5192 else
5193 {
5194 /* Align up. */
5199 }
5200 }
5202 /* Check for overflow. */
5210 /* Reload high part into base reg, leaving the low part
5211 in the mem instruction.
5212 Note that replacing this gen_rtx_PLUS with plus_constant is
5213 wrong in this case because we rely on the
5214 (plus (plus reg c1) c2) structure being preserved so that
5215 XEXP (*p, 0) in push_reload below uses the correct term. */
5224 }
5227 }
5230 /* Return the reload icode required for a constant pool in mode. */
5231 static enum insn_code
5233 {
5235 {
5271 }
5274 }
5275 static reg_class_t
5277 reg_class_t rclass,
5278 machine_mode mode,
5280 {
5282 /* If we have to disable direct literal pool loads and stores because the
5283 function is too big, then we need a scratch register. */
5288 {
5291 }
5293 /* Without the TARGET_SIMD instructions we cannot move a Q register
5294 to a Q register directly. We need a scratch. */
5298 {
5304 }
5306 /* A TFmode or TImode memory access should be handled via an FP_REGS
5307 because AArch64 has richer addressing modes for LDR/STR instructions
5308 than LDP/STP instructions. */
5317 }
5319 static bool
5321 {
5322 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5323 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5326 {
5338 }
5339 else
5340 {
5341 /* If we decided that we didn't need a leaf frame pointer but then used
5342 LR in the function, then we'll want a frame pointer after all, so
5343 prevent this elimination to ensure a frame pointer is used. */
5345 && flag_omit_leaf_frame_pointer
5348 }
5351 }
5353 HOST_WIDE_INT
5355 {
5359 {
5366 }
5369 {
5373 }
5376 }
5378 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5379 previous frame. */
5381 rtx
5383 {
5387 }
5390 static void
5392 {
5394 {
5397 }
5398 else
5399 {
5402 }
5407 }
5409 static void
5411 {
5415 /* Don't need to copy the trailing D-words, we fill those in below. */
5427 /* XXX We should really define a "clear_cache" pattern and use
5428 gen_clear_cache(). */
5433 ptr_mode);
5434 }
5436 static unsigned char
5438 {
5440 {
5447 return
5459 }
5461 }
5463 static reg_class_t
5465 {
5470 {
5476 }
5478 /* If it's an integer immediate that MOVI can't handle, then
5479 FP_REGS is not an option, so we return NO_REGS instead. */
5484 /* Register eliminiation can result in a request for
5485 SP+constant->FP_REGS. We cannot support such operations which
5486 use SP as source and an FP_REG as destination, so reject out
5487 right now. */
5489 {
5492 /* Look through a possible SUBREG introduced by ILP32. */
5498 POINTER_REGS));
5500 }
5503 }
5505 void
5507 {
5509 }
5511 static void
5513 {
5516 else
5517 {
5525 }
5526 }
5528 static void
5530 {
5533 else
5534 {
5542 }
5543 }
5547 {
5553 {
5554 {
5557 },
5558 {
5561 },
5562 {
5565 },
5566 /* We assume that DImode is only generated when not optimizing and
5567 that we don't really need 64-bit address offsets. That would
5568 imply an object file with 8GB of code in a single function! */
5569 {
5572 }
5573 };
5581 /* Need to implement table size reduction, by chaning the code below. */
5591 }
5594 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5595 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5596 operator. */
5598 int
5600 {
5602 {
5605 {
5609 }
5610 }
5612 }
5614 /* Constant pools are per function only when PC relative
5615 literal loads are true or we are in the large memory
5616 model. */
5620 {
5623 }
5625 static bool
5627 {
5628 /* Fixme:: In an ideal world this would work similar
5629 to the logic in aarch64_select_rtx_section but this
5630 breaks bootstrap in gcc go. For now we workaround
5631 this by returning false here. */
5633 }
5635 /* Select appropriate section for constants depending
5636 on where we place literal pools. */
5640 rtx x,
5642 {
5647 }
5649 /* Costs. */
5651 /* Helper function for rtx cost calculation. Strip a shift expression
5652 from X. Returns the inner operand if successful, or the original
5653 expression on failure. */
5654 static rtx
5656 {
5659 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5660 we can convert both to ROR during final output. */
5675 }
5677 /* Helper function for rtx cost calculation. Strip an extend
5678 expression from X. Returns the inner operand if successful, or the
5679 original expression on failure. We deal with a number of possible
5680 canonicalization variations here. */
5681 static rtx
5683 {
5686 /* Zero and sign extraction of a widened value. */
5694 /* It can also be represented (for zero-extend) as an AND with an
5695 immediate. */
5704 /* Now handle extended register, as this may also have an optional
5705 left shift by 1..4. */
5719 }
5721 /* Return true iff CODE is a shift supported in combination
5722 with arithmetic instructions. */
5724 static bool
5726 {
5728 }
5730 /* Helper function for rtx cost calculation. Calculate the cost of
5731 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5732 Return the calculated cost of the expression, recursing manually in to
5733 operands where needed. */
5735 static int
5737 {
5753 /* Integer multiply/fma. */
5755 {
5756 /* The multiply will be canonicalized as a shift, cost it as such. */
5760 {
5764 {
5766 {
5768 /* ARITH + shift-by-register. */
5771 /* ARITH + extended register. We don't have a cost field
5772 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5774 else
5775 /* ARITH + shift-by-immediate. */
5777 }
5778 else
5779 /* LSL (immediate). */
5782 }
5783 /* Strip extends as we will have costed them in the case above. */
5790 }
5792 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5793 compound and let the below cases handle it. After all, MNEG is a
5794 special-case alias of MSUB. */
5796 {
5799 }
5801 /* Integer multiplies or FMAs have zero/sign extending variants. */
5806 {
5811 {
5813 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5815 else
5816 /* MUL/SMULL/UMULL. */
5818 }
5821 }
5823 /* This is either an integer multiply or a MADD. In both cases
5824 we want to recurse and cost the operands. */
5829 {
5831 /* MADD/MSUB. */
5833 else
5834 /* MUL. */
5836 }
5839 }
5840 else
5841 {
5843 {
5844 /* Floating-point FMA/FMUL can also support negations of the
5845 operands, unless the rounding mode is upward or downward in
5846 which case FNMUL is different than FMUL with operand negation. */
5850 {
5855 }
5858 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5860 else
5861 /* FMUL/FNMUL. */
5863 }
5868 }
5869 }
5871 static int
5873 machine_mode mode,
5874 addr_space_t as ATTRIBUTE_UNUSED,
5876 {
5884 {
5886 {
5887 /* This is a CONST or SYMBOL ref which will be split
5888 in a different way depending on the code model in use.
5889 Cost it through the generic infrastructure. */
5891 /* Divide through by the cost of one instruction to
5892 bring it to the same units as the address costs. */
5894 /* The cost is then the cost of preparing the address,
5895 followed by an immediate (possibly 0) offset. */
5897 }
5898 else
5899 {
5900 /* This is most likely a jump table from a case
5901 statement. */
5903 }
5904 }
5907 {
5919 else
5938 }
5942 {
5943 /* For the sake of calculating the cost of the shifted register
5944 component, we can treat same sized modes in the same way. */
5946 {
5959 /* We can't tell, or this is a 128-bit vector. */
5963 }
5964 }
5967 }
5969 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5970 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5971 to be taken. */
5973 int
5975 {
5976 /* When optimizing for speed, use the cost of unpredictable branches. */
5982 else
5984 }
5986 /* Return true if the RTX X in mode MODE is a zero or sign extract
5987 usable in an ADD or SUB (extended register) instruction. */
5988 static bool
5990 {
5991 /* Catch add with a sign extract.
5992 This is add_<optab><mode>_multp2. */
5995 {
6006 op1))
6007 {
6009 }
6010 }
6011 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6012 No shift. */
6018 }
6020 static bool
6022 {
6024 {
6036 }
6037 }
6039 /* Return true iff X is an rtx that will match an extr instruction
6040 i.e. as described in the *extr<mode>5_insn family of patterns.
6041 OP0 and OP1 will be set to the operands of the shifts involved
6042 on success and will be NULL_RTX otherwise. */
6044 static bool
6046 {
6061 {
6062 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6074 {
6078 }
6079 }
6082 }
6084 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6085 storing it in *COST. Result is true if the total cost of the operation
6086 has now been calculated. */
6087 static bool
6089 {
6090 rtx inner;
6091 rtx comparator;
6095 {
6099 }
6100 else
6101 {
6105 }
6108 {
6109 /* Conditional branch. */
6112 else
6113 {
6115 {
6117 {
6118 /* TBZ/TBNZ/CBZ/CBNZ. */
6120 /* TBZ/TBNZ. */
6123 else
6124 /* CBZ/CBNZ. */
6128 }
6129 }
6131 {
6132 /* TBZ/TBNZ. */
6135 }
6136 }
6137 }
6139 {
6140 /* It's a conditional operation based on the status flags,
6141 so it must be some flavor of CSEL. */
6143 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6149 {
6150 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6153 }
6158 }
6160 /* We don't know what this is, cost all operands. */
6162 }
6164 /* Check whether X is a bitfield operation of the form shift + extend that
6165 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6166 operand to which the bitfield operation is applied. Otherwise return
6167 NULL_RTX. */
6169 static rtx
6171 {
6185 {
6203 }
6206 }
6208 /* Calculate the cost of calculating X, storing it in *COST. Result
6209 is true if the total cost of the operation has now been calculated. */
6210 static bool
6213 {
6219 /* By default, assume that everything has equivalent cost to the
6220 cheapest instruction. Any additional costs are applied as a delta
6221 above this default. */
6225 {
6227 /* The cost depends entirely on the operands to SET. */
6233 {
6236 {
6250 }
6259 /* Fall through. */
6261 /* The cost is one per vector-register copied. */
6263 {
6267 }
6268 /* const0_rtx is in general free, but we will use an
6269 instruction to set a register to 0. */
6271 {
6272 /* The cost is 1 per register copied. */
6276 }
6277 else
6278 /* Cost is just the cost of the RHS of the set. */
6284 /* Bit-field insertion. Strip any redundant widening of
6285 the RHS to meet the width of the target. */
6296 {
6297 /* MOV immediate is assumed to always be cheap. */
6299 }
6300 else
6301 {
6302 /* BFM. */
6306 }
6311 /* We can't make sense of this, assume default cost. */
6314 }
6318 /* If an instruction can incorporate a constant within the
6319 instruction, the instruction's expression avoids calling
6320 rtx_cost() on the constant. If rtx_cost() is called on a
6321 constant, then it is usually because the constant must be
6322 moved into a register by one or more instructions.
6324 The exception is constant 0, which can be expressed
6325 as XZR/WZR and is therefore free. The exception to this is
6326 if we have (set (reg) (const0_rtx)) in which case we must cost
6327 the move. However, we can catch that when we cost the SET, so
6328 we don't need to consider that here. */
6331 else
6332 {
6333 /* To an approximation, building any other constant is
6334 proportionally expensive to the number of instructions
6335 required to build that constant. This is true whether we
6336 are compiling for SPEED or otherwise. */
6339 }
6344 {
6345 /* mov[df,sf]_aarch64. */
6347 /* FMOV (scalar immediate). */
6350 {
6351 /* This will be a load from memory. */
6354 else
6356 }
6357 else
6358 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6359 or MOV v0.s[0], wzr - neither of which are modeled by the
6360 cost tables. Just use the default cost. */
6361 {
6362 }
6363 }
6369 {
6370 /* For loads we want the base cost of a load, plus an
6371 approximation for the additional cost of the addressing
6372 mode. */
6386 }
6394 {
6396 {
6397 /* FNEG. */
6399 }
6401 }
6404 {
6407 {
6408 /* CSETM. */
6411 }
6413 /* Cost this as SUB wzr, X. */
6417 }
6420 {
6421 /* Support (neg(fma...)) as a single instruction only if
6422 sign of zeros is unimportant. This matches the decision
6423 making in aarch64.md. */
6425 {
6426 /* FNMADD. */
6429 }
6431 {
6432 /* FNMUL. */
6435 }
6437 /* FNEG. */
6440 }
6447 {
6450 else
6452 }
6462 {
6466 }
6469 {
6470 /* TODO: A write to the CC flags possibly costs extra, this
6471 needs encoding in the cost tables. */
6473 /* CC_ZESWPmode supports zero extend for free. */
6478 /* ANDS. */
6480 {
6483 }
6486 {
6487 /* ADDS (and CMN alias). */
6490 }
6493 {
6494 /* SUBS. */
6497 }
6502 {
6503 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6504 Handle it here directly rather than going to cost_logic
6505 since we know the immediate generated for the TST is valid
6506 so we can avoid creating an intermediate rtx for it only
6507 for costing purposes. */
6514 }
6517 {
6518 /* CMN. */
6525 }
6527 /* CMP.
6529 Compare can freely swap the order of operands, and
6530 canonicalization puts the more complex operation first.
6531 But the integer MINUS logic expects the shift/extend
6532 operation in op1. */
6535 {
6538 }
6540 }
6543 {
6544 /* FCMP. */
6549 {
6551 /* FCMP supports constant 0.0 for no extra cost. */
6553 }
6555 }
6558 {
6559 /* Vector compare. */
6564 {
6565 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6566 cost. */
6568 }
6570 }
6574 {
6578 cost_minus:
6581 /* Detect valid immediates. */
6587 {
6589 /* SUB(S) (immediate). */
6592 }
6594 /* Look for SUB (extended register). */
6596 {
6604 }
6608 /* Cost this as an FMA-alike operation. */
6612 {
6615 speed);
6617 }
6622 {
6624 {
6625 /* Vector SUB. */
6627 }
6629 {
6630 /* SUB(S). */
6632 }
6634 {
6635 /* FSUB. */
6637 }
6638 }
6640 }
6643 {
6644 rtx new_op0;
6649 cost_plus:
6652 {
6653 /* CSINC. */
6657 }
6662 {
6666 /* ADD (immediate). */
6669 }
6673 /* Look for ADD (extended register). */
6675 {
6683 }
6685 /* Strip any extend, leave shifts behind as we will
6686 cost them through mult_cost. */
6691 {
6693 speed);
6695 }
6700 {
6702 {
6703 /* Vector ADD. */
6705 }
6707 {
6708 /* ADD. */
6710 }
6712 {
6713 /* FADD. */
6715 }
6716 }
6718 }
6724 {
6727 else
6729 }
6734 {
6738 {
6741 else
6743 }
6745 }
6748 {
6755 }
6756 /* Fall through. */
6759 cost_logic:
6764 {
6768 }
6776 {
6777 /* This is a UBFM/SBFM. */
6782 }
6785 {
6786 /* We possibly get the immediate for free, this is not
6787 modelled. */
6790 {
6797 }
6798 else
6799 {
6802 /* Handle ORN, EON, or BIC. */
6808 /* If we had a shift on op0 then this is a logical-shift-
6809 by-register/immediate operation. Otherwise, this is just
6810 a logical operation. */
6812 {
6814 {
6815 /* Shift by immediate. */
6818 else
6820 }
6821 else
6823 }
6825 /* In both cases we want to cost both operands. */
6830 }
6831 }
6839 {
6840 /* Vector NOT. */
6843 }
6845 /* MVN-shifted-reg. */
6847 {
6854 }
6855 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6856 Handle the second form here taking care that 'a' in the above can
6857 be a shift. */
6859 {
6868 {
6871 else
6873 }
6876 }
6877 /* MVN. */
6886 /* If a value is written in SI mode, then zero extended to DI
6887 mode, the operation will in general be free as a write to
6888 a 'w' register implicitly zeroes the upper bits of an 'x'
6889 register. However, if this is
6891 (set (reg) (zero_extend (reg)))
6893 we must cost the explicit register move. */
6897 {
6901 /* MOV. */
6903 else
6904 /* Free, the cost is that of the SI mode operation. */
6908 }
6910 {
6911 /* All loads can zero extend to any size for free. */
6914 }
6918 {
6923 }
6926 {
6928 {
6929 /* UMOV. */
6931 }
6932 else
6933 {
6934 /* UXTB/UXTH. */
6936 }
6937 }
6942 {
6943 /* LDRSH. */
6945 {
6952 }
6954 }
6958 {
6963 }
6966 {
6969 else
6971 }
6979 {
6981 {
6983 {
6984 /* Vector shift (immediate). */
6986 }
6987 else
6988 {
6989 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6990 aliases. */
6992 }
6993 }
6995 /* We can incorporate zero/sign extend for free. */
7002 }
7003 else
7004 {
7006 {
7008 {
7009 /* Vector shift (register). */
7011 }
7012 else
7013 {
7014 /* LSLV. */
7016 }
7017 }
7019 }
7029 {
7030 /* ASR (immediate) and friends. */
7032 {
7035 else
7037 }
7041 }
7042 else
7043 {
7045 /* ASR (register) and friends. */
7047 {
7050 else
7052 }
7054 }
7060 {
7061 /* LDR. */
7064 }
7067 {
7068 /* ADRP, followed by ADD. */
7072 }
7075 {
7076 /* ADR. */
7079 }
7082 {
7083 /* One extra load instruction, after accessing the GOT. */
7087 }
7092 /* ADRP/ADD (immediate). */
7099 /* UBFX/SBFX. */
7101 {
7104 else
7106 }
7108 /* We can trust that the immediates used will be correct (there
7109 are no by-register forms), so we need only cost op0. */
7115 /* aarch64_rtx_mult_cost always handles recursion to its
7116 operands. */
7120 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7121 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7122 an unconditional negate. This case should only ever be reached through
7123 the set_smod_pow2_cheap check in expmed.c. */
7127 {
7128 /* We expand to 4 instructions. Reset the baseline. */
7136 }
7138 /* Fall-through. */
7141 {
7153 }
7160 {
7164 /* There is no integer SQRT, so only DIV and UDIV can get
7165 here. */
7167 else
7169 }
7195 {
7198 else
7200 }
7202 /* FMSUB, FNMADD, and FNMSUB are free. */
7209 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7210 and the by-element operand as operand 0. */
7214 /* Catch vector-by-element operations. The by-element operand can
7215 either be (vec_duplicate (vec_select (x))) or just
7216 (vec_select (x)), depending on whether we are multiplying by
7217 a vector or a scalar.
7219 Canonicalization is not very good in these cases, FMA4 will put the
7220 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7231 /* If the remaining parameters are not registers,
7232 get the cost to put them into registers. */
7246 {
7248 {
7249 /*Vector truncate. */
7251 }
7252 else
7254 }
7259 {
7261 {
7262 /*Vector conversion. */
7264 }
7265 else
7267 }
7273 /* Strip the rounding part. They will all be implemented
7274 by the fcvt* family of instructions anyway. */
7276 {
7285 }
7288 {
7291 else
7293 }
7295 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7296 fixed-point fcvt. */
7301 {
7305 }
7312 {
7313 /* ABS (vector). */
7316 }
7318 {
7321 /* FABD, which is analogous to FADD. */
7323 {
7330 }
7331 /* Simple FABS is analogous to FNEG. */
7334 }
7335 else
7336 {
7337 /* Integer ABS will either be split to
7338 two arithmetic instructions, or will be an ABS
7339 (scalar), which we don't model. */
7343 }
7349 {
7352 else
7353 {
7354 /* FMAXNM/FMINNM/FMAX/FMIN.
7355 TODO: This may not be accurate for all implementations, but
7356 we do not model this in the cost tables. */
7358 }
7359 }
7363 /* The floating point round to integer frint* instructions. */
7365 {
7370 }
7373 {
7378 }
7383 /* Decompose <su>muldi3_highpart. */
7385 mode == DImode
7386 /* (lshiftrt:TI */
7389 /* (mult:TI */
7391 /* (ANY_EXTEND:TI (reg:DI))
7392 (ANY_EXTEND:TI (reg:DI))) */
7399 /* (const_int 64) */
7402 {
7403 /* UMULH/SMULH. */
7411 }
7413 /* Fall through. */
7416 }
7423 }
7425 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7426 calculated for X. This cost is stored in *COST. Returns true
7427 if the total cost of X was calculated. */
7428 static bool
7431 {
7435 {
7440 }
7443 }
7445 static int
7448 {
7454 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7461 /* Moving between GPR and stack cost is the same as GP2GP. */
7466 /* To/From the stack register, we move via the gprs. */
7472 {
7473 /* 128-bit operations on general registers require 2 instructions. */
7481 /* When AdvSIMD instructions are disabled it is not possible to move
7482 a 128-bit value directly between Q registers. This is handled in
7483 secondary reload. A general register is used as a scratch to move
7484 the upper DI value and the lower DI value is moved directly,
7485 hence the cost is the sum of three moves. */
7490 }
7500 }
7502 static int
7504 reg_class_t rclass ATTRIBUTE_UNUSED,
7506 {
7508 }
7510 /* Return true if it is safe and beneficial to use the rsqrt optabs to
7511 optimize 1.0/sqrt. */
7513 static bool
7515 {
7517 && flag_unsafe_math_optimizations
7520 }
7522 /* Function to decide when to use
7523 reciprocal square root builtins. */
7525 static tree
7527 {
7531 }
7535 /* Select reciprocal square root initial estimate
7536 insn depending on machine mode. */
7538 rsqrte_type
7540 {
7542 {
7549 }
7550 }
7554 /* Select reciprocal square root Newton-Raphson step
7555 insn depending on machine mode. */
7557 rsqrts_type
7559 {
7561 {
7568 }
7569 }
7571 /* Emit instruction sequence to compute
7572 reciprocal square root. Use two Newton-Raphson steps
7573 for single precision and three for double precision. */
7575 void
7577 {
7594 iterations--;
7597 {
7607 }
7610 }
7612 /* Return the number of instructions that can be issued per cycle. */
7613 static int
7615 {
7617 }
7619 static int
7621 {
7625 }
7628 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
7629 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
7630 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
7632 static int
7635 {
7637 }
7640 /* Vectorizer cost model target hooks. */
7642 /* Implement targetm.vectorize.builtin_vectorization_cost. */
7643 static int
7645 tree vectype,
7647 {
7651 {
7698 }
7699 }
7701 /* Implement targetm.vectorize.add_stmt_cost. */
7702 static unsigned
7706 {
7711 {
7716 /* Statements in an inner loop relative to the loop being
7717 vectorized are weighted more heavily. The value here is
7718 arbitrary and could potentially be improved with analysis. */
7724 }
7727 }
7731 /* Enum describing the various ways that the
7732 aarch64_parse_{arch,tune,cpu,extension} functions can fail.
7733 This way their callers can choose what kind of error to give. */
7735 enum aarch64_parse_opt_result
7736 {
7740 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */
7741 };
7743 /* Parse the architecture extension string STR and update ISA_FLAGS
7744 with the architecture features turned on or off. Return a
7745 aarch64_parse_opt_result describing the result. */
7747 static enum aarch64_parse_opt_result
7749 {
7750 /* The extension string is parsed left to right. */
7753 /* Flag to say whether we are adding or removing an extension. */
7757 {
7761 str++;
7766 else
7770 {
7774 }
7782 /* Scan over the extensions table trying to find an exact match. */
7784 {
7786 {
7787 /* Add or remove the extension. */
7790 else
7793 }
7794 }
7797 {
7798 /* Extension not found in list. */
7800 }
7803 };
7806 }
7808 /* Parse the TO_PARSE string and put the architecture struct that it
7809 selects into RES and the architectural features into ISA_FLAGS.
7810 Return an aarch64_parse_opt_result describing the parse result.
7811 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
7813 static enum aarch64_parse_opt_result
7816 {
7828 else
7835 /* Loop through the list of supported ARCHes to find a match. */
7837 {
7839 {
7843 {
7844 /* TO_PARSE string contains at least one extension. */
7845 enum aarch64_parse_opt_result ext_res
7850 }
7851 /* Extension parsing was successful. Confirm the result
7852 arch and ISA flags. */
7856 }
7857 }
7859 /* ARCH name not found in list. */
7861 }
7863 /* Parse the TO_PARSE string and put the result tuning in RES and the
7864 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
7865 describing the parse result. If there is an error parsing, RES and
7866 ISA_FLAGS are left unchanged. */
7868 static enum aarch64_parse_opt_result
7871 {
7883 else
7890 /* Loop through the list of supported CPUs to find a match. */
7892 {
7894 {
7899 {
7900 /* TO_PARSE string contains at least one extension. */
7901 enum aarch64_parse_opt_result ext_res
7906 }
7907 /* Extension parsing was successfull. Confirm the result
7908 cpu and ISA flags. */
7912 }
7913 }
7915 /* CPU name not found in list. */
7917 }
7919 /* Parse the TO_PARSE string and put the cpu it selects into RES.
7920 Return an aarch64_parse_opt_result describing the parse result.
7921 If the parsing fails the RES does not change. */
7923 static enum aarch64_parse_opt_result
7925 {
7931 /* Loop through the list of supported CPUs to find a match. */
7933 {
7935 {
7938 }
7939 }
7941 /* CPU name not found in list. */
7943 }
7945 /* Parse TOKEN, which has length LENGTH to see if it is an option
7946 described in FLAG. If it is, return the index bit for that fusion type.
7947 If not, error (printing OPTION_NAME) and return zero. */
7949 static unsigned int
7954 {
7956 {
7960 }
7964 }
7966 /* Parse OPTION which is a comma-separated list of flags to enable.
7967 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7968 default state we inherit from the CPU tuning structures. OPTION_NAME
7969 gives the top-level option we are parsing in the -moverride string,
7970 for use in error messages. */
7972 static unsigned int
7977 {
7984 {
7987 token_length,
7988 flags,
7989 option_name);
7990 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7991 in the token stream, reset the supported operations. So:
7993 adrp+add.cmp+branch.none.adrp+add
7995 would have the result of turning on only adrp+add fusion. */
8001 }
8003 /* We ended with a comma, print something. */
8005 {
8008 }
8010 /* We still have one more token to parse. */
8013 token_length,
8014 flags,
8015 option_name);
8021 }
8023 /* Support for overriding instruction fusion. */
8025 static void
8028 {
8030 aarch64_fusible_pairs,
8033 }
8035 /* Support for overriding other tuning flags. */
8037 static void
8040 {
8041 tune->extra_tuning_flags
8043 aarch64_tuning_flags,
8046 }
8048 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8049 we understand. If it is, extract the option string and handoff to
8050 the appropriate function. */
8052 void
8056 {
8062 {
8065 }
8067 /* Get the length of the option name. */
8069 /* Skip the '=' to get to the option string. */
8070 option_part++;
8073 {
8075 {
8078 }
8079 }
8083 }
8085 /* A checking mechanism for the implementation of the tls size. */
8087 static void
8089 {
8094 {
8096 /* Both the default and maximum TLS size allowed under tiny is 1M which
8097 needs two instructions to address, so we clamp the size to 24. */
8102 /* The maximum TLS size allowed under small is 4G. */
8107 /* The maximum TLS size allowed under large is 16E.
8108 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8114 }
8117 }
8119 /* Parse STRING looking for options in the format:
8120 string :: option:string
8121 option :: name=substring
8122 name :: {a-z}
8123 substring :: defined by option. */
8125 static void
8128 {
8139 {
8141 /* Make this substring look like a string. */
8145 }
8147 /* One last option to parse. */
8150 }
8153 static void
8155 {
8161 /* If not optimizing for size, set the default
8162 alignment to what the target wants. */
8164 {
8171 }
8173 /* If nopcrelative_literal_loads is set on the command line, this
8174 implies that the user asked for PC relative literal loads. */
8178 /* If it is not set on the command line, we default to no
8179 pc relative literal loads. */
8183 /* In the tiny memory model it makes no sense
8184 to disallow non PC relative literal pool loads
8185 as many other things will break anyway. */
8190 }
8192 /* 'Unpack' up the internal tuning structs and update the options
8193 in OPTS. The caller must have set up selected_tune and selected_arch
8194 as all the other target-specific codegen decisions are
8195 derived from them. */
8197 void
8199 {
8202 /* Make a copy of the tuning parameters attached to the core, which
8203 we may later overwrite. */
8211 /* This target defaults to strict volatile bitfields. */
8220 {
8232 }
8234 /* We don't mind passing in global_options_set here as we don't use
8235 the *options_set structs anyway. */
8237 queue_depth,
8241 /* Set the L1 cache line size. */
8249 }
8251 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8252 specified in STR and throw errors if appropriate. Put the results if
8253 they are valid in RES and ISA_FLAGS. Return whether the option is
8254 valid. */
8256 static bool
8259 {
8260 enum aarch64_parse_opt_result parse_res
8267 {
8279 }
8282 }
8284 /* Validate a command-line -march option. Parse the arch and extensions
8285 (if any) specified in STR and throw errors if appropriate. Put the
8286 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8287 option is valid. */
8289 static bool
8292 {
8293 enum aarch64_parse_opt_result parse_res
8300 {
8312 }
8315 }
8317 /* Validate a command-line -mtune option. Parse the cpu
8318 specified in STR and throw errors if appropriate. Put the
8319 result, if it is valid, in RES. Return whether the option is
8320 valid. */
8322 static bool
8324 {
8325 enum aarch64_parse_opt_result parse_res
8332 {
8341 }
8343 }
8345 /* Return the CPU corresponding to the enum CPU.
8346 If it doesn't specify a cpu, return the default. */
8350 {
8354 /* The & 0x3f is to extract the bottom 6 bits that encode the
8355 default cpu as selected by the --with-cpu GCC configure option
8356 in config.gcc.
8357 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8358 flags mechanism should be reworked to make it more sane. */
8360 }
8362 /* Return the architecture corresponding to the enum ARCH.
8363 If it doesn't specify a valid architecture, return the default. */
8367 {
8374 }
8376 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8377 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8378 tuning structs. In particular it must set selected_tune and
8379 aarch64_isa_flags that define the available ISA features and tuning
8380 decisions. It must also set selected_arch as this will be used to
8381 output the .arch asm tags for each function. */
8383 static void
8385 {
8398 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8399 If either of -march or -mtune is given, they override their
8400 respective component of -mcpu. */
8412 /* If the user did not specify a processor, choose the default
8413 one for them. This will be the CPU set during configuration using
8414 --with-cpu, otherwise it is "generic". */
8416 {
8418 {
8422 }
8423 else
8424 {
8425 /* Get default configure-time CPU. */
8428 }
8432 }
8433 /* If both -mcpu and -march are specified check that they are architecturally
8434 compatible, warn if they're not and prefer the -march ISA flags. */
8436 {
8438 {
8442 }
8447 }
8448 else
8449 {
8450 /* -mcpu but no -march. */
8457 }
8459 /* Set the arch as well as we will need it when outputing
8460 the .arch directive in assembly. */
8462 {
8465 }
8470 #ifndef HAVE_AS_MABI_OPTION
8471 /* The compiler may have been configured with 2.23.* binutils, which does
8472 not have support for ILP32. */
8475 #endif
8477 /* Make sure we properly set up the explicit options. */
8488 /* Save these options as the default ones in case we push and pop them later
8489 while processing functions with potential target attributes. */
8490 target_option_default_node = target_option_current_node
8495 }
8497 /* Implement targetm.override_options_after_change. */
8499 static void
8501 {
8503 }
8507 {
8511 }
8513 void
8515 {
8517 }
8519 /* A checking mechanism for the implementation of the various code models. */
8520 static void
8522 {
8524 {
8526 {
8531 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8533 ? AARCH64_CMODEL_SMALL_PIC
8535 #else
8537 #endif
8545 }
8546 }
8547 else
8549 }
8551 /* Implement TARGET_OPTION_SAVE. */
8553 static void
8555 {
8557 }
8559 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8560 using the information saved in PTR. */
8562 static void
8564 {
8572 }
8574 /* Implement TARGET_OPTION_PRINT. */
8576 static void
8578 {
8589 }
8593 void
8595 {
8597 }
8599 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
8600 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
8601 of the function, if such exists. This function may be called multiple
8602 times on a single function so use aarch64_previous_fndecl to avoid
8603 setting up identical state. */
8605 static void
8607 {
8608 tree old_tree = (aarch64_previous_fndecl
8612 tree new_tree = (fndecl
8618 {
8621 ;
8624 {
8629 else
8632 }
8635 {
8643 else
8646 }
8647 }
8652 /* If we turned on SIMD make sure that any vector parameters are re-laid out
8653 so that they use proper vector modes. */
8655 {
8658 {
8663 }
8664 }
8665 }
8667 /* Enum describing the various ways we can handle attributes.
8668 In many cases we can reuse the generic option handling machinery. */
8670 enum aarch64_attr_opt_type
8671 {
8675 aarch64_attr_custom /* Attribute requires a custom handling function. */
8676 };
8678 /* All the information needed to handle a target attribute.
8679 NAME is the name of the attribute.
8680 ATTR_TYPE specifies the type of behaviour of the attribute as described
8681 in the definition of enum aarch64_attr_opt_type.
8682 ALLOW_NEG is true if the attribute supports a "no-" form.
8683 HANDLER is the function that takes the attribute string and whether
8684 it is a pragma or attribute and handles the option. It is needed only
8685 when the ATTR_TYPE is aarch64_attr_custom.
8686 OPT_NUM is the enum specifying the option that the attribute modifies.
8687 This is needed for attributes that mirror the behaviour of a command-line
8688 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
8689 aarch64_attr_enum. */
8691 struct aarch64_attribute_info
8692 {
8698 };
8700 /* Handle the ARCH_STR argument to the arch= target attribute.
8701 PRAGMA_OR_ATTR is used in potential error messages. */
8703 static bool
8705 {
8707 enum aarch64_parse_opt_result parse_res
8711 {
8716 }
8719 {
8732 }
8735 }
8737 /* Handle the argument CPU_STR to the cpu= target attribute.
8738 PRAGMA_OR_ATTR is used in potential error messages. */
8740 static bool
8742 {
8744 enum aarch64_parse_opt_result parse_res
8748 {
8756 }
8759 {
8772 }
8775 }
8777 /* Handle the argument STR to the tune= target attribute.
8778 PRAGMA_OR_ATTR is used in potential error messages. */
8780 static bool
8782 {
8784 enum aarch64_parse_opt_result parse_res
8788 {
8793 }
8796 {
8802 }
8805 }
8807 /* Parse an architecture extensions target attribute string specified in STR.
8808 For example "+fp+nosimd". Show any errors if needed. Return TRUE
8809 if successful. Update aarch64_isa_flags to reflect the ISA features
8810 modified.
8811 PRAGMA_OR_ATTR is used in potential error messages. */
8813 static bool
8815 {
8819 /* We allow "+nothing" in the beginning to clear out all architectural
8820 features if the user wants to handpick specific features. */
8822 {
8825 }
8830 {
8833 }
8836 {
8849 }
8852 }
8854 /* The target attributes that we support. On top of these we also support just
8855 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
8856 handled explicitly in aarch64_process_one_target_attr. */
8859 {
8861 OPT_mgeneral_regs_only },
8863 OPT_mfix_cortex_a53_835769 },
8867 OPT_momit_leaf_frame_pointer },
8870 OPT_march_ },
8873 OPT_mtune_ },
8875 };
8877 /* Parse ARG_STR which contains the definition of one target attribute.
8878 Show appropriate errors if any or return true if the attribute is valid.
8879 PRAGMA_OR_ATTR holds the string to use in error messages about whether
8880 we're processing a target attribute or pragma. */
8882 static bool
8884 {
8890 {
8893 }
8898 /* Skip leading whitespace. */
8900 str_to_check++;
8902 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
8903 It is easier to detect and handle it explicitly here rather than going
8904 through the machinery for the rest of the target attributes in this
8905 function. */
8910 {
8913 }
8916 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
8917 and point ARG to "foo". */
8919 {
8921 arg++;
8922 }
8926 {
8927 /* If the names don't match up, or the user has given an argument
8928 to an attribute that doesn't accept one, or didn't give an argument
8929 to an attribute that expects one, fail to match. */
8938 {
8942 }
8944 /* If the name matches but the attribute does not allow "no-" versions
8945 then we can't match. */
8947 {
8951 }
8954 {
8955 /* Has a custom handler registered.
8956 For example, cpu=, arch=, tune=. */
8963 /* Either set or unset a boolean option. */
8965 {
8973 }
8974 /* Set or unset a bit in the target_flags. aarch64_handle_option
8975 should know what mask to apply given the option number. */
8977 {
8979 /* We only need to specify the option number.
8980 aarch64_handle_option will know which mask to apply. */
8986 }
8987 /* Use the option setting machinery to set an option to an enum. */
8989 {
8996 {
8999 global_dc);
9000 }
9001 else
9002 {
9005 }
9007 }
9010 }
9011 }
9013 /* If we reached here we either have found an attribute and validated
9014 it or didn't match any. If we matched an attribute but its arguments
9015 were malformed we will have returned false already. */
9017 }
9019 /* Count how many times the character C appears in
9020 NULL-terminated string STR. */
9022 static unsigned int
9024 {
9027 {
9029 res++;
9031 str++;
9032 }
9035 }
9037 /* Parse the tree in ARGS that contains the target attribute information
9038 and update the global target options space. PRAGMA_OR_ATTR is a string
9039 to be used in error messages, specifying whether this is processing
9040 a target attribute or a target pragma. */
9042 bool
9044 {
9046 {
9047 do
9048 {
9051 {
9054 }
9059 }
9060 /* We expect to find a string to parse. */
9068 {
9071 }
9073 /* Used to catch empty spaces between commas i.e.
9074 attribute ((target ("attr1,,attr2"))). */
9077 /* Handle multiple target attributes separated by ','. */
9082 {
9083 num_attrs++;
9085 {
9088 }
9091 }
9094 {
9098 }
9101 }
9103 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9104 process attribute ((target ("..."))). */
9106 static bool
9108 {
9111 tree old_optimize;
9115 /* If what we're processing is the current pragma string then the
9116 target option node is already stored in target_option_current_node
9117 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9118 having to re-parse the string. This is especially useful to keep
9119 arm_neon.h compile times down since that header contains a lot
9120 of intrinsics enclosed in pragmas. */
9122 {
9125 }
9131 /* If the function changed the optimization levels as well as setting
9132 target options, start with the optimizations specified. */
9137 /* Save the current target options to restore at the end. */
9140 /* If fndecl already has some target attributes applied to it, unpack
9141 them so that we add this attribute on top of them, rather than
9142 overwriting them. */
9144 {
9150 }
9151 else
9158 /* Set up any additional state. */
9160 {
9162 /* Initialize SIMD builtins if we haven't already.
9163 Set current_target_pragma to NULL for the duration so that
9164 the builtin initialization code doesn't try to tag the functions
9165 being built with the attributes specified by any current pragma, thus
9166 going into an infinite recursion. */
9168 {
9173 }
9175 }
9176 else
9182 {
9187 }
9195 }
9197 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9198 tri-bool options (yes, no, don't care) and the default value is
9199 DEF, determine whether to reject inlining. */
9201 static bool
9204 {
9205 /* If the callee doesn't care, always allow inlining. */
9209 /* If the caller doesn't care, always allow inlining. */
9213 /* Otherwise, allow inlining if either the callee and caller values
9214 agree, or if the callee is using the default value. */
9216 }
9218 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9219 to inline CALLEE into CALLER based on target-specific info.
9220 Make sure that the caller and callee have compatible architectural
9221 features. Then go through the other possible target attributes
9222 and see if they can block inlining. Try not to reject always_inline
9223 callees unless they are incompatible architecturally. */
9225 static bool
9227 {
9231 /* If callee has no option attributes, then it is ok to inline. */
9242 /* Callee's ISA flags should be a subset of the caller's. */
9247 /* Allow non-strict aligned functions inlining into strict
9248 aligned ones. */
9258 /* If the architectural features match up and the callee is always_inline
9259 then the other attributes don't matter. */
9271 /* Honour explicit requests to workaround errata. */
9278 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9279 caller and calle and they don't match up, reject inlining. */
9286 /* If the callee has specific tuning overrides, respect them. */
9291 /* If the user specified tuning override strings for the
9292 caller and callee and they don't match up, reject inlining.
9293 We just do a string compare here, we don't analyze the meaning
9294 of the string, as it would be too costly for little gain. */
9302 }
9304 /* Return true if SYMBOL_REF X binds locally. */
9306 static bool
9308 {
9312 }
9314 /* Return true if SYMBOL_REF X is thread local */
9315 static bool
9317 {
9325 }
9327 /* Classify a TLS symbol into one of the TLS kinds. */
9328 enum aarch64_symbol_type
9330 {
9334 {
9341 {
9347 }
9358 else
9367 }
9368 }
9370 /* Return the method that should be used to access SYMBOL_REF or
9371 LABEL_REF X. */
9373 enum aarch64_symbol_type
9375 {
9377 {
9379 {
9394 }
9395 }
9398 {
9400 {
9401 /* This is alright even in PIC code as the constant
9402 pool reference is always PC relative and within
9403 the same translation unit. */
9407 else
9409 }
9415 {
9417 /* When we retreive symbol + offset address, we have to make sure
9418 the offset does not cause overflow of the final address. But
9419 we have no way of knowing the address of symbol at compile time
9420 so we can't accurately say if the distance between the PC and
9421 symbol + offset is outside the addressible range of +/-1M in the
9422 TINY code model. So we rely on images not being greater than
9423 1M and cap the offset at 1M and anything beyond 1M will have to
9424 be loaded using an alternative mechanism. */
9431 /* Same reasoning as the tiny code model, but the offset cap here is
9432 4G. */
9453 }
9454 }
9456 /* By default push everything into the constant pool. */
9458 }
9460 bool
9462 {
9464 }
9466 bool
9468 {
9476 }
9478 /* Return true if X holds either a quarter-precision or
9479 floating-point +0.0 constant. */
9480 static bool
9482 {
9489 /* We only handle moving 0.0 to a TFmode register. */
9494 }
9496 static bool
9498 {
9499 /* Do not allow vector struct mode constants. We could support
9500 0 and -1 easily, but they need support in aarch64-simd.md. */
9504 /* This could probably go away because
9505 we now decompose CONST_INTs according to expand_mov_immediate. */
9516 }
9518 rtx
9520 {
9526 /* Can return in any reg. */
9529 }
9531 /* On AAPCS systems, this is the "struct __va_list". */
9534 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9535 Return the type to use as __builtin_va_list.
9537 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9539 struct __va_list
9540 {
9541 void *__stack;
9542 void *__gr_top;
9543 void *__vr_top;
9544 int __gr_offs;
9545 int __vr_offs;
9546 }; */
9548 static tree
9550 {
9551 tree va_list_name;
9554 /* Create the type. */
9556 /* Give it the required name. */
9558 TYPE_DECL,
9560 va_list_type);
9565 /* Create the fields. */
9568 ptr_type_node);
9571 ptr_type_node);
9574 ptr_type_node);
9577 integer_type_node);
9580 integer_type_node);
9600 /* Compute its layout. */
9604 }
9606 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
9607 static void
9609 {
9613 tree t;
9619 gr_save_area_size
9621 vr_save_area_size
9625 {
9628 }
9637 NULL_TREE);
9639 NULL_TREE);
9641 NULL_TREE);
9643 NULL_TREE);
9645 NULL_TREE);
9647 /* Emit code to initialize STACK, which points to the next varargs stack
9648 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
9649 by named arguments. STACK is 8-byte aligned. */
9656 /* Emit code to initialize GRTOP, the top of the GR save area.
9657 virtual_incoming_args_rtx should have been 16 byte aligned. */
9662 /* Emit code to initialize VRTOP, the top of the VR save area.
9663 This address is gr_save_area_bytes below GRTOP, rounded
9664 down to the next 16-byte boundary. */
9674 /* Emit code to initialize GROFF, the offset from GRTOP of the
9675 next GPR argument. */
9680 /* Likewise emit code to initialize VROFF, the offset from FTOP
9681 of the next VR argument. */
9685 }
9687 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
9689 static tree
9692 {
9693 tree addr;
9699 machine_mode mode;
9726 type,
9730 {
9731 /* TYPE passed in fp/simd registers. */
9743 {
9746 }
9749 {
9751 }
9752 }
9753 else
9754 {
9755 /* TYPE passed in general registers. */
9768 {
9770 }
9771 }
9773 /* Get a local temporary for the field value. */
9776 /* Emit code to branch if off >= 0. */
9782 {
9783 /* Emit: offs = (offs + 15) & -16. */
9789 }
9790 else
9793 /* Update ap.__[g|v]r_offs */
9798 /* String up. */
9802 /* [cond2] if (ap.__[g|v]r_offs > 0) */
9807 /* String up: make sure the assignment happens before the use. */
9811 /* Prepare the trees handling the argument that is passed on the stack;
9812 the top level node will store in ON_STACK. */
9815 {
9816 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
9824 }
9825 else
9827 /* Advance ap.__stack */
9835 /* String up roundup and advance. */
9838 /* String up with arg */
9840 /* Big-endianness related address adjustment. */
9843 {
9847 }
9852 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
9862 {
9863 /* type ha; // treat as "struct {ftype field[n];}"
9864 ... [computing offs]
9865 for (i = 0; i <nregs; ++i, offs += 16)
9866 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
9867 return ha; */
9871 /* Declare a local variable. */
9875 /* Establish the base type. */
9877 {
9890 /* The half precision and quad precision are not fully supported yet. Enable
9891 the following code after the support is complete. Need to find the correct
9892 type node for __fp16 *. */
9893 #if 0
9898 #endif
9901 {
9905 }
9909 }
9911 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
9919 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
9921 {
9931 }
9935 }
9945 }
9947 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
9949 static void
9953 {
9955 CUMULATIVE_ARGS local_cum;
9958 /* The caller has advanced CUM up to, but not beyond, the last named
9959 argument. Advance a local copy of CUM past the last "real" named
9960 argument, to find out how many registers are left over. */
9964 /* Found out how many registers we need to save. */
9969 {
9972 }
9975 {
9977 {
9980 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
9988 }
9990 {
9991 /* We can't use move_block_from_reg, because it will use
9992 the wrong mode, storing D regs only. */
9996 /* Set OFF to the offset from virtual_incoming_args_rtx of
9997 the first vector register. The VR save area lies below
9998 the GR one, and is aligned to 16 bytes. */
10004 {
10012 }
10013 }
10014 }
10016 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10017 any complication of having crtl->args.pretend_args_size changed. */
10022 }
10024 static void
10026 {
10029 {
10031 {
10034 }
10035 }
10036 }
10038 /* Walk down the type tree of TYPE counting consecutive base elements.
10039 If *MODEP is VOIDmode, then set it to the first valid floating point
10040 type. If a non-floating point type is found, or if a floating point
10041 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10042 otherwise return the count in the sub-tree. */
10043 static int
10045 {
10046 machine_mode mode;
10047 HOST_WIDE_INT size;
10050 {
10078 /* Use V2SImode and V4SImode as representatives of all 64-bit
10079 and 128-bit vector types. */
10082 {
10091 }
10096 /* Vector modes are considered to be opaque: two vectors are
10097 equivalent for the purposes of being homogeneous aggregates
10098 if they are the same size. */
10105 {
10109 /* Can't handle incomplete types nor sizes that are not
10110 fixed. */
10117 || !index
10128 /* There must be no padding. */
10133 }
10136 {
10139 tree field;
10141 /* Can't handle incomplete types nor sizes that are not
10142 fixed. */
10148 {
10156 }
10158 /* There must be no padding. */
10163 }
10167 {
10168 /* These aren't very interesting except in a degenerate case. */
10171 tree field;
10173 /* Can't handle incomplete types nor sizes that are not
10174 fixed. */
10180 {
10188 }
10190 /* There must be no padding. */
10195 }
10199 }
10202 }
10204 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10205 type as described in AAPCS64 \S 4.1.2.
10207 See the comment above aarch64_composite_type_p for the notes on MODE. */
10209 static bool
10211 machine_mode mode)
10212 {
10222 }
10224 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10225 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10226 array types. The C99 floating-point complex types are also considered
10227 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10228 types, which are GCC extensions and out of the scope of AAPCS64, are
10229 treated as composite types here as well.
10231 Note that MODE itself is not sufficient in determining whether a type
10232 is such a composite type or not. This is because
10233 stor-layout.c:compute_record_mode may have already changed the MODE
10234 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10235 structure with only one field may have its MODE set to the mode of the
10236 field. Also an integer mode whose size matches the size of the
10237 RECORD_TYPE type may be used to substitute the original mode
10238 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10239 solely relied on. */
10241 static bool
10243 machine_mode mode)
10244 {
10257 }
10259 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10260 shall be passed or returned in simd/fp register(s) (providing these
10261 parameter passing registers are available).
10263 Upon successful return, *COUNT returns the number of needed registers,
10264 *BASE_MODE returns the mode of the individual register and when IS_HAF
10265 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10266 floating-point aggregate or a homogeneous short-vector aggregate. */
10268 static bool
10270 const_tree type,
10274 {
10282 {
10285 }
10287 {
10291 }
10293 {
10297 {
10300 }
10301 else
10303 }
10304 else
10309 }
10311 /* Implement TARGET_STRUCT_VALUE_RTX. */
10313 static rtx
10316 {
10318 }
10320 /* Implements target hook vector_mode_supported_p. */
10321 static bool
10323 {
10335 }
10337 /* Return appropriate SIMD container
10338 for MODE within a vector of WIDTH bits. */
10339 static machine_mode
10341 {
10344 {
10347 {
10362 }
10363 else
10365 {
10376 }
10377 }
10379 }
10381 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10382 static machine_mode
10384 {
10386 }
10388 /* Return the bitmask of possible vector sizes for the vectorizer
10389 to iterate over. */
10390 static unsigned int
10392 {
10394 }
10396 /* Implement TARGET_MANGLE_TYPE. */
10400 {
10401 /* The AArch64 ABI documents say that "__va_list" has to be
10402 managled as if it is in the "std" namespace. */
10406 /* Half-precision float. */
10410 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10411 builtin types. */
10415 /* Use the default mangling. */
10417 }
10420 /* Return true if the rtx_insn contains a MEM RTX somewhere
10421 in it. */
10423 static bool
10425 {
10432 }
10434 /* Find the first rtx_insn before insn that will generate an assembly
10435 instruction. */
10439 {
10443 do
10444 {
10446 }
10450 }
10452 static bool
10454 {
10456 /* A number of these may be AArch32 only. */
10461 };
10464 {
10467 }
10470 }
10472 /* Check if there is a register dependency between a load and the insn
10473 for which we hold recog_data. */
10475 static bool
10477 {
10478 rtx load_reg;
10488 {
10494 }
10496 }
10499 /* When working around the Cortex-A53 erratum 835769,
10500 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10501 instruction and has a preceding memory instruction such that a NOP
10502 should be inserted between them. */
10504 bool
10506 {
10509 rtx body;
10522 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10523 Restore recog state to INSN to avoid state corruption. */
10531 /* If the previous insn is a memory op and there is no dependency between
10532 it and the DImode madd, emit a NOP between them. If body is NULL then we
10533 have a complex memory operation, probably a load/store pair.
10534 Be conservative for now and emit a NOP. */
10541 }
10544 /* Implement FINAL_PRESCAN_INSN. */
10546 void
10548 {
10551 }
10554 /* Return the equivalent letter for size. */
10555 static char
10557 {
10559 {
10565 }
10566 }
10568 /* Return true iff x is a uniform vector of floating-point
10569 constants, and the constant can be represented in
10570 quarter-precision form. Note, as aarch64_float_const_representable
10571 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10572 static bool
10574 {
10575 rtx elt;
10579 }
10581 /* Return true for valid and false for invalid. */
10582 bool
10585 {
10586 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
10587 matches = 1; \
10588 for (i = 0; i < idx; i += (STRIDE)) \
10589 if (!(TEST)) \
10590 matches = 0; \
10591 if (matches) \
10592 { \
10593 immtype = (CLASS); \
10594 elsize = (ELSIZE); \
10595 eshift = (SHIFT); \
10596 emvn = (NEG); \
10597 break; \
10598 }
10608 {
10614 {
10619 }
10622 }
10624 /* Splat vector constant out into a byte vector. */
10626 {
10627 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
10628 it must be laid out in the vector register in reverse order. */
10636 {
10639 }
10641 }
10643 /* Sanity check. */
10646 do
10647 {
10696 }
10703 {
10713 /* Un-invert bytes of recognized vector, if necessary. */
10719 {
10720 /* FIXME: Broken on 32-bit H_W_I hosts. */
10729 }
10730 else
10731 {
10735 /* Construct 'abcdefgh' because the assembler cannot handle
10736 generic constants. */
10741 }
10742 }
10745 #undef CHECK
10746 }
10748 /* Check of immediate shift constants are within range. */
10749 bool
10751 {
10755 else
10757 }
10759 /* Return true if X is a uniform vector where all elements
10760 are either the floating-point constant 0.0 or the
10761 integer constant 0. */
10762 bool
10764 {
10766 }
10769 /* Return the bitmask CONST_INT to select the bits required by a zero extract
10770 operation of width WIDTH at bit position POS. */
10772 rtx
10774 {
10778 unsigned HOST_WIDE_INT mask
10781 }
10783 bool
10785 {
10790 {
10795 }
10798 }
10800 bool
10802 {
10815 }
10817 /* Return a const_int vector of VAL. */
10818 rtx
10820 {
10829 }
10831 /* Check OP is a legal scalar immediate for the MOVI instruction. */
10833 bool
10835 {
10836 machine_mode vmode;
10842 }
10844 /* Construct and return a PARALLEL RTX vector with elements numbering the
10845 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
10846 the vector - from the perspective of the architecture. This does not
10847 line up with GCC's perspective on lane numbers, so we end up with
10848 different masks depending on our target endian-ness. The diagram
10849 below may help. We must draw the distinction when building masks
10850 which select one half of the vector. An instruction selecting
10851 architectural low-lanes for a big-endian target, must be described using
10852 a mask selecting GCC high-lanes.
10854 Big-Endian Little-Endian
10856 GCC 0 1 2 3 3 2 1 0
10857 | x | x | x | x | | x | x | x | x |
10858 Architecture 3 2 1 0 3 2 1 0
10860 Low Mask: { 2, 3 } { 0, 1 }
10861 High Mask: { 0, 1 } { 2, 3 }
10862 */
10864 rtx
10866 {
10872 rtx t1;
10877 else
10885 }
10887 /* Check OP for validity as a PARALLEL RTX vector with elements
10888 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
10889 from the perspective of the architecture. See the diagram above
10890 aarch64_simd_vect_par_cnst_half for more details. */
10892 bool
10895 {
10908 {
10915 }
10917 }
10919 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
10920 HIGH (exclusive). */
10921 void
10923 const_tree exp)
10924 {
10925 HOST_WIDE_INT lane;
10930 {
10933 else
10935 }
10936 }
10938 /* Return TRUE if OP is a valid vector addressing mode. */
10939 bool
10941 {
10944 }
10946 /* Emit a register copy from operand to operand, taking care not to
10947 early-clobber source registers in the process.
10949 COUNT is the number of components into which the copy needs to be
10950 decomposed. */
10951 void
10954 {
10964 else
10968 }
10970 /* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
10971 one of VSTRUCT modes: OI, CI or XI. */
10972 int
10974 {
10975 machine_mode mode;
10980 {
10983 {
10992 }
10993 }
10995 }
10997 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
10998 one of VSTRUCT modes: OI, CI, or XI. */
10999 int
11001 {
11003 }
11005 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11006 alignment of a vector to 128 bits. */
11007 static HOST_WIDE_INT
11009 {
11012 }
11014 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11015 static bool
11017 {
11021 /* We guarantee alignment for vectors up to 128-bits. */
11026 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11028 }
11030 /* If VALS is a vector constant that can be loaded into a register
11031 using DUP, generate instructions to do so and return an RTX to
11032 assign to the register. Otherwise return NULL_RTX. */
11033 static rtx
11035 {
11038 rtx x;
11043 /* We can load this constant by using DUP and a constant in a
11044 single ARM register. This will be cheaper than a vector
11045 load. */
11048 }
11051 /* Generate code to load VALS, which is a PARALLEL containing only
11052 constants (for vec_init) or CONST_VECTOR, efficiently into a
11053 register. Returns an RTX to copy into the register, or NULL_RTX
11054 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11055 static rtx
11057 {
11059 rtx const_dup;
11068 {
11069 /* A CONST_VECTOR must contain only CONST_INTs and
11070 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11071 Only store valid constants in a CONST_VECTOR. */
11073 {
11076 n_const++;
11077 }
11080 }
11081 else
11086 /* Load using MOVI/MVNI. */
11089 /* Loaded using DUP. */
11092 /* Load from constant pool. We can not take advantage of single-cycle
11093 LD1 because we need a PC-relative addressing mode. */
11095 else
11096 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11097 We can not construct an initializer. */
11099 }
11101 void
11103 {
11112 {
11116 else
11121 }
11124 {
11127 {
11130 }
11131 }
11133 /* Splat a single non-constant element if we can. */
11135 {
11139 }
11141 /* Half the fields (or less) are non-constant. Load constant then overwrite
11142 varying fields. Hope that this is more efficient than using the stack. */
11144 {
11147 /* Load constant part of vector. We really don't care what goes into the
11148 parts we will overwrite, but we're more likely to be able to load the
11149 constant efficiently if it has fewer, larger, repeating parts
11150 (see aarch64_simd_valid_immediate). */
11152 {
11158 {
11159 /* Look in the copied vector, as more elements are const. */
11162 {
11165 }
11166 }
11168 }
11171 /* Insert variables. */
11176 {
11182 }
11184 }
11186 /* Construct the vector in memory one field at a time
11187 and load the whole vector. */
11195 }
11197 static unsigned HOST_WIDE_INT
11199 {
11200 return
11203 }
11205 /* Select a format to encode pointers in exception handling data. */
11206 int
11208 {
11211 {
11217 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11218 for everything. */
11222 /* No assumptions here. 8-byte relocs required. */
11225 }
11227 }
11229 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11230 by the function fndecl. */
11232 void
11234 tree fndecl)
11235 {
11241 else
11254 /* Print the cpu name we're tuning for in the comments, might be
11255 useful to readers of the generated asm. */
11263 /* Don't forget the type directive for ELF. */
11266 }
11268 /* Emit load exclusive. */
11270 static void
11273 {
11277 {
11284 }
11287 }
11289 /* Emit store exclusive. */
11291 static void
11294 {
11298 {
11305 }
11308 }
11310 /* Mark the previous jump instruction as unlikely. */
11312 static void
11314 {
11319 }
11321 /* Expand a compare and swap pattern. */
11323 void
11325 {
11330 gen_cas_fn gen;
11332 {
11333 gen_aarch64_compare_and_swapqi,
11334 gen_aarch64_compare_and_swaphi,
11335 gen_aarch64_compare_and_swapsi,
11336 gen_aarch64_compare_and_swapdi
11337 };
11339 {
11340 gen_aarch64_compare_and_swapqi_lse,
11341 gen_aarch64_compare_and_swaphi_lse,
11342 gen_aarch64_compare_and_swapsi_lse,
11343 gen_aarch64_compare_and_swapdi_lse
11344 };
11357 /* Normally the succ memory model must be stronger than fail, but in the
11358 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11359 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11366 {
11369 /* For short modes, we're going to perform the comparison in SImode,
11370 so do the zero-extension now. */
11374 /* Fall through. */
11378 /* Force the value into a register if needed. */
11385 }
11388 {
11395 }
11398 else
11409 }
11411 /* Test whether the target supports using a atomic load-operate instruction.
11412 CODE is the operation and AFTER is TRUE if the data in memory after the
11413 operation should be returned and FALSE if the data before the operation
11414 should be returned. Returns FALSE if the operation isn't supported by the
11415 architecture. */
11417 bool
11419 {
11424 {
11434 }
11435 }
11437 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11438 sequence implementing an atomic operation. */
11440 static void
11442 {
11449 {
11451 }
11452 }
11454 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11455 for the data in memory. EXPECTED is the value expected to be in memory.
11456 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11457 is the memory ordering to use. */
11459 void
11462 rtx model)
11463 {
11465 machine_mode mode;
11470 {
11477 }
11479 /* Move the expected value into the CAS destination register. */
11482 /* Emit the CAS. */
11485 /* Compare the expected value with the value loaded by the CAS, to establish
11486 whether the swap was made. */
11488 }
11490 /* Split a compare and swap pattern. */
11492 void
11494 {
11496 machine_mode mode;
11501 rtx model_rtx;
11515 {
11518 }
11521 /* The initial load can be relaxed for a __sync operation since a final
11522 barrier will be emitted to stop code hoisting. */
11526 else
11538 {
11543 }
11544 else
11545 {
11549 }
11553 /* Emit any final barrier needed for a __sync operation. */
11556 }
11558 /* Emit a BIC instruction. */
11560 static void
11562 {
11567 {
11572 }
11575 }
11577 /* Emit an atomic swap. */
11579 static void
11582 {
11586 {
11593 }
11596 }
11598 /* Operations supported by aarch64_emit_atomic_load_op. */
11600 enum aarch64_atomic_load_op_code
11601 {
11605 AARCH64_LDOP_BIC /* A & ~B */
11606 };
11608 /* Emit an atomic load-operate. */
11610 static void
11614 {
11617 {
11618 gen_aarch64_atomic_loadaddqi,
11619 gen_aarch64_atomic_loadaddhi,
11620 gen_aarch64_atomic_loadaddsi,
11621 gen_aarch64_atomic_loadadddi
11622 };
11624 {
11625 gen_aarch64_atomic_loadeorqi,
11626 gen_aarch64_atomic_loadeorhi,
11627 gen_aarch64_atomic_loadeorsi,
11628 gen_aarch64_atomic_loadeordi
11629 };
11631 {
11632 gen_aarch64_atomic_loadsetqi,
11633 gen_aarch64_atomic_loadsethi,
11634 gen_aarch64_atomic_loadsetsi,
11635 gen_aarch64_atomic_loadsetdi
11636 };
11638 {
11639 gen_aarch64_atomic_loadclrqi,
11640 gen_aarch64_atomic_loadclrhi,
11641 gen_aarch64_atomic_loadclrsi,
11642 gen_aarch64_atomic_loadclrdi
11643 };
11644 aarch64_atomic_load_op_fn gen;
11648 {
11655 }
11658 {
11665 }
11668 }
11670 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
11671 location to store the data read from memory. OUT_RESULT is the location to
11672 store the result of the operation. MEM is the memory location to read and
11673 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
11674 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
11675 be NULL. */
11677 void
11680 {
11684 aarch64_atomic_load_op_code ldop_code;
11685 rtx src;
11686 rtx x;
11694 /* Make sure the value is in a register, putting it into a destination
11695 register if it needs to be manipulated. */
11698 {
11701 }
11702 else
11706 /* Preprocess the data for the operation as necessary. If the operation is
11707 a SET then emit a swap instruction and finish. */
11709 {
11715 /* Negate the value and treat it as a PLUS. */
11716 {
11717 rtx neg_src;
11719 /* Resize the value if necessary. */
11728 }
11729 /* Fall-through. */
11743 {
11744 rtx not_src;
11746 /* Resize the value if necessary. */
11755 }
11760 /* The operation can't be done with atomic instructions. */
11762 }
11766 /* If necessary, calculate the data in memory after the update by redoing the
11767 operation from values in registers. */
11772 {
11776 }
11781 {
11797 }
11802 }
11804 /* Split an atomic operation. */
11806 void
11809 {
11815 rtx x;
11817 /* Split the atomic operation into a sequence. */
11825 else
11829 /* The initial load can be relaxed for a __sync operation since a final
11830 barrier will be emitted to stop code hoisting. */
11834 else
11838 {
11852 {
11855 }
11856 /* Fall through. */
11862 }
11872 /* Emit any final barrier needed for a __sync operation. */
11875 }
11877 static void
11879 {
11880 /* Half-precision float operations. The compiler handles all operations
11881 with NULL libfuncs by converting to SFmode. */
11883 /* Conversions. */
11887 /* Arithmetic. */
11894 /* Comparisons. */
11902 }
11904 /* Target hook for c_mode_for_suffix. */
11905 static machine_mode
11907 {
11912 }
11914 /* We can only represent floating point constants which will fit in
11915 "quarter-precision" values. These values are characterised by
11916 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
11917 by:
11919 (-1)^s * (n/16) * 2^r
11921 Where:
11922 's' is the sign bit.
11923 'n' is an integer in the range 16 <= n <= 31.
11924 'r' is an integer in the range -3 <= r <= 4. */
11926 /* Return true iff X can be represented by a quarter-precision
11927 floating point immediate operand X. Note, we cannot represent 0.0. */
11928 bool
11930 {
11931 /* This represents our current view of how many bits
11932 make up the mantissa. */
11942 /* We don't support HFmode constants yet. */
11948 /* We cannot represent infinities, NaNs or +/-zero. We won't
11949 know if we have +zero until we analyse the mantissa, but we
11950 can reject the other invalid values. */
11955 /* Extract exponent. */
11959 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
11960 highest (sign) bit, with a fixed binary point at bit point_pos.
11961 m1 holds the low part of the mantissa, m2 the high part.
11962 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
11963 bits for the mantissa, this can fail (low bits will be lost). */
11967 /* If the low part of the mantissa has bits set we cannot represent
11968 the value. */
11971 /* We have rejected the lower HOST_WIDE_INT, so update our
11972 understanding of how many bits lie in the mantissa and
11973 look only at the high HOST_WIDE_INT. */
11977 /* We can only represent values with a mantissa of the form 1.xxxx. */
11982 /* Having filtered unrepresentable values, we may now remove all
11983 but the highest 5 bits. */
11986 /* We cannot represent the value 0.0, so reject it. This is handled
11987 elsewhere. */
11991 /* Then, as bit 4 is always set, we can mask it off, leaving
11992 the mantissa in the range [0, 15]. */
11996 /* GCC internally does not use IEEE754-like encoding (where normalized
11997 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
11998 Our mantissa values are shifted 4 places to the left relative to
11999 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12000 by 5 places to correct for GCC's representation. */
12004 }
12008 machine_mode mode,
12010 {
12020 /* This will return true to show const_vector is legal for use as either
12021 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12022 also update INFO to show how the immediate should be generated. */
12031 {
12033 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12034 move immediate path. */
12037 else
12038 {
12039 #define buf_size 20
12044 #undef buf_size
12048 else
12052 }
12053 }
12066 else
12070 }
12074 machine_mode mode)
12075 {
12076 machine_mode vmode;
12082 }
12084 /* Split operands into moves from op[1] + op[2] into op[0]. */
12086 void
12088 {
12099 {
12100 /* No-op move. Can't split to nothing; emit something. */
12103 }
12105 /* Preserve register attributes for variable tracking. */
12110 /* Special case of reversed high/low parts. */
12113 {
12117 }
12119 {
12120 /* Try to avoid unnecessary moves if part of the result
12121 is in the right place already. */
12126 }
12127 else
12128 {
12133 }
12134 }
12136 /* vec_perm support. */
12138 #define MAX_VECT_LEN 16
12140 struct expand_vec_perm_d
12141 {
12144 machine_mode vmode;
12148 };
12150 /* Generate a variable permutation. */
12152 static void
12154 {
12165 {
12167 {
12168 /* Expand the argument to a V16QI mode by duplicating it. */
12172 }
12173 else
12174 {
12176 }
12177 }
12178 else
12179 {
12180 rtx pair;
12183 {
12187 }
12188 else
12189 {
12193 }
12194 }
12195 }
12197 void
12199 {
12203 rtx mask;
12205 /* The TBL instruction does not use a modulo index, so we must take care
12206 of that ourselves. */
12211 /* For big-endian, we also need to reverse the index within the vector
12212 (but not which vector). */
12214 {
12215 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12220 }
12222 }
12224 /* Recognize patterns suitable for the TRN instructions. */
12225 static bool
12227 {
12236 /* Note that these are little-endian tests.
12237 We correct for big-endian later. */
12242 else
12247 {
12252 }
12254 /* Success! */
12261 {
12264 }
12268 {
12270 {
12283 }
12284 }
12285 else
12286 {
12288 {
12301 }
12302 }
12306 }
12308 /* Recognize patterns suitable for the UZP instructions. */
12309 static bool
12311 {
12320 /* Note that these are little-endian tests.
12321 We correct for big-endian later. */
12326 else
12331 {
12335 }
12337 /* Success! */
12344 {
12347 }
12351 {
12353 {
12366 }
12367 }
12368 else
12369 {
12371 {
12384 }
12385 }
12389 }
12391 /* Recognize patterns suitable for the ZIP instructions. */
12392 static bool
12394 {
12403 /* Note that these are little-endian tests.
12404 We correct for big-endian later. */
12407 /* Do Nothing. */
12408 ;
12411 else
12416 {
12423 }
12425 /* Success! */
12432 {
12435 }
12439 {
12441 {
12454 }
12455 }
12456 else
12457 {
12459 {
12472 }
12473 }
12477 }
12479 /* Recognize patterns for the EXT insn. */
12481 static bool
12483 {
12486 rtx offset;
12490 /* Check if the extracted indices are increasing by one. */
12492 {
12495 {
12496 /* We'll pass the same vector in twice, so allow indices to wrap. */
12498 }
12501 }
12504 {
12517 }
12519 /* Success! */
12523 /* The case where (location == 0) is a no-op for both big- and little-endian,
12524 and is removed by the mid-end at optimization levels -O1 and higher. */
12527 {
12528 /* After setup, we want the high elements of the first vector (stored
12529 at the LSB end of the register), and the low elements of the second
12530 vector (stored at the MSB end of the register). So swap. */
12532 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
12534 }
12539 }
12541 /* Recognize patterns for the REV insns. */
12543 static bool
12545 {
12554 {
12557 {
12562 }
12566 {
12573 }
12577 {
12588 }
12592 }
12596 {
12597 /* This is guaranteed to be true as the value of diff
12598 is 7, 3, 1 and we should have enough elements in the
12599 queue to generate this. Getting a vector mask with a
12600 value of diff other than these values implies that
12601 something is wrong by the time we get here. */
12605 }
12607 /* Success! */
12613 }
12615 static bool
12617 {
12620 rtx in0;
12623 rtx lane;
12627 {
12630 }
12632 /* The generic preparation in aarch64_expand_vec_perm_const_1
12633 swaps the operand order and the permute indices if it finds
12634 d->perm[0] to be in the second operand. Thus, we can always
12635 use d->op0 and need not do any extra arithmetic to get the
12636 correct lane number. */
12641 {
12656 }
12660 }
12662 static bool
12664 {
12672 /* Generic code will try constant permutation twice. Once with the
12673 original mode and again with the elements lowered to QImode.
12674 So wait and don't do the selector expansion ourselves. */
12679 {
12682 /* If big-endian and two vectors we end up with a weird mixed-endian
12683 mode on NEON. Reverse the index within each word but not the word
12684 itself. */
12687 }
12693 }
12695 static bool
12697 {
12698 /* The pattern matching functions above are written to look for a small
12699 number to begin the sequence (0, 1, N/2). If we begin with an index
12700 from the second operand, we can swap the operands. */
12702 {
12710 }
12713 {
12727 }
12729 }
12731 /* Expand a vec_perm_const pattern. */
12733 bool
12735 {
12749 {
12754 }
12757 {
12766 /* The elements of PERM do not suggest that only the first operand
12767 is used, but both operands are identical. Allow easier matching
12768 of the permutation by folding the permutation into the single
12769 input vector. */
12770 /* Fall Through. */
12782 }
12785 }
12787 static bool
12790 {
12800 /* Calculate whether all elements are in one vector. */
12802 {
12806 }
12808 /* If all elements are from the second vector, reindex as if from the
12809 first vector. */
12814 /* Check whether the mask can be applied to a single vector. */
12827 }
12829 /* Implement target hook CANNOT_CHANGE_MODE_CLASS. */
12830 bool
12832 machine_mode to,
12834 {
12835 /* We cannot allow word_mode subregs of full vector modes.
12836 Otherwise the middle-end will assume it's ok to store to
12837 (subreg:DI (reg:TI 100) 0) in order to modify only the low 64 bits
12838 of the 128-bit register. However, after reload the subreg will
12839 be dropped leaving a plain DImode store. See PR67609 for a more
12840 detailed dicussion. In all other cases, we want to be permissive
12841 and return false. */
12845 }
12847 rtx
12849 {
12850 /* We have to reverse each vector because we dont have
12851 a permuted load that can reverse-load according to ABI rules. */
12852 rtx mask;
12866 }
12868 /* Implement MODES_TIEABLE_P. */
12870 bool
12872 {
12876 /* We specifically want to allow elements of "structure" modes to
12877 be tieable to the structure. This more general condition allows
12878 other rarer situations too. */
12885 }
12887 /* Return a new RTX holding the result of moving POINTER forward by
12888 AMOUNT bytes. */
12890 static rtx
12892 {
12897 }
12899 /* Return a new RTX holding the result of moving POINTER forward by the
12900 size of the mode it points to. */
12902 static rtx
12904 {
12908 }
12910 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
12911 MODE bytes. */
12913 static void
12915 machine_mode mode)
12916 {
12919 /* "Cast" the pointers to the correct mode. */
12922 /* Emit the memcpy. */
12925 /* Move the pointers forward. */
12928 }
12930 /* Expand movmem, as if from a __builtin_memcpy. Return true if
12931 we succeed, otherwise return false. */
12933 bool
12935 {
12939 rtx base;
12942 /* When optimizing for size, give a better estimate of the length of a
12943 memcpy call, but use the default otherwise. */
12946 /* We can't do anything smart if the amount to copy is not constant. */
12952 /* Try to keep the number of instructions low. For cases below 16 bytes we
12953 need to make at most two moves. For cases above 16 bytes it will be one
12954 move for each 16 byte chunk, then at most two additional moves. */
12964 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
12965 1-byte chunk. */
12967 {
12969 {
12972 }
12978 }
12980 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
12981 4-byte chunk, partially overlapping with the previously copied chunk. */
12983 {
12987 {
12993 }
12995 }
12997 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
12998 them, then (if applicable) an 8-byte chunk. */
13000 {
13002 {
13005 }
13006 else
13007 {
13010 }
13011 }
13013 /* Finish the final bytes of the copy. We can always do this in one
13014 instruction. We either copy the exact amount we need, or partially
13015 overlap with the previous chunk we copied and copy 8-bytes. */
13024 else
13025 {
13027 {
13031 }
13032 else
13033 {
13039 }
13040 }
13043 }
13045 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13047 static unsigned HOST_WIDE_INT
13049 {
13051 }
13053 static bool
13058 {
13059 /* STORE_BY_PIECES can be used when copying a constant string, but
13060 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13061 For now we always fail this and let the move_by_pieces code copy
13062 the string from read-only memory. */
13067 }
13069 static enum machine_mode
13071 {
13073 {
13106 }
13107 }
13109 static rtx
13112 {
13131 {
13147 }
13152 {
13155 }
13169 {
13172 }
13177 }
13179 static rtx
13182 {
13201 {
13219 }
13224 {
13227 }
13244 {
13247 }
13253 }
13255 #undef TARGET_GEN_CCMP_FIRST
13256 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13258 #undef TARGET_GEN_CCMP_NEXT
13259 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13261 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13262 instruction fusion of some sort. */
13264 static bool
13266 {
13268 }
13271 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13272 should be kept together during scheduling. */
13274 static bool
13276 {
13277 rtx set_dest;
13280 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13288 {
13289 /* We are trying to match:
13290 prev (mov) == (set (reg r0) (const_int imm16))
13291 curr (movk) == (set (zero_extract (reg r0)
13292 (const_int 16)
13293 (const_int 16))
13294 (const_int imm16_1)) */
13306 {
13308 }
13309 }
13313 {
13315 /* We're trying to match:
13316 prev (adrp) == (set (reg r1)
13317 (high (symbol_ref ("SYM"))))
13318 curr (add) == (set (reg r0)
13319 (lo_sum (reg r1)
13320 (symbol_ref ("SYM"))))
13321 Note that r0 need not necessarily be the same as r1, especially
13322 during pre-regalloc scheduling. */
13326 {
13334 }
13335 }
13339 {
13341 /* We're trying to match:
13342 prev (movk) == (set (zero_extract (reg r0)
13343 (const_int 16)
13344 (const_int 32))
13345 (const_int imm16_1))
13346 curr (movk) == (set (zero_extract (reg r0)
13347 (const_int 16)
13348 (const_int 48))
13349 (const_int imm16_2)) */
13365 }
13368 {
13369 /* We're trying to match:
13370 prev (adrp) == (set (reg r0)
13371 (high (symbol_ref ("SYM"))))
13372 curr (ldr) == (set (reg r1)
13373 (mem (lo_sum (reg r0)
13374 (symbol_ref ("SYM")))))
13375 or
13376 curr (ldr) == (set (reg r1)
13377 (zero_extend (mem
13378 (lo_sum (reg r0)
13379 (symbol_ref ("SYM")))))) */
13382 {
13395 }
13396 }
13400 {
13403 /* FIXME: this misses some which is considered simple arthematic
13404 instructions for ThunderX. Simple shifts are missed here. */
13410 }
13413 }
13415 /* If MEM is in the form of [base+offset], extract the two parts
13416 of address and set to BASE and OFFSET, otherwise return false
13417 after clearing BASE and OFFSET. */
13419 bool
13421 {
13422 rtx addr;
13429 {
13433 }
13437 {
13441 }
13447 }
13449 /* Types for scheduling fusion. */
13450 enum sched_fusion_type
13451 {
13453 SCHED_FUSION_LD_SIGN_EXTEND,
13454 SCHED_FUSION_LD_ZERO_EXTEND,
13455 SCHED_FUSION_LD,
13456 SCHED_FUSION_ST,
13457 SCHED_FUSION_NUM
13458 };
13460 /* If INSN is a load or store of address in the form of [base+offset],
13461 extract the two parts and set to BASE and OFFSET. Return scheduling
13462 fusion type this INSN is. */
13464 static enum sched_fusion_type
13466 {
13484 {
13489 }
13491 {
13496 }
13501 {
13504 }
13505 else
13512 }
13514 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
13516 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
13517 and PRI are only calculated for these instructions. For other instruction,
13518 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
13519 type instruction fusion can be added by returning different priorities.
13521 It's important that irrelevant instructions get the largest FUSION_PRI. */
13523 static void
13526 {
13536 {
13540 }
13542 /* Set FUSION_PRI according to fusion type and base register. */
13545 /* Calculate PRI. */
13548 /* INSN with smaller offset goes first. */
13552 else
13557 }
13559 /* Given OPERANDS of consecutive load/store, check if we can merge
13560 them into ldp/stp. LOAD is true if they are load instructions.
13561 MODE is the mode of memory operands. */
13563 bool
13566 {
13572 {
13580 }
13581 else
13582 {
13587 }
13589 /* The mems cannot be volatile. */
13593 /* Check if the addresses are in the form of [base+offset]. */
13601 /* Check if the bases are same. */
13608 /* Check if the offsets are consecutive. */
13612 /* Check if the addresses are clobbered by load. */
13614 {
13618 /* In increasing order, the last load can clobber the address. */
13621 }
13625 else
13630 else
13633 /* Check if the registers are of same class. */
13638 }
13640 /* Given OPERANDS of consecutive load/store, check if we can merge
13641 them into ldp/stp by adjusting the offset. LOAD is true if they
13642 are load instructions. MODE is the mode of memory operands.
13644 Given below consecutive stores:
13646 str w1, [xb, 0x100]
13647 str w1, [xb, 0x104]
13648 str w1, [xb, 0x108]
13649 str w1, [xb, 0x10c]
13651 Though the offsets are out of the range supported by stp, we can
13652 still pair them after adjusting the offset, like:
13654 add scratch, xb, 0x100
13655 stp w1, w1, [scratch]
13656 stp w1, w1, [scratch, 0x8]
13658 The peephole patterns detecting this opportunity should guarantee
13659 the scratch register is avaliable. */
13661 bool
13664 {
13671 {
13684 }
13685 else
13686 {
13695 }
13696 /* Skip if memory operand is by itslef valid for ldp/stp. */
13700 /* The mems cannot be volatile. */
13705 /* Check if the addresses are in the form of [base+offset]. */
13719 /* Check if the bases are same. */
13730 /* Check if the offsets are consecutive. */
13739 /* Check if the addresses are clobbered by load. */
13741 {
13747 /* In increasing order, the last load can clobber the address. */
13750 }
13754 else
13759 else
13764 else
13769 else
13772 /* Check if the registers are of same class. */
13777 }
13779 /* Given OPERANDS of consecutive load/store, this function pairs them
13780 into ldp/stp after adjusting the offset. It depends on the fact
13781 that addresses of load/store instructions are in increasing order.
13782 MODE is the mode of memory operands. CODE is the rtl operator
13783 which should be applied to all memory operands, it's SIGN_EXTEND,
13784 ZERO_EXTEND or UNKNOWN. */
13786 bool
13789 {
13795 {
13800 }
13801 else
13802 {
13808 }
13813 /* Adjust offset thus it can fit in ldp/stp instruction. */
13821 /* Further adjust to make sure all offsets are OK. */
13823 {
13826 }
13828 /* Make sure the adjustment can be done with ADD/SUB instructions. */
13833 {
13836 }
13838 /* Create new memory references. */
13842 /* Check if the adjusted address is OK for ldp/stp. */
13861 {
13866 }
13868 {
13873 }
13876 {
13881 }
13882 else
13883 {
13888 }
13890 /* Emit adjusting instruction. */
13892 /* Emit ldp/stp instructions. */
13900 }
13902 /* Return 1 if pseudo register should be created and used to hold
13903 GOT address for PIC code. */
13905 bool
13907 {
13909 }
13911 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
13913 static int
13915 {
13917 {
13924 }
13927 }
13930 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
13931 return the log2 of that value. Otherwise return -1. */
13933 int
13935 {
13950 }
13952 /* If X is a vector of equal CONST_DOUBLE values and that value is
13953 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
13955 int
13957 {
13973 }
13975 /* Implement TARGET_PROMOTED_TYPE to promote __fp16 to float. */
13976 static tree
13978 {
13982 }
13984 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
13986 static bool
13988 optimization_type opt_type)
13989 {
13991 {
13997 }
13998 }
14000 #undef TARGET_ADDRESS_COST
14001 #define TARGET_ADDRESS_COST aarch64_address_cost
14003 /* This hook will determines whether unnamed bitfields affect the alignment
14004 of the containing structure. The hook returns true if the structure
14005 should inherit the alignment requirements of an unnamed bitfield's
14006 type. */
14007 #undef TARGET_ALIGN_ANON_BITFIELD
14008 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14010 #undef TARGET_ASM_ALIGNED_DI_OP
14013 #undef TARGET_ASM_ALIGNED_HI_OP
14016 #undef TARGET_ASM_ALIGNED_SI_OP
14019 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14020 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14021 hook_bool_const_tree_hwi_hwi_const_tree_true
14023 #undef TARGET_ASM_OUTPUT_MI_THUNK
14024 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14026 #undef TARGET_ASM_SELECT_RTX_SECTION
14027 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14029 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14030 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14032 #undef TARGET_BUILD_BUILTIN_VA_LIST
14033 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14035 #undef TARGET_CALLEE_COPIES
14036 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14038 #undef TARGET_CAN_ELIMINATE
14039 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14041 #undef TARGET_CAN_INLINE_P
14042 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14044 #undef TARGET_CANNOT_FORCE_CONST_MEM
14045 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14047 #undef TARGET_CASE_VALUES_THRESHOLD
14048 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14050 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14051 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14053 /* Only the least significant bit is used for initialization guard
14054 variables. */
14055 #undef TARGET_CXX_GUARD_MASK_BIT
14056 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14058 #undef TARGET_C_MODE_FOR_SUFFIX
14059 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14061 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14062 #undef TARGET_DEFAULT_TARGET_FLAGS
14063 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14064 #endif
14066 #undef TARGET_CLASS_MAX_NREGS
14067 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14069 #undef TARGET_BUILTIN_DECL
14070 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14072 #undef TARGET_BUILTIN_RECIPROCAL
14073 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14075 #undef TARGET_EXPAND_BUILTIN
14076 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14078 #undef TARGET_EXPAND_BUILTIN_VA_START
14079 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14081 #undef TARGET_FOLD_BUILTIN
14082 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14084 #undef TARGET_FUNCTION_ARG
14085 #define TARGET_FUNCTION_ARG aarch64_function_arg
14087 #undef TARGET_FUNCTION_ARG_ADVANCE
14088 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14090 #undef TARGET_FUNCTION_ARG_BOUNDARY
14091 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14093 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14094 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14096 #undef TARGET_FUNCTION_VALUE
14097 #define TARGET_FUNCTION_VALUE aarch64_function_value
14099 #undef TARGET_FUNCTION_VALUE_REGNO_P
14100 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14102 #undef TARGET_FRAME_POINTER_REQUIRED
14103 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14105 #undef TARGET_GIMPLE_FOLD_BUILTIN
14106 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14108 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14109 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14111 #undef TARGET_INIT_BUILTINS
14112 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14114 #undef TARGET_LEGITIMATE_ADDRESS_P
14115 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14117 #undef TARGET_LEGITIMATE_CONSTANT_P
14118 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14120 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14121 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14123 #undef TARGET_LRA_P
14124 #define TARGET_LRA_P hook_bool_void_true
14126 #undef TARGET_MANGLE_TYPE
14127 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14129 #undef TARGET_MEMORY_MOVE_COST
14130 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14132 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14133 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14135 #undef TARGET_MUST_PASS_IN_STACK
14136 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14138 /* This target hook should return true if accesses to volatile bitfields
14139 should use the narrowest mode possible. It should return false if these
14140 accesses should use the bitfield container type. */
14141 #undef TARGET_NARROW_VOLATILE_BITFIELD
14142 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14144 #undef TARGET_OPTION_OVERRIDE
14145 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14147 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14148 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14149 aarch64_override_options_after_change
14151 #undef TARGET_OPTION_SAVE
14152 #define TARGET_OPTION_SAVE aarch64_option_save
14154 #undef TARGET_OPTION_RESTORE
14155 #define TARGET_OPTION_RESTORE aarch64_option_restore
14157 #undef TARGET_OPTION_PRINT
14158 #define TARGET_OPTION_PRINT aarch64_option_print
14160 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14161 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14163 #undef TARGET_SET_CURRENT_FUNCTION
14164 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14166 #undef TARGET_PASS_BY_REFERENCE
14167 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14169 #undef TARGET_PREFERRED_RELOAD_CLASS
14170 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14172 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14173 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14175 #undef TARGET_PROMOTED_TYPE
14176 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14178 #undef TARGET_SECONDARY_RELOAD
14179 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14181 #undef TARGET_SHIFT_TRUNCATION_MASK
14182 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14184 #undef TARGET_SETUP_INCOMING_VARARGS
14185 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14187 #undef TARGET_STRUCT_VALUE_RTX
14188 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14190 #undef TARGET_REGISTER_MOVE_COST
14191 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14193 #undef TARGET_RETURN_IN_MEMORY
14194 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14196 #undef TARGET_RETURN_IN_MSB
14197 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14199 #undef TARGET_RTX_COSTS
14200 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14202 #undef TARGET_SCHED_ISSUE_RATE
14203 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14205 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14206 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14207 aarch64_sched_first_cycle_multipass_dfa_lookahead
14209 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14210 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14211 aarch64_first_cycle_multipass_dfa_lookahead_guard
14213 #undef TARGET_TRAMPOLINE_INIT
14214 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14216 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14217 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14219 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14220 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14222 #undef TARGET_ARRAY_MODE_SUPPORTED_P
14223 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
14225 #undef TARGET_VECTORIZE_ADD_STMT_COST
14226 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
14228 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
14229 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
14230 aarch64_builtin_vectorization_cost
14232 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14233 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
14235 #undef TARGET_VECTORIZE_BUILTINS
14236 #define TARGET_VECTORIZE_BUILTINS
14238 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
14239 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
14240 aarch64_builtin_vectorized_function
14242 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
14243 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
14244 aarch64_autovectorize_vector_sizes
14246 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14247 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
14248 aarch64_atomic_assign_expand_fenv
14250 /* Section anchor support. */
14252 #undef TARGET_MIN_ANCHOR_OFFSET
14253 #define TARGET_MIN_ANCHOR_OFFSET -256
14255 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
14256 byte offset; we can do much more for larger data types, but have no way
14257 to determine the size of the access. We assume accesses are aligned. */
14258 #undef TARGET_MAX_ANCHOR_OFFSET
14259 #define TARGET_MAX_ANCHOR_OFFSET 4095
14261 #undef TARGET_VECTOR_ALIGNMENT
14262 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
14264 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
14265 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
14266 aarch64_simd_vector_alignment_reachable
14268 /* vec_perm support. */
14270 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
14271 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
14272 aarch64_vectorize_vec_perm_const_ok
14274 #undef TARGET_INIT_LIBFUNCS
14275 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
14277 #undef TARGET_FIXED_CONDITION_CODE_REGS
14278 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
14280 #undef TARGET_FLAGS_REGNUM
14281 #define TARGET_FLAGS_REGNUM CC_REGNUM
14283 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
14284 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
14286 #undef TARGET_ASAN_SHADOW_OFFSET
14287 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
14289 #undef TARGET_LEGITIMIZE_ADDRESS
14290 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
14292 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14293 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14294 aarch64_use_by_pieces_infrastructure_p
14296 #undef TARGET_CAN_USE_DOLOOP_P
14297 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
14299 #undef TARGET_SCHED_MACRO_FUSION_P
14300 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
14302 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
14303 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
14305 #undef TARGET_SCHED_FUSION_PRIORITY
14306 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
14308 #undef TARGET_UNSPEC_MAY_TRAP_P
14309 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
14311 #undef TARGET_USE_PSEUDO_PIC_REG
14312 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
14314 #undef TARGET_PRINT_OPERAND
14315 #define TARGET_PRINT_OPERAND aarch64_print_operand
14317 #undef TARGET_PRINT_OPERAND_ADDRESS
14318 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
14320 #undef TARGET_OPTAB_SUPPORTED_P
14321 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p