gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c

   1 /* { dg-do compile } */
   2 /* { dg-require-effective-target aarch64_small } */
   3 /* { dg-options "-O3 -mcpu=cortex-a57" } */
   4
   5 enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS,
   6                  XGRF_REGS, ALL_REGS, LIM_REG_CLASSES };
   7
   8 enum rtx_code { REG,  LAST_AND_UNUSED_RTX_CODE };
   9
  10 typedef union rtunion_def
  11 {
  12   int rtint;
  13 } rtunion;
  14
  15 typedef struct rtx_def
  16 {
  17   unsigned int volatil : 1;
  18   rtunion fld[1];
  19 } *rtx;
  20
  21 extern char fixed_regs[64];
  22 extern char global_regs[64];
  23
  24 int
  25 rtx_cost (rtx x, int outer_code)
  26 {
  27   register enum rtx_code code;
  28   switch (code)
  29     {
  30       case REG:
  31         return ! ((((x)->volatil) && ((x)->fld[0].rtint) < 64)
  32                  || ((((x)->fld[0].rtint)) == 30 || (((x)->fld[0].rtint)) == 30
  33                  || (((x)->fld[0].rtint)) == 31 || (((x)->fld[0].rtint)) == 0
  34                  || ((((x)->fld[0].rtint)) >= (64)
  35                      && (((x)->fld[0].rtint)) <= (((64)) + 3))
  36                  || ((((x)->fld[0].rtint)) < 64 && ((((x)->fld[0].rtint)) == 30
  37                  || (((x)->fld[0].rtint)) == 30 || fixed_regs[((x)->fld[0].rtint)]
  38                  || global_regs[((x)->fld[0].rtint)])
  39                     && ((((x)->fld[0].rtint))
  40                           ? ((((x)->fld[0].rtint) < 32)
  41                              ? GENERAL_REGS : XRF_REGS)
  42                           : AP_REG) != NO_REGS)));
  43     }
  44 }
  45
  46 /* { dg-final { scan-assembler "adrp\tx.*, fixed_regs\n\tadd\tx.*, x.*fixed_regs" } } */