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PR target/79569
[official-gcc.git] / gcc / common / config / i386 / i386-common.c
blob4185176495a2096a49ba305c5a411f1e96741458
1 /* IA-32 common hooks.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET OPTION_MASK_ISA_AVX512VPOPCNTDQ
84 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
85 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
86 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
87 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
88 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
89 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
90 #define OPTION_MASK_ISA_XSAVES_SET \
91 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE)
92 #define OPTION_MASK_ISA_XSAVEC_SET \
93 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
94 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
95
96 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
97 as -msse4.2. */
98 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
99
100 #define OPTION_MASK_ISA_SSE4A_SET \
101 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
102 #define OPTION_MASK_ISA_FMA4_SET \
103 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
104 | OPTION_MASK_ISA_AVX_SET)
105 #define OPTION_MASK_ISA_XOP_SET \
106 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
107 #define OPTION_MASK_ISA_LWP_SET \
108 OPTION_MASK_ISA_LWP
109
110 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
111 #define OPTION_MASK_ISA_AES_SET \
112 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
113 #define OPTION_MASK_ISA_SHA_SET \
114 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
115 #define OPTION_MASK_ISA_PCLMUL_SET \
116 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
117
118 #define OPTION_MASK_ISA_ABM_SET \
119 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
120
121 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
122 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
123 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
124 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
125 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
126 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
127 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
128 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
129 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
130 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
131
132 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
133 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
134 #define OPTION_MASK_ISA_F16C_SET \
135 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
136 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
137 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
138 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
139 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID
140
141 /* Define a set of ISAs which aren't available when a given ISA is
142 disabled. MMX and SSE ISAs are handled separately. */
143
144 #define OPTION_MASK_ISA_MMX_UNSET \
145 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
146 #define OPTION_MASK_ISA_3DNOW_UNSET \
147 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
148 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
149
150 #define OPTION_MASK_ISA_SSE_UNSET \
151 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
152 #define OPTION_MASK_ISA_SSE2_UNSET \
153 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
154 #define OPTION_MASK_ISA_SSE3_UNSET \
155 (OPTION_MASK_ISA_SSE3 \
156 | OPTION_MASK_ISA_SSSE3_UNSET \
157 | OPTION_MASK_ISA_SSE4A_UNSET )
158 #define OPTION_MASK_ISA_SSSE3_UNSET \
159 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
160 #define OPTION_MASK_ISA_SSE4_1_UNSET \
161 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
162 #define OPTION_MASK_ISA_SSE4_2_UNSET \
163 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
164 #define OPTION_MASK_ISA_AVX_UNSET \
165 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
166 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
167 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
168 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
169 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
170 #define OPTION_MASK_ISA_XSAVE_UNSET \
171 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET)
172 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
173 #define OPTION_MASK_ISA_AVX2_UNSET \
174 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
175 #define OPTION_MASK_ISA_AVX512F_UNSET \
176 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
177 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
178 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
179 | OPTION_MASK_ISA_AVX512VL_UNSET)
180 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
181 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
182 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
183 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
184 #define OPTION_MASK_ISA_AVX512BW_UNSET \
185 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
186 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
187 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
188 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
189 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
190 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
191 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
192 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
193 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
194 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
195 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
196 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
197 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
198 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
199 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
200 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
201 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
202 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
203 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
204 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID
205
206 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
207 as -mno-sse4.1. */
208 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
209
210 #define OPTION_MASK_ISA_SSE4A_UNSET \
211 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
212
213 #define OPTION_MASK_ISA_FMA4_UNSET \
214 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
215 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
216 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
217
218 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
219 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
220 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
221 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
222 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
223 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
224 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
225 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
226 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
227 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
228 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
229 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
230 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
231 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
232
233 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
234 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
235 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
236
237 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
238 (OPTION_MASK_ISA_MMX_UNSET \
239 | OPTION_MASK_ISA_SSE_UNSET \
240 | OPTION_MASK_ISA_MPX)
241
242 /* Implement TARGET_HANDLE_OPTION. */
243
244 bool
245 ix86_handle_option (struct gcc_options *opts,
246 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
247 const struct cl_decoded_option *decoded,
248 location_t loc)
249 {
250 size_t code = decoded->opt_index;
251 int value = decoded->value;
252
253 switch (code)
254 {
255 case OPT_mgeneral_regs_only:
256 if (value)
257 {
258 /* Disable MPX, MMX, SSE and x87 instructions if only
259 general registers are allowed. */
260 opts->x_ix86_isa_flags
261 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
262 opts->x_ix86_isa_flags_explicit
263 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
264
265 opts->x_target_flags &= ~MASK_80387;
266 }
267 else
268 gcc_unreachable ();
269 return true;
270
271 case OPT_mmmx:
272 if (value)
273 {
274 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
275 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
276 }
277 else
278 {
279 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
280 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
281 }
282 return true;
283
284 case OPT_m3dnow:
285 if (value)
286 {
287 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
288 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
289 }
290 else
291 {
292 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
293 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
294 }
295 return true;
296
297 case OPT_m3dnowa:
298 if (value)
299 {
300 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
301 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
302 }
303 else
304 {
305 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
306 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
307 }
308 return true;
309
310 case OPT_msse:
311 if (value)
312 {
313 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
314 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
315 }
316 else
317 {
318 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
319 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
320 }
321 return true;
322
323 case OPT_msse2:
324 if (value)
325 {
326 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
327 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
328 }
329 else
330 {
331 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
332 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
333 }
334 return true;
335
336 case OPT_msse3:
337 if (value)
338 {
339 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
340 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
341 }
342 else
343 {
344 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
345 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
346 }
347 return true;
348
349 case OPT_mssse3:
350 if (value)
351 {
352 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
353 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
354 }
355 else
356 {
357 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
358 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
359 }
360 return true;
361
362 case OPT_msse4_1:
363 if (value)
364 {
365 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
366 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
367 }
368 else
369 {
370 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
371 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
372 }
373 return true;
374
375 case OPT_msse4_2:
376 if (value)
377 {
378 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
379 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
380 }
381 else
382 {
383 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
384 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
385 }
386 return true;
387
388 case OPT_mavx:
389 if (value)
390 {
391 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
392 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
393 }
394 else
395 {
396 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
397 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
398 }
399 return true;
400
401 case OPT_mavx2:
402 if (value)
403 {
404 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
405 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
406 }
407 else
408 {
409 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
410 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
411 }
412 return true;
413
414 case OPT_mavx512f:
415 if (value)
416 {
417 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
418 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
419 }
420 else
421 {
422 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
423 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
424
425 /* Turn off additional isa flags. */
426 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
427 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
428 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
429 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
430 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
431 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
432 }
433 return true;
434
435 case OPT_mavx512cd:
436 if (value)
437 {
438 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
439 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
440 }
441 else
442 {
443 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
444 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
445 }
446 return true;
447
448 case OPT_mavx512pf:
449 if (value)
450 {
451 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
452 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
453 }
454 else
455 {
456 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
457 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
458 }
459 return true;
460
461 case OPT_mavx512er:
462 if (value)
463 {
464 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
465 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
466 }
467 else
468 {
469 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
470 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
471 }
472 return true;
473
474 case OPT_mrdpid:
475 if (value)
476 {
477 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET;
478 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET;
479 }
480 else
481 {
482 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET;
483 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET;
484 }
485 return true;
486
487 case OPT_mavx5124fmaps:
488 if (value)
489 {
490 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
491 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
492 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
493 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
494 }
495 else
496 {
497 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
498 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
499 }
500 return true;
501
502 case OPT_mavx5124vnniw:
503 if (value)
504 {
505 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
506 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
507 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
508 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
509 }
510 else
511 {
512 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
513 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
514 }
515 return true;
516
517 case OPT_mavx512vpopcntdq:
518 if (value)
519 {
520 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
521 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
522 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
523 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
524 }
525 else
526 {
527 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
528 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
529 }
530 return true;
531
532 case OPT_msgx:
533 if (value)
534 {
535 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET;
536 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET;
537 }
538 else
539 {
540 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET;
541 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET;
542 }
543 return true;
544
545 case OPT_mavx512dq:
546 if (value)
547 {
548 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
549 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
550 }
551 else
552 {
553 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
554 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
555 }
556 return true;
557
558 case OPT_mavx512bw:
559 if (value)
560 {
561 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
562 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
563 }
564 else
565 {
566 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
567 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
568 }
569 return true;
570
571 case OPT_mavx512vl:
572 if (value)
573 {
574 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
575 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
576 }
577 else
578 {
579 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
580 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
581 }
582 return true;
583
584 case OPT_mavx512ifma:
585 if (value)
586 {
587 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
588 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
589 }
590 else
591 {
592 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
593 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
594 }
595 return true;
596
597 case OPT_mavx512vbmi:
598 if (value)
599 {
600 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
601 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
602 }
603 else
604 {
605 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
606 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
607 }
608 return true;
609
610 case OPT_mfma:
611 if (value)
612 {
613 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
614 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
615 }
616 else
617 {
618 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
619 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
620 }
621 return true;
622
623 case OPT_mrtm:
624 if (value)
625 {
626 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
627 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
628 }
629 else
630 {
631 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
632 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
633 }
634 return true;
635
636 case OPT_msse4:
637 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
638 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
639 return true;
640
641 case OPT_mno_sse4:
642 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
643 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
644 return true;
645
646 case OPT_msse4a:
647 if (value)
648 {
649 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
650 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
651 }
652 else
653 {
654 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
655 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
656 }
657 return true;
658
659 case OPT_mfma4:
660 if (value)
661 {
662 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
663 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
664 }
665 else
666 {
667 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
668 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
669 }
670 return true;
671
672 case OPT_mxop:
673 if (value)
674 {
675 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
676 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
677 }
678 else
679 {
680 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
681 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
682 }
683 return true;
684
685 case OPT_mlwp:
686 if (value)
687 {
688 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
689 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
690 }
691 else
692 {
693 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
694 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
695 }
696 return true;
697
698 case OPT_mabm:
699 if (value)
700 {
701 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
702 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
703 }
704 else
705 {
706 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
707 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
708 }
709 return true;
710
711 case OPT_mbmi:
712 if (value)
713 {
714 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
715 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
716 }
717 else
718 {
719 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
720 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
721 }
722 return true;
723
724 case OPT_mbmi2:
725 if (value)
726 {
727 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
728 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
729 }
730 else
731 {
732 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
733 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
734 }
735 return true;
736
737 case OPT_mlzcnt:
738 if (value)
739 {
740 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
741 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
742 }
743 else
744 {
745 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
746 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
747 }
748 return true;
749
750 case OPT_mtbm:
751 if (value)
752 {
753 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
754 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
755 }
756 else
757 {
758 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
759 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
760 }
761 return true;
762
763 case OPT_mpopcnt:
764 if (value)
765 {
766 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
767 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
768 }
769 else
770 {
771 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
772 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
773 }
774 return true;
775
776 case OPT_msahf:
777 if (value)
778 {
779 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
780 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
781 }
782 else
783 {
784 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
785 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
786 }
787 return true;
788
789 case OPT_mcx16:
790 if (value)
791 {
792 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
793 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
794 }
795 else
796 {
797 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
798 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
799 }
800 return true;
801
802 case OPT_mmovbe:
803 if (value)
804 {
805 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
806 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
807 }
808 else
809 {
810 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
811 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
812 }
813 return true;
814
815 case OPT_mcrc32:
816 if (value)
817 {
818 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
819 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
820 }
821 else
822 {
823 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
824 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
825 }
826 return true;
827
828 case OPT_maes:
829 if (value)
830 {
831 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
832 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
833 }
834 else
835 {
836 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
837 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
838 }
839 return true;
840
841 case OPT_msha:
842 if (value)
843 {
844 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
845 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
846 }
847 else
848 {
849 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
850 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
851 }
852 return true;
853
854 case OPT_mpclmul:
855 if (value)
856 {
857 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
858 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
859 }
860 else
861 {
862 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
863 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
864 }
865 return true;
866
867 case OPT_mfsgsbase:
868 if (value)
869 {
870 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
871 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
872 }
873 else
874 {
875 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
876 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
877 }
878 return true;
879
880 case OPT_mrdrnd:
881 if (value)
882 {
883 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
884 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
885 }
886 else
887 {
888 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
889 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
890 }
891 return true;
892
893 case OPT_mf16c:
894 if (value)
895 {
896 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
897 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
898 }
899 else
900 {
901 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
902 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
903 }
904 return true;
905
906 case OPT_mfxsr:
907 if (value)
908 {
909 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
910 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
911 }
912 else
913 {
914 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
915 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
916 }
917 return true;
918
919 case OPT_mxsave:
920 if (value)
921 {
922 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
923 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
924 }
925 else
926 {
927 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
928 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
929 }
930 return true;
931
932 case OPT_mxsaveopt:
933 if (value)
934 {
935 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
936 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
937 }
938 else
939 {
940 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
941 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
942 }
943 return true;
944
945 case OPT_mxsavec:
946 if (value)
947 {
948 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
949 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
950 }
951 else
952 {
953 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
954 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
955 }
956 return true;
957
958 case OPT_mxsaves:
959 if (value)
960 {
961 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
962 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
963 }
964 else
965 {
966 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
967 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
968 }
969 return true;
970
971 case OPT_mrdseed:
972 if (value)
973 {
974 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
975 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
976 }
977 else
978 {
979 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
980 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
981 }
982 return true;
983
984 case OPT_mprfchw:
985 if (value)
986 {
987 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
988 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
989 }
990 else
991 {
992 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
993 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
994 }
995 return true;
996
997 case OPT_madx:
998 if (value)
999 {
1000 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1001 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1002 }
1003 else
1004 {
1005 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1006 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1007 }
1008 return true;
1009
1010 case OPT_mprefetchwt1:
1011 if (value)
1012 {
1013 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1014 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1015 }
1016 else
1017 {
1018 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1019 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1020 }
1021 return true;
1022
1023 case OPT_mclflushopt:
1024 if (value)
1025 {
1026 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1027 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1028 }
1029 else
1030 {
1031 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1032 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1033 }
1034 return true;
1035
1036 case OPT_mclwb:
1037 if (value)
1038 {
1039 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1040 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1041 }
1042 else
1043 {
1044 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1045 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1046 }
1047 return true;
1048
1049 case OPT_mmwaitx:
1050 if (value)
1051 {
1052 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX_SET;
1053 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MWAITX_SET;
1054 }
1055 else
1056 {
1057 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MWAITX_UNSET;
1058 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MWAITX_UNSET;
1059 }
1060 return true;
1061
1062 case OPT_mclzero:
1063 if (value)
1064 {
1065 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLZERO_SET;
1066 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLZERO_SET;
1067 }
1068 else
1069 {
1070 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLZERO_UNSET;
1071 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLZERO_UNSET;
1072 }
1073 return true;
1074
1075 case OPT_mpku:
1076 if (value)
1077 {
1078 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1079 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1080 }
1081 else
1082 {
1083 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1084 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1085 }
1086 return true;
1087
1088
1089 /* Comes from final.c -- no real reason to change it. */
1090 #define MAX_CODE_ALIGN 16
1091
1092 case OPT_malign_loops_:
1093 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops");
1094 if (value > MAX_CODE_ALIGN)
1095 error_at (loc, "-malign-loops=%d is not between 0 and %d",
1096 value, MAX_CODE_ALIGN);
1097 else
1098 opts->x_align_loops = 1 << value;
1099 return true;
1100
1101 case OPT_malign_jumps_:
1102 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps");
1103 if (value > MAX_CODE_ALIGN)
1104 error_at (loc, "-malign-jumps=%d is not between 0 and %d",
1105 value, MAX_CODE_ALIGN);
1106 else
1107 opts->x_align_jumps = 1 << value;
1108 return true;
1109
1110 case OPT_malign_functions_:
1111 warning_at (loc, 0,
1112 "-malign-functions is obsolete, use -falign-functions");
1113 if (value > MAX_CODE_ALIGN)
1114 error_at (loc, "-malign-functions=%d is not between 0 and %d",
1115 value, MAX_CODE_ALIGN);
1116 else
1117 opts->x_align_functions = 1 << value;
1118 return true;
1119
1120 case OPT_mbranch_cost_:
1121 if (value > 5)
1122 {
1123 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value);
1124 opts->x_ix86_branch_cost = 5;
1125 }
1126 return true;
1127
1128 default:
1129 return true;
1130 }
1131 }
1132
1133 static const struct default_options ix86_option_optimization_table[] =
1134 {
1135 /* Enable redundant extension instructions removal at -O2 and higher. */
1136 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1137 /* Enable function splitting at -O2 and higher. */
1138 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1139 /* The STC algorithm produces the smallest code at -Os, for x86. */
1140 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1141 REORDER_BLOCKS_ALGORITHM_STC },
1142 /* Turn off -fschedule-insns by default. It tends to make the
1143 problem with not enough registers even worse. */
1144 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1145
1146 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1147 SUBTARGET_OPTIMIZATION_OPTIONS,
1148 #endif
1149 { OPT_LEVELS_NONE, 0, NULL, 0 }
1150 };
1151
1152 /* Implement TARGET_OPTION_INIT_STRUCT. */
1153
1154 static void
1155 ix86_option_init_struct (struct gcc_options *opts)
1156 {
1157 if (TARGET_MACHO)
1158 /* The Darwin libraries never set errno, so we might as well
1159 avoid calling them when that's the only reason we would. */
1160 opts->x_flag_errno_math = 0;
1161
1162 opts->x_flag_pcc_struct_return = 2;
1163 opts->x_flag_asynchronous_unwind_tables = 2;
1164 }
1165
1166 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1167 field in the TCB, so they can not be used together. */
1168
1169 static bool
1170 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1171 struct gcc_options *opts ATTRIBUTE_UNUSED)
1172 {
1173 bool ret = true;
1174
1175 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1176 if (report)
1177 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1178 ret = false;
1179 #else
1180 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1181 {
1182 if (report)
1183 error ("%<-fsplit-stack%> requires "
1184 "assembler support for CFI directives");
1185 ret = false;
1186 }
1187 #endif
1188
1189 return ret;
1190 }
1191
1192 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1193
1194 static enum unwind_info_type
1195 i386_except_unwind_info (struct gcc_options *opts)
1196 {
1197 /* Honor the --enable-sjlj-exceptions configure switch. */
1198 #ifdef CONFIG_SJLJ_EXCEPTIONS
1199 if (CONFIG_SJLJ_EXCEPTIONS)
1200 return UI_SJLJ;
1201 #endif
1202
1203 /* On windows 64, prefer SEH exceptions over anything else. */
1204 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1205 return UI_SEH;
1206
1207 if (DWARF2_UNWIND_INFO)
1208 return UI_DWARF2;
1209
1210 return UI_SJLJ;
1211 }
1212
1213 #undef TARGET_EXCEPT_UNWIND_INFO
1214 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1215
1216 #undef TARGET_DEFAULT_TARGET_FLAGS
1217 #define TARGET_DEFAULT_TARGET_FLAGS \
1218 (TARGET_DEFAULT \
1219 | TARGET_SUBTARGET_DEFAULT \
1220 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1221
1222 #undef TARGET_HANDLE_OPTION
1223 #define TARGET_HANDLE_OPTION ix86_handle_option
1224
1225 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1226 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1227 #undef TARGET_OPTION_INIT_STRUCT
1228 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1229
1230 #undef TARGET_SUPPORTS_SPLIT_STACK
1231 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1232
1233 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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