1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "integrate.h"
54 #define FRV_INLINE inline
57 /* Information about a relocation unspec. SYMBOL is the relocation symbol
58 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
59 is the constant addend. */
66 /* Temporary register allocation support structure. */
67 typedef struct frv_tmp_reg_struct
69 HARD_REG_SET regs
; /* possible registers to allocate */
70 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
74 /* Register state information for VLIW re-packing phase. These values must fit
75 within an unsigned char. */
76 #define REGSTATE_DEAD 0x00 /* register is currently dead */
77 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
78 #define REGSTATE_LIVE 0x08 /* register is live */
79 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
80 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
81 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
82 #define REGSTATE_UNUSED 0x80 /* bit for hire */
83 #define REGSTATE_MASK 0xff /* mask for the bits to set */
85 /* conditional expression used */
86 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
88 /* The following is not sure in the reg_state bytes, so can have a larger value
90 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
92 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
100 /* Information required by frv_frame_access. */
103 /* This field is FRV_LOAD if registers are to be loaded from the stack and
104 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
105 the move is being done by the prologue code while FRV_LOAD implies it
106 is being done by the epilogue. */
107 enum frv_stack_op op
;
109 /* The base register to use when accessing the stack. This may be the
110 frame pointer, stack pointer, or a temporary. The choice of register
111 depends on which part of the frame is being accessed and how big the
115 /* The offset of BASE from the bottom of the current frame, in bytes. */
117 } frv_frame_accessor_t
;
119 /* Define the information needed to generate branch and scc insns. This is
120 stored from the compare operation. */
124 /* Conditional execution support gathered together in one structure. */
127 /* Linked list of insns to add if the conditional execution conversion was
128 successful. Each link points to an EXPR_LIST which points to the pattern
129 of the insn to add, and the insn to be inserted before. */
130 rtx added_insns_list
;
132 /* Identify which registers are safe to allocate for if conversions to
133 conditional execution. We keep the last allocated register in the
134 register classes between COND_EXEC statements. This will mean we allocate
135 different registers for each different COND_EXEC group if we can. This
136 might allow the scheduler to intermix two different COND_EXEC sections. */
137 frv_tmp_reg_t tmp_reg
;
139 /* For nested IFs, identify which CC registers are used outside of setting
140 via a compare isnsn, and using via a check insn. This will allow us to
141 know if we can rewrite the register to use a different register that will
142 be paired with the CR register controlling the nested IF-THEN blocks. */
143 HARD_REG_SET nested_cc_ok_rewrite
;
145 /* Temporary registers allocated to hold constants during conditional
147 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
149 /* Current number of temp registers available. */
150 int cur_scratch_regs
;
152 /* Number of nested conditional execution blocks. */
153 int num_nested_cond_exec
;
155 /* Map of insns that set up constants in scratch registers. */
156 bitmap scratch_insns_bitmap
;
158 /* Conditional execution test register (CC0..CC7). */
161 /* Conditional execution compare register that is paired with cr_reg, so that
162 nested compares can be done. The csubcc and caddcc instructions don't
163 have enough bits to specify both a CC register to be set and a CR register
164 to do the test on, so the same bit number is used for both. Needless to
165 say, this is rather inconvenient for GCC. */
168 /* Extra CR registers used for &&, ||. */
172 /* Previous CR used in nested if, to make sure we are dealing with the same
173 nested if as the previous statement. */
174 rtx last_nested_if_cr
;
178 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
180 /* Map register number to smallest register class. */
181 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
183 /* Map class letter into register class. */
184 enum reg_class reg_class_from_letter
[256];
186 /* Cached value of frv_stack_info. */
187 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
189 /* -mbranch-cost= support */
190 const char *frv_branch_cost_string
;
191 int frv_branch_cost_int
= DEFAULT_BRANCH_COST
;
194 const char *frv_cpu_string
; /* -mcpu= option */
195 frv_cpu_t frv_cpu_type
= CPU_TYPE
; /* value of -mcpu= */
197 /* -mcond-exec-insns= support */
198 const char *frv_condexec_insns_str
; /* -mcond-exec-insns= option */
199 int frv_condexec_insns
= DEFAULT_CONDEXEC_INSNS
; /* value of -mcond-exec-insns*/
201 /* -mcond-exec-temps= support */
202 const char *frv_condexec_temps_str
; /* -mcond-exec-temps= option */
203 int frv_condexec_temps
= DEFAULT_CONDEXEC_TEMPS
; /* value of -mcond-exec-temps*/
205 /* -msched-lookahead=n */
206 const char *frv_sched_lookahead_str
; /* -msched-lookahead=n */
207 int frv_sched_lookahead
= 4; /* -msched-lookahead=n */
209 /* Forward references */
210 static int frv_default_flags_for_cpu (void);
211 static int frv_string_begins_with (tree
, const char *);
212 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
213 static FRV_INLINE
bool frv_const_unspec_p (rtx
, struct frv_unspec
*);
214 static void frv_print_operand_memory_reference_reg
216 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
217 static int frv_print_operand_jump_hint (rtx
);
218 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
219 static rtx
single_set_pattern (rtx
);
220 static int frv_function_contains_far_jump (void);
221 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
225 static rtx
frv_frame_offset_rtx (int);
226 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
227 static rtx
frv_dwarf_store (rtx
, int);
228 static void frv_frame_insn (rtx
, rtx
);
229 static void frv_frame_access (frv_frame_accessor_t
*,
231 static void frv_frame_access_multi (frv_frame_accessor_t
*,
233 static void frv_frame_access_standard_regs (enum frv_stack_op
,
235 static struct machine_function
*frv_init_machine_status (void);
236 static int frv_legitimate_memory_operand (rtx
, enum machine_mode
, int);
237 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
238 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
239 static rtx
frv_read_argument (tree
*);
240 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
241 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
242 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
243 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
244 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
245 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
246 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
247 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
248 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
249 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
250 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
251 static rtx
frv_expand_mclracc_builtin (tree
);
252 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
253 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
254 static rtx
frv_expand_noargs_builtin (enum insn_code
);
255 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
256 static int frv_clear_registers_used (rtx
*, void *);
257 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
258 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
259 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
260 static void frv_registers_update (rtx
, unsigned char [],
262 static int frv_registers_used_p (rtx
, unsigned char [], int);
263 static int frv_registers_set_p (rtx
, unsigned char [], int);
264 static int frv_issue_rate (void);
265 static int frv_use_dfa_pipeline_interface (void);
266 static void frv_pack_insns (void);
267 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
268 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
269 static bool frv_assemble_integer (rtx
, unsigned, int);
270 static void frv_init_builtins (void);
271 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
272 static void frv_init_libfuncs (void);
273 static bool frv_in_small_data_p (tree
);
274 static void frv_asm_output_mi_thunk
275 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
276 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS
*,
279 static rtx
frv_expand_builtin_saveregs (void);
280 static bool frv_rtx_costs (rtx
, int, int, int*);
281 static void frv_asm_out_constructor (rtx
, int);
282 static void frv_asm_out_destructor (rtx
, int);
283 static bool frv_function_symbol_referenced_p (rtx
);
284 static bool frv_cannot_force_const_mem (rtx
);
285 static const char *unspec_got_name (int);
286 static void frv_output_const_unspec (FILE *,
287 const struct frv_unspec
*);
288 static bool frv_function_ok_for_sibcall (tree
, tree
);
289 static rtx
frv_struct_value_rtx (tree
, int);
291 /* Initialize the GCC target structure. */
292 #undef TARGET_ASM_FUNCTION_PROLOGUE
293 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
294 #undef TARGET_ASM_FUNCTION_EPILOGUE
295 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
296 #undef TARGET_ASM_INTEGER
297 #define TARGET_ASM_INTEGER frv_assemble_integer
298 #undef TARGET_INIT_BUILTINS
299 #define TARGET_INIT_BUILTINS frv_init_builtins
300 #undef TARGET_EXPAND_BUILTIN
301 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
302 #undef TARGET_INIT_LIBFUNCS
303 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
304 #undef TARGET_IN_SMALL_DATA_P
305 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
306 #undef TARGET_RTX_COSTS
307 #define TARGET_RTX_COSTS frv_rtx_costs
308 #undef TARGET_ASM_CONSTRUCTOR
309 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
310 #undef TARGET_ASM_DESTRUCTOR
311 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
313 #undef TARGET_ASM_OUTPUT_MI_THUNK
314 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
315 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
316 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
318 #undef TARGET_SCHED_ISSUE_RATE
319 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
320 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
321 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE frv_use_dfa_pipeline_interface
323 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
324 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
325 #undef TARGET_CANNOT_FORCE_CONST_MEM
326 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
328 #undef TARGET_STRUCT_VALUE_RTX
329 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
331 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
332 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
333 #undef TARGET_SETUP_INCOMING_VARARGS
334 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
336 struct gcc_target targetm
= TARGET_INITIALIZER
;
338 /* Any function call that satisfies the machine-independent
339 requirements is eligible on FR-V. */
342 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
343 tree exp ATTRIBUTE_UNUSED
)
348 /* Return true if SYMBOL is a small data symbol and relocation RELOC
349 can be used to access it directly in a load or store. */
351 static FRV_INLINE
bool
352 frv_small_data_reloc_p (rtx symbol
, int reloc
)
354 return (GET_CODE (symbol
) == SYMBOL_REF
355 && SYMBOL_REF_SMALL_P (symbol
)
356 && (!TARGET_FDPIC
|| flag_pic
== 1)
357 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
360 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
363 static FRV_INLINE
bool
364 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
366 if (GET_CODE (x
) == CONST
)
370 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
372 unspec
->offset
+= INTVAL (XEXP (x
, 1));
375 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
377 unspec
->symbol
= XVECEXP (x
, 0, 0);
378 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
380 if (unspec
->offset
== 0)
383 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
384 && unspec
->offset
> 0
385 && (unsigned HOST_WIDE_INT
) unspec
->offset
< g_switch_value
)
392 /* Decide whether we can force certain constants to memory. If we
393 decide we can't, the caller should be able to cope with it in
396 We never allow constants to be forced into memory for TARGET_FDPIC.
397 This is necessary for several reasons:
399 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
400 target-independent code will try to force them into the constant
401 pool, thus leading to infinite recursion.
403 2. We can never introduce new constant pool references during reload.
404 Any such reference would require use of the pseudo FDPIC register.
406 3. We can't represent a constant added to a function pointer (which is
407 not the same as a pointer to a function+constant).
409 4. In many cases, it's more efficient to calculate the constant in-line. */
412 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED
)
418 frv_default_flags_for_cpu (void)
420 switch (frv_cpu_type
)
422 case FRV_CPU_GENERIC
:
423 return MASK_DEFAULT_FRV
;
427 return MASK_DEFAULT_FR500
;
430 return MASK_DEFAULT_FR400
;
434 return MASK_DEFAULT_SIMPLE
;
439 /* Sometimes certain combinations of command options do not make
440 sense on a particular target machine. You can define a macro
441 `OVERRIDE_OPTIONS' to take account of this. This macro, if
442 defined, is executed once just after all the command options have
445 Don't use this macro to turn on various extra optimizations for
446 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
449 frv_override_options (void)
453 /* Set the cpu type. */
456 if (strcmp (frv_cpu_string
, "simple") == 0)
457 frv_cpu_type
= FRV_CPU_SIMPLE
;
459 else if (strcmp (frv_cpu_string
, "tomcat") == 0)
460 frv_cpu_type
= FRV_CPU_TOMCAT
;
462 else if (strncmp (frv_cpu_string
, "fr", sizeof ("fr")-1) != 0)
463 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
467 const char *p
= frv_cpu_string
+ sizeof ("fr") - 1;
468 if (strcmp (p
, "500") == 0)
469 frv_cpu_type
= FRV_CPU_FR500
;
471 else if (strcmp (p
, "400") == 0)
472 frv_cpu_type
= FRV_CPU_FR400
;
474 else if (strcmp (p
, "300") == 0)
475 frv_cpu_type
= FRV_CPU_FR300
;
477 else if (strcmp (p
, "v") == 0)
478 frv_cpu_type
= FRV_CPU_GENERIC
;
481 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
485 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
487 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
488 linker about linking pic and non-pic code. */
491 if (!flag_pic
) /* -fPIC */
494 if (! g_switch_set
) /* -G0 */
501 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
503 if (write_symbols
== DWARF_DEBUG
&& flag_pic
)
504 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
506 /* Change the branch cost value. */
507 if (frv_branch_cost_string
)
508 frv_branch_cost_int
= atoi (frv_branch_cost_string
);
510 /* Change the # of insns to be converted to conditional execution. */
511 if (frv_condexec_insns_str
)
512 frv_condexec_insns
= atoi (frv_condexec_insns_str
);
514 /* Change # of temporary registers used to hold integer constants. */
515 if (frv_condexec_temps_str
)
516 frv_condexec_temps
= atoi (frv_condexec_temps_str
);
518 /* Change scheduling look ahead. */
519 if (frv_sched_lookahead_str
)
520 frv_sched_lookahead
= atoi (frv_sched_lookahead_str
);
522 /* A C expression whose value is a register class containing hard
523 register REGNO. In general there is more than one such class;
524 choose a class which is "minimal", meaning that no smaller class
525 also contains the register. */
527 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
529 enum reg_class
class;
533 int gpr_reg
= regno
- GPR_FIRST
;
534 if ((gpr_reg
& 3) == 0)
537 else if ((gpr_reg
& 1) == 0)
544 else if (FPR_P (regno
))
546 int fpr_reg
= regno
- GPR_FIRST
;
547 if ((fpr_reg
& 3) == 0)
548 class = QUAD_FPR_REGS
;
550 else if ((fpr_reg
& 1) == 0)
557 else if (regno
== LR_REGNO
)
560 else if (regno
== LCR_REGNO
)
563 else if (ICC_P (regno
))
566 else if (FCC_P (regno
))
569 else if (ICR_P (regno
))
572 else if (FCR_P (regno
))
575 else if (ACC_P (regno
))
577 int r
= regno
- ACC_FIRST
;
579 class = QUAD_ACC_REGS
;
580 else if ((r
& 1) == 0)
581 class = EVEN_ACC_REGS
;
586 else if (ACCG_P (regno
))
592 regno_reg_class
[regno
] = class;
595 /* Check for small data option */
597 g_switch_value
= SDATA_DEFAULT_SIZE
;
599 /* A C expression which defines the machine-dependent operand
600 constraint letters for register classes. If CHAR is such a
601 letter, the value should be the register class corresponding to
602 it. Otherwise, the value should be `NO_REGS'. The register
603 letter `r', corresponding to class `GENERAL_REGS', will not be
604 passed to this macro; you do not need to handle it.
606 The following letters are unavailable, due to being used as
611 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
612 'Q', 'R', 'S', 'T', 'U'
614 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
616 for (i
= 0; i
< 256; i
++)
617 reg_class_from_letter
[i
] = NO_REGS
;
619 reg_class_from_letter
['a'] = ACC_REGS
;
620 reg_class_from_letter
['b'] = EVEN_ACC_REGS
;
621 reg_class_from_letter
['c'] = CC_REGS
;
622 reg_class_from_letter
['d'] = GPR_REGS
;
623 reg_class_from_letter
['e'] = EVEN_REGS
;
624 reg_class_from_letter
['f'] = FPR_REGS
;
625 reg_class_from_letter
['h'] = FEVEN_REGS
;
626 reg_class_from_letter
['l'] = LR_REG
;
627 reg_class_from_letter
['q'] = QUAD_REGS
;
628 reg_class_from_letter
['t'] = ICC_REGS
;
629 reg_class_from_letter
['u'] = FCC_REGS
;
630 reg_class_from_letter
['v'] = ICR_REGS
;
631 reg_class_from_letter
['w'] = FCR_REGS
;
632 reg_class_from_letter
['x'] = QUAD_FPR_REGS
;
633 reg_class_from_letter
['y'] = LCR_REG
;
634 reg_class_from_letter
['z'] = SPR_REGS
;
635 reg_class_from_letter
['A'] = QUAD_ACC_REGS
;
636 reg_class_from_letter
['B'] = ACCG_REGS
;
637 reg_class_from_letter
['C'] = CR_REGS
;
638 reg_class_from_letter
['W'] = FDPIC_CALL_REGS
; /* gp14+15 */
639 reg_class_from_letter
['Z'] = FDPIC_REGS
; /* gp15 */
641 /* There is no single unaligned SI op for PIC code. Sometimes we
642 need to use ".4byte" and sometimes we need to use ".picptr".
643 See frv_assemble_integer for details. */
644 if (flag_pic
|| TARGET_FDPIC
)
645 targetm
.asm_out
.unaligned_op
.si
= 0;
647 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
648 target_flags
|= MASK_LINKED_FP
;
650 init_machine_status
= frv_init_machine_status
;
654 /* Some machines may desire to change what optimizations are performed for
655 various optimization levels. This macro, if defined, is executed once just
656 after the optimization level is determined and before the remainder of the
657 command options have been parsed. Values set in this macro are used as the
658 default values for the other command line options.
660 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
661 `-O' is specified, and 0 if neither is specified.
663 SIZE is nonzero if `-Os' is specified, 0 otherwise.
665 You should not use this macro to change options that are not
666 machine-specific. These should uniformly selected by the same optimization
667 level on all supported machines. Use this macro to enable machbine-specific
670 *Do not examine `write_symbols' in this macro!* The debugging options are
671 *not supposed to alter the generated code. */
673 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
674 scheduling pass at the current time. */
676 frv_optimization_options (int level
, int size ATTRIBUTE_UNUSED
)
680 #ifdef DISABLE_SCHED2
681 flag_schedule_insns_after_reload
= 0;
690 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
693 frv_string_begins_with (tree name
, const char *prefix
)
695 int prefix_len
= strlen (prefix
);
697 /* Remember: NAME's length includes the null terminator. */
698 return (TREE_STRING_LENGTH (name
) > prefix_len
699 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
702 /* Zero or more C statements that may conditionally modify two variables
703 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
704 been initialized from the two preceding macros.
706 This is necessary in case the fixed or call-clobbered registers depend on
709 You need not define this macro if it has no work to do.
711 If the usage of an entire class of registers depends on the target flags,
712 you may indicate this to GCC by using this macro to modify `fixed_regs' and
713 `call_used_regs' to 1 for each of the registers in the classes which should
714 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
715 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
717 (However, if this class is not included in `GENERAL_REGS' and all of the
718 insn patterns whose constraints permit this class are controlled by target
719 switches, then GCC will automatically avoid using these registers when the
720 target switches are opposed to them.) */
723 frv_conditional_register_usage (void)
727 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
728 fixed_regs
[i
] = call_used_regs
[i
] = 1;
730 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
731 fixed_regs
[i
] = call_used_regs
[i
] = 1;
733 for (i
= ACC_FIRST
+ NUM_ACCS
; i
<= ACC_LAST
; i
++)
734 fixed_regs
[i
] = call_used_regs
[i
] = 1;
736 for (i
= ACCG_FIRST
+ NUM_ACCS
; i
<= ACCG_LAST
; i
++)
737 fixed_regs
[i
] = call_used_regs
[i
] = 1;
739 /* Reserve the registers used for conditional execution. At present, we need
740 1 ICC and 1 ICR register. */
741 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
742 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
746 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
747 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
748 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
749 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
753 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
754 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
757 /* If -fpic, SDA_BASE_REG is the PIC register. */
758 if (g_switch_value
== 0 && !flag_pic
)
759 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
762 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
768 * Compute the stack frame layout
771 * +---------------+-----------------------+-----------------------+
772 * |Register |type |caller-save/callee-save|
773 * +---------------+-----------------------+-----------------------+
774 * |GR0 |Zero register | - |
775 * |GR1 |Stack pointer(SP) | - |
776 * |GR2 |Frame pointer(FP) | - |
777 * |GR3 |Hidden parameter | caller save |
778 * |GR4-GR7 | - | caller save |
779 * |GR8-GR13 |Argument register | caller save |
780 * |GR14-GR15 | - | caller save |
781 * |GR16-GR31 | - | callee save |
782 * |GR32-GR47 | - | caller save |
783 * |GR48-GR63 | - | callee save |
784 * |FR0-FR15 | - | caller save |
785 * |FR16-FR31 | - | callee save |
786 * |FR32-FR47 | - | caller save |
787 * |FR48-FR63 | - | callee save |
788 * +---------------+-----------------------+-----------------------+
792 * SP-> |-----------------------------------|
794 * |-----------------------------------|
795 * | Register save area |
796 * |-----------------------------------|
797 * | Local variable save area |
798 * FP-> |-----------------------------------|
800 * |-----------------------------------|
801 * | Hidden parameter save area |
802 * |-----------------------------------|
803 * | Return address(LR) storage area |
804 * |-----------------------------------|
805 * | Padding for alignment |
806 * |-----------------------------------|
807 * | Register argument area |
808 * OLD SP-> |-----------------------------------|
810 * |-----------------------------------|
813 * Argument area/Parameter area:
815 * When a function is called, this area is used for argument transfer. When
816 * the argument is set up by the caller function, this area is referred to as
817 * the argument area. When the argument is referenced by the callee function,
818 * this area is referred to as the parameter area. The area is allocated when
819 * all arguments cannot be placed on the argument register at the time of
822 * Register save area:
824 * This is a register save area that must be guaranteed for the caller
825 * function. This area is not secured when the register save operation is not
828 * Local variable save area:
830 * This is the area for local variables and temporary variables.
834 * This area stores the FP value of the caller function.
836 * Hidden parameter save area:
838 * This area stores the start address of the return value storage
839 * area for a struct/union return function.
840 * When a struct/union is used as the return value, the caller
841 * function stores the return value storage area start address in
842 * register GR3 and passes it to the caller function.
843 * The callee function interprets the address stored in the GR3
844 * as the return value storage area start address.
845 * When register GR3 needs to be saved into memory, the callee
846 * function saves it in the hidden parameter save area. This
847 * area is not secured when the save operation is not needed.
849 * Return address(LR) storage area:
851 * This area saves the LR. The LR stores the address of a return to the caller
852 * function for the purpose of function calling.
854 * Argument register area:
856 * This area saves the argument register. This area is not secured when the
857 * save operation is not needed.
861 * Arguments, the count of which equals the count of argument registers (6
862 * words), are positioned in registers GR8 to GR13 and delivered to the callee
863 * function. When a struct/union return function is called, the return value
864 * area address is stored in register GR3. Arguments not placed in the
865 * argument registers will be stored in the stack argument area for transfer
866 * purposes. When an 8-byte type argument is to be delivered using registers,
867 * it is divided into two and placed in two registers for transfer. When
868 * argument registers must be saved to memory, the callee function secures an
869 * argument register save area in the stack. In this case, a continuous
870 * argument register save area must be established in the parameter area. The
871 * argument register save area must be allocated as needed to cover the size of
872 * the argument register to be saved. If the function has a variable count of
873 * arguments, it saves all argument registers in the argument register save
876 * Argument Extension Format:
878 * When an argument is to be stored in the stack, its type is converted to an
879 * extended type in accordance with the individual argument type. The argument
880 * is freed by the caller function after the return from the callee function is
883 * +-----------------------+---------------+------------------------+
884 * | Argument Type |Extended Type |Stack Storage Size(byte)|
885 * +-----------------------+---------------+------------------------+
887 * |signed char |int | 4 |
888 * |unsigned char |int | 4 |
889 * |[signed] short int |int | 4 |
890 * |unsigned short int |int | 4 |
891 * |[signed] int |No extension | 4 |
892 * |unsigned int |No extension | 4 |
893 * |[signed] long int |No extension | 4 |
894 * |unsigned long int |No extension | 4 |
895 * |[signed] long long int |No extension | 8 |
896 * |unsigned long long int |No extension | 8 |
897 * |float |double | 8 |
898 * |double |No extension | 8 |
899 * |long double |No extension | 8 |
900 * |pointer |No extension | 4 |
901 * |struct/union |- | 4 (*1) |
902 * +-----------------------+---------------+------------------------+
904 * When a struct/union is to be delivered as an argument, the caller copies it
905 * to the local variable area and delivers the address of that area.
909 * +-------------------------------+----------------------+
910 * |Return Value Type |Return Value Interface|
911 * +-------------------------------+----------------------+
913 * |[signed|unsigned] char |GR8 |
914 * |[signed|unsigned] short int |GR8 |
915 * |[signed|unsigned] int |GR8 |
916 * |[signed|unsigned] long int |GR8 |
918 * |[signed|unsigned] long long int|GR8 & GR9 |
920 * |double |GR8 & GR9 |
921 * |long double |GR8 & GR9 |
922 * |struct/union |(*1) |
923 * +-------------------------------+----------------------+
925 * When a struct/union is used as the return value, the caller function stores
926 * the start address of the return value storage area into GR3 and then passes
927 * it to the callee function. The callee function interprets GR3 as the start
928 * address of the return value storage area. When this address needs to be
929 * saved in memory, the callee function secures the hidden parameter save area
930 * and saves the address in that area.
934 frv_stack_info (void)
936 static frv_stack_t info
, zero_info
;
937 frv_stack_t
*info_ptr
= &info
;
938 tree fndecl
= current_function_decl
;
946 /* If we've already calculated the values and reload is complete,
949 return frv_stack_cache
;
951 /* Zero all fields. */
954 /* Set up the register range information. */
955 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
956 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
957 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
958 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
960 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
961 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
962 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
963 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
965 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
966 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
967 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
968 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
970 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
971 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
972 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
973 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
975 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
976 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
977 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
979 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
980 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
981 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
982 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
983 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
985 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
986 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
987 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
988 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
990 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
991 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
992 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
993 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
995 /* Determine if this is a stdarg function. If so, allocate space to store
1002 /* Find the last argument, and see if it is __builtin_va_alist. */
1003 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1005 next_arg
= TREE_CHAIN (cur_arg
);
1006 if (next_arg
== (tree
)0)
1008 if (DECL_NAME (cur_arg
)
1009 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1017 /* Iterate over all of the register ranges. */
1018 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1020 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1021 int first
= reg_ptr
->first
;
1022 int last
= reg_ptr
->last
;
1024 int size_2words
= 0;
1027 /* Calculate which registers need to be saved & save area size. */
1031 for (regno
= first
; regno
<= last
; regno
++)
1033 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
1034 || (current_function_calls_eh_return
1035 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1036 || (!TARGET_FDPIC
&& flag_pic
1037 && cfun
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1039 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1040 size_1word
+= UNITS_PER_WORD
;
1045 /* Calculate whether we need to create a frame after everything else
1046 has been processed. */
1051 if (regs_ever_live
[LR_REGNO
]
1053 /* This is set for __builtin_return_address, etc. */
1054 || cfun
->machine
->frame_needed
1055 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1056 || (!TARGET_FDPIC
&& flag_pic
1057 && cfun
->uses_pic_offset_table
))
1059 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1060 size_1word
+= UNITS_PER_WORD
;
1064 case STACK_REGS_STDARG
:
1067 /* If this is a stdarg function with a non varardic
1068 argument split between registers and the stack,
1069 adjust the saved registers downward. */
1070 last
-= (ADDR_ALIGN (cfun
->pretend_args_size
, UNITS_PER_WORD
)
1073 for (regno
= first
; regno
<= last
; regno
++)
1075 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1076 size_1word
+= UNITS_PER_WORD
;
1079 info_ptr
->stdarg_size
= size_1word
;
1083 case STACK_REGS_STRUCT
:
1084 if (cfun
->returns_struct
)
1086 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1087 size_1word
+= UNITS_PER_WORD
;
1095 /* If this is a field, it only takes one word. */
1096 if (reg_ptr
->field_p
)
1097 size_1word
= UNITS_PER_WORD
;
1099 /* Determine which register pairs can be saved together. */
1100 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1102 for (regno
= first
; regno
< last
; regno
+= 2)
1104 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1106 size_2words
+= 2 * UNITS_PER_WORD
;
1107 size_1word
-= 2 * UNITS_PER_WORD
;
1108 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1109 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1114 reg_ptr
->size_1word
= size_1word
;
1115 reg_ptr
->size_2words
= size_2words
;
1117 if (! reg_ptr
->special_p
)
1119 info_ptr
->regs_size_1word
+= size_1word
;
1120 info_ptr
->regs_size_2words
+= size_2words
;
1125 /* Set up the sizes of each each field in the frame body, making the sizes
1126 of each be divisible by the size of a dword if dword operations might
1127 be used, or the size of a word otherwise. */
1128 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1130 info_ptr
->parameter_size
= ADDR_ALIGN (cfun
->outgoing_args_size
, alignment
);
1131 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1132 + info_ptr
->regs_size_1word
,
1134 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1136 info_ptr
->pretend_size
= cfun
->pretend_args_size
;
1138 /* Work out the size of the frame, excluding the header. Both the frame
1139 body and register parameter area will be dword-aligned. */
1140 info_ptr
->total_size
1141 = (ADDR_ALIGN (info_ptr
->parameter_size
1142 + info_ptr
->regs_size
1143 + info_ptr
->vars_size
,
1145 + ADDR_ALIGN (info_ptr
->pretend_size
1146 + info_ptr
->stdarg_size
,
1147 2 * UNITS_PER_WORD
));
1149 /* See if we need to create a frame at all, if so add header area. */
1150 if (info_ptr
->total_size
> 0
1151 || frame_pointer_needed
1152 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1153 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1155 offset
= info_ptr
->parameter_size
;
1156 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1157 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1159 /* Calculate the offsets to save normal register pairs. */
1160 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1162 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1163 if (! reg_ptr
->special_p
)
1165 int first
= reg_ptr
->first
;
1166 int last
= reg_ptr
->last
;
1169 for (regno
= first
; regno
<= last
; regno
++)
1170 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1171 && regno
!= FRAME_POINTER_REGNUM
1172 && (regno
< FIRST_ARG_REGNUM
1173 || regno
> LAST_ARG_REGNUM
))
1175 info_ptr
->reg_offset
[regno
] = offset
;
1176 offset
+= 2 * UNITS_PER_WORD
;
1181 /* Calculate the offsets to save normal single registers. */
1182 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1184 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1185 if (! reg_ptr
->special_p
)
1187 int first
= reg_ptr
->first
;
1188 int last
= reg_ptr
->last
;
1191 for (regno
= first
; regno
<= last
; regno
++)
1192 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1193 && regno
!= FRAME_POINTER_REGNUM
1194 && (regno
< FIRST_ARG_REGNUM
1195 || regno
> LAST_ARG_REGNUM
))
1197 info_ptr
->reg_offset
[regno
] = offset
;
1198 offset
+= UNITS_PER_WORD
;
1203 /* Calculate the offset to save the local variables at. */
1204 offset
= ADDR_ALIGN (offset
, alignment
);
1205 if (info_ptr
->vars_size
)
1207 info_ptr
->vars_offset
= offset
;
1208 offset
+= info_ptr
->vars_size
;
1211 /* Align header to a dword-boundary. */
1212 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1214 /* Calculate the offsets in the fixed frame. */
1215 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1216 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1217 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1219 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1220 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1221 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1223 if (cfun
->returns_struct
)
1225 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1226 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1227 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1230 /* Calculate the offsets to store the arguments passed in registers
1231 for stdarg functions. The register pairs are first and the single
1232 register if any is last. The register save area starts on a
1234 if (info_ptr
->stdarg_size
)
1236 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1237 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1240 /* Skip the header. */
1241 offset
+= 4 * UNITS_PER_WORD
;
1242 for (regno
= first
; regno
<= last
; regno
++)
1244 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1246 info_ptr
->reg_offset
[regno
] = offset
;
1247 offset
+= 2 * UNITS_PER_WORD
;
1249 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1251 info_ptr
->reg_offset
[regno
] = offset
;
1252 offset
+= UNITS_PER_WORD
;
1258 if (reload_completed
)
1259 frv_stack_cache
= info_ptr
;
1265 /* Print the information about the frv stack offsets, etc. when debugging. */
1268 frv_debug_stack (frv_stack_t
*info
)
1273 info
= frv_stack_info ();
1275 fprintf (stderr
, "\nStack information for function %s:\n",
1276 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1277 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1280 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1281 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1282 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1283 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1284 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1286 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1287 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1288 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1289 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1291 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1293 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1294 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1296 int first
= regs
->first
;
1297 int last
= regs
->last
;
1300 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1301 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1302 regs
->size_1word
, regs
->size_2words
);
1304 for (regno
= first
; regno
<= last
; regno
++)
1306 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1307 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1308 info
->reg_offset
[regno
]);
1310 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1311 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1312 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1315 fputc ('\n', stderr
);
1325 /* The following variable value is TRUE if the next output insn should
1326 finish cpu cycle. In order words the insn will have packing bit
1327 (which means absence of asm code suffix `.p' on assembler. */
1329 static int frv_insn_packing_flag
;
1331 /* True if the current function contains a far jump. */
1334 frv_function_contains_far_jump (void)
1336 rtx insn
= get_insns ();
1338 && !(GET_CODE (insn
) == JUMP_INSN
1339 /* Ignore tablejump patterns. */
1340 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1341 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1342 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1343 insn
= NEXT_INSN (insn
);
1344 return (insn
!= NULL
);
1347 /* For the FRV, this function makes sure that a function with far jumps
1348 will return correctly. It also does the VLIW packing. */
1351 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1353 /* If no frame was created, check whether the function uses a call
1354 instruction to implement a far jump. If so, save the link in gr3 and
1355 replace all returns to LR with returns to GR3. GR3 is used because it
1356 is call-clobbered, because is not available to the register allocator,
1357 and because all functions that take a hidden argument pointer will have
1359 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1363 /* Just to check that the above comment is true. */
1364 if (regs_ever_live
[GPR_FIRST
+ 3])
1367 /* Generate the instruction that saves the link register. */
1368 fprintf (file
, "\tmovsg lr,gr3\n");
1370 /* Replace the LR with GR3 in *return_internal patterns. The insn
1371 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1372 simply emit a different assembly directive because bralr and jmpl
1373 execute in different units. */
1374 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1375 if (GET_CODE (insn
) == JUMP_INSN
)
1377 rtx pattern
= PATTERN (insn
);
1378 if (GET_CODE (pattern
) == PARALLEL
1379 && XVECLEN (pattern
, 0) >= 2
1380 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1381 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1383 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1384 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1385 REGNO (address
) = GPR_FIRST
+ 3;
1391 frv_insn_packing_flag
= TRUE
;
1395 /* Return the next available temporary register in a given class. */
1398 frv_alloc_temp_reg (
1399 frv_tmp_reg_t
*info
, /* which registers are available */
1400 enum reg_class
class, /* register class desired */
1401 enum machine_mode mode
, /* mode to allocate register with */
1402 int mark_as_used
, /* register not available after allocation */
1403 int no_abort
) /* return NULL instead of aborting */
1405 int regno
= info
->next_reg
[ (int)class ];
1406 int orig_regno
= regno
;
1407 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)class ];
1412 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1413 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1416 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1418 if (regno
== orig_regno
)
1427 nr
= HARD_REGNO_NREGS (regno
, mode
);
1428 info
->next_reg
[ (int)class ] = regno
+ nr
;
1431 for (i
= 0; i
< nr
; i
++)
1432 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1434 return gen_rtx_REG (mode
, regno
);
1438 /* Return an rtx with the value OFFSET, which will either be a register or a
1439 signed 12-bit integer. It can be used as the second operand in an "add"
1440 instruction, or as the index in a load or store.
1442 The function returns a constant rtx if OFFSET is small enough, otherwise
1443 it loads the constant into register OFFSET_REGNO and returns that. */
1445 frv_frame_offset_rtx (int offset
)
1447 rtx offset_rtx
= GEN_INT (offset
);
1448 if (IN_RANGE_P (offset
, -2048, 2047))
1452 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1453 if (IN_RANGE_P (offset
, -32768, 32767))
1454 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1457 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1458 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1464 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1465 prologue and epilogue uses such expressions to access the stack. */
1467 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1469 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1471 frv_frame_offset_rtx (offset
)));
1474 /* Generate a frame-related expression:
1476 (set REG (mem (plus (sp) (const_int OFFSET)))).
1478 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1479 instructions. Marking the expressions as frame-related is superfluous if
1480 the note contains just a single set. But if the note contains a PARALLEL
1481 or SEQUENCE that has several sets, each set must be individually marked
1482 as frame-related. */
1484 frv_dwarf_store (rtx reg
, int offset
)
1486 rtx set
= gen_rtx_SET (VOIDmode
,
1487 gen_rtx_MEM (GET_MODE (reg
),
1488 plus_constant (stack_pointer_rtx
,
1491 RTX_FRAME_RELATED_P (set
) = 1;
1495 /* Emit a frame-related instruction whose pattern is PATTERN. The
1496 instruction is the last in a sequence that cumulatively performs the
1497 operation described by DWARF_PATTERN. The instruction is marked as
1498 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1501 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1503 rtx insn
= emit_insn (pattern
);
1504 RTX_FRAME_RELATED_P (insn
) = 1;
1505 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1510 /* Emit instructions that transfer REG to or from the memory location (sp +
1511 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1512 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1513 function to store registers and only the epilogue uses it to load them.
1515 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1516 The generated instruction will use BASE as its base register. BASE may
1517 simply be the stack pointer, but if several accesses are being made to a
1518 region far away from the stack pointer, it may be more efficient to set
1519 up a temporary instead.
1521 Store instructions will be frame-related and will be annotated with the
1522 overall effect of the store. Load instructions will be followed by a
1523 (use) to prevent later optimizations from zapping them.
1525 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1526 as a temporary in such cases. */
1528 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1530 enum machine_mode mode
= GET_MODE (reg
);
1531 rtx mem
= frv_frame_mem (mode
,
1533 stack_offset
- accessor
->base_offset
);
1535 if (accessor
->op
== FRV_LOAD
)
1537 if (SPR_P (REGNO (reg
)))
1539 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1540 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1541 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1544 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1545 emit_insn (gen_rtx_USE (VOIDmode
, reg
));
1549 if (SPR_P (REGNO (reg
)))
1551 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1552 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1553 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1554 frv_dwarf_store (reg
, stack_offset
));
1556 else if (GET_MODE (reg
) == DImode
)
1558 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1559 with a separate save for each register. */
1560 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1561 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1562 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1563 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1564 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1565 gen_rtx_PARALLEL (VOIDmode
,
1566 gen_rtvec (2, set1
, set2
)));
1569 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1570 frv_dwarf_store (reg
, stack_offset
));
1574 /* A function that uses frv_frame_access to transfer a group of registers to
1575 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1576 is the stack information generated by frv_stack_info, and REG_SET is the
1577 number of the register set to transfer. */
1579 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1583 frv_stack_regs_t
*regs_info
;
1586 regs_info
= &info
->regs
[reg_set
];
1587 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1588 if (info
->save_p
[regno
])
1589 frv_frame_access (accessor
,
1590 info
->save_p
[regno
] == REG_SAVE_2WORDS
1591 ? gen_rtx_REG (DImode
, regno
)
1592 : gen_rtx_REG (SImode
, regno
),
1593 info
->reg_offset
[regno
]);
1596 /* Save or restore callee-saved registers that are kept outside the frame
1597 header. The function saves the registers if OP is FRV_STORE and restores
1598 them if OP is FRV_LOAD. INFO is the stack information generated by
1601 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1603 frv_frame_accessor_t accessor
;
1606 accessor
.base
= stack_pointer_rtx
;
1607 accessor
.base_offset
= 0;
1608 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1609 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1610 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1614 /* Called after register allocation to add any instructions needed for the
1615 prologue. Using a prologue insn is favored compared to putting all of the
1616 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1617 it allows the scheduler to intermix instructions with the saves of
1618 the caller saved registers. In some cases, it might be necessary
1619 to emit a barrier instruction as the last insn to prevent such
1622 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1623 so that the debug info generation code can handle them properly. */
1625 frv_expand_prologue (void)
1627 frv_stack_t
*info
= frv_stack_info ();
1628 rtx sp
= stack_pointer_rtx
;
1629 rtx fp
= frame_pointer_rtx
;
1630 frv_frame_accessor_t accessor
;
1632 if (TARGET_DEBUG_STACK
)
1633 frv_debug_stack (info
);
1635 if (info
->total_size
== 0)
1638 /* We're interested in three areas of the frame here:
1640 A: the register save area
1642 C: the header after B
1644 If the frame pointer isn't used, we'll have to set up A, B and C
1645 using the stack pointer. If the frame pointer is used, we'll access
1649 B: set up using sp or a temporary (see below)
1652 We set up B using the stack pointer if the frame is small enough.
1653 Otherwise, it's more efficient to copy the old stack pointer into a
1654 temporary and use that.
1656 Note that it's important to make sure the prologue and epilogue use the
1657 same registers to access A and C, since doing otherwise will confuse
1658 the aliasing code. */
1660 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1661 isn't used, the same method will serve for C. */
1662 accessor
.op
= FRV_STORE
;
1663 if (frame_pointer_needed
&& info
->total_size
> 2048)
1667 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1668 accessor
.base_offset
= info
->total_size
;
1669 insn
= emit_insn (gen_movsi (accessor
.base
, sp
));
1673 accessor
.base
= stack_pointer_rtx
;
1674 accessor
.base_offset
= 0;
1677 /* Allocate the stack space. */
1679 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1680 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1682 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1685 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1688 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1689 and point the new one to that location. */
1690 if (frame_pointer_needed
)
1692 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1694 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1695 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1697 rtx asm_src
= plus_constant (accessor
.base
,
1698 fp_offset
- accessor
.base_offset
);
1699 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1701 /* Store the old frame pointer at (sp + FP_OFFSET). */
1702 frv_frame_access (&accessor
, fp
, fp_offset
);
1704 /* Set up the new frame pointer. */
1705 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1706 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1708 /* Access region C from the frame pointer. */
1710 accessor
.base_offset
= fp_offset
;
1713 /* Set up region C. */
1714 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1715 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1716 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1718 /* Set up region A. */
1719 frv_frame_access_standard_regs (FRV_STORE
, info
);
1721 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1722 scheduler from moving loads before the stores saving the registers. */
1723 if (info
->stdarg_size
> 0)
1724 emit_insn (gen_blockage ());
1726 /* Set up pic register/small data register for this function. */
1727 if (!TARGET_FDPIC
&& flag_pic
&& cfun
->uses_pic_offset_table
)
1728 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1729 gen_rtx_REG (Pmode
, LR_REGNO
),
1730 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1734 /* Under frv, all of the work is done via frv_expand_epilogue, but
1735 this function provides a convenient place to do cleanup. */
1738 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1739 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1741 frv_stack_cache
= (frv_stack_t
*)0;
1743 /* Zap last used registers for conditional execution. */
1744 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1746 /* Release the bitmap of created insns. */
1747 BITMAP_XFREE (frv_ifcvt
.scratch_insns_bitmap
);
1751 /* Called after register allocation to add any instructions needed for the
1752 epilogue. Using an epilogue insn is favored compared to putting all of the
1753 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1754 it allows the scheduler to intermix instructions with the saves of
1755 the caller saved registers. In some cases, it might be necessary
1756 to emit a barrier instruction as the last insn to prevent such
1759 If SIBCALL_P is true, the final branch back to the calling function is
1760 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1761 we must not clobber any arguments used for parameter passing or any stack
1762 slots for arguments passed to the current function. */
1765 frv_expand_epilogue (bool emit_return
)
1767 frv_stack_t
*info
= frv_stack_info ();
1768 rtx fp
= frame_pointer_rtx
;
1769 rtx sp
= stack_pointer_rtx
;
1773 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1775 /* Restore the stack pointer to its original value if alloca or the like
1777 if (! current_function_sp_is_unchanging
)
1778 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1780 /* Restore the callee-saved registers that were used in this function. */
1781 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1783 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1784 no return instruction should be emitted. */
1785 if (info
->save_p
[LR_REGNO
])
1790 /* Use the same method to access the link register's slot as we did in
1791 the prologue. In other words, use the frame pointer if available,
1792 otherwise use the stack pointer.
1794 LR_OFFSET is the offset of the link register's slot from the start
1795 of the frame and MEM is a memory rtx for it. */
1796 lr_offset
= info
->reg_offset
[LR_REGNO
];
1797 if (frame_pointer_needed
)
1798 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1800 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1802 /* Load the old link register into a GPR. */
1803 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1804 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1807 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1809 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1810 the load is preserved. */
1811 if (frame_pointer_needed
)
1813 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1814 emit_insn (gen_rtx_USE (VOIDmode
, fp
));
1817 /* Deallocate the stack frame. */
1818 if (info
->total_size
!= 0)
1820 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1821 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1824 /* If this function uses eh_return, add the final stack adjustment now. */
1825 if (current_function_calls_eh_return
)
1826 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1829 emit_jump_insn (gen_epilogue_return (return_addr
));
1832 rtx lr
= return_addr
;
1834 if (REGNO (return_addr
) != LR_REGNO
)
1836 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1837 emit_move_insn (lr
, return_addr
);
1840 emit_insn (gen_rtx_USE (VOIDmode
, lr
));
1845 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1848 frv_asm_output_mi_thunk (FILE *file
,
1849 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1850 HOST_WIDE_INT delta
,
1851 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1854 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1855 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1856 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1857 const char *parallel
= ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1859 /* Do the add using an addi if possible. */
1860 if (IN_RANGE_P (delta
, -2048, 2047))
1861 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1864 const char *const name_add
= reg_names
[TEMP_REGNO
];
1865 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1866 parallel
, delta
, name_add
);
1867 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1869 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1874 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1875 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
1879 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
1880 assemble_name (file
, name_func
);
1881 fprintf (file
, "),%s\n", name_jmp
);
1883 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
1884 assemble_name (file
, name_func
);
1885 fprintf (file
, "),%s\n", name_jmp
);
1887 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
1891 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
1892 assemble_name (file
, name_func
);
1893 fprintf (file
, "\t)), %s\n", name_jmp
);
1898 fprintf (file
, "\tsethi%s #hi(", parallel
);
1899 assemble_name (file
, name_func
);
1900 fprintf (file
, "),%s\n", name_jmp
);
1902 fprintf (file
, "\tsetlo #lo(");
1903 assemble_name (file
, name_func
);
1904 fprintf (file
, "),%s\n", name_jmp
);
1908 /* Use JUMP_REGNO as a temporary PIC register. */
1909 const char *name_lr
= reg_names
[LR_REGNO
];
1910 const char *name_gppic
= name_jmp
;
1911 const char *name_tmp
= reg_names
[TEMP_REGNO
];
1913 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
1914 fprintf (file
, "\tcall 1f\n");
1915 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
1916 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
1917 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
1918 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
1919 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
1921 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
1922 assemble_name (file
, name_func
);
1923 fprintf (file
, "),%s\n", name_tmp
);
1925 fprintf (file
, "\tsetlo #gprello(");
1926 assemble_name (file
, name_func
);
1927 fprintf (file
, "),%s\n", name_tmp
);
1929 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
1932 /* Jump to the function address. */
1933 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
1937 /* A C expression which is nonzero if a function must have and use a frame
1938 pointer. This expression is evaluated in the reload pass. If its value is
1939 nonzero the function will have a frame pointer.
1941 The expression can in principle examine the current function and decide
1942 according to the facts, but on most machines the constant 0 or the constant
1943 1 suffices. Use 0 when the machine allows code to be generated with no
1944 frame pointer, and doing so saves some time or space. Use 1 when there is
1945 no possible advantage to avoiding a frame pointer.
1947 In certain cases, the compiler does not know how to produce valid code
1948 without a frame pointer. The compiler recognizes those cases and
1949 automatically gives the function a frame pointer regardless of what
1950 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1952 In a function that does not require a frame pointer, the frame pointer
1953 register can be allocated for ordinary usage, unless you mark it as a fixed
1954 register. See `FIXED_REGISTERS' for more information. */
1956 /* On frv, create a frame whenever we need to create stack. */
1959 frv_frame_pointer_required (void)
1961 /* If we forgoing the usual linkage requirements, we only need
1962 a frame pointer if the stack pointer might change. */
1963 if (!TARGET_LINKED_FP
)
1964 return !current_function_sp_is_unchanging
;
1966 if (! current_function_is_leaf
)
1969 if (get_frame_size () != 0)
1975 if (!current_function_sp_is_unchanging
)
1978 if (!TARGET_FDPIC
&& flag_pic
&& cfun
->uses_pic_offset_table
)
1984 if (cfun
->machine
->frame_needed
)
1991 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1992 initial difference between the specified pair of registers. This macro must
1993 be defined if `ELIMINABLE_REGS' is defined. */
1995 /* See frv_stack_info for more details on the frv stack frame. */
1998 frv_initial_elimination_offset (int from
, int to
)
2000 frv_stack_t
*info
= frv_stack_info ();
2003 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2004 ret
= info
->total_size
- info
->pretend_size
;
2006 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2007 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2009 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2010 ret
= (info
->total_size
2011 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2012 - info
->pretend_size
);
2017 if (TARGET_DEBUG_STACK
)
2018 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2019 reg_names
[from
], reg_names
[to
], ret
);
2025 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2028 frv_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
2029 enum machine_mode mode
,
2030 tree type ATTRIBUTE_UNUSED
,
2034 if (TARGET_DEBUG_ARG
)
2036 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2037 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2041 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2044 frv_expand_builtin_saveregs (void)
2046 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2048 if (TARGET_DEBUG_ARG
)
2049 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2052 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2056 /* Expand __builtin_va_start to do the va_start macro. */
2059 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2062 int num
= cfun
->args_info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2064 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2065 GEN_INT (UNITS_PER_WORD
* num
));
2067 if (TARGET_DEBUG_ARG
)
2069 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2070 cfun
->args_info
, num
);
2072 debug_rtx (nextarg
);
2075 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2076 make_tree (ptr_type_node
, nextarg
));
2077 TREE_SIDE_EFFECTS (t
) = 1;
2079 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2083 /* Expand __builtin_va_arg to do the va_arg macro. */
2086 frv_expand_builtin_va_arg (tree valist
, tree type
)
2092 if (TARGET_DEBUG_ARG
)
2094 fprintf (stderr
, "va_arg:\n");
2098 if (! AGGREGATE_TYPE_P (type
))
2099 return std_expand_builtin_va_arg (valist
, type
);
2101 addr
= std_expand_builtin_va_arg (valist
, ptr_type_node
);
2102 mem
= gen_rtx_MEM (Pmode
, addr
);
2103 reg
= gen_reg_rtx (Pmode
);
2105 set_mem_alias_set (mem
, get_varargs_alias_set ());
2106 emit_move_insn (reg
, mem
);
2112 /* Expand a block move operation, and return 1 if successful. Return 0
2113 if we should let the compiler generate normal code.
2115 operands[0] is the destination
2116 operands[1] is the source
2117 operands[2] is the length
2118 operands[3] is the alignment */
2120 /* Maximum number of loads to do before doing the stores */
2121 #ifndef MAX_MOVE_REG
2122 #define MAX_MOVE_REG 4
2125 /* Maximum number of total loads to do. */
2126 #ifndef TOTAL_MOVE_REG
2127 #define TOTAL_MOVE_REG 8
2131 frv_expand_block_move (rtx operands
[])
2133 rtx orig_dest
= operands
[0];
2134 rtx orig_src
= operands
[1];
2135 rtx bytes_rtx
= operands
[2];
2136 rtx align_rtx
= operands
[3];
2137 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2150 rtx stores
[MAX_MOVE_REG
];
2152 enum machine_mode mode
;
2154 /* If this is not a fixed size move, just call memcpy. */
2158 /* If this is not a fixed size alignment, abort. */
2159 if (GET_CODE (align_rtx
) != CONST_INT
)
2162 align
= INTVAL (align_rtx
);
2164 /* Anything to move? */
2165 bytes
= INTVAL (bytes_rtx
);
2169 /* Don't support real large moves. */
2170 if (bytes
> TOTAL_MOVE_REG
*align
)
2173 /* Move the address into scratch registers. */
2174 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2175 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2177 num_reg
= offset
= 0;
2178 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2180 /* Calculate the correct offset for src/dest. */
2184 dest_addr
= dest_reg
;
2188 src_addr
= plus_constant (src_reg
, offset
);
2189 dest_addr
= plus_constant (dest_reg
, offset
);
2192 /* Generate the appropriate load and store, saving the stores
2194 if (bytes
>= 4 && align
>= 4)
2196 else if (bytes
>= 2 && align
>= 2)
2201 move_bytes
= GET_MODE_SIZE (mode
);
2202 tmp_reg
= gen_reg_rtx (mode
);
2203 src_mem
= change_address (orig_src
, mode
, src_addr
);
2204 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2205 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2206 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2208 if (num_reg
>= MAX_MOVE_REG
)
2210 for (i
= 0; i
< num_reg
; i
++)
2211 emit_insn (stores
[i
]);
2216 for (i
= 0; i
< num_reg
; i
++)
2217 emit_insn (stores
[i
]);
2223 /* Expand a block clear operation, and return 1 if successful. Return 0
2224 if we should let the compiler generate normal code.
2226 operands[0] is the destination
2227 operands[1] is the length
2228 operands[2] is the alignment */
2231 frv_expand_block_clear (rtx operands
[])
2233 rtx orig_dest
= operands
[0];
2234 rtx bytes_rtx
= operands
[1];
2235 rtx align_rtx
= operands
[2];
2236 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2245 enum machine_mode mode
;
2247 /* If this is not a fixed size move, just call memcpy. */
2251 /* If this is not a fixed size alignment, abort. */
2252 if (GET_CODE (align_rtx
) != CONST_INT
)
2255 align
= INTVAL (align_rtx
);
2257 /* Anything to move? */
2258 bytes
= INTVAL (bytes_rtx
);
2262 /* Don't support real large clears. */
2263 if (bytes
> TOTAL_MOVE_REG
*align
)
2266 /* Move the address into a scratch register. */
2267 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2269 num_reg
= offset
= 0;
2270 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2272 /* Calculate the correct offset for src/dest. */
2273 dest_addr
= ((offset
== 0)
2275 : plus_constant (dest_reg
, offset
));
2277 /* Generate the appropriate store of gr0. */
2278 if (bytes
>= 4 && align
>= 4)
2280 else if (bytes
>= 2 && align
>= 2)
2285 clear_bytes
= GET_MODE_SIZE (mode
);
2286 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2287 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2294 /* The following variable is used to output modifiers of assembler
2295 code of the current output insn. */
2297 static rtx
*frv_insn_operands
;
2299 /* The following function is used to add assembler insn code suffix .p
2300 if it is necessary. */
2303 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2307 if (! PACKING_FLAG_USED_P())
2310 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2313 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2314 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2316 int letter
= *ptr
++;
2319 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2320 while ((c
= *ptr
) >= '0' && c
<= '9')
2327 if (!frv_insn_packing_flag
)
2333 /* The following function sets up the packing bit for the current
2334 output insn. Remember that the function is not called for asm
2338 frv_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands ATTRIBUTE_UNUSED
)
2340 if (! PACKING_FLAG_USED_P())
2346 frv_insn_operands
= opvec
;
2348 /* Look for the next printable instruction. frv_pack_insns () has set
2349 things up so that any printable instruction will have TImode if it
2350 starts a new packet and VOIDmode if it should be packed with the
2351 previous instruction.
2353 Printable instructions will be asm_operands or match one of the .md
2354 patterns. Since asm instructions cannot be packed -- and will
2355 therefore have TImode -- this loop terminates on any recognizable
2356 instruction, and on any unrecognizable instruction with TImode. */
2357 for (insn
= NEXT_INSN (insn
); insn
; insn
= NEXT_INSN (insn
))
2361 else if (!INSN_P (insn
))
2363 else if (GET_MODE (insn
) == TImode
|| INSN_CODE (insn
) != -1)
2367 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2368 be packed with this one. Set it to TRUE otherwise. If the next
2369 instruction is an asm instruction, this statement will set the
2370 flag to TRUE, and that value will still hold when the asm operands
2371 themselves are printed. */
2372 frv_insn_packing_flag
= ! (insn
&& INSN_P (insn
)
2373 && GET_MODE (insn
) != TImode
);
2378 /* A C expression whose value is RTL representing the address in a stack frame
2379 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2380 an RTL expression for the address of the stack frame itself.
2382 If you don't define this macro, the default is to return the value of
2383 FRAMEADDR--that is, the stack frame address is also the address of the stack
2384 word that points to the previous frame. */
2386 /* The default is correct, but we need to make sure the frame gets created. */
2388 frv_dynamic_chain_address (rtx frame
)
2390 cfun
->machine
->frame_needed
= 1;
2395 /* A C expression whose value is RTL representing the value of the return
2396 address for the frame COUNT steps up from the current frame, after the
2397 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2398 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2401 The value of the expression must always be the correct address when COUNT is
2402 zero, but may be `NULL_RTX' if there is not way to determine the return
2403 address of other frames. */
2406 frv_return_addr_rtx (int count
, rtx frame
)
2410 cfun
->machine
->frame_needed
= 1;
2411 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2414 /* Given a memory reference MEMREF, interpret the referenced memory as
2415 an array of MODE values, and return a reference to the element
2416 specified by INDEX. Assume that any pre-modification implicit in
2417 MEMREF has already happened.
2419 MEMREF must be a legitimate operand for modes larger than SImode.
2420 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2421 this function cannot handle. */
2423 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2425 rtx base
= XEXP (memref
, 0);
2426 if (GET_CODE (base
) == PRE_MODIFY
)
2427 base
= XEXP (base
, 0);
2428 return change_address (memref
, mode
,
2429 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2433 /* Print a memory address as an operand to reference that memory location. */
2435 frv_print_operand_address (FILE * stream
, rtx x
)
2437 if (GET_CODE (x
) == MEM
)
2440 switch (GET_CODE (x
))
2443 fputs (reg_names
[ REGNO (x
)], stream
);
2447 fprintf (stream
, "%ld", (long) INTVAL (x
));
2451 assemble_name (stream
, XSTR (x
, 0));
2456 output_addr_const (stream
, x
);
2463 fatal_insn ("Bad insn to frv_print_operand_address:", x
);
2468 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2470 int regno
= true_regnum (x
);
2472 fputs (reg_names
[regno
], stream
);
2474 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x
);
2477 /* Print a memory reference suitable for the ld/st instructions. */
2480 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2482 struct frv_unspec unspec
;
2486 switch (GET_CODE (x
))
2493 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2495 x1
= XEXP (XEXP (x
, 1), 1);
2505 if (GET_CODE (x0
) == CONST_INT
)
2513 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2522 else if (GET_CODE (x1
) != CONST_INT
)
2523 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2526 fputs ("@(", stream
);
2528 fputs (reg_names
[GPR_R0
], stream
);
2529 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2530 frv_print_operand_memory_reference_reg (stream
, x0
);
2532 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2534 fputs (",", stream
);
2536 fputs (reg_names
[GPR_R0
], stream
);
2540 switch (GET_CODE (x1
))
2544 frv_print_operand_memory_reference_reg (stream
, x1
);
2548 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2552 if (!frv_const_unspec_p (x1
, &unspec
))
2553 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1
);
2554 frv_output_const_unspec (stream
, &unspec
);
2558 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2562 fputs (")", stream
);
2566 /* Return 2 for likely branches and 0 for non-likely branches */
2568 #define FRV_JUMP_LIKELY 2
2569 #define FRV_JUMP_NOT_LIKELY 0
2572 frv_print_operand_jump_hint (rtx insn
)
2577 HOST_WIDE_INT prob
= -1;
2578 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2580 if (GET_CODE (insn
) != JUMP_INSN
)
2583 /* Assume any non-conditional jump is likely. */
2584 if (! any_condjump_p (insn
))
2585 ret
= FRV_JUMP_LIKELY
;
2589 labelref
= condjump_label (insn
);
2592 rtx label
= XEXP (labelref
, 0);
2593 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2598 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2600 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2604 prob
= INTVAL (XEXP (note
, 0));
2605 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2607 : FRV_JUMP_NOT_LIKELY
);
2619 case UNKNOWN
: direction
= "unknown jump direction"; break;
2620 case BACKWARD
: direction
= "jump backward"; break;
2621 case FORWARD
: direction
= "jump forward"; break;
2625 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2626 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2627 (long)INSN_UID (insn
), direction
, (long)prob
,
2628 (long)REG_BR_PROB_BASE
, ret
);
2636 /* Print an operand to an assembler instruction.
2638 `%' followed by a letter and a digit says to output an operand in an
2639 alternate fashion. Four letters have standard, built-in meanings described
2640 below. The machine description macro `PRINT_OPERAND' can define additional
2641 letters with nonstandard meanings.
2643 `%cDIGIT' can be used to substitute an operand that is a constant value
2644 without the syntax that normally indicates an immediate operand.
2646 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2649 `%aDIGIT' can be used to substitute an operand as if it were a memory
2650 reference, with the actual operand treated as the address. This may be
2651 useful when outputting a "load address" instruction, because often the
2652 assembler syntax for such an instruction requires you to write the operand
2653 as if it were a memory reference.
2655 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2657 `%=' outputs a number which is unique to each instruction in the entire
2658 compilation. This is useful for making local labels to be referred to more
2659 than once in a single template that generates multiple assembler
2662 `%' followed by a punctuation character specifies a substitution that does
2663 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2664 assembler code. Other nonstandard cases can be defined in the
2665 `PRINT_OPERAND' macro. You must also define which punctuation characters
2666 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2669 frv_print_operand (FILE * file
, rtx x
, int code
)
2671 struct frv_unspec unspec
;
2672 HOST_WIDE_INT value
;
2675 if (code
!= 0 && !isalpha (code
))
2678 else if (GET_CODE (x
) == CONST_INT
)
2681 else if (GET_CODE (x
) == CONST_DOUBLE
)
2683 if (GET_MODE (x
) == SFmode
)
2688 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2689 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2693 else if (GET_MODE (x
) == VOIDmode
)
2694 value
= CONST_DOUBLE_LOW (x
);
2697 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x
);
2708 fputs (reg_names
[GPR_R0
], file
);
2712 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2716 /* Output small data area base register (gr16). */
2717 fputs (reg_names
[SDA_BASE_REG
], file
);
2721 /* Output pic register (gr17). */
2722 fputs (reg_names
[PIC_REGNO
], file
);
2726 /* Output the temporary integer CCR register. */
2727 fputs (reg_names
[ICR_TEMP
], file
);
2731 /* Output the temporary integer CC register. */
2732 fputs (reg_names
[ICC_TEMP
], file
);
2735 /* case 'a': print an address. */
2738 /* Print appropriate test for integer branch false operation. */
2739 switch (GET_CODE (x
))
2742 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x
);
2744 case EQ
: fputs ("ne", file
); break;
2745 case NE
: fputs ("eq", file
); break;
2746 case LT
: fputs ("ge", file
); break;
2747 case LE
: fputs ("gt", file
); break;
2748 case GT
: fputs ("le", file
); break;
2749 case GE
: fputs ("lt", file
); break;
2750 case LTU
: fputs ("nc", file
); break;
2751 case LEU
: fputs ("hi", file
); break;
2752 case GTU
: fputs ("ls", file
); break;
2753 case GEU
: fputs ("c", file
); break;
2757 /* case 'c': print a constant without the constant prefix. If
2758 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2761 /* Print appropriate test for integer branch true operation. */
2762 switch (GET_CODE (x
))
2765 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x
);
2767 case EQ
: fputs ("eq", file
); break;
2768 case NE
: fputs ("ne", file
); break;
2769 case LT
: fputs ("lt", file
); break;
2770 case LE
: fputs ("le", file
); break;
2771 case GT
: fputs ("gt", file
); break;
2772 case GE
: fputs ("ge", file
); break;
2773 case LTU
: fputs ("c", file
); break;
2774 case LEU
: fputs ("ls", file
); break;
2775 case GTU
: fputs ("hi", file
); break;
2776 case GEU
: fputs ("nc", file
); break;
2781 /* Print 1 for a NE and 0 for an EQ to give the final argument
2782 for a conditional instruction. */
2783 if (GET_CODE (x
) == NE
)
2786 else if (GET_CODE (x
) == EQ
)
2790 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x
);
2794 /* Print appropriate test for floating point branch false operation. */
2795 switch (GET_CODE (x
))
2798 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x
);
2800 case EQ
: fputs ("ne", file
); break;
2801 case NE
: fputs ("eq", file
); break;
2802 case LT
: fputs ("uge", file
); break;
2803 case LE
: fputs ("ug", file
); break;
2804 case GT
: fputs ("ule", file
); break;
2805 case GE
: fputs ("ul", file
); break;
2810 /* Print appropriate test for floating point branch true operation. */
2811 switch (GET_CODE (x
))
2814 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x
);
2816 case EQ
: fputs ("eq", file
); break;
2817 case NE
: fputs ("ne", file
); break;
2818 case LT
: fputs ("lt", file
); break;
2819 case LE
: fputs ("le", file
); break;
2820 case GT
: fputs ("gt", file
); break;
2821 case GE
: fputs ("ge", file
); break;
2826 /* Print appropriate GOT function. */
2827 if (GET_CODE (x
) != CONST_INT
)
2828 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x
);
2829 fputs (unspec_got_name (INTVAL (x
)), file
);
2833 /* Print 'i' if the operand is a constant, or is a memory reference that
2835 if (GET_CODE (x
) == MEM
)
2836 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2837 ? XEXP (XEXP (x
, 0), 1)
2839 else if (GET_CODE (x
) == PLUS
)
2842 switch (GET_CODE (x
))
2856 /* For jump instructions, print 'i' if the operand is a constant or
2857 is an expression that adds a constant. */
2858 if (GET_CODE (x
) == CONST_INT
)
2863 if (GET_CODE (x
) == CONST_INT
2864 || (GET_CODE (x
) == PLUS
2865 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2866 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2872 /* Print the lower register of a double word register pair */
2873 if (GET_CODE (x
) == REG
)
2874 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2876 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x
);
2879 /* case 'l': print a LABEL_REF. */
2883 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2884 for the second word of double memory operations. */
2885 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2886 switch (GET_CODE (x
))
2889 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x
);
2892 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2900 frv_print_operand_memory_reference (file
, x
, offset
);
2906 /* Print the opcode of a command. */
2907 switch (GET_CODE (x
))
2910 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x
);
2912 case PLUS
: fputs ("add", file
); break;
2913 case MINUS
: fputs ("sub", file
); break;
2914 case AND
: fputs ("and", file
); break;
2915 case IOR
: fputs ("or", file
); break;
2916 case XOR
: fputs ("xor", file
); break;
2917 case ASHIFT
: fputs ("sll", file
); break;
2918 case ASHIFTRT
: fputs ("sra", file
); break;
2919 case LSHIFTRT
: fputs ("srl", file
); break;
2923 /* case 'n': negate and print a constant int. */
2926 /* Print PIC label using operand as the number. */
2927 if (GET_CODE (x
) != CONST_INT
)
2928 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x
);
2930 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2934 /* Print 'u' if the operand is a update load/store. */
2935 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2940 /* If value is 0, print gr0, otherwise it must be a register. */
2941 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
2942 fputs (reg_names
[GPR_R0
], file
);
2944 else if (GET_CODE (x
) == REG
)
2945 fputs (reg_names
[REGNO (x
)], file
);
2948 fatal_insn ("Bad insn in frv_print_operand, z case", x
);
2952 /* Print constant in hex. */
2953 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2955 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
2962 if (GET_CODE (x
) == REG
)
2963 fputs (reg_names
[REGNO (x
)], file
);
2965 else if (GET_CODE (x
) == CONST_INT
2966 || GET_CODE (x
) == CONST_DOUBLE
)
2967 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
2969 else if (frv_const_unspec_p (x
, &unspec
))
2970 frv_output_const_unspec (file
, &unspec
);
2972 else if (GET_CODE (x
) == MEM
)
2973 frv_print_operand_address (file
, XEXP (x
, 0));
2975 else if (CONSTANT_ADDRESS_P (x
))
2976 frv_print_operand_address (file
, x
);
2979 fatal_insn ("Bad insn in frv_print_operand, 0 case", x
);
2984 fatal_insn ("frv_print_operand: unknown code", x
);
2992 /* A C statement (sans semicolon) for initializing the variable CUM for the
2993 state at the beginning of the argument list. The variable has type
2994 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
2995 of the function which will receive the args, or 0 if the args are to a
2996 compiler support library function. The value of INDIRECT is nonzero when
2997 processing an indirect call, for example a call through a function pointer.
2998 The value of INDIRECT is zero for a call to an explicitly named function, a
2999 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3000 arguments for the function being compiled.
3002 When processing a call to a compiler support library function, LIBNAME
3003 identifies which one. It is a `symbol_ref' rtx which contains the name of
3004 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3005 being processed. Thus, each time this macro is called, either LIBNAME or
3006 FNTYPE is nonzero, but never both of them at once. */
3009 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3015 *cum
= FIRST_ARG_REGNUM
;
3017 if (TARGET_DEBUG_ARG
)
3019 fprintf (stderr
, "\ninit_cumulative_args:");
3020 if (!fndecl
&& fntype
)
3021 fputs (" indirect", stderr
);
3024 fputs (" incoming", stderr
);
3028 tree ret_type
= TREE_TYPE (fntype
);
3029 fprintf (stderr
, " return=%s,",
3030 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3033 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3034 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3036 if (cfun
->returns_struct
)
3037 fprintf (stderr
, " return-struct");
3039 putc ('\n', stderr
);
3044 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3045 argument with the specified mode and type. If it is not defined,
3046 `PARM_BOUNDARY' is used for all arguments. */
3049 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
3050 tree type ATTRIBUTE_UNUSED
)
3052 return BITS_PER_WORD
;
3056 /* A C expression that controls whether a function argument is passed in a
3057 register, and which register.
3059 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
3060 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3061 arguments so far passed in registers; MODE, the machine mode of the argument;
3062 TYPE, the data type of the argument as a tree node or 0 if that is not known
3063 (which happens for C support library functions); and NAMED, which is 1 for an
3064 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3065 called function's prototype.
3067 The value of the expression should either be a `reg' RTX for the hard
3068 register in which to pass the argument, or zero to pass the argument on the
3071 For machines like the VAX and 68000, where normally all arguments are
3072 pushed, zero suffices as a definition.
3074 The usual way to make the ANSI library `stdarg.h' work on a machine where
3075 some arguments are usually passed in registers, is to cause nameless
3076 arguments to be passed on the stack instead. This is done by making
3077 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3079 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3080 this macro to determine if this argument is of a type that must be passed in
3081 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3082 returns nonzero for such an argument, the compiler will abort. If
3083 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3084 stack and then loaded into a register. */
3087 frv_function_arg (CUMULATIVE_ARGS
*cum
,
3088 enum machine_mode mode
,
3089 tree type ATTRIBUTE_UNUSED
,
3091 int incoming ATTRIBUTE_UNUSED
)
3093 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3098 /* Return a marker for use in the call instruction. */
3099 if (xmode
== VOIDmode
)
3105 else if (arg_num
<= LAST_ARG_REGNUM
)
3107 ret
= gen_rtx_REG (xmode
, arg_num
);
3108 debstr
= reg_names
[arg_num
];
3117 if (TARGET_DEBUG_ARG
)
3119 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3120 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3126 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3127 advance past an argument in the argument list. The values MODE, TYPE and
3128 NAMED describe that argument. Once this is done, the variable CUM is
3129 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3131 This macro need not do anything if the argument in question was passed on
3132 the stack. The compiler knows how to track the amount of stack space used
3133 for arguments without any special help. */
3136 frv_function_arg_advance (CUMULATIVE_ARGS
*cum
,
3137 enum machine_mode mode
,
3138 tree type ATTRIBUTE_UNUSED
,
3141 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3142 int bytes
= GET_MODE_SIZE (xmode
);
3143 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3146 *cum
= arg_num
+ words
;
3148 if (TARGET_DEBUG_ARG
)
3150 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3151 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3155 /* A C expression for the number of words, at the beginning of an argument,
3156 must be put in registers. The value must be zero for arguments that are
3157 passed entirely in registers or that are entirely pushed on the stack.
3159 On some machines, certain arguments must be passed partially in registers
3160 and partially in memory. On these machines, typically the first N words of
3161 arguments are passed in registers, and the rest on the stack. If a
3162 multi-word argument (a `double' or a structure) crosses that boundary, its
3163 first few words must be passed in registers and the rest must be pushed.
3164 This macro tells the compiler when this occurs, and how many of the words
3165 should go in registers.
3167 `FUNCTION_ARG' for these arguments should return the first register to be
3168 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3169 the called function. */
3172 frv_function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
,
3173 enum machine_mode mode
,
3174 tree type ATTRIBUTE_UNUSED
,
3175 int named ATTRIBUTE_UNUSED
)
3177 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3178 int bytes
= GET_MODE_SIZE (xmode
);
3179 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3183 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3184 ? LAST_ARG_REGNUM
- arg_num
+ 1
3187 if (TARGET_DEBUG_ARG
&& ret
)
3188 fprintf (stderr
, "function_arg_partial_nregs: %d\n", ret
);
3196 /* A C expression that indicates when an argument must be passed by reference.
3197 If nonzero for an argument, a copy of that argument is made in memory and a
3198 pointer to the argument is passed instead of the argument itself. The
3199 pointer is passed in whatever way is appropriate for passing a pointer to
3202 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3203 definition of this macro might be
3204 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3205 MUST_PASS_IN_STACK (MODE, TYPE) */
3208 frv_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3209 enum machine_mode mode
,
3211 int named ATTRIBUTE_UNUSED
)
3213 return MUST_PASS_IN_STACK (mode
, type
);
3216 /* If defined, a C expression that indicates when it is the called function's
3217 responsibility to make a copy of arguments passed by invisible reference.
3218 Normally, the caller makes a copy and passes the address of the copy to the
3219 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3220 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3221 the "live" value. The called function must not modify this value. If it
3222 can be determined that the value won't be modified, it need not make a copy;
3223 otherwise a copy must be made. */
3226 frv_function_arg_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3227 enum machine_mode mode ATTRIBUTE_UNUSED
,
3228 tree type ATTRIBUTE_UNUSED
,
3229 int named ATTRIBUTE_UNUSED
)
3235 /* Return true if a register is ok to use as a base or index register. */
3237 static FRV_INLINE
int
3238 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3244 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3246 if (regno
== ARG_POINTER_REGNUM
)
3249 return (regno
>= FIRST_PSEUDO_REGISTER
);
3253 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3254 RTX) is a legitimate memory address on the target machine for a memory
3255 operand of mode MODE.
3257 It usually pays to define several simpler macros to serve as subroutines for
3258 this one. Otherwise it may be too complicated to understand.
3260 This macro must exist in two variants: a strict variant and a non-strict
3261 one. The strict variant is used in the reload pass. It must be defined so
3262 that any pseudo-register that has not been allocated a hard register is
3263 considered a memory reference. In contexts where some kind of register is
3264 required, a pseudo-register with no hard register must be rejected.
3266 The non-strict variant is used in other passes. It must be defined to
3267 accept all pseudo-registers in every context where some kind of register is
3270 Compiler source files that want to use the strict variant of this macro
3271 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3272 conditional to define the strict variant in that case and the non-strict
3275 Subroutines to check for acceptable registers for various purposes (one for
3276 base registers, one for index registers, and so on) are typically among the
3277 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3278 subroutine macros need have two variants; the higher levels of macros may be
3279 the same whether strict or not.
3281 Normally, constant addresses which are the sum of a `symbol_ref' and an
3282 integer are stored inside a `const' RTX to mark them as constant.
3283 Therefore, there is no need to recognize such sums specifically as
3284 legitimate addresses. Normally you would simply recognize any `const' as
3287 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3288 are not marked with `const'. It assumes that a naked `plus' indicates
3289 indexing. If so, then you *must* reject such naked constant sums as
3290 illegitimate addresses, so that none of them will be given to
3291 `PRINT_OPERAND_ADDRESS'.
3293 On some machines, whether a symbolic address is legitimate depends on the
3294 section that the address refers to. On these machines, define the macro
3295 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3296 then check for it here. When you see a `const', you will have to look
3297 inside it to find the `symbol_ref' in order to determine the section.
3299 The best way to modify the name string is by adding text to the beginning,
3300 with suitable punctuation to prevent any ambiguity. Allocate the new name
3301 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3302 remove and decode the added text and output the name accordingly, and define
3303 `(* targetm.strip_name_encoding)' to access the original name string.
3305 You can check the information stored here into the `symbol_ref' in the
3306 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3307 `PRINT_OPERAND_ADDRESS'. */
3310 frv_legitimate_address_p (enum machine_mode mode
,
3314 int allow_double_reg_p
)
3318 HOST_WIDE_INT value
;
3321 switch (GET_CODE (x
))
3328 if (GET_CODE (x
) != REG
)
3334 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3340 if (GET_CODE (x0
) != REG
3341 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3342 || GET_CODE (x1
) != PLUS
3343 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3344 || GET_CODE (XEXP (x1
, 1)) != REG
3345 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3352 /* 12 bit immediate */
3357 ret
= IN_RANGE_P (INTVAL (x
), -2048, 2047);
3359 /* If we can't use load/store double operations, make sure we can
3360 address the second word. */
3361 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3362 ret
= IN_RANGE_P (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3371 if (GET_CODE (x0
) == SUBREG
)
3372 x0
= SUBREG_REG (x0
);
3374 if (GET_CODE (x0
) != REG
)
3377 regno0
= REGNO (x0
);
3378 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3381 switch (GET_CODE (x1
))
3387 x1
= SUBREG_REG (x1
);
3388 if (GET_CODE (x1
) != REG
)
3394 /* Do not allow reg+reg addressing for modes > 1 word if we
3395 can't depend on having move double instructions. */
3396 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3399 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3403 /* 12 bit immediate */
3408 value
= INTVAL (x1
);
3409 ret
= IN_RANGE_P (value
, -2048, 2047);
3411 /* If we can't use load/store double operations, make sure we can
3412 address the second word. */
3413 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3414 ret
= IN_RANGE_P (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3419 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3427 if (TARGET_DEBUG_ADDR
)
3429 fprintf (stderr
, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3430 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3431 (condexec_p
) ? ", inside conditional code" : "");
3439 /* Test whether a local function descriptor is canonical, i.e.,
3440 whether we can use FUNCDESC_GOTOFF to compute the address of the
3444 frv_local_funcdesc_p (rtx fnx
)
3447 enum symbol_visibility vis
;
3450 if (! SYMBOL_REF_LOCAL_P (fnx
))
3453 fn
= SYMBOL_REF_DECL (fnx
);
3458 vis
= DECL_VISIBILITY (fn
);
3460 if (vis
== VISIBILITY_PROTECTED
)
3461 /* Private function descriptors for protected functions are not
3462 canonical. Temporarily change the visibility to global. */
3463 vis
= VISIBILITY_DEFAULT
;
3464 else if (flag_shlib
)
3465 /* If we're already compiling for a shared library (that, unlike
3466 executables, can't assume that the existence of a definition
3467 implies local binding), we can skip the re-testing. */
3470 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3472 DECL_VISIBILITY (fn
) = vis
;
3477 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3481 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3483 tree gp
= get_identifier ("_gp");
3484 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3486 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3490 unspec_got_name (int i
)
3494 case R_FRV_GOT12
: return "got12";
3495 case R_FRV_GOTHI
: return "gothi";
3496 case R_FRV_GOTLO
: return "gotlo";
3497 case R_FRV_FUNCDESC
: return "funcdesc";
3498 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3499 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3500 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3501 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3502 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3503 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3504 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3505 case R_FRV_GOTOFF12
: return "gotoff12";
3506 case R_FRV_GOTOFFHI
: return "gotoffhi";
3507 case R_FRV_GOTOFFLO
: return "gotofflo";
3508 case R_FRV_GPREL12
: return "gprel12";
3509 case R_FRV_GPRELHI
: return "gprelhi";
3510 case R_FRV_GPRELLO
: return "gprello";
3515 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3516 is added inside the relocation operator. */
3519 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3521 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3522 output_addr_const (stream
, plus_constant (unspec
->symbol
, unspec
->offset
));
3523 fputs (")", stream
);
3526 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3527 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3528 otherwise return ORIG_X. */
3531 frv_find_base_term (rtx x
)
3533 struct frv_unspec unspec
;
3535 if (frv_const_unspec_p (x
, &unspec
)
3536 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3537 return plus_constant (unspec
.symbol
, unspec
.offset
);
3542 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3543 the operand is used by a predicated instruction. */
3546 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3548 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3549 && GET_CODE (op
) == MEM
3550 && frv_legitimate_address_p (mode
, XEXP (op
, 0),
3551 reload_completed
, condexec_p
, FALSE
));
3555 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3557 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3558 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3564 rvrtx
= operands
[0];
3568 addr
= XEXP (operands
[0], 0);
3570 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3571 any calls that would involve a PLT, but can't tell, since we
3572 don't know whether an extern function is going to be provided by
3573 a separate translation unit or imported from a separate module.
3574 When compiling for shared libraries, if the function has default
3575 visibility, we assume it's overridable, so we inline the PLT, but
3576 for executables, we don't really have a way to make a good
3577 decision: a function is as likely to be imported from a shared
3578 library as it is to be defined in the executable itself. We
3579 assume executables will get global functions defined locally,
3580 whereas shared libraries will have them potentially overridden,
3581 so we only inline PLTs when compiling for shared libraries.
3583 In order to mark a function as local to a shared library, any
3584 non-default visibility attribute suffices. Unfortunately,
3585 there's no simple way to tag a function declaration as ``in a
3586 different module'', which we could then use to trigger PLT
3587 inlining on executables. There's -minline-plt, but it affects
3588 all external functions, so one would have to also mark function
3589 declarations available in the same module with non-default
3590 visibility, which is advantageous in itself. */
3591 if (GET_CODE (addr
) == SYMBOL_REF
3592 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3596 dest
= gen_reg_rtx (SImode
);
3598 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3599 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3601 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3602 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3604 cfun
->uses_pic_offset_table
= TRUE
;
3607 else if (GET_CODE (addr
) == SYMBOL_REF
)
3609 /* These are always either local, or handled through a local
3612 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3613 operands
[2], picreg
, lr
);
3615 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3619 else if (! ldd_address_operand (addr
, Pmode
))
3620 addr
= force_reg (Pmode
, addr
);
3622 picreg
= gen_reg_rtx (DImode
);
3623 emit_insn (gen_movdi_ldd (picreg
, addr
));
3625 if (sibcall
&& ret_value
)
3626 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3628 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3630 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3632 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3636 /* An address operand that may use a pair of registers, an addressing
3637 mode that we reject in general. */
3640 ldd_address_operand (rtx x
, enum machine_mode mode
)
3642 if (GET_MODE (x
) != mode
&& GET_MODE (x
) != VOIDmode
)
3645 return frv_legitimate_address_p (DImode
, x
, reload_completed
, FALSE
, TRUE
);
3649 fdpic_fptr_operand (rtx op
, enum machine_mode mode
)
3651 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3653 if (GET_CODE (op
) != REG
)
3655 if (REGNO (op
) != FDPIC_FPTR_REGNO
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
3660 /* Return 1 is OP is a memory operand, or will be turned into one by
3664 frv_load_operand (rtx op
, enum machine_mode mode
)
3666 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3669 if (reload_in_progress
)
3672 if (GET_CODE (tmp
) == SUBREG
)
3673 tmp
= SUBREG_REG (tmp
);
3674 if (GET_CODE (tmp
) == REG
3675 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
3676 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
3679 return op
&& memory_operand (op
, mode
);
3683 /* Return 1 if operand is a GPR register or a FPR register. */
3686 gpr_or_fpr_operand (rtx op
, enum machine_mode mode
)
3690 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3693 if (GET_CODE (op
) == SUBREG
)
3695 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3696 return register_operand (op
, mode
);
3698 op
= SUBREG_REG (op
);
3701 if (GET_CODE (op
) != REG
)
3705 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3711 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3714 gpr_or_int12_operand (rtx op
, enum machine_mode mode
)
3716 if (GET_CODE (op
) == CONST_INT
)
3717 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3719 if (got12_operand (op
, mode
))
3722 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3725 if (GET_CODE (op
) == SUBREG
)
3727 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3728 return register_operand (op
, mode
);
3730 op
= SUBREG_REG (op
);
3733 if (GET_CODE (op
) != REG
)
3736 return GPR_OR_PSEUDO_P (REGNO (op
));
3739 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3740 signed immediate. */
3743 gpr_fpr_or_int12_operand (rtx op
, enum machine_mode mode
)
3747 if (GET_CODE (op
) == CONST_INT
)
3748 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3750 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3753 if (GET_CODE (op
) == SUBREG
)
3755 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3756 return register_operand (op
, mode
);
3758 op
= SUBREG_REG (op
);
3761 if (GET_CODE (op
) != REG
)
3765 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3771 /* Return 1 if operand is a register or 6 bit signed immediate. */
3774 fpr_or_int6_operand (rtx op
, enum machine_mode mode
)
3776 if (GET_CODE (op
) == CONST_INT
)
3777 return IN_RANGE_P (INTVAL (op
), -32, 31);
3779 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3782 if (GET_CODE (op
) == SUBREG
)
3784 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3785 return register_operand (op
, mode
);
3787 op
= SUBREG_REG (op
);
3790 if (GET_CODE (op
) != REG
)
3793 return FPR_OR_PSEUDO_P (REGNO (op
));
3796 /* Return 1 if operand is a register or 10 bit signed immediate. */
3799 gpr_or_int10_operand (rtx op
, enum machine_mode mode
)
3801 if (GET_CODE (op
) == CONST_INT
)
3802 return IN_RANGE_P (INTVAL (op
), -512, 511);
3804 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3807 if (GET_CODE (op
) == SUBREG
)
3809 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3810 return register_operand (op
, mode
);
3812 op
= SUBREG_REG (op
);
3815 if (GET_CODE (op
) != REG
)
3818 return GPR_OR_PSEUDO_P (REGNO (op
));
3821 /* Return 1 if operand is a register or an integer immediate. */
3824 gpr_or_int_operand (rtx op
, enum machine_mode mode
)
3826 if (GET_CODE (op
) == CONST_INT
)
3829 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3832 if (GET_CODE (op
) == SUBREG
)
3834 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3835 return register_operand (op
, mode
);
3837 op
= SUBREG_REG (op
);
3840 if (GET_CODE (op
) != REG
)
3843 return GPR_OR_PSEUDO_P (REGNO (op
));
3846 /* Return 1 if operand is a 12 bit signed immediate. */
3849 int12_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3851 if (GET_CODE (op
) != CONST_INT
)
3854 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3857 /* Return 1 if operand is a 6 bit signed immediate. */
3860 int6_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3862 if (GET_CODE (op
) != CONST_INT
)
3865 return IN_RANGE_P (INTVAL (op
), -32, 31);
3868 /* Return 1 if operand is a 5 bit signed immediate. */
3871 int5_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3873 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), -16, 15);
3876 /* Return 1 if operand is a 5 bit unsigned immediate. */
3879 uint5_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3881 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 31);
3884 /* Return 1 if operand is a 4 bit unsigned immediate. */
3887 uint4_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3889 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 15);
3892 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3895 uint1_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3897 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 1);
3900 /* Return 1 if operand is an integer constant that takes 2 instructions
3901 to load up and can be split into sethi/setlo instructions.. */
3904 int_2word_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3906 HOST_WIDE_INT value
;
3910 switch (GET_CODE (op
))
3919 return (flag_pic
== 0);
3922 if (flag_pic
|| TARGET_FDPIC
)
3926 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
3928 return GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
;
3934 /* small data references are already 1 word */
3935 return (flag_pic
== 0) && (! SYMBOL_REF_SMALL_P (op
));
3938 return ! IN_RANGE_P (INTVAL (op
), -32768, 32767);
3941 if (GET_MODE (op
) == SFmode
)
3943 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
3944 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
3946 return ! IN_RANGE_P (value
, -32768, 32767);
3948 else if (GET_MODE (op
) == VOIDmode
)
3950 value
= CONST_DOUBLE_LOW (op
);
3951 return ! IN_RANGE_P (value
, -32768, 32767);
3959 /* Return 1 if operand is a 16 bit unsigned immediate. */
3962 uint16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3964 if (GET_CODE (op
) != CONST_INT
)
3967 return IN_RANGE_P (INTVAL (op
), 0, 0xffff);
3970 /* Return 1 if operand is an integer constant with the bottom 16 bits
3974 upper_int16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3976 if (GET_CODE (op
) != CONST_INT
)
3979 return ((INTVAL (op
) & 0xffff) == 0);
3982 /* Return true if operand is a GPR register. */
3985 integer_register_operand (rtx op
, enum machine_mode mode
)
3987 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3990 if (GET_CODE (op
) == SUBREG
)
3992 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3993 return register_operand (op
, mode
);
3995 op
= SUBREG_REG (op
);
3998 if (GET_CODE (op
) != REG
)
4001 return GPR_OR_PSEUDO_P (REGNO (op
));
4004 /* Return true if operand is a GPR register. Do not allow SUBREG's
4005 here, in order to prevent a combine bug. */
4008 gpr_no_subreg_operand (rtx op
, enum machine_mode mode
)
4010 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4013 if (GET_CODE (op
) != REG
)
4016 return GPR_OR_PSEUDO_P (REGNO (op
));
4019 /* Return true if operand is a FPR register. */
4022 fpr_operand (rtx op
, enum machine_mode mode
)
4024 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4027 if (GET_CODE (op
) == SUBREG
)
4029 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4030 return register_operand (op
, mode
);
4032 op
= SUBREG_REG (op
);
4035 if (GET_CODE (op
) != REG
)
4038 return FPR_OR_PSEUDO_P (REGNO (op
));
4041 /* Return true if operand is an even GPR or FPR register. */
4044 even_reg_operand (rtx op
, enum machine_mode mode
)
4048 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4051 if (GET_CODE (op
) == SUBREG
)
4053 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4054 return register_operand (op
, mode
);
4056 op
= SUBREG_REG (op
);
4059 if (GET_CODE (op
) != REG
)
4063 if (regno
>= FIRST_PSEUDO_REGISTER
)
4067 return (((regno
- GPR_FIRST
) & 1) == 0);
4070 return (((regno
- FPR_FIRST
) & 1) == 0);
4075 /* Return true if operand is an odd GPR register. */
4078 odd_reg_operand (rtx op
, enum machine_mode mode
)
4082 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4085 if (GET_CODE (op
) == SUBREG
)
4087 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4088 return register_operand (op
, mode
);
4090 op
= SUBREG_REG (op
);
4093 if (GET_CODE (op
) != REG
)
4097 /* Assume that reload will give us an even register. */
4098 if (regno
>= FIRST_PSEUDO_REGISTER
)
4102 return (((regno
- GPR_FIRST
) & 1) != 0);
4105 return (((regno
- FPR_FIRST
) & 1) != 0);
4110 /* Return true if operand is an even GPR register. */
4113 even_gpr_operand (rtx op
, enum machine_mode mode
)
4117 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4120 if (GET_CODE (op
) == SUBREG
)
4122 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4123 return register_operand (op
, mode
);
4125 op
= SUBREG_REG (op
);
4128 if (GET_CODE (op
) != REG
)
4132 if (regno
>= FIRST_PSEUDO_REGISTER
)
4135 if (! GPR_P (regno
))
4138 return (((regno
- GPR_FIRST
) & 1) == 0);
4141 /* Return true if operand is an odd GPR register. */
4144 odd_gpr_operand (rtx op
, enum machine_mode mode
)
4148 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4151 if (GET_CODE (op
) == SUBREG
)
4153 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4154 return register_operand (op
, mode
);
4156 op
= SUBREG_REG (op
);
4159 if (GET_CODE (op
) != REG
)
4163 /* Assume that reload will give us an even register. */
4164 if (regno
>= FIRST_PSEUDO_REGISTER
)
4167 if (! GPR_P (regno
))
4170 return (((regno
- GPR_FIRST
) & 1) != 0);
4173 /* Return true if operand is a quad aligned FPR register. */
4176 quad_fpr_operand (rtx op
, enum machine_mode mode
)
4180 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4183 if (GET_CODE (op
) == SUBREG
)
4185 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4186 return register_operand (op
, mode
);
4188 op
= SUBREG_REG (op
);
4191 if (GET_CODE (op
) != REG
)
4195 if (regno
>= FIRST_PSEUDO_REGISTER
)
4198 if (! FPR_P (regno
))
4201 return (((regno
- FPR_FIRST
) & 3) == 0);
4204 /* Return true if operand is an even FPR register. */
4207 even_fpr_operand (rtx op
, enum machine_mode mode
)
4211 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4214 if (GET_CODE (op
) == SUBREG
)
4216 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4217 return register_operand (op
, mode
);
4219 op
= SUBREG_REG (op
);
4222 if (GET_CODE (op
) != REG
)
4226 if (regno
>= FIRST_PSEUDO_REGISTER
)
4229 if (! FPR_P (regno
))
4232 return (((regno
- FPR_FIRST
) & 1) == 0);
4235 /* Return true if operand is an odd FPR register. */
4238 odd_fpr_operand (rtx op
, enum machine_mode mode
)
4242 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4245 if (GET_CODE (op
) == SUBREG
)
4247 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4248 return register_operand (op
, mode
);
4250 op
= SUBREG_REG (op
);
4253 if (GET_CODE (op
) != REG
)
4257 /* Assume that reload will give us an even register. */
4258 if (regno
>= FIRST_PSEUDO_REGISTER
)
4261 if (! FPR_P (regno
))
4264 return (((regno
- FPR_FIRST
) & 1) != 0);
4267 /* Return true if operand is a 2 word memory address that can be loaded in one
4268 instruction to load or store. We assume the stack and frame pointers are
4269 suitably aligned, and variables in the small data area. FIXME -- at some we
4270 should recognize other globals and statics. We can't assume that any old
4271 pointer is aligned, given that arguments could be passed on an odd word on
4272 the stack and the address taken and passed through to another function. */
4275 dbl_memory_one_insn_operand (rtx op
, enum machine_mode mode
)
4283 if (GET_CODE (op
) != MEM
)
4286 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4289 addr
= XEXP (op
, 0);
4290 if (GET_CODE (addr
) == REG
)
4293 else if (GET_CODE (addr
) == PLUS
)
4295 rtx addr0
= XEXP (addr
, 0);
4296 rtx addr1
= XEXP (addr
, 1);
4298 if (GET_CODE (addr0
) != REG
)
4301 if (got12_operand (addr1
, VOIDmode
))
4304 if (GET_CODE (addr1
) != CONST_INT
)
4307 if ((INTVAL (addr1
) & 7) != 0)
4316 if (addr_reg
== frame_pointer_rtx
|| addr_reg
== stack_pointer_rtx
)
4322 /* Return true if operand is a 2 word memory address that needs to
4323 use two instructions to load or store. */
4326 dbl_memory_two_insn_operand (rtx op
, enum machine_mode mode
)
4328 if (GET_CODE (op
) != MEM
)
4331 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4337 return ! dbl_memory_one_insn_operand (op
, mode
);
4340 /* Return true if operand is something that can be an output for a move
4344 move_destination_operand (rtx op
, enum machine_mode mode
)
4349 switch (GET_CODE (op
))
4355 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4358 subreg
= SUBREG_REG (op
);
4359 code
= GET_CODE (subreg
);
4361 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4362 reload_completed
, FALSE
, FALSE
);
4364 return (code
== REG
);
4367 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4373 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4376 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4382 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4383 process these separately from any offsets, such that we add any
4384 offsets to the function descriptor (the actual pointer), not to the
4385 function address. */
4388 frv_function_symbol_referenced_p (rtx x
)
4394 if (GET_CODE (x
) == SYMBOL_REF
)
4395 return SYMBOL_REF_FUNCTION_P (x
);
4397 length
= GET_RTX_LENGTH (GET_CODE (x
));
4398 format
= GET_RTX_FORMAT (GET_CODE (x
));
4400 for (j
= 0; j
< length
; ++j
)
4405 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
4411 if (XVEC (x
, j
) != 0)
4414 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
4415 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
4421 /* Nothing to do. */
4429 /* Return true if operand is something that can be an input for a move
4433 move_source_operand (rtx op
, enum machine_mode mode
)
4438 switch (GET_CODE (op
))
4445 return immediate_operand (op
, mode
);
4448 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4451 subreg
= SUBREG_REG (op
);
4452 code
= GET_CODE (subreg
);
4454 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4455 reload_completed
, FALSE
, FALSE
);
4457 return (code
== REG
);
4460 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4466 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4469 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4475 /* Return true if operand is something that can be an output for a conditional
4479 condexec_dest_operand (rtx op
, enum machine_mode mode
)
4484 switch (GET_CODE (op
))
4490 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4493 subreg
= SUBREG_REG (op
);
4494 code
= GET_CODE (subreg
);
4496 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4497 reload_completed
, TRUE
, FALSE
);
4499 return (code
== REG
);
4502 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4508 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4511 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4517 /* Return true if operand is something that can be an input for a conditional
4521 condexec_source_operand (rtx op
, enum machine_mode mode
)
4526 switch (GET_CODE (op
))
4536 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4539 subreg
= SUBREG_REG (op
);
4540 code
= GET_CODE (subreg
);
4542 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4543 reload_completed
, TRUE
, FALSE
);
4545 return (code
== REG
);
4548 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4554 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4557 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4563 /* Return true if operand is a register of any flavor or a 0 of the
4564 appropriate type. */
4567 reg_or_0_operand (rtx op
, enum machine_mode mode
)
4569 switch (GET_CODE (op
))
4576 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4579 return register_operand (op
, mode
);
4589 /* Return true if operand is the link register. */
4592 lr_operand (rtx op
, enum machine_mode mode
)
4594 if (GET_CODE (op
) != REG
)
4597 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4600 if (REGNO (op
) != LR_REGNO
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
4606 /* Return true if operand is the uClinux PIC register. */
4609 fdpic_operand (rtx op
, enum machine_mode mode
)
4614 if (GET_CODE (op
) != REG
)
4617 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4620 if (REGNO (op
) != FDPIC_REGNO
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
4627 got12_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4629 struct frv_unspec unspec
;
4631 if (frv_const_unspec_p (op
, &unspec
))
4632 switch (unspec
.reloc
)
4635 case R_FRV_GOTOFF12
:
4636 case R_FRV_FUNCDESC_GOT12
:
4637 case R_FRV_FUNCDESC_GOTOFF12
:
4644 /* Return true if OP is a valid const-unspec expression. */
4647 const_unspec_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4649 struct frv_unspec unspec
;
4651 return frv_const_unspec_p (op
, &unspec
);
4653 /* Return true if operand is a gpr register or a valid memory operation. */
4656 gpr_or_memory_operand (rtx op
, enum machine_mode mode
)
4658 return (integer_register_operand (op
, mode
)
4659 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4662 /* Return true if operand is a fpr register or a valid memory operation. */
4665 fpr_or_memory_operand (rtx op
, enum machine_mode mode
)
4667 return (fpr_operand (op
, mode
)
4668 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4671 /* Return true if operand is an icc register. */
4674 icc_operand (rtx op
, enum machine_mode mode
)
4678 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4681 if (GET_CODE (op
) != REG
)
4685 return ICC_OR_PSEUDO_P (regno
);
4688 /* Return true if operand is an fcc register. */
4691 fcc_operand (rtx op
, enum machine_mode mode
)
4695 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4698 if (GET_CODE (op
) != REG
)
4702 return FCC_OR_PSEUDO_P (regno
);
4705 /* Return true if operand is either an fcc or icc register. */
4708 cc_operand (rtx op
, enum machine_mode mode
)
4712 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4715 if (GET_CODE (op
) != REG
)
4719 if (CC_OR_PSEUDO_P (regno
))
4725 /* Return true if operand is an integer CCR register. */
4728 icr_operand (rtx op
, enum machine_mode mode
)
4732 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4735 if (GET_CODE (op
) != REG
)
4739 return ICR_OR_PSEUDO_P (regno
);
4742 /* Return true if operand is an fcc register. */
4745 fcr_operand (rtx op
, enum machine_mode mode
)
4749 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4752 if (GET_CODE (op
) != REG
)
4756 return FCR_OR_PSEUDO_P (regno
);
4759 /* Return true if operand is either an fcc or icc register. */
4762 cr_operand (rtx op
, enum machine_mode mode
)
4766 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4769 if (GET_CODE (op
) != REG
)
4773 if (CR_OR_PSEUDO_P (regno
))
4779 /* Return true if operand is a memory reference suitable for a call. */
4782 call_operand (rtx op
, enum machine_mode mode
)
4784 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
&& GET_CODE (op
) != CONST_INT
)
4787 if (GET_CODE (op
) == SYMBOL_REF
)
4790 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4791 never occur anyway), but prevents reload from not handling the case
4792 properly of a call through a pointer on a function that calls
4793 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4794 return gpr_or_int12_operand (op
, mode
);
4797 /* Return true if operand is a memory reference suitable for a sibcall. */
4800 sibcall_operand (rtx op
, enum machine_mode mode
)
4802 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
&& GET_CODE (op
) != CONST_INT
)
4805 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4806 never occur anyway), but prevents reload from not handling the case
4807 properly of a call through a pointer on a function that calls
4808 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4809 return gpr_or_int12_operand (op
, mode
);
4812 /* Return true if operator is a kind of relational operator. */
4815 relational_operator (rtx op
, enum machine_mode mode
)
4821 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4824 switch (GET_CODE (op
))
4843 if (op1
!= const0_rtx
)
4847 if (GET_CODE (op0
) != REG
)
4850 regno
= REGNO (op0
);
4851 switch (GET_MODE (op0
))
4858 return ICC_OR_PSEUDO_P (regno
);
4861 return FCC_OR_PSEUDO_P (regno
);
4864 return CR_OR_PSEUDO_P (regno
);
4870 /* Return true if operator is a signed integer relational operator. */
4873 signed_relational_operator (rtx op
, enum machine_mode mode
)
4879 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4882 switch (GET_CODE (op
))
4897 if (op1
!= const0_rtx
)
4901 if (GET_CODE (op0
) != REG
)
4904 regno
= REGNO (op0
);
4905 if (GET_MODE (op0
) == CCmode
&& ICC_OR_PSEUDO_P (regno
))
4908 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4914 /* Return true if operator is a signed integer relational operator. */
4917 unsigned_relational_operator (rtx op
, enum machine_mode mode
)
4923 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4926 switch (GET_CODE (op
))
4939 if (op1
!= const0_rtx
)
4943 if (GET_CODE (op0
) != REG
)
4946 regno
= REGNO (op0
);
4947 if (GET_MODE (op0
) == CC_UNSmode
&& ICC_OR_PSEUDO_P (regno
))
4950 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4956 /* Return true if operator is a floating point relational operator. */
4959 float_relational_operator (rtx op
, enum machine_mode mode
)
4965 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4968 switch (GET_CODE (op
))
4987 if (op1
!= const0_rtx
)
4991 if (GET_CODE (op0
) != REG
)
4994 regno
= REGNO (op0
);
4995 if (GET_MODE (op0
) == CC_FPmode
&& FCC_OR_PSEUDO_P (regno
))
4998 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
5004 /* Return true if operator is EQ/NE of a conditional execution register. */
5007 ccr_eqne_operator (rtx op
, enum machine_mode mode
)
5009 enum machine_mode op_mode
= GET_MODE (op
);
5014 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5017 switch (GET_CODE (op
))
5028 if (op1
!= const0_rtx
)
5032 if (GET_CODE (op0
) != REG
)
5035 regno
= REGNO (op0
);
5036 if (op_mode
== CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
5042 /* Return true if operator is a minimum or maximum operator (both signed and
5046 minmax_operator (rtx op
, enum machine_mode mode
)
5048 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
5051 switch (GET_CODE (op
))
5063 if (! integer_register_operand (XEXP (op
, 0), mode
))
5066 if (! gpr_or_int10_operand (XEXP (op
, 1), mode
))
5072 /* Return true if operator is an integer binary operator that can executed
5073 conditionally and takes 1 cycle. */
5076 condexec_si_binary_operator (rtx op
, enum machine_mode mode
)
5078 enum machine_mode op_mode
= GET_MODE (op
);
5080 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5083 switch (GET_CODE (op
))
5100 /* Return true if operator is an integer binary operator that can be
5101 executed conditionally by a media instruction. */
5104 condexec_si_media_operator (rtx op
, enum machine_mode mode
)
5106 enum machine_mode op_mode
= GET_MODE (op
);
5108 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5111 switch (GET_CODE (op
))
5123 /* Return true if operator is an integer division operator that can executed
5127 condexec_si_divide_operator (rtx op
, enum machine_mode mode
)
5129 enum machine_mode op_mode
= GET_MODE (op
);
5131 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5134 switch (GET_CODE (op
))
5145 /* Return true if operator is an integer unary operator that can executed
5149 condexec_si_unary_operator (rtx op
, enum machine_mode mode
)
5151 enum machine_mode op_mode
= GET_MODE (op
);
5153 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5156 switch (GET_CODE (op
))
5167 /* Return true if operator is a conversion-type expression that can be
5168 evaluated conditionally by floating-point instructions. */
5171 condexec_sf_conv_operator (rtx op
, enum machine_mode mode
)
5173 enum machine_mode op_mode
= GET_MODE (op
);
5175 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5178 switch (GET_CODE (op
))
5189 /* Return true if operator is an addition or subtraction expression.
5190 Such expressions can be evaluated conditionally by floating-point
5194 condexec_sf_add_operator (rtx op
, enum machine_mode mode
)
5196 enum machine_mode op_mode
= GET_MODE (op
);
5198 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5201 switch (GET_CODE (op
))
5212 /* Return true if the memory operand is one that can be conditionally
5216 condexec_memory_operand (rtx op
, enum machine_mode mode
)
5218 enum machine_mode op_mode
= GET_MODE (op
);
5221 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5236 if (GET_CODE (op
) != MEM
)
5239 addr
= XEXP (op
, 0);
5240 if (GET_CODE (addr
) == ADDRESSOF
)
5243 return frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
, FALSE
);
5246 /* Return true if operator is an integer binary operator that can be combined
5247 with a setcc operation. Do not allow the arithmetic operations that could
5248 potentially overflow since the FR-V sets the condition code based on the
5249 "true" value of the result, not the result after truncating to a 32-bit
5253 intop_compare_operator (rtx op
, enum machine_mode mode
)
5255 enum machine_mode op_mode
= GET_MODE (op
);
5257 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5260 switch (GET_CODE (op
))
5273 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5276 if (! gpr_or_int10_operand (XEXP (op
, 1), SImode
))
5282 /* Return true if operator is an integer binary operator that can be combined
5283 with a setcc operation inside of a conditional execution. */
5286 condexec_intop_cmp_operator (rtx op
, enum machine_mode mode
)
5288 enum machine_mode op_mode
= GET_MODE (op
);
5290 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5293 switch (GET_CODE (op
))
5306 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5309 if (! integer_register_operand (XEXP (op
, 1), SImode
))
5315 /* Return 1 if operand is a valid ACC register number. */
5318 acc_operand (rtx op
, enum machine_mode mode
)
5322 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5325 if (GET_CODE (op
) == SUBREG
)
5327 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5328 return register_operand (op
, mode
);
5330 op
= SUBREG_REG (op
);
5333 if (GET_CODE (op
) != REG
)
5337 return ACC_OR_PSEUDO_P (regno
);
5340 /* Return 1 if operand is a valid even ACC register number. */
5343 even_acc_operand (rtx op
, enum machine_mode mode
)
5347 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5350 if (GET_CODE (op
) == SUBREG
)
5352 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5353 return register_operand (op
, mode
);
5355 op
= SUBREG_REG (op
);
5358 if (GET_CODE (op
) != REG
)
5362 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 1) == 0);
5365 /* Return 1 if operand is zero or four. */
5368 quad_acc_operand (rtx op
, enum machine_mode mode
)
5372 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5375 if (GET_CODE (op
) == SUBREG
)
5377 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5378 return register_operand (op
, mode
);
5380 op
= SUBREG_REG (op
);
5383 if (GET_CODE (op
) != REG
)
5387 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 3) == 0);
5390 /* Return 1 if operand is a valid ACCG register number. */
5393 accg_operand (rtx op
, enum machine_mode mode
)
5395 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5398 if (GET_CODE (op
) == SUBREG
)
5400 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5401 return register_operand (op
, mode
);
5403 op
= SUBREG_REG (op
);
5406 if (GET_CODE (op
) != REG
)
5409 return ACCG_OR_PSEUDO_P (REGNO (op
));
5413 /* Return true if the bare return instruction can be used outside of the
5414 epilog code. For frv, we only do it if there was no stack allocation. */
5417 direct_return_p (void)
5421 if (!reload_completed
)
5424 info
= frv_stack_info ();
5425 return (info
->total_size
== 0);
5429 /* Emit code to handle a MOVSI, adding in the small data register or pic
5430 register if needed to load up addresses. Return TRUE if the appropriate
5431 instructions are emitted. */
5434 frv_emit_movsi (rtx dest
, rtx src
)
5436 int base_regno
= -1;
5439 struct frv_unspec old_unspec
;
5441 if (!reload_in_progress
5442 && !reload_completed
5443 && !register_operand (dest
, SImode
)
5444 && (!reg_or_0_operand (src
, SImode
)
5445 /* Virtual registers will almost always be replaced by an
5446 add instruction, so expose this to CSE by copying to
5447 an intermediate register. */
5448 || (GET_CODE (src
) == REG
5449 && IN_RANGE_P (REGNO (src
),
5450 FIRST_VIRTUAL_REGISTER
,
5451 LAST_VIRTUAL_REGISTER
))))
5453 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
5457 /* Explicitly add in the PIC or small data register if needed. */
5458 switch (GET_CODE (src
))
5467 /* Using GPREL12, we use a single GOT entry for all symbols
5468 in read-only sections, but trade sequences such as:
5470 sethi #gothi(label), gr#
5471 setlo #gotlo(label), gr#
5476 ld @(gr15,#got12(_gp)), gr#
5477 sethi #gprelhi(label), gr##
5478 setlo #gprello(label), gr##
5481 We may often be able to share gr# for multiple
5482 computations of GPREL addresses, and we may often fold
5483 the final add into the pair of registers of a load or
5484 store instruction, so it's often profitable. Even when
5485 optimizing for size, we're trading a GOT entry for an
5486 additional instruction, which trades GOT space
5487 (read-write) for code size (read-only, shareable), as
5488 long as the symbol is not used in more than two different
5491 With -fpie/-fpic, we'd be trading a single load for a
5492 sequence of 4 instructions, because the offset of the
5493 label can't be assumed to be addressable with 12 bits, so
5494 we don't do this. */
5495 if (TARGET_GPREL_RO
)
5496 unspec
= R_FRV_GPREL12
;
5498 unspec
= R_FRV_GOT12
;
5501 base_regno
= PIC_REGNO
;
5506 if (frv_const_unspec_p (src
, &old_unspec
))
5509 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
5512 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
5513 emit_move_insn (dest
, src
);
5518 sym
= XEXP (sym
, 0);
5519 if (GET_CODE (sym
) == PLUS
5520 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
5521 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
5522 sym
= XEXP (sym
, 0);
5523 if (GET_CODE (sym
) == SYMBOL_REF
)
5525 else if (GET_CODE (sym
) == LABEL_REF
)
5528 goto handle_whatever
;
5536 if (SYMBOL_REF_FUNCTION_P (sym
))
5538 if (frv_local_funcdesc_p (sym
))
5539 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
5541 unspec
= R_FRV_FUNCDESC_GOT12
;
5545 if (CONSTANT_POOL_ADDRESS_P (sym
))
5546 switch (GET_CODE (get_pool_constant (sym
)))
5553 unspec
= R_FRV_GOTOFF12
;
5558 if (TARGET_GPREL_RO
)
5559 unspec
= R_FRV_GPREL12
;
5561 unspec
= R_FRV_GOT12
;
5564 else if (SYMBOL_REF_LOCAL_P (sym
)
5565 && !SYMBOL_REF_EXTERNAL_P (sym
)
5566 && SYMBOL_REF_DECL (sym
)
5567 && (!DECL_P (SYMBOL_REF_DECL (sym
))
5568 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
5570 tree decl
= SYMBOL_REF_DECL (sym
);
5571 tree init
= TREE_CODE (decl
) == VAR_DECL
5572 ? DECL_INITIAL (decl
)
5573 : TREE_CODE (decl
) == CONSTRUCTOR
5576 bool named_section
, readonly
;
5578 if (init
&& init
!= error_mark_node
)
5579 reloc
= compute_reloc_for_constant (init
);
5581 named_section
= TREE_CODE (decl
) == VAR_DECL
5582 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
5583 readonly
= decl_readonly_section (decl
, reloc
);
5586 unspec
= R_FRV_GOT12
;
5588 unspec
= R_FRV_GOTOFF12
;
5589 else if (readonly
&& TARGET_GPREL_RO
)
5590 unspec
= R_FRV_GPREL12
;
5592 unspec
= R_FRV_GOT12
;
5595 unspec
= R_FRV_GOT12
;
5599 else if (SYMBOL_REF_SMALL_P (sym
))
5600 base_regno
= SDA_BASE_REG
;
5603 base_regno
= PIC_REGNO
;
5608 if (base_regno
>= 0)
5610 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
5611 emit_insn (gen_symGOTOFF2reg (dest
, src
,
5612 gen_rtx_REG (Pmode
, base_regno
),
5613 GEN_INT (R_FRV_GPREL12
)));
5615 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
5616 gen_rtx_REG (Pmode
, base_regno
),
5617 GEN_INT (R_FRV_GPREL12
)));
5618 if (base_regno
== PIC_REGNO
)
5619 cfun
->uses_pic_offset_table
= TRUE
;
5627 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5628 new uses of it once reload has begun. */
5629 if (reload_in_progress
|| reload_completed
)
5634 case R_FRV_GOTOFF12
:
5635 if (!frv_small_data_reloc_p (sym
, unspec
))
5636 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
5639 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
5642 if (!frv_small_data_reloc_p (sym
, unspec
))
5643 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
5646 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
5648 case R_FRV_FUNCDESC_GOTOFF12
:
5650 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
5653 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
5657 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
5660 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
5664 cfun
->uses_pic_offset_table
= TRUE
;
5673 /* Return a string to output a single word move. */
5676 output_move_single (rtx operands
[], rtx insn
)
5678 rtx dest
= operands
[0];
5679 rtx src
= operands
[1];
5681 if (GET_CODE (dest
) == REG
)
5683 int dest_regno
= REGNO (dest
);
5684 enum machine_mode mode
= GET_MODE (dest
);
5686 if (GPR_P (dest_regno
))
5688 if (GET_CODE (src
) == REG
)
5690 /* gpr <- some sort of register */
5691 int src_regno
= REGNO (src
);
5693 if (GPR_P (src_regno
))
5694 return "mov %1, %0";
5696 else if (FPR_P (src_regno
))
5697 return "movfg %1, %0";
5699 else if (SPR_P (src_regno
))
5700 return "movsg %1, %0";
5703 else if (GET_CODE (src
) == MEM
)
5712 return "ldsb%I1%U1 %M1,%0";
5715 return "ldsh%I1%U1 %M1,%0";
5719 return "ld%I1%U1 %M1, %0";
5723 else if (GET_CODE (src
) == CONST_INT
5724 || GET_CODE (src
) == CONST_DOUBLE
)
5726 /* gpr <- integer/floating constant */
5727 HOST_WIDE_INT value
;
5729 if (GET_CODE (src
) == CONST_INT
)
5730 value
= INTVAL (src
);
5732 else if (mode
== SFmode
)
5737 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
5738 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5743 value
= CONST_DOUBLE_LOW (src
);
5745 if (IN_RANGE_P (value
, -32768, 32767))
5746 return "setlos %1, %0";
5751 else if (GET_CODE (src
) == SYMBOL_REF
5752 || GET_CODE (src
) == LABEL_REF
5753 || GET_CODE (src
) == CONST
)
5759 else if (FPR_P (dest_regno
))
5761 if (GET_CODE (src
) == REG
)
5763 /* fpr <- some sort of register */
5764 int src_regno
= REGNO (src
);
5766 if (GPR_P (src_regno
))
5767 return "movgf %1, %0";
5769 else if (FPR_P (src_regno
))
5771 if (TARGET_HARD_FLOAT
)
5772 return "fmovs %1, %0";
5774 return "mor %1, %1, %0";
5778 else if (GET_CODE (src
) == MEM
)
5787 return "ldbf%I1%U1 %M1,%0";
5790 return "ldhf%I1%U1 %M1,%0";
5794 return "ldf%I1%U1 %M1, %0";
5798 else if (ZERO_P (src
))
5799 return "movgf %., %0";
5802 else if (SPR_P (dest_regno
))
5804 if (GET_CODE (src
) == REG
)
5806 /* spr <- some sort of register */
5807 int src_regno
= REGNO (src
);
5809 if (GPR_P (src_regno
))
5810 return "movgs %1, %0";
5815 else if (GET_CODE (dest
) == MEM
)
5817 if (GET_CODE (src
) == REG
)
5819 int src_regno
= REGNO (src
);
5820 enum machine_mode mode
= GET_MODE (dest
);
5822 if (GPR_P (src_regno
))
5830 return "stb%I0%U0 %1, %M0";
5833 return "sth%I0%U0 %1, %M0";
5837 return "st%I0%U0 %1, %M0";
5841 else if (FPR_P (src_regno
))
5849 return "stbf%I0%U0 %1, %M0";
5852 return "sthf%I0%U0 %1, %M0";
5856 return "stf%I0%U0 %1, %M0";
5861 else if (ZERO_P (src
))
5863 switch (GET_MODE (dest
))
5869 return "stb%I0%U0 %., %M0";
5872 return "sth%I0%U0 %., %M0";
5876 return "st%I0%U0 %., %M0";
5881 fatal_insn ("Bad output_move_single operand", insn
);
5886 /* Return a string to output a double word move. */
5889 output_move_double (rtx operands
[], rtx insn
)
5891 rtx dest
= operands
[0];
5892 rtx src
= operands
[1];
5893 enum machine_mode mode
= GET_MODE (dest
);
5895 if (GET_CODE (dest
) == REG
)
5897 int dest_regno
= REGNO (dest
);
5899 if (GPR_P (dest_regno
))
5901 if (GET_CODE (src
) == REG
)
5903 /* gpr <- some sort of register */
5904 int src_regno
= REGNO (src
);
5906 if (GPR_P (src_regno
))
5909 else if (FPR_P (src_regno
))
5911 if (((dest_regno
- GPR_FIRST
) & 1) == 0
5912 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5913 return "movfgd %1, %0";
5919 else if (GET_CODE (src
) == MEM
)
5922 if (dbl_memory_one_insn_operand (src
, mode
))
5923 return "ldd%I1%U1 %M1, %0";
5928 else if (GET_CODE (src
) == CONST_INT
5929 || GET_CODE (src
) == CONST_DOUBLE
)
5933 else if (FPR_P (dest_regno
))
5935 if (GET_CODE (src
) == REG
)
5937 /* fpr <- some sort of register */
5938 int src_regno
= REGNO (src
);
5940 if (GPR_P (src_regno
))
5942 if (((dest_regno
- FPR_FIRST
) & 1) == 0
5943 && ((src_regno
- GPR_FIRST
) & 1) == 0)
5944 return "movgfd %1, %0";
5949 else if (FPR_P (src_regno
))
5952 && ((dest_regno
- FPR_FIRST
) & 1) == 0
5953 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5954 return "fmovd %1, %0";
5960 else if (GET_CODE (src
) == MEM
)
5963 if (dbl_memory_one_insn_operand (src
, mode
))
5964 return "lddf%I1%U1 %M1, %0";
5969 else if (ZERO_P (src
))
5974 else if (GET_CODE (dest
) == MEM
)
5976 if (GET_CODE (src
) == REG
)
5978 int src_regno
= REGNO (src
);
5980 if (GPR_P (src_regno
))
5982 if (((src_regno
- GPR_FIRST
) & 1) == 0
5983 && dbl_memory_one_insn_operand (dest
, mode
))
5984 return "std%I0%U0 %1, %M0";
5989 if (FPR_P (src_regno
))
5991 if (((src_regno
- FPR_FIRST
) & 1) == 0
5992 && dbl_memory_one_insn_operand (dest
, mode
))
5993 return "stdf%I0%U0 %1, %M0";
5999 else if (ZERO_P (src
))
6001 if (dbl_memory_one_insn_operand (dest
, mode
))
6002 return "std%I0%U0 %., %M0";
6008 fatal_insn ("Bad output_move_double operand", insn
);
6013 /* Return a string to output a single word conditional move.
6014 Operand0 -- EQ/NE of ccr register and 0
6015 Operand1 -- CCR register
6016 Operand2 -- destination
6017 Operand3 -- source */
6020 output_condmove_single (rtx operands
[], rtx insn
)
6022 rtx dest
= operands
[2];
6023 rtx src
= operands
[3];
6025 if (GET_CODE (dest
) == REG
)
6027 int dest_regno
= REGNO (dest
);
6028 enum machine_mode mode
= GET_MODE (dest
);
6030 if (GPR_P (dest_regno
))
6032 if (GET_CODE (src
) == REG
)
6034 /* gpr <- some sort of register */
6035 int src_regno
= REGNO (src
);
6037 if (GPR_P (src_regno
))
6038 return "cmov %z3, %2, %1, %e0";
6040 else if (FPR_P (src_regno
))
6041 return "cmovfg %3, %2, %1, %e0";
6044 else if (GET_CODE (src
) == MEM
)
6053 return "cldsb%I3%U3 %M3, %2, %1, %e0";
6056 return "cldsh%I3%U3 %M3, %2, %1, %e0";
6060 return "cld%I3%U3 %M3, %2, %1, %e0";
6064 else if (ZERO_P (src
))
6065 return "cmov %., %2, %1, %e0";
6068 else if (FPR_P (dest_regno
))
6070 if (GET_CODE (src
) == REG
)
6072 /* fpr <- some sort of register */
6073 int src_regno
= REGNO (src
);
6075 if (GPR_P (src_regno
))
6076 return "cmovgf %3, %2, %1, %e0";
6078 else if (FPR_P (src_regno
))
6080 if (TARGET_HARD_FLOAT
)
6081 return "cfmovs %3,%2,%1,%e0";
6083 return "cmor %3, %3, %2, %1, %e0";
6087 else if (GET_CODE (src
) == MEM
)
6090 if (mode
== SImode
|| mode
== SFmode
)
6091 return "cldf%I3%U3 %M3, %2, %1, %e0";
6094 else if (ZERO_P (src
))
6095 return "cmovgf %., %2, %1, %e0";
6099 else if (GET_CODE (dest
) == MEM
)
6101 if (GET_CODE (src
) == REG
)
6103 int src_regno
= REGNO (src
);
6104 enum machine_mode mode
= GET_MODE (dest
);
6106 if (GPR_P (src_regno
))
6114 return "cstb%I2%U2 %3, %M2, %1, %e0";
6117 return "csth%I2%U2 %3, %M2, %1, %e0";
6121 return "cst%I2%U2 %3, %M2, %1, %e0";
6125 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
6126 return "cstf%I2%U2 %3, %M2, %1, %e0";
6129 else if (ZERO_P (src
))
6131 enum machine_mode mode
= GET_MODE (dest
);
6138 return "cstb%I2%U2 %., %M2, %1, %e0";
6141 return "csth%I2%U2 %., %M2, %1, %e0";
6145 return "cst%I2%U2 %., %M2, %1, %e0";
6150 fatal_insn ("Bad output_condmove_single operand", insn
);
6155 /* Emit the appropriate code to do a comparison, returning the register the
6156 comparison was done it. */
6159 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
6161 enum machine_mode cc_mode
;
6164 /* Floating point doesn't have comparison against a constant. */
6165 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
6166 op1
= force_reg (GET_MODE (op0
), op1
);
6168 /* Possibly disable using anything but a fixed register in order to work
6169 around cse moving comparisons past function calls. */
6170 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
6171 cc_reg
= ((TARGET_ALLOC_CC
)
6172 ? gen_reg_rtx (cc_mode
)
6173 : gen_rtx_REG (cc_mode
,
6174 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
6176 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6177 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
6183 /* Emit code for a conditional branch. The comparison operands were previously
6184 stored in frv_compare_op0 and frv_compare_op1.
6186 XXX: I originally wanted to add a clobber of a CCR register to use in
6187 conditional execution, but that confuses the rest of the compiler. */
6190 frv_emit_cond_branch (enum rtx_code test
, rtx label
)
6195 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6196 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
6198 /* Branches generate:
6200 (if_then_else (<test>, <cc_reg>, (const_int 0))
6201 (label_ref <branch_label>)
6203 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, label
);
6204 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
6205 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
6206 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
6211 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6212 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6215 frv_emit_scc (enum rtx_code test
, rtx target
)
6221 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6223 /* SCC instructions generate:
6224 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6225 (clobber (<ccr_reg>))]) */
6226 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
6227 set
= gen_rtx_SET (VOIDmode
, target
, test_rtx
);
6229 cr_reg
= ((TARGET_ALLOC_CC
)
6230 ? gen_reg_rtx (CC_CCRmode
)
6231 : gen_rtx_REG (CC_CCRmode
,
6232 ((GET_MODE (cc_reg
) == CC_FPmode
)
6236 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
6237 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
6242 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6243 the separate insns. */
6246 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
6252 /* Set the appropriate CCR bit. */
6253 emit_insn (gen_rtx_SET (VOIDmode
,
6255 gen_rtx_fmt_ee (GET_CODE (test
),
6260 /* Move the value into the destination. */
6261 emit_move_insn (dest
, GEN_INT (value
));
6263 /* Move 0 into the destination if the test failed */
6264 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6265 gen_rtx_EQ (GET_MODE (cr_reg
),
6268 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
6270 /* Finish up, return sequence. */
6277 /* Emit the code for a conditional move, return TRUE if we could do the
6281 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
6288 enum rtx_code test
= GET_CODE (test_rtx
);
6289 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6290 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
6292 /* Conditional move instructions generate:
6293 (parallel [(set <target>
6294 (if_then_else (<test> <cc_reg> (const_int 0))
6297 (clobber (<ccr_reg>))]) */
6299 /* Handle various cases of conditional move involving two constants. */
6300 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
6302 HOST_WIDE_INT value1
= INTVAL (src1
);
6303 HOST_WIDE_INT value2
= INTVAL (src2
);
6305 /* Having 0 as one of the constants can be done by loading the other
6306 constant, and optionally moving in gr0. */
6307 if (value1
== 0 || value2
== 0)
6310 /* If the first value is within an addi range and also the difference
6311 between the two fits in an addi's range, load up the difference, then
6312 conditionally move in 0, and then unconditionally add the first
6314 else if (IN_RANGE_P (value1
, -2048, 2047)
6315 && IN_RANGE_P (value2
- value1
, -2048, 2047))
6318 /* If neither condition holds, just force the constant into a
6322 src1
= force_reg (GET_MODE (dest
), src1
);
6323 src2
= force_reg (GET_MODE (dest
), src2
);
6327 /* If one value is a register, insure the other value is either 0 or a
6331 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
6332 src1
= force_reg (GET_MODE (dest
), src1
);
6334 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6335 src2
= force_reg (GET_MODE (dest
), src2
);
6338 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
6339 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
6341 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
6343 cr_reg
= ((TARGET_ALLOC_CC
)
6344 ? gen_reg_rtx (CC_CCRmode
)
6345 : gen_rtx_REG (CC_CCRmode
,
6346 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
6348 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
6349 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
6354 /* Split a conditional move into constituent parts, returning a SEQUENCE
6355 containing all of the insns. */
6358 frv_split_cond_move (rtx operands
[])
6360 rtx dest
= operands
[0];
6361 rtx test
= operands
[1];
6362 rtx cc_reg
= operands
[2];
6363 rtx src1
= operands
[3];
6364 rtx src2
= operands
[4];
6365 rtx cr_reg
= operands
[5];
6367 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6371 /* Set the appropriate CCR bit. */
6372 emit_insn (gen_rtx_SET (VOIDmode
,
6374 gen_rtx_fmt_ee (GET_CODE (test
),
6379 /* Handle various cases of conditional move involving two constants. */
6380 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
6382 HOST_WIDE_INT value1
= INTVAL (src1
);
6383 HOST_WIDE_INT value2
= INTVAL (src2
);
6385 /* Having 0 as one of the constants can be done by loading the other
6386 constant, and optionally moving in gr0. */
6389 emit_move_insn (dest
, src2
);
6390 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6391 gen_rtx_NE (cr_mode
, cr_reg
,
6393 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6396 else if (value2
== 0)
6398 emit_move_insn (dest
, src1
);
6399 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6400 gen_rtx_EQ (cr_mode
, cr_reg
,
6402 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6405 /* If the first value is within an addi range and also the difference
6406 between the two fits in an addi's range, load up the difference, then
6407 conditionally move in 0, and then unconditionally add the first
6409 else if (IN_RANGE_P (value1
, -2048, 2047)
6410 && IN_RANGE_P (value2
- value1
, -2048, 2047))
6412 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
6414 : gen_rtx_SUBREG (SImode
, dest
, 0));
6416 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
6417 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6418 gen_rtx_NE (cr_mode
, cr_reg
,
6420 gen_rtx_SET (VOIDmode
, dest_si
,
6422 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
6430 /* Emit the conditional move for the test being true if needed. */
6431 if (! rtx_equal_p (dest
, src1
))
6432 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6433 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6434 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6436 /* Emit the conditional move for the test being false if needed. */
6437 if (! rtx_equal_p (dest
, src2
))
6438 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6439 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6440 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6443 /* Finish up, return sequence. */
6450 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6451 memory location that is not known to be dword-aligned. */
6453 frv_split_double_load (rtx dest
, rtx source
)
6455 int regno
= REGNO (dest
);
6456 rtx dest1
= gen_highpart (SImode
, dest
);
6457 rtx dest2
= gen_lowpart (SImode
, dest
);
6458 rtx address
= XEXP (source
, 0);
6460 /* If the address is pre-modified, load the lower-numbered register
6461 first, then load the other register using an integer offset from
6462 the modified base register. This order should always be safe,
6463 since the pre-modification cannot affect the same registers as the
6466 The situation for other loads is more complicated. Loading one
6467 of the registers could affect the value of ADDRESS, so we must
6468 be careful which order we do them in. */
6469 if (GET_CODE (address
) == PRE_MODIFY
6470 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
6472 /* It is safe to load the lower-numbered register first. */
6473 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6474 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6478 /* ADDRESS is not pre-modified and the address depends on the
6479 lower-numbered register. Load the higher-numbered register
6481 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6482 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6486 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6487 and SOURCE is either a double register or the constant zero. */
6489 frv_split_double_store (rtx dest
, rtx source
)
6491 rtx dest1
= change_address (dest
, SImode
, NULL
);
6492 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
6493 if (ZERO_P (source
))
6495 emit_move_insn (dest1
, CONST0_RTX (SImode
));
6496 emit_move_insn (dest2
, CONST0_RTX (SImode
));
6500 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
6501 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
6506 /* Split a min/max operation returning a SEQUENCE containing all of the
6510 frv_split_minmax (rtx operands
[])
6512 rtx dest
= operands
[0];
6513 rtx minmax
= operands
[1];
6514 rtx src1
= operands
[2];
6515 rtx src2
= operands
[3];
6516 rtx cc_reg
= operands
[4];
6517 rtx cr_reg
= operands
[5];
6519 enum rtx_code test_code
;
6520 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6524 /* Figure out which test to use. */
6525 switch (GET_CODE (minmax
))
6530 case SMIN
: test_code
= LT
; break;
6531 case SMAX
: test_code
= GT
; break;
6532 case UMIN
: test_code
= LTU
; break;
6533 case UMAX
: test_code
= GTU
; break;
6536 /* Issue the compare instruction. */
6537 emit_insn (gen_rtx_SET (VOIDmode
,
6539 gen_rtx_COMPARE (GET_MODE (cc_reg
),
6542 /* Set the appropriate CCR bit. */
6543 emit_insn (gen_rtx_SET (VOIDmode
,
6545 gen_rtx_fmt_ee (test_code
,
6550 /* If are taking the min/max of a nonzero constant, load that first, and
6551 then do a conditional move of the other value. */
6552 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6554 if (rtx_equal_p (dest
, src1
))
6557 emit_move_insn (dest
, src2
);
6558 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6559 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6560 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6563 /* Otherwise, do each half of the move. */
6566 /* Emit the conditional move for the test being true if needed. */
6567 if (! rtx_equal_p (dest
, src1
))
6568 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6569 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6570 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6572 /* Emit the conditional move for the test being false if needed. */
6573 if (! rtx_equal_p (dest
, src2
))
6574 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6575 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6576 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6579 /* Finish up, return sequence. */
6586 /* Split an integer abs operation returning a SEQUENCE containing all of the
6590 frv_split_abs (rtx operands
[])
6592 rtx dest
= operands
[0];
6593 rtx src
= operands
[1];
6594 rtx cc_reg
= operands
[2];
6595 rtx cr_reg
= operands
[3];
6600 /* Issue the compare < 0 instruction. */
6601 emit_insn (gen_rtx_SET (VOIDmode
,
6603 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
6605 /* Set the appropriate CCR bit. */
6606 emit_insn (gen_rtx_SET (VOIDmode
,
6608 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
6610 /* Emit the conditional negate if the value is negative. */
6611 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6612 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
6613 gen_negsi2 (dest
, src
)));
6615 /* Emit the conditional move for the test being false if needed. */
6616 if (! rtx_equal_p (dest
, src
))
6617 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6618 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
6619 gen_rtx_SET (VOIDmode
, dest
, src
)));
6621 /* Finish up, return sequence. */
6628 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6629 register used in an insn. */
6632 frv_clear_registers_used (rtx
*ptr
, void *data
)
6634 if (GET_CODE (*ptr
) == REG
)
6636 int regno
= REGNO (*ptr
);
6637 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
6639 if (regno
< FIRST_PSEUDO_REGISTER
)
6641 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
6643 while (regno
< reg_max
)
6645 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
6655 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6657 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6658 initialize the static storage. */
6660 frv_ifcvt_init_extra_fields (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6662 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6663 frv_ifcvt
.cur_scratch_regs
= 0;
6664 frv_ifcvt
.num_nested_cond_exec
= 0;
6665 frv_ifcvt
.cr_reg
= NULL_RTX
;
6666 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
6667 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
6668 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
6669 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
6673 /* Internal function to add a potential insn to the list of insns to be inserted
6674 if the conditional execution conversion is successful. */
6677 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
6679 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
6681 link
->jump
= before_p
; /* Mark to add this before or after insn. */
6682 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
6683 frv_ifcvt
.added_insns_list
);
6685 if (TARGET_DEBUG_COND_EXEC
)
6688 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6689 (before_p
) ? "before" : "after",
6690 (int)INSN_UID (insn
));
6692 debug_rtx (pattern
);
6697 /* A C expression to modify the code described by the conditional if
6698 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6699 FALSE_EXPR for converting if-then and if-then-else code to conditional
6700 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6701 tests cannot be converted. */
6704 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
6706 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
6707 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
6708 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
6709 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
6710 rtx true_expr
= *p_true
;
6714 enum machine_mode mode
= GET_MODE (true_expr
);
6718 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
6720 rtx sub_cond_exec_reg
;
6722 enum rtx_code code_true
;
6723 enum rtx_code code_false
;
6724 enum reg_class cc_class
;
6725 enum reg_class cr_class
;
6729 /* Make sure we are only dealing with hard registers. Also honor the
6730 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6732 if (!reload_completed
|| TARGET_NO_COND_EXEC
6733 || (TARGET_NO_NESTED_CE
&& ce_info
->pass
> 1))
6736 /* Figure out which registers we can allocate for our own purposes. Only
6737 consider registers that are not preserved across function calls and are
6738 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6739 if we did not need to use them in reloading other registers. */
6740 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
6741 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
6742 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
6743 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
6744 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
6746 /* If this is a nested IF, we need to discover whether the CC registers that
6747 are set/used inside of the block are used anywhere else. If not, we can
6748 change them to be the CC register that is paired with the CR register that
6749 controls the outermost IF block. */
6750 if (ce_info
->pass
> 1)
6752 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
6753 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6754 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6756 if (REGNO_REG_SET_P (then_bb
->global_live_at_start
, j
))
6759 if (else_bb
&& REGNO_REG_SET_P (else_bb
->global_live_at_start
, j
))
6762 if (join_bb
&& REGNO_REG_SET_P (join_bb
->global_live_at_start
, j
))
6765 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
6769 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
6770 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
6772 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6773 frv_ifcvt
.cur_scratch_regs
= 0;
6775 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
6776 * sizeof (basic_block
));
6782 /* Remove anything live at the beginning of the join block from being
6783 available for allocation. */
6784 EXECUTE_IF_SET_IN_REG_SET (join_bb
->global_live_at_start
, 0, regno
,
6786 if (regno
< FIRST_PSEUDO_REGISTER
)
6787 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6791 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6793 if (ce_info
->num_multiple_test_blocks
)
6795 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
6797 while (multiple_test_bb
!= test_bb
)
6799 bb
[num_bb
++] = multiple_test_bb
;
6800 multiple_test_bb
= multiple_test_bb
->pred
->src
;
6804 /* Add in the THEN and ELSE blocks to be scanned. */
6805 bb
[num_bb
++] = then_bb
;
6807 bb
[num_bb
++] = else_bb
;
6809 sub_cond_exec_reg
= NULL_RTX
;
6810 frv_ifcvt
.num_nested_cond_exec
= 0;
6812 /* Scan all of the blocks for registers that must not be allocated. */
6813 for (j
= 0; j
< num_bb
; j
++)
6815 rtx last_insn
= BB_END (bb
[j
]);
6816 rtx insn
= BB_HEAD (bb
[j
]);
6820 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
6821 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
6823 (int) INSN_UID (BB_HEAD (bb
[j
])),
6824 (int) INSN_UID (BB_END (bb
[j
])));
6826 /* Anything live at the beginning of the block is obviously unavailable
6828 EXECUTE_IF_SET_IN_REG_SET (bb
[j
]->global_live_at_start
, 0, regno
,
6830 if (regno
< FIRST_PSEUDO_REGISTER
)
6831 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6834 /* Loop through the insns in the block. */
6837 /* Mark any new registers that are created as being unavailable for
6838 allocation. Also see if the CC register used in nested IFs can be
6844 int skip_nested_if
= FALSE
;
6846 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6847 (void *)&tmp_reg
->regs
);
6849 pattern
= PATTERN (insn
);
6850 if (GET_CODE (pattern
) == COND_EXEC
)
6852 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
6854 if (reg
!= sub_cond_exec_reg
)
6856 sub_cond_exec_reg
= reg
;
6857 frv_ifcvt
.num_nested_cond_exec
++;
6861 set
= single_set_pattern (pattern
);
6864 rtx dest
= SET_DEST (set
);
6865 rtx src
= SET_SRC (set
);
6867 if (GET_CODE (dest
) == REG
)
6869 int regno
= REGNO (dest
);
6870 enum rtx_code src_code
= GET_CODE (src
);
6872 if (CC_P (regno
) && src_code
== COMPARE
)
6873 skip_nested_if
= TRUE
;
6875 else if (CR_P (regno
)
6876 && (src_code
== IF_THEN_ELSE
6877 || COMPARISON_P (src
)))
6878 skip_nested_if
= TRUE
;
6882 if (! skip_nested_if
)
6883 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6884 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
6887 if (insn
== last_insn
)
6890 insn
= NEXT_INSN (insn
);
6894 /* If this is a nested if, rewrite the CC registers that are available to
6895 include the ones that can be rewritten, to increase the chance of being
6896 able to allocate a paired CC/CR register combination. */
6897 if (ce_info
->pass
> 1)
6899 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6900 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
6901 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
6903 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
6909 fprintf (dump_file
, "Available GPRs: ");
6911 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
6912 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6914 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
6915 if (++num_gprs
> GPR_TEMP_NUM
+2)
6919 fprintf (dump_file
, "%s\nAvailable CRs: ",
6920 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
6922 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
6923 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6924 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
6926 fputs ("\n", dump_file
);
6928 if (ce_info
->pass
> 1)
6930 fprintf (dump_file
, "Modifiable CCs: ");
6931 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6932 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6933 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
6935 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
6936 frv_ifcvt
.num_nested_cond_exec
);
6940 /* Allocate the appropriate temporary condition code register. Try to
6941 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6942 that conditional cmp's can be done. */
6943 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6945 cr_class
= ICR_REGS
;
6946 cc_class
= ICC_REGS
;
6947 cc_first
= ICC_FIRST
;
6950 else if (mode
== CC_FPmode
)
6952 cr_class
= FCR_REGS
;
6953 cc_class
= FCC_REGS
;
6954 cc_first
= FCC_FIRST
;
6959 cc_first
= cc_last
= 0;
6960 cr_class
= cc_class
= NO_REGS
;
6963 cc
= XEXP (true_expr
, 0);
6964 nested_cc
= cr
= NULL_RTX
;
6965 if (cc_class
!= NO_REGS
)
6967 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6968 so we can execute a csubcc/caddcc/cfcmps instruction. */
6971 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
6973 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
6975 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
6976 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
6978 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
6979 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
6982 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
6983 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
6993 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
7000 "Will use %s for conditional execution, %s for nested comparisons\n",
7001 reg_names
[ REGNO (cr
)],
7002 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
7004 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
7005 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
7006 bit being true. We don't do this for floating point, because of NaNs. */
7007 code
= GET_CODE (true_expr
);
7008 if (GET_MODE (cc
) != CC_FPmode
)
7010 code
= reverse_condition (code
);
7020 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
7021 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
7023 /* Record the check insn to be inserted later. */
7024 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
7026 /* Update the tests. */
7027 frv_ifcvt
.cr_reg
= cr
;
7028 frv_ifcvt
.nested_cc_reg
= nested_cc
;
7029 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
7030 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
7033 /* Fail, don't do this conditional execution. */
7036 *p_false
= NULL_RTX
;
7038 fprintf (dump_file
, "Disabling this conditional execution.\n");
7044 /* A C expression to modify the code described by the conditional if
7045 information CE_INFO, for the basic block BB, possibly updating the tests in
7046 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
7047 if-then-else code to conditional instructions. Set either TRUE_EXPR or
7048 FALSE_EXPR to a null pointer if the tests cannot be converted. */
7050 /* p_true and p_false are given expressions of the form:
7052 (and (eq:CC_CCR (reg:CC_CCR)
7058 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
7063 rtx old_true
= XEXP (*p_true
, 0);
7064 rtx old_false
= XEXP (*p_false
, 0);
7065 rtx true_expr
= XEXP (*p_true
, 1);
7066 rtx false_expr
= XEXP (*p_false
, 1);
7069 rtx cr
= XEXP (old_true
, 0);
7071 rtx new_cr
= NULL_RTX
;
7072 rtx
*p_new_cr
= (rtx
*)0;
7076 enum reg_class cr_class
;
7077 enum machine_mode mode
= GET_MODE (true_expr
);
7078 rtx (*logical_func
)(rtx
, rtx
, rtx
);
7080 if (TARGET_DEBUG_COND_EXEC
)
7083 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
7084 ce_info
->and_and_p
? "&&" : "||");
7086 debug_rtx (*p_true
);
7088 fputs ("\nfalse insn:\n", stderr
);
7089 debug_rtx (*p_false
);
7092 if (TARGET_NO_MULTI_CE
)
7095 if (GET_CODE (cr
) != REG
)
7098 if (mode
== CCmode
|| mode
== CC_UNSmode
)
7100 cr_class
= ICR_REGS
;
7101 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
7103 else if (mode
== CC_FPmode
)
7105 cr_class
= FCR_REGS
;
7106 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
7111 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7112 more &&/|| tests. */
7116 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
7117 CC_CCRmode
, TRUE
, TRUE
);
7122 if (ce_info
->and_and_p
)
7124 old_test
= old_false
;
7125 test_expr
= true_expr
;
7126 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
7127 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
7128 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
7132 old_test
= old_false
;
7133 test_expr
= false_expr
;
7134 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
7135 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
7136 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
7139 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7140 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7142 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
7144 /* Now add the conditional check insn. */
7145 cc
= XEXP (test_expr
, 0);
7146 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
7147 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
7149 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
7151 /* Add the new check insn to the list of check insns that need to be
7153 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
7155 if (TARGET_DEBUG_COND_EXEC
)
7157 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7160 debug_rtx (*p_true
);
7162 fputs ("\nfalse insn:\n", stderr
);
7163 debug_rtx (*p_false
);
7169 *p_true
= *p_false
= NULL_RTX
;
7171 /* If we allocated a CR register, release it. */
7174 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
7175 *p_new_cr
= NULL_RTX
;
7178 if (TARGET_DEBUG_COND_EXEC
)
7179 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
7185 /* Return a register which will be loaded with a value if an IF block is
7186 converted to conditional execution. This is used to rewrite instructions
7187 that use constants to ones that just use registers. */
7190 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
7192 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
7196 /* We know gr0 == 0, so replace any errant uses. */
7197 if (value
== const0_rtx
)
7198 return gen_rtx_REG (SImode
, GPR_FIRST
);
7200 /* First search all registers currently loaded to see if we have an
7201 applicable constant. */
7202 if (CONSTANT_P (value
)
7203 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
7205 for (i
= 0; i
< num_alloc
; i
++)
7207 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
7208 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
7212 /* Have we exhausted the number of registers available? */
7213 if (num_alloc
>= GPR_TEMP_NUM
)
7216 fprintf (dump_file
, "Too many temporary registers allocated\n");
7221 /* Allocate the new register. */
7222 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
7226 fputs ("Could not find a scratch register\n", dump_file
);
7231 frv_ifcvt
.cur_scratch_regs
++;
7232 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
7236 if (GET_CODE (value
) == CONST_INT
)
7237 fprintf (dump_file
, "Register %s will hold %ld\n",
7238 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
7240 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
7241 fprintf (dump_file
, "Register %s will hold LR\n",
7242 reg_names
[ REGNO (reg
)]);
7245 fprintf (dump_file
, "Register %s will hold a saved value\n",
7246 reg_names
[ REGNO (reg
)]);
7253 /* Update a MEM used in conditional code that might contain an offset to put
7254 the offset into a scratch register, so that the conditional load/store
7255 operations can be used. This function returns the original pointer if the
7256 MEM is valid to use in conditional code, NULL if we can't load up the offset
7257 into a temporary register, or the new MEM if we were successful. */
7260 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
7262 rtx addr
= XEXP (mem
, 0);
7264 if (!frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
, FALSE
))
7266 if (GET_CODE (addr
) == PLUS
)
7268 rtx addr_op0
= XEXP (addr
, 0);
7269 rtx addr_op1
= XEXP (addr
, 1);
7271 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
7273 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
7277 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
7284 else if (CONSTANT_P (addr
))
7285 addr
= frv_ifcvt_load_value (addr
, insn
);
7290 if (addr
== NULL_RTX
)
7293 else if (XEXP (mem
, 0) != addr
)
7294 return change_address (mem
, mode
, addr
);
7301 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7302 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7305 single_set_pattern (rtx pattern
)
7310 if (GET_CODE (pattern
) == COND_EXEC
)
7311 pattern
= COND_EXEC_CODE (pattern
);
7313 if (GET_CODE (pattern
) == SET
)
7316 else if (GET_CODE (pattern
) == PARALLEL
)
7318 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
7320 rtx sub
= XVECEXP (pattern
, 0, i
);
7322 switch (GET_CODE (sub
))
7346 /* A C expression to modify the code described by the conditional if
7347 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7348 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7349 insn cannot be converted to be executed conditionally. */
7352 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info
,
7356 rtx orig_ce_pattern
= pattern
;
7362 if (GET_CODE (pattern
) != COND_EXEC
)
7365 test
= COND_EXEC_TEST (pattern
);
7366 if (GET_CODE (test
) == AND
)
7368 rtx cr
= frv_ifcvt
.cr_reg
;
7371 op0
= XEXP (test
, 0);
7372 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
7375 op1
= XEXP (test
, 1);
7376 test_reg
= XEXP (op1
, 0);
7377 if (GET_CODE (test_reg
) != REG
)
7380 /* Is this the first nested if block in this sequence? If so, generate
7381 an andcr or andncr. */
7382 if (! frv_ifcvt
.last_nested_if_cr
)
7386 frv_ifcvt
.last_nested_if_cr
= test_reg
;
7387 if (GET_CODE (op0
) == NE
)
7388 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
7390 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
7392 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
7395 /* If this isn't the first statement in the nested if sequence, see if we
7396 are dealing with the same register. */
7397 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
7400 COND_EXEC_TEST (pattern
) = test
= op1
;
7403 /* If this isn't a nested if, reset state variables. */
7406 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
7409 set
= single_set_pattern (pattern
);
7412 rtx dest
= SET_DEST (set
);
7413 rtx src
= SET_SRC (set
);
7414 enum machine_mode mode
= GET_MODE (dest
);
7416 /* Check for normal binary operators. */
7417 if (mode
== SImode
&& ARITHMETIC_P (src
))
7419 op0
= XEXP (src
, 0);
7420 op1
= XEXP (src
, 1);
7422 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
7424 op1
= frv_ifcvt_load_value (op1
, insn
);
7426 COND_EXEC_CODE (pattern
)
7427 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
7435 /* For multiply by a constant, we need to handle the sign extending
7436 correctly. Add a USE of the value after the multiply to prevent flow
7437 from cratering because only one register out of the two were used. */
7438 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
7440 op0
= XEXP (src
, 0);
7441 op1
= XEXP (src
, 1);
7442 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
7444 op1
= frv_ifcvt_load_value (op1
, insn
);
7447 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
7448 COND_EXEC_CODE (pattern
)
7449 = gen_rtx_SET (VOIDmode
, dest
,
7450 gen_rtx_MULT (DImode
, op0
, op1
));
7456 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode
, dest
), insn
, FALSE
);
7459 /* If we are just loading a constant created for a nested conditional
7460 execution statement, just load the constant without any conditional
7461 execution, since we know that the constant will not interfere with any
7463 else if (frv_ifcvt
.scratch_insns_bitmap
7464 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
7466 /* We must not unconditionally set a reg set used as
7467 scratch in the THEN branch if the same reg is live
7468 in the ELSE branch. */
7469 && REG_P (SET_DEST (set
))
7470 && (! ce_info
->else_bb
7471 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
7472 || ! (REGNO_REG_SET_P
7473 (ce_info
->else_bb
->global_live_at_start
,
7474 REGNO (SET_DEST (set
))))))
7477 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
7480 int changed_p
= FALSE
;
7482 /* Check for just loading up a constant */
7483 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
7485 src
= frv_ifcvt_load_value (src
, insn
);
7492 /* See if we need to fix up stores */
7493 if (GET_CODE (dest
) == MEM
)
7495 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
7500 else if (new_mem
!= dest
)
7507 /* See if we need to fix up loads */
7508 if (GET_CODE (src
) == MEM
)
7510 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
7515 else if (new_mem
!= src
)
7522 /* If either src or destination changed, redo SET. */
7524 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7527 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7528 rewriting the CC register to be the same as the paired CC/CR register
7530 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
7532 int regno
= REGNO (XEXP (src
, 0));
7535 if (ce_info
->pass
> 1
7536 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
7537 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
7539 src
= gen_rtx_fmt_ee (GET_CODE (src
),
7541 frv_ifcvt
.nested_cc_reg
,
7545 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
7546 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
7549 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7550 else if (ce_info
->pass
> 1
7551 && GET_CODE (dest
) == REG
7552 && CC_P (REGNO (dest
))
7553 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
7554 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
7556 && GET_CODE (src
) == COMPARE
)
7558 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
7559 COND_EXEC_CODE (pattern
)
7560 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
7564 if (TARGET_DEBUG_COND_EXEC
)
7566 rtx orig_pattern
= PATTERN (insn
);
7568 PATTERN (insn
) = pattern
;
7570 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7574 PATTERN (insn
) = orig_pattern
;
7580 if (TARGET_DEBUG_COND_EXEC
)
7582 rtx orig_pattern
= PATTERN (insn
);
7584 PATTERN (insn
) = orig_ce_pattern
;
7586 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7590 PATTERN (insn
) = orig_pattern
;
7597 /* A C expression to perform any final machine dependent modifications in
7598 converting code to conditional execution in the code described by the
7599 conditional if information CE_INFO. */
7602 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
7606 rtx p
= frv_ifcvt
.added_insns_list
;
7609 /* Loop inserting the check insns. The last check insn is the first test,
7610 and is the appropriate place to insert constants. */
7616 rtx check_and_insert_insns
= XEXP (p
, 0);
7619 check_insn
= XEXP (check_and_insert_insns
, 0);
7620 existing_insn
= XEXP (check_and_insert_insns
, 1);
7623 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7624 the existing insn, otherwise it is to be inserted AFTER. */
7625 if (check_and_insert_insns
->jump
)
7627 emit_insn_before (check_insn
, existing_insn
);
7628 check_and_insert_insns
->jump
= 0;
7631 emit_insn_after (check_insn
, existing_insn
);
7633 free_EXPR_LIST_node (check_and_insert_insns
);
7634 free_EXPR_LIST_node (old_p
);
7636 while (p
!= NULL_RTX
);
7638 /* Load up any constants needed into temp gprs */
7639 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7641 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
7642 if (! frv_ifcvt
.scratch_insns_bitmap
)
7643 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_XMALLOC ();
7644 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
7645 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7648 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7649 frv_ifcvt
.cur_scratch_regs
= 0;
7653 /* A C expression to cancel any machine dependent modifications in converting
7654 code to conditional execution in the code described by the conditional if
7655 information CE_INFO. */
7658 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
7661 rtx p
= frv_ifcvt
.added_insns_list
;
7663 /* Loop freeing up the EXPR_LIST's allocated. */
7664 while (p
!= NULL_RTX
)
7666 rtx check_and_jump
= XEXP (p
, 0);
7670 free_EXPR_LIST_node (check_and_jump
);
7671 free_EXPR_LIST_node (old_p
);
7674 /* Release any temporary gprs allocated. */
7675 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7676 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7678 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7679 frv_ifcvt
.cur_scratch_regs
= 0;
7683 /* A C expression for the size in bytes of the trampoline, as an integer.
7687 setlo #0, <static_chain>
7689 sethi #0, <static_chain>
7690 jmpl @(gr0,<jmp_reg>) */
7693 frv_trampoline_size (void)
7696 /* Allocate room for the function descriptor and the lddi
7699 return 5 /* instructions */ * 4 /* instruction size. */;
7703 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7704 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7705 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7706 should be passed to the function when it is called.
7711 setlo #0, <static_chain>
7713 sethi #0, <static_chain>
7714 jmpl @(gr0,<jmp_reg>) */
7717 frv_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
7719 rtx sc_reg
= force_reg (Pmode
, static_chain
);
7721 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
7724 GEN_INT (frv_trampoline_size ()), SImode
,
7730 /* Many machines have some registers that cannot be copied directly to or from
7731 memory or even from other types of registers. An example is the `MQ'
7732 register, which on most machines, can only be copied to or from general
7733 registers, but not memory. Some machines allow copying all registers to and
7734 from memory, but require a scratch register for stores to some memory
7735 locations (e.g., those with symbolic address on the RT, and those with
7736 certain symbolic address on the SPARC when compiling PIC). In some cases,
7737 both an intermediate and a scratch register are required.
7739 You should define these macros to indicate to the reload phase that it may
7740 need to allocate at least one register for a reload in addition to the
7741 register to contain the data. Specifically, if copying X to a register
7742 CLASS in MODE requires an intermediate register, you should define
7743 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7744 whose registers can be used as intermediate registers or scratch registers.
7746 If copying a register CLASS in MODE to X requires an intermediate or scratch
7747 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7748 largest register class required. If the requirements for input and output
7749 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7750 instead of defining both macros identically.
7752 The values returned by these macros are often `GENERAL_REGS'. Return
7753 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7754 to or from a register of CLASS in MODE without requiring a scratch register.
7755 Do not define this macro if it would always return `NO_REGS'.
7757 If a scratch register is required (either with or without an intermediate
7758 register), you should define patterns for `reload_inM' or `reload_outM', as
7759 required.. These patterns, which will normally be implemented with a
7760 `define_expand', should be similar to the `movM' patterns, except that
7761 operand 2 is the scratch register.
7763 Define constraints for the reload register and scratch register that contain
7764 a single register class. If the original reload register (whose class is
7765 CLASS) can meet the constraint given in the pattern, the value returned by
7766 these macros is used for the class of the scratch register. Otherwise, two
7767 additional reload registers are required. Their classes are obtained from
7768 the constraints in the insn pattern.
7770 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7771 either be in a hard register or in memory. Use `true_regnum' to find out;
7772 it will return -1 if the pseudo is in memory and the hard register number if
7773 it is in a register.
7775 These macros should not be used in the case where a particular class of
7776 registers can only be copied to memory and not to another class of
7777 registers. In that case, secondary reload registers are not needed and
7778 would not be helpful. Instead, a stack location must be used to perform the
7779 copy and the `movM' pattern should use memory as an intermediate storage.
7780 This case often occurs between floating-point and general registers. */
7783 frv_secondary_reload_class (enum reg_class
class,
7784 enum machine_mode mode ATTRIBUTE_UNUSED
,
7786 int in_p ATTRIBUTE_UNUSED
)
7796 /* Accumulators/Accumulator guard registers need to go through floating
7802 if (x
&& GET_CODE (x
) == REG
)
7804 int regno
= REGNO (x
);
7806 if (ACC_P (regno
) || ACCG_P (regno
))
7811 /* Nonzero constants should be loaded into an FPR through a GPR. */
7815 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
7821 /* All of these types need gpr registers. */
7833 /* The accumulators need fpr registers */
7846 /* A C expression whose value is nonzero if pseudos that have been assigned to
7847 registers of class CLASS would likely be spilled because registers of CLASS
7848 are needed for spill registers.
7850 The default value of this macro returns 1 if CLASS has exactly one register
7851 and zero otherwise. On most machines, this default should be used. Only
7852 define this macro to some other expression if pseudo allocated by
7853 `local-alloc.c' end up in memory because their hard registers were needed
7854 for spill registers. If this macro returns nonzero for those classes, those
7855 pseudos will only be allocated by `global.c', which knows how to reallocate
7856 the pseudo to another register. If there would not be another register
7857 available for reallocation, you should not change the definition of this
7858 macro since the only effect of such a definition would be to slow down
7859 register allocation. */
7862 frv_class_likely_spilled_p (enum reg_class
class)
7889 /* An expression for the alignment of a structure field FIELD if the
7890 alignment computed in the usual way is COMPUTED. GCC uses this
7891 value instead of the value in `BIGGEST_ALIGNMENT' or
7892 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7894 /* The definition type of the bit field data is either char, short, long or
7895 long long. The maximum bit size is the number of bits of its own type.
7897 The bit field data is assigned to a storage unit that has an adequate size
7898 for bit field data retention and is located at the smallest address.
7900 Consecutive bit field data are packed at consecutive bits having the same
7901 storage unit, with regard to the type, beginning with the MSB and continuing
7904 If a field to be assigned lies over a bit field type boundary, its
7905 assignment is completed by aligning it with a boundary suitable for the
7908 When a bit field having a bit length of 0 is declared, it is forcibly
7909 assigned to the next storage unit.
7922 &x 00000000 00000000 00000000 00000000
7925 &x+4 00000000 00000000 00000000 00000000
7928 &x+8 00000000 00000000 00000000 00000000
7931 &x+12 00000000 00000000 00000000 00000000
7937 frv_adjust_field_align (tree field
, int computed
)
7939 /* Make sure that the bitfield is not wider than the type. */
7940 if (DECL_BIT_FIELD (field
)
7941 && !DECL_ARTIFICIAL (field
))
7943 tree parent
= DECL_CONTEXT (field
);
7944 tree prev
= NULL_TREE
;
7947 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= TREE_CHAIN (cur
))
7949 if (TREE_CODE (cur
) != FIELD_DECL
)
7958 /* If this isn't a :0 field and if the previous element is a bitfield
7959 also, see if the type is different, if so, we will need to align the
7960 bit-field to the next boundary. */
7962 && ! DECL_PACKED (field
)
7963 && ! integer_zerop (DECL_SIZE (field
))
7964 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
7966 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
7967 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
7968 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
7976 /* A C expression that is nonzero if it is permissible to store a value of mode
7977 MODE in hard register number REGNO (or in several registers starting with
7978 that one). For a machine where all registers are equivalent, a suitable
7981 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7983 It is not necessary for this macro to check for the numbers of fixed
7984 registers, because the allocation mechanism considers them to be always
7987 On some machines, double-precision values must be kept in even/odd register
7988 pairs. The way to implement that is to define this macro to reject odd
7989 register numbers for such modes.
7991 The minimum requirement for a mode to be OK in a register is that the
7992 `movMODE' instruction pattern support moves between the register and any
7993 other hard register for which the mode is OK; and that moving a value into
7994 the register and back out not alter it.
7996 Since the same instruction used to move `SImode' will work for all narrower
7997 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7998 to distinguish between these modes, provided you define patterns `movhi',
7999 etc., to take advantage of this. This is useful because of the interaction
8000 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
8001 all integer modes to be tieable.
8003 Many machines have special registers for floating point arithmetic. Often
8004 people assume that floating point machine modes are allowed only in floating
8005 point registers. This is not true. Any registers that can hold integers
8006 can safely *hold* a floating point machine mode, whether or not floating
8007 arithmetic can be done on it in those registers. Integer move instructions
8008 can be used to move the values.
8010 On some machines, though, the converse is true: fixed-point machine modes
8011 may not go in floating registers. This is true if the floating registers
8012 normalize any value stored in them, because storing a non-floating value
8013 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
8014 fixed-point machine modes in floating registers. But if the floating
8015 registers do not automatically normalize, if you can store any bit pattern
8016 in one and retrieve it unchanged without a trap, then any machine mode may
8017 go in a floating register, so you can define this macro to say so.
8019 The primary significance of special floating registers is rather that they
8020 are the registers acceptable in floating point arithmetic instructions.
8021 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
8022 writing the proper constraints for those instructions.
8024 On some machines, the floating registers are especially slow to access, so
8025 that it is better to store a value in a stack frame than in such a register
8026 if floating point arithmetic is not being done. As long as the floating
8027 registers are not in class `GENERAL_REGS', they will not be used unless some
8028 pattern's constraint asks for one. */
8031 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
8040 return ICC_P (regno
) || GPR_P (regno
);
8043 return CR_P (regno
) || GPR_P (regno
);
8046 return FCC_P (regno
) || GPR_P (regno
);
8052 /* Set BASE to the first register in REGNO's class. Set MASK to the
8053 bits that must be clear in (REGNO - BASE) for the register to be
8055 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
8059 /* ACCGs store one byte. Two-byte quantities must start in
8060 even-numbered registers, four-byte ones in registers whose
8061 numbers are divisible by four, and so on. */
8063 mask
= GET_MODE_SIZE (mode
) - 1;
8067 /* The other registers store one word. */
8068 if (GPR_P (regno
) || regno
== AP_FIRST
)
8071 else if (FPR_P (regno
))
8074 else if (ACC_P (regno
))
8077 else if (SPR_P (regno
))
8078 return mode
== SImode
;
8080 /* Fill in the table. */
8084 /* Anything smaller than an SI is OK in any word-sized register. */
8085 if (GET_MODE_SIZE (mode
) < 4)
8088 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
8090 return (((regno
- base
) & mask
) == 0);
8097 /* A C expression for the number of consecutive hard registers, starting at
8098 register number REGNO, required to hold a value of mode MODE.
8100 On a machine where all registers are exactly one word, a suitable definition
8103 #define HARD_REGNO_NREGS(REGNO, MODE) \
8104 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8105 / UNITS_PER_WORD)) */
8107 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8108 that we can build the appropriate instructions to properly reload the
8109 values. Also, make the byte-sized accumulator guards use one guard
8113 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
8116 return GET_MODE_SIZE (mode
);
8118 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8122 /* A C expression for the maximum number of consecutive registers of
8123 class CLASS needed to hold a value of mode MODE.
8125 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8126 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8127 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8129 This macro helps control the handling of multiple-word values in
8132 This declaration is required. */
8135 frv_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
8137 if (class == ACCG_REGS
)
8138 /* An N-byte value requires N accumulator guards. */
8139 return GET_MODE_SIZE (mode
);
8141 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8145 /* A C expression that is nonzero if X is a legitimate constant for an
8146 immediate operand on the target machine. You can assume that X satisfies
8147 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8148 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8151 frv_legitimate_constant_p (rtx x
)
8153 enum machine_mode mode
= GET_MODE (x
);
8155 /* frv_cannot_force_const_mem always returns true for FDPIC. This
8156 means that the move expanders will be expected to deal with most
8157 kinds of constant, regardless of what we return here.
8159 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
8160 a constant can be entered into reg_equiv_constant[]. If we return true,
8161 reload can create new instances of the constant whenever it likes.
8163 The idea is therefore to accept as many constants as possible (to give
8164 reload more freedom) while rejecting constants that can only be created
8165 at certain times. In particular, anything with a symbolic component will
8166 require use of the pseudo FDPIC register, which is only available before
8169 return LEGITIMATE_PIC_OPERAND_P (x
);
8171 /* All of the integer constants are ok. */
8172 if (GET_CODE (x
) != CONST_DOUBLE
)
8175 /* double integer constants are ok. */
8176 if (mode
== VOIDmode
|| mode
== DImode
)
8179 /* 0 is always ok. */
8180 if (x
== CONST0_RTX (mode
))
8183 /* If floating point is just emulated, allow any constant, since it will be
8184 constructed in the GPRs. */
8185 if (!TARGET_HAS_FPRS
)
8188 if (mode
== DFmode
&& !TARGET_DOUBLE
)
8191 /* Otherwise store the constant away and do a load. */
8195 /* A C expression for the cost of moving data from a register in class FROM to
8196 one in class TO. The classes are expressed using the enumeration values
8197 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8198 interpreted relative to that.
8200 It is not required that the cost always equal 2 when FROM is the same as TO;
8201 on some machines it is expensive to move between registers if they are not
8204 If reload sees an insn consisting of a single `set' between two hard
8205 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8206 value of 2, reload does not check to ensure that the constraints of the insn
8207 are met. Setting a cost of other than 2 will allow reload to verify that
8208 the constraints are met. You should do this if the `movM' pattern's
8209 constraints do not allow such copying. */
8211 #define HIGH_COST 40
8212 #define MEDIUM_COST 3
8216 frv_register_move_cost (enum reg_class from
, enum reg_class to
)
8300 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8301 use ".picptr" to generate safe relocations for PIC code. We also
8302 need a fixup entry for aligned (non-debugging) code. */
8305 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
8307 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
8309 if (GET_CODE (value
) == CONST
8310 || GET_CODE (value
) == SYMBOL_REF
8311 || GET_CODE (value
) == LABEL_REF
)
8313 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
8314 && SYMBOL_REF_FUNCTION_P (value
))
8316 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
8317 output_addr_const (asm_out_file
, value
);
8318 fputs (")\n", asm_out_file
);
8321 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
8322 && frv_function_symbol_referenced_p (value
))
8324 if (aligned_p
&& !TARGET_FDPIC
)
8326 static int label_num
= 0;
8330 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
8331 p
= (* targetm
.strip_name_encoding
) (buf
);
8333 fprintf (asm_out_file
, "%s:\n", p
);
8334 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
8335 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
8336 fprintf (asm_out_file
, "\t.previous\n");
8338 assemble_integer_with_op ("\t.picptr\t", value
);
8343 /* We've set the unaligned SI op to NULL, so we always have to
8344 handle the unaligned case here. */
8345 assemble_integer_with_op ("\t.4byte\t", value
);
8349 return default_assemble_integer (value
, size
, aligned_p
);
8352 /* Function to set up the backend function structure. */
8354 static struct machine_function
*
8355 frv_init_machine_status (void)
8357 return ggc_alloc_cleared (sizeof (struct machine_function
));
8360 /* Implement TARGET_SCHED_ISSUE_RATE. */
8363 frv_issue_rate (void)
8368 switch (frv_cpu_type
)
8372 case FRV_CPU_SIMPLE
:
8378 case FRV_CPU_GENERIC
:
8380 case FRV_CPU_TOMCAT
:
8386 /* Implement TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. */
8389 frv_use_dfa_pipeline_interface (void)
8394 /* Update the register state information, to know about which registers are set
8398 frv_registers_update (rtx x
,
8399 unsigned char reg_state
[],
8411 switch (GET_CODE (x
))
8416 /* Clobber just modifies a register, it doesn't make it live. */
8418 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
8419 flag
| REGSTATE_MODIFIED
);
8422 /* Pre modify updates the first argument, just references the second. */
8425 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
8426 flag
| REGSTATE_MODIFIED
| REGSTATE_LIVE
);
8427 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
, flag
);
8430 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8431 statement, but just to be sure, make sure it is the type of cond_exec
8435 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8436 && GET_CODE (XEXP (cond
, 0)) == REG
8437 && CR_P (REGNO (XEXP (cond
, 0)))
8438 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8439 && INTVAL (XEXP (cond
, 1)) == 0
8440 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8442 frv_registers_update (cond
, reg_state
, modified
, p_num_mod
, flag
);
8443 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8444 | ((GET_CODE (cond
) == NE
)
8446 : REGSTATE_IF_FALSE
));
8448 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
,
8453 fatal_insn ("frv_registers_update", x
);
8455 /* MEM resets the modification bits. */
8457 flag
&= ~REGSTATE_MODIFIED
;
8460 /* See if we need to set the modified flag. */
8462 reg
= SUBREG_REG (x
);
8463 if (GET_CODE (reg
) == REG
)
8465 regno
= subreg_regno (x
);
8466 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8473 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8477 if (flag
& REGSTATE_MODIFIED
)
8479 flag
&= REGSTATE_MASK
;
8480 while (regno
< reg_max
)
8482 int rs
= reg_state
[regno
];
8486 if ((rs
& REGSTATE_MODIFIED
) == 0)
8488 modified
[ *p_num_mod
] = regno
;
8492 /* If the previous register state had the register as
8493 modified, possibly in some conditional execution context,
8494 and the current insn modifies in some other context, or
8495 outside of conditional execution, just mark the variable
8498 flag
&= ~(REGSTATE_IF_EITHER
| REGSTATE_CC_MASK
);
8500 reg_state
[regno
] = (rs
| flag
);
8509 length
= GET_RTX_LENGTH (GET_CODE (x
));
8510 format
= GET_RTX_FORMAT (GET_CODE (x
));
8512 for (j
= 0; j
< length
; ++j
)
8517 frv_registers_update (XEXP (x
, j
), reg_state
, modified
, p_num_mod
,
8523 if (XVEC (x
, j
) != 0)
8526 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8527 frv_registers_update (XVECEXP (x
, j
, k
), reg_state
, modified
,
8533 /* Nothing to do. */
8542 /* Return if any registers in a hard register set were used an insn. */
8545 frv_registers_used_p (rtx x
, unsigned char reg_state
[], int flag
)
8556 switch (GET_CODE (x
))
8561 /* Skip clobber, that doesn't use the previous value. */
8565 /* For SET, if a conditional jump has occurred in the same insn, only
8566 allow a set of a CR register if that register is not currently live.
8567 This is because on the FR-V, B0/B1 instructions are always last.
8568 Otherwise, don't look at the result, except within a MEM, but do look
8571 dest
= SET_DEST (x
);
8572 if (flag
& REGSTATE_CONDJUMP
8573 && GET_CODE (dest
) == REG
&& CR_P (REGNO (dest
))
8574 && (reg_state
[ REGNO (dest
) ] & REGSTATE_LIVE
) != 0)
8577 if (GET_CODE (dest
) == MEM
)
8579 result
= frv_registers_used_p (XEXP (dest
, 0), reg_state
, flag
);
8584 return frv_registers_used_p (SET_SRC (x
), reg_state
, flag
);
8586 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8587 statement, but just to be sure, make sure it is the type of cond_exec
8591 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8592 && GET_CODE (XEXP (cond
, 0)) == REG
8593 && CR_P (REGNO (XEXP (cond
, 0)))
8594 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8595 && INTVAL (XEXP (cond
, 1)) == 0
8596 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8598 result
= frv_registers_used_p (cond
, reg_state
, flag
);
8602 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8603 | ((GET_CODE (cond
) == NE
)
8605 : REGSTATE_IF_FALSE
));
8607 return frv_registers_used_p (XEXP (x
, 1), reg_state
, flag
);
8610 fatal_insn ("frv_registers_used_p", x
);
8612 /* See if a register or subreg was modified in the same VLIW insn. */
8614 reg
= SUBREG_REG (x
);
8615 if (GET_CODE (reg
) == REG
)
8617 regno
= subreg_regno (x
);
8618 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8625 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8629 while (regno
< reg_max
)
8631 int rs
= reg_state
[regno
];
8633 if (rs
& REGSTATE_MODIFIED
)
8635 int rs_if
= rs
& REGSTATE_IF_EITHER
;
8636 int flag_if
= flag
& REGSTATE_IF_EITHER
;
8638 /* Simple modification, no conditional execution */
8639 if ((rs
& REGSTATE_IF_EITHER
) == 0)
8642 /* See if the variable is only modified in a conditional
8643 execution expression opposite to the conditional execution
8644 expression that governs this expression (ie, true vs. false
8645 for the same CC register). If this isn't two halves of the
8646 same conditional expression, consider the register
8648 if (((rs_if
== REGSTATE_IF_TRUE
&& flag_if
== REGSTATE_IF_FALSE
)
8649 || (rs_if
== REGSTATE_IF_FALSE
&& flag_if
== REGSTATE_IF_TRUE
))
8650 && ((rs
& REGSTATE_CC_MASK
) == (flag
& REGSTATE_CC_MASK
)))
8662 length
= GET_RTX_LENGTH (GET_CODE (x
));
8663 format
= GET_RTX_FORMAT (GET_CODE (x
));
8665 for (j
= 0; j
< length
; ++j
)
8670 result
= frv_registers_used_p (XEXP (x
, j
), reg_state
, flag
);
8677 if (XVEC (x
, j
) != 0)
8680 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8682 result
= frv_registers_used_p (XVECEXP (x
, j
, k
), reg_state
,
8691 /* Nothing to do. */
8699 /* Return if any registers in a hard register set were set in an insn. */
8702 frv_registers_set_p (rtx x
, unsigned char reg_state
[], int modify_p
)
8711 switch (GET_CODE (x
))
8717 return frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
);
8721 return (frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
)
8722 || frv_registers_set_p (XEXP (x
, 1), reg_state
, FALSE
));
8726 /* Just to be sure, make sure it is the type of cond_exec we
8728 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8729 && GET_CODE (XEXP (cond
, 0)) == REG
8730 && CR_P (REGNO (XEXP (cond
, 0)))
8731 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8732 && INTVAL (XEXP (cond
, 1)) == 0
8734 return frv_registers_set_p (XEXP (x
, 1), reg_state
, modify_p
);
8736 fatal_insn ("frv_registers_set_p", x
);
8738 /* MEM resets the modification bits. */
8743 /* See if we need to set the modified modify_p. */
8745 reg
= SUBREG_REG (x
);
8746 if (GET_CODE (reg
) == REG
)
8748 regno
= subreg_regno (x
);
8749 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8756 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8761 while (regno
< reg_max
)
8763 int rs
= reg_state
[regno
];
8765 if (rs
& REGSTATE_MODIFIED
)
8773 length
= GET_RTX_LENGTH (GET_CODE (x
));
8774 format
= GET_RTX_FORMAT (GET_CODE (x
));
8776 for (j
= 0; j
< length
; ++j
)
8781 if (frv_registers_set_p (XEXP (x
, j
), reg_state
, modify_p
))
8787 if (XVEC (x
, j
) != 0)
8790 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8791 if (frv_registers_set_p (XVECEXP (x
, j
, k
), reg_state
,
8798 /* Nothing to do. */
8807 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8808 conditional branches/calls/jumps, etc. with previous insns where it can. It
8809 does not reorder the instructions. We assume the scheduler left the flow
8810 information in a reasonable state. */
8813 frv_pack_insns (void)
8815 state_t frv_state
; /* frv state machine */
8816 int cur_start_vliw_p
; /* current insn starts a VLIW insn */
8817 int next_start_vliw_p
; /* next insn starts a VLIW insn */
8818 int cur_condjump_p
; /* flag if current insn is a cond jump*/
8819 int next_condjump_p
; /* flag if next insn is a cond jump */
8823 int num_mod
= 0; /* # of modified registers */
8824 int modified
[FIRST_PSEUDO_REGISTER
]; /* registers modified in current VLIW */
8825 /* register state information */
8826 unsigned char reg_state
[FIRST_PSEUDO_REGISTER
];
8828 /* If we weren't going to pack the insns, don't bother with this pass. */
8830 || !flag_schedule_insns_after_reload
8831 || TARGET_NO_VLIW_BRANCH
8832 || frv_issue_rate () == 1)
8835 /* Set up the instruction and register states. */
8837 frv_state
= (state_t
) xmalloc (state_size ());
8838 memset (reg_state
, REGSTATE_DEAD
, sizeof (reg_state
));
8840 /* Go through the insns, and repack the insns. */
8841 state_reset (frv_state
);
8842 cur_start_vliw_p
= FALSE
;
8843 next_start_vliw_p
= TRUE
;
8845 next_condjump_p
= 0;
8847 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
8849 enum rtx_code code
= GET_CODE (insn
);
8850 enum rtx_code pattern_code
;
8852 /* For basic block begin notes redo the live information, and skip other
8856 if (NOTE_LINE_NUMBER (insn
) == (int)NOTE_INSN_BASIC_BLOCK
)
8860 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
8861 reg_state
[j
] &= ~ REGSTATE_LIVE
;
8863 live
= NOTE_BASIC_BLOCK (insn
)->global_live_at_start
;
8864 EXECUTE_IF_SET_IN_REG_SET(live
, 0, j
,
8866 reg_state
[j
] |= REGSTATE_LIVE
;
8873 /* Things like labels reset everything. */
8876 next_start_vliw_p
= TRUE
;
8880 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8881 set on the USE insn that precedes the return, and potentially on
8882 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8883 holding the case table labels. */
8884 pattern_code
= GET_CODE (PATTERN (insn
));
8885 if (pattern_code
== USE
|| pattern_code
== CLOBBER
8886 || pattern_code
== ADDR_VEC
|| pattern_code
== ADDR_DIFF_VEC
)
8888 CLEAR_VLIW_START (insn
);
8892 cur_start_vliw_p
= next_start_vliw_p
;
8893 next_start_vliw_p
= FALSE
;
8895 cur_condjump_p
|= next_condjump_p
;
8896 next_condjump_p
= 0;
8898 /* Unconditional branches and calls end the current VLIW insn. */
8899 if (code
== CALL_INSN
)
8901 next_start_vliw_p
= TRUE
;
8903 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8904 if (frv_cpu_type
== FRV_CPU_TOMCAT
)
8905 cur_start_vliw_p
= TRUE
;
8907 else if (code
== JUMP_INSN
)
8909 if (any_condjump_p (insn
))
8910 next_condjump_p
= REGSTATE_CONDJUMP
;
8912 next_start_vliw_p
= TRUE
;
8915 /* Only allow setting a CCR register after a conditional branch. */
8916 else if (((cur_condjump_p
& REGSTATE_CONDJUMP
) != 0)
8917 && get_attr_type (insn
) != TYPE_CCR
)
8918 cur_start_vliw_p
= TRUE
;
8920 /* Determine if we need to start a new VLIW instruction. */
8921 if (cur_start_vliw_p
8922 /* Do not check for register conflicts in a setlo instruction
8923 because any output or true dependencies will be with the
8924 partnering sethi instruction, with which it can be packed.
8926 Although output dependencies are rare they are still
8927 possible. So check output dependencies in VLIW insn. */
8928 || (get_attr_type (insn
) != TYPE_SETLO
8929 && (frv_registers_used_p (PATTERN (insn
),
8932 || frv_registers_set_p (PATTERN (insn
), reg_state
, FALSE
)))
8933 || state_transition (frv_state
, insn
) >= 0)
8935 SET_VLIW_START (insn
);
8936 state_reset (frv_state
);
8937 state_transition (frv_state
, insn
);
8940 /* Update the modified registers. */
8941 for (j
= 0; j
< num_mod
; j
++)
8942 reg_state
[ modified
[j
] ] &= ~(REGSTATE_CC_MASK
8943 | REGSTATE_IF_EITHER
8944 | REGSTATE_MODIFIED
);
8949 CLEAR_VLIW_START (insn
);
8951 /* Record which registers are modified. */
8952 frv_registers_update (PATTERN (insn
), reg_state
, modified
, &num_mod
, 0);
8954 /* Process the death notices. */
8955 for (link
= REG_NOTES (insn
);
8957 link
= XEXP (link
, 1))
8959 rtx reg
= XEXP (link
, 0);
8961 if (REG_NOTE_KIND (link
) == REG_DEAD
&& GET_CODE (reg
) == REG
)
8963 int regno
= REGNO (reg
);
8964 int n
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8965 for (; regno
< n
; regno
++)
8966 reg_state
[regno
] &= ~REGSTATE_LIVE
;
8977 #define def_builtin(name, type, code) \
8978 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8980 struct builtin_description
8982 enum insn_code icode
;
8984 enum frv_builtins code
;
8985 enum rtx_code comparison
;
8989 /* Media intrinsics that take a single, constant argument. */
8991 static struct builtin_description bdesc_set
[] =
8993 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, 0, 0 }
8996 /* Media intrinsics that take just one argument. */
8998 static struct builtin_description bdesc_1arg
[] =
9000 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, 0, 0 },
9001 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, 0, 0 },
9002 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, 0, 0 },
9003 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, 0, 0 },
9004 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, 0, 0 }
9007 /* Media intrinsics that take two arguments. */
9009 static struct builtin_description bdesc_2arg
[] =
9011 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, 0, 0 },
9012 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, 0, 0 },
9013 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, 0, 0 },
9014 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, 0, 0 },
9015 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, 0, 0 },
9016 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, 0, 0 },
9017 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, 0, 0 },
9018 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, 0, 0 },
9019 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, 0, 0 },
9020 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, 0, 0 },
9021 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, 0, 0 },
9022 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, 0, 0 },
9023 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, 0, 0 },
9024 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, 0, 0 },
9025 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, 0, 0 },
9026 { CODE_FOR_mdpackh
, "__MDPACKH", FRV_BUILTIN_MDPACKH
, 0, 0 },
9027 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, 0, 0 },
9028 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, 0, 0 },
9029 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, 0, 0 },
9030 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, 0, 0 }
9033 /* Media intrinsics that take two arguments, the first being an ACC number. */
9035 static struct builtin_description bdesc_cut
[] =
9037 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, 0, 0 },
9038 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, 0, 0 },
9039 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, 0, 0 }
9042 /* Two-argument media intrinsics with an immediate second argument. */
9044 static struct builtin_description bdesc_2argimm
[] =
9046 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, 0, 0 },
9047 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, 0, 0 },
9048 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, 0, 0 },
9049 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, 0, 0 },
9050 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, 0, 0 },
9051 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, 0, 0 },
9052 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, 0, 0 },
9053 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, 0, 0 },
9054 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, 0, 0 },
9055 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, 0, 0 },
9056 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, 0, 0 },
9057 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, 0, 0 },
9058 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, 0, 0 },
9059 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, 0, 0 },
9060 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, 0, 0 }
9063 /* Media intrinsics that take two arguments and return void, the first argument
9064 being a pointer to 4 words in memory. */
9066 static struct builtin_description bdesc_void2arg
[] =
9068 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, 0, 0 },
9069 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, 0, 0 },
9072 /* Media intrinsics that take three arguments, the first being a const_int that
9073 denotes an accumulator, and that return void. */
9075 static struct builtin_description bdesc_void3arg
[] =
9077 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, 0, 0 },
9078 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, 0, 0 },
9079 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, 0, 0 },
9080 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, 0, 0 },
9081 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, 0, 0 },
9082 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, 0, 0 },
9083 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, 0, 0 },
9084 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, 0, 0 },
9085 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, 0, 0 },
9086 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, 0, 0 },
9087 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, 0, 0 },
9088 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, 0, 0 },
9089 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, 0, 0 },
9090 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, 0, 0 },
9091 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, 0, 0 },
9092 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, 0, 0 },
9093 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, 0, 0 },
9094 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, 0, 0 },
9095 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, 0, 0 },
9096 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, 0, 0 },
9097 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, 0, 0 },
9098 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, 0, 0 },
9099 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, 0, 0 },
9100 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, 0, 0 },
9101 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, 0, 0 }
9104 /* Media intrinsics that take two accumulator numbers as argument and
9107 static struct builtin_description bdesc_voidacc
[] =
9109 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, 0, 0 },
9110 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, 0, 0 },
9111 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, 0, 0 },
9112 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, 0, 0 },
9113 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, 0, 0 },
9114 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, 0, 0 }
9117 /* Initialize media builtins. */
9120 frv_init_builtins (void)
9122 tree endlink
= void_list_node
;
9123 tree accumulator
= integer_type_node
;
9124 tree integer
= integer_type_node
;
9125 tree voidt
= void_type_node
;
9126 tree uhalf
= short_unsigned_type_node
;
9127 tree sword1
= long_integer_type_node
;
9128 tree uword1
= long_unsigned_type_node
;
9129 tree sword2
= long_long_integer_type_node
;
9130 tree uword2
= long_long_unsigned_type_node
;
9131 tree uword4
= build_pointer_type (uword1
);
9133 #define UNARY(RET, T1) \
9134 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9136 #define BINARY(RET, T1, T2) \
9137 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9138 tree_cons (NULL_TREE, T2, endlink)))
9140 #define TRINARY(RET, T1, T2, T3) \
9141 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9142 tree_cons (NULL_TREE, T2, \
9143 tree_cons (NULL_TREE, T3, endlink))))
9145 tree void_ftype_void
= build_function_type (voidt
, endlink
);
9147 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
9148 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
9149 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
9150 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
9151 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
9152 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
9153 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
9154 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
9155 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
9157 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
9158 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
9159 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
9160 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
9161 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
9162 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
9163 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
9164 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
9165 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
9166 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
9167 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
9169 tree sw1_ftype_int
= UNARY (sword1
, integer
);
9170 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
9171 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
9173 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
9174 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
9175 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
9176 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
9177 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
9179 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
9181 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
9182 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
9183 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
9184 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
9185 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
9186 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
9187 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
9188 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
9189 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
9190 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
9191 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
9192 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
9193 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
9194 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
9195 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
9196 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
9197 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
9198 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
9199 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
9200 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
9201 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
9202 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
9203 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
9204 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
9205 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
9206 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
9207 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
9208 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
9209 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
9210 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
9211 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
9212 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
9213 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
9214 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
9215 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
9216 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
9217 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
9218 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
9219 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
9220 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
9221 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
9222 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
9223 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
9224 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
9225 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
9226 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
9227 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
9228 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
9229 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
9230 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MDPACKH
);
9231 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
9232 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
9233 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
9234 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
9235 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
9236 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
9237 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
9238 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
9239 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
9240 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
9241 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
9242 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
9243 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
9244 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
9245 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
9246 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
9247 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
9248 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
9249 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
9250 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
9251 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
9252 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
9253 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
9254 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
9255 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
9256 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
9257 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
9258 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
9259 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
9260 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
9261 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
9262 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
9263 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
9264 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
9271 /* Set the names for various arithmetic operations according to the
9274 frv_init_libfuncs (void)
9276 set_optab_libfunc (smod_optab
, SImode
, "__modi");
9277 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
9279 set_optab_libfunc (add_optab
, DImode
, "__addll");
9280 set_optab_libfunc (sub_optab
, DImode
, "__subll");
9281 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
9282 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
9283 set_optab_libfunc (smod_optab
, DImode
, "__modll");
9284 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
9285 set_optab_libfunc (and_optab
, DImode
, "__andll");
9286 set_optab_libfunc (ior_optab
, DImode
, "__orll");
9287 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
9288 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
9290 set_optab_libfunc (add_optab
, SFmode
, "__addf");
9291 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
9292 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
9293 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
9295 set_optab_libfunc (add_optab
, DFmode
, "__addd");
9296 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
9297 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
9298 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
9300 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
9301 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
9303 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
9304 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9305 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
9306 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9308 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
9309 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9310 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
9311 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9313 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
9314 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
9315 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
9316 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
9319 /* Convert an integer constant to an accumulator register. ICODE is the
9320 code of the target instruction, OPNUM is the number of the
9321 accumulator operand and OPVAL is the constant integer. Try both
9322 ACC and ACCG registers; only report an error if neither fit the
9326 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
9330 if (GET_CODE (opval
) != CONST_INT
)
9332 error ("accumulator is not a constant integer");
9335 if (! IN_RANGE_P (INTVAL (opval
), 0, NUM_ACCS
- 1))
9337 error ("accumulator number is out of bounds");
9341 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
9342 ACC_FIRST
+ INTVAL (opval
));
9343 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
9344 REGNO (reg
) = ACCG_FIRST
+ INTVAL (opval
);
9346 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
9348 error ("inappropriate accumulator for `%s'", insn_data
[icode
].name
);
9354 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9357 static enum machine_mode
9358 frv_matching_accg_mode (enum machine_mode mode
)
9376 /* Return the accumulator guard that should be paired with accumulator
9377 register ACC. The mode of the returned register is in the same
9378 class as ACC, but is four times smaller. */
9381 frv_matching_accg_for_acc (rtx acc
)
9383 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
9384 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
9387 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9388 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9392 frv_read_argument (tree
*arglistptr
)
9394 tree next
= TREE_VALUE (*arglistptr
);
9395 *arglistptr
= TREE_CHAIN (*arglistptr
);
9396 return expand_expr (next
, NULL_RTX
, VOIDmode
, 0);
9399 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9400 The instruction should require a constant operand of some sort. The
9401 function prints an error if OPVAL is not valid. */
9404 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
9406 if (GET_CODE (opval
) != CONST_INT
)
9408 error ("`%s' expects a constant argument", insn_data
[icode
].name
);
9411 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
9413 error ("constant argument out of range for `%s'", insn_data
[icode
].name
);
9419 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9420 if it's not null, has the right mode, and satisfies operand 0's
9424 frv_legitimize_target (enum insn_code icode
, rtx target
)
9426 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
9429 || GET_MODE (target
) != mode
9430 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
9431 return gen_reg_rtx (mode
);
9436 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9437 check whether ARG satisfies the operand's constraints. If it doesn't,
9438 copy ARG to a temporary register and return that. Otherwise return ARG
9442 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
9444 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
9446 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
9449 return copy_to_mode_reg (mode
, arg
);
9452 /* Expand builtins that take a single, constant argument. At the moment,
9453 only MHDSETS falls into this category. */
9456 frv_expand_set_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9459 rtx op0
= frv_read_argument (&arglist
);
9461 if (! frv_check_constant_argument (icode
, 1, op0
))
9464 target
= frv_legitimize_target (icode
, target
);
9465 pat
= GEN_FCN (icode
) (target
, op0
);
9473 /* Expand builtins that take one operand. */
9476 frv_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9479 rtx op0
= frv_read_argument (&arglist
);
9481 target
= frv_legitimize_target (icode
, target
);
9482 op0
= frv_legitimize_argument (icode
, 1, op0
);
9483 pat
= GEN_FCN (icode
) (target
, op0
);
9491 /* Expand builtins that take two operands. */
9494 frv_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9497 rtx op0
= frv_read_argument (&arglist
);
9498 rtx op1
= frv_read_argument (&arglist
);
9500 target
= frv_legitimize_target (icode
, target
);
9501 op0
= frv_legitimize_argument (icode
, 1, op0
);
9502 op1
= frv_legitimize_argument (icode
, 2, op1
);
9503 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9511 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9515 frv_expand_cut_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9518 rtx op0
= frv_read_argument (&arglist
);
9519 rtx op1
= frv_read_argument (&arglist
);
9522 target
= frv_legitimize_target (icode
, target
);
9523 op0
= frv_int_to_acc (icode
, 1, op0
);
9527 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
9529 if (! frv_check_constant_argument (icode
, 2, op1
))
9533 op1
= frv_legitimize_argument (icode
, 2, op1
);
9535 op2
= frv_matching_accg_for_acc (op0
);
9536 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
9544 /* Expand builtins that take two operands and the second is immediate. */
9547 frv_expand_binopimm_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9550 rtx op0
= frv_read_argument (&arglist
);
9551 rtx op1
= frv_read_argument (&arglist
);
9553 if (! frv_check_constant_argument (icode
, 2, op1
))
9556 target
= frv_legitimize_target (icode
, target
);
9557 op0
= frv_legitimize_argument (icode
, 1, op0
);
9558 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9566 /* Expand builtins that take two operands, the first operand being a pointer to
9567 ints and return void. */
9570 frv_expand_voidbinop_builtin (enum insn_code icode
, tree arglist
)
9573 rtx op0
= frv_read_argument (&arglist
);
9574 rtx op1
= frv_read_argument (&arglist
);
9575 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
9578 if (GET_CODE (op0
) != MEM
)
9582 if (! offsettable_address_p (0, mode0
, op0
))
9584 reg
= gen_reg_rtx (Pmode
);
9585 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
9588 op0
= gen_rtx_MEM (SImode
, reg
);
9591 addr
= XEXP (op0
, 0);
9592 if (! offsettable_address_p (0, mode0
, addr
))
9593 addr
= copy_to_mode_reg (Pmode
, op0
);
9595 op0
= change_address (op0
, V4SImode
, addr
);
9596 op1
= frv_legitimize_argument (icode
, 1, op1
);
9597 pat
= GEN_FCN (icode
) (op0
, op1
);
9605 /* Expand builtins that take three operands and return void. The first
9606 argument must be a constant that describes a pair or quad accumulators. A
9607 fourth argument is created that is the accumulator guard register that
9608 corresponds to the accumulator. */
9611 frv_expand_voidtriop_builtin (enum insn_code icode
, tree arglist
)
9614 rtx op0
= frv_read_argument (&arglist
);
9615 rtx op1
= frv_read_argument (&arglist
);
9616 rtx op2
= frv_read_argument (&arglist
);
9619 op0
= frv_int_to_acc (icode
, 0, op0
);
9623 op1
= frv_legitimize_argument (icode
, 1, op1
);
9624 op2
= frv_legitimize_argument (icode
, 2, op2
);
9625 op3
= frv_matching_accg_for_acc (op0
);
9626 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9634 /* Expand builtins that perform accumulator-to-accumulator operations.
9635 These builtins take two accumulator numbers as argument and return
9639 frv_expand_voidaccop_builtin (enum insn_code icode
, tree arglist
)
9642 rtx op0
= frv_read_argument (&arglist
);
9643 rtx op1
= frv_read_argument (&arglist
);
9647 op0
= frv_int_to_acc (icode
, 0, op0
);
9651 op1
= frv_int_to_acc (icode
, 1, op1
);
9655 op2
= frv_matching_accg_for_acc (op0
);
9656 op3
= frv_matching_accg_for_acc (op1
);
9657 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9665 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9666 number as argument. */
9669 frv_expand_mclracc_builtin (tree arglist
)
9671 enum insn_code icode
= CODE_FOR_mclracc
;
9673 rtx op0
= frv_read_argument (&arglist
);
9675 op0
= frv_int_to_acc (icode
, 0, op0
);
9679 pat
= GEN_FCN (icode
) (op0
);
9686 /* Expand builtins that take no arguments. */
9689 frv_expand_noargs_builtin (enum insn_code icode
)
9691 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9698 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9699 number or accumulator guard number as argument and return an SI integer. */
9702 frv_expand_mrdacc_builtin (enum insn_code icode
, tree arglist
)
9705 rtx target
= gen_reg_rtx (SImode
);
9706 rtx op0
= frv_read_argument (&arglist
);
9708 op0
= frv_int_to_acc (icode
, 1, op0
);
9712 pat
= GEN_FCN (icode
) (target
, op0
);
9720 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9721 accumulator guard as their first argument and an SImode value as their
9725 frv_expand_mwtacc_builtin (enum insn_code icode
, tree arglist
)
9728 rtx op0
= frv_read_argument (&arglist
);
9729 rtx op1
= frv_read_argument (&arglist
);
9731 op0
= frv_int_to_acc (icode
, 0, op0
);
9735 op1
= frv_legitimize_argument (icode
, 1, op1
);
9736 pat
= GEN_FCN (icode
) (op0
, op1
);
9743 /* Expand builtins. */
9746 frv_expand_builtin (tree exp
,
9748 rtx subtarget ATTRIBUTE_UNUSED
,
9749 enum machine_mode mode ATTRIBUTE_UNUSED
,
9750 int ignore ATTRIBUTE_UNUSED
)
9752 tree arglist
= TREE_OPERAND (exp
, 1);
9753 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9754 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9756 struct builtin_description
*d
;
9760 error ("media functions are not available unless -mmedia is used");
9766 case FRV_BUILTIN_MCOP1
:
9767 case FRV_BUILTIN_MCOP2
:
9768 case FRV_BUILTIN_MDUNPACKH
:
9769 case FRV_BUILTIN_MBTOHE
:
9770 if (! TARGET_MEDIA_REV1
)
9772 error ("this media function is only available on the fr500");
9777 case FRV_BUILTIN_MQXMACHS
:
9778 case FRV_BUILTIN_MQXMACXHS
:
9779 case FRV_BUILTIN_MQMACXHS
:
9780 case FRV_BUILTIN_MADDACCS
:
9781 case FRV_BUILTIN_MSUBACCS
:
9782 case FRV_BUILTIN_MASACCS
:
9783 case FRV_BUILTIN_MDADDACCS
:
9784 case FRV_BUILTIN_MDSUBACCS
:
9785 case FRV_BUILTIN_MDASACCS
:
9786 case FRV_BUILTIN_MABSHS
:
9787 case FRV_BUILTIN_MDROTLI
:
9788 case FRV_BUILTIN_MCPLHI
:
9789 case FRV_BUILTIN_MCPLI
:
9790 case FRV_BUILTIN_MDCUTSSI
:
9791 case FRV_BUILTIN_MQSATHS
:
9792 case FRV_BUILTIN_MHSETLOS
:
9793 case FRV_BUILTIN_MHSETLOH
:
9794 case FRV_BUILTIN_MHSETHIS
:
9795 case FRV_BUILTIN_MHSETHIH
:
9796 case FRV_BUILTIN_MHDSETS
:
9797 case FRV_BUILTIN_MHDSETH
:
9798 if (! TARGET_MEDIA_REV2
)
9800 error ("this media function is only available on the fr400");
9809 /* Expand unique builtins. */
9813 case FRV_BUILTIN_MTRAP
:
9814 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9816 case FRV_BUILTIN_MCLRACC
:
9817 return frv_expand_mclracc_builtin (arglist
);
9819 case FRV_BUILTIN_MCLRACCA
:
9821 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9823 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9825 case FRV_BUILTIN_MRDACC
:
9826 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, arglist
);
9828 case FRV_BUILTIN_MRDACCG
:
9829 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, arglist
);
9831 case FRV_BUILTIN_MWTACC
:
9832 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, arglist
);
9834 case FRV_BUILTIN_MWTACCG
:
9835 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, arglist
);
9841 /* Expand groups of builtins. */
9843 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9844 if (d
->code
== fcode
)
9845 return frv_expand_set_builtin (d
->icode
, arglist
, target
);
9847 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9848 if (d
->code
== fcode
)
9849 return frv_expand_unop_builtin (d
->icode
, arglist
, target
);
9851 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9852 if (d
->code
== fcode
)
9853 return frv_expand_binop_builtin (d
->icode
, arglist
, target
);
9855 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9856 if (d
->code
== fcode
)
9857 return frv_expand_cut_builtin (d
->icode
, arglist
, target
);
9859 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9860 if (d
->code
== fcode
)
9861 return frv_expand_binopimm_builtin (d
->icode
, arglist
, target
);
9863 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9864 if (d
->code
== fcode
)
9865 return frv_expand_voidbinop_builtin (d
->icode
, arglist
);
9867 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9868 if (d
->code
== fcode
)
9869 return frv_expand_voidtriop_builtin (d
->icode
, arglist
);
9871 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9872 if (d
->code
== fcode
)
9873 return frv_expand_voidaccop_builtin (d
->icode
, arglist
);
9879 frv_in_small_data_p (tree decl
)
9884 /* Don't apply the -G flag to internal compiler structures. We
9885 should leave such structures in the main data section, partly
9886 for efficiency and partly because the size of some of them
9887 (such as C++ typeinfos) is not known until later. */
9888 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9891 /* If we already know which section the decl should be in, see if
9892 it's a small data section. */
9893 section_name
= DECL_SECTION_NAME (decl
);
9896 if (TREE_CODE (section_name
) != STRING_CST
)
9898 if (frv_string_begins_with (section_name
, ".sdata"))
9900 if (frv_string_begins_with (section_name
, ".sbss"))
9905 size
= int_size_in_bytes (TREE_TYPE (decl
));
9906 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
9913 frv_rtx_costs (rtx x
,
9914 int code ATTRIBUTE_UNUSED
,
9915 int outer_code ATTRIBUTE_UNUSED
,
9918 if (outer_code
== MEM
)
9920 /* Don't differentiate between memory addresses. All the ones
9921 we accept have equal cost. */
9922 *total
= COSTS_N_INSNS (0);
9929 /* Make 12 bit integers really cheap. */
9930 if (IN_RANGE_P (INTVAL (x
), -2048, 2047))
9941 *total
= COSTS_N_INSNS (2);
9955 if (GET_MODE (x
) == SImode
)
9956 *total
= COSTS_N_INSNS (1);
9957 else if (GET_MODE (x
) == DImode
)
9958 *total
= COSTS_N_INSNS (2);
9960 *total
= COSTS_N_INSNS (3);
9964 if (GET_MODE (x
) == SImode
)
9965 *total
= COSTS_N_INSNS (2);
9967 *total
= COSTS_N_INSNS (6); /* guess */
9974 *total
= COSTS_N_INSNS (18);
9978 *total
= COSTS_N_INSNS (3);
9987 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9990 assemble_align (POINTER_SIZE
);
9993 if (!frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1))
9997 assemble_integer_with_op ("\t.picptr\t", symbol
);
10001 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
10004 assemble_align (POINTER_SIZE
);
10007 if (!frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1))
10011 assemble_integer_with_op ("\t.picptr\t", symbol
);
10014 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10017 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
10018 int incoming ATTRIBUTE_UNUSED
)
10020 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);