| blob | 23f35ebf4f1034434e2a71f82b1bdc14569f9b69 |
1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
53 #include <splay-tree.h>
57 /* Specify which cpu to schedule for. */
61 {
63 };
65 /* Specify how accurate floating-point traps need to be. */
69 /* Specify the floating-point rounding mode. */
73 /* Specify which things cause traps. */
77 /* Specify bit size of immediate TLS offsets. */
81 /* Strings decoded into the above options. */
91 /* Save information from a "cmpxx" operation until the branch or scc is
92 emitted. */
96 /* Nonzero if inside of a function, because the Alpha asm can't
97 handle .files inside of functions. */
101 /* The number of cycles of latency we should assume on memory reads. */
105 /* Whether the function needs the GP. */
109 /* The alias set for prologue/epilogue register save/restore. */
113 /* The assembler name of the current function. */
117 /* The next explicit relocation sequence number. */
121 /* The literal and gpdisp sequence numbers for this insn, as printed
122 by %# and %* respectively. */
128 /* Costs of various operations on the different architectures. */
130 struct alpha_rtx_cost_data
131 {
141 };
144 {
155 },
166 },
177 },
178 };
180 /* Similar but tuned for code size instead of execution latency. The
181 extra +N is fractional cost tuning based on latency. It's used to
182 encourage use of cheaper insns like shift, but only if there's just
183 one of them. */
186 {
196 };
198 /* Get the number of args of a function in one of two ways. */
199 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
200 #define NUM_ARGS current_function_args_info.num_args
201 #else
202 #define NUM_ARGS current_function_args_info
203 #endif
205 #define REG_PV 27
206 #define REG_RA 26
208 /* Declarations of static functions. */
212 #if TARGET_ABI_OPEN_VMS
214 #endif
220 \f
221 /* Parse target option strings. */
223 void
225 {
232 #define EV5_MASK (MASK_CPU_EV5)
233 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
249 };
251 /* Unicos/Mk doesn't have shared libraries. */
253 {
257 }
259 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
260 floating-point instructions. Make that the default for this target. */
263 else
269 /* We cannot use su and sui qualifiers for conversion instructions on
270 Unicos/Mk. I'm not sure if this is due to assembler or hardware
271 limitations. Right now, we issue a warning if -mieee is specified
272 and then ignore it; eventually, we should either get it right or
273 disable the option altogether. */
276 {
279 else
280 {
283 }
284 }
287 {
290 else
291 {
294 }
295 }
298 {
305 else
307 }
310 {
319 else
321 alpha_fprm_string);
322 }
325 {
334 else
336 }
339 {
346 else
348 }
350 alpha_cpu
355 {
358 {
364 }
367 }
370 {
373 {
376 }
379 }
381 /* Do some sanity checks on the above options. */
384 {
387 }
391 {
394 }
397 {
398 /* Except for EV6 pass 1 (not released), we always have precise
399 arithmetic traps. Which means we can do software completion
400 without minding trap shadows. */
402 }
405 {
407 {
410 }
412 {
415 }
419 }
421 {
430 ;
434 {
436 {
440 };
444 {
448 }
449 else
451 }
453 {
454 /* Most current memories have about 370ns latency. This is
455 a reasonable guess for a fast cpu. */
457 }
458 else
459 {
462 }
465 }
467 /* Default the definition of "small data" to 8 bytes. */
471 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
477 /* Align labels and loops for optimal branching. */
478 /* ??? Kludge these by not doing anything if we don't optimize and also if
479 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
481 {
486 }
490 /* Acquire a unique set number for our register saves and restores. */
493 /* Register variables and functions with the garbage collector. */
495 /* Set up function hooks. */
498 /* Tell the compiler when we're using VAX floating point. */
500 {
504 }
505 }
506 \f
507 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
509 int
511 {
520 }
522 /* Returns 1 if OP is either the constant zero or a register. If a
523 register, it must be in the proper mode unless MODE is VOIDmode. */
525 int
527 {
529 }
531 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
532 any register. */
534 int
536 {
540 }
543 /* Return 1 if OP is an 8-bit constant or any register. */
545 int
547 {
551 }
553 /* Return 1 if OP is a constant or any register. */
555 int
557 {
559 }
561 /* Return 1 if OP is an 8-bit constant. */
563 int
565 {
568 }
570 /* Return 1 if the operand is a valid second operand to an add insn. */
572 int
574 {
576 /* Constraints I, J, O and P are covered by K. */
581 }
583 /* Return 1 if the operand is a valid second operand to a sign-extending
584 add insn. */
586 int
588 {
594 }
596 /* Return 1 if OP is the constant 4 or 8. */
598 int
600 {
603 }
605 /* Return 1 if OP is a valid first operand to an AND insn. */
607 int
609 {
620 }
622 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
624 int
626 {
632 }
634 /* Return 1 if OP is a constant that is the width, in bits, of an integral
635 mode smaller than DImode. */
637 int
639 {
643 }
645 /* Return 1 if OP is a constant that is the width of an integral machine mode
646 smaller than an integer. */
648 int
650 {
652 {
663 }
665 {
668 }
671 }
673 /* Return 1 if OP is a multiple of 8 less than 64. */
675 int
677 {
681 }
683 /* Return 1 if OP is the zero constant for MODE. */
685 int
687 {
689 }
691 /* Return 1 if OP is a hard floating-point register. */
693 int
695 {
702 }
704 /* Return 1 if OP is a hard general register. */
706 int
708 {
715 }
717 /* Return 1 if OP is a register or a constant integer. */
720 int
722 {
725 }
727 /* Return 1 if OP is something that can be reloaded into a register;
728 if it is a MEM, it need not be valid. */
730 int
732 {
737 {
754 }
757 }
759 /* Likewise, but don't accept constants. */
761 int
763 {
771 }
773 /* Return 1 if OP is a valid operand for the source of a move insn. */
775 int
777 {
785 {
790 {
791 /* We don't split symbolic operands into something unintelligable
792 until after reload, but we do not wish non-small, non-global
793 symbolic operands to be reconstructed from their high/lo_sum
794 form. */
799 }
801 /* This handles both the Windows/NT and OSF cases. */
815 /* ... fall through ... */
829 }
832 }
834 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
835 file, and in the same section as the current function. */
837 int
839 {
843 /* Easy test for recursion. */
847 /* Functions that are not local can be overridden, and thus may
848 not share the same gp. */
852 /* If -msmall-data is in effect, assume that there is only one GP
853 for the module, and so any local symbol has this property. We
854 need explicit relocations to be able to enforce this for symbols
855 not defined in this unit of translation, however. */
859 /* Functions that are not external are defined in this UoT,
860 and thus must share the same gp. */
862 }
864 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
866 int
868 {
871 /* Must share the same GP. */
875 /* If profiling is implemented via linker tricks, we can't jump
876 to the nogp alternate entry point. Note that current_function_profile
877 would not be correct, since that doesn't indicate if the target
878 function uses profiling. */
879 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
880 but is approximately correct for the OSF ABIs. Don't know
881 what to do for VMS, NT, or UMK. */
885 /* Must be a function. In some cases folks create thunks in static
886 data structures and then make calls to them. If we allow the
887 direct call, we'll get an error from the linker about !samegp reloc
888 against a symbol without a .prologue directive. */
892 /* Must be "near" so that the branch is assumed to reach. With
893 -msmall-text, this is assumed true of all local symbols. Since
894 we've already checked samegp, locality is already assured. */
898 /* Otherwise, a decl is "near" if it is defined in the same section. */
913 }
915 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
916 a (non-tls) variable known to be defined in this file. */
918 int
920 {
936 }
938 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
939 known to be defined in this file in the small data area. */
941 int
943 {
958 /* ??? There's no encode_section_info equivalent for the rtl
959 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
966 }
968 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
969 not known (or known not) to be defined in this file. */
971 int
973 {
986 }
988 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
990 int
992 {
997 {
999 {
1000 /* Disallow virtual registers to cope with pathological test cases
1001 such as compile/930117-1.c in which the virtual reg decomposes
1002 to the frame pointer. Which is a hard reg that is not $27. */
1004 }
1005 else
1007 }
1014 }
1016 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1017 possibly with an offset. */
1019 int
1021 {
1032 }
1034 /* Return true if OP is valid for a particular TLS relocation. */
1036 static int
1038 {
1054 {
1057 }
1058 else
1059 {
1062 }
1065 {
1074 }
1075 }
1077 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1079 int
1081 {
1083 }
1085 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1087 int
1089 {
1091 }
1093 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1095 int
1097 {
1099 }
1101 /* Return true if OP is valid for 16-bit TP relative relocations. */
1103 int
1105 {
1107 }
1109 /* Return true if OP is valid for 32-bit TP relative relocations. */
1111 int
1113 {
1115 }
1117 /* Return true if OP is valid for 64-bit TP relative relocations. */
1119 int
1121 {
1123 }
1125 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1126 comparisons are valid in which insn. */
1128 int
1130 {
1138 }
1140 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1141 Here we know which comparisons are valid in which insn. */
1143 int
1145 {
1153 }
1155 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1157 int
1159 {
1169 }
1171 /* Return 1 if OP is a signed comparison operation. */
1173 int
1175 {
1184 }
1186 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1187 Here we know which comparisons are valid in which insn. */
1189 int
1191 {
1198 }
1200 /* Return 1 if this is a divide or modulus operator. */
1202 int
1204 {
1208 }
1210 /* Return 1 if this is a float->int conversion operator. */
1212 int
1214 {
1218 }
1220 /* Return 1 if this memory address is a known aligned register plus
1221 a constant. It must be a valid address. This means that we can do
1222 this as an aligned reference plus some offset.
1224 Take into account what reload will do. */
1226 int
1228 {
1229 rtx base;
1232 {
1238 {
1242 }
1243 }
1251 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1252 sorts of constructs. Dig for the real base register. */
1257 else
1258 {
1262 }
1265 }
1267 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1269 int
1271 {
1272 rtx base;
1275 {
1281 {
1285 }
1286 }
1294 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1295 sorts of constructs. Dig for the real base register. */
1300 else
1301 {
1305 }
1308 }
1310 /* Return 1 if OP is either a register or an unaligned memory location. */
1312 int
1314 {
1316 }
1318 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1320 int
1322 {
1330 }
1332 /* Returns 1 if OP is not an eliminable register.
1334 This exists to cure a pathological abort in the s8addq (et al) patterns,
1336 long foo () { long t; bar(); return (long) &t * 26107; }
1338 which run afoul of a hack in reload to cure a (presumably) similar
1339 problem with lea-type instructions on other targets. But there is
1340 one of us and many of them, so work around the problem by selectively
1341 preventing combine from making the optimization. */
1343 int
1345 {
1353 }
1355 /* Return 1 is OP is a memory location that is not a reference (using
1356 an AND) to an unaligned location. Take into account what reload
1357 will do. */
1359 int
1361 {
1363 {
1369 {
1372 /* This may not have been assigned an equivalent address if it will
1373 be eliminated. In that case, it doesn't matter what we do. */
1376 }
1377 }
1380 }
1382 /* Accept a register, but not a subreg of any kind. This allows us to
1383 avoid pathological cases in reload wrt data movement common in
1384 int->fp conversion. */
1386 int
1388 {
1392 }
1394 /* Recognize an addition operation that includes a constant. Used to
1395 convince reload to canonize (plus (plus reg c1) c2) during register
1396 elimination. */
1398 int
1400 {
1409 }
1411 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1412 the range defined for C in [I-P]. */
1414 bool
1416 {
1418 {
1420 /* An unsigned 8 bit constant. */
1423 /* The constant zero. */
1426 /* A signed 16 bit constant. */
1429 /* A shifted signed 16 bit constant appropriate for LDAH. */
1433 /* A constant that can be AND'ed with using a ZAP insn. */
1436 /* A complemented unsigned 8 bit constant. */
1439 /* A negated unsigned 8 bit constant. */
1442 /* The constant 1, 2 or 3. */
1447 }
1448 }
1450 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1451 matches for C in [GH]. */
1453 bool
1455 {
1457 {
1459 /* The floating point zero constant. */
1464 /* A valid operand of a ZAP insn. */
1471 }
1472 }
1474 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1475 matches for C. */
1477 bool
1479 {
1481 {
1498 }
1499 }
1501 /* Return 1 if this function can directly return via $26. */
1503 int
1505 {
1507 && reload_completed
1512 }
1514 /* Return the ADDR_VEC associated with a tablejump insn. */
1516 rtx
1518 {
1519 rtx tmp;
1531 }
1533 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1535 rtx
1537 {
1541 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1542 there for edge frequency counts from profile data. */
1545 {
1551 {
1557 count++;
1561 }
1562 }
1565 }
1567 /* Return the TLS model to use for SYMBOL. */
1569 static enum tls_model
1571 {
1578 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1583 }
1584 \f
1585 /* Return true if the function DECL will share the same GP as any
1586 function in the current unit of translation. */
1588 static bool
1590 {
1591 /* Functions that are not local can be overridden, and thus may
1592 not share the same gp. */
1596 /* If -msmall-data is in effect, assume that there is only one GP
1597 for the module, and so any local symbol has this property. We
1598 need explicit relocations to be able to enforce this for symbols
1599 not defined in this unit of translation, however. */
1603 /* Functions that are not external are defined in this UoT. */
1604 /* ??? Irritatingly, static functions not yet emitted are still
1605 marked "external". Apply this to non-static functions only. */
1607 }
1609 /* Return true if EXP should be placed in the small data section. */
1611 static bool
1613 {
1614 /* We want to merge strings, so we never consider them small data. */
1618 /* Functions are never in the small data area. Duh. */
1623 {
1628 }
1629 else
1630 {
1633 /* If this is an incomplete type with size 0, then we can't put it
1634 in sdata because it might be too big when completed. */
1637 }
1640 }
1642 #if TARGET_ABI_OPEN_VMS
1643 static bool
1645 {
1652 }
1654 #define LINKAGE_SYMBOL_REF_P(X) \
1655 ((GET_CODE (X) == SYMBOL_REF \
1656 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1657 || (GET_CODE (X) == CONST \
1658 && GET_CODE (XEXP (X, 0)) == PLUS \
1659 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1660 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1661 #endif
1663 /* legitimate_address_p recognizes an RTL expression that is a valid
1664 memory address for an instruction. The MODE argument is the
1665 machine mode for the MEM expression that wants to use this address.
1667 For Alpha, we have either a constant address or the sum of a
1668 register and a constant address, or just a register. For DImode,
1669 any of those forms can be surrounded with an AND that clear the
1670 low-order three bits; this is an "unaligned" access. */
1672 bool
1674 {
1675 /* If this is an ldq_u type address, discard the outer AND. */
1682 /* Discard non-paradoxical subregs. */
1688 /* Unadorned general registers are valid. */
1690 && (strict
1695 /* Constant addresses (i.e. +/- 32k) are valid. */
1699 #if TARGET_ABI_OPEN_VMS
1702 #endif
1704 /* Register plus a small constant offset is valid. */
1706 {
1710 /* Discard non-paradoxical subregs. */
1717 {
1727 }
1731 }
1733 /* If we're managing explicit relocations, LO_SUM is valid, as
1734 are small data symbols. */
1736 {
1741 {
1745 /* Discard non-paradoxical subregs. */
1751 /* Must have a valid base register. */
1753 && (strict
1758 /* The symbol must be local. */
1763 }
1764 }
1767 }
1769 /* Build the SYMBOL_REF for __tls_get_addr. */
1773 static rtx
1775 {
1779 }
1781 /* Try machine-dependent ways of modifying an illegitimate address
1782 to be legitimate. If we find one, return the new, valid address. */
1784 rtx
1787 {
1788 HOST_WIDE_INT addend;
1790 /* If the address is (plus reg const_int) and the CONST_INT is not a
1791 valid offset, compute the high part of the constant and add it to
1792 the register. Then our address is (plus temp low-part-const). */
1797 {
1801 }
1803 /* If the address is (const (plus FOO const_int)), find the low-order
1804 part of the CONST_INT. Then load FOO plus any high-order part of the
1805 CONST_INT into a register. Our address is (plus reg low-part-const).
1806 This is done to reduce the number of GOT entries. */
1811 {
1815 }
1817 /* If we have a (plus reg const), emit the load as in (2), then add
1818 the two registers, and finally generate (plus reg low-part-const) as
1819 our address. */
1826 {
1832 }
1834 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1836 {
1840 {
1881 UNSPEC_TLSLDM_CALL);
1888 {
1893 }
1895 {
1900 }
1922 {
1927 }
1929 }
1932 {
1935 else
1936 {
1942 }
1943 }
1944 }
1948 split_addend:
1949 {
1967 }
1968 }
1970 /* We do not allow indirect calls to be optimized into sibling calls, nor
1971 can we allow a call to a function with a different GP to be optimized
1972 into a sibcall. */
1974 static bool
1976 {
1977 /* Can't do indirect tail calls, since we don't know if the target
1978 uses the same GP. */
1982 /* Otherwise, we can make a tail call if the target function shares
1983 the same GP. */
1985 }
1987 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1988 small symbolic operand until after reload. At which point we need
1989 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1990 so that sched2 has the proper dependency information. */
1992 static int
1994 {
1997 /* Don't re-split. */
2002 }
2004 int
2006 {
2008 }
2010 static int
2012 {
2015 /* Don't re-split. */
2020 {
2024 }
2027 }
2029 rtx
2031 {
2035 }
2037 /* Indicate that INSN cannot be duplicated. This is true for any insn
2038 that we've marked with gpdisp relocs, since those have to stay in
2039 1-1 correspondence with one another.
2041 Technically we could copy them if we could set up a mapping from one
2042 sequence number to another, across the set of insns to be duplicated.
2043 This seems overly complicated and error-prone since interblock motion
2044 from sched-ebb could move one of the pair of insns to a different block.
2046 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2047 then they'll be in a different block from their ldgp. Which could lead
2048 the bb reorder code to think that it would be ok to copy just the block
2049 containing the call and branch to the block containing the ldgp. */
2051 static bool
2053 {
2058 else
2060 }
2063 /* Try a machine-dependent way of reloading an illegitimate address
2064 operand. If we find one, push the reload and return the new rtx. */
2066 rtx
2071 {
2072 /* We must recognize output that we have already generated ourselves. */
2078 {
2083 }
2085 /* We wish to handle large displacements off a base register by
2086 splitting the addend across an ldah and the mem insn. This
2087 cuts number of extra insns needed from 3 to 1. */
2093 {
2096 HOST_WIDE_INT high
2099 /* Check for 32-bit overflow. */
2103 /* Reload the high part into a base reg; leave the low part
2104 in the mem directly. */
2114 }
2117 }
2118 \f
2119 /* Compute a (partial) cost for rtx X. Return true if the complete
2120 cost has been computed, and false if subexpressions should be
2121 scanned. In either case, *TOTAL contains the cost result. */
2123 static bool
2125 {
2132 else
2136 {
2138 /* If this is an 8-bit constant, return zero since it can be used
2139 nearly anywhere with no cost. If it is a valid operand for an
2140 ADD or AND, likewise return 0 if we know it will be used in that
2141 context. Otherwise, return 2 since it might be used there later.
2142 All other constants take at least two insns. */
2144 {
2147 }
2148 /* FALLTHRU */
2158 else
2170 /* Estimate of cost for call_pal rduniq. */
2171 /* ??? How many insns do we emit here? More than one... */
2173 else
2174 /* Otherwise we do a load from the GOT. */
2184 {
2188 }
2196 else
2203 {
2206 }
2207 /* FALLTHRU */
2217 else
2229 else
2239 {
2242 }
2243 /* FALLTHRU */
2247 {
2250 }
2251 /* FALLTHRU */
2264 }
2265 }
2266 \f
2267 /* REF is an alignable memory location. Place an aligned SImode
2268 reference into *PALIGNED_MEM and the number of bits to shift into
2269 *PBITNUM. SCRATCH is a free register for use in reloading out
2270 of range stack slots. */
2272 void
2274 {
2275 rtx base;
2283 {
2288 }
2289 else
2290 {
2292 }
2297 *paligned_mem
2303 else
2305 }
2307 /* Similar, but just get the address. Handle the two reload cases.
2308 Add EXTRA_OFFSET to the address we return. */
2310 rtx
2312 {
2313 rtx base;
2321 {
2326 }
2327 else
2328 {
2330 }
2336 }
2338 /* On the Alpha, all (non-symbolic) constants except zero go into
2339 a floating-point register via memory. Note that we cannot
2340 return anything that is not a subset of CLASS, and that some
2341 symbolic constants cannot be dropped to memory. */
2343 enum reg_class
2345 {
2346 /* Zero is present in any register class. */
2350 /* These sorts of constants we can easily drop to memory. */
2352 {
2358 }
2360 /* All other kinds of constants should not (and in the case of HIGH
2361 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2362 secondary reload. */
2367 }
2369 /* Loading and storing HImode or QImode values to and from memory
2370 usually requires a scratch register. The exceptions are loading
2371 QImode and HImode from an aligned address to a general register
2372 unless byte instructions are permitted.
2374 We also cannot load an unaligned address or a paradoxical SUBREG
2375 into an FP register.
2377 We also cannot do integral arithmetic into FP regs, as might result
2378 from register elimination into a DImode fp register. */
2380 enum reg_class
2383 {
2385 {
2392 {
2395 }
2396 }
2399 {
2411 }
2414 }
2415 \f
2416 /* Subfunction of the following function. Update the flags of any MEM
2417 found in part of X. */
2419 static void
2421 {
2425 {
2432 unchanging_p);
2437 unchanging_p);
2442 unchanging_p);
2444 unchanging_p);
2451 /* Sadly, we cannot use alias sets because the extra aliasing
2452 produced by the AND interferes. Given that two-byte quantities
2453 are the only thing we would be able to differentiate anyway,
2454 there does not seem to be any point in convoluting the early
2455 out of the alias check. */
2460 }
2461 }
2463 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2464 generated to perform a memory operation, look for any MEMs in either
2465 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2466 volatile flags from REF into each of the MEMs found. If REF is not
2467 a MEM, don't do anything. */
2469 void
2471 {
2481 /* This is only called from alpha.md, after having had something
2482 generated from one of the insn patterns. So if everything is
2483 zero, the pattern is already up-to-date. */
2488 }
2489 \f
2490 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2492 static rtx
2495 {
2498 /* Use a pseudo if highly optimizing and still generating RTL. */
2499 rtx subtarget
2503 /* If this is a sign-extended 32-bit constant, we can do this in at most
2504 three insns, so do it if we have enough insns left. We always have
2505 a sign-extended 32-bit constant when compiling on a narrow machine. */
2509 {
2515 /* If HIGH will be interpreted as negative but the constant is
2516 positive, we must adjust it to do two ldha insns. */
2519 {
2523 }
2526 {
2527 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2528 but that meant that we can't handle INT_MIN on 32-bit machines
2529 (like NT/Alpha), because we recurse indefinitely through
2530 emit_move_insn to gen_movdi. So instead, since we know exactly
2531 what we want, create it explicitly. */
2537 }
2539 {
2541 {
2544 }
2545 else
2549 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2550 This means that if we go through expand_binop, we'll try to
2551 generate extensions, etc, which will require new pseudos, which
2552 will fail during some split phases. The SImode add patterns
2553 still exist, but are not named. So build the insns by hand. */
2556 {
2563 }
2571 }
2572 }
2574 /* If we couldn't do it that way, try some other methods. But if we have
2575 no instructions left, don't bother. Likewise, if this is SImode and
2576 we can't make pseudos, we can't do anything since the expand_binop
2577 and expand_unop calls will widen and try to make pseudos. */
2582 /* Next, see if we can load a related constant and then shift and possibly
2583 negate it to get the constant we want. Try this once each increasing
2584 numbers of insns. */
2587 {
2588 /* First, see if minus some low bits, we've an easy load of
2589 high bits. */
2597 /* Next try complementing. */
2601 /* Next try to form a constant and do a left shift. We can do this
2602 if some low-order bits are zero; the exact_log2 call below tells
2603 us that information. The bits we are shifting out could be any
2604 value, but here we'll just try the 0- and sign-extended forms of
2605 the constant. To try to increase the chance of having the same
2606 constant in more than one insn, start at the highest number of
2607 bits to shift, but try all possibilities in case a ZAPNOT will
2608 be useful. */
2621 /* Now try high-order zero bits. Here we try the shifted-in bits as
2622 all zero and all ones. Be careful to avoid shifting outside the
2623 mode and to avoid shifting outside the host wide int size. */
2624 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2625 confuse the recursive call and set all of the high 32 bits. */
2635 i)))
2640 /* Now try high-order 1 bits. We get that with a sign-extension.
2641 But one bit isn't enough here. Be careful to avoid shifting outside
2642 the mode and to avoid shifting outside the host wide int size. */
2652 i)))
2656 }
2658 #if HOST_BITS_PER_WIDE_INT == 64
2659 /* Finally, see if can load a value into the target that is the same as the
2660 constant except that all bytes that are 0 are changed to be 0xff. If we
2661 can, then we can do a ZAPNOT to obtain the desired constant. */
2668 /* We are only called for SImode and DImode. If this is SImode, ensure that
2669 we are sign extended to a full word. */
2678 #endif
2681 }
2683 /* Try to output insns to set TARGET equal to the constant C if it can be
2684 done in less than N insns. Do all computations in MODE. Returns the place
2685 where the output has been placed if it can be done and the insns have been
2686 emitted. If it would take more than N insns, zero is returned and no
2687 insns and emitted. */
2689 rtx
2692 {
2697 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2698 can't load this constant in one insn, do this in DImode. */
2702 {
2705 }
2707 /* Try 1 insn, then 2, then up to N. */
2709 {
2712 {
2718 }
2719 }
2721 /* Allow for the case where we changed the mode of TARGET. */
2726 }
2728 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2729 fall back to a straight forward decomposition. We do this to avoid
2730 exponential run times encountered when looking for longer sequences
2731 with alpha_emit_set_const. */
2733 rtx
2735 {
2738 /* Decompose the entire word */
2739 #if HOST_BITS_PER_WIDE_INT >= 64
2751 #else
2763 #endif
2765 /* Construct the high word */
2767 {
2771 }
2772 else
2775 /* Shift it into place */
2778 /* Add in the low bits. */
2785 }
2787 /* Expand a move instruction; return true if all work is done.
2788 We don't handle non-bwx subword loads here. */
2790 bool
2792 {
2793 /* If the output is not a register, the input must be. */
2798 /* Allow legitimize_address to perform some simplifications. */
2800 {
2801 rtx tmp;
2803 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2804 compiled at the end of compilation. In the meantime, someone can
2805 re-encode-section-info on some symbol changing it e.g. from global
2806 to local-not-small. If this happens, we'd have emitted a plain
2807 load rather than a high+losum load and not recognize the insn.
2809 So if rtl inlining is in effect, we delay the global/not-global
2810 decision until rest_of_compilation by wrapping it in an
2811 UNSPEC_SYMBOL. */
2813 && rtx_equal_function_value_matters
2815 {
2818 }
2822 {
2827 }
2828 }
2830 /* Early out for non-constants and valid constants. */
2834 /* Split large integers. */
2837 {
2842 {
2845 }
2847 {
2850 }
2851 else
2852 {
2855 }
2864 {
2869 }
2870 }
2872 /* Otherwise we've nothing left but to drop the thing to memory. */
2875 {
2879 }
2880 else
2883 }
2885 /* Expand a non-bwx QImode or HImode move instruction;
2886 return true if all work is done. */
2888 bool
2890 {
2891 /* If the output is not a register, the input must be. */
2895 /* Handle four memory cases, unaligned and aligned for either the input
2896 or the output. The only case where we can be called during reload is
2897 for aligned loads; all other cases require temporaries. */
2907 {
2909 {
2911 {
2913 ? gen_reload_inqi_help
2917 }
2918 else
2919 {
2922 rtx subtarget;
2930 else
2934 ? gen_aligned_loadqi
2940 }
2941 }
2942 else
2943 {
2944 /* Don't pass these as parameters since that makes the generated
2945 code depend on parameter evaluation order which will cause
2946 bootstrap failures. */
2957 else
2961 ? gen_unaligned_loadqi
2970 }
2972 }
2982 {
2984 {
2993 }
2994 else
2995 {
3000 ? gen_unaligned_storeqi
3007 }
3009 }
3012 }
3014 /* Generate an unsigned DImode to FP conversion. This is the same code
3015 optabs would emit if we didn't have TFmode patterns.
3017 For SFmode, this is the only construction I've found that can pass
3018 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3019 intermediates will work, because you'll get intermediate rounding
3020 that ruins the end result. Some of this could be fixed by turning
3021 on round-to-positive-infinity, but that requires diddling the fpsr,
3022 which kills performance. I tried turning this around and converting
3023 to a negative number, so that I could turn on /m, but either I did
3024 it wrong or there's something else cause I wound up with the exact
3025 same single-bit error. There is a branch-less form of this same code:
3027 srl $16,1,$1
3028 and $16,1,$2
3029 cmplt $16,0,$3
3030 or $1,$2,$2
3031 cmovge $16,$16,$2
3032 itoft $3,$f10
3033 itoft $2,$f11
3034 cvtqs $f11,$f11
3035 adds $f11,$f11,$f0
3036 fcmoveq $f10,$f11,$f0
3038 I'm not using it because it's the same number of instructions as
3039 this branch-full form, and it has more serialized long latency
3040 instructions on the critical path.
3042 For DFmode, we can avoid rounding errors by breaking up the word
3043 into two pieces, converting them separately, and adding them back:
3045 LC0: .long 0,0x5f800000
3047 itoft $16,$f11
3048 lda $2,LC0
3049 cmplt $16,0,$1
3050 cpyse $f11,$f31,$f10
3051 cpyse $f31,$f11,$f11
3052 s4addq $1,$2,$1
3053 lds $f12,0($1)
3054 cvtqt $f10,$f10
3055 cvtqt $f11,$f11
3056 addt $f12,$f10,$f0
3057 addt $f0,$f11,$f0
3059 This doesn't seem to be a clear-cut win over the optabs form.
3060 It probably all depends on the distribution of numbers being
3061 converted -- in the optabs form, all but high-bit-set has a
3062 much lower minimum execution time. */
3064 void
3066 {
3094 }
3096 /* Generate the comparison for a conditional branch. */
3098 rtx
3100 {
3104 rtx tem;
3107 {
3111 /* X_floating library comparison functions return
3112 -1 unordered
3113 0 false
3114 1 true
3115 Convert the compare against the raw return value. */
3118 {
3135 }
3140 }
3142 /* The general case: fold the comparison code to the types of compares
3143 that we have, choosing the branch as necessary. */
3145 {
3148 /* We have these compares: */
3154 /* These must be reversed. */
3159 /* For FP, we swap them, for INT, we reverse them. */
3161 {
3165 }
3166 else
3167 {
3170 }
3175 }
3178 {
3181 {
3182 /* When we are not as concerned about non-finite values, and we
3183 are comparing against zero, we can branch directly. */
3187 {
3188 /* Undo the swap we probably did just above. */
3192 }
3193 }
3194 else
3195 {
3196 /* ??? We mark the branch mode to be CCmode to prevent the
3197 compare and branch from being combined, since the compare
3198 insn follows IEEE rules that the branch does not. */
3200 }
3201 }
3202 else
3203 {
3206 /* The following optimizations are only for signed compares. */
3208 {
3209 /* Whee. Compare and branch against 0 directly. */
3213 /* If the constants doesn't fit into an immediate, but can
3214 be generated by lda/ldah, we adjust the argument and
3215 compare against zero, so we can use beq/bne directly. */
3216 /* ??? Don't do this when comparing against symbols, otherwise
3217 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
3218 be declared false out of hand (at least for non-weak). */
3223 {
3229 {
3232 }
3233 }
3234 }
3240 }
3242 /* Emit an initial compare instruction, if necessary. */
3245 {
3248 }
3250 /* Zero the operands. */
3253 /* Return the branch comparison. */
3255 }
3257 /* Certain simplifications can be done to make invalid setcc operations
3258 valid. Return the final comparison, or NULL if we can't work. */
3260 rtx
3262 {
3266 rtx tmp;
3268 /* Zero the operands. */
3272 {
3276 /* X_floating library comparison functions return
3277 -1 unordered
3278 0 false
3279 1 true
3280 Convert the compare against the raw return value. */
3284 else
3295 else
3297 }
3302 /* The general case: fold the comparison code to the types of compares
3303 that we have, choosing the branch as necessary. */
3307 {
3310 /* We have these compares. */
3318 /* FALLTHRU */
3326 /* These normally need swapping, but for integer zero we have
3327 special patterns that recognize swapped operands. */
3338 }
3341 {
3346 }
3348 /* Emit an initial compare instruction, if necessary. */
3350 {
3359 }
3361 /* Return the setcc comparison. */
3363 }
3366 /* Rewrite a comparison against zero CMP of the form
3367 (CODE (cc0) (const_int 0)) so it can be written validly in
3368 a conditional move (if_then_else CMP ...).
3369 If both of the operands that set cc0 are nonzero we must emit
3370 an insn to perform the compare (it can't be done within
3371 the conditional move). */
3373 rtx
3375 {
3381 enum machine_mode cmp_mode
3386 rtx tem;
3388 /* Zero the operands. */
3392 {
3398 /* If we have fp<->int register move instructions, do a cmov by
3399 performing the comparison in fp registers, and move the
3400 zero/nonzero value to integer registers, where we can then
3401 use a normal cmov, or vice-versa. */
3404 {
3406 /* We have these compares. */
3411 /* This must be reversed. */
3416 /* These normally need swapping, but for integer zero we have
3417 special patterns that recognize swapped operands. */
3420 else
3421 {
3425 }
3430 }
3442 }
3444 /* We may be able to use a conditional move directly.
3445 This avoids emitting spurious compares. */
3451 /* We can't put the comparison inside the conditional move;
3452 emit a compare instruction and put that inside the
3453 conditional move. Make sure we emit only comparisons we have;
3454 swap or reverse as necessary. */
3460 {
3462 /* We have these compares: */
3466 /* This must be reversed. */
3472 /* These must be swapped. */
3474 {
3477 }
3482 }
3485 {
3490 }
3492 /* ??? We mark the branch mode to be CCmode to prevent the compare
3493 and cmov from being combined, since the compare insn follows IEEE
3494 rules that the cmov does not. */
3501 }
3503 /* Simplify a conditional move of two constants into a setcc with
3504 arithmetic. This is done with a splitter since combine would
3505 just undo the work if done during code generation. It also catches
3506 cases we wouldn't have before cse. */
3508 int
3511 {
3523 {
3527 }
3531 {
3535 else
3537 }
3538 /* Below, we must be careful to use copy_rtx on target and subtarget
3539 in intermediate insns, as they may be a subreg rtx, which may not
3540 be shared. */
3543 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3544 viable over a longer latency cmove. On EV5, the E0 slot is a
3545 scarce resource, and on EV4 shift has the same latency as a cmove. */
3547 {
3554 }
3556 {
3561 }
3563 {
3564 rtx add_op;
3571 else
3572 {
3575 {
3580 }
3581 else
3583 }
3584 }
3585 else
3589 }
3590 \f
3591 /* Look up the function X_floating library function name for the
3592 given operation. */
3595 {
3599 rtx libcall;
3600 };
3603 {
3619 };
3622 {
3625 };
3627 static rtx
3629 {
3634 /* How irritating. Nothing to key off for the main table. */
3636 {
3639 }
3643 {
3646 {
3650 }
3652 }
3655 }
3657 /* Most X_floating operations take the rounding mode as an argument.
3658 Compute that here. */
3660 static int
3663 {
3667 {
3683 /* XXX For reference, round to +inf is mode = 3. */
3684 }
3690 }
3692 /* Emit an X_floating library function call.
3694 Note that these functions do not follow normal calling conventions:
3695 TFmode arguments are passed in two integer registers (as opposed to
3696 indirect); TFmode return values appear in R16+R17.
3698 FUNC is the function to call.
3699 TARGET is where the output belongs.
3700 OPERANDS are the inputs.
3701 NOPERANDS is the count of inputs.
3702 EQUIV is the expression equivalent for the function.
3703 */
3705 static void
3708 {
3715 {
3717 {
3731 /* FALLTHRU */
3739 }
3743 }
3746 {
3758 }
3770 }
3772 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3774 void
3776 {
3777 rtx func;
3790 }
3792 /* Emit an X_floating library function call for a comparison. */
3794 static rtx
3796 {
3797 rtx func;
3806 /* ??? Strange mode for equiv because what's actually returned
3807 is -1,0,1, not a proper boolean value. */
3812 }
3814 /* Emit an X_floating library function call for a conversion. */
3816 void
3818 {
3821 rtx func;
3832 {
3845 }
3851 }
3853 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3854 OP[0] into OP[0,1]. Naturally, output operand ordering is
3855 little-endian. */
3857 void
3859 {
3861 {
3864 }
3866 {
3869 }
3872 else
3876 {
3879 }
3881 {
3884 }
3885 else
3887 }
3889 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3890 op2 is a register containing the sign bit, operation is the
3891 logical operation to be performed. */
3893 void
3895 {
3897 rtx scratch;
3902 /* Detect three flavors of operand overlap. */
3907 {
3910 else
3912 }
3917 /* ??? If the destination overlaps both source tf and high_bit, then
3918 assume source tf is dead in its entirety and use the other half
3919 for a scratch register. Otherwise "scratch" is just the proper
3920 destination register. */
3926 {
3930 }
3931 }
3932 \f
3933 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3934 unaligned data:
3936 unsigned: signed:
3937 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3938 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3939 lda r3,X(r11) lda r3,X+2(r11)
3940 extwl r1,r3,r1 extql r1,r3,r1
3941 extwh r2,r3,r2 extqh r2,r3,r2
3942 or r1.r2.r1 or r1,r2,r1
3943 sra r1,48,r1
3945 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3946 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3947 lda r3,X(r11) lda r3,X(r11)
3948 extll r1,r3,r1 extll r1,r3,r1
3949 extlh r2,r3,r2 extlh r2,r3,r2
3950 or r1.r2.r1 addl r1,r2,r1
3952 quad: ldq_u r1,X(r11)
3953 ldq_u r2,X+7(r11)
3954 lda r3,X(r11)
3955 extql r1,r3,r1
3956 extqh r2,r3,r2
3957 or r1.r2.r1
3958 */
3960 void
3963 {
3977 /* AND addresses cannot be in any alias set, since they may implicitly
3978 alias surrounding code. Ideally we'd have some alias set that
3979 covered all types except those with alignment 8 or higher. */
3996 {
4005 }
4007 {
4013 /* We must use tgt here for the target. Alpha-vms port fails if we use
4014 addr for the target, because addr is marked as a pointer and combine
4015 knows that pointers are always sign-extended 32 bit values. */
4019 }
4020 else
4021 {
4023 {
4026 {
4044 }
4046 }
4047 else
4048 {
4052 {
4070 }
4071 }
4076 }
4080 }
4082 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4084 void
4087 {
4099 /* AND addresses cannot be in any alias set, since they may implicitly
4100 alias surrounding code. Ideally we'd have some alias set that
4101 covered all types except those with alignment 8 or higher. */
4118 {
4122 {
4124 {
4134 }
4137 }
4140 {
4145 {
4149 }
4153 }
4156 }
4157 else
4158 {
4162 {
4167 {
4177 }
4178 }
4183 {
4188 {
4192 }
4196 }
4197 }
4200 {
4203 }
4206 {
4209 }
4210 else
4211 {
4212 /* Must store high before low for degenerate case of aligned. */
4215 }
4216 }
4218 /* The block move code tries to maximize speed by separating loads and
4219 stores at the expense of register pressure: we load all of the data
4220 before we store it back out. There are two secondary effects worth
4221 mentioning, that this speeds copying to/from aligned and unaligned
4222 buffers, and that it makes the code significantly easier to write. */
4224 #define MAX_MOVE_WORDS 8
4226 /* Load an integral number of consecutive unaligned quadwords. */
4228 static void
4231 {
4236 HOST_WIDE_INT i;
4242 /* Generate all the tmp registers we need. */
4244 {
4247 }
4253 /* Load up all of the source data. */
4255 {
4259 im8));
4262 }
4267 im8));
4271 /* Extract the half-word fragments. Unfortunately DEC decided to make
4272 extxh with offset zero a noop instead of zeroing the register, so
4273 we must take care of that edge condition ourselves with cmov. */
4281 {
4283 {
4286 }
4287 else
4288 {
4291 }
4295 const0_rtx),
4297 }
4299 /* Merge the half-words into whole words. */
4301 {
4304 }
4305 }
4307 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4308 may be NULL to store zeros. */
4310 static void
4313 {
4319 HOST_WIDE_INT i;
4325 /* Generate all the tmp registers we need. */
4338 im8));
4345 /* Load up the destination end bits. */
4349 /* Shift the input data into place. */
4354 {
4356 {
4358 {
4361 }
4362 else
4363 {
4366 }
4367 }
4369 {
4372 OPTAB_WIDEN);
4373 }
4374 }
4376 /* Split and merge the ends with the destination data. */
4378 {
4381 }
4382 else
4383 {
4386 }
4389 {
4394 }
4396 /* Store it all. */
4399 else
4402 {
4407 im8));
4410 }
4413 else
4415 }
4418 /* Expand string/block move operations.
4420 operands[0] is the pointer to the destination.
4421 operands[1] is the pointer to the source.
4422 operands[2] is the number of bytes to move.
4423 operands[3] is the alignment. */
4425 int
4427 {
4437 rtx tmp;
4445 /* Look for additional alignment information from recorded register info. */
4453 {
4458 {
4465 }
4466 }
4474 {
4479 {
4486 }
4487 }
4489 /* Load the entire block into registers. */
4491 {
4496 /* Don't use the existing register if we're reading more than
4497 is held in the register. Nor if there is not a mode that
4498 handles the exact size. */
4503 {
4505 {
4509 }
4510 else
4514 }
4516 /* No appropriate mode; fall back on memory. */
4520 }
4524 {
4537 }
4540 {
4553 }
4556 {
4568 }
4571 {
4576 }
4579 {
4581 {
4588 }
4590 {
4595 }
4596 }
4599 {
4604 }
4606 src_done:
4611 /* Now save it back out again. */
4616 {
4622 {
4624 {
4628 }
4631 {
4632 /* Undo the subregging done above when copying between
4633 two TImode registers. */
4637 else
4638 {
4639 rtx seq;
4649 }
4653 }
4654 }
4656 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4657 /* ??? Optimize mode < dst_mode with strict_low_part. */
4659 /* No appropriate mode; fall back on memory. We can speed things
4660 up by recognizing extra alignment information. */
4664 }
4666 /* Write out the data in whatever chunks reading the source allowed. */
4668 {
4670 {
4674 i++;
4675 }
4676 }
4679 {
4680 /* If the source has remaining DImode regs, write them out in
4681 two pieces. */
4683 {
4692 i++;
4693 }
4696 {
4700 i++;
4701 }
4702 }
4705 {
4706 /* Write out a remaining block of words using unaligned methods. */
4714 else
4720 }
4722 /* Due to the above, this won't be aligned. */
4723 /* ??? If we have more than one of these, consider constructing full
4724 words in registers and using alpha_expand_unaligned_store_words. */
4726 {
4729 i++;
4730 }
4734 {
4736 i++;
4738 }
4739 else
4741 {
4743 i++;
4745 }
4748 {
4750 i++;
4752 }
4754 dst_done:
4760 }
4762 int
4764 {
4772 rtx tmp;
4780 /* Look for stricter alignment. */
4787 {
4792 {
4799 }
4800 }
4802 {
4807 {
4810 }
4812 /* No appropriate mode; fall back on memory. */
4815 }
4817 /* Handle an unaligned prefix first. */
4820 {
4821 #if HOST_BITS_PER_WIDE_INT >= 64
4822 /* Given that alignofs is bounded by align, the only time BWX could
4823 generate three stores is for a 7 byte fill. Prefer two individual
4824 stores over a load/mask/store sequence. */
4828 {
4832 HOST_WIDE_INT mask;
4839 {
4843 }
4844 else
4845 {
4848 }
4855 }
4856 #endif
4859 {
4864 }
4866 {
4871 }
4873 {
4878 }
4880 /* If we've not used the extra lead alignment information by now,
4881 we won't be able to. Downgrade align to match what's left over. */
4883 {
4886 }
4887 }
4889 /* Handle a block of contiguous long-words. */
4892 {
4897 const0_rtx);
4901 }
4903 /* If the block is large and appropriately aligned, emit a single
4904 store followed by a sequence of stq_u insns. */
4907 {
4908 rtx orig_dsta;
4920 {
4921 rtx mem
4928 }
4930 /* Depending on the alignment, the first stq_u may have overlapped
4931 with the initial stl, which means that the last stq_u didn't
4932 write as much as it would appear. Leave those questionable bytes
4933 unaccounted for. */
4936 }
4938 /* Handle a smaller block of aligned words. */
4942 {
4947 const0_rtx);
4951 }
4953 /* An unaligned block uses stq_u stores for as many as possible. */
4956 {
4963 }
4965 /* Next clean up any trailing pieces. */
4967 #if HOST_BITS_PER_WIDE_INT >= 64
4968 /* Count the number of bits in BYTES for which aligned stores could
4969 be emitted. */
4975 /* If we have appropriate alignment (and it wouldn't take too many
4976 instructions otherwise), mask out the bytes we need. */
4978 {
4980 {
4982 HOST_WIDE_INT mask;
4994 }
4996 {
4998 HOST_WIDE_INT mask;
5010 }
5011 }
5012 #endif
5015 {
5019 }
5022 {
5024 {
5027 const0_rtx);
5031 }
5033 {
5037 }
5038 }
5041 {
5045 }
5048 }
5050 /* Returns a mask so that zap(x, value) == x & mask. */
5052 rtx
5054 {
5055 rtx result;
5059 {
5063 {
5067 }
5070 }
5072 {
5076 {
5080 }
5083 {
5087 }
5090 }
5091 else
5095 }
5097 void
5101 {
5106 else
5111 else
5115 }
5116 \f
5117 /* Adjust the cost of a scheduling dependency. Return the new cost of
5118 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5120 static int
5122 {
5125 /* If the dependence is an anti-dependence, there is no cost. For an
5126 output dependence, there is sometimes a cost, but it doesn't seem
5127 worth handling those few cases. */
5131 /* If we can't recognize the insns, we can't really do anything. */
5138 /* Bring in the user-defined memory latency. */
5144 /* Everything else handled in DFA bypasses now. */
5147 }
5149 /* The number of instructions that can be issued per cycle. */
5151 static int
5153 {
5155 }
5157 static int
5159 {
5161 }
5163 /* How many alternative schedules to try. This should be as wide as the
5164 scheduling freedom in the DFA, but no wider. Making this value too
5165 large results extra work for the scheduler.
5167 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5168 alternative schedules. For EV5, we can choose between E0/E1 and
5169 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5171 static int
5173 {
5175 }
5176 \f
5177 /* Machine-specific function data. */
5180 {
5181 /* For unicosmk. */
5182 /* List of call information words for calls from this function. */
5187 /* List of deferred case vectors. */
5190 /* For OSF. */
5193 /* For TARGET_LD_BUGGY_LDGP. */
5195 };
5197 /* How to allocate a 'struct machine_function'. */
5201 {
5204 }
5206 /* Functions to save and restore alpha_return_addr_rtx. */
5208 /* Start the ball rolling with RETURN_ADDR_RTX. */
5210 rtx
5212 {
5217 }
5219 /* Return or create a memory slot containing the gp value for the current
5220 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5222 rtx
5224 {
5228 {
5240 }
5243 }
5245 static int
5247 {
5248 rtx top;
5258 }
5260 \f
5261 /* Return the trap mode suffix applicable to the current
5262 instruction, or NULL. */
5266 {
5270 {
5286 {
5294 }
5299 {
5308 }
5313 {
5322 }
5324 }
5326 }
5328 /* Return the rounding mode suffix applicable to the current
5329 instruction, or NULL. */
5333 {
5337 {
5342 {
5351 }
5356 }
5358 }
5360 /* Locate some local-dynamic symbol still in use by this function
5361 so that we can print its name in some movdi_er_tlsldm pattern. */
5363 static int
5365 {
5370 {
5373 }
5376 }
5380 {
5381 rtx insn;
5392 }
5394 /* Print an operand. Recognize special options, documented below. */
5396 void
5398 {
5402 {
5404 /* Print the assembler name of the current function. */
5413 {
5421 }
5424 /* Generates single precision instruction suffix. */
5429 /* Generates double precision instruction suffix. */
5434 /* Generates a nop after a noreturn call at the very end of the
5435 function. */
5455 else
5460 {
5464 {
5467 }
5469 {
5472 }
5475 else
5476 {
5479 }
5483 }
5487 /* If this operand is the constant zero, write it as "$31". */
5492 else
5497 /* Similar, but for floating-point. */
5502 else
5507 /* Write the 1's complement of a constant. */
5515 /* Write 1 << C, for a constant C. */
5523 /* Write the high-order 16 bits of a constant, sign-extended. */
5531 /* Write the low-order 16 bits of a constant, sign-extended. */
5540 /* Write mask for ZAP insn. */
5542 {
5544 HOST_WIDE_INT value;
5559 }
5562 {
5570 }
5571 else
5576 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5590 /* Similar, except do it from the mask. */
5592 {
5596 {
5599 }
5601 {
5604 }
5606 {
5609 }
5611 {
5614 }
5615 }
5620 {
5623 }
5628 /* Write the constant value divided by 8 for little-endian mode or
5629 (56 - value) / 8 for big-endian mode. */
5639 WORDS_BIG_ENDIAN
5645 /* Same, except compute (64 - c) / 8 */
5656 {
5657 /* On Unicos/Mk systems: use a DEX expression if the symbol
5658 clashes with a register name. */
5662 else
5664 }
5668 /* Write out comparison name. */
5669 {
5688 else
5690 }
5694 /* Write the divide or modulus operator. */
5696 {
5712 }
5716 /* Write "_u" for unaligned access. */
5727 {
5729 {
5737 }
5738 }
5739 else
5745 }
5746 }
5748 void
5750 {
5759 {
5762 }
5765 {
5770 {
5773 {
5785 }
5788 }
5789 else
5790 {
5794 }
5805 else
5811 }
5821 #if TARGET_ABI_OPEN_VMS
5823 {
5826 }
5830 {
5835 }
5836 #endif
5838 else
5842 }
5843 \f
5844 /* Emit RTL insns to initialize the variable parts of a trampoline at
5845 TRAMP. FNADDR is an RTX for the address of the function's pure
5846 code. CXT is an RTX for the static chain value for the function.
5848 The three offset parameters are for the individual template's
5849 layout. A JMPOFS < 0 indicates that the trampoline does not
5850 contain instructions at all.
5852 We assume here that a function will be called many more times than
5853 its address is taken (e.g., it might be passed to qsort), so we
5854 take the trouble to initialize the "hint" field in the JMP insn.
5855 Note that the hint field is PC (new) + 4 * bits 13:0. */
5857 void
5860 {
5862 /* VMS really uses DImode pointers in memory at this point. */
5865 #ifdef POINTERS_EXTEND_UNSIGNED
5868 #endif
5870 /* Store function address and CXT. */
5876 /* This has been disabled since the hint only has a 32k range, and in
5877 no existing OS is the stack within 32k of the text segment. */
5879 {
5880 /* Compute hint value. */
5883 OPTAB_WIDEN);
5889 /* Merge in the hint. */
5894 OPTAB_WIDEN);
5896 }
5898 #ifdef TRANSFER_FROM_TRAMPOLINE
5901 #endif
5905 }
5906 \f
5907 /* Determine where to put an argument to a function.
5908 Value is zero to push the argument on the stack,
5909 or a hard register in which to store the argument.
5911 MODE is the argument's machine mode.
5912 TYPE is the data type of the argument (as a tree).
5913 This is null for libcalls where that information may
5914 not be available.
5915 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5916 the preceding args and about the function being called.
5917 NAMED is nonzero if this argument is a named parameter
5918 (otherwise it is an extra parameter matching an ellipsis).
5920 On Alpha the first 6 words of args are normally in registers
5921 and the rest are pushed. */
5923 rtx
5926 {
5930 /* Don't get confused and pass small structures in FP registers. */
5933 else
5934 {
5935 #ifdef ENABLE_CHECKING
5936 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5937 values here. */
5940 #endif
5942 /* Set up defaults for FP operands passed in FP registers, and
5943 integral operands passed in integer registers. */
5946 else
5948 }
5950 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5951 the three platforms, so we can't avoid conditional compilation. */
5952 #if TARGET_ABI_OPEN_VMS
5953 {
5960 }
5961 #elif TARGET_ABI_UNICOSMK
5962 {
5965 /* If this is the last argument, generate the call info word (CIW). */
5966 /* ??? We don't include the caller's line number in the CIW because
5967 I don't know how to determine it if debug infos are turned off. */
5969 {
5971 HOST_WIDE_INT lo;
5972 HOST_WIDE_INT hi;
5973 rtx ciw;
5983 else
5986 #if HOST_BITS_PER_WIDE_INT == 32
5988 #else
5992 #endif
5996 UNSPEC_UMK_LOAD_CIW);
5997 }
6005 {
6011 /* The argument fits in two registers. Note that we still need to
6012 reserve a register for empty structures. */
6017 else
6018 {
6022 }
6023 }
6024 }
6025 #elif TARGET_ABI_OSF
6026 {
6031 /* VOID is passed as a special flag for "last argument". */
6038 }
6039 #else
6040 #error Unhandled ABI
6041 #endif
6044 }
6046 /* Return true if TYPE must be returned in memory, instead of in registers. */
6048 static bool
6050 {
6055 {
6058 /* All aggregates are returned in memory. */
6061 }
6065 {
6067 /* Pass all float vectors in memory, like an aggregate. */
6071 /* We judge complex floats on the size of their element,
6072 not the size of the whole type. */
6083 /* ??? We get called on all sorts of random stuff from
6084 aggregate_value_p. We can't abort, but it's not clear
6085 what's safe to return. Pretend it's a struct I guess. */
6087 }
6089 /* Otherwise types must fit in one register. */
6091 }
6093 /* Define how to find the value returned by a function. VALTYPE is the
6094 data type of the value (as a tree). If the precise function being
6095 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6096 MODE is set instead of VALTYPE for libcalls.
6098 On Alpha the value is found in $0 for integer functions and
6099 $f0 for floating-point functions. */
6101 rtx
6104 {
6108 #ifdef ENABLE_CHECKING
6111 #endif
6118 {
6120 /* Do the same thing as PROMOTE_MODE. */
6122 /* FALLTHRU */
6134 {
6137 return gen_rtx_PARALLEL
6141 const0_rtx),
6144 }
6148 }
6151 }
6153 /* TCmode complex values are passed by invisible reference. We
6154 should not split these values. */
6156 static bool
6158 {
6160 }
6162 static tree
6164 {
6175 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6177 /* Dummy field to prevent alignment warnings. */
6184 integer_type_node);
6189 ptr_type_node);
6197 }
6199 /* Perform any needed actions needed for a function that is receiving a
6200 variable number of arguments. */
6202 static void
6205 tree type ATTRIBUTE_UNUSED,
6207 {
6208 #if TARGET_ABI_UNICOSMK
6209 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6210 arguments on the stack. Unfortunately, it doesn't always store the first
6211 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6212 with stdargs as we always have at least one named argument there. */
6215 {
6217 {
6220 }
6222 }
6223 #elif TARGET_ABI_OPEN_VMS
6224 /* For VMS, we allocate space for all 6 arg registers plus a count.
6226 However, if NO registers need to be saved, don't allocate any space.
6227 This is not only because we won't need the space, but because AP
6228 includes the current_pretend_args_size and we don't want to mess up
6229 any ap-relative addresses already made. */
6231 {
6233 {
6236 }
6238 }
6239 #else
6240 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6241 only push those that are remaining. However, if NO registers need to
6242 be saved, don't allocate any space. This is not only because we won't
6243 need the space, but because AP includes the current_pretend_args_size
6244 and we don't want to mess up any ap-relative addresses already made.
6246 If we are not to use the floating-point registers, save the integer
6247 registers where we would put the floating-point registers. This is
6248 not the most efficient way to implement varargs with just one register
6249 class, but it isn't worth doing anything more efficient in this rare
6250 case. */
6257 {
6259 rtx tmp;
6273 }
6275 #endif
6276 }
6278 void
6280 {
6281 HOST_WIDE_INT offset;
6290 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6291 up by 48, storing fp arg registers in the first 48 bytes, and the
6292 integer arg registers in the next 48 bytes. This is only done,
6293 however, if any integer registers need to be stored.
6295 If no integer registers need be stored, then we must subtract 48
6296 in order to account for the integer arg registers which are counted
6297 in argsize above, but which are not actually stored on the stack.
6298 Must further be careful here about structures straddling the last
6299 integer argument register; that futzes with pretend_args_size,
6300 which changes the meaning of AP. */
6304 else
6308 {
6316 }
6317 else
6318 {
6337 }
6338 }
6340 static tree
6342 {
6346 /* If the type could not be passed in registers, skip the block
6347 reserved for the registers. */
6349 {
6354 }
6361 {
6365 }
6367 {
6373 /* Copy the value into a new temporary, lest the formal temporary
6374 be reused out from under us. */
6381 }
6383 {
6392 }
6394 /* Build the final address and force that value into a temporary. */
6403 /* Update the offset field. */
6407 else
6408 {
6412 }
6419 }
6421 static tree
6423 {
6436 /* Pull the fields of the structure out into temporaries. Since we never
6437 modify the base field, we can use a formal temporary. Sign-extend the
6438 offset field so that it's the proper width for pointer arithmetic. */
6444 /* Find the value. Note that this will be a stable indirection, or
6445 a composite of stable indirections in the case of complex. */
6448 /* Stuff the offset temporary back into its field. */
6454 }
6455 \f
6456 /* Builtins. */
6458 enum alpha_builtin
6459 {
6460 ALPHA_BUILTIN_CMPBGE,
6461 ALPHA_BUILTIN_EXTBL,
6462 ALPHA_BUILTIN_EXTWL,
6463 ALPHA_BUILTIN_EXTLL,
6464 ALPHA_BUILTIN_EXTQL,
6465 ALPHA_BUILTIN_EXTWH,
6466 ALPHA_BUILTIN_EXTLH,
6467 ALPHA_BUILTIN_EXTQH,
6468 ALPHA_BUILTIN_INSBL,
6469 ALPHA_BUILTIN_INSWL,
6470 ALPHA_BUILTIN_INSLL,
6471 ALPHA_BUILTIN_INSQL,
6472 ALPHA_BUILTIN_INSWH,
6473 ALPHA_BUILTIN_INSLH,
6474 ALPHA_BUILTIN_INSQH,
6475 ALPHA_BUILTIN_MSKBL,
6476 ALPHA_BUILTIN_MSKWL,
6477 ALPHA_BUILTIN_MSKLL,
6478 ALPHA_BUILTIN_MSKQL,
6479 ALPHA_BUILTIN_MSKWH,
6480 ALPHA_BUILTIN_MSKLH,
6481 ALPHA_BUILTIN_MSKQH,
6482 ALPHA_BUILTIN_UMULH,
6483 ALPHA_BUILTIN_ZAP,
6484 ALPHA_BUILTIN_ZAPNOT,
6485 ALPHA_BUILTIN_AMASK,
6486 ALPHA_BUILTIN_IMPLVER,
6487 ALPHA_BUILTIN_RPCC,
6488 ALPHA_BUILTIN_THREAD_POINTER,
6489 ALPHA_BUILTIN_SET_THREAD_POINTER,
6491 /* TARGET_MAX */
6492 ALPHA_BUILTIN_MINUB8,
6493 ALPHA_BUILTIN_MINSB8,
6494 ALPHA_BUILTIN_MINUW4,
6495 ALPHA_BUILTIN_MINSW4,
6496 ALPHA_BUILTIN_MAXUB8,
6497 ALPHA_BUILTIN_MAXSB8,
6498 ALPHA_BUILTIN_MAXUW4,
6499 ALPHA_BUILTIN_MAXSW4,
6500 ALPHA_BUILTIN_PERR,
6501 ALPHA_BUILTIN_PKLB,
6502 ALPHA_BUILTIN_PKWB,
6503 ALPHA_BUILTIN_UNPKBL,
6504 ALPHA_BUILTIN_UNPKBW,
6506 /* TARGET_CIX */
6507 ALPHA_BUILTIN_CTTZ,
6508 ALPHA_BUILTIN_CTLZ,
6509 ALPHA_BUILTIN_CTPOP,
6511 ALPHA_BUILTIN_max
6512 };
6515 CODE_FOR_builtin_cmpbge,
6516 CODE_FOR_builtin_extbl,
6517 CODE_FOR_builtin_extwl,
6518 CODE_FOR_builtin_extll,
6519 CODE_FOR_builtin_extql,
6520 CODE_FOR_builtin_extwh,
6521 CODE_FOR_builtin_extlh,
6522 CODE_FOR_builtin_extqh,
6523 CODE_FOR_builtin_insbl,
6524 CODE_FOR_builtin_inswl,
6525 CODE_FOR_builtin_insll,
6526 CODE_FOR_builtin_insql,
6527 CODE_FOR_builtin_inswh,
6528 CODE_FOR_builtin_inslh,
6529 CODE_FOR_builtin_insqh,
6530 CODE_FOR_builtin_mskbl,
6531 CODE_FOR_builtin_mskwl,
6532 CODE_FOR_builtin_mskll,
6533 CODE_FOR_builtin_mskql,
6534 CODE_FOR_builtin_mskwh,
6535 CODE_FOR_builtin_msklh,
6536 CODE_FOR_builtin_mskqh,
6537 CODE_FOR_umuldi3_highpart,
6538 CODE_FOR_builtin_zap,
6539 CODE_FOR_builtin_zapnot,
6540 CODE_FOR_builtin_amask,
6541 CODE_FOR_builtin_implver,
6542 CODE_FOR_builtin_rpcc,
6543 CODE_FOR_load_tp,
6544 CODE_FOR_set_tp,
6546 /* TARGET_MAX */
6547 CODE_FOR_builtin_minub8,
6548 CODE_FOR_builtin_minsb8,
6549 CODE_FOR_builtin_minuw4,
6550 CODE_FOR_builtin_minsw4,
6551 CODE_FOR_builtin_maxub8,
6552 CODE_FOR_builtin_maxsb8,
6553 CODE_FOR_builtin_maxuw4,
6554 CODE_FOR_builtin_maxsw4,
6555 CODE_FOR_builtin_perr,
6556 CODE_FOR_builtin_pklb,
6557 CODE_FOR_builtin_pkwb,
6558 CODE_FOR_builtin_unpkbl,
6559 CODE_FOR_builtin_unpkbw,
6561 /* TARGET_CIX */
6562 CODE_FOR_builtin_cttz,
6563 CODE_FOR_builtin_ctlz,
6564 CODE_FOR_builtin_ctpop
6565 };
6567 struct alpha_builtin_def
6568 {
6572 };
6577 };
6588 };
6625 };
6627 static void
6629 {
6631 tree ftype;
6652 long_integer_type_node,
6670 }
6672 /* Expand an expression EXP that calls a built-in function,
6673 with result going to TARGET if that's convenient
6674 (and in mode MODE if that's convenient).
6675 SUBTARGET may be used as the target for computing one of EXP's operands.
6676 IGNORE is nonzero if the value is to be ignored. */
6678 static rtx
6680 rtx subtarget ATTRIBUTE_UNUSED,
6683 {
6684 #define MAX_ARGS 2
6703 arglist;
6705 {
6720 }
6723 {
6729 }
6732 {
6739 else
6747 }
6754 else
6756 }
6757 \f
6758 /* This page contains routines that are used to determine what the function
6759 prologue and epilogue code will do and write them out. */
6761 /* Compute the size of the save area in the stack. */
6763 /* These variables are used for communication between the following functions.
6764 They indicate various things about the current function being compiled
6765 that are used to tell what kind of prologue, epilogue and procedure
6766 descriptor to generate. */
6768 /* Nonzero if we need a stack procedure. */
6772 /* Register number (either FP or SP) that is used to unwind the frame. */
6775 /* Register number used to save FP. We need not have one for RA since
6776 we don't modify it for register procedures. This is only defined
6777 for register frame procedures. */
6780 /* Register number used to reference objects off our PV. */
6783 /* Compute register masks for saved registers. */
6785 static void
6787 {
6792 /* When outputting a thunk, we don't have valid register life info,
6793 but assemble_start_function wants to output .frame and .mask
6794 directives. */
6796 {
6800 }
6805 /* One for every register we have to save. */
6810 {
6813 else
6815 }
6817 /* We need to restore these for the handler. */
6819 {
6821 {
6826 }
6828 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6829 avoid hackery in unwind-dw2.c, we need to actively store a
6830 zero in the prologue of _Unwind_RaiseException et al. */
6832 }
6834 /* If any register spilled, then spill the return address also. */
6835 /* ??? This is required by the Digital stack unwind specification
6836 and isn't needed if we're doing Dwarf2 unwinding. */
6842 }
6844 int
6846 {
6854 {
6857 }
6858 else
6859 {
6863 sa_size++;
6864 }
6867 {
6868 /* We might not need to generate a frame if we don't make any calls
6869 (including calls to __T3E_MISMATCH if this is a vararg function),
6870 don't have any local variables which require stack slots, don't
6871 use alloca and have not determined that we need a frame for other
6872 reasons. */
6874 alpha_procedure_type
6876 || current_function_outgoing_args_size
6881 /* Always reserve space for saving callee-saved registers if we
6882 need a frame as required by the calling convention. */
6885 }
6887 {
6888 /* Start by assuming we can use a register procedure if we don't
6889 make any calls (REG_RA not used) or need to save any
6890 registers and a stack procedure if we do. */
6895 else
6898 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6899 made the final decision on stack procedure vs register procedure. */
6903 /* Decide whether to refer to objects off our PV via FP or PV.
6904 If we need FP for something else or if we receive a nonlocal
6905 goto (which expects PV to contain the value), we must use PV.
6906 Otherwise, start by assuming we can use FP. */
6908 vms_base_regno
6909 = (frame_pointer_needed
6910 || current_function_has_nonlocal_label
6915 /* If we want to copy PV into FP, we need to find some register
6916 in which to save FP. */
6929 /* Stack unwinding should be done via FP unless we use it for PV. */
6933 /* If this is a stack procedure, allow space for saving FP and RA. */
6936 }
6937 else
6938 {
6939 /* Our size must be even (multiple of 16 bytes). */
6941 sa_size++;
6942 }
6945 }
6947 /* Define the offset between two registers, one to be eliminated,
6948 and the other its replacement, at the start of a routine. */
6950 HOST_WIDE_INT
6953 {
6954 HOST_WIDE_INT ret;
6960 ;
6965 else
6969 }
6971 int
6973 {
6976 }
6978 int
6980 {
6983 }
6985 #if TARGET_ABI_OPEN_VMS
6988 {
6989 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6994 };
6996 #endif
6998 static int
7000 {
7002 }
7004 int
7006 {
7008 }
7010 static int
7012 {
7013 rtx insn;
7015 /* The GP being variable is an OSF abi thing. */
7019 /* We need the gp to load the address of __mcount. */
7023 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7027 /* The nonlocal receiver pattern assumes that the gp is valid for
7028 the nested function. Reasonable because it's almost always set
7029 correctly already. For the cases where that's wrong, make sure
7030 the nested function loads its gp on entry. */
7034 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7035 Even if we are a static function, we still need to do this in case
7036 our address is taken and passed to something like qsort. */
7050 }
7052 \f
7053 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7054 sequences. */
7056 static rtx
7058 {
7060 rtx insn;
7068 {
7071 {
7074 }
7076 }
7077 else
7078 {
7081 }
7083 }
7085 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7087 /* Write function prologue. */
7089 /* On vms we have two kinds of functions:
7091 - stack frame (PROC_STACK)
7092 these are 'normal' functions with local vars and which are
7093 calling other functions
7094 - register frame (PROC_REGISTER)
7095 keeps all data in registers, needs no stack
7097 We must pass this to the assembler so it can generate the
7098 proper pdsc (procedure descriptor)
7099 This is done with the '.pdesc' command.
7101 On not-vms, we don't really differentiate between the two, as we can
7102 simply allocate stack without saving registers. */
7104 void
7106 {
7107 /* Registers to save. */
7110 /* Stack space needed for pushing registers clobbered by us. */
7111 HOST_WIDE_INT sa_size;
7112 /* Complete stack size needed. */
7113 HOST_WIDE_INT frame_size;
7114 /* Offset from base reg to register save area. */
7115 HOST_WIDE_INT reg_offset;
7125 + frame_size
7128 /* We have to allocate space for the DSIB if we generate a frame. */
7133 else
7135 + sa_size
7141 else
7146 /* Emit an insn to reload GP, if needed. */
7148 {
7152 }
7154 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7155 the call to mcount ourselves, rather than having the linker do it
7156 magically in response to -pg. Since _mcount has special linkage,
7157 don't represent the call as a call. */
7164 /* Adjust the stack by the frame size. If the frame size is > 4096
7165 bytes, we need to be sure we probe somewhere in the first and last
7166 4096 bytes (we can probably get away without the latter test) and
7167 every 8192 bytes in between. If the frame size is > 32768, we
7168 do this in a loop. Otherwise, we generate the explicit probe
7169 instructions.
7171 Note that we are only allowed to adjust sp once in the prologue. */
7174 {
7176 {
7179 do
7185 /* We only have to do this probe if we aren't saving registers. */
7188 }
7195 }
7196 else
7197 {
7198 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7199 number of 8192 byte blocks to probe. We then probe each block
7200 in the loop and then set SP to the proper location. If the
7201 amount remaining is > 4096, we have to do one more probe if we
7202 are not saving any registers. */
7208 rtx seq;
7214 /* Because of the difficulty in emitting a new basic block this
7215 late in the compilation, generate the loop as a single insn. */
7219 {
7223 }
7226 {
7227 /* For NT stack unwind (done by 'reverse execution'), it's
7228 not OK to take the result of a loop, even though the value
7229 is already in ptr, so we reload it via a single operation
7230 and subtract it to sp.
7232 Yes, that's correct -- we have to reload the whole constant
7233 into a temporary via ldah+lda then subtract from sp. */
7242 ptr));
7243 }
7244 else
7245 {
7248 }
7250 /* This alternative is special, because the DWARF code cannot
7251 possibly intuit through the loop above. So we invent this
7252 note it looks at instead. */
7262 }
7265 {
7266 /* Cope with very large offsets to the register save area. */
7269 {
7271 HOST_WIDE_INT bias;
7275 else
7281 }
7283 /* Save regs in stack order. Beginning with VMS PV. */
7285 {
7289 }
7291 /* Save register RA next. */
7293 {
7299 }
7301 /* Now save any other registers required to be saved. */
7304 {
7309 }
7311 /* Store a zero if requested for unwinding. */
7313 {
7327 }
7331 {
7336 }
7337 }
7339 {
7340 /* The standard frame on the T3E includes space for saving registers.
7341 We just have to use it. We don't have to save the return address and
7342 the old frame pointer here - they are saved in the DSIB. */
7347 {
7349 reg_offset));
7353 }
7356 {
7358 reg_offset));
7362 }
7363 }
7366 {
7368 /* Register frame procedures save the fp.
7369 ?? Ought to have a dwarf2 save for this. */
7371 hard_frame_pointer_rtx);
7381 /* If we have to allocate space for outgoing args, do it now. */
7383 {
7384 rtx seq
7386 plus_constant
7388 - (ALPHA_ROUND
7391 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7392 if ! frame_pointer_needed. Setting the bit will change the CFA
7393 computation rule to use sp again, which would be wrong if we had
7394 frame_pointer_needed, as this means sp might move unpredictably
7395 later on.
7397 Also, note that
7398 frame_pointer_needed
7399 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7400 and
7401 current_function_outgoing_args_size != 0
7402 => alpha_procedure_type != PT_NULL,
7404 so when we are not setting the bit here, we are guaranteed to
7405 have emitted an FRP frame pointer update just before. */
7407 }
7408 }
7410 {
7411 /* If we need a frame pointer, set it from the stack pointer. */
7413 {
7416 else
7417 /* This must always be the last instruction in the
7418 prologue, thus we emit a special move + clobber. */
7421 }
7422 }
7424 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7425 the prologue, for exception handling reasons, we cannot do this for
7426 any insn that might fault. We could prevent this for mems with a
7427 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7428 have to prevent all such scheduling with a blockage.
7430 Linux, on the other hand, never bothered to implement OSF/1's
7431 exception handling, and so doesn't care about such things. Anyone
7432 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7436 }
7438 /* Output the textual info surrounding the prologue. */
7440 void
7442 tree decl ATTRIBUTE_UNUSED)
7443 {
7446 /* Stack space needed for pushing registers clobbered by us. */
7447 HOST_WIDE_INT sa_size;
7448 /* Complete stack size needed. */
7450 /* Offset from base reg to register save area. */
7451 HOST_WIDE_INT reg_offset;
7455 /* Don't emit an extern directive for functions defined in the same file. */
7457 {
7458 tree name_tree;
7461 }
7470 + frame_size
7477 else
7479 + sa_size
7485 else
7490 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7491 We have to do that before the .ent directive as we cannot switch
7492 files within procedures with native ecoff because line numbers are
7493 linked to procedure descriptors.
7494 Outputting the lineno helps debugging of one line functions as they
7495 would otherwise get no line number at all. Please note that we would
7496 like to put out last_linenum from final.c, but it is not accessible. */
7499 {
7500 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7503 #endif
7504 #ifdef ASM_OUTPUT_SOURCE_LINE
7508 #endif
7509 }
7511 /* Issue function start and label. */
7514 {
7519 /* If the function needs GP, we'll write the "..ng" label there.
7520 Otherwise, do it here. */
7522 && ! alpha_function_needs_gp
7524 {
7528 }
7529 }
7535 /* For public functions, the label must be globalized by appending an
7536 additional colon. */
7548 {
7549 /* Set flags in procedure descriptor to request IEEE-conformant
7550 math-library routines. The value we set it to is PDSC_EXC_IEEE
7551 (/usr/include/pdsc.h). */
7553 }
7555 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7559 /* Describe our frame. If the frame size is larger than an integer,
7560 print it as zero to avoid an assembler error. We won't be
7561 properly describing such a frame, but that's the best we can do. */
7563 ;
7567 vms_unwind_regno,
7569 reg_offset);
7572 (frame_pointer_needed
7575 current_function_pretend_args_size);
7577 /* Describe which registers were spilled. */
7579 ;
7581 {
7583 /* ??? Does VMS care if mask contains ra? The old code didn't
7584 set it, so I don't here. */
7590 }
7592 {
7594 {
7601 }
7606 }
7608 #if TARGET_ABI_OPEN_VMS
7609 /* Ifdef'ed cause link_section are only available then. */
7618 #endif
7619 }
7621 /* Emit the .prologue note at the scheduled end of the prologue. */
7623 static void
7625 {
7627 ;
7635 }
7637 /* Write function epilogue. */
7639 /* ??? At some point we will want to support full unwind, and so will
7640 need to mark the epilogue as well. At the moment, we just confuse
7641 dwarf2out. */
7642 #undef FRP
7643 #define FRP(exp) exp
7645 void
7647 {
7648 /* Registers to save. */
7651 /* Stack space needed for pushing registers clobbered by us. */
7652 HOST_WIDE_INT sa_size;
7653 /* Complete stack size needed. */
7654 HOST_WIDE_INT frame_size;
7655 /* Offset from base reg to register save area. */
7656 HOST_WIDE_INT reg_offset;
7660 rtx eh_ofs;
7669 + frame_size
7676 else
7678 + sa_size
7683 {
7686 else
7688 }
7689 else
7694 fp_is_frame_pointer
7702 else
7706 {
7707 /* If we have a frame pointer, restore SP from it. */
7713 /* Cope with very large offsets to the register save area. */
7715 {
7717 HOST_WIDE_INT bias;
7721 else
7728 }
7730 /* Restore registers in order, excepting a true frame pointer. */
7742 {
7745 else
7746 {
7750 }
7752 }
7759 {
7764 }
7765 }
7767 {
7768 /* Restore callee-saved general-purpose registers. */
7774 {
7776 reg_offset));
7780 }
7784 {
7786 reg_offset));
7790 }
7792 /* Restore the return address from the DSIB. */
7797 }
7800 {
7804 {
7808 }
7810 /* If the stack size is large, begin computation into a temporary
7811 register so as not to interfere with a potential fp restore,
7812 which must be consecutive with an SP restore. */
7817 {
7821 }
7823 {
7829 else
7830 {
7833 }
7835 }
7836 else
7837 {
7841 {
7842 /* We can't drop new things to memory this late, afaik,
7843 so build it up by pieces. */
7848 }
7849 }
7851 /* From now on, things must be in order. So emit blockages. */
7853 /* Restore the frame pointer. */
7855 {
7861 }
7863 {
7868 }
7870 {
7874 }
7876 /* Restore the stack pointer. */
7880 else
7883 }
7884 else
7885 {
7887 {
7891 }
7893 {
7894 /* Decrement the frame pointer if the function does not have a
7895 frame. */
7900 }
7901 }
7902 }
7903 \f
7904 /* Output the rest of the textual info surrounding the epilogue. */
7906 void
7908 {
7909 #if TARGET_ABI_OPEN_VMS
7911 #endif
7913 /* End the function. */
7915 {
7919 }
7922 /* Output jump tables and the static subroutine information block. */
7924 {
7927 }
7928 }
7930 #if TARGET_ABI_OSF
7931 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7933 In order to avoid the hordes of differences between generated code
7934 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7935 lots of code loading up large constants, generate rtl and emit it
7936 instead of going straight to text.
7938 Not sure why this idea hasn't been explored before... */
7940 static void
7943 tree function)
7944 {
7950 /* We always require a valid GP. */
7954 /* Find the "this" pointer. If the function returns a structure,
7955 the structure return pointer is in $16. */
7958 else
7961 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7962 entire constant for the add. */
7966 {
7971 }
7972 else
7973 {
7977 }
7979 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7981 {
7990 {
7993 }
7994 else
7995 {
8000 }
8003 else
8008 }
8010 /* Generate a tail call to the target function. */
8012 {
8015 }
8021 /* Run just enough of rest_of_compilation to get the insns emitted.
8022 There's not really enough bulk here to make other passes such as
8023 instruction scheduling worth while. Note that use_thunk calls
8024 assemble_start_function and assemble_end_function. */
8031 }
8033 \f
8034 /* Debugging support. */
8038 /* Count the number of sdb related labels are generated (to find block
8039 start and end boundaries). */
8043 /* Next label # for each statement. */
8047 /* Count the number of .file directives, so that .loc is up to date. */
8051 /* Name of the file containing the current function. */
8055 /* Offsets to alpha virtual arg/local debugging pointers. */
8059 \f
8060 /* Emit a new filename to a stream. */
8062 void
8064 {
8069 {
8078 }
8081 {
8086 }
8090 {
8093 else
8094 {
8098 }
8102 }
8103 }
8105 /* Emit a linenumber to a stream. */
8107 void
8109 {
8111 {
8112 /* mips-tfile doesn't understand .stabd directives. */
8116 }
8117 else
8119 }
8120 \f
8121 /* Structure to show the current status of registers and memory. */
8123 struct shadow_summary
8124 {
8130 };
8132 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8133 to the summary structure. SET is nonzero if the insn is setting the
8134 object, otherwise zero. */
8136 static void
8138 {
8146 {
8147 /* ??? Note that this case would be incorrect if the Alpha had a
8148 ZERO_EXTRACT in SET_DEST. */
8177 {
8185 {
8188 else
8190 }
8191 else
8192 {
8195 else
8197 }
8198 }
8204 else
8207 /* Find the regs used in memory address computation: */
8216 /* Handle common unary and binary ops for efficiency. */
8238 {
8253 }
8254 }
8255 }
8257 /* Ensure a sufficient number of `trapb' insns are in the code when
8258 the user requests code with a trap precision of functions or
8259 instructions.
8261 In naive mode, when the user requests a trap-precision of
8262 "instruction", a trapb is needed after every instruction that may
8263 generate a trap. This ensures that the code is resumption safe but
8264 it is also slow.
8266 When optimizations are turned on, we delay issuing a trapb as long
8267 as possible. In this context, a trap shadow is the sequence of
8268 instructions that starts with a (potentially) trap generating
8269 instruction and extends to the next trapb or call_pal instruction
8270 (but GCC never generates call_pal by itself). We can delay (and
8271 therefore sometimes omit) a trapb subject to the following
8272 conditions:
8274 (a) On entry to the trap shadow, if any Alpha register or memory
8275 location contains a value that is used as an operand value by some
8276 instruction in the trap shadow (live on entry), then no instruction
8277 in the trap shadow may modify the register or memory location.
8279 (b) Within the trap shadow, the computation of the base register
8280 for a memory load or store instruction may not involve using the
8281 result of an instruction that might generate an UNPREDICTABLE
8282 result.
8284 (c) Within the trap shadow, no register may be used more than once
8285 as a destination register. (This is to make life easier for the
8286 trap-handler.)
8288 (d) The trap shadow may not include any branch instructions. */
8290 static void
8292 {
8305 {
8307 {
8309 {
8311 exception_nesting++;
8317 exception_nesting--;
8326 }
8327 }
8329 {
8331 {
8335 }
8337 {
8339 {
8348 {
8350 /* Annoyingly, get_attr_trap will abort on these. */
8359 {
8360 /* (c) would be violated */
8362 }
8364 /* Combine shadow with summary of current insn: */
8375 {
8376 /* (a) would be violated (also takes care of (b)) */
8383 }
8393 }
8394 }
8395 else
8396 {
8397 close_shadow:
8406 }
8407 }
8408 }
8415 {
8419 }
8420 }
8421 }
8422 \f
8423 /* Alpha can only issue instruction groups simultaneously if they are
8424 suitably aligned. This is very processor-specific. */
8431 };
8442 };
8444 static enum alphaev4_pipe
8446 {
8453 {
8483 }
8484 }
8486 static enum alphaev5_pipe
8488 {
8495 {
8532 }
8533 }
8535 /* IN_USE is a mask of the slots currently filled within the insn group.
8536 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8537 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8539 LEN is, of course, the length of the group in bytes. */
8541 static rtx
8543 {
8554 {
8559 {
8561 /* Force complex instructions to start new groups. */
8565 /* If this is a completely unrecognized insn, its an asm.
8566 We don't know how long it is, so record length as -1 to
8567 signal a needed realignment. */
8570 else
8576 {
8580 }
8581 else
8587 {
8591 }
8603 }
8606 /* Haifa doesn't do well scheduling branches. */
8610 next:
8616 /* Let Haifa tell us where it thinks insn group boundaries are. */
8622 }
8624 next_and_done:
8627 done:
8631 }
8633 /* IN_USE is a mask of the slots currently filled within the insn group.
8634 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8635 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8637 LEN is, of course, the length of the group in bytes. */
8639 static rtx
8641 {
8652 {
8657 {
8659 /* Force complex instructions to start new groups. */
8663 /* If this is a completely unrecognized insn, its an asm.
8664 We don't know how long it is, so record length as -1 to
8665 signal a needed realignment. */
8668 else
8672 /* ??? Most of the places below, we would like to abort, as
8673 it would indicate an error either in Haifa, or in the
8674 scheduling description. Unfortunately, Haifa never
8675 schedules the last instruction of the BB, so we don't
8676 have an accurate TI bit to go off. */
8679 {
8683 }
8684 else
8690 {
8694 }
8706 {
8710 }
8711 else
8732 }
8735 /* Haifa doesn't do well scheduling branches. */
8736 /* ??? If this is predicted not-taken, slotting continues, except
8737 that no more IBR, FBR, or JSR insns may be slotted. */
8741 next:
8747 /* Let Haifa tell us where it thinks insn group boundaries are. */
8753 }
8755 next_and_done:
8758 done:
8762 }
8764 static rtx
8766 {
8768 rtx nop;
8771 {
8774 }
8776 {
8779 }
8781 {
8784 }
8785 else
8790 }
8792 static rtx
8794 {
8796 rtx nop;
8799 {
8802 }
8804 {
8807 }
8809 {
8812 }
8813 else
8818 }
8820 /* The instruction group alignment main loop. */
8822 static void
8826 {
8827 /* ALIGN is the known alignment for the insn group. */
8829 /* OFS is the offset of the current insn in the insn group. */
8834 /* Let shorten branches care for assigning alignments to code labels. */
8841 else
8850 {
8853 /* When we see a label, resync alignment etc. */
8855 {
8859 {
8862 }
8868 }
8870 /* Handle complex instructions special. */
8872 {
8873 /* Asms will have length < 0. This is a signal that we have
8874 lost alignment knowledge. Assume, however, that the asm
8875 will not mis-align instructions. */
8877 {
8881 }
8882 }
8884 /* If the known alignment is smaller than the recognized insn group,
8885 realign the output. */
8887 {
8895 /* Can't realign between a call and its gp reload. */
8898 {
8902 }
8903 }
8905 /* If the group won't fit in the same INT16 as the previous,
8906 we need to add padding to keep the group together. Rather
8907 than simply leaving the insn filling to the assembler, we
8908 can make use of the knowledge of what sorts of instructions
8909 were issued in the previous group to make sure that all of
8910 the added nops are really free. */
8912 {
8914 rtx where;
8916 /* Insert nops before labels, branches, and calls to truly merge
8917 the execution of the nops with the previous instruction group. */
8920 {
8922 {
8926 }
8929 }
8930 else
8933 do
8937 }
8942 }
8943 }
8944 \f
8945 /* Machine dependent reorg pass. */
8947 static void
8949 {
8953 /* Due to the number of extra trapb insns, don't bother fixing up
8954 alignment when trap precision is instruction. Moreover, we can
8955 only do our job when sched2 is run. */
8959 {
8964 }
8965 }
8966 \f
8967 #if !TARGET_ABI_UNICOSMK
8969 #ifdef HAVE_STAMP_H
8970 #include <stamp.h>
8971 #endif
8973 static void
8975 {
8976 #ifdef OBJECT_FORMAT_ELF
8977 /* If emitting dwarf2 debug information, we cannot generate a .file
8978 directive to start the file, as it will conflict with dwarf2out
8979 file numbers. So it's only useful when emitting mdebug output. */
8981 #endif
8984 #ifdef MS_STAMP
8986 #endif
8998 : (TARGET_CPU_EV5
9001 }
9002 #endif
9004 #ifdef OBJECT_FORMAT_ELF
9006 /* Switch to the section to which we should output X. The only thing
9007 special we do here is to honor small data. */
9009 static void
9012 {
9014 /* ??? Consider using mergeable sdata sections. */
9016 else
9018 }
9021 \f
9022 /* Structure to collect function names for final output in link section. */
9023 /* Note that items marked with GTY can't be ifdef'ed out. */
9029 {
9031 rtx linkage;
9034 };
9037 {
9040 links;
9041 };
9044 splay_tree alpha_links_tree;
9046 splay_tree alpha_funcs_tree;
9050 #if TARGET_ABI_OPEN_VMS
9052 /* Return the VMS argument type corresponding to MODE. */
9054 enum avms_arg_type
9056 {
9058 {
9065 }
9066 }
9068 /* Return an rtx for an integer representing the VMS Argument Information
9069 register value. */
9071 rtx
9073 {
9081 }
9082 \f
9083 /* Make (or fake) .linkage entry for function call.
9085 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9087 Return an SYMBOL_REF rtx for the linkage. */
9089 rtx
9091 {
9092 splay_tree_node node;
9096 name++;
9099 {
9104 splay_tree_compare_pointers);
9114 }
9117 {
9118 /* Is this name already defined? */
9122 {
9125 {
9126 /* Defined here but external assumed. */
9129 }
9130 else
9131 {
9132 /* Used here but unused assumed. */
9135 }
9137 }
9138 }
9139 else
9145 /* Assume external if no definition. */
9148 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9151 /* Construct a SYMBOL_REF for us to call. */
9152 {
9160 }
9166 }
9168 rtx
9170 {
9171 splay_tree_node cfunnode;
9183 {
9184 splay_tree_node lnode;
9186 /* Is this name already defined? */
9191 }
9192 else
9196 {
9205 name++;
9214 {
9217 }
9229 }
9233 else
9238 else
9240 }
9242 static int
9244 {
9251 {
9253 {
9254 /* Local and used */
9256 }
9257 else
9258 {
9259 /* External and used, request code address. */
9261 }
9262 }
9263 else
9264 {
9266 {
9267 /* Local and used, build linkage pair. */
9270 }
9271 else
9272 {
9273 /* External and used, request linkage pair. */
9275 }
9276 }
9279 }
9281 static void
9283 {
9284 splay_tree_node node;
9303 {
9305 /* splay_tree_delete (func->links); */
9306 }
9307 }
9309 /* Given a decl, a section name, and whether the decl initializer
9310 has relocs, choose attributes for the section. */
9312 #define SECTION_VMS_OVERLAY SECTION_FORGET
9313 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9314 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9316 static unsigned int
9318 {
9332 }
9334 /* Switch to an arbitrary section NAME with attributes as specified
9335 by FLAGS. ALIGN specifies any known alignment requirements for
9336 the section; 0 if the default should be used. */
9338 static void
9340 {
9354 }
9356 /* Record an element in the table of global constructors. SYMBOL is
9357 a SYMBOL_REF of the function to be called; PRIORITY is a number
9358 between 0 and MAX_INIT_PRIORITY.
9360 Differs from default_ctors_section_asm_out_constructor in that the
9361 width of the .ctors entry is always 64 bits, rather than the 32 bits
9362 used by a normal pointer. */
9364 static void
9366 {
9370 }
9372 static void
9374 {
9378 }
9379 #else
9381 rtx
9384 {
9386 }
9388 rtx
9390 tree cfundecl ATTRIBUTE_UNUSED,
9393 {
9395 }
9398 \f
9399 #if TARGET_ABI_UNICOSMK
9401 /* Define the offset between two registers, one to be eliminated, and the
9402 other its replacement, at the start of a routine. */
9404 int
9406 {
9424 else
9426 }
9428 /* Output the module name for .ident and .end directives. We have to strip
9429 directories and add make sure that the module name starts with a letter
9430 or '$'. */
9432 static void
9434 {
9440 /* CAM only accepts module names that start with a letter or '$'. We
9441 prefix the module name with a '$' if necessary. */
9448 }
9450 /* Output the definition of a common variable. */
9452 void
9454 {
9455 tree name_tree;
9464 /* Mark the symbol as defined in this module. */
9467 }
9469 #define SECTION_PUBLIC SECTION_MACH_DEP
9470 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9473 static unsigned int
9476 {
9483 {
9490 }
9491 else
9498 }
9500 /* Generate a section name for decl and associate it with the
9501 declaration. */
9503 static void
9505 {
9517 {
9520 /* It is essential that we prefix the section name here because
9521 otherwise the section names generated for constructors and
9522 destructors confuse collect2. */
9527 }
9530 else
9531 {
9537 }
9538 }
9540 /* Switch to an arbitrary section NAME with attributes as specified
9541 by FLAGS. ALIGN specifies any known alignment requirements for
9542 the section; 0 if the default should be used. */
9544 static void
9546 {
9549 /* Close the previous section. */
9553 /* Find out what kind of section we are opening. */
9562 else
9568 else
9570 }
9572 static void
9574 {
9578 }
9580 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9581 in code sections because .align fill unused space with zeroes. */
9583 void
9585 {
9588 else
9590 }
9592 /* Add a case vector to the current function's list of deferred case
9593 vectors. Case vectors have to be put into a separate section because CAM
9594 does not allow data definitions in code sections. */
9596 void
9598 {
9604 }
9606 /* Output a case vector. */
9608 static void
9610 {
9619 {
9620 ASM_OUTPUT_ADDR_VEC_ELT
9622 }
9623 }
9625 /* Output current function's deferred case vectors. */
9627 static void
9629 {
9631 rtx t;
9639 }
9641 /* Generate the name of the SSIB section for the current function. */
9644 #define SSIB_PREFIX_LEN 7
9648 {
9649 /* This is ok since CAM won't be able to deal with names longer than that
9650 anyway. */
9654 rtx x;
9675 }
9677 /* Set up the dynamic subprogram information block (DSIB) and update the
9678 frame pointer register ($15) for subroutines which have a frame. If the
9679 subroutine doesn't have a frame, simply increment $15. */
9681 static void
9683 {
9685 {
9687 rtx mem;
9689 /* Allocate 64 bytes for the DSIB. */
9695 /* Save the return address. */
9702 /* Save the old frame pointer. */
9711 /* Store the SSIB pointer. */
9721 /* Save the CIW index. */
9729 /* Set the new frame pointer. */
9734 }
9735 else
9736 {
9737 /* Increment the frame pointer register to indicate that we do not
9738 have a frame. */
9742 }
9743 }
9745 /* Output the static subroutine information block for the current
9746 function. */
9748 static void
9750 {
9753 rtx x;
9754 rtx ciw;
9761 /* Some required stuff and the function name length. */
9766 /* Saved registers
9767 ??? We don't do that yet. */
9771 /* Function address. */
9780 /* Function name.
9781 ??? We do it the same way Cray CC does it but this could be
9782 simplified. */
9788 else
9791 /* All call information words used in the function. */
9794 {
9796 #if HOST_BITS_PER_WIDE_INT == 32
9799 #else
9801 #endif
9802 }
9803 }
9805 /* Add a call information word (CIW) to the list of the current function's
9806 CIWs and return its index.
9808 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9810 rtx
9812 {
9813 rtx node;
9819 else
9827 }
9833 {
9836 count++);
9838 }
9842 {
9845 count++);
9847 }
9849 /* The Cray assembler doesn't accept extern declarations for symbols which
9850 are defined in the same file. We have to keep track of all global
9851 symbols which are referenced and/or defined in a source file and output
9852 extern declarations for those which are referenced but not defined at
9853 the end of file. */
9855 /* List of identifiers for which an extern declaration might have to be
9856 emitted. */
9857 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9859 struct unicosmk_extern_list
9860 {
9863 };
9867 /* Output extern declarations which are required for every asm file. */
9869 static void
9871 {
9882 }
9884 /* Output extern declarations for global symbols which are have been
9885 referenced but not defined. */
9887 static void
9889 {
9893 tree name_tree;
9897 {
9898 /* We have to strip the encoding and possibly remove user_label_prefix
9899 from the identifier in order to handle -fleading-underscore and
9900 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9908 {
9913 }
9914 }
9915 }
9917 /* Record an extern. */
9919 void
9921 {
9929 }
9931 /* The Cray assembler generates incorrect code if identifiers which
9932 conflict with register names are used as instruction operands. We have
9933 to replace such identifiers with DEX expressions. */
9935 /* Structure to collect identifiers which have been replaced by DEX
9936 expressions. */
9937 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9942 };
9944 /* List of identifiers which have been replaced by DEX expressions. The DEX
9945 number is determined by the position in the list. */
9949 /* The number of elements in the DEX list. */
9953 /* Check if NAME must be replaced by a DEX expression. */
9955 static int
9957 {
9968 {
9978 }
9979 }
9981 /* Return the DEX number if X must be replaced by a DEX expression and 0
9982 otherwise. */
9984 static int
9986 {
10000 {
10004 }
10013 }
10015 /* Output the DEX definitions for this file. */
10017 static void
10019 {
10030 {
10035 }
10038 }
10040 /* Output text that to appear at the beginning of an assembler file. */
10042 static void
10044 {
10051 /* The Unicos/Mk assembler uses different register names. Instead of trying
10052 to support them, we simply use micro definitions. */
10054 /* CAM has different register names: rN for the integer register N and fN
10055 for the floating-point register N. Instead of trying to use these in
10056 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10057 register. */
10067 /* The .align directive fill unused space with zeroes which does not work
10068 in code sections. We define the macro 'gcc@code@align' which uses nops
10069 instead. Note that it assumes that code sections always have the
10070 biggest possible alignment since . refers to the current offset from
10071 the beginning of the section. */
10083 /* Output extern declarations which should always be visible. */
10086 /* Open a dummy section. We always need to be inside a section for the
10087 section-switching code to work correctly.
10088 ??? This should be a module id or something like that. I still have to
10089 figure out what the rules for those are. */
10091 }
10093 /* Output text to appear at the end of an assembler file. This includes all
10094 pending extern declarations and DEX expressions. */
10096 static void
10098 {
10101 /* Output all pending externs. */
10105 /* Output dex definitions used for functions whose names conflict with
10106 register names. */
10113 }
10115 #else
10117 static void
10119 {}
10121 static void
10123 {}
10125 static void
10128 {}
10130 rtx
10132 {
10134 }
10136 static int
10138 {
10140 }
10144 static void
10146 {
10148 {
10149 /* Prevent gcc from generating calls to __divsi3. */
10153 /* Use the functions provided by the system library
10154 for DImode integer division. */
10157 }
10159 {
10160 /* Use the VMS runtime library functions for division and
10161 remainder. */
10170 }
10171 }
10173 \f
10174 /* Initialize the GCC target structure. */
10175 #if TARGET_ABI_OPEN_VMS
10176 # undef TARGET_ATTRIBUTE_TABLE
10177 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10178 # undef TARGET_SECTION_TYPE_FLAGS
10179 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10180 #endif
10182 #undef TARGET_IN_SMALL_DATA_P
10183 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10185 #if TARGET_ABI_UNICOSMK
10186 # undef TARGET_INSERT_ATTRIBUTES
10187 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10188 # undef TARGET_SECTION_TYPE_FLAGS
10189 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10190 # undef TARGET_ASM_UNIQUE_SECTION
10191 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10192 # undef TARGET_ASM_GLOBALIZE_LABEL
10193 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10194 #endif
10196 #undef TARGET_ASM_ALIGNED_HI_OP
10198 #undef TARGET_ASM_ALIGNED_DI_OP
10201 /* Default unaligned ops are provided for ELF systems. To get unaligned
10202 data for non-ELF systems, we have to turn off auto alignment. */
10203 #ifndef OBJECT_FORMAT_ELF
10204 #undef TARGET_ASM_UNALIGNED_HI_OP
10206 #undef TARGET_ASM_UNALIGNED_SI_OP
10208 #undef TARGET_ASM_UNALIGNED_DI_OP
10210 #endif
10212 #ifdef OBJECT_FORMAT_ELF
10213 #undef TARGET_ASM_SELECT_RTX_SECTION
10214 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10215 #endif
10217 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10218 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10220 #undef TARGET_INIT_LIBFUNCS
10221 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10223 #if TARGET_ABI_UNICOSMK
10224 #undef TARGET_ASM_FILE_START
10225 #define TARGET_ASM_FILE_START unicosmk_file_start
10226 #undef TARGET_ASM_FILE_END
10227 #define TARGET_ASM_FILE_END unicosmk_file_end
10228 #else
10229 #undef TARGET_ASM_FILE_START
10230 #define TARGET_ASM_FILE_START alpha_file_start
10231 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10232 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10233 #endif
10235 #undef TARGET_SCHED_ADJUST_COST
10236 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10237 #undef TARGET_SCHED_ISSUE_RATE
10238 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10239 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10240 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10241 alpha_use_dfa_pipeline_interface
10242 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10243 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10244 alpha_multipass_dfa_lookahead
10246 #undef TARGET_HAVE_TLS
10247 #define TARGET_HAVE_TLS HAVE_AS_TLS
10249 #undef TARGET_INIT_BUILTINS
10250 #define TARGET_INIT_BUILTINS alpha_init_builtins
10251 #undef TARGET_EXPAND_BUILTIN
10252 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10254 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10255 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10256 #undef TARGET_CANNOT_COPY_INSN_P
10257 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10259 #if TARGET_ABI_OSF
10260 #undef TARGET_ASM_OUTPUT_MI_THUNK
10261 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10262 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10263 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10264 #endif
10266 #undef TARGET_RTX_COSTS
10267 #define TARGET_RTX_COSTS alpha_rtx_costs
10268 #undef TARGET_ADDRESS_COST
10269 #define TARGET_ADDRESS_COST hook_int_rtx_0
10271 #undef TARGET_MACHINE_DEPENDENT_REORG
10272 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10274 #undef TARGET_PROMOTE_FUNCTION_ARGS
10275 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10276 #undef TARGET_PROMOTE_FUNCTION_RETURN
10277 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10278 #undef TARGET_PROMOTE_PROTOTYPES
10279 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10280 #undef TARGET_RETURN_IN_MEMORY
10281 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10282 #undef TARGET_SETUP_INCOMING_VARARGS
10283 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10284 #undef TARGET_STRICT_ARGUMENT_NAMING
10285 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10286 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10287 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10288 #undef TARGET_SPLIT_COMPLEX_ARG
10289 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10290 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10291 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10293 #undef TARGET_BUILD_BUILTIN_VA_LIST
10294 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10298 \f