1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004-2013 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
34 (define_predicate "imm_for_neon_inv_logic_operand"
35 (match_code "const_vector")
38 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
41 (define_predicate "neon_inv_logic_op2"
42 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
43 (match_operand 0 "s_register_operand")))
46 (define_predicate "arm_hard_register_operand"
49 return REGNO (op) < FIRST_PSEUDO_REGISTER;
53 (define_predicate "low_register_operand"
54 (and (match_code "reg")
55 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
57 ;; A low register or const_int.
58 (define_predicate "low_reg_or_int_operand"
59 (ior (match_code "const_int")
60 (match_operand 0 "low_register_operand")))
62 ;; Any core register, or any pseudo. */
63 (define_predicate "arm_general_register_operand"
64 (match_code "reg,subreg")
66 if (GET_CODE (op) == SUBREG)
70 && (REGNO (op) <= LAST_ARM_REGNUM
71 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
74 (define_predicate "vfp_register_operand"
75 (match_code "reg,subreg")
77 if (GET_CODE (op) == SUBREG)
80 /* We don't consider registers whose class is NO_REGS
81 to be a register operand. */
83 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
84 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
85 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
87 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
90 (define_predicate "zero_operand"
91 (and (match_code "const_int,const_double,const_vector")
92 (match_test "op == CONST0_RTX (mode)")))
94 ;; Match a register, or zero in the appropriate mode.
95 (define_predicate "reg_or_zero_operand"
96 (ior (match_operand 0 "s_register_operand")
97 (match_operand 0 "zero_operand")))
99 (define_special_predicate "subreg_lowpart_operator"
100 (and (match_code "subreg")
101 (match_test "subreg_lowpart_p (op)")))
103 ;; Reg, subreg(reg) or const_int.
104 (define_predicate "reg_or_int_operand"
105 (ior (match_code "const_int")
106 (match_operand 0 "s_register_operand")))
108 (define_predicate "arm_immediate_operand"
109 (and (match_code "const_int")
110 (match_test "const_ok_for_arm (INTVAL (op))")))
112 ;; A constant value which fits into two instructions, each taking
113 ;; an arithmetic constant operand for one of the words.
114 (define_predicate "arm_immediate_di_operand"
115 (and (match_code "const_int,const_double")
116 (match_test "arm_const_double_by_immediates (op)")))
118 (define_predicate "arm_neg_immediate_operand"
119 (and (match_code "const_int")
120 (match_test "const_ok_for_arm (-INTVAL (op))")))
122 (define_predicate "arm_not_immediate_operand"
123 (and (match_code "const_int")
124 (match_test "const_ok_for_arm (~INTVAL (op))")))
126 (define_predicate "const0_operand"
127 (and (match_code "const_int")
128 (match_test "INTVAL (op) == 0")))
130 ;; Something valid on the RHS of an ARM data-processing instruction
131 (define_predicate "arm_rhs_operand"
132 (ior (match_operand 0 "s_register_operand")
133 (match_operand 0 "arm_immediate_operand")))
135 (define_predicate "arm_rhsm_operand"
136 (ior (match_operand 0 "arm_rhs_operand")
137 (match_operand 0 "memory_operand")))
139 ;; This doesn't have to do much because the constant is already checked
140 ;; in the shift_operator predicate.
141 (define_predicate "shift_amount_operand"
142 (ior (and (match_test "TARGET_ARM")
143 (match_operand 0 "s_register_operand"))
144 (match_operand 0 "const_int_operand")))
146 (define_predicate "const_neon_scalar_shift_amount_operand"
147 (and (match_code "const_int")
148 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
149 && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
151 (define_predicate "ldrd_strd_offset_operand"
152 (and (match_operand 0 "const_int_operand")
153 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
155 (define_predicate "arm_add_operand"
156 (ior (match_operand 0 "arm_rhs_operand")
157 (match_operand 0 "arm_neg_immediate_operand")))
159 (define_predicate "arm_anddi_operand_neon"
160 (ior (match_operand 0 "s_register_operand")
161 (and (match_code "const_int")
162 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))
163 (match_operand 0 "neon_inv_logic_op2")))
165 (define_predicate "arm_adddi_operand"
166 (ior (match_operand 0 "s_register_operand")
167 (and (match_code "const_int")
168 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
170 (define_predicate "arm_addimm_operand"
171 (ior (match_operand 0 "arm_immediate_operand")
172 (match_operand 0 "arm_neg_immediate_operand")))
174 (define_predicate "arm_not_operand"
175 (ior (match_operand 0 "arm_rhs_operand")
176 (match_operand 0 "arm_not_immediate_operand")))
178 (define_predicate "arm_di_operand"
179 (ior (match_operand 0 "s_register_operand")
180 (match_operand 0 "arm_immediate_di_operand")))
182 ;; True if the operand is a memory reference which contains an
183 ;; offsettable address.
184 (define_predicate "offsettable_memory_operand"
185 (and (match_code "mem")
187 "offsettable_address_p (reload_completed | reload_in_progress,
188 mode, XEXP (op, 0))")))
190 ;; True if the operand is a memory operand that does not have an
191 ;; automodified base register (and thus will not generate output reloads).
192 (define_predicate "call_memory_operand"
193 (and (match_code "mem")
194 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
196 (match_operand 0 "memory_operand"))))
198 (define_predicate "arm_reload_memory_operand"
199 (and (match_code "mem,reg,subreg")
200 (match_test "(!CONSTANT_P (op)
201 && (true_regnum(op) == -1
203 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
205 (define_predicate "vfp_compare_operand"
206 (ior (match_operand 0 "s_register_operand")
207 (and (match_code "const_double")
208 (match_test "arm_const_double_rtx (op)"))))
210 (define_predicate "arm_float_compare_operand"
211 (if_then_else (match_test "TARGET_VFP")
212 (match_operand 0 "vfp_compare_operand")
213 (match_operand 0 "s_register_operand")))
215 ;; True for valid index operands.
216 (define_predicate "index_operand"
217 (ior (match_operand 0 "s_register_operand")
218 (and (match_operand 0 "immediate_operand")
219 (match_test "(!CONST_INT_P (op)
220 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
222 ;; True for operators that can be combined with a shift in ARM state.
223 (define_special_predicate "shiftable_operator"
224 (and (match_code "plus,minus,ior,xor,and")
225 (match_test "mode == GET_MODE (op)")))
227 ;; True for logical binary operators.
228 (define_special_predicate "logical_binary_operator"
229 (and (match_code "ior,xor,and")
230 (match_test "mode == GET_MODE (op)")))
232 ;; True for commutative operators
233 (define_special_predicate "commutative_binary_operator"
234 (and (match_code "ior,xor,and,plus")
235 (match_test "mode == GET_MODE (op)")))
237 ;; True for shift operators.
239 ;; * mult is only permitted with a constant shift amount
240 ;; * patterns that permit register shift amounts only in ARM mode use
241 ;; shift_amount_operand, patterns that always allow registers do not,
242 ;; so we don't have to worry about that sort of thing here.
243 (define_special_predicate "shift_operator"
244 (and (ior (ior (and (match_code "mult")
245 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
246 (and (match_code "rotate")
247 (match_test "CONST_INT_P (XEXP (op, 1))
248 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
249 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
250 (match_test "!CONST_INT_P (XEXP (op, 1))
251 || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
252 (match_test "mode == GET_MODE (op)")))
254 ;; True for shift operators which can be used with saturation instructions.
255 (define_special_predicate "sat_shift_operator"
256 (and (ior (and (match_code "mult")
257 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
258 (and (match_code "ashift,ashiftrt")
259 (match_test "CONST_INT_P (XEXP (op, 1))
260 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
261 (match_test "mode == GET_MODE (op)")))
263 ;; True for MULT, to identify which variant of shift_operator is in use.
264 (define_special_predicate "mult_operator"
267 ;; True for operators that have 16-bit thumb variants. */
268 (define_special_predicate "thumb_16bit_operator"
269 (match_code "plus,minus,and,ior,xor"))
272 (define_special_predicate "equality_operator"
273 (match_code "eq,ne"))
275 ;; True for integer comparisons and, if FP is active, for comparisons
276 ;; other than LTGT or UNEQ.
277 (define_special_predicate "expandable_comparison_operator"
278 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
279 unordered,ordered,unlt,unle,unge,ungt"))
281 ;; Likewise, but only accept comparisons that are directly supported
282 ;; by ARM condition codes.
283 (define_special_predicate "arm_comparison_operator"
284 (and (match_operand 0 "expandable_comparison_operator")
285 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
287 (define_special_predicate "lt_ge_comparison_operator"
288 (match_code "lt,ge"))
290 ;; The vsel instruction only accepts the ARM condition codes listed below.
291 (define_special_predicate "arm_vsel_comparison_operator"
292 (and (match_operand 0 "expandable_comparison_operator")
293 (match_test "maybe_get_arm_condition_code (op) == ARM_GE
294 || maybe_get_arm_condition_code (op) == ARM_GT
295 || maybe_get_arm_condition_code (op) == ARM_EQ
296 || maybe_get_arm_condition_code (op) == ARM_VS
297 || maybe_get_arm_condition_code (op) == ARM_LT
298 || maybe_get_arm_condition_code (op) == ARM_LE
299 || maybe_get_arm_condition_code (op) == ARM_NE
300 || maybe_get_arm_condition_code (op) == ARM_VC")))
302 (define_special_predicate "noov_comparison_operator"
303 (match_code "lt,ge,eq,ne"))
305 (define_special_predicate "minmax_operator"
306 (and (match_code "smin,smax,umin,umax")
307 (match_test "mode == GET_MODE (op)")))
309 (define_special_predicate "cc_register"
310 (and (match_code "reg")
311 (and (match_test "REGNO (op) == CC_REGNUM")
312 (ior (match_test "mode == GET_MODE (op)")
313 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
315 (define_special_predicate "dominant_cc_register"
318 if (mode == VOIDmode)
320 mode = GET_MODE (op);
322 if (GET_MODE_CLASS (mode) != MODE_CC)
326 return (cc_register (op, mode)
327 && (mode == CC_DNEmode
328 || mode == CC_DEQmode
329 || mode == CC_DLEmode
330 || mode == CC_DLTmode
331 || mode == CC_DGEmode
332 || mode == CC_DGTmode
333 || mode == CC_DLEUmode
334 || mode == CC_DLTUmode
335 || mode == CC_DGEUmode
336 || mode == CC_DGTUmode));
339 (define_special_predicate "arm_extendqisi_mem_op"
340 (and (match_operand 0 "memory_operand")
341 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
345 : memory_address_p (QImode, XEXP (op, 0))")))
347 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
348 (ior (match_operand 0 "arm_extendqisi_mem_op")
349 (match_operand 0 "s_register_operand")))
351 (define_predicate "power_of_two_operand"
352 (match_code "const_int")
354 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
356 return value != 0 && (value & (value - 1)) == 0;
359 (define_predicate "nonimmediate_di_operand"
360 (match_code "reg,subreg,mem")
362 if (s_register_operand (op, mode))
365 if (GET_CODE (op) == SUBREG)
366 op = SUBREG_REG (op);
368 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
371 (define_predicate "di_operand"
372 (ior (match_code "const_int,const_double")
373 (and (match_code "reg,subreg,mem")
374 (match_operand 0 "nonimmediate_di_operand"))))
376 (define_predicate "nonimmediate_soft_df_operand"
377 (match_code "reg,subreg,mem")
379 if (s_register_operand (op, mode))
382 if (GET_CODE (op) == SUBREG)
383 op = SUBREG_REG (op);
385 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
388 (define_predicate "soft_df_operand"
389 (ior (match_code "const_double")
390 (and (match_code "reg,subreg,mem")
391 (match_operand 0 "nonimmediate_soft_df_operand"))))
393 (define_special_predicate "load_multiple_operation"
394 (match_code "parallel")
396 return ldm_stm_operation_p (op, /*load=*/true, SImode,
397 /*consecutive=*/false,
398 /*return_pc=*/false);
401 (define_special_predicate "store_multiple_operation"
402 (match_code "parallel")
404 return ldm_stm_operation_p (op, /*load=*/false, SImode,
405 /*consecutive=*/false,
406 /*return_pc=*/false);
409 (define_special_predicate "pop_multiple_return"
410 (match_code "parallel")
412 return ldm_stm_operation_p (op, /*load=*/true, SImode,
413 /*consecutive=*/false,
417 (define_special_predicate "pop_multiple_fp"
418 (match_code "parallel")
420 return ldm_stm_operation_p (op, /*load=*/true, DFmode,
421 /*consecutive=*/true,
422 /*return_pc=*/false);
425 (define_special_predicate "multi_register_push"
426 (match_code "parallel")
428 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
429 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
430 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
436 (define_predicate "push_mult_memory_operand"
439 /* ??? Given how PUSH_MULT is generated in the prologues, is there
440 any point in testing for thumb1 specially? All of the variants
441 use the same form. */
444 /* ??? No attempt is made to represent STMIA, or validate that
445 the stack adjustment matches the register count. This is
446 true of the ARM/Thumb2 path as well. */
447 rtx x = XEXP (op, 0);
448 if (GET_CODE (x) != PRE_MODIFY)
450 if (XEXP (x, 0) != stack_pointer_rtx)
453 if (GET_CODE (x) != PLUS)
455 if (XEXP (x, 0) != stack_pointer_rtx)
457 return CONST_INT_P (XEXP (x, 1));
460 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
461 return memory_operand (op, mode);
464 ;;-------------------------------------------------------------------------
469 (define_predicate "thumb1_cmp_operand"
470 (ior (and (match_code "reg,subreg")
471 (match_operand 0 "s_register_operand"))
472 (and (match_code "const_int")
473 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
475 (define_predicate "thumb1_cmpneg_operand"
476 (and (match_code "const_int")
477 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
479 ;; Return TRUE if a result can be stored in OP without clobbering the
480 ;; condition code register. Prior to reload we only accept a
481 ;; register. After reload we have to be able to handle memory as
482 ;; well, since a pseudo may not get a hard reg and reload cannot
483 ;; handle output-reloads on jump insns.
485 ;; We could possibly handle mem before reload as well, but that might
486 ;; complicate things with the need to handle increment
488 (define_predicate "thumb_cbrch_target_operand"
489 (and (match_code "reg,subreg,mem")
490 (ior (match_operand 0 "s_register_operand")
491 (and (match_test "reload_in_progress || reload_completed")
492 (match_operand 0 "memory_operand")))))
494 ;;-------------------------------------------------------------------------
499 (define_predicate "imm_or_reg_operand"
500 (ior (match_operand 0 "immediate_operand")
501 (match_operand 0 "register_operand")))
505 (define_predicate "const_multiple_of_8_operand"
506 (match_code "const_int")
508 unsigned HOST_WIDE_INT val = INTVAL (op);
509 return (val & 7) == 0;
512 (define_predicate "imm_for_neon_mov_operand"
513 (match_code "const_vector,const_int")
515 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
518 (define_predicate "imm_for_neon_lshift_operand"
519 (match_code "const_vector")
521 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
524 (define_predicate "imm_for_neon_rshift_operand"
525 (match_code "const_vector")
527 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
530 (define_predicate "imm_lshift_or_reg_neon"
531 (ior (match_operand 0 "s_register_operand")
532 (match_operand 0 "imm_for_neon_lshift_operand")))
534 (define_predicate "imm_rshift_or_reg_neon"
535 (ior (match_operand 0 "s_register_operand")
536 (match_operand 0 "imm_for_neon_rshift_operand")))
538 (define_predicate "imm_for_neon_logic_operand"
539 (match_code "const_vector")
542 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
545 (define_predicate "neon_logic_op2"
546 (ior (match_operand 0 "imm_for_neon_logic_operand")
547 (match_operand 0 "s_register_operand")))
549 ;; Predicates for named expanders that overlap multiple ISAs.
551 (define_predicate "cmpdi_operand"
552 (and (match_test "TARGET_32BIT")
553 (match_operand 0 "arm_di_operand")))
555 ;; True if the operand is memory reference suitable for a ldrex/strex.
556 (define_predicate "arm_sync_memory_operand"
557 (and (match_operand 0 "memory_operand")
558 (match_code "reg" "0")))
560 ;; Predicates for parallel expanders based on mode.
561 (define_special_predicate "vect_par_constant_high"
562 (match_code "parallel")
564 HOST_WIDE_INT count = XVECLEN (op, 0);
566 int base = GET_MODE_NUNITS (mode);
569 || (count != base/2))
572 if (!VECTOR_MODE_P (mode))
575 for (i = 0; i < count; i++)
577 rtx elt = XVECEXP (op, 0, i);
580 if (!CONST_INT_P (elt))
584 if (val != (base/2) + i)
590 (define_special_predicate "vect_par_constant_low"
591 (match_code "parallel")
593 HOST_WIDE_INT count = XVECLEN (op, 0);
595 int base = GET_MODE_NUNITS (mode);
598 || (count != base/2))
601 if (!VECTOR_MODE_P (mode))
604 for (i = 0; i < count; i++)
606 rtx elt = XVECEXP (op, 0, i);
609 if (!CONST_INT_P (elt))
619 (define_predicate "const_double_vcvt_power_of_two_reciprocal"
620 (and (match_code "const_double")
621 (match_test "TARGET_32BIT && TARGET_VFP
622 && vfp3_const_double_for_fract_bits (op)")))
624 (define_predicate "neon_struct_operand"
625 (and (match_code "mem")
626 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
628 (define_predicate "neon_struct_or_register_operand"
629 (ior (match_operand 0 "neon_struct_operand")
630 (match_operand 0 "s_register_operand")))
632 (define_special_predicate "add_operator"
635 (define_predicate "mem_noofs_operand"
636 (and (match_code "mem")
637 (match_code "reg" "0")))