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1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
97 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
107 /* Number of attempts to combine instructions in this function. */
111 /* Number of attempts that got as far as substitution in this function. */
115 /* Number of instructions combined with added SETs in this function. */
119 /* Number of instructions combined in this function. */
123 /* Totals over entire compilation. */
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 \f
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
158 following ways:
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
173 register's value
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
178 table.
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
196 rtx last_set_value;
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
203 /* Record the value of label_tick when the value for register n is placed in
204 last_set_value. */
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
231 zero.
233 If an entry is zero, it means that we don't know anything special. */
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
248 value. */
251 };
256 /* One plus the highest pseudo for which we track REG_N_SETS.
257 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
258 but during combine_split_insns new pseudos can be created. As we don't have
259 updated DF information in that case, it is hard to initialize the array
260 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
261 so instead of growing the arrays, just assume all newly created pseudos
262 during combine might be set multiple times. */
266 /* Record the luid of the last insn that invalidated memory
267 (anything that writes memory, and subroutine calls, but not pushes). */
271 /* Record the luid of the last CALL_INSN
272 so we can tell whether a potential combination crosses any calls. */
276 /* When `subst' is called, this is the insn that is being modified
277 (by combining in a previous insn). The PATTERN of this insn
278 is still the old pattern partially modified and it should not be
279 looked at, but this may be used to examine the successors of the insn
280 to judge whether a simplification is valid. */
284 /* This is the lowest LUID that `subst' is currently dealing with.
285 get_last_value will not return a value if the register was set at or
286 after this LUID. If not for this mechanism, we could get confused if
287 I2 or I1 in try_combine were an insn that used the old value of a register
288 to obtain a new value. In that case, we might erroneously get the
289 new value of the register when we wanted the old one. */
293 /* This contains any hard registers that are used in newpat; reg_dead_at_p
294 must consider all these registers to be always live. */
298 /* This is an insn to which a LOG_LINKS entry has been added. If this
299 insn is the earlier than I2 or I3, combine should rescan starting at
300 that location. */
304 /* Basic block in which we are performing combines. */
308 \f
309 /* Length of the currently allocated uid_insn_cost array. */
313 /* The following array records the insn_rtx_cost for every insn
314 in the instruction stream. */
318 /* The following array records the LOG_LINKS for every insn in the
319 instruction stream as struct insn_link pointers. */
325 };
329 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
330 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
332 #define FOR_EACH_LOG_LINK(L, INSN) \
333 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
335 /* Links for LOG_LINKS are allocated from this obstack. */
339 /* Allocate a link. */
343 {
351 }
353 /* Incremented for each basic block. */
357 /* Reset to label_tick for each extended basic block in scanning order. */
361 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
362 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
366 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
367 be safely used. It is zero while computing them and after combine has
368 completed. This former test prevents propagating values based on
369 previously set values, which can be incorrect if a variable is modified
370 in a loop. */
374 \f
375 /* Record one modification to rtl structure
376 to be undone by storing old_contents into *where. */
380 struct undo
381 {
386 };
388 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
389 num_undo says how many are currently recorded.
391 other_insn is nonzero if we have modified some other insn in the process
392 of working on subst_insn. It must be verified too. */
394 struct undobuf
395 {
399 };
403 /* Number of times the pseudo being substituted for
404 was found and replaced. */
409 machine_mode,
413 machine_mode,
485 \f
487 /* It is not safe to use ordinary gen_lowpart in combine.
488 See comments in gen_lowpart_for_combine. */
489 #undef RTL_HOOKS_GEN_LOWPART
490 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
492 /* Our implementation of gen_lowpart never emits a new pseudo. */
493 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
494 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
496 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
497 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
499 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
500 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
502 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
503 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
507 \f
508 /* Convenience wrapper for the canonicalize_comparison target hook.
509 Target hooks cannot use enum rtx_code. */
513 {
517 }
519 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
520 PATTERN can not be split. Otherwise, it returns an insn sequence.
521 This is a wrapper around split_insns which ensures that the
522 reg_stat vector is made larger if the splitter creates a new
523 register. */
527 {
536 }
538 /* This is used by find_single_use to locate an rtx in LOC that
539 contains exactly one use of DEST, which is typically either a REG
540 or CC0. It returns a pointer to the innermost rtx expression
541 containing DEST. Appearances of DEST that are being used to
542 totally replace it are not counted. */
546 {
555 {
559 CASE_CONST_ANY:
564 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
565 of a REG that occupies all of the REG, the insn uses DEST if
566 it is mentioned in the destination or the source. Otherwise, we
567 need just check the source. */
587 }
589 /* If it wasn't one of the common cases above, check each expression and
590 vector of this code. Look for a unique usage of DEST. */
594 {
596 {
601 else
607 /* Duplicate usage. */
609 }
611 {
615 {
621 else
628 }
629 }
630 }
633 }
636 /* See if DEST, produced in INSN, is used only a single time in the
637 sequel. If so, return a pointer to the innermost rtx expression in which
638 it is used.
640 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
642 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
643 care about REG_DEAD notes or LOG_LINKS.
645 Otherwise, we find the single use by finding an insn that has a
646 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
647 only referenced once in that insn, we know that it must be the first
648 and last insn referencing DEST. */
652 {
653 basic_block bb;
659 {
669 }
679 {
685 {
690 }
691 }
694 }
695 \f
696 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
697 insn. The substitution can be undone by undo_all. If INTO is already
698 set to NEWVAL, do not record this change. Because computing NEWVAL might
699 also call SUBST, we have to compute it before we put anything into
700 the undo table. */
702 static void
704 {
711 /* We'd like to catch as many invalid transformations here as
712 possible. Unfortunately, there are way too many mode changes
713 that are perfectly valid, so we'd waste too much effort for
714 little gain doing the checks here. Focus on catching invalid
715 transformations involving integer constants. */
718 {
719 /* Sanity check that we're replacing oldval with a CONST_INT
720 that is a valid sign-extension for the original mode. */
724 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
725 CONST_INT is not valid, because after the replacement, the
726 original mode would be gone. Unfortunately, we can't tell
727 when do_SUBST is called to replace the operand thereof, so we
728 perform this test on oldval instead, checking whether an
729 invalid replacement took place before we got here. */
734 }
738 else
747 }
749 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
751 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
752 for the value of a HOST_WIDE_INT value (including CONST_INT) is
753 not safe. */
755 static void
757 {
766 else
775 }
777 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
779 /* Similar to SUBST, but just substitute the mode. This is used when
780 changing the mode of a pseudo-register, so that any other
781 references to the entry in the regno_reg_rtx array will change as
782 well. */
784 static void
786 {
795 else
804 }
806 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
808 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
810 static void
812 {
821 else
830 }
832 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
833 \f
834 /* Subroutine of try_combine. Determine whether the replacement patterns
835 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
836 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
837 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
838 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
839 of all the instructions can be estimated and the replacements are more
840 expensive than the original sequence. */
842 static bool
845 {
850 /* Lookup the original insn_rtx_costs. */
855 {
858 {
862 }
863 else
864 {
868 }
869 }
870 else
871 {
874 }
876 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
877 correct that. */
882 /* Calculate the replacement insn_rtx_costs. */
885 {
889 }
890 else
891 {
894 }
897 {
903 {
906 }
907 else
909 }
911 /* Disallow this combination if both new_cost and old_cost are greater than
912 zero, and new_cost is greater than old cost. */
916 {
935 else
937 }
942 /* Update the uid_insn_cost array with the replacement costs. */
946 {
950 }
953 }
956 /* Delete any insns that copy a register to itself. */
958 static void
960 {
962 basic_block bb;
965 {
967 {
970 {
975 }
976 }
977 }
978 }
980 \f
981 /* Return false if we do not want to (or cannot) combine DEF. */
982 static bool
984 {
985 /* Do not consider if it is pre/post modification in MEM. */
991 /* Do not combine frame pointer adjustments. */
994 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1002 }
1004 /* Return false if we do not want to (or cannot) combine USE. */
1005 static bool
1007 {
1008 /* Do not consider the usage of the stack pointer by function call. */
1013 }
1015 /* Fill in log links field for all insns. */
1017 static void
1019 {
1020 basic_block bb;
1027 /* Pass through each block from the end, recording the uses of each
1028 register and establishing log links when def is encountered.
1029 Note that we do not clear next_use array in order to save time,
1030 so we have to test whether the use is in the same basic block as def.
1032 There are a few cases below when we do not consider the definition or
1033 usage -- these are taken from original flow.c did. Don't ask me why it is
1034 done this way; I don't know and if it works, I don't want to know. */
1037 {
1039 {
1043 /* Log links are created only once. */
1047 {
1063 /* flow.c claimed:
1065 We don't build a LOG_LINK for hard registers contained
1066 in ASM_OPERANDs. If these registers get replaced,
1067 we might wind up changing the semantics of the insn,
1068 even if reload can make what appear to be valid
1069 assignments later. */
1074 /* Don't add duplicate links between instructions. */
1083 }
1088 }
1089 }
1092 }
1094 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1095 true if we found a LOG_LINK that proves that A feeds B. This only works
1096 if there are no instructions between A and B which could have a link
1097 depending on A, since in that case we would not record a link for B.
1098 We also check the implicit dependency created by a cc0 setter/user
1099 pair. */
1101 static bool
1103 {
1111 }
1112 \f
1113 /* Main entry point for combiner. F is the first insn of the function.
1114 NREGS is the first unused pseudo-reg number.
1116 Return nonzero if the combiner has turned an indirect jump
1117 instruction into a direct jump. */
1118 static int
1120 {
1125 basic_block last_bb;
1145 /* Allocate array for insn info. */
1153 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1154 problems when, for example, we have j <<= 1 in a loop. */
1159 /* Scan all SETs and see if we can deduce anything about what
1160 bits are known to be zero for some registers and how many copies
1161 of the sign bit are known to exist for those registers.
1163 Also set any known values so that we can use it while searching
1164 for what bits are known to be set. */
1167 /* Allow the entry block and the first block to fall into the same EBB.
1168 Conceptually the incoming promotions are assigned to the entry block. */
1173 {
1178 label_tick++;
1186 {
1187 rtx links;
1193 insn);
1200 insn);
1202 /* Record the current insn_rtx_cost of this instruction. */
1205 optimize_this_for_speed_p);
1209 }
1210 }
1214 /* Now scan all the insns in forward order. */
1222 {
1228 label_tick++;
1238 {
1252 /* See if we know about function return values before this
1253 insn based upon SUBREG flags. */
1256 /* See if we can find hardregs and subreg of pseudos in
1257 narrower modes. This could help turning TRUNCATEs
1258 into SUBREGs. */
1261 /* Try this insn with each insn it links back to. */
1267 {
1270 }
1272 /* Try each sequence of three linked insns ending with this one. */
1276 {
1279 /* If the linked insn has been replaced by a note, then there
1280 is no point in pursuing this chain any further. */
1288 {
1291 }
1292 }
1294 /* Try to combine a jump insn that uses CC0
1295 with a preceding insn that sets CC0, and maybe with its
1296 logical predecessor as well.
1297 This is how we make decrement-and-branch insns.
1298 We need this special code because data flow connections
1299 via CC0 do not get entered in LOG_LINKS. */
1306 {
1317 }
1319 /* Do the same for an insn that explicitly references CC0. */
1326 {
1337 }
1339 /* Finally, see if any of the insns that this insn links to
1340 explicitly references CC0. If so, try this insn, that insn,
1341 and its predecessor if it sets CC0. */
1343 {
1355 }
1357 /* Try combining an insn with two different insns whose results it
1358 uses. */
1368 {
1371 }
1373 /* Try four-instruction combinations. */
1376 {
1380 /* If the linked insn has been replaced by a note, then there
1381 is no point in pursuing this chain any further. */
1386 {
1390 /* I0 -> I1 -> I2 -> I3. */
1396 {
1399 }
1400 /* I0, I1 -> I2, I2 -> I3. */
1407 {
1410 }
1411 }
1414 {
1418 /* I0 -> I2; I1, I2 -> I3. */
1424 {
1427 }
1428 /* I0 -> I1; I1, I2 -> I3. */
1434 {
1437 }
1438 }
1439 }
1441 /* Try this insn with each REG_EQUAL note it links back to. */
1443 {
1449 /* Avoid using a register that may already been marked
1450 dead by an earlier instruction. */
1458 {
1459 /* Temporarily replace the set's source with the
1460 contents of the REG_EQUAL note. The insn will
1461 be deleted or recognized by try_combine. */
1472 last_combined_insn);
1475 {
1478 }
1481 }
1482 }
1487 retry:
1488 ;
1489 }
1490 }
1497 /* Clean up. */
1503 {
1506 {
1509 }
1511 }
1521 /* Make recognizer allow volatile MEMs again. */
1525 }
1527 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1529 static void
1531 {
1537 }
1538 \f
1539 /* Set up any promoted values for incoming argument registers. */
1541 static void
1543 {
1544 tree arg;
1549 {
1554 /* Only continue if the incoming argument is in a register. */
1558 /* Determine, if possible, whether all call sites of the current
1559 function lie within the current compilation unit. (This does
1560 take into account the exporting of a function via taking its
1561 address, and so forth.) */
1564 /* The mode and signedness of the argument before any promotions happen
1565 (equal to the mode of the pseudo holding it at that stage). */
1569 /* The mode and signedness of the argument after any source language and
1570 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1574 /* The mode and signedness of the argument as it is actually passed,
1575 see assign_parm_setup_reg in function.c. */
1579 /* The mode of the register in which the argument is being passed. */
1582 /* Eliminate sign extensions in the callee when:
1583 (a) A mode promotion has occurred; */
1586 /* (b) The mode of the register is the same as the mode of
1587 the argument as it is passed; */
1590 /* (c) There's no language level extension; */
1592 ;
1593 /* (c.1) All callers are from the current compilation unit. If that's
1594 the case we don't have to rely on an ABI, we only have to know
1595 what we're generating right now, and we know that we will do the
1596 mode1 to mode2 promotion with the given sign. */
1599 /* (c.2) The combination of the two promotions is useful. This is
1600 true when the signs match, or if the first promotion is unsigned.
1601 In the later case, (sign_extend (zero_extend x)) is the same as
1602 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1608 /* Record that the value was promoted from mode1 to mode3,
1609 so that any sign extension at the head of the current
1610 function may be eliminated. */
1614 }
1615 }
1617 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1618 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1619 because some machines (maybe most) will actually do the sign-extension and
1620 this is the conservative approach.
1622 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1623 kludge. */
1625 static rtx
1627 {
1635 }
1637 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1638 and SET. */
1640 static void
1642 rtx x)
1643 {
1653 {
1657 }
1659 /* Don't call nonzero_bits if it cannot change anything. */
1661 {
1666 }
1668 /* Don't call num_sign_bit_copies if it cannot change anything. */
1670 {
1673 {
1677 }
1680 }
1681 }
1683 /* Called via note_stores. If X is a pseudo that is narrower than
1684 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1686 If we are setting only a portion of X and we can't figure out what
1687 portion, assume all bits will be used since we don't know what will
1688 be happening.
1690 Similarly, set how many bits of X are known to be copies of the sign bit
1691 at all locations in the function. This is the smallest number implied
1692 by any set of X. */
1694 static void
1696 {
1701 /* If this register is undefined at the start of the file, we can't
1702 say what its contents were. */
1703 && ! REGNO_REG_SET_P
1706 {
1710 {
1714 }
1716 /* If this register is being initialized using itself, and the
1717 register is uninitialized in this basic block, and there are
1718 no LOG_LINKS which set the register, then part of the
1719 register is uninitialized. In that case we can't assume
1720 anything about the number of nonzero bits.
1722 ??? We could do better if we checked this in
1723 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1724 could avoid making assumptions about the insn which initially
1725 sets the register, while still using the information in other
1726 insns. We would have to be careful to check every insn
1727 involved in the combination. */
1733 {
1740 {
1744 }
1745 }
1747 /* If this is a complex assignment, see if we can convert it into a
1748 simple assignment. */
1751 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1752 set what we know about X. */
1758 else
1759 {
1762 }
1763 }
1764 }
1765 \f
1766 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1767 optionally insns that were previously combined into I3 or that will be
1768 combined into the merger of INSN and I3. The order is PRED, PRED2,
1769 INSN, SUCC, SUCC2, I3.
1771 Return 0 if the combination is not allowed for any reason.
1773 If the combination is allowed, *PDEST will be set to the single
1774 destination of INSN and *PSRC to the single source, and this function
1775 will return 1. */
1777 static int
1781 {
1786 rtx link;
1791 {
1793 {
1798 }
1803 }
1807 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1808 or a PARALLEL consisting of such a SET and CLOBBERs.
1810 If INSN has CLOBBER parallel parts, ignore them for our processing.
1811 By definition, these happen during the execution of the insn. When it
1812 is merged with another insn, all bets are off. If they are, in fact,
1813 needed and aren't also supplied in I3, they may be added by
1814 recog_for_combine. Otherwise, it won't match.
1816 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1817 note.
1819 Get the source and destination of INSN. If more than one, can't
1820 combine. */
1826 {
1828 {
1832 {
1833 /* This is important to combine floating point insns
1834 for the SH4 port. */
1836 /* Combining an isolated USE doesn't make sense.
1837 We depend here on combinable_i3pat to reject them. */
1838 /* The code below this loop only verifies that the inputs of
1839 the SET in INSN do not change. We call reg_set_between_p
1840 to verify that the REG in the USE does not change between
1841 I3 and INSN.
1842 If the USE in INSN was for a pseudo register, the matching
1843 insn pattern will likely match any register; combining this
1844 with any other USE would only be safe if we knew that the
1845 used registers have identical values, or if there was
1846 something to tell them apart, e.g. different modes. For
1847 now, we forgo such complicated tests and simply disallow
1848 combining of USES of pseudo registers with any other USE. */
1851 {
1856 do
1857 {
1867 }
1869 }
1872 /* We can ignore CLOBBERs. */
1877 /* Ignore SETs whose result isn't used but not those that
1878 have side-effects. */
1884 /* If we have already found a SET, this is a second one and
1885 so we cannot combine with this insn. */
1893 /* Anything else means we can't combine. */
1895 }
1896 }
1899 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1900 so don't do anything with it. */
1903 }
1904 else
1910 /* The simplification in expand_field_assignment may call back to
1911 get_last_value, so set safe guard here. */
1917 /* Do not eliminate user-specified register if it is in an
1918 asm input because we may break the register asm usage defined
1919 in GCC manual if allow to do so.
1920 Be aware that this may cover more cases than we expect but this
1921 should be harmless. */
1926 /* Don't eliminate a store in the stack pointer. */
1928 /* Don't combine with an insn that sets a register to itself if it has
1929 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1931 /* Can't merge an ASM_OPERANDS. */
1933 /* Can't merge a function call. */
1935 /* Don't eliminate a function call argument. */
1941 /* Don't substitute into an incremented register. */
1945 /* Don't substitute into a non-local goto, this confuses CFG. */
1947 /* Make sure that DEST is not used after SUCC but before I3. */
1948 || (!all_adjacent
1949 && ((succ2
1953 /* Make sure that the value that is to be substituted for the register
1954 does not use any registers whose values alter in between. However,
1955 If the insns are adjacent, a use can't cross a set even though we
1956 think it might (this can happen for a sequence of insns each setting
1957 the same destination; last_set of that register might point to
1958 a NOTE). If INSN has a REG_EQUIV note, the register is always
1959 equivalent to the memory so the substitution is valid even if there
1960 are intervening stores. Also, don't move a volatile asm or
1961 UNSPEC_VOLATILE across any other insns. */
1962 || (! all_adjacent
1968 /* Don't combine across a CALL_INSN, because that would possibly
1969 change whether the life span of some REGs crosses calls or not,
1970 and it is a pain to update that information.
1971 Exception: if source is a constant, moving it later can't hurt.
1972 Accept that as a special case. */
1976 /* DEST must either be a REG or CC0. */
1978 {
1979 /* If register alignment is being enforced for multi-word items in all
1980 cases except for parameters, it is possible to have a register copy
1981 insn referencing a hard register that is not allowed to contain the
1982 mode being copied and which would not be valid as an operand of most
1983 insns. Eliminate this problem by not combining with such an insn.
1985 Also, on some machines we don't want to extend the life of a hard
1986 register. */
1991 /* Don't extend the life of a hard register unless it is
1992 user variable (if we have few registers) or it can't
1993 fit into the desired register (meaning something special
1994 is going on).
1995 Also avoid substituting a return register into I3, because
1996 reload can't handle a conflict with constraints of other
1997 inputs. */
2001 }
2009 {
2012 /* If the clobber represents an earlyclobber operand, we must not
2013 substitute an expression containing the clobbered register.
2014 As we do not analyze the constraint strings here, we have to
2015 make the conservative assumption. However, if the register is
2016 a fixed hard reg, the clobber cannot represent any operand;
2017 we leave it up to the machine description to either accept or
2018 reject use-and-clobber patterns. */
2024 }
2026 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2027 or not), reject, unless nothing volatile comes between it and I3 */
2030 {
2031 /* Make sure neither succ nor succ2 contains a volatile reference. */
2036 /* We'll check insns between INSN and I3 below. */
2037 }
2039 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2040 to be an explicit register variable, and was chosen for a reason. */
2046 /* If INSN contains volatile references (specifically volatile MEMs),
2047 we cannot combine across any other volatile references.
2048 Even if INSN doesn't contain volatile references, any intervening
2049 volatile insn might affect machine state. */
2052 ? volatile_refs_p
2059 /* If INSN contains an autoincrement or autodecrement, make sure that
2060 register is not used between there and I3, and not already used in
2061 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2062 Also insist that I3 not be a jump; if it were one
2063 and the incremented register were spilled, we would lose. */
2081 /* Don't combine an insn that follows a CC0-setting insn.
2082 An insn that uses CC0 must not be separated from the one that sets it.
2083 We do, however, allow I2 to follow a CC0-setting insn if that insn
2084 is passed as I1; in that case it will be deleted also.
2085 We also allow combining in this case if all the insns are adjacent
2086 because that would leave the two CC0 insns adjacent as well.
2087 It would be more logical to test whether CC0 occurs inside I1 or I2,
2088 but that would be much slower, and this ought to be equivalent. */
2091 {
2096 }
2098 /* If we get here, we have passed all the tests and the combination is
2099 to be allowed. */
2105 }
2106 \f
2107 /* LOC is the location within I3 that contains its pattern or the component
2108 of a PARALLEL of the pattern. We validate that it is valid for combining.
2110 One problem is if I3 modifies its output, as opposed to replacing it
2111 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2112 doing so would produce an insn that is not equivalent to the original insns.
2114 Consider:
2116 (set (reg:DI 101) (reg:DI 100))
2117 (set (subreg:SI (reg:DI 101) 0) <foo>)
2119 This is NOT equivalent to:
2121 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2122 (set (reg:DI 101) (reg:DI 100))])
2124 Not only does this modify 100 (in which case it might still be valid
2125 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2127 We can also run into a problem if I2 sets a register that I1
2128 uses and I1 gets directly substituted into I3 (not via I2). In that
2129 case, we would be getting the wrong value of I2DEST into I3, so we
2130 must reject the combination. This case occurs when I2 and I1 both
2131 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2132 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2133 of a SET must prevent combination from occurring. The same situation
2134 can occur for I0, in which case I0_NOT_IN_SRC is set.
2136 Before doing the above check, we first try to expand a field assignment
2137 into a set of logical operations.
2139 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2140 we place a register that is both set and used within I3. If more than one
2141 such register is detected, we fail.
2143 Return 1 if the combination is valid, zero otherwise. */
2145 static int
2148 {
2152 {
2157 rtx subdest;
2164 /* Check for the case where I3 modifies its output, as discussed
2165 above. We don't want to prevent pseudos from being combined
2166 into the address of a MEM, so only prevent the combination if
2167 i1 or i2 set the same MEM. */
2177 /* This is the same test done in can_combine_p except we can't test
2178 all_adjacent; we don't have to, since this instruction will stay
2179 in place, thus we are not considering increasing the lifetime of
2180 INNER_DEST.
2182 Also, if this insn sets a function argument, combining it with
2183 something that might need a spill could clobber a previous
2184 function argument; the all_adjacent test in can_combine_p also
2185 checks this; here, we do a more specific test for this case. */
2195 /* If DEST is used in I3, it is being killed in this insn, so
2196 record that for later. We have to consider paradoxical
2197 subregs here, since they kill the whole register, but we
2198 ignore partial subregs, STRICT_LOW_PART, etc.
2199 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2200 STACK_POINTER_REGNUM, since these are always considered to be
2201 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2211 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2217 {
2222 }
2223 }
2226 {
2233 }
2236 }
2237 \f
2238 /* Return 1 if X is an arithmetic expression that contains a multiplication
2239 and division. We don't count multiplications by powers of two here. */
2241 static int
2243 {
2245 {
2261 }
2262 }
2263 \f
2264 /* Determine whether INSN can be used in a combination. Return nonzero if
2265 not. This is used in try_combine to detect early some cases where we
2266 can't perform combinations. */
2268 static int
2270 {
2271 rtx set;
2274 /* If this isn't really an insn, we can't do anything.
2275 This can occur when flow deletes an insn that it has merged into an
2276 auto-increment address. */
2280 /* Never combine loads and stores involving hard regs that are likely
2281 to be spilled. The register allocator can usually handle such
2282 reg-reg moves by tying. If we allow the combiner to make
2283 substitutions of likely-spilled regs, reload might die.
2284 As an exception, we allow combinations involving fixed regs; these are
2285 not available to the register allocator so there's no risk involved. */
2306 }
2308 struct likely_spilled_retval_info
2309 {
2312 };
2314 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2315 hard registers that are known to be written to / clobbered in full. */
2316 static void
2318 {
2335 else
2338 }
2340 /* Return nonzero iff part of the return value is live during INSN, and
2341 it is likely spilled. This can happen when more than one insn is needed
2342 to copy the return value, e.g. when we consider to combine into the
2343 second copy insn for a complex value. */
2345 static int
2347 {
2349 rtx reg;
2352 /* We assume here that no machine mode needs more than
2353 32 hard registers when the value overlaps with a register
2354 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2369 /* Disregard parts of the return value that are set later. */
2378 /* Check if any of the (probably) live return value registers is
2379 likely spilled. */
2380 nregs --;
2381 do
2382 {
2388 }
2390 /* Adjust INSN after we made a change to its destination.
2392 Changing the destination can invalidate notes that say something about
2393 the results of the insn and a LOG_LINK pointing to the insn. */
2395 static void
2397 {
2398 /* For notes, be conservative and simply remove them. */
2401 /* The new insn will have a destination that was previously the destination
2402 of an insn just above it. Call distribute_links to make a LOG_LINK from
2403 the next use of that destination. */
2419 }
2421 /* Return TRUE if combine can reuse reg X in mode MODE.
2422 ADDED_SETS is nonzero if the original set is still required. */
2423 static bool
2425 {
2432 /* Allow hard registers if the new mode is legal, and occupies no more
2433 registers than the old mode. */
2438 /* Or a pseudo that is only used once. */
2441 && !added_sets
2443 }
2446 /* Check whether X, the destination of a set, refers to part of
2447 the register specified by REG. */
2449 static bool
2451 {
2452 /* Check that reg is an integer mode register. */
2463 }
2465 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2466 Note that the INSN should be deleted *after* removing dead edges, so
2467 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2468 but not for a (set (pc) (label_ref FOO)). */
2470 static void
2472 {
2480 {
2485 /* Remove barriers from the footer if there are any. */
2488 {
2491 else
2495 }
2498 }
2499 }
2501 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2502 by an arbitrary number of CLOBBERs. */
2503 static bool
2505 {
2524 }
2526 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2527 CLOBBERs), can be split into individual SETs in that order, without
2528 changing semantics. */
2529 static bool
2531 {
2539 {
2548 }
2551 }
2553 /* Try to combine the insns I0, I1 and I2 into I3.
2554 Here I0, I1 and I2 appear earlier than I3.
2555 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2556 I3.
2558 If we are combining more than two insns and the resulting insn is not
2559 recognized, try splitting it into two insns. If that happens, I2 and I3
2560 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2561 Otherwise, I0, I1 and I2 are pseudo-deleted.
2563 Return 0 if the combination does not work. Then nothing is changed.
2564 If we did the combination, return the insn at which combine should
2565 resume scanning.
2567 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2568 new direct jump instruction.
2570 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2571 been I3 passed to an earlier try_combine within the same basic
2572 block. */
2577 {
2578 /* New patterns for I3 and I2, respectively. */
2582 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2583 dead. */
2585 /* Total number of SETs to put into I3. */
2587 /* Nonzero if I2's or I1's body now appears in I3. */
2589 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2591 /* Contains I3 if the destination of I3 is used in its source, which means
2592 that the old life of I3 is being killed. If that usage is placed into
2593 I2 and not in I3, a REG_DEAD note must be made. */
2595 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2597 /* Copy of SET_SRC of I1 and I0, if needed. */
2599 /* Set if I2DEST was reused as a scratch register. */
2601 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2603 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2608 /* Notes that must be added to REG_NOTES in I3 and I2. */
2610 /* Notes that we substituted I3 into I2 instead of the normal case. */
2612 /* Notes that I1, I2 or I3 is a MULT operation. */
2619 rtx temp_expr;
2622 rtx new_other_notes;
2625 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2626 never be). */
2630 /* Only try four-insn combinations when there's high likelihood of
2631 success. Look for simple insns, such as loads of constants or
2632 binary operations involving a constant. */
2634 {
2644 {
2647 rtx src;
2652 {
2655 }
2657 ngood++;
2660 nshift++;
2661 }
2663 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2664 are likely manipulating its value. Ideally we'll be able to combine
2665 all four insns into a bitfield insertion of some kind.
2667 Note the source in I0 might be inside a sign/zero extension and the
2668 memory modes in I0 and I3 might be different. So extract the address
2669 from the destination of I3 and search for it in the source of I0.
2671 In the event that there's a match but the source/dest do not actually
2672 refer to the same memory, the worst that happens is we try some
2673 combinations that we wouldn't have otherwise. */
2675 /* Ensure the source of SET0 is a MEM, possibly buried inside
2676 an extension. */
2682 /* Ensure the destination of SET3 is a MEM. */
2684 /* Would it be better to extract the base address for the MEM
2685 in SET3 and look for that? I don't have cases where it matters
2686 but I could envision such cases. */
2692 }
2694 /* Exit early if one of the insns involved can't be used for
2695 combinations. */
2706 combine_attempts++;
2709 /* Reset the hard register usage information. */
2713 {
2720 else
2723 }
2725 /* If multiple insns feed into one of I2 or I3, they can be in any
2726 order. To simplify the code below, reorder them in sequence. */
2736 /* First check for one important special case that the code below will
2737 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2738 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2739 we may be able to replace that destination with the destination of I3.
2740 This occurs in the common code where we compute both a quotient and
2741 remainder into a structure, in which case we want to do the computation
2742 directly into the structure to avoid register-register copies.
2744 Note that this case handles both multiple sets in I2 and also cases
2745 where I2 has a number of CLOBBERs inside the PARALLEL.
2747 We make very conservative checks below and only try to handle the
2748 most common cases of this. For example, we only handle the case
2749 where I2 and I3 are adjacent to avoid making difficult register
2750 usage tests. */
2758 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2759 below would need to check what is inside (and reg_overlap_mentioned_p
2760 doesn't support those codes anyway). Don't allow those destinations;
2761 the resulting insn isn't likely to be recognized anyway. */
2767 {
2770 /* Make sure that the destination of I3,
2771 which we are going to substitute into one output of I2,
2772 is not used within another output of I2. We must avoid making this:
2773 (parallel [(set (mem (reg 69)) ...)
2774 (set (reg 69) ...)])
2775 which is not well-defined as to order of actions.
2776 (Besides, reload can't handle output reloads for this.)
2778 The problem can also happen if the dest of I3 is a memory ref,
2779 if another dest in I2 is an indirect memory ref. */
2787 /* Make sure this PARALLEL is not an asm. We do not allow combining
2788 that usually (see can_combine_p), so do not here either. */
2798 {
2799 combine_merges++;
2809 /* Replace the dest in I2 with our dest and make the resulting
2810 insn the new pattern for I3. Then skip to where we validate
2811 the pattern. Everything was set up above. */
2816 }
2817 }
2819 /* If I2 is setting a pseudo to a constant and I3 is setting some
2820 sub-part of it to another constant, merge them by making a new
2821 constant. */
2828 {
2834 {
2837 {
2843 }
2844 }
2845 else
2846 {
2851 }
2854 {
2855 /* If this is the low part, we're done. */
2857 ;
2858 /* Handle the case where inner is twice the size of outer. */
2862 /* Otherwise give up for now. */
2863 else
2865 }
2868 {
2872 wide_int o
2877 combine_merges++;
2884 /* Replace the source in I2 with the new constant and make the
2885 resulting insn the new pattern for I3. Then skip to where we
2886 validate the pattern. Everything was set up above. */
2892 /* The dest of I3 has been replaced with the dest of I2. */
2895 }
2896 }
2898 /* If we have no I1 and I2 looks like:
2899 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2900 (set Y OP)])
2901 make up a dummy I1 that is
2902 (set Y OP)
2903 and change I2 to be
2904 (set (reg:CC X) (compare:CC Y (const_int 0)))
2906 (We can ignore any trailing CLOBBERs.)
2908 This undoes a previous combination and allows us to match a branch-and-
2909 decrement insn. */
2921 {
2922 /* We make I1 with the same INSN_UID as I2. This gives it
2923 the same DF_INSN_LUID for value tracking. Our fake I1 will
2924 never appear in the insn stream so giving it the same INSN_UID
2925 as I2 will not cause a problem. */
2938 }
2940 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2941 make those two SETs separate I1 and I2 insns, and make an I0 that is
2942 the original I1. */
2948 {
2949 /* If there is no I1, there is no I0 either. */
2952 /* We make I1 with the same INSN_UID as I2. This gives it
2953 the same DF_INSN_LUID for value tracking. Our fake I1 will
2954 never appear in the insn stream so giving it the same INSN_UID
2955 as I2 will not cause a problem. */
2963 }
2965 /* Verify that I2 and I1 are valid for combining. */
2971 {
2974 }
2976 /* Record whether I2DEST is used in I2SRC and similarly for the other
2977 cases. Knowing this will help in register status updating below. */
2988 /* For the earlier insns, determine which of the subsequent ones they
2989 feed. */
2996 /* Ensure that I3's pattern can be the destination of combines. */
3002 {
3005 }
3007 /* See if any of the insns is a MULT operation. Unless one is, we will
3008 reject a combination that is, since it must be slower. Be conservative
3009 here. */
3017 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3018 We used to do this EXCEPT in one case: I3 has a post-inc in an
3019 output operand. However, that exception can give rise to insns like
3020 mov r3,(r3)+
3021 which is a famous insn on the PDP-11 where the value of r3 used as the
3022 source was model-dependent. Avoid this sort of thing. */
3024 #if 0
3030 /* It's not the exception. */
3031 #endif
3033 {
3034 rtx link;
3040 {
3043 }
3044 }
3046 /* See if the SETs in I1 or I2 need to be kept around in the merged
3047 instruction: whenever the value set there is still needed past I3.
3048 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3050 For the SET in I1, we have two cases: if I1 and I2 independently feed
3051 into I3, the set in I1 needs to be kept around unless I1DEST dies
3052 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3053 in I1 needs to be kept around unless I1DEST dies or is set in either
3054 I2 or I3. The same considerations apply to I0. */
3061 else
3069 else
3072 /* We are about to copy insns for the case where they need to be kept
3073 around. Check that they can be copied in the merged instruction. */
3079 {
3082 }
3084 /* If the set in I2 needs to be kept around, we must make a copy of
3085 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3086 PATTERN (I2), we are only substituting for the original I1DEST, not into
3087 an already-substituted copy. This also prevents making self-referential
3088 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3089 I2DEST. */
3092 {
3095 else
3097 }
3100 {
3103 else
3105 }
3108 {
3111 else
3113 }
3115 combine_merges++;
3117 /* Substitute in the latest insn for the regs set by the earlier ones. */
3123 /* Many machines that don't use CC0 have insns that can both perform an
3124 arithmetic operation and set the condition code. These operations will
3125 be represented as a PARALLEL with the first element of the vector
3126 being a COMPARE of an arithmetic operation with the constant zero.
3127 The second element of the vector will set some pseudo to the result
3128 of the same arithmetic operation. If we simplify the COMPARE, we won't
3129 match such a pattern and so will generate an extra insn. Here we test
3130 for this case, where both the comparison and the operation result are
3131 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3132 I2SRC. Later we will make the PARALLEL that contains I2. */
3138 {
3139 rtx newpat_dest;
3153 {
3158 }
3160 /* Do the rest only if op1 is const0_rtx, which may be the
3161 result of simplification. */
3163 {
3164 /* If a single use of the CC is found, prepare to modify it
3165 when SELECT_CC_MODE returns a new CC-class mode, or when
3166 the above simplify_compare_const() returned a new comparison
3167 operator. undobuf.other_insn is assigned the CC use insn
3168 when modifying it. */
3170 {
3171 #ifdef SELECT_CC_MODE
3172 machine_mode new_mode
3177 {
3182 else
3183 {
3186 }
3187 }
3188 #endif
3189 /* Cases for modifying the CC-using comparison. */
3191 /* ??? Do we need to verify the zero rtx? */
3193 {
3194 /* Replace cc_use_loc with entire new RTX. */
3199 }
3201 {
3202 /* Just replace the CC reg with a new mode. */
3205 }
3206 }
3208 /* Now we modify the current newpat:
3209 First, SET_DEST(newpat) is updated if the CC mode has been
3210 altered. For targets without SELECT_CC_MODE, this should be
3211 optimized away. */
3214 /* This is always done to propagate i2src into newpat. */
3217 /* Create new version of i2pat if needed; the below PARALLEL
3218 creation needs this to work correctly. */
3222 }
3223 }
3226 {
3227 /* It is possible that the source of I2 or I1 may be performing
3228 an unneeded operation, such as a ZERO_EXTEND of something
3229 that is known to have the high part zero. Handle that case
3230 by letting subst look at the inner insns.
3232 Another way to do this would be to have a function that tries
3233 to simplify a single insn instead of merging two or more
3234 insns. We don't do this because of the potential of infinite
3235 loops and because of the potential extra memory required.
3236 However, doing it the way we are is a bit of a kludge and
3237 doesn't catch all cases.
3239 But only do this if -fexpensive-optimizations since it slows
3240 things down and doesn't usually win.
3242 This is not done in the COMPARE case above because the
3243 unmodified I2PAT is used in the PARALLEL and so a pattern
3244 with a modified I2SRC would not match. */
3247 {
3248 /* Pass pc_rtx so no substitutions are done, just
3249 simplifications. */
3251 {
3254 }
3258 }
3263 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3264 copy of I2SRC each time we substitute it, in order to avoid creating
3265 self-referential RTL when we will be substituting I1SRC for I1DEST
3266 later. Likewise if I0 feeds into I2, either directly or indirectly
3267 through I1, and I0DEST is in I0SRC. */
3274 /* Record whether I2's body now appears within I3's body. */
3276 }
3278 /* If we already got a failure, don't try to do more. Otherwise, try to
3279 substitute I1 if we have it. */
3282 {
3283 /* Check that an autoincrement side-effect on I1 has not been lost.
3284 This happens if I1DEST is mentioned in I2 and dies there, and
3285 has disappeared from the new pattern. */
3287 && i1_feeds_i2_n
3290 /* Before we can do this substitution, we must redo the test done
3291 above (see detailed comments there) that ensures I1DEST isn't
3292 mentioned in any SETs in NEWPAT that are field assignments. */
3295 {
3298 }
3303 /* If the following substitution will modify I1SRC, make a copy of it
3304 for the case where it is substituted for I1DEST in I2PAT later. */
3308 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3309 copy of I1SRC each time we substitute it, in order to avoid creating
3310 self-referential RTL when we will be substituting I0SRC for I0DEST
3311 later. */
3316 /* Record whether I1's body now appears within I3's body. */
3318 }
3320 /* Likewise for I0 if we have it. */
3323 {
3330 {
3333 }
3335 /* If the following substitution will modify I0SRC, make a copy of it
3336 for the case where it is substituted for I0DEST in I1PAT later. */
3339 /* And a copy for I0DEST in I2PAT substitution. */
3348 }
3350 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3351 to count all the ways that I2SRC and I1SRC can be used. */
3362 /* Fail if we tried to make a new register. */
3364 /* Fail if we couldn't do something and have a CLOBBER. */
3366 /* Fail if this new pattern is a MULT and we didn't have one before
3367 at the outer level. */
3370 {
3373 }
3375 /* If the actions of the earlier insns must be kept
3376 in addition to substituting them into the latest one,
3377 we must make a new PARALLEL for the latest insn
3378 to hold additional the SETs. */
3381 {
3383 combine_extras++;
3386 {
3392 }
3393 else
3394 {
3399 }
3405 {
3411 }
3413 {
3422 }
3423 }
3425 validate_replacement:
3427 /* Note which hard regs this insn has as inputs. */
3430 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3431 consider splitting this pattern, we might need these clobbers. */
3434 {
3440 }
3442 /* We have recognized nothing yet. */
3445 /* See if this is a PARALLEL of two SETs where one SET's destination is
3446 a register that is unused and this isn't marked as an instruction that
3447 might trap in an EH region. In that case, we just need the other SET.
3448 We prefer this over the PARALLEL.
3450 This can occur when simplifying a divmod insn. We *must* test for this
3451 case here because the code below that splits two independent SETs doesn't
3452 handle this case correctly when it updates the register status.
3454 It's pointless doing this if we originally had two sets, one from
3455 i3, and one from i2. Combining then splitting the parallel results
3456 in the original i2 again plus an invalid insn (which we delete).
3457 The net effect is only to move instructions around, which makes
3458 debug info less accurate. */
3463 {
3474 {
3477 }
3486 {
3492 }
3496 }
3498 /* Is the result of combination a valid instruction? */
3502 /* If we were combining three insns and the result is a simple SET
3503 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3504 insns. There are two ways to do this. It can be split using a
3505 machine-specific method (like when you have an addition of a large
3506 constant) or by combine in the function find_split_point. */
3510 {
3514 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3515 use I2DEST as a scratch register will help. In the latter case,
3516 convert I2DEST to the mode of the source of NEWPAT if we can. */
3520 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3521 inputs of NEWPAT. */
3523 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3524 possible to try that as a scratch reg. This would require adding
3525 more code to make it work though. */
3528 {
3531 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3532 (temporarily, until we are committed to this instruction
3533 combination) does not work: for example, any call to nonzero_bits
3534 on the register (from a splitter in the MD file, for example)
3535 will get the old information, which is invalid.
3537 Since nowadays we can create registers during combine just fine,
3538 we should just create a new one here, not reuse i2dest. */
3540 /* First try to split using the original register as a
3541 scratch register. */
3545 i2dest)));
3548 /* If that didn't work, try changing the mode of I2DEST if
3549 we can. */
3554 {
3556 rtx ni2dest;
3560 else
3561 {
3564 }
3566 parallel = (gen_rtx_PARALLEL
3570 ni2dest))));
3575 {
3583 }
3584 }
3587 }
3589 /* If recog_for_combine has discarded clobbers, try to use them
3590 again for the split. */
3592 {
3595 }
3598 {
3603 }
3607 {
3617 /* If I2 or I3 has multiple SETs, we won't know how to track
3618 register status, so don't use these insns. If I2's destination
3619 is used between I2 and I3, we also can't use these insns. */
3629 /* It is possible that both insns now set the destination of I3.
3630 If so, we must show an extra use of it. */
3633 {
3652 }
3653 }
3655 /* If we can split it and use I2DEST, go ahead and see if that
3656 helps things be recognized. Verify that none of the registers
3657 are set between I2 and I3. */
3661 /* We need I2DEST in the proper mode. If it is a hard register
3662 or the only use of a pseudo, we can change its mode.
3663 Make sure we don't change a hard register to have a mode that
3664 isn't valid for it, or change the number of registers. */
3671 /* We can't overwrite I2DEST if its value is still used by
3672 NEWPAT. */
3674 {
3683 /* *SPLIT may be part of I2SRC, so make sure we have the
3684 original expression around for later debug processing.
3685 We should not need I2SRC any more in other cases. */
3688 else
3691 /* Get NEWDEST as a register in the proper mode. We have already
3692 validated that we can do this. */
3694 {
3697 else
3698 {
3701 }
3702 }
3704 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3705 an ASHIFT. This can occur if it was inside a PLUS and hence
3706 appeared to be a memory address. This is a kludge. */
3711 {
3714 /* Update split_code because we may not have a multiply
3715 anymore. */
3717 }
3719 /* Similarly for (plus (mult FOO (const_int pow2))). */
3725 {
3729 /* Update split_code because we may not have a multiply
3730 anymore. */
3732 }
3734 #ifdef INSN_SCHEDULING
3735 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3736 be written as a ZERO_EXTEND. */
3738 {
3739 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3740 what it really is. */
3745 else
3748 }
3749 #endif
3751 /* Attempt to split binary operators using arithmetic identities. */
3755 {
3762 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3764 {
3769 }
3770 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3777 {
3783 /* Split both "((X op Y) op X) op Y" and
3784 "((X op Y) op Y) op X" as "T op T" where T is
3785 "X op Y". */
3788 {
3793 }
3794 /* Split "((X op X) op Y) op Y)" as "T op T" where
3795 T is "X op Y". */
3797 {
3803 }
3804 }
3805 }
3808 {
3811 }
3815 /* recog_for_combine might have added CLOBBERs to newi2pat.
3816 Make sure NEWPAT does not depend on the clobbered regs. */
3820 {
3823 {
3826 }
3827 }
3829 /* If the split point was a MULT and we didn't have one before,
3830 don't use one now. */
3833 }
3834 }
3836 /* Check for a case where we loaded from memory in a narrow mode and
3837 then sign extended it, but we need both registers. In that case,
3838 we have a PARALLEL with both loads from the same memory location.
3839 We can split this into a load from memory followed by a register-register
3840 copy. This saves at least one insn, more if register allocation can
3841 eliminate the copy.
3843 We cannot do this if the destination of the first assignment is a
3844 condition code register or cc0. We eliminate this case by making sure
3845 the SET_DEST and SET_SRC have the same mode.
3847 We cannot do this if the destination of the second assignment is
3848 a register that we have already assumed is zero-extended. Similarly
3849 for a SUBREG of such a register. */
3884 {
3885 rtx ni2dest;
3899 }
3901 /* Similarly, check for a case where we have a PARALLEL of two independent
3902 SETs but we started with three insns. In this case, we can do the sets
3903 as two separate insns. This case occurs when some SET allows two
3904 other insns to combine, but the destination of that SET is still live.
3906 Also do this if we started with two insns and (at least) one of the
3907 resulting sets is a noop; this noop will be deleted later. */
3926 {
3930 /* Normally, it doesn't matter which of the two is done first,
3931 but the one that references cc0 can't be the second, and
3932 one which uses any regs/memory set in between i2 and i3 can't
3933 be first. The PARALLEL might also have been pre-existing in i3,
3934 so we need to make sure that we won't wrongly hoist a SET to i2
3935 that would conflict with a death note present in there. */
3943 /* If I3 is a jump, ensure that set0 is a jump so that
3944 we do not create invalid RTL. */
3946 )
3947 {
3950 }
3958 /* If I3 is a jump, ensure that set1 is a jump so that
3959 we do not create invalid RTL. */
3961 )
3962 {
3965 }
3966 else
3967 {
3970 }
3975 {
3976 /* recog_for_combine might have added CLOBBERs to newi2pat.
3977 Make sure NEWPAT does not depend on the clobbered regs. */
3979 {
3982 {
3985 {
3988 }
3989 }
3990 }
3993 }
3994 }
3996 /* If it still isn't recognized, fail and change things back the way they
3997 were. */
3999 /* Is the result a reasonable ASM_OPERANDS? */
4001 {
4004 }
4006 /* If we had to change another insn, make sure it is valid also. */
4008 {
4016 {
4019 }
4020 }
4022 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4023 they are adjacent to each other or not. */
4025 {
4029 {
4032 }
4033 }
4035 /* Only allow this combination if insn_rtx_costs reports that the
4036 replacement instructions are cheaper than the originals. */
4038 {
4041 }
4044 {
4049 {
4054 /* Temporarily revert mode back. */
4058 {
4059 /* If we used i2dest as a scratch register with a
4060 different mode, substitute it for the original
4061 i2src while its original mode is temporarily
4062 restored, and then clear i2scratch so that we don't
4063 do it again later. */
4065 this_basic_block);
4067 /* Put back the new mode. */
4069 }
4070 else
4071 {
4076 {
4079 }
4080 else
4081 {
4088 }
4090 /* We're dealing with a reg that changed mode but not
4091 meaning, so we want to turn it into a subreg for
4092 the new mode. However, because of REG sharing and
4093 because its mode had already changed, we have to do
4094 it in two steps. First, replace any debug uses of
4095 reg, with its original mode temporarily restored,
4096 with this copy we have created; then, replace the
4097 copy with the SUBREG of the original shared reg,
4098 once again changed to the new mode. */
4100 this_basic_block);
4104 this_basic_block);
4105 }
4106 }
4107 }
4109 /* If we will be able to accept this, we have made a
4110 change to the destination of I3. This requires us to
4111 do a few adjustments. */
4114 {
4117 }
4119 /* We now know that we can do this combination. Merge the insns and
4120 update the status of registers and LOG_LINKS. */
4123 {
4128 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4129 ensure that they are still valid. Then add any non-duplicate
4130 notes added by recog_for_combine. */
4132 {
4142 }
4146 NULL_RTX);
4147 }
4150 {
4153 rtx ni2dest;
4155 /* I3 now uses what used to be its destination and which is now
4156 I2's destination. This requires us to do a few adjustments. */
4160 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4161 so we still will.
4163 However, some later insn might be using I2's dest and have
4164 a LOG_LINK pointing at I3. We must remove this link.
4165 The simplest way to remove the link is to point it at I1,
4166 which we know will be a NOTE. */
4168 /* newi2pat is usually a SET here; however, recog_for_combine might
4169 have added some clobbers. */
4172 else
4179 {
4181 {
4187 }
4188 }
4189 }
4191 {
4196 /* Compute which registers we expect to eliminate. newi2pat may be setting
4197 either i3dest or i2dest, so we must check it. */
4200 || !i2dest_killed
4202 /* For i1, we need to compute both local elimination and global
4203 elimination information with respect to newi2pat because i1dest
4204 may be the same as i3dest, in which case newi2pat may be setting
4205 i1dest. Global information is used when distributing REG_DEAD
4206 note for i2 and i3, in which case it does matter if newi2pat sets
4207 i1dest or not.
4209 Local information is used when distributing REG_DEAD note for i1,
4210 in which case it doesn't matter if newi2pat sets i1dest or not.
4211 See PR62151, if we have four insns combination:
4212 i0: r0 <- i0src
4213 i1: r1 <- i1src (using r0)
4214 REG_DEAD (r0)
4215 i2: r0 <- i2src (using r1)
4216 i3: r3 <- i3src (using r0)
4217 ix: using r0
4218 From i1's point of view, r0 is eliminated, no matter if it is set
4219 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4220 should be discarded.
4222 Note local information only affects cases in forms like "I1->I2->I3",
4223 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4224 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4225 i0dest anyway. */
4227 || !i1dest_killed
4232 /* Same case as i1. */
4239 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4240 clear them. */
4248 /* Ensure that we do not have something that should not be shared but
4249 occurs multiple times in the new insns. Check this by first
4250 resetting all the `used' flags and then copying anything is shared. */
4274 {
4281 {
4282 /* I2SRC must still be meaningful at this point. Some splitting
4283 operations can invalidate I2SRC, but those operations do not
4284 apply to calls. */
4287 }
4295 }
4300 /* We had one special case above where I2 had more than one set and
4301 we replaced a destination of one of those sets with the destination
4302 of I3. In that case, we have to update LOG_LINKS of insns later
4303 in this basic block. Note that this (expensive) case is rare.
4305 Also, in this case, we must pretend that all REG_NOTEs for I2
4306 actually came from I3, so that REG_UNUSED notes from I2 will be
4307 properly handled. */
4310 {
4319 temp_insn
4329 {
4334 }
4335 else
4338 }
4346 {
4349 this_basic_block);
4352 }
4353 else
4354 {
4357 this_basic_block);
4359 }
4362 {
4367 this_basic_block);
4369 }
4372 {
4377 this_basic_block);
4379 }
4381 /* Get death notes for everything that is now used in either I3 or
4382 I2 and used to die in a previous insn. If we built two new
4383 patterns, move from I1 to I2 then I2 to I3 so that we get the
4384 proper movement on registers that I2 modifies. */
4390 else
4396 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4413 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4414 know these are REG_UNUSED and want them to go to the desired insn,
4415 so we always pass it as i3. */
4419 NULL_RTX);
4423 NULL_RTX);
4425 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4426 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4427 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4428 in that case, it might delete I2. Similarly for I2 and I1.
4429 Show an additional death due to the REG_DEAD note we make here. If
4430 we discard it in distribute_notes, we will decrement it again. */
4433 {
4438 else
4441 }
4444 {
4449 else
4452 }
4455 {
4460 else
4463 }
4466 {
4471 else
4474 }
4482 {
4487 /* The insn that used to set this register doesn't exist, and
4488 this life of the register may not exist either. See if one of
4489 I3's links points to an insn that sets I2DEST. If it does,
4490 that is now the last known value for I2DEST. If we don't update
4491 this and I2 set the register to a value that depended on its old
4492 contents, we will get confused. If this insn is used, thing
4493 will be set correctly in combine_instructions. */
4501 /* If the reg formerly set in I2 died only once and that was in I3,
4502 zero its use count so it won't make `reload' do any work. */
4505 && ! i2dest_in_i2src
4508 }
4511 {
4524 && ! i1dest_in_i1src
4527 }
4530 {
4543 && ! i0dest_in_i0src
4546 }
4548 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4549 been made to this insn. The order is important, because newi2pat
4550 can affect nonzero_bits of newpat. */
4554 }
4557 {
4559 {
4562 }
4564 }
4567 {
4569 {
4572 }
4574 }
4577 {
4579 {
4582 }
4584 }
4587 {
4589 {
4592 }
4594 }
4597 {
4599 {
4602 }
4604 }
4606 /* Set new_direct_jump_p if a new return or simple jump instruction
4607 has been created. Adjust the CFG accordingly. */
4609 {
4613 }
4618 {
4621 }
4623 /* A noop might also need cleaning up of CFG, if it comes from the
4624 simplification of a jump. */
4629 {
4632 }
4639 {
4642 }
4644 combine_successes++;
4651 else
4653 }
4654 \f
4655 /* Get a marker for undoing to the current state. */
4659 {
4661 }
4663 /* Undo the modifications up to the marker. */
4665 static void
4667 {
4671 {
4676 {
4691 }
4695 }
4698 }
4700 /* Undo all the modifications recorded in undobuf. */
4702 static void
4704 {
4706 }
4708 /* We've committed to accepting the changes we made. Move all
4709 of the undos to the free list. */
4711 static void
4713 {
4717 {
4721 }
4723 }
4724 \f
4725 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4726 where we have an arithmetic expression and return that point. LOC will
4727 be inside INSN.
4729 try_combine will call this function to see if an insn can be split into
4730 two insns. */
4734 {
4743 /* First special-case some codes. */
4745 {
4747 #ifdef INSN_SCHEDULING
4748 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4749 point. */
4752 #endif
4756 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4757 using LO_SUM and HIGH. */
4760 {
4768 }
4770 /* If we have a PLUS whose second operand is a constant and the
4771 address is not valid, perhaps will can split it up using
4772 the machine-specific way to split large constants. We use
4773 the first pseudo-reg (one of the virtual regs) as a placeholder;
4774 it will not remain in the result. */
4779 {
4782 subst_insn);
4784 /* This should have produced two insns, each of which sets our
4785 placeholder. If the source of the second is a valid address,
4786 we can make put both sources together and make a split point
4787 in the middle. */
4800 && memory_address_addr_space_p
4803 {
4807 /* Replace the placeholder in SRC2 with SRC1. If we can
4808 find where in SRC2 it was placed, that can become our
4809 split point and we can replace this address with SRC2.
4810 Just try two obvious places. */
4821 {
4824 }
4825 }
4827 /* If that didn't work, perhaps the first operand is complex and
4828 needs to be computed separately, so make a split point there.
4829 This will occur on machines that just support REG + CONST
4830 and have a constant moved through some previous computation. */
4836 }
4838 /* If we have a PLUS whose first operand is complex, try computing it
4839 separately by making a split there. */
4850 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4851 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4852 we need to put the operand into a register. So split at that
4853 point. */
4863 /* See if we can split SET_SRC as it stands. */
4868 /* See if we can split SET_DEST as it stands. */
4873 /* See if this is a bitfield assignment with everything constant. If
4874 so, this is an IOR of an AND, so split it into that. */
4884 {
4890 unsigned HOST_WIDE_INT mask
4892 rtx or_mask;
4901 else
4902 {
4908 or_mask));
4909 }
4916 }
4918 /* Otherwise, see if this is an operation that we can split into two.
4919 If so, try to split that. */
4923 {
4925 /* If we are AND'ing with a large constant that is only a single
4926 bit and the result is only being used in a context where we
4927 need to know if it is zero or nonzero, replace it with a bit
4928 extraction. This will avoid the large constant, which might
4929 have taken more than one insn to make. If the constant were
4930 not a valid argument to the AND but took only one insn to make,
4931 this is no worse, but if it took more than one insn, it will
4932 be better. */
4942 {
4947 {
4950 }
4951 }
4955 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4956 is known to be on, this can be converted into a NEG of a shift. */
4962 {
4974 }
4980 /* We can't optimize if either mode is a partial integer
4981 mode as we don't know how many bits are significant
4982 in those modes. */
4996 {
5004 }
5009 }
5013 {
5016 /* For unsigned, we have a choice of a shift followed by an
5017 AND or two shifts. Use two shifts for field sizes where the
5018 constant might be too large. We assume here that we can
5019 always at least get 8-bit constants in an AND insn, which is
5020 true for every current RISC. */
5023 {
5024 unsigned HOST_WIDE_INT mask
5028 gen_rtx_LSHIFTRT
5036 }
5037 else
5038 {
5040 gen_rtx_fmt_ee
5051 }
5052 }
5054 /* See if this is a simple operation with a constant as the second
5055 operand. It might be that this constant is out of range and hence
5056 could be used as a split point. */
5064 /* Finally, see if this is a simple operation with its first operand
5065 not in a register. The operation might require this operand in a
5066 register, so return it as a split point. We can always do this
5067 because if the first operand were another operation, we would have
5068 already found it as a split point. */
5077 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5078 it is better to write this as (not (ior A B)) so we can split it.
5079 Similarly for IOR. */
5081 {
5089 }
5091 /* Many RISC machines have a large set of logical insns. If the
5092 second operand is a NOT, put it first so we will try to split the
5093 other operand first. */
5095 {
5099 }
5104 /* Canonicalization can produce (minus A (mult B C)), where C is a
5105 constant. It may be better to try splitting (plus (mult B -C) A)
5106 instead if this isn't a multiply by a power of two. */
5110 {
5118 mode)),
5121 }
5123 /* Split at a multiply-accumulate instruction. However if this is
5124 the SET_SRC, we likely do not have such an instruction and it's
5125 worthless to try this split. */
5134 }
5136 /* Otherwise, select our actions depending on our rtx class. */
5138 {
5144 /* fall through */
5152 /* fall through */
5154 /* Some machines have (and (shift ...) ...) insns. If X is not
5155 an AND, but XEXP (X, 0) is, use it as our split point. */
5165 /* Otherwise, we don't have a split point. */
5167 }
5168 }
5169 \f
5170 /* Throughout X, replace FROM with TO, and return the result.
5171 The result is TO if X is FROM;
5172 otherwise the result is X, but its contents may have been modified.
5173 If they were modified, a record was made in undobuf so that
5174 undo_all will (among other things) return X to its original state.
5176 If the number of changes necessary is too much to record to undo,
5177 the excess changes are not made, so the result is invalid.
5178 The changes already made can still be undone.
5179 undobuf.num_undo is incremented for such changes, so by testing that
5180 the caller can tell whether the result is valid.
5182 `n_occurrences' is incremented each time FROM is replaced.
5184 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5186 IN_COND is nonzero if we are at the top level of a condition.
5188 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5189 by copying if `n_occurrences' is nonzero. */
5191 static rtx
5193 {
5198 rtx new_rtx;
5200 /* Two expressions are equal if they are identical copies of a shared
5201 RTX or if they are both registers with the same register number
5202 and mode. */
5204 #define COMBINE_RTX_EQUAL_P(X,Y) \
5205 ((X) == (Y) \
5206 || (REG_P (X) && REG_P (Y) \
5207 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5209 /* Do not substitute into clobbers of regs -- this will never result in
5210 valid RTL. */
5215 {
5216 n_occurrences++;
5218 }
5220 /* If X and FROM are the same register but different modes, they
5221 will not have been seen as equal above. However, the log links code
5222 will make a LOG_LINKS entry for that case. If we do nothing, we
5223 will try to rerecognize our original insn and, when it succeeds,
5224 we will delete the feeding insn, which is incorrect.
5226 So force this insn not to match in this (rare) case. */
5231 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5232 of which may contain things that can be combined. */
5236 /* It is possible to have a subexpression appear twice in the insn.
5237 Suppose that FROM is a register that appears within TO.
5238 Then, after that subexpression has been scanned once by `subst',
5239 the second time it is scanned, TO may be found. If we were
5240 to scan TO here, we would find FROM within it and create a
5241 self-referent rtl structure which is completely wrong. */
5245 /* Parallel asm_operands need special attention because all of the
5246 inputs are shared across the arms. Furthermore, unsharing the
5247 rtl results in recognition failures. Failure to handle this case
5248 specially can result in circular rtl.
5250 Solve this by doing a normal pass across the first entry of the
5251 parallel, and only processing the SET_DESTs of the subsequent
5252 entries. Ug. */
5257 {
5260 /* If this substitution failed, this whole thing fails. */
5268 {
5274 {
5277 /* If this substitution failed, this whole thing fails. */
5283 }
5284 }
5285 }
5286 else
5287 {
5291 /* We don't need to process a SET_DEST that is a register, CC0,
5292 or PC, so set up to skip this common case. All other cases
5293 where we want to suppress replacing something inside a
5294 SET_SRC are handled via the IN_DEST operand. */
5301 /* Trying to simplify the operands of a widening MULT is not likely
5302 to create RTL matching a machine insn. */
5314 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5315 constant. */
5320 {
5322 {
5325 {
5327 {
5330 n_occurrences++;
5331 }
5332 else
5333 {
5335 unique_copy);
5337 /* If this substitution failed, this whole thing
5338 fails. */
5342 }
5345 }
5346 }
5348 {
5349 /* If this is a register being set, ignore it. */
5356 ;
5359 {
5360 /* In general, don't install a subreg involving two
5361 modes not tieable. It can worsen register
5362 allocation, and can even make invalid reload
5363 insns, since the reg inside may need to be copied
5364 from in the outside mode, and that may be invalid
5365 if it is an fp reg copied in integer mode.
5367 We allow two exceptions to this: It is valid if
5368 it is inside another SUBREG and the mode of that
5369 SUBREG and the mode of the inside of TO is
5370 tieable and it is valid if X is a SET that copies
5371 FROM to CC0. */
5379 && (!HAVE_cc0
5394 n_occurrences++;
5395 }
5396 else
5397 /* If we are in a SET_DEST, suppress most cases unless we
5398 have gone inside a MEM, in which case we want to
5399 simplify the address. We assume here that things that
5400 are actually part of the destination have their inner
5401 parts in the first expression. This is true for SUBREG,
5402 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5403 things aside from REG and MEM that should appear in a
5404 SET_DEST. */
5406 (((in_dest
5412 unique_copy);
5414 /* If we found that we will have to reject this combination,
5415 indicate that by returning the CLOBBER ourselves, rather than
5416 an expression containing it. This will speed things up as
5417 well as prevent accidents where two CLOBBERs are considered
5418 to be equal, thus producing an incorrect simplification. */
5424 {
5432 }
5435 {
5439 }
5440 else
5442 }
5443 }
5444 }
5446 /* Check if we are loading something from the constant pool via float
5447 extension; in this case we would undo compress_float_constant
5448 optimization and degenerate constant load to an immediate value. */
5452 {
5456 }
5458 /* Try to simplify X. If the simplification changed the code, it is likely
5459 that further simplification will help, so loop, but limit the number
5460 of repetitions that will be performed. */
5463 {
5464 /* If X is sufficiently simple, don't bother trying to do anything
5465 with it. */
5474 /* We no longer know the original mode of operand 0 since we
5475 have changed the form of X) */
5477 }
5480 }
5481 \f
5482 /* Simplify X, a piece of RTL. We just operate on the expression at the
5483 outer level; call `subst' to simplify recursively. Return the new
5484 expression.
5486 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5487 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5488 of a condition. */
5490 static rtx
5493 {
5496 rtx temp;
5499 /* If this is a commutative operation, put a constant last and a complex
5500 expression first. We don't need to do this for comparisons here. */
5503 {
5507 }
5509 /* Try to fold this expression in case we have constants that weren't
5510 present before. */
5513 {
5521 {
5524 {
5528 }
5531 }
5544 }
5547 {
5552 }
5554 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5555 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5556 things. Check for cases where both arms are testing the same
5557 condition.
5559 Don't do anything if all operands are very simple. */
5572 {
5577 /* If everything is a comparison, what we have is highly unlikely
5578 to be simpler, so don't use it. */
5581 {
5588 /* Simplify the alternative arms; this may collapse the true and
5589 false arms to store-flag values. Be careful to use copy_rtx
5590 here since true_rtx or false_rtx might share RTL with x as a
5591 result of the if_then_else_cond call above. */
5595 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5596 is unlikely to be simpler. */
5599 {
5602 /* Restarting if we generate a store-flag expression will cause
5603 us to loop. Just drop through in this case. */
5605 /* If the result values are STORE_FLAG_VALUE and zero, we can
5606 just make the comparison operation. */
5617 /* Likewise, we can make the negate of a comparison operation
5618 if the result values are - STORE_FLAG_VALUE and zero. */
5626 mode);
5637 mode);
5638 else
5641 mode,
5642 VOIDmode,
5643 cond,
5644 cop1),
5649 }
5650 }
5651 }
5653 /* First see if we can apply the inverse distributive law. */
5656 {
5660 }
5662 /* If CODE is an associative operation not otherwise handled, see if we
5663 can associate some operands. This can win if they are constants or
5664 if they are logically related (i.e. (a & b) & a). */
5670 {
5672 {
5676 rtx inner;
5678 /* Make sure we pass the constant operand if any as the second
5679 one if this is a commutative operation. */
5687 /* For commutative operations, try the other pair if that one
5688 didn't simplify. */
5690 {
5695 }
5699 }
5700 }
5702 /* A little bit of algebraic simplification here. */
5704 {
5706 /* Ensure that our address has any ASHIFTs converted to MULT in case
5707 address-recognizing predicates are called later. */
5716 /* See if this can be moved to simplify_subreg. */
5719 /* Don't call gen_lowpart if the inner mode
5720 is VOIDmode and we cannot simplify it, as SUBREG without
5721 inner mode is invalid. */
5728 {
5729 rtx temp;
5735 /* If op is known to have all lower bits zero, the result is zero. */
5745 }
5747 /* Don't change the mode of the MEM if that would change the meaning
5748 of the address. */
5755 /* Note that we cannot do any narrowing for non-constants since
5756 we might have been counting on using the fact that some bits were
5757 zero. We now do this in the SET. */
5764 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5765 replaced by (lshiftrt X C). This will convert
5766 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5774 /* If X has only a single bit that might be nonzero, say, bit I, convert
5775 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5776 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5777 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5778 or a SUBREG of one since we'd be making the expression more
5779 complex if it was just a register. */
5785 {
5786 rtx temp1 = simplify_shift_const
5792 /* If all we did was surround TEMP with the two shifts, we
5793 haven't improved anything, so don't use it. Otherwise,
5794 we are better off with TEMP1. */
5799 }
5803 /* We can't handle truncation to a partial integer mode here
5804 because we don't know the real bitsize of the partial
5805 integer mode. */
5814 /* We can truncate a constant value and return it. */
5818 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5819 whose value is a comparison can be replaced with a subreg if
5820 STORE_FLAG_VALUE permits. */
5829 /* (const (const X)) can become (const X). Do it this way rather than
5830 returning the inner CONST since CONST can be shared with a
5831 REG_EQUAL note. */
5837 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5838 can add in an offset. find_split_point will split this address up
5839 again if it doesn't match. */
5846 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5847 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5848 bit-field and can be replaced by either a sign_extend or a
5849 sign_extract. The `and' may be a zero_extend and the two
5850 <c>, -<c> constants may be reversed. */
5865 return simplify_shift_const
5872 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5873 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5874 the bitsize of the mode - 1. This allows simplification of
5875 "a = (b & 8) == 0;" */
5887 /* If we are adding two things that have no bits in common, convert
5888 the addition into an IOR. This will often be further simplified,
5889 for example in cases like ((a & 1) + (a & 2)), which can
5890 become a & 3. */
5895 {
5896 /* Try to simplify the expression further. */
5900 /* If we could, great. If not, do not go ahead with the IOR
5901 replacement, since PLUS appears in many special purpose
5902 address arithmetic instructions. */
5910 }
5912 /* Canonicalize x + x into x << 1. */
5921 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5922 (and <foo> (const_int pow2-1)) */
5932 /* If we have (mult (plus A B) C), apply the distributive law and then
5933 the inverse distributive law to see if things simplify. This
5934 occurs mostly in addresses, often when unrolling loops. */
5937 {
5941 }
5943 /* Try simplify a*(b/c) as (a*b)/c. */
5946 {
5952 }
5956 /* If this is a divide by a power of two, treat it as a shift if
5957 its first operand is a shift. */
5975 /* If the first operand is a condition code, we can't do anything
5976 with it. */
5980 {
5988 /* Simplify our comparison, if possible. */
5991 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5992 if only the low-order bit is possibly nonzero in X (such as when
5993 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5994 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5995 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5996 (plus X 1).
5998 Remove any ZERO_EXTRACT we made when thinking this was a
5999 comparison. It may now be simpler to use, e.g., an AND. If a
6000 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6001 the call to make_compound_operation in the SET case.
6003 Don't apply these optimizations if the caller would
6004 prefer a comparison rather than a value.
6005 E.g., for the condition in an IF_THEN_ELSE most targets need
6006 an explicit comparison. */
6009 ;
6025 {
6029 mode);
6030 }
6037 {
6041 const1_rtx);
6042 }
6050 {
6053 }
6055 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6056 those above. */
6058 ;
6074 {
6078 mode);
6079 }
6087 {
6091 mode);
6092 }
6094 /* If X is 0/1, (eq X 0) is X-1. */
6100 {
6103 }
6105 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6106 one bit that might be nonzero, we can convert (ne x 0) to
6107 (ashift x c) where C puts the bit in the sign bit. Remove any
6108 AND with STORE_FLAG_VALUE when we are done, since we are only
6109 going to test the sign bit. */
6116 {
6122 else
6124 }
6126 /* If the code changed, return a whole new comparison.
6127 We also need to avoid using SUBST in cases where
6128 simplify_comparison has widened a comparison with a CONST_INT,
6129 since in that case the wider CONST_INT may fail the sanity
6130 checks in do_SUBST. */
6137 /* Otherwise, keep this operation, but maybe change its operands.
6138 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6141 }
6151 /* If we are processing SET_DEST, we are done. */
6169 /* If this is a shift by a constant amount, simplify it. */
6177 (HOST_WIDE_INT_1U
6185 }
6188 }
6189 \f
6190 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6192 static rtx
6194 {
6201 rtx temp;
6204 rtx reversed;
6206 /* Simplify storing of the truth value. */
6211 /* Also when the truth value has to be reversed. */
6217 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6218 in it is being compared against certain values. Get the true and false
6219 comparisons and see if that says anything about the value of each arm. */
6225 {
6226 HOST_WIDE_INT nzb;
6232 /* If FALSE_CODE is EQ, swap the codes and arms. */
6235 {
6238 }
6240 /* If we are comparing against zero and the expression being tested has
6241 only a single bit that might be nonzero, that is its value when it is
6242 not equal to zero. Similarly if it is known to be -1 or 0. */
6246 {
6249 }
6253 {
6256 }
6258 /* Now simplify an arm if we know the value of the register in the
6259 branch and it is used in the arm. Be careful due to the potential
6260 of locally-shared RTL. */
6277 }
6279 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6280 reversed, do so to avoid needing two sets of patterns for
6281 subtract-and-branch insns. Similarly if we have a constant in the true
6282 arm, the false arm is the same as the first operand of the comparison, or
6283 the false arm is more complicated than the true arm. */
6296 {
6305 /* It is possible that the conditional has been simplified out. */
6308 }
6310 /* If the two arms are identical, we don't need the comparison. */
6315 /* Convert a == b ? b : a to "a". */
6327 /* Look for cases where we have (abs x) or (neg (abs X)). */
6330 && comparison_p
6337 {
6343 return
6346 mode);
6349 }
6351 /* Look for MIN or MAX. */
6354 && comparison_p
6359 {
6374 }
6376 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6377 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6378 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6379 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6380 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6381 neither 1 or -1, but it isn't worth checking for. */
6384 && comparison_p
6387 {
6403 /* If an identity-zero op is commutative, check whether there
6404 would be a match if we swapped the operands. */
6424 {
6428 }
6440 {
6444 }
6460 {
6464 }
6476 {
6480 }
6483 {
6489 const_true_rtx));
6497 }
6498 }
6500 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6501 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6502 negation of a single bit, we can convert this operation to a shift. We
6503 can actually do this more generally, but it doesn't seem worth it. */
6512 return
6516 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6526 }
6527 \f
6528 /* Simplify X, a SET expression. Return the new expression. */
6530 static rtx
6532 {
6535 machine_mode mode
6540 /* (set (pc) (return)) gets written as (return). */
6544 /* Now that we know for sure which bits of SRC we are using, see if we can
6545 simplify the expression for the object knowing that we only need the
6546 low-order bits. */
6549 {
6552 }
6554 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6555 the comparison result and try to simplify it unless we already have used
6556 undobuf.other_insn. */
6564 {
6573 {
6576 {
6579 }
6580 }
6581 else
6589 {
6593 }
6594 else
6595 {
6600 /* Attempt to simplify CC user. */
6602 {
6606 }
6608 /* Convert X into a no-op move. */
6612 }
6614 /* Simplify our comparison, if possible. */
6617 #ifdef SELECT_CC_MODE
6618 /* If this machine has CC modes other than CCmode, check to see if we
6619 need to use a different CC mode here. */
6628 else
6631 /* If the mode changed, we have to change SET_DEST, the mode in the
6632 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6633 a hard register, just build new versions with the proper mode. If it
6634 is a pseudo, we lose unless it is only time we set the pseudo, in
6635 which case we can safely change its mode. */
6637 {
6639 {
6641 rtx new_dest;
6645 else
6646 {
6649 }
6656 }
6657 }
6660 /* If the code changed, we have to build a new comparison in
6661 undobuf.other_insn. */
6663 {
6672 /* If the only change we made was to change an EQ into an NE or
6673 vice versa, OP0 has only one bit that might be nonzero, and OP1
6674 is zero, check if changing the user of the condition code will
6675 produce a valid insn. If it won't, we can keep the original code
6676 in that insn by surrounding our operation with an XOR. */
6683 {
6688 {
6695 }
6696 }
6697 }
6702 /* Don't generate a compare of a CC with 0, just use that CC. */
6704 {
6707 }
6708 /* Otherwise, if we didn't previously have the same COMPARE we
6709 want, create it from scratch. */
6712 {
6715 }
6716 }
6717 else
6718 {
6719 /* Get SET_SRC in a form where we have placed back any
6720 compound expressions. Then do the checks below. */
6723 }
6725 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6726 and X being a REG or (subreg (reg)), we may be able to convert this to
6727 (set (subreg:m2 x) (op)).
6729 We can always do this if M1 is narrower than M2 because that means that
6730 we only care about the low bits of the result.
6732 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6733 perform a narrower operation than requested since the high-order bits will
6734 be undefined. On machine where it is defined, this transformation is safe
6735 as long as M1 and M2 have the same number of words. */
6743 && (WORD_REGISTER_OPERATIONS
6746 #ifdef CANNOT_CHANGE_MODE_CLASS
6751 #endif
6755 {
6758 dest));
6762 }
6764 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6765 in SRC. */
6771 {
6775 /* Here we make sure that we don't have a sign bit on. */
6778 {
6781 }
6782 }
6784 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6785 would require a paradoxical subreg. Replace the subreg with a
6786 zero_extend to avoid the reload that would otherwise be required. */
6794 {
6800 }
6802 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6803 are comparing an item known to be 0 or -1 against 0, use a logical
6804 operation instead. Check for one of the arms being an IOR of the other
6805 arm with some value. We compute three terms to be IOR'ed together. In
6806 practice, at most two will be nonzero. Then we do the IOR's. */
6814 && (!HAVE_conditional_move
6820 {
6846 false_rtx);
6852 term3));
6855 }
6857 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6858 whole thing fail. */
6863 else
6864 /* Convert this into a field assignment operation, if possible. */
6866 }
6867 \f
6868 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6869 result. */
6871 static rtx
6873 {
6879 {
6881 /* We can call simplify_and_const_int only if we don't lose
6882 any (sign) bits when converting INTVAL (op1) to
6883 "unsigned HOST_WIDE_INT". */
6887 {
6894 }
6896 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6897 apply the distributive law and then the inverse distributive
6898 law to see if things simplify. */
6900 {
6904 }
6906 {
6910 }
6914 /* If we have (ior (and A B) C), apply the distributive law and then
6915 the inverse distributive law to see if things simplify. */
6918 {
6922 }
6925 {
6929 }
6934 }
6937 }
6938 \f
6939 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6940 operations" because they can be replaced with two more basic operations.
6941 ZERO_EXTEND is also considered "compound" because it can be replaced with
6942 an AND operation, which is simpler, though only one operation.
6944 The function expand_compound_operation is called with an rtx expression
6945 and will convert it to the appropriate shifts and AND operations,
6946 simplifying at each stage.
6948 The function make_compound_operation is called to convert an expression
6949 consisting of shifts and ANDs into the equivalent compound expression.
6950 It is the inverse of this function, loosely speaking. */
6952 static rtx
6954 {
6958 rtx tem;
6961 {
6964 /* FALLTHRU */
6966 /* We can't necessarily use a const_int for a multiword mode;
6967 it depends on implicitly extending the value.
6968 Since we don't know the right way to extend it,
6969 we can't tell whether the implicit way is right.
6971 Even for a mode that is no wider than a const_int,
6972 we can't win, because we need to sign extend one of its bits through
6973 the rest of it, and we don't know which bit. */
6977 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6978 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6979 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6980 reloaded. If not for that, MEM's would very rarely be safe.
6982 Reject MODEs bigger than a word, because we might not be able
6983 to reference a two-register group starting with an arbitrary register
6984 (and currently gen_lowpart might crash for a SUBREG). */
6989 /* Reject MODEs that aren't scalar integers because turning vector
6990 or complex modes into shifts causes problems. */
6996 /* If the inner object has VOIDmode (the only way this can happen
6997 is if it is an ASM_OPERANDS), we can't do anything since we don't
6998 know how much masking to do. */
7007 /* fall through */
7010 /* If the operand is a CLOBBER, just return it. */
7019 /* Reject MODEs that aren't scalar integers because turning vector
7020 or complex modes into shifts causes problems. */
7028 /* This should stay within the object being extracted, fail otherwise. */
7039 }
7040 /* Convert sign extension to zero extension, if we know that the high
7041 bit is not set, as this is easier to optimize. It will be converted
7042 back to cheaper alternative in make_extraction. */
7050 {
7055 /* Make sure this is a profitable operation. */
7062 else
7064 }
7066 /* We can optimize some special cases of ZERO_EXTEND. */
7068 {
7069 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7070 know that the last value didn't have any inappropriate bits
7071 set. */
7079 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7088 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7089 is a comparison and STORE_FLAG_VALUE permits. This is like
7090 the first case, but it works even when GET_MODE (x) is larger
7091 than HOST_WIDE_INT. */
7100 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7110 }
7112 /* If we reach here, we want to return a pair of shifts. The inner
7113 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7114 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7115 logical depending on the value of UNSIGNEDP.
7117 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7118 converted into an AND of a shift.
7120 We must check for the case where the left shift would have a negative
7121 count. This can happen in a case like (x >> 31) & 255 on machines
7122 that can't shift by a constant. On those machines, we would first
7123 combine the shift with the AND to produce a variable-position
7124 extraction. Then the constant of 31 would be substituted in
7125 to produce such a position. */
7129 {
7138 }
7145 else
7146 /* Any other cases we can't handle. */
7149 /* If we couldn't do this for some reason, return the original
7150 expression. */
7155 }
7156 \f
7157 /* X is a SET which contains an assignment of one object into
7158 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7159 or certain SUBREGS). If possible, convert it into a series of
7160 logical operations.
7162 We half-heartedly support variable positions, but do not at all
7163 support variable lengths. */
7165 static const_rtx
7167 {
7168 rtx inner;
7172 machine_mode compute_mode;
7174 /* Loop until we find something we can't simplify. */
7176 {
7179 {
7183 }
7186 {
7191 /* A constant position should stay within the width of INNER. */
7197 {
7205 /* If position is ADJUST - X, new position is X. */
7207 else
7208 {
7213 pos);
7214 }
7215 }
7216 }
7218 /* A SUBREG between two modes that occupy the same numbers of words
7219 can be done by moving the SUBREG to the source. */
7221 /* We need SUBREGs to compute nonzero_bits properly. */
7222 && nonzero_sign_valid
7227 {
7229 gen_lowpart
7233 }
7234 else
7242 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7244 {
7245 machine_mode imode;
7247 /* Don't do anything for vector or complex integral types. */
7251 /* Try to find an integral mode to pun with. */
7258 }
7260 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7264 /* Don't try to compute in too wide unsupported modes. */
7268 /* Now compute the equivalent expression. Make a copy of INNER
7269 for the SET_DEST in case it is a MEM into which we will substitute;
7270 we don't want shared RTL in that case. */
7272 compute_mode);
7276 compute_mode,
7278 compute_mode),
7279 inner);
7284 mask),
7285 pos);
7290 }
7293 }
7294 \f
7295 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7296 it is an RTX that represents the (variable) starting position; otherwise,
7297 POS is the (constant) starting bit position. Both are counted from the LSB.
7299 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7301 IN_DEST is nonzero if this is a reference in the destination of a SET.
7302 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7303 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7304 be used.
7306 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7307 ZERO_EXTRACT should be built even for bits starting at bit 0.
7309 MODE is the desired mode of the result (if IN_DEST == 0).
7311 The result is an RTX for the extraction or NULL_RTX if the target
7312 can't handle it. */
7314 static rtx
7318 {
7319 /* This mode describes the size of the storage area
7320 to fetch the overall value from. Within that, we
7321 ignore the POS lowest bits, etc. */
7323 machine_mode inner_mode;
7324 machine_mode wanted_inner_mode;
7331 HOST_WIDE_INT orig_pos;
7337 {
7338 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7339 consider just the QI as the memory to extract from.
7340 The subreg adds or removes high bits; its mode is
7341 irrelevant to the meaning of this extraction,
7342 since POS and LEN count from the lsb. */
7346 }
7351 {
7352 /* We're extracting the least significant bits of an rtx
7353 (ashift X (const_int C)), where LEN > C. Extract the
7354 least significant (LEN - C) bits of X, giving an rtx
7355 whose mode is MODE, then shift it left C times. */
7361 }
7367 /* See if this can be done without an extraction. We never can if the
7368 width of the field is not the same as that of some integer mode. For
7369 registers, we can only avoid the extraction if the position is at the
7370 low-order bit and this is either not in the destination or we have the
7371 appropriate STRICT_LOW_PART operation available.
7373 For MEM, we can avoid an extract if the field starts on an appropriate
7374 boundary and we can change the mode of the memory reference. */
7383 && (! in_dest
7387 && (pos
7390 /* We can't do this if we are widening INNER_MODE (it
7391 may not be aligned, for one thing). */
7397 {
7398 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7399 field. If the original and current mode are the same, we need not
7400 adjust the offset. Otherwise, we do if bytes big endian.
7402 If INNER is not a MEM, get a piece consisting of just the field
7403 of interest (in this case POS % BITS_PER_WORD must be 0). */
7406 {
7407 HOST_WIDE_INT offset;
7409 /* POS counts from lsb, but make OFFSET count in memory order. */
7412 else
7416 }
7418 {
7420 {
7421 /* We can't call gen_lowpart in a DEST since we
7422 always want a SUBREG (see below) and it would sometimes
7423 return a new hard register. */
7425 {
7440 /* Avoid creating invalid subregs, for example when
7441 simplifying (x>>32)&255. */
7446 }
7447 else
7449 }
7450 else
7452 }
7453 else
7455 len >= HOST_BITS_PER_WIDE_INT
7456 ? HOST_WIDE_INT_M1U
7460 /* If this extraction is going into the destination of a SET,
7461 make a STRICT_LOW_PART unless we made a MEM. */
7476 /* If we know that no extraneous bits are set, and that the high
7477 bit is not set, convert the extraction to the cheaper of
7478 sign and zero extension, that are equivalent in these cases. */
7484 {
7488 /* Prefer ZERO_EXTENSION, since it gives more information to
7489 backends. */
7494 }
7496 /* Otherwise, sign- or zero-extend unless we already are in the
7497 proper mode. */
7501 }
7503 /* Unless this is a COMPARE or we have a funny memory reference,
7504 don't do anything with zero-extending field extracts starting at
7505 the low-order bit since they are simple AND operations. */
7510 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7511 if the position is not a constant and the length is not 1. In all
7512 other cases, we would only be going outside our object in cases when
7513 an original shift would have been undefined. */
7522 /* If INNER is not from memory, we want it to have the mode of a register
7523 extraction pattern's structure operand, or word_mode if there is no
7524 such pattern. The same applies to extraction_mode and pos_mode
7525 and their respective operands.
7527 For memory, assume that the desired extraction_mode and pos_mode
7528 are the same as for a register operation, since at present we don't
7529 have named patterns for aligned memory structures. */
7533 {
7537 }
7539 /* Never narrow an object, since that might not be safe. */
7547 else
7548 {
7549 /* Be careful not to go beyond the extracted object and maintain the
7550 natural alignment of the memory. */
7554 {
7557 }
7558 }
7563 {
7564 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7565 BITS_BIG_ENDIAN style. If position is constant, compute new
7566 position. Otherwise, build subtraction.
7567 Note that POS is relative to the mode of the original argument.
7568 If it's a MEM we need to recompute POS relative to that.
7569 However, if we're extracting from (or inserting into) a register,
7570 we want to recompute POS relative to wanted_inner_mode. */
7577 else
7578 pos_rtx
7581 pos_rtx);
7582 /* POS may be less than 0 now, but we check for that below.
7583 Note that it can only be less than 0 if !MEM_P (inner). */
7584 }
7586 /* If INNER has a wider mode, and this is a constant extraction, try to
7587 make it smaller and adjust the byte to point to the byte containing
7588 the value. */
7591 && ! pos_rtx
7596 {
7599 /* The computations below will be correct if the machine is big
7600 endian in both bits and bytes or little endian in bits and bytes.
7601 If it is mixed, we must adjust. */
7603 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7604 adjust OFFSET to compensate. */
7609 /* We can now move to the desired byte. */
7620 }
7622 /* If INNER is not memory, get it into the proper mode. If we are changing
7623 its mode, POS must be a constant and smaller than the size of the new
7624 mode. */
7626 {
7627 /* On the LHS, don't create paradoxical subregs implicitely truncating
7628 the register unless TRULY_NOOP_TRUNCATION. */
7631 wanted_inner_mode))
7643 pos_rtx
7645 ? HOST_WIDE_INT_M1U
7649 }
7651 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7652 have to zero extend. Otherwise, we can just use a SUBREG. */
7655 {
7659 /* If we know that no extraneous bits are set, and that the high
7660 bit is not set, convert extraction to cheaper one - either
7661 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7662 cases. */
7670 {
7674 /* Prefer ZERO_EXTENSION, since it gives more information to
7675 backends. */
7679 }
7681 }
7683 /* Make POS_RTX unless we already have it and it is correct. If we don't
7684 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7685 be a CONST_INT. */
7692 /* Make the required operation. See if we can use existing rtx. */
7699 }
7700 \f
7701 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7702 with any other operations in X. Return X without that shift if so. */
7704 static rtx
7706 {
7709 rtx tem;
7712 {
7714 /* This is the shift itself. If it is wide enough, we will return
7715 either the value being shifted if the shift count is equal to
7716 COUNT or a shift for the difference. */
7730 /* If we can safely shift this constant and we find the inner shift,
7731 make a new operation. */
7736 {
7740 }
7745 }
7748 }
7749 \f
7750 /* Look at the expression rooted at X. Look for expressions
7751 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7752 Form these expressions.
7754 Return the new rtx, usually just X.
7756 Also, for machines like the VAX that don't have logical shift insns,
7757 try to convert logical to arithmetic shift operations in cases where
7758 they are equivalent. This undoes the canonicalizations to logical
7759 shifts done elsewhere.
7761 We try, as much as possible, to re-use rtl expressions to save memory.
7763 IN_CODE says what kind of expression we are processing. Normally, it is
7764 SET. In a memory address it is MEM. When processing the arguments of
7765 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
7766 precisely it is an equality comparison against zero. */
7768 rtx
7770 {
7778 rtx tem;
7782 /* PR rtl-optimization/70944. */
7786 /* Select the code to be used in recursive calls. Once we are inside an
7787 address, we stay there. If we have a comparison, set to COMPARE,
7788 but once inside, go back to our default of SET. */
7791 {
7794 }
7800 /* Process depending on the code of this operation. If NEW is set
7801 nonzero, it will be returned. */
7804 {
7806 /* Convert shifts by constants into multiplications if inside
7807 an address. */
7812 {
7818 {
7821 }
7824 }
7834 {
7838 }
7841 {
7845 mode));
7847 }
7848 else
7849 {
7853 }
7864 {
7868 }
7871 {
7875 mode));
7877 }
7878 else
7879 {
7883 }
7887 /* If the second operand is not a constant, we can't do anything
7888 with it. */
7892 /* If the constant is a power of two minus one and the first operand
7893 is a logical right shift, make an extraction. */
7896 {
7900 }
7902 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7907 {
7916 {
7917 /* If we narrowed the mode when dropping the subreg, then
7918 we must zero-extend to keep the semantics of the AND. */
7920 ;
7924 else
7926 }
7928 /* If that didn't give anything, see if the AND simplifies on
7929 its own. */
7931 {
7935 }
7936 }
7937 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7943 {
7944 /* Apply the distributive law, and then try to make extractions. */
7951 }
7953 /* If we are have (and (rotate X C) M) and C is larger than the number
7954 of bits in M, this is an extraction. */
7960 {
7966 }
7968 /* On machines without logical shifts, if the operand of the AND is
7969 a logical shift and our mask turns off all the propagated sign
7970 bits, we can replace the logical shift with an arithmetic shift. */
7978 {
7985 make_compound_operation
7988 }
7990 /* If the constant is one less than a power of two, this might be
7991 representable by an extraction even if no shift is present.
7992 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7993 we are in a COMPARE. */
7997 next_code),
8000 /* If we are in a comparison and this is an AND with a power of two,
8001 convert this into the appropriate bit extract. */
8007 next_code),
8010 /* If the one operand is a paradoxical subreg of a register or memory and
8011 the constant (limited to the smaller mode) has only zero bits where
8012 the sub expression has known zero bits, this can be expressed as
8013 a zero_extend. */
8015 {
8016 rtx sub;
8022 {
8026 /* original AND constant with all the known zero bits set */
8029 {
8034 }
8035 }
8036 }
8041 /* If the sign bit is known to be zero, replace this with an
8042 arithmetic shift. */
8047 {
8050 next_code),
8053 }
8055 /* fall through */
8061 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8062 this is a SIGN_EXTRACT. */
8069 {
8076 }
8078 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8079 If so, try to merge the shifts into a SIGN_EXTEND. We could
8080 also do this for some cases of SIGN_EXTRACT, but it doesn't
8081 seem worth the effort; the case checked for occurs on Alpha. */
8098 /* Call ourselves recursively on the inner expression. If we are
8099 narrowing the object and it has a different RTL code from
8100 what it originally did, do this SUBREG as a force_to_mode. */
8101 {
8105 /* If in_code is COMPARE, it isn't always safe to pass it through
8106 to the recursive make_compound_operation call. */
8110 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8111 is (const_int 0), rather than
8112 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8122 simplified
8130 {
8131 rtx newer
8134 /* If we have something other than a SUBREG, we might have
8135 done an expansion, so rerun ourselves. */
8139 /* force_to_mode can expand compounds. If it just re-expanded the
8140 compound, use gen_lowpart to convert to the desired mode. */
8142 /* Likewise if it re-expanded the compound only partially.
8143 This happens for SUBREG of ZERO_EXTRACT if they extract
8144 the same number of bits. */
8153 }
8157 }
8162 }
8165 {
8168 }
8170 /* Now recursively process each operand of this operation. We need to
8171 handle ZERO_EXTEND specially so that we don't lose track of the
8172 inner mode. */
8174 {
8182 }
8187 {
8190 }
8193 {
8196 }
8198 maybe_swap:
8199 /* If this is a commutative operation, the changes to the operands
8200 may have made it noncanonical. */
8203 {
8207 }
8210 }
8211 \f
8212 /* Given M see if it is a value that would select a field of bits
8213 within an item, but not the entire word. Return -1 if not.
8214 Otherwise, return the starting position of the field, where 0 is the
8215 low-order bit.
8217 *PLEN is set to the length of the field. */
8219 static int
8221 {
8222 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8227 /* Now shift off the low-order zero bits and see if we have a
8228 power of two minus 1. */
8236 }
8237 \f
8238 /* If X refers to a register that equals REG in value, replace these
8239 references with REG. */
8240 static rtx
8242 {
8250 {
8283 /* FALLTHRU */
8287 {
8291 else
8293 }
8295 /* fall through */
8302 {
8305 {
8307 {
8310 }
8312 }
8313 }
8315 {
8318 {
8321 {
8323 {
8326 }
8328 }
8329 }
8330 }
8333 }
8336 }
8338 /* Return X converted to MODE. If the value is already truncated to
8339 MODE we can just return a subreg even though in the general case we
8340 would need an explicit truncation. */
8342 static rtx
8344 {
8349 {
8350 /* Bit-cast X into an integer mode. */
8355 }
8358 }
8360 /* See if X can be simplified knowing that we will only refer to it in
8361 MODE and will only refer to those bits that are nonzero in MASK.
8362 If other bits are being computed or if masking operations are done
8363 that select a superset of the bits in MASK, they can sometimes be
8364 ignored.
8366 Return a possibly simplified expression, but always convert X to
8367 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8369 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8370 are all off in X. This is used when X will be complemented, by either
8371 NOT, NEG, or XOR. */
8373 static rtx
8376 {
8379 machine_mode op_mode;
8383 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8384 code below will do the wrong thing since the mode of such an
8385 expression is VOIDmode.
8387 Also do nothing if X is a CLOBBER; this can happen if X was
8388 the return value from a call to gen_lowpart. */
8392 /* We want to perform the operation in its present mode unless we know
8393 that the operation is valid in MODE, in which case we do the operation
8394 in MODE. */
8399 /* It is not valid to do a right-shift in a narrower mode
8400 than the one it came in with. */
8405 /* Truncate MASK to fit OP_MODE. */
8409 /* When we have an arithmetic operation, or a shift whose count we
8410 do not know, we need to assume that all bits up to the highest-order
8411 bit in MASK will be needed. This is how we form such a mask. */
8414 else
8418 /* Determine what bits of X are guaranteed to be (non)zero. */
8421 /* If none of the bits in X are needed, return a zero. */
8425 /* If X is a CONST_INT, return a new one. Do this here since the
8426 test below will fail. */
8428 {
8431 else
8432 {
8435 }
8436 }
8438 /* If X is narrower than MODE and we want all the bits in X's mode, just
8439 get X in the proper mode. */
8444 /* We can ignore the effect of a SUBREG if it narrows the mode or
8445 if the constant masks to zero all the bits the mode doesn't have. */
8455 /* The arithmetic simplifications here only work for scalar integer modes. */
8460 {
8462 /* If X is a (clobber (const_int)), return it since we know we are
8463 generating something that won't match. */
8476 /* Similarly for a truncate. */
8480 /* If this is an AND with a constant, convert it into an AND
8481 whose constant is the AND of that constant with MASK. If it
8482 remains an AND of MASK, delete it since it is redundant. */
8485 {
8489 /* If X is still an AND, see if it is an AND with a mask that
8490 is just some low-order bits. If so, and it is MASK, we don't
8491 need it. */
8498 /* If it remains an AND, try making another AND with the bits
8499 in the mode mask that aren't in MASK turned on. If the
8500 constant in the AND is wide enough, this might make a
8501 cheaper constant. */
8506 {
8507 unsigned HOST_WIDE_INT cval
8510 rtx y;
8517 }
8520 }
8525 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8526 low-order bits (as in an alignment operation) and FOO is already
8527 aligned to that boundary, mask C1 to that boundary as well.
8528 This may eliminate that PLUS and, later, the AND. */
8530 {
8534 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8535 number, sign extend it. */
8548 }
8550 /* fall through */
8553 /* Substituting into the operands of a widening MULT is not likely to
8554 create RTL matching a machine insn. */
8564 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8565 most significant bit in MASK since carries from those bits will
8566 affect the bits we are interested in. */
8571 /* If X is (minus C Y) where C's least set bit is larger than any bit
8572 in the mask, then we may replace with (neg Y). */
8575 {
8579 }
8581 /* Similarly, if C contains every bit in the fuller_mask, then we may
8582 replace with (not Y). */
8585 {
8589 }
8596 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8597 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8598 operation which may be a bitfield extraction. Ensure that the
8599 constant we form is not wider than the mode of X. */
8611 {
8620 }
8622 binop:
8623 /* For most binary operations, just propagate into the operation and
8624 change the mode if we have an operation of that mode. */
8629 /* If we ended up truncating both operands, truncate the result of the
8630 operation instead. */
8633 {
8636 }
8646 /* For left shifts, do the same, but just for the first operand.
8647 However, we cannot do anything with shifts where we cannot
8648 guarantee that the counts are smaller than the size of the mode
8649 because such a count will have a different meaning in a
8650 wider mode. */
8660 /* If the shift count is a constant and we can do arithmetic in
8661 the mode of the shift, refine which bits we need. Otherwise, use the
8662 conservative form of the mask. */
8668 else
8680 /* Here we can only do something if the shift count is a constant,
8681 this shift constant is valid for the host, and we can do arithmetic
8682 in OP_MODE. */
8688 {
8692 /* Select the mask of the bits we need for the shift operand. */
8695 /* We can only change the mode of the shift if we can do arithmetic
8696 in the mode of the shift and INNER_MASK is no wider than the
8697 width of X's mode. */
8705 }
8707 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8708 shift and AND produces only copies of the sign bit (C2 is one less
8709 than a power of two), we can do this with just a shift. */
8713 /* The shift puts one of the sign bit copies in the least significant
8714 bit. */
8719 /* Number of bits left after the shift must be more than the mask
8720 needs. */
8723 /* Must be more sign bit copies than the mask needs. */
8733 /* If we are just looking for the sign bit, we don't need this shift at
8734 all, even if it has a variable count. */
8738 /* If this is a shift by a constant, get a mask that contains those bits
8739 that are not copies of the sign bit. We then have two cases: If
8740 MASK only includes those bits, this can be a logical shift, which may
8741 allow simplifications. If MASK is a single-bit field not within
8742 those bits, we are requesting a copy of the sign bit and hence can
8743 shift the sign bit to the appropriate location. */
8747 {
8750 /* If the considered data is wider than HOST_WIDE_INT, we can't
8751 represent a mask for all its bits in a single scalar.
8752 But we only care about the lower bits, so calculate these. */
8755 {
8758 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8759 is the number of bits a full-width mask would have set.
8760 We need only shift if these are fewer than nonzero can
8761 hold. If not, we must keep all bits set in nonzero. */
8766 + HOST_BITS_PER_WIDE_INT
8768 }
8769 else
8770 {
8773 }
8776 {
8781 }
8784 {
8785 x = simplify_shift_const
8791 }
8792 }
8794 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8795 even if the shift count isn't a constant. */
8800 shiftrt:
8802 /* If this is a zero- or sign-extension operation that just affects bits
8803 we don't care about, remove it. Be sure the call above returned
8804 something that is still a shift. */
8814 next_select);
8820 /* If the shift count is constant and we can do computations
8821 in the mode of X, compute where the bits we care about are.
8822 Otherwise, we can't do anything. Don't change the mode of
8823 the shift or propagate MODE into the shift, though. */
8826 {
8836 }
8840 /* If we just want the low-order bit, the NEG isn't needed since it
8841 won't change the low-order bit. */
8845 /* We need any bits less significant than the most significant bit in
8846 MASK since carries from those bits will affect the bits we are
8847 interested in. */
8852 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8853 same as the XOR case above. Ensure that the constant we form is not
8854 wider than the mode of X. */
8862 {
8871 }
8873 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8874 use the full mask inside the NOT. */
8877 unop:
8880 next_select));
8886 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8887 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8888 which is equal to STORE_FLAG_VALUE. */
8900 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8901 written in a narrower mode. We play it safe and do not do so. */
8917 }
8919 /* Ensure we return a value of the proper mode. */
8921 }
8922 \f
8923 /* Return nonzero if X is an expression that has one of two values depending on
8924 whether some other value is zero or nonzero. In that case, we return the
8925 value that is being tested, *PTRUE is set to the value if the rtx being
8926 returned has a nonzero value, and *PFALSE is set to the other alternative.
8928 If we return zero, we set *PTRUE and *PFALSE to X. */
8930 static rtx
8932 {
8938 /* If we are comparing a value against zero, we are done. */
8941 {
8945 }
8947 /* If this is a unary operation whose operand has one of two values, apply
8948 our opcode to compute those values. */
8951 {
8956 }
8958 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8959 make can't possibly match and would suppress other optimizations. */
8961 ;
8963 /* If this is a binary operation, see if either side has only one of two
8964 values. If either one does or if both do and they are conditional on
8965 the same value, compute the new true and false values. */
8967 {
8973 {
8974 /* If if_then_else_cond returned zero, then true/false are the
8975 same rtl. We must copy one of them to prevent invalid rtl
8976 sharing. */
8983 {
8988 }
8989 else
8990 {
8993 }
8996 }
8998 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8999 operands is zero when the other is nonzero, and vice-versa,
9000 and STORE_FLAG_VALUE is 1 or -1. */
9006 {
9023 {
9030 const_true_rtx);
9032 }
9033 }
9035 /* Similarly for MULT, AND and UMIN, except that for these the result
9036 is always zero. */
9040 {
9054 {
9057 }
9058 }
9059 }
9062 {
9063 /* If we have IF_THEN_ELSE already, extract the condition and
9064 canonicalize it if it is NE or EQ. */
9070 {
9073 }
9074 else
9076 }
9078 /* If X is a SUBREG, we can narrow both the true and false values
9079 if the inner expression, if there is a condition. */
9083 {
9089 {
9093 }
9094 }
9096 /* If X is a constant, this isn't special and will cause confusions
9097 if we treat it as such. Likewise if it is equivalent to a constant. */
9100 ;
9102 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9103 will be least confusing to the rest of the compiler. */
9105 {
9108 }
9110 /* If X is known to be either 0 or -1, those are the true and
9111 false values when testing X. */
9115 {
9118 }
9120 /* Likewise for 0 or a single bit. */
9123 {
9126 }
9128 /* Otherwise fail; show no condition with true and false values the same. */
9131 }
9132 \f
9133 /* Return the value of expression X given the fact that condition COND
9134 is known to be true when applied to REG as its first operand and VAL
9135 as its second. X is known to not be shared and so can be modified in
9136 place.
9138 We only handle the simplest cases, and specifically those cases that
9139 arise with IF_THEN_ELSE expressions. */
9141 static rtx
9143 {
9151 /* If either operand of the condition is a floating point value,
9152 then we have to avoid collapsing an EQ comparison. */
9162 /* If X is (abs REG) and we know something about REG's relationship
9163 with zero, we may be able to simplify this. */
9167 {
9176 }
9178 /* The only other cases we handle are MIN, MAX, and comparisons if the
9179 operands are the same as REG and VAL. */
9182 {
9184 {
9187 }
9190 {
9192 {
9200 else
9202 }
9205 {
9208 /* Do not reverse the condition when it is NE or EQ.
9209 This is because we cannot conclude anything about
9210 the value of 'SMAX (x, y)' when x is not equal to y,
9211 but we can when x equals y. */
9217 {
9228 }
9229 }
9230 }
9231 }
9233 {
9238 {
9239 /* We must simplify subreg here, before we lose track of the
9240 original inner_mode. */
9245 else
9247 }
9250 }
9251 /* We don't have to handle SIGN_EXTEND here, because even in the
9252 case of replacing something with a modeless CONST_INT, a
9253 CONST_INT is already (supposed to be) a valid sign extension for
9254 its narrower mode, which implies it's already properly
9255 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9256 story is different. */
9258 {
9263 {
9264 /* We must simplify the zero_extend here, before we lose
9265 track of the original inner_mode. */
9270 else
9272 }
9275 }
9279 {
9286 }
9289 }
9290 \f
9291 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9292 assignment as a field assignment. */
9294 static int
9296 {
9298 {
9303 /* For big endian, adjust the memory offset. */
9308 else
9310 }
9318 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9319 Note that all SUBREGs of MEM are paradoxical; otherwise they
9320 would have been rewritten. */
9333 /* We used to see if get_last_value of X and Y were the same but that's
9334 not correct. In one direction, we'll cause the assignment to have
9335 the wrong destination and in the case, we'll import a register into this
9336 insn that might have already have been dead. So fail if none of the
9337 above cases are true. */
9339 }
9340 \f
9341 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9342 Return that assignment if so.
9344 We only handle the most common cases. */
9346 static rtx
9348 {
9351 rtx assign;
9353 HOST_WIDE_INT c1;
9354 HOST_WIDE_INT pos;
9356 rtx other;
9357 machine_mode mode;
9359 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9360 a clear of a one-bit field. We will have changed it to
9361 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9362 for a SUBREG. */
9368 {
9374 }
9384 {
9391 }
9393 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9394 one-bit field. */
9398 {
9404 }
9406 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9407 SRC is an AND with all bits of that field set, then we can discard
9408 the AND. */
9413 {
9420 else
9423 /* Complete overlap. We can remove the source AND. */
9427 /* Partial overlap. We can reduce the source AND. */
9429 {
9434 }
9435 }
9437 /* The other case we handle is assignments into a constant-position
9438 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9439 a mask that has all one bits except for a group of zero bits and
9440 OTHER is known to have zeros where C1 has ones, this is such an
9441 assignment. Compute the position and length from C1. Shift OTHER
9442 to the appropriate position, force it to the required mode, and
9443 make the extraction. Check for the AND in both operands. */
9445 /* One or more SUBREGs might obscure the constant-position field
9446 assignment. The first one we are likely to encounter is an outer
9447 narrowing SUBREG, which we can just strip for the purposes of
9448 identifying the constant-field assignment. */
9462 /* The second SUBREG that might get in the way is a paradoxical
9463 SUBREG around the first operand of the AND. We want to
9464 pretend the operand is as wide as the destination here. We
9465 do this by adjusting the MEM to wider mode for the sole
9466 purpose of the call to rtx_equal_for_field_assignment_p. Also
9467 note this trick only works for MEMs. */
9479 /* The second SUBREG that might get in the way is a paradoxical
9480 SUBREG around the first operand of the AND. We want to
9481 pretend the operand is as wide as the destination here. We
9482 do this by adjusting the MEM to wider mode for the sole
9483 purpose of the call to rtx_equal_for_field_assignment_p. Also
9484 note this trick only works for MEMs. */
9492 else
9505 /* The mode to use for the source is the mode of the assignment, or of
9506 what is inside a possible STRICT_LOW_PART. */
9510 /* Shift OTHER right POS places and make it the source, restricting it
9511 to the proper length and mode. */
9516 dest);
9519 ? HOST_WIDE_INT_M1U
9523 /* If SRC is masked by an AND that does not make a difference in
9524 the value being stored, strip it. */
9535 }
9536 \f
9537 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9538 if so. */
9540 static rtx
9542 {
9546 rtx tem;
9548 /* Distributivity is not true for floating point as it can change the
9549 value. So we don't do it unless -funsafe-math-optimizations. */
9554 /* The outer operation can only be one of the following: */
9562 /* If either operand is a primitive we can't do anything, so get out
9563 fast. */
9573 /* See if the inner and outer operations distribute. */
9575 {
9580 /* These all distribute except over PLUS. */
9591 /* This is also a multiply, so it distributes over everything. */
9594 /* This used to handle SUBREG, but this turned out to be counter-
9595 productive, since (subreg (op ...)) usually is not handled by
9596 insn patterns, and this "optimization" therefore transformed
9597 recognizable patterns into unrecognizable ones. Therefore the
9598 SUBREG case was removed from here.
9600 It is possible that distributing SUBREG over arithmetic operations
9601 leads to an intermediate result than can then be optimized further,
9602 e.g. by moving the outer SUBREG to the other side of a SET as done
9603 in simplify_set. This seems to have been the original intent of
9604 handling SUBREGs here.
9606 However, with current GCC this does not appear to actually happen,
9607 at least on major platforms. If some case is found where removing
9608 the SUBREG case here prevents follow-on optimizations, distributing
9609 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9613 }
9615 /* Set LHS and RHS to the inner operands (A and B in the example
9616 above) and set OTHER to the common operand (C in the example).
9617 There is only one way to do this unless the inner operation is
9618 commutative. */
9630 else
9633 /* Form the new inner operation, seeing if it simplifies first. */
9636 /* There is one exception to the general way of distributing:
9637 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9639 {
9642 }
9644 /* We may be able to continuing distributing the result, so call
9645 ourselves recursively on the inner operation before forming the
9646 outer operation, which we return. */
9649 }
9651 /* See if X is of the form (* (+ A B) C), and if so convert to
9652 (+ (* A C) (* B C)) and try to simplify.
9654 Most of the time, this results in no change. However, if some of
9655 the operands are the same or inverses of each other, simplifications
9656 will result.
9658 For example, (and (ior A B) (not B)) can occur as the result of
9659 expanding a bit field assignment. When we apply the distributive
9660 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9661 which then simplifies to (and (A (not B))).
9663 Note that no checks happen on the validity of applying the inverse
9664 distributive law. This is pointless since we can do it in the
9665 few places where this routine is called.
9667 N is the index of the term that is decomposed (the arithmetic operation,
9668 i.e. (+ A B) in the first example above). !N is the index of the term that
9669 is distributed, i.e. of C in the first example above. */
9670 static rtx
9672 {
9673 machine_mode mode;
9677 /* Distributivity is not true for floating point as it can change the
9678 value. So we don't do it unless -funsafe-math-optimizations. */
9695 /* Special case (and (xor B C) (not A)), which is equivalent to
9696 (xor (ior A B) (ior A C)) */
9698 {
9701 }
9704 {
9705 /* Distribute the second term. */
9708 }
9709 else
9710 {
9711 /* Distribute the first term. */
9714 }
9724 }
9725 \f
9726 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9727 in MODE. Return an equivalent form, if different from (and VAROP
9728 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9730 static rtx
9733 {
9736 rtx orig_varop;
9744 /* Simplify VAROP knowing that we will be only looking at some of the
9745 bits in it.
9747 Note by passing in CONSTOP, we guarantee that the bits not set in
9748 CONSTOP are not significant and will never be examined. We must
9749 ensure that is the case by explicitly masking out those bits
9750 before returning. */
9753 /* If VAROP is a CLOBBER, we will fail so return it. */
9757 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9758 to VAROP and return the new constant. */
9762 /* See what bits may be nonzero in VAROP. Unlike the general case of
9763 a call to nonzero_bits, here we don't care about bits outside
9764 MODE. */
9768 /* Turn off all bits in the constant that are known to already be zero.
9769 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9770 which is tested below. */
9774 /* If we don't have any bits left, return zero. */
9778 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9779 a power of two, we can replace this with an ASHIFT. */
9784 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9785 or XOR, then try to apply the distributive law. This may eliminate
9786 operations if either branch can be simplified because of the AND.
9787 It may also make some cases more complex, but those cases probably
9788 won't match a pattern either with or without this. */
9791 return
9792 gen_lowpart
9794 apply_distributive_law
9799 constop),
9803 constop))));
9805 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9806 the AND and see if one of the operands simplifies to zero. If so, we
9807 may eliminate it. */
9811 {
9820 }
9822 /* Make a SUBREG if necessary. If we can't make it, fail. */
9827 /* If we are only masking insignificant bits, return VAROP. */
9834 /* Otherwise, return an AND. */
9836 }
9839 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9840 in MODE.
9842 Return an equivalent form, if different from X. Otherwise, return X. If
9843 X is zero, we are to always construct the equivalent form. */
9845 static rtx
9848 {
9859 }
9860 \f
9861 /* Given a REG, X, compute which bits in X can be nonzero.
9862 We don't care about bits outside of those defined in MODE.
9864 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9865 a shift, AND, or zero_extract, we can do better. */
9867 static rtx
9869 const_rtx known_x ATTRIBUTE_UNUSED,
9870 machine_mode known_mode ATTRIBUTE_UNUSED,
9873 {
9874 rtx tem;
9877 /* If X is a register whose nonzero bits value is current, use it.
9878 Otherwise, if X is a register whose value we can find, use that
9879 value. Otherwise, use the previously-computed global nonzero bits
9880 for this register. */
9894 && !REGNO_REG_SET_P
9897 {
9898 /* Note that, even if the precision of last_set_mode is lower than that
9899 of mode, record_value_for_reg invoked nonzero_bits on the register
9900 with nonzero_bits_mode (because last_set_mode is necessarily integral
9901 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
9902 are all valid, hence in mode too since nonzero_bits_mode is defined
9903 to the largest HWI_COMPUTABLE_MODE_P mode. */
9906 }
9910 {
9916 }
9919 {
9923 /* We don't know anything about the upper bits. */
9927 }
9930 }
9932 /* Return the number of bits at the high-order end of X that are known to
9933 be equal to the sign bit. X will be used in mode MODE; if MODE is
9934 VOIDmode, X will be used in its own mode. The returned value will always
9935 be between 1 and the number of bits in MODE. */
9937 static rtx
9939 const_rtx known_x ATTRIBUTE_UNUSED,
9940 machine_mode known_mode
9941 ATTRIBUTE_UNUSED,
9944 {
9945 rtx tem;
9958 && !REGNO_REG_SET_P
9961 {
9964 }
9975 }
9976 \f
9977 /* Return the number of "extended" bits there are in X, when interpreted
9978 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9979 unsigned quantities, this is the number of high-order zero bits.
9980 For signed quantities, this is the number of copies of the sign bit
9981 minus 1. In both case, this function returns the number of "spare"
9982 bits. For example, if two quantities for which this function returns
9983 at least 1 are added, the addition is known not to overflow.
9985 This function will always return 0 unless called during combine, which
9986 implies that it must be called from a define_split. */
9988 unsigned int
9990 {
10000 }
10002 /* This function is called from `simplify_shift_const' to merge two
10003 outer operations. Specifically, we have already found that we need
10004 to perform operation *POP0 with constant *PCONST0 at the outermost
10005 position. We would now like to also perform OP1 with constant CONST1
10006 (with *POP0 being done last).
10008 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10009 the resulting operation. *PCOMP_P is set to 1 if we would need to
10010 complement the innermost operand, otherwise it is unchanged.
10012 MODE is the mode in which the operation will be done. No bits outside
10013 the width of this mode matter. It is assumed that the width of this mode
10014 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10016 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10017 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10018 result is simply *PCONST0.
10020 If the resulting operation cannot be expressed as one operation, we
10021 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10023 static int
10024 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10025 {
10032 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10036 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10037 if OP0 is SET. */
10046 {
10048 {
10066 }
10067 }
10069 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10073 /* If the two constants aren't the same, we can't do anything. The
10074 remaining six cases can all be done. */
10078 else
10080 {
10083 /* (a & b) | b == b */
10086 /* (a ^ b) | b == a | b */
10087 {;}
10092 /* (a & b) ^ b == (~a) & b */
10095 /* (a | b) ^ b == a & ~b */
10101 /* (a | b) & b == b */
10104 /* (a ^ b) & b) == (~a) & b */
10109 }
10111 /* Check for NO-OP cases. */
10124 /* ??? Slightly redundant with the above mask, but not entirely.
10125 Moving this above means we'd have to sign-extend the mode mask
10126 for the final test. */
10131 }
10132 \f
10133 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10134 the shift in. The original shift operation CODE is performed on OP in
10135 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10136 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10137 result of the shift is subject to operation OUTER_CODE with operand
10138 OUTER_CONST. */
10140 static machine_mode
10144 {
10149 /* In general we can't perform in wider mode for right shift and rotate. */
10151 {
10153 /* We can still widen if the bits brought in from the left are identical
10154 to the sign bit of ORIG_MODE. */
10162 /* Similarly here but with zero bits. */
10167 /* We can also widen if the bits brought in will be masked off. This
10168 operation is performed in ORIG_MODE. */
10170 {
10176 }
10177 /* fall through */
10187 }
10188 }
10190 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10191 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10192 if we cannot simplify it. Otherwise, return a simplified value.
10194 The shift is normally computed in the widest mode we find in VAROP, as
10195 long as it isn't a different number of words than RESULT_MODE. Exceptions
10196 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10198 static rtx
10201 {
10207 unsigned int mode_words
10209 /* We form (outer_op (code varop count) (outer_const)). */
10215 /* Make sure and truncate the "natural" shift on the way in. We don't
10216 want to do this inside the loop as it makes it more difficult to
10217 combine shifts. */
10221 /* If we were given an invalid count, don't do anything except exactly
10222 what was requested. */
10229 /* Unless one of the branches of the `if' in this loop does a `continue',
10230 we will `break' the loop after the `if'. */
10233 {
10234 /* If we have an operand of (clobber (const_int 0)), fail. */
10238 /* Convert ROTATERT to ROTATE. */
10240 {
10245 else
10247 }
10252 /* Handle cases where the count is greater than the size of the mode
10253 minus 1. For ASHIFT, use the size minus one as the count (this can
10254 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10255 take the count modulo the size. For other shifts, the result is
10256 zero.
10258 Since these shifts are being produced by the compiler by combining
10259 multiple operations, each of which are defined, we know what the
10260 result is supposed to be. */
10263 {
10268 else
10269 {
10270 /* We can't simply return zero because there may be an
10271 outer op. */
10275 }
10276 }
10278 /* If we discovered we had to complement VAROP, leave. Making a NOT
10279 here would cause an infinite loop. */
10283 /* An arithmetic right shift of a quantity known to be -1 or 0
10284 is a no-op. */
10288 {
10291 }
10293 /* If we are doing an arithmetic right shift and discarding all but
10294 the sign bit copies, this is equivalent to doing a shift by the
10295 bitsize minus one. Convert it into that shift because it will often
10296 allow other simplifications. */
10303 /* We simplify the tests below and elsewhere by converting
10304 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10305 `make_compound_operation' will convert it to an ASHIFTRT for
10306 those machines (such as VAX) that don't have an LSHIFTRT. */
10323 {
10330 {
10333 }
10337 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10338 minus the width of a smaller mode, we can do this with a
10339 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10346 {
10355 }
10359 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10360 the same number of words as what we've seen so far. Then store
10361 the widest mode in MODE. */
10367 == mode_words
10370 {
10375 }
10379 /* Some machines use MULT instead of ASHIFT because MULT
10380 is cheaper. But it is still better on those machines to
10381 merge two shifts into one. */
10384 {
10385 varop
10391 }
10395 /* Similar, for when divides are cheaper. */
10398 {
10399 varop
10405 }
10409 /* If we are extracting just the sign bit of an arithmetic
10410 right shift, that shift is not needed. However, the sign
10411 bit of a wider mode may be different from what would be
10412 interpreted as the sign bit in a narrower mode, so, if
10413 the result is narrower, don't discard the shift. */
10418 {
10421 }
10423 /* fall through */
10428 /* Here we have two nested shifts. The result is usually the
10429 AND of a new shift with a mask. We compute the result below. */
10436 {
10440 rtx mask_rtx;
10442 /* We have one common special case. We can't do any merging if
10443 the inner code is an ASHIFTRT of a smaller mode. However, if
10444 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10445 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10446 we can convert it to
10447 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10448 This simplifies certain SIGN_EXTEND operations. */
10452 {
10453 /* C3 has the low-order C1 bits zero. */
10465 }
10467 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10468 than C1 high-order bits equal to the sign bit, we can convert
10469 this to either an ASHIFT or an ASHIFTRT depending on the
10470 two counts.
10472 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10478 {
10482 {
10485 }
10488 }
10490 /* There are some cases we can't do. If CODE is ASHIFTRT,
10491 we can only do this if FIRST_CODE is also ASHIFTRT.
10493 We can't do the case when CODE is ROTATE and FIRST_CODE is
10494 ASHIFTRT.
10496 If the mode of this shift is not the mode of the outer shift,
10497 we can't do this if either shift is a right shift or ROTATE.
10499 Finally, we can't do any of these if the mode is too wide
10500 unless the codes are the same.
10502 Handle the case where the shift codes are the same
10503 first. */
10506 {
10515 }
10526 /* To compute the mask to apply after the shift, shift the
10527 nonzero bits of the inner shift the same way the
10528 outer shift will. */
10531 result_mode);
10533 mask_rtx
10537 /* Give up if we can't compute an outer operation to use. */
10545 /* If the shifts are in the same direction, we add the
10546 counts. Otherwise, we subtract them. */
10550 else
10553 /* If COUNT is positive, the new shift is usually CODE,
10554 except for the two exceptions below, in which case it is
10555 FIRST_CODE. If the count is negative, FIRST_CODE should
10556 always be used */
10566 }
10568 /* If we have (A << B << C) for any shift, we can convert this to
10569 (A << C << B). This wins if A is a constant. Only try this if
10570 B is not a constant. */
10575 {
10576 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10577 sure the result will be masked. See PR70222. */
10585 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10586 up outer sign extension (often left and right shift) is
10587 hardly more efficient than the original. See PR70429. */
10597 }
10604 /* Make this fit the case below. */
10611 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10612 with C the size of VAROP - 1 and the shift is logical if
10613 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10614 we have an (le X 0) operation. If we have an arithmetic shift
10615 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10616 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10624 {
10627 const0_rtx);
10633 }
10635 /* If we have (shift (logical)), move the logical to the outside
10636 to allow it to possibly combine with another logical and the
10637 shift to combine with another shift. This also canonicalizes to
10638 what a ZERO_EXTRACT looks like. Also, some machines have
10639 (and (shift)) insns. */
10642 /* We can't do this if we have (ashiftrt (xor)) and the
10643 constant has its sign bit set in shift_mode with shift_mode
10644 wider than result_mode. */
10648 shift_mode))
10656 {
10659 }
10661 /* If we can't do that, try to simplify the shift in each arm of the
10662 logical expression, make a new logical expression, and apply
10663 the inverse distributive law. This also can't be done for
10664 (ashiftrt (xor)) where we've widened the shift and the constant
10665 changes the sign bit. */
10670 shift_mode)))
10671 {
10683 }
10687 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10688 says that the sign bit can be tested, FOO has mode MODE, C is
10689 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10690 that may be nonzero. */
10700 {
10704 }
10708 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10709 than the number of bits in the mode is equivalent to A. */
10713 {
10717 }
10719 /* NEG commutes with ASHIFT since it is multiplication. Move the
10720 NEG outside to allow shifts to combine. */
10724 {
10727 }
10731 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10732 is one less than the number of bits in the mode is
10733 equivalent to (xor A 1). */
10740 {
10744 }
10746 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10747 that might be nonzero in BAR are those being shifted out and those
10748 bits are known zero in FOO, we can replace the PLUS with FOO.
10749 Similarly in the other operand order. This code occurs when
10750 we are computing the size of a variable-size array. */
10757 {
10760 }
10768 result_mode)))
10769 {
10772 }
10774 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10784 {
10787 }
10789 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10790 signbit', and attempt to change the PLUS to an XOR and move it to
10791 the outer operation as is done above in the AND/IOR/XOR case
10792 leg for shift(logical). See details in logical handling above
10793 for reasoning in doing so. */
10804 {
10807 }
10812 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10813 with C the size of VAROP - 1 and the shift is logical if
10814 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10815 we have a (gt X 0) operation. If the shift is arithmetic with
10816 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10817 we have a (neg (gt X 0)) operation. */
10826 {
10829 const0_rtx);
10835 }
10839 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10840 if the truncate does not affect the value. */
10847 {
10850 varop_inner
10853 GEN_INT
10858 }
10863 }
10866 }
10871 /* We have now finished analyzing the shift. The result should be
10872 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10873 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10874 to the result of the shift. OUTER_CONST is the relevant constant,
10875 but we must turn off all bits turned off in the shift. */
10883 /* Make a SUBREG if necessary. If we can't make it, fail. */
10888 /* If we have an outer operation and we just made a shift, it is
10889 possible that we could have simplified the shift were it not
10890 for the outer operation. So try to do the simplification
10891 recursively. */
10895 else
10901 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10902 turn off all the bits that the shift would have turned off. */
10907 /* Do the remainder of the processing in RESULT_MODE. */
10910 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10911 operation. */
10916 {
10924 {
10925 /* This means that we have determined that the result is
10926 equivalent to a constant. This should be rare. */
10929 }
10932 else
10935 }
10938 }
10940 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10941 The result of the shift is RESULT_MODE. If we cannot simplify it,
10942 return X or, if it is NULL, synthesize the expression with
10943 simplify_gen_binary. Otherwise, return a simplified value.
10945 The shift is normally computed in the widest mode we find in VAROP, as
10946 long as it isn't a different number of words than RESULT_MODE. Exceptions
10947 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10949 static rtx
10952 {
10962 }
10964 \f
10965 /* A subroutine of recog_for_combine. See there for arguments and
10966 return value. */
10968 static int
10970 {
10972 rtx pat_without_clobbers;
10980 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10981 we use to indicate that something didn't match. If we find such a
10982 thing, force rejection. */
10996 {
10999 else
11002 }
11004 /* If it isn't, there is the possibility that we previously had an insn
11005 that clobbered some register as a side effect, but the combined
11006 insn doesn't need to do that. So try once more without the clobbers
11007 unless this represents an ASM insn. */
11011 {
11016 {
11019 pos++;
11020 }
11030 {
11033 else
11036 }
11037 }
11044 /* Recognize all noop sets, these will be killed by followup pass. */
11048 /* If we had any clobbers to add, make a new pattern than contains
11049 them. Then check to make sure that all of them are dead. */
11051 {
11061 else
11068 {
11073 {
11077 }
11078 }
11080 }
11084 {
11091 /* Allow targets to reject combined insn. */
11093 {
11096 dump_file);
11098 /* Callers expect recog_for_combine to strip
11099 clobbers from the pattern on failure. */
11104 }
11109 }
11115 }
11117 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11118 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11119 Return whether anything was so changed. */
11121 static bool
11123 {
11129 {
11138 {
11147 else
11149 }
11155 {
11158 }
11163 {
11166 }
11167 else
11175 }
11179 {
11183 {
11187 }
11188 }
11195 {
11210 else
11218 }
11221 }
11223 /* Like recog, but we receive the address of a pointer to a new pattern.
11224 We try to match the rtx that the pointer points to.
11225 If that fails, we may try to modify or replace the pattern,
11226 storing the replacement into the same pointer object.
11228 Modifications include deletion or addition of CLOBBERs. If the
11229 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11230 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11231 (and undo if that fails).
11233 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11234 the CLOBBERs are placed.
11236 The value is the final insn code from the pattern ultimately matched,
11237 or -1. */
11239 static int
11241 {
11253 {
11256 {
11260 }
11261 }
11264 {
11269 }
11272 }
11273 \f
11274 /* Like gen_lowpart_general but for use by combine. In combine it
11275 is not possible to create any new pseudoregs. However, it is
11276 safe to create invalid memory addresses, because combine will
11277 try to recognize them and all they will do is make the combine
11278 attempt fail.
11280 If for some reason this cannot do its job, an rtx
11281 (clobber (const_int 0)) is returned.
11282 An insn containing that will not be recognized. */
11284 static rtx
11286 {
11290 rtx result;
11295 /* We can only support MODE being wider than a word if X is a
11296 constant integer or has a mode the same size. */
11301 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11302 won't know what to do. So we will strip off the SUBREG here and
11303 process normally. */
11305 {
11308 /* For use in case we fall down into the address adjustments
11309 further below, we need to adjust the known mode and size of
11310 x; imode and isize, since we just adjusted x. */
11317 }
11325 {
11328 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11329 address. */
11334 /* If we want to refer to something bigger than the original memref,
11335 generate a paradoxical subreg instead. That will force a reload
11336 of the original memref X. */
11343 /* Adjust the address so that the address-after-the-data is
11344 unchanged. */
11349 }
11351 /* If X is a comparison operator, rewrite it in a new mode. This
11352 probably won't match, but may allow further simplifications. */
11356 /* If we couldn't simplify X any other way, just enclose it in a
11357 SUBREG. Normally, this SUBREG won't match, but some patterns may
11358 include an explicit SUBREG or we may simplify it further in combine. */
11359 else
11360 {
11361 rtx res;
11364 {
11369 }
11373 }
11375 fail:
11377 }
11378 \f
11379 /* Try to simplify a comparison between OP0 and a constant OP1,
11380 where CODE is the comparison code that will be tested, into a
11381 (CODE OP0 const0_rtx) form.
11383 The result is a possibly different comparison code to use.
11384 *POP1 may be updated. */
11386 static enum rtx_code
11389 {
11393 /* Get the constant we are comparing against and turn off all bits
11394 not on in our mode. */
11398 /* If we are comparing against a constant power of two and the value
11399 being compared can only have that single bit nonzero (e.g., it was
11400 `and'ed with that bit), we can replace this with a comparison
11401 with zero. */
11409 {
11412 }
11414 /* Similarly, if we are comparing a value known to be either -1 or
11415 0 with -1, change it to the opposite comparison against zero. */
11420 {
11423 }
11425 /* Do some canonicalizations based on the comparison code. We prefer
11426 comparisons against zero and then prefer equality comparisons.
11427 If we can reduce the size of a constant, we will do that too. */
11429 {
11431 /* < C is equivalent to <= (C - 1) */
11433 {
11436 /* ... fall through to LE case below. */
11438 }
11439 else
11443 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11445 {
11448 }
11450 /* If we are doing a <= 0 comparison on a value known to have
11451 a zero sign bit, we can replace this with == 0. */
11461 /* >= C is equivalent to > (C - 1). */
11463 {
11466 /* ... fall through to GT below. */
11468 }
11469 else
11473 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11475 {
11478 }
11480 /* If we are doing a > 0 comparison on a value known to have
11481 a zero sign bit, we can replace this with != 0. */
11491 /* < C is equivalent to <= (C - 1). */
11493 {
11496 /* ... fall through ... */
11497 }
11498 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11502 {
11506 }
11507 else
11511 /* unsigned <= 0 is equivalent to == 0 */
11514 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11518 {
11521 }
11525 /* >= C is equivalent to > (C - 1). */
11527 {
11530 /* ... fall through ... */
11531 }
11533 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11537 {
11541 }
11542 else
11546 /* unsigned > 0 is equivalent to != 0 */
11549 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11553 {
11556 }
11561 }
11565 }
11566 \f
11567 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11568 comparison code that will be tested.
11570 The result is a possibly different comparison code to use. *POP0 and
11571 *POP1 may be updated.
11573 It is possible that we might detect that a comparison is either always
11574 true or always false. However, we do not perform general constant
11575 folding in combine, so this knowledge isn't useful. Such tautologies
11576 should have been detected earlier. Hence we ignore all such cases. */
11578 static enum rtx_code
11580 {
11587 /* Try a few ways of applying the same transformation to both operands. */
11589 {
11590 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11591 so check specially. */
11607 - (GET_MODE_PRECISION
11609 {
11612 }
11614 /* If both operands are the same constant shift, see if we can ignore the
11615 shift. We can if the shift is a rotate or if the bits shifted out of
11616 this shift are known to be zero for both inputs and if the type of
11617 comparison is compatible with the shift. */
11630 {
11643 else
11645 }
11647 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11648 SUBREGs are of the same mode, and, in both cases, the AND would
11649 be redundant if the comparison was done in the narrower mode,
11650 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11651 and the operand's possibly nonzero bits are 0xffffff01; in that case
11652 if we only care about QImode, we don't need the AND). This case
11653 occurs if the output mode of an scc insn is not SImode and
11654 STORE_FLAG_VALUE == 1 (e.g., the 386).
11656 Similarly, check for a case where the AND's are ZERO_EXTEND
11657 operations from some narrower mode even though a SUBREG is not
11658 present. */
11663 {
11680 {
11684 /* The resulting comparison is always unsigned since we masked
11685 off the original sign bit. */
11689 }
11696 {
11702 }
11706 }
11708 /* If both operands are NOT, we can strip off the outer operation
11709 and adjust the comparison code for swapped operands; similarly for
11710 NEG, except that this must be an equality comparison. */
11716 else
11718 }
11720 /* If the first operand is a constant, swap the operands and adjust the
11721 comparison code appropriately, but don't do this if the second operand
11722 is already a constant integer. */
11724 {
11727 }
11729 /* We now enter a loop during which we will try to simplify the comparison.
11730 For the most part, we only are concerned with comparisons with zero,
11731 but some things may really be comparisons with zero but not start
11732 out looking that way. */
11735 {
11742 HOST_WIDE_INT const_op;
11744 /* We only want to handle integral modes. This catches VOIDmode,
11745 CCmode, and the floating-point modes. An exception is that we
11746 can handle VOIDmode if OP0 is a COMPARE or a comparison
11747 operation. */
11754 /* Try to simplify the compare to constant, possibly changing the
11755 comparison op, and/or changing op1 to zero. */
11759 /* Compute some predicates to simplify code below. */
11766 /* If this is a sign bit comparison and we can do arithmetic in
11767 MODE, say that we will only be needing the sign bit of OP0. */
11770 HOST_WIDE_INT_1U
11774 /* Now try cases based on the opcode of OP0. If none of the cases
11775 does a "continue", we exit this loop immediately after the
11776 switch. */
11779 {
11781 /* If we are extracting a single bit from a variable position in
11782 a constant that has only a single bit set and are comparing it
11783 with zero, we can convert this into an equality comparison
11784 between the position and the location of the single bit. */
11785 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11786 have already reduced the shift count modulo the word size. */
11792 {
11800 /* Result is nonzero iff shift count is equal to I. */
11803 }
11805 /* fall through */
11810 {
11813 }
11817 /* If testing for equality, we can take the NOT of the constant. */
11820 {
11824 }
11826 /* If just looking at the sign bit, reverse the sense of the
11827 comparison. */
11829 {
11833 }
11837 /* If testing for equality, we can take the NEG of the constant. */
11840 {
11844 }
11846 /* The remaining cases only apply to comparisons with zero. */
11850 /* When X is ABS or is known positive,
11851 (neg X) is < 0 if and only if X != 0. */
11859 {
11863 }
11865 /* If we have NEG of something whose two high-order bits are the
11866 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11868 {
11872 }
11876 /* If we are testing equality and our count is a constant, we
11877 can perform the inverse operation on our RHS. */
11881 {
11885 }
11887 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11888 a particular bit. Convert it to an AND of a constant of that
11889 bit. This will be converted into a ZERO_EXTRACT. */
11893 {
11895 (HOST_WIDE_INT_1U
11900 }
11902 /* Fall through. */
11905 /* ABS is ignorable inside an equality comparison with zero. */
11907 {
11910 }
11914 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11915 (compare FOO CONST) if CONST fits in FOO's mode and we
11916 are either testing inequality or have an unsigned
11917 comparison with ZERO_EXTEND or a signed comparison with
11918 SIGN_EXTEND. But don't do it if we don't have a compare
11919 insn of the given mode, since we'd have to revert it
11920 later on, and then we wouldn't know whether to sign- or
11921 zero-extend. */
11924 && ! unsigned_comparison_p
11928 {
11931 }
11935 /* Check for the case where we are comparing A - C1 with C2, that is
11937 (subreg:MODE (plus (A) (-C1))) op (C2)
11939 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11940 comparison in the wider mode. One of the following two conditions
11941 must be true in order for this to be valid:
11943 1. The mode extension results in the same bit pattern being added
11944 on both sides and the comparison is equality or unsigned. As
11945 C2 has been truncated to fit in MODE, the pattern can only be
11946 all 0s or all 1s.
11948 2. The mode extension results in the sign bit being copied on
11949 each side.
11951 The difficulty here is that we have predicates for A but not for
11952 (A - C1) so we need to check that C1 is within proper bounds so
11953 as to perturbate A as little as possible. */
11960 {
11969 /* (A - C1) zero-extends if it is positive and sign-extends
11970 if it is negative, C2 both zero- and sign-extends. */
11974 /* (A - C1) sign-extends if it is positive and 1-extends
11975 if it is negative, C2 both sign- and 1-extends. */
11982 /* (A - C1) always sign-extends, like C2. */
11986 {
11989 }
11990 }
11992 /* If the inner mode is narrower and we are extracting the low part,
11993 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11996 ;
11997 else
12000 /* FALLTHROUGH */
12010 {
12013 }
12017 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12018 this for equality comparisons due to pathological cases involving
12019 overflows. */
12023 {
12027 }
12029 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12032 {
12036 }
12040 /* We used to optimize signed comparisons against zero, but that
12041 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12042 arrive here as equality comparisons, or (GEU, LTU) are
12043 optimized away. No need to special-case them. */
12045 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12046 (eq B (minus A C)), whichever simplifies. We can only do
12047 this for equality comparisons due to pathological cases involving
12048 overflows. */
12052 {
12056 }
12061 {
12065 }
12067 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12068 of bits in X minus 1, is one iff X > 0. */
12073 {
12077 }
12081 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12082 if C is zero or B is a constant. */
12086 {
12090 }
12098 /* We can't do anything if OP0 is a condition code value, rather
12099 than an actual data value. */
12105 /* Get the two operands being compared. */
12108 else
12111 /* Check for the cases where we simply want the result of the
12112 earlier test or the opposite of that result. */
12116 {
12120 else
12124 {
12129 }
12130 }
12134 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12135 iff X <= 0. */
12139 {
12143 }
12147 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12148 will be converted to a ZERO_EXTRACT later. */
12152 {
12157 }
12159 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12160 zero and X is a comparison and C1 and C2 describe only bits set
12161 in STORE_FLAG_VALUE, we can compare with X. */
12169 {
12176 {
12179 }
12180 }
12182 /* If we are doing an equality comparison of an AND of a bit equal
12183 to the sign bit, replace this with a LT or GE comparison of
12184 the underlying value. */
12191 {
12195 }
12197 /* If this AND operation is really a ZERO_EXTEND from a narrower
12198 mode, the constant fits within that mode, and this is either an
12199 equality or unsigned comparison, try to do this comparison in
12200 the narrower mode.
12202 Note that in:
12204 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12205 -> (ne:DI (reg:SI 4) (const_int 0))
12207 unless TRULY_NOOP_TRUNCATION allows it or the register is
12208 known to hold a value of the required mode the
12209 transformation is invalid. */
12217 {
12220 }
12222 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12223 fits in both M1 and M2 and the SUBREG is either paradoxical
12224 or represents the low part, permute the SUBREG and the AND
12225 and try again. */
12228 {
12231 /* Require an integral mode, to avoid creating something like
12232 (AND:SF ...). */
12234 /* It is unsafe to commute the AND into the SUBREG if the
12235 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12236 not defined. As originally written the upper bits
12237 have a defined value due to the AND operation.
12238 However, if we commute the AND inside the SUBREG then
12239 they no longer have defined values and the meaning of
12240 the code has been changed.
12241 Also C1 should not change value in the smaller mode,
12242 see PR67028 (a positive C1 can become negative in the
12243 smaller mode, so that the AND does no longer mask the
12244 upper bits). */
12245 && ((WORD_REGISTER_OPERATIONS
12257 {
12263 }
12264 }
12266 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12270 {
12275 }
12277 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12278 (eq (and (lshiftrt X) 1) 0).
12279 Also handle the case where (not X) is expressed using xor. */
12283 {
12293 == HOST_WIDE_INT_1U
12295 {
12296 op0
12301 }
12302 }
12306 /* If we have (compare (ashift FOO N) (const_int C)) and
12307 the high order N bits of FOO (N+1 if an inequality comparison)
12308 are known to be zero, we can do this by comparing FOO with C
12309 shifted right N bits so long as the low-order N bits of C are
12310 zero. */
12322 {
12323 /* We must perform a logical shift, not an arithmetic one,
12324 as we want the top N bits of C to be zero. */
12331 }
12333 /* If we are doing a sign bit comparison, it means we are testing
12334 a particular bit. Convert it to the appropriate AND. */
12337 {
12339 (HOST_WIDE_INT_1U
12344 }
12346 /* If this an equality comparison with zero and we are shifting
12347 the low bit to the sign bit, we can convert this to an AND of the
12348 low-order bit. */
12352 {
12355 }
12359 /* If this is an equality comparison with zero, we can do this
12360 as a logical shift, which might be much simpler. */
12363 {
12368 }
12370 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12371 do the comparison in a narrower mode. */
12381 {
12384 }
12386 /* Likewise if OP0 is a PLUS of a sign extension with a
12387 constant, which is usually represented with the PLUS
12388 between the shifts. */
12400 {
12408 new_const);
12410 }
12412 /* FALLTHROUGH */
12414 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12415 the low order N bits of FOO are known to be zero, we can do this
12416 by comparing FOO with C shifted left N bits so long as no
12417 overflow occurs. Even if the low order N bits of FOO aren't known
12418 to be zero, if the comparison is >= or < we can use the same
12419 optimization and for > or <= by setting all the low
12420 order N bits in the comparison constant. */
12431 {
12432 unsigned HOST_WIDE_INT low_bits
12434 & ((HOST_WIDE_INT_1U
12437 {
12438 /* If the shift was logical, then we must make the condition
12439 unsigned. */
12447 const_op
12452 }
12453 }
12455 /* If we are using this shift to extract just the sign bit, we
12456 can replace this with an LT or GE comparison. */
12461 {
12465 }
12470 }
12473 }
12475 /* Now make any compound operations involved in this comparison. Then,
12476 check for an outmost SUBREG on OP0 that is not doing anything or is
12477 paradoxical. The latter transformation must only be performed when
12478 it is known that the "extra" bits will be the same in op0 and op1 or
12479 that they don't matter. There are three cases to consider:
12481 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12482 care bits and we can assume they have any convenient value. So
12483 making the transformation is safe.
12485 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12486 In this case the upper bits of op0 are undefined. We should not make
12487 the simplification in that case as we do not know the contents of
12488 those bits.
12490 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12491 In that case we know those bits are zeros or ones. We must also be
12492 sure that they are the same as the upper bits of op1.
12494 We can never remove a SUBREG for a non-equality comparison because
12495 the sign bit is in a different place in the underlying object. */
12508 {
12510 {
12511 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12512 implemented. */
12514 {
12517 }
12518 }
12524 {
12530 }
12531 }
12533 /* We now do the opposite procedure: Some machines don't have compare
12534 insns in all modes. If OP0's mode is an integer mode smaller than a
12535 word and we can't do a compare in that mode, see if there is a larger
12536 mode for which we can do the compare. There are a number of cases in
12537 which we can use the wider mode. */
12547 {
12550 /* If this is a test for negative, we can make an explicit
12551 test of the sign bit. Test this first so we can use
12552 a paradoxical subreg to extend OP0. */
12556 {
12557 unsigned HOST_WIDE_INT sign
12564 }
12566 /* If the only nonzero bits in OP0 and OP1 are those in the
12567 narrower mode and this is an equality or unsigned comparison,
12568 we can use the wider mode. Similarly for sign-extended
12569 values, in which case it is true for all comparisons. */
12586 {
12587 /* If OP0 is an AND and we don't have an AND in MODE either,
12588 make a new AND in the proper mode. */
12596 else
12597 {
12599 {
12602 }
12603 else
12604 {
12607 }
12609 }
12610 }
12611 }
12613 /* We may have changed the comparison operands. Re-canonicalize. */
12615 {
12618 }
12620 /* If this machine only supports a subset of valid comparisons, see if we
12621 can convert an unsupported one into a supported one. */
12628 }
12629 \f
12630 /* Utility function for record_value_for_reg. Count number of
12631 rtxs in X. */
12632 static int
12634 {
12641 {
12661 }
12672 }
12673 \f
12674 /* Utility function for following routine. Called when X is part of a value
12675 being stored into last_set_value. Sets last_set_table_tick
12676 for each register mentioned. Similar to mention_regs in cse.c */
12678 static void
12680 {
12686 {
12692 {
12695 }
12698 }
12702 {
12703 /* Check for identical subexpressions. If x contains
12704 identical subexpression we only have to traverse one of
12705 them. */
12707 {
12708 /* Note that at this point x1 has already been
12709 processed. */
12713 /* If x0 and x1 are identical then there is no need to
12714 process x0. */
12718 /* If x0 is identical to a subexpression of x1 then while
12719 processing x1, x0 has already been processed. Thus we
12720 are done with x. */
12725 /* If x1 is identical to a subexpression of x0 then we
12726 still have to process the rest of x0. */
12729 {
12732 }
12733 }
12736 }
12740 }
12742 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12743 are saying that the register is clobbered and we no longer know its
12744 value. If INSN is zero, don't update reg_stat[].last_set; this is
12745 only permitted with VALUE also zero and is used to invalidate the
12746 register. */
12748 static void
12750 {
12756 /* If VALUE contains REG and we have a previous value for REG, substitute
12757 the previous value. */
12759 {
12760 rtx tem;
12762 /* Set things up so get_last_value is allowed to see anything set up to
12763 our insn. */
12767 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12768 it isn't going to be useful and will take a lot of time to process,
12769 so just use the CLOBBER. */
12772 {
12778 {
12779 /* If there are two or more occurrences of REG in VALUE,
12780 prevent the value from growing too much. */
12783 }
12786 }
12787 }
12789 /* For each register modified, show we don't know its value, that
12790 we don't know about its bitwise content, that its value has been
12791 updated, and that we don't know the location of the death of the
12792 register. */
12794 {
12806 }
12808 /* Mark registers that are being referenced in this value. */
12812 /* Now update the status of each register being set.
12813 If someone is using this register in this block, set this register
12814 to invalid since we will get confused between the two lives in this
12815 basic block. This makes using this register always invalid. In cse, we
12816 scan the table to invalidate all entries using this register, but this
12817 is too much work for us. */
12820 {
12826 else
12828 }
12830 /* The value being assigned might refer to X (like in "x++;"). In that
12831 case, we must replace it with (clobber (const_int 0)) to prevent
12832 infinite loops. */
12835 {
12839 }
12841 /* For the main register being modified, update the value, the mode, the
12842 nonzero bits, and the number of sign bit copies. */
12847 {
12855 rsp->last_set_sign_bit_copies
12857 }
12858 }
12860 /* Called via note_stores from record_dead_and_set_regs to handle one
12861 SET or CLOBBER in an insn. DATA is the instruction in which the
12862 set is occurring. */
12864 static void
12866 {
12873 {
12877 }
12880 {
12881 /* If we are setting the whole register, we know its value. Otherwise
12882 show that we don't know the value. We can handle SUBREG in
12883 some cases. */
12894 else
12896 }
12898 /* Ignore pushes, they clobber nothing. */
12901 }
12903 /* Update the records of when each REG was most recently set or killed
12904 for the things done by INSN. This is the last thing done in processing
12905 INSN in the combiner loop.
12907 We update reg_stat[], in particular fields last_set, last_set_value,
12908 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12909 last_death, and also the similar information mem_last_set (which insn
12910 most recently modified memory) and last_call_luid (which insn was the
12911 most recent subroutine call). */
12913 static void
12915 {
12916 rtx link;
12920 {
12923 {
12928 {
12933 }
12934 }
12937 }
12940 {
12941 hard_reg_set_iterator hrsi;
12943 {
12955 }
12959 /* We can't combine into a call pattern. Remember, though, that
12960 the return value register is set at this LUID. We could
12961 still replace a register with the return value from the
12962 wrong subroutine call! */
12964 }
12965 else
12967 }
12969 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12970 register present in the SUBREG, so for each such SUBREG go back and
12971 adjust nonzero and sign bit information of the registers that are
12972 known to have some zero/sign bits set.
12974 This is needed because when combine blows the SUBREGs away, the
12975 information on zero/sign bits is lost and further combines can be
12976 missed because of that. */
12978 static void
12980 {
12982 rtx set;
12990 {
12999 {
13002 }
13006 {
13009 }
13012 {
13015 }
13016 else
13018 }
13019 }
13021 /* Check if X, a register, is known to contain a value already
13022 truncated to MODE. In this case we can use a subreg to refer to
13023 the truncated value even though in the generic case we would need
13024 an explicit truncation. */
13026 static bool
13028 {
13040 }
13042 /* If X is a hard reg or a subreg record the mode that the register is
13043 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13044 to turn a truncate into a subreg using this information. Return true
13045 if traversing X is complete. */
13047 static bool
13049 {
13050 machine_mode truncated_mode;
13054 {
13065 }
13066 /* ??? For hard-regs we now record everything. We might be able to
13067 optimize this using last_set_mode. */
13070 else
13078 {
13081 }
13084 }
13086 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13087 the modes they are used in. This can help truning TRUNCATEs into
13088 SUBREGs. */
13090 static void
13092 {
13097 }
13099 /* Scan X for promoted SUBREGs. For each one found,
13100 note what it implies to the registers used in it. */
13102 static void
13104 {
13109 else
13110 {
13116 {
13126 }
13127 }
13128 }
13129 \f
13130 /* Verify that all the registers and memory references mentioned in *LOC are
13131 still valid. *LOC was part of a value set in INSN when label_tick was
13132 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13133 the invalid references with (clobber (const_int 0)) and return 1. This
13134 replacement is useful because we often can get useful information about
13135 the form of a value (e.g., if it was produced by a shift that always
13136 produces -1 or 0) even though we don't know exactly what registers it
13137 was produced from. */
13139 static int
13141 {
13148 {
13154 {
13157 /* If this is a pseudo-register that was only set once and not
13158 live at the beginning of the function, it is always valid. */
13162 && (!REGNO_REG_SET_P
13164 regno)))
13166 {
13170 }
13171 }
13174 }
13175 /* If this is a memory reference, make sure that there were no stores after
13176 it that might have clobbered the value. We don't have alias info, so we
13177 assume any store invalidates it. Moreover, we only have local UIDs, so
13178 we also assume that there were stores in the intervening basic blocks. */
13181 {
13185 }
13188 {
13190 {
13191 /* Check for identical subexpressions. If x contains
13192 identical subexpression we only have to traverse one of
13193 them. */
13195 {
13196 /* Note that at this point x0 has already been checked
13197 and found valid. */
13201 /* If x0 and x1 are identical then x is also valid. */
13205 /* If x1 is identical to a subexpression of x0 then
13206 while checking x0, x1 has already been checked. Thus
13207 it is valid and so as x. */
13212 /* If x0 is identical to a subexpression of x1 then x is
13213 valid iff the rest of x1 is valid. */
13216 return
13220 }
13225 }
13231 }
13233 /* If we haven't found a reason for it to be invalid, it is valid. */
13235 }
13237 /* Get the last value assigned to X, if known. Some registers
13238 in the value may be replaced with (clobber (const_int 0)) if their value
13239 is known longer known reliably. */
13241 static rtx
13243 {
13245 rtx value;
13248 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13249 then convert it to the desired mode. If this is a paradoxical SUBREG,
13250 we cannot predict what values the "extra" bits might have. */
13264 /* If we don't have a value, or if it isn't for this basic block and
13265 it's either a hard register, set more than once, or it's a live
13266 at the beginning of the function, return 0.
13268 Because if it's not live at the beginning of the function then the reg
13269 is always set before being used (is never used without being set).
13270 And, if it's set only once, and it's always set before use, then all
13271 uses must have the same last value, even if it's not from this basic
13272 block. */
13279 || REGNO_REG_SET_P
13283 /* If the value was set in a later insn than the ones we are processing,
13284 we can't use it even if the register was only set once. */
13289 /* If fewer bits were set than what we are asked for now, we cannot use
13290 the value. */
13295 /* If the value has all its registers valid, return it. */
13299 /* Otherwise, make a copy and replace any invalid register with
13300 (clobber (const_int 0)). If that fails for some reason, return 0. */
13307 }
13308 \f
13309 /* Return nonzero if expression X refers to a REG or to memory
13310 that is set in an instruction more recent than FROM_LUID. */
13312 static int
13314 {
13320 {
13324 #ifdef PUSH_ROUNDING
13325 /* Don't allow uses of the stack pointer to be moved,
13326 because we don't know whether the move crosses a push insn. */
13329 #endif
13331 {
13337 }
13339 }
13347 {
13349 {
13354 }
13358 }
13360 }
13361 \f
13362 /* Define three variables used for communication between the following
13363 routines. */
13368 /* Function called via note_stores from reg_dead_at_p.
13370 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13371 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13373 static void
13375 {
13385 }
13387 /* Return nonzero if REG is known to be dead at INSN.
13389 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13390 referencing REG, it is dead. If we hit a SET referencing REG, it is
13391 live. Otherwise, see if it is live or dead at the start of the basic
13392 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13393 must be assumed to be always live. */
13395 static int
13397 {
13398 basic_block block;
13401 /* Set variables for reg_dead_at_p_1. */
13407 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13408 we allow the machine description to decide whether use-and-clobber
13409 patterns are OK. */
13411 {
13415 }
13417 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13418 beginning of basic block. */
13421 {
13423 {
13433 }
13439 }
13441 /* Look at live-in sets for the basic block that we were in. */
13447 }
13448 \f
13449 /* Note hard registers in X that are used. */
13451 static void
13453 {
13459 {
13463 CASE_CONST_ANY:
13468 /* CC0 must die in the insn after it is set, so we don't need to take
13469 special note of it here. */
13474 /* If we are clobbering a MEM, mark any hard registers inside the
13475 address as used. */
13482 /* A hard reg in a wide mode may really be multiple registers.
13483 If so, mark all of them just like the first. */
13485 {
13486 /* None of this applies to the stack, frame or arg pointers. */
13488 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13496 }
13500 {
13501 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13502 the address. */
13514 }
13519 }
13521 /* Recursively scan the operands of this expression. */
13523 {
13527 {
13531 {
13536 }
13537 }
13538 }
13539 }
13540 \f
13541 /* Remove register number REGNO from the dead registers list of INSN.
13543 Return the note used to record the death, if there was one. */
13545 rtx
13547 {
13554 }
13556 /* For each register (hardware or pseudo) used within expression X, if its
13557 death is in an instruction with luid between FROM_LUID (inclusive) and
13558 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13559 list headed by PNOTES.
13561 That said, don't move registers killed by maybe_kill_insn.
13563 This is done when X is being merged by combination into TO_INSN. These
13564 notes will then be distributed as needed. */
13566 static void
13569 {
13575 {
13579 /* Don't move the register if it gets killed in between from and to. */
13588 {
13591 /* It is possible for the call above to return 0. This can occur
13592 when last_death points to I2 or I1 that we combined with.
13593 In that case make a new note.
13595 We must also check for the case where X is a hard register
13596 and NOTE is a death note for a range of hard registers
13597 including X. In that case, we must put REG_DEAD notes for
13598 the remaining registers in place of NOTE. */
13603 {
13612 }
13614 /* If we didn't find any note, or if we found a REG_DEAD note that
13615 covers only part of the given reg, and we have a multi-reg hard
13616 register, then to be safe we must check for REG_DEAD notes
13617 for each register other than the first. They could have
13618 their own REG_DEAD notes lying around. */
13625 {
13632 else
13638 }
13641 {
13644 }
13645 else
13647 }
13650 }
13653 {
13658 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13659 that accesses one word of a multi-word item, some
13660 piece of everything register in the expression is used by
13661 this insn, so remove any old death. */
13662 /* ??? So why do we test for equality of the sizes? */
13671 {
13674 }
13676 /* If this is some other SUBREG, we know it replaces the entire
13677 value, so use that as the destination. */
13681 /* If this is a MEM, adjust deaths of anything used in the address.
13682 For a REG (the only other possibility), the entire value is
13683 being replaced so the old value is not used in this insn. */
13689 }
13698 {
13700 {
13705 }
13708 }
13709 }
13710 \f
13711 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13712 pattern of an insn. X must be a REG. */
13714 static int
13716 {
13720 {
13722 rtx target;
13729 else
13746 }
13754 }
13755 \f
13756 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13757 as appropriate. I3 and I2 are the insns resulting from the combination
13758 insns including FROM (I2 may be zero).
13760 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13761 not need REG_DEAD notes because they are being substituted for. This
13762 saves searching in the most common cases.
13764 Each note in the list is either ignored or placed on some insns, depending
13765 on the type of note. */
13767 static void
13770 {
13772 rtx tem_note;
13776 {
13781 {
13784 /* Doesn't matter much where we put this, as long as it's somewhere.
13785 It is preferable to keep these notes on branches, which is most
13786 likely to be i3. */
13793 else
13794 {
13797 }
13801 /* These notes must remain with the call or trapping instruction. */
13806 else
13807 {
13813 /* ??? Otherwise assume we've combined things such that we
13814 can now prove that the instructions can't trap. Drop the
13815 note in this case. */
13816 }
13820 /* ??? How to distribute between i3-i1. Assume i3 contains the
13821 entire adjustment. Assert i3 contains at least some adjust. */
13823 {
13825 /* fixup_args_size_notes looks at REG_NORETURN note,
13826 so ensure the note is placed there first. */
13828 {
13832 {
13838 }
13839 }
13841 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13842 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13845 && !ACCUMULATE_OUTGOING_ARGS
13847 }
13854 /* These notes must remain with the call. It should not be
13855 possible for both I2 and I3 to be a call. */
13858 else
13859 {
13862 }
13866 /* Any clobbers for i3 may still exist, and so we must process
13867 REG_UNUSED notes from that insn.
13869 Any clobbers from i2 or i1 can only exist if they were added by
13870 recog_for_combine. In that case, recog_for_combine created the
13871 necessary REG_UNUSED notes. Trying to keep any original
13872 REG_UNUSED notes from these insns can cause incorrect output
13873 if it is for the same register as the original i3 dest.
13874 In that case, we will notice that the register is set in i3,
13875 and then add a REG_UNUSED note for the destination of i3, which
13876 is wrong. However, it is possible to have REG_UNUSED notes from
13877 i2 or i1 for register which were both used and clobbered, so
13878 we keep notes from i2 or i1 if they will turn into REG_DEAD
13879 notes. */
13881 /* If this register is set or clobbered in I3, put the note there
13882 unless there is one already. */
13884 {
13892 }
13893 /* Otherwise, if this register is used by I3, then this register
13894 now dies here, so we must put a REG_DEAD note here unless there
13895 is one already. */
13901 {
13904 }
13910 /* These notes say something about results of an insn. We can
13911 only support them if they used to be on I3 in which case they
13912 remain on I3. Otherwise they are ignored.
13914 If the note refers to an expression that is not a constant, we
13915 must also ignore the note since we cannot tell whether the
13916 equivalence is still true. It might be possible to do
13917 slightly better than this (we only have a problem if I2DEST
13918 or I1DEST is present in the expression), but it doesn't
13919 seem worth the trouble. */
13927 /* These notes say something about how a register is used. They must
13928 be present on any use of the register in I2 or I3. */
13933 {
13936 else
13938 }
13943 /* This can show up in several ways -- either directly in the
13944 pattern, or hidden off in the constant pool with (or without?)
13945 a REG_EQUAL note. */
13946 /* ??? Ignore the without-reg_equal-note problem for now. */
13958 {
13961 else
13963 }
13965 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13966 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13967 there. */
13972 {
13979 }
13985 {
13993 }
13997 /* This note says something about the value of a register prior
13998 to the execution of an insn. It is too much trouble to see
13999 if the note is still correct in all situations. It is better
14000 to simply delete it. */
14004 /* If we replaced the right hand side of FROM_INSN with a
14005 REG_EQUAL note, the original use of the dying register
14006 will not have been combined into I3 and I2. In such cases,
14007 FROM_INSN is guaranteed to be the first of the combined
14008 instructions, so we simply need to search back before
14009 FROM_INSN for the previous use or set of this register,
14010 then alter the notes there appropriately.
14012 If the register is used as an input in I3, it dies there.
14013 Similarly for I2, if it is nonzero and adjacent to I3.
14015 If the register is not used as an input in either I3 or I2
14016 and it is not one of the registers we were supposed to eliminate,
14017 there are two possibilities. We might have a non-adjacent I2
14018 or we might have somehow eliminated an additional register
14019 from a computation. For example, we might have had A & B where
14020 we discover that B will always be zero. In this case we will
14021 eliminate the reference to A.
14023 In both cases, we must search to see if we can find a previous
14024 use of A and put the death note there. */
14030 else
14031 {
14042 && !(i2mod
14044 i2mod_old_rhs)))
14049 /* If the new I2 sets the same register that is marked dead
14050 in the note, we do not know where to put the note.
14051 Give up. */
14054 }
14057 {
14061 {
14063 {
14067 }
14069 /* If the register is being set at TEM_INSN, see if that is all
14070 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14071 into a REG_UNUSED note instead. Don't delete sets to
14072 global register vars. */
14076 {
14087 ;
14089 /* Verify that it was the set, and not a clobber that
14090 modified the register.
14092 CC0 targets must be careful to maintain setter/user
14093 pairs. If we cannot delete the setter due to side
14094 effects, mark the user with an UNUSED note instead
14095 of deleting it. */
14099 && (!HAVE_cc0
14103 {
14104 /* Move the notes and links of TEM_INSN elsewhere.
14105 This might delete other dead insns recursively.
14106 First set the pattern to something that won't use
14107 any register. */
14121 /* Delete the setter too. */
14123 {
14136 }
14137 }
14138 else
14139 {
14142 /* If there isn't already a REG_UNUSED note, put one
14143 here. Do not place a REG_DEAD note, even if
14144 the register is also used here; that would not
14145 match the algorithm used in lifetime analysis
14146 and can cause the consistency check in the
14147 scheduler to fail. */
14152 }
14153 }
14157 {
14160 /* If we are doing a 3->2 combination, and we have a
14161 register which formerly died in i3 and was not used
14162 by i2, which now no longer dies in i3 and is used in
14163 i2 but does not die in i2, and place is between i2
14164 and i3, then we may need to move a link from place to
14165 i2. */
14167 && from_insn
14170 {
14174 }
14176 }
14180 }
14182 }
14184 /* If the register is set or already dead at PLACE, we needn't do
14185 anything with this note if it is still a REG_DEAD note.
14186 We check here if it is set at all, not if is it totally replaced,
14187 which is what `dead_or_set_p' checks, so also check for it being
14188 set partially. */
14191 {
14197 {
14198 /* Unless the register previously died in PLACE, clear
14199 last_death. [I no longer understand why this is
14200 being done.] */
14204 }
14205 else
14208 /* If this is a death note for a hard reg that is occupying
14209 multiple registers, ensure that we are still using all
14210 parts of the object. If we find a piece of the object
14211 that is unused, we must arrange for an appropriate REG_DEAD
14212 note to be added for it. However, we can't just emit a USE
14213 and tag the note to it, since the register might actually
14214 be dead; so we recourse, and the recursive call then finds
14215 the previous insn that used this register. */
14218 {
14227 {
14230 }
14233 {
14234 /* Put only REG_DEAD notes for pieces that are
14235 not already dead or set. */
14239 {
14246 {
14248 NULL_RTX);
14252 NULL_RTX);
14253 }
14258 {
14260 {
14264 }
14268 {
14271 }
14272 }
14273 }
14276 }
14277 }
14278 }
14282 /* Any other notes should not be present at this point in the
14283 compilation. */
14285 }
14288 {
14291 }
14295 }
14296 }
14297 \f
14298 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14299 I3, I2, and I1 to new locations. This is also called to add a link
14300 pointing at I3 when I3's destination is changed. */
14302 static void
14304 {
14308 {
14315 /* If the insn that this link points to is a NOTE, ignore it. */
14324 {
14327 {
14343 }
14346 }
14347 else
14357 /* A LOG_LINK is defined as being placed on the first insn that uses
14358 a register and points to the insn that sets the register. Start
14359 searching at the next insn after the target of the link and stop
14360 when we reach a set of the register or the end of the basic block.
14362 Note that this correctly handles the link that used to point from
14363 I3 to I2. Also note that not much searching is typically done here
14364 since most links don't point very far away. */
14373 {
14377 }
14380 {
14383 }
14387 /* If we found a place to put the link, place it there unless there
14388 is already a link to the same insn as LINK at that point. */
14391 {
14399 {
14403 /* Set added_links_insn to the earliest insn we added a
14404 link to. */
14408 }
14409 }
14410 }
14411 }
14412 \f
14413 /* Check for any register or memory mentioned in EQUIV that is not
14414 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14415 of EXPR where some registers may have been replaced by constants. */
14417 static bool
14419 {
14422 {
14427 }
14429 }
14430 \f
14431 DEBUG_FUNCTION void
14433 {
14434 fprintf
14436 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14438 }
14440 void
14442 {
14443 fprintf
14445 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14447 }
14448 \f
14449 /* Try combining insns through substitution. */
14450 static unsigned int
14452 {
14462 rebuild_jump_labels_after_combine
14465 /* Combining insns may have turned an indirect jump into a
14466 direct jump. Rebuild the JUMP_LABEL fields of jumping
14467 instructions. */
14469 {
14476 }
14480 }
14485 {
14495 };
14498 {
14502 {}
14504 /* opt_pass methods: */
14507 {
14509 }
14515 rtl_opt_pass *
14517 {
14519 }