2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
31 (UNSPEC_VMHRADDSHS 72)
68 (UNSPEC_VPERM_UNS 145)
78 (UNSPEC_VRSQRTEFP 157)
100 (UNSPEC_GET_VRSAVE 214)
102 (UNSPEC_REDUC_PLUS 217)
104 (UNSPEC_EXTEVEN_V4SI 220)
105 (UNSPEC_EXTEVEN_V8HI 221)
106 (UNSPEC_EXTEVEN_V16QI 222)
107 (UNSPEC_EXTEVEN_V4SF 223)
108 (UNSPEC_EXTODD_V4SI 224)
109 (UNSPEC_EXTODD_V8HI 225)
110 (UNSPEC_EXTODD_V16QI 226)
111 (UNSPEC_EXTODD_V4SF 227)
112 (UNSPEC_INTERHI_V4SI 228)
113 (UNSPEC_INTERHI_V8HI 229)
114 (UNSPEC_INTERHI_V16QI 230)
116 (UNSPEC_INTERLO_V4SI 232)
117 (UNSPEC_INTERLO_V8HI 233)
118 (UNSPEC_INTERLO_V16QI 234)
128 (UNSPEC_VMULWHUB 308)
129 (UNSPEC_VMULWLUB 309)
130 (UNSPEC_VMULWHSB 310)
131 (UNSPEC_VMULWLSB 311)
132 (UNSPEC_VMULWHUH 312)
133 (UNSPEC_VMULWLUH 313)
134 (UNSPEC_VMULWHSH 314)
135 (UNSPEC_VMULWLSH 315)
144 (UNSPEC_VUPKHS_V4SF 324)
145 (UNSPEC_VUPKLS_V4SF 325)
146 (UNSPEC_VUPKHU_V4SF 326)
147 (UNSPEC_VUPKLU_V4SF 327)
151 [(UNSPECV_SET_VRSAVE 30)
159 (define_mode_iterator VI [V4SI V8HI V16QI])
160 ;; Short vec in modes
161 (define_mode_iterator VIshort [V8HI V16QI])
163 (define_mode_iterator VF [V4SF])
164 ;; Vec modes, pity mode iterators are not composable
165 (define_mode_iterator V [V4SI V8HI V16QI V4SF])
166 ;; Vec modes for move/logical/permute ops, include vector types for move not
167 ;; otherwise handled by altivec (v2df, v2di, ti)
168 (define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI])
170 ;; Like VM, except don't do TImode
171 (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])
173 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
175 ;; Vector move instructions.
176 (define_insn "*altivec_mov<mode>"
177 [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*o,*r,*r,v,v")
178 (match_operand:VM2 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
179 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)
180 && (register_operand (operands[0], <MODE>mode)
181 || register_operand (operands[1], <MODE>mode))"
183 switch (which_alternative)
185 case 0: return "stvx %1,%y0";
186 case 1: return "lvx %0,%y1";
187 case 2: return "vor %0,%1,%1";
191 case 6: return "vxor %0,%0,%0";
192 case 7: return output_vec_const_move (operands);
193 default: gcc_unreachable ();
196 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
198 ;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
199 ;; is for unions. However for plain data movement, slightly favor the vector
201 (define_insn "*altivec_movti"
202 [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,v,v,?o,?r,?r,v,v")
203 (match_operand:TI 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
204 "VECTOR_MEM_ALTIVEC_P (TImode)
205 && (register_operand (operands[0], TImode)
206 || register_operand (operands[1], TImode))"
208 switch (which_alternative)
210 case 0: return "stvx %1,%y0";
211 case 1: return "lvx %0,%y1";
212 case 2: return "vor %0,%1,%1";
216 case 6: return "vxor %0,%0,%0";
217 case 7: return output_vec_const_move (operands);
218 default: gcc_unreachable ();
221 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
223 ;; Load up a vector with the most significant bit set by loading up -1 and
224 ;; doing a shift left
226 [(set (match_operand:VM 0 "altivec_register_operand" "")
227 (match_operand:VM 1 "easy_vector_constant_msb" ""))]
228 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode) && reload_completed"
231 rtx dest = operands[0];
232 enum machine_mode mode = GET_MODE (operands[0]);
236 if (mode == V4SFmode)
239 dest = gen_lowpart (V4SImode, dest);
242 num_elements = GET_MODE_NUNITS (mode);
243 v = rtvec_alloc (num_elements);
244 for (i = 0; i < num_elements; i++)
245 RTVEC_ELT (v, i) = constm1_rtx;
247 emit_insn (gen_vec_initv4si (dest, gen_rtx_PARALLEL (mode, v)));
248 emit_insn (gen_rtx_SET (VOIDmode, dest, gen_rtx_ASHIFT (mode, dest, dest)));
253 [(set (match_operand:VM 0 "altivec_register_operand" "")
254 (match_operand:VM 1 "easy_vector_constant_add_self" ""))]
255 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode) && reload_completed"
256 [(set (match_dup 0) (match_dup 3))
257 (set (match_dup 0) (match_dup 4))]
259 rtx dup = gen_easy_altivec_constant (operands[1]);
261 enum machine_mode op_mode = <MODE>mode;
263 /* Divide the operand of the resulting VEC_DUPLICATE, and use
264 simplify_rtx to make a CONST_VECTOR. */
265 XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
266 XEXP (dup, 0), const1_rtx);
267 const_vec = simplify_rtx (dup);
269 if (op_mode == V4SFmode)
272 operands[0] = gen_lowpart (op_mode, operands[0]);
274 if (GET_MODE (const_vec) == op_mode)
275 operands[3] = const_vec;
277 operands[3] = gen_lowpart (op_mode, const_vec);
278 operands[4] = gen_rtx_PLUS (op_mode, operands[0], operands[0]);
281 (define_insn "get_vrsave_internal"
282 [(set (match_operand:SI 0 "register_operand" "=r")
283 (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
287 return "mfspr %0,256";
289 return "mfvrsave %0";
291 [(set_attr "type" "*")])
293 (define_insn "*set_vrsave_internal"
294 [(match_parallel 0 "vrsave_operation"
296 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
297 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
301 return "mtspr 256,%1";
303 return "mtvrsave %1";
305 [(set_attr "type" "*")])
307 (define_insn "*save_world"
308 [(match_parallel 0 "save_world_operation"
309 [(clobber (reg:SI 65))
310 (use (match_operand:SI 1 "call_operand" "s"))])]
311 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
313 [(set_attr "type" "branch")
314 (set_attr "length" "4")])
316 (define_insn "*restore_world"
317 [(match_parallel 0 "restore_world_operation"
320 (use (match_operand:SI 1 "call_operand" "s"))
321 (clobber (match_operand:SI 2 "gpc_reg_operand" "=r"))])]
322 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
325 ;; Simple binary operations.
328 (define_insn "add<mode>3"
329 [(set (match_operand:VI 0 "register_operand" "=v")
330 (plus:VI (match_operand:VI 1 "register_operand" "v")
331 (match_operand:VI 2 "register_operand" "v")))]
333 "vaddu<VI_char>m %0,%1,%2"
334 [(set_attr "type" "vecsimple")])
336 (define_insn "*altivec_addv4sf3"
337 [(set (match_operand:V4SF 0 "register_operand" "=v")
338 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
339 (match_operand:V4SF 2 "register_operand" "v")))]
340 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
342 [(set_attr "type" "vecfloat")])
344 (define_insn "altivec_vaddcuw"
345 [(set (match_operand:V4SI 0 "register_operand" "=v")
346 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
347 (match_operand:V4SI 2 "register_operand" "v")]
351 [(set_attr "type" "vecsimple")])
353 (define_insn "altivec_vaddu<VI_char>s"
354 [(set (match_operand:VI 0 "register_operand" "=v")
355 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
356 (match_operand:VI 2 "register_operand" "v")]
358 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
360 "vaddu<VI_char>s %0,%1,%2"
361 [(set_attr "type" "vecsimple")])
363 (define_insn "altivec_vadds<VI_char>s"
364 [(set (match_operand:VI 0 "register_operand" "=v")
365 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
366 (match_operand:VI 2 "register_operand" "v")]
368 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
370 "vadds<VI_char>s %0,%1,%2"
371 [(set_attr "type" "vecsimple")])
374 (define_insn "sub<mode>3"
375 [(set (match_operand:VI 0 "register_operand" "=v")
376 (minus:VI (match_operand:VI 1 "register_operand" "v")
377 (match_operand:VI 2 "register_operand" "v")))]
379 "vsubu<VI_char>m %0,%1,%2"
380 [(set_attr "type" "vecsimple")])
382 (define_insn "*altivec_subv4sf3"
383 [(set (match_operand:V4SF 0 "register_operand" "=v")
384 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
385 (match_operand:V4SF 2 "register_operand" "v")))]
386 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
388 [(set_attr "type" "vecfloat")])
390 (define_insn "altivec_vsubcuw"
391 [(set (match_operand:V4SI 0 "register_operand" "=v")
392 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
393 (match_operand:V4SI 2 "register_operand" "v")]
397 [(set_attr "type" "vecsimple")])
399 (define_insn "altivec_vsubu<VI_char>s"
400 [(set (match_operand:VI 0 "register_operand" "=v")
401 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
402 (match_operand:VI 2 "register_operand" "v")]
404 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
406 "vsubu<VI_char>s %0,%1,%2"
407 [(set_attr "type" "vecsimple")])
409 (define_insn "altivec_vsubs<VI_char>s"
410 [(set (match_operand:VI 0 "register_operand" "=v")
411 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
412 (match_operand:VI 2 "register_operand" "v")]
414 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
416 "vsubs<VI_char>s %0,%1,%2"
417 [(set_attr "type" "vecsimple")])
420 (define_insn "altivec_vavgu<VI_char>"
421 [(set (match_operand:VI 0 "register_operand" "=v")
422 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
423 (match_operand:VI 2 "register_operand" "v")]
426 "vavgu<VI_char> %0,%1,%2"
427 [(set_attr "type" "vecsimple")])
429 (define_insn "altivec_vavgs<VI_char>"
430 [(set (match_operand:VI 0 "register_operand" "=v")
431 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
432 (match_operand:VI 2 "register_operand" "v")]
435 "vavgs<VI_char> %0,%1,%2"
436 [(set_attr "type" "vecsimple")])
438 (define_insn "altivec_vcmpbfp"
439 [(set (match_operand:V4SI 0 "register_operand" "=v")
440 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
441 (match_operand:V4SF 2 "register_operand" "v")]
445 [(set_attr "type" "veccmp")])
447 (define_insn "*altivec_eq<mode>"
448 [(set (match_operand:VI 0 "altivec_register_operand" "=v")
449 (eq:VI (match_operand:VI 1 "altivec_register_operand" "v")
450 (match_operand:VI 2 "altivec_register_operand" "v")))]
452 "vcmpequ<VI_char> %0,%1,%2"
453 [(set_attr "type" "veccmp")])
455 (define_insn "*altivec_gt<mode>"
456 [(set (match_operand:VI 0 "altivec_register_operand" "=v")
457 (gt:VI (match_operand:VI 1 "altivec_register_operand" "v")
458 (match_operand:VI 2 "altivec_register_operand" "v")))]
460 "vcmpgts<VI_char> %0,%1,%2"
461 [(set_attr "type" "veccmp")])
463 (define_insn "*altivec_gtu<mode>"
464 [(set (match_operand:VI 0 "altivec_register_operand" "=v")
465 (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v")
466 (match_operand:VI 2 "altivec_register_operand" "v")))]
468 "vcmpgtu<VI_char> %0,%1,%2"
469 [(set_attr "type" "veccmp")])
471 (define_insn "*altivec_eqv4sf"
472 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
473 (eq:V4SF (match_operand:V4SF 1 "altivec_register_operand" "v")
474 (match_operand:V4SF 2 "altivec_register_operand" "v")))]
475 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
477 [(set_attr "type" "veccmp")])
479 (define_insn "*altivec_gtv4sf"
480 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
481 (gt:V4SF (match_operand:V4SF 1 "altivec_register_operand" "v")
482 (match_operand:V4SF 2 "altivec_register_operand" "v")))]
483 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
485 [(set_attr "type" "veccmp")])
487 (define_insn "*altivec_gev4sf"
488 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
489 (ge:V4SF (match_operand:V4SF 1 "altivec_register_operand" "v")
490 (match_operand:V4SF 2 "altivec_register_operand" "v")))]
491 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
493 [(set_attr "type" "veccmp")])
495 (define_insn "*altivec_vsel<mode>"
496 [(set (match_operand:VM 0 "altivec_register_operand" "=v")
498 (ne:CC (match_operand:VM 1 "altivec_register_operand" "v")
500 (match_operand:VM 2 "altivec_register_operand" "v")
501 (match_operand:VM 3 "altivec_register_operand" "v")))]
502 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
504 [(set_attr "type" "vecperm")])
506 (define_insn "*altivec_vsel<mode>_uns"
507 [(set (match_operand:VM 0 "altivec_register_operand" "=v")
509 (ne:CCUNS (match_operand:VM 1 "altivec_register_operand" "v")
511 (match_operand:VM 2 "altivec_register_operand" "v")
512 (match_operand:VM 3 "altivec_register_operand" "v")))]
513 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
515 [(set_attr "type" "vecperm")])
517 ;; Fused multiply add
518 (define_insn "altivec_vmaddfp"
519 [(set (match_operand:V4SF 0 "register_operand" "=v")
520 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
521 (match_operand:V4SF 2 "register_operand" "v"))
522 (match_operand:V4SF 3 "register_operand" "v")))]
523 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
524 "vmaddfp %0,%1,%2,%3"
525 [(set_attr "type" "vecfloat")])
527 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
529 (define_expand "altivec_mulv4sf3"
530 [(use (match_operand:V4SF 0 "register_operand" ""))
531 (use (match_operand:V4SF 1 "register_operand" ""))
532 (use (match_operand:V4SF 2 "register_operand" ""))]
533 "VECTOR_UNIT_ALTIVEC_P (V4SFmode) && TARGET_FUSED_MADD"
538 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
539 neg0 = gen_reg_rtx (V4SImode);
540 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
541 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
543 /* Use the multiply-add. */
544 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
545 gen_lowpart (V4SFmode, neg0)));
549 ;; 32-bit integer multiplication
550 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
551 ;; A_low = Operand_0 & 0xFFFF
552 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
553 ;; B_low = Operand_1 & 0xFFFF
554 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
556 ;; (define_insn "mulv4si3"
557 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
558 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
559 ;; (match_operand:V4SI 2 "register_operand" "v")))]
560 (define_expand "mulv4si3"
561 [(use (match_operand:V4SI 0 "register_operand" ""))
562 (use (match_operand:V4SI 1 "register_operand" ""))
563 (use (match_operand:V4SI 2 "register_operand" ""))]
576 zero = gen_reg_rtx (V4SImode);
577 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
579 sixteen = gen_reg_rtx (V4SImode);
580 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
582 swap = gen_reg_rtx (V4SImode);
583 emit_insn (gen_vrotlv4si3 (swap, operands[2], sixteen));
585 one = gen_reg_rtx (V8HImode);
586 convert_move (one, operands[1], 0);
588 two = gen_reg_rtx (V8HImode);
589 convert_move (two, operands[2], 0);
591 small_swap = gen_reg_rtx (V8HImode);
592 convert_move (small_swap, swap, 0);
594 low_product = gen_reg_rtx (V4SImode);
595 emit_insn (gen_altivec_vmulouh (low_product, one, two));
597 high_product = gen_reg_rtx (V4SImode);
598 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
600 emit_insn (gen_vashlv4si3 (high_product, high_product, sixteen));
602 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
607 (define_expand "mulv8hi3"
608 [(use (match_operand:V8HI 0 "register_operand" ""))
609 (use (match_operand:V8HI 1 "register_operand" ""))
610 (use (match_operand:V8HI 2 "register_operand" ""))]
614 rtx odd = gen_reg_rtx (V4SImode);
615 rtx even = gen_reg_rtx (V4SImode);
616 rtx high = gen_reg_rtx (V4SImode);
617 rtx low = gen_reg_rtx (V4SImode);
619 emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2]));
620 emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2]));
622 emit_insn (gen_altivec_vmrghw (high, even, odd));
623 emit_insn (gen_altivec_vmrglw (low, even, odd));
625 emit_insn (gen_altivec_vpkuwum (operands[0], high, low));
630 ;; Fused multiply subtract
631 (define_insn "altivec_vnmsubfp"
632 [(set (match_operand:V4SF 0 "register_operand" "=v")
633 (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
634 (match_operand:V4SF 2 "register_operand" "v"))
635 (match_operand:V4SF 3 "register_operand" "v"))))]
636 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
637 "vnmsubfp %0,%1,%2,%3"
638 [(set_attr "type" "vecfloat")])
640 (define_insn "altivec_vmsumu<VI_char>m"
641 [(set (match_operand:V4SI 0 "register_operand" "=v")
642 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
643 (match_operand:VIshort 2 "register_operand" "v")
644 (match_operand:V4SI 3 "register_operand" "v")]
647 "vmsumu<VI_char>m %0,%1,%2,%3"
648 [(set_attr "type" "veccomplex")])
650 (define_insn "altivec_vmsumm<VI_char>m"
651 [(set (match_operand:V4SI 0 "register_operand" "=v")
652 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
653 (match_operand:VIshort 2 "register_operand" "v")
654 (match_operand:V4SI 3 "register_operand" "v")]
657 "vmsumm<VI_char>m %0,%1,%2,%3"
658 [(set_attr "type" "veccomplex")])
660 (define_insn "altivec_vmsumshm"
661 [(set (match_operand:V4SI 0 "register_operand" "=v")
662 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
663 (match_operand:V8HI 2 "register_operand" "v")
664 (match_operand:V4SI 3 "register_operand" "v")]
667 "vmsumshm %0,%1,%2,%3"
668 [(set_attr "type" "veccomplex")])
670 (define_insn "altivec_vmsumuhs"
671 [(set (match_operand:V4SI 0 "register_operand" "=v")
672 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
673 (match_operand:V8HI 2 "register_operand" "v")
674 (match_operand:V4SI 3 "register_operand" "v")]
676 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
678 "vmsumuhs %0,%1,%2,%3"
679 [(set_attr "type" "veccomplex")])
681 (define_insn "altivec_vmsumshs"
682 [(set (match_operand:V4SI 0 "register_operand" "=v")
683 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
684 (match_operand:V8HI 2 "register_operand" "v")
685 (match_operand:V4SI 3 "register_operand" "v")]
687 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
689 "vmsumshs %0,%1,%2,%3"
690 [(set_attr "type" "veccomplex")])
694 (define_insn "umax<mode>3"
695 [(set (match_operand:VI 0 "register_operand" "=v")
696 (umax:VI (match_operand:VI 1 "register_operand" "v")
697 (match_operand:VI 2 "register_operand" "v")))]
699 "vmaxu<VI_char> %0,%1,%2"
700 [(set_attr "type" "vecsimple")])
702 (define_insn "smax<mode>3"
703 [(set (match_operand:VI 0 "register_operand" "=v")
704 (smax:VI (match_operand:VI 1 "register_operand" "v")
705 (match_operand:VI 2 "register_operand" "v")))]
707 "vmaxs<VI_char> %0,%1,%2"
708 [(set_attr "type" "vecsimple")])
710 (define_insn "*altivec_smaxv4sf3"
711 [(set (match_operand:V4SF 0 "register_operand" "=v")
712 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
713 (match_operand:V4SF 2 "register_operand" "v")))]
714 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
716 [(set_attr "type" "veccmp")])
718 (define_insn "umin<mode>3"
719 [(set (match_operand:VI 0 "register_operand" "=v")
720 (umin:VI (match_operand:VI 1 "register_operand" "v")
721 (match_operand:VI 2 "register_operand" "v")))]
723 "vminu<VI_char> %0,%1,%2"
724 [(set_attr "type" "vecsimple")])
726 (define_insn "smin<mode>3"
727 [(set (match_operand:VI 0 "register_operand" "=v")
728 (smin:VI (match_operand:VI 1 "register_operand" "v")
729 (match_operand:VI 2 "register_operand" "v")))]
731 "vmins<VI_char> %0,%1,%2"
732 [(set_attr "type" "vecsimple")])
734 (define_insn "*altivec_sminv4sf3"
735 [(set (match_operand:V4SF 0 "register_operand" "=v")
736 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
737 (match_operand:V4SF 2 "register_operand" "v")))]
738 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
740 [(set_attr "type" "veccmp")])
742 (define_insn "altivec_vmhaddshs"
743 [(set (match_operand:V8HI 0 "register_operand" "=v")
744 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
745 (match_operand:V8HI 2 "register_operand" "v")
746 (match_operand:V8HI 3 "register_operand" "v")]
748 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
750 "vmhaddshs %0,%1,%2,%3"
751 [(set_attr "type" "veccomplex")])
753 (define_insn "altivec_vmhraddshs"
754 [(set (match_operand:V8HI 0 "register_operand" "=v")
755 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
756 (match_operand:V8HI 2 "register_operand" "v")
757 (match_operand:V8HI 3 "register_operand" "v")]
759 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
761 "vmhraddshs %0,%1,%2,%3"
762 [(set_attr "type" "veccomplex")])
764 (define_insn "altivec_vmladduhm"
765 [(set (match_operand:V8HI 0 "register_operand" "=v")
766 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
767 (match_operand:V8HI 2 "register_operand" "v")
768 (match_operand:V8HI 3 "register_operand" "v")]
771 "vmladduhm %0,%1,%2,%3"
772 [(set_attr "type" "veccomplex")])
774 (define_insn "altivec_vmrghb"
775 [(set (match_operand:V16QI 0 "register_operand" "=v")
776 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
777 (parallel [(const_int 0)
793 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
794 (parallel [(const_int 8)
813 [(set_attr "type" "vecperm")])
815 (define_insn "altivec_vmrghh"
816 [(set (match_operand:V8HI 0 "register_operand" "=v")
817 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
818 (parallel [(const_int 0)
826 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
827 (parallel [(const_int 4)
838 [(set_attr "type" "vecperm")])
840 (define_insn "altivec_vmrghw"
841 [(set (match_operand:V4SI 0 "register_operand" "=v")
842 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
843 (parallel [(const_int 0)
847 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
848 (parallel [(const_int 2)
853 "VECTOR_MEM_ALTIVEC_P (V4SImode)"
855 [(set_attr "type" "vecperm")])
857 (define_insn "*altivec_vmrghsf"
858 [(set (match_operand:V4SF 0 "register_operand" "=v")
859 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
860 (parallel [(const_int 0)
864 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
865 (parallel [(const_int 2)
870 "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
872 [(set_attr "type" "vecperm")])
874 (define_insn "altivec_vmrglb"
875 [(set (match_operand:V16QI 0 "register_operand" "=v")
876 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
877 (parallel [(const_int 8)
893 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
894 (parallel [(const_int 0)
913 [(set_attr "type" "vecperm")])
915 (define_insn "altivec_vmrglh"
916 [(set (match_operand:V8HI 0 "register_operand" "=v")
917 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
918 (parallel [(const_int 4)
926 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
927 (parallel [(const_int 0)
938 [(set_attr "type" "vecperm")])
940 (define_insn "altivec_vmrglw"
941 [(set (match_operand:V4SI 0 "register_operand" "=v")
943 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
944 (parallel [(const_int 2)
948 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
949 (parallel [(const_int 0)
954 "VECTOR_MEM_ALTIVEC_P (V4SImode)"
956 [(set_attr "type" "vecperm")])
958 (define_insn "*altivec_vmrglsf"
959 [(set (match_operand:V4SF 0 "register_operand" "=v")
961 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
962 (parallel [(const_int 2)
966 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
967 (parallel [(const_int 0)
972 "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
974 [(set_attr "type" "vecperm")])
976 (define_insn "altivec_vmuleub"
977 [(set (match_operand:V8HI 0 "register_operand" "=v")
978 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
979 (match_operand:V16QI 2 "register_operand" "v")]
983 [(set_attr "type" "veccomplex")])
985 (define_insn "altivec_vmulesb"
986 [(set (match_operand:V8HI 0 "register_operand" "=v")
987 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
988 (match_operand:V16QI 2 "register_operand" "v")]
992 [(set_attr "type" "veccomplex")])
994 (define_insn "altivec_vmuleuh"
995 [(set (match_operand:V4SI 0 "register_operand" "=v")
996 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
997 (match_operand:V8HI 2 "register_operand" "v")]
1001 [(set_attr "type" "veccomplex")])
1003 (define_insn "altivec_vmulesh"
1004 [(set (match_operand:V4SI 0 "register_operand" "=v")
1005 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1006 (match_operand:V8HI 2 "register_operand" "v")]
1010 [(set_attr "type" "veccomplex")])
1012 (define_insn "altivec_vmuloub"
1013 [(set (match_operand:V8HI 0 "register_operand" "=v")
1014 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1015 (match_operand:V16QI 2 "register_operand" "v")]
1019 [(set_attr "type" "veccomplex")])
1021 (define_insn "altivec_vmulosb"
1022 [(set (match_operand:V8HI 0 "register_operand" "=v")
1023 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1024 (match_operand:V16QI 2 "register_operand" "v")]
1028 [(set_attr "type" "veccomplex")])
1030 (define_insn "altivec_vmulouh"
1031 [(set (match_operand:V4SI 0 "register_operand" "=v")
1032 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1033 (match_operand:V8HI 2 "register_operand" "v")]
1037 [(set_attr "type" "veccomplex")])
1039 (define_insn "altivec_vmulosh"
1040 [(set (match_operand:V4SI 0 "register_operand" "=v")
1041 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1042 (match_operand:V8HI 2 "register_operand" "v")]
1046 [(set_attr "type" "veccomplex")])
1049 ;; logical ops. Have the logical ops follow the memory ops in
1050 ;; terms of whether to prefer VSX or Altivec
1052 (define_insn "*altivec_and<mode>3"
1053 [(set (match_operand:VM 0 "register_operand" "=v")
1054 (and:VM (match_operand:VM 1 "register_operand" "v")
1055 (match_operand:VM 2 "register_operand" "v")))]
1056 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1058 [(set_attr "type" "vecsimple")])
1060 (define_insn "*altivec_ior<mode>3"
1061 [(set (match_operand:VM 0 "register_operand" "=v")
1062 (ior:VM (match_operand:VM 1 "register_operand" "v")
1063 (match_operand:VM 2 "register_operand" "v")))]
1064 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1066 [(set_attr "type" "vecsimple")])
1068 (define_insn "*altivec_xor<mode>3"
1069 [(set (match_operand:VM 0 "register_operand" "=v")
1070 (xor:VM (match_operand:VM 1 "register_operand" "v")
1071 (match_operand:VM 2 "register_operand" "v")))]
1072 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1074 [(set_attr "type" "vecsimple")])
1076 (define_insn "*altivec_one_cmpl<mode>2"
1077 [(set (match_operand:VM 0 "register_operand" "=v")
1078 (not:VM (match_operand:VM 1 "register_operand" "v")))]
1079 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1081 [(set_attr "type" "vecsimple")])
1083 (define_insn "*altivec_nor<mode>3"
1084 [(set (match_operand:VM 0 "register_operand" "=v")
1085 (not:VM (ior:VM (match_operand:VM 1 "register_operand" "v")
1086 (match_operand:VM 2 "register_operand" "v"))))]
1087 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1089 [(set_attr "type" "vecsimple")])
1091 (define_insn "*altivec_andc<mode>3"
1092 [(set (match_operand:VM 0 "register_operand" "=v")
1093 (and:VM (not:VM (match_operand:VM 2 "register_operand" "v"))
1094 (match_operand:VM 1 "register_operand" "v")))]
1095 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1097 [(set_attr "type" "vecsimple")])
1099 (define_insn "altivec_vpkuhum"
1100 [(set (match_operand:V16QI 0 "register_operand" "=v")
1101 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1102 (match_operand:V8HI 2 "register_operand" "v")]
1106 [(set_attr "type" "vecperm")])
1108 (define_insn "altivec_vpkuwum"
1109 [(set (match_operand:V8HI 0 "register_operand" "=v")
1110 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1111 (match_operand:V4SI 2 "register_operand" "v")]
1115 [(set_attr "type" "vecperm")])
1117 (define_insn "altivec_vpkpx"
1118 [(set (match_operand:V8HI 0 "register_operand" "=v")
1119 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1120 (match_operand:V4SI 2 "register_operand" "v")]
1124 [(set_attr "type" "vecperm")])
1126 (define_insn "altivec_vpkshss"
1127 [(set (match_operand:V16QI 0 "register_operand" "=v")
1128 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1129 (match_operand:V8HI 2 "register_operand" "v")]
1131 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1134 [(set_attr "type" "vecperm")])
1136 (define_insn "altivec_vpkswss"
1137 [(set (match_operand:V8HI 0 "register_operand" "=v")
1138 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1139 (match_operand:V4SI 2 "register_operand" "v")]
1141 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1144 [(set_attr "type" "vecperm")])
1146 (define_insn "altivec_vpkuhus"
1147 [(set (match_operand:V16QI 0 "register_operand" "=v")
1148 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1149 (match_operand:V8HI 2 "register_operand" "v")]
1151 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1154 [(set_attr "type" "vecperm")])
1156 (define_insn "altivec_vpkshus"
1157 [(set (match_operand:V16QI 0 "register_operand" "=v")
1158 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1159 (match_operand:V8HI 2 "register_operand" "v")]
1161 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1164 [(set_attr "type" "vecperm")])
1166 (define_insn "altivec_vpkuwus"
1167 [(set (match_operand:V8HI 0 "register_operand" "=v")
1168 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1169 (match_operand:V4SI 2 "register_operand" "v")]
1171 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1174 [(set_attr "type" "vecperm")])
1176 (define_insn "altivec_vpkswus"
1177 [(set (match_operand:V8HI 0 "register_operand" "=v")
1178 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1179 (match_operand:V4SI 2 "register_operand" "v")]
1181 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1184 [(set_attr "type" "vecperm")])
1186 (define_insn "*altivec_vrl<VI_char>"
1187 [(set (match_operand:VI 0 "register_operand" "=v")
1188 (rotate:VI (match_operand:VI 1 "register_operand" "v")
1189 (match_operand:VI 2 "register_operand" "v")))]
1191 "vrl<VI_char> %0,%1,%2"
1192 [(set_attr "type" "vecsimple")])
1194 (define_insn "altivec_vsl"
1195 [(set (match_operand:V4SI 0 "register_operand" "=v")
1196 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1197 (match_operand:V4SI 2 "register_operand" "v")]
1201 [(set_attr "type" "vecperm")])
1203 (define_insn "altivec_vslo"
1204 [(set (match_operand:V4SI 0 "register_operand" "=v")
1205 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1206 (match_operand:V4SI 2 "register_operand" "v")]
1210 [(set_attr "type" "vecperm")])
1212 (define_insn "*altivec_vsl<VI_char>"
1213 [(set (match_operand:VI 0 "register_operand" "=v")
1214 (ashift:VI (match_operand:VI 1 "register_operand" "v")
1215 (match_operand:VI 2 "register_operand" "v")))]
1217 "vsl<VI_char> %0,%1,%2"
1218 [(set_attr "type" "vecsimple")])
1220 (define_insn "*altivec_vsr<VI_char>"
1221 [(set (match_operand:VI 0 "register_operand" "=v")
1222 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1223 (match_operand:VI 2 "register_operand" "v")))]
1225 "vsr<VI_char> %0,%1,%2"
1226 [(set_attr "type" "vecsimple")])
1228 (define_insn "*altivec_vsra<VI_char>"
1229 [(set (match_operand:VI 0 "register_operand" "=v")
1230 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1231 (match_operand:VI 2 "register_operand" "v")))]
1233 "vsra<VI_char> %0,%1,%2"
1234 [(set_attr "type" "vecsimple")])
1236 (define_insn "altivec_vsr"
1237 [(set (match_operand:V4SI 0 "register_operand" "=v")
1238 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1239 (match_operand:V4SI 2 "register_operand" "v")]
1243 [(set_attr "type" "vecperm")])
1245 (define_insn "altivec_vsro"
1246 [(set (match_operand:V4SI 0 "register_operand" "=v")
1247 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1248 (match_operand:V4SI 2 "register_operand" "v")]
1252 [(set_attr "type" "vecperm")])
1254 (define_insn "altivec_vsum4ubs"
1255 [(set (match_operand:V4SI 0 "register_operand" "=v")
1256 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1257 (match_operand:V4SI 2 "register_operand" "v")]
1259 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1262 [(set_attr "type" "veccomplex")])
1264 (define_insn "altivec_vsum4s<VI_char>s"
1265 [(set (match_operand:V4SI 0 "register_operand" "=v")
1266 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1267 (match_operand:V4SI 2 "register_operand" "v")]
1269 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1271 "vsum4s<VI_char>s %0,%1,%2"
1272 [(set_attr "type" "veccomplex")])
1274 (define_insn "altivec_vsum2sws"
1275 [(set (match_operand:V4SI 0 "register_operand" "=v")
1276 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1277 (match_operand:V4SI 2 "register_operand" "v")]
1279 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1282 [(set_attr "type" "veccomplex")])
1284 (define_insn "altivec_vsumsws"
1285 [(set (match_operand:V4SI 0 "register_operand" "=v")
1286 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1287 (match_operand:V4SI 2 "register_operand" "v")]
1289 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1292 [(set_attr "type" "veccomplex")])
1294 (define_insn "altivec_vspltb"
1295 [(set (match_operand:V16QI 0 "register_operand" "=v")
1296 (vec_duplicate:V16QI
1297 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1299 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1302 [(set_attr "type" "vecperm")])
1304 (define_insn "altivec_vsplth"
1305 [(set (match_operand:V8HI 0 "register_operand" "=v")
1307 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1309 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1312 [(set_attr "type" "vecperm")])
1314 (define_insn "altivec_vspltw"
1315 [(set (match_operand:V4SI 0 "register_operand" "=v")
1317 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1319 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1322 [(set_attr "type" "vecperm")])
1324 (define_insn "altivec_vspltsf"
1325 [(set (match_operand:V4SF 0 "register_operand" "=v")
1327 (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1329 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1330 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1332 [(set_attr "type" "vecperm")])
1334 (define_insn "altivec_vspltis<VI_char>"
1335 [(set (match_operand:VI 0 "register_operand" "=v")
1337 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1339 "vspltis<VI_char> %0,%1"
1340 [(set_attr "type" "vecperm")])
1342 (define_insn "*altivec_vrfiz"
1343 [(set (match_operand:V4SF 0 "register_operand" "=v")
1344 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1345 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1347 [(set_attr "type" "vecfloat")])
1349 (define_insn "altivec_vperm_<mode>"
1350 [(set (match_operand:VM 0 "register_operand" "=v")
1351 (unspec:VM [(match_operand:VM 1 "register_operand" "v")
1352 (match_operand:VM 2 "register_operand" "v")
1353 (match_operand:V16QI 3 "register_operand" "v")]
1357 [(set_attr "type" "vecperm")])
1359 (define_insn "altivec_vperm_<mode>_uns"
1360 [(set (match_operand:VM 0 "register_operand" "=v")
1361 (unspec:VM [(match_operand:VM 1 "register_operand" "v")
1362 (match_operand:VM 2 "register_operand" "v")
1363 (match_operand:V16QI 3 "register_operand" "v")]
1367 [(set_attr "type" "vecperm")])
1369 (define_insn "altivec_vrfip" ; ceil
1370 [(set (match_operand:V4SF 0 "register_operand" "=v")
1371 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1375 [(set_attr "type" "vecfloat")])
1377 (define_insn "altivec_vrfin"
1378 [(set (match_operand:V4SF 0 "register_operand" "=v")
1379 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1383 [(set_attr "type" "vecfloat")])
1385 (define_insn "*altivec_vrfim" ; floor
1386 [(set (match_operand:V4SF 0 "register_operand" "=v")
1387 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1391 [(set_attr "type" "vecfloat")])
1393 (define_insn "altivec_vcfux"
1394 [(set (match_operand:V4SF 0 "register_operand" "=v")
1395 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1396 (match_operand:QI 2 "immediate_operand" "i")]
1400 [(set_attr "type" "vecfloat")])
1402 (define_insn "altivec_vcfsx"
1403 [(set (match_operand:V4SF 0 "register_operand" "=v")
1404 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1405 (match_operand:QI 2 "immediate_operand" "i")]
1409 [(set_attr "type" "vecfloat")])
1411 (define_insn "altivec_vctuxs"
1412 [(set (match_operand:V4SI 0 "register_operand" "=v")
1413 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1414 (match_operand:QI 2 "immediate_operand" "i")]
1416 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1419 [(set_attr "type" "vecfloat")])
1421 (define_insn "altivec_vctsxs"
1422 [(set (match_operand:V4SI 0 "register_operand" "=v")
1423 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1424 (match_operand:QI 2 "immediate_operand" "i")]
1426 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1429 [(set_attr "type" "vecfloat")])
1431 (define_insn "altivec_vlogefp"
1432 [(set (match_operand:V4SF 0 "register_operand" "=v")
1433 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1437 [(set_attr "type" "vecfloat")])
1439 (define_insn "altivec_vexptefp"
1440 [(set (match_operand:V4SF 0 "register_operand" "=v")
1441 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1445 [(set_attr "type" "vecfloat")])
1447 (define_insn "altivec_vrsqrtefp"
1448 [(set (match_operand:V4SF 0 "register_operand" "=v")
1449 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1453 [(set_attr "type" "vecfloat")])
1455 (define_insn "altivec_vrefp"
1456 [(set (match_operand:V4SF 0 "register_operand" "=v")
1457 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1461 [(set_attr "type" "vecfloat")])
1463 (define_expand "altivec_copysign_v4sf3"
1464 [(use (match_operand:V4SF 0 "register_operand" ""))
1465 (use (match_operand:V4SF 1 "register_operand" ""))
1466 (use (match_operand:V4SF 2 "register_operand" ""))]
1467 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1470 rtx mask = gen_reg_rtx (V4SImode);
1471 rtvec v = rtvec_alloc (4);
1472 unsigned HOST_WIDE_INT mask_val = ((unsigned HOST_WIDE_INT)1) << 31;
1474 RTVEC_ELT (v, 0) = GEN_INT (mask_val);
1475 RTVEC_ELT (v, 1) = GEN_INT (mask_val);
1476 RTVEC_ELT (v, 2) = GEN_INT (mask_val);
1477 RTVEC_ELT (v, 3) = GEN_INT (mask_val);
1479 emit_insn (gen_vec_initv4si (mask, gen_rtx_PARALLEL (V4SImode, v)));
1480 emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],
1481 gen_lowpart (V4SFmode, mask)));
1485 (define_insn "altivec_vsldoi_<mode>"
1486 [(set (match_operand:VM 0 "register_operand" "=v")
1487 (unspec:VM [(match_operand:VM 1 "register_operand" "v")
1488 (match_operand:VM 2 "register_operand" "v")
1489 (match_operand:QI 3 "immediate_operand" "i")]
1492 "vsldoi %0,%1,%2,%3"
1493 [(set_attr "type" "vecperm")])
1495 (define_insn "altivec_vupkhsb"
1496 [(set (match_operand:V8HI 0 "register_operand" "=v")
1497 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1501 [(set_attr "type" "vecperm")])
1503 (define_insn "altivec_vupkhpx"
1504 [(set (match_operand:V4SI 0 "register_operand" "=v")
1505 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1509 [(set_attr "type" "vecperm")])
1511 (define_insn "altivec_vupkhsh"
1512 [(set (match_operand:V4SI 0 "register_operand" "=v")
1513 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1517 [(set_attr "type" "vecperm")])
1519 (define_insn "altivec_vupklsb"
1520 [(set (match_operand:V8HI 0 "register_operand" "=v")
1521 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1525 [(set_attr "type" "vecperm")])
1527 (define_insn "altivec_vupklpx"
1528 [(set (match_operand:V4SI 0 "register_operand" "=v")
1529 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1533 [(set_attr "type" "vecperm")])
1535 (define_insn "altivec_vupklsh"
1536 [(set (match_operand:V4SI 0 "register_operand" "=v")
1537 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1541 [(set_attr "type" "vecperm")])
1543 ;; Compare vectors producing a vector result and a predicate, setting CR6 to
1544 ;; indicate a combined status
1545 (define_insn "*altivec_vcmpequ<VI_char>_p"
1547 (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v")
1548 (match_operand:VI 2 "register_operand" "v"))]
1550 (set (match_operand:VI 0 "register_operand" "=v")
1551 (eq:VI (match_dup 1)
1553 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
1554 "vcmpequ<VI_char>. %0,%1,%2"
1555 [(set_attr "type" "veccmp")])
1557 (define_insn "*altivec_vcmpgts<VI_char>_p"
1559 (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v")
1560 (match_operand:VI 2 "register_operand" "v"))]
1562 (set (match_operand:VI 0 "register_operand" "=v")
1563 (gt:VI (match_dup 1)
1565 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
1566 "vcmpgts<VI_char>. %0,%1,%2"
1567 [(set_attr "type" "veccmp")])
1569 (define_insn "*altivec_vcmpgtu<VI_char>_p"
1571 (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v")
1572 (match_operand:VI 2 "register_operand" "v"))]
1574 (set (match_operand:VI 0 "register_operand" "=v")
1575 (gtu:VI (match_dup 1)
1577 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
1578 "vcmpgtu<VI_char>. %0,%1,%2"
1579 [(set_attr "type" "veccmp")])
1581 (define_insn "*altivec_vcmpeqfp_p"
1583 (unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
1584 (match_operand:V4SF 2 "register_operand" "v"))]
1586 (set (match_operand:V4SF 0 "register_operand" "=v")
1587 (eq:V4SF (match_dup 1)
1589 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1590 "vcmpeqfp. %0,%1,%2"
1591 [(set_attr "type" "veccmp")])
1593 (define_insn "*altivec_vcmpgtfp_p"
1595 (unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v")
1596 (match_operand:V4SF 2 "register_operand" "v"))]
1598 (set (match_operand:V4SF 0 "register_operand" "=v")
1599 (gt:V4SF (match_dup 1)
1601 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1602 "vcmpgtfp. %0,%1,%2"
1603 [(set_attr "type" "veccmp")])
1605 (define_insn "*altivec_vcmpgefp_p"
1607 (unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v")
1608 (match_operand:V4SF 2 "register_operand" "v"))]
1610 (set (match_operand:V4SF 0 "register_operand" "=v")
1611 (ge:V4SF (match_dup 1)
1613 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1614 "vcmpgefp. %0,%1,%2"
1615 [(set_attr "type" "veccmp")])
1617 (define_insn "altivec_vcmpbfp_p"
1619 (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1620 (match_operand:V4SF 2 "register_operand" "v")]
1622 (set (match_operand:V4SF 0 "register_operand" "=v")
1623 (unspec:V4SF [(match_dup 1)
1626 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
1628 [(set_attr "type" "veccmp")])
1630 (define_insn "altivec_mtvscr"
1633 [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1636 [(set_attr "type" "vecsimple")])
1638 (define_insn "altivec_mfvscr"
1639 [(set (match_operand:V8HI 0 "register_operand" "=v")
1640 (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1643 [(set_attr "type" "vecsimple")])
1645 (define_insn "altivec_dssall"
1646 [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1649 [(set_attr "type" "vecsimple")])
1651 (define_insn "altivec_dss"
1652 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1656 [(set_attr "type" "vecsimple")])
1658 (define_insn "altivec_dst"
1659 [(unspec [(match_operand 0 "register_operand" "b")
1660 (match_operand:SI 1 "register_operand" "r")
1661 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1662 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1664 [(set_attr "type" "vecsimple")])
1666 (define_insn "altivec_dstt"
1667 [(unspec [(match_operand 0 "register_operand" "b")
1668 (match_operand:SI 1 "register_operand" "r")
1669 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1670 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1672 [(set_attr "type" "vecsimple")])
1674 (define_insn "altivec_dstst"
1675 [(unspec [(match_operand 0 "register_operand" "b")
1676 (match_operand:SI 1 "register_operand" "r")
1677 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1678 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1680 [(set_attr "type" "vecsimple")])
1682 (define_insn "altivec_dststt"
1683 [(unspec [(match_operand 0 "register_operand" "b")
1684 (match_operand:SI 1 "register_operand" "r")
1685 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1686 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1688 [(set_attr "type" "vecsimple")])
1690 (define_insn "altivec_lvsl"
1691 [(set (match_operand:V16QI 0 "register_operand" "=v")
1692 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1695 [(set_attr "type" "vecload")])
1697 (define_insn "altivec_lvsr"
1698 [(set (match_operand:V16QI 0 "register_operand" "=v")
1699 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1702 [(set_attr "type" "vecload")])
1704 (define_expand "build_vector_mask_for_load"
1705 [(set (match_operand:V16QI 0 "register_operand" "")
1706 (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1713 gcc_assert (GET_CODE (operands[1]) == MEM);
1715 addr = XEXP (operands[1], 0);
1716 temp = gen_reg_rtx (GET_MODE (addr));
1717 emit_insn (gen_rtx_SET (VOIDmode, temp,
1718 gen_rtx_NEG (GET_MODE (addr), addr)));
1719 emit_insn (gen_altivec_lvsr (operands[0],
1720 replace_equiv_address (operands[1], temp)));
1724 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1725 ;; identical rtl but different instructions-- and gcc gets confused.
1727 (define_insn "altivec_lve<VI_char>x"
1729 [(set (match_operand:VI 0 "register_operand" "=v")
1730 (match_operand:VI 1 "memory_operand" "Z"))
1731 (unspec [(const_int 0)] UNSPEC_LVE)])]
1733 "lve<VI_char>x %0,%y1"
1734 [(set_attr "type" "vecload")])
1736 (define_insn "*altivec_lvesfx"
1738 [(set (match_operand:V4SF 0 "register_operand" "=v")
1739 (match_operand:V4SF 1 "memory_operand" "Z"))
1740 (unspec [(const_int 0)] UNSPEC_LVE)])]
1743 [(set_attr "type" "vecload")])
1745 (define_insn "altivec_lvxl"
1747 [(set (match_operand:V4SI 0 "register_operand" "=v")
1748 (match_operand:V4SI 1 "memory_operand" "Z"))
1749 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1752 [(set_attr "type" "vecload")])
1754 (define_insn "altivec_lvx"
1755 [(set (match_operand:V4SI 0 "register_operand" "=v")
1756 (match_operand:V4SI 1 "memory_operand" "Z"))]
1759 [(set_attr "type" "vecload")])
1761 (define_insn "altivec_stvx"
1763 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1764 (match_operand:V4SI 1 "register_operand" "v"))
1765 (unspec [(const_int 0)] UNSPEC_STVX)])]
1768 [(set_attr "type" "vecstore")])
1770 (define_insn "altivec_stvxl"
1772 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1773 (match_operand:V4SI 1 "register_operand" "v"))
1774 (unspec [(const_int 0)] UNSPEC_STVXL)])]
1777 [(set_attr "type" "vecstore")])
1779 (define_insn "altivec_stve<VI_char>x"
1781 [(set (match_operand:VI 0 "memory_operand" "=Z")
1782 (match_operand:VI 1 "register_operand" "v"))
1783 (unspec [(const_int 0)] UNSPEC_STVE)])]
1785 "stve<VI_char>x %1,%y0"
1786 [(set_attr "type" "vecstore")])
1788 (define_insn "*altivec_stvesfx"
1790 [(set (match_operand:V4SF 0 "memory_operand" "=Z")
1791 (match_operand:V4SF 1 "register_operand" "v"))
1792 (unspec [(const_int 0)] UNSPEC_STVE)])]
1795 [(set_attr "type" "vecstore")])
1798 ;; vspltis? SCRATCH0,0
1799 ;; vsubu?m SCRATCH2,SCRATCH1,%1
1800 ;; vmaxs? %0,%1,SCRATCH2"
1801 (define_expand "abs<mode>2"
1802 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1804 (minus:VI (match_dup 2)
1805 (match_operand:VI 1 "register_operand" "v")))
1806 (set (match_operand:VI 0 "register_operand" "=v")
1807 (smax:VI (match_dup 1) (match_dup 3)))]
1810 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1811 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1815 ;; vspltisw SCRATCH1,-1
1816 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
1817 ;; vandc %0,%1,SCRATCH2
1818 (define_expand "altivec_absv4sf2"
1820 (vec_duplicate:V4SI (const_int -1)))
1822 (ashift:V4SI (match_dup 2) (match_dup 2)))
1823 (set (match_operand:V4SF 0 "register_operand" "=v")
1824 (and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
1825 (match_operand:V4SF 1 "register_operand" "v")))]
1828 operands[2] = gen_reg_rtx (V4SImode);
1829 operands[3] = gen_reg_rtx (V4SImode);
1833 ;; vspltis? SCRATCH0,0
1834 ;; vsubs?s SCRATCH2,SCRATCH1,%1
1835 ;; vmaxs? %0,%1,SCRATCH2"
1836 (define_expand "altivec_abss_<mode>"
1837 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1838 (parallel [(set (match_dup 3)
1839 (unspec:VI [(match_dup 2)
1840 (match_operand:VI 1 "register_operand" "v")]
1842 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
1843 (set (match_operand:VI 0 "register_operand" "=v")
1844 (smax:VI (match_dup 1) (match_dup 3)))]
1847 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1848 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1851 (define_insn "altivec_vsumsws_nomode"
1852 [(set (match_operand 0 "register_operand" "=v")
1853 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1854 (match_operand:V4SI 2 "register_operand" "v")]
1856 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1859 [(set_attr "type" "veccomplex")])
1861 (define_expand "reduc_splus_<mode>"
1862 [(set (match_operand:VIshort 0 "register_operand" "=v")
1863 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
1864 UNSPEC_REDUC_PLUS))]
1868 rtx vzero = gen_reg_rtx (V4SImode);
1869 rtx vtmp1 = gen_reg_rtx (V4SImode);
1871 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
1872 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
1873 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
1877 (define_expand "reduc_uplus_v16qi"
1878 [(set (match_operand:V16QI 0 "register_operand" "=v")
1879 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
1880 UNSPEC_REDUC_PLUS))]
1884 rtx vzero = gen_reg_rtx (V4SImode);
1885 rtx vtmp1 = gen_reg_rtx (V4SImode);
1887 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
1888 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
1889 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
1893 (define_expand "neg<mode>2"
1894 [(use (match_operand:VI 0 "register_operand" ""))
1895 (use (match_operand:VI 1 "register_operand" ""))]
1901 vzero = gen_reg_rtx (GET_MODE (operands[0]));
1902 emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
1903 emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
1908 (define_expand "udot_prod<mode>"
1909 [(set (match_operand:V4SI 0 "register_operand" "=v")
1910 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
1911 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1912 (match_operand:VIshort 2 "register_operand" "v")]
1917 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
1921 (define_expand "sdot_prodv8hi"
1922 [(set (match_operand:V4SI 0 "register_operand" "=v")
1923 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
1924 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1925 (match_operand:V8HI 2 "register_operand" "v")]
1930 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
1934 (define_expand "widen_usum<mode>3"
1935 [(set (match_operand:V4SI 0 "register_operand" "=v")
1936 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
1937 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
1942 rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
1944 emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
1945 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
1949 (define_expand "widen_ssumv16qi3"
1950 [(set (match_operand:V4SI 0 "register_operand" "=v")
1951 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
1952 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
1957 rtx vones = gen_reg_rtx (V16QImode);
1959 emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
1960 emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
1964 (define_expand "widen_ssumv8hi3"
1965 [(set (match_operand:V4SI 0 "register_operand" "=v")
1966 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
1967 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1972 rtx vones = gen_reg_rtx (V8HImode);
1974 emit_insn (gen_altivec_vspltish (vones, const1_rtx));
1975 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
1979 (define_expand "vec_unpacks_hi_v16qi"
1980 [(set (match_operand:V8HI 0 "register_operand" "=v")
1981 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1986 emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
1990 (define_expand "vec_unpacks_hi_v8hi"
1991 [(set (match_operand:V4SI 0 "register_operand" "=v")
1992 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1997 emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
2001 (define_expand "vec_unpacks_lo_v16qi"
2002 [(set (match_operand:V8HI 0 "register_operand" "=v")
2003 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2008 emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
2012 (define_expand "vec_unpacks_lo_v8hi"
2013 [(set (match_operand:V4SI 0 "register_operand" "=v")
2014 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2019 emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
2023 (define_insn "vperm_v8hiv4si"
2024 [(set (match_operand:V4SI 0 "register_operand" "=v")
2025 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2026 (match_operand:V4SI 2 "register_operand" "v")
2027 (match_operand:V16QI 3 "register_operand" "v")]
2031 [(set_attr "type" "vecperm")])
2033 (define_insn "vperm_v16qiv8hi"
2034 [(set (match_operand:V8HI 0 "register_operand" "=v")
2035 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2036 (match_operand:V8HI 2 "register_operand" "v")
2037 (match_operand:V16QI 3 "register_operand" "v")]
2041 [(set_attr "type" "vecperm")])
2044 (define_expand "vec_unpacku_hi_v16qi"
2045 [(set (match_operand:V8HI 0 "register_operand" "=v")
2046 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2051 rtx vzero = gen_reg_rtx (V8HImode);
2052 rtx mask = gen_reg_rtx (V16QImode);
2053 rtvec v = rtvec_alloc (16);
2055 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2057 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2058 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
2059 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2060 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2061 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2062 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
2063 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2064 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2065 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2066 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
2067 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2068 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2069 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2070 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
2071 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2072 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2074 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2075 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2079 (define_expand "vec_unpacku_hi_v8hi"
2080 [(set (match_operand:V4SI 0 "register_operand" "=v")
2081 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2086 rtx vzero = gen_reg_rtx (V4SImode);
2087 rtx mask = gen_reg_rtx (V16QImode);
2088 rtvec v = rtvec_alloc (16);
2090 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2092 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2093 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2094 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
2095 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2096 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2097 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2098 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
2099 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2100 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2101 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2102 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
2103 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2104 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2105 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2106 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
2107 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2109 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2110 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2114 (define_expand "vec_unpacku_lo_v16qi"
2115 [(set (match_operand:V8HI 0 "register_operand" "=v")
2116 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2121 rtx vzero = gen_reg_rtx (V8HImode);
2122 rtx mask = gen_reg_rtx (V16QImode);
2123 rtvec v = rtvec_alloc (16);
2125 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2127 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2128 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
2129 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2130 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2131 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2132 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2133 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2134 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2135 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2136 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
2137 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2138 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2139 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2140 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
2141 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2142 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2144 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2145 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2149 (define_expand "vec_unpacku_lo_v8hi"
2150 [(set (match_operand:V4SI 0 "register_operand" "=v")
2151 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2156 rtx vzero = gen_reg_rtx (V4SImode);
2157 rtx mask = gen_reg_rtx (V16QImode);
2158 rtvec v = rtvec_alloc (16);
2160 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2162 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2163 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2164 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
2165 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2166 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2167 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2168 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2169 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2170 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2171 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2172 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
2173 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2174 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2175 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2176 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
2177 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2179 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2180 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2184 (define_expand "vec_widen_umult_hi_v16qi"
2185 [(set (match_operand:V8HI 0 "register_operand" "=v")
2186 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2187 (match_operand:V16QI 2 "register_operand" "v")]
2192 rtx ve = gen_reg_rtx (V8HImode);
2193 rtx vo = gen_reg_rtx (V8HImode);
2195 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2196 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2197 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2201 (define_expand "vec_widen_umult_lo_v16qi"
2202 [(set (match_operand:V8HI 0 "register_operand" "=v")
2203 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2204 (match_operand:V16QI 2 "register_operand" "v")]
2209 rtx ve = gen_reg_rtx (V8HImode);
2210 rtx vo = gen_reg_rtx (V8HImode);
2212 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2213 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2214 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2218 (define_expand "vec_widen_smult_hi_v16qi"
2219 [(set (match_operand:V8HI 0 "register_operand" "=v")
2220 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2221 (match_operand:V16QI 2 "register_operand" "v")]
2226 rtx ve = gen_reg_rtx (V8HImode);
2227 rtx vo = gen_reg_rtx (V8HImode);
2229 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2230 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2231 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2235 (define_expand "vec_widen_smult_lo_v16qi"
2236 [(set (match_operand:V8HI 0 "register_operand" "=v")
2237 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2238 (match_operand:V16QI 2 "register_operand" "v")]
2243 rtx ve = gen_reg_rtx (V8HImode);
2244 rtx vo = gen_reg_rtx (V8HImode);
2246 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2247 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2248 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2252 (define_expand "vec_widen_umult_hi_v8hi"
2253 [(set (match_operand:V4SI 0 "register_operand" "=v")
2254 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2255 (match_operand:V8HI 2 "register_operand" "v")]
2260 rtx ve = gen_reg_rtx (V4SImode);
2261 rtx vo = gen_reg_rtx (V4SImode);
2263 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2264 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2265 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2269 (define_expand "vec_widen_umult_lo_v8hi"
2270 [(set (match_operand:V4SI 0 "register_operand" "=v")
2271 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2272 (match_operand:V8HI 2 "register_operand" "v")]
2277 rtx ve = gen_reg_rtx (V4SImode);
2278 rtx vo = gen_reg_rtx (V4SImode);
2280 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2281 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2282 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2286 (define_expand "vec_widen_smult_hi_v8hi"
2287 [(set (match_operand:V4SI 0 "register_operand" "=v")
2288 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2289 (match_operand:V8HI 2 "register_operand" "v")]
2294 rtx ve = gen_reg_rtx (V4SImode);
2295 rtx vo = gen_reg_rtx (V4SImode);
2297 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2298 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2299 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2303 (define_expand "vec_widen_smult_lo_v8hi"
2304 [(set (match_operand:V4SI 0 "register_operand" "=v")
2305 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2306 (match_operand:V8HI 2 "register_operand" "v")]
2311 rtx ve = gen_reg_rtx (V4SImode);
2312 rtx vo = gen_reg_rtx (V4SImode);
2314 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2315 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2316 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2320 (define_expand "vec_pack_trunc_v8hi"
2321 [(set (match_operand:V16QI 0 "register_operand" "=v")
2322 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
2323 (match_operand:V8HI 2 "register_operand" "v")]
2328 emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
2332 (define_expand "vec_pack_trunc_v4si"
2333 [(set (match_operand:V8HI 0 "register_operand" "=v")
2334 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
2335 (match_operand:V4SI 2 "register_operand" "v")]
2340 emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
2344 (define_expand "altivec_negv4sf2"
2345 [(use (match_operand:V4SF 0 "register_operand" ""))
2346 (use (match_operand:V4SF 1 "register_operand" ""))]
2352 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
2353 neg0 = gen_reg_rtx (V4SImode);
2354 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
2355 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
2358 emit_insn (gen_xorv4sf3 (operands[0],
2359 gen_lowpart (V4SFmode, neg0), operands[1]));
2364 ;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
2365 ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
2366 (define_insn "altivec_lvlx"
2367 [(set (match_operand:V16QI 0 "register_operand" "=v")
2368 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2370 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2372 [(set_attr "type" "vecload")])
2374 (define_insn "altivec_lvlxl"
2375 [(set (match_operand:V16QI 0 "register_operand" "=v")
2376 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2378 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2380 [(set_attr "type" "vecload")])
2382 (define_insn "altivec_lvrx"
2383 [(set (match_operand:V16QI 0 "register_operand" "=v")
2384 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2386 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2388 [(set_attr "type" "vecload")])
2390 (define_insn "altivec_lvrxl"
2391 [(set (match_operand:V16QI 0 "register_operand" "=v")
2392 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2394 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2396 [(set_attr "type" "vecload")])
2398 (define_insn "altivec_stvlx"
2400 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2401 (match_operand:V4SI 1 "register_operand" "v"))
2402 (unspec [(const_int 0)] UNSPEC_STVLX)])]
2403 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2405 [(set_attr "type" "vecstore")])
2407 (define_insn "altivec_stvlxl"
2409 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2410 (match_operand:V4SI 1 "register_operand" "v"))
2411 (unspec [(const_int 0)] UNSPEC_STVLXL)])]
2412 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2414 [(set_attr "type" "vecstore")])
2416 (define_insn "altivec_stvrx"
2418 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2419 (match_operand:V4SI 1 "register_operand" "v"))
2420 (unspec [(const_int 0)] UNSPEC_STVRX)])]
2421 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2423 [(set_attr "type" "vecstore")])
2425 (define_insn "altivec_stvrxl"
2427 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2428 (match_operand:V4SI 1 "register_operand" "v"))
2429 (unspec [(const_int 0)] UNSPEC_STVRXL)])]
2430 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2432 [(set_attr "type" "vecstore")])
2434 (define_expand "vec_extract_evenv4si"
2435 [(set (match_operand:V4SI 0 "register_operand" "")
2436 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2437 (match_operand:V4SI 2 "register_operand" "")]
2438 UNSPEC_EXTEVEN_V4SI))]
2442 rtx mask = gen_reg_rtx (V16QImode);
2443 rtvec v = rtvec_alloc (16);
2445 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2446 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2447 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2448 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2449 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2450 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2451 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2452 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2453 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2454 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2455 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2456 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2457 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2458 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2459 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2460 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2461 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2462 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2467 (define_expand "vec_extract_evenv4sf"
2468 [(set (match_operand:V4SF 0 "register_operand" "")
2469 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2470 (match_operand:V4SF 2 "register_operand" "")]
2471 UNSPEC_EXTEVEN_V4SF))]
2475 rtx mask = gen_reg_rtx (V16QImode);
2476 rtvec v = rtvec_alloc (16);
2478 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2479 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2480 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2481 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2482 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2483 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2484 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2485 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2486 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2487 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2488 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2489 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2490 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2491 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2492 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2493 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2494 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2495 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2500 (define_expand "vec_extract_evenv8hi"
2501 [(set (match_operand:V4SI 0 "register_operand" "")
2502 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2503 (match_operand:V8HI 2 "register_operand" "")]
2504 UNSPEC_EXTEVEN_V8HI))]
2508 rtx mask = gen_reg_rtx (V16QImode);
2509 rtvec v = rtvec_alloc (16);
2511 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2512 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2513 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2514 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5);
2515 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2516 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2517 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2518 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13);
2519 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2520 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2521 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2522 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21);
2523 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2524 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2525 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2526 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29);
2527 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2528 emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask));
2533 (define_expand "vec_extract_evenv16qi"
2534 [(set (match_operand:V4SI 0 "register_operand" "")
2535 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
2536 (match_operand:V16QI 2 "register_operand" "")]
2537 UNSPEC_EXTEVEN_V16QI))]
2541 rtx mask = gen_reg_rtx (V16QImode);
2542 rtvec v = rtvec_alloc (16);
2544 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2545 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2);
2546 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2547 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6);
2548 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2549 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2550 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2551 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14);
2552 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2553 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18);
2554 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2555 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22);
2556 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2557 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26);
2558 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2559 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30);
2560 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2561 emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask));
2566 (define_expand "vec_extract_oddv4si"
2567 [(set (match_operand:V4SI 0 "register_operand" "")
2568 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2569 (match_operand:V4SI 2 "register_operand" "")]
2570 UNSPEC_EXTODD_V4SI))]
2574 rtx mask = gen_reg_rtx (V16QImode);
2575 rtvec v = rtvec_alloc (16);
2577 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2578 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2579 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2580 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2581 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2582 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2583 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2584 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2585 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2586 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2587 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2588 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2589 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2590 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2591 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2592 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2593 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2594 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2599 (define_expand "vec_extract_oddv4sf"
2600 [(set (match_operand:V4SF 0 "register_operand" "")
2601 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2602 (match_operand:V4SF 2 "register_operand" "")]
2603 UNSPEC_EXTODD_V4SF))]
2607 rtx mask = gen_reg_rtx (V16QImode);
2608 rtvec v = rtvec_alloc (16);
2610 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2611 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2612 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2613 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2614 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2615 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2616 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2617 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2618 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2619 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2620 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2621 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2622 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2623 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2624 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2625 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2626 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2627 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2632 (define_insn "vpkuhum_nomode"
2633 [(set (match_operand:V16QI 0 "register_operand" "=v")
2634 (unspec:V16QI [(match_operand 1 "register_operand" "v")
2635 (match_operand 2 "register_operand" "v")]
2639 [(set_attr "type" "vecperm")])
2641 (define_insn "vpkuwum_nomode"
2642 [(set (match_operand:V8HI 0 "register_operand" "=v")
2643 (unspec:V8HI [(match_operand 1 "register_operand" "v")
2644 (match_operand 2 "register_operand" "v")]
2648 [(set_attr "type" "vecperm")])
2650 (define_expand "vec_extract_oddv8hi"
2651 [(set (match_operand:V8HI 0 "register_operand" "")
2652 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2653 (match_operand:V8HI 2 "register_operand" "")]
2654 UNSPEC_EXTODD_V8HI))]
2658 emit_insn (gen_vpkuwum_nomode (operands[0], operands[1], operands[2]));
2662 (define_expand "vec_extract_oddv16qi"
2663 [(set (match_operand:V16QI 0 "register_operand" "")
2664 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
2665 (match_operand:V16QI 2 "register_operand" "")]
2666 UNSPEC_EXTODD_V16QI))]
2670 emit_insn (gen_vpkuhum_nomode (operands[0], operands[1], operands[2]));
2674 (define_expand "vec_interleave_high<mode>"
2675 [(set (match_operand:VI 0 "register_operand" "")
2676 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2677 (match_operand:VI 2 "register_operand" "")]
2682 emit_insn (gen_altivec_vmrgh<VI_char> (operands[0], operands[1], operands[2]));
2686 (define_expand "vec_interleave_low<mode>"
2687 [(set (match_operand:VI 0 "register_operand" "")
2688 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2689 (match_operand:VI 2 "register_operand" "")]
2694 emit_insn (gen_altivec_vmrgl<VI_char> (operands[0], operands[1], operands[2]));
2698 (define_expand "vec_unpacks_float_hi_v8hi"
2699 [(set (match_operand:V4SF 0 "register_operand" "")
2700 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2701 UNSPEC_VUPKHS_V4SF))]
2705 rtx tmp = gen_reg_rtx (V4SImode);
2707 emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
2708 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
2712 (define_expand "vec_unpacks_float_lo_v8hi"
2713 [(set (match_operand:V4SF 0 "register_operand" "")
2714 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2715 UNSPEC_VUPKLS_V4SF))]
2719 rtx tmp = gen_reg_rtx (V4SImode);
2721 emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
2722 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
2726 (define_expand "vec_unpacku_float_hi_v8hi"
2727 [(set (match_operand:V4SF 0 "register_operand" "")
2728 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2729 UNSPEC_VUPKHU_V4SF))]
2733 rtx tmp = gen_reg_rtx (V4SImode);
2735 emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
2736 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
2740 (define_expand "vec_unpacku_float_lo_v8hi"
2741 [(set (match_operand:V4SF 0 "register_operand" "")
2742 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2743 UNSPEC_VUPKLU_V4SF))]
2747 rtx tmp = gen_reg_rtx (V4SImode);
2749 emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
2750 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));