1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "insn-config.h"
34 #include "diagnostic-core.h"
36 #include "sparseset.h"
39 #include "alloc-pool.h"
42 /* The code in this file is similar to one in global but the code
43 works on the allocno basis and creates live ranges instead of
44 pseudo-register conflicts. */
46 /* Program points are enumerated by numbers from range
47 0..IRA_MAX_POINT-1. There are approximately two times more program
48 points than insns. Program points are places in the program where
49 liveness info can be changed. In most general case (there are more
50 complicated cases too) some program points correspond to places
51 where input operand dies and other ones correspond to places where
52 output operands are born. */
55 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
56 live ranges with given start/finish point. */
57 live_range_t
*ira_start_point_ranges
, *ira_finish_point_ranges
;
59 /* Number of the current program point. */
60 static int curr_point
;
62 /* Point where register pressure excess started or -1 if there is no
63 register pressure excess. Excess pressure for a register class at
64 some point means that there are more allocnos of given register
65 class living at the point than number of hard-registers of the
66 class available for the allocation. It is defined only for
68 static int high_pressure_start_point
[N_REG_CLASSES
];
70 /* Objects live at current point in the scan. */
71 static sparseset objects_live
;
73 /* A temporary bitmap used in functions that wish to avoid visiting an allocno
75 static sparseset allocnos_processed
;
77 /* Set of hard regs (except eliminable ones) currently live. */
78 static HARD_REG_SET hard_regs_live
;
80 /* The loop tree node corresponding to the current basic block. */
81 static ira_loop_tree_node_t curr_bb_node
;
83 /* The number of the last processed call. */
84 static int last_call_num
;
85 /* The number of last call at which given allocno was saved. */
86 static int *allocno_saved_at_call
;
88 /* The value of get_preferred_alternatives for the current instruction,
89 supplemental to recog_data. */
90 static alternative_mask preferred_alternatives
;
92 /* Record the birth of hard register REGNO, updating hard_regs_live and
93 hard reg conflict information for living allocnos. */
95 make_hard_regno_born (int regno
)
99 SET_HARD_REG_BIT (hard_regs_live
, regno
);
100 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
102 ira_object_t obj
= ira_object_id_map
[i
];
104 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
);
105 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
);
109 /* Process the death of hard register REGNO. This updates
112 make_hard_regno_dead (int regno
)
114 CLEAR_HARD_REG_BIT (hard_regs_live
, regno
);
117 /* Record the birth of object OBJ. Set a bit for it in objects_live,
118 start a new live range for it if necessary and update hard register
121 make_object_born (ira_object_t obj
)
123 live_range_t lr
= OBJECT_LIVE_RANGES (obj
);
125 sparseset_set_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
126 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
127 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
130 || (lr
->finish
!= curr_point
&& lr
->finish
+ 1 != curr_point
))
131 ira_add_live_range_to_object (obj
, curr_point
, -1);
134 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
135 associated with object OBJ. */
137 update_allocno_pressure_excess_length (ira_object_t obj
)
139 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
141 enum reg_class aclass
, pclass
, cl
;
144 aclass
= ALLOCNO_CLASS (a
);
145 pclass
= ira_pressure_class_translate
[aclass
];
147 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
150 if (! ira_reg_pressure_class_p
[cl
])
152 if (high_pressure_start_point
[cl
] < 0)
154 p
= OBJECT_LIVE_RANGES (obj
);
155 ira_assert (p
!= NULL
);
156 start
= (high_pressure_start_point
[cl
] > p
->start
157 ? high_pressure_start_point
[cl
] : p
->start
);
158 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a
) += curr_point
- start
+ 1;
162 /* Process the death of object OBJ, which is associated with allocno
163 A. This finishes the current live range for it. */
165 make_object_dead (ira_object_t obj
)
169 sparseset_clear_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
170 lr
= OBJECT_LIVE_RANGES (obj
);
171 ira_assert (lr
!= NULL
);
172 lr
->finish
= curr_point
;
173 update_allocno_pressure_excess_length (obj
);
176 /* The current register pressures for each pressure class for the current
178 static int curr_reg_pressure
[N_REG_CLASSES
];
180 /* Record that register pressure for PCLASS increased by N registers.
181 Update the current register pressure, maximal register pressure for
182 the current BB and the start point of the register pressure
185 inc_register_pressure (enum reg_class pclass
, int n
)
191 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
194 if (! ira_reg_pressure_class_p
[cl
])
196 curr_reg_pressure
[cl
] += n
;
197 if (high_pressure_start_point
[cl
] < 0
198 && (curr_reg_pressure
[cl
] > ira_class_hard_regs_num
[cl
]))
199 high_pressure_start_point
[cl
] = curr_point
;
200 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
201 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
205 /* Record that register pressure for PCLASS has decreased by NREGS
206 registers; update current register pressure, start point of the
207 register pressure excess, and register pressure excess length for
211 dec_register_pressure (enum reg_class pclass
, int nregs
)
219 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
222 if (! ira_reg_pressure_class_p
[cl
])
224 curr_reg_pressure
[cl
] -= nregs
;
225 ira_assert (curr_reg_pressure
[cl
] >= 0);
226 if (high_pressure_start_point
[cl
] >= 0
227 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
232 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, j
)
233 update_allocno_pressure_excess_length (ira_object_id_map
[j
]);
235 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
238 if (! ira_reg_pressure_class_p
[cl
])
240 if (high_pressure_start_point
[cl
] >= 0
241 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
242 high_pressure_start_point
[cl
] = -1;
247 /* Determine from the objects_live bitmap whether REGNO is currently live,
248 and occupies only one object. Return false if we have no information. */
250 pseudo_regno_single_word_and_live_p (int regno
)
252 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
257 if (ALLOCNO_NUM_OBJECTS (a
) > 1)
260 obj
= ALLOCNO_OBJECT (a
, 0);
262 return sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
));
265 /* Mark the pseudo register REGNO as live. Update all information about
266 live ranges and register pressure. */
268 mark_pseudo_regno_live (int regno
)
270 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
271 enum reg_class pclass
;
277 /* Invalidate because it is referenced. */
278 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
280 n
= ALLOCNO_NUM_OBJECTS (a
);
281 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
282 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
285 /* We track every subobject separately. */
286 gcc_assert (nregs
== n
);
290 for (i
= 0; i
< n
; i
++)
292 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
294 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
297 inc_register_pressure (pclass
, nregs
);
298 make_object_born (obj
);
302 /* Like mark_pseudo_regno_live, but try to only mark one subword of
303 the pseudo as live. SUBWORD indicates which; a value of 0
304 indicates the low part. */
306 mark_pseudo_regno_subword_live (int regno
, int subword
)
308 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
310 enum reg_class pclass
;
316 /* Invalidate because it is referenced. */
317 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
319 n
= ALLOCNO_NUM_OBJECTS (a
);
322 mark_pseudo_regno_live (regno
);
326 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
328 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
329 obj
= ALLOCNO_OBJECT (a
, subword
);
331 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
334 inc_register_pressure (pclass
, 1);
335 make_object_born (obj
);
338 /* Mark the register REG as live. Store a 1 in hard_regs_live for
339 this register, record how many consecutive hardware registers it
342 mark_hard_reg_live (rtx reg
)
344 int regno
= REGNO (reg
);
346 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
348 int last
= END_REGNO (reg
);
349 enum reg_class aclass
, pclass
;
353 if (! TEST_HARD_REG_BIT (hard_regs_live
, regno
)
354 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
356 aclass
= ira_hard_regno_allocno_class
[regno
];
357 pclass
= ira_pressure_class_translate
[aclass
];
358 inc_register_pressure (pclass
, 1);
359 make_hard_regno_born (regno
);
366 /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
367 register number; ORIG_REG is the access in the insn, which may be a
370 mark_pseudo_reg_live (rtx orig_reg
, unsigned regno
)
372 if (df_read_modify_subreg_p (orig_reg
))
374 mark_pseudo_regno_subword_live (regno
,
375 subreg_lowpart_p (orig_reg
) ? 0 : 1);
378 mark_pseudo_regno_live (regno
);
381 /* Mark the register referenced by use or def REF as live. */
383 mark_ref_live (df_ref ref
)
385 rtx reg
= DF_REF_REG (ref
);
388 if (GET_CODE (reg
) == SUBREG
)
389 reg
= SUBREG_REG (reg
);
391 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
392 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
394 mark_hard_reg_live (reg
);
397 /* Mark the pseudo register REGNO as dead. Update all information about
398 live ranges and register pressure. */
400 mark_pseudo_regno_dead (int regno
)
402 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
409 /* Invalidate because it is referenced. */
410 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
412 n
= ALLOCNO_NUM_OBJECTS (a
);
413 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
414 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
417 /* We track every subobject separately. */
418 gcc_assert (nregs
== n
);
421 for (i
= 0; i
< n
; i
++)
423 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
424 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
427 dec_register_pressure (cl
, nregs
);
428 make_object_dead (obj
);
432 /* Like mark_pseudo_regno_dead, but called when we know that only part of the
433 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
435 mark_pseudo_regno_subword_dead (int regno
, int subword
)
437 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
445 /* Invalidate because it is referenced. */
446 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
448 n
= ALLOCNO_NUM_OBJECTS (a
);
450 /* The allocno as a whole doesn't die in this case. */
453 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
455 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
457 obj
= ALLOCNO_OBJECT (a
, subword
);
458 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
461 dec_register_pressure (cl
, 1);
462 make_object_dead (obj
);
465 /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the
468 mark_hard_reg_dead (rtx reg
)
470 int regno
= REGNO (reg
);
472 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
474 int last
= END_REGNO (reg
);
475 enum reg_class aclass
, pclass
;
479 if (TEST_HARD_REG_BIT (hard_regs_live
, regno
))
481 aclass
= ira_hard_regno_allocno_class
[regno
];
482 pclass
= ira_pressure_class_translate
[aclass
];
483 dec_register_pressure (pclass
, 1);
484 make_hard_regno_dead (regno
);
491 /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
492 register number; ORIG_REG is the access in the insn, which may be a
495 mark_pseudo_reg_dead (rtx orig_reg
, unsigned regno
)
497 if (df_read_modify_subreg_p (orig_reg
))
499 mark_pseudo_regno_subword_dead (regno
,
500 subreg_lowpart_p (orig_reg
) ? 0 : 1);
503 mark_pseudo_regno_dead (regno
);
506 /* Mark the register referenced by definition DEF as dead, if the
507 definition is a total one. */
509 mark_ref_dead (df_ref def
)
511 rtx reg
= DF_REF_REG (def
);
514 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
))
517 if (GET_CODE (reg
) == SUBREG
)
518 reg
= SUBREG_REG (reg
);
520 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
)
521 && (GET_CODE (orig_reg
) != SUBREG
522 || REGNO (reg
) < FIRST_PSEUDO_REGISTER
523 || !df_read_modify_subreg_p (orig_reg
)))
526 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
527 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
529 mark_hard_reg_dead (reg
);
532 /* If REG is a pseudo or a subreg of it, and the class of its allocno
533 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
534 rtx actually accessed, it may be identical to DREG or a subreg of it.
535 Advance the current program point before making the conflict if
536 ADVANCE_P. Return TRUE if we will need to advance the current
539 make_pseudo_conflict (rtx reg
, enum reg_class cl
, rtx dreg
, rtx orig_dreg
,
545 if (GET_CODE (reg
) == SUBREG
)
546 reg
= SUBREG_REG (reg
);
548 if (! REG_P (reg
) || REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
551 a
= ira_curr_regno_allocno_map
[REGNO (reg
)];
552 if (! reg_classes_intersect_p (cl
, ALLOCNO_CLASS (a
)))
558 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
559 mark_pseudo_reg_live (orig_dreg
, REGNO (dreg
));
560 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
561 mark_pseudo_reg_dead (orig_dreg
, REGNO (dreg
));
566 /* Check and make if necessary conflicts for pseudo DREG of class
567 DEF_CL of the current insn with input operand USE of class USE_CL.
568 ORIG_DREG is the rtx actually accessed, it may be identical to
569 DREG or a subreg of it. Advance the current program point before
570 making the conflict if ADVANCE_P. Return TRUE if we will need to
571 advance the current program point. */
573 check_and_make_def_use_conflict (rtx dreg
, rtx orig_dreg
,
574 enum reg_class def_cl
, int use
,
575 enum reg_class use_cl
, bool advance_p
)
577 if (! reg_classes_intersect_p (def_cl
, use_cl
))
580 advance_p
= make_pseudo_conflict (recog_data
.operand
[use
],
581 use_cl
, dreg
, orig_dreg
, advance_p
);
583 /* Reload may end up swapping commutative operands, so you
584 have to take both orderings into account. The
585 constraints for the two operands can be completely
586 different. (Indeed, if the constraints for the two
587 operands are the same for all alternatives, there's no
588 point marking them as commutative.) */
589 if (use
< recog_data
.n_operands
- 1
590 && recog_data
.constraints
[use
][0] == '%')
592 = make_pseudo_conflict (recog_data
.operand
[use
+ 1],
593 use_cl
, dreg
, orig_dreg
, advance_p
);
595 && recog_data
.constraints
[use
- 1][0] == '%')
597 = make_pseudo_conflict (recog_data
.operand
[use
- 1],
598 use_cl
, dreg
, orig_dreg
, advance_p
);
602 /* Check and make if necessary conflicts for definition DEF of class
603 DEF_CL of the current insn with input operands. Process only
604 constraints of alternative ALT. */
606 check_and_make_def_conflict (int alt
, int def
, enum reg_class def_cl
)
610 enum reg_class use_cl
, acl
;
612 rtx dreg
= recog_data
.operand
[def
];
613 rtx orig_dreg
= dreg
;
615 if (def_cl
== NO_REGS
)
618 if (GET_CODE (dreg
) == SUBREG
)
619 dreg
= SUBREG_REG (dreg
);
621 if (! REG_P (dreg
) || REGNO (dreg
) < FIRST_PSEUDO_REGISTER
)
624 a
= ira_curr_regno_allocno_map
[REGNO (dreg
)];
625 acl
= ALLOCNO_CLASS (a
);
626 if (! reg_classes_intersect_p (acl
, def_cl
))
631 int n_operands
= recog_data
.n_operands
;
632 const operand_alternative
*op_alt
= &recog_op_alt
[alt
* n_operands
];
633 for (use
= 0; use
< n_operands
; use
++)
637 if (use
== def
|| recog_data
.operand_type
[use
] == OP_OUT
)
640 if (op_alt
[use
].anything_ok
)
643 use_cl
= op_alt
[use
].cl
;
645 /* If there's any alternative that allows USE to match DEF, do not
646 record a conflict. If that causes us to create an invalid
647 instruction due to the earlyclobber, reload must fix it up. */
648 for (alt1
= 0; alt1
< recog_data
.n_alternatives
; alt1
++)
650 if (!TEST_BIT (preferred_alternatives
, alt1
))
652 const operand_alternative
*op_alt1
653 = &recog_op_alt
[alt1
* n_operands
];
654 if (op_alt1
[use
].matches
== def
655 || (use
< n_operands
- 1
656 && recog_data
.constraints
[use
][0] == '%'
657 && op_alt1
[use
+ 1].matches
== def
)
659 && recog_data
.constraints
[use
- 1][0] == '%'
660 && op_alt1
[use
- 1].matches
== def
))
664 if (alt1
< recog_data
.n_alternatives
)
667 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
668 use
, use_cl
, advance_p
);
670 if ((use_match
= op_alt
[use
].matches
) >= 0)
672 if (use_match
== def
)
675 if (op_alt
[use_match
].anything_ok
)
678 use_cl
= op_alt
[use_match
].cl
;
679 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
680 use
, use_cl
, advance_p
);
685 /* Make conflicts of early clobber pseudo registers of the current
686 insn with its inputs. Avoid introducing unnecessary conflicts by
687 checking classes of the constraints and pseudos because otherwise
688 significant code degradation is possible for some targets. */
690 make_early_clobber_and_input_conflicts (void)
694 enum reg_class def_cl
;
696 int n_alternatives
= recog_data
.n_alternatives
;
697 int n_operands
= recog_data
.n_operands
;
698 const operand_alternative
*op_alt
= recog_op_alt
;
699 for (alt
= 0; alt
< n_alternatives
; alt
++, op_alt
+= n_operands
)
700 if (TEST_BIT (preferred_alternatives
, alt
))
701 for (def
= 0; def
< n_operands
; def
++)
704 if (op_alt
[def
].earlyclobber
)
706 if (op_alt
[def
].anything_ok
)
709 def_cl
= op_alt
[def
].cl
;
710 check_and_make_def_conflict (alt
, def
, def_cl
);
712 if ((def_match
= op_alt
[def
].matches
) >= 0
713 && (op_alt
[def_match
].earlyclobber
714 || op_alt
[def
].earlyclobber
))
716 if (op_alt
[def_match
].anything_ok
)
719 def_cl
= op_alt
[def_match
].cl
;
720 check_and_make_def_conflict (alt
, def
, def_cl
);
725 /* Mark early clobber hard registers of the current INSN as live (if
726 LIVE_P) or dead. Return true if there are such registers. */
728 mark_hard_reg_early_clobbers (rtx_insn
*insn
, bool live_p
)
733 FOR_EACH_INSN_DEF (def
, insn
)
734 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_MUST_CLOBBER
))
736 rtx dreg
= DF_REF_REG (def
);
738 if (GET_CODE (dreg
) == SUBREG
)
739 dreg
= SUBREG_REG (dreg
);
740 if (! REG_P (dreg
) || REGNO (dreg
) >= FIRST_PSEUDO_REGISTER
)
743 /* Hard register clobbers are believed to be early clobber
744 because there is no way to say that non-operand hard
745 register clobbers are not early ones. */
756 /* Checks that CONSTRAINTS permits to use only one hard register. If
757 it is so, the function returns the class of the hard register.
758 Otherwise it returns NO_REGS. */
759 static enum reg_class
760 single_reg_class (const char *constraints
, rtx op
, rtx equiv_const
)
763 enum reg_class cl
, next_cl
;
764 enum constraint_num cn
;
767 alternative_mask preferred
= preferred_alternatives
;
768 for (; (c
= *constraints
); constraints
+= CONSTRAINT_LEN (c
, constraints
))
770 preferred
&= ~ALTERNATIVE_BIT (0);
773 else if (preferred
& 1)
780 /* ??? Is this the best way to handle memory constraints? */
781 cn
= lookup_constraint (constraints
);
782 if (insn_extra_memory_constraint (cn
)
783 || insn_extra_address_constraint (cn
))
785 if (constraint_satisfied_p (op
, cn
)
786 || (equiv_const
!= NULL_RTX
787 && CONSTANT_P (equiv_const
)
788 && constraint_satisfied_p (equiv_const
, cn
)))
790 next_cl
= reg_class_for_constraint (cn
);
791 if (next_cl
== NO_REGS
)
794 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
795 : (ira_class_singleton
[cl
][GET_MODE (op
)]
796 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
801 case '0': case '1': case '2': case '3': case '4':
802 case '5': case '6': case '7': case '8': case '9':
804 = single_reg_class (recog_data
.constraints
[c
- '0'],
805 recog_data
.operand
[c
- '0'], NULL_RTX
);
807 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
808 : (ira_class_singleton
[cl
][GET_MODE (op
)]
809 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
817 /* The function checks that operand OP_NUM of the current insn can use
818 only one hard register. If it is so, the function returns the
819 class of the hard register. Otherwise it returns NO_REGS. */
820 static enum reg_class
821 single_reg_operand_class (int op_num
)
823 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
825 return single_reg_class (recog_data
.constraints
[op_num
],
826 recog_data
.operand
[op_num
], NULL_RTX
);
829 /* The function sets up hard register set *SET to hard registers which
830 might be used by insn reloads because the constraints are too
833 ira_implicitly_set_insn_hard_regs (HARD_REG_SET
*set
,
834 alternative_mask preferred
)
841 CLEAR_HARD_REG_SET (*set
);
842 for (i
= 0; i
< recog_data
.n_operands
; i
++)
844 op
= recog_data
.operand
[i
];
846 if (GET_CODE (op
) == SUBREG
)
847 op
= SUBREG_REG (op
);
849 if (GET_CODE (op
) == SCRATCH
850 || (REG_P (op
) && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
))
852 const char *p
= recog_data
.constraints
[i
];
854 mode
= (GET_CODE (op
) == SCRATCH
855 ? GET_MODE (op
) : PSEUDO_REGNO_MODE (regno
));
857 for (; (c
= *p
); p
+= CONSTRAINT_LEN (c
, p
))
859 preferred
&= ~ALTERNATIVE_BIT (0);
862 else if (preferred
& 1)
864 cl
= reg_class_for_constraint (lookup_constraint (p
));
867 /* There is no register pressure problem if all of the
868 regs in this class are fixed. */
869 int regno
= ira_class_singleton
[cl
][mode
];
871 add_to_hard_reg_set (set
, mode
, regno
);
877 /* Processes input operands, if IN_P, or output operands otherwise of
878 the current insn with FREQ to find allocno which can use only one
879 hard register and makes other currently living allocnos conflicting
880 with the hard register. */
882 process_single_reg_class_operands (bool in_p
, int freq
)
888 ira_allocno_t operand_a
, a
;
890 for (i
= 0; i
< recog_data
.n_operands
; i
++)
892 operand
= recog_data
.operand
[i
];
893 if (in_p
&& recog_data
.operand_type
[i
] != OP_IN
894 && recog_data
.operand_type
[i
] != OP_INOUT
)
896 if (! in_p
&& recog_data
.operand_type
[i
] != OP_OUT
897 && recog_data
.operand_type
[i
] != OP_INOUT
)
899 cl
= single_reg_operand_class (i
);
905 if (GET_CODE (operand
) == SUBREG
)
906 operand
= SUBREG_REG (operand
);
909 && (regno
= REGNO (operand
)) >= FIRST_PSEUDO_REGISTER
)
911 enum reg_class aclass
;
913 operand_a
= ira_curr_regno_allocno_map
[regno
];
914 aclass
= ALLOCNO_CLASS (operand_a
);
915 if (ira_class_subset_p
[cl
][aclass
])
917 /* View the desired allocation of OPERAND as:
923 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
924 machine_mode ymode
, xmode
;
926 HOST_WIDE_INT offset
;
928 xmode
= recog_data
.operand_mode
[i
];
929 xregno
= ira_class_singleton
[cl
][xmode
];
930 gcc_assert (xregno
>= 0);
931 ymode
= ALLOCNO_MODE (operand_a
);
932 offset
= subreg_lowpart_offset (ymode
, xmode
);
933 yregno
= simplify_subreg_regno (xregno
, xmode
, offset
, ymode
);
935 && ira_class_hard_reg_index
[aclass
][yregno
] >= 0)
939 ira_allocate_and_set_costs
940 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
),
942 ira_init_register_move_cost_if_necessary (xmode
);
944 ? ira_register_move_cost
[xmode
][aclass
][cl
]
945 : ira_register_move_cost
[xmode
][cl
][aclass
]);
946 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
)
947 [ira_class_hard_reg_index
[aclass
][yregno
]] -= cost
;
952 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
954 ira_object_t obj
= ira_object_id_map
[px
];
955 a
= OBJECT_ALLOCNO (obj
);
958 /* We could increase costs of A instead of making it
959 conflicting with the hard register. But it works worse
960 because it will be spilled in reload in anyway. */
961 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
962 reg_class_contents
[cl
]);
963 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
964 reg_class_contents
[cl
]);
970 /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
971 we find a SET rtx that we can use to deduce that a register can be cheaply
972 caller-saved. Return such a register, or NULL_RTX if none is found. */
974 find_call_crossed_cheap_reg (rtx_insn
*insn
)
976 rtx cheap_reg
= NULL_RTX
;
977 rtx exp
= CALL_INSN_FUNCTION_USAGE (insn
);
981 rtx x
= XEXP (exp
, 0);
982 if (GET_CODE (x
) == SET
)
991 basic_block bb
= BLOCK_FOR_INSN (insn
);
992 rtx reg
= SET_SRC (exp
);
993 rtx_insn
*prev
= PREV_INSN (insn
);
994 while (prev
&& !(INSN_P (prev
)
995 && BLOCK_FOR_INSN (prev
) != bb
))
997 if (NONDEBUG_INSN_P (prev
))
999 rtx set
= single_set (prev
);
1001 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
1003 rtx src
= SET_SRC (set
);
1004 if (!REG_P (src
) || HARD_REGISTER_P (src
)
1005 || !pseudo_regno_single_word_and_live_p (REGNO (src
)))
1007 if (!modified_between_p (src
, prev
, insn
))
1011 if (set
&& rtx_equal_p (SET_SRC (set
), reg
))
1013 rtx dest
= SET_DEST (set
);
1014 if (!REG_P (dest
) || HARD_REGISTER_P (dest
)
1015 || !pseudo_regno_single_word_and_live_p (REGNO (dest
)))
1017 if (!modified_between_p (dest
, prev
, insn
))
1022 if (reg_overlap_mentioned_p (reg
, PATTERN (prev
)))
1025 prev
= PREV_INSN (prev
);
1031 /* Process insns of the basic block given by its LOOP_TREE_NODE to
1032 update allocno live ranges, allocno hard register conflicts,
1033 intersected calls, and register pressure info for allocnos for the
1034 basic block for and regions containing the basic block. */
1036 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node
)
1043 bitmap reg_live_out
;
1047 bb
= loop_tree_node
->bb
;
1050 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1052 curr_reg_pressure
[ira_pressure_classes
[i
]] = 0;
1053 high_pressure_start_point
[ira_pressure_classes
[i
]] = -1;
1055 curr_bb_node
= loop_tree_node
;
1056 reg_live_out
= df_get_live_out (bb
);
1057 sparseset_clear (objects_live
);
1058 REG_SET_TO_HARD_REG_SET (hard_regs_live
, reg_live_out
);
1059 AND_COMPL_HARD_REG_SET (hard_regs_live
, eliminable_regset
);
1060 AND_COMPL_HARD_REG_SET (hard_regs_live
, ira_no_alloc_regs
);
1061 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1062 if (TEST_HARD_REG_BIT (hard_regs_live
, i
))
1064 enum reg_class aclass
, pclass
, cl
;
1066 aclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (i
)];
1067 pclass
= ira_pressure_class_translate
[aclass
];
1069 (cl
= ira_reg_class_super_classes
[pclass
][j
])
1073 if (! ira_reg_pressure_class_p
[cl
])
1075 curr_reg_pressure
[cl
]++;
1076 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
1077 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
1078 ira_assert (curr_reg_pressure
[cl
]
1079 <= ira_class_hard_regs_num
[cl
]);
1082 EXECUTE_IF_SET_IN_BITMAP (reg_live_out
, FIRST_PSEUDO_REGISTER
, j
, bi
)
1083 mark_pseudo_regno_live (j
);
1085 freq
= REG_FREQ_FROM_BB (bb
);
1089 /* Invalidate all allocno_saved_at_call entries. */
1092 /* Scan the code of this basic block, noting which allocnos and
1093 hard regs are born or die.
1095 Note that this loop treats uninitialized values as live until
1096 the beginning of the block. For example, if an instruction
1097 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1098 set, FOO will remain live until the beginning of the block.
1099 Likewise if FOO is not set at all. This is unnecessarily
1100 pessimistic, but it probably doesn't matter much in practice. */
1101 FOR_BB_INSNS_REVERSE (bb
, insn
)
1107 if (!NONDEBUG_INSN_P (insn
))
1110 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1111 fprintf (ira_dump_file
, " Insn %u(l%d): point = %d\n",
1112 INSN_UID (insn
), loop_tree_node
->parent
->loop_num
,
1115 call_p
= CALL_P (insn
);
1116 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1118 bool clear_pic_use_conflict_p
= false;
1119 /* Processing insn usage in call insn can create conflict
1120 with pic pseudo and pic hard reg and that is wrong.
1121 Check this situation and fix it at the end of the insn
1123 if (call_p
&& pic_offset_table_rtx
!= NULL_RTX
1124 && (regno
= REGNO (pic_offset_table_rtx
)) >= FIRST_PSEUDO_REGISTER
1125 && (a
= ira_curr_regno_allocno_map
[regno
]) != NULL
)
1126 clear_pic_use_conflict_p
1127 = (find_regno_fusage (insn
, USE
, REAL_PIC_OFFSET_TABLE_REGNUM
)
1128 && ! TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS
1129 (ALLOCNO_OBJECT (a
, 0)),
1130 REAL_PIC_OFFSET_TABLE_REGNUM
));
1133 /* Mark each defined value as live. We need to do this for
1134 unused values because they still conflict with quantities
1135 that are live at the time of the definition.
1137 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1138 references represent the effect of the called function
1139 on a call-clobbered register. Marking the register as
1140 live would stop us from allocating it to a call-crossing
1142 FOR_EACH_INSN_DEF (def
, insn
)
1143 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1144 mark_ref_live (def
);
1146 /* If INSN has multiple outputs, then any value used in one
1147 of the outputs conflicts with the other outputs. Model this
1148 by making the used value live during the output phase.
1150 It is unsafe to use !single_set here since it will ignore
1151 an unused output. Just because an output is unused does
1152 not mean the compiler can assume the side effect will not
1153 occur. Consider if ALLOCNO appears in the address of an
1154 output and we reload the output. If we allocate ALLOCNO
1155 to the same hard register as an unused output we could
1156 set the hard register before the output reload insn. */
1157 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1158 FOR_EACH_INSN_USE (use
, insn
)
1163 reg
= DF_REF_REG (use
);
1164 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
1168 set
= XVECEXP (PATTERN (insn
), 0, i
);
1169 if (GET_CODE (set
) == SET
1170 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1172 /* After the previous loop, this is a no-op if
1173 REG is contained within SET_DEST (SET). */
1174 mark_ref_live (use
);
1180 extract_insn (insn
);
1181 preferred_alternatives
= get_preferred_alternatives (insn
);
1182 preprocess_constraints (insn
);
1183 process_single_reg_class_operands (false, freq
);
1185 /* See which defined values die here. */
1186 FOR_EACH_INSN_DEF (def
, insn
)
1187 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1188 mark_ref_dead (def
);
1192 /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1193 there, try to find a pseudo that is live across the call but
1194 can be cheaply reconstructed from the return value. */
1195 rtx cheap_reg
= find_call_crossed_cheap_reg (insn
);
1196 if (cheap_reg
!= NULL_RTX
)
1197 add_reg_note (insn
, REG_RETURNED
, cheap_reg
);
1200 sparseset_clear (allocnos_processed
);
1201 /* The current set of live allocnos are live across the call. */
1202 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1204 ira_object_t obj
= ira_object_id_map
[i
];
1205 a
= OBJECT_ALLOCNO (obj
);
1206 int num
= ALLOCNO_NUM (a
);
1207 HARD_REG_SET this_call_used_reg_set
;
1209 get_call_reg_set_usage (insn
, &this_call_used_reg_set
,
1212 /* Don't allocate allocnos that cross setjmps or any
1213 call, if this function receives a nonlocal
1215 if (cfun
->has_nonlocal_label
1216 || find_reg_note (insn
, REG_SETJMP
,
1217 NULL_RTX
) != NULL_RTX
)
1219 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
));
1220 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
));
1222 if (can_throw_internal (insn
))
1224 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
1225 this_call_used_reg_set
);
1226 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1227 this_call_used_reg_set
);
1230 if (sparseset_bit_p (allocnos_processed
, num
))
1232 sparseset_set_bit (allocnos_processed
, num
);
1234 if (allocno_saved_at_call
[num
] != last_call_num
)
1235 /* Here we are mimicking caller-save.c behavior
1236 which does not save hard register at a call if
1237 it was saved on previous call in the same basic
1238 block and the hard register was not mentioned
1239 between the two calls. */
1240 ALLOCNO_CALL_FREQ (a
) += freq
;
1241 /* Mark it as saved at the next call. */
1242 allocno_saved_at_call
[num
] = last_call_num
+ 1;
1243 ALLOCNO_CALLS_CROSSED_NUM (a
)++;
1244 IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
),
1245 this_call_used_reg_set
);
1246 if (cheap_reg
!= NULL_RTX
1247 && ALLOCNO_REGNO (a
) == (int) REGNO (cheap_reg
))
1248 ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
)++;
1252 make_early_clobber_and_input_conflicts ();
1256 /* Mark each used value as live. */
1257 FOR_EACH_INSN_USE (use
, insn
)
1258 mark_ref_live (use
);
1260 process_single_reg_class_operands (true, freq
);
1262 set_p
= mark_hard_reg_early_clobbers (insn
, true);
1266 mark_hard_reg_early_clobbers (insn
, false);
1268 /* Mark each hard reg as live again. For example, a
1269 hard register can be in clobber and in an insn
1271 FOR_EACH_INSN_USE (use
, insn
)
1273 rtx ureg
= DF_REF_REG (use
);
1275 if (GET_CODE (ureg
) == SUBREG
)
1276 ureg
= SUBREG_REG (ureg
);
1277 if (! REG_P (ureg
) || REGNO (ureg
) >= FIRST_PSEUDO_REGISTER
)
1280 mark_ref_live (use
);
1284 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1285 if (clear_pic_use_conflict_p
)
1287 regno
= REGNO (pic_offset_table_rtx
);
1288 a
= ira_curr_regno_allocno_map
[regno
];
1289 CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a
, 0)),
1290 REAL_PIC_OFFSET_TABLE_REGNUM
);
1291 CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS
1292 (ALLOCNO_OBJECT (a
, 0)),
1293 REAL_PIC_OFFSET_TABLE_REGNUM
);
1299 if (bb_has_eh_pred (bb
))
1302 unsigned int regno
= EH_RETURN_DATA_REGNO (j
);
1303 if (regno
== INVALID_REGNUM
)
1305 make_hard_regno_born (regno
);
1308 /* Allocnos can't go in stack regs at the start of a basic block
1309 that is reached by an abnormal edge. Likewise for call
1310 clobbered regs, because caller-save, fixup_abnormal_edges and
1311 possibly the table driven EH machinery are not quite ready to
1312 handle such allocnos live across such edges. */
1313 if (bb_has_abnormal_pred (bb
))
1316 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1318 ira_allocno_t a
= OBJECT_ALLOCNO (ira_object_id_map
[px
]);
1320 ALLOCNO_NO_STACK_REG_P (a
) = true;
1321 ALLOCNO_TOTAL_NO_STACK_REG_P (a
) = true;
1323 for (px
= FIRST_STACK_REG
; px
<= LAST_STACK_REG
; px
++)
1324 make_hard_regno_born (px
);
1326 /* No need to record conflicts for call clobbered regs if we
1327 have nonlocal labels around, as we don't ever try to
1328 allocate such regs in this case. */
1329 if (!cfun
->has_nonlocal_label
1330 && has_abnormal_call_or_eh_pred_edge_p (bb
))
1331 for (px
= 0; px
< FIRST_PSEUDO_REGISTER
; px
++)
1332 if (call_used_regs
[px
]
1333 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1334 /* We should create a conflict of PIC pseudo with
1335 PIC hard reg as PIC hard reg can have a wrong
1336 value after jump described by the abnormal edge.
1337 In this case we can not allocate PIC hard reg to
1338 PIC pseudo as PIC pseudo will also have a wrong
1339 value. This code is not critical as LRA can fix
1340 it but it is better to have the right allocation
1342 || (px
== REAL_PIC_OFFSET_TABLE_REGNUM
1343 && pic_offset_table_rtx
!= NULL_RTX
1344 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
1347 make_hard_regno_born (px
);
1350 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1351 make_object_dead (ira_object_id_map
[i
]);
1356 /* Propagate register pressure to upper loop tree nodes. */
1357 if (loop_tree_node
!= ira_loop_tree_root
)
1358 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1360 enum reg_class pclass
;
1362 pclass
= ira_pressure_classes
[i
];
1363 if (loop_tree_node
->reg_pressure
[pclass
]
1364 > loop_tree_node
->parent
->reg_pressure
[pclass
])
1365 loop_tree_node
->parent
->reg_pressure
[pclass
]
1366 = loop_tree_node
->reg_pressure
[pclass
];
1370 /* Create and set up IRA_START_POINT_RANGES and
1371 IRA_FINISH_POINT_RANGES. */
1373 create_start_finish_chains (void)
1376 ira_object_iterator oi
;
1379 ira_start_point_ranges
1380 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1381 memset (ira_start_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1382 ira_finish_point_ranges
1383 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1384 memset (ira_finish_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1385 FOR_EACH_OBJECT (obj
, oi
)
1386 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1388 r
->start_next
= ira_start_point_ranges
[r
->start
];
1389 ira_start_point_ranges
[r
->start
] = r
;
1390 r
->finish_next
= ira_finish_point_ranges
[r
->finish
];
1391 ira_finish_point_ranges
[r
->finish
] = r
;
1395 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1396 new live ranges and program points were added as a result if new
1399 ira_rebuild_start_finish_chains (void)
1401 ira_free (ira_finish_point_ranges
);
1402 ira_free (ira_start_point_ranges
);
1403 create_start_finish_chains ();
1406 /* Compress allocno live ranges by removing program points where
1409 remove_some_program_points_and_update_live_ranges (void)
1415 ira_object_iterator oi
;
1416 live_range_t r
, prev_r
, next_r
;
1417 sbitmap born_or_dead
, born
, dead
;
1418 sbitmap_iterator sbi
;
1419 bool born_p
, dead_p
, prev_born_p
, prev_dead_p
;
1421 born
= sbitmap_alloc (ira_max_point
);
1422 dead
= sbitmap_alloc (ira_max_point
);
1423 bitmap_clear (born
);
1424 bitmap_clear (dead
);
1425 FOR_EACH_OBJECT (obj
, oi
)
1426 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1428 ira_assert (r
->start
<= r
->finish
);
1429 bitmap_set_bit (born
, r
->start
);
1430 bitmap_set_bit (dead
, r
->finish
);
1433 born_or_dead
= sbitmap_alloc (ira_max_point
);
1434 bitmap_ior (born_or_dead
, born
, dead
);
1435 map
= (int *) ira_allocate (sizeof (int) * ira_max_point
);
1437 prev_born_p
= prev_dead_p
= false;
1438 EXECUTE_IF_SET_IN_BITMAP (born_or_dead
, 0, i
, sbi
)
1440 born_p
= bitmap_bit_p (born
, i
);
1441 dead_p
= bitmap_bit_p (dead
, i
);
1442 if ((prev_born_p
&& ! prev_dead_p
&& born_p
&& ! dead_p
)
1443 || (prev_dead_p
&& ! prev_born_p
&& dead_p
&& ! born_p
))
1447 prev_born_p
= born_p
;
1448 prev_dead_p
= dead_p
;
1450 sbitmap_free (born_or_dead
);
1451 sbitmap_free (born
);
1452 sbitmap_free (dead
);
1454 if (internal_flag_ira_verbose
> 1 && ira_dump_file
!= NULL
)
1455 fprintf (ira_dump_file
, "Compressing live ranges: from %d to %d - %d%%\n",
1456 ira_max_point
, n
, 100 * n
/ ira_max_point
);
1459 FOR_EACH_OBJECT (obj
, oi
)
1460 for (r
= OBJECT_LIVE_RANGES (obj
), prev_r
= NULL
; r
!= NULL
; r
= next_r
)
1463 r
->start
= map
[r
->start
];
1464 r
->finish
= map
[r
->finish
];
1465 if (prev_r
== NULL
|| prev_r
->start
> r
->finish
+ 1)
1470 prev_r
->start
= r
->start
;
1471 prev_r
->next
= next_r
;
1472 ira_finish_live_range (r
);
1478 /* Print live ranges R to file F. */
1480 ira_print_live_range_list (FILE *f
, live_range_t r
)
1482 for (; r
!= NULL
; r
= r
->next
)
1483 fprintf (f
, " [%d..%d]", r
->start
, r
->finish
);
1488 debug (live_range
&ref
)
1490 ira_print_live_range_list (stderr
, &ref
);
1494 debug (live_range
*ptr
)
1499 fprintf (stderr
, "<nil>\n");
1502 /* Print live ranges R to stderr. */
1504 ira_debug_live_range_list (live_range_t r
)
1506 ira_print_live_range_list (stderr
, r
);
1509 /* Print live ranges of object OBJ to file F. */
1511 print_object_live_ranges (FILE *f
, ira_object_t obj
)
1513 ira_print_live_range_list (f
, OBJECT_LIVE_RANGES (obj
));
1516 /* Print live ranges of allocno A to file F. */
1518 print_allocno_live_ranges (FILE *f
, ira_allocno_t a
)
1520 int n
= ALLOCNO_NUM_OBJECTS (a
);
1523 for (i
= 0; i
< n
; i
++)
1525 fprintf (f
, " a%d(r%d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
1527 fprintf (f
, " [%d]", i
);
1529 print_object_live_ranges (f
, ALLOCNO_OBJECT (a
, i
));
1533 /* Print live ranges of allocno A to stderr. */
1535 ira_debug_allocno_live_ranges (ira_allocno_t a
)
1537 print_allocno_live_ranges (stderr
, a
);
1540 /* Print live ranges of all allocnos to file F. */
1542 print_live_ranges (FILE *f
)
1545 ira_allocno_iterator ai
;
1547 FOR_EACH_ALLOCNO (a
, ai
)
1548 print_allocno_live_ranges (f
, a
);
1551 /* Print live ranges of all allocnos to stderr. */
1553 ira_debug_live_ranges (void)
1555 print_live_ranges (stderr
);
1558 /* The main entry function creates live ranges, set up
1559 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1560 calculate register pressure info. */
1562 ira_create_allocno_live_ranges (void)
1564 objects_live
= sparseset_alloc (ira_objects_num
);
1565 allocnos_processed
= sparseset_alloc (ira_allocnos_num
);
1568 allocno_saved_at_call
1569 = (int *) ira_allocate (ira_allocnos_num
* sizeof (int));
1570 memset (allocno_saved_at_call
, 0, ira_allocnos_num
* sizeof (int));
1571 ira_traverse_loop_tree (true, ira_loop_tree_root
, NULL
,
1572 process_bb_node_lives
);
1573 ira_max_point
= curr_point
;
1574 create_start_finish_chains ();
1575 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1576 print_live_ranges (ira_dump_file
);
1578 ira_free (allocno_saved_at_call
);
1579 sparseset_free (objects_live
);
1580 sparseset_free (allocnos_processed
);
1583 /* Compress allocno live ranges. */
1585 ira_compress_allocno_live_ranges (void)
1587 remove_some_program_points_and_update_live_ranges ();
1588 ira_rebuild_start_finish_chains ();
1589 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1591 fprintf (ira_dump_file
, "Ranges after the compression:\n");
1592 print_live_ranges (ira_dump_file
);
1596 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1598 ira_finish_allocno_live_ranges (void)
1600 ira_free (ira_finish_point_ranges
);
1601 ira_free (ira_start_point_ranges
);