1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
36 #include "stringpool.h"
43 #include "diagnostic.h"
44 #include "insn-attr.h"
47 #include "fold-const.h"
49 #include "stor-layout.h"
55 #include "common/common-target.h"
56 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "target-globals.h"
62 #include "tree-pass.h"
67 /* This file should be included last. */
68 #include "target-def.h"
70 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
71 #define UNSPEC_ADDRESS_P(X) \
72 (GET_CODE (X) == UNSPEC \
73 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
74 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
76 /* Extract the symbol or label from UNSPEC wrapper X. */
77 #define UNSPEC_ADDRESS(X) \
80 /* Extract the symbol type from UNSPEC wrapper X. */
81 #define UNSPEC_ADDRESS_TYPE(X) \
82 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
84 /* The maximum distance between the top of the stack frame and the
85 value $sp has when we save and restore registers.
87 The value for normal-mode code must be a SMALL_OPERAND and must
88 preserve the maximum stack alignment. We therefore use a value
89 of 0x7ff0 in this case.
91 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
92 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
94 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
95 up to 0x7f8 bytes and can usually save or restore all the registers
96 that we need to save or restore. (Note that we can only use these
97 instructions for o32, for which the stack alignment is 8 bytes.)
99 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
100 RESTORE are not available. We can then use unextended instructions
101 to save and restore registers, and to allocate and deallocate the top
102 part of the frame. */
103 #define MIPS_MAX_FIRST_STACK_STEP \
104 (!TARGET_COMPRESSION ? 0x7ff0 \
105 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
106 : TARGET_64BIT ? 0x100 : 0x400)
108 /* True if INSN is a mips.md pattern or asm statement. */
109 /* ??? This test exists through the compiler, perhaps it should be
111 #define USEFUL_INSN_P(INSN) \
112 (NONDEBUG_INSN_P (INSN) \
113 && GET_CODE (PATTERN (INSN)) != USE \
114 && GET_CODE (PATTERN (INSN)) != CLOBBER)
116 /* If INSN is a delayed branch sequence, return the first instruction
117 in the sequence, otherwise return INSN itself. */
118 #define SEQ_BEGIN(INSN) \
119 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
120 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
123 /* Likewise for the last instruction in a delayed branch sequence. */
124 #define SEQ_END(INSN) \
125 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
126 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
128 XVECLEN (PATTERN (INSN), 0) - 1)) \
131 /* Execute the following loop body with SUBINSN set to each instruction
132 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
133 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
134 for ((SUBINSN) = SEQ_BEGIN (INSN); \
135 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
136 (SUBINSN) = NEXT_INSN (SUBINSN))
138 /* True if bit BIT is set in VALUE. */
139 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
141 /* Return the opcode for a ptr_mode load of the form:
143 l[wd] DEST, OFFSET(BASE). */
144 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
145 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
150 /* Return the opcode to move register SRC into register DEST. */
151 #define MIPS_MOVE(DEST, SRC) \
152 ((TARGET_64BIT ? 0x2d : 0x21) \
156 /* Return the opcode for:
159 #define MIPS_LUI(DEST, VALUE) \
160 ((0xf << 26) | ((DEST) << 16) | (VALUE))
162 /* Return the opcode to jump to register DEST. When the JR opcode is not
163 available use JALR $0, DEST. */
164 #define MIPS_JR(DEST) \
165 (TARGET_CB_ALWAYS ? ((0x1b << 27) | ((DEST) << 16)) \
166 : (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9)))
168 /* Return the opcode for:
170 bal . + (1 + OFFSET) * 4. */
171 #define MIPS_BAL(OFFSET) \
172 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
174 /* Return the usual opcode for a nop. */
177 /* Classifies an address.
180 A natural register + offset address. The register satisfies
181 mips_valid_base_register_p and the offset is a const_arith_operand.
184 A LO_SUM rtx. The first operand is a valid base register and
185 the second operand is a symbolic address.
188 A signed 16-bit constant address.
191 A constant symbolic address. */
192 enum mips_address_type
{
199 /* Macros to create an enumeration identifier for a function prototype. */
200 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
201 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
202 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
203 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
205 /* Classifies the prototype of a built-in function. */
206 enum mips_function_type
{
207 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
208 #include "config/mips/mips-ftypes.def"
209 #undef DEF_MIPS_FTYPE
213 /* Specifies how a built-in function should be converted into rtl. */
214 enum mips_builtin_type
{
215 /* The function corresponds directly to an .md pattern. The return
216 value is mapped to operand 0 and the arguments are mapped to
217 operands 1 and above. */
220 /* The function corresponds directly to an .md pattern. There is no return
221 value and the arguments are mapped to operands 0 and above. */
222 MIPS_BUILTIN_DIRECT_NO_TARGET
,
224 /* The function corresponds to a comparison instruction followed by
225 a mips_cond_move_tf_ps pattern. The first two arguments are the
226 values to compare and the second two arguments are the vector
227 operands for the movt.ps or movf.ps instruction (in assembly order). */
231 /* The function corresponds to a V2SF comparison instruction. Operand 0
232 of this instruction is the result of the comparison, which has mode
233 CCV2 or CCV4. The function arguments are mapped to operands 1 and
234 above. The function's return value is an SImode boolean that is
235 true under the following conditions:
237 MIPS_BUILTIN_CMP_ANY: one of the registers is true
238 MIPS_BUILTIN_CMP_ALL: all of the registers are true
239 MIPS_BUILTIN_CMP_LOWER: the first register is true
240 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
241 MIPS_BUILTIN_CMP_ANY
,
242 MIPS_BUILTIN_CMP_ALL
,
243 MIPS_BUILTIN_CMP_UPPER
,
244 MIPS_BUILTIN_CMP_LOWER
,
246 /* As above, but the instruction only sets a single $fcc register. */
247 MIPS_BUILTIN_CMP_SINGLE
,
249 /* The function corresponds to an MSA conditional branch instruction
250 combined with a compare instruction. */
251 MIPS_BUILTIN_MSA_TEST_BRANCH
,
253 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
254 MIPS_BUILTIN_BPOSGE32
257 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
258 #define MIPS_FP_CONDITIONS(MACRO) \
276 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
277 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
278 enum mips_fp_condition
{
279 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
281 #undef DECLARE_MIPS_COND
283 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
284 #define STRINGIFY(X) #X
285 static const char *const mips_fp_conditions
[] = {
286 MIPS_FP_CONDITIONS (STRINGIFY
)
290 /* A class used to control a comdat-style stub that we output in each
291 translation unit that needs it. */
292 class mips_one_only_stub
{
294 virtual ~mips_one_only_stub () {}
296 /* Return the name of the stub. */
297 virtual const char *get_name () = 0;
299 /* Output the body of the function to asm_out_file. */
300 virtual void output_body () = 0;
303 /* Tuning information that is automatically derived from other sources
304 (such as the scheduler). */
306 /* The architecture and tuning settings that this structure describes. */
310 /* True if this structure describes MIPS16 settings. */
313 /* True if the structure has been initialized. */
316 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
317 when optimizing for speed. */
318 bool fast_mult_zero_zero_p
;
321 /* Information about a single argument. */
322 struct mips_arg_info
{
323 /* True if the argument is passed in a floating-point register, or
324 would have been if we hadn't run out of registers. */
327 /* The number of words passed in registers, rounded up. */
328 unsigned int reg_words
;
330 /* For EABI, the offset of the first register from GP_ARG_FIRST or
331 FP_ARG_FIRST. For other ABIs, the offset of the first register from
332 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
333 comment for details).
335 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
337 unsigned int reg_offset
;
339 /* The number of words that must be passed on the stack, rounded up. */
340 unsigned int stack_words
;
342 /* The offset from the start of the stack overflow area of the argument's
343 first stack word. Only meaningful when STACK_WORDS is nonzero. */
344 unsigned int stack_offset
;
347 /* Information about an address described by mips_address_type.
353 REG is the base register and OFFSET is the constant offset.
356 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
357 is the type of symbol it references.
360 SYMBOL_TYPE is the type of symbol that the address references. */
361 struct mips_address_info
{
362 enum mips_address_type type
;
365 enum mips_symbol_type symbol_type
;
368 /* One stage in a constant building sequence. These sequences have
372 A = A CODE[1] VALUE[1]
373 A = A CODE[2] VALUE[2]
376 where A is an accumulator, each CODE[i] is a binary rtl operation
377 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
378 struct mips_integer_op
{
380 unsigned HOST_WIDE_INT value
;
383 /* The largest number of operations needed to load an integer constant.
384 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
385 When the lowest bit is clear, we can try, but reject a sequence with
386 an extra SLL at the end. */
387 #define MIPS_MAX_INTEGER_OPS 7
389 /* Information about a MIPS16e SAVE or RESTORE instruction. */
390 struct mips16e_save_restore_info
{
391 /* The number of argument registers saved by a SAVE instruction.
392 0 for RESTORE instructions. */
395 /* Bit X is set if the instruction saves or restores GPR X. */
398 /* The total number of bytes to allocate. */
402 /* Costs of various operations on the different architectures. */
404 struct mips_rtx_cost_data
406 unsigned short fp_add
;
407 unsigned short fp_mult_sf
;
408 unsigned short fp_mult_df
;
409 unsigned short fp_div_sf
;
410 unsigned short fp_div_df
;
411 unsigned short int_mult_si
;
412 unsigned short int_mult_di
;
413 unsigned short int_div_si
;
414 unsigned short int_div_di
;
415 unsigned short branch_cost
;
416 unsigned short memory_latency
;
419 /* Global variables for machine-dependent things. */
421 /* The -G setting, or the configuration's default small-data limit if
422 no -G option is given. */
423 static unsigned int mips_small_data_threshold
;
425 /* The number of file directives written by mips_output_filename. */
426 int num_source_filenames
;
428 /* The name that appeared in the last .file directive written by
429 mips_output_filename, or "" if mips_output_filename hasn't
430 written anything yet. */
431 const char *current_function_file
= "";
433 /* Arrays that map GCC register numbers to debugger register numbers. */
434 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
435 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
437 /* Information about the current function's epilogue, used only while
440 /* A list of queued REG_CFA_RESTORE notes. */
443 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
445 HOST_WIDE_INT cfa_offset
;
447 /* The offset of the CFA from the stack pointer while restoring
449 HOST_WIDE_INT cfa_restore_sp_offset
;
452 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
453 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
454 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
455 struct mips_asm_switch mips_noat
= { "at", 0 };
457 /* True if we're writing out a branch-likely instruction rather than a
459 static bool mips_branch_likely
;
461 /* The current instruction-set architecture. */
462 enum processor mips_arch
;
463 const struct mips_cpu_info
*mips_arch_info
;
465 /* The processor that we should tune the code for. */
466 enum processor mips_tune
;
467 const struct mips_cpu_info
*mips_tune_info
;
469 /* The ISA level associated with mips_arch. */
472 /* The ISA revision level. This is 0 for MIPS I to V and N for
476 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
477 static const struct mips_cpu_info
*mips_isa_option_info
;
479 /* Which cost information to use. */
480 static const struct mips_rtx_cost_data
*mips_cost
;
482 /* The ambient target flags, excluding MASK_MIPS16. */
483 static int mips_base_target_flags
;
485 /* The default compression mode. */
486 unsigned int mips_base_compression_flags
;
488 /* The ambient values of other global variables. */
489 static int mips_base_schedule_insns
; /* flag_schedule_insns */
490 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
491 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
492 static int mips_base_align_loops
; /* align_loops */
493 static int mips_base_align_jumps
; /* align_jumps */
494 static int mips_base_align_functions
; /* align_functions */
496 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
497 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
499 /* Index C is true if character C is a valid PRINT_OPERAND punctation
501 static bool mips_print_operand_punct
[256];
503 static GTY (()) int mips_output_filename_first_time
= 1;
505 /* mips_split_p[X] is true if symbols of type X can be split by
506 mips_split_symbol. */
507 bool mips_split_p
[NUM_SYMBOL_TYPES
];
509 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
510 can be split by mips_split_symbol. */
511 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
513 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
514 forced into a PC-relative constant pool. */
515 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
517 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
518 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
519 if they are matched by a special .md file pattern. */
520 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
522 /* Likewise for HIGHs. */
523 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
525 /* Target state for MIPS16. */
526 struct target_globals
*mips16_globals
;
528 /* Target state for MICROMIPS. */
529 struct target_globals
*micromips_globals
;
531 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
532 and returned from mips_sched_reorder2. */
533 static int cached_can_issue_more
;
535 /* The stubs for various MIPS16 support functions, if used. */
536 static mips_one_only_stub
*mips16_rdhwr_stub
;
537 static mips_one_only_stub
*mips16_get_fcsr_stub
;
538 static mips_one_only_stub
*mips16_set_fcsr_stub
;
540 /* Index R is the smallest register class that contains register R. */
541 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
542 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
543 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
544 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
545 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
546 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
547 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
548 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
549 LEA_REGS
, M16_SP_REGS
, LEA_REGS
, LEA_REGS
,
551 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
552 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
553 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
554 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
555 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
556 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
557 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
558 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
559 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
560 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
561 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
562 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
563 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
564 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
565 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
566 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
567 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
568 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
569 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
570 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
571 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
572 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
573 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
574 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
575 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
576 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
577 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
578 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
579 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
580 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
581 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
582 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
583 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
584 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
585 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
586 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
587 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
588 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
589 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
592 static tree
mips_handle_interrupt_attr (tree
*, tree
, tree
, int, bool *);
593 static tree
mips_handle_use_shadow_register_set_attr (tree
*, tree
, tree
, int,
596 /* The value of TARGET_ATTRIBUTE_TABLE. */
597 static const struct attribute_spec mips_attribute_table
[] = {
598 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
600 { "long_call", 0, 0, false, true, true, NULL
, false },
601 { "far", 0, 0, false, true, true, NULL
, false },
602 { "near", 0, 0, false, true, true, NULL
, false },
603 /* We would really like to treat "mips16" and "nomips16" as type
604 attributes, but GCC doesn't provide the hooks we need to support
605 the right conversion rules. As declaration attributes, they affect
606 code generation but don't carry other semantics. */
607 { "mips16", 0, 0, true, false, false, NULL
, false },
608 { "nomips16", 0, 0, true, false, false, NULL
, false },
609 { "micromips", 0, 0, true, false, false, NULL
, false },
610 { "nomicromips", 0, 0, true, false, false, NULL
, false },
611 { "nocompression", 0, 0, true, false, false, NULL
, false },
612 /* Allow functions to be specified as interrupt handlers */
613 { "interrupt", 0, 1, false, true, true, mips_handle_interrupt_attr
,
615 { "use_shadow_register_set", 0, 1, false, true, true,
616 mips_handle_use_shadow_register_set_attr
, false },
617 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
618 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
619 { NULL
, 0, 0, false, false, false, NULL
, false }
622 /* A table describing all the processors GCC knows about; see
623 mips-cpus.def for details. */
624 static const struct mips_cpu_info mips_cpu_info_table
[] = {
625 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
626 { NAME, CPU, ISA, FLAGS },
627 #include "mips-cpus.def"
631 /* Default costs. If these are used for a processor we should look
632 up the actual costs. */
633 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
634 COSTS_N_INSNS (7), /* fp_mult_sf */ \
635 COSTS_N_INSNS (8), /* fp_mult_df */ \
636 COSTS_N_INSNS (23), /* fp_div_sf */ \
637 COSTS_N_INSNS (36), /* fp_div_df */ \
638 COSTS_N_INSNS (10), /* int_mult_si */ \
639 COSTS_N_INSNS (10), /* int_mult_di */ \
640 COSTS_N_INSNS (69), /* int_div_si */ \
641 COSTS_N_INSNS (69), /* int_div_di */ \
642 2, /* branch_cost */ \
643 4 /* memory_latency */
645 /* Floating-point costs for processors without an FPU. Just assume that
646 all floating-point libcalls are very expensive. */
647 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
648 COSTS_N_INSNS (256), /* fp_mult_sf */ \
649 COSTS_N_INSNS (256), /* fp_mult_df */ \
650 COSTS_N_INSNS (256), /* fp_div_sf */ \
651 COSTS_N_INSNS (256) /* fp_div_df */
653 /* Costs to use when optimizing for size. */
654 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
655 COSTS_N_INSNS (1), /* fp_add */
656 COSTS_N_INSNS (1), /* fp_mult_sf */
657 COSTS_N_INSNS (1), /* fp_mult_df */
658 COSTS_N_INSNS (1), /* fp_div_sf */
659 COSTS_N_INSNS (1), /* fp_div_df */
660 COSTS_N_INSNS (1), /* int_mult_si */
661 COSTS_N_INSNS (1), /* int_mult_di */
662 COSTS_N_INSNS (1), /* int_div_si */
663 COSTS_N_INSNS (1), /* int_div_di */
665 4 /* memory_latency */
668 /* Costs to use when optimizing for speed, indexed by processor. */
669 static const struct mips_rtx_cost_data
670 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
672 COSTS_N_INSNS (2), /* fp_add */
673 COSTS_N_INSNS (4), /* fp_mult_sf */
674 COSTS_N_INSNS (5), /* fp_mult_df */
675 COSTS_N_INSNS (12), /* fp_div_sf */
676 COSTS_N_INSNS (19), /* fp_div_df */
677 COSTS_N_INSNS (12), /* int_mult_si */
678 COSTS_N_INSNS (12), /* int_mult_di */
679 COSTS_N_INSNS (35), /* int_div_si */
680 COSTS_N_INSNS (35), /* int_div_di */
682 4 /* memory_latency */
686 COSTS_N_INSNS (6), /* int_mult_si */
687 COSTS_N_INSNS (6), /* int_mult_di */
688 COSTS_N_INSNS (36), /* int_div_si */
689 COSTS_N_INSNS (36), /* int_div_di */
691 4 /* memory_latency */
695 COSTS_N_INSNS (36), /* int_mult_si */
696 COSTS_N_INSNS (36), /* int_mult_di */
697 COSTS_N_INSNS (37), /* int_div_si */
698 COSTS_N_INSNS (37), /* int_div_di */
700 4 /* memory_latency */
704 COSTS_N_INSNS (4), /* int_mult_si */
705 COSTS_N_INSNS (11), /* int_mult_di */
706 COSTS_N_INSNS (36), /* int_div_si */
707 COSTS_N_INSNS (68), /* int_div_di */
709 4 /* memory_latency */
712 COSTS_N_INSNS (4), /* fp_add */
713 COSTS_N_INSNS (4), /* fp_mult_sf */
714 COSTS_N_INSNS (5), /* fp_mult_df */
715 COSTS_N_INSNS (17), /* fp_div_sf */
716 COSTS_N_INSNS (32), /* fp_div_df */
717 COSTS_N_INSNS (4), /* int_mult_si */
718 COSTS_N_INSNS (11), /* int_mult_di */
719 COSTS_N_INSNS (36), /* int_div_si */
720 COSTS_N_INSNS (68), /* int_div_di */
722 4 /* memory_latency */
725 COSTS_N_INSNS (4), /* fp_add */
726 COSTS_N_INSNS (4), /* fp_mult_sf */
727 COSTS_N_INSNS (5), /* fp_mult_df */
728 COSTS_N_INSNS (17), /* fp_div_sf */
729 COSTS_N_INSNS (32), /* fp_div_df */
730 COSTS_N_INSNS (4), /* int_mult_si */
731 COSTS_N_INSNS (7), /* int_mult_di */
732 COSTS_N_INSNS (42), /* int_div_si */
733 COSTS_N_INSNS (72), /* int_div_di */
735 4 /* memory_latency */
739 COSTS_N_INSNS (5), /* int_mult_si */
740 COSTS_N_INSNS (5), /* int_mult_di */
741 COSTS_N_INSNS (41), /* int_div_si */
742 COSTS_N_INSNS (41), /* int_div_di */
744 4 /* memory_latency */
747 COSTS_N_INSNS (8), /* fp_add */
748 COSTS_N_INSNS (8), /* fp_mult_sf */
749 COSTS_N_INSNS (10), /* fp_mult_df */
750 COSTS_N_INSNS (34), /* fp_div_sf */
751 COSTS_N_INSNS (64), /* fp_div_df */
752 COSTS_N_INSNS (5), /* int_mult_si */
753 COSTS_N_INSNS (5), /* int_mult_di */
754 COSTS_N_INSNS (41), /* int_div_si */
755 COSTS_N_INSNS (41), /* int_div_di */
757 4 /* memory_latency */
760 COSTS_N_INSNS (4), /* fp_add */
761 COSTS_N_INSNS (4), /* fp_mult_sf */
762 COSTS_N_INSNS (5), /* fp_mult_df */
763 COSTS_N_INSNS (17), /* fp_div_sf */
764 COSTS_N_INSNS (32), /* fp_div_df */
765 COSTS_N_INSNS (5), /* int_mult_si */
766 COSTS_N_INSNS (5), /* int_mult_di */
767 COSTS_N_INSNS (41), /* int_div_si */
768 COSTS_N_INSNS (41), /* int_div_di */
770 4 /* memory_latency */
774 COSTS_N_INSNS (5), /* int_mult_si */
775 COSTS_N_INSNS (5), /* int_mult_di */
776 COSTS_N_INSNS (41), /* int_div_si */
777 COSTS_N_INSNS (41), /* int_div_di */
779 4 /* memory_latency */
782 COSTS_N_INSNS (8), /* fp_add */
783 COSTS_N_INSNS (8), /* fp_mult_sf */
784 COSTS_N_INSNS (10), /* fp_mult_df */
785 COSTS_N_INSNS (34), /* fp_div_sf */
786 COSTS_N_INSNS (64), /* fp_div_df */
787 COSTS_N_INSNS (5), /* int_mult_si */
788 COSTS_N_INSNS (5), /* int_mult_di */
789 COSTS_N_INSNS (41), /* int_div_si */
790 COSTS_N_INSNS (41), /* int_div_di */
792 4 /* memory_latency */
795 COSTS_N_INSNS (4), /* fp_add */
796 COSTS_N_INSNS (4), /* fp_mult_sf */
797 COSTS_N_INSNS (5), /* fp_mult_df */
798 COSTS_N_INSNS (17), /* fp_div_sf */
799 COSTS_N_INSNS (32), /* fp_div_df */
800 COSTS_N_INSNS (5), /* int_mult_si */
801 COSTS_N_INSNS (5), /* int_mult_di */
802 COSTS_N_INSNS (41), /* int_div_si */
803 COSTS_N_INSNS (41), /* int_div_di */
805 4 /* memory_latency */
808 COSTS_N_INSNS (6), /* fp_add */
809 COSTS_N_INSNS (6), /* fp_mult_sf */
810 COSTS_N_INSNS (7), /* fp_mult_df */
811 COSTS_N_INSNS (25), /* fp_div_sf */
812 COSTS_N_INSNS (48), /* fp_div_df */
813 COSTS_N_INSNS (5), /* int_mult_si */
814 COSTS_N_INSNS (5), /* int_mult_di */
815 COSTS_N_INSNS (41), /* int_div_si */
816 COSTS_N_INSNS (41), /* int_div_di */
818 4 /* memory_latency */
835 COSTS_N_INSNS (5), /* int_mult_si */
836 COSTS_N_INSNS (5), /* int_mult_di */
837 COSTS_N_INSNS (72), /* int_div_si */
838 COSTS_N_INSNS (72), /* int_div_di */
840 4 /* memory_latency */
845 COSTS_N_INSNS (6), /* int_mult_si */
846 COSTS_N_INSNS (6), /* int_mult_di */
847 COSTS_N_INSNS (18), /* int_div_si */
848 COSTS_N_INSNS (35), /* int_div_di */
850 4 /* memory_latency */
854 COSTS_N_INSNS (6), /* fp_add */
855 COSTS_N_INSNS (6), /* fp_mult_sf */
856 COSTS_N_INSNS (7), /* fp_mult_df */
857 COSTS_N_INSNS (25), /* fp_div_sf */
858 COSTS_N_INSNS (48), /* fp_div_df */
859 COSTS_N_INSNS (6), /* int_mult_si */
860 COSTS_N_INSNS (6), /* int_mult_di */
861 COSTS_N_INSNS (18), /* int_div_si */
862 COSTS_N_INSNS (35), /* int_div_di */
864 4 /* memory_latency */
867 COSTS_N_INSNS (2), /* fp_add */
868 COSTS_N_INSNS (4), /* fp_mult_sf */
869 COSTS_N_INSNS (5), /* fp_mult_df */
870 COSTS_N_INSNS (12), /* fp_div_sf */
871 COSTS_N_INSNS (19), /* fp_div_df */
872 COSTS_N_INSNS (2), /* int_mult_si */
873 COSTS_N_INSNS (2), /* int_mult_di */
874 COSTS_N_INSNS (35), /* int_div_si */
875 COSTS_N_INSNS (35), /* int_div_di */
877 4 /* memory_latency */
880 COSTS_N_INSNS (3), /* fp_add */
881 COSTS_N_INSNS (5), /* fp_mult_sf */
882 COSTS_N_INSNS (6), /* fp_mult_df */
883 COSTS_N_INSNS (15), /* fp_div_sf */
884 COSTS_N_INSNS (16), /* fp_div_df */
885 COSTS_N_INSNS (17), /* int_mult_si */
886 COSTS_N_INSNS (17), /* int_mult_di */
887 COSTS_N_INSNS (38), /* int_div_si */
888 COSTS_N_INSNS (38), /* int_div_di */
890 6 /* memory_latency */
893 COSTS_N_INSNS (6), /* fp_add */
894 COSTS_N_INSNS (7), /* fp_mult_sf */
895 COSTS_N_INSNS (8), /* fp_mult_df */
896 COSTS_N_INSNS (23), /* fp_div_sf */
897 COSTS_N_INSNS (36), /* fp_div_df */
898 COSTS_N_INSNS (10), /* int_mult_si */
899 COSTS_N_INSNS (10), /* int_mult_di */
900 COSTS_N_INSNS (69), /* int_div_si */
901 COSTS_N_INSNS (69), /* int_div_di */
903 6 /* memory_latency */
915 /* The only costs that appear to be updated here are
916 integer multiplication. */
918 COSTS_N_INSNS (4), /* int_mult_si */
919 COSTS_N_INSNS (6), /* int_mult_di */
920 COSTS_N_INSNS (69), /* int_div_si */
921 COSTS_N_INSNS (69), /* int_div_di */
923 4 /* memory_latency */
938 COSTS_N_INSNS (6), /* fp_add */
939 COSTS_N_INSNS (4), /* fp_mult_sf */
940 COSTS_N_INSNS (5), /* fp_mult_df */
941 COSTS_N_INSNS (23), /* fp_div_sf */
942 COSTS_N_INSNS (36), /* fp_div_df */
943 COSTS_N_INSNS (5), /* int_mult_si */
944 COSTS_N_INSNS (5), /* int_mult_di */
945 COSTS_N_INSNS (36), /* int_div_si */
946 COSTS_N_INSNS (36), /* int_div_di */
948 4 /* memory_latency */
951 COSTS_N_INSNS (6), /* fp_add */
952 COSTS_N_INSNS (5), /* fp_mult_sf */
953 COSTS_N_INSNS (6), /* fp_mult_df */
954 COSTS_N_INSNS (30), /* fp_div_sf */
955 COSTS_N_INSNS (59), /* fp_div_df */
956 COSTS_N_INSNS (3), /* int_mult_si */
957 COSTS_N_INSNS (4), /* int_mult_di */
958 COSTS_N_INSNS (42), /* int_div_si */
959 COSTS_N_INSNS (74), /* int_div_di */
961 4 /* memory_latency */
964 COSTS_N_INSNS (6), /* fp_add */
965 COSTS_N_INSNS (5), /* fp_mult_sf */
966 COSTS_N_INSNS (6), /* fp_mult_df */
967 COSTS_N_INSNS (30), /* fp_div_sf */
968 COSTS_N_INSNS (59), /* fp_div_df */
969 COSTS_N_INSNS (5), /* int_mult_si */
970 COSTS_N_INSNS (9), /* int_mult_di */
971 COSTS_N_INSNS (42), /* int_div_si */
972 COSTS_N_INSNS (74), /* int_div_di */
974 4 /* memory_latency */
977 COSTS_N_INSNS (4), /* fp_add */
978 COSTS_N_INSNS (4), /* fp_mult_sf */
979 COSTS_N_INSNS (256), /* fp_mult_df */
980 COSTS_N_INSNS (8), /* fp_div_sf */
981 COSTS_N_INSNS (256), /* fp_div_df */
982 COSTS_N_INSNS (4), /* int_mult_si */
983 COSTS_N_INSNS (256), /* int_mult_di */
984 COSTS_N_INSNS (37), /* int_div_si */
985 COSTS_N_INSNS (256), /* int_div_di */
987 4 /* memory_latency */
990 /* The only costs that are changed here are
991 integer multiplication. */
992 COSTS_N_INSNS (6), /* fp_add */
993 COSTS_N_INSNS (7), /* fp_mult_sf */
994 COSTS_N_INSNS (8), /* fp_mult_df */
995 COSTS_N_INSNS (23), /* fp_div_sf */
996 COSTS_N_INSNS (36), /* fp_div_df */
997 COSTS_N_INSNS (5), /* int_mult_si */
998 COSTS_N_INSNS (9), /* int_mult_di */
999 COSTS_N_INSNS (69), /* int_div_si */
1000 COSTS_N_INSNS (69), /* int_div_di */
1001 1, /* branch_cost */
1002 4 /* memory_latency */
1008 /* The only costs that are changed here are
1009 integer multiplication. */
1010 COSTS_N_INSNS (6), /* fp_add */
1011 COSTS_N_INSNS (7), /* fp_mult_sf */
1012 COSTS_N_INSNS (8), /* fp_mult_df */
1013 COSTS_N_INSNS (23), /* fp_div_sf */
1014 COSTS_N_INSNS (36), /* fp_div_df */
1015 COSTS_N_INSNS (3), /* int_mult_si */
1016 COSTS_N_INSNS (8), /* int_mult_di */
1017 COSTS_N_INSNS (69), /* int_div_si */
1018 COSTS_N_INSNS (69), /* int_div_di */
1019 1, /* branch_cost */
1020 4 /* memory_latency */
1023 COSTS_N_INSNS (2), /* fp_add */
1024 COSTS_N_INSNS (2), /* fp_mult_sf */
1025 COSTS_N_INSNS (2), /* fp_mult_df */
1026 COSTS_N_INSNS (12), /* fp_div_sf */
1027 COSTS_N_INSNS (19), /* fp_div_df */
1028 COSTS_N_INSNS (5), /* int_mult_si */
1029 COSTS_N_INSNS (9), /* int_mult_di */
1030 COSTS_N_INSNS (34), /* int_div_si */
1031 COSTS_N_INSNS (66), /* int_div_di */
1032 1, /* branch_cost */
1033 4 /* memory_latency */
1036 /* These costs are the same as the SB-1A below. */
1037 COSTS_N_INSNS (4), /* fp_add */
1038 COSTS_N_INSNS (4), /* fp_mult_sf */
1039 COSTS_N_INSNS (4), /* fp_mult_df */
1040 COSTS_N_INSNS (24), /* fp_div_sf */
1041 COSTS_N_INSNS (32), /* fp_div_df */
1042 COSTS_N_INSNS (3), /* int_mult_si */
1043 COSTS_N_INSNS (4), /* int_mult_di */
1044 COSTS_N_INSNS (36), /* int_div_si */
1045 COSTS_N_INSNS (68), /* int_div_di */
1046 1, /* branch_cost */
1047 4 /* memory_latency */
1050 /* These costs are the same as the SB-1 above. */
1051 COSTS_N_INSNS (4), /* fp_add */
1052 COSTS_N_INSNS (4), /* fp_mult_sf */
1053 COSTS_N_INSNS (4), /* fp_mult_df */
1054 COSTS_N_INSNS (24), /* fp_div_sf */
1055 COSTS_N_INSNS (32), /* fp_div_df */
1056 COSTS_N_INSNS (3), /* int_mult_si */
1057 COSTS_N_INSNS (4), /* int_mult_di */
1058 COSTS_N_INSNS (36), /* int_div_si */
1059 COSTS_N_INSNS (68), /* int_div_di */
1060 1, /* branch_cost */
1061 4 /* memory_latency */
1068 COSTS_N_INSNS (8), /* int_mult_si */
1069 COSTS_N_INSNS (8), /* int_mult_di */
1070 COSTS_N_INSNS (72), /* int_div_si */
1071 COSTS_N_INSNS (72), /* int_div_di */
1072 1, /* branch_cost */
1073 4 /* memory_latency */
1076 /* These costs are the same as 5KF above. */
1077 COSTS_N_INSNS (4), /* fp_add */
1078 COSTS_N_INSNS (4), /* fp_mult_sf */
1079 COSTS_N_INSNS (5), /* fp_mult_df */
1080 COSTS_N_INSNS (17), /* fp_div_sf */
1081 COSTS_N_INSNS (32), /* fp_div_df */
1082 COSTS_N_INSNS (4), /* int_mult_si */
1083 COSTS_N_INSNS (11), /* int_mult_di */
1084 COSTS_N_INSNS (36), /* int_div_si */
1085 COSTS_N_INSNS (68), /* int_div_di */
1086 1, /* branch_cost */
1087 4 /* memory_latency */
1090 COSTS_N_INSNS (4), /* fp_add */
1091 COSTS_N_INSNS (5), /* fp_mult_sf */
1092 COSTS_N_INSNS (5), /* fp_mult_df */
1093 COSTS_N_INSNS (17), /* fp_div_sf */
1094 COSTS_N_INSNS (17), /* fp_div_df */
1095 COSTS_N_INSNS (5), /* int_mult_si */
1096 COSTS_N_INSNS (5), /* int_mult_di */
1097 COSTS_N_INSNS (8), /* int_div_si */
1098 COSTS_N_INSNS (8), /* int_div_di */
1099 2, /* branch_cost */
1100 4 /* memory_latency */
1103 COSTS_N_INSNS (4), /* fp_add */
1104 COSTS_N_INSNS (4), /* fp_mult_sf */
1105 COSTS_N_INSNS (5), /* fp_mult_df */
1106 COSTS_N_INSNS (17), /* fp_div_sf */
1107 COSTS_N_INSNS (32), /* fp_div_df */
1108 COSTS_N_INSNS (5), /* int_mult_si */
1109 COSTS_N_INSNS (5), /* int_mult_di */
1110 COSTS_N_INSNS (34), /* int_div_si */
1111 COSTS_N_INSNS (68), /* int_div_di */
1112 1, /* branch_cost */
1113 4 /* memory_latency */
1116 COSTS_N_INSNS (4), /* fp_add */
1117 COSTS_N_INSNS (5), /* fp_mult_sf */
1118 COSTS_N_INSNS (5), /* fp_mult_df */
1119 COSTS_N_INSNS (32), /* fp_div_sf */
1120 COSTS_N_INSNS (32), /* fp_div_df */
1121 COSTS_N_INSNS (5), /* int_mult_si */
1122 COSTS_N_INSNS (5), /* int_mult_di */
1123 COSTS_N_INSNS (36), /* int_div_si */
1124 COSTS_N_INSNS (36), /* int_div_di */
1125 2, /* branch_cost */
1126 4 /* memory_latency */
1130 static rtx
mips_find_pic_call_symbol (rtx_insn
*, rtx
, bool);
1131 static int mips_register_move_cost (machine_mode
, reg_class_t
,
1133 static unsigned int mips_function_arg_boundary (machine_mode
, const_tree
);
1134 static machine_mode
mips_get_reg_raw_mode (int regno
);
1135 static rtx
mips_gen_const_int_vector_shuffle (machine_mode
, int);
1137 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1138 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1139 static GTY (()) hash_map
<nofree_string_hash
, bool> *mflip_mips16_htab
;
1141 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1142 mode, false if it should next add an attribute for the opposite mode. */
1143 static GTY(()) bool mips16_flipper
;
1145 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1146 for -mflip-mips16. Return true if it should use "mips16" and false if
1147 it should use "nomips16". */
1150 mflip_mips16_use_mips16_p (tree decl
)
1153 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1155 /* Use the opposite of the command-line setting for anonymous decls. */
1156 if (!DECL_NAME (decl
))
1157 return !base_is_mips16
;
1159 if (!mflip_mips16_htab
)
1160 mflip_mips16_htab
= hash_map
<nofree_string_hash
, bool>::create_ggc (37);
1162 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1165 bool *slot
= &mflip_mips16_htab
->get_or_insert (name
, &existed
);
1168 mips16_flipper
= !mips16_flipper
;
1169 *slot
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1174 /* Predicates to test for presence of "near" and "far"/"long_call"
1175 attributes on the given TYPE. */
1178 mips_near_type_p (const_tree type
)
1180 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1184 mips_far_type_p (const_tree type
)
1186 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1187 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1191 /* Check if the interrupt attribute is set for a function. */
1194 mips_interrupt_type_p (tree type
)
1196 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1199 /* Return the mask for the "interrupt" attribute. */
1201 static enum mips_int_mask
1202 mips_interrupt_mask (tree type
)
1204 tree attr
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
));
1208 /* For missing attributes or no arguments then return 'eic' as a safe
1211 return INT_MASK_EIC
;
1213 args
= TREE_VALUE (attr
);
1216 return INT_MASK_EIC
;
1218 cst
= TREE_VALUE (args
);
1220 if (strcmp (TREE_STRING_POINTER (cst
), "eic") == 0)
1221 return INT_MASK_EIC
;
1223 /* The validation code in mips_handle_interrupt_attr guarantees that the
1224 argument is now in the form:
1225 vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5). */
1226 str
= TREE_STRING_POINTER (cst
);
1228 gcc_assert (strlen (str
) == strlen ("vector=sw0"));
1231 return (enum mips_int_mask
) (INT_MASK_SW0
+ (str
[9] - '0'));
1233 return (enum mips_int_mask
) (INT_MASK_HW0
+ (str
[9] - '0'));
1236 /* Return the mips_shadow_set if the "use_shadow_register_set" attribute is
1237 set for a function. */
1239 static enum mips_shadow_set
1240 mips_use_shadow_register_set (tree type
)
1242 tree attr
= lookup_attribute ("use_shadow_register_set",
1243 TYPE_ATTRIBUTES (type
));
1246 /* The validation code in mips_handle_use_shadow_register_set_attr guarantees
1247 that if an argument is present then it means: Assume the shadow register
1248 set has a valid stack pointer in it. */
1250 return SHADOW_SET_NO
;
1252 args
= TREE_VALUE (attr
);
1255 return SHADOW_SET_YES
;
1257 return SHADOW_SET_INTSTACK
;
1260 /* Check if the attribute to keep interrupts masked is set for a function. */
1263 mips_keep_interrupts_masked_p (tree type
)
1265 return lookup_attribute ("keep_interrupts_masked",
1266 TYPE_ATTRIBUTES (type
)) != NULL
;
1269 /* Check if the attribute to use debug exception return is set for
1273 mips_use_debug_exception_return_p (tree type
)
1275 return lookup_attribute ("use_debug_exception_return",
1276 TYPE_ATTRIBUTES (type
)) != NULL
;
1279 /* Return the set of compression modes that are explicitly required
1280 by the attributes in ATTRIBUTES. */
1283 mips_get_compress_on_flags (tree attributes
)
1285 unsigned int flags
= 0;
1287 if (lookup_attribute ("mips16", attributes
) != NULL
)
1288 flags
|= MASK_MIPS16
;
1290 if (lookup_attribute ("micromips", attributes
) != NULL
)
1291 flags
|= MASK_MICROMIPS
;
1296 /* Return the set of compression modes that are explicitly forbidden
1297 by the attributes in ATTRIBUTES. */
1300 mips_get_compress_off_flags (tree attributes
)
1302 unsigned int flags
= 0;
1304 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1305 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1307 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1308 flags
|= MASK_MIPS16
;
1310 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1311 flags
|= MASK_MICROMIPS
;
1316 /* Return the compression mode that should be used for function DECL.
1317 Return the ambient setting if DECL is null. */
1320 mips_get_compress_mode (tree decl
)
1322 unsigned int flags
, force_on
;
1324 flags
= mips_base_compression_flags
;
1327 /* Nested functions must use the same frame pointer as their
1328 parent and must therefore use the same ISA mode. */
1329 tree parent
= decl_function_context (decl
);
1332 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1335 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1340 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1344 mips_get_compress_on_name (unsigned int flags
)
1346 if (flags
== MASK_MIPS16
)
1351 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1355 mips_get_compress_off_name (unsigned int flags
)
1357 if (flags
== MASK_MIPS16
)
1359 if (flags
== MASK_MICROMIPS
)
1360 return "nomicromips";
1361 return "nocompression";
1364 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1367 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1369 /* Disallow mixed near/far attributes. */
1370 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1372 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1377 /* Implement TARGET_INSERT_ATTRIBUTES. */
1380 mips_insert_attributes (tree decl
, tree
*attributes
)
1383 unsigned int compression_flags
, nocompression_flags
;
1385 /* Check for "mips16" and "nomips16" attributes. */
1386 compression_flags
= mips_get_compress_on_flags (*attributes
);
1387 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1389 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1391 if (nocompression_flags
)
1392 error ("%qs attribute only applies to functions",
1393 mips_get_compress_off_name (nocompression_flags
));
1395 if (compression_flags
)
1396 error ("%qs attribute only applies to functions",
1397 mips_get_compress_on_name (nocompression_flags
));
1401 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1402 nocompression_flags
|=
1403 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1405 if (compression_flags
&& nocompression_flags
)
1406 error ("%qE cannot have both %qs and %qs attributes",
1407 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1408 mips_get_compress_off_name (nocompression_flags
));
1410 if (compression_flags
& MASK_MIPS16
1411 && compression_flags
& MASK_MICROMIPS
)
1412 error ("%qE cannot have both %qs and %qs attributes",
1413 DECL_NAME (decl
), "mips16", "micromips");
1415 if (TARGET_FLIP_MIPS16
1416 && !DECL_ARTIFICIAL (decl
)
1417 && compression_flags
== 0
1418 && nocompression_flags
== 0)
1420 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1421 "mips16" attribute, arbitrarily pick one. We must pick the same
1422 setting for duplicate declarations of a function. */
1423 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1424 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1425 name
= "nomicromips";
1426 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1431 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1434 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1438 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1439 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1441 error ("%qE redeclared with conflicting %qs attributes",
1442 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1444 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1445 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1447 error ("%qE redeclared with conflicting %qs attributes",
1448 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1450 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1451 DECL_ATTRIBUTES (newdecl
));
1454 /* Implement TARGET_CAN_INLINE_P. */
1457 mips_can_inline_p (tree caller
, tree callee
)
1459 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1461 return default_target_can_inline_p (caller
, callee
);
1464 /* Handle an "interrupt" attribute with an optional argument. */
1467 mips_handle_interrupt_attr (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
1468 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1470 /* Check for an argument. */
1471 if (is_attribute_p ("interrupt", name
) && args
!= NULL
)
1475 cst
= TREE_VALUE (args
);
1476 if (TREE_CODE (cst
) != STRING_CST
)
1478 warning (OPT_Wattributes
,
1479 "%qE attribute requires a string argument",
1481 *no_add_attrs
= true;
1483 else if (strcmp (TREE_STRING_POINTER (cst
), "eic") != 0
1484 && strncmp (TREE_STRING_POINTER (cst
), "vector=", 7) != 0)
1486 warning (OPT_Wattributes
,
1487 "argument to %qE attribute is neither eic, nor "
1488 "vector=<line>", name
);
1489 *no_add_attrs
= true;
1491 else if (strncmp (TREE_STRING_POINTER (cst
), "vector=", 7) == 0)
1493 const char *arg
= TREE_STRING_POINTER (cst
) + 7;
1495 /* Acceptable names are: sw0,sw1,hw0,hw1,hw2,hw3,hw4,hw5. */
1496 if (strlen (arg
) != 3
1497 || (arg
[0] != 's' && arg
[0] != 'h')
1499 || (arg
[0] == 's' && arg
[2] != '0' && arg
[2] != '1')
1500 || (arg
[0] == 'h' && (arg
[2] < '0' || arg
[2] > '5')))
1502 warning (OPT_Wattributes
,
1503 "interrupt vector to %qE attribute is not "
1504 "vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5)",
1506 *no_add_attrs
= true;
1516 /* Handle a "use_shadow_register_set" attribute with an optional argument. */
1519 mips_handle_use_shadow_register_set_attr (tree
*node ATTRIBUTE_UNUSED
,
1520 tree name
, tree args
,
1521 int flags ATTRIBUTE_UNUSED
,
1524 /* Check for an argument. */
1525 if (is_attribute_p ("use_shadow_register_set", name
) && args
!= NULL
)
1529 cst
= TREE_VALUE (args
);
1530 if (TREE_CODE (cst
) != STRING_CST
)
1532 warning (OPT_Wattributes
,
1533 "%qE attribute requires a string argument",
1535 *no_add_attrs
= true;
1537 else if (strcmp (TREE_STRING_POINTER (cst
), "intstack") != 0)
1539 warning (OPT_Wattributes
,
1540 "argument to %qE attribute is not intstack", name
);
1541 *no_add_attrs
= true;
1550 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1551 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1554 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1556 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1558 *base_ptr
= XEXP (x
, 0);
1559 *offset_ptr
= INTVAL (XEXP (x
, 1));
1568 static unsigned int mips_build_integer (struct mips_integer_op
*,
1569 unsigned HOST_WIDE_INT
);
1571 /* A subroutine of mips_build_integer, with the same interface.
1572 Assume that the final action in the sequence should be a left shift. */
1575 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1577 unsigned int i
, shift
;
1579 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1580 since signed numbers are easier to load than unsigned ones. */
1582 while ((value
& 1) == 0)
1583 value
/= 2, shift
++;
1585 i
= mips_build_integer (codes
, value
);
1586 codes
[i
].code
= ASHIFT
;
1587 codes
[i
].value
= shift
;
1591 /* As for mips_build_shift, but assume that the final action will be
1592 an IOR or PLUS operation. */
1595 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1597 unsigned HOST_WIDE_INT high
;
1600 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1601 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1603 /* The constant is too complex to load with a simple LUI/ORI pair,
1604 so we want to give the recursive call as many trailing zeros as
1605 possible. In this case, we know bit 16 is set and that the
1606 low 16 bits form a negative number. If we subtract that number
1607 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1608 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1609 codes
[i
].code
= PLUS
;
1610 codes
[i
].value
= CONST_LOW_PART (value
);
1614 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1615 bits gives a value with at least 17 trailing zeros. */
1616 i
= mips_build_integer (codes
, high
);
1617 codes
[i
].code
= IOR
;
1618 codes
[i
].value
= value
& 0xffff;
1623 /* Fill CODES with a sequence of rtl operations to load VALUE.
1624 Return the number of operations needed. */
1627 mips_build_integer (struct mips_integer_op
*codes
,
1628 unsigned HOST_WIDE_INT value
)
1630 if (SMALL_OPERAND (value
)
1631 || SMALL_OPERAND_UNSIGNED (value
)
1632 || LUI_OPERAND (value
))
1634 /* The value can be loaded with a single instruction. */
1635 codes
[0].code
= UNKNOWN
;
1636 codes
[0].value
= value
;
1639 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1641 /* Either the constant is a simple LUI/ORI combination or its
1642 lowest bit is set. We don't want to shift in this case. */
1643 return mips_build_lower (codes
, value
);
1645 else if ((value
& 0xffff) == 0)
1647 /* The constant will need at least three actions. The lowest
1648 16 bits are clear, so the final action will be a shift. */
1649 return mips_build_shift (codes
, value
);
1653 /* The final action could be a shift, add or inclusive OR.
1654 Rather than use a complex condition to select the best
1655 approach, try both mips_build_shift and mips_build_lower
1656 and pick the one that gives the shortest sequence.
1657 Note that this case is only used once per constant. */
1658 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1659 unsigned int cost
, alt_cost
;
1661 cost
= mips_build_shift (codes
, value
);
1662 alt_cost
= mips_build_lower (alt_codes
, value
);
1663 if (alt_cost
< cost
)
1665 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1672 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1675 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1677 return mips_const_insns (x
) > 0;
1680 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1683 mips16_stub_function (const char *name
)
1687 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1688 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1692 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1693 support function. */
1696 mips16_stub_call_address (mips_one_only_stub
*stub
)
1698 rtx fn
= mips16_stub_function (stub
->get_name ());
1699 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1700 if (!call_insn_operand (fn
, VOIDmode
))
1701 fn
= force_reg (Pmode
, fn
);
1705 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1707 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1709 virtual const char *get_name ();
1710 virtual void output_body ();
1714 mips16_rdhwr_one_only_stub::get_name ()
1716 return "__mips16_rdhwr";
1720 mips16_rdhwr_one_only_stub::output_body ()
1722 fprintf (asm_out_file
,
1724 "\t.set\tmips32r2\n"
1725 "\t.set\tnoreorder\n"
1731 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1732 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1734 virtual const char *get_name ();
1735 virtual void output_body ();
1739 mips16_get_fcsr_one_only_stub::get_name ()
1741 return "__mips16_get_fcsr";
1745 mips16_get_fcsr_one_only_stub::output_body ()
1747 fprintf (asm_out_file
,
1749 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1752 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1753 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1755 virtual const char *get_name ();
1756 virtual void output_body ();
1760 mips16_set_fcsr_one_only_stub::get_name ()
1762 return "__mips16_set_fcsr";
1766 mips16_set_fcsr_one_only_stub::output_body ()
1768 fprintf (asm_out_file
,
1770 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1773 /* Return true if symbols of type TYPE require a GOT access. */
1776 mips_got_symbol_type_p (enum mips_symbol_type type
)
1780 case SYMBOL_GOT_PAGE_OFST
:
1781 case SYMBOL_GOT_DISP
:
1789 /* Return true if X is a thread-local symbol. */
1792 mips_tls_symbol_p (rtx x
)
1794 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1797 /* Return true if SYMBOL_REF X is associated with a global symbol
1798 (in the STB_GLOBAL sense). */
1801 mips_global_symbol_p (const_rtx x
)
1803 const_tree decl
= SYMBOL_REF_DECL (x
);
1806 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1808 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1809 or weak symbols. Relocations in the object file will be against
1810 the target symbol, so it's that symbol's binding that matters here. */
1811 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1814 /* Return true if function X is a libgcc MIPS16 stub function. */
1817 mips16_stub_function_p (const_rtx x
)
1819 return (GET_CODE (x
) == SYMBOL_REF
1820 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1823 /* Return true if function X is a locally-defined and locally-binding
1827 mips16_local_function_p (const_rtx x
)
1829 return (GET_CODE (x
) == SYMBOL_REF
1830 && SYMBOL_REF_LOCAL_P (x
)
1831 && !SYMBOL_REF_EXTERNAL_P (x
)
1832 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1835 /* Return true if SYMBOL_REF X binds locally. */
1838 mips_symbol_binds_local_p (const_rtx x
)
1840 return (SYMBOL_REF_DECL (x
)
1841 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1842 : SYMBOL_REF_LOCAL_P (x
));
1845 /* Return true if OP is a constant vector with the number of units in MODE,
1846 and each unit has the same bit set. */
1849 mips_const_vector_bitimm_set_p (rtx op
, machine_mode mode
)
1851 if (GET_CODE (op
) == CONST_VECTOR
&& op
!= CONST0_RTX (mode
))
1853 unsigned HOST_WIDE_INT val
= UINTVAL (CONST_VECTOR_ELT (op
, 0));
1854 int vlog2
= exact_log2 (val
& GET_MODE_MASK (GET_MODE_INNER (mode
)));
1858 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
1859 gcc_assert (vlog2
>= 0 && vlog2
<= GET_MODE_UNIT_BITSIZE (mode
) - 1);
1860 return mips_const_vector_same_val_p (op
, mode
);
1867 /* Return true if OP is a constant vector with the number of units in MODE,
1868 and each unit has the same bit clear. */
1871 mips_const_vector_bitimm_clr_p (rtx op
, machine_mode mode
)
1873 if (GET_CODE (op
) == CONST_VECTOR
&& op
!= CONSTM1_RTX (mode
))
1875 unsigned HOST_WIDE_INT val
= ~UINTVAL (CONST_VECTOR_ELT (op
, 0));
1876 int vlog2
= exact_log2 (val
& GET_MODE_MASK (GET_MODE_INNER (mode
)));
1880 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
1881 gcc_assert (vlog2
>= 0 && vlog2
<= GET_MODE_UNIT_BITSIZE (mode
) - 1);
1882 return mips_const_vector_same_val_p (op
, mode
);
1889 /* Return true if OP is a constant vector with the number of units in MODE,
1890 and each unit has the same value. */
1893 mips_const_vector_same_val_p (rtx op
, machine_mode mode
)
1895 int i
, nunits
= GET_MODE_NUNITS (mode
);
1898 if (GET_CODE (op
) != CONST_VECTOR
|| GET_MODE (op
) != mode
)
1901 first
= CONST_VECTOR_ELT (op
, 0);
1902 for (i
= 1; i
< nunits
; i
++)
1903 if (!rtx_equal_p (first
, CONST_VECTOR_ELT (op
, i
)))
1909 /* Return true if OP is a constant vector with the number of units in MODE,
1910 and each unit has the same value as well as replicated bytes in the value.
1914 mips_const_vector_same_bytes_p (rtx op
, machine_mode mode
)
1917 HOST_WIDE_INT val
, first_byte
;
1920 if (!mips_const_vector_same_val_p (op
, mode
))
1923 first
= CONST_VECTOR_ELT (op
, 0);
1924 bytes
= GET_MODE_UNIT_SIZE (mode
);
1925 val
= INTVAL (first
);
1926 first_byte
= val
& 0xff;
1927 for (i
= 1; i
< bytes
; i
++)
1930 if ((val
& 0xff) != first_byte
)
1937 /* Return true if OP is a constant vector with the number of units in MODE,
1938 and each unit has the same integer value in the range [LOW, HIGH]. */
1941 mips_const_vector_same_int_p (rtx op
, machine_mode mode
, HOST_WIDE_INT low
,
1944 HOST_WIDE_INT value
;
1947 if (!mips_const_vector_same_val_p (op
, mode
))
1950 elem0
= CONST_VECTOR_ELT (op
, 0);
1951 if (!CONST_INT_P (elem0
))
1954 value
= INTVAL (elem0
);
1955 return (value
>= low
&& value
<= high
);
1958 /* Return true if OP is a constant vector with repeated 4-element sets
1962 mips_const_vector_shuffle_set_p (rtx op
, machine_mode mode
)
1964 int nunits
= GET_MODE_NUNITS (mode
);
1965 int nsets
= nunits
/ 4;
1969 /* Check if we have the same 4-element sets. */
1970 for (j
= 0; j
< nsets
; j
++, set
= 4 * j
)
1971 for (i
= 0; i
< 4; i
++)
1972 if ((INTVAL (XVECEXP (op
, 0, i
))
1973 != (INTVAL (XVECEXP (op
, 0, set
+ i
)) - set
))
1974 || !IN_RANGE (INTVAL (XVECEXP (op
, 0, set
+ i
)), 0, set
+ 3))
1979 /* Return true if rtx constants of mode MODE should be put into a small
1983 mips_rtx_constant_in_small_data_p (machine_mode mode
)
1985 return (!TARGET_EMBEDDED_DATA
1986 && TARGET_LOCAL_SDATA
1987 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1990 /* Return true if X should not be moved directly into register $25.
1991 We need this because many versions of GAS will treat "la $25,foo" as
1992 part of a call sequence and so allow a global "foo" to be lazily bound. */
1995 mips_dangerous_for_la25_p (rtx x
)
1997 return (!TARGET_EXPLICIT_RELOCS
1999 && GET_CODE (x
) == SYMBOL_REF
2000 && mips_global_symbol_p (x
));
2003 /* Return true if calls to X might need $25 to be valid on entry. */
2006 mips_use_pic_fn_addr_reg_p (const_rtx x
)
2008 if (!TARGET_USE_PIC_FN_ADDR_REG
)
2011 /* MIPS16 stub functions are guaranteed not to use $25. */
2012 if (mips16_stub_function_p (x
))
2015 if (GET_CODE (x
) == SYMBOL_REF
)
2017 /* If PLTs and copy relocations are available, the static linker
2018 will make sure that $25 is valid on entry to the target function. */
2019 if (TARGET_ABICALLS_PIC0
)
2022 /* Locally-defined functions use absolute accesses to set up
2023 the global pointer. */
2024 if (TARGET_ABSOLUTE_ABICALLS
2025 && mips_symbol_binds_local_p (x
)
2026 && !SYMBOL_REF_EXTERNAL_P (x
))
2033 /* Return the method that should be used to access SYMBOL_REF or
2034 LABEL_REF X in context CONTEXT. */
2036 static enum mips_symbol_type
2037 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
2040 return SYMBOL_GOT_DISP
;
2042 if (GET_CODE (x
) == LABEL_REF
)
2044 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
2045 code and if we know that the label is in the current function's
2046 text section. LABEL_REFs are used for jump tables as well as
2047 text labels, so we must check whether jump tables live in the
2049 if (TARGET_MIPS16_SHORT_JUMP_TABLES
2050 && !LABEL_REF_NONLOCAL_P (x
))
2051 return SYMBOL_PC_RELATIVE
;
2053 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
2054 return SYMBOL_GOT_PAGE_OFST
;
2056 return SYMBOL_ABSOLUTE
;
2059 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
2061 if (SYMBOL_REF_TLS_MODEL (x
))
2064 if (CONSTANT_POOL_ADDRESS_P (x
))
2066 if (TARGET_MIPS16_TEXT_LOADS
)
2067 return SYMBOL_PC_RELATIVE
;
2069 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
2070 return SYMBOL_PC_RELATIVE
;
2072 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
2073 return SYMBOL_GP_RELATIVE
;
2076 /* Do not use small-data accesses for weak symbols; they may end up
2078 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
2079 return SYMBOL_GP_RELATIVE
;
2081 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
2083 if (TARGET_ABICALLS_PIC2
2084 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
2086 /* There are three cases to consider:
2088 - o32 PIC (either with or without explicit relocs)
2089 - n32/n64 PIC without explicit relocs
2090 - n32/n64 PIC with explicit relocs
2092 In the first case, both local and global accesses will use an
2093 R_MIPS_GOT16 relocation. We must correctly predict which of
2094 the two semantics (local or global) the assembler and linker
2095 will apply. The choice depends on the symbol's binding rather
2096 than its visibility.
2098 In the second case, the assembler will not use R_MIPS_GOT16
2099 relocations, but it chooses between local and global accesses
2100 in the same way as for o32 PIC.
2102 In the third case we have more freedom since both forms of
2103 access will work for any kind of symbol. However, there seems
2104 little point in doing things differently. */
2105 if (mips_global_symbol_p (x
))
2106 return SYMBOL_GOT_DISP
;
2108 return SYMBOL_GOT_PAGE_OFST
;
2111 return SYMBOL_ABSOLUTE
;
2114 /* Classify the base of symbolic expression X, given that X appears in
2117 static enum mips_symbol_type
2118 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
2122 split_const (x
, &x
, &offset
);
2123 if (UNSPEC_ADDRESS_P (x
))
2124 return UNSPEC_ADDRESS_TYPE (x
);
2126 return mips_classify_symbol (x
, context
);
2129 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
2130 is the alignment in bytes of SYMBOL_REF X. */
2133 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
2135 HOST_WIDE_INT align
;
2137 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
2138 return IN_RANGE (offset
, 0, align
- 1);
2141 /* Return true if X is a symbolic constant that can be used in context
2142 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
2145 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
2146 enum mips_symbol_type
*symbol_type
)
2150 split_const (x
, &x
, &offset
);
2151 if (UNSPEC_ADDRESS_P (x
))
2153 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
2154 x
= UNSPEC_ADDRESS (x
);
2156 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
2158 *symbol_type
= mips_classify_symbol (x
, context
);
2159 if (*symbol_type
== SYMBOL_TLS
)
2165 if (offset
== const0_rtx
)
2168 /* Check whether a nonzero offset is valid for the underlying
2170 switch (*symbol_type
)
2172 case SYMBOL_ABSOLUTE
:
2173 case SYMBOL_64_HIGH
:
2176 /* If the target has 64-bit pointers and the object file only
2177 supports 32-bit symbols, the values of those symbols will be
2178 sign-extended. In this case we can't allow an arbitrary offset
2179 in case the 32-bit value X + OFFSET has a different sign from X. */
2180 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2181 return offset_within_block_p (x
, INTVAL (offset
));
2183 /* In other cases the relocations can handle any offset. */
2186 case SYMBOL_PC_RELATIVE
:
2187 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2188 In this case, we no longer have access to the underlying constant,
2189 but the original symbol-based access was known to be valid. */
2190 if (GET_CODE (x
) == LABEL_REF
)
2195 case SYMBOL_GP_RELATIVE
:
2196 /* Make sure that the offset refers to something within the
2197 same object block. This should guarantee that the final
2198 PC- or GP-relative offset is within the 16-bit limit. */
2199 return offset_within_block_p (x
, INTVAL (offset
));
2201 case SYMBOL_GOT_PAGE_OFST
:
2202 case SYMBOL_GOTOFF_PAGE
:
2203 /* If the symbol is global, the GOT entry will contain the symbol's
2204 address, and we will apply a 16-bit offset after loading it.
2205 If the symbol is local, the linker should provide enough local
2206 GOT entries for a 16-bit offset, but larger offsets may lead
2208 return SMALL_INT (offset
);
2212 /* There is no carry between the HI and LO REL relocations, so the
2213 offset is only valid if we know it won't lead to such a carry. */
2214 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2216 case SYMBOL_GOT_DISP
:
2217 case SYMBOL_GOTOFF_DISP
:
2218 case SYMBOL_GOTOFF_CALL
:
2219 case SYMBOL_GOTOFF_LOADGP
:
2222 case SYMBOL_GOTTPREL
:
2230 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2231 single instruction. We rely on the fact that, in the worst case,
2232 all instructions involved in a MIPS16 address calculation are usually
2236 mips_symbol_insns_1 (enum mips_symbol_type type
, machine_mode mode
)
2238 if (mips_use_pcrel_pool_p
[(int) type
])
2240 if (mode
== MAX_MACHINE_MODE
)
2241 /* LEAs will be converted into constant-pool references by
2243 type
= SYMBOL_PC_RELATIVE
;
2245 /* The constant must be loaded and then dereferenced. */
2251 case SYMBOL_ABSOLUTE
:
2252 /* When using 64-bit symbols, we need 5 preparatory instructions,
2255 lui $at,%highest(symbol)
2256 daddiu $at,$at,%higher(symbol)
2258 daddiu $at,$at,%hi(symbol)
2261 The final address is then $at + %lo(symbol). With 32-bit
2262 symbols we just need a preparatory LUI for normal mode and
2263 a preparatory LI and SLL for MIPS16. */
2264 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2266 case SYMBOL_GP_RELATIVE
:
2267 /* Treat GP-relative accesses as taking a single instruction on
2268 MIPS16 too; the copy of $gp can often be shared. */
2271 case SYMBOL_PC_RELATIVE
:
2272 /* PC-relative constants can be only be used with ADDIUPC,
2273 DADDIUPC, LWPC and LDPC. */
2274 if (mode
== MAX_MACHINE_MODE
2275 || GET_MODE_SIZE (mode
) == 4
2276 || GET_MODE_SIZE (mode
) == 8)
2279 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2282 case SYMBOL_GOT_DISP
:
2283 /* The constant will have to be loaded from the GOT before it
2284 is used in an address. */
2285 if (mode
!= MAX_MACHINE_MODE
)
2290 case SYMBOL_GOT_PAGE_OFST
:
2291 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2292 local/global classification is accurate. The worst cases are:
2294 (1) For local symbols when generating o32 or o64 code. The assembler
2300 ...and the final address will be $at + %lo(symbol).
2302 (2) For global symbols when -mxgot. The assembler will use:
2304 lui $at,%got_hi(symbol)
2307 ...and the final address will be $at + %got_lo(symbol). */
2310 case SYMBOL_GOTOFF_PAGE
:
2311 case SYMBOL_GOTOFF_DISP
:
2312 case SYMBOL_GOTOFF_CALL
:
2313 case SYMBOL_GOTOFF_LOADGP
:
2314 case SYMBOL_64_HIGH
:
2320 case SYMBOL_GOTTPREL
:
2323 /* A 16-bit constant formed by a single relocation, or a 32-bit
2324 constant formed from a high 16-bit relocation and a low 16-bit
2325 relocation. Use mips_split_p to determine which. 32-bit
2326 constants need an "lui; addiu" sequence for normal mode and
2327 an "li; sll; addiu" sequence for MIPS16 mode. */
2328 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2331 /* We don't treat a bare TLS symbol as a constant. */
2337 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2338 to load symbols of type TYPE into a register. Return 0 if the given
2339 type of symbol cannot be used as an immediate operand.
2341 Otherwise, return the number of instructions needed to load or store
2342 values of mode MODE to or from addresses of type TYPE. Return 0 if
2343 the given type of symbol is not valid in addresses.
2345 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2348 mips_symbol_insns (enum mips_symbol_type type
, machine_mode mode
)
2350 /* MSA LD.* and ST.* cannot support loading symbols via an immediate
2352 if (MSA_SUPPORTED_MODE_P (mode
))
2355 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2358 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2361 mips_cannot_force_const_mem (machine_mode mode
, rtx x
)
2363 enum mips_symbol_type type
;
2366 /* There is no assembler syntax for expressing an address-sized
2368 if (GET_CODE (x
) == HIGH
)
2371 /* As an optimization, reject constants that mips_legitimize_move
2374 Suppose we have a multi-instruction sequence that loads constant C
2375 into register R. If R does not get allocated a hard register, and
2376 R is used in an operand that allows both registers and memory
2377 references, reload will consider forcing C into memory and using
2378 one of the instruction's memory alternatives. Returning false
2379 here will force it to use an input reload instead. */
2380 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2383 split_const (x
, &base
, &offset
);
2384 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2386 /* See whether we explicitly want these symbols in the pool. */
2387 if (mips_use_pcrel_pool_p
[(int) type
])
2390 /* The same optimization as for CONST_INT. */
2391 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2394 /* If MIPS16 constant pools live in the text section, they should
2395 not refer to anything that might need run-time relocation. */
2396 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2400 /* TLS symbols must be computed by mips_legitimize_move. */
2401 if (tls_referenced_p (x
))
2407 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2408 constants when we're using a per-function constant pool. */
2411 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED
,
2412 const_rtx x ATTRIBUTE_UNUSED
)
2414 return !TARGET_MIPS16_PCREL_LOADS
;
2417 /* Return true if register REGNO is a valid base register for mode MODE.
2418 STRICT_P is true if REG_OK_STRICT is in effect. */
2421 mips_regno_mode_ok_for_base_p (int regno
, machine_mode mode
,
2424 if (!HARD_REGISTER_NUM_P (regno
))
2428 regno
= reg_renumber
[regno
];
2431 /* These fake registers will be eliminated to either the stack or
2432 hard frame pointer, both of which are usually valid base registers.
2433 Reload deals with the cases where the eliminated form isn't valid. */
2434 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2437 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2438 values, nothing smaller. */
2439 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2440 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2442 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2445 /* Return true if X is a valid base register for mode MODE.
2446 STRICT_P is true if REG_OK_STRICT is in effect. */
2449 mips_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
2451 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2455 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2458 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2459 can address a value of mode MODE. */
2462 mips_valid_offset_p (rtx x
, machine_mode mode
)
2464 /* Check that X is a signed 16-bit number. */
2465 if (!const_arith_operand (x
, Pmode
))
2468 /* We may need to split multiword moves, so make sure that every word
2470 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2471 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2474 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2475 if (MSA_SUPPORTED_MODE_P (mode
)
2476 && !mips_signed_immediate_p (INTVAL (x
), 10,
2477 mips_ldst_scaled_shift (mode
)))
2483 /* Return true if a LO_SUM can address a value of mode MODE when the
2484 LO_SUM symbol has type SYMBOL_TYPE. */
2487 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, machine_mode mode
)
2489 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2491 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2494 /* Check that there is a known low-part relocation. */
2495 if (mips_lo_relocs
[symbol_type
] == NULL
)
2498 /* We may need to split multiword moves, so make sure that each word
2499 can be accessed without inducing a carry. This is mainly needed
2500 for o64, which has historically only guaranteed 64-bit alignment
2501 for 128-bit types. */
2502 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2503 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2506 /* MSA LD.* and ST.* cannot support loading symbols via %lo($base). */
2507 if (MSA_SUPPORTED_MODE_P (mode
))
2513 /* Return true if X is a valid address for machine mode MODE. If it is,
2514 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2518 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2519 machine_mode mode
, bool strict_p
)
2521 switch (GET_CODE (x
))
2525 info
->type
= ADDRESS_REG
;
2527 info
->offset
= const0_rtx
;
2528 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2531 info
->type
= ADDRESS_REG
;
2532 info
->reg
= XEXP (x
, 0);
2533 info
->offset
= XEXP (x
, 1);
2534 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2535 && mips_valid_offset_p (info
->offset
, mode
));
2538 info
->type
= ADDRESS_LO_SUM
;
2539 info
->reg
= XEXP (x
, 0);
2540 info
->offset
= XEXP (x
, 1);
2541 /* We have to trust the creator of the LO_SUM to do something vaguely
2542 sane. Target-independent code that creates a LO_SUM should also
2543 create and verify the matching HIGH. Target-independent code that
2544 adds an offset to a LO_SUM must prove that the offset will not
2545 induce a carry. Failure to do either of these things would be
2546 a bug, and we are not required to check for it here. The MIPS
2547 backend itself should only create LO_SUMs for valid symbolic
2548 constants, with the high part being either a HIGH or a copy
2551 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2552 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2553 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2556 /* Small-integer addresses don't occur very often, but they
2557 are legitimate if $0 is a valid base register. */
2558 info
->type
= ADDRESS_CONST_INT
;
2559 return !TARGET_MIPS16
&& SMALL_INT (x
);
2564 info
->type
= ADDRESS_SYMBOLIC
;
2565 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2567 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2568 && !mips_split_p
[info
->symbol_type
]);
2575 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2578 mips_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2580 struct mips_address_info addr
;
2582 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2585 /* Return true if X is a legitimate $sp-based address for mode MODE. */
2588 mips_stack_address_p (rtx x
, machine_mode mode
)
2590 struct mips_address_info addr
;
2592 return (mips_classify_address (&addr
, x
, mode
, false)
2593 && addr
.type
== ADDRESS_REG
2594 && addr
.reg
== stack_pointer_rtx
);
2597 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2598 address instruction. Note that such addresses are not considered
2599 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2600 is so restricted. */
2603 mips_lwxs_address_p (rtx addr
)
2606 && GET_CODE (addr
) == PLUS
2607 && REG_P (XEXP (addr
, 1)))
2609 rtx offset
= XEXP (addr
, 0);
2610 if (GET_CODE (offset
) == MULT
2611 && REG_P (XEXP (offset
, 0))
2612 && CONST_INT_P (XEXP (offset
, 1))
2613 && INTVAL (XEXP (offset
, 1)) == 4)
2619 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2620 indexed address instruction. Note that such addresses are
2621 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2622 sense, because their use is so restricted. */
2625 mips_lx_address_p (rtx addr
, machine_mode mode
)
2627 if (GET_CODE (addr
) != PLUS
2628 || !REG_P (XEXP (addr
, 0))
2629 || !REG_P (XEXP (addr
, 1)))
2631 if (ISA_HAS_LBX
&& mode
== QImode
)
2633 if (ISA_HAS_LHX
&& mode
== HImode
)
2635 if (ISA_HAS_LWX
&& mode
== SImode
)
2637 if (ISA_HAS_LDX
&& mode
== DImode
)
2639 if (MSA_SUPPORTED_MODE_P (mode
))
2644 /* Return true if a value at OFFSET bytes from base register BASE can be
2645 accessed using an unextended MIPS16 instruction. MODE is the mode of
2648 Usually the offset in an unextended instruction is a 5-bit field.
2649 The offset is unsigned and shifted left once for LH and SH, twice
2650 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2651 an 8-bit immediate field that's shifted left twice. */
2654 mips16_unextended_reference_p (machine_mode mode
, rtx base
,
2655 unsigned HOST_WIDE_INT offset
)
2657 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2659 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2660 return offset
< 256U * GET_MODE_SIZE (mode
);
2661 return offset
< 32U * GET_MODE_SIZE (mode
);
2666 /* Return the number of instructions needed to load or store a value
2667 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2668 length of one instruction. Return 0 if X isn't valid for MODE.
2669 Assume that multiword moves may need to be split into word moves
2670 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2674 mips_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
2676 struct mips_address_info addr
;
2678 bool msa_p
= (!might_split_p
&& MSA_SUPPORTED_MODE_P (mode
));
2680 /* BLKmode is used for single unaligned loads and stores and should
2681 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2682 meaningless, so we have to single it out as a special case one way
2684 if (mode
!= BLKmode
&& might_split_p
)
2685 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2689 if (mips_classify_address (&addr
, x
, mode
, false))
2695 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2696 if (mips_signed_immediate_p (INTVAL (addr
.offset
), 10,
2697 mips_ldst_scaled_shift (mode
)))
2703 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2704 UINTVAL (addr
.offset
)))
2708 case ADDRESS_LO_SUM
:
2709 return msa_p
? 0 : TARGET_MIPS16
? factor
* 2 : factor
;
2711 case ADDRESS_CONST_INT
:
2712 return msa_p
? 0 : factor
;
2714 case ADDRESS_SYMBOLIC
:
2715 return msa_p
? 0 : factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2720 /* Return true if X fits within an unsigned field of BITS bits that is
2721 shifted left SHIFT bits before being used. */
2724 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2726 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2729 /* Return true if X fits within a signed field of BITS bits that is
2730 shifted left SHIFT bits before being used. */
2733 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2735 x
+= 1 << (bits
+ shift
- 1);
2736 return mips_unsigned_immediate_p (x
, bits
, shift
);
2739 /* Return the scale shift that applied to MSA LD/ST address offset. */
2742 mips_ldst_scaled_shift (machine_mode mode
)
2744 int shift
= exact_log2 (GET_MODE_UNIT_SIZE (mode
));
2746 if (shift
< 0 || shift
> 8)
2752 /* Return true if X is legitimate for accessing values of mode MODE,
2753 if it is based on a MIPS16 register, and if the offset satisfies
2754 OFFSET_PREDICATE. */
2757 m16_based_address_p (rtx x
, machine_mode mode
,
2758 insn_operand_predicate_fn offset_predicate
)
2760 struct mips_address_info addr
;
2762 return (mips_classify_address (&addr
, x
, mode
, false)
2763 && addr
.type
== ADDRESS_REG
2764 && M16_REG_P (REGNO (addr
.reg
))
2765 && offset_predicate (addr
.offset
, mode
));
2768 /* Return true if X is a legitimate address that conforms to the requirements
2769 for a microMIPS LWSP or SWSP insn. */
2772 lwsp_swsp_address_p (rtx x
, machine_mode mode
)
2774 struct mips_address_info addr
;
2776 return (mips_classify_address (&addr
, x
, mode
, false)
2777 && addr
.type
== ADDRESS_REG
2778 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2779 && uw5_operand (addr
.offset
, mode
));
2782 /* Return true if X is a legitimate address with a 12-bit offset.
2783 MODE is the mode of the value being accessed. */
2786 umips_12bit_offset_address_p (rtx x
, machine_mode mode
)
2788 struct mips_address_info addr
;
2790 return (mips_classify_address (&addr
, x
, mode
, false)
2791 && addr
.type
== ADDRESS_REG
2792 && CONST_INT_P (addr
.offset
)
2793 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2796 /* Return true if X is a legitimate address with a 9-bit offset.
2797 MODE is the mode of the value being accessed. */
2800 mips_9bit_offset_address_p (rtx x
, machine_mode mode
)
2802 struct mips_address_info addr
;
2804 return (mips_classify_address (&addr
, x
, mode
, false)
2805 && addr
.type
== ADDRESS_REG
2806 && CONST_INT_P (addr
.offset
)
2807 && MIPS_9BIT_OFFSET_P (INTVAL (addr
.offset
)));
2810 /* Return the number of instructions needed to load constant X,
2811 assuming that BASE_INSN_LENGTH is the length of one instruction.
2812 Return 0 if X isn't a valid constant. */
2815 mips_const_insns (rtx x
)
2817 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2818 enum mips_symbol_type symbol_type
;
2821 switch (GET_CODE (x
))
2824 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2826 || !mips_split_p
[symbol_type
])
2829 /* This is simply an LUI for normal mode. It is an extended
2830 LI followed by an extended SLL for MIPS16. */
2831 return TARGET_MIPS16
? 4 : 1;
2835 /* Unsigned 8-bit constants can be loaded using an unextended
2836 LI instruction. Unsigned 16-bit constants can be loaded
2837 using an extended LI. Negative constants must be loaded
2838 using LI and then negated. */
2839 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2840 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2841 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2842 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2845 return mips_build_integer (codes
, INTVAL (x
));
2849 && mips_const_vector_same_int_p (x
, GET_MODE (x
), -512, 511))
2853 /* Allow zeros for normal mode, where we can use $0. */
2854 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2860 /* See if we can refer to X directly. */
2861 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2862 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2864 /* Otherwise try splitting the constant into a base and offset.
2865 If the offset is a 16-bit value, we can load the base address
2866 into a register and then use (D)ADDIU to add in the offset.
2867 If the offset is larger, we can load the base and offset
2868 into separate registers and add them together with (D)ADDU.
2869 However, the latter is only possible before reload; during
2870 and after reload, we must have the option of forcing the
2871 constant into the pool instead. */
2872 split_const (x
, &x
, &offset
);
2875 int n
= mips_const_insns (x
);
2878 if (SMALL_INT (offset
))
2880 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2881 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2888 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2896 /* X is a doubleword constant that can be handled by splitting it into
2897 two words and loading each word separately. Return the number of
2898 instructions required to do this, assuming that BASE_INSN_LENGTH
2899 is the length of one instruction. */
2902 mips_split_const_insns (rtx x
)
2904 unsigned int low
, high
;
2906 low
= mips_const_insns (mips_subword (x
, false));
2907 high
= mips_const_insns (mips_subword (x
, true));
2908 gcc_assert (low
> 0 && high
> 0);
2912 /* Return one word of 128-bit value OP, taking into account the fixed
2913 endianness of certain registers. BYTE selects from the byte address. */
2916 mips_subword_at_byte (rtx op
, unsigned int byte
)
2920 mode
= GET_MODE (op
);
2921 if (mode
== VOIDmode
)
2924 gcc_assert (!FP_REG_RTX_P (op
));
2927 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
2929 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
2932 /* Return the number of instructions needed to implement INSN,
2933 given that it loads from or stores to MEM. Assume that
2934 BASE_INSN_LENGTH is the length of one instruction. */
2937 mips_load_store_insns (rtx mem
, rtx_insn
*insn
)
2943 gcc_assert (MEM_P (mem
));
2944 mode
= GET_MODE (mem
);
2946 /* Try to prove that INSN does not need to be split. */
2947 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2950 set
= single_set (insn
);
2951 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2952 might_split_p
= false;
2955 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2958 /* Return the number of instructions needed for an integer division,
2959 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2962 mips_idiv_insns (machine_mode mode
)
2967 if (TARGET_CHECK_ZERO_DIV
)
2969 if (GENERATE_DIVIDE_TRAPS
&& !MSA_SUPPORTED_MODE_P (mode
))
2975 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2981 /* Emit a move from SRC to DEST. Assume that the move expanders can
2982 handle all moves if !can_create_pseudo_p (). The distinction is
2983 important because, unlike emit_move_insn, the move expanders know
2984 how to force Pmode objects into the constant pool even when the
2985 constant pool address is not itself legitimate. */
2988 mips_emit_move (rtx dest
, rtx src
)
2990 return (can_create_pseudo_p ()
2991 ? emit_move_insn (dest
, src
)
2992 : emit_move_insn_1 (dest
, src
));
2995 /* Emit a move from SRC to DEST, splitting compound moves into individual
2996 instructions. SPLIT_TYPE is the type of split to perform. */
2999 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
3001 if (mips_split_move_p (dest
, src
, split_type
))
3002 mips_split_move (dest
, src
, split_type
);
3004 mips_emit_move (dest
, src
);
3007 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
3010 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
3012 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
3015 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
3016 Return that new register. */
3019 mips_force_unary (machine_mode mode
, enum rtx_code code
, rtx op0
)
3023 reg
= gen_reg_rtx (mode
);
3024 mips_emit_unary (code
, reg
, op0
);
3028 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3031 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
3033 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (code
, GET_MODE (target
),
3037 /* Compute (CODE OP0 OP1) and store the result in a new register
3038 of mode MODE. Return that new register. */
3041 mips_force_binary (machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
3045 reg
= gen_reg_rtx (mode
);
3046 mips_emit_binary (code
, reg
, op0
, op1
);
3050 /* Copy VALUE to a register and return that register. If new pseudos
3051 are allowed, copy it into a new register, otherwise use DEST. */
3054 mips_force_temporary (rtx dest
, rtx value
)
3056 if (can_create_pseudo_p ())
3057 return force_reg (Pmode
, value
);
3060 mips_emit_move (dest
, value
);
3065 /* Emit a call sequence with call pattern PATTERN and return the call
3066 instruction itself (which is not necessarily the last instruction
3067 emitted). ORIG_ADDR is the original, unlegitimized address,
3068 ADDR is the legitimized form, and LAZY_P is true if the call
3069 address is lazily-bound. */
3072 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
3077 insn
= emit_call_insn (pattern
);
3079 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
3081 /* MIPS16 JALRs only take MIPS16 registers. If the target
3082 function requires $25 to be valid on entry, we must copy it
3083 there separately. The move instruction can be put in the
3084 call's delay slot. */
3085 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
3086 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
3087 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
3091 /* Lazy-binding stubs require $gp to be valid on entry. */
3092 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3096 /* See the comment above load_call<mode> for details. */
3097 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
3098 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
3099 emit_insn (gen_update_got_version ());
3103 && TARGET_EXPLICIT_RELOCS
3104 && TARGET_CALL_CLOBBERED_GP
)
3106 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
3107 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
3113 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
3114 then add CONST_INT OFFSET to the result. */
3117 mips_unspec_address_offset (rtx base
, rtx offset
,
3118 enum mips_symbol_type symbol_type
)
3120 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
3121 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
3122 if (offset
!= const0_rtx
)
3123 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
3124 return gen_rtx_CONST (Pmode
, base
);
3127 /* Return an UNSPEC address with underlying address ADDRESS and symbol
3128 type SYMBOL_TYPE. */
3131 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
3135 split_const (address
, &base
, &offset
);
3136 return mips_unspec_address_offset (base
, offset
, symbol_type
);
3139 /* If OP is an UNSPEC address, return the address to which it refers,
3140 otherwise return OP itself. */
3143 mips_strip_unspec_address (rtx op
)
3147 split_const (op
, &base
, &offset
);
3148 if (UNSPEC_ADDRESS_P (base
))
3149 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
3153 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
3154 high part to BASE and return the result. Just return BASE otherwise.
3155 TEMP is as for mips_force_temporary.
3157 The returned expression can be used as the first operand to a LO_SUM. */
3160 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
3161 enum mips_symbol_type symbol_type
)
3163 if (mips_split_p
[symbol_type
])
3165 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
3166 addr
= mips_force_temporary (temp
, addr
);
3167 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
3172 /* Return an instruction that copies $gp into register REG. We want
3173 GCC to treat the register's value as constant, so that its value
3174 can be rematerialized on demand. */
3177 gen_load_const_gp (rtx reg
)
3179 return PMODE_INSN (gen_load_const_gp
, (reg
));
3182 /* Return a pseudo register that contains the value of $gp throughout
3183 the current function. Such registers are needed by MIPS16 functions,
3184 for which $gp itself is not a valid base register or addition operand. */
3187 mips16_gp_pseudo_reg (void)
3189 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
3193 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
3195 push_topmost_sequence ();
3197 scan
= get_insns ();
3198 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
3199 scan
= NEXT_INSN (scan
);
3201 rtx set
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
3202 rtx_insn
*insn
= emit_insn_after (set
, scan
);
3203 INSN_LOCATION (insn
) = 0;
3205 pop_topmost_sequence ();
3208 return cfun
->machine
->mips16_gp_pseudo_rtx
;
3211 /* Return a base register that holds pic_offset_table_rtx.
3212 TEMP, if nonnull, is a scratch Pmode base register. */
3215 mips_pic_base_register (rtx temp
)
3218 return pic_offset_table_rtx
;
3220 if (currently_expanding_to_rtl
)
3221 return mips16_gp_pseudo_reg ();
3223 if (can_create_pseudo_p ())
3224 temp
= gen_reg_rtx (Pmode
);
3227 /* The first post-reload split exposes all references to $gp
3228 (both uses and definitions). All references must remain
3229 explicit after that point.
3231 It is safe to introduce uses of $gp at any time, so for
3232 simplicity, we do that before the split too. */
3233 mips_emit_move (temp
, pic_offset_table_rtx
);
3235 emit_insn (gen_load_const_gp (temp
));
3239 /* Return the RHS of a load_call<mode> insn. */
3242 mips_unspec_call (rtx reg
, rtx symbol
)
3246 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
3247 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
3250 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3251 reference. Return NULL_RTX otherwise. */
3254 mips_strip_unspec_call (rtx src
)
3256 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3257 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3261 /* Create and return a GOT reference of type TYPE for address ADDR.
3262 TEMP, if nonnull, is a scratch Pmode base register. */
3265 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3267 rtx base
, high
, lo_sum_symbol
;
3269 base
= mips_pic_base_register (temp
);
3271 /* If we used the temporary register to load $gp, we can't use
3272 it for the high part as well. */
3273 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3276 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3277 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3279 if (type
== SYMBOL_GOTOFF_CALL
)
3280 return mips_unspec_call (high
, lo_sum_symbol
);
3282 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3285 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3286 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3287 constant in that context and can be split into high and low parts.
3288 If so, and if LOW_OUT is nonnull, emit the high part and store the
3289 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3291 TEMP is as for mips_force_temporary and is used to load the high
3292 part into a register.
3294 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3295 a legitimize SET_SRC for an .md pattern, otherwise the low part
3296 is guaranteed to be a legitimate address for mode MODE. */
3299 mips_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
3301 enum mips_symbol_context context
;
3302 enum mips_symbol_type symbol_type
;
3305 context
= (mode
== MAX_MACHINE_MODE
3306 ? SYMBOL_CONTEXT_LEA
3307 : SYMBOL_CONTEXT_MEM
);
3308 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3310 addr
= XEXP (addr
, 0);
3311 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3312 && mips_symbol_insns (symbol_type
, mode
) > 0
3313 && mips_split_hi_p
[symbol_type
])
3316 switch (symbol_type
)
3318 case SYMBOL_GOT_PAGE_OFST
:
3319 /* The high part of a page/ofst pair is loaded from the GOT. */
3320 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3331 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3332 && mips_symbol_insns (symbol_type
, mode
) > 0
3333 && mips_split_p
[symbol_type
])
3336 switch (symbol_type
)
3338 case SYMBOL_GOT_DISP
:
3339 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3340 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3343 case SYMBOL_GP_RELATIVE
:
3344 high
= mips_pic_base_register (temp
);
3345 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3349 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3350 high
= mips_force_temporary (temp
, high
);
3351 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3360 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3361 mips_force_temporary; it is only needed when OFFSET is not a
3365 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3367 if (!SMALL_OPERAND (offset
))
3373 /* Load the full offset into a register so that we can use
3374 an unextended instruction for the address itself. */
3375 high
= GEN_INT (offset
);
3380 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3381 The addition inside the macro CONST_HIGH_PART may cause an
3382 overflow, so we need to force a sign-extension check. */
3383 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3384 offset
= CONST_LOW_PART (offset
);
3386 high
= mips_force_temporary (temp
, high
);
3387 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3389 return plus_constant (Pmode
, reg
, offset
);
3392 /* The __tls_get_attr symbol. */
3393 static GTY(()) rtx mips_tls_symbol
;
3395 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3396 the TLS symbol we are referencing and TYPE is the symbol type to use
3397 (either global dynamic or local dynamic). V0 is an RTX for the
3398 return value location. */
3401 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3406 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3408 if (!mips_tls_symbol
)
3409 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3411 loc
= mips_unspec_address (sym
, type
);
3415 emit_insn (gen_rtx_SET (a0
, gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
,
3417 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3418 const0_rtx
, NULL_RTX
, false);
3419 RTL_CONST_CALL_P (insn
) = 1;
3420 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3421 insn
= get_insns ();
3428 /* Return a pseudo register that contains the current thread pointer. */
3431 mips_expand_thread_pointer (rtx tp
)
3437 if (!mips16_rdhwr_stub
)
3438 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3439 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3440 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3443 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3450 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3453 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3454 its address. The return value will be both a valid address and a valid
3455 SET_SRC (either a REG or a LO_SUM). */
3458 mips_legitimize_tls_address (rtx loc
)
3460 rtx dest
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3461 enum tls_model model
;
3463 model
= SYMBOL_REF_TLS_MODEL (loc
);
3464 /* Only TARGET_ABICALLS code can have more than one module; other
3465 code must be static and should not use a GOT. All TLS models
3466 reduce to local exec in this situation. */
3467 if (!TARGET_ABICALLS
)
3468 model
= TLS_MODEL_LOCAL_EXEC
;
3472 case TLS_MODEL_GLOBAL_DYNAMIC
:
3474 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3475 rtx_insn
*insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3476 dest
= gen_reg_rtx (Pmode
);
3477 emit_libcall_block (insn
, dest
, v0
, loc
);
3481 case TLS_MODEL_LOCAL_DYNAMIC
:
3483 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3484 rtx_insn
*insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3485 tmp1
= gen_reg_rtx (Pmode
);
3487 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3488 share the LDM result with other LD model accesses. */
3489 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3491 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3493 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3494 if (mips_split_p
[SYMBOL_DTPREL
])
3496 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3497 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3500 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3501 0, 0, OPTAB_DIRECT
);
3505 case TLS_MODEL_INITIAL_EXEC
:
3506 tp
= mips_get_tp ();
3507 tmp1
= gen_reg_rtx (Pmode
);
3508 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3509 if (Pmode
== DImode
)
3510 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3512 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3513 dest
= gen_reg_rtx (Pmode
);
3514 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3517 case TLS_MODEL_LOCAL_EXEC
:
3518 tmp1
= mips_get_tp ();
3519 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3520 if (mips_split_p
[SYMBOL_TPREL
])
3522 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3523 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3526 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3527 0, 0, OPTAB_DIRECT
);
3536 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3540 mips16_expand_get_fcsr (rtx target
)
3542 if (!mips16_get_fcsr_stub
)
3543 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3544 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3545 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3546 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3549 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3552 mips16_expand_set_fcsr (rtx newval
)
3554 if (!mips16_set_fcsr_stub
)
3555 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3556 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3557 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3558 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3561 /* If X is not a valid address for mode MODE, force it into a register. */
3564 mips_force_address (rtx x
, machine_mode mode
)
3566 if (!mips_legitimate_address_p (mode
, x
, false))
3567 x
= force_reg (Pmode
, x
);
3571 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3572 be legitimized in a way that the generic machinery might not expect,
3573 return a new address, otherwise return NULL. MODE is the mode of
3574 the memory being accessed. */
3577 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3581 HOST_WIDE_INT offset
;
3583 if (mips_tls_symbol_p (x
))
3584 return mips_legitimize_tls_address (x
);
3586 /* See if the address can split into a high part and a LO_SUM. */
3587 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3588 return mips_force_address (addr
, mode
);
3590 /* Handle BASE + OFFSET using mips_add_offset. */
3591 mips_split_plus (x
, &base
, &offset
);
3594 if (!mips_valid_base_register_p (base
, mode
, false))
3595 base
= copy_to_mode_reg (Pmode
, base
);
3596 addr
= mips_add_offset (NULL
, base
, offset
);
3597 return mips_force_address (addr
, mode
);
3603 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3606 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3608 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3610 unsigned int i
, num_ops
;
3613 mode
= GET_MODE (dest
);
3614 num_ops
= mips_build_integer (codes
, value
);
3616 /* Apply each binary operation to X. Invariant: X is a legitimate
3617 source operand for a SET pattern. */
3618 x
= GEN_INT (codes
[0].value
);
3619 for (i
= 1; i
< num_ops
; i
++)
3621 if (!can_create_pseudo_p ())
3623 emit_insn (gen_rtx_SET (temp
, x
));
3627 x
= force_reg (mode
, x
);
3628 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3631 emit_insn (gen_rtx_SET (dest
, x
));
3634 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3635 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3639 mips_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
3643 /* Split moves of big integers into smaller pieces. */
3644 if (splittable_const_int_operand (src
, mode
))
3646 mips_move_integer (dest
, dest
, INTVAL (src
));
3650 /* Split moves of symbolic constants into high/low pairs. */
3651 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3653 emit_insn (gen_rtx_SET (dest
, src
));
3657 /* Generate the appropriate access sequences for TLS symbols. */
3658 if (mips_tls_symbol_p (src
))
3660 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3664 /* If we have (const (plus symbol offset)), and that expression cannot
3665 be forced into memory, load the symbol first and add in the offset.
3666 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3667 forced into memory, as it usually produces better code. */
3668 split_const (src
, &base
, &offset
);
3669 if (offset
!= const0_rtx
3670 && (targetm
.cannot_force_const_mem (mode
, src
)
3671 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3673 base
= mips_force_temporary (dest
, base
);
3674 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3678 src
= force_const_mem (mode
, src
);
3680 /* When using explicit relocs, constant pool references are sometimes
3681 not legitimate addresses. */
3682 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3683 mips_emit_move (dest
, src
);
3686 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3687 sequence that is valid. */
3690 mips_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
3692 /* Both src and dest are non-registers; one special case is supported where
3693 the source is (const_int 0) and the store can source the zero register.
3694 MIPS16 and MSA are never able to source the zero register directly in
3695 memory operations. */
3696 if (!register_operand (dest
, mode
)
3697 && !register_operand (src
, mode
)
3698 && (TARGET_MIPS16
|| !const_0_operand (src
, mode
)
3699 || MSA_SUPPORTED_MODE_P (mode
)))
3701 mips_emit_move (dest
, force_reg (mode
, src
));
3705 /* We need to deal with constants that would be legitimate
3706 immediate_operands but aren't legitimate move_operands. */
3707 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3709 mips_legitimize_const_move (mode
, dest
, src
);
3710 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3716 /* Return true if value X in context CONTEXT is a small-data address
3717 that can be rewritten as a LO_SUM. */
3720 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3722 enum mips_symbol_type symbol_type
;
3724 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3725 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3726 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3727 && symbol_type
== SYMBOL_GP_RELATIVE
);
3730 /* Return true if OP refers to small data symbols directly, not through
3731 a LO_SUM. CONTEXT is the context in which X appears. */
3734 mips_small_data_pattern_1 (rtx x
, enum mips_symbol_context context
)
3736 subrtx_var_iterator::array_type array
;
3737 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
3741 /* Ignore things like "g" constraints in asms. We make no particular
3742 guarantee about which symbolic constants are acceptable as asm operands
3743 versus which must be forced into a GPR. */
3744 if (GET_CODE (x
) == LO_SUM
|| GET_CODE (x
) == ASM_OPERANDS
)
3745 iter
.skip_subrtxes ();
3748 if (mips_small_data_pattern_1 (XEXP (x
, 0), SYMBOL_CONTEXT_MEM
))
3750 iter
.skip_subrtxes ();
3752 else if (mips_rewrite_small_data_p (x
, context
))
3758 /* Return true if OP refers to small data symbols directly, not through
3762 mips_small_data_pattern_p (rtx op
)
3764 return mips_small_data_pattern_1 (op
, SYMBOL_CONTEXT_LEA
);
3767 /* Rewrite *LOC so that it refers to small data using explicit
3768 relocations. CONTEXT is the context in which *LOC appears. */
3771 mips_rewrite_small_data_1 (rtx
*loc
, enum mips_symbol_context context
)
3773 subrtx_ptr_iterator::array_type array
;
3774 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3779 mips_rewrite_small_data_1 (&XEXP (*loc
, 0), SYMBOL_CONTEXT_MEM
);
3780 iter
.skip_subrtxes ();
3782 else if (mips_rewrite_small_data_p (*loc
, context
))
3784 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3785 iter
.skip_subrtxes ();
3787 else if (GET_CODE (*loc
) == LO_SUM
)
3788 iter
.skip_subrtxes ();
3792 /* Rewrite instruction pattern PATTERN so that it refers to small data
3793 using explicit relocations. */
3796 mips_rewrite_small_data (rtx pattern
)
3798 pattern
= copy_insn (pattern
);
3799 mips_rewrite_small_data_1 (&pattern
, SYMBOL_CONTEXT_LEA
);
3803 /* The cost of loading values from the constant pool. It should be
3804 larger than the cost of any constant we want to synthesize inline. */
3805 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3807 /* Return the cost of X when used as an operand to the MIPS16 instruction
3808 that implements CODE. Return -1 if there is no such instruction, or if
3809 X is not a valid immediate operand for it. */
3812 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3819 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3820 other shifts are extended. The shift patterns truncate the shift
3821 count to the right size, so there are no out-of-range values. */
3822 if (IN_RANGE (x
, 1, 8))
3824 return COSTS_N_INSNS (1);
3827 if (IN_RANGE (x
, -128, 127))
3829 if (SMALL_OPERAND (x
))
3830 return COSTS_N_INSNS (1);
3834 /* Like LE, but reject the always-true case. */
3839 /* We add 1 to the immediate and use SLT. */
3843 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3846 if (IN_RANGE (x
, 0, 255))
3848 if (SMALL_OPERAND_UNSIGNED (x
))
3849 return COSTS_N_INSNS (1);
3854 /* Equality comparisons with 0 are cheap. */
3864 /* Return true if there is a non-MIPS16 instruction that implements CODE
3865 and if that instruction accepts X as an immediate operand. */
3868 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3875 /* All shift counts are truncated to a valid constant. */
3880 /* Likewise rotates, if the target supports rotates at all. */
3886 /* These instructions take 16-bit unsigned immediates. */
3887 return SMALL_OPERAND_UNSIGNED (x
);
3892 /* These instructions take 16-bit signed immediates. */
3893 return SMALL_OPERAND (x
);
3899 /* The "immediate" forms of these instructions are really
3900 implemented as comparisons with register 0. */
3905 /* Likewise, meaning that the only valid immediate operand is 1. */
3909 /* We add 1 to the immediate and use SLT. */
3910 return SMALL_OPERAND (x
+ 1);
3913 /* Likewise SLTU, but reject the always-true case. */
3914 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3918 /* The bit position and size are immediate operands. */
3919 return ISA_HAS_EXT_INS
;
3922 /* By default assume that $0 can be used for 0. */
3927 /* Return the cost of binary operation X, given that the instruction
3928 sequence for a word-sized or smaller operation has cost SINGLE_COST
3929 and that the sequence of a double-word operation has cost DOUBLE_COST.
3930 If SPEED is true, optimize for speed otherwise optimize for size. */
3933 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3937 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3942 + set_src_cost (XEXP (x
, 0), GET_MODE (x
), speed
)
3943 + rtx_cost (XEXP (x
, 1), GET_MODE (x
), GET_CODE (x
), 1, speed
));
3946 /* Return the cost of floating-point multiplications of mode MODE. */
3949 mips_fp_mult_cost (machine_mode mode
)
3951 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3954 /* Return the cost of floating-point divisions of mode MODE. */
3957 mips_fp_div_cost (machine_mode mode
)
3959 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3962 /* Return the cost of sign-extending OP to mode MODE, not including the
3963 cost of OP itself. */
3966 mips_sign_extend_cost (machine_mode mode
, rtx op
)
3969 /* Extended loads are as cheap as unextended ones. */
3972 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3973 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3976 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3977 /* We can use SEB or SEH. */
3978 return COSTS_N_INSNS (1);
3980 /* We need to use a shift left and a shift right. */
3981 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3984 /* Return the cost of zero-extending OP to mode MODE, not including the
3985 cost of OP itself. */
3988 mips_zero_extend_cost (machine_mode mode
, rtx op
)
3991 /* Extended loads are as cheap as unextended ones. */
3994 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3995 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3996 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3998 if (GENERATE_MIPS16E
)
3999 /* We can use ZEB or ZEH. */
4000 return COSTS_N_INSNS (1);
4003 /* We need to load 0xff or 0xffff into a register and use AND. */
4004 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
4006 /* We can use ANDI. */
4007 return COSTS_N_INSNS (1);
4010 /* Return the cost of moving between two registers of mode MODE,
4011 assuming that the move will be in pieces of at most UNITS bytes. */
4014 mips_set_reg_reg_piece_cost (machine_mode mode
, unsigned int units
)
4016 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
4019 /* Return the cost of moving between two registers of mode MODE. */
4022 mips_set_reg_reg_cost (machine_mode mode
)
4024 switch (GET_MODE_CLASS (mode
))
4027 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
4030 case MODE_COMPLEX_FLOAT
:
4031 case MODE_VECTOR_FLOAT
:
4032 if (TARGET_HARD_FLOAT
)
4033 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
4037 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
4041 /* Implement TARGET_RTX_COSTS. */
4044 mips_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
4045 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
4047 int code
= GET_CODE (x
);
4048 bool float_mode_p
= FLOAT_MODE_P (mode
);
4052 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
4053 appear in the instruction stream, and the cost of a comparison is
4054 really the cost of the branch or scc condition. At the time of
4055 writing, GCC only uses an explicit outer COMPARE code when optabs
4056 is testing whether a constant is expensive enough to force into a
4057 register. We want optabs to pass such constants through the MIPS
4058 expanders instead, so make all constants very cheap here. */
4059 if (outer_code
== COMPARE
)
4061 gcc_assert (CONSTANT_P (x
));
4069 /* Treat *clear_upper32-style ANDs as having zero cost in the
4070 second operand. The cost is entirely in the first operand.
4072 ??? This is needed because we would otherwise try to CSE
4073 the constant operand. Although that's the right thing for
4074 instructions that continue to be a register operation throughout
4075 compilation, it is disastrous for instructions that could
4076 later be converted into a memory operation. */
4078 && outer_code
== AND
4079 && UINTVAL (x
) == 0xffffffff)
4087 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
4096 /* When not optimizing for size, we care more about the cost
4097 of hot code, and hot code is often in a loop. If a constant
4098 operand needs to be forced into a register, we will often be
4099 able to hoist the constant load out of the loop, so the load
4100 should not contribute to the cost. */
4101 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
4113 if (force_to_mem_operand (x
, VOIDmode
))
4115 *total
= COSTS_N_INSNS (1);
4118 cost
= mips_const_insns (x
);
4121 /* If the constant is likely to be stored in a GPR, SETs of
4122 single-insn constants are as cheap as register sets; we
4123 never want to CSE them.
4125 Don't reduce the cost of storing a floating-point zero in
4126 FPRs. If we have a zero in an FPR for other reasons, we
4127 can get better cfg-cleanup and delayed-branch results by
4128 using it consistently, rather than using $0 sometimes and
4129 an FPR at other times. Also, moves between floating-point
4130 registers are sometimes cheaper than (D)MTC1 $0. */
4132 && outer_code
== SET
4133 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
4135 /* When non-MIPS16 code loads a constant N>1 times, we rarely
4136 want to CSE the constant itself. It is usually better to
4137 have N copies of the last operation in the sequence and one
4138 shared copy of the other operations. (Note that this is
4139 not true for MIPS16 code, where the final operation in the
4140 sequence is often an extended instruction.)
4142 Also, if we have a CONST_INT, we don't know whether it is
4143 for a word or doubleword operation, so we cannot rely on
4144 the result of mips_build_integer. */
4145 else if (!TARGET_MIPS16
4146 && (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
))
4148 *total
= COSTS_N_INSNS (cost
);
4151 /* The value will need to be fetched from the constant pool. */
4152 *total
= CONSTANT_POOL_COST
;
4156 /* If the address is legitimate, return the number of
4157 instructions it needs. */
4159 cost
= mips_address_insns (addr
, mode
, true);
4162 *total
= COSTS_N_INSNS (cost
+ 1);
4165 /* Check for a scaled indexed address. */
4166 if (mips_lwxs_address_p (addr
)
4167 || mips_lx_address_p (addr
, mode
))
4169 *total
= COSTS_N_INSNS (2);
4172 /* Otherwise use the default handling. */
4176 *total
= COSTS_N_INSNS (6);
4180 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
4184 /* Check for a *clear_upper32 pattern and treat it like a zero
4185 extension. See the pattern's comment for details. */
4188 && CONST_INT_P (XEXP (x
, 1))
4189 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
4191 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
4192 + set_src_cost (XEXP (x
, 0), mode
, speed
));
4195 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
4197 rtx op
= XEXP (x
, 0);
4198 if (GET_CODE (op
) == ASHIFT
4199 && CONST_INT_P (XEXP (op
, 1))
4200 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
4202 *total
= COSTS_N_INSNS (1);
4203 *total
+= set_src_cost (XEXP (op
, 0), mode
, speed
);
4207 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
4208 a single instruction. */
4210 && GET_CODE (XEXP (x
, 0)) == NOT
4211 && GET_CODE (XEXP (x
, 1)) == NOT
)
4213 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
4214 *total
= (COSTS_N_INSNS (cost
)
4215 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
4216 + set_src_cost (XEXP (XEXP (x
, 1), 0), mode
, speed
));
4224 /* Double-word operations use two single-word operations. */
4225 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4234 if (CONSTANT_P (XEXP (x
, 1)))
4235 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4238 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4244 *total
= mips_cost
->fp_add
;
4246 *total
= COSTS_N_INSNS (4);
4250 /* Low-part immediates need an extended MIPS16 instruction. */
4251 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
4252 + set_src_cost (XEXP (x
, 0), mode
, speed
));
4271 /* Branch comparisons have VOIDmode, so use the first operand's
4273 mode
= GET_MODE (XEXP (x
, 0));
4274 if (FLOAT_MODE_P (mode
))
4276 *total
= mips_cost
->fp_add
;
4279 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4284 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
&& !HONOR_SIGNED_ZEROS (mode
))
4286 /* See if we can use NMADD or NMSUB via the *nmadd4<mode>_fastmath
4287 or *nmsub4<mode>_fastmath patterns. These patterns check for
4288 HONOR_SIGNED_ZEROS so we check here too. */
4289 rtx op0
= XEXP (x
, 0);
4290 rtx op1
= XEXP (x
, 1);
4291 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4293 *total
= (mips_fp_mult_cost (mode
)
4294 + set_src_cost (XEXP (XEXP (op0
, 0), 0), mode
, speed
)
4295 + set_src_cost (XEXP (op0
, 1), mode
, speed
)
4296 + set_src_cost (op1
, mode
, speed
));
4299 if (GET_CODE (op1
) == MULT
)
4301 *total
= (mips_fp_mult_cost (mode
)
4302 + set_src_cost (op0
, mode
, speed
)
4303 + set_src_cost (XEXP (op1
, 0), mode
, speed
)
4304 + set_src_cost (XEXP (op1
, 1), mode
, speed
));
4313 /* If this is part of a MADD or MSUB, treat the PLUS as
4315 if (ISA_HAS_UNFUSED_MADD4
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4318 *total
= mips_cost
->fp_add
;
4322 /* If it's an add + mult (which is equivalent to shift left) and
4323 it's immediate operand satisfies const_immlsa_operand predicate. */
4324 if (((ISA_HAS_LSA
&& mode
== SImode
)
4325 || (ISA_HAS_DLSA
&& mode
== DImode
))
4326 && GET_CODE (XEXP (x
, 0)) == MULT
)
4328 rtx op2
= XEXP (XEXP (x
, 0), 1);
4329 if (const_immlsa_operand (op2
, mode
))
4331 *total
= (COSTS_N_INSNS (1)
4332 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
4333 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4338 /* Double-word operations require three single-word operations and
4339 an SLTU. The MIPS16 version then needs to move the result of
4340 the SLTU from $24 to a MIPS16 register. */
4341 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4342 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4347 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
)
4349 /* See if we can use NMADD or NMSUB via the *nmadd4<mode> or
4350 *nmsub4<mode> patterns. */
4351 rtx op
= XEXP (x
, 0);
4352 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4353 && GET_CODE (XEXP (op
, 0)) == MULT
)
4355 *total
= (mips_fp_mult_cost (mode
)
4356 + set_src_cost (XEXP (XEXP (op
, 0), 0), mode
, speed
)
4357 + set_src_cost (XEXP (XEXP (op
, 0), 1), mode
, speed
)
4358 + set_src_cost (XEXP (op
, 1), mode
, speed
));
4364 *total
= mips_cost
->fp_add
;
4366 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4370 *total
= mips_fp_mult_cost (mode
);
4375 *total
= mips_fp_mult_cost (mode
);
4376 else if (mode
== DImode
&& !TARGET_64BIT
)
4377 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4378 where the mulsidi3 always includes an MFHI and an MFLO. */
4380 ? mips_cost
->int_mult_si
* 3 + 6
4381 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4383 *total
= COSTS_N_INSNS ((ISA_HAS_MUL3
|| ISA_HAS_R6MUL
) ? 1 : 2) + 1;
4384 else if (mode
== DImode
)
4385 *total
= mips_cost
->int_mult_di
;
4387 *total
= mips_cost
->int_mult_si
;
4391 /* Check for a reciprocal. */
4393 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4394 && flag_unsafe_math_optimizations
4395 && XEXP (x
, 0) == CONST1_RTX (mode
))
4397 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4398 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4399 division as being free. */
4400 *total
= set_src_cost (XEXP (x
, 1), mode
, speed
);
4402 *total
= (mips_fp_div_cost (mode
)
4403 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4412 *total
= mips_fp_div_cost (mode
);
4421 /* It is our responsibility to make division by a power of 2
4422 as cheap as 2 register additions if we want the division
4423 expanders to be used for such operations; see the setting
4424 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4425 should always produce shorter code than using
4426 expand_sdiv2_pow2. */
4428 && CONST_INT_P (XEXP (x
, 1))
4429 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4431 *total
= COSTS_N_INSNS (2);
4432 *total
+= set_src_cost (XEXP (x
, 0), mode
, speed
);
4435 *total
= COSTS_N_INSNS (mips_idiv_insns (mode
));
4437 else if (mode
== DImode
)
4438 *total
= mips_cost
->int_div_di
;
4440 *total
= mips_cost
->int_div_si
;
4444 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4448 if (outer_code
== SET
4450 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4451 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4452 && GET_MODE (XEXP (x
, 0)) == QImode
4453 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4455 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, speed
);
4458 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4461 /* Costings for highpart multiplies. Matching patterns of the form:
4463 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4464 (sign_extend:DI (...))
4468 && (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4469 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
4470 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4471 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) == 32
4472 && GET_MODE (XEXP (x
, 0)) == DImode
)
4474 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 64
4475 && GET_MODE (XEXP (x
, 0)) == TImode
))
4476 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4477 && ((GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
4478 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SIGN_EXTEND
)
4479 || (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4480 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4484 *total
= COSTS_N_INSNS (1) + 1;
4485 else if (mode
== DImode
)
4486 *total
= mips_cost
->int_mult_di
;
4488 *total
= mips_cost
->int_mult_si
;
4490 /* Sign extension is free, zero extension costs for DImode when
4491 on a 64bit core / when DMUL is present. */
4492 for (int i
= 0; i
< 2; ++i
)
4494 rtx op
= XEXP (XEXP (XEXP (x
, 0), 0), i
);
4496 && GET_CODE (op
) == ZERO_EXTEND
4497 && GET_MODE (op
) == DImode
)
4498 *total
+= rtx_cost (op
, DImode
, MULT
, i
, speed
);
4500 *total
+= rtx_cost (XEXP (op
, 0), VOIDmode
, GET_CODE (op
),
4509 case UNSIGNED_FLOAT
:
4512 case FLOAT_TRUNCATE
:
4513 *total
= mips_cost
->fp_add
;
4517 if (register_operand (SET_DEST (x
), VOIDmode
)
4518 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4520 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4530 /* Implement TARGET_ADDRESS_COST. */
4533 mips_address_cost (rtx addr
, machine_mode mode
,
4534 addr_space_t as ATTRIBUTE_UNUSED
,
4535 bool speed ATTRIBUTE_UNUSED
)
4537 return mips_address_insns (addr
, mode
, false);
4540 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
4543 mips_no_speculation_in_delay_slots_p ()
4545 return TARGET_CB_MAYBE
;
4548 /* Information about a single instruction in a multi-instruction
4550 struct mips_multi_member
{
4551 /* True if this is a label, false if it is code. */
4554 /* The output_asm_insn format of the instruction. */
4557 /* The operands to the instruction. */
4558 rtx operands
[MAX_RECOG_OPERANDS
];
4560 typedef struct mips_multi_member mips_multi_member
;
4562 /* The instructions that make up the current multi-insn sequence. */
4563 static vec
<mips_multi_member
> mips_multi_members
;
4565 /* How many instructions (as opposed to labels) are in the current
4566 multi-insn sequence. */
4567 static unsigned int mips_multi_num_insns
;
4569 /* Start a new multi-insn sequence. */
4572 mips_multi_start (void)
4574 mips_multi_members
.truncate (0);
4575 mips_multi_num_insns
= 0;
4578 /* Add a new, zero initialized member to the current multi-insn sequence. */
4580 static struct mips_multi_member
*
4581 mips_multi_add (void)
4583 mips_multi_member empty
;
4584 memset (&empty
, 0, sizeof (empty
));
4585 return mips_multi_members
.safe_push (empty
);
4588 /* Add a normal insn with the given asm format to the current multi-insn
4589 sequence. The other arguments are a null-terminated list of operands. */
4592 mips_multi_add_insn (const char *format
, ...)
4594 struct mips_multi_member
*member
;
4599 member
= mips_multi_add ();
4600 member
->is_label_p
= false;
4601 member
->format
= format
;
4602 va_start (ap
, format
);
4604 while ((op
= va_arg (ap
, rtx
)))
4605 member
->operands
[i
++] = op
;
4607 mips_multi_num_insns
++;
4610 /* Add the given label definition to the current multi-insn sequence.
4611 The definition should include the colon. */
4614 mips_multi_add_label (const char *label
)
4616 struct mips_multi_member
*member
;
4618 member
= mips_multi_add ();
4619 member
->is_label_p
= true;
4620 member
->format
= label
;
4623 /* Return the index of the last member of the current multi-insn sequence. */
4626 mips_multi_last_index (void)
4628 return mips_multi_members
.length () - 1;
4631 /* Add a copy of an existing instruction to the current multi-insn
4632 sequence. I is the index of the instruction that should be copied. */
4635 mips_multi_copy_insn (unsigned int i
)
4637 struct mips_multi_member
*member
;
4639 member
= mips_multi_add ();
4640 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4641 gcc_assert (!member
->is_label_p
);
4644 /* Change the operand of an existing instruction in the current
4645 multi-insn sequence. I is the index of the instruction,
4646 OP is the index of the operand, and X is the new value. */
4649 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4651 mips_multi_members
[i
].operands
[op
] = x
;
4654 /* Write out the asm code for the current multi-insn sequence. */
4657 mips_multi_write (void)
4659 struct mips_multi_member
*member
;
4662 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4663 if (member
->is_label_p
)
4664 fprintf (asm_out_file
, "%s\n", member
->format
);
4666 output_asm_insn (member
->format
, member
->operands
);
4669 /* Return one word of double-word value OP, taking into account the fixed
4670 endianness of certain registers. HIGH_P is true to select the high part,
4671 false to select the low part. */
4674 mips_subword (rtx op
, bool high_p
)
4676 unsigned int byte
, offset
;
4679 mode
= GET_MODE (op
);
4680 if (mode
== VOIDmode
)
4681 mode
= TARGET_64BIT
? TImode
: DImode
;
4683 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4684 byte
= UNITS_PER_WORD
;
4688 if (FP_REG_RTX_P (op
))
4690 /* Paired FPRs are always ordered little-endian. */
4691 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4692 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4696 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4698 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4701 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4702 SPLIT_TYPE is the condition under which moves should be split. */
4705 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4707 return ((split_type
!= SPLIT_FOR_SPEED
4708 || mips_tuning_info
.fast_mult_zero_zero_p
)
4709 && src
== const0_rtx
4711 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4712 && (ISA_HAS_DSP_MULT
4713 ? ACC_REG_P (REGNO (dest
))
4714 : MD_REG_P (REGNO (dest
))));
4717 /* Return true if a move from SRC to DEST should be split into two.
4718 SPLIT_TYPE describes the split condition. */
4721 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4723 /* Check whether the move can be done using some variant of MULT $0,$0. */
4724 if (mips_mult_move_p (dest
, src
, split_type
))
4727 /* FPR-to-FPR moves can be done in a single instruction, if they're
4729 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4730 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4733 /* Check for floating-point loads and stores. */
4734 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4736 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4738 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4742 /* Check if MSA moves need splitting. */
4743 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest
)))
4744 return mips_split_128bit_move_p (dest
, src
);
4746 /* Otherwise split all multiword moves. */
4747 return size
> UNITS_PER_WORD
;
4750 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4751 SPLIT_TYPE describes the split condition. */
4754 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4758 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4759 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest
)))
4760 mips_split_128bit_move (dest
, src
);
4761 else if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4763 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4764 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4765 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4766 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4767 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4768 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4769 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4770 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4771 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4772 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4773 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4774 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4775 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4776 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4780 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4782 low_dest
= mips_subword (dest
, false);
4783 mips_emit_move (low_dest
, mips_subword (src
, false));
4785 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4787 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4789 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4791 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4793 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4795 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4799 /* The operation can be split into two normal moves. Decide in
4800 which order to do them. */
4801 low_dest
= mips_subword (dest
, false);
4802 if (REG_P (low_dest
)
4803 && reg_overlap_mentioned_p (low_dest
, src
))
4805 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4806 mips_emit_move (low_dest
, mips_subword (src
, false));
4810 mips_emit_move (low_dest
, mips_subword (src
, false));
4811 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4816 /* Return the split type for instruction INSN. */
4818 static enum mips_split_type
4819 mips_insn_split_type (rtx insn
)
4821 basic_block bb
= BLOCK_FOR_INSN (insn
);
4824 if (optimize_bb_for_speed_p (bb
))
4825 return SPLIT_FOR_SPEED
;
4827 return SPLIT_FOR_SIZE
;
4829 /* Once CFG information has been removed, we should trust the optimization
4830 decisions made by previous passes and only split where necessary. */
4831 return SPLIT_IF_NECESSARY
;
4834 /* Return true if a 128-bit move from SRC to DEST should be split. */
4837 mips_split_128bit_move_p (rtx dest
, rtx src
)
4839 /* MSA-to-MSA moves can be done in a single instruction. */
4840 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4843 /* Check for MSA loads and stores. */
4844 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4846 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4849 /* Check for MSA set to an immediate const vector with valid replicated
4851 if (FP_REG_RTX_P (dest
)
4852 && mips_const_vector_same_int_p (src
, GET_MODE (src
), -512, 511))
4855 /* Check for MSA load zero immediate. */
4856 if (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))
4862 /* Split a 128-bit move from SRC to DEST. */
4865 mips_split_128bit_move (rtx dest
, rtx src
)
4868 rtx low_dest
, low_src
, d
, s
;
4870 if (FP_REG_RTX_P (dest
))
4872 gcc_assert (!MEM_P (src
));
4874 rtx new_dest
= dest
;
4877 if (GET_MODE (dest
) != V4SImode
)
4878 new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
4882 if (GET_MODE (dest
) != V2DImode
)
4883 new_dest
= simplify_gen_subreg (V2DImode
, dest
, GET_MODE (dest
), 0);
4886 for (byte
= 0, index
= 0; byte
< GET_MODE_SIZE (TImode
);
4887 byte
+= UNITS_PER_WORD
, index
++)
4889 s
= mips_subword_at_byte (src
, byte
);
4891 emit_insn (gen_msa_insert_w (new_dest
, s
, new_dest
,
4892 GEN_INT (1 << index
)));
4894 emit_insn (gen_msa_insert_d (new_dest
, s
, new_dest
,
4895 GEN_INT (1 << index
)));
4898 else if (FP_REG_RTX_P (src
))
4900 gcc_assert (!MEM_P (dest
));
4905 if (GET_MODE (src
) != V4SImode
)
4906 new_src
= simplify_gen_subreg (V4SImode
, src
, GET_MODE (src
), 0);
4910 if (GET_MODE (src
) != V2DImode
)
4911 new_src
= simplify_gen_subreg (V2DImode
, src
, GET_MODE (src
), 0);
4914 for (byte
= 0, index
= 0; byte
< GET_MODE_SIZE (TImode
);
4915 byte
+= UNITS_PER_WORD
, index
++)
4917 d
= mips_subword_at_byte (dest
, byte
);
4919 emit_insn (gen_msa_copy_s_w (d
, new_src
, GEN_INT (index
)));
4921 emit_insn (gen_msa_copy_s_d (d
, new_src
, GEN_INT (index
)));
4926 low_dest
= mips_subword_at_byte (dest
, 0);
4927 low_src
= mips_subword_at_byte (src
, 0);
4928 gcc_assert (REG_P (low_dest
) && REG_P (low_src
));
4929 /* Make sure the source register is not written before reading. */
4930 if (REGNO (low_dest
) <= REGNO (low_src
))
4932 for (byte
= 0; byte
< GET_MODE_SIZE (TImode
);
4933 byte
+= UNITS_PER_WORD
)
4935 d
= mips_subword_at_byte (dest
, byte
);
4936 s
= mips_subword_at_byte (src
, byte
);
4937 mips_emit_move (d
, s
);
4942 for (byte
= GET_MODE_SIZE (TImode
) - UNITS_PER_WORD
; byte
>= 0;
4943 byte
-= UNITS_PER_WORD
)
4945 d
= mips_subword_at_byte (dest
, byte
);
4946 s
= mips_subword_at_byte (src
, byte
);
4947 mips_emit_move (d
, s
);
4953 /* Split a COPY_S.D with operands DEST, SRC and INDEX. GEN is a function
4954 used to generate subregs. */
4957 mips_split_msa_copy_d (rtx dest
, rtx src
, rtx index
,
4958 rtx (*gen_fn
)(rtx
, rtx
, rtx
))
4960 gcc_assert ((GET_MODE (src
) == V2DImode
&& GET_MODE (dest
) == DImode
)
4961 || (GET_MODE (src
) == V2DFmode
&& GET_MODE (dest
) == DFmode
));
4963 /* Note that low is always from the lower index, and high is always
4964 from the higher index. */
4965 rtx low
= mips_subword (dest
, false);
4966 rtx high
= mips_subword (dest
, true);
4967 rtx new_src
= simplify_gen_subreg (V4SImode
, src
, GET_MODE (src
), 0);
4969 emit_insn (gen_fn (low
, new_src
, GEN_INT (INTVAL (index
) * 2)));
4970 emit_insn (gen_fn (high
, new_src
, GEN_INT (INTVAL (index
) * 2 + 1)));
4973 /* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2. */
4976 mips_split_msa_insert_d (rtx dest
, rtx src1
, rtx index
, rtx src2
)
4979 gcc_assert (GET_MODE (dest
) == GET_MODE (src1
));
4980 gcc_assert ((GET_MODE (dest
) == V2DImode
4981 && (GET_MODE (src2
) == DImode
|| src2
== const0_rtx
))
4982 || (GET_MODE (dest
) == V2DFmode
&& GET_MODE (src2
) == DFmode
));
4984 /* Note that low is always from the lower index, and high is always
4985 from the higher index. */
4986 rtx low
= mips_subword (src2
, false);
4987 rtx high
= mips_subword (src2
, true);
4988 rtx new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
4989 rtx new_src1
= simplify_gen_subreg (V4SImode
, src1
, GET_MODE (src1
), 0);
4990 i
= exact_log2 (INTVAL (index
));
4991 gcc_assert (i
!= -1);
4993 emit_insn (gen_msa_insert_w (new_dest
, low
, new_src1
,
4994 GEN_INT (1 << (i
* 2))));
4995 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
,
4996 GEN_INT (1 << (i
* 2 + 1))));
5002 mips_split_msa_fill_d (rtx dest
, rtx src
)
5004 gcc_assert ((GET_MODE (dest
) == V2DImode
5005 && (GET_MODE (src
) == DImode
|| src
== const0_rtx
))
5006 || (GET_MODE (dest
) == V2DFmode
&& GET_MODE (src
) == DFmode
));
5008 /* Note that low is always from the lower index, and high is always
5009 from the higher index. */
5011 if (src
== const0_rtx
)
5018 low
= mips_subword (src
, false);
5019 high
= mips_subword (src
, true);
5021 rtx new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
5022 emit_insn (gen_msa_fill_w (new_dest
, low
));
5023 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
, GEN_INT (1 << 1)));
5024 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
, GEN_INT (1 << 3)));
5027 /* Return true if a move from SRC to DEST in INSN should be split. */
5030 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
5032 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
5035 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
5039 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
5041 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
5044 /* Return the appropriate instructions to move SRC into DEST. Assume
5045 that SRC is operand 1 and DEST is operand 0. */
5048 mips_output_move (rtx dest
, rtx src
)
5050 enum rtx_code dest_code
= GET_CODE (dest
);
5051 enum rtx_code src_code
= GET_CODE (src
);
5052 machine_mode mode
= GET_MODE (dest
);
5053 bool dbl_p
= (GET_MODE_SIZE (mode
) == 8);
5054 bool msa_p
= MSA_SUPPORTED_MODE_P (mode
);
5055 enum mips_symbol_type symbol_type
;
5057 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
5061 && dest_code
== REG
&& FP_REG_P (REGNO (dest
))
5062 && src_code
== CONST_VECTOR
5063 && CONST_INT_P (CONST_VECTOR_ELT (src
, 0)))
5065 gcc_assert (mips_const_vector_same_int_p (src
, mode
, -512, 511));
5066 return "ldi.%v0\t%w0,%E1";
5069 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
5070 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
5072 if (dest_code
== REG
)
5074 if (GP_REG_P (REGNO (dest
)))
5075 return "move\t%0,%z1";
5077 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
5079 if (ISA_HAS_DSP_MULT
)
5080 return "mult\t%q0,%.,%.";
5082 return "mult\t%.,%.";
5085 /* Moves to HI are handled by special .md insns. */
5086 if (REGNO (dest
) == LO_REGNUM
)
5089 if (DSP_ACC_REG_P (REGNO (dest
)))
5091 static char retval
[] = "mt__\t%z1,%q0";
5093 retval
[2] = reg_names
[REGNO (dest
)][4];
5094 retval
[3] = reg_names
[REGNO (dest
)][5];
5098 if (FP_REG_P (REGNO (dest
)))
5102 gcc_assert (src
== CONST0_RTX (GET_MODE (src
)));
5103 return "ldi.%v0\t%w0,0";
5106 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
5109 if (ALL_COP_REG_P (REGNO (dest
)))
5111 static char retval
[] = "dmtc_\t%z1,%0";
5113 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
5114 return dbl_p
? retval
: retval
+ 1;
5117 if (dest_code
== MEM
)
5118 switch (GET_MODE_SIZE (mode
))
5120 case 1: return "sb\t%z1,%0";
5121 case 2: return "sh\t%z1,%0";
5122 case 4: return "sw\t%z1,%0";
5123 case 8: return "sd\t%z1,%0";
5124 default: gcc_unreachable ();
5127 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
5129 if (src_code
== REG
)
5131 /* Moves from HI are handled by special .md insns. */
5132 if (REGNO (src
) == LO_REGNUM
)
5134 /* When generating VR4120 or VR4130 code, we use MACC and
5135 DMACC instead of MFLO. This avoids both the normal
5136 MIPS III HI/LO hazards and the errata related to
5139 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
5143 if (DSP_ACC_REG_P (REGNO (src
)))
5145 static char retval
[] = "mf__\t%0,%q1";
5147 retval
[2] = reg_names
[REGNO (src
)][4];
5148 retval
[3] = reg_names
[REGNO (src
)][5];
5152 if (FP_REG_P (REGNO (src
)))
5154 gcc_assert (!msa_p
);
5155 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
5158 if (ALL_COP_REG_P (REGNO (src
)))
5160 static char retval
[] = "dmfc_\t%0,%1";
5162 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
5163 return dbl_p
? retval
: retval
+ 1;
5167 if (src_code
== MEM
)
5168 switch (GET_MODE_SIZE (mode
))
5170 case 1: return "lbu\t%0,%1";
5171 case 2: return "lhu\t%0,%1";
5172 case 4: return "lw\t%0,%1";
5173 case 8: return "ld\t%0,%1";
5174 default: gcc_unreachable ();
5177 if (src_code
== CONST_INT
)
5179 /* Don't use the X format for the operand itself, because that
5180 will give out-of-range numbers for 64-bit hosts and 32-bit
5183 return "li\t%0,%1\t\t\t# %X1";
5185 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
5188 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
5192 if (src_code
== HIGH
)
5193 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
5195 if (CONST_GP_P (src
))
5196 return "move\t%0,%1";
5198 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
5199 && mips_lo_relocs
[symbol_type
] != 0)
5201 /* A signed 16-bit constant formed by applying a relocation
5202 operator to a symbolic address. */
5203 gcc_assert (!mips_split_p
[symbol_type
]);
5204 return "li\t%0,%R1";
5207 if (symbolic_operand (src
, VOIDmode
))
5209 gcc_assert (TARGET_MIPS16
5210 ? TARGET_MIPS16_TEXT_LOADS
5211 : !TARGET_EXPLICIT_RELOCS
);
5212 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
5215 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
5217 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
5219 if (GET_MODE (dest
) == V2SFmode
)
5220 return "mov.ps\t%0,%1";
5222 return "move.v\t%w0,%w1";
5224 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
5227 if (dest_code
== MEM
)
5230 return "st.%v1\t%w1,%0";
5232 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
5235 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
5237 if (src_code
== MEM
)
5240 return "ld.%v0\t%w0,%1";
5242 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
5245 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
5247 static char retval
[] = "l_c_\t%0,%1";
5249 retval
[1] = (dbl_p
? 'd' : 'w');
5250 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
5253 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
5255 static char retval
[] = "s_c_\t%1,%0";
5257 retval
[1] = (dbl_p
? 'd' : 'w');
5258 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
5264 /* Return true if CMP1 is a suitable second operand for integer ordering
5265 test CODE. See also the *sCC patterns in mips.md. */
5268 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
5274 return reg_or_0_operand (cmp1
, VOIDmode
);
5278 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
5282 return arith_operand (cmp1
, VOIDmode
);
5285 return sle_operand (cmp1
, VOIDmode
);
5288 return sleu_operand (cmp1
, VOIDmode
);
5295 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
5296 integer ordering test *CODE, or if an equivalent combination can
5297 be formed by adjusting *CODE and *CMP1. When returning true, update
5298 *CODE and *CMP1 with the chosen code and operand, otherwise leave
5302 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
5305 HOST_WIDE_INT plus_one
;
5307 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
5310 if (CONST_INT_P (*cmp1
))
5314 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
5315 if (INTVAL (*cmp1
) < plus_one
)
5318 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
5324 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
5328 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
5339 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
5340 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
5341 is nonnull, it's OK to set TARGET to the inverse of the result and
5342 flip *INVERT_PTR instead. */
5345 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
5346 rtx target
, rtx cmp0
, rtx cmp1
)
5350 /* First see if there is a MIPS instruction that can do this operation.
5351 If not, try doing the same for the inverse operation. If that also
5352 fails, force CMP1 into a register and try again. */
5353 mode
= GET_MODE (cmp0
);
5354 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
5355 mips_emit_binary (code
, target
, cmp0
, cmp1
);
5358 enum rtx_code inv_code
= reverse_condition (code
);
5359 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
5361 cmp1
= force_reg (mode
, cmp1
);
5362 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
5364 else if (invert_ptr
== 0)
5368 inv_target
= mips_force_binary (GET_MODE (target
),
5369 inv_code
, cmp0
, cmp1
);
5370 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
5374 *invert_ptr
= !*invert_ptr
;
5375 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
5380 /* Return a register that is zero iff CMP0 and CMP1 are equal.
5381 The register will have the same mode as CMP0. */
5384 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
5386 if (cmp1
== const0_rtx
)
5389 if (uns_arith_operand (cmp1
, VOIDmode
))
5390 return expand_binop (GET_MODE (cmp0
), xor_optab
,
5391 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
5393 return expand_binop (GET_MODE (cmp0
), sub_optab
,
5394 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
5397 /* Convert *CODE into a code that can be used in a floating-point
5398 scc instruction (C.cond.fmt). Return true if the values of
5399 the condition code registers will be inverted, with 0 indicating
5400 that the condition holds. */
5403 mips_reversed_fp_cond (enum rtx_code
*code
)
5410 *code
= reverse_condition_maybe_unordered (*code
);
5418 /* Allocate a floating-point condition-code register of mode MODE.
5420 These condition code registers are used for certain kinds
5421 of compound operation, such as compare and branches, vconds,
5422 and built-in functions. At expand time, their use is entirely
5423 controlled by MIPS-specific code and is entirely internal
5424 to these compound operations.
5426 We could (and did in the past) expose condition-code values
5427 as pseudo registers and leave the register allocator to pick
5428 appropriate registers. The problem is that it is not practically
5429 possible for the rtl optimizers to guarantee that no spills will
5430 be needed, even when AVOID_CCMODE_COPIES is defined. We would
5431 therefore need spill and reload sequences to handle the worst case.
5433 Although such sequences do exist, they are very expensive and are
5434 not something we'd want to use. This is especially true of CCV2 and
5435 CCV4, where all the shuffling would greatly outweigh whatever benefit
5436 the vectorization itself provides.
5438 The main benefit of having more than one condition-code register
5439 is to allow the pipelining of operations, especially those involving
5440 comparisons and conditional moves. We don't really expect the
5441 registers to be live for long periods, and certainly never want
5442 them to be live across calls.
5444 Also, there should be no penalty attached to using all the available
5445 registers. They are simply bits in the same underlying FPU control
5448 We therefore expose the hardware registers from the outset and use
5449 a simple round-robin allocation scheme. */
5452 mips_allocate_fcc (machine_mode mode
)
5454 unsigned int regno
, count
;
5456 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
5460 else if (mode
== CCV2mode
)
5462 else if (mode
== CCV4mode
)
5467 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
5468 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
5469 cfun
->machine
->next_fcc
= 0;
5470 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
5471 cfun
->machine
->next_fcc
+= count
;
5472 return gen_rtx_REG (mode
, regno
);
5475 /* Convert a comparison into something that can be used in a branch or
5476 conditional move. On entry, *OP0 and *OP1 are the values being
5477 compared and *CODE is the code used to compare them.
5479 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5480 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5481 otherwise any standard branch condition can be used. The standard branch
5484 - EQ or NE between two registers.
5485 - any comparison between a register and zero.
5486 - if compact branches are available then any condition is valid. */
5489 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
5494 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
5496 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
5498 else if (*code
== EQ
|| *code
== NE
)
5502 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
5506 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5508 else if (!need_eq_ne_p
&& TARGET_CB_MAYBE
)
5538 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5548 /* The comparison needs a separate scc instruction. Store the
5549 result of the scc in *OP0 and compare it against zero. */
5550 bool invert
= false;
5551 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
5552 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
5553 *code
= (invert
? EQ
: NE
);
5557 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
5559 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
5560 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
5566 enum rtx_code cmp_code
;
5568 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5569 comparison to set a register. The branch or conditional move will
5570 then compare that register against zero.
5572 Set CMP_CODE to the code of the comparison instruction and
5573 *CODE to the code that the branch or move should use. */
5577 /* All FP conditions can be implemented directly with CMP.cond.fmt
5578 or by reversing the operands. */
5580 *op0
= gen_reg_rtx (CCFmode
);
5584 /* Three FP conditions cannot be implemented by reversing the
5585 operands for C.cond.fmt, instead a reversed condition code is
5586 required and a test for false. */
5587 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
5589 *op0
= mips_allocate_fcc (CCmode
);
5591 *op0
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
5595 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
5599 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5600 and OPERAND[3]. Store the result in OPERANDS[0].
5602 On 64-bit targets, the mode of the comparison and target will always be
5603 SImode, thus possibly narrower than that of the comparison's operands. */
5606 mips_expand_scc (rtx operands
[])
5608 rtx target
= operands
[0];
5609 enum rtx_code code
= GET_CODE (operands
[1]);
5610 rtx op0
= operands
[2];
5611 rtx op1
= operands
[3];
5613 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
5615 if (code
== EQ
|| code
== NE
)
5618 && reg_imm10_operand (op1
, GET_MODE (op1
)))
5619 mips_emit_binary (code
, target
, op0
, op1
);
5622 rtx zie
= mips_zero_if_equal (op0
, op1
);
5623 mips_emit_binary (code
, target
, zie
, const0_rtx
);
5627 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5630 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5631 CODE and jump to OPERANDS[3] if the condition holds. */
5634 mips_expand_conditional_branch (rtx
*operands
)
5636 enum rtx_code code
= GET_CODE (operands
[0]);
5637 rtx op0
= operands
[1];
5638 rtx op1
= operands
[2];
5641 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5642 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5643 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5648 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5649 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5652 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5653 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5658 reversed_p
= mips_reversed_fp_cond (&cond
);
5659 cmp_result
= mips_allocate_fcc (CCV2mode
);
5660 emit_insn (gen_scc_ps (cmp_result
,
5661 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5663 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5666 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5670 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5671 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5674 mips_expand_conditional_move (rtx
*operands
)
5677 enum rtx_code code
= GET_CODE (operands
[1]);
5678 rtx op0
= XEXP (operands
[1], 0);
5679 rtx op1
= XEXP (operands
[1], 1);
5681 mips_emit_compare (&code
, &op0
, &op1
, true);
5682 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5684 /* There is no direct support for general conditional GP move involving
5685 two registers using SEL. */
5687 && INTEGRAL_MODE_P (GET_MODE (operands
[2]))
5688 && register_operand (operands
[2], VOIDmode
)
5689 && register_operand (operands
[3], VOIDmode
))
5691 machine_mode mode
= GET_MODE (operands
[0]);
5692 rtx temp
= gen_reg_rtx (mode
);
5693 rtx temp2
= gen_reg_rtx (mode
);
5695 emit_insn (gen_rtx_SET (temp
,
5696 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5697 operands
[2], const0_rtx
)));
5699 /* Flip the test for the second operand. */
5700 cond
= gen_rtx_fmt_ee ((code
== EQ
) ? NE
: EQ
, GET_MODE (op0
), op0
, op1
);
5702 emit_insn (gen_rtx_SET (temp2
,
5703 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5704 operands
[3], const0_rtx
)));
5706 /* Merge the two results, at least one is guaranteed to be zero. */
5707 emit_insn (gen_rtx_SET (operands
[0], gen_rtx_IOR (mode
, temp
, temp2
)));
5711 if (FLOAT_MODE_P (GET_MODE (operands
[2])) && !ISA_HAS_SEL
)
5713 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
5714 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
5717 emit_insn (gen_rtx_SET (operands
[0],
5718 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5719 operands
[2], operands
[3])));
5723 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5726 mips_expand_conditional_trap (rtx comparison
)
5732 /* MIPS conditional trap instructions don't have GT or LE flavors,
5733 so we must swap the operands and convert to LT and GE respectively. */
5734 code
= GET_CODE (comparison
);
5741 code
= swap_condition (code
);
5742 op0
= XEXP (comparison
, 1);
5743 op1
= XEXP (comparison
, 0);
5747 op0
= XEXP (comparison
, 0);
5748 op1
= XEXP (comparison
, 1);
5752 mode
= GET_MODE (XEXP (comparison
, 0));
5753 op0
= force_reg (mode
, op0
);
5754 if (!(ISA_HAS_COND_TRAPI
5755 ? arith_operand (op1
, mode
)
5756 : reg_or_0_operand (op1
, mode
)))
5757 op1
= force_reg (mode
, op1
);
5759 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5760 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5764 /* Initialize *CUM for a call to a function of type FNTYPE. */
5767 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5769 memset (cum
, 0, sizeof (*cum
));
5770 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5771 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5774 /* Fill INFO with information about a single argument. CUM is the
5775 cumulative state for earlier arguments. MODE is the mode of this
5776 argument and TYPE is its type (if known). NAMED is true if this
5777 is a named (fixed) argument rather than a variable one. */
5780 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5781 machine_mode mode
, const_tree type
, bool named
)
5783 bool doubleword_aligned_p
;
5784 unsigned int num_bytes
, num_words
, max_regs
;
5786 /* Work out the size of the argument. */
5787 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5788 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5790 /* Decide whether it should go in a floating-point register, assuming
5791 one is free. Later code checks for availability.
5793 The checks against UNITS_PER_FPVALUE handle the soft-float and
5794 single-float cases. */
5798 /* The EABI conventions have traditionally been defined in terms
5799 of TYPE_MODE, regardless of the actual type. */
5800 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5801 || mode
== V2SFmode
)
5802 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5807 /* Only leading floating-point scalars are passed in
5808 floating-point registers. We also handle vector floats the same
5809 say, which is OK because they are not covered by the standard ABI. */
5810 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5811 info
->fpr_p
= (!cum
->gp_reg_found
5812 && cum
->arg_number
< 2
5814 || SCALAR_FLOAT_TYPE_P (type
)
5815 || VECTOR_FLOAT_TYPE_P (type
))
5816 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5817 || mode
== V2SFmode
)
5818 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5823 /* Scalar, complex and vector floating-point types are passed in
5824 floating-point registers, as long as this is a named rather
5825 than a variable argument. */
5826 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5827 info
->fpr_p
= (named
5828 && (type
== 0 || FLOAT_TYPE_P (type
))
5829 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5830 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5831 || mode
== V2SFmode
)
5832 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5834 /* ??? According to the ABI documentation, the real and imaginary
5835 parts of complex floats should be passed in individual registers.
5836 The real and imaginary parts of stack arguments are supposed
5837 to be contiguous and there should be an extra word of padding
5840 This has two problems. First, it makes it impossible to use a
5841 single "void *" va_list type, since register and stack arguments
5842 are passed differently. (At the time of writing, MIPSpro cannot
5843 handle complex float varargs correctly.) Second, it's unclear
5844 what should happen when there is only one register free.
5846 For now, we assume that named complex floats should go into FPRs
5847 if there are two FPRs free, otherwise they should be passed in the
5848 same way as a struct containing two floats. */
5850 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5851 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5853 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5854 info
->fpr_p
= false;
5864 /* See whether the argument has doubleword alignment. */
5865 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5868 /* Set REG_OFFSET to the register count we're interested in.
5869 The EABI allocates the floating-point registers separately,
5870 but the other ABIs allocate them like integer registers. */
5871 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5875 /* Advance to an even register if the argument is doubleword-aligned. */
5876 if (doubleword_aligned_p
)
5877 info
->reg_offset
+= info
->reg_offset
& 1;
5879 /* Work out the offset of a stack argument. */
5880 info
->stack_offset
= cum
->stack_words
;
5881 if (doubleword_aligned_p
)
5882 info
->stack_offset
+= info
->stack_offset
& 1;
5884 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5886 /* Partition the argument between registers and stack. */
5887 info
->reg_words
= MIN (num_words
, max_regs
);
5888 info
->stack_words
= num_words
- info
->reg_words
;
5891 /* INFO describes a register argument that has the normal format for the
5892 argument's mode. Return the register it uses, assuming that FPRs are
5893 available if HARD_FLOAT_P. */
5896 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5898 if (!info
->fpr_p
|| !hard_float_p
)
5899 return GP_ARG_FIRST
+ info
->reg_offset
;
5900 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5901 /* In o32, the second argument is always passed in $f14
5902 for TARGET_DOUBLE_FLOAT, regardless of whether the
5903 first argument was a word or doubleword. */
5904 return FP_ARG_FIRST
+ 2;
5906 return FP_ARG_FIRST
+ info
->reg_offset
;
5909 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5912 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5914 return !TARGET_OLDABI
;
5917 /* Implement TARGET_FUNCTION_ARG. */
5920 mips_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
5921 const_tree type
, bool named
)
5923 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5924 struct mips_arg_info info
;
5926 /* We will be called with a mode of VOIDmode after the last argument
5927 has been seen. Whatever we return will be passed to the call expander.
5928 If we need a MIPS16 fp_code, return a REG with the code stored as
5930 if (mode
== VOIDmode
)
5932 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5933 return gen_rtx_REG ((machine_mode
) cum
->fp_code
, 0);
5938 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5940 /* Return straight away if the whole argument is passed on the stack. */
5941 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5944 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5945 contains a double in its entirety, then that 64-bit chunk is passed
5946 in a floating-point register. */
5948 && TARGET_HARD_FLOAT
5951 && TREE_CODE (type
) == RECORD_TYPE
5952 && TYPE_SIZE_UNIT (type
)
5953 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5957 /* First check to see if there is any such field. */
5958 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5959 if (TREE_CODE (field
) == FIELD_DECL
5960 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5961 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5962 && tree_fits_shwi_p (bit_position (field
))
5963 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5968 /* Now handle the special case by returning a PARALLEL
5969 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5970 chunks are passed in registers. */
5972 HOST_WIDE_INT bitpos
;
5975 /* assign_parms checks the mode of ENTRY_PARM, so we must
5976 use the actual mode here. */
5977 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5980 field
= TYPE_FIELDS (type
);
5981 for (i
= 0; i
< info
.reg_words
; i
++)
5985 for (; field
; field
= DECL_CHAIN (field
))
5986 if (TREE_CODE (field
) == FIELD_DECL
5987 && int_bit_position (field
) >= bitpos
)
5991 && int_bit_position (field
) == bitpos
5992 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5993 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5994 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5996 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5999 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
6000 GEN_INT (bitpos
/ BITS_PER_UNIT
));
6002 bitpos
+= BITS_PER_WORD
;
6008 /* Handle the n32/n64 conventions for passing complex floating-point
6009 arguments in FPR pairs. The real part goes in the lower register
6010 and the imaginary part goes in the upper register. */
6013 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6019 inner
= GET_MODE_INNER (mode
);
6020 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
6021 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
6023 /* Real part in registers, imaginary part on stack. */
6024 gcc_assert (info
.stack_words
== info
.reg_words
);
6025 return gen_rtx_REG (inner
, regno
);
6029 gcc_assert (info
.stack_words
== 0);
6030 real
= gen_rtx_EXPR_LIST (VOIDmode
,
6031 gen_rtx_REG (inner
, regno
),
6033 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
6035 regno
+ info
.reg_words
/ 2),
6036 GEN_INT (GET_MODE_SIZE (inner
)));
6037 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
6041 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
6044 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
6047 mips_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
6048 const_tree type
, bool named
)
6050 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6051 struct mips_arg_info info
;
6053 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
6056 cum
->gp_reg_found
= true;
6058 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
6059 an explanation of what this code does. It assumes that we're using
6060 either the o32 or the o64 ABI, both of which pass at most 2 arguments
6062 if (cum
->arg_number
< 2 && info
.fpr_p
)
6063 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
6065 /* Advance the register count. This has the effect of setting
6066 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
6067 argument required us to skip the final GPR and pass the whole
6068 argument on the stack. */
6069 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
6070 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
6071 else if (info
.reg_words
> 0)
6072 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
6074 /* Advance the stack word count. */
6075 if (info
.stack_words
> 0)
6076 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
6081 /* Implement TARGET_ARG_PARTIAL_BYTES. */
6084 mips_arg_partial_bytes (cumulative_args_t cum
,
6085 machine_mode mode
, tree type
, bool named
)
6087 struct mips_arg_info info
;
6089 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
6090 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
6093 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
6094 least PARM_BOUNDARY bits of alignment, but will be given anything up
6095 to STACK_BOUNDARY bits if the type requires it. */
6098 mips_function_arg_boundary (machine_mode mode
, const_tree type
)
6100 unsigned int alignment
;
6102 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
6103 if (alignment
< PARM_BOUNDARY
)
6104 alignment
= PARM_BOUNDARY
;
6105 if (alignment
> STACK_BOUNDARY
)
6106 alignment
= STACK_BOUNDARY
;
6110 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
6113 mips_get_reg_raw_mode (int regno
)
6115 if (TARGET_FLOATXX
&& FP_REG_P (regno
))
6117 return default_get_reg_raw_mode (regno
);
6120 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
6121 upward rather than downward. In other words, return true if the
6122 first byte of the stack slot has useful data, false if the last
6126 mips_pad_arg_upward (machine_mode mode
, const_tree type
)
6128 /* On little-endian targets, the first byte of every stack argument
6129 is passed in the first byte of the stack slot. */
6130 if (!BYTES_BIG_ENDIAN
)
6133 /* Otherwise, integral types are padded downward: the last byte of a
6134 stack argument is passed in the last byte of the stack slot. */
6136 ? (INTEGRAL_TYPE_P (type
)
6137 || POINTER_TYPE_P (type
)
6138 || FIXED_POINT_TYPE_P (type
))
6139 : (SCALAR_INT_MODE_P (mode
)
6140 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
6143 /* Big-endian o64 pads floating-point arguments downward. */
6144 if (mips_abi
== ABI_O64
)
6145 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6148 /* Other types are padded upward for o32, o64, n32 and n64. */
6149 if (mips_abi
!= ABI_EABI
)
6152 /* Arguments smaller than a stack slot are padded downward. */
6153 if (mode
!= BLKmode
)
6154 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
6156 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
6159 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
6160 if the least significant byte of the register has useful data. Return
6161 the opposite if the most significant byte does. */
6164 mips_pad_reg_upward (machine_mode mode
, tree type
)
6166 /* No shifting is required for floating-point arguments. */
6167 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6168 return !BYTES_BIG_ENDIAN
;
6170 /* Otherwise, apply the same padding to register arguments as we do
6171 to stack arguments. */
6172 return mips_pad_arg_upward (mode
, type
);
6175 /* Return nonzero when an argument must be passed by reference. */
6178 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6179 machine_mode mode
, const_tree type
,
6180 bool named ATTRIBUTE_UNUSED
)
6182 if (mips_abi
== ABI_EABI
)
6186 /* ??? How should SCmode be handled? */
6187 if (mode
== DImode
|| mode
== DFmode
6188 || mode
== DQmode
|| mode
== UDQmode
6189 || mode
== DAmode
|| mode
== UDAmode
)
6192 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
6193 return size
== -1 || size
> UNITS_PER_WORD
;
6197 /* If we have a variable-sized parameter, we have no choice. */
6198 return targetm
.calls
.must_pass_in_stack (mode
, type
);
6202 /* Implement TARGET_CALLEE_COPIES. */
6205 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6206 machine_mode mode ATTRIBUTE_UNUSED
,
6207 const_tree type ATTRIBUTE_UNUSED
, bool named
)
6209 return mips_abi
== ABI_EABI
&& named
;
6212 /* See whether VALTYPE is a record whose fields should be returned in
6213 floating-point registers. If so, return the number of fields and
6214 list them in FIELDS (which should have two elements). Return 0
6217 For n32 & n64, a structure with one or two fields is returned in
6218 floating-point registers as long as every field has a floating-point
6222 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
6230 if (TREE_CODE (valtype
) != RECORD_TYPE
)
6234 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
6236 if (TREE_CODE (field
) != FIELD_DECL
)
6239 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
6245 fields
[i
++] = field
;
6250 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6251 a value in the most significant part of $2/$3 if:
6253 - the target is big-endian;
6255 - the value has a structure or union type (we generalize this to
6256 cover aggregates from other languages too); and
6258 - the structure is not returned in floating-point registers. */
6261 mips_return_in_msb (const_tree valtype
)
6265 return (TARGET_NEWABI
6266 && TARGET_BIG_ENDIAN
6267 && AGGREGATE_TYPE_P (valtype
)
6268 && mips_fpr_return_fields (valtype
, fields
) == 0);
6271 /* Return true if the function return value MODE will get returned in a
6272 floating-point register. */
6275 mips_return_mode_in_fpr_p (machine_mode mode
)
6277 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
6278 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
6280 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6281 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
6284 /* Return the representation of an FPR return register when the
6285 value being returned in FP_RETURN has mode VALUE_MODE and the
6286 return type itself has mode TYPE_MODE. On NewABI targets,
6287 the two modes may be different for structures like:
6289 struct __attribute__((packed)) foo { float f; }
6291 where we return the SFmode value of "f" in FP_RETURN, but where
6292 the structure itself has mode BLKmode. */
6295 mips_return_fpr_single (machine_mode type_mode
,
6296 machine_mode value_mode
)
6300 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
6301 if (type_mode
!= value_mode
)
6303 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
6304 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
6309 /* Return a composite value in a pair of floating-point registers.
6310 MODE1 and OFFSET1 are the mode and byte offset for the first value,
6311 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
6314 For n32 & n64, $f0 always holds the first value and $f2 the second.
6315 Otherwise the values are packed together as closely as possible. */
6318 mips_return_fpr_pair (machine_mode mode
,
6319 machine_mode mode1
, HOST_WIDE_INT offset1
,
6320 machine_mode mode2
, HOST_WIDE_INT offset2
)
6324 inc
= (TARGET_NEWABI
|| mips_abi
== ABI_32
? 2 : MAX_FPRS_PER_FMT
);
6325 return gen_rtx_PARALLEL
6328 gen_rtx_EXPR_LIST (VOIDmode
,
6329 gen_rtx_REG (mode1
, FP_RETURN
),
6331 gen_rtx_EXPR_LIST (VOIDmode
,
6332 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
6333 GEN_INT (offset2
))));
6337 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
6338 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
6339 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
6342 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
6351 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
6352 func
= fn_decl_or_type
;
6356 mode
= TYPE_MODE (valtype
);
6357 unsigned_p
= TYPE_UNSIGNED (valtype
);
6359 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
6360 return values, promote the mode here too. */
6361 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
6363 /* Handle structures whose fields are returned in $f0/$f2. */
6364 switch (mips_fpr_return_fields (valtype
, fields
))
6367 return mips_return_fpr_single (mode
,
6368 TYPE_MODE (TREE_TYPE (fields
[0])));
6371 return mips_return_fpr_pair (mode
,
6372 TYPE_MODE (TREE_TYPE (fields
[0])),
6373 int_byte_position (fields
[0]),
6374 TYPE_MODE (TREE_TYPE (fields
[1])),
6375 int_byte_position (fields
[1]));
6378 /* If a value is passed in the most significant part of a register, see
6379 whether we have to round the mode up to a whole number of words. */
6380 if (mips_return_in_msb (valtype
))
6382 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
6383 if (size
% UNITS_PER_WORD
!= 0)
6385 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
6386 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6390 /* For EABI, the class of return register depends entirely on MODE.
6391 For example, "struct { some_type x; }" and "union { some_type x; }"
6392 are returned in the same way as a bare "some_type" would be.
6393 Other ABIs only use FPRs for scalar, complex or vector types. */
6394 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
6395 return gen_rtx_REG (mode
, GP_RETURN
);
6400 /* Handle long doubles for n32 & n64. */
6402 return mips_return_fpr_pair (mode
,
6404 DImode
, GET_MODE_SIZE (mode
) / 2);
6406 if (mips_return_mode_in_fpr_p (mode
))
6408 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6409 return mips_return_fpr_pair (mode
,
6410 GET_MODE_INNER (mode
), 0,
6411 GET_MODE_INNER (mode
),
6412 GET_MODE_SIZE (mode
) / 2);
6414 return gen_rtx_REG (mode
, FP_RETURN
);
6418 return gen_rtx_REG (mode
, GP_RETURN
);
6421 /* Implement TARGET_FUNCTION_VALUE. */
6424 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
6425 bool outgoing ATTRIBUTE_UNUSED
)
6427 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
6430 /* Implement TARGET_LIBCALL_VALUE. */
6433 mips_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
6435 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
6438 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
6440 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
6443 mips_function_value_regno_p (const unsigned int regno
)
6445 /* Most types only require one GPR or one FPR for return values but for
6446 hard-float two FPRs can be used for _Complex types (for all ABIs)
6447 and long doubles (for n64). */
6448 if (regno
== GP_RETURN
6449 || regno
== FP_RETURN
6450 || (FP_RETURN
!= GP_RETURN
6451 && regno
== FP_RETURN
+ 2))
6454 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
6455 This does not apply to o32 FPXX as floating-point function argument and
6456 return registers are described as 64-bit even though floating-point
6457 registers are primarily described as 32-bit internally.
6458 See: mips_get_reg_raw_mode. */
6459 if ((mips_abi
== ABI_32
&& TARGET_FLOAT32
)
6460 && FP_RETURN
!= GP_RETURN
6461 && (regno
== FP_RETURN
+ 1
6462 || regno
== FP_RETURN
+ 3))
6468 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
6469 all BLKmode objects are returned in memory. Under the n32, n64
6470 and embedded ABIs, small structures are returned in a register.
6471 Objects with varying size must still be returned in memory, of
6475 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
6478 /* Ensure that any floating point vector types are returned via memory
6479 even if they are supported through a vector mode with some ASEs. */
6480 return (VECTOR_FLOAT_TYPE_P (type
)
6481 || TYPE_MODE (type
) == BLKmode
);
6483 return (!IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
6486 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6489 mips_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
6490 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6493 CUMULATIVE_ARGS local_cum
;
6494 int gp_saved
, fp_saved
;
6496 /* The caller has advanced CUM up to, but not beyond, the last named
6497 argument. Advance a local copy of CUM past the last "real" named
6498 argument, to find out how many registers are left over. */
6499 local_cum
= *get_cumulative_args (cum
);
6500 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
6503 /* Found out how many registers we need to save. */
6504 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
6505 fp_saved
= (EABI_FLOAT_VARARGS_P
6506 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
6515 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
6516 REG_PARM_STACK_SPACE (cfun
->decl
)
6517 - gp_saved
* UNITS_PER_WORD
);
6518 mem
= gen_frame_mem (BLKmode
, ptr
);
6519 set_mem_alias_set (mem
, get_varargs_alias_set ());
6521 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
6526 /* We can't use move_block_from_reg, because it will use
6531 /* Set OFF to the offset from virtual_incoming_args_rtx of
6532 the first float register. The FP save area lies below
6533 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6534 off
= ROUND_DOWN (-gp_saved
* UNITS_PER_WORD
, UNITS_PER_FPVALUE
);
6535 off
-= fp_saved
* UNITS_PER_FPREG
;
6537 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6539 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
6540 i
+= MAX_FPRS_PER_FMT
)
6544 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
6545 mem
= gen_frame_mem (mode
, ptr
);
6546 set_mem_alias_set (mem
, get_varargs_alias_set ());
6547 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
6548 off
+= UNITS_PER_HWFPVALUE
;
6552 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
6553 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
6554 + fp_saved
* UNITS_PER_FPREG
);
6557 /* Implement TARGET_BUILTIN_VA_LIST. */
6560 mips_build_builtin_va_list (void)
6562 if (EABI_FLOAT_VARARGS_P
)
6564 /* We keep 3 pointers, and two offsets.
6566 Two pointers are to the overflow area, which starts at the CFA.
6567 One of these is constant, for addressing into the GPR save area
6568 below it. The other is advanced up the stack through the
6571 The third pointer is to the bottom of the GPR save area.
6572 Since the FPR save area is just below it, we can address
6573 FPR slots off this pointer.
6575 We also keep two one-byte offsets, which are to be subtracted
6576 from the constant pointers to yield addresses in the GPR and
6577 FPR save areas. These are downcounted as float or non-float
6578 arguments are used, and when they get to zero, the argument
6579 must be obtained from the overflow region. */
6580 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
6583 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
6585 f_ovfl
= build_decl (BUILTINS_LOCATION
,
6586 FIELD_DECL
, get_identifier ("__overflow_argptr"),
6588 f_gtop
= build_decl (BUILTINS_LOCATION
,
6589 FIELD_DECL
, get_identifier ("__gpr_top"),
6591 f_ftop
= build_decl (BUILTINS_LOCATION
,
6592 FIELD_DECL
, get_identifier ("__fpr_top"),
6594 f_goff
= build_decl (BUILTINS_LOCATION
,
6595 FIELD_DECL
, get_identifier ("__gpr_offset"),
6596 unsigned_char_type_node
);
6597 f_foff
= build_decl (BUILTINS_LOCATION
,
6598 FIELD_DECL
, get_identifier ("__fpr_offset"),
6599 unsigned_char_type_node
);
6600 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6601 warn on every user file. */
6602 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
6603 array
= build_array_type (unsigned_char_type_node
,
6604 build_index_type (index
));
6605 f_res
= build_decl (BUILTINS_LOCATION
,
6606 FIELD_DECL
, get_identifier ("__reserved"), array
);
6608 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
6609 DECL_FIELD_CONTEXT (f_gtop
) = record
;
6610 DECL_FIELD_CONTEXT (f_ftop
) = record
;
6611 DECL_FIELD_CONTEXT (f_goff
) = record
;
6612 DECL_FIELD_CONTEXT (f_foff
) = record
;
6613 DECL_FIELD_CONTEXT (f_res
) = record
;
6615 TYPE_FIELDS (record
) = f_ovfl
;
6616 DECL_CHAIN (f_ovfl
) = f_gtop
;
6617 DECL_CHAIN (f_gtop
) = f_ftop
;
6618 DECL_CHAIN (f_ftop
) = f_goff
;
6619 DECL_CHAIN (f_goff
) = f_foff
;
6620 DECL_CHAIN (f_foff
) = f_res
;
6622 layout_type (record
);
6626 /* Otherwise, we use 'void *'. */
6627 return ptr_type_node
;
6630 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6633 mips_va_start (tree valist
, rtx nextarg
)
6635 if (EABI_FLOAT_VARARGS_P
)
6637 const CUMULATIVE_ARGS
*cum
;
6638 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6639 tree ovfl
, gtop
, ftop
, goff
, foff
;
6641 int gpr_save_area_size
;
6642 int fpr_save_area_size
;
6645 cum
= &crtl
->args
.info
;
6647 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
6649 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
6651 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6652 f_gtop
= DECL_CHAIN (f_ovfl
);
6653 f_ftop
= DECL_CHAIN (f_gtop
);
6654 f_goff
= DECL_CHAIN (f_ftop
);
6655 f_foff
= DECL_CHAIN (f_goff
);
6657 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6659 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
6661 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
6663 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
6665 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
6668 /* Emit code to initialize OVFL, which points to the next varargs
6669 stack argument. CUM->STACK_WORDS gives the number of stack
6670 words used by named arguments. */
6671 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
6672 if (cum
->stack_words
> 0)
6673 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
6674 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
6675 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6677 /* Emit code to initialize GTOP, the top of the GPR save area. */
6678 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
6679 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
6680 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6682 /* Emit code to initialize FTOP, the top of the FPR save area.
6683 This address is gpr_save_area_bytes below GTOP, rounded
6684 down to the next fp-aligned boundary. */
6685 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
6686 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
6687 fpr_offset
&= -UNITS_PER_FPVALUE
;
6689 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
6690 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
6691 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6693 /* Emit code to initialize GOFF, the offset from GTOP of the
6694 next GPR argument. */
6695 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6696 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6697 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6699 /* Likewise emit code to initialize FOFF, the offset from FTOP
6700 of the next FPR argument. */
6701 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6702 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6703 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6707 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6708 std_expand_builtin_va_start (valist
, nextarg
);
6712 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6716 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6719 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6720 unsigned HOST_WIDE_INT align
, boundary
;
6723 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6725 type
= build_pointer_type (type
);
6727 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6728 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6730 /* When we align parameter on stack for caller, if the parameter
6731 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6732 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6733 here with caller. */
6734 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6735 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6737 boundary
/= BITS_PER_UNIT
;
6739 /* Hoist the valist value into a temporary for the moment. */
6740 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6742 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6743 requires greater alignment, we must perform dynamic alignment. */
6744 if (boundary
> align
)
6746 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6747 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6748 gimplify_and_add (t
, pre_p
);
6750 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6751 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6753 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6754 gimplify_and_add (t
, pre_p
);
6759 /* If the actual alignment is less than the alignment of the type,
6760 adjust the type accordingly so that we don't assume strict alignment
6761 when dereferencing the pointer. */
6762 boundary
*= BITS_PER_UNIT
;
6763 if (boundary
< TYPE_ALIGN (type
))
6765 type
= build_variant_type_copy (type
);
6766 SET_TYPE_ALIGN (type
, boundary
);
6769 /* Compute the rounded size of the type. */
6770 type_size
= size_in_bytes (type
);
6771 rounded_size
= round_up (type_size
, align
);
6773 /* Reduce rounded_size so it's sharable with the postqueue. */
6774 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6778 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6780 /* Small args are padded downward. */
6781 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6782 rounded_size
, size_int (align
));
6783 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6784 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6785 addr
= fold_build_pointer_plus (addr
, t
);
6788 /* Compute new value for AP. */
6789 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6790 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6791 gimplify_and_add (t
, pre_p
);
6793 addr
= fold_convert (build_pointer_type (type
), addr
);
6796 addr
= build_va_arg_indirect_ref (addr
);
6798 return build_va_arg_indirect_ref (addr
);
6801 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6804 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6810 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6812 type
= build_pointer_type (type
);
6814 if (!EABI_FLOAT_VARARGS_P
)
6815 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6818 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6819 tree ovfl
, top
, off
, align
;
6820 HOST_WIDE_INT size
, rsize
, osize
;
6823 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6824 f_gtop
= DECL_CHAIN (f_ovfl
);
6825 f_ftop
= DECL_CHAIN (f_gtop
);
6826 f_goff
= DECL_CHAIN (f_ftop
);
6827 f_foff
= DECL_CHAIN (f_goff
);
6831 TOP be the top of the GPR or FPR save area;
6832 OFF be the offset from TOP of the next register;
6833 ADDR_RTX be the address of the argument;
6834 SIZE be the number of bytes in the argument type;
6835 RSIZE be the number of bytes used to store the argument
6836 when it's in the register save area; and
6837 OSIZE be the number of bytes used to store it when it's
6838 in the stack overflow area.
6840 The code we want is:
6842 1: off &= -rsize; // round down
6845 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6850 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6851 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6855 [1] and [9] can sometimes be optimized away. */
6857 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6859 size
= int_size_in_bytes (type
);
6861 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6862 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6864 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6865 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6866 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6867 unshare_expr (valist
), f_foff
, NULL_TREE
);
6869 /* When va_start saves FPR arguments to the stack, each slot
6870 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6871 argument's precision. */
6872 rsize
= UNITS_PER_HWFPVALUE
;
6874 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6875 (= PARM_BOUNDARY bits). This can be different from RSIZE
6878 (1) On 32-bit targets when TYPE is a structure such as:
6880 struct s { float f; };
6882 Such structures are passed in paired FPRs, so RSIZE
6883 will be 8 bytes. However, the structure only takes
6884 up 4 bytes of memory, so OSIZE will only be 4.
6886 (2) In combinations such as -mgp64 -msingle-float
6887 -fshort-double. Doubles passed in registers will then take
6888 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6889 stack take up UNITS_PER_WORD bytes. */
6890 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6894 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6895 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6896 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6897 unshare_expr (valist
), f_goff
, NULL_TREE
);
6898 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
6899 if (rsize
> UNITS_PER_WORD
)
6901 /* [1] Emit code for: off &= -rsize. */
6902 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6903 build_int_cst (TREE_TYPE (off
), -rsize
));
6904 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6909 /* [2] Emit code to branch if off == 0. */
6910 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6911 build_int_cst (TREE_TYPE (off
), 0));
6912 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6914 /* [5] Emit code for: off -= rsize. We do this as a form of
6915 post-decrement not available to C. */
6916 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6917 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6919 /* [4] Emit code for:
6920 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6921 t
= fold_convert (sizetype
, t
);
6922 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6923 t
= fold_build_pointer_plus (top
, t
);
6924 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6925 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6926 COND_EXPR_THEN (addr
) = t
;
6928 if (osize
> UNITS_PER_WORD
)
6930 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6931 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6932 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6933 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6934 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6935 unshare_expr (ovfl
), t
);
6940 /* [10, 11] Emit code for:
6941 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6943 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6944 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6945 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6946 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6948 /* String [9] and [10, 11] together. */
6950 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6951 COND_EXPR_ELSE (addr
) = t
;
6953 addr
= fold_convert (build_pointer_type (type
), addr
);
6954 addr
= build_va_arg_indirect_ref (addr
);
6958 addr
= build_va_arg_indirect_ref (addr
);
6963 /* Declare a unique, locally-binding function called NAME, then start
6967 mips_start_unique_function (const char *name
)
6971 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6972 get_identifier (name
),
6973 build_function_type_list (void_type_node
, NULL_TREE
));
6974 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6975 NULL_TREE
, void_type_node
);
6976 TREE_PUBLIC (decl
) = 1;
6977 TREE_STATIC (decl
) = 1;
6979 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
6981 targetm
.asm_out
.unique_section (decl
, 0);
6982 switch_to_section (get_named_section (decl
, NULL
, 0));
6984 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6985 fputs ("\t.hidden\t", asm_out_file
);
6986 assemble_name (asm_out_file
, name
);
6987 putc ('\n', asm_out_file
);
6990 /* Start a definition of function NAME. MIPS16_P indicates whether the
6991 function contains MIPS16 code. */
6994 mips_start_function_definition (const char *name
, bool mips16_p
)
6997 fprintf (asm_out_file
, "\t.set\tmips16\n");
6999 fprintf (asm_out_file
, "\t.set\tnomips16\n");
7001 if (TARGET_MICROMIPS
)
7002 fprintf (asm_out_file
, "\t.set\tmicromips\n");
7003 #ifdef HAVE_GAS_MICROMIPS
7005 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
7008 if (!flag_inhibit_size_directive
)
7010 fputs ("\t.ent\t", asm_out_file
);
7011 assemble_name (asm_out_file
, name
);
7012 fputs ("\n", asm_out_file
);
7015 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
7017 /* Start the definition proper. */
7018 assemble_name (asm_out_file
, name
);
7019 fputs (":\n", asm_out_file
);
7022 /* End a function definition started by mips_start_function_definition. */
7025 mips_end_function_definition (const char *name
)
7027 if (!flag_inhibit_size_directive
)
7029 fputs ("\t.end\t", asm_out_file
);
7030 assemble_name (asm_out_file
, name
);
7031 fputs ("\n", asm_out_file
);
7035 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
7036 then free *STUB_PTR. */
7039 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
7041 mips_one_only_stub
*stub
= *stub_ptr
;
7045 const char *name
= stub
->get_name ();
7046 mips_start_unique_function (name
);
7047 mips_start_function_definition (name
, false);
7048 stub
->output_body ();
7049 mips_end_function_definition (name
);
7054 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
7057 mips_ok_for_lazy_binding_p (rtx x
)
7059 return (TARGET_USE_GOT
7060 && GET_CODE (x
) == SYMBOL_REF
7061 && !SYMBOL_REF_BIND_NOW_P (x
)
7062 && !mips_symbol_binds_local_p (x
));
7065 /* Load function address ADDR into register DEST. TYPE is as for
7066 mips_expand_call. Return true if we used an explicit lazy-binding
7070 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
7072 /* If we're generating PIC, and this call is to a global function,
7073 try to allow its address to be resolved lazily. This isn't
7074 possible for sibcalls when $gp is call-saved because the value
7075 of $gp on entry to the stub would be our caller's gp, not ours. */
7076 if (TARGET_EXPLICIT_RELOCS
7077 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
7078 && mips_ok_for_lazy_binding_p (addr
))
7080 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
7081 emit_insn (gen_rtx_SET (dest
, addr
));
7086 mips_emit_move (dest
, addr
);
7091 /* Each locally-defined hard-float MIPS16 function has a local symbol
7092 associated with it. This hash table maps the function symbol (FUNC)
7093 to the local symbol (LOCAL). */
7094 static GTY (()) hash_map
<nofree_string_hash
, rtx
> *mips16_local_aliases
;
7096 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
7097 Return a local alias for it, creating a new one if necessary. */
7100 mips16_local_alias (rtx func
)
7102 /* Create the hash table if this is the first call. */
7103 if (mips16_local_aliases
== NULL
)
7104 mips16_local_aliases
= hash_map
<nofree_string_hash
, rtx
>::create_ggc (37);
7106 /* Look up the function symbol, creating a new entry if need be. */
7108 const char *func_name
= XSTR (func
, 0);
7109 rtx
*slot
= &mips16_local_aliases
->get_or_insert (func_name
, &existed
);
7110 gcc_assert (slot
!= NULL
);
7116 /* Create a new SYMBOL_REF for the local symbol. The choice of
7117 __fn_local_* is based on the __fn_stub_* names that we've
7118 traditionally used for the non-MIPS16 stub. */
7119 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
7120 const char *local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
7121 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
7122 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
7124 /* Create a new structure to represent the mapping. */
7130 /* A chained list of functions for which mips16_build_call_stub has already
7131 generated a stub. NAME is the name of the function and FP_RET_P is true
7132 if the function returns a value in floating-point registers. */
7133 struct mips16_stub
{
7134 struct mips16_stub
*next
;
7138 static struct mips16_stub
*mips16_stubs
;
7140 /* Return the two-character string that identifies floating-point
7141 return mode MODE in the name of a MIPS16 function stub. */
7144 mips16_call_stub_mode_suffix (machine_mode mode
)
7148 else if (mode
== DFmode
)
7150 else if (mode
== SCmode
)
7152 else if (mode
== DCmode
)
7154 else if (mode
== V2SFmode
)
7156 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
);
7163 /* Write instructions to move a 32-bit value between general register
7164 GPREG and floating-point register FPREG. DIRECTION is 't' to move
7165 from GPREG to FPREG and 'f' to move in the opposite direction. */
7168 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
7170 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7171 reg_names
[gpreg
], reg_names
[fpreg
]);
7174 /* Likewise for 64-bit values. */
7177 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
7180 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
7181 reg_names
[gpreg
], reg_names
[fpreg
]);
7182 else if (ISA_HAS_MXHC1
)
7184 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7185 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
7186 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
7187 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
7189 else if (TARGET_FLOATXX
&& direction
== 't')
7191 /* Use the argument save area to move via memory. */
7192 fprintf (asm_out_file
, "\tsw\t%s,0($sp)\n", reg_names
[gpreg
]);
7193 fprintf (asm_out_file
, "\tsw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
7194 fprintf (asm_out_file
, "\tldc1\t%s,0($sp)\n", reg_names
[fpreg
]);
7196 else if (TARGET_FLOATXX
&& direction
== 'f')
7198 /* Use the argument save area to move via memory. */
7199 fprintf (asm_out_file
, "\tsdc1\t%s,0($sp)\n", reg_names
[fpreg
]);
7200 fprintf (asm_out_file
, "\tlw\t%s,0($sp)\n", reg_names
[gpreg
]);
7201 fprintf (asm_out_file
, "\tlw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
7205 /* Move the least-significant word. */
7206 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7207 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
7208 /* ...then the most significant word. */
7209 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7210 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
7214 /* Write out code to move floating-point arguments into or out of
7215 general registers. FP_CODE is the code describing which arguments
7216 are present (see the comment above the definition of CUMULATIVE_ARGS
7217 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
7220 mips_output_args_xfer (int fp_code
, char direction
)
7222 unsigned int gparg
, fparg
, f
;
7223 CUMULATIVE_ARGS cum
;
7225 /* This code only works for o32 and o64. */
7226 gcc_assert (TARGET_OLDABI
);
7228 mips_init_cumulative_args (&cum
, NULL
);
7230 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7233 struct mips_arg_info info
;
7237 else if ((f
& 3) == 2)
7242 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
7243 gparg
= mips_arg_regno (&info
, false);
7244 fparg
= mips_arg_regno (&info
, true);
7247 mips_output_32bit_xfer (direction
, gparg
, fparg
);
7249 mips_output_64bit_xfer (direction
, gparg
, fparg
);
7251 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
7255 /* Write a MIPS16 stub for the current function. This stub is used
7256 for functions which take arguments in the floating-point registers.
7257 It is normal-mode code that moves the floating-point arguments
7258 into the general registers and then jumps to the MIPS16 code. */
7261 mips16_build_function_stub (void)
7263 const char *fnname
, *alias_name
, *separator
;
7264 char *secname
, *stubname
;
7269 /* Create the name of the stub, and its unique section. */
7270 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
7271 alias
= mips16_local_alias (symbol
);
7273 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
7274 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
7275 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
7276 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
7278 /* Build a decl for the stub. */
7279 stubdecl
= build_decl (BUILTINS_LOCATION
,
7280 FUNCTION_DECL
, get_identifier (stubname
),
7281 build_function_type_list (void_type_node
, NULL_TREE
));
7282 set_decl_section_name (stubdecl
, secname
);
7283 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7284 RESULT_DECL
, NULL_TREE
, void_type_node
);
7286 /* Output a comment. */
7287 fprintf (asm_out_file
, "\t# Stub function for %s (",
7288 current_function_name ());
7290 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
7292 fprintf (asm_out_file
, "%s%s", separator
,
7293 (f
& 3) == 1 ? "float" : "double");
7296 fprintf (asm_out_file
, ")\n");
7298 /* Start the function definition. */
7299 assemble_start_function (stubdecl
, stubname
);
7300 mips_start_function_definition (stubname
, false);
7302 /* If generating pic2 code, either set up the global pointer or
7304 if (TARGET_ABICALLS_PIC2
)
7306 if (TARGET_ABSOLUTE_ABICALLS
)
7307 fprintf (asm_out_file
, "\t.option\tpic0\n");
7310 output_asm_insn ("%(.cpload\t%^%)", NULL
);
7311 /* Emit an R_MIPS_NONE relocation to tell the linker what the
7312 target function is. Use a local GOT access when loading the
7313 symbol, to cut down on the number of unnecessary GOT entries
7314 for stubs that aren't needed. */
7315 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
7320 /* Load the address of the MIPS16 function into $25. Do this first so
7321 that targets with coprocessor interlocks can use an MFC1 to fill the
7323 output_asm_insn ("la\t%^,%0", &symbol
);
7325 /* Move the arguments from floating-point registers to general registers. */
7326 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
7328 /* Jump to the MIPS16 function. */
7329 output_asm_insn ("jr\t%^", NULL
);
7331 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
7332 fprintf (asm_out_file
, "\t.option\tpic2\n");
7334 mips_end_function_definition (stubname
);
7336 /* If the linker needs to create a dynamic symbol for the target
7337 function, it will associate the symbol with the stub (which,
7338 unlike the target function, follows the proper calling conventions).
7339 It is therefore useful to have a local alias for the target function,
7340 so that it can still be identified as MIPS16 code. As an optimization,
7341 this symbol can also be used for indirect MIPS16 references from
7342 within this file. */
7343 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
7345 switch_to_section (function_section (current_function_decl
));
7348 /* The current function is a MIPS16 function that returns a value in an FPR.
7349 Copy the return value from its soft-float to its hard-float location.
7350 libgcc2 has special non-MIPS16 helper functions for each case. */
7353 mips16_copy_fpr_return_value (void)
7355 rtx fn
, insn
, retval
;
7357 machine_mode return_mode
;
7360 return_type
= DECL_RESULT (current_function_decl
);
7361 return_mode
= DECL_MODE (return_type
);
7363 name
= ACONCAT (("__mips16_ret_",
7364 mips16_call_stub_mode_suffix (return_mode
),
7366 fn
= mips16_stub_function (name
);
7368 /* The function takes arguments in $2 (and possibly $3), so calls
7369 to it cannot be lazily bound. */
7370 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
7372 /* Model the call as something that takes the GPR return value as
7373 argument and returns an "updated" value. */
7374 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
7375 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
7376 const0_rtx
, NULL_RTX
, false);
7377 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
7380 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
7381 RETVAL is the location of the return value, or null if this is
7382 a "call" rather than a "call_value". ARGS_SIZE is the size of the
7383 arguments and FP_CODE is the code built by mips_function_arg;
7384 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
7386 There are three alternatives:
7388 - If a stub was needed, emit the call and return the call insn itself.
7390 - If we can avoid using a stub by redirecting the call, set *FN_PTR
7391 to the new target and return null.
7393 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
7396 A stub is needed for calls to functions that, in normal mode,
7397 receive arguments in FPRs or return values in FPRs. The stub
7398 copies the arguments from their soft-float positions to their
7399 hard-float positions, calls the real function, then copies the
7400 return value from its hard-float position to its soft-float
7403 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
7404 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
7405 automatically redirects the JAL to the stub, otherwise the JAL
7406 continues to call FN directly. */
7409 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
7413 struct mips16_stub
*l
;
7417 /* We don't need to do anything if we aren't in MIPS16 mode, or if
7418 we were invoked with the -msoft-float option. */
7419 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
7422 /* Figure out whether the value might come back in a floating-point
7424 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
7426 /* We don't need to do anything if there were no floating-point
7427 arguments and the value will not be returned in a floating-point
7429 if (fp_code
== 0 && !fp_ret_p
)
7432 /* We don't need to do anything if this is a call to a special
7433 MIPS16 support function. */
7435 if (mips16_stub_function_p (fn
))
7438 /* If we're calling a locally-defined MIPS16 function, we know that
7439 it will return values in both the "soft-float" and "hard-float"
7440 registers. There is no need to use a stub to move the latter
7442 if (fp_code
== 0 && mips16_local_function_p (fn
))
7445 /* This code will only work for o32 and o64 abis. The other ABI's
7446 require more sophisticated support. */
7447 gcc_assert (TARGET_OLDABI
);
7449 /* If we're calling via a function pointer, use one of the magic
7450 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
7451 Each stub expects the function address to arrive in register $2. */
7452 if (GET_CODE (fn
) != SYMBOL_REF
7453 || !call_insn_operand (fn
, VOIDmode
))
7460 /* If this is a locally-defined and locally-binding function,
7461 avoid the stub by calling the local alias directly. */
7462 if (mips16_local_function_p (fn
))
7464 *fn_ptr
= mips16_local_alias (fn
);
7468 /* Create a SYMBOL_REF for the libgcc.a function. */
7470 sprintf (buf
, "__mips16_call_stub_%s_%d",
7471 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
7474 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
7475 stub_fn
= mips16_stub_function (buf
);
7477 /* The function uses $2 as an argument, so calls to it
7478 cannot be lazily bound. */
7479 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
7481 /* Load the target function into $2. */
7482 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
7483 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
7485 /* Emit the call. */
7486 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
7487 args_size
, NULL_RTX
, lazy_p
);
7489 /* Tell GCC that this call does indeed use the value of $2. */
7490 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
7492 /* If we are handling a floating-point return value, we need to
7493 save $18 in the function prologue. Putting a note on the
7494 call will mean that df_regs_ever_live_p ($18) will be true if the
7495 call is not eliminated, and we can check that in the prologue
7498 CALL_INSN_FUNCTION_USAGE (insn
) =
7499 gen_rtx_EXPR_LIST (VOIDmode
,
7500 gen_rtx_CLOBBER (VOIDmode
,
7501 gen_rtx_REG (word_mode
, 18)),
7502 CALL_INSN_FUNCTION_USAGE (insn
));
7507 /* We know the function we are going to call. If we have already
7508 built a stub, we don't need to do anything further. */
7509 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
7510 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
7511 if (strcmp (l
->name
, fnname
) == 0)
7516 const char *separator
;
7517 char *secname
, *stubname
;
7518 tree stubid
, stubdecl
;
7521 /* If the function does not return in FPRs, the special stub
7525 If the function does return in FPRs, the stub section is named
7526 .mips16.call.fp.FNNAME
7528 Build a decl for the stub. */
7529 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
7531 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
7533 stubid
= get_identifier (stubname
);
7534 stubdecl
= build_decl (BUILTINS_LOCATION
,
7535 FUNCTION_DECL
, stubid
,
7536 build_function_type_list (void_type_node
,
7538 set_decl_section_name (stubdecl
, secname
);
7539 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7540 RESULT_DECL
, NULL_TREE
,
7543 /* Output a comment. */
7544 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
7546 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
7550 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7552 fprintf (asm_out_file
, "%s%s", separator
,
7553 (f
& 3) == 1 ? "float" : "double");
7556 fprintf (asm_out_file
, ")\n");
7558 /* Start the function definition. */
7559 assemble_start_function (stubdecl
, stubname
);
7560 mips_start_function_definition (stubname
, false);
7564 fprintf (asm_out_file
, "\t.cfi_startproc\n");
7566 /* Create a fake CFA 4 bytes below the stack pointer.
7567 This works around unwinders (like libgcc's) that expect
7568 the CFA for non-signal frames to be unique. */
7569 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
7571 /* "Save" $sp in itself so we don't use the fake CFA.
7572 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7573 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
7575 /* Save the return address in $18. The stub's caller knows
7576 that $18 might be clobbered, even though $18 is usually
7577 a call-saved register.
7579 Do it early on in case the last move to a floating-point
7580 register can be scheduled into the delay slot of the
7581 call we are about to make. */
7582 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
7583 reg_names
[GP_REG_FIRST
+ 18],
7584 reg_names
[RETURN_ADDR_REGNUM
]);
7588 /* Load the address of the MIPS16 function into $25. Do this
7589 first so that targets with coprocessor interlocks can use
7590 an MFC1 to fill the delay slot. */
7591 if (TARGET_EXPLICIT_RELOCS
)
7593 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
7594 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
7597 output_asm_insn ("la\t%^,%0", &fn
);
7600 /* Move the arguments from general registers to floating-point
7602 mips_output_args_xfer (fp_code
, 't');
7606 /* Now call the non-MIPS16 function. */
7607 output_asm_insn (mips_output_jump (&fn
, 0, -1, true), &fn
);
7608 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
7610 /* Move the result from floating-point registers to
7611 general registers. */
7612 switch (GET_MODE (retval
))
7615 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
7619 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
7620 TARGET_LITTLE_ENDIAN
7623 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
7625 /* On 64-bit targets, complex floats are returned in
7626 a single GPR, such that "sd" on a suitably-aligned
7627 target would store the value correctly. */
7628 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7629 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7630 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7631 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7632 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
7633 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
7634 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
7635 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7636 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7637 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
7638 reg_names
[GP_RETURN
],
7639 reg_names
[GP_RETURN
],
7640 reg_names
[GP_RETURN
+ 1]);
7645 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7649 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
7654 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7655 || GET_MODE (retval
) != V2SFmode
);
7656 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7662 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
7663 fprintf (asm_out_file
, "\t.cfi_endproc\n");
7667 /* Jump to the previously-loaded address. */
7668 output_asm_insn ("jr\t%^", NULL
);
7671 #ifdef ASM_DECLARE_FUNCTION_SIZE
7672 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7675 mips_end_function_definition (stubname
);
7677 /* Record this stub. */
7678 l
= XNEW (struct mips16_stub
);
7679 l
->name
= xstrdup (fnname
);
7680 l
->fp_ret_p
= fp_ret_p
;
7681 l
->next
= mips16_stubs
;
7685 /* If we expect a floating-point return value, but we've built a
7686 stub which does not expect one, then we're in trouble. We can't
7687 use the existing stub, because it won't handle the floating-point
7688 value. We can't build a new stub, because the linker won't know
7689 which stub to use for the various calls in this object file.
7690 Fortunately, this case is illegal, since it means that a function
7691 was declared in two different ways in a single compilation. */
7692 if (fp_ret_p
&& !l
->fp_ret_p
)
7693 error ("cannot handle inconsistent calls to %qs", fnname
);
7695 if (retval
== NULL_RTX
)
7696 pattern
= gen_call_internal_direct (fn
, args_size
);
7698 pattern
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7699 insn
= mips_emit_call_insn (pattern
, fn
, fn
, false);
7701 /* If we are calling a stub which handles a floating-point return
7702 value, we need to arrange to save $18 in the prologue. We do this
7703 by marking the function call as using the register. The prologue
7704 will later see that it is used, and emit code to save it. */
7706 CALL_INSN_FUNCTION_USAGE (insn
) =
7707 gen_rtx_EXPR_LIST (VOIDmode
,
7708 gen_rtx_CLOBBER (VOIDmode
,
7709 gen_rtx_REG (word_mode
, 18)),
7710 CALL_INSN_FUNCTION_USAGE (insn
));
7715 /* Expand a call of type TYPE. RESULT is where the result will go (null
7716 for "call"s and "sibcall"s), ADDR is the address of the function,
7717 ARGS_SIZE is the size of the arguments and AUX is the value passed
7718 to us by mips_function_arg. LAZY_P is true if this call already
7719 involves a lazily-bound function address (such as when calling
7720 functions through a MIPS16 hard-float stub).
7722 Return the call itself. */
7725 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7726 rtx args_size
, rtx aux
, bool lazy_p
)
7728 rtx orig_addr
, pattern
;
7732 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7733 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7736 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7741 if (!call_insn_operand (addr
, VOIDmode
))
7743 if (type
== MIPS_CALL_EPILOGUE
)
7744 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7746 addr
= gen_reg_rtx (Pmode
);
7747 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7752 rtx (*fn
) (rtx
, rtx
);
7754 if (type
== MIPS_CALL_SIBCALL
)
7755 fn
= gen_sibcall_internal
;
7757 fn
= gen_call_internal
;
7759 pattern
= fn (addr
, args_size
);
7761 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7763 /* Handle return values created by mips_return_fpr_pair. */
7764 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7767 if (type
== MIPS_CALL_SIBCALL
)
7768 fn
= gen_sibcall_value_multiple_internal
;
7770 fn
= gen_call_value_multiple_internal
;
7772 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7773 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7774 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7778 rtx (*fn
) (rtx
, rtx
, rtx
);
7780 if (type
== MIPS_CALL_SIBCALL
)
7781 fn
= gen_sibcall_value_internal
;
7783 fn
= gen_call_value_internal
;
7785 /* Handle return values created by mips_return_fpr_single. */
7786 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7787 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7788 pattern
= fn (result
, addr
, args_size
);
7791 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7794 /* Split call instruction INSN into a $gp-clobbering call and
7795 (where necessary) an instruction to restore $gp from its save slot.
7796 CALL_PATTERN is the pattern of the new call. */
7799 mips_split_call (rtx insn
, rtx call_pattern
)
7801 emit_call_insn (call_pattern
);
7802 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7803 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7804 POST_CALL_TMP_REG
));
7807 /* Return true if a call to DECL may need to use JALX. */
7810 mips_call_may_need_jalx_p (tree decl
)
7812 /* If the current translation unit would use a different mode for DECL,
7813 assume that the call needs JALX. */
7814 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7817 /* mips_get_compress_mode is always accurate for locally-binding
7818 functions in the current translation unit. */
7819 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7822 /* When -minterlink-compressed is in effect, assume that functions
7823 could use a different encoding mode unless an attribute explicitly
7824 tells us otherwise. */
7825 if (TARGET_INTERLINK_COMPRESSED
)
7827 if (!TARGET_COMPRESSION
7828 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7830 if (TARGET_COMPRESSION
7831 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7838 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7841 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7843 if (!TARGET_SIBCALLS
)
7846 /* Interrupt handlers need special epilogue code and therefore can't
7848 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7851 /* Direct Js are only possible to functions that use the same ISA encoding.
7852 There is no JX counterpoart of JALX. */
7854 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7855 && mips_call_may_need_jalx_p (decl
))
7858 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7859 require $gp to be valid on entry, so sibcalls can only use stubs
7860 if $gp is call-clobbered. */
7862 && TARGET_CALL_SAVED_GP
7863 && !TARGET_ABICALLS_PIC0
7864 && !targetm
.binds_local_p (decl
))
7871 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7874 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
7876 enum by_pieces_operation op
,
7879 if (op
== STORE_BY_PIECES
)
7880 return mips_store_by_pieces_p (size
, align
);
7881 if (op
== MOVE_BY_PIECES
&& HAVE_movmemsi
)
7883 /* movmemsi is meant to generate code that is at least as good as
7884 move_by_pieces. However, movmemsi effectively uses a by-pieces
7885 implementation both for moves smaller than a word and for
7886 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7887 bytes. We should allow the tree-level optimisers to do such
7888 moves by pieces, as it often exposes other optimization
7889 opportunities. We might as well continue to use movmemsi at
7890 the rtl level though, as it produces better code when
7891 scheduling is disabled (such as at -O). */
7892 if (currently_expanding_to_rtl
)
7894 if (align
< BITS_PER_WORD
)
7895 return size
< UNITS_PER_WORD
;
7896 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7899 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
7902 /* Implement a handler for STORE_BY_PIECES operations
7903 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7906 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7908 /* Storing by pieces involves moving constants into registers
7909 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7910 We need to decide whether it is cheaper to load the address of
7911 constant data into a register and use a block move instead. */
7913 /* If the data is only byte aligned, then:
7915 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7916 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7919 (a2) A block move of 4 bytes from aligned source data can use an
7920 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7921 4 SBs that we would generate when storing by pieces. */
7922 if (align
<= BITS_PER_UNIT
)
7925 /* If the data is 2-byte aligned, then:
7927 (b1) A block move of less than 4 bytes would use a combination of LBs,
7928 LHs, SBs and SHs. We get better code by using single-instruction
7929 LIs, SBs and SHs instead.
7931 (b2) A block move of 4 bytes from aligned source data would again use
7932 an LW/SWL/SWR sequence. In most cases, loading the address of
7933 the source data would require at least one extra instruction.
7934 It is often more efficient to use 2 single-instruction LIs and
7937 (b3) A block move of up to 3 additional bytes would be like (b1).
7939 (b4) A block move of 8 bytes from aligned source data can use two
7940 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7941 sequences are better than the 4 LIs and 4 SHs that we'd generate
7942 when storing by pieces.
7944 The reasoning for higher alignments is similar:
7946 (c1) A block move of less than 4 bytes would be the same as (b1).
7948 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7949 loading the address of the source data would typically require
7950 at least one extra instruction. It is generally better to use
7953 (c3) A block move of up to 3 additional bytes would be like (b1).
7955 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7956 LD/SD sequence, and in these cases we've traditionally preferred
7957 the memory copy over the more bulky constant moves. */
7961 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7962 Assume that the areas do not overlap. */
7965 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7967 HOST_WIDE_INT offset
, delta
;
7968 unsigned HOST_WIDE_INT bits
;
7973 /* Work out how many bits to move at a time. If both operands have
7974 half-word alignment, it is usually better to move in half words.
7975 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7976 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7977 Otherwise move word-sized chunks.
7979 For ISA_HAS_LWL_LWR we rely on the lwl/lwr & swl/swr load. Otherwise
7980 picking the minimum of alignment or BITS_PER_WORD gets us the
7981 desired size for bits. */
7983 if (!ISA_HAS_LWL_LWR
)
7984 bits
= MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)));
7987 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7988 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7989 bits
= BITS_PER_WORD
/ 2;
7991 bits
= BITS_PER_WORD
;
7994 mode
= mode_for_size (bits
, MODE_INT
, 0);
7995 delta
= bits
/ BITS_PER_UNIT
;
7997 /* Allocate a buffer for the temporary registers. */
7998 regs
= XALLOCAVEC (rtx
, length
/ delta
);
8000 /* Load as many BITS-sized chunks as possible. Use a normal load if
8001 the source has enough alignment, otherwise use left/right pairs. */
8002 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
8004 regs
[i
] = gen_reg_rtx (mode
);
8005 if (MEM_ALIGN (src
) >= bits
)
8006 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
8009 rtx part
= adjust_address (src
, BLKmode
, offset
);
8010 set_mem_size (part
, delta
);
8011 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
8016 /* Copy the chunks to the destination. */
8017 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
8018 if (MEM_ALIGN (dest
) >= bits
)
8019 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
8022 rtx part
= adjust_address (dest
, BLKmode
, offset
);
8023 set_mem_size (part
, delta
);
8024 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
8028 /* Mop up any left-over bytes. */
8029 if (offset
< length
)
8031 src
= adjust_address (src
, BLKmode
, offset
);
8032 dest
= adjust_address (dest
, BLKmode
, offset
);
8033 move_by_pieces (dest
, src
, length
- offset
,
8034 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
8038 /* Helper function for doing a loop-based block operation on memory
8039 reference MEM. Each iteration of the loop will operate on LENGTH
8042 Create a new base register for use within the loop and point it to
8043 the start of MEM. Create a new memory reference that uses this
8044 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
8047 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
8048 rtx
*loop_reg
, rtx
*loop_mem
)
8050 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
8052 /* Although the new mem does not refer to a known location,
8053 it does keep up to LENGTH bytes of alignment. */
8054 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
8055 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
8058 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
8059 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
8060 the memory regions do not overlap. */
8063 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
8064 HOST_WIDE_INT bytes_per_iter
)
8066 rtx_code_label
*label
;
8067 rtx src_reg
, dest_reg
, final_src
, test
;
8068 HOST_WIDE_INT leftover
;
8070 leftover
= length
% bytes_per_iter
;
8073 /* Create registers and memory references for use within the loop. */
8074 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
8075 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
8077 /* Calculate the value that SRC_REG should have after the last iteration
8079 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
8082 /* Emit the start of the loop. */
8083 label
= gen_label_rtx ();
8086 /* Emit the loop body. */
8087 mips_block_move_straight (dest
, src
, bytes_per_iter
);
8089 /* Move on to the next block. */
8090 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
8091 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
8093 /* Emit the loop condition. */
8094 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
8095 if (Pmode
== DImode
)
8096 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
8098 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
8100 /* Mop up any left-over bytes. */
8102 mips_block_move_straight (dest
, src
, leftover
);
8104 /* Temporary fix for PR79150. */
8105 emit_insn (gen_nop ());
8108 /* Expand a movmemsi instruction, which copies LENGTH bytes from
8109 memory reference SRC to memory reference DEST. */
8112 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
8114 if (!ISA_HAS_LWL_LWR
8115 && (MEM_ALIGN (src
) < MIPS_MIN_MOVE_MEM_ALIGN
8116 || MEM_ALIGN (dest
) < MIPS_MIN_MOVE_MEM_ALIGN
))
8119 if (CONST_INT_P (length
))
8121 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
8123 mips_block_move_straight (dest
, src
, INTVAL (length
));
8128 mips_block_move_loop (dest
, src
, INTVAL (length
),
8129 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
8136 /* Expand a loop of synci insns for the address range [BEGIN, END). */
8139 mips_expand_synci_loop (rtx begin
, rtx end
)
8141 rtx inc
, cmp_result
, mask
, length
;
8142 rtx_code_label
*label
, *end_label
;
8144 /* Create end_label. */
8145 end_label
= gen_label_rtx ();
8147 /* Check if begin equals end. */
8148 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
8149 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
8151 /* Load INC with the cache line size (rdhwr INC,$1). */
8152 inc
= gen_reg_rtx (Pmode
);
8153 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
8155 /* Check if inc is 0. */
8156 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
8157 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
8159 /* Calculate mask. */
8160 mask
= mips_force_unary (Pmode
, NEG
, inc
);
8162 /* Mask out begin by mask. */
8163 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
8165 /* Calculate length. */
8166 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
8168 /* Loop back to here. */
8169 label
= gen_label_rtx ();
8172 emit_insn (gen_synci (begin
));
8174 /* Update length. */
8175 mips_emit_binary (MINUS
, length
, length
, inc
);
8178 mips_emit_binary (PLUS
, begin
, begin
, inc
);
8180 /* Check if length is greater than 0. */
8181 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
8182 emit_jump_insn (gen_condjump (cmp_result
, label
));
8184 emit_label (end_label
);
8187 /* Expand a QI or HI mode atomic memory operation.
8189 GENERATOR contains a pointer to the gen_* function that generates
8190 the SI mode underlying atomic operation using masks that we
8193 RESULT is the return register for the operation. Its value is NULL
8196 MEM is the location of the atomic access.
8198 OLDVAL is the first operand for the operation.
8200 NEWVAL is the optional second operand for the operation. Its value
8201 is NULL if unused. */
8204 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
8205 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
8207 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
8208 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
8212 mode
= GET_MODE (mem
);
8214 /* Compute the address of the containing SImode value. */
8215 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
8216 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
8217 force_reg (Pmode
, GEN_INT (-4)));
8219 /* Create a memory reference for it. */
8220 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
8221 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
8222 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
8224 /* Work out the byte offset of the QImode or HImode value,
8225 counting from the least significant byte. */
8226 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
8227 if (TARGET_BIG_ENDIAN
)
8228 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
8230 /* Multiply by eight to convert the shift value from bytes to bits. */
8231 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
8233 /* Make the final shift an SImode value, so that it can be used in
8234 SImode operations. */
8235 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
8237 /* Set MASK to an inclusive mask of the QImode or HImode value. */
8238 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
8239 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
8240 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
8242 /* Compute the equivalent exclusive mask. */
8243 inverted_mask
= gen_reg_rtx (SImode
);
8244 emit_insn (gen_rtx_SET (inverted_mask
, gen_rtx_NOT (SImode
, mask
)));
8246 /* Shift the old value into place. */
8247 if (oldval
!= const0_rtx
)
8249 oldval
= convert_modes (SImode
, mode
, oldval
, true);
8250 oldval
= force_reg (SImode
, oldval
);
8251 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
8254 /* Do the same for the new value. */
8255 if (newval
&& newval
!= const0_rtx
)
8257 newval
= convert_modes (SImode
, mode
, newval
, true);
8258 newval
= force_reg (SImode
, newval
);
8259 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
8262 /* Do the SImode atomic access. */
8264 res
= gen_reg_rtx (SImode
);
8266 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
8268 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
8270 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
8276 /* Shift and convert the result. */
8277 mips_emit_binary (AND
, res
, res
, mask
);
8278 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
8279 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
8283 /* Return true if it is possible to use left/right accesses for a
8284 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
8285 When returning true, update *LEFT and *RIGHT as follows:
8287 *LEFT is a QImode reference to the first byte if big endian or
8288 the last byte if little endian. This address can be used in the
8289 left-side instructions (LWL, SWL, LDL, SDL).
8291 *RIGHT is a QImode reference to the opposite end of the field and
8292 can be used in the patterning right-side instruction. */
8295 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
8296 rtx
*left
, rtx
*right
)
8300 /* Check that the size is valid. */
8301 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
8304 /* We can only access byte-aligned values. Since we are always passed
8305 a reference to the first byte of the field, it is not necessary to
8306 do anything with BITPOS after this check. */
8307 if (bitpos
% BITS_PER_UNIT
!= 0)
8310 /* Reject aligned bitfields: we want to use a normal load or store
8311 instead of a left/right pair. */
8312 if (MEM_ALIGN (op
) >= width
)
8315 /* Get references to both ends of the field. */
8316 first
= adjust_address (op
, QImode
, 0);
8317 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
8319 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
8320 correspond to the MSB and RIGHT to the LSB. */
8321 if (TARGET_BIG_ENDIAN
)
8322 *left
= first
, *right
= last
;
8324 *left
= last
, *right
= first
;
8329 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
8330 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
8331 the operation is the equivalent of:
8333 (set DEST (*_extract SRC WIDTH BITPOS))
8335 Return true on success. */
8338 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
8339 HOST_WIDE_INT bitpos
, bool unsigned_p
)
8341 rtx left
, right
, temp
;
8342 rtx dest1
= NULL_RTX
;
8344 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
8345 be a DImode, create a new temp and emit a zero extend at the end. */
8346 if (GET_MODE (dest
) == DImode
8348 && GET_MODE_BITSIZE (SImode
) == width
)
8351 dest
= gen_reg_rtx (SImode
);
8354 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
8357 temp
= gen_reg_rtx (GET_MODE (dest
));
8358 if (GET_MODE (dest
) == DImode
)
8360 emit_insn (gen_mov_ldl (temp
, src
, left
));
8361 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
8365 emit_insn (gen_mov_lwl (temp
, src
, left
));
8366 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
8369 /* If we were loading 32bits and the original register was DI then
8370 sign/zero extend into the orignal dest. */
8374 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
8376 emit_insn (gen_extendsidi2 (dest1
, dest
));
8381 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
8382 BITPOS and SRC are the operands passed to the expander; the operation
8383 is the equivalent of:
8385 (set (zero_extract DEST WIDTH BITPOS) SRC)
8387 Return true on success. */
8390 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
8391 HOST_WIDE_INT bitpos
)
8396 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
8399 mode
= mode_for_size (width
, MODE_INT
, 0);
8400 src
= gen_lowpart (mode
, src
);
8403 emit_insn (gen_mov_sdl (dest
, src
, left
));
8404 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
8408 emit_insn (gen_mov_swl (dest
, src
, left
));
8409 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
8414 /* Return true if X is a MEM with the same size as MODE. */
8417 mips_mem_fits_mode_p (machine_mode mode
, rtx x
)
8420 && MEM_SIZE_KNOWN_P (x
)
8421 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
8424 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
8425 source of an "ext" instruction or the destination of an "ins"
8426 instruction. OP must be a register operand and the following
8427 conditions must hold:
8429 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
8430 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8431 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8433 Also reject lengths equal to a word as they are better handled
8434 by the move patterns. */
8437 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
8439 if (!ISA_HAS_EXT_INS
8440 || !register_operand (op
, VOIDmode
)
8441 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
8444 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
8447 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
8453 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
8454 operation if MAXLEN is the maxium length of consecutive bits that
8455 can make up MASK. MODE is the mode of the operation. See
8456 mask_low_and_shift_len for the actual definition. */
8459 mask_low_and_shift_p (machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
8461 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
8464 /* Return true iff OP1 and OP2 are valid operands together for the
8465 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
8466 see the table in the comment before the pattern. */
8469 and_operands_ok (machine_mode mode
, rtx op1
, rtx op2
)
8472 if (memory_operand (op1
, mode
))
8474 if (TARGET_MIPS16
) {
8475 struct mips_address_info addr
;
8476 if (!mips_classify_address (&addr
, op1
, mode
, false))
8479 return and_load_operand (op2
, mode
);
8482 return and_reg_operand (op2
, mode
);
8485 /* The canonical form of a mask-low-and-shift-left operation is
8486 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
8487 cleared. Thus we need to shift MASK to the right before checking if it
8488 is a valid mask value. MODE is the mode of the operation. If true
8489 return the length of the mask, otherwise return -1. */
8492 mask_low_and_shift_len (machine_mode mode
, rtx mask
, rtx shift
)
8494 HOST_WIDE_INT shval
;
8496 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
8497 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
8500 /* Return true if -msplit-addresses is selected and should be honored.
8502 -msplit-addresses is a half-way house between explicit relocations
8503 and the traditional assembler macros. It can split absolute 32-bit
8504 symbolic constants into a high/lo_sum pair but uses macros for other
8507 Like explicit relocation support for REL targets, it relies
8508 on GNU extensions in the assembler and the linker.
8510 Although this code should work for -O0, it has traditionally
8511 been treated as an optimization. */
8514 mips_split_addresses_p (void)
8516 return (TARGET_SPLIT_ADDRESSES
8520 && !ABI_HAS_64BIT_SYMBOLS
);
8523 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
8526 mips_init_relocs (void)
8528 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
8529 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
8530 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
8531 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
8532 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
8534 if (TARGET_MIPS16_PCREL_LOADS
)
8535 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
8538 if (ABI_HAS_64BIT_SYMBOLS
)
8540 if (TARGET_EXPLICIT_RELOCS
)
8542 mips_split_p
[SYMBOL_64_HIGH
] = true;
8543 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
8544 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
8546 mips_split_p
[SYMBOL_64_MID
] = true;
8547 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
8548 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
8550 mips_split_p
[SYMBOL_64_LOW
] = true;
8551 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
8552 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
8554 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8555 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8560 if (TARGET_EXPLICIT_RELOCS
8561 || mips_split_addresses_p ()
8564 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8565 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
8566 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8573 /* The high part is provided by a pseudo copy of $gp. */
8574 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
8575 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
8577 else if (TARGET_EXPLICIT_RELOCS
)
8578 /* Small data constants are kept whole until after reload,
8579 then lowered by mips_rewrite_small_data. */
8580 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
8582 if (TARGET_EXPLICIT_RELOCS
)
8584 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8587 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
8588 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
8592 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
8593 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
8596 /* Expose the use of $28 as soon as possible. */
8597 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8601 /* The HIGH and LO_SUM are matched by special .md patterns. */
8602 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8604 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
8605 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
8606 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
8608 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
8609 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
8610 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
8615 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
8617 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
8618 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
8620 /* Expose the use of $28 as soon as possible. */
8621 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8627 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
8628 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
8629 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
8632 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
8633 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
8635 if (TARGET_MIPS16_PCREL_LOADS
)
8637 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
8638 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
8642 mips_split_p
[SYMBOL_DTPREL
] = true;
8643 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
8644 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
8646 mips_split_p
[SYMBOL_TPREL
] = true;
8647 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
8648 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
8651 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
8652 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
8655 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8656 in context CONTEXT. RELOCS is the array of relocations to use. */
8659 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
8660 const char **relocs
)
8662 enum mips_symbol_type symbol_type
;
8665 symbol_type
= mips_classify_symbolic_expression (op
, context
);
8666 gcc_assert (relocs
[symbol_type
]);
8668 fputs (relocs
[symbol_type
], file
);
8669 output_addr_const (file
, mips_strip_unspec_address (op
));
8670 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
8675 /* Start a new block with the given asm switch enabled. If we need
8676 to print a directive, emit PREFIX before it and SUFFIX after it. */
8679 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8680 const char *prefix
, const char *suffix
)
8682 if (asm_switch
->nesting_level
== 0)
8683 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
8684 asm_switch
->nesting_level
++;
8687 /* Likewise, but end a block. */
8690 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8691 const char *prefix
, const char *suffix
)
8693 gcc_assert (asm_switch
->nesting_level
);
8694 asm_switch
->nesting_level
--;
8695 if (asm_switch
->nesting_level
== 0)
8696 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
8699 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8700 that either print a complete line or print nothing. */
8703 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8705 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8709 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8711 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8714 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8715 The punctuation characters are:
8717 '(' Start a nested ".set noreorder" block.
8718 ')' End a nested ".set noreorder" block.
8719 '[' Start a nested ".set noat" block.
8720 ']' End a nested ".set noat" block.
8721 '<' Start a nested ".set nomacro" block.
8722 '>' End a nested ".set nomacro" block.
8723 '*' Behave like %(%< if generating a delayed-branch sequence.
8724 '#' Print a nop if in a ".set noreorder" block.
8725 '/' Like '#', but do nothing within a delayed-branch sequence.
8726 '?' Print "l" if mips_branch_likely is true
8727 '~' Print a nop if mips_branch_likely is true
8728 '.' Print the name of the register with a hard-wired zero (zero or $0).
8729 '@' Print the name of the assembler temporary register (at or $1).
8730 '^' Print the name of the pic call-through register (t9 or $25).
8731 '+' Print the name of the gp register (usually gp or $28).
8732 '$' Print the name of the stack pointer register (sp or $29).
8733 ':' Print "c" to use the compact version if the delay slot is a nop.
8734 '!' Print "s" to use the short version if the delay slot contains a
8737 See also mips_init_print_operand_punct. */
8740 mips_print_operand_punctuation (FILE *file
, int ch
)
8745 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8749 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8753 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8757 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8761 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8765 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8769 if (final_sequence
!= 0)
8771 mips_print_operand_punctuation (file
, '(');
8772 mips_print_operand_punctuation (file
, '<');
8777 if (mips_noreorder
.nesting_level
> 0)
8778 fputs ("\n\tnop", file
);
8782 /* Print an extra newline so that the delayed insn is separated
8783 from the following ones. This looks neater and is consistent
8784 with non-nop delayed sequences. */
8785 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8786 fputs ("\n\tnop\n", file
);
8790 if (mips_branch_likely
)
8795 if (mips_branch_likely
)
8796 fputs ("\n\tnop", file
);
8800 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8804 fputs (reg_names
[AT_REGNUM
], file
);
8808 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8812 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8816 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8820 /* When final_sequence is 0, the delay slot will be a nop. We can
8821 use the compact version where available. The %: formatter will
8822 only be present if a compact form of the branch is available. */
8823 if (final_sequence
== 0)
8828 /* If the delay slot instruction is short, then use the
8830 if (TARGET_MICROMIPS
&& !TARGET_INTERLINK_COMPRESSED
&& mips_isa_rev
<= 5
8831 && (final_sequence
== 0
8832 || get_attr_length (final_sequence
->insn (1)) == 2))
8842 /* Initialize mips_print_operand_punct. */
8845 mips_init_print_operand_punct (void)
8849 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8850 mips_print_operand_punct
[(unsigned char) *p
] = true;
8853 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8854 associated with condition CODE. Print the condition part of the
8858 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8872 /* Conveniently, the MIPS names for these conditions are the same
8873 as their RTL equivalents. */
8874 fputs (GET_RTX_NAME (code
), file
);
8878 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8883 /* Likewise floating-point branches. */
8886 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8892 fputs ("c1eqz", file
);
8894 fputs ("c1f", file
);
8899 fputs ("c1nez", file
);
8901 fputs ("c1t", file
);
8905 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8910 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8913 mips_print_operand_punct_valid_p (unsigned char code
)
8915 return mips_print_operand_punct
[code
];
8918 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8920 'E' Print CONST_INT OP element 0 of a replicated CONST_VECTOR in decimal.
8921 'X' Print CONST_INT OP in hexadecimal format.
8922 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8923 'd' Print CONST_INT OP in decimal.
8924 'B' Print CONST_INT OP element 0 of a replicated CONST_VECTOR
8925 as an unsigned byte [0..255].
8926 'm' Print one less than CONST_INT OP in decimal.
8927 'y' Print exact log2 of CONST_INT OP in decimal.
8928 'h' Print the high-part relocation associated with OP, after stripping
8930 'R' Print the low-part relocation associated with OP.
8931 'C' Print the integer branch condition for comparison OP.
8932 'N' Print the inverse of the integer branch condition for comparison OP.
8933 'F' Print the FPU branch condition for comparison OP.
8934 'W' Print the inverse of the FPU branch condition for comparison OP.
8935 'w' Print a MSA register.
8936 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8937 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8938 't' Like 'T', but with the EQ/NE cases reversed
8939 'Y' Print mips_fp_conditions[INTVAL (OP)]
8940 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8941 'q' Print a DSP accumulator register.
8942 'D' Print the second part of a double-word register or memory operand.
8943 'L' Print the low-order register in a double-word register operand.
8944 'M' Print high-order register in a double-word register operand.
8945 'z' Print $0 if OP is zero, otherwise print OP normally.
8946 'b' Print the address of a memory operand, without offset.
8947 'v' Print the insn size suffix b, h, w or d for vector modes V16QI, V8HI,
8948 V4SI, V2SI, and w, d for vector modes V4SF, V2DF respectively.
8949 'V' Print exact log2 of CONST_INT OP element 0 of a replicated
8950 CONST_VECTOR in decimal. */
8953 mips_print_operand (FILE *file
, rtx op
, int letter
)
8957 if (mips_print_operand_punct_valid_p (letter
))
8959 mips_print_operand_punctuation (file
, letter
);
8964 code
= GET_CODE (op
);
8969 if (GET_CODE (op
) == CONST_VECTOR
)
8971 gcc_assert (mips_const_vector_same_val_p (op
, GET_MODE (op
)));
8972 op
= CONST_VECTOR_ELT (op
, 0);
8973 gcc_assert (CONST_INT_P (op
));
8974 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8977 output_operand_lossage ("invalid use of '%%%c'", letter
);
8981 if (CONST_INT_P (op
))
8982 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8984 output_operand_lossage ("invalid use of '%%%c'", letter
);
8988 if (CONST_INT_P (op
))
8989 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8991 output_operand_lossage ("invalid use of '%%%c'", letter
);
8995 if (CONST_INT_P (op
))
8996 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8998 output_operand_lossage ("invalid use of '%%%c'", letter
);
9002 if (GET_CODE (op
) == CONST_VECTOR
)
9004 gcc_assert (mips_const_vector_same_val_p (op
, GET_MODE (op
)));
9005 op
= CONST_VECTOR_ELT (op
, 0);
9006 gcc_assert (CONST_INT_P (op
));
9007 unsigned HOST_WIDE_INT val8
= UINTVAL (op
) & GET_MODE_MASK (QImode
);
9008 fprintf (file
, HOST_WIDE_INT_PRINT_UNSIGNED
, val8
);
9011 output_operand_lossage ("invalid use of '%%%c'", letter
);
9015 if (CONST_INT_P (op
))
9016 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
9018 output_operand_lossage ("invalid use of '%%%c'", letter
);
9022 if (CONST_INT_P (op
))
9024 int val
= exact_log2 (INTVAL (op
));
9026 fprintf (file
, "%d", val
);
9028 output_operand_lossage ("invalid use of '%%%c'", letter
);
9031 output_operand_lossage ("invalid use of '%%%c'", letter
);
9035 if (GET_CODE (op
) == CONST_VECTOR
)
9037 machine_mode mode
= GET_MODE_INNER (GET_MODE (op
));
9038 unsigned HOST_WIDE_INT val
= UINTVAL (CONST_VECTOR_ELT (op
, 0));
9039 int vlog2
= exact_log2 (val
& GET_MODE_MASK (mode
));
9041 fprintf (file
, "%d", vlog2
);
9043 output_operand_lossage ("invalid use of '%%%c'", letter
);
9046 output_operand_lossage ("invalid use of '%%%c'", letter
);
9052 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
9056 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
9060 mips_print_int_branch_condition (file
, code
, letter
);
9064 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
9068 mips_print_float_branch_condition (file
, code
, letter
);
9072 mips_print_float_branch_condition (file
, reverse_condition (code
),
9079 int truth
= (code
== NE
) == (letter
== 'T');
9080 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
9085 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
9086 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
9088 output_operand_lossage ("'%%%c' is not a valid operand prefix",
9093 if (ISA_HAS_8CC
|| ISA_HAS_CCF
)
9095 mips_print_operand (file
, op
, 0);
9101 if (code
== REG
&& MD_REG_P (REGNO (op
)))
9102 fprintf (file
, "$ac0");
9103 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
9104 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
9106 output_operand_lossage ("invalid use of '%%%c'", letter
);
9110 if (code
== REG
&& MSA_REG_P (REGNO (op
)))
9111 fprintf (file
, "$w%s", ®_names
[REGNO (op
)][2]);
9113 output_operand_lossage ("invalid use of '%%%c'", letter
);
9117 switch (GET_MODE (op
))
9120 fprintf (file
, "b");
9123 fprintf (file
, "h");
9127 fprintf (file
, "w");
9131 fprintf (file
, "d");
9134 output_operand_lossage ("invalid use of '%%%c'", letter
);
9143 unsigned int regno
= REGNO (op
);
9144 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
9145 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
9148 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
9149 output_operand_lossage ("invalid use of '%%%c'", letter
);
9150 /* We need to print $0 .. $31 for COP0 registers. */
9151 if (COP0_REG_P (regno
))
9152 fprintf (file
, "$%s", ®_names
[regno
][4]);
9154 fprintf (file
, "%s", reg_names
[regno
]);
9160 output_address (GET_MODE (op
), plus_constant (Pmode
,
9162 else if (letter
== 'b')
9164 gcc_assert (REG_P (XEXP (op
, 0)));
9165 mips_print_operand (file
, XEXP (op
, 0), 0);
9167 else if (letter
&& letter
!= 'z')
9168 output_operand_lossage ("invalid use of '%%%c'", letter
);
9170 output_address (GET_MODE (op
), XEXP (op
, 0));
9174 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
9175 fputs (reg_names
[GP_REG_FIRST
], file
);
9176 else if (letter
&& letter
!= 'z')
9177 output_operand_lossage ("invalid use of '%%%c'", letter
);
9178 else if (CONST_GP_P (op
))
9179 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
9181 output_addr_const (file
, mips_strip_unspec_address (op
));
9187 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9190 mips_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9192 struct mips_address_info addr
;
9194 if (mips_classify_address (&addr
, x
, word_mode
, true))
9198 mips_print_operand (file
, addr
.offset
, 0);
9199 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
9202 case ADDRESS_LO_SUM
:
9203 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
9205 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
9208 case ADDRESS_CONST_INT
:
9209 output_addr_const (file
, x
);
9210 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
9213 case ADDRESS_SYMBOLIC
:
9214 output_addr_const (file
, mips_strip_unspec_address (x
));
9220 /* Implement TARGET_ENCODE_SECTION_INFO. */
9223 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
9225 default_encode_section_info (decl
, rtl
, first
);
9227 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9229 rtx symbol
= XEXP (rtl
, 0);
9230 tree type
= TREE_TYPE (decl
);
9232 /* Encode whether the symbol is short or long. */
9233 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
9234 || mips_far_type_p (type
))
9235 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
9239 /* Implement TARGET_SELECT_RTX_SECTION. */
9242 mips_select_rtx_section (machine_mode mode
, rtx x
,
9243 unsigned HOST_WIDE_INT align
)
9245 /* ??? Consider using mergeable small data sections. */
9246 if (mips_rtx_constant_in_small_data_p (mode
))
9247 return get_named_section (NULL
, ".sdata", 0);
9249 return default_elf_select_rtx_section (mode
, x
, align
);
9252 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
9254 The complication here is that, with the combination TARGET_ABICALLS
9255 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
9256 absolute addresses, and should therefore not be included in the
9257 read-only part of a DSO. Handle such cases by selecting a normal
9258 data section instead of a read-only one. The logic apes that in
9259 default_function_rodata_section. */
9262 mips_function_rodata_section (tree decl
)
9264 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
9265 return default_function_rodata_section (decl
);
9267 if (decl
&& DECL_SECTION_NAME (decl
))
9269 const char *name
= DECL_SECTION_NAME (decl
);
9270 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
9272 char *rname
= ASTRDUP (name
);
9274 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
9276 else if (flag_function_sections
9277 && flag_data_sections
9278 && strncmp (name
, ".text.", 6) == 0)
9280 char *rname
= ASTRDUP (name
);
9281 memcpy (rname
+ 1, "data", 4);
9282 return get_section (rname
, SECTION_WRITE
, decl
);
9285 return data_section
;
9288 /* Implement TARGET_IN_SMALL_DATA_P. */
9291 mips_in_small_data_p (const_tree decl
)
9293 unsigned HOST_WIDE_INT size
;
9295 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
9298 /* We don't yet generate small-data references for -mabicalls
9299 or VxWorks RTP code. See the related -G handling in
9300 mips_option_override. */
9301 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
9304 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
9308 /* Reject anything that isn't in a known small-data section. */
9309 name
= DECL_SECTION_NAME (decl
);
9310 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
9313 /* If a symbol is defined externally, the assembler will use the
9314 usual -G rules when deciding how to implement macros. */
9315 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
9318 else if (TARGET_EMBEDDED_DATA
)
9320 /* Don't put constants into the small data section: we want them
9321 to be in ROM rather than RAM. */
9322 if (TREE_CODE (decl
) != VAR_DECL
)
9325 if (TREE_READONLY (decl
)
9326 && !TREE_SIDE_EFFECTS (decl
)
9327 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
9331 /* Enforce -mlocal-sdata. */
9332 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
9335 /* Enforce -mextern-sdata. */
9336 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
9338 if (DECL_EXTERNAL (decl
))
9340 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
9344 /* We have traditionally not treated zero-sized objects as small data,
9345 so this is now effectively part of the ABI. */
9346 size
= int_size_in_bytes (TREE_TYPE (decl
));
9347 return size
> 0 && size
<= mips_small_data_threshold
;
9350 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
9351 anchors for small data: the GP register acts as an anchor in that
9352 case. We also don't want to use them for PC-relative accesses,
9353 where the PC acts as an anchor. */
9356 mips_use_anchors_for_symbol_p (const_rtx symbol
)
9358 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
9360 case SYMBOL_PC_RELATIVE
:
9361 case SYMBOL_GP_RELATIVE
:
9365 return default_use_anchors_for_symbol_p (symbol
);
9369 /* The MIPS debug format wants all automatic variables and arguments
9370 to be in terms of the virtual frame pointer (stack pointer before
9371 any adjustment in the function), while the MIPS 3.0 linker wants
9372 the frame pointer to be the stack pointer after the initial
9373 adjustment. So, we do the adjustment here. The arg pointer (which
9374 is eliminated) points to the virtual frame pointer, while the frame
9375 pointer (which may be eliminated) points to the stack pointer after
9376 the initial adjustments. */
9379 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
9381 rtx offset2
= const0_rtx
;
9382 rtx reg
= eliminate_constant_term (addr
, &offset2
);
9385 offset
= INTVAL (offset2
);
9387 if (reg
== stack_pointer_rtx
9388 || reg
== frame_pointer_rtx
9389 || reg
== hard_frame_pointer_rtx
)
9391 offset
-= cfun
->machine
->frame
.total_size
;
9392 if (reg
== hard_frame_pointer_rtx
)
9393 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9399 /* Implement ASM_OUTPUT_EXTERNAL. */
9402 mips_output_external (FILE *file
, tree decl
, const char *name
)
9404 default_elf_asm_output_external (file
, decl
, name
);
9406 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9407 set in order to avoid putting out names that are never really
9409 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
9411 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
9413 /* When using assembler macros, emit .extern directives for
9414 all small-data externs so that the assembler knows how
9417 In most cases it would be safe (though pointless) to emit
9418 .externs for other symbols too. One exception is when an
9419 object is within the -G limit but declared by the user to
9420 be in a section other than .sbss or .sdata. */
9421 fputs ("\t.extern\t", file
);
9422 assemble_name (file
, name
);
9423 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
9424 int_size_in_bytes (TREE_TYPE (decl
)));
9429 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
9432 mips_output_filename (FILE *stream
, const char *name
)
9434 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
9436 if (write_symbols
== DWARF2_DEBUG
)
9438 else if (mips_output_filename_first_time
)
9440 mips_output_filename_first_time
= 0;
9441 num_source_filenames
+= 1;
9442 current_function_file
= name
;
9443 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
9444 output_quoted_string (stream
, name
);
9445 putc ('\n', stream
);
9447 /* If we are emitting stabs, let dbxout.c handle this (except for
9448 the mips_output_filename_first_time case). */
9449 else if (write_symbols
== DBX_DEBUG
)
9451 else if (name
!= current_function_file
9452 && strcmp (name
, current_function_file
) != 0)
9454 num_source_filenames
+= 1;
9455 current_function_file
= name
;
9456 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
9457 output_quoted_string (stream
, name
);
9458 putc ('\n', stream
);
9462 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
9464 static void ATTRIBUTE_UNUSED
9465 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9470 fputs ("\t.dtprelword\t", file
);
9474 fputs ("\t.dtpreldword\t", file
);
9480 output_addr_const (file
, x
);
9481 fputs ("+0x8000", file
);
9484 /* Implement TARGET_DWARF_REGISTER_SPAN. */
9487 mips_dwarf_register_span (rtx reg
)
9492 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
9493 ensures that double-precision registers are treated as if they were
9494 64-bit physical registers. The code will run correctly with 32-bit or
9495 64-bit registers which means that dwarf information cannot be precise
9496 for all scenarios. We choose to state that the 64-bit values are stored
9497 in a single 64-bit 'piece'. This slightly unusual construct can then be
9498 interpreted as either a pair of registers if the registers are 32-bit or
9499 a single 64-bit register depending on hardware. */
9500 mode
= GET_MODE (reg
);
9501 if (FP_REG_P (REGNO (reg
))
9503 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
9505 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, reg
));
9507 /* By default, GCC maps increasing register numbers to increasing
9508 memory locations, but paired FPRs are always little-endian,
9509 regardless of the prevailing endianness. */
9510 else if (FP_REG_P (REGNO (reg
))
9511 && TARGET_BIG_ENDIAN
9512 && MAX_FPRS_PER_FMT
> 1
9513 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
9515 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
9516 high
= mips_subword (reg
, true);
9517 low
= mips_subword (reg
, false);
9518 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
9524 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
9527 mips_dwarf_frame_reg_mode (int regno
)
9529 machine_mode mode
= default_dwarf_frame_reg_mode (regno
);
9531 if (FP_REG_P (regno
) && mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9537 /* DSP ALU can bypass data with no delays for the following pairs. */
9538 enum insn_code dspalu_bypass_table
[][2] =
9540 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
9541 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
9542 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
9543 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
9544 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
9545 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
9546 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
9547 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
9551 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
9554 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
9555 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
9556 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
9558 for (i
= 0; i
< num_bypass
; i
++)
9560 if (out_icode
== dspalu_bypass_table
[i
][0]
9561 && in_icode
== dspalu_bypass_table
[i
][1])
9567 /* Implement ASM_OUTPUT_ASCII. */
9570 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
9576 fprintf (stream
, "\t.ascii\t\"");
9577 for (i
= 0; i
< len
; i
++)
9581 c
= (unsigned char) string
[i
];
9584 if (c
== '\\' || c
== '\"')
9586 putc ('\\', stream
);
9594 fprintf (stream
, "\\%03o", c
);
9598 if (cur_pos
> 72 && i
+1 < len
)
9601 fprintf (stream
, "\"\n\t.ascii\t\"");
9604 fprintf (stream
, "\"\n");
9607 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
9608 Update *ADDR with the operand that should be printed. */
9611 mips_output_tls_reloc_directive (rtx
*addr
)
9613 enum mips_symbol_type type
;
9615 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
9616 *addr
= mips_strip_unspec_address (*addr
);
9620 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
9623 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
9630 /* Emit either a label, .comm, or .lcomm directive. When using assembler
9631 macros, mark the symbol as written so that mips_asm_output_external
9632 won't emit an .extern for it. STREAM is the output file, NAME is the
9633 name of the symbol, INIT_STRING is the string that should be written
9634 before the symbol and FINAL_STRING is the string that should be
9635 written after it. FINAL_STRING is a printf format that consumes the
9636 remaining arguments. */
9639 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
9640 const char *final_string
, ...)
9644 fputs (init_string
, stream
);
9645 assemble_name (stream
, name
);
9646 va_start (ap
, final_string
);
9647 vfprintf (stream
, final_string
, ap
);
9650 if (!TARGET_EXPLICIT_RELOCS
)
9652 tree name_tree
= get_identifier (name
);
9653 TREE_ASM_WRITTEN (name_tree
) = 1;
9657 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9658 NAME is the name of the object and ALIGN is the required alignment
9659 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9660 alignment argument. */
9663 mips_declare_common_object (FILE *stream
, const char *name
,
9664 const char *init_string
,
9665 unsigned HOST_WIDE_INT size
,
9666 unsigned int align
, bool takes_alignment_p
)
9668 if (!takes_alignment_p
)
9670 size
+= (align
/ BITS_PER_UNIT
) - 1;
9671 size
-= size
% (align
/ BITS_PER_UNIT
);
9672 mips_declare_object (stream
, name
, init_string
,
9673 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
9676 mips_declare_object (stream
, name
, init_string
,
9677 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
9678 size
, align
/ BITS_PER_UNIT
);
9681 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9682 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9685 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
9686 unsigned HOST_WIDE_INT size
,
9689 /* If the target wants uninitialized const declarations in
9690 .rdata then don't put them in .comm. */
9691 if (TARGET_EMBEDDED_DATA
9692 && TARGET_UNINIT_CONST_IN_RODATA
9693 && TREE_CODE (decl
) == VAR_DECL
9694 && TREE_READONLY (decl
)
9695 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
9697 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
9698 targetm
.asm_out
.globalize_label (stream
, name
);
9700 switch_to_section (readonly_data_section
);
9701 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
9702 mips_declare_object (stream
, name
, "",
9703 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
9707 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
9711 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9712 extern int size_directive_output
;
9714 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9715 definitions except that it uses mips_declare_object to emit the label. */
9718 mips_declare_object_name (FILE *stream
, const char *name
,
9719 tree decl ATTRIBUTE_UNUSED
)
9721 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9722 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
9725 size_directive_output
= 0;
9726 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
9730 size_directive_output
= 1;
9731 size
= int_size_in_bytes (TREE_TYPE (decl
));
9732 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9735 mips_declare_object (stream
, name
, "", ":\n");
9738 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9741 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
9745 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
9746 if (!flag_inhibit_size_directive
9747 && DECL_SIZE (decl
) != 0
9750 && DECL_INITIAL (decl
) == error_mark_node
9751 && !size_directive_output
)
9755 size_directive_output
= 1;
9756 size
= int_size_in_bytes (TREE_TYPE (decl
));
9757 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9762 /* Mark text contents as code or data, mainly for the purpose of correct
9763 disassembly. Emit a local symbol and set its type appropriately for
9764 that purpose. Also emit `.insn' if marking contents as code so that
9765 the ISA mode is recorded and any padding that follows is disassembled
9766 as correct instructions. */
9769 mips_set_text_contents_type (FILE *file ATTRIBUTE_UNUSED
,
9770 const char *prefix ATTRIBUTE_UNUSED
,
9771 unsigned long num ATTRIBUTE_UNUSED
,
9772 bool function_p ATTRIBUTE_UNUSED
)
9774 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9775 char buf
[(sizeof (num
) * 10) / 4 + 2];
9780 sprintf (buf
, "%lu", num
);
9781 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
9782 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
9783 sname
= ACONCAT ((prefix
, fnname
, "_", buf
, NULL
));
9785 ASM_OUTPUT_TYPE_DIRECTIVE (file
, sname
, function_p
? "function" : "object");
9786 assemble_name (file
, sname
);
9787 fputs (":\n", file
);
9789 fputs ("\t.insn\n", file
);
9793 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9794 with the current ABI. */
9797 mips_mdebug_abi_name (void)
9810 return TARGET_64BIT
? "eabi64" : "eabi32";
9816 /* Implement TARGET_ASM_FILE_START. */
9819 mips_file_start (void)
9821 default_file_start ();
9823 /* Generate a special section to describe the ABI switches used to
9824 produce the resultant binary. */
9826 /* Record the ABI itself. Modern versions of binutils encode
9827 this information in the ELF header flags, but GDB needs the
9828 information in order to correctly debug binaries produced by
9829 older binutils. See the function mips_gdbarch_init in
9831 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
9832 mips_mdebug_abi_name ());
9834 /* There is no ELF header flag to distinguish long32 forms of the
9835 EABI from long64 forms. Emit a special section to help tools
9836 such as GDB. Do the same for o64, which is sometimes used with
9838 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
9839 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
9840 "\t.previous\n", TARGET_LONG64
? 64 : 32);
9842 /* Record the NaN encoding. */
9843 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
9844 fprintf (asm_out_file
, "\t.nan\t%s\n",
9845 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
9847 #ifdef HAVE_AS_DOT_MODULE
9848 /* Record the FP ABI. See below for comments. */
9849 if (TARGET_NO_FLOAT
)
9850 #ifdef HAVE_AS_GNU_ATTRIBUTE
9851 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file
);
9855 else if (!TARGET_HARD_FLOAT_ABI
)
9856 fputs ("\t.module\tsoftfloat\n", asm_out_file
);
9857 else if (!TARGET_DOUBLE_FLOAT
)
9858 fputs ("\t.module\tsinglefloat\n", asm_out_file
);
9859 else if (TARGET_FLOATXX
)
9860 fputs ("\t.module\tfp=xx\n", asm_out_file
);
9861 else if (TARGET_FLOAT64
)
9862 fputs ("\t.module\tfp=64\n", asm_out_file
);
9864 fputs ("\t.module\tfp=32\n", asm_out_file
);
9866 if (TARGET_ODD_SPREG
)
9867 fputs ("\t.module\toddspreg\n", asm_out_file
);
9869 fputs ("\t.module\tnooddspreg\n", asm_out_file
);
9872 #ifdef HAVE_AS_GNU_ATTRIBUTE
9876 /* No floating-point operations, -mno-float. */
9877 if (TARGET_NO_FLOAT
)
9879 /* Soft-float code, -msoft-float. */
9880 else if (!TARGET_HARD_FLOAT_ABI
)
9882 /* Single-float code, -msingle-float. */
9883 else if (!TARGET_DOUBLE_FLOAT
)
9885 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9887 This case used 12 callee-saved double-precision registers
9888 and is deprecated. */
9889 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9890 else if (TARGET_FLOATXX
)
9892 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9893 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
&& TARGET_ODD_SPREG
)
9895 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9896 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9898 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9902 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9906 fprintf (asm_out_file
, "\t.gnu_attribute 8, 1\n");
9911 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9912 if (TARGET_ABICALLS
)
9914 fprintf (asm_out_file
, "\t.abicalls\n");
9915 if (TARGET_ABICALLS_PIC0
)
9916 fprintf (asm_out_file
, "\t.option\tpic0\n");
9919 if (flag_verbose_asm
)
9920 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9922 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9925 /* Implement TARGET_ASM_CODE_END. */
9928 mips_code_end (void)
9930 mips_finish_stub (&mips16_rdhwr_stub
);
9931 mips_finish_stub (&mips16_get_fcsr_stub
);
9932 mips_finish_stub (&mips16_set_fcsr_stub
);
9935 /* Make the last instruction frame-related and note that it performs
9936 the operation described by FRAME_PATTERN. */
9939 mips_set_frame_expr (rtx frame_pattern
)
9943 insn
= get_last_insn ();
9944 RTX_FRAME_RELATED_P (insn
) = 1;
9945 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9950 /* Return a frame-related rtx that stores REG at MEM.
9951 REG must be a single register. */
9954 mips_frame_set (rtx mem
, rtx reg
)
9958 set
= gen_rtx_SET (mem
, reg
);
9959 RTX_FRAME_RELATED_P (set
) = 1;
9964 /* Record that the epilogue has restored call-saved register REG. */
9967 mips_add_cfa_restore (rtx reg
)
9969 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9970 mips_epilogue
.cfa_restores
);
9973 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9974 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9975 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9976 static const unsigned char mips16e_s2_s8_regs
[] = {
9977 30, 23, 22, 21, 20, 19, 18
9979 static const unsigned char mips16e_a0_a3_regs
[] = {
9983 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9984 ordered from the uppermost in memory to the lowest in memory. */
9985 static const unsigned char mips16e_save_restore_regs
[] = {
9986 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9989 /* Return the index of the lowest X in the range [0, SIZE) for which
9990 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9993 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9998 for (i
= 0; i
< size
; i
++)
9999 if (BITSET_P (mask
, regs
[i
]))
10005 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
10006 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
10007 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
10008 is true for all indexes (X, SIZE). */
10011 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
10012 unsigned int size
, unsigned int *num_regs_ptr
)
10016 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
10017 for (i
++; i
< size
; i
++)
10018 if (!BITSET_P (*mask_ptr
, regs
[i
]))
10020 *num_regs_ptr
+= 1;
10021 *mask_ptr
|= 1 << regs
[i
];
10025 /* Return a simplified form of X using the register values in REG_VALUES.
10026 REG_VALUES[R] is the last value assigned to hard register R, or null
10027 if R has not been modified.
10029 This function is rather limited, but is good enough for our purposes. */
10032 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
10034 x
= avoid_constant_pool_reference (x
);
10038 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
10039 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
10040 x0
, GET_MODE (XEXP (x
, 0)));
10043 if (ARITHMETIC_P (x
))
10045 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
10046 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
10047 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
10051 && reg_values
[REGNO (x
)]
10052 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
10053 return reg_values
[REGNO (x
)];
10058 /* Return true if (set DEST SRC) stores an argument register into its
10059 caller-allocated save slot, storing the number of that argument
10060 register in *REGNO_PTR if so. REG_VALUES is as for
10061 mips16e_collect_propagate_value. */
10064 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
10065 unsigned int *regno_ptr
)
10067 unsigned int argno
, regno
;
10068 HOST_WIDE_INT offset
, required_offset
;
10071 /* Check that this is a word-mode store. */
10072 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
10075 /* Check that the register being saved is an unmodified argument
10077 regno
= REGNO (src
);
10078 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
10080 argno
= regno
- GP_ARG_FIRST
;
10082 /* Check whether the address is an appropriate stack-pointer or
10083 frame-pointer access. */
10084 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
10085 mips_split_plus (addr
, &base
, &offset
);
10086 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
10087 if (base
== hard_frame_pointer_rtx
)
10088 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10089 else if (base
!= stack_pointer_rtx
)
10091 if (offset
!= required_offset
)
10094 *regno_ptr
= regno
;
10098 /* A subroutine of mips_expand_prologue, called only when generating
10099 MIPS16e SAVE instructions. Search the start of the function for any
10100 instructions that save argument registers into their caller-allocated
10101 save slots. Delete such instructions and return a value N such that
10102 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
10103 instructions redundant. */
10105 static unsigned int
10106 mips16e_collect_argument_saves (void)
10108 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
10109 rtx_insn
*insn
, *next
;
10110 rtx set
, dest
, src
;
10111 unsigned int nargs
, regno
;
10113 push_topmost_sequence ();
10115 memset (reg_values
, 0, sizeof (reg_values
));
10116 for (insn
= get_insns (); insn
; insn
= next
)
10118 next
= NEXT_INSN (insn
);
10119 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
10122 if (!INSN_P (insn
))
10125 set
= PATTERN (insn
);
10126 if (GET_CODE (set
) != SET
)
10129 dest
= SET_DEST (set
);
10130 src
= SET_SRC (set
);
10131 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
10133 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
10135 delete_insn (insn
);
10136 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
10139 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
10140 reg_values
[REGNO (dest
)]
10141 = mips16e_collect_propagate_value (src
, reg_values
);
10145 pop_topmost_sequence ();
10150 /* Return a move between register REGNO and memory location SP + OFFSET.
10151 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
10152 Make the move a load if RESTORE_P, otherwise make it a store. */
10155 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
10156 HOST_WIDE_INT offset
, unsigned int regno
)
10160 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
10162 reg
= gen_rtx_REG (SImode
, regno
);
10165 mips_add_cfa_restore (reg
);
10166 return gen_rtx_SET (reg
, mem
);
10169 return gen_rtx_SET (mem
, reg
);
10170 return mips_frame_set (mem
, reg
);
10173 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
10174 The instruction must:
10176 - Allocate or deallocate SIZE bytes in total; SIZE is known
10179 - Save or restore as many registers in *MASK_PTR as possible.
10180 The instruction saves the first registers at the top of the
10181 allocated area, with the other registers below it.
10183 - Save NARGS argument registers above the allocated area.
10185 (NARGS is always zero if RESTORE_P.)
10187 The SAVE and RESTORE instructions cannot save and restore all general
10188 registers, so there may be some registers left over for the caller to
10189 handle. Destructively modify *MASK_PTR so that it contains the registers
10190 that still need to be saved or restored. The caller can save these
10191 registers in the memory immediately below *OFFSET_PTR, which is a
10192 byte offset from the bottom of the allocated stack area. */
10195 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
10196 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
10197 HOST_WIDE_INT size
)
10200 HOST_WIDE_INT offset
, top_offset
;
10201 unsigned int i
, regno
;
10204 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
10206 /* Calculate the number of elements in the PARALLEL. We need one element
10207 for the stack adjustment, one for each argument register save, and one
10208 for each additional register move. */
10210 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
10211 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
10214 /* Create the final PARALLEL. */
10215 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
10218 /* Add the stack pointer adjustment. */
10219 set
= gen_rtx_SET (stack_pointer_rtx
,
10220 plus_constant (Pmode
, stack_pointer_rtx
,
10221 restore_p
? size
: -size
));
10222 RTX_FRAME_RELATED_P (set
) = 1;
10223 XVECEXP (pattern
, 0, n
++) = set
;
10225 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10226 top_offset
= restore_p
? size
: 0;
10228 /* Save the arguments. */
10229 for (i
= 0; i
< nargs
; i
++)
10231 offset
= top_offset
+ i
* UNITS_PER_WORD
;
10232 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
10234 XVECEXP (pattern
, 0, n
++) = set
;
10237 /* Then fill in the other register moves. */
10238 offset
= top_offset
;
10239 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
10241 regno
= mips16e_save_restore_regs
[i
];
10242 if (BITSET_P (*mask_ptr
, regno
))
10244 offset
-= UNITS_PER_WORD
;
10245 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
10246 XVECEXP (pattern
, 0, n
++) = set
;
10247 *mask_ptr
&= ~(1 << regno
);
10251 /* Tell the caller what offset it should use for the remaining registers. */
10252 *offset_ptr
= size
+ (offset
- top_offset
);
10254 gcc_assert (n
== XVECLEN (pattern
, 0));
10259 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
10260 pointer. Return true if PATTERN matches the kind of instruction
10261 generated by mips16e_build_save_restore. If INFO is nonnull,
10262 initialize it when returning true. */
10265 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
10266 struct mips16e_save_restore_info
*info
)
10268 unsigned int i
, nargs
, mask
, extra
;
10269 HOST_WIDE_INT top_offset
, save_offset
, offset
;
10270 rtx set
, reg
, mem
, base
;
10273 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
10276 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10277 top_offset
= adjust
> 0 ? adjust
: 0;
10279 /* Interpret all other members of the PARALLEL. */
10280 save_offset
= top_offset
- UNITS_PER_WORD
;
10284 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
10286 /* Check that we have a SET. */
10287 set
= XVECEXP (pattern
, 0, n
);
10288 if (GET_CODE (set
) != SET
)
10291 /* Check that the SET is a load (if restoring) or a store
10293 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
10297 /* Check that the address is the sum of the stack pointer and a
10298 possibly-zero constant offset. */
10299 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
10300 if (base
!= stack_pointer_rtx
)
10303 /* Check that SET's other operand is a register. */
10304 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
10308 /* Check for argument saves. */
10309 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
10310 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
10312 else if (offset
== save_offset
)
10314 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
10315 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
10318 mask
|= 1 << REGNO (reg
);
10319 save_offset
-= UNITS_PER_WORD
;
10325 /* Check that the restrictions on register ranges are met. */
10327 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
10328 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
10329 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
10330 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
10334 /* Make sure that the topmost argument register is not saved twice.
10335 The checks above ensure that the same is then true for the other
10336 argument registers. */
10337 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
10340 /* Pass back information, if requested. */
10343 info
->nargs
= nargs
;
10345 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
10351 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
10352 for the register range [MIN_REG, MAX_REG]. Return a pointer to
10353 the null terminator. */
10356 mips16e_add_register_range (char *s
, unsigned int min_reg
,
10357 unsigned int max_reg
)
10359 if (min_reg
!= max_reg
)
10360 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
10362 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
10366 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
10367 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
10370 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
10372 static char buffer
[300];
10374 struct mips16e_save_restore_info info
;
10375 unsigned int i
, end
;
10378 /* Parse the pattern. */
10379 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
10380 gcc_unreachable ();
10382 /* Add the mnemonic. */
10383 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
10386 /* Save the arguments. */
10387 if (info
.nargs
> 1)
10388 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
10389 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
10390 else if (info
.nargs
== 1)
10391 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
10393 /* Emit the amount of stack space to allocate or deallocate. */
10394 s
+= sprintf (s
, "%d", (int) info
.size
);
10396 /* Save or restore $16. */
10397 if (BITSET_P (info
.mask
, 16))
10398 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
10400 /* Save or restore $17. */
10401 if (BITSET_P (info
.mask
, 17))
10402 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
10404 /* Save or restore registers in the range $s2...$s8, which
10405 mips16e_s2_s8_regs lists in decreasing order. Note that this
10406 is a software register range; the hardware registers are not
10407 numbered consecutively. */
10408 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
10409 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
10411 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
10412 mips16e_s2_s8_regs
[i
]);
10414 /* Save or restore registers in the range $a0...$a3. */
10415 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
10416 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
10418 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
10419 mips16e_a0_a3_regs
[end
- 1]);
10421 /* Save or restore $31. */
10422 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
10423 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
10428 /* Return true if the current function returns its value in a floating-point
10429 register in MIPS16 mode. */
10432 mips16_cfun_returns_in_fpr_p (void)
10434 tree return_type
= DECL_RESULT (current_function_decl
);
10435 return (TARGET_MIPS16
10436 && TARGET_HARD_FLOAT_ABI
10437 && !aggregate_value_p (return_type
, current_function_decl
)
10438 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
10441 /* Return true if predicate PRED is true for at least one instruction.
10442 Cache the result in *CACHE, and assume that the result is true
10443 if *CACHE is already true. */
10446 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx_insn
*))
10448 rtx_insn
*insn
, *subinsn
;
10452 push_topmost_sequence ();
10453 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10454 FOR_EACH_SUBINSN (subinsn
, insn
)
10455 if (USEFUL_INSN_P (subinsn
) && pred (subinsn
))
10460 pop_topmost_sequence ();
10465 /* Return true if INSN refers to the global pointer in an "inflexible" way.
10466 See mips_cfun_has_inflexible_gp_ref_p for details. */
10469 mips_insn_has_inflexible_gp_ref_p (rtx_insn
*insn
)
10471 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
10472 indicate that the target could be a traditional MIPS
10473 lazily-binding stub. */
10474 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
10477 /* Return true if the current function refers to the global pointer
10478 in a way that forces $28 to be valid. This means that we can't
10479 change the choice of global pointer, even for NewABI code.
10481 One example of this (and one which needs several checks) is that
10482 $28 must be valid when calling traditional MIPS lazy-binding stubs.
10483 (This restriction does not apply to PLTs.) */
10486 mips_cfun_has_inflexible_gp_ref_p (void)
10488 /* If the function has a nonlocal goto, $28 must hold the correct
10489 global pointer for the target function. That is, the target
10490 of the goto implicitly uses $28. */
10491 if (crtl
->has_nonlocal_goto
)
10494 if (TARGET_ABICALLS_PIC2
)
10496 /* Symbolic accesses implicitly use the global pointer unless
10497 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
10498 might go to traditional MIPS lazy-binding stubs. */
10499 if (!TARGET_EXPLICIT_RELOCS
)
10502 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
10503 can be lazily-bound. */
10507 /* MIPS16 functions that return in FPRs need to call an
10508 external libgcc routine. This call is only made explict
10509 during mips_expand_epilogue, and it too might be lazily bound. */
10510 if (mips16_cfun_returns_in_fpr_p ())
10514 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
10515 mips_insn_has_inflexible_gp_ref_p
);
10518 /* Return true if INSN refers to the global pointer in a "flexible" way.
10519 See mips_cfun_has_flexible_gp_ref_p for details. */
10522 mips_insn_has_flexible_gp_ref_p (rtx_insn
*insn
)
10524 return (get_attr_got (insn
) != GOT_UNSET
10525 || mips_small_data_pattern_p (PATTERN (insn
))
10526 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
10529 /* Return true if the current function references the global pointer,
10530 but if those references do not inherently require the global pointer
10531 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
10534 mips_cfun_has_flexible_gp_ref_p (void)
10536 /* Reload can sometimes introduce constant pool references
10537 into a function that otherwise didn't need them. For example,
10538 suppose we have an instruction like:
10540 (set (reg:DF R1) (float:DF (reg:SI R2)))
10542 If R2 turns out to be a constant such as 1, the instruction may
10543 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
10544 the option of using this constant if R2 doesn't get allocated
10547 In cases like these, reload will have added the constant to the
10548 pool but no instruction will yet refer to it. */
10549 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
10552 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
10553 mips_insn_has_flexible_gp_ref_p
);
10556 /* Return the register that should be used as the global pointer
10557 within this function. Return INVALID_REGNUM if the function
10558 doesn't need a global pointer. */
10560 static unsigned int
10561 mips_global_pointer (void)
10563 unsigned int regno
;
10565 /* $gp is always available unless we're using a GOT. */
10566 if (!TARGET_USE_GOT
)
10567 return GLOBAL_POINTER_REGNUM
;
10569 /* If there are inflexible references to $gp, we must use the
10570 standard register. */
10571 if (mips_cfun_has_inflexible_gp_ref_p ())
10572 return GLOBAL_POINTER_REGNUM
;
10574 /* If there are no current references to $gp, then the only uses
10575 we can introduce later are those involved in long branches. */
10576 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
10577 return INVALID_REGNUM
;
10579 /* If the global pointer is call-saved, try to use a call-clobbered
10581 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
10582 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10583 if (!df_regs_ever_live_p (regno
)
10584 && call_really_used_regs
[regno
]
10585 && !fixed_regs
[regno
]
10586 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
10589 return GLOBAL_POINTER_REGNUM
;
10592 /* Return true if the current function's prologue must load the global
10593 pointer value into pic_offset_table_rtx and store the same value in
10594 the function's cprestore slot (if any).
10596 One problem we have to deal with is that, when emitting GOT-based
10597 position independent code, long-branch sequences will need to load
10598 the address of the branch target from the GOT. We don't know until
10599 the very end of compilation whether (and where) the function needs
10600 long branches, so we must ensure that _any_ branch can access the
10601 global pointer in some form. However, we do not want to pessimize
10602 the usual case in which all branches are short.
10604 We handle this as follows:
10606 (1) During reload, we set cfun->machine->global_pointer to
10607 INVALID_REGNUM if we _know_ that the current function
10608 doesn't need a global pointer. This is only valid if
10609 long branches don't need the GOT.
10611 Otherwise, we assume that we might need a global pointer
10612 and pick an appropriate register.
10614 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
10615 we ensure that the global pointer is available at every
10616 block boundary bar entry and exit. We do this in one of two ways:
10618 - If the function has a cprestore slot, we ensure that this
10619 slot is valid at every branch. However, as explained in
10620 point (6) below, there is no guarantee that pic_offset_table_rtx
10621 itself is valid if new uses of the global pointer are introduced
10622 after the first post-epilogue split.
10624 We guarantee that the cprestore slot is valid by loading it
10625 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
10626 this register live at every block boundary bar function entry
10627 and exit. It is then invalid to move the load (and thus the
10628 preceding store) across a block boundary.
10630 - If the function has no cprestore slot, we guarantee that
10631 pic_offset_table_rtx itself is valid at every branch.
10633 See mips_eh_uses for the handling of the register liveness.
10635 (3) During prologue and epilogue generation, we emit "ghost"
10636 placeholder instructions to manipulate the global pointer.
10638 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
10639 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
10640 that the function needs a global pointer. (There is no need to set
10641 them earlier than this, and doing it as late as possible leads to
10642 fewer false positives.)
10644 (5) If cfun->machine->must_initialize_gp_p is true during a
10645 split_insns pass, we split the ghost instructions into real
10646 instructions. These split instructions can then be optimized in
10647 the usual way. Otherwise, we keep the ghost instructions intact,
10648 and optimize for the case where they aren't needed. We still
10649 have the option of splitting them later, if we need to introduce
10650 new uses of the global pointer.
10652 For example, the scheduler ignores a ghost instruction that
10653 stores $28 to the stack, but it handles the split form of
10654 the ghost instruction as an ordinary store.
10656 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
10657 is true during the first post-epilogue split_insns pass, we split
10658 calls and restore_gp patterns into instructions that explicitly
10659 load pic_offset_table_rtx from the cprestore slot. Otherwise,
10660 we split these patterns into instructions that _don't_ load from
10661 the cprestore slot.
10663 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
10664 time of the split, then any instructions that exist at that time
10665 can make free use of pic_offset_table_rtx. However, if we want
10666 to introduce new uses of the global pointer after the split,
10667 we must explicitly load the value from the cprestore slot, since
10668 pic_offset_table_rtx itself might not be valid at a given point
10671 The idea is that we want to be able to delete redundant
10672 loads from the cprestore slot in the usual case where no
10673 long branches are needed.
10675 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10676 of md_reorg, we decide whether the global pointer is needed for
10677 long branches. If so, we set cfun->machine->must_initialize_gp_p
10678 to true and split the ghost instructions into real instructions
10681 Note that the ghost instructions must have a zero length for three reasons:
10683 - Giving the length of the underlying $gp sequence might cause
10684 us to use long branches in cases where they aren't really needed.
10686 - They would perturb things like alignment calculations.
10688 - More importantly, the hazard detection in md_reorg relies on
10689 empty instructions having a zero length.
10691 If we find a long branch and split the ghost instructions at the
10692 end of md_reorg, the split could introduce more long branches.
10693 That isn't a problem though, because we still do the split before
10694 the final shorten_branches pass.
10696 This is extremely ugly, but it seems like the best compromise between
10697 correctness and efficiency. */
10700 mips_must_initialize_gp_p (void)
10702 return cfun
->machine
->must_initialize_gp_p
;
10705 /* Return true if REGNO is a register that is ordinarily call-clobbered
10706 but must nevertheless be preserved by an interrupt handler. */
10709 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
10711 if ((ISA_HAS_HILO
|| TARGET_DSP
)
10712 && MD_REG_P (regno
))
10715 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
10718 if (GP_REG_P (regno
)
10719 && cfun
->machine
->use_shadow_register_set
== SHADOW_SET_NO
)
10721 /* $0 is hard-wired. */
10722 if (regno
== GP_REG_FIRST
)
10725 /* The interrupt handler can treat kernel registers as
10726 scratch registers. */
10727 if (KERNEL_REG_P (regno
))
10730 /* The function will return the stack pointer to its original value
10732 if (regno
== STACK_POINTER_REGNUM
)
10735 /* Otherwise, return true for registers that aren't ordinarily
10737 return call_really_used_regs
[regno
];
10743 /* Return true if the current function should treat register REGNO
10747 mips_cfun_call_saved_reg_p (unsigned int regno
)
10749 /* If the user makes an ordinarily-call-saved register global,
10750 that register is no longer call-saved. */
10751 if (global_regs
[regno
])
10754 /* Interrupt handlers need to save extra registers. */
10755 if (cfun
->machine
->interrupt_handler_p
10756 && mips_interrupt_extra_call_saved_reg_p (regno
))
10759 /* call_insns preserve $28 unless they explicitly say otherwise,
10760 so call_really_used_regs[] treats $28 as call-saved. However,
10761 we want the ABI property rather than the default call_insn
10763 return (regno
== GLOBAL_POINTER_REGNUM
10764 ? TARGET_CALL_SAVED_GP
10765 : !call_really_used_regs
[regno
]);
10768 /* Return true if the function body might clobber register REGNO.
10769 We know that REGNO is call-saved. */
10772 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
10774 /* Some functions should be treated as clobbering all call-saved
10776 if (crtl
->saves_all_registers
)
10779 /* DF handles cases where a register is explicitly referenced in
10780 the rtl. Incoming values are passed in call-clobbered registers,
10781 so we can assume that any live call-saved register is set within
10783 if (df_regs_ever_live_p (regno
))
10786 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10787 These clobbers are not explicit in the rtl. */
10788 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
10791 /* If we're using a call-saved global pointer, the function's
10792 prologue will need to set it up. */
10793 if (cfun
->machine
->global_pointer
== regno
)
10796 /* The function's prologue will need to set the frame pointer if
10797 frame_pointer_needed. */
10798 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
10801 /* If a MIPS16 function returns a value in FPRs, its epilogue
10802 will need to call an external libgcc routine. This yet-to-be
10803 generated call_insn will clobber $31. */
10804 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
10807 /* If REGNO is ordinarily call-clobbered, we must assume that any
10808 called function could modify it. */
10809 if (cfun
->machine
->interrupt_handler_p
10811 && mips_interrupt_extra_call_saved_reg_p (regno
))
10817 /* Return true if the current function must save register REGNO. */
10820 mips_save_reg_p (unsigned int regno
)
10822 if (mips_cfun_call_saved_reg_p (regno
))
10824 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
10827 /* Save both registers in an FPR pair if either one is used. This is
10828 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10829 register to be used without the even register. */
10830 if (FP_REG_P (regno
)
10831 && MAX_FPRS_PER_FMT
== 2
10832 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
10836 /* We need to save the incoming return address if __builtin_eh_return
10837 is being used to set a different return address. */
10838 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
10844 /* Populate the current function's mips_frame_info structure.
10846 MIPS stack frames look like:
10848 +-------------------------------+
10850 | incoming stack arguments |
10852 +-------------------------------+
10854 | caller-allocated save area |
10855 A | for register arguments |
10857 +-------------------------------+ <-- incoming stack pointer
10859 | callee-allocated save area |
10860 B | for arguments that are |
10861 | split between registers and |
10864 +-------------------------------+ <-- arg_pointer_rtx
10866 C | callee-allocated save area |
10867 | for register varargs |
10869 +-------------------------------+ <-- frame_pointer_rtx
10870 | | + cop0_sp_offset
10871 | COP0 reg save area | + UNITS_PER_WORD
10873 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10874 | | + UNITS_PER_WORD
10875 | accumulator save area |
10877 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10878 | | + UNITS_PER_HWFPVALUE
10881 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10882 | | + UNITS_PER_WORD
10885 +-------------------------------+ <-- frame_pointer_rtx with
10886 | | \ -fstack-protector
10887 | local variables | | var_size
10889 +-------------------------------+
10891 | $gp save area | | cprestore_size
10893 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10895 | outgoing stack arguments | |
10897 +-------------------------------+ | args_size
10899 | caller-allocated save area | |
10900 | for register arguments | |
10902 +-------------------------------+ <-- stack_pointer_rtx
10903 frame_pointer_rtx without
10905 hard_frame_pointer_rtx for
10908 At least two of A, B and C will be empty.
10910 Dynamic stack allocations such as alloca insert data at point P.
10911 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10912 hard_frame_pointer_rtx unchanged. */
10915 mips_compute_frame_info (void)
10917 struct mips_frame_info
*frame
;
10918 HOST_WIDE_INT offset
, size
;
10919 unsigned int regno
, i
;
10921 /* Skip re-computing the frame info after reload completed. */
10922 if (reload_completed
)
10925 /* Set this function's interrupt properties. */
10926 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10928 if (mips_isa_rev
< 2)
10929 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10930 else if (TARGET_MIPS16
)
10931 error ("interrupt handlers cannot be MIPS16 functions");
10934 cfun
->machine
->interrupt_handler_p
= true;
10935 cfun
->machine
->int_mask
=
10936 mips_interrupt_mask (TREE_TYPE (current_function_decl
));
10937 cfun
->machine
->use_shadow_register_set
=
10938 mips_use_shadow_register_set (TREE_TYPE (current_function_decl
));
10939 cfun
->machine
->keep_interrupts_masked_p
=
10940 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10941 cfun
->machine
->use_debug_exception_return_p
=
10942 mips_use_debug_exception_return_p (TREE_TYPE
10943 (current_function_decl
));
10947 frame
= &cfun
->machine
->frame
;
10948 memset (frame
, 0, sizeof (*frame
));
10949 size
= get_frame_size ();
10951 /* The first two blocks contain the outgoing argument area and the $gp save
10952 slot. This area isn't needed in leaf functions. We can also skip it
10953 if we know that none of the called functions will use this space.
10955 But if the target-independent frame size is nonzero, we have already
10956 committed to allocating these in STARTING_FRAME_OFFSET for
10957 !FRAME_GROWS_DOWNWARD. */
10959 if ((size
== 0 || FRAME_GROWS_DOWNWARD
)
10960 && (crtl
->is_leaf
|| (cfun
->machine
->optimize_call_stack
&& !flag_pic
)))
10962 /* The MIPS 3.0 linker does not like functions that dynamically
10963 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10964 looks like we are trying to create a second frame pointer to the
10965 function, so allocate some stack space to make it happy. */
10966 if (cfun
->calls_alloca
)
10967 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10969 frame
->args_size
= 0;
10970 frame
->cprestore_size
= 0;
10974 frame
->args_size
= crtl
->outgoing_args_size
;
10975 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10978 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10979 arguments. This tends to increase the chances of using unextended
10980 instructions for local variables and incoming arguments. */
10982 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10984 /* PR 69129 / 69012: Beware of a possible race condition. mips_global_pointer
10985 might call mips_cfun_has_inflexible_gp_ref_p which in turn can call
10986 mips_find_gp_ref which will iterate over the current insn sequence.
10987 If any of these insns use the cprestore_save_slot_operand or
10988 cprestore_load_slot_operand predicates in order to be recognised then
10989 they will call mips_cprestore_address_p which calls
10990 mips_get_cprestore_base_and_offset which expects the frame information
10991 to be filled in... In fact mips_get_cprestore_base_and_offset only
10992 needs the args_size and hard_frame_pointer_offset fields to be filled
10993 in, which is why the global_pointer field is initialised here and not
10995 cfun
->machine
->global_pointer
= mips_global_pointer ();
10997 offset
= frame
->args_size
+ frame
->cprestore_size
;
10999 /* Move above the local variables. */
11000 frame
->var_size
= MIPS_STACK_ALIGN (size
);
11001 offset
+= frame
->var_size
;
11003 /* Find out which GPRs we need to save. */
11004 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
11005 if (mips_save_reg_p (regno
))
11008 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
11011 /* If this function calls eh_return, we must also save and restore the
11012 EH data registers. */
11013 if (crtl
->calls_eh_return
)
11014 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
11017 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
11020 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
11021 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
11022 save all later registers too. */
11023 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11025 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
11026 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
11027 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
11028 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
11031 /* Move above the GPR save area. */
11032 if (frame
->num_gp
> 0)
11034 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
11035 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
11038 /* Find out which FPRs we need to save. This loop must iterate over
11039 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
11040 if (TARGET_HARD_FLOAT
)
11041 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
11042 if (mips_save_reg_p (regno
))
11044 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
11045 frame
->fmask
|= ~(~0U << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
11048 /* Move above the FPR save area. */
11049 if (frame
->num_fp
> 0)
11051 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
11052 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
11055 /* Add in space for the interrupt context information. */
11056 if (cfun
->machine
->interrupt_handler_p
)
11059 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
11062 frame
->acc_mask
|= (1 << 0);
11065 /* Check accumulators 1, 2, 3. */
11066 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
11067 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
11070 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
11073 /* All interrupt context functions need space to preserve STATUS. */
11074 frame
->num_cop0_regs
++;
11076 /* We need to save EPC regardless of whether interrupts remain masked
11077 as exceptions will corrupt EPC. */
11078 frame
->num_cop0_regs
++;
11081 /* Move above the accumulator save area. */
11082 if (frame
->num_acc
> 0)
11084 /* Each accumulator needs 2 words. */
11085 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
11086 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
11089 /* Move above the COP0 register save area. */
11090 if (frame
->num_cop0_regs
> 0)
11092 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
11093 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
11096 /* Determine if we can save the callee-saved registers in the frame
11097 header. Restrict this to functions where there is no other reason
11098 to allocate stack space so that we can eliminate the instructions
11099 that modify the stack pointer. */
11103 && flag_frame_header_optimization
11104 && !MAIN_NAME_P (DECL_NAME (current_function_decl
))
11105 && cfun
->machine
->varargs_size
== 0
11106 && crtl
->args
.pretend_args_size
== 0
11107 && frame
->var_size
== 0
11108 && frame
->num_acc
== 0
11109 && frame
->num_cop0_regs
== 0
11110 && frame
->num_fp
== 0
11111 && frame
->num_gp
> 0
11112 && frame
->num_gp
<= MAX_ARGS_IN_REGISTERS
11113 && !GENERATE_MIPS16E_SAVE_RESTORE
11114 && !cfun
->machine
->interrupt_handler_p
11115 && cfun
->machine
->does_not_use_frame_header
11116 && cfun
->machine
->optimize_call_stack
11117 && !cfun
->machine
->callers_may_not_allocate_frame
11118 && !mips_cfun_has_cprestore_slot_p ())
11121 frame
->gp_sp_offset
= REG_PARM_STACK_SPACE(cfun
) - UNITS_PER_WORD
;
11122 cfun
->machine
->use_frame_header_for_callee_saved_regs
= true;
11125 /* Move above the callee-allocated varargs save area. */
11126 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
11127 frame
->arg_pointer_offset
= offset
;
11129 /* Move above the callee-allocated area for pretend stack arguments. */
11130 offset
+= crtl
->args
.pretend_args_size
;
11131 frame
->total_size
= offset
;
11133 /* Work out the offsets of the save areas from the top of the frame. */
11134 if (frame
->gp_sp_offset
> 0)
11135 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
11136 if (frame
->fp_sp_offset
> 0)
11137 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
11138 if (frame
->acc_sp_offset
> 0)
11139 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
11140 if (frame
->num_cop0_regs
> 0)
11141 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
11144 /* Return the style of GP load sequence that is being used for the
11145 current function. */
11147 enum mips_loadgp_style
11148 mips_current_loadgp_style (void)
11150 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
11151 return LOADGP_NONE
;
11153 if (TARGET_RTP_PIC
)
11156 if (TARGET_ABSOLUTE_ABICALLS
)
11157 return LOADGP_ABSOLUTE
;
11159 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
11162 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11165 mips_frame_pointer_required (void)
11167 /* If the function contains dynamic stack allocations, we need to
11168 use the frame pointer to access the static parts of the frame. */
11169 if (cfun
->calls_alloca
)
11172 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
11173 reload may be unable to compute the address of a local variable,
11174 since there is no way to add a large constant to the stack pointer
11175 without using a second temporary register. */
11178 mips_compute_frame_info ();
11179 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
11186 /* Make sure that we're not trying to eliminate to the wrong hard frame
11190 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
11192 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
11195 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
11196 or argument pointer. TO is either the stack pointer or hard frame
11200 mips_initial_elimination_offset (int from
, int to
)
11202 HOST_WIDE_INT offset
;
11204 mips_compute_frame_info ();
11206 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
11209 case FRAME_POINTER_REGNUM
:
11210 if (FRAME_GROWS_DOWNWARD
)
11211 offset
= (cfun
->machine
->frame
.args_size
11212 + cfun
->machine
->frame
.cprestore_size
11213 + cfun
->machine
->frame
.var_size
);
11218 case ARG_POINTER_REGNUM
:
11219 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
11223 gcc_unreachable ();
11226 if (to
== HARD_FRAME_POINTER_REGNUM
)
11227 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
11232 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
11235 mips_extra_live_on_entry (bitmap regs
)
11237 if (TARGET_USE_GOT
)
11239 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
11240 the global pointer. */
11241 if (!TARGET_ABSOLUTE_ABICALLS
)
11242 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
11244 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
11245 the global pointer. */
11247 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
11249 /* See the comment above load_call<mode> for details. */
11250 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
11254 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
11258 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
11263 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
11266 /* Emit code to change the current function's return address to
11267 ADDRESS. SCRATCH is available as a scratch register, if needed.
11268 ADDRESS and SCRATCH are both word-mode GPRs. */
11271 mips_set_return_address (rtx address
, rtx scratch
)
11275 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
11276 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
11277 cfun
->machine
->frame
.gp_sp_offset
);
11278 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
11281 /* Return true if the current function has a cprestore slot. */
11284 mips_cfun_has_cprestore_slot_p (void)
11286 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
11287 && cfun
->machine
->frame
.cprestore_size
> 0);
11290 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
11291 cprestore slot. LOAD_P is true if the caller wants to load from
11292 the cprestore slot; it is false if the caller wants to store to
11296 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
11299 const struct mips_frame_info
*frame
;
11301 frame
= &cfun
->machine
->frame
;
11302 /* .cprestore always uses the stack pointer instead of the frame pointer.
11303 We have a free choice for direct stores for non-MIPS16 functions,
11304 and for MIPS16 functions whose cprestore slot is in range of the
11305 stack pointer. Using the stack pointer would sometimes give more
11306 (early) scheduling freedom, but using the frame pointer would
11307 sometimes give more (late) scheduling freedom. It's hard to
11308 predict which applies to a given function, so let's keep things
11311 Loads must always use the frame pointer in functions that call
11312 alloca, and there's little benefit to using the stack pointer
11314 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
11316 *base
= hard_frame_pointer_rtx
;
11317 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
11321 *base
= stack_pointer_rtx
;
11322 *offset
= frame
->args_size
;
11326 /* Return true if X is the load or store address of the cprestore slot;
11327 LOAD_P says which. */
11330 mips_cprestore_address_p (rtx x
, bool load_p
)
11332 rtx given_base
, required_base
;
11333 HOST_WIDE_INT given_offset
, required_offset
;
11335 mips_split_plus (x
, &given_base
, &given_offset
);
11336 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
11337 return given_base
== required_base
&& given_offset
== required_offset
;
11340 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
11341 going to load from it, false if we are going to store to it.
11342 Use TEMP as a temporary register if need be. */
11345 mips_cprestore_slot (rtx temp
, bool load_p
)
11348 HOST_WIDE_INT offset
;
11350 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
11351 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
11354 /* Emit instructions to save global pointer value GP into cprestore
11355 slot MEM. OFFSET is the offset that MEM applies to the base register.
11357 MEM may not be a legitimate address. If it isn't, TEMP is a
11358 temporary register that can be used, otherwise it is a SCRATCH. */
11361 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
11363 if (TARGET_CPRESTORE_DIRECTIVE
)
11365 gcc_assert (gp
== pic_offset_table_rtx
);
11366 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
11369 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
11372 /* Restore $gp from its save slot, using TEMP as a temporary base register
11373 if need be. This function is for o32 and o64 abicalls only.
11375 See mips_must_initialize_gp_p for details about how we manage the
11379 mips_restore_gp_from_cprestore_slot (rtx temp
)
11381 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
11383 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
11385 emit_note (NOTE_INSN_DELETED
);
11391 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
11392 mips_emit_move (pic_offset_table_rtx
, temp
);
11395 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
11396 if (!TARGET_EXPLICIT_RELOCS
)
11397 emit_insn (gen_blockage ());
11400 /* A function to save or store a register. The first argument is the
11401 register and the second is the stack slot. */
11402 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
11404 /* Use FN to save or restore register REGNO. MODE is the register's
11405 mode and OFFSET is the offset of its save slot from the current
11409 mips_save_restore_reg (machine_mode mode
, int regno
,
11410 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
11414 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11416 fn (gen_rtx_REG (mode
, regno
), mem
);
11419 /* Call FN for each accumulator that is saved by the current function.
11420 SP_OFFSET is the offset of the current stack pointer from the start
11424 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
11426 HOST_WIDE_INT offset
;
11429 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
11430 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
11432 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
11433 offset
-= UNITS_PER_WORD
;
11434 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
11435 offset
-= UNITS_PER_WORD
;
11438 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
11439 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
11440 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
11442 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
11443 offset
-= UNITS_PER_WORD
;
11447 /* Save register REG to MEM. Make the instruction frame-related. */
11450 mips_save_reg (rtx reg
, rtx mem
)
11452 if (GET_MODE (reg
) == DFmode
11453 && (!TARGET_FLOAT64
11454 || mips_abi
== ABI_32
))
11458 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
11460 x1
= mips_frame_set (mips_subword (mem
, false),
11461 mips_subword (reg
, false));
11462 x2
= mips_frame_set (mips_subword (mem
, true),
11463 mips_subword (reg
, true));
11464 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
11467 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
11470 /* Capture the register combinations that are allowed in a SWM or LWM
11471 instruction. The entries are ordered by number of registers set in
11472 the mask. We also ignore the single register encodings because a
11473 normal SW/LW is preferred. */
11475 static const unsigned int umips_swm_mask
[17] = {
11476 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
11477 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
11478 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
11479 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
11483 static const unsigned int umips_swm_encoding
[17] = {
11484 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
11487 /* Try to use a microMIPS LWM or SWM instruction to save or restore
11488 as many GPRs in *MASK as possible. *OFFSET is the offset from the
11489 stack pointer of the topmost save slot.
11491 Remove from *MASK all registers that were handled using LWM and SWM.
11492 Update *OFFSET so that it points to the first unused save slot. */
11495 umips_build_save_restore (mips_save_restore_fn fn
,
11496 unsigned *mask
, HOST_WIDE_INT
*offset
)
11500 rtx pattern
, set
, reg
, mem
;
11501 HOST_WIDE_INT this_offset
;
11504 /* Try matching $16 to $31 (s0 to ra). */
11505 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
11506 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
11509 if (i
== ARRAY_SIZE (umips_swm_mask
))
11512 /* Get the offset of the lowest save slot. */
11513 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
11514 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
11516 /* LWM/SWM can only support offsets from -2048 to 2047. */
11517 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
11520 /* Create the final PARALLEL. */
11521 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
11522 this_base
= stack_pointer_rtx
;
11524 /* For registers $16-$23 and $30. */
11525 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
11527 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
11528 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
11529 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
11530 *mask
&= ~(1 << regno
);
11531 reg
= gen_rtx_REG (SImode
, regno
);
11532 if (fn
== mips_save_reg
)
11533 set
= mips_frame_set (mem
, reg
);
11536 set
= gen_rtx_SET (reg
, mem
);
11537 mips_add_cfa_restore (reg
);
11539 XVECEXP (pattern
, 0, j
) = set
;
11542 /* For register $31. */
11543 if (umips_swm_encoding
[i
] >> 4)
11545 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
11546 *mask
&= ~(1 << 31);
11547 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
11548 reg
= gen_rtx_REG (SImode
, 31);
11549 if (fn
== mips_save_reg
)
11550 set
= mips_frame_set (mem
, reg
);
11553 set
= gen_rtx_SET (reg
, mem
);
11554 mips_add_cfa_restore (reg
);
11556 XVECEXP (pattern
, 0, j
) = set
;
11559 pattern
= emit_insn (pattern
);
11560 if (fn
== mips_save_reg
)
11561 RTX_FRAME_RELATED_P (pattern
) = 1;
11563 /* Adjust the last offset. */
11564 *offset
-= UNITS_PER_WORD
* nregs
;
11569 /* Call FN for each register that is saved by the current function.
11570 SP_OFFSET is the offset of the current stack pointer from the start
11574 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
11575 mips_save_restore_fn fn
)
11577 machine_mode fpr_mode
;
11579 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
11580 HOST_WIDE_INT offset
;
11583 /* Save registers starting from high to low. The debuggers prefer at least
11584 the return register be stored at func+4, and also it allows us not to
11585 need a nop in the epilogue if at least one register is reloaded in
11586 addition to return address. */
11587 offset
= frame
->gp_sp_offset
- sp_offset
;
11588 mask
= frame
->mask
;
11590 if (TARGET_MICROMIPS
)
11591 umips_build_save_restore (fn
, &mask
, &offset
);
11593 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
11594 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11596 /* Record the ra offset for use by mips_function_profiler. */
11597 if (regno
== RETURN_ADDR_REGNUM
)
11598 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
11599 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
11600 offset
-= UNITS_PER_WORD
;
11603 /* This loop must iterate over the same space as its companion in
11604 mips_compute_frame_info. */
11605 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
11606 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
11607 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
11608 regno
>= FP_REG_FIRST
;
11609 regno
-= MAX_FPRS_PER_FMT
)
11610 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
11612 if (!TARGET_FLOAT64
&& TARGET_DOUBLE_FLOAT
11613 && (fixed_regs
[regno
] || fixed_regs
[regno
+ 1]))
11615 if (fixed_regs
[regno
])
11616 mips_save_restore_reg (SFmode
, regno
+ 1, offset
, fn
);
11618 mips_save_restore_reg (SFmode
, regno
, offset
, fn
);
11621 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
11622 offset
-= GET_MODE_SIZE (fpr_mode
);
11626 /* Return true if a move between register REGNO and its save slot (MEM)
11627 can be done in a single move. LOAD_P is true if we are loading
11628 from the slot, false if we are storing to it. */
11631 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
11633 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
11634 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
11637 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
11638 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
11641 /* Emit a move from SRC to DEST, given that one of them is a register
11642 save slot and that the other is a register. TEMP is a temporary
11643 GPR of the same mode that is available if need be. */
11646 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
11648 unsigned int regno
;
11653 regno
= REGNO (src
);
11658 regno
= REGNO (dest
);
11662 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
11664 /* We don't yet know whether we'll need this instruction or not.
11665 Postpone the decision by emitting a ghost move. This move
11666 is specifically not frame-related; only the split version is. */
11668 emit_insn (gen_move_gpdi (dest
, src
));
11670 emit_insn (gen_move_gpsi (dest
, src
));
11674 if (regno
== HI_REGNUM
)
11678 mips_emit_move (temp
, src
);
11680 emit_insn (gen_mthidi_ti (gen_rtx_REG (TImode
, MD_REG_FIRST
),
11681 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
11683 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
11684 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
11689 emit_insn (gen_mfhidi_ti (temp
,
11690 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
11692 emit_insn (gen_mfhisi_di (temp
,
11693 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
11694 mips_emit_move (dest
, temp
);
11697 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
11698 mips_emit_move (dest
, src
);
11701 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
11702 mips_emit_move (temp
, src
);
11703 mips_emit_move (dest
, temp
);
11706 mips_set_frame_expr (mips_frame_set (dest
, src
));
11709 /* If we're generating n32 or n64 abicalls, and the current function
11710 does not use $28 as its global pointer, emit a cplocal directive.
11711 Use pic_offset_table_rtx as the argument to the directive. */
11714 mips_output_cplocal (void)
11716 if (!TARGET_EXPLICIT_RELOCS
11717 && mips_must_initialize_gp_p ()
11718 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
11719 output_asm_insn (".cplocal %+", 0);
11722 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11725 mips_output_function_prologue (FILE *file
)
11727 const char *fnname
;
11729 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11730 floating-point arguments. */
11732 && TARGET_HARD_FLOAT_ABI
11733 && crtl
->args
.info
.fp_code
!= 0)
11734 mips16_build_function_stub ();
11736 /* Get the function name the same way that toplev.c does before calling
11737 assemble_start_function. This is needed so that the name used here
11738 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11739 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11740 mips_start_function_definition (fnname
, TARGET_MIPS16
);
11742 /* Output MIPS-specific frame information. */
11743 if (!flag_inhibit_size_directive
)
11745 const struct mips_frame_info
*frame
;
11747 frame
= &cfun
->machine
->frame
;
11749 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11751 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
11752 "# vars= " HOST_WIDE_INT_PRINT_DEC
11754 ", args= " HOST_WIDE_INT_PRINT_DEC
11755 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
11756 reg_names
[frame_pointer_needed
11757 ? HARD_FRAME_POINTER_REGNUM
11758 : STACK_POINTER_REGNUM
],
11759 (frame_pointer_needed
11760 ? frame
->total_size
- frame
->hard_frame_pointer_offset
11761 : frame
->total_size
),
11762 reg_names
[RETURN_ADDR_REGNUM
],
11764 frame
->num_gp
, frame
->num_fp
,
11766 frame
->cprestore_size
);
11768 /* .mask MASK, OFFSET. */
11769 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11770 frame
->mask
, frame
->gp_save_offset
);
11772 /* .fmask MASK, OFFSET. */
11773 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11774 frame
->fmask
, frame
->fp_save_offset
);
11777 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11778 Also emit the ".set noreorder; .set nomacro" sequence for functions
11780 if (mips_must_initialize_gp_p ()
11781 && mips_current_loadgp_style () == LOADGP_OLDABI
)
11785 /* This is a fixed-form sequence. The position of the
11786 first two instructions is important because of the
11787 way _gp_disp is defined. */
11788 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11789 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11790 output_asm_insn ("sll\t$2,16", 0);
11791 output_asm_insn ("addu\t$2,$3", 0);
11795 /* .cpload must be in a .set noreorder but not a
11796 .set nomacro block. */
11797 mips_push_asm_switch (&mips_noreorder
);
11798 output_asm_insn (".cpload\t%^", 0);
11799 if (!cfun
->machine
->all_noreorder_p
)
11800 mips_pop_asm_switch (&mips_noreorder
);
11802 mips_push_asm_switch (&mips_nomacro
);
11805 else if (cfun
->machine
->all_noreorder_p
)
11807 mips_push_asm_switch (&mips_noreorder
);
11808 mips_push_asm_switch (&mips_nomacro
);
11811 /* Tell the assembler which register we're using as the global
11812 pointer. This is needed for thunks, since they can use either
11813 explicit relocs or assembler macros. */
11814 mips_output_cplocal ();
11817 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11820 mips_output_function_epilogue (FILE *)
11822 const char *fnname
;
11824 /* Reinstate the normal $gp. */
11825 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
11826 mips_output_cplocal ();
11828 if (cfun
->machine
->all_noreorder_p
)
11830 mips_pop_asm_switch (&mips_nomacro
);
11831 mips_pop_asm_switch (&mips_noreorder
);
11834 /* Get the function name the same way that toplev.c does before calling
11835 assemble_start_function. This is needed so that the name used here
11836 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11837 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11838 mips_end_function_definition (fnname
);
11841 /* Emit an optimisation barrier for accesses to the current frame. */
11844 mips_frame_barrier (void)
11846 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
11850 /* The __gnu_local_gp symbol. */
11852 static GTY(()) rtx mips_gnu_local_gp
;
11854 /* If we're generating n32 or n64 abicalls, emit instructions
11855 to set up the global pointer. */
11858 mips_emit_loadgp (void)
11860 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
11862 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11863 switch (mips_current_loadgp_style ())
11865 case LOADGP_ABSOLUTE
:
11866 if (mips_gnu_local_gp
== NULL
)
11868 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
11869 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
11871 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
11872 (pic_reg
, mips_gnu_local_gp
)));
11875 case LOADGP_OLDABI
:
11876 /* Added by mips_output_function_prologue. */
11879 case LOADGP_NEWABI
:
11880 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
11881 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
11882 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11883 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
11884 (pic_reg
, offset
, incoming_address
)));
11888 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
11889 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
11890 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
11898 emit_insn (PMODE_INSN (gen_copygp_mips16
,
11899 (pic_offset_table_rtx
, pic_reg
)));
11901 /* Emit a blockage if there are implicit uses of the GP register.
11902 This includes profiled functions, because FUNCTION_PROFILE uses
11904 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
11905 emit_insn (gen_loadgp_blockage ());
11908 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11910 #if PROBE_INTERVAL > 32768
11911 #error Cannot use indexed addressing mode for stack probing
11914 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11915 inclusive. These are offsets from the current stack pointer. */
11918 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
11921 sorry ("-fstack-check=specific not implemented for MIPS16");
11923 /* See if we have a constant small number of probes to generate. If so,
11924 that's the easy case. */
11925 if (first
+ size
<= 32768)
11929 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11930 it exceeds SIZE. If only one probe is needed, this will not
11931 generate any code. Then probe at FIRST + SIZE. */
11932 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
11933 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11936 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11940 /* Otherwise, do the same as above, but in a loop. Note that we must be
11941 extra careful with variables wrapping around because we might be at
11942 the very top (or the very bottom) of the address space and we have
11943 to be able to handle this case properly; in particular, we use an
11944 equality test for the loop condition. */
11947 HOST_WIDE_INT rounded_size
;
11948 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
11949 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
11951 /* Sanity check for the addressing mode we're going to use. */
11952 gcc_assert (first
<= 32768);
11955 /* Step 1: round SIZE to the previous multiple of the interval. */
11957 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
11960 /* Step 2: compute initial and final value of the loop counter. */
11962 /* TEST_ADDR = SP + FIRST. */
11963 emit_insn (gen_rtx_SET (r3
, plus_constant (Pmode
, stack_pointer_rtx
,
11966 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11967 if (rounded_size
> 32768)
11969 emit_move_insn (r12
, GEN_INT (rounded_size
));
11970 emit_insn (gen_rtx_SET (r12
, gen_rtx_MINUS (Pmode
, r3
, r12
)));
11973 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, r3
,
11977 /* Step 3: the loop
11981 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11984 while (TEST_ADDR != LAST_ADDR)
11986 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11987 until it is equal to ROUNDED_SIZE. */
11989 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11992 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11993 that SIZE is equal to ROUNDED_SIZE. */
11995 if (size
!= rounded_size
)
11996 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
11999 /* Make sure nothing is scheduled before we are done. */
12000 emit_insn (gen_blockage ());
12003 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
12004 absolute addresses. */
12007 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
12009 static int labelno
= 0;
12010 char loop_lab
[32], tmp
[64];
12013 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
12016 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
12018 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
12020 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
12021 if (TARGET_64BIT
&& TARGET_LONG64
)
12022 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
12024 output_asm_insn ("addiu\t%0,%0,%1", xops
);
12026 /* Probe at TEST_ADDR, test if TEST_ADDR == LAST_ADDR and branch. */
12028 strcpy (tmp
, "%(%<bne\t%0,%1,");
12029 output_asm_insn (strcat (tmp
, &loop_lab
[1]), xops
);
12031 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
12033 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
12038 /* Return true if X contains a kernel register. */
12041 mips_refers_to_kernel_reg_p (const_rtx x
)
12043 subrtx_iterator::array_type array
;
12044 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
12045 if (REG_P (*iter
) && KERNEL_REG_P (REGNO (*iter
)))
12050 /* Expand the "prologue" pattern. */
12053 mips_expand_prologue (void)
12055 const struct mips_frame_info
*frame
;
12056 HOST_WIDE_INT size
;
12057 unsigned int nargs
;
12059 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
12061 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
12062 or implicitly. If so, we can commit to using a global pointer
12063 straight away, otherwise we need to defer the decision. */
12064 if (mips_cfun_has_inflexible_gp_ref_p ()
12065 || mips_cfun_has_flexible_gp_ref_p ())
12067 cfun
->machine
->must_initialize_gp_p
= true;
12068 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
12071 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
12074 frame
= &cfun
->machine
->frame
;
12075 size
= frame
->total_size
;
12077 if (flag_stack_usage_info
)
12078 current_function_static_stack_size
= size
;
12080 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
12082 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
12084 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
12085 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
12086 size
- STACK_CHECK_PROTECT
);
12089 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
12092 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
12093 bytes beforehand; this is enough to cover the register save area
12094 without going out of range. */
12095 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
12096 || frame
->num_cop0_regs
> 0)
12098 HOST_WIDE_INT step1
;
12100 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
12101 if (GENERATE_MIPS16E_SAVE_RESTORE
)
12103 HOST_WIDE_INT offset
;
12104 unsigned int mask
, regno
;
12106 /* Try to merge argument stores into the save instruction. */
12107 nargs
= mips16e_collect_argument_saves ();
12109 /* Build the save instruction. */
12110 mask
= frame
->mask
;
12111 rtx insn
= mips16e_build_save_restore (false, &mask
, &offset
,
12113 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12114 mips_frame_barrier ();
12117 /* Check if we need to save other registers. */
12118 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
12119 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
12121 offset
-= UNITS_PER_WORD
;
12122 mips_save_restore_reg (word_mode
, regno
,
12123 offset
, mips_save_reg
);
12128 if (cfun
->machine
->interrupt_handler_p
)
12130 HOST_WIDE_INT offset
;
12133 /* If this interrupt is using a shadow register set, we need to
12134 get the stack pointer from the previous register set. */
12135 if (cfun
->machine
->use_shadow_register_set
== SHADOW_SET_YES
)
12136 emit_insn (PMODE_INSN (gen_mips_rdpgpr
, (stack_pointer_rtx
,
12137 stack_pointer_rtx
)));
12139 if (!cfun
->machine
->keep_interrupts_masked_p
)
12141 if (cfun
->machine
->int_mask
== INT_MASK_EIC
)
12142 /* Move from COP0 Cause to K0. */
12143 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
12144 gen_rtx_REG (SImode
, COP0_CAUSE_REG_NUM
)));
12146 /* Move from COP0 EPC to K1. */
12147 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
12148 gen_rtx_REG (SImode
,
12149 COP0_EPC_REG_NUM
)));
12151 /* Allocate the first part of the frame. */
12152 rtx insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
12154 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12155 mips_frame_barrier ();
12158 /* Start at the uppermost location for saving. */
12159 offset
= frame
->cop0_sp_offset
- size
;
12161 /* Push EPC into its stack slot. */
12162 mem
= gen_frame_mem (word_mode
,
12163 plus_constant (Pmode
, stack_pointer_rtx
,
12165 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
12166 offset
-= UNITS_PER_WORD
;
12168 /* Move from COP0 Status to K1. */
12169 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
12170 gen_rtx_REG (SImode
,
12171 COP0_STATUS_REG_NUM
)));
12173 /* Right justify the RIPL in k0. */
12174 if (!cfun
->machine
->keep_interrupts_masked_p
12175 && cfun
->machine
->int_mask
== INT_MASK_EIC
)
12176 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
12177 gen_rtx_REG (SImode
, K0_REG_NUM
),
12178 GEN_INT (CAUSE_IPL
)));
12180 /* Push Status into its stack slot. */
12181 mem
= gen_frame_mem (word_mode
,
12182 plus_constant (Pmode
, stack_pointer_rtx
,
12184 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
12185 offset
-= UNITS_PER_WORD
;
12187 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
12188 if (!cfun
->machine
->keep_interrupts_masked_p
12189 && cfun
->machine
->int_mask
== INT_MASK_EIC
)
12190 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12193 gen_rtx_REG (SImode
, K0_REG_NUM
)));
12195 /* Clear all interrupt mask bits up to and including the
12196 handler's interrupt line. */
12197 if (!cfun
->machine
->keep_interrupts_masked_p
12198 && cfun
->machine
->int_mask
!= INT_MASK_EIC
)
12199 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12200 GEN_INT (cfun
->machine
->int_mask
+ 1),
12202 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12204 if (!cfun
->machine
->keep_interrupts_masked_p
)
12205 /* Enable interrupts by clearing the KSU ERL and EXL bits.
12206 IE is already the correct value, so we don't have to do
12207 anything explicit. */
12208 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12211 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12213 /* Disable interrupts by clearing the KSU, ERL, EXL,
12215 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12218 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12220 if (TARGET_HARD_FLOAT
)
12221 /* Disable COP1 for hard-float. This will lead to an exception
12222 if floating-point code is executed in an ISR. */
12223 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12226 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12232 rtx insn
= gen_add3_insn (stack_pointer_rtx
,
12235 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12236 mips_frame_barrier ();
12240 mips_for_each_saved_acc (size
, mips_save_reg
);
12241 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
12245 /* Allocate the rest of the frame. */
12248 if (SMALL_OPERAND (-size
))
12249 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
12251 GEN_INT (-size
)))) = 1;
12254 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
12257 /* There are no instructions to add or subtract registers
12258 from the stack pointer, so use the frame pointer as a
12259 temporary. We should always be using a frame pointer
12260 in this case anyway. */
12261 gcc_assert (frame_pointer_needed
);
12262 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12263 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
12264 hard_frame_pointer_rtx
,
12265 MIPS_PROLOGUE_TEMP (Pmode
)));
12266 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
12269 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
12271 MIPS_PROLOGUE_TEMP (Pmode
)));
12273 /* Describe the combined effect of the previous instructions. */
12274 mips_set_frame_expr
12275 (gen_rtx_SET (stack_pointer_rtx
,
12276 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
12278 mips_frame_barrier ();
12281 /* Set up the frame pointer, if we're using one. */
12282 if (frame_pointer_needed
)
12284 HOST_WIDE_INT offset
;
12286 offset
= frame
->hard_frame_pointer_offset
;
12289 rtx insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12290 RTX_FRAME_RELATED_P (insn
) = 1;
12292 else if (SMALL_OPERAND (offset
))
12294 rtx insn
= gen_add3_insn (hard_frame_pointer_rtx
,
12295 stack_pointer_rtx
, GEN_INT (offset
));
12296 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12300 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
12301 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12302 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
12303 hard_frame_pointer_rtx
,
12304 MIPS_PROLOGUE_TEMP (Pmode
)));
12305 mips_set_frame_expr
12306 (gen_rtx_SET (hard_frame_pointer_rtx
,
12307 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
12311 mips_emit_loadgp ();
12313 /* Initialize the $gp save slot. */
12314 if (mips_cfun_has_cprestore_slot_p ())
12316 rtx base
, mem
, gp
, temp
;
12317 HOST_WIDE_INT offset
;
12319 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
12320 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
12321 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
12322 temp
= (SMALL_OPERAND (offset
)
12323 ? gen_rtx_SCRATCH (Pmode
)
12324 : MIPS_PROLOGUE_TEMP (Pmode
));
12325 emit_insn (PMODE_INSN (gen_potential_cprestore
,
12326 (mem
, GEN_INT (offset
), gp
, temp
)));
12328 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12329 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
12330 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
12333 /* We need to search back to the last use of K0 or K1. */
12334 if (cfun
->machine
->interrupt_handler_p
)
12337 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
12339 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
12341 /* Emit a move from K1 to COP0 Status after insn. */
12342 gcc_assert (insn
!= NULL_RTX
);
12343 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
12344 gen_rtx_REG (SImode
, K1_REG_NUM
)),
12348 /* If we are profiling, make sure no instructions are scheduled before
12349 the call to mcount. */
12351 emit_insn (gen_blockage ());
12354 /* Attach all pending register saves to the previous instruction.
12355 Return that instruction. */
12358 mips_epilogue_emit_cfa_restores (void)
12362 insn
= get_last_insn ();
12363 if (mips_epilogue
.cfa_restores
)
12365 gcc_assert (insn
&& !REG_NOTES (insn
));
12366 RTX_FRAME_RELATED_P (insn
) = 1;
12367 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
12368 mips_epilogue
.cfa_restores
= 0;
12373 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
12374 now at REG + OFFSET. */
12377 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
12381 insn
= mips_epilogue_emit_cfa_restores ();
12382 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
12384 RTX_FRAME_RELATED_P (insn
) = 1;
12385 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
12386 plus_constant (Pmode
, reg
, offset
),
12388 mips_epilogue
.cfa_reg
= reg
;
12389 mips_epilogue
.cfa_offset
= offset
;
12393 /* Emit instructions to restore register REG from slot MEM. Also update
12394 the cfa_restores list. */
12397 mips_restore_reg (rtx reg
, rtx mem
)
12399 /* There's no MIPS16 instruction to load $31 directly. Load into
12400 $7 instead and adjust the return insn appropriately. */
12401 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
12402 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
12403 else if (GET_MODE (reg
) == DFmode
12404 && (!TARGET_FLOAT64
12405 || mips_abi
== ABI_32
))
12407 mips_add_cfa_restore (mips_subword (reg
, true));
12408 mips_add_cfa_restore (mips_subword (reg
, false));
12411 mips_add_cfa_restore (reg
);
12413 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
12414 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
12415 /* The CFA is currently defined in terms of the register whose
12416 value we have just restored. Redefine the CFA in terms of
12417 the stack pointer. */
12418 mips_epilogue_set_cfa (stack_pointer_rtx
,
12419 mips_epilogue
.cfa_restore_sp_offset
);
12422 /* Emit code to set the stack pointer to BASE + OFFSET, given that
12423 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
12424 BASE, if not the stack pointer, is available as a temporary. */
12427 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
12429 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
12432 mips_frame_barrier ();
12433 if (offset
== const0_rtx
)
12435 emit_move_insn (stack_pointer_rtx
, base
);
12436 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
12438 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
12440 emit_insn (gen_add3_insn (base
, base
, offset
));
12441 mips_epilogue_set_cfa (base
, new_frame_size
);
12442 emit_move_insn (stack_pointer_rtx
, base
);
12446 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
12447 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
12451 /* Emit any instructions needed before a return. */
12454 mips_expand_before_return (void)
12456 /* When using a call-clobbered gp, we start out with unified call
12457 insns that include instructions to restore the gp. We then split
12458 these unified calls after reload. These split calls explicitly
12459 clobber gp, so there is no need to define
12460 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
12462 For consistency, we should also insert an explicit clobber of $28
12463 before return insns, so that the post-reload optimizers know that
12464 the register is not live on exit. */
12465 if (TARGET_CALL_CLOBBERED_GP
)
12466 emit_clobber (pic_offset_table_rtx
);
12469 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
12473 mips_expand_epilogue (bool sibcall_p
)
12475 const struct mips_frame_info
*frame
;
12476 HOST_WIDE_INT step1
, step2
;
12479 bool use_jraddiusp_p
= false;
12481 if (!sibcall_p
&& mips_can_use_return_insn ())
12483 emit_jump_insn (gen_return ());
12487 /* In MIPS16 mode, if the return value should go into a floating-point
12488 register, we need to call a helper routine to copy it over. */
12489 if (mips16_cfun_returns_in_fpr_p ())
12490 mips16_copy_fpr_return_value ();
12492 /* Split the frame into two. STEP1 is the amount of stack we should
12493 deallocate before restoring the registers. STEP2 is the amount we
12494 should deallocate afterwards.
12496 Start off by assuming that no registers need to be restored. */
12497 frame
= &cfun
->machine
->frame
;
12498 step1
= frame
->total_size
;
12501 /* Work out which register holds the frame address. */
12502 if (!frame_pointer_needed
)
12503 base
= stack_pointer_rtx
;
12506 base
= hard_frame_pointer_rtx
;
12507 step1
-= frame
->hard_frame_pointer_offset
;
12509 mips_epilogue
.cfa_reg
= base
;
12510 mips_epilogue
.cfa_offset
= step1
;
12511 mips_epilogue
.cfa_restores
= NULL_RTX
;
12513 /* If we need to restore registers, deallocate as much stack as
12514 possible in the second step without going out of range. */
12515 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
12516 || frame
->num_cop0_regs
> 0)
12518 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
12522 /* Get an rtx for STEP1 that we can add to BASE. */
12523 adjust
= GEN_INT (step1
);
12524 if (!SMALL_OPERAND (step1
))
12526 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
12527 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
12529 mips_deallocate_stack (base
, adjust
, step2
);
12531 /* If we're using addressing macros, $gp is implicitly used by all
12532 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
12534 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
12535 emit_insn (gen_blockage ());
12537 mips_epilogue
.cfa_restore_sp_offset
= step2
;
12538 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
12540 unsigned int regno
, mask
;
12541 HOST_WIDE_INT offset
;
12544 /* Generate the restore instruction. */
12545 mask
= frame
->mask
;
12546 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
12548 /* Restore any other registers manually. */
12549 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
12550 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
12552 offset
-= UNITS_PER_WORD
;
12553 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
12556 /* Restore the remaining registers and deallocate the final bit
12558 mips_frame_barrier ();
12559 emit_insn (restore
);
12560 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
12564 /* Restore the registers. */
12565 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
12566 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
12569 if (cfun
->machine
->interrupt_handler_p
)
12571 HOST_WIDE_INT offset
;
12574 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
12576 /* Restore the original EPC. */
12577 mem
= gen_frame_mem (word_mode
,
12578 plus_constant (Pmode
, stack_pointer_rtx
,
12580 mips_emit_move (gen_rtx_REG (word_mode
, K1_REG_NUM
), mem
);
12581 offset
-= UNITS_PER_WORD
;
12583 /* Move to COP0 EPC. */
12584 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
12585 gen_rtx_REG (SImode
, K1_REG_NUM
)));
12587 /* Restore the original Status. */
12588 mem
= gen_frame_mem (word_mode
,
12589 plus_constant (Pmode
, stack_pointer_rtx
,
12591 mips_emit_move (gen_rtx_REG (word_mode
, K1_REG_NUM
), mem
);
12592 offset
-= UNITS_PER_WORD
;
12594 /* If we don't use shadow register set, we need to update SP. */
12595 if (cfun
->machine
->use_shadow_register_set
== SHADOW_SET_NO
)
12596 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
12598 /* The choice of position is somewhat arbitrary in this case. */
12599 mips_epilogue_emit_cfa_restores ();
12601 /* Move to COP0 Status. */
12602 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
12603 gen_rtx_REG (SImode
, K1_REG_NUM
)));
12605 else if (TARGET_MICROMIPS
12606 && !crtl
->calls_eh_return
12609 && mips_unsigned_immediate_p (step2
, 5, 2))
12610 use_jraddiusp_p
= true;
12612 /* Deallocate the final bit of the frame. */
12613 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
12616 if (cfun
->machine
->use_frame_header_for_callee_saved_regs
)
12617 mips_epilogue_emit_cfa_restores ();
12618 else if (!use_jraddiusp_p
)
12619 gcc_assert (!mips_epilogue
.cfa_restores
);
12621 /* Add in the __builtin_eh_return stack adjustment. We need to
12622 use a temporary in MIPS16 code. */
12623 if (crtl
->calls_eh_return
)
12627 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
12628 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
12629 MIPS_EPILOGUE_TEMP (Pmode
),
12630 EH_RETURN_STACKADJ_RTX
));
12631 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
12634 emit_insn (gen_add3_insn (stack_pointer_rtx
,
12636 EH_RETURN_STACKADJ_RTX
));
12641 mips_expand_before_return ();
12642 if (cfun
->machine
->interrupt_handler_p
)
12644 /* Interrupt handlers generate eret or deret. */
12645 if (cfun
->machine
->use_debug_exception_return_p
)
12646 emit_jump_insn (gen_mips_deret ());
12648 emit_jump_insn (gen_mips_eret ());
12654 /* When generating MIPS16 code, the normal
12655 mips_for_each_saved_gpr_and_fpr path will restore the return
12656 address into $7 rather than $31. */
12658 && !GENERATE_MIPS16E_SAVE_RESTORE
12659 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
12661 /* simple_returns cannot rely on values that are only available
12662 on paths through the epilogue (because return paths that do
12663 not pass through the epilogue may nevertheless reuse a
12664 simple_return that occurs at the end of the epilogue).
12665 Use a normal return here instead. */
12666 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
12667 pat
= gen_return_internal (reg
);
12669 else if (use_jraddiusp_p
)
12670 pat
= gen_jraddiusp (GEN_INT (step2
));
12673 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
12674 pat
= gen_simple_return_internal (reg
);
12676 emit_jump_insn (pat
);
12677 if (use_jraddiusp_p
)
12678 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
12682 /* Search from the beginning to the first use of K0 or K1. */
12683 if (cfun
->machine
->interrupt_handler_p
12684 && !cfun
->machine
->keep_interrupts_masked_p
)
12686 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
12688 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
12690 gcc_assert (insn
!= NULL_RTX
);
12691 /* Insert disable interrupts before the first use of K0 or K1. */
12692 emit_insn_before (gen_mips_di (), insn
);
12693 emit_insn_before (gen_mips_ehb (), insn
);
12697 /* Return nonzero if this function is known to have a null epilogue.
12698 This allows the optimizer to omit jumps to jumps if no stack
12702 mips_can_use_return_insn (void)
12704 /* Interrupt handlers need to go through the epilogue. */
12705 if (cfun
->machine
->interrupt_handler_p
)
12708 if (!reload_completed
)
12714 /* In MIPS16 mode, a function that returns a floating-point value
12715 needs to arrange to copy the return value into the floating-point
12717 if (mips16_cfun_returns_in_fpr_p ())
12720 return (cfun
->machine
->frame
.total_size
== 0
12721 && !cfun
->machine
->use_frame_header_for_callee_saved_regs
);
12724 /* Return true if register REGNO can store a value of mode MODE.
12725 The result of this function is cached in mips_hard_regno_mode_ok. */
12728 mips_hard_regno_mode_ok_p (unsigned int regno
, machine_mode mode
)
12731 enum mode_class mclass
;
12733 if (mode
== CCV2mode
)
12734 return (ISA_HAS_8CC
12735 && ST_REG_P (regno
)
12736 && (regno
- ST_REG_FIRST
) % 2 == 0);
12738 if (mode
== CCV4mode
)
12739 return (ISA_HAS_8CC
12740 && ST_REG_P (regno
)
12741 && (regno
- ST_REG_FIRST
) % 4 == 0);
12743 if (mode
== CCmode
)
12744 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
12746 size
= GET_MODE_SIZE (mode
);
12747 mclass
= GET_MODE_CLASS (mode
);
12749 if (GP_REG_P (regno
) && mode
!= CCFmode
&& !MSA_SUPPORTED_MODE_P (mode
))
12750 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
12752 /* For MSA, allow TImode and 128-bit vector modes in all FPR. */
12753 if (FP_REG_P (regno
) && MSA_SUPPORTED_MODE_P (mode
))
12756 if (FP_REG_P (regno
)
12757 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
12758 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
12760 /* Deny use of odd-numbered registers for 32-bit data for
12761 the o32 FP64A ABI. */
12762 if (TARGET_O32_FP64A_ABI
&& size
<= 4 && (regno
& 1) != 0)
12765 /* The FPXX ABI requires double-precision values to be placed in
12766 even-numbered registers. Disallow odd-numbered registers with
12767 CCFmode because CCFmode double-precision compares will write a
12768 64-bit value to a register. */
12769 if (mode
== CCFmode
)
12770 return !(TARGET_FLOATXX
&& (regno
& 1) != 0);
12772 /* Allow 64-bit vector modes for Loongson-2E/2F. */
12773 if (TARGET_LOONGSON_VECTORS
12774 && (mode
== V2SImode
12775 || mode
== V4HImode
12776 || mode
== V8QImode
12777 || mode
== DImode
))
12780 if (mclass
== MODE_FLOAT
12781 || mclass
== MODE_COMPLEX_FLOAT
12782 || mclass
== MODE_VECTOR_FLOAT
)
12783 return size
<= UNITS_PER_FPVALUE
;
12785 /* Allow integer modes that fit into a single register. We need
12786 to put integers into FPRs when using instructions like CVT
12787 and TRUNC. There's no point allowing sizes smaller than a word,
12788 because the FPU has no appropriate load/store instructions. */
12789 if (mclass
== MODE_INT
)
12790 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
12793 /* Don't allow vector modes in accumulators. */
12794 if (ACC_REG_P (regno
)
12795 && !VECTOR_MODE_P (mode
)
12796 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
12798 if (MD_REG_P (regno
))
12800 /* After a multiplication or division, clobbering HI makes
12801 the value of LO unpredictable, and vice versa. This means
12802 that, for all interesting cases, HI and LO are effectively
12805 We model this by requiring that any value that uses HI
12807 if (size
<= UNITS_PER_WORD
* 2)
12808 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
12812 /* DSP accumulators do not have the same restrictions as
12813 HI and LO, so we can treat them as normal doubleword
12815 if (size
<= UNITS_PER_WORD
)
12818 if (size
<= UNITS_PER_WORD
* 2
12819 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
12824 if (ALL_COP_REG_P (regno
))
12825 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
12827 if (regno
== GOT_VERSION_REGNUM
)
12828 return mode
== SImode
;
12833 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
12836 mips_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
12837 unsigned int new_reg
)
12839 /* Interrupt functions can only use registers that have already been
12840 saved by the prologue, even if they would normally be call-clobbered. */
12841 if (cfun
->machine
->interrupt_handler_p
&& !df_regs_ever_live_p (new_reg
))
12847 /* Return nonzero if register REGNO can be used as a scratch register
12851 mips_hard_regno_scratch_ok (unsigned int regno
)
12853 /* See mips_hard_regno_rename_ok. */
12854 if (cfun
->machine
->interrupt_handler_p
&& !df_regs_ever_live_p (regno
))
12860 /* Implement HARD_REGNO_NREGS. */
12863 mips_hard_regno_nregs (int regno
, machine_mode mode
)
12865 if (ST_REG_P (regno
))
12866 /* The size of FP status registers is always 4, because they only hold
12867 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12868 return (GET_MODE_SIZE (mode
) + 3) / 4;
12870 if (FP_REG_P (regno
))
12872 if (MSA_SUPPORTED_MODE_P (mode
))
12875 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
12878 /* All other registers are word-sized. */
12879 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
12882 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12883 in mips_hard_regno_nregs. */
12886 mips_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
12892 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
12893 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
12895 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
12896 size
= MIN (size
, 4);
12898 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
12900 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
12902 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
12904 if (MSA_SUPPORTED_MODE_P (mode
))
12905 size
= MIN (size
, UNITS_PER_MSA_REG
);
12907 size
= MIN (size
, UNITS_PER_FPREG
);
12910 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
12912 if (!hard_reg_set_empty_p (left
))
12913 size
= MIN (size
, UNITS_PER_WORD
);
12914 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
12917 /* Implement CANNOT_CHANGE_MODE_CLASS. */
12920 mips_cannot_change_mode_class (machine_mode from
,
12922 enum reg_class rclass
)
12924 /* Allow conversions between different Loongson integer vectors,
12925 and between those vectors and DImode. */
12926 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
12927 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
12930 /* Allow conversions between different MSA vector modes. */
12931 if (MSA_SUPPORTED_MODE_P (from
) && MSA_SUPPORTED_MODE_P (to
))
12934 /* Otherwise, there are several problems with changing the modes of
12935 values in floating-point registers:
12937 - When a multi-word value is stored in paired floating-point
12938 registers, the first register always holds the low word. We
12939 therefore can't allow FPRs to change between single-word and
12940 multi-word modes on big-endian targets.
12942 - GCC assumes that each word of a multiword register can be
12943 accessed individually using SUBREGs. This is not true for
12944 floating-point registers if they are bigger than a word.
12946 - Loading a 32-bit value into a 64-bit floating-point register
12947 will not sign-extend the value, despite what LOAD_EXTEND_OP
12948 says. We can't allow FPRs to change from SImode to a wider
12949 mode on 64-bit targets.
12951 - If the FPU has already interpreted a value in one format, we
12952 must not ask it to treat the value as having a different
12955 We therefore disallow all mode changes involving FPRs. */
12957 return reg_classes_intersect_p (FP_REGS
, rclass
);
12960 /* Implement target hook small_register_classes_for_mode_p. */
12963 mips_small_register_classes_for_mode_p (machine_mode mode
12966 return TARGET_MIPS16
;
12969 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction,
12970 or use the MSA's move.v instruction. */
12973 mips_mode_ok_for_mov_fmt_p (machine_mode mode
)
12979 return TARGET_HARD_FLOAT
;
12982 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
12985 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
12988 return MSA_SUPPORTED_MODE_P (mode
);
12992 /* Implement MODES_TIEABLE_P. */
12995 mips_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
12997 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
12998 prefer to put one of them in FPRs. */
12999 return (mode1
== mode2
13000 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
13001 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
13004 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
13007 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
13009 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
13012 if (reg_class_subset_p (FP_REGS
, rclass
)
13013 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
13016 if (reg_class_subset_p (GR_REGS
, rclass
))
13019 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
13025 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
13026 Return a "canonical" class to represent it in later calculations. */
13029 mips_canonicalize_move_class (reg_class_t rclass
)
13031 /* All moves involving accumulator registers have the same cost. */
13032 if (reg_class_subset_p (rclass
, ACC_REGS
))
13035 /* Likewise promote subclasses of general registers to the most
13036 interesting containing class. */
13037 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
13039 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
13040 rclass
= GENERAL_REGS
;
13045 /* Return the cost of moving a value from a register of class FROM to a GPR.
13046 Return 0 for classes that are unions of other classes handled by this
13050 mips_move_to_gpr_cost (reg_class_t from
)
13056 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13060 /* MFLO and MFHI. */
13070 /* This choice of value is historical. */
13078 /* Return the cost of moving a value from a GPR to a register of class TO.
13079 Return 0 for classes that are unions of other classes handled by this
13083 mips_move_from_gpr_cost (reg_class_t to
)
13089 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13093 /* MTLO and MTHI. */
13103 /* This choice of value is historical. */
13111 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
13112 maximum of the move costs for subclasses; regclass will work out
13113 the maximum for us. */
13116 mips_register_move_cost (machine_mode mode
,
13117 reg_class_t from
, reg_class_t to
)
13122 from
= mips_canonicalize_move_class (from
);
13123 to
= mips_canonicalize_move_class (to
);
13125 /* Handle moves that can be done without using general-purpose registers. */
13126 if (from
== FP_REGS
)
13128 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
13133 /* Handle cases in which only one class deviates from the ideal. */
13134 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
13136 return mips_move_from_gpr_cost (to
);
13138 return mips_move_to_gpr_cost (from
);
13140 /* Handles cases that require a GPR temporary. */
13141 cost1
= mips_move_to_gpr_cost (from
);
13144 cost2
= mips_move_from_gpr_cost (to
);
13146 return cost1
+ cost2
;
13152 /* Implement TARGET_REGISTER_PRIORITY. */
13155 mips_register_priority (int hard_regno
)
13157 /* Treat MIPS16 registers with higher priority than other regs. */
13159 && TEST_HARD_REG_BIT (reg_class_contents
[M16_REGS
], hard_regno
))
13164 /* Implement TARGET_MEMORY_MOVE_COST. */
13167 mips_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
13169 return (mips_cost
->memory_latency
13170 + memory_move_secondary_cost (mode
, rclass
, in
));
13173 /* Implement SECONDARY_MEMORY_NEEDED. */
13176 mips_secondary_memory_needed (enum reg_class class1
, enum reg_class class2
,
13179 /* Ignore spilled pseudos. */
13180 if (lra_in_progress
&& (class1
== NO_REGS
|| class2
== NO_REGS
))
13183 if (((class1
== FP_REGS
) != (class2
== FP_REGS
))
13184 && ((TARGET_FLOATXX
&& !ISA_HAS_MXHC1
)
13185 || TARGET_O32_FP64A_ABI
)
13186 && GET_MODE_SIZE (mode
) >= 8)
13192 /* Return the register class required for a secondary register when
13193 copying between one of the registers in RCLASS and value X, which
13194 has mode MODE. X is the source of the move if IN_P, otherwise it
13195 is the destination. Return NO_REGS if no secondary register is
13199 mips_secondary_reload_class (enum reg_class rclass
,
13200 machine_mode mode
, rtx x
, bool)
13204 /* If X is a constant that cannot be loaded into $25, it must be loaded
13205 into some other GPR. No other register class allows a direct move. */
13206 if (mips_dangerous_for_la25_p (x
))
13207 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
13209 regno
= true_regnum (x
);
13212 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
13213 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
13219 /* Copying from accumulator registers to anywhere other than a general
13220 register requires a temporary general register. */
13221 if (reg_class_subset_p (rclass
, ACC_REGS
))
13222 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
13223 if (ACC_REG_P (regno
))
13224 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
13226 if (reg_class_subset_p (rclass
, FP_REGS
))
13230 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)))
13231 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
13232 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
13235 if (MEM_P (x
) && MSA_SUPPORTED_MODE_P (mode
))
13236 /* In this case we can use MSA LD.* and ST.*. */
13239 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
13240 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
13243 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
13244 /* We can force the constant to memory and use lwc1
13245 and ldc1. As above, we will use pairs of lwc1s if
13246 ldc1 is not supported. */
13249 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
13250 /* In this case we can use mov.fmt. */
13253 /* Otherwise, we need to reload through an integer register. */
13256 if (FP_REG_P (regno
))
13257 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
13262 /* Implement TARGET_MODE_REP_EXTENDED. */
13265 mips_mode_rep_extended (machine_mode mode
, machine_mode mode_rep
)
13267 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
13268 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
13269 return SIGN_EXTEND
;
13274 /* Implement TARGET_VALID_POINTER_MODE. */
13277 mips_valid_pointer_mode (machine_mode mode
)
13279 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
13282 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
13285 mips_vector_mode_supported_p (machine_mode mode
)
13290 return TARGET_PAIRED_SINGLE_FLOAT
;
13305 return TARGET_LOONGSON_VECTORS
;
13308 return MSA_SUPPORTED_MODE_P (mode
);
13312 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
13315 mips_scalar_mode_supported_p (machine_mode mode
)
13317 if (ALL_FIXED_POINT_MODE_P (mode
)
13318 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
13321 return default_scalar_mode_supported_p (mode
);
13324 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
13326 static machine_mode
13327 mips_preferred_simd_mode (machine_mode mode
)
13329 if (TARGET_PAIRED_SINGLE_FLOAT
13359 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. */
13361 static unsigned int
13362 mips_autovectorize_vector_sizes (void)
13364 return ISA_HAS_MSA
? 16 : 0;
13367 /* Implement TARGET_INIT_LIBFUNCS. */
13370 mips_init_libfuncs (void)
13372 if (TARGET_FIX_VR4120
)
13374 /* Register the special divsi3 and modsi3 functions needed to work
13375 around VR4120 division errata. */
13376 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
13377 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
13380 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
13382 /* Register the MIPS16 -mhard-float stubs. */
13383 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
13384 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
13385 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
13386 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
13388 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
13389 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
13390 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
13391 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
13392 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
13393 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
13394 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
13396 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
13397 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
13398 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
13400 if (TARGET_DOUBLE_FLOAT
)
13402 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
13403 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
13404 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
13405 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
13407 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
13408 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
13409 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
13410 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
13411 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
13412 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
13413 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
13415 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
13416 "__mips16_extendsfdf2");
13417 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
13418 "__mips16_truncdfsf2");
13419 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
13420 "__mips16_fix_truncdfsi");
13421 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
13422 "__mips16_floatsidf");
13423 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
13424 "__mips16_floatunsidf");
13428 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
13429 on an external non-MIPS16 routine to implement __sync_synchronize.
13430 Similarly for the rest of the ll/sc libfuncs. */
13433 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
13434 init_sync_libfuncs (UNITS_PER_WORD
);
13438 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
13441 mips_process_load_label (rtx target
)
13443 rtx base
, gp
, intop
;
13444 HOST_WIDE_INT offset
;
13446 mips_multi_start ();
13450 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
13451 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
13455 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
13456 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
13460 gp
= pic_offset_table_rtx
;
13461 if (mips_cfun_has_cprestore_slot_p ())
13463 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
13464 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
13465 if (!SMALL_OPERAND (offset
))
13467 intop
= GEN_INT (CONST_HIGH_PART (offset
));
13468 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
13469 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
13472 offset
= CONST_LOW_PART (offset
);
13474 intop
= GEN_INT (offset
);
13475 if (ISA_HAS_LOAD_DELAY
)
13476 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
13478 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
13480 if (ISA_HAS_LOAD_DELAY
)
13481 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
13483 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
13484 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
13489 /* Return the number of instructions needed to load a label into $AT. */
13491 static unsigned int
13492 mips_load_label_num_insns (void)
13494 if (cfun
->machine
->load_label_num_insns
== 0)
13496 mips_process_load_label (pc_rtx
);
13497 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
13499 return cfun
->machine
->load_label_num_insns
;
13502 /* Emit an asm sequence to start a noat block and load the address
13503 of a label into $1. */
13506 mips_output_load_label (rtx target
)
13508 mips_push_asm_switch (&mips_noat
);
13509 if (TARGET_EXPLICIT_RELOCS
)
13511 mips_process_load_label (target
);
13512 mips_multi_write ();
13516 if (Pmode
== DImode
)
13517 output_asm_insn ("dla\t%@,%0", &target
);
13519 output_asm_insn ("la\t%@,%0", &target
);
13523 /* Return the length of INSN. LENGTH is the initial length computed by
13524 attributes in the machine-description file. */
13527 mips_adjust_insn_length (rtx_insn
*insn
, int length
)
13529 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
13530 of a PIC long-branch sequence. Substitute the correct value. */
13531 if (length
== MAX_PIC_BRANCH_LENGTH
13533 && INSN_CODE (insn
) >= 0
13534 && get_attr_type (insn
) == TYPE_BRANCH
)
13536 /* Add the branch-over instruction and its delay slot, if this
13537 is a conditional branch. */
13538 length
= simplejump_p (insn
) ? 0 : 8;
13540 /* Add the size of a load into $AT. */
13541 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
13543 /* Add the length of an indirect jump, ignoring the delay slot. */
13544 length
+= TARGET_COMPRESSION
? 2 : 4;
13547 /* A unconditional jump has an unfilled delay slot if it is not part
13548 of a sequence. A conditional jump normally has a delay slot, but
13549 does not on MIPS16. */
13550 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
13551 length
+= TARGET_MIPS16
? 2 : 4;
13553 /* See how many nops might be needed to avoid hardware hazards. */
13554 if (!cfun
->machine
->ignore_hazard_length_p
13556 && INSN_CODE (insn
) >= 0)
13557 switch (get_attr_hazard (insn
))
13563 case HAZARD_FORBIDDEN_SLOT
:
13564 length
+= NOP_INSN_LENGTH
;
13568 length
+= NOP_INSN_LENGTH
* 2;
13575 /* Return the asm template for a call. OPERANDS are the operands, TARGET_OPNO
13576 is the operand number of the target. SIZE_OPNO is the operand number of
13577 the argument size operand that can optionally hold the call attributes. If
13578 SIZE_OPNO is not -1 and the call is indirect, use the function symbol from
13579 the call attributes to attach a R_MIPS_JALR relocation to the call. LINK_P
13580 indicates whether the jump is a call and needs to set the link register.
13582 When generating GOT code without explicit relocation operators, all calls
13583 should use assembly macros. Otherwise, all indirect calls should use "jr"
13584 or "jalr"; we will arrange to restore $gp afterwards if necessary. Finally,
13585 we can only generate direct calls for -mabicalls by temporarily switching
13588 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
13589 instruction is in the delay slot of jal(r).
13591 Where compact branches are available, we try to use them if the delay slot
13592 has a NOP (or equivalently delay slots were not enabled for the instruction
13596 mips_output_jump (rtx
*operands
, int target_opno
, int size_opno
, bool link_p
)
13598 static char buffer
[300];
13600 bool reg_p
= REG_P (operands
[target_opno
]);
13602 const char *and_link
= link_p
? "al" : "";
13603 const char *reg
= reg_p
? "r" : "";
13604 const char *compact
= "";
13605 const char *nop
= "%/";
13606 const char *short_delay
= link_p
? "%!" : "";
13607 const char *insn_name
= TARGET_CB_NEVER
|| reg_p
? "j" : "b";
13609 /* Compact branches can only be described when the ISA has support for them
13610 as both the compact formatter '%:' and the delay slot NOP formatter '%/'
13611 work as a mutually exclusive pair. I.e. a NOP is never required if a
13612 compact form is available. */
13613 if (!final_sequence
13614 && (TARGET_CB_MAYBE
13615 || (ISA_HAS_JRC
&& !link_p
&& reg_p
)))
13621 if (TARGET_USE_GOT
&& !TARGET_EXPLICIT_RELOCS
)
13622 sprintf (s
, "%%*%s%s\t%%%d%%/", insn_name
, and_link
, target_opno
);
13625 if (!reg_p
&& TARGET_ABICALLS_PIC2
)
13626 s
+= sprintf (s
, ".option\tpic0\n\t");
13628 if (reg_p
&& mips_get_pic_call_symbol (operands
, size_opno
))
13629 s
+= sprintf (s
, "%%*.reloc\t1f,%s,%%%d\n1:\t",
13630 TARGET_MICROMIPS
? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
13633 s
+= sprintf (s
, "%%*");
13635 s
+= sprintf (s
, "%s%s%s%s%s\t%%%d%s",
13636 insn_name
, and_link
, reg
, compact
, short_delay
,
13639 if (!reg_p
&& TARGET_ABICALLS_PIC2
)
13640 s
+= sprintf (s
, "\n\t.option\tpic2");
13645 /* Return the assembly code for INSN, which has the operands given by
13646 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
13647 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
13648 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
13649 version of BRANCH_IF_TRUE. */
13652 mips_output_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
13653 const char *branch_if_true
,
13654 const char *branch_if_false
)
13656 unsigned int length
;
13659 gcc_assert (LABEL_P (operands
[0]));
13661 length
= get_attr_length (insn
);
13664 /* Just a simple conditional branch. */
13665 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
13666 return branch_if_true
;
13669 /* Generate a reversed branch around a direct jump. This fallback does
13670 not use branch-likely instructions. */
13671 mips_branch_likely
= false;
13672 rtx_code_label
*not_taken
= gen_label_rtx ();
13673 taken
= operands
[0];
13675 /* Generate the reversed branch to NOT_TAKEN. */
13676 operands
[0] = not_taken
;
13677 output_asm_insn (branch_if_false
, operands
);
13679 /* If INSN has a delay slot, we must provide delay slots for both the
13680 branch to NOT_TAKEN and the conditional jump. We must also ensure
13681 that INSN's delay slot is executed in the appropriate cases. */
13682 if (final_sequence
)
13684 /* This first delay slot will always be executed, so use INSN's
13685 delay slot if is not annulled. */
13686 if (!INSN_ANNULLED_BRANCH_P (insn
))
13688 final_scan_insn (final_sequence
->insn (1),
13689 asm_out_file
, optimize
, 1, NULL
);
13690 final_sequence
->insn (1)->set_deleted ();
13693 output_asm_insn ("nop", 0);
13694 fprintf (asm_out_file
, "\n");
13697 /* Output the unconditional branch to TAKEN. */
13698 if (TARGET_ABSOLUTE_JUMPS
&& TARGET_CB_MAYBE
)
13700 /* Add a hazard nop. */
13701 if (!final_sequence
)
13703 output_asm_insn ("nop\t\t# hazard nop", 0);
13704 fprintf (asm_out_file
, "\n");
13706 output_asm_insn (MIPS_ABSOLUTE_JUMP ("bc\t%0"), &taken
);
13708 else if (TARGET_ABSOLUTE_JUMPS
)
13709 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
13712 mips_output_load_label (taken
);
13713 if (TARGET_CB_MAYBE
)
13714 output_asm_insn ("jrc\t%@%]", 0);
13716 output_asm_insn ("jr\t%@%]%/", 0);
13719 /* Now deal with its delay slot; see above. */
13720 if (final_sequence
)
13722 /* This delay slot will only be executed if the branch is taken.
13723 Use INSN's delay slot if is annulled. */
13724 if (INSN_ANNULLED_BRANCH_P (insn
))
13726 final_scan_insn (final_sequence
->insn (1),
13727 asm_out_file
, optimize
, 1, NULL
);
13728 final_sequence
->insn (1)->set_deleted ();
13730 else if (TARGET_CB_NEVER
)
13731 output_asm_insn ("nop", 0);
13732 fprintf (asm_out_file
, "\n");
13735 /* Output NOT_TAKEN. */
13736 targetm
.asm_out
.internal_label (asm_out_file
, "L",
13737 CODE_LABEL_NUMBER (not_taken
));
13741 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13742 if some equality condition is true. The condition is given by
13743 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13744 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13745 OPERANDS[3] is the second operand and may be zero or a register. */
13748 mips_output_equal_conditional_branch (rtx_insn
* insn
, rtx
*operands
,
13751 const char *branch
[2];
13752 /* For a simple BNEZ or BEQZ microMIPSr3 branch. */
13753 if (TARGET_MICROMIPS
13754 && mips_isa_rev
<= 5
13755 && operands
[3] == const0_rtx
13756 && get_attr_length (insn
) <= 8)
13758 if (mips_cb
== MIPS_CB_OPTIMAL
)
13760 branch
[!inverted_p
] = "%*b%C1z%:\t%2,%0";
13761 branch
[inverted_p
] = "%*b%N1z%:\t%2,%0";
13765 branch
[!inverted_p
] = "%*b%C1z\t%2,%0%/";
13766 branch
[inverted_p
] = "%*b%N1z\t%2,%0%/";
13769 else if (TARGET_CB_MAYBE
)
13771 if (operands
[3] == const0_rtx
)
13773 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13774 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13776 else if (REGNO (operands
[2]) != REGNO (operands
[3]))
13778 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13779 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13783 /* This case is degenerate. It should not happen, but does. */
13784 if (GET_CODE (operands
[1]) == NE
)
13785 inverted_p
= !inverted_p
;
13787 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13788 branch
[inverted_p
] = "%*\t\t# branch never";
13793 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1", "%2,%z3,%0");
13794 branch
[inverted_p
] = MIPS_BRANCH ("b%N1", "%2,%z3,%0");
13797 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
13800 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13801 if some ordering condition is true. The condition is given by
13802 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13803 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13804 OPERANDS[3] is the second operand and may be zero or a register. */
13807 mips_output_order_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
13810 const char *branch
[2];
13812 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
13813 Make BRANCH[0] branch on the inverse condition. */
13814 if (operands
[3] != const0_rtx
)
13816 /* Handle degenerate cases that should not, but do, occur. */
13817 if (REGNO (operands
[2]) == REGNO (operands
[3]))
13819 switch (GET_CODE (operands
[1]))
13823 inverted_p
= !inverted_p
;
13824 /* Fall through. */
13827 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13828 branch
[inverted_p
] = "%*\t\t# branch never";
13831 gcc_unreachable ();
13836 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13837 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13842 switch (GET_CODE (operands
[1]))
13844 /* These cases are equivalent to comparisons against zero. */
13846 inverted_p
= !inverted_p
;
13847 /* Fall through. */
13849 if (TARGET_CB_MAYBE
)
13851 branch
[!inverted_p
] = MIPS_BRANCH_C ("bnez", "%2,%0");
13852 branch
[inverted_p
] = MIPS_BRANCH_C ("beqz", "%2,%0");
13856 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
13857 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
13861 /* These cases are always true or always false. */
13863 inverted_p
= !inverted_p
;
13864 /* Fall through. */
13866 if (TARGET_CB_MAYBE
)
13868 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13869 branch
[inverted_p
] = "%*\t\t# branch never";
13873 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
13874 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
13879 if (TARGET_CB_MAYBE
)
13881 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13882 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13886 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
13887 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
13892 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
13895 /* Start a block of code that needs access to the LL, SC and SYNC
13899 mips_start_ll_sc_sync_block (void)
13901 if (!ISA_HAS_LL_SC
)
13903 output_asm_insn (".set\tpush", 0);
13905 output_asm_insn (".set\tmips3", 0);
13907 output_asm_insn (".set\tmips2", 0);
13911 /* End a block started by mips_start_ll_sc_sync_block. */
13914 mips_end_ll_sc_sync_block (void)
13916 if (!ISA_HAS_LL_SC
)
13917 output_asm_insn (".set\tpop", 0);
13920 /* Output and/or return the asm template for a sync instruction. */
13923 mips_output_sync (void)
13925 mips_start_ll_sc_sync_block ();
13926 output_asm_insn ("sync", 0);
13927 mips_end_ll_sc_sync_block ();
13931 /* Return the asm template associated with sync_insn1 value TYPE.
13932 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
13934 static const char *
13935 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
13939 case SYNC_INSN1_MOVE
:
13940 return "move\t%0,%z2";
13941 case SYNC_INSN1_LI
:
13942 return "li\t%0,%2";
13943 case SYNC_INSN1_ADDU
:
13944 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
13945 case SYNC_INSN1_ADDIU
:
13946 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
13947 case SYNC_INSN1_SUBU
:
13948 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
13949 case SYNC_INSN1_AND
:
13950 return "and\t%0,%1,%z2";
13951 case SYNC_INSN1_ANDI
:
13952 return "andi\t%0,%1,%2";
13953 case SYNC_INSN1_OR
:
13954 return "or\t%0,%1,%z2";
13955 case SYNC_INSN1_ORI
:
13956 return "ori\t%0,%1,%2";
13957 case SYNC_INSN1_XOR
:
13958 return "xor\t%0,%1,%z2";
13959 case SYNC_INSN1_XORI
:
13960 return "xori\t%0,%1,%2";
13962 gcc_unreachable ();
13965 /* Return the asm template associated with sync_insn2 value TYPE. */
13967 static const char *
13968 mips_sync_insn2_template (enum attr_sync_insn2 type
)
13972 case SYNC_INSN2_NOP
:
13973 gcc_unreachable ();
13974 case SYNC_INSN2_AND
:
13975 return "and\t%0,%1,%z2";
13976 case SYNC_INSN2_XOR
:
13977 return "xor\t%0,%1,%z2";
13978 case SYNC_INSN2_NOT
:
13979 return "nor\t%0,%1,%.";
13981 gcc_unreachable ();
13984 /* OPERANDS are the operands to a sync loop instruction and INDEX is
13985 the value of the one of the sync_* attributes. Return the operand
13986 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
13987 have the associated attribute. */
13990 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
13993 default_value
= operands
[index
- 1];
13994 return default_value
;
13997 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
13998 sequence for it. */
14001 mips_process_sync_loop (rtx_insn
*insn
, rtx
*operands
)
14003 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
14004 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
14005 unsigned int tmp3_insn
;
14006 enum attr_sync_insn1 insn1
;
14007 enum attr_sync_insn2 insn2
;
14010 enum memmodel model
;
14012 /* Read an operand from the sync_WHAT attribute and store it in
14013 variable WHAT. DEFAULT is the default value if no attribute
14015 #define READ_OPERAND(WHAT, DEFAULT) \
14016 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
14019 /* Read the memory. */
14020 READ_OPERAND (mem
, 0);
14022 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
14024 /* Read the other attributes. */
14025 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
14026 READ_OPERAND (oldval
, at
);
14027 READ_OPERAND (cmp
, 0);
14028 READ_OPERAND (newval
, at
);
14029 READ_OPERAND (inclusive_mask
, 0);
14030 READ_OPERAND (exclusive_mask
, 0);
14031 READ_OPERAND (required_oldval
, 0);
14032 READ_OPERAND (insn1_op2
, 0);
14033 insn1
= get_attr_sync_insn1 (insn
);
14034 insn2
= get_attr_sync_insn2 (insn
);
14036 /* Don't bother setting CMP result that is never used. */
14037 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
14040 memmodel_attr
= get_attr_sync_memmodel (insn
);
14041 switch (memmodel_attr
)
14044 model
= MEMMODEL_ACQ_REL
;
14047 model
= MEMMODEL_ACQUIRE
;
14050 model
= memmodel_from_int (INTVAL (operands
[memmodel_attr
]));
14053 mips_multi_start ();
14055 /* Output the release side of the memory barrier. */
14056 if (need_atomic_barrier_p (model
, true))
14058 if (required_oldval
== 0 && TARGET_OCTEON
)
14060 /* Octeon doesn't reorder reads, so a full barrier can be
14061 created by using SYNCW to order writes combined with the
14062 write from the following SC. When the SC successfully
14063 completes, we know that all preceding writes are also
14064 committed to the coherent memory system. It is possible
14065 for a single SYNCW to fail, but a pair of them will never
14066 fail, so we use two. */
14067 mips_multi_add_insn ("syncw", NULL
);
14068 mips_multi_add_insn ("syncw", NULL
);
14071 mips_multi_add_insn ("sync", NULL
);
14074 /* Output the branch-back label. */
14075 mips_multi_add_label ("1:");
14077 /* OLDVAL = *MEM. */
14078 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
14079 oldval
, mem
, NULL
);
14081 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
14082 if (required_oldval
)
14084 if (inclusive_mask
== 0)
14088 gcc_assert (oldval
!= at
);
14089 mips_multi_add_insn ("and\t%0,%1,%2",
14090 at
, oldval
, inclusive_mask
, NULL
);
14093 if (TARGET_CB_NEVER
)
14094 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
14096 /* CMP = 0 [delay slot]. */
14098 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
14100 if (TARGET_CB_MAYBE
&& required_oldval
== const0_rtx
)
14101 mips_multi_add_insn ("bnezc\t%0,2f", tmp1
, NULL
);
14102 else if (TARGET_CB_MAYBE
)
14103 mips_multi_add_insn ("bnec\t%0,%1,2f", tmp1
, required_oldval
, NULL
);
14107 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
14108 if (exclusive_mask
== 0)
14112 gcc_assert (oldval
!= at
);
14113 mips_multi_add_insn ("and\t%0,%1,%z2",
14114 at
, oldval
, exclusive_mask
, NULL
);
14118 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
14120 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
14121 at least one instruction in that case. */
14122 if (insn1
== SYNC_INSN1_MOVE
14123 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
14127 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
14128 newval
, oldval
, insn1_op2
, NULL
);
14132 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
14133 if (insn2
== SYNC_INSN2_NOP
)
14137 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
14138 newval
, tmp2
, inclusive_mask
, NULL
);
14141 tmp3_insn
= mips_multi_last_index ();
14143 /* $AT = $TMP1 | $TMP3. */
14144 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
14146 mips_multi_set_operand (tmp3_insn
, 0, at
);
14151 gcc_assert (tmp1
!= tmp3
);
14152 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
14155 /* if (!commit (*MEM = $AT)) goto 1.
14157 This will sometimes be a delayed branch; see the write code below
14159 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
14161 /* When using branch likely (-mfix-r10000), the delay slot instruction
14162 will be annulled on false. The normal delay slot instructions
14163 calculate the overall result of the atomic operation and must not
14164 be annulled. To ensure this behavior unconditionally use a NOP
14165 in the delay slot for the branch likely case. */
14167 if (TARGET_CB_MAYBE
)
14168 mips_multi_add_insn ("beqzc\t%0,1b", at
, NULL
);
14170 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at
, NULL
);
14172 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
14173 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
14175 mips_multi_copy_insn (tmp3_insn
);
14176 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
14178 else if (!(required_oldval
&& cmp
) && !mips_branch_likely
)
14179 mips_multi_add_insn ("nop", NULL
);
14181 /* CMP = 1 -- either standalone or in a delay slot. */
14182 if (required_oldval
&& cmp
)
14183 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
14185 /* Output the acquire side of the memory barrier. */
14186 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
14187 mips_multi_add_insn ("sync", NULL
);
14189 /* Output the exit label, if needed. */
14190 if (required_oldval
)
14191 mips_multi_add_label ("2:");
14193 #undef READ_OPERAND
14196 /* Output and/or return the asm template for sync loop INSN, which has
14197 the operands given by OPERANDS. */
14200 mips_output_sync_loop (rtx_insn
*insn
, rtx
*operands
)
14202 /* Use branch-likely instructions to work around the LL/SC R10000
14204 mips_branch_likely
= TARGET_FIX_R10000
;
14206 mips_process_sync_loop (insn
, operands
);
14208 mips_push_asm_switch (&mips_noreorder
);
14209 mips_push_asm_switch (&mips_nomacro
);
14210 mips_push_asm_switch (&mips_noat
);
14211 mips_start_ll_sc_sync_block ();
14213 mips_multi_write ();
14215 mips_end_ll_sc_sync_block ();
14216 mips_pop_asm_switch (&mips_noat
);
14217 mips_pop_asm_switch (&mips_nomacro
);
14218 mips_pop_asm_switch (&mips_noreorder
);
14223 /* Return the number of individual instructions in sync loop INSN,
14224 which has the operands given by OPERANDS. */
14227 mips_sync_loop_insns (rtx_insn
*insn
, rtx
*operands
)
14229 /* Use branch-likely instructions to work around the LL/SC R10000
14231 mips_branch_likely
= TARGET_FIX_R10000
;
14232 mips_process_sync_loop (insn
, operands
);
14233 return mips_multi_num_insns
;
14236 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
14237 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
14239 When working around R4000 and R4400 errata, we need to make sure that
14240 the division is not immediately followed by a shift[1][2]. We also
14241 need to stop the division from being put into a branch delay slot[3].
14242 The easiest way to avoid both problems is to add a nop after the
14243 division. When a divide-by-zero check is needed, this nop can be
14244 used to fill the branch delay slot.
14246 [1] If a double-word or a variable shift executes immediately
14247 after starting an integer division, the shift may give an
14248 incorrect result. See quotations of errata #16 and #28 from
14249 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14250 in mips.md for details.
14252 [2] A similar bug to [1] exists for all revisions of the
14253 R4000 and the R4400 when run in an MC configuration.
14254 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
14256 "19. In this following sequence:
14258 ddiv (or ddivu or div or divu)
14259 dsll32 (or dsrl32, dsra32)
14261 if an MPT stall occurs, while the divide is slipping the cpu
14262 pipeline, then the following double shift would end up with an
14265 Workaround: The compiler needs to avoid generating any
14266 sequence with divide followed by extended double shift."
14268 This erratum is also present in "MIPS R4400MC Errata, Processor
14269 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
14270 & 3.0" as errata #10 and #4, respectively.
14272 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14273 (also valid for MIPS R4000MC processors):
14275 "52. R4000SC: This bug does not apply for the R4000PC.
14277 There are two flavors of this bug:
14279 1) If the instruction just after divide takes an RF exception
14280 (tlb-refill, tlb-invalid) and gets an instruction cache
14281 miss (both primary and secondary) and the line which is
14282 currently in secondary cache at this index had the first
14283 data word, where the bits 5..2 are set, then R4000 would
14284 get a wrong result for the div.
14289 ------------------- # end-of page. -tlb-refill
14294 ------------------- # end-of page. -tlb-invalid
14297 2) If the divide is in the taken branch delay slot, where the
14298 target takes RF exception and gets an I-cache miss for the
14299 exception vector or where I-cache miss occurs for the
14300 target address, under the above mentioned scenarios, the
14301 div would get wrong results.
14304 j r2 # to next page mapped or unmapped
14305 div r8,r9 # this bug would be there as long
14306 # as there is an ICache miss and
14307 nop # the "data pattern" is present
14310 beq r0, r0, NextPage # to Next page
14314 This bug is present for div, divu, ddiv, and ddivu
14317 Workaround: For item 1), OS could make sure that the next page
14318 after the divide instruction is also mapped. For item 2), the
14319 compiler could make sure that the divide instruction is not in
14320 the branch delay slot."
14322 These processors have PRId values of 0x00004220 and 0x00004300 for
14323 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
14326 mips_output_division (const char *division
, rtx
*operands
)
14331 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
14333 output_asm_insn (s
, operands
);
14336 if (TARGET_CHECK_ZERO_DIV
)
14340 output_asm_insn (s
, operands
);
14341 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
14343 else if (GENERATE_DIVIDE_TRAPS
)
14345 /* Avoid long replay penalty on load miss by putting the trap before
14348 output_asm_insn ("teq\t%2,%.,7", operands
);
14351 output_asm_insn (s
, operands
);
14352 s
= "teq\t%2,%.,7";
14357 if (flag_delayed_branch
)
14359 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
14360 output_asm_insn (s
, operands
);
14361 s
= "break\t7%)\n1:";
14365 output_asm_insn (s
, operands
);
14366 s
= "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
14373 /* Return the assembly code for MSA DIV_{S,U}.DF or MOD_{S,U}.DF instructions,
14374 which has the operands given by OPERANDS. Add in a divide-by-zero check
14378 mips_msa_output_division (const char *division
, rtx
*operands
)
14383 if (TARGET_CHECK_ZERO_DIV
)
14385 output_asm_insn ("%(bnz.%v0\t%w2,1f", operands
);
14386 output_asm_insn (s
, operands
);
14387 s
= "break\t7%)\n1:";
14392 /* Return true if destination of IN_INSN is used as add source in
14393 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
14394 madd.s dst, x, y, z
14395 madd.s a, dst, b, c */
14398 mips_fmadd_bypass (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14400 int dst_reg
, src_reg
;
14402 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
14403 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
14405 extract_insn (in_insn
);
14406 dst_reg
= REG_P (recog_data
.operand
[0]);
14408 extract_insn (out_insn
);
14409 src_reg
= REG_P (recog_data
.operand
[1]);
14411 if (dst_reg
== src_reg
)
14417 /* Return true if IN_INSN is a multiply-add or multiply-subtract
14418 instruction and if OUT_INSN assigns to the accumulator operand. */
14421 mips_linked_madd_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14423 enum attr_accum_in accum_in
;
14424 int accum_in_opnum
;
14427 if (recog_memoized (in_insn
) < 0)
14430 accum_in
= get_attr_accum_in (in_insn
);
14431 if (accum_in
== ACCUM_IN_NONE
)
14434 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
14436 extract_insn (in_insn
);
14437 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
14438 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
14440 return reg_set_p (accum_in_op
, out_insn
);
14443 /* True if the dependency between OUT_INSN and IN_INSN is on the store
14444 data rather than the address. We need this because the cprestore
14445 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
14446 which causes the default routine to abort. We just return false
14450 mips_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14452 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
14455 return store_data_bypass_p (out_insn
, in_insn
);
14459 /* Variables and flags used in scheduler hooks when tuning for
14463 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
14466 /* If true, then next ALU1/2 instruction will go to ALU1. */
14469 /* If true, then next FALU1/2 unstruction will go to FALU1. */
14472 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
14473 int alu1_core_unit_code
;
14474 int alu2_core_unit_code
;
14475 int falu1_core_unit_code
;
14476 int falu2_core_unit_code
;
14478 /* True if current cycle has a multi instruction.
14479 This flag is used in mips_ls2_dfa_post_advance_cycle. */
14480 bool cycle_has_multi_p
;
14482 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
14483 These are used in mips_ls2_dfa_post_advance_cycle to initialize
14485 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
14486 instruction to go ALU1. */
14487 rtx_insn
*alu1_turn_enabled_insn
;
14488 rtx_insn
*alu2_turn_enabled_insn
;
14489 rtx_insn
*falu1_turn_enabled_insn
;
14490 rtx_insn
*falu2_turn_enabled_insn
;
14493 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
14494 dependencies have no cost, except on the 20Kc where output-dependence
14495 is treated like input-dependence. */
14498 mips_adjust_cost (rtx_insn
*, int dep_type
, rtx_insn
*, int cost
, unsigned int)
14500 if (dep_type
!= 0 && (dep_type
!= REG_DEP_OUTPUT
|| !TUNE_20KC
))
14505 /* Return the number of instructions that can be issued per cycle. */
14508 mips_issue_rate (void)
14512 case PROCESSOR_74KC
:
14513 case PROCESSOR_74KF2_1
:
14514 case PROCESSOR_74KF1_1
:
14515 case PROCESSOR_74KF3_2
:
14516 /* The 74k is not strictly quad-issue cpu, but can be seen as one
14517 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
14518 but in reality only a maximum of 3 insns can be issued as
14519 floating-point loads and stores also require a slot in the
14521 case PROCESSOR_R10000
:
14522 /* All R10K Processors are quad-issue (being the first MIPS
14523 processors to support this feature). */
14526 case PROCESSOR_20KC
:
14527 case PROCESSOR_R4130
:
14528 case PROCESSOR_R5400
:
14529 case PROCESSOR_R5500
:
14530 case PROCESSOR_R5900
:
14531 case PROCESSOR_R7000
:
14532 case PROCESSOR_R9000
:
14533 case PROCESSOR_OCTEON
:
14534 case PROCESSOR_OCTEON2
:
14535 case PROCESSOR_OCTEON3
:
14536 case PROCESSOR_I6400
:
14539 case PROCESSOR_SB1
:
14540 case PROCESSOR_SB1A
:
14541 /* This is actually 4, but we get better performance if we claim 3.
14542 This is partly because of unwanted speculative code motion with the
14543 larger number, and partly because in most common cases we can't
14544 reach the theoretical max of 4. */
14547 case PROCESSOR_LOONGSON_2E
:
14548 case PROCESSOR_LOONGSON_2F
:
14549 case PROCESSOR_LOONGSON_3A
:
14550 case PROCESSOR_P5600
:
14553 case PROCESSOR_XLP
:
14554 return (reload_completed
? 4 : 3);
14561 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
14564 mips_ls2_init_dfa_post_cycle_insn (void)
14567 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
14568 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
14572 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
14573 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
14577 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
14578 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
14582 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
14583 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
14586 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
14587 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
14588 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
14589 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
14592 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
14593 Init data used in mips_dfa_post_advance_cycle. */
14596 mips_init_dfa_post_cycle_insn (void)
14598 if (TUNE_LOONGSON_2EF
)
14599 mips_ls2_init_dfa_post_cycle_insn ();
14602 /* Initialize STATE when scheduling for Loongson 2E/2F.
14603 Support round-robin dispatch scheme by enabling only one of
14604 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
14608 mips_ls2_dfa_post_advance_cycle (state_t state
)
14610 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
14612 /* Though there are no non-pipelined ALU1 insns,
14613 we can get an instruction of type 'multi' before reload. */
14614 gcc_assert (mips_ls2
.cycle_has_multi_p
);
14615 mips_ls2
.alu1_turn_p
= false;
14618 mips_ls2
.cycle_has_multi_p
= false;
14620 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
14621 /* We have a non-pipelined alu instruction in the core,
14622 adjust round-robin counter. */
14623 mips_ls2
.alu1_turn_p
= true;
14625 if (mips_ls2
.alu1_turn_p
)
14627 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
14628 gcc_unreachable ();
14632 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
14633 gcc_unreachable ();
14636 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
14638 /* There are no non-pipelined FALU1 insns. */
14639 gcc_unreachable ();
14640 mips_ls2
.falu1_turn_p
= false;
14643 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
14644 /* We have a non-pipelined falu instruction in the core,
14645 adjust round-robin counter. */
14646 mips_ls2
.falu1_turn_p
= true;
14648 if (mips_ls2
.falu1_turn_p
)
14650 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
14651 gcc_unreachable ();
14655 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
14656 gcc_unreachable ();
14660 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
14661 This hook is being called at the start of each cycle. */
14664 mips_dfa_post_advance_cycle (void)
14666 if (TUNE_LOONGSON_2EF
)
14667 mips_ls2_dfa_post_advance_cycle (curr_state
);
14670 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
14671 be as wide as the scheduling freedom in the DFA. */
14674 mips_multipass_dfa_lookahead (void)
14676 /* Can schedule up to 4 of the 6 function units in any one cycle. */
14680 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
14686 if (TUNE_P5600
|| TUNE_I6400
)
14692 /* Remove the instruction at index LOWER from ready queue READY and
14693 reinsert it in front of the instruction at index HIGHER. LOWER must
14697 mips_promote_ready (rtx_insn
**ready
, int lower
, int higher
)
14699 rtx_insn
*new_head
;
14702 new_head
= ready
[lower
];
14703 for (i
= lower
; i
< higher
; i
++)
14704 ready
[i
] = ready
[i
+ 1];
14705 ready
[i
] = new_head
;
14708 /* If the priority of the instruction at POS2 in the ready queue READY
14709 is within LIMIT units of that of the instruction at POS1, swap the
14710 instructions if POS2 is not already less than POS1. */
14713 mips_maybe_swap_ready (rtx_insn
**ready
, int pos1
, int pos2
, int limit
)
14716 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
14720 temp
= ready
[pos1
];
14721 ready
[pos1
] = ready
[pos2
];
14722 ready
[pos2
] = temp
;
14726 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
14727 that may clobber hi or lo. */
14728 static rtx_insn
*mips_macc_chains_last_hilo
;
14730 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
14731 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
14734 mips_macc_chains_record (rtx_insn
*insn
)
14736 if (get_attr_may_clobber_hilo (insn
))
14737 mips_macc_chains_last_hilo
= insn
;
14740 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
14741 has NREADY elements, looking for a multiply-add or multiply-subtract
14742 instruction that is cumulative with mips_macc_chains_last_hilo.
14743 If there is one, promote it ahead of anything else that might
14744 clobber hi or lo. */
14747 mips_macc_chains_reorder (rtx_insn
**ready
, int nready
)
14751 if (mips_macc_chains_last_hilo
!= 0)
14752 for (i
= nready
- 1; i
>= 0; i
--)
14753 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
14755 for (j
= nready
- 1; j
> i
; j
--)
14756 if (recog_memoized (ready
[j
]) >= 0
14757 && get_attr_may_clobber_hilo (ready
[j
]))
14759 mips_promote_ready (ready
, i
, j
);
14766 /* The last instruction to be scheduled. */
14767 static rtx_insn
*vr4130_last_insn
;
14769 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
14770 points to an rtx that is initially an instruction. Nullify the rtx
14771 if the instruction uses the value of register X. */
14774 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14779 insn_ptr
= (rtx
*) data
;
14782 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
14786 /* Return true if there is true register dependence between vr4130_last_insn
14790 vr4130_true_reg_dependence_p (rtx insn
)
14792 note_stores (PATTERN (vr4130_last_insn
),
14793 vr4130_true_reg_dependence_p_1
, &insn
);
14797 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
14798 the ready queue and that INSN2 is the instruction after it, return
14799 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
14800 in which INSN1 and INSN2 can probably issue in parallel, but for
14801 which (INSN2, INSN1) should be less sensitive to instruction
14802 alignment than (INSN1, INSN2). See 4130.md for more details. */
14805 vr4130_swap_insns_p (rtx_insn
*insn1
, rtx_insn
*insn2
)
14807 sd_iterator_def sd_it
;
14810 /* Check for the following case:
14812 1) there is some other instruction X with an anti dependence on INSN1;
14813 2) X has a higher priority than INSN2; and
14814 3) X is an arithmetic instruction (and thus has no unit restrictions).
14816 If INSN1 is the last instruction blocking X, it would better to
14817 choose (INSN1, X) over (INSN2, INSN1). */
14818 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
14819 if (DEP_TYPE (dep
) == REG_DEP_ANTI
14820 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
14821 && recog_memoized (DEP_CON (dep
)) >= 0
14822 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
14825 if (vr4130_last_insn
!= 0
14826 && recog_memoized (insn1
) >= 0
14827 && recog_memoized (insn2
) >= 0)
14829 /* See whether INSN1 and INSN2 use different execution units,
14830 or if they are both ALU-type instructions. If so, they can
14831 probably execute in parallel. */
14832 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
14833 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
14834 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
14836 /* If only one of the instructions has a dependence on
14837 vr4130_last_insn, prefer to schedule the other one first. */
14838 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
14839 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
14840 if (dep1_p
!= dep2_p
)
14843 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
14844 is not an ALU-type instruction and if INSN1 uses the same
14845 execution unit. (Note that if this condition holds, we already
14846 know that INSN2 uses a different execution unit.) */
14847 if (class1
!= VR4130_CLASS_ALU
14848 && recog_memoized (vr4130_last_insn
) >= 0
14849 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
14856 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
14857 queue with at least two instructions. Swap the first two if
14858 vr4130_swap_insns_p says that it could be worthwhile. */
14861 vr4130_reorder (rtx_insn
**ready
, int nready
)
14863 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
14864 mips_promote_ready (ready
, nready
- 2, nready
- 1);
14867 /* Record whether last 74k AGEN instruction was a load or store. */
14868 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
14870 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
14871 resets to TYPE_UNKNOWN state. */
14874 mips_74k_agen_init (rtx_insn
*insn
)
14876 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
14877 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
14880 enum attr_type type
= get_attr_type (insn
);
14881 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
14882 mips_last_74k_agen_insn
= type
;
14886 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
14887 loads to be grouped together, and multiple stores to be grouped
14888 together. Swap things around in the ready queue to make this happen. */
14891 mips_74k_agen_reorder (rtx_insn
**ready
, int nready
)
14894 int store_pos
, load_pos
;
14899 for (i
= nready
- 1; i
>= 0; i
--)
14901 rtx_insn
*insn
= ready
[i
];
14902 if (USEFUL_INSN_P (insn
))
14903 switch (get_attr_type (insn
))
14906 if (store_pos
== -1)
14911 if (load_pos
== -1)
14920 if (load_pos
== -1 || store_pos
== -1)
14923 switch (mips_last_74k_agen_insn
)
14926 /* Prefer to schedule loads since they have a higher latency. */
14928 /* Swap loads to the front of the queue. */
14929 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
14932 /* Swap stores to the front of the queue. */
14933 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
14940 /* Implement TARGET_SCHED_INIT. */
14943 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
14944 int max_ready ATTRIBUTE_UNUSED
)
14946 mips_macc_chains_last_hilo
= 0;
14947 vr4130_last_insn
= 0;
14948 mips_74k_agen_init (NULL
);
14950 /* When scheduling for Loongson2, branch instructions go to ALU1,
14951 therefore basic block is most likely to start with round-robin counter
14952 pointed to ALU2. */
14953 mips_ls2
.alu1_turn_p
= false;
14954 mips_ls2
.falu1_turn_p
= true;
14957 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
14960 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
14961 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
14963 if (!reload_completed
14964 && TUNE_MACC_CHAINS
14966 mips_macc_chains_reorder (ready
, *nreadyp
);
14968 if (reload_completed
14970 && !TARGET_VR4130_ALIGN
14972 vr4130_reorder (ready
, *nreadyp
);
14975 mips_74k_agen_reorder (ready
, *nreadyp
);
14978 /* Implement TARGET_SCHED_REORDER. */
14981 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
14982 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
14984 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
14985 return mips_issue_rate ();
14988 /* Implement TARGET_SCHED_REORDER2. */
14991 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
14992 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
14994 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
14995 return cached_can_issue_more
;
14998 /* Update round-robin counters for ALU1/2 and FALU1/2. */
15001 mips_ls2_variable_issue (rtx_insn
*insn
)
15003 if (mips_ls2
.alu1_turn_p
)
15005 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
15006 mips_ls2
.alu1_turn_p
= false;
15010 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
15011 mips_ls2
.alu1_turn_p
= true;
15014 if (mips_ls2
.falu1_turn_p
)
15016 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
15017 mips_ls2
.falu1_turn_p
= false;
15021 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
15022 mips_ls2
.falu1_turn_p
= true;
15025 if (recog_memoized (insn
) >= 0)
15026 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
15029 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
15032 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15033 rtx_insn
*insn
, int more
)
15035 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
15036 if (USEFUL_INSN_P (insn
))
15038 if (get_attr_type (insn
) != TYPE_GHOST
)
15040 if (!reload_completed
&& TUNE_MACC_CHAINS
)
15041 mips_macc_chains_record (insn
);
15042 vr4130_last_insn
= insn
;
15044 mips_74k_agen_init (insn
);
15045 else if (TUNE_LOONGSON_2EF
)
15046 mips_ls2_variable_issue (insn
);
15049 /* Instructions of type 'multi' should all be split before
15050 the second scheduling pass. */
15051 gcc_assert (!reload_completed
15052 || recog_memoized (insn
) < 0
15053 || get_attr_type (insn
) != TYPE_MULTI
);
15055 cached_can_issue_more
= more
;
15059 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
15060 return the first operand of the associated PREF or PREFX insn. */
15063 mips_prefetch_cookie (rtx write
, rtx locality
)
15065 /* store_streamed / load_streamed. */
15066 if (INTVAL (locality
) <= 0)
15067 return GEN_INT (INTVAL (write
) + 4);
15069 /* store / load. */
15070 if (INTVAL (locality
) <= 2)
15073 /* store_retained / load_retained. */
15074 return GEN_INT (INTVAL (write
) + 6);
15077 /* Flags that indicate when a built-in function is available.
15079 BUILTIN_AVAIL_NON_MIPS16
15080 The function is available on the current target if !TARGET_MIPS16.
15082 BUILTIN_AVAIL_MIPS16
15083 The function is available on the current target if TARGET_MIPS16. */
15084 #define BUILTIN_AVAIL_NON_MIPS16 1
15085 #define BUILTIN_AVAIL_MIPS16 2
15087 /* Declare an availability predicate for built-in functions that
15088 require non-MIPS16 mode and also require COND to be true.
15089 NAME is the main part of the predicate's name. */
15090 #define AVAIL_NON_MIPS16(NAME, COND) \
15091 static unsigned int \
15092 mips_builtin_avail_##NAME (void) \
15094 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
15097 /* Declare an availability predicate for built-in functions that
15098 support both MIPS16 and non-MIPS16 code and also require COND
15099 to be true. NAME is the main part of the predicate's name. */
15100 #define AVAIL_ALL(NAME, COND) \
15101 static unsigned int \
15102 mips_builtin_avail_##NAME (void) \
15104 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
15107 /* This structure describes a single built-in function. */
15108 struct mips_builtin_description
{
15109 /* The code of the main .md file instruction. See mips_builtin_type
15110 for more information. */
15111 enum insn_code icode
;
15113 /* The floating-point comparison code to use with ICODE, if any. */
15114 enum mips_fp_condition cond
;
15116 /* The name of the built-in function. */
15119 /* Specifies how the function should be expanded. */
15120 enum mips_builtin_type builtin_type
;
15122 /* The function's prototype. */
15123 enum mips_function_type function_type
;
15125 /* Whether the function is available. */
15126 unsigned int (*avail
) (void);
15129 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
15130 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
15131 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
15132 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
15133 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
15134 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
15135 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
15136 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
15137 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
15138 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
15139 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
15140 AVAIL_NON_MIPS16 (msa
, TARGET_MSA
)
15142 /* Construct a mips_builtin_description from the given arguments.
15144 INSN is the name of the associated instruction pattern, without the
15145 leading CODE_FOR_mips_.
15147 CODE is the floating-point condition code associated with the
15148 function. It can be 'f' if the field is not applicable.
15150 NAME is the name of the function itself, without the leading
15153 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
15155 AVAIL is the name of the availability predicate, without the leading
15156 mips_builtin_avail_. */
15157 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
15158 FUNCTION_TYPE, AVAIL) \
15159 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
15160 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
15161 mips_builtin_avail_ ## AVAIL }
15163 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
15164 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
15165 are as for MIPS_BUILTIN. */
15166 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15167 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
15169 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
15170 are subject to mips_builtin_avail_<AVAIL>. */
15171 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
15172 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
15173 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
15174 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
15175 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
15177 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
15178 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
15179 while the any and all forms are subject to mips_builtin_avail_mips3d. */
15180 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
15181 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
15182 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
15184 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
15185 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
15187 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
15188 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
15190 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
15191 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
15194 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
15195 are subject to mips_builtin_avail_mips3d. */
15196 #define CMP_4S_BUILTINS(INSN, COND) \
15197 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
15198 MIPS_BUILTIN_CMP_ANY, \
15199 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
15200 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
15201 MIPS_BUILTIN_CMP_ALL, \
15202 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
15204 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
15205 instruction requires mips_builtin_avail_<AVAIL>. */
15206 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
15207 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
15208 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15210 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
15211 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15214 /* Define all the built-in functions related to C.cond.fmt condition COND. */
15215 #define CMP_BUILTINS(COND) \
15216 MOVTF_BUILTINS (c, COND, paired_single), \
15217 MOVTF_BUILTINS (cabs, COND, mips3d), \
15218 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
15219 CMP_PS_BUILTINS (c, COND, paired_single), \
15220 CMP_PS_BUILTINS (cabs, COND, mips3d), \
15221 CMP_4S_BUILTINS (c, COND), \
15222 CMP_4S_BUILTINS (cabs, COND)
15224 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
15225 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
15226 and AVAIL are as for MIPS_BUILTIN. */
15227 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15228 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15229 FUNCTION_TYPE, AVAIL)
15231 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
15232 branch instruction. AVAIL is as for MIPS_BUILTIN. */
15233 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
15234 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
15235 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
15237 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
15238 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15239 builtin_description field. */
15240 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
15241 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
15242 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
15243 FUNCTION_TYPE, mips_builtin_avail_loongson }
15245 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
15246 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15247 builtin_description field. */
15248 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
15249 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
15251 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
15252 We use functions of this form when the same insn can be usefully applied
15253 to more than one datatype. */
15254 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
15255 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
15257 /* Define an MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15258 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15260 #define MSA_BUILTIN(INSN, FUNCTION_TYPE) \
15261 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15262 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15263 FUNCTION_TYPE, mips_builtin_avail_msa }
15265 /* Define a remapped MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15266 for instruction CODE_FOR_msa_<INSN2>. FUNCTION_TYPE is
15267 a builtin_description field. */
15268 #define MSA_BUILTIN_REMAP(INSN, INSN2, FUNCTION_TYPE) \
15269 { CODE_FOR_msa_ ## INSN2, MIPS_FP_COND_f, \
15270 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15271 FUNCTION_TYPE, mips_builtin_avail_msa }
15273 /* Define an MSA MIPS_BUILTIN_MSA_TEST_BRANCH function __builtin_msa_<INSN>
15274 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15276 #define MSA_BUILTIN_TEST_BRANCH(INSN, FUNCTION_TYPE) \
15277 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15278 "__builtin_msa_" #INSN, MIPS_BUILTIN_MSA_TEST_BRANCH, \
15279 FUNCTION_TYPE, mips_builtin_avail_msa }
15281 /* Define an MSA MIPS_BUILTIN_DIRECT_NO_TARGET function __builtin_msa_<INSN>
15282 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15284 #define MSA_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE) \
15285 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15286 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15287 FUNCTION_TYPE, mips_builtin_avail_msa }
15289 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
15290 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
15291 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
15292 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
15293 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
15294 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
15295 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
15296 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
15298 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
15299 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
15300 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
15301 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
15302 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
15303 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
15304 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
15305 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
15306 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
15307 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
15308 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
15309 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
15310 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
15311 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
15312 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
15313 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
15314 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
15315 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
15316 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
15317 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
15318 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
15319 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
15320 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
15321 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
15322 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
15323 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
15324 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
15325 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
15326 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
15327 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
15329 #define CODE_FOR_msa_adds_s_b CODE_FOR_ssaddv16qi3
15330 #define CODE_FOR_msa_adds_s_h CODE_FOR_ssaddv8hi3
15331 #define CODE_FOR_msa_adds_s_w CODE_FOR_ssaddv4si3
15332 #define CODE_FOR_msa_adds_s_d CODE_FOR_ssaddv2di3
15333 #define CODE_FOR_msa_adds_u_b CODE_FOR_usaddv16qi3
15334 #define CODE_FOR_msa_adds_u_h CODE_FOR_usaddv8hi3
15335 #define CODE_FOR_msa_adds_u_w CODE_FOR_usaddv4si3
15336 #define CODE_FOR_msa_adds_u_d CODE_FOR_usaddv2di3
15337 #define CODE_FOR_msa_addv_b CODE_FOR_addv16qi3
15338 #define CODE_FOR_msa_addv_h CODE_FOR_addv8hi3
15339 #define CODE_FOR_msa_addv_w CODE_FOR_addv4si3
15340 #define CODE_FOR_msa_addv_d CODE_FOR_addv2di3
15341 #define CODE_FOR_msa_addvi_b CODE_FOR_addv16qi3
15342 #define CODE_FOR_msa_addvi_h CODE_FOR_addv8hi3
15343 #define CODE_FOR_msa_addvi_w CODE_FOR_addv4si3
15344 #define CODE_FOR_msa_addvi_d CODE_FOR_addv2di3
15345 #define CODE_FOR_msa_and_v CODE_FOR_andv16qi3
15346 #define CODE_FOR_msa_andi_b CODE_FOR_andv16qi3
15347 #define CODE_FOR_msa_bmnz_v CODE_FOR_msa_bmnz_b
15348 #define CODE_FOR_msa_bmnzi_b CODE_FOR_msa_bmnz_b
15349 #define CODE_FOR_msa_bmz_v CODE_FOR_msa_bmz_b
15350 #define CODE_FOR_msa_bmzi_b CODE_FOR_msa_bmz_b
15351 #define CODE_FOR_msa_bnz_v CODE_FOR_msa_bnz_v_b
15352 #define CODE_FOR_msa_bz_v CODE_FOR_msa_bz_v_b
15353 #define CODE_FOR_msa_bsel_v CODE_FOR_msa_bsel_b
15354 #define CODE_FOR_msa_bseli_b CODE_FOR_msa_bsel_b
15355 #define CODE_FOR_msa_ceqi_b CODE_FOR_msa_ceq_b
15356 #define CODE_FOR_msa_ceqi_h CODE_FOR_msa_ceq_h
15357 #define CODE_FOR_msa_ceqi_w CODE_FOR_msa_ceq_w
15358 #define CODE_FOR_msa_ceqi_d CODE_FOR_msa_ceq_d
15359 #define CODE_FOR_msa_clti_s_b CODE_FOR_msa_clt_s_b
15360 #define CODE_FOR_msa_clti_s_h CODE_FOR_msa_clt_s_h
15361 #define CODE_FOR_msa_clti_s_w CODE_FOR_msa_clt_s_w
15362 #define CODE_FOR_msa_clti_s_d CODE_FOR_msa_clt_s_d
15363 #define CODE_FOR_msa_clti_u_b CODE_FOR_msa_clt_u_b
15364 #define CODE_FOR_msa_clti_u_h CODE_FOR_msa_clt_u_h
15365 #define CODE_FOR_msa_clti_u_w CODE_FOR_msa_clt_u_w
15366 #define CODE_FOR_msa_clti_u_d CODE_FOR_msa_clt_u_d
15367 #define CODE_FOR_msa_clei_s_b CODE_FOR_msa_cle_s_b
15368 #define CODE_FOR_msa_clei_s_h CODE_FOR_msa_cle_s_h
15369 #define CODE_FOR_msa_clei_s_w CODE_FOR_msa_cle_s_w
15370 #define CODE_FOR_msa_clei_s_d CODE_FOR_msa_cle_s_d
15371 #define CODE_FOR_msa_clei_u_b CODE_FOR_msa_cle_u_b
15372 #define CODE_FOR_msa_clei_u_h CODE_FOR_msa_cle_u_h
15373 #define CODE_FOR_msa_clei_u_w CODE_FOR_msa_cle_u_w
15374 #define CODE_FOR_msa_clei_u_d CODE_FOR_msa_cle_u_d
15375 #define CODE_FOR_msa_div_s_b CODE_FOR_divv16qi3
15376 #define CODE_FOR_msa_div_s_h CODE_FOR_divv8hi3
15377 #define CODE_FOR_msa_div_s_w CODE_FOR_divv4si3
15378 #define CODE_FOR_msa_div_s_d CODE_FOR_divv2di3
15379 #define CODE_FOR_msa_div_u_b CODE_FOR_udivv16qi3
15380 #define CODE_FOR_msa_div_u_h CODE_FOR_udivv8hi3
15381 #define CODE_FOR_msa_div_u_w CODE_FOR_udivv4si3
15382 #define CODE_FOR_msa_div_u_d CODE_FOR_udivv2di3
15383 #define CODE_FOR_msa_fadd_w CODE_FOR_addv4sf3
15384 #define CODE_FOR_msa_fadd_d CODE_FOR_addv2df3
15385 #define CODE_FOR_msa_fexdo_w CODE_FOR_vec_pack_trunc_v2df
15386 #define CODE_FOR_msa_ftrunc_s_w CODE_FOR_fix_truncv4sfv4si2
15387 #define CODE_FOR_msa_ftrunc_s_d CODE_FOR_fix_truncv2dfv2di2
15388 #define CODE_FOR_msa_ftrunc_u_w CODE_FOR_fixuns_truncv4sfv4si2
15389 #define CODE_FOR_msa_ftrunc_u_d CODE_FOR_fixuns_truncv2dfv2di2
15390 #define CODE_FOR_msa_ffint_s_w CODE_FOR_floatv4siv4sf2
15391 #define CODE_FOR_msa_ffint_s_d CODE_FOR_floatv2div2df2
15392 #define CODE_FOR_msa_ffint_u_w CODE_FOR_floatunsv4siv4sf2
15393 #define CODE_FOR_msa_ffint_u_d CODE_FOR_floatunsv2div2df2
15394 #define CODE_FOR_msa_fsub_w CODE_FOR_subv4sf3
15395 #define CODE_FOR_msa_fsub_d CODE_FOR_subv2df3
15396 #define CODE_FOR_msa_fmadd_w CODE_FOR_fmav4sf4
15397 #define CODE_FOR_msa_fmadd_d CODE_FOR_fmav2df4
15398 #define CODE_FOR_msa_fmsub_w CODE_FOR_fnmav4sf4
15399 #define CODE_FOR_msa_fmsub_d CODE_FOR_fnmav2df4
15400 #define CODE_FOR_msa_fmul_w CODE_FOR_mulv4sf3
15401 #define CODE_FOR_msa_fmul_d CODE_FOR_mulv2df3
15402 #define CODE_FOR_msa_fdiv_w CODE_FOR_divv4sf3
15403 #define CODE_FOR_msa_fdiv_d CODE_FOR_divv2df3
15404 #define CODE_FOR_msa_fmax_w CODE_FOR_smaxv4sf3
15405 #define CODE_FOR_msa_fmax_d CODE_FOR_smaxv2df3
15406 #define CODE_FOR_msa_fmin_w CODE_FOR_sminv4sf3
15407 #define CODE_FOR_msa_fmin_d CODE_FOR_sminv2df3
15408 #define CODE_FOR_msa_fsqrt_w CODE_FOR_sqrtv4sf2
15409 #define CODE_FOR_msa_fsqrt_d CODE_FOR_sqrtv2df2
15410 #define CODE_FOR_msa_max_s_b CODE_FOR_smaxv16qi3
15411 #define CODE_FOR_msa_max_s_h CODE_FOR_smaxv8hi3
15412 #define CODE_FOR_msa_max_s_w CODE_FOR_smaxv4si3
15413 #define CODE_FOR_msa_max_s_d CODE_FOR_smaxv2di3
15414 #define CODE_FOR_msa_maxi_s_b CODE_FOR_smaxv16qi3
15415 #define CODE_FOR_msa_maxi_s_h CODE_FOR_smaxv8hi3
15416 #define CODE_FOR_msa_maxi_s_w CODE_FOR_smaxv4si3
15417 #define CODE_FOR_msa_maxi_s_d CODE_FOR_smaxv2di3
15418 #define CODE_FOR_msa_max_u_b CODE_FOR_umaxv16qi3
15419 #define CODE_FOR_msa_max_u_h CODE_FOR_umaxv8hi3
15420 #define CODE_FOR_msa_max_u_w CODE_FOR_umaxv4si3
15421 #define CODE_FOR_msa_max_u_d CODE_FOR_umaxv2di3
15422 #define CODE_FOR_msa_maxi_u_b CODE_FOR_umaxv16qi3
15423 #define CODE_FOR_msa_maxi_u_h CODE_FOR_umaxv8hi3
15424 #define CODE_FOR_msa_maxi_u_w CODE_FOR_umaxv4si3
15425 #define CODE_FOR_msa_maxi_u_d CODE_FOR_umaxv2di3
15426 #define CODE_FOR_msa_min_s_b CODE_FOR_sminv16qi3
15427 #define CODE_FOR_msa_min_s_h CODE_FOR_sminv8hi3
15428 #define CODE_FOR_msa_min_s_w CODE_FOR_sminv4si3
15429 #define CODE_FOR_msa_min_s_d CODE_FOR_sminv2di3
15430 #define CODE_FOR_msa_mini_s_b CODE_FOR_sminv16qi3
15431 #define CODE_FOR_msa_mini_s_h CODE_FOR_sminv8hi3
15432 #define CODE_FOR_msa_mini_s_w CODE_FOR_sminv4si3
15433 #define CODE_FOR_msa_mini_s_d CODE_FOR_sminv2di3
15434 #define CODE_FOR_msa_min_u_b CODE_FOR_uminv16qi3
15435 #define CODE_FOR_msa_min_u_h CODE_FOR_uminv8hi3
15436 #define CODE_FOR_msa_min_u_w CODE_FOR_uminv4si3
15437 #define CODE_FOR_msa_min_u_d CODE_FOR_uminv2di3
15438 #define CODE_FOR_msa_mini_u_b CODE_FOR_uminv16qi3
15439 #define CODE_FOR_msa_mini_u_h CODE_FOR_uminv8hi3
15440 #define CODE_FOR_msa_mini_u_w CODE_FOR_uminv4si3
15441 #define CODE_FOR_msa_mini_u_d CODE_FOR_uminv2di3
15442 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15443 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15444 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15445 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15446 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15447 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15448 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15449 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15450 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15451 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15452 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15453 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15454 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15455 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15456 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15457 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15458 #define CODE_FOR_msa_mulv_b CODE_FOR_mulv16qi3
15459 #define CODE_FOR_msa_mulv_h CODE_FOR_mulv8hi3
15460 #define CODE_FOR_msa_mulv_w CODE_FOR_mulv4si3
15461 #define CODE_FOR_msa_mulv_d CODE_FOR_mulv2di3
15462 #define CODE_FOR_msa_nlzc_b CODE_FOR_clzv16qi2
15463 #define CODE_FOR_msa_nlzc_h CODE_FOR_clzv8hi2
15464 #define CODE_FOR_msa_nlzc_w CODE_FOR_clzv4si2
15465 #define CODE_FOR_msa_nlzc_d CODE_FOR_clzv2di2
15466 #define CODE_FOR_msa_nor_v CODE_FOR_msa_nor_b
15467 #define CODE_FOR_msa_or_v CODE_FOR_iorv16qi3
15468 #define CODE_FOR_msa_ori_b CODE_FOR_iorv16qi3
15469 #define CODE_FOR_msa_nori_b CODE_FOR_msa_nor_b
15470 #define CODE_FOR_msa_pcnt_b CODE_FOR_popcountv16qi2
15471 #define CODE_FOR_msa_pcnt_h CODE_FOR_popcountv8hi2
15472 #define CODE_FOR_msa_pcnt_w CODE_FOR_popcountv4si2
15473 #define CODE_FOR_msa_pcnt_d CODE_FOR_popcountv2di2
15474 #define CODE_FOR_msa_xor_v CODE_FOR_xorv16qi3
15475 #define CODE_FOR_msa_xori_b CODE_FOR_xorv16qi3
15476 #define CODE_FOR_msa_sll_b CODE_FOR_vashlv16qi3
15477 #define CODE_FOR_msa_sll_h CODE_FOR_vashlv8hi3
15478 #define CODE_FOR_msa_sll_w CODE_FOR_vashlv4si3
15479 #define CODE_FOR_msa_sll_d CODE_FOR_vashlv2di3
15480 #define CODE_FOR_msa_slli_b CODE_FOR_vashlv16qi3
15481 #define CODE_FOR_msa_slli_h CODE_FOR_vashlv8hi3
15482 #define CODE_FOR_msa_slli_w CODE_FOR_vashlv4si3
15483 #define CODE_FOR_msa_slli_d CODE_FOR_vashlv2di3
15484 #define CODE_FOR_msa_sra_b CODE_FOR_vashrv16qi3
15485 #define CODE_FOR_msa_sra_h CODE_FOR_vashrv8hi3
15486 #define CODE_FOR_msa_sra_w CODE_FOR_vashrv4si3
15487 #define CODE_FOR_msa_sra_d CODE_FOR_vashrv2di3
15488 #define CODE_FOR_msa_srai_b CODE_FOR_vashrv16qi3
15489 #define CODE_FOR_msa_srai_h CODE_FOR_vashrv8hi3
15490 #define CODE_FOR_msa_srai_w CODE_FOR_vashrv4si3
15491 #define CODE_FOR_msa_srai_d CODE_FOR_vashrv2di3
15492 #define CODE_FOR_msa_srl_b CODE_FOR_vlshrv16qi3
15493 #define CODE_FOR_msa_srl_h CODE_FOR_vlshrv8hi3
15494 #define CODE_FOR_msa_srl_w CODE_FOR_vlshrv4si3
15495 #define CODE_FOR_msa_srl_d CODE_FOR_vlshrv2di3
15496 #define CODE_FOR_msa_srli_b CODE_FOR_vlshrv16qi3
15497 #define CODE_FOR_msa_srli_h CODE_FOR_vlshrv8hi3
15498 #define CODE_FOR_msa_srli_w CODE_FOR_vlshrv4si3
15499 #define CODE_FOR_msa_srli_d CODE_FOR_vlshrv2di3
15500 #define CODE_FOR_msa_subv_b CODE_FOR_subv16qi3
15501 #define CODE_FOR_msa_subv_h CODE_FOR_subv8hi3
15502 #define CODE_FOR_msa_subv_w CODE_FOR_subv4si3
15503 #define CODE_FOR_msa_subv_d CODE_FOR_subv2di3
15504 #define CODE_FOR_msa_subvi_b CODE_FOR_subv16qi3
15505 #define CODE_FOR_msa_subvi_h CODE_FOR_subv8hi3
15506 #define CODE_FOR_msa_subvi_w CODE_FOR_subv4si3
15507 #define CODE_FOR_msa_subvi_d CODE_FOR_subv2di3
15509 #define CODE_FOR_msa_move_v CODE_FOR_movv16qi
15511 #define CODE_FOR_msa_vshf_b CODE_FOR_vec_permv16qi
15512 #define CODE_FOR_msa_vshf_h CODE_FOR_vec_permv8hi
15513 #define CODE_FOR_msa_vshf_w CODE_FOR_vec_permv4si
15514 #define CODE_FOR_msa_vshf_d CODE_FOR_vec_permv2di
15516 #define CODE_FOR_msa_ilvod_d CODE_FOR_msa_ilvl_d
15517 #define CODE_FOR_msa_ilvev_d CODE_FOR_msa_ilvr_d
15518 #define CODE_FOR_msa_pckod_d CODE_FOR_msa_ilvl_d
15519 #define CODE_FOR_msa_pckev_d CODE_FOR_msa_ilvr_d
15521 #define CODE_FOR_msa_ldi_b CODE_FOR_msa_ldiv16qi
15522 #define CODE_FOR_msa_ldi_h CODE_FOR_msa_ldiv8hi
15523 #define CODE_FOR_msa_ldi_w CODE_FOR_msa_ldiv4si
15524 #define CODE_FOR_msa_ldi_d CODE_FOR_msa_ldiv2di
15526 static const struct mips_builtin_description mips_builtins
[] = {
15527 #define MIPS_GET_FCSR 0
15528 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
15529 #define MIPS_SET_FCSR 1
15530 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
15532 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15533 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15534 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15535 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15536 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
15537 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
15538 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
15539 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
15541 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
15542 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15543 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15544 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15545 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15547 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
15548 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
15549 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15550 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
15551 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
15552 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15554 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
15555 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
15556 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15557 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
15558 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
15559 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15561 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
15563 /* Built-in functions for the SB-1 processor. */
15564 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
15566 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
15567 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15568 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15569 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15570 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15571 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15572 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15573 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15574 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15575 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15576 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15577 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15578 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15579 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15580 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
15581 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
15582 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
15583 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
15584 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
15585 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
15586 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
15587 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
15588 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
15589 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15590 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15591 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15592 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15593 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15594 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15595 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15596 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15597 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
15598 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15599 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15600 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15601 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
15602 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15603 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15604 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15605 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
15606 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
15607 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15608 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
15609 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
15610 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
15611 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15612 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
15613 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
15614 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15615 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15616 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15617 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15618 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15619 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15620 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15621 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15622 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15623 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15624 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15625 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15626 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
15627 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
15628 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15629 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15630 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15631 BPOSGE_BUILTIN (32, dsp
),
15633 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
15634 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
15635 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15636 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15637 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15638 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15639 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15640 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15641 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15642 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15643 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15644 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15645 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15646 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15647 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15648 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15649 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
15650 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
15651 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
15652 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15653 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
15654 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
15655 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
15656 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15657 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15658 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15659 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15660 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15661 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15662 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15663 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15664 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15665 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15666 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15667 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15669 /* Built-in functions for the DSP ASE (32-bit only). */
15670 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15671 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15672 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15673 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15674 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15675 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15676 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15677 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15678 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15679 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15680 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15681 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15682 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15683 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15684 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15685 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15686 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15687 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15688 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15689 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
15690 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
15691 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15692 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
15693 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15694 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
15695 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
15696 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
15698 /* Built-in functions for the DSP ASE (64-bit only). */
15699 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
15701 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
15702 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15703 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15704 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15705 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15706 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15707 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15708 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15709 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15710 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15712 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
15713 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
15714 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
15715 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
15716 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15717 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15718 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15719 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15720 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15721 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15722 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
15723 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
15724 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15725 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15726 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15727 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15728 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
15729 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15730 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15731 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15732 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
15733 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15734 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15735 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15736 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15737 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15738 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15739 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15740 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15741 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15742 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15743 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15744 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15745 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15746 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15747 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15748 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15749 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15750 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
15751 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
15752 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15753 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15754 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15755 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15756 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15757 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15758 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15759 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15760 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
15761 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15762 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15763 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15764 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15765 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
15766 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
15767 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15768 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15769 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15770 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
15771 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15772 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
15773 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
15774 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15775 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15776 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15777 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15778 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15779 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15780 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15781 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15782 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15783 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15784 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15785 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15786 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15787 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15788 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15789 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15790 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15791 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15792 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15793 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15794 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
15795 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
15796 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15797 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15798 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15799 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15800 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15801 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15802 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15803 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15804 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15805 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15806 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15807 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15808 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15809 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15810 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15811 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15813 /* Sundry other built-in functions. */
15814 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
),
15816 /* Built-in functions for MSA. */
15817 MSA_BUILTIN (sll_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15818 MSA_BUILTIN (sll_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15819 MSA_BUILTIN (sll_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15820 MSA_BUILTIN (sll_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15821 MSA_BUILTIN (slli_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15822 MSA_BUILTIN (slli_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15823 MSA_BUILTIN (slli_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15824 MSA_BUILTIN (slli_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15825 MSA_BUILTIN (sra_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15826 MSA_BUILTIN (sra_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15827 MSA_BUILTIN (sra_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15828 MSA_BUILTIN (sra_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15829 MSA_BUILTIN (srai_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15830 MSA_BUILTIN (srai_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15831 MSA_BUILTIN (srai_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15832 MSA_BUILTIN (srai_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15833 MSA_BUILTIN (srar_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15834 MSA_BUILTIN (srar_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15835 MSA_BUILTIN (srar_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15836 MSA_BUILTIN (srar_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15837 MSA_BUILTIN (srari_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15838 MSA_BUILTIN (srari_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15839 MSA_BUILTIN (srari_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15840 MSA_BUILTIN (srari_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15841 MSA_BUILTIN (srl_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15842 MSA_BUILTIN (srl_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15843 MSA_BUILTIN (srl_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15844 MSA_BUILTIN (srl_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15845 MSA_BUILTIN (srli_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15846 MSA_BUILTIN (srli_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15847 MSA_BUILTIN (srli_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15848 MSA_BUILTIN (srli_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15849 MSA_BUILTIN (srlr_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15850 MSA_BUILTIN (srlr_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15851 MSA_BUILTIN (srlr_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15852 MSA_BUILTIN (srlr_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15853 MSA_BUILTIN (srlri_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15854 MSA_BUILTIN (srlri_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15855 MSA_BUILTIN (srlri_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15856 MSA_BUILTIN (srlri_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15857 MSA_BUILTIN (bclr_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15858 MSA_BUILTIN (bclr_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15859 MSA_BUILTIN (bclr_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15860 MSA_BUILTIN (bclr_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15861 MSA_BUILTIN (bclri_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15862 MSA_BUILTIN (bclri_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15863 MSA_BUILTIN (bclri_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15864 MSA_BUILTIN (bclri_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15865 MSA_BUILTIN (bset_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15866 MSA_BUILTIN (bset_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15867 MSA_BUILTIN (bset_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15868 MSA_BUILTIN (bset_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15869 MSA_BUILTIN (bseti_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15870 MSA_BUILTIN (bseti_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15871 MSA_BUILTIN (bseti_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15872 MSA_BUILTIN (bseti_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15873 MSA_BUILTIN (bneg_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15874 MSA_BUILTIN (bneg_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15875 MSA_BUILTIN (bneg_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15876 MSA_BUILTIN (bneg_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15877 MSA_BUILTIN (bnegi_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15878 MSA_BUILTIN (bnegi_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15879 MSA_BUILTIN (bnegi_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15880 MSA_BUILTIN (bnegi_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15881 MSA_BUILTIN (binsl_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
15882 MSA_BUILTIN (binsl_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI
),
15883 MSA_BUILTIN (binsl_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI
),
15884 MSA_BUILTIN (binsl_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI
),
15885 MSA_BUILTIN (binsli_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
15886 MSA_BUILTIN (binsli_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI
),
15887 MSA_BUILTIN (binsli_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI
),
15888 MSA_BUILTIN (binsli_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI
),
15889 MSA_BUILTIN (binsr_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
15890 MSA_BUILTIN (binsr_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI
),
15891 MSA_BUILTIN (binsr_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI
),
15892 MSA_BUILTIN (binsr_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI
),
15893 MSA_BUILTIN (binsri_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
15894 MSA_BUILTIN (binsri_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI
),
15895 MSA_BUILTIN (binsri_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI
),
15896 MSA_BUILTIN (binsri_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI
),
15897 MSA_BUILTIN (addv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15898 MSA_BUILTIN (addv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15899 MSA_BUILTIN (addv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15900 MSA_BUILTIN (addv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15901 MSA_BUILTIN (addvi_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15902 MSA_BUILTIN (addvi_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15903 MSA_BUILTIN (addvi_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15904 MSA_BUILTIN (addvi_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15905 MSA_BUILTIN (subv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15906 MSA_BUILTIN (subv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15907 MSA_BUILTIN (subv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15908 MSA_BUILTIN (subv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15909 MSA_BUILTIN (subvi_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15910 MSA_BUILTIN (subvi_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15911 MSA_BUILTIN (subvi_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15912 MSA_BUILTIN (subvi_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15913 MSA_BUILTIN (max_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15914 MSA_BUILTIN (max_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15915 MSA_BUILTIN (max_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15916 MSA_BUILTIN (max_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15917 MSA_BUILTIN (maxi_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15918 MSA_BUILTIN (maxi_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
15919 MSA_BUILTIN (maxi_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
15920 MSA_BUILTIN (maxi_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
15921 MSA_BUILTIN (max_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15922 MSA_BUILTIN (max_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15923 MSA_BUILTIN (max_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15924 MSA_BUILTIN (max_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15925 MSA_BUILTIN (maxi_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15926 MSA_BUILTIN (maxi_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15927 MSA_BUILTIN (maxi_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15928 MSA_BUILTIN (maxi_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15929 MSA_BUILTIN (min_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15930 MSA_BUILTIN (min_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15931 MSA_BUILTIN (min_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15932 MSA_BUILTIN (min_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15933 MSA_BUILTIN (mini_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15934 MSA_BUILTIN (mini_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
15935 MSA_BUILTIN (mini_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
15936 MSA_BUILTIN (mini_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
15937 MSA_BUILTIN (min_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15938 MSA_BUILTIN (min_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15939 MSA_BUILTIN (min_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15940 MSA_BUILTIN (min_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15941 MSA_BUILTIN (mini_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15942 MSA_BUILTIN (mini_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15943 MSA_BUILTIN (mini_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15944 MSA_BUILTIN (mini_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15945 MSA_BUILTIN (max_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15946 MSA_BUILTIN (max_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15947 MSA_BUILTIN (max_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15948 MSA_BUILTIN (max_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15949 MSA_BUILTIN (min_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15950 MSA_BUILTIN (min_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15951 MSA_BUILTIN (min_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15952 MSA_BUILTIN (min_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15953 MSA_BUILTIN (ceq_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15954 MSA_BUILTIN (ceq_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15955 MSA_BUILTIN (ceq_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15956 MSA_BUILTIN (ceq_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15957 MSA_BUILTIN (ceqi_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15958 MSA_BUILTIN (ceqi_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
15959 MSA_BUILTIN (ceqi_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
15960 MSA_BUILTIN (ceqi_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
15961 MSA_BUILTIN (clt_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15962 MSA_BUILTIN (clt_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15963 MSA_BUILTIN (clt_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15964 MSA_BUILTIN (clt_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15965 MSA_BUILTIN (clti_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15966 MSA_BUILTIN (clti_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
15967 MSA_BUILTIN (clti_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
15968 MSA_BUILTIN (clti_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
15969 MSA_BUILTIN (clt_u_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
15970 MSA_BUILTIN (clt_u_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
15971 MSA_BUILTIN (clt_u_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
15972 MSA_BUILTIN (clt_u_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
15973 MSA_BUILTIN (clti_u_b
, MIPS_V16QI_FTYPE_UV16QI_UQI
),
15974 MSA_BUILTIN (clti_u_h
, MIPS_V8HI_FTYPE_UV8HI_UQI
),
15975 MSA_BUILTIN (clti_u_w
, MIPS_V4SI_FTYPE_UV4SI_UQI
),
15976 MSA_BUILTIN (clti_u_d
, MIPS_V2DI_FTYPE_UV2DI_UQI
),
15977 MSA_BUILTIN (cle_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15978 MSA_BUILTIN (cle_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15979 MSA_BUILTIN (cle_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15980 MSA_BUILTIN (cle_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15981 MSA_BUILTIN (clei_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15982 MSA_BUILTIN (clei_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
15983 MSA_BUILTIN (clei_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
15984 MSA_BUILTIN (clei_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
15985 MSA_BUILTIN (cle_u_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
15986 MSA_BUILTIN (cle_u_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
15987 MSA_BUILTIN (cle_u_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
15988 MSA_BUILTIN (cle_u_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
15989 MSA_BUILTIN (clei_u_b
, MIPS_V16QI_FTYPE_UV16QI_UQI
),
15990 MSA_BUILTIN (clei_u_h
, MIPS_V8HI_FTYPE_UV8HI_UQI
),
15991 MSA_BUILTIN (clei_u_w
, MIPS_V4SI_FTYPE_UV4SI_UQI
),
15992 MSA_BUILTIN (clei_u_d
, MIPS_V2DI_FTYPE_UV2DI_UQI
),
15993 MSA_BUILTIN (ld_b
, MIPS_V16QI_FTYPE_CVPOINTER_SI
),
15994 MSA_BUILTIN (ld_h
, MIPS_V8HI_FTYPE_CVPOINTER_SI
),
15995 MSA_BUILTIN (ld_w
, MIPS_V4SI_FTYPE_CVPOINTER_SI
),
15996 MSA_BUILTIN (ld_d
, MIPS_V2DI_FTYPE_CVPOINTER_SI
),
15997 MSA_NO_TARGET_BUILTIN (st_b
, MIPS_VOID_FTYPE_V16QI_CVPOINTER_SI
),
15998 MSA_NO_TARGET_BUILTIN (st_h
, MIPS_VOID_FTYPE_V8HI_CVPOINTER_SI
),
15999 MSA_NO_TARGET_BUILTIN (st_w
, MIPS_VOID_FTYPE_V4SI_CVPOINTER_SI
),
16000 MSA_NO_TARGET_BUILTIN (st_d
, MIPS_VOID_FTYPE_V2DI_CVPOINTER_SI
),
16001 MSA_BUILTIN (sat_s_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16002 MSA_BUILTIN (sat_s_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16003 MSA_BUILTIN (sat_s_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16004 MSA_BUILTIN (sat_s_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16005 MSA_BUILTIN (sat_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16006 MSA_BUILTIN (sat_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
16007 MSA_BUILTIN (sat_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
16008 MSA_BUILTIN (sat_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
16009 MSA_BUILTIN (add_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16010 MSA_BUILTIN (add_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16011 MSA_BUILTIN (add_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16012 MSA_BUILTIN (add_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16013 MSA_BUILTIN (adds_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16014 MSA_BUILTIN (adds_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16015 MSA_BUILTIN (adds_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16016 MSA_BUILTIN (adds_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16017 MSA_BUILTIN (adds_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16018 MSA_BUILTIN (adds_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16019 MSA_BUILTIN (adds_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16020 MSA_BUILTIN (adds_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16021 MSA_BUILTIN (adds_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16022 MSA_BUILTIN (adds_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16023 MSA_BUILTIN (adds_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16024 MSA_BUILTIN (adds_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16025 MSA_BUILTIN (ave_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16026 MSA_BUILTIN (ave_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16027 MSA_BUILTIN (ave_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16028 MSA_BUILTIN (ave_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16029 MSA_BUILTIN (ave_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16030 MSA_BUILTIN (ave_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16031 MSA_BUILTIN (ave_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16032 MSA_BUILTIN (ave_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16033 MSA_BUILTIN (aver_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16034 MSA_BUILTIN (aver_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16035 MSA_BUILTIN (aver_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16036 MSA_BUILTIN (aver_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16037 MSA_BUILTIN (aver_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16038 MSA_BUILTIN (aver_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16039 MSA_BUILTIN (aver_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16040 MSA_BUILTIN (aver_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16041 MSA_BUILTIN (subs_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16042 MSA_BUILTIN (subs_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16043 MSA_BUILTIN (subs_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16044 MSA_BUILTIN (subs_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16045 MSA_BUILTIN (subs_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16046 MSA_BUILTIN (subs_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16047 MSA_BUILTIN (subs_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16048 MSA_BUILTIN (subs_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16049 MSA_BUILTIN (subsuu_s_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
16050 MSA_BUILTIN (subsuu_s_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
16051 MSA_BUILTIN (subsuu_s_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
16052 MSA_BUILTIN (subsuu_s_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
16053 MSA_BUILTIN (subsus_u_b
, MIPS_UV16QI_FTYPE_UV16QI_V16QI
),
16054 MSA_BUILTIN (subsus_u_h
, MIPS_UV8HI_FTYPE_UV8HI_V8HI
),
16055 MSA_BUILTIN (subsus_u_w
, MIPS_UV4SI_FTYPE_UV4SI_V4SI
),
16056 MSA_BUILTIN (subsus_u_d
, MIPS_UV2DI_FTYPE_UV2DI_V2DI
),
16057 MSA_BUILTIN (asub_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16058 MSA_BUILTIN (asub_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16059 MSA_BUILTIN (asub_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16060 MSA_BUILTIN (asub_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16061 MSA_BUILTIN (asub_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16062 MSA_BUILTIN (asub_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16063 MSA_BUILTIN (asub_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16064 MSA_BUILTIN (asub_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16065 MSA_BUILTIN (mulv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16066 MSA_BUILTIN (mulv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16067 MSA_BUILTIN (mulv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16068 MSA_BUILTIN (mulv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16069 MSA_BUILTIN (maddv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16070 MSA_BUILTIN (maddv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16071 MSA_BUILTIN (maddv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16072 MSA_BUILTIN (maddv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16073 MSA_BUILTIN (msubv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16074 MSA_BUILTIN (msubv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16075 MSA_BUILTIN (msubv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16076 MSA_BUILTIN (msubv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16077 MSA_BUILTIN (div_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16078 MSA_BUILTIN (div_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16079 MSA_BUILTIN (div_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16080 MSA_BUILTIN (div_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16081 MSA_BUILTIN (div_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16082 MSA_BUILTIN (div_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16083 MSA_BUILTIN (div_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16084 MSA_BUILTIN (div_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16085 MSA_BUILTIN (hadd_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16086 MSA_BUILTIN (hadd_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16087 MSA_BUILTIN (hadd_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16088 MSA_BUILTIN (hadd_u_h
, MIPS_UV8HI_FTYPE_UV16QI_UV16QI
),
16089 MSA_BUILTIN (hadd_u_w
, MIPS_UV4SI_FTYPE_UV8HI_UV8HI
),
16090 MSA_BUILTIN (hadd_u_d
, MIPS_UV2DI_FTYPE_UV4SI_UV4SI
),
16091 MSA_BUILTIN (hsub_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16092 MSA_BUILTIN (hsub_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16093 MSA_BUILTIN (hsub_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16094 MSA_BUILTIN (hsub_u_h
, MIPS_V8HI_FTYPE_UV16QI_UV16QI
),
16095 MSA_BUILTIN (hsub_u_w
, MIPS_V4SI_FTYPE_UV8HI_UV8HI
),
16096 MSA_BUILTIN (hsub_u_d
, MIPS_V2DI_FTYPE_UV4SI_UV4SI
),
16097 MSA_BUILTIN (mod_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16098 MSA_BUILTIN (mod_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16099 MSA_BUILTIN (mod_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16100 MSA_BUILTIN (mod_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16101 MSA_BUILTIN (mod_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16102 MSA_BUILTIN (mod_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16103 MSA_BUILTIN (mod_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16104 MSA_BUILTIN (mod_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16105 MSA_BUILTIN (dotp_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16106 MSA_BUILTIN (dotp_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16107 MSA_BUILTIN (dotp_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16108 MSA_BUILTIN (dotp_u_h
, MIPS_UV8HI_FTYPE_UV16QI_UV16QI
),
16109 MSA_BUILTIN (dotp_u_w
, MIPS_UV4SI_FTYPE_UV8HI_UV8HI
),
16110 MSA_BUILTIN (dotp_u_d
, MIPS_UV2DI_FTYPE_UV4SI_UV4SI
),
16111 MSA_BUILTIN (dpadd_s_h
, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI
),
16112 MSA_BUILTIN (dpadd_s_w
, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI
),
16113 MSA_BUILTIN (dpadd_s_d
, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI
),
16114 MSA_BUILTIN (dpadd_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV16QI_UV16QI
),
16115 MSA_BUILTIN (dpadd_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV8HI_UV8HI
),
16116 MSA_BUILTIN (dpadd_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV4SI_UV4SI
),
16117 MSA_BUILTIN (dpsub_s_h
, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI
),
16118 MSA_BUILTIN (dpsub_s_w
, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI
),
16119 MSA_BUILTIN (dpsub_s_d
, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI
),
16120 MSA_BUILTIN (dpsub_u_h
, MIPS_V8HI_FTYPE_V8HI_UV16QI_UV16QI
),
16121 MSA_BUILTIN (dpsub_u_w
, MIPS_V4SI_FTYPE_V4SI_UV8HI_UV8HI
),
16122 MSA_BUILTIN (dpsub_u_d
, MIPS_V2DI_FTYPE_V2DI_UV4SI_UV4SI
),
16123 MSA_BUILTIN (sld_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_SI
),
16124 MSA_BUILTIN (sld_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_SI
),
16125 MSA_BUILTIN (sld_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_SI
),
16126 MSA_BUILTIN (sld_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_SI
),
16127 MSA_BUILTIN (sldi_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_UQI
),
16128 MSA_BUILTIN (sldi_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_UQI
),
16129 MSA_BUILTIN (sldi_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_UQI
),
16130 MSA_BUILTIN (sldi_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_UQI
),
16131 MSA_BUILTIN (splat_b
, MIPS_V16QI_FTYPE_V16QI_SI
),
16132 MSA_BUILTIN (splat_h
, MIPS_V8HI_FTYPE_V8HI_SI
),
16133 MSA_BUILTIN (splat_w
, MIPS_V4SI_FTYPE_V4SI_SI
),
16134 MSA_BUILTIN (splat_d
, MIPS_V2DI_FTYPE_V2DI_SI
),
16135 MSA_BUILTIN (splati_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16136 MSA_BUILTIN (splati_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16137 MSA_BUILTIN (splati_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16138 MSA_BUILTIN (splati_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16139 MSA_BUILTIN (pckev_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16140 MSA_BUILTIN (pckev_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16141 MSA_BUILTIN (pckev_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16142 MSA_BUILTIN (pckev_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16143 MSA_BUILTIN (pckod_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16144 MSA_BUILTIN (pckod_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16145 MSA_BUILTIN (pckod_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16146 MSA_BUILTIN (pckod_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16147 MSA_BUILTIN (ilvl_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16148 MSA_BUILTIN (ilvl_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16149 MSA_BUILTIN (ilvl_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16150 MSA_BUILTIN (ilvl_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16151 MSA_BUILTIN (ilvr_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16152 MSA_BUILTIN (ilvr_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16153 MSA_BUILTIN (ilvr_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16154 MSA_BUILTIN (ilvr_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16155 MSA_BUILTIN (ilvev_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16156 MSA_BUILTIN (ilvev_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16157 MSA_BUILTIN (ilvev_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16158 MSA_BUILTIN (ilvev_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16159 MSA_BUILTIN (ilvod_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16160 MSA_BUILTIN (ilvod_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16161 MSA_BUILTIN (ilvod_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16162 MSA_BUILTIN (ilvod_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16163 MSA_BUILTIN (vshf_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16164 MSA_BUILTIN (vshf_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16165 MSA_BUILTIN (vshf_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16166 MSA_BUILTIN (vshf_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16167 MSA_BUILTIN (and_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16168 MSA_BUILTIN (andi_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16169 MSA_BUILTIN (or_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16170 MSA_BUILTIN (ori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16171 MSA_BUILTIN (nor_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16172 MSA_BUILTIN (nori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16173 MSA_BUILTIN (xor_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16174 MSA_BUILTIN (xori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16175 MSA_BUILTIN (bmnz_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16176 MSA_BUILTIN (bmnzi_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16177 MSA_BUILTIN (bmz_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16178 MSA_BUILTIN (bmzi_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16179 MSA_BUILTIN (bsel_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16180 MSA_BUILTIN (bseli_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16181 MSA_BUILTIN (shf_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16182 MSA_BUILTIN (shf_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16183 MSA_BUILTIN (shf_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16184 MSA_BUILTIN_TEST_BRANCH (bnz_v
, MIPS_SI_FTYPE_UV16QI
),
16185 MSA_BUILTIN_TEST_BRANCH (bz_v
, MIPS_SI_FTYPE_UV16QI
),
16186 MSA_BUILTIN (fill_b
, MIPS_V16QI_FTYPE_SI
),
16187 MSA_BUILTIN (fill_h
, MIPS_V8HI_FTYPE_SI
),
16188 MSA_BUILTIN (fill_w
, MIPS_V4SI_FTYPE_SI
),
16189 MSA_BUILTIN (fill_d
, MIPS_V2DI_FTYPE_DI
),
16190 MSA_BUILTIN (pcnt_b
, MIPS_V16QI_FTYPE_V16QI
),
16191 MSA_BUILTIN (pcnt_h
, MIPS_V8HI_FTYPE_V8HI
),
16192 MSA_BUILTIN (pcnt_w
, MIPS_V4SI_FTYPE_V4SI
),
16193 MSA_BUILTIN (pcnt_d
, MIPS_V2DI_FTYPE_V2DI
),
16194 MSA_BUILTIN (nloc_b
, MIPS_V16QI_FTYPE_V16QI
),
16195 MSA_BUILTIN (nloc_h
, MIPS_V8HI_FTYPE_V8HI
),
16196 MSA_BUILTIN (nloc_w
, MIPS_V4SI_FTYPE_V4SI
),
16197 MSA_BUILTIN (nloc_d
, MIPS_V2DI_FTYPE_V2DI
),
16198 MSA_BUILTIN (nlzc_b
, MIPS_V16QI_FTYPE_V16QI
),
16199 MSA_BUILTIN (nlzc_h
, MIPS_V8HI_FTYPE_V8HI
),
16200 MSA_BUILTIN (nlzc_w
, MIPS_V4SI_FTYPE_V4SI
),
16201 MSA_BUILTIN (nlzc_d
, MIPS_V2DI_FTYPE_V2DI
),
16202 MSA_BUILTIN (copy_s_b
, MIPS_SI_FTYPE_V16QI_UQI
),
16203 MSA_BUILTIN (copy_s_h
, MIPS_SI_FTYPE_V8HI_UQI
),
16204 MSA_BUILTIN (copy_s_w
, MIPS_SI_FTYPE_V4SI_UQI
),
16205 MSA_BUILTIN (copy_s_d
, MIPS_DI_FTYPE_V2DI_UQI
),
16206 MSA_BUILTIN (copy_u_b
, MIPS_USI_FTYPE_V16QI_UQI
),
16207 MSA_BUILTIN (copy_u_h
, MIPS_USI_FTYPE_V8HI_UQI
),
16208 MSA_BUILTIN_REMAP (copy_u_w
, copy_s_w
, MIPS_USI_FTYPE_V4SI_UQI
),
16209 MSA_BUILTIN_REMAP (copy_u_d
, copy_s_d
, MIPS_UDI_FTYPE_V2DI_UQI
),
16210 MSA_BUILTIN (insert_b
, MIPS_V16QI_FTYPE_V16QI_UQI_SI
),
16211 MSA_BUILTIN (insert_h
, MIPS_V8HI_FTYPE_V8HI_UQI_SI
),
16212 MSA_BUILTIN (insert_w
, MIPS_V4SI_FTYPE_V4SI_UQI_SI
),
16213 MSA_BUILTIN (insert_d
, MIPS_V2DI_FTYPE_V2DI_UQI_DI
),
16214 MSA_BUILTIN (insve_b
, MIPS_V16QI_FTYPE_V16QI_UQI_V16QI
),
16215 MSA_BUILTIN (insve_h
, MIPS_V8HI_FTYPE_V8HI_UQI_V8HI
),
16216 MSA_BUILTIN (insve_w
, MIPS_V4SI_FTYPE_V4SI_UQI_V4SI
),
16217 MSA_BUILTIN (insve_d
, MIPS_V2DI_FTYPE_V2DI_UQI_V2DI
),
16218 MSA_BUILTIN_TEST_BRANCH (bnz_b
, MIPS_SI_FTYPE_UV16QI
),
16219 MSA_BUILTIN_TEST_BRANCH (bnz_h
, MIPS_SI_FTYPE_UV8HI
),
16220 MSA_BUILTIN_TEST_BRANCH (bnz_w
, MIPS_SI_FTYPE_UV4SI
),
16221 MSA_BUILTIN_TEST_BRANCH (bnz_d
, MIPS_SI_FTYPE_UV2DI
),
16222 MSA_BUILTIN_TEST_BRANCH (bz_b
, MIPS_SI_FTYPE_UV16QI
),
16223 MSA_BUILTIN_TEST_BRANCH (bz_h
, MIPS_SI_FTYPE_UV8HI
),
16224 MSA_BUILTIN_TEST_BRANCH (bz_w
, MIPS_SI_FTYPE_UV4SI
),
16225 MSA_BUILTIN_TEST_BRANCH (bz_d
, MIPS_SI_FTYPE_UV2DI
),
16226 MSA_BUILTIN (ldi_b
, MIPS_V16QI_FTYPE_HI
),
16227 MSA_BUILTIN (ldi_h
, MIPS_V8HI_FTYPE_HI
),
16228 MSA_BUILTIN (ldi_w
, MIPS_V4SI_FTYPE_HI
),
16229 MSA_BUILTIN (ldi_d
, MIPS_V2DI_FTYPE_HI
),
16230 MSA_BUILTIN (fcaf_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16231 MSA_BUILTIN (fcaf_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16232 MSA_BUILTIN (fcor_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16233 MSA_BUILTIN (fcor_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16234 MSA_BUILTIN (fcun_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16235 MSA_BUILTIN (fcun_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16236 MSA_BUILTIN (fcune_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16237 MSA_BUILTIN (fcune_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16238 MSA_BUILTIN (fcueq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16239 MSA_BUILTIN (fcueq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16240 MSA_BUILTIN (fceq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16241 MSA_BUILTIN (fceq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16242 MSA_BUILTIN (fcne_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16243 MSA_BUILTIN (fcne_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16244 MSA_BUILTIN (fclt_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16245 MSA_BUILTIN (fclt_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16246 MSA_BUILTIN (fcult_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16247 MSA_BUILTIN (fcult_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16248 MSA_BUILTIN (fcle_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16249 MSA_BUILTIN (fcle_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16250 MSA_BUILTIN (fcule_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16251 MSA_BUILTIN (fcule_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16252 MSA_BUILTIN (fsaf_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16253 MSA_BUILTIN (fsaf_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16254 MSA_BUILTIN (fsor_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16255 MSA_BUILTIN (fsor_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16256 MSA_BUILTIN (fsun_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16257 MSA_BUILTIN (fsun_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16258 MSA_BUILTIN (fsune_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16259 MSA_BUILTIN (fsune_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16260 MSA_BUILTIN (fsueq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16261 MSA_BUILTIN (fsueq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16262 MSA_BUILTIN (fseq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16263 MSA_BUILTIN (fseq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16264 MSA_BUILTIN (fsne_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16265 MSA_BUILTIN (fsne_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16266 MSA_BUILTIN (fslt_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16267 MSA_BUILTIN (fslt_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16268 MSA_BUILTIN (fsult_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16269 MSA_BUILTIN (fsult_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16270 MSA_BUILTIN (fsle_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16271 MSA_BUILTIN (fsle_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16272 MSA_BUILTIN (fsule_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16273 MSA_BUILTIN (fsule_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16274 MSA_BUILTIN (fadd_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16275 MSA_BUILTIN (fadd_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16276 MSA_BUILTIN (fsub_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16277 MSA_BUILTIN (fsub_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16278 MSA_BUILTIN (fmul_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16279 MSA_BUILTIN (fmul_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16280 MSA_BUILTIN (fdiv_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16281 MSA_BUILTIN (fdiv_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16282 MSA_BUILTIN (fmadd_w
, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF
),
16283 MSA_BUILTIN (fmadd_d
, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF
),
16284 MSA_BUILTIN (fmsub_w
, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF
),
16285 MSA_BUILTIN (fmsub_d
, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF
),
16286 MSA_BUILTIN (fexp2_w
, MIPS_V4SF_FTYPE_V4SF_V4SI
),
16287 MSA_BUILTIN (fexp2_d
, MIPS_V2DF_FTYPE_V2DF_V2DI
),
16288 MSA_BUILTIN (fexdo_h
, MIPS_V8HI_FTYPE_V4SF_V4SF
),
16289 MSA_BUILTIN (fexdo_w
, MIPS_V4SF_FTYPE_V2DF_V2DF
),
16290 MSA_BUILTIN (ftq_h
, MIPS_V8HI_FTYPE_V4SF_V4SF
),
16291 MSA_BUILTIN (ftq_w
, MIPS_V4SI_FTYPE_V2DF_V2DF
),
16292 MSA_BUILTIN (fmin_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16293 MSA_BUILTIN (fmin_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16294 MSA_BUILTIN (fmin_a_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16295 MSA_BUILTIN (fmin_a_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16296 MSA_BUILTIN (fmax_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16297 MSA_BUILTIN (fmax_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16298 MSA_BUILTIN (fmax_a_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16299 MSA_BUILTIN (fmax_a_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16300 MSA_BUILTIN (mul_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16301 MSA_BUILTIN (mul_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16302 MSA_BUILTIN (mulr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16303 MSA_BUILTIN (mulr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16304 MSA_BUILTIN (madd_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16305 MSA_BUILTIN (madd_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16306 MSA_BUILTIN (maddr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16307 MSA_BUILTIN (maddr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16308 MSA_BUILTIN (msub_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16309 MSA_BUILTIN (msub_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16310 MSA_BUILTIN (msubr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16311 MSA_BUILTIN (msubr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16312 MSA_BUILTIN (fclass_w
, MIPS_V4SI_FTYPE_V4SF
),
16313 MSA_BUILTIN (fclass_d
, MIPS_V2DI_FTYPE_V2DF
),
16314 MSA_BUILTIN (fsqrt_w
, MIPS_V4SF_FTYPE_V4SF
),
16315 MSA_BUILTIN (fsqrt_d
, MIPS_V2DF_FTYPE_V2DF
),
16316 MSA_BUILTIN (frcp_w
, MIPS_V4SF_FTYPE_V4SF
),
16317 MSA_BUILTIN (frcp_d
, MIPS_V2DF_FTYPE_V2DF
),
16318 MSA_BUILTIN (frint_w
, MIPS_V4SF_FTYPE_V4SF
),
16319 MSA_BUILTIN (frint_d
, MIPS_V2DF_FTYPE_V2DF
),
16320 MSA_BUILTIN (frsqrt_w
, MIPS_V4SF_FTYPE_V4SF
),
16321 MSA_BUILTIN (frsqrt_d
, MIPS_V2DF_FTYPE_V2DF
),
16322 MSA_BUILTIN (flog2_w
, MIPS_V4SF_FTYPE_V4SF
),
16323 MSA_BUILTIN (flog2_d
, MIPS_V2DF_FTYPE_V2DF
),
16324 MSA_BUILTIN (fexupl_w
, MIPS_V4SF_FTYPE_V8HI
),
16325 MSA_BUILTIN (fexupl_d
, MIPS_V2DF_FTYPE_V4SF
),
16326 MSA_BUILTIN (fexupr_w
, MIPS_V4SF_FTYPE_V8HI
),
16327 MSA_BUILTIN (fexupr_d
, MIPS_V2DF_FTYPE_V4SF
),
16328 MSA_BUILTIN (ffql_w
, MIPS_V4SF_FTYPE_V8HI
),
16329 MSA_BUILTIN (ffql_d
, MIPS_V2DF_FTYPE_V4SI
),
16330 MSA_BUILTIN (ffqr_w
, MIPS_V4SF_FTYPE_V8HI
),
16331 MSA_BUILTIN (ffqr_d
, MIPS_V2DF_FTYPE_V4SI
),
16332 MSA_BUILTIN (ftint_s_w
, MIPS_V4SI_FTYPE_V4SF
),
16333 MSA_BUILTIN (ftint_s_d
, MIPS_V2DI_FTYPE_V2DF
),
16334 MSA_BUILTIN (ftint_u_w
, MIPS_UV4SI_FTYPE_V4SF
),
16335 MSA_BUILTIN (ftint_u_d
, MIPS_UV2DI_FTYPE_V2DF
),
16336 MSA_BUILTIN (ftrunc_s_w
, MIPS_V4SI_FTYPE_V4SF
),
16337 MSA_BUILTIN (ftrunc_s_d
, MIPS_V2DI_FTYPE_V2DF
),
16338 MSA_BUILTIN (ftrunc_u_w
, MIPS_UV4SI_FTYPE_V4SF
),
16339 MSA_BUILTIN (ftrunc_u_d
, MIPS_UV2DI_FTYPE_V2DF
),
16340 MSA_BUILTIN (ffint_s_w
, MIPS_V4SF_FTYPE_V4SI
),
16341 MSA_BUILTIN (ffint_s_d
, MIPS_V2DF_FTYPE_V2DI
),
16342 MSA_BUILTIN (ffint_u_w
, MIPS_V4SF_FTYPE_UV4SI
),
16343 MSA_BUILTIN (ffint_u_d
, MIPS_V2DF_FTYPE_UV2DI
),
16344 MSA_NO_TARGET_BUILTIN (ctcmsa
, MIPS_VOID_FTYPE_UQI_SI
),
16345 MSA_BUILTIN (cfcmsa
, MIPS_SI_FTYPE_UQI
),
16346 MSA_BUILTIN (move_v
, MIPS_V16QI_FTYPE_V16QI
),
16349 /* Index I is the function declaration for mips_builtins[I], or null if the
16350 function isn't defined on this target. */
16351 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
16352 /* Get the index I of the function declaration for mips_builtin_decls[I]
16353 using the instruction code or return null if not defined for the target. */
16354 static GTY(()) int mips_get_builtin_decl_index
[NUM_INSN_CODES
];
16356 /* MODE is a vector mode whose elements have type TYPE. Return the type
16357 of the vector itself. */
16360 mips_builtin_vector_type (tree type
, machine_mode mode
)
16362 static tree types
[2 * (int) MAX_MACHINE_MODE
];
16365 mode_index
= (int) mode
;
16367 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
16368 mode_index
+= MAX_MACHINE_MODE
;
16370 if (types
[mode_index
] == NULL_TREE
)
16371 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
16372 return types
[mode_index
];
16375 /* Return a type for 'const volatile void *'. */
16378 mips_build_cvpointer_type (void)
16382 if (cache
== NULL_TREE
)
16383 cache
= build_pointer_type (build_qualified_type
16385 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
16389 /* Source-level argument types. */
16390 #define MIPS_ATYPE_VOID void_type_node
16391 #define MIPS_ATYPE_INT integer_type_node
16392 #define MIPS_ATYPE_POINTER ptr_type_node
16393 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
16395 /* Standard mode-based argument types. */
16396 #define MIPS_ATYPE_QI intQI_type_node
16397 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
16398 #define MIPS_ATYPE_HI intHI_type_node
16399 #define MIPS_ATYPE_SI intSI_type_node
16400 #define MIPS_ATYPE_USI unsigned_intSI_type_node
16401 #define MIPS_ATYPE_DI intDI_type_node
16402 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
16403 #define MIPS_ATYPE_SF float_type_node
16404 #define MIPS_ATYPE_DF double_type_node
16406 /* Vector argument types. */
16407 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
16408 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
16409 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
16410 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
16411 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
16412 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
16414 #define MIPS_ATYPE_V2DI \
16415 mips_builtin_vector_type (long_long_integer_type_node, V2DImode)
16416 #define MIPS_ATYPE_V4SI mips_builtin_vector_type (intSI_type_node, V4SImode)
16417 #define MIPS_ATYPE_V8HI mips_builtin_vector_type (intHI_type_node, V8HImode)
16418 #define MIPS_ATYPE_V16QI mips_builtin_vector_type (intQI_type_node, V16QImode)
16419 #define MIPS_ATYPE_V2DF mips_builtin_vector_type (double_type_node, V2DFmode)
16420 #define MIPS_ATYPE_V4SF mips_builtin_vector_type (float_type_node, V4SFmode)
16422 #define MIPS_ATYPE_UV2DI \
16423 mips_builtin_vector_type (long_long_unsigned_type_node, V2DImode)
16424 #define MIPS_ATYPE_UV4SI \
16425 mips_builtin_vector_type (unsigned_intSI_type_node, V4SImode)
16426 #define MIPS_ATYPE_UV8HI \
16427 mips_builtin_vector_type (unsigned_intHI_type_node, V8HImode)
16428 #define MIPS_ATYPE_UV16QI \
16429 mips_builtin_vector_type (unsigned_intQI_type_node, V16QImode)
16431 #define MIPS_ATYPE_UV2SI \
16432 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
16433 #define MIPS_ATYPE_UV4HI \
16434 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
16435 #define MIPS_ATYPE_UV8QI \
16436 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
16438 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
16439 their associated MIPS_ATYPEs. */
16440 #define MIPS_FTYPE_ATYPES1(A, B) \
16441 MIPS_ATYPE_##A, MIPS_ATYPE_##B
16443 #define MIPS_FTYPE_ATYPES2(A, B, C) \
16444 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
16446 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
16447 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
16449 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
16450 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
16453 /* Return the function type associated with function prototype TYPE. */
16456 mips_build_function_type (enum mips_function_type type
)
16458 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
16460 if (types
[(int) type
] == NULL_TREE
)
16463 #define DEF_MIPS_FTYPE(NUM, ARGS) \
16464 case MIPS_FTYPE_NAME##NUM ARGS: \
16465 types[(int) type] \
16466 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
16469 #include "config/mips/mips-ftypes.def"
16470 #undef DEF_MIPS_FTYPE
16472 gcc_unreachable ();
16475 return types
[(int) type
];
16478 /* Implement TARGET_INIT_BUILTINS. */
16481 mips_init_builtins (void)
16483 const struct mips_builtin_description
*d
;
16486 /* Iterate through all of the bdesc arrays, initializing all of the
16487 builtin functions. */
16488 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
16490 d
= &mips_builtins
[i
];
16493 mips_builtin_decls
[i
]
16494 = add_builtin_function (d
->name
,
16495 mips_build_function_type (d
->function_type
),
16496 i
, BUILT_IN_MD
, NULL
, NULL
);
16497 mips_get_builtin_decl_index
[d
->icode
] = i
;
16502 /* Implement TARGET_BUILTIN_DECL. */
16505 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
16507 if (code
>= ARRAY_SIZE (mips_builtins
))
16508 return error_mark_node
;
16509 return mips_builtin_decls
[code
];
16512 /* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION. */
16515 mips_builtin_vectorized_function (unsigned int fn
, tree type_out
, tree type_in
)
16517 machine_mode in_mode
, out_mode
;
16520 if (TREE_CODE (type_out
) != VECTOR_TYPE
16521 || TREE_CODE (type_in
) != VECTOR_TYPE
16525 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
16526 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
16527 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
16528 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
16530 /* INSN is the name of the associated instruction pattern, without
16531 the leading CODE_FOR_. */
16532 #define MIPS_GET_BUILTIN(INSN) \
16533 mips_builtin_decls[mips_get_builtin_decl_index[CODE_FOR_##INSN]]
16537 case BUILT_IN_SQRT
:
16538 if (out_mode
== DFmode
&& out_n
== 2
16539 && in_mode
== DFmode
&& in_n
== 2)
16540 return MIPS_GET_BUILTIN (msa_fsqrt_d
);
16542 case BUILT_IN_SQRTF
:
16543 if (out_mode
== SFmode
&& out_n
== 4
16544 && in_mode
== SFmode
&& in_n
== 4)
16545 return MIPS_GET_BUILTIN (msa_fsqrt_w
);
16554 /* Take argument ARGNO from EXP's argument list and convert it into
16555 an expand operand. Store the operand in *OP. */
16558 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
16559 unsigned int argno
)
16564 arg
= CALL_EXPR_ARG (exp
, argno
);
16565 value
= expand_normal (arg
);
16566 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
16569 /* Expand instruction ICODE as part of a built-in function sequence.
16570 Use the first NOPS elements of OPS as the instruction's operands.
16571 HAS_TARGET_P is true if operand 0 is a target; it is false if the
16572 instruction has no target.
16574 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
16577 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
16578 struct expand_operand
*ops
, bool has_target_p
)
16580 machine_mode imode
;
16581 int rangelo
= 0, rangehi
= 0, error_opno
= 0;
16586 /* The third operand of these instructions is in SImode, so we need to
16587 bring the corresponding builtin argument from QImode into SImode. */
16588 case CODE_FOR_loongson_pshufh
:
16589 case CODE_FOR_loongson_psllh
:
16590 case CODE_FOR_loongson_psllw
:
16591 case CODE_FOR_loongson_psrah
:
16592 case CODE_FOR_loongson_psraw
:
16593 case CODE_FOR_loongson_psrlh
:
16594 case CODE_FOR_loongson_psrlw
:
16595 gcc_assert (has_target_p
&& nops
== 3 && ops
[2].mode
== QImode
);
16596 sireg
= gen_reg_rtx (SImode
);
16597 emit_insn (gen_zero_extendqisi2 (sireg
,
16598 force_reg (QImode
, ops
[2].value
)));
16599 ops
[2].value
= sireg
;
16600 ops
[2].mode
= SImode
;
16603 case CODE_FOR_msa_addvi_b
:
16604 case CODE_FOR_msa_addvi_h
:
16605 case CODE_FOR_msa_addvi_w
:
16606 case CODE_FOR_msa_addvi_d
:
16607 case CODE_FOR_msa_clti_u_b
:
16608 case CODE_FOR_msa_clti_u_h
:
16609 case CODE_FOR_msa_clti_u_w
:
16610 case CODE_FOR_msa_clti_u_d
:
16611 case CODE_FOR_msa_clei_u_b
:
16612 case CODE_FOR_msa_clei_u_h
:
16613 case CODE_FOR_msa_clei_u_w
:
16614 case CODE_FOR_msa_clei_u_d
:
16615 case CODE_FOR_msa_maxi_u_b
:
16616 case CODE_FOR_msa_maxi_u_h
:
16617 case CODE_FOR_msa_maxi_u_w
:
16618 case CODE_FOR_msa_maxi_u_d
:
16619 case CODE_FOR_msa_mini_u_b
:
16620 case CODE_FOR_msa_mini_u_h
:
16621 case CODE_FOR_msa_mini_u_w
:
16622 case CODE_FOR_msa_mini_u_d
:
16623 case CODE_FOR_msa_subvi_b
:
16624 case CODE_FOR_msa_subvi_h
:
16625 case CODE_FOR_msa_subvi_w
:
16626 case CODE_FOR_msa_subvi_d
:
16627 gcc_assert (has_target_p
&& nops
== 3);
16628 /* We only generate a vector of constants iff the second argument
16629 is an immediate. We also validate the range of the immediate. */
16630 if (CONST_INT_P (ops
[2].value
))
16634 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16636 ops
[2].mode
= ops
[0].mode
;
16637 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16638 INTVAL (ops
[2].value
));
16645 case CODE_FOR_msa_ceqi_b
:
16646 case CODE_FOR_msa_ceqi_h
:
16647 case CODE_FOR_msa_ceqi_w
:
16648 case CODE_FOR_msa_ceqi_d
:
16649 case CODE_FOR_msa_clti_s_b
:
16650 case CODE_FOR_msa_clti_s_h
:
16651 case CODE_FOR_msa_clti_s_w
:
16652 case CODE_FOR_msa_clti_s_d
:
16653 case CODE_FOR_msa_clei_s_b
:
16654 case CODE_FOR_msa_clei_s_h
:
16655 case CODE_FOR_msa_clei_s_w
:
16656 case CODE_FOR_msa_clei_s_d
:
16657 case CODE_FOR_msa_maxi_s_b
:
16658 case CODE_FOR_msa_maxi_s_h
:
16659 case CODE_FOR_msa_maxi_s_w
:
16660 case CODE_FOR_msa_maxi_s_d
:
16661 case CODE_FOR_msa_mini_s_b
:
16662 case CODE_FOR_msa_mini_s_h
:
16663 case CODE_FOR_msa_mini_s_w
:
16664 case CODE_FOR_msa_mini_s_d
:
16665 gcc_assert (has_target_p
&& nops
== 3);
16666 /* We only generate a vector of constants iff the second argument
16667 is an immediate. We also validate the range of the immediate. */
16668 if (CONST_INT_P (ops
[2].value
))
16672 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16674 ops
[2].mode
= ops
[0].mode
;
16675 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16676 INTVAL (ops
[2].value
));
16683 case CODE_FOR_msa_andi_b
:
16684 case CODE_FOR_msa_ori_b
:
16685 case CODE_FOR_msa_nori_b
:
16686 case CODE_FOR_msa_xori_b
:
16687 gcc_assert (has_target_p
&& nops
== 3);
16688 if (!CONST_INT_P (ops
[2].value
))
16690 ops
[2].mode
= ops
[0].mode
;
16691 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16692 INTVAL (ops
[2].value
));
16695 case CODE_FOR_msa_bmzi_b
:
16696 case CODE_FOR_msa_bmnzi_b
:
16697 case CODE_FOR_msa_bseli_b
:
16698 gcc_assert (has_target_p
&& nops
== 4);
16699 if (!CONST_INT_P (ops
[3].value
))
16701 ops
[3].mode
= ops
[0].mode
;
16702 ops
[3].value
= mips_gen_const_int_vector (ops
[3].mode
,
16703 INTVAL (ops
[3].value
));
16706 case CODE_FOR_msa_fill_b
:
16707 case CODE_FOR_msa_fill_h
:
16708 case CODE_FOR_msa_fill_w
:
16709 case CODE_FOR_msa_fill_d
:
16710 /* Map the built-ins to vector fill operations. We need fix up the mode
16711 for the element being inserted. */
16712 gcc_assert (has_target_p
&& nops
== 2);
16713 imode
= GET_MODE_INNER (ops
[0].mode
);
16714 ops
[1].value
= lowpart_subreg (imode
, ops
[1].value
, ops
[1].mode
);
16715 ops
[1].mode
= imode
;
16718 case CODE_FOR_msa_ilvl_b
:
16719 case CODE_FOR_msa_ilvl_h
:
16720 case CODE_FOR_msa_ilvl_w
:
16721 case CODE_FOR_msa_ilvl_d
:
16722 case CODE_FOR_msa_ilvr_b
:
16723 case CODE_FOR_msa_ilvr_h
:
16724 case CODE_FOR_msa_ilvr_w
:
16725 case CODE_FOR_msa_ilvr_d
:
16726 case CODE_FOR_msa_ilvev_b
:
16727 case CODE_FOR_msa_ilvev_h
:
16728 case CODE_FOR_msa_ilvev_w
:
16729 case CODE_FOR_msa_ilvod_b
:
16730 case CODE_FOR_msa_ilvod_h
:
16731 case CODE_FOR_msa_ilvod_w
:
16732 case CODE_FOR_msa_pckev_b
:
16733 case CODE_FOR_msa_pckev_h
:
16734 case CODE_FOR_msa_pckev_w
:
16735 case CODE_FOR_msa_pckod_b
:
16736 case CODE_FOR_msa_pckod_h
:
16737 case CODE_FOR_msa_pckod_w
:
16738 /* Swap the operands 1 and 2 for interleave operations. Built-ins follow
16739 convention of ISA, which have op1 as higher component and op2 as lower
16740 component. However, the VEC_PERM op in tree and vec_concat in RTL
16741 expects first operand to be lower component, because of which this
16742 swap is needed for builtins. */
16743 gcc_assert (has_target_p
&& nops
== 3);
16744 std::swap (ops
[1], ops
[2]);
16747 case CODE_FOR_msa_slli_b
:
16748 case CODE_FOR_msa_slli_h
:
16749 case CODE_FOR_msa_slli_w
:
16750 case CODE_FOR_msa_slli_d
:
16751 case CODE_FOR_msa_srai_b
:
16752 case CODE_FOR_msa_srai_h
:
16753 case CODE_FOR_msa_srai_w
:
16754 case CODE_FOR_msa_srai_d
:
16755 case CODE_FOR_msa_srli_b
:
16756 case CODE_FOR_msa_srli_h
:
16757 case CODE_FOR_msa_srli_w
:
16758 case CODE_FOR_msa_srli_d
:
16759 gcc_assert (has_target_p
&& nops
== 3);
16760 if (CONST_INT_P (ops
[2].value
))
16763 rangehi
= GET_MODE_UNIT_BITSIZE (ops
[0].mode
) - 1;
16764 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16766 ops
[2].mode
= ops
[0].mode
;
16767 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16768 INTVAL (ops
[2].value
));
16775 case CODE_FOR_msa_insert_b
:
16776 case CODE_FOR_msa_insert_h
:
16777 case CODE_FOR_msa_insert_w
:
16778 case CODE_FOR_msa_insert_d
:
16779 /* Map the built-ins to insert operations. We need to swap operands,
16780 fix up the mode for the element being inserted, and generate
16781 a bit mask for vec_merge. */
16782 gcc_assert (has_target_p
&& nops
== 4);
16783 std::swap (ops
[1], ops
[2]);
16784 std::swap (ops
[1], ops
[3]);
16785 imode
= GET_MODE_INNER (ops
[0].mode
);
16786 ops
[1].value
= lowpart_subreg (imode
, ops
[1].value
, ops
[1].mode
);
16787 ops
[1].mode
= imode
;
16789 rangehi
= GET_MODE_NUNITS (ops
[0].mode
) - 1;
16790 if (CONST_INT_P (ops
[3].value
)
16791 && IN_RANGE (INTVAL (ops
[3].value
), rangelo
, rangehi
))
16792 ops
[3].value
= GEN_INT (1 << INTVAL (ops
[3].value
));
16797 case CODE_FOR_msa_insve_b
:
16798 case CODE_FOR_msa_insve_h
:
16799 case CODE_FOR_msa_insve_w
:
16800 case CODE_FOR_msa_insve_d
:
16801 /* Map the built-ins to element insert operations. We need to swap
16802 operands and generate a bit mask. */
16803 gcc_assert (has_target_p
&& nops
== 4);
16804 std::swap (ops
[1], ops
[2]);
16805 std::swap (ops
[1], ops
[3]);
16807 rangehi
= GET_MODE_NUNITS (ops
[0].mode
) - 1;
16808 if (CONST_INT_P (ops
[3].value
)
16809 && IN_RANGE (INTVAL (ops
[3].value
), rangelo
, rangehi
))
16810 ops
[3].value
= GEN_INT (1 << INTVAL (ops
[3].value
));
16815 case CODE_FOR_msa_shf_b
:
16816 case CODE_FOR_msa_shf_h
:
16817 case CODE_FOR_msa_shf_w
:
16818 case CODE_FOR_msa_shf_w_f
:
16819 gcc_assert (has_target_p
&& nops
== 3);
16820 ops
[2].value
= mips_gen_const_int_vector_shuffle (ops
[0].mode
,
16821 INTVAL (ops
[2].value
));
16824 case CODE_FOR_msa_vshf_b
:
16825 case CODE_FOR_msa_vshf_h
:
16826 case CODE_FOR_msa_vshf_w
:
16827 case CODE_FOR_msa_vshf_d
:
16828 gcc_assert (has_target_p
&& nops
== 4);
16829 std::swap (ops
[1], ops
[3]);
16836 if (error_opno
!= 0)
16838 error ("argument %d to the built-in must be a constant"
16839 " in range %d to %d", error_opno
, rangelo
, rangehi
);
16840 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
16842 else if (!maybe_expand_insn (icode
, nops
, ops
))
16844 error ("invalid argument to built-in function");
16845 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
16847 return has_target_p
? ops
[0].value
: const0_rtx
;
16850 /* Expand a floating-point comparison for built-in function call EXP.
16851 The first NARGS arguments are the values to be compared. ICODE is
16852 the .md pattern that does the comparison and COND is the condition
16853 that is being tested. Return an rtx for the result. */
16856 mips_expand_builtin_compare_1 (enum insn_code icode
,
16857 enum mips_fp_condition cond
,
16858 tree exp
, int nargs
)
16860 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
16864 /* The instruction should have a target operand, an operand for each
16865 argument, and an operand for COND. */
16866 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
16868 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
16870 create_fixed_operand (&ops
[opno
++], output
);
16871 for (argno
= 0; argno
< nargs
; argno
++)
16872 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
16873 create_integer_operand (&ops
[opno
++], (int) cond
);
16874 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
16877 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
16878 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
16879 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
16880 suggests a good place to put the result. */
16883 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
16886 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
16889 /* Map any target to operand 0. */
16892 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
16894 /* Map the arguments to the other operands. */
16895 gcc_assert (opno
+ call_expr_nargs (exp
)
16896 == insn_data
[icode
].n_generator_args
);
16897 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
16898 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
16900 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
16903 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
16904 function; TYPE says which. EXP is the CALL_EXPR that calls the
16905 function, ICODE is the instruction that should be used to compare
16906 the first two arguments, and COND is the condition it should test.
16907 TARGET, if nonnull, suggests a good place to put the result. */
16910 mips_expand_builtin_movtf (enum mips_builtin_type type
,
16911 enum insn_code icode
, enum mips_fp_condition cond
,
16912 rtx target
, tree exp
)
16914 struct expand_operand ops
[4];
16917 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
16918 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
16919 if (type
== MIPS_BUILTIN_MOVT
)
16921 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
16922 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
16926 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
16927 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
16929 create_fixed_operand (&ops
[3], cmp_result
);
16930 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
16934 /* Expand an MSA built-in for a compare and branch instruction specified by
16935 ICODE, set a general-purpose register to 1 if the branch was taken,
16939 mips_expand_builtin_msa_test_branch (enum insn_code icode
, tree exp
)
16941 struct expand_operand ops
[3];
16943 rtx_code_label
*true_label
, *done_label
;
16946 true_label
= gen_label_rtx ();
16947 done_label
= gen_label_rtx ();
16949 create_input_operand (&ops
[0], true_label
, TYPE_MODE (TREE_TYPE (exp
)));
16950 mips_prepare_builtin_arg (&ops
[1], exp
, 0);
16951 create_fixed_operand (&ops
[2], const0_rtx
);
16953 /* Make sure that the operand 1 is a REG. */
16954 if (GET_CODE (ops
[1].value
) != REG
)
16955 ops
[1].value
= force_reg (ops
[1].mode
, ops
[1].value
);
16957 if ((cbranch
= maybe_gen_insn (icode
, 3, ops
)) == NULL_RTX
)
16958 error ("failed to expand built-in function");
16960 cmp_result
= gen_reg_rtx (SImode
);
16962 /* First assume that CMP_RESULT is false. */
16963 mips_emit_move (cmp_result
, const0_rtx
);
16965 /* Branch to TRUE_LABEL if CBRANCH is taken and DONE_LABEL otherwise. */
16966 emit_jump_insn (cbranch
);
16967 emit_jump_insn (gen_jump (done_label
));
16970 /* Set CMP_RESULT to true if the branch was taken. */
16971 emit_label (true_label
);
16972 mips_emit_move (cmp_result
, const1_rtx
);
16974 emit_label (done_label
);
16978 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
16979 into TARGET otherwise. Return TARGET. */
16982 mips_builtin_branch_and_move (rtx condition
, rtx target
,
16983 rtx value_if_true
, rtx value_if_false
)
16985 rtx_code_label
*true_label
, *done_label
;
16987 true_label
= gen_label_rtx ();
16988 done_label
= gen_label_rtx ();
16990 /* First assume that CONDITION is false. */
16991 mips_emit_move (target
, value_if_false
);
16993 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
16994 emit_jump_insn (gen_condjump (condition
, true_label
));
16995 emit_jump_insn (gen_jump (done_label
));
16998 /* Fix TARGET if CONDITION is true. */
16999 emit_label (true_label
);
17000 mips_emit_move (target
, value_if_true
);
17002 emit_label (done_label
);
17006 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
17007 the CALL_EXPR that calls the function, ICODE is the code of the
17008 comparison instruction, and COND is the condition it should test.
17009 TARGET, if nonnull, suggests a good place to put the boolean result. */
17012 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
17013 enum insn_code icode
, enum mips_fp_condition cond
,
17014 rtx target
, tree exp
)
17016 rtx offset
, condition
, cmp_result
;
17018 if (target
== 0 || GET_MODE (target
) != SImode
)
17019 target
= gen_reg_rtx (SImode
);
17020 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
17021 call_expr_nargs (exp
));
17023 /* If the comparison sets more than one register, we define the result
17024 to be 0 if all registers are false and -1 if all registers are true.
17025 The value of the complete result is indeterminate otherwise. */
17026 switch (builtin_type
)
17028 case MIPS_BUILTIN_CMP_ALL
:
17029 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
17030 return mips_builtin_branch_and_move (condition
, target
,
17031 const0_rtx
, const1_rtx
);
17033 case MIPS_BUILTIN_CMP_UPPER
:
17034 case MIPS_BUILTIN_CMP_LOWER
:
17035 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
17036 condition
= gen_single_cc (cmp_result
, offset
);
17037 return mips_builtin_branch_and_move (condition
, target
,
17038 const1_rtx
, const0_rtx
);
17041 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
17042 return mips_builtin_branch_and_move (condition
, target
,
17043 const1_rtx
, const0_rtx
);
17047 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
17048 if nonnull, suggests a good place to put the boolean result. */
17051 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
17053 rtx condition
, cmp_result
;
17056 if (target
== 0 || GET_MODE (target
) != SImode
)
17057 target
= gen_reg_rtx (SImode
);
17059 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
17061 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
17066 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
17067 return mips_builtin_branch_and_move (condition
, target
,
17068 const1_rtx
, const0_rtx
);
17071 /* Implement TARGET_EXPAND_BUILTIN. */
17074 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
17075 machine_mode mode
, int ignore
)
17078 unsigned int fcode
, avail
;
17079 const struct mips_builtin_description
*d
;
17081 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
17082 fcode
= DECL_FUNCTION_CODE (fndecl
);
17083 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
17084 d
= &mips_builtins
[fcode
];
17085 avail
= d
->avail ();
17086 gcc_assert (avail
!= 0);
17087 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
17089 error ("built-in function %qE not supported for MIPS16",
17090 DECL_NAME (fndecl
));
17091 return ignore
? const0_rtx
: CONST0_RTX (mode
);
17093 switch (d
->builtin_type
)
17095 case MIPS_BUILTIN_DIRECT
:
17096 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
17098 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
17099 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
17101 case MIPS_BUILTIN_MOVT
:
17102 case MIPS_BUILTIN_MOVF
:
17103 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
17104 d
->cond
, target
, exp
);
17106 case MIPS_BUILTIN_CMP_ANY
:
17107 case MIPS_BUILTIN_CMP_ALL
:
17108 case MIPS_BUILTIN_CMP_UPPER
:
17109 case MIPS_BUILTIN_CMP_LOWER
:
17110 case MIPS_BUILTIN_CMP_SINGLE
:
17111 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
17112 d
->cond
, target
, exp
);
17114 case MIPS_BUILTIN_MSA_TEST_BRANCH
:
17115 return mips_expand_builtin_msa_test_branch (d
->icode
, exp
);
17117 case MIPS_BUILTIN_BPOSGE32
:
17118 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
17120 gcc_unreachable ();
17123 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
17124 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
17125 struct mips16_constant
{
17126 struct mips16_constant
*next
;
17128 rtx_code_label
*label
;
17132 /* Information about an incomplete MIPS16 constant pool. FIRST is the
17133 first constant, HIGHEST_ADDRESS is the highest address that the first
17134 byte of the pool can have, and INSN_ADDRESS is the current instruction
17136 struct mips16_constant_pool
{
17137 struct mips16_constant
*first
;
17138 int highest_address
;
17142 /* Add constant VALUE to POOL and return its label. MODE is the
17143 value's mode (used for CONST_INTs, etc.). */
17145 static rtx_code_label
*
17146 mips16_add_constant (struct mips16_constant_pool
*pool
,
17147 rtx value
, machine_mode mode
)
17149 struct mips16_constant
**p
, *c
;
17150 bool first_of_size_p
;
17152 /* See whether the constant is already in the pool. If so, return the
17153 existing label, otherwise leave P pointing to the place where the
17154 constant should be added.
17156 Keep the pool sorted in increasing order of mode size so that we can
17157 reduce the number of alignments needed. */
17158 first_of_size_p
= true;
17159 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
17161 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
17162 return (*p
)->label
;
17163 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
17165 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
17166 first_of_size_p
= false;
17169 /* In the worst case, the constant needed by the earliest instruction
17170 will end up at the end of the pool. The entire pool must then be
17171 accessible from that instruction.
17173 When adding the first constant, set the pool's highest address to
17174 the address of the first out-of-range byte. Adjust this address
17175 downwards each time a new constant is added. */
17176 if (pool
->first
== 0)
17177 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
17178 of the instruction with the lowest two bits clear. The base PC
17179 value for LDPC has the lowest three bits clear. Assume the worst
17180 case here; namely that the PC-relative instruction occupies the
17181 last 2 bytes in an aligned word. */
17182 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
17183 pool
->highest_address
-= GET_MODE_SIZE (mode
);
17184 if (first_of_size_p
)
17185 /* Take into account the worst possible padding due to alignment. */
17186 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
17188 /* Create a new entry. */
17189 c
= XNEW (struct mips16_constant
);
17192 c
->label
= gen_label_rtx ();
17199 /* Output constant VALUE after instruction INSN and return the last
17200 instruction emitted. MODE is the mode of the constant. */
17203 mips16_emit_constants_1 (machine_mode mode
, rtx value
, rtx_insn
*insn
)
17205 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
17207 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
17208 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
17211 if (SCALAR_FLOAT_MODE_P (mode
))
17212 return emit_insn_after (gen_consttable_float (value
), insn
);
17214 if (VECTOR_MODE_P (mode
))
17218 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
17219 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
17220 CONST_VECTOR_ELT (value
, i
), insn
);
17224 gcc_unreachable ();
17227 /* Dump out the constants in CONSTANTS after INSN. Record the initial
17228 label number in the `consttable' and `consttable_end' insns emitted
17229 at the beginning and the end of the constant pool respectively, so
17230 that individual pools can be uniquely marked as data for the purpose
17234 mips16_emit_constants (struct mips16_constant
*constants
, rtx_insn
*insn
)
17236 int label_num
= constants
? CODE_LABEL_NUMBER (constants
->label
) : 0;
17237 struct mips16_constant
*c
, *next
;
17242 insn
= emit_insn_after (gen_consttable (GEN_INT (label_num
)), insn
);
17243 for (c
= constants
; c
!= NULL
; c
= next
)
17245 /* If necessary, increase the alignment of PC. */
17246 if (align
< GET_MODE_SIZE (c
->mode
))
17248 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
17249 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
17251 align
= GET_MODE_SIZE (c
->mode
);
17253 insn
= emit_label_after (c
->label
, insn
);
17254 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
17260 insn
= emit_insn_after (gen_consttable_end (GEN_INT (label_num
)), insn
);
17262 emit_barrier_after (insn
);
17265 /* Return the length of instruction INSN. */
17268 mips16_insn_length (rtx_insn
*insn
)
17270 if (JUMP_TABLE_DATA_P (insn
))
17272 rtx body
= PATTERN (insn
);
17273 if (GET_CODE (body
) == ADDR_VEC
)
17274 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
17275 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
17276 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
17278 gcc_unreachable ();
17280 return get_attr_length (insn
);
17283 /* If *X is a symbolic constant that refers to the constant pool, add
17284 the constant to POOL and rewrite *X to use the constant's label. */
17287 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
17290 rtx_code_label
*label
;
17292 split_const (*x
, &base
, &offset
);
17293 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
17295 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
17296 get_pool_mode (base
));
17297 base
= gen_rtx_LABEL_REF (Pmode
, label
);
17298 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
17302 /* Rewrite INSN so that constant pool references refer to the constant's
17306 mips16_rewrite_pool_refs (rtx_insn
*insn
, struct mips16_constant_pool
*pool
)
17308 subrtx_ptr_iterator::array_type array
;
17309 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), ALL
)
17313 if (force_to_mem_operand (*loc
, Pmode
))
17315 rtx mem
= force_const_mem (GET_MODE (*loc
), *loc
);
17316 validate_change (insn
, loc
, mem
, false);
17321 mips16_rewrite_pool_constant (pool
, &XEXP (*loc
, 0));
17322 iter
.skip_subrtxes ();
17326 if (TARGET_MIPS16_TEXT_LOADS
)
17327 mips16_rewrite_pool_constant (pool
, loc
);
17328 if (GET_CODE (*loc
) == CONST
17329 /* Don't rewrite the __mips16_rdwr symbol. */
17330 || (GET_CODE (*loc
) == UNSPEC
17331 && XINT (*loc
, 1) == UNSPEC_TLS_GET_TP
))
17332 iter
.skip_subrtxes ();
17337 /* Return whether CFG is used in mips_reorg. */
17340 mips_cfg_in_reorg (void)
17342 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17343 || TARGET_RELAX_PIC_CALLS
);
17346 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
17347 otherwise assume that they are already split. */
17350 mips16_lay_out_constants (bool split_p
)
17352 struct mips16_constant_pool pool
;
17353 rtx_insn
*insn
, *barrier
;
17355 if (!TARGET_MIPS16_PCREL_LOADS
)
17360 if (mips_cfg_in_reorg ())
17361 split_all_insns ();
17363 split_all_insns_noflow ();
17366 memset (&pool
, 0, sizeof (pool
));
17367 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17369 /* Rewrite constant pool references in INSN. */
17370 if (USEFUL_INSN_P (insn
))
17371 mips16_rewrite_pool_refs (insn
, &pool
);
17373 pool
.insn_address
+= mips16_insn_length (insn
);
17375 if (pool
.first
!= NULL
)
17377 /* If there are no natural barriers between the first user of
17378 the pool and the highest acceptable address, we'll need to
17379 create a new instruction to jump around the constant pool.
17380 In the worst case, this instruction will be 4 bytes long.
17382 If it's too late to do this transformation after INSN,
17383 do it immediately before INSN. */
17384 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
17386 rtx_code_label
*label
;
17389 label
= gen_label_rtx ();
17391 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
17392 JUMP_LABEL (jump
) = label
;
17393 LABEL_NUSES (label
) = 1;
17394 barrier
= emit_barrier_after (jump
);
17396 emit_label_after (label
, barrier
);
17397 pool
.insn_address
+= 4;
17400 /* See whether the constant pool is now out of range of the first
17401 user. If so, output the constants after the previous barrier.
17402 Note that any instructions between BARRIER and INSN (inclusive)
17403 will use negative offsets to refer to the pool. */
17404 if (pool
.insn_address
> pool
.highest_address
)
17406 mips16_emit_constants (pool
.first
, barrier
);
17410 else if (BARRIER_P (insn
))
17414 mips16_emit_constants (pool
.first
, get_last_insn ());
17417 /* Return true if it is worth r10k_simplify_address's while replacing
17418 an address with X. We are looking for constants, and for addresses
17419 at a known offset from the incoming stack pointer. */
17422 r10k_simplified_address_p (rtx x
)
17424 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
17426 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
17429 /* X is an expression that appears in INSN. Try to use the UD chains
17430 to simplify it, returning the simplified form on success and the
17431 original form otherwise. Replace the incoming value of $sp with
17432 virtual_incoming_args_rtx (which should never occur in X otherwise). */
17435 r10k_simplify_address (rtx x
, rtx_insn
*insn
)
17437 rtx newx
, op0
, op1
, set
, note
;
17438 rtx_insn
*def_insn
;
17440 struct df_link
*defs
;
17445 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17446 if (op0
!= XEXP (x
, 0))
17447 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
17448 op0
, GET_MODE (XEXP (x
, 0)));
17450 else if (BINARY_P (x
))
17452 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17453 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
17454 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
17455 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
17457 else if (GET_CODE (x
) == LO_SUM
)
17459 /* LO_SUMs can be offset from HIGHs, if we know they won't
17460 overflow. See mips_classify_address for the rationale behind
17462 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17463 if (GET_CODE (op0
) == HIGH
)
17464 newx
= XEXP (x
, 1);
17466 else if (REG_P (x
))
17468 /* Uses are recorded by regno_reg_rtx, not X itself. */
17469 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
17471 defs
= DF_REF_CHAIN (use
);
17473 /* Require a single definition. */
17474 if (defs
&& defs
->next
== NULL
)
17477 if (DF_REF_IS_ARTIFICIAL (def
))
17479 /* Replace the incoming value of $sp with
17480 virtual_incoming_args_rtx. */
17481 if (x
== stack_pointer_rtx
17482 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
17483 newx
= virtual_incoming_args_rtx
;
17485 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
17488 /* Make sure that DEF_INSN is a single set of REG. */
17489 def_insn
= DF_REF_INSN (def
);
17490 if (NONJUMP_INSN_P (def_insn
))
17492 set
= single_set (def_insn
);
17493 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
17495 /* Prefer to use notes, since the def-use chains
17496 are often shorter. */
17497 note
= find_reg_equal_equiv_note (def_insn
);
17499 newx
= XEXP (note
, 0);
17501 newx
= SET_SRC (set
);
17502 newx
= r10k_simplify_address (newx
, def_insn
);
17508 if (newx
&& r10k_simplified_address_p (newx
))
17513 /* Return true if ADDRESS is known to be an uncached address
17514 on R10K systems. */
17517 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
17519 unsigned HOST_WIDE_INT upper
;
17521 /* Check for KSEG1. */
17522 if (address
+ 0x60000000 < 0x20000000)
17525 /* Check for uncached XKPHYS addresses. */
17526 if (Pmode
== DImode
)
17528 upper
= (address
>> 40) & 0xf9ffff;
17529 if (upper
== 0x900000 || upper
== 0xb80000)
17535 /* Return true if we can prove that an access to address X in instruction
17536 INSN would be safe from R10K speculation. This X is a general
17537 expression; it might not be a legitimate address. */
17540 r10k_safe_address_p (rtx x
, rtx_insn
*insn
)
17543 HOST_WIDE_INT offset_val
;
17545 x
= r10k_simplify_address (x
, insn
);
17547 /* Check for references to the stack frame. It doesn't really matter
17548 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
17549 allows us to assume that accesses to any part of the eventual frame
17550 is safe from speculation at any point in the function. */
17551 mips_split_plus (x
, &base
, &offset_val
);
17552 if (base
== virtual_incoming_args_rtx
17553 && offset_val
>= -cfun
->machine
->frame
.total_size
17554 && offset_val
< cfun
->machine
->frame
.args_size
)
17557 /* Check for uncached addresses. */
17558 if (CONST_INT_P (x
))
17559 return r10k_uncached_address_p (INTVAL (x
));
17561 /* Check for accesses to a static object. */
17562 split_const (x
, &base
, &offset
);
17563 return offset_within_block_p (base
, INTVAL (offset
));
17566 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
17567 an in-range access to an automatic variable, or to an object with
17568 a link-time-constant address. */
17571 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
17573 HOST_WIDE_INT bitoffset
, bitsize
;
17574 tree inner
, var_offset
;
17576 int unsigned_p
, reverse_p
, volatile_p
;
17578 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
17579 &unsigned_p
, &reverse_p
, &volatile_p
);
17580 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
17583 offset
+= bitoffset
/ BITS_PER_UNIT
;
17584 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
17587 /* Return true if X contains a MEM that is not safe from R10K speculation.
17588 INSN is the instruction that contains X. */
17591 r10k_needs_protection_p_1 (rtx x
, rtx_insn
*insn
)
17593 subrtx_var_iterator::array_type array
;
17594 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
17599 if ((MEM_EXPR (mem
)
17600 && MEM_OFFSET_KNOWN_P (mem
)
17601 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
17602 || r10k_safe_address_p (XEXP (mem
, 0), insn
))
17603 iter
.skip_subrtxes ();
17611 /* A note_stores callback for which DATA points to an instruction pointer.
17612 If *DATA is nonnull, make it null if it X contains a MEM that is not
17613 safe from R10K speculation. */
17616 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
17619 rtx_insn
**insn_ptr
;
17621 insn_ptr
= (rtx_insn
**) data
;
17622 if (*insn_ptr
&& r10k_needs_protection_p_1 (x
, *insn_ptr
))
17626 /* X is the pattern of a call instruction. Return true if the call is
17627 not to a declared function. */
17630 r10k_needs_protection_p_call (const_rtx x
)
17632 subrtx_iterator::array_type array
;
17633 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
17635 const_rtx mem
= *iter
;
17638 const_rtx addr
= XEXP (mem
, 0);
17639 if (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_DECL (addr
))
17640 iter
.skip_subrtxes ();
17648 /* Return true if instruction INSN needs to be protected by an R10K
17652 r10k_needs_protection_p (rtx_insn
*insn
)
17655 return r10k_needs_protection_p_call (PATTERN (insn
));
17657 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
17659 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
17660 return insn
== NULL_RTX
;
17663 return r10k_needs_protection_p_1 (PATTERN (insn
), insn
);
17666 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
17667 edge is unconditional. */
17670 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
17675 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
17676 if (!single_succ_p (e
->src
)
17677 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
17678 || (e
->flags
& EDGE_COMPLEX
) != 0)
17683 /* Implement -mr10k-cache-barrier= for the current function. */
17686 r10k_insert_cache_barriers (void)
17688 int *rev_post_order
;
17691 sbitmap protected_bbs
;
17692 rtx_insn
*insn
, *end
;
17693 rtx unprotected_region
;
17697 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
17701 /* Calculate dominators. */
17702 calculate_dominance_info (CDI_DOMINATORS
);
17704 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
17705 X is protected by a cache barrier. */
17706 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
17707 bitmap_clear (protected_bbs
);
17709 /* Iterate over the basic blocks in reverse post-order. */
17710 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
17711 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
17712 for (i
= 0; i
< n
; i
++)
17714 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
17716 /* If this block is only reached by unconditional edges, and if the
17717 source of every edge is protected, the beginning of the block is
17719 if (r10k_protected_bb_p (bb
, protected_bbs
))
17720 unprotected_region
= NULL_RTX
;
17722 unprotected_region
= pc_rtx
;
17723 end
= NEXT_INSN (BB_END (bb
));
17725 /* UNPROTECTED_REGION is:
17727 - null if we are processing a protected region,
17728 - pc_rtx if we are processing an unprotected region but have
17729 not yet found the first instruction in it
17730 - the first instruction in an unprotected region otherwise. */
17731 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
17733 if (unprotected_region
&& USEFUL_INSN_P (insn
))
17735 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
17736 /* This CACHE instruction protects the following code. */
17737 unprotected_region
= NULL_RTX
;
17740 /* See if INSN is the first instruction in this
17741 unprotected region. */
17742 if (unprotected_region
== pc_rtx
)
17743 unprotected_region
= insn
;
17745 /* See if INSN needs to be protected. If so,
17746 we must insert a cache barrier somewhere between
17747 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
17748 clear which position is better performance-wise,
17749 but as a tie-breaker, we assume that it is better
17750 to allow delay slots to be back-filled where
17751 possible, and that it is better not to insert
17752 barriers in the middle of already-scheduled code.
17753 We therefore insert the barrier at the beginning
17755 if (r10k_needs_protection_p (insn
))
17757 emit_insn_before (gen_r10k_cache_barrier (),
17758 unprotected_region
);
17759 unprotected_region
= NULL_RTX
;
17765 /* The called function is not required to protect the exit path.
17766 The code that follows a call is therefore unprotected. */
17767 unprotected_region
= pc_rtx
;
17770 /* Record whether the end of this block is protected. */
17771 if (unprotected_region
== NULL_RTX
)
17772 bitmap_set_bit (protected_bbs
, bb
->index
);
17774 XDELETEVEC (rev_post_order
);
17776 sbitmap_free (protected_bbs
);
17778 free_dominance_info (CDI_DOMINATORS
);
17781 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
17782 otherwise. If INSN has two call rtx, then store the second one in
17786 mips_call_expr_from_insn (rtx_insn
*insn
, rtx
*second_call
)
17791 if (!CALL_P (insn
))
17794 x
= PATTERN (insn
);
17795 if (GET_CODE (x
) == PARALLEL
)
17797 /* Calls returning complex values have two CALL rtx. Look for the second
17798 one here, and return it via the SECOND_CALL arg. */
17799 x2
= XVECEXP (x
, 0, 1);
17800 if (GET_CODE (x2
) == SET
)
17802 if (GET_CODE (x2
) == CALL
)
17805 x
= XVECEXP (x
, 0, 0);
17807 if (GET_CODE (x
) == SET
)
17809 gcc_assert (GET_CODE (x
) == CALL
);
17814 /* REG is set in DEF. See if the definition is one of the ways we load a
17815 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
17816 If it is, return the symbol reference of the function, otherwise return
17819 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
17820 the values of source registers, otherwise treat such registers as
17821 having an unknown value. */
17824 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
17826 rtx_insn
*def_insn
;
17829 if (DF_REF_IS_ARTIFICIAL (def
))
17832 def_insn
= DF_REF_INSN (def
);
17833 set
= single_set (def_insn
);
17834 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
17836 rtx note
, src
, symbol
;
17838 /* First see whether the source is a plain symbol. This is used
17839 when calling symbols that are not lazily bound. */
17840 src
= SET_SRC (set
);
17841 if (GET_CODE (src
) == SYMBOL_REF
)
17844 /* Handle %call16 references. */
17845 symbol
= mips_strip_unspec_call (src
);
17848 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
17852 /* If we have something more complicated, look for a
17853 REG_EQUAL or REG_EQUIV note. */
17854 note
= find_reg_equal_equiv_note (def_insn
);
17855 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
17856 return XEXP (note
, 0);
17858 /* Follow at most one simple register copy. Such copies are
17859 interesting in cases like:
17863 locally_binding_fn (...);
17868 locally_binding_fn (...);
17870 locally_binding_fn (...);
17872 where the load of locally_binding_fn can legitimately be
17873 hoisted or shared. However, we do not expect to see complex
17874 chains of copies, so a full worklist solution to the problem
17875 would probably be overkill. */
17876 if (recurse_p
&& REG_P (src
))
17877 return mips_find_pic_call_symbol (def_insn
, src
, false);
17883 /* Find the definition of the use of REG in INSN. See if the definition
17884 is one of the ways we load a register with a symbol address for a
17885 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
17886 of the function, otherwise return NULL_RTX. RECURSE_P is as for
17887 mips_pic_call_symbol_from_set. */
17890 mips_find_pic_call_symbol (rtx_insn
*insn
, rtx reg
, bool recurse_p
)
17893 struct df_link
*defs
;
17896 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
17899 defs
= DF_REF_CHAIN (use
);
17902 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
17906 /* If we have more than one definition, they need to be identical. */
17907 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
17911 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
17912 if (!rtx_equal_p (symbol
, other
))
17919 /* Replace the args_size operand of the call expression CALL with the
17920 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
17923 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
17927 args_size
= XEXP (call
, 1);
17928 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
17929 gen_rtvec (2, args_size
, symbol
),
17933 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
17934 if instead of the arg_size argument it contains the call attributes. If
17935 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
17936 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
17940 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
17942 rtx args_size
, symbol
;
17944 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
17947 args_size
= operands
[args_size_opno
];
17948 if (GET_CODE (args_size
) != UNSPEC
)
17950 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
17952 symbol
= XVECEXP (args_size
, 0, 1);
17953 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
17955 operands
[args_size_opno
] = symbol
;
17959 /* Use DF to annotate PIC indirect calls with the function symbol they
17963 mips_annotate_pic_calls (void)
17968 FOR_EACH_BB_FN (bb
, cfun
)
17969 FOR_BB_INSNS (bb
, insn
)
17971 rtx call
, reg
, symbol
, second_call
;
17974 call
= mips_call_expr_from_insn (insn
, &second_call
);
17977 gcc_assert (MEM_P (XEXP (call
, 0)));
17978 reg
= XEXP (XEXP (call
, 0), 0);
17982 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
17985 mips_annotate_pic_call_expr (call
, symbol
);
17987 mips_annotate_pic_call_expr (second_call
, symbol
);
17992 /* A temporary variable used by note_uses callbacks, etc. */
17993 static rtx_insn
*mips_sim_insn
;
17995 /* A structure representing the state of the processor pipeline.
17996 Used by the mips_sim_* family of functions. */
17998 /* The maximum number of instructions that can be issued in a cycle.
17999 (Caches mips_issue_rate.) */
18000 unsigned int issue_rate
;
18002 /* The current simulation time. */
18005 /* How many more instructions can be issued in the current cycle. */
18006 unsigned int insns_left
;
18008 /* LAST_SET[X].INSN is the last instruction to set register X.
18009 LAST_SET[X].TIME is the time at which that instruction was issued.
18010 INSN is null if no instruction has yet set register X. */
18014 } last_set
[FIRST_PSEUDO_REGISTER
];
18016 /* The pipeline's current DFA state. */
18020 /* Reset STATE to the initial simulation state. */
18023 mips_sim_reset (struct mips_sim
*state
)
18025 curr_state
= state
->dfa_state
;
18028 state
->insns_left
= state
->issue_rate
;
18029 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
18030 state_reset (curr_state
);
18032 targetm
.sched
.init (0, false, 0);
18033 advance_state (curr_state
);
18036 /* Initialize STATE before its first use. DFA_STATE points to an
18037 allocated but uninitialized DFA state. */
18040 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
18042 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
18043 targetm
.sched
.init_dfa_pre_cycle_insn ();
18045 if (targetm
.sched
.init_dfa_post_cycle_insn
)
18046 targetm
.sched
.init_dfa_post_cycle_insn ();
18048 state
->issue_rate
= mips_issue_rate ();
18049 state
->dfa_state
= dfa_state
;
18050 mips_sim_reset (state
);
18053 /* Advance STATE by one clock cycle. */
18056 mips_sim_next_cycle (struct mips_sim
*state
)
18058 curr_state
= state
->dfa_state
;
18061 state
->insns_left
= state
->issue_rate
;
18062 advance_state (curr_state
);
18065 /* Advance simulation state STATE until instruction INSN can read
18069 mips_sim_wait_reg (struct mips_sim
*state
, rtx_insn
*insn
, rtx reg
)
18071 unsigned int regno
, end_regno
;
18073 end_regno
= END_REGNO (reg
);
18074 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
18075 if (state
->last_set
[regno
].insn
!= 0)
18079 t
= (state
->last_set
[regno
].time
18080 + insn_latency (state
->last_set
[regno
].insn
, insn
));
18081 while (state
->time
< t
)
18082 mips_sim_next_cycle (state
);
18086 /* A note_uses callback. For each register in *X, advance simulation
18087 state DATA until mips_sim_insn can read the register's value. */
18090 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
18092 subrtx_var_iterator::array_type array
;
18093 FOR_EACH_SUBRTX_VAR (iter
, array
, *x
, NONCONST
)
18095 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *iter
);
18098 /* Advance simulation state STATE until all of INSN's register
18099 dependencies are satisfied. */
18102 mips_sim_wait_regs (struct mips_sim
*state
, rtx_insn
*insn
)
18104 mips_sim_insn
= insn
;
18105 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
18108 /* Advance simulation state STATE until the units required by
18109 instruction INSN are available. */
18112 mips_sim_wait_units (struct mips_sim
*state
, rtx_insn
*insn
)
18116 tmp_state
= alloca (state_size ());
18117 while (state
->insns_left
== 0
18118 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
18119 state_transition (tmp_state
, insn
) >= 0))
18120 mips_sim_next_cycle (state
);
18123 /* Advance simulation state STATE until INSN is ready to issue. */
18126 mips_sim_wait_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18128 mips_sim_wait_regs (state
, insn
);
18129 mips_sim_wait_units (state
, insn
);
18132 /* mips_sim_insn has just set X. Update the LAST_SET array
18133 in simulation state DATA. */
18136 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
18138 struct mips_sim
*state
;
18140 state
= (struct mips_sim
*) data
;
18143 unsigned int regno
, end_regno
;
18145 end_regno
= END_REGNO (x
);
18146 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
18148 state
->last_set
[regno
].insn
= mips_sim_insn
;
18149 state
->last_set
[regno
].time
= state
->time
;
18154 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
18155 can issue immediately (i.e., that mips_sim_wait_insn has already
18159 mips_sim_issue_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18161 curr_state
= state
->dfa_state
;
18163 state_transition (curr_state
, insn
);
18164 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
18165 state
->insns_left
);
18167 mips_sim_insn
= insn
;
18168 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
18171 /* Simulate issuing a NOP in state STATE. */
18174 mips_sim_issue_nop (struct mips_sim
*state
)
18176 if (state
->insns_left
== 0)
18177 mips_sim_next_cycle (state
);
18178 state
->insns_left
--;
18181 /* Update simulation state STATE so that it's ready to accept the instruction
18182 after INSN. INSN should be part of the main rtl chain, not a member of a
18186 mips_sim_finish_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18188 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
18190 mips_sim_issue_nop (state
);
18192 switch (GET_CODE (SEQ_BEGIN (insn
)))
18196 /* We can't predict the processor state after a call or label. */
18197 mips_sim_reset (state
);
18201 /* The delay slots of branch likely instructions are only executed
18202 when the branch is taken. Therefore, if the caller has simulated
18203 the delay slot instruction, STATE does not really reflect the state
18204 of the pipeline for the instruction after the delay slot. Also,
18205 branch likely instructions tend to incur a penalty when not taken,
18206 so there will probably be an extra delay between the branch and
18207 the instruction after the delay slot. */
18208 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
18209 mips_sim_reset (state
);
18217 /* Use simulator state STATE to calculate the execution time of
18218 instruction sequence SEQ. */
18220 static unsigned int
18221 mips_seq_time (struct mips_sim
*state
, rtx_insn
*seq
)
18223 mips_sim_reset (state
);
18224 for (rtx_insn
*insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
18226 mips_sim_wait_insn (state
, insn
);
18227 mips_sim_issue_insn (state
, insn
);
18229 return state
->time
;
18232 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
18233 setting SETTING, using STATE to simulate instruction sequences. */
18235 static unsigned int
18236 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
18238 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
18241 machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
18242 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
18243 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
18245 /* If the target provides mulsidi3_32bit then that's the most likely
18246 consumer of the result. Test for bypasses. */
18247 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
18249 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
18250 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
18253 unsigned int time
= mips_seq_time (state
, get_insns ());
18258 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
18259 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
18260 Prefer MULT -- which is shorter -- in the event of a tie. */
18263 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
18265 if (TARGET_MIPS16
|| !ISA_HAS_HILO
)
18266 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
18267 registers then there is no reason to zero them, arbitrarily choose to
18268 say that "MULT $0,$0" would be faster. */
18269 mips_tuning_info
.fast_mult_zero_zero_p
= true;
18272 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
18273 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
18274 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
18278 /* Set up costs based on the current architecture and tuning settings. */
18281 mips_set_tuning_info (void)
18283 if (mips_tuning_info
.initialized_p
18284 && mips_tuning_info
.arch
== mips_arch
18285 && mips_tuning_info
.tune
== mips_tune
18286 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
18289 mips_tuning_info
.arch
= mips_arch
;
18290 mips_tuning_info
.tune
= mips_tune
;
18291 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
18292 mips_tuning_info
.initialized_p
= true;
18296 struct mips_sim state
;
18297 mips_sim_init (&state
, alloca (state_size ()));
18299 mips_set_fast_mult_zero_zero_p (&state
);
18304 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
18307 mips_expand_to_rtl_hook (void)
18309 /* We need to call this at a point where we can safely create sequences
18310 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
18311 need to call it at a point where the DFA infrastructure is not
18312 already in use, so we can't just call it lazily on demand.
18314 At present, mips_tuning_info is only needed during post-expand
18315 RTL passes such as split_insns, so this hook should be early enough.
18316 We may need to move the call elsewhere if mips_tuning_info starts
18317 to be used for other things (such as rtx_costs, or expanders that
18318 could be called during gimple optimization). */
18319 mips_set_tuning_info ();
18322 /* The VR4130 pipeline issues aligned pairs of instructions together,
18323 but it stalls the second instruction if it depends on the first.
18324 In order to cut down the amount of logic required, this dependence
18325 check is not based on a full instruction decode. Instead, any non-SPECIAL
18326 instruction is assumed to modify the register specified by bits 20-16
18327 (which is usually the "rt" field).
18329 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
18330 input, so we can end up with a false dependence between the branch
18331 and its delay slot. If this situation occurs in instruction INSN,
18332 try to avoid it by swapping rs and rt. */
18335 vr4130_avoid_branch_rt_conflict (rtx_insn
*insn
)
18337 rtx_insn
*first
, *second
;
18339 first
= SEQ_BEGIN (insn
);
18340 second
= SEQ_END (insn
);
18342 && NONJUMP_INSN_P (second
)
18343 && GET_CODE (PATTERN (first
)) == SET
18344 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
18345 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
18347 /* Check for the right kind of condition. */
18348 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
18349 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
18350 && REG_P (XEXP (cond
, 0))
18351 && REG_P (XEXP (cond
, 1))
18352 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
18353 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
18355 /* SECOND mentions the rt register but not the rs register. */
18356 rtx tmp
= XEXP (cond
, 0);
18357 XEXP (cond
, 0) = XEXP (cond
, 1);
18358 XEXP (cond
, 1) = tmp
;
18363 /* Implement -mvr4130-align. Go through each basic block and simulate the
18364 processor pipeline. If we find that a pair of instructions could execute
18365 in parallel, and the first of those instructions is not 8-byte aligned,
18366 insert a nop to make it aligned. */
18369 vr4130_align_insns (void)
18371 struct mips_sim state
;
18372 rtx_insn
*insn
, *subinsn
, *last
, *last2
, *next
;
18377 /* LAST is the last instruction before INSN to have a nonzero length.
18378 LAST2 is the last such instruction before LAST. */
18382 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
18385 mips_sim_init (&state
, alloca (state_size ()));
18386 for (insn
= get_insns (); insn
!= 0; insn
= next
)
18388 unsigned int length
;
18390 next
= NEXT_INSN (insn
);
18392 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
18393 This isn't really related to the alignment pass, but we do it on
18394 the fly to avoid a separate instruction walk. */
18395 vr4130_avoid_branch_rt_conflict (insn
);
18397 length
= get_attr_length (insn
);
18398 if (length
> 0 && USEFUL_INSN_P (insn
))
18399 FOR_EACH_SUBINSN (subinsn
, insn
)
18401 mips_sim_wait_insn (&state
, subinsn
);
18403 /* If we want this instruction to issue in parallel with the
18404 previous one, make sure that the previous instruction is
18405 aligned. There are several reasons why this isn't worthwhile
18406 when the second instruction is a call:
18408 - Calls are less likely to be performance critical,
18409 - There's a good chance that the delay slot can execute
18410 in parallel with the call.
18411 - The return address would then be unaligned.
18413 In general, if we're going to insert a nop between instructions
18414 X and Y, it's better to insert it immediately after X. That
18415 way, if the nop makes Y aligned, it will also align any labels
18416 between X and Y. */
18417 if (state
.insns_left
!= state
.issue_rate
18418 && !CALL_P (subinsn
))
18420 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
18422 /* SUBINSN is the first instruction in INSN and INSN is
18423 aligned. We want to align the previous instruction
18424 instead, so insert a nop between LAST2 and LAST.
18426 Note that LAST could be either a single instruction
18427 or a branch with a delay slot. In the latter case,
18428 LAST, like INSN, is already aligned, but the delay
18429 slot must have some extra delay that stops it from
18430 issuing at the same time as the branch. We therefore
18431 insert a nop before the branch in order to align its
18433 gcc_assert (last2
);
18434 emit_insn_after (gen_nop (), last2
);
18437 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
18439 /* SUBINSN is the delay slot of INSN, but INSN is
18440 currently unaligned. Insert a nop between
18441 LAST and INSN to align it. */
18443 emit_insn_after (gen_nop (), last
);
18447 mips_sim_issue_insn (&state
, subinsn
);
18449 mips_sim_finish_insn (&state
, insn
);
18451 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
18452 length
= get_attr_length (insn
);
18455 /* If the instruction is an asm statement or multi-instruction
18456 mips.md patern, the length is only an estimate. Insert an
18457 8 byte alignment after it so that the following instructions
18458 can be handled correctly. */
18459 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
18460 && (recog_memoized (insn
) < 0 || length
>= 8))
18462 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
18463 next
= NEXT_INSN (next
);
18464 mips_sim_next_cycle (&state
);
18467 else if (length
& 4)
18468 aligned_p
= !aligned_p
;
18473 /* See whether INSN is an aligned label. */
18474 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
18480 /* This structure records that the current function has a LO_SUM
18481 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
18482 the largest offset applied to BASE by all such LO_SUMs. */
18483 struct mips_lo_sum_offset
{
18485 HOST_WIDE_INT offset
;
18488 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
18491 mips_hash_base (rtx base
)
18493 int do_not_record_p
;
18495 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
18498 /* Hashtable helpers. */
18500 struct mips_lo_sum_offset_hasher
: free_ptr_hash
<mips_lo_sum_offset
>
18502 typedef rtx_def
*compare_type
;
18503 static inline hashval_t
hash (const mips_lo_sum_offset
*);
18504 static inline bool equal (const mips_lo_sum_offset
*, const rtx_def
*);
18507 /* Hash-table callbacks for mips_lo_sum_offsets. */
18510 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset
*entry
)
18512 return mips_hash_base (entry
->base
);
18516 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset
*entry
,
18517 const rtx_def
*value
)
18519 return rtx_equal_p (entry
->base
, value
);
18522 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
18524 /* Look up symbolic constant X in HTAB, which is a hash table of
18525 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
18526 paired with a recorded LO_SUM, otherwise record X in the table. */
18529 mips_lo_sum_offset_lookup (mips_offset_table
*htab
, rtx x
,
18530 enum insert_option option
)
18533 mips_lo_sum_offset
**slot
;
18534 struct mips_lo_sum_offset
*entry
;
18536 /* Split X into a base and offset. */
18537 split_const (x
, &base
, &offset
);
18538 if (UNSPEC_ADDRESS_P (base
))
18539 base
= UNSPEC_ADDRESS (base
);
18541 /* Look up the base in the hash table. */
18542 slot
= htab
->find_slot_with_hash (base
, mips_hash_base (base
), option
);
18546 entry
= (struct mips_lo_sum_offset
*) *slot
;
18547 if (option
== INSERT
)
18551 entry
= XNEW (struct mips_lo_sum_offset
);
18552 entry
->base
= base
;
18553 entry
->offset
= INTVAL (offset
);
18558 if (INTVAL (offset
) > entry
->offset
)
18559 entry
->offset
= INTVAL (offset
);
18562 return INTVAL (offset
) <= entry
->offset
;
18565 /* Search X for LO_SUMs and record them in HTAB. */
18568 mips_record_lo_sums (const_rtx x
, mips_offset_table
*htab
)
18570 subrtx_iterator::array_type array
;
18571 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
18572 if (GET_CODE (*iter
) == LO_SUM
)
18573 mips_lo_sum_offset_lookup (htab
, XEXP (*iter
, 1), INSERT
);
18576 /* Return true if INSN is a SET of an orphaned high-part relocation.
18577 HTAB is a hash table of mips_lo_sum_offsets that describes all the
18578 LO_SUMs in the current function. */
18581 mips_orphaned_high_part_p (mips_offset_table
*htab
, rtx_insn
*insn
)
18583 enum mips_symbol_type type
;
18586 set
= single_set (insn
);
18589 /* Check for %his. */
18591 if (GET_CODE (x
) == HIGH
18592 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
18593 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
18595 /* Check for local %gots (and %got_pages, which is redundant but OK). */
18596 if (GET_CODE (x
) == UNSPEC
18597 && XINT (x
, 1) == UNSPEC_LOAD_GOT
18598 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
18599 SYMBOL_CONTEXT_LEA
, &type
)
18600 && type
== SYMBOL_GOTOFF_PAGE
)
18601 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
18606 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
18607 INSN and a previous instruction, avoid it by inserting nops after
18610 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
18611 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
18612 before using the value of that register. *HILO_DELAY counts the
18613 number of instructions since the last hilo hazard (that is,
18614 the number of instructions since the last MFLO or MFHI).
18616 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
18617 for the next instruction.
18619 LO_REG is an rtx for the LO register, used in dependence checking. */
18622 mips_avoid_hazard (rtx_insn
*after
, rtx_insn
*insn
, int *hilo_delay
,
18623 rtx
*delayed_reg
, rtx lo_reg
, bool *fs_delay
)
18628 pattern
= PATTERN (insn
);
18630 /* Do not put the whole function in .set noreorder if it contains
18631 an asm statement. We don't know whether there will be hazards
18632 between the asm statement and the gcc-generated code. */
18633 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
18634 cfun
->machine
->all_noreorder_p
= false;
18636 /* Ignore zero-length instructions (barriers and the like). */
18637 ninsns
= get_attr_length (insn
) / 4;
18641 /* Work out how many nops are needed. Note that we only care about
18642 registers that are explicitly mentioned in the instruction's pattern.
18643 It doesn't matter that calls use the argument registers or that they
18644 clobber hi and lo. */
18645 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
18646 nops
= 2 - *hilo_delay
;
18647 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
18649 /* If processing a forbidden slot hazard then a NOP is required if the
18650 branch instruction was not in a sequence (as the sequence would
18651 imply it is not actually a compact branch anyway) and the current
18652 insn is not an inline asm, and can't go in a delay slot. */
18653 else if (*fs_delay
&& get_attr_can_delay (insn
) == CAN_DELAY_NO
18654 && GET_CODE (PATTERN (after
)) != SEQUENCE
18655 && GET_CODE (pattern
) != ASM_INPUT
18656 && asm_noperands (pattern
) < 0)
18661 /* Insert the nops between this instruction and the previous one.
18662 Each new nop takes us further from the last hilo hazard. */
18663 *hilo_delay
+= nops
;
18665 emit_insn_after (gen_hazard_nop (), after
);
18667 /* Set up the state for the next instruction. */
18668 *hilo_delay
+= ninsns
;
18671 if (INSN_CODE (insn
) >= 0)
18672 switch (get_attr_hazard (insn
))
18677 case HAZARD_FORBIDDEN_SLOT
:
18678 if (TARGET_CB_MAYBE
)
18687 set
= single_set (insn
);
18689 *delayed_reg
= SET_DEST (set
);
18694 /* A SEQUENCE is breakable iff the branch inside it has a compact form
18695 and the target has compact branches. */
18698 mips_breakable_sequence_p (rtx_insn
*insn
)
18700 return (insn
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
18702 && get_attr_compact_form (SEQ_BEGIN (insn
)) != COMPACT_FORM_NEVER
);
18705 /* Remove a SEQUENCE and replace it with the delay slot instruction
18706 followed by the branch and return the instruction in the delay slot.
18707 Return the first of the two new instructions.
18708 Subroutine of mips_reorg_process_insns. */
18711 mips_break_sequence (rtx_insn
*insn
)
18713 rtx_insn
*before
= PREV_INSN (insn
);
18714 rtx_insn
*branch
= SEQ_BEGIN (insn
);
18715 rtx_insn
*ds
= SEQ_END (insn
);
18716 remove_insn (insn
);
18717 add_insn_after (ds
, before
, NULL
);
18718 add_insn_after (branch
, ds
, NULL
);
18722 /* Go through the instruction stream and insert nops where necessary.
18723 Also delete any high-part relocations whose partnering low parts
18724 are now all dead. See if the whole function can then be put into
18725 .set noreorder and .set nomacro. */
18728 mips_reorg_process_insns (void)
18730 rtx_insn
*insn
, *last_insn
, *subinsn
, *next_insn
;
18731 rtx lo_reg
, delayed_reg
;
18735 /* Force all instructions to be split into their final form. */
18736 split_all_insns_noflow ();
18738 /* Recalculate instruction lengths without taking nops into account. */
18739 cfun
->machine
->ignore_hazard_length_p
= true;
18740 shorten_branches (get_insns ());
18742 cfun
->machine
->all_noreorder_p
= true;
18744 /* We don't track MIPS16 PC-relative offsets closely enough to make
18745 a good job of "set .noreorder" code in MIPS16 mode. */
18747 cfun
->machine
->all_noreorder_p
= false;
18749 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
18750 if (!TARGET_EXPLICIT_RELOCS
)
18751 cfun
->machine
->all_noreorder_p
= false;
18753 /* Profiled functions can't be all noreorder because the profiler
18754 support uses assembler macros. */
18756 cfun
->machine
->all_noreorder_p
= false;
18758 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
18759 all noreorder because we rely on the assembler to work around some
18760 errata. The R5900 too has several bugs. */
18761 if (TARGET_FIX_VR4120
18762 || TARGET_FIX_RM7000
18764 || TARGET_MIPS5900
)
18765 cfun
->machine
->all_noreorder_p
= false;
18767 /* The same is true for -mfix-vr4130 if we might generate MFLO or
18768 MFHI instructions. Note that we avoid using MFLO and MFHI if
18769 the VR4130 MACC and DMACC instructions are available instead;
18770 see the *mfhilo_{si,di}_macc patterns. */
18771 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
18772 cfun
->machine
->all_noreorder_p
= false;
18774 mips_offset_table
htab (37);
18776 /* Make a first pass over the instructions, recording all the LO_SUMs. */
18777 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
18778 FOR_EACH_SUBINSN (subinsn
, insn
)
18779 if (USEFUL_INSN_P (subinsn
))
18781 rtx body
= PATTERN (insn
);
18782 int noperands
= asm_noperands (body
);
18783 if (noperands
>= 0)
18785 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
18786 bool *used
= XALLOCAVEC (bool, noperands
);
18787 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
18789 get_referenced_operands (string
, used
, noperands
);
18790 for (int i
= 0; i
< noperands
; ++i
)
18792 mips_record_lo_sums (ops
[i
], &htab
);
18795 mips_record_lo_sums (PATTERN (subinsn
), &htab
);
18801 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
18804 /* Make a second pass over the instructions. Delete orphaned
18805 high-part relocations or turn them into NOPs. Avoid hazards
18806 by inserting NOPs. */
18807 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
18809 next_insn
= NEXT_INSN (insn
);
18810 if (USEFUL_INSN_P (insn
))
18812 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
18814 rtx_insn
*next_active
= next_active_insn (insn
);
18815 /* Undo delay slots to avoid bubbles if the next instruction can
18816 be placed in a forbidden slot or the cost of adding an
18817 explicit NOP in a forbidden slot is OK and if the SEQUENCE is
18818 safely breakable. */
18819 if (TARGET_CB_MAYBE
18820 && mips_breakable_sequence_p (insn
)
18821 && INSN_P (SEQ_BEGIN (insn
))
18822 && INSN_P (SEQ_END (insn
))
18824 && INSN_P (next_active
)
18825 && GET_CODE (PATTERN (next_active
)) != SEQUENCE
18826 && get_attr_can_delay (next_active
) == CAN_DELAY_YES
)
18827 || !optimize_size
))
18829 /* To hide a potential pipeline bubble, if we scan backwards
18830 from the current SEQUENCE and find that there is a load
18831 of a value that is used in the CTI and there are no
18832 dependencies between the CTI and instruction in the delay
18833 slot, break the sequence so the load delay is hidden. */
18835 CLEAR_HARD_REG_SET (uses
);
18836 note_uses (&PATTERN (SEQ_BEGIN (insn
)), record_hard_reg_uses
,
18838 HARD_REG_SET delay_sets
;
18839 CLEAR_HARD_REG_SET (delay_sets
);
18840 note_stores (PATTERN (SEQ_END (insn
)), record_hard_reg_sets
,
18843 rtx_insn
*prev
= prev_active_insn (insn
);
18845 && GET_CODE (PATTERN (prev
)) == SET
18846 && MEM_P (SET_SRC (PATTERN (prev
))))
18849 CLEAR_HARD_REG_SET (sets
);
18850 note_stores (PATTERN (prev
), record_hard_reg_sets
,
18853 /* Re-order if safe. */
18854 if (!hard_reg_set_intersect_p (delay_sets
, uses
)
18855 && hard_reg_set_intersect_p (uses
, sets
))
18857 next_insn
= mips_break_sequence (insn
);
18858 /* Need to process the hazards of the newly
18859 introduced instructions. */
18864 /* If we find an orphaned high-part relocation in a delay
18865 slot then we can convert to a compact branch and get
18866 the orphaned high part deleted. */
18867 if (mips_orphaned_high_part_p (&htab
, SEQ_END (insn
)))
18869 next_insn
= mips_break_sequence (insn
);
18870 /* Need to process the hazards of the newly
18871 introduced instructions. */
18876 /* If we find an orphaned high-part relocation in a delay
18877 slot, it's easier to turn that instruction into a NOP than
18878 to delete it. The delay slot will be a NOP either way. */
18879 FOR_EACH_SUBINSN (subinsn
, insn
)
18880 if (INSN_P (subinsn
))
18882 if (mips_orphaned_high_part_p (&htab
, subinsn
))
18884 PATTERN (subinsn
) = gen_nop ();
18885 INSN_CODE (subinsn
) = CODE_FOR_nop
;
18887 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
18888 &delayed_reg
, lo_reg
, &fs_delay
);
18894 /* INSN is a single instruction. Delete it if it's an
18895 orphaned high-part relocation. */
18896 if (mips_orphaned_high_part_p (&htab
, insn
))
18897 delete_insn (insn
);
18898 /* Also delete cache barriers if the last instruction
18899 was an annulled branch. INSN will not be speculatively
18901 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
18903 && JUMP_P (SEQ_BEGIN (last_insn
))
18904 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
18905 delete_insn (insn
);
18908 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
18909 &delayed_reg
, lo_reg
, &fs_delay
);
18910 /* When a compact branch introduces a forbidden slot hazard
18911 and the next useful instruction is a SEQUENCE of a jump
18912 and a non-nop instruction in the delay slot, remove the
18913 sequence and replace it with the delay slot instruction
18914 then the jump to clear the forbidden slot hazard. */
18918 /* Search onwards from the current position looking for
18919 a SEQUENCE. We are looking for pipeline hazards here
18920 and do not need to worry about labels or barriers as
18921 the optimization only undoes delay slot filling which
18922 only affects the order of the branch and its delay
18924 rtx_insn
*next
= next_active_insn (insn
);
18926 && USEFUL_INSN_P (next
)
18927 && GET_CODE (PATTERN (next
)) == SEQUENCE
18928 && mips_breakable_sequence_p (next
))
18931 next_insn
= mips_break_sequence (next
);
18932 /* Need to process the hazards of the newly
18933 introduced instructions. */
18944 /* Return true if the function has a long branch instruction. */
18947 mips_has_long_branch_p (void)
18949 rtx_insn
*insn
, *subinsn
;
18952 /* We need up-to-date instruction lengths. */
18953 shorten_branches (get_insns ());
18955 /* Look for a branch that is longer than normal. The normal length for
18956 non-MIPS16 branches is 8, because the length includes the delay slot.
18957 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
18958 but they have no delay slot. */
18959 normal_length
= (TARGET_MIPS16
? 4 : 8);
18960 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
18961 FOR_EACH_SUBINSN (subinsn
, insn
)
18962 if (JUMP_P (subinsn
)
18963 && get_attr_length (subinsn
) > normal_length
18964 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
18970 /* If we are using a GOT, but have not decided to use a global pointer yet,
18971 see whether we need one to implement long branches. Convert the ghost
18972 global-pointer instructions into real ones if so. */
18975 mips_expand_ghost_gp_insns (void)
18977 /* Quick exit if we already know that we will or won't need a
18979 if (!TARGET_USE_GOT
18980 || cfun
->machine
->global_pointer
== INVALID_REGNUM
18981 || mips_must_initialize_gp_p ())
18984 /* Run a full check for long branches. */
18985 if (!mips_has_long_branch_p ())
18988 /* We've now established that we need $gp. */
18989 cfun
->machine
->must_initialize_gp_p
= true;
18990 split_all_insns_noflow ();
18995 /* Subroutine of mips_reorg to manage passes that require DF. */
18998 mips_df_reorg (void)
19000 /* Create def-use chains. */
19001 df_set_flags (DF_EQ_NOTES
);
19002 df_chain_add_problem (DF_UD_CHAIN
);
19005 if (TARGET_RELAX_PIC_CALLS
)
19006 mips_annotate_pic_calls ();
19008 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
19009 r10k_insert_cache_barriers ();
19011 df_finish_pass (false);
19014 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
19015 called very late in mips_reorg, but the caller is required to run
19016 mips16_lay_out_constants on the result. */
19019 mips16_load_branch_target (rtx dest
, rtx src
)
19021 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
19025 if (mips_cfun_has_cprestore_slot_p ())
19026 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
19028 mips_emit_move (dest
, pic_offset_table_rtx
);
19029 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
19030 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
19031 emit_insn (gen_rtx_SET (dest
,
19032 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
19033 emit_insn (gen_rtx_SET (dest
, gen_rtx_LO_SUM (Pmode
, dest
, low
)));
19037 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
19038 mips_emit_move (dest
, src
);
19042 /* If we're compiling a MIPS16 function, look for and split any long branches.
19043 This must be called after all other instruction modifications in
19047 mips16_split_long_branches (void)
19049 bool something_changed
;
19051 if (!TARGET_MIPS16
)
19054 /* Loop until the alignments for all targets are sufficient. */
19058 rtx_jump_insn
*jump_insn
;
19060 shorten_branches (get_insns ());
19061 something_changed
= false;
19062 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
19063 if ((jump_insn
= dyn_cast
<rtx_jump_insn
*> (insn
))
19064 && get_attr_length (jump_insn
) > 4
19065 && (any_condjump_p (jump_insn
) || any_uncondjump_p (jump_insn
)))
19067 rtx old_label
, temp
, saved_temp
;
19068 rtx_code_label
*new_label
;
19070 rtx_insn
*jump
, *jump_sequence
;
19074 /* Free up a MIPS16 register by saving it in $1. */
19075 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
19076 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
19077 emit_move_insn (saved_temp
, temp
);
19079 /* Load the branch target into TEMP. */
19080 old_label
= JUMP_LABEL (jump_insn
);
19081 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
19082 mips16_load_branch_target (temp
, target
);
19084 /* Jump to the target and restore the register's
19086 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
19087 (temp
, temp
, saved_temp
)));
19088 JUMP_LABEL (jump
) = old_label
;
19089 LABEL_NUSES (old_label
)++;
19091 /* Rewrite any symbolic references that are supposed to use
19092 a PC-relative constant pool. */
19093 mips16_lay_out_constants (false);
19095 if (simplejump_p (jump_insn
))
19096 /* We're going to replace INSN with a longer form. */
19100 /* Create a branch-around label for the original
19102 new_label
= gen_label_rtx ();
19103 emit_label (new_label
);
19106 jump_sequence
= get_insns ();
19109 emit_insn_after (jump_sequence
, jump_insn
);
19111 invert_jump (jump_insn
, new_label
, false);
19113 delete_insn (jump_insn
);
19114 something_changed
= true;
19117 while (something_changed
);
19120 /* Insert a `.insn' assembly pseudo-op after any labels followed by
19121 a MIPS16 constant pool or no insn at all. This is needed so that
19122 targets that have been optimized away are still marked as code
19123 and therefore branches that remained and point to them are known
19124 to retain the ISA mode and as such can be successfully assembled. */
19127 mips_insert_insn_pseudos (void)
19129 bool insn_pseudo_needed
= TRUE
;
19132 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
19133 switch (GET_CODE (insn
))
19136 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
19137 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE
)
19139 insn_pseudo_needed
= TRUE
;
19142 /* Fall through. */
19145 case JUMP_TABLE_DATA
:
19146 insn_pseudo_needed
= FALSE
;
19149 if (insn_pseudo_needed
)
19151 emit_insn_after (gen_insn_pseudo (), insn
);
19152 insn_pseudo_needed
= FALSE
;
19160 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
19165 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
19166 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
19167 to date if the CFG is available. */
19168 if (mips_cfg_in_reorg ())
19169 compute_bb_for_insn ();
19170 mips16_lay_out_constants (true);
19171 if (mips_cfg_in_reorg ())
19174 free_bb_for_insn ();
19178 /* We use a machine specific pass to do a second machine dependent reorg
19179 pass after delay branch scheduling. */
19181 static unsigned int
19182 mips_machine_reorg2 (void)
19184 mips_reorg_process_insns ();
19186 && TARGET_EXPLICIT_RELOCS
19188 && TARGET_VR4130_ALIGN
)
19189 vr4130_align_insns ();
19190 if (mips_expand_ghost_gp_insns ())
19191 /* The expansion could invalidate some of the VR4130 alignment
19192 optimizations, but this should be an extremely rare case anyhow. */
19193 mips_reorg_process_insns ();
19194 mips16_split_long_branches ();
19195 mips_insert_insn_pseudos ();
19201 const pass_data pass_data_mips_machine_reorg2
=
19203 RTL_PASS
, /* type */
19204 "mach2", /* name */
19205 OPTGROUP_NONE
, /* optinfo_flags */
19206 TV_MACH_DEP
, /* tv_id */
19207 0, /* properties_required */
19208 0, /* properties_provided */
19209 0, /* properties_destroyed */
19210 0, /* todo_flags_start */
19211 0, /* todo_flags_finish */
19214 class pass_mips_machine_reorg2
: public rtl_opt_pass
19217 pass_mips_machine_reorg2(gcc::context
*ctxt
)
19218 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
19221 /* opt_pass methods: */
19222 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
19224 }; // class pass_mips_machine_reorg2
19226 } // anon namespace
19229 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
19231 return new pass_mips_machine_reorg2 (ctxt
);
19235 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
19236 in order to avoid duplicating too much logic from elsewhere. */
19239 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
19240 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
19243 rtx this_rtx
, temp1
, temp2
, fnaddr
;
19245 bool use_sibcall_p
;
19247 /* Pretend to be a post-reload pass while generating rtl. */
19248 reload_completed
= 1;
19250 /* Mark the end of the (empty) prologue. */
19251 emit_note (NOTE_INSN_PROLOGUE_END
);
19253 /* Determine if we can use a sibcall to call FUNCTION directly. */
19254 fnaddr
= XEXP (DECL_RTL (function
), 0);
19255 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
19256 && const_call_insn_operand (fnaddr
, Pmode
));
19258 /* Determine if we need to load FNADDR from the GOT. */
19260 && (mips_got_symbol_type_p
19261 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
19263 /* Pick a global pointer. Use a call-clobbered register if
19264 TARGET_CALL_SAVED_GP. */
19265 cfun
->machine
->global_pointer
19266 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
19267 cfun
->machine
->must_initialize_gp_p
= true;
19268 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
19270 /* Set up the global pointer for n32 or n64 abicalls. */
19271 mips_emit_loadgp ();
19274 /* We need two temporary registers in some cases. */
19275 temp1
= gen_rtx_REG (Pmode
, 2);
19276 temp2
= gen_rtx_REG (Pmode
, 3);
19278 /* Find out which register contains the "this" pointer. */
19279 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
19280 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
19282 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
19284 /* Add DELTA to THIS_RTX. */
19287 rtx offset
= GEN_INT (delta
);
19288 if (!SMALL_OPERAND (delta
))
19290 mips_emit_move (temp1
, offset
);
19293 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
19296 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
19297 if (vcall_offset
!= 0)
19301 /* Set TEMP1 to *THIS_RTX. */
19302 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
19304 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
19305 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
19307 /* Load the offset and add it to THIS_RTX. */
19308 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
19309 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
19312 /* Jump to the target function. Use a sibcall if direct jumps are
19313 allowed, otherwise load the address into a register first. */
19316 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
19317 SIBLING_CALL_P (insn
) = 1;
19321 /* This is messy. GAS treats "la $25,foo" as part of a call
19322 sequence and may allow a global "foo" to be lazily bound.
19323 The general move patterns therefore reject this combination.
19325 In this context, lazy binding would actually be OK
19326 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
19327 TARGET_CALL_SAVED_GP; see mips_load_call_address.
19328 We must therefore load the address via a temporary
19329 register if mips_dangerous_for_la25_p.
19331 If we jump to the temporary register rather than $25,
19332 the assembler can use the move insn to fill the jump's
19335 We can use the same technique for MIPS16 code, where $25
19336 is not a valid JR register. */
19337 if (TARGET_USE_PIC_FN_ADDR_REG
19339 && !mips_dangerous_for_la25_p (fnaddr
))
19340 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
19341 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
19343 if (TARGET_USE_PIC_FN_ADDR_REG
19344 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
19345 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
19346 emit_jump_insn (gen_indirect_jump (temp1
));
19349 /* Run just enough of rest_of_compilation. This sequence was
19350 "borrowed" from alpha.c. */
19351 insn
= get_insns ();
19352 split_all_insns_noflow ();
19353 mips16_lay_out_constants (true);
19354 shorten_branches (insn
);
19355 final_start_function (insn
, file
, 1);
19356 final (insn
, file
, 1);
19357 final_end_function ();
19359 /* Clean up the vars set above. Note that final_end_function resets
19360 the global pointer for us. */
19361 reload_completed
= 0;
19365 /* The last argument passed to mips_set_compression_mode,
19366 or negative if the function hasn't been called yet. */
19367 static unsigned int old_compression_mode
= -1;
19369 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
19370 which is either MASK_MIPS16 or MASK_MICROMIPS. */
19373 mips_set_compression_mode (unsigned int compression_mode
)
19376 if (compression_mode
== old_compression_mode
)
19379 /* Restore base settings of various flags. */
19380 target_flags
= mips_base_target_flags
;
19381 flag_schedule_insns
= mips_base_schedule_insns
;
19382 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
19383 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
19384 align_loops
= mips_base_align_loops
;
19385 align_jumps
= mips_base_align_jumps
;
19386 align_functions
= mips_base_align_functions
;
19387 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
19388 target_flags
|= compression_mode
;
19390 if (compression_mode
& MASK_MIPS16
)
19392 /* Switch to MIPS16 mode. */
19393 target_flags
|= MASK_MIPS16
;
19395 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
19396 target_flags
&= ~MASK_SYNCI
;
19398 /* Don't run the scheduler before reload, since it tends to
19399 increase register pressure. */
19400 flag_schedule_insns
= 0;
19402 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
19403 the whole function to be in a single section. */
19404 flag_reorder_blocks_and_partition
= 0;
19406 /* Don't move loop invariants, because it tends to increase
19407 register pressure. It also introduces an extra move in cases
19408 where the constant is the first operand in a two-operand binary
19409 instruction, or when it forms a register argument to a functon
19411 flag_move_loop_invariants
= 0;
19413 target_flags
|= MASK_EXPLICIT_RELOCS
;
19415 /* Experiments suggest we get the best overall section-anchor
19416 results from using the range of an unextended LW or SW. Code
19417 that makes heavy use of byte or short accesses can do better
19418 with ranges of 0...31 and 0...63 respectively, but most code is
19419 sensitive to the range of LW and SW instead. */
19420 targetm
.min_anchor_offset
= 0;
19421 targetm
.max_anchor_offset
= 127;
19423 targetm
.const_anchor
= 0;
19425 /* MIPS16 has no BAL instruction. */
19426 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
19428 /* The R4000 errata don't apply to any known MIPS16 cores.
19429 It's simpler to make the R4000 fixes and MIPS16 mode
19430 mutually exclusive. */
19431 target_flags
&= ~MASK_FIX_R4000
;
19433 if (flag_pic
&& !TARGET_OLDABI
)
19434 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
19437 sorry ("MIPS16 -mxgot code");
19439 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
19440 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
19443 sorry ("MSA MIPS16 code");
19447 /* Switch to microMIPS or the standard encoding. */
19449 if (TARGET_MICROMIPS
)
19450 /* Avoid branch likely. */
19451 target_flags
&= ~MASK_BRANCHLIKELY
;
19453 /* Provide default values for align_* for 64-bit targets. */
19456 if (align_loops
== 0)
19458 if (align_jumps
== 0)
19460 if (align_functions
== 0)
19461 align_functions
= 8;
19464 targetm
.min_anchor_offset
= -32768;
19465 targetm
.max_anchor_offset
= 32767;
19467 targetm
.const_anchor
= 0x8000;
19470 /* (Re)initialize MIPS target internals for new ISA. */
19471 mips_init_relocs ();
19473 if (compression_mode
& MASK_MIPS16
)
19475 if (!mips16_globals
)
19476 mips16_globals
= save_target_globals_default_opts ();
19478 restore_target_globals (mips16_globals
);
19480 else if (compression_mode
& MASK_MICROMIPS
)
19482 if (!micromips_globals
)
19483 micromips_globals
= save_target_globals_default_opts ();
19485 restore_target_globals (micromips_globals
);
19488 restore_target_globals (&default_target_globals
);
19490 old_compression_mode
= compression_mode
;
19493 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
19494 function should use the MIPS16 or microMIPS ISA and switch modes
19498 mips_set_current_function (tree fndecl
)
19500 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
19503 /* Allocate a chunk of memory for per-function machine-dependent data. */
19505 static struct machine_function
*
19506 mips_init_machine_status (void)
19508 return ggc_cleared_alloc
<machine_function
> ();
19511 /* Return the processor associated with the given ISA level, or null
19512 if the ISA isn't valid. */
19514 static const struct mips_cpu_info
*
19515 mips_cpu_info_from_isa (int isa
)
19519 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
19520 if (mips_cpu_info_table
[i
].isa
== isa
)
19521 return mips_cpu_info_table
+ i
;
19526 /* Return a mips_cpu_info entry determined by an option valued
19529 static const struct mips_cpu_info
*
19530 mips_cpu_info_from_opt (int opt
)
19534 case MIPS_ARCH_OPTION_FROM_ABI
:
19535 /* 'from-abi' selects the most compatible architecture for the
19536 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
19537 ABIs. For the EABIs, we have to decide whether we're using
19538 the 32-bit or 64-bit version. */
19539 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
19540 : ABI_NEEDS_64BIT_REGS
? 3
19541 : (TARGET_64BIT
? 3 : 1));
19543 case MIPS_ARCH_OPTION_NATIVE
:
19544 gcc_unreachable ();
19547 return &mips_cpu_info_table
[opt
];
19551 /* Return a default mips_cpu_info entry, given that no -march= option
19552 was explicitly specified. */
19554 static const struct mips_cpu_info
*
19555 mips_default_arch (void)
19557 #if defined (MIPS_CPU_STRING_DEFAULT)
19559 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
19560 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
19561 return mips_cpu_info_table
+ i
;
19562 gcc_unreachable ();
19563 #elif defined (MIPS_ISA_DEFAULT)
19564 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
19566 /* 'from-abi' makes a good default: you get whatever the ABI
19568 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
19572 /* Set up globals to generate code for the ISA or processor
19573 described by INFO. */
19576 mips_set_architecture (const struct mips_cpu_info
*info
)
19580 mips_arch_info
= info
;
19581 mips_arch
= info
->cpu
;
19582 mips_isa
= info
->isa
;
19586 mips_isa_rev
= (mips_isa
& 31) + 1;
19590 /* Likewise for tuning. */
19593 mips_set_tune (const struct mips_cpu_info
*info
)
19597 mips_tune_info
= info
;
19598 mips_tune
= info
->cpu
;
19602 /* Implement TARGET_OPTION_OVERRIDE. */
19605 mips_option_override (void)
19607 int i
, start
, regno
, mode
;
19609 if (global_options_set
.x_mips_isa_option
)
19610 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
19612 #ifdef SUBTARGET_OVERRIDE_OPTIONS
19613 SUBTARGET_OVERRIDE_OPTIONS
;
19616 /* MIPS16 and microMIPS cannot coexist. */
19617 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
19618 error ("unsupported combination: %s", "-mips16 -mmicromips");
19620 /* Prohibit Paired-Single and MSA combination. This is software restriction
19621 rather than architectural. */
19622 if (ISA_HAS_MSA
&& TARGET_PAIRED_SINGLE_FLOAT
)
19623 error ("unsupported combination: %s", "-mmsa -mpaired-single");
19625 /* Save the base compression state and process flags as though we
19626 were generating uncompressed code. */
19627 mips_base_compression_flags
= TARGET_COMPRESSION
;
19628 target_flags
&= ~TARGET_COMPRESSION
;
19630 /* -mno-float overrides -mhard-float and -msoft-float. */
19631 if (TARGET_NO_FLOAT
)
19633 target_flags
|= MASK_SOFT_FLOAT_ABI
;
19634 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
19637 if (TARGET_FLIP_MIPS16
)
19638 TARGET_INTERLINK_COMPRESSED
= 1;
19640 /* Set the small data limit. */
19641 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
19643 : MIPS_DEFAULT_GVALUE
);
19645 /* The following code determines the architecture and register size.
19646 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
19647 The GAS and GCC code should be kept in sync as much as possible. */
19649 if (global_options_set
.x_mips_arch_option
)
19650 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
19652 if (mips_isa_option_info
!= 0)
19654 if (mips_arch_info
== 0)
19655 mips_set_architecture (mips_isa_option_info
);
19656 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
19657 error ("%<-%s%> conflicts with the other architecture options, "
19658 "which specify a %s processor",
19659 mips_isa_option_info
->name
,
19660 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
19663 if (mips_arch_info
== 0)
19664 mips_set_architecture (mips_default_arch ());
19666 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
19667 error ("%<-march=%s%> is not compatible with the selected ABI",
19668 mips_arch_info
->name
);
19670 /* Optimize for mips_arch, unless -mtune selects a different processor. */
19671 if (global_options_set
.x_mips_tune_option
)
19672 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
19674 if (mips_tune_info
== 0)
19675 mips_set_tune (mips_arch_info
);
19677 if ((target_flags_explicit
& MASK_64BIT
) != 0)
19679 /* The user specified the size of the integer registers. Make sure
19680 it agrees with the ABI and ISA. */
19681 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
19682 error ("%<-mgp64%> used with a 32-bit processor");
19683 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
19684 error ("%<-mgp32%> used with a 64-bit ABI");
19685 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
19686 error ("%<-mgp64%> used with a 32-bit ABI");
19690 /* Infer the integer register size from the ABI and processor.
19691 Restrict ourselves to 32-bit registers if that's all the
19692 processor has, or if the ABI cannot handle 64-bit registers. */
19693 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
19694 target_flags
&= ~MASK_64BIT
;
19696 target_flags
|= MASK_64BIT
;
19699 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
19701 if (mips_isa_rev
>= 6 && !TARGET_FLOAT64
)
19702 error ("the %qs architecture does not support %<-mfp32%>",
19703 mips_arch_info
->name
);
19704 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
19705 error ("unsupported combination: %s", "-mfp64 -msingle-float");
19706 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
19707 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
19708 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
19710 if (!ISA_HAS_MXHC1
)
19711 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
19712 " the target supports the mfhc1 and mthc1 instructions");
19713 else if (mips_abi
!= ABI_32
)
19714 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
19720 /* -msingle-float selects 32-bit float registers. On r6 and later,
19721 -mdouble-float selects 64-bit float registers, since the old paired
19722 register model is not supported. In other cases the float registers
19723 should be the same size as the integer ones. */
19724 if (mips_isa_rev
>= 6 && TARGET_DOUBLE_FLOAT
&& !TARGET_FLOATXX
)
19725 target_flags
|= MASK_FLOAT64
;
19726 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
19727 target_flags
|= MASK_FLOAT64
;
19728 else if (mips_abi
== ABI_32
&& ISA_HAS_MSA
&& !TARGET_FLOATXX
)
19729 target_flags
|= MASK_FLOAT64
;
19731 target_flags
&= ~MASK_FLOAT64
;
19734 if (mips_abi
!= ABI_32
&& TARGET_FLOATXX
)
19735 error ("%<-mfpxx%> can only be used with the o32 ABI");
19736 else if (TARGET_FLOAT64
&& TARGET_FLOATXX
)
19737 error ("unsupported combination: %s", "-mfp64 -mfpxx");
19738 else if (ISA_MIPS1
&& !TARGET_FLOAT32
)
19739 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info
->name
);
19740 else if (TARGET_FLOATXX
&& !mips_lra_flag
)
19741 error ("%<-mfpxx%> requires %<-mlra%>");
19743 /* End of code shared with GAS. */
19745 /* The R5900 FPU only supports single precision. */
19746 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
19747 error ("unsupported combination: %s",
19748 "-march=r5900 -mhard-float -mdouble-float");
19750 /* If a -mlong* option was given, check that it matches the ABI,
19751 otherwise infer the -mlong* setting from the other options. */
19752 if ((target_flags_explicit
& MASK_LONG64
) != 0)
19756 if (mips_abi
== ABI_N32
)
19757 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
19758 else if (mips_abi
== ABI_32
)
19759 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
19760 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
19761 /* We have traditionally allowed non-abicalls code to use
19762 an LP64 form of o64. However, it would take a bit more
19763 effort to support the combination of 32-bit GOT entries
19764 and 64-bit pointers, so we treat the abicalls case as
19766 error ("the combination of %qs and %qs is incompatible with %qs",
19767 "-mabi=o64", "-mabicalls", "-mlong64");
19771 if (mips_abi
== ABI_64
)
19772 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
19777 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
19778 target_flags
|= MASK_LONG64
;
19780 target_flags
&= ~MASK_LONG64
;
19783 if (!TARGET_OLDABI
)
19784 flag_pcc_struct_return
= 0;
19786 /* Decide which rtx_costs structure to use. */
19788 mips_cost
= &mips_rtx_cost_optimize_size
;
19790 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
19792 /* If the user hasn't specified a branch cost, use the processor's
19794 if (mips_branch_cost
== 0)
19795 mips_branch_cost
= mips_cost
->branch_cost
;
19797 /* If neither -mbranch-likely nor -mno-branch-likely was given
19798 on the command line, set MASK_BRANCHLIKELY based on the target
19799 architecture and tuning flags. Annulled delay slots are a
19800 size win, so we only consider the processor-specific tuning
19801 for !optimize_size. */
19802 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
19804 if (ISA_HAS_BRANCHLIKELY
19806 && (mips_tune_info
->tune_flags
19807 & PTF_AVOID_BRANCHLIKELY_SIZE
) == 0)
19810 && (mips_tune_info
->tune_flags
19811 & PTF_AVOID_BRANCHLIKELY_SPEED
) == 0)
19812 || (mips_tune_info
->tune_flags
19813 & PTF_AVOID_BRANCHLIKELY_ALWAYS
) == 0))
19814 target_flags
|= MASK_BRANCHLIKELY
;
19816 target_flags
&= ~MASK_BRANCHLIKELY
;
19818 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
19819 warning (0, "the %qs architecture does not support branch-likely"
19820 " instructions", mips_arch_info
->name
);
19822 /* If the user hasn't specified -mimadd or -mno-imadd set
19823 MASK_IMADD based on the target architecture and tuning
19825 if ((target_flags_explicit
& MASK_IMADD
) == 0)
19827 if (ISA_HAS_MADD_MSUB
&&
19828 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
19829 target_flags
|= MASK_IMADD
;
19831 target_flags
&= ~MASK_IMADD
;
19833 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
19834 warning (0, "the %qs architecture does not support madd or msub"
19835 " instructions", mips_arch_info
->name
);
19837 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
19838 line, set MASK_ODD_SPREG based on the ISA and ABI. */
19839 if ((target_flags_explicit
& MASK_ODD_SPREG
) == 0)
19841 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
19842 if (!ISA_HAS_ODD_SPREG
|| TARGET_FLOATXX
)
19843 target_flags
&= ~MASK_ODD_SPREG
;
19845 target_flags
|= MASK_ODD_SPREG
;
19847 else if (TARGET_ODD_SPREG
&& !ISA_HAS_ODD_SPREG
)
19848 warning (0, "the %qs architecture does not support odd single-precision"
19849 " registers", mips_arch_info
->name
);
19851 if (!TARGET_ODD_SPREG
&& TARGET_64BIT
)
19853 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
19854 /* Allow compilation to continue further even though invalid output
19855 will be produced. */
19856 target_flags
|= MASK_ODD_SPREG
;
19859 if (!ISA_HAS_COMPACT_BRANCHES
&& mips_cb
== MIPS_CB_ALWAYS
)
19861 error ("unsupported combination: %qs%s %s",
19862 mips_arch_info
->name
, TARGET_MICROMIPS
? " -mmicromips" : "",
19863 "-mcompact-branches=always");
19865 else if (!ISA_HAS_DELAY_SLOTS
&& mips_cb
== MIPS_CB_NEVER
)
19867 error ("unsupported combination: %qs%s %s",
19868 mips_arch_info
->name
, TARGET_MICROMIPS
? " -mmicromips" : "",
19869 "-mcompact-branches=never");
19872 /* Require explicit relocs for MIPS R6 onwards. This enables simplification
19873 of the compact branch and jump support through the backend. */
19874 if (!TARGET_EXPLICIT_RELOCS
&& mips_isa_rev
>= 6)
19876 error ("unsupported combination: %qs %s",
19877 mips_arch_info
->name
, "-mno-explicit-relocs");
19880 /* The effect of -mabicalls isn't defined for the EABI. */
19881 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
19883 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
19884 target_flags
&= ~MASK_ABICALLS
;
19887 /* PIC requires -mabicalls. */
19890 if (mips_abi
== ABI_EABI
)
19891 error ("cannot generate position-independent code for %qs",
19893 else if (!TARGET_ABICALLS
)
19894 error ("position-independent code requires %qs", "-mabicalls");
19897 if (TARGET_ABICALLS_PIC2
)
19898 /* We need to set flag_pic for executables as well as DSOs
19899 because we may reference symbols that are not defined in
19900 the final executable. (MIPS does not use things like
19901 copy relocs, for example.)
19903 There is a body of code that uses __PIC__ to distinguish
19904 between -mabicalls and -mno-abicalls code. The non-__PIC__
19905 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
19906 long as any indirect jumps use $25. */
19909 /* -mvr4130-align is a "speed over size" optimization: it usually produces
19910 faster code, but at the expense of more nops. Enable it at -O3 and
19912 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
19913 target_flags
|= MASK_VR4130_ALIGN
;
19915 /* Prefer a call to memcpy over inline code when optimizing for size,
19916 though see MOVE_RATIO in mips.h. */
19917 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
19918 target_flags
|= MASK_MEMCPY
;
19920 /* If we have a nonzero small-data limit, check that the -mgpopt
19921 setting is consistent with the other target flags. */
19922 if (mips_small_data_threshold
> 0)
19926 if (!TARGET_EXPLICIT_RELOCS
)
19927 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
19929 TARGET_LOCAL_SDATA
= false;
19930 TARGET_EXTERN_SDATA
= false;
19934 if (TARGET_VXWORKS_RTP
)
19935 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
19937 if (TARGET_ABICALLS
)
19938 warning (0, "cannot use small-data accesses for %qs",
19943 /* Set NaN and ABS defaults. */
19944 if (mips_nan
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
19945 mips_nan
= MIPS_IEEE_754_2008
;
19946 if (mips_abs
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
19947 mips_abs
= MIPS_IEEE_754_2008
;
19949 /* Check for IEEE 754 legacy/2008 support. */
19950 if ((mips_nan
== MIPS_IEEE_754_LEGACY
19951 || mips_abs
== MIPS_IEEE_754_LEGACY
)
19952 && !ISA_HAS_IEEE_754_LEGACY
)
19953 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
19954 mips_arch_info
->name
,
19955 mips_nan
== MIPS_IEEE_754_LEGACY
? "nan" : "abs");
19957 if ((mips_nan
== MIPS_IEEE_754_2008
19958 || mips_abs
== MIPS_IEEE_754_2008
)
19959 && !ISA_HAS_IEEE_754_2008
)
19960 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
19961 mips_arch_info
->name
,
19962 mips_nan
== MIPS_IEEE_754_2008
? "nan" : "abs");
19964 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
19965 for all its floating point. */
19966 if (mips_nan
!= MIPS_IEEE_754_2008
)
19968 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
19969 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
19970 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
19973 /* Make sure that the user didn't turn off paired single support when
19974 MIPS-3D support is requested. */
19976 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
19977 && !TARGET_PAIRED_SINGLE_FLOAT
)
19978 error ("%<-mips3d%> requires %<-mpaired-single%>");
19980 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
19982 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
19984 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
19985 and TARGET_HARD_FLOAT_ABI are both true. */
19986 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
19988 error ("%qs must be used with %qs",
19989 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
19990 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
19991 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
19995 /* Make sure that when ISA_HAS_MSA is true, TARGET_FLOAT64 and
19996 TARGET_HARD_FLOAT_ABI and both true. */
19997 if (ISA_HAS_MSA
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
19998 error ("%<-mmsa%> must be used with %<-mfp64%> and %<-mhard-float%>");
20000 /* Make sure that -mpaired-single is only used on ISAs that support it.
20001 We must disable it otherwise since it relies on other ISA properties
20002 like ISA_HAS_8CC having their normal values. */
20003 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
20005 error ("the %qs architecture does not support paired-single"
20006 " instructions", mips_arch_info
->name
);
20007 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
20011 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
20012 && !TARGET_CACHE_BUILTIN
)
20014 error ("%qs requires a target that provides the %qs instruction",
20015 "-mr10k-cache-barrier", "cache");
20016 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
20019 /* If TARGET_DSPR2, enable TARGET_DSP. */
20023 if (TARGET_DSP
&& mips_isa_rev
>= 6)
20025 error ("the %qs architecture does not support DSP instructions",
20026 mips_arch_info
->name
);
20027 TARGET_DSP
= false;
20028 TARGET_DSPR2
= false;
20031 /* .eh_frame addresses should be the same width as a C pointer.
20032 Most MIPS ABIs support only one pointer size, so the assembler
20033 will usually know exactly how big an .eh_frame address is.
20035 Unfortunately, this is not true of the 64-bit EABI. The ABI was
20036 originally defined to use 64-bit pointers (i.e. it is LP64), and
20037 this is still the default mode. However, we also support an n32-like
20038 ILP32 mode, which is selected by -mlong32. The problem is that the
20039 assembler has traditionally not had an -mlong option, so it has
20040 traditionally not known whether we're using the ILP32 or LP64 form.
20042 As it happens, gas versions up to and including 2.19 use _32-bit_
20043 addresses for EABI64 .cfi_* directives. This is wrong for the
20044 default LP64 mode, so we can't use the directives by default.
20045 Moreover, since gas's current behavior is at odds with gcc's
20046 default behavior, it seems unwise to rely on future versions
20047 of gas behaving the same way. We therefore avoid using .cfi
20048 directives for -mlong32 as well. */
20049 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
20050 flag_dwarf2_cfi_asm
= 0;
20052 /* .cfi_* directives generate a read-only section, so fall back on
20053 manual .eh_frame creation if we need the section to be writable. */
20054 if (TARGET_WRITABLE_EH_FRAME
)
20055 flag_dwarf2_cfi_asm
= 0;
20057 mips_init_print_operand_punct ();
20059 /* Set up array to map GCC register number to debug register number.
20060 Ignore the special purpose register numbers. */
20062 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
20064 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
20065 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
20066 mips_dwarf_regno
[i
] = i
;
20068 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
20071 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
20072 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
20073 mips_dbx_regno
[i
] = i
+ start
;
20075 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
20076 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
20077 mips_dbx_regno
[i
] = i
+ start
;
20079 /* Accumulator debug registers use big-endian ordering. */
20080 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
20081 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
20082 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
20083 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
20084 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
20086 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
20087 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
20090 /* Set up mips_hard_regno_mode_ok. */
20091 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
20092 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
20093 mips_hard_regno_mode_ok
[mode
][regno
]
20094 = mips_hard_regno_mode_ok_p (regno
, (machine_mode
) mode
);
20096 /* Function to allocate machine-dependent function status. */
20097 init_machine_status
= &mips_init_machine_status
;
20099 /* Default to working around R4000 errata only if the processor
20100 was selected explicitly. */
20101 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
20102 && strcmp (mips_arch_info
->name
, "r4000") == 0)
20103 target_flags
|= MASK_FIX_R4000
;
20105 /* Default to working around R4400 errata only if the processor
20106 was selected explicitly. */
20107 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
20108 && strcmp (mips_arch_info
->name
, "r4400") == 0)
20109 target_flags
|= MASK_FIX_R4400
;
20111 /* Default to working around R10000 errata only if the processor
20112 was selected explicitly. */
20113 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
20114 && strcmp (mips_arch_info
->name
, "r10000") == 0)
20115 target_flags
|= MASK_FIX_R10000
;
20117 /* Make sure that branch-likely instructions available when using
20118 -mfix-r10000. The instructions are not available if either:
20120 1. -mno-branch-likely was passed.
20121 2. The selected ISA does not support branch-likely and
20122 the command line does not include -mbranch-likely. */
20123 if (TARGET_FIX_R10000
20124 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
20125 ? !ISA_HAS_BRANCHLIKELY
20126 : !TARGET_BRANCHLIKELY
))
20127 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
20129 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
20131 warning (0, "the %qs architecture does not support the synci "
20132 "instruction", mips_arch_info
->name
);
20133 target_flags
&= ~MASK_SYNCI
;
20136 /* Only optimize PIC indirect calls if they are actually required. */
20137 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
20138 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
20140 /* Save base state of options. */
20141 mips_base_target_flags
= target_flags
;
20142 mips_base_schedule_insns
= flag_schedule_insns
;
20143 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
20144 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
20145 mips_base_align_loops
= align_loops
;
20146 mips_base_align_jumps
= align_jumps
;
20147 mips_base_align_functions
= align_functions
;
20149 /* Now select the ISA mode.
20151 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
20152 later if required. */
20153 mips_set_compression_mode (0);
20155 /* We register a second machine specific reorg pass after delay slot
20156 filling. Registering the pass must be done at start up. It's
20157 convenient to do it here. */
20158 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
20159 struct register_pass_info insert_pass_mips_machine_reorg2
=
20161 new_pass
, /* pass */
20162 "dbr", /* reference_pass_name */
20163 1, /* ref_pass_instance_number */
20164 PASS_POS_INSERT_AFTER
/* po_op */
20166 register_pass (&insert_pass_mips_machine_reorg2
);
20168 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
20169 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
20171 mips_register_frame_header_opt ();
20174 /* Swap the register information for registers I and I + 1, which
20175 currently have the wrong endianness. Note that the registers'
20176 fixedness and call-clobberedness might have been set on the
20180 mips_swap_registers (unsigned int i
)
20185 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
20186 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
20188 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
20189 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
20190 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
20191 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
20197 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
20200 mips_conditional_register_usage (void)
20205 /* These DSP control register fields are global. */
20206 global_regs
[CCDSP_PO_REGNUM
] = 1;
20207 global_regs
[CCDSP_SC_REGNUM
] = 1;
20210 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20211 reg_class_contents
[(int) DSP_ACC_REGS
]);
20214 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20215 reg_class_contents
[(int) MD_REGS
]);
20217 if (!TARGET_HARD_FLOAT
)
20219 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20220 reg_class_contents
[(int) FP_REGS
]);
20221 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20222 reg_class_contents
[(int) ST_REGS
]);
20224 else if (!ISA_HAS_8CC
)
20226 /* We only have a single condition-code register. We implement
20227 this by fixing all the condition-code registers and generating
20228 RTL that refers directly to ST_REG_FIRST. */
20229 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20230 reg_class_contents
[(int) ST_REGS
]);
20232 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
20233 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
20237 /* In MIPS16 mode, we prohibit the unused $s registers, since they
20238 are call-saved, and saving them via a MIPS16 register would
20239 probably waste more time than just reloading the value.
20241 We permit the $t temporary registers when optimizing for speed
20242 but not when optimizing for space because using them results in
20243 code that is larger (but faster) then not using them. We do
20244 allow $24 (t8) because it is used in CMP and CMPI instructions
20245 and $25 (t9) because it is used as the function call address in
20248 fixed_regs
[18] = call_used_regs
[18] = 1;
20249 fixed_regs
[19] = call_used_regs
[19] = 1;
20250 fixed_regs
[20] = call_used_regs
[20] = 1;
20251 fixed_regs
[21] = call_used_regs
[21] = 1;
20252 fixed_regs
[22] = call_used_regs
[22] = 1;
20253 fixed_regs
[23] = call_used_regs
[23] = 1;
20254 fixed_regs
[26] = call_used_regs
[26] = 1;
20255 fixed_regs
[27] = call_used_regs
[27] = 1;
20256 fixed_regs
[30] = call_used_regs
[30] = 1;
20259 fixed_regs
[8] = call_used_regs
[8] = 1;
20260 fixed_regs
[9] = call_used_regs
[9] = 1;
20261 fixed_regs
[10] = call_used_regs
[10] = 1;
20262 fixed_regs
[11] = call_used_regs
[11] = 1;
20263 fixed_regs
[12] = call_used_regs
[12] = 1;
20264 fixed_regs
[13] = call_used_regs
[13] = 1;
20265 fixed_regs
[14] = call_used_regs
[14] = 1;
20266 fixed_regs
[15] = call_used_regs
[15] = 1;
20269 /* Do not allow HI and LO to be treated as register operands.
20270 There are no MTHI or MTLO instructions (or any real need
20271 for them) and one-way registers cannot easily be reloaded. */
20272 AND_COMPL_HARD_REG_SET (operand_reg_set
,
20273 reg_class_contents
[(int) MD_REGS
]);
20275 /* $f20-$f23 are call-clobbered for n64. */
20276 if (mips_abi
== ABI_64
)
20279 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
20280 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
20282 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
20283 for n32 and o32 FP64. */
20284 if (mips_abi
== ABI_N32
20285 || (mips_abi
== ABI_32
20286 && TARGET_FLOAT64
))
20289 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
20290 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
20292 /* Make sure that double-register accumulator values are correctly
20293 ordered for the current endianness. */
20294 if (TARGET_LITTLE_ENDIAN
)
20296 unsigned int regno
;
20298 mips_swap_registers (MD_REG_FIRST
);
20299 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
20300 mips_swap_registers (regno
);
20304 /* Implement EH_USES. */
20307 mips_eh_uses (unsigned int regno
)
20309 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
20311 /* We need to force certain registers to be live in order to handle
20312 PIC long branches correctly. See mips_must_initialize_gp_p for
20314 if (mips_cfun_has_cprestore_slot_p ())
20316 if (regno
== CPRESTORE_SLOT_REGNUM
)
20321 if (cfun
->machine
->global_pointer
== regno
)
20329 /* Implement EPILOGUE_USES. */
20332 mips_epilogue_uses (unsigned int regno
)
20334 /* Say that the epilogue uses the return address register. Note that
20335 in the case of sibcalls, the values "used by the epilogue" are
20336 considered live at the start of the called function. */
20337 if (regno
== RETURN_ADDR_REGNUM
)
20340 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
20341 See the comment above load_call<mode> for details. */
20342 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
20345 /* An interrupt handler must preserve some registers that are
20346 ordinarily call-clobbered. */
20347 if (cfun
->machine
->interrupt_handler_p
20348 && mips_interrupt_extra_call_saved_reg_p (regno
))
20354 /* Return true if INSN needs to be wrapped in ".set noat".
20355 INSN has NOPERANDS operands, stored in OPVEC. */
20358 mips_need_noat_wrapper_p (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
20360 if (recog_memoized (insn
) >= 0)
20362 subrtx_iterator::array_type array
;
20363 for (int i
= 0; i
< noperands
; i
++)
20364 FOR_EACH_SUBRTX (iter
, array
, opvec
[i
], NONCONST
)
20365 if (REG_P (*iter
) && REGNO (*iter
) == AT_REGNUM
)
20371 /* Implement FINAL_PRESCAN_INSN. Mark MIPS16 inline constant pools
20372 as data for the purpose of disassembly. For simplicity embed the
20373 pool's initial label number in the local symbol produced so that
20374 multiple pools within a single function end up marked with unique
20375 symbols. The label number is carried by the `consttable' insn
20376 emitted at the beginning of each pool. */
20379 mips_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
20382 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
20383 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE
)
20384 mips_set_text_contents_type (asm_out_file
, "__pool_",
20385 XINT (XVECEXP (PATTERN (insn
), 0, 0), 0),
20388 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
20389 mips_push_asm_switch (&mips_noat
);
20392 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. Reset text marking to
20393 code after a MIPS16 inline constant pool. Like with the beginning
20394 of a pool table use the pool's initial label number to keep symbols
20395 unique. The label number is carried by the `consttable_end' insn
20396 emitted at the end of each pool. */
20399 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx_insn
*insn
,
20400 rtx
*opvec
, int noperands
)
20402 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
20403 mips_pop_asm_switch (&mips_noat
);
20406 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
20407 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE_END
)
20408 mips_set_text_contents_type (asm_out_file
, "__pend_",
20409 XINT (XVECEXP (PATTERN (insn
), 0, 0), 0),
20413 /* Return the function that is used to expand the <u>mulsidi3 pattern.
20414 EXT_CODE is the code of the extension used. Return NULL if widening
20415 multiplication shouldn't be used. */
20418 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
20422 signed_p
= ext_code
== SIGN_EXTEND
;
20425 /* Don't use widening multiplication with MULT when we have DMUL. Even
20426 with the extension of its input operands DMUL is faster. Note that
20427 the extension is not needed for signed multiplication. In order to
20428 ensure that we always remove the redundant sign-extension in this
20429 case we still expand mulsidi3 for DMUL. */
20430 if (ISA_HAS_R6DMUL
)
20431 return signed_p
? gen_mulsidi3_64bit_r6dmul
: NULL
;
20433 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
20436 ? gen_mulsidi3_64bit_mips16
20437 : gen_umulsidi3_64bit_mips16
);
20438 if (TARGET_FIX_R4000
)
20440 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
20445 return (signed_p
? gen_mulsidi3_32bit_r6
: gen_umulsidi3_32bit_r6
);
20448 ? gen_mulsidi3_32bit_mips16
20449 : gen_umulsidi3_32bit_mips16
);
20450 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
20451 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
20452 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
20456 /* Return true if PATTERN matches the kind of instruction generated by
20457 umips_build_save_restore. SAVE_P is true for store. */
20460 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
20464 HOST_WIDE_INT first_offset
= 0;
20465 rtx first_base
= 0;
20466 unsigned int regmask
= 0;
20468 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
20470 rtx set
, reg
, mem
, this_base
;
20471 HOST_WIDE_INT this_offset
;
20473 /* Check that we have a SET. */
20474 set
= XVECEXP (pattern
, 0, n
);
20475 if (GET_CODE (set
) != SET
)
20478 /* Check that the SET is a load (if restoring) or a store
20480 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
20481 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
20484 /* Check that the address is the sum of base and a possibly-zero
20485 constant offset. Determine if the offset is in range. */
20486 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
20487 if (!REG_P (this_base
))
20492 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
20494 first_base
= this_base
;
20495 first_offset
= this_offset
;
20499 /* Check that the save slots are consecutive. */
20500 if (REGNO (this_base
) != REGNO (first_base
)
20501 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
20505 /* Check that SET's other operand is a register. */
20506 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
20510 regmask
|= 1 << REGNO (reg
);
20513 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
20514 if (regmask
== umips_swm_mask
[i
])
20520 /* Return the assembly instruction for microMIPS LWM or SWM.
20521 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
20524 umips_output_save_restore (bool save_p
, rtx pattern
)
20526 static char buffer
[300];
20529 HOST_WIDE_INT offset
;
20530 rtx base
, mem
, set
, last_set
, last_reg
;
20532 /* Parse the pattern. */
20533 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
20535 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
20537 n
= XVECLEN (pattern
, 0);
20539 set
= XVECEXP (pattern
, 0, 0);
20540 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
20541 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
20543 last_set
= XVECEXP (pattern
, 0, n
- 1);
20544 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
20546 if (REGNO (last_reg
) == 31)
20549 gcc_assert (n
<= 9);
20553 s
+= sprintf (s
, "%s,", reg_names
[16]);
20555 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
20557 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
20560 if (REGNO (last_reg
) == 31)
20561 s
+= sprintf (s
, "%s,", reg_names
[31]);
20563 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
20567 /* Return true if MEM1 and MEM2 use the same base register, and the
20568 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
20569 register into (from) which the contents of MEM1 will be loaded
20570 (stored), depending on the value of LOAD_P.
20571 SWAP_P is true when the 1st and 2nd instructions are swapped. */
20574 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
20575 rtx first_reg
, rtx mem1
, rtx mem2
)
20578 HOST_WIDE_INT offset1
, offset2
;
20580 if (!MEM_P (mem1
) || !MEM_P (mem2
))
20583 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
20584 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
20586 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
20589 /* Avoid invalid load pair instructions. */
20590 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
20593 /* We must avoid this case for anti-dependence.
20596 first_reg is $2, but the base is $3. */
20599 && REGNO (first_reg
) + 1 == REGNO (base1
))
20602 if (offset2
!= offset1
+ 4)
20605 if (!UMIPS_12BIT_OFFSET_P (offset1
))
20612 mips_load_store_bonding_p (rtx
*operands
, machine_mode mode
, bool load_p
)
20614 rtx reg1
, reg2
, mem1
, mem2
, base1
, base2
;
20615 enum reg_class rc1
, rc2
;
20616 HOST_WIDE_INT offset1
, offset2
;
20620 reg1
= operands
[0];
20621 reg2
= operands
[2];
20622 mem1
= operands
[1];
20623 mem2
= operands
[3];
20627 reg1
= operands
[1];
20628 reg2
= operands
[3];
20629 mem1
= operands
[0];
20630 mem2
= operands
[2];
20633 if (mips_address_insns (XEXP (mem1
, 0), mode
, false) == 0
20634 || mips_address_insns (XEXP (mem2
, 0), mode
, false) == 0)
20637 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
20638 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
20640 /* Base regs do not match. */
20641 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
20644 /* Either of the loads is clobbering base register. It is legitimate to bond
20645 loads if second load clobbers base register. However, hardware does not
20646 support such bonding. */
20648 && (REGNO (reg1
) == REGNO (base1
)
20649 || (REGNO (reg2
) == REGNO (base1
))))
20652 /* Loading in same registers. */
20654 && REGNO (reg1
) == REGNO (reg2
))
20657 /* The loads/stores are not of same type. */
20658 rc1
= REGNO_REG_CLASS (REGNO (reg1
));
20659 rc2
= REGNO_REG_CLASS (REGNO (reg2
));
20661 && !reg_class_subset_p (rc1
, rc2
)
20662 && !reg_class_subset_p (rc2
, rc1
))
20665 if (abs (offset1
- offset2
) != GET_MODE_SIZE (mode
))
20671 /* OPERANDS describes the operands to a pair of SETs, in the order
20672 dest1, src1, dest2, src2. Return true if the operands can be used
20673 in an LWP or SWP instruction; LOAD_P says which. */
20676 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
20678 rtx reg1
, reg2
, mem1
, mem2
;
20682 reg1
= operands
[0];
20683 reg2
= operands
[2];
20684 mem1
= operands
[1];
20685 mem2
= operands
[3];
20689 reg1
= operands
[1];
20690 reg2
= operands
[3];
20691 mem1
= operands
[0];
20692 mem2
= operands
[2];
20695 if (REGNO (reg2
) == REGNO (reg1
) + 1)
20696 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
20698 if (REGNO (reg1
) == REGNO (reg2
) + 1)
20699 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
20704 /* Return the assembly instruction for a microMIPS LWP or SWP in which
20705 the first register is REG and the first memory slot is MEM.
20706 LOAD_P is true for LWP. */
20709 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
20711 rtx ops
[] = {reg
, mem
};
20714 output_asm_insn ("lwp\t%0,%1", ops
);
20716 output_asm_insn ("swp\t%0,%1", ops
);
20719 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
20720 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
20723 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
20725 rtx reg1
, reg2
, mem1
, mem2
;
20728 reg1
= operands
[0];
20729 reg2
= operands
[2];
20730 mem1
= operands
[1];
20731 mem2
= operands
[3];
20735 reg1
= operands
[1];
20736 reg2
= operands
[3];
20737 mem1
= operands
[0];
20738 mem2
= operands
[2];
20741 if (REGNO (reg2
) == REGNO (reg1
) + 1)
20743 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
20747 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
20748 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
20751 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
20754 umips_movep_target_p (rtx reg1
, rtx reg2
)
20756 int regno1
, regno2
, pair
;
20758 static const int match
[8] = {
20759 0x00000060, /* 5, 6 */
20760 0x000000a0, /* 5, 7 */
20761 0x000000c0, /* 6, 7 */
20762 0x00200010, /* 4, 21 */
20763 0x00400010, /* 4, 22 */
20764 0x00000030, /* 4, 5 */
20765 0x00000050, /* 4, 6 */
20766 0x00000090 /* 4, 7 */
20769 if (!REG_P (reg1
) || !REG_P (reg2
))
20772 regno1
= REGNO (reg1
);
20773 regno2
= REGNO (reg2
);
20775 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
20778 pair
= (1 << regno1
) | (1 << regno2
);
20780 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
20781 if (pair
== match
[i
])
20787 /* Return the size in bytes of the trampoline code, padded to
20788 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
20789 function address immediately follow. */
20792 mips_trampoline_code_size (void)
20794 if (TARGET_USE_PIC_FN_ADDR_REG
)
20796 else if (ptr_mode
== DImode
)
20798 else if (ISA_HAS_LOAD_DELAY
)
20804 /* Implement TARGET_TRAMPOLINE_INIT. */
20807 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
20809 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
20812 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
20814 /* Work out the offsets of the pointers from the start of the
20815 trampoline code. */
20816 end_addr_offset
= mips_trampoline_code_size ();
20817 static_chain_offset
= end_addr_offset
;
20818 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
20820 /* Get pointers to the beginning and end of the code block. */
20821 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
20822 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
20824 #define OP(X) gen_int_mode (X, SImode)
20826 /* Build up the code in TRAMPOLINE. */
20828 if (TARGET_USE_PIC_FN_ADDR_REG
)
20830 /* $25 contains the address of the trampoline. Emit code of the form:
20832 l[wd] $1, target_function_offset($25)
20833 l[wd] $static_chain, static_chain_offset($25)
20836 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
20837 target_function_offset
,
20838 PIC_FUNCTION_ADDR_REGNUM
));
20839 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
20840 static_chain_offset
,
20841 PIC_FUNCTION_ADDR_REGNUM
));
20842 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
20843 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
20845 else if (ptr_mode
== DImode
)
20847 /* It's too cumbersome to create the full 64-bit address, so let's
20853 1: l[wd] $25, target_function_offset - 12($31)
20854 l[wd] $static_chain, static_chain_offset - 12($31)
20858 where 12 is the offset of "1:" from the start of the code block. */
20859 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
20860 trampoline
[i
++] = OP (MIPS_BAL (1));
20861 trampoline
[i
++] = OP (MIPS_NOP
);
20862 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
20863 target_function_offset
- 12,
20864 RETURN_ADDR_REGNUM
));
20865 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
20866 static_chain_offset
- 12,
20867 RETURN_ADDR_REGNUM
));
20868 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
20869 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
20873 /* If the target has load delays, emit:
20875 lui $1, %hi(end_addr)
20876 lw $25, %lo(end_addr + ...)($1)
20877 lw $static_chain, %lo(end_addr + ...)($1)
20883 lui $1, %hi(end_addr)
20884 lw $25, %lo(end_addr + ...)($1)
20886 lw $static_chain, %lo(end_addr + ...)($1). */
20888 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
20889 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
20890 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
20891 NULL
, false, OPTAB_WIDEN
);
20892 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
20893 NULL
, false, OPTAB_WIDEN
);
20894 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
20896 /* Emit the LUI. */
20897 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
20898 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
20899 NULL
, false, OPTAB_WIDEN
);
20901 /* Emit the load of the target function. */
20902 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
20903 target_function_offset
- end_addr_offset
,
20905 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
20906 NULL
, false, OPTAB_WIDEN
);
20908 /* Emit the JR here, if we can. */
20909 if (!ISA_HAS_LOAD_DELAY
)
20910 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
20912 /* Emit the load of the static chain register. */
20913 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
20914 static_chain_offset
- end_addr_offset
,
20916 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
20917 NULL
, false, OPTAB_WIDEN
);
20919 /* Emit the JR, if we couldn't above. */
20920 if (ISA_HAS_LOAD_DELAY
)
20922 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
20923 trampoline
[i
++] = OP (MIPS_NOP
);
20929 /* If we are using compact branches we don't have delay slots so
20930 place the instruction that was in the delay slot before the JRC
20933 if (TARGET_CB_ALWAYS
)
20936 temp
= trampoline
[i
-2];
20937 trampoline
[i
-2] = trampoline
[i
-1];
20938 trampoline
[i
-1] = temp
;
20941 /* Copy the trampoline code. Leave any padding uninitialized. */
20942 for (j
= 0; j
< i
; j
++)
20944 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
20945 mips_emit_move (mem
, trampoline
[j
]);
20948 /* Set up the static chain pointer field. */
20949 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
20950 mips_emit_move (mem
, chain_value
);
20952 /* Set up the target function field. */
20953 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
20954 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
20956 /* Flush the code part of the trampoline. */
20957 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
20958 emit_insn (gen_clear_cache (addr
, end_addr
));
20961 /* Implement FUNCTION_PROFILER. */
20963 void mips_function_profiler (FILE *file
)
20966 sorry ("mips16 function profiling");
20967 if (TARGET_LONG_CALLS
)
20969 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
20970 if (Pmode
== DImode
)
20971 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
20973 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
20975 mips_push_asm_switch (&mips_noat
);
20976 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
20977 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
20978 /* _mcount treats $2 as the static chain register. */
20979 if (cfun
->static_chain_decl
!= NULL
)
20980 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
20981 reg_names
[STATIC_CHAIN_REGNUM
]);
20982 if (TARGET_MCOUNT_RA_ADDRESS
)
20984 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
20985 ra save location. */
20986 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
20987 /* ra not saved, pass zero. */
20988 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
20990 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
20991 Pmode
== DImode
? "dla" : "la", reg_names
[12],
20992 cfun
->machine
->frame
.ra_fp_offset
,
20993 reg_names
[STACK_POINTER_REGNUM
]);
20995 if (!TARGET_NEWABI
)
20997 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
20998 TARGET_64BIT
? "dsubu" : "subu",
20999 reg_names
[STACK_POINTER_REGNUM
],
21000 reg_names
[STACK_POINTER_REGNUM
],
21001 Pmode
== DImode
? 16 : 8);
21003 if (TARGET_LONG_CALLS
)
21004 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
21006 fprintf (file
, "\tjal\t_mcount\n");
21007 mips_pop_asm_switch (&mips_noat
);
21008 /* _mcount treats $2 as the static chain register. */
21009 if (cfun
->static_chain_decl
!= NULL
)
21010 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
21014 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
21015 behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
21016 when TARGET_LOONGSON_VECTORS is true. */
21018 static unsigned HOST_WIDE_INT
21019 mips_shift_truncation_mask (machine_mode mode
)
21021 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
21024 return GET_MODE_BITSIZE (mode
) - 1;
21027 /* Implement TARGET_PREPARE_PCH_SAVE. */
21030 mips_prepare_pch_save (void)
21032 /* We are called in a context where the current compression vs.
21033 non-compression setting should be irrelevant. The question then is:
21034 which setting makes most sense at load time?
21036 The PCH is loaded before the first token is read. We should never have
21037 switched into a compression mode by that point, and thus should not have
21038 populated mips16_globals or micromips_globals. Nor can we load the
21039 entire contents of mips16_globals or micromips_globals from the PCH file,
21040 because they contain a combination of GGC and non-GGC data.
21042 There is therefore no point in trying save the GGC part of
21043 mips16_globals/micromips_globals to the PCH file, or to preserve a
21044 compression setting across the PCH save and load. The loading compiler
21045 would not have access to the non-GGC parts of mips16_globals or
21046 micromips_globals (either from the PCH file, or from a copy that the
21047 loading compiler generated itself) and would have to call target_reinit
21050 It therefore seems best to switch back to non-MIPS16 mode and
21051 non-microMIPS mode to save time, and to ensure that mips16_globals and
21052 micromips_globals remain null after a PCH load. */
21053 mips_set_compression_mode (0);
21054 mips16_globals
= 0;
21055 micromips_globals
= 0;
21058 /* Generate or test for an insn that supports a constant permutation. */
21060 #define MAX_VECT_LEN 16
21062 struct expand_vec_perm_d
21064 rtx target
, op0
, op1
;
21065 unsigned char perm
[MAX_VECT_LEN
];
21066 machine_mode vmode
;
21067 unsigned char nelt
;
21072 /* Construct (set target (vec_select op0 (parallel perm))) and
21073 return true if that's a valid instruction in the active ISA. */
21076 mips_expand_vselect (rtx target
, rtx op0
,
21077 const unsigned char *perm
, unsigned nelt
)
21079 rtx rperm
[MAX_VECT_LEN
], x
;
21083 for (i
= 0; i
< nelt
; ++i
)
21084 rperm
[i
] = GEN_INT (perm
[i
]);
21086 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
21087 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
21088 x
= gen_rtx_SET (target
, x
);
21090 insn
= emit_insn (x
);
21091 if (recog_memoized (insn
) < 0)
21093 remove_insn (insn
);
21099 /* Similar, but generate a vec_concat from op0 and op1 as well. */
21102 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
21103 const unsigned char *perm
, unsigned nelt
)
21105 machine_mode v2mode
;
21108 if (!GET_MODE_2XWIDER_MODE (GET_MODE (op0
)).exists (&v2mode
))
21110 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
21111 return mips_expand_vselect (target
, x
, perm
, nelt
);
21114 /* Recognize patterns for even-odd extraction. */
21117 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
21119 unsigned i
, odd
, nelt
= d
->nelt
;
21120 rtx t0
, t1
, t2
, t3
;
21122 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
21124 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
21131 for (i
= 1; i
< nelt
; ++i
)
21132 if (d
->perm
[i
] != i
* 2 + odd
)
21138 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
21139 t0
= gen_reg_rtx (d
->vmode
);
21140 t1
= gen_reg_rtx (d
->vmode
);
21144 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
21145 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
21147 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
21149 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
21153 t2
= gen_reg_rtx (d
->vmode
);
21154 t3
= gen_reg_rtx (d
->vmode
);
21155 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
21156 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
21157 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
21158 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
21160 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
21162 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
21166 gcc_unreachable ();
21171 /* Recognize patterns for the Loongson PSHUFH instruction. */
21174 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
21179 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
21181 if (d
->vmode
!= V4HImode
)
21186 /* Convert the selector into the packed 8-bit form for pshufh. */
21187 /* Recall that loongson is little-endian only. No big-endian
21188 adjustment required. */
21189 for (i
= mask
= 0; i
< 4; i
++)
21190 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
21191 rmask
= force_reg (SImode
, GEN_INT (mask
));
21193 if (d
->one_vector_p
)
21194 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
21197 rtx t0
, t1
, x
, merge
, rmerge
[4];
21199 t0
= gen_reg_rtx (V4HImode
);
21200 t1
= gen_reg_rtx (V4HImode
);
21201 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
21202 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
21204 for (i
= 0; i
< 4; ++i
)
21205 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
21206 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
21207 merge
= force_reg (V4HImode
, merge
);
21209 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
21210 emit_insn (gen_rtx_SET (t1
, x
));
21212 x
= gen_rtx_NOT (V4HImode
, merge
);
21213 x
= gen_rtx_AND (V4HImode
, x
, t0
);
21214 emit_insn (gen_rtx_SET (t0
, x
));
21216 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
21217 emit_insn (gen_rtx_SET (d
->target
, x
));
21223 /* Recognize broadcast patterns for the Loongson. */
21226 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
21231 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
21233 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
21234 if (d
->vmode
!= V8QImode
)
21236 if (!d
->one_vector_p
)
21240 for (i
= 1; i
< 8; ++i
)
21241 if (d
->perm
[i
] != elt
)
21247 /* With one interleave we put two of the desired element adjacent. */
21248 t0
= gen_reg_rtx (V8QImode
);
21250 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
21252 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
21254 /* Shuffle that one HImode element into all locations. */
21257 t1
= gen_reg_rtx (V4HImode
);
21258 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
21259 force_reg (SImode
, GEN_INT (elt
))));
21261 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
21265 /* Construct (set target (vec_select op0 (parallel selector))) and
21266 return true if that's a valid instruction in the active ISA. */
21269 mips_expand_msa_shuffle (struct expand_vec_perm_d
*d
)
21271 rtx x
, elts
[MAX_VECT_LEN
];
21279 for (i
= 0; i
< d
->nelt
; i
++)
21280 elts
[i
] = GEN_INT (d
->perm
[i
]);
21282 v
= gen_rtvec_v (d
->nelt
, elts
);
21283 x
= gen_rtx_PARALLEL (VOIDmode
, v
);
21285 if (!mips_const_vector_shuffle_set_p (x
, d
->vmode
))
21288 x
= gen_rtx_VEC_SELECT (d
->vmode
, d
->op0
, x
);
21289 x
= gen_rtx_SET (d
->target
, x
);
21291 insn
= emit_insn (x
);
21292 if (recog_memoized (insn
) < 0)
21294 remove_insn (insn
);
21301 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
21303 unsigned int i
, nelt
= d
->nelt
;
21304 unsigned char perm2
[MAX_VECT_LEN
];
21306 if (d
->one_vector_p
)
21308 /* Try interleave with alternating operands. */
21309 memcpy (perm2
, d
->perm
, sizeof(perm2
));
21310 for (i
= 1; i
< nelt
; i
+= 2)
21312 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
21317 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
21321 /* Try again with swapped operands. */
21322 for (i
= 0; i
< nelt
; ++i
)
21323 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
21324 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
21328 if (mips_expand_vpc_loongson_even_odd (d
))
21330 if (mips_expand_vpc_loongson_pshufh (d
))
21332 if (mips_expand_vpc_loongson_bcast (d
))
21334 if (mips_expand_msa_shuffle (d
))
21339 /* Expand a vec_perm_const pattern. */
21342 mips_expand_vec_perm_const (rtx operands
[4])
21344 struct expand_vec_perm_d d
;
21345 int i
, nelt
, which
;
21346 unsigned char orig_perm
[MAX_VECT_LEN
];
21350 d
.target
= operands
[0];
21351 d
.op0
= operands
[1];
21352 d
.op1
= operands
[2];
21355 d
.vmode
= GET_MODE (d
.target
);
21356 gcc_assert (VECTOR_MODE_P (d
.vmode
));
21357 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
21358 d
.testing_p
= false;
21360 /* This is overly conservative, but ensures we don't get an
21361 uninitialized warning on ORIG_PERM. */
21362 memset (orig_perm
, 0, MAX_VECT_LEN
);
21363 for (i
= which
= 0; i
< nelt
; ++i
)
21365 rtx e
= XVECEXP (sel
, 0, i
);
21366 int ei
= INTVAL (e
) & (2 * nelt
- 1);
21367 which
|= (ei
< nelt
? 1 : 2);
21370 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
21378 d
.one_vector_p
= false;
21379 if (!rtx_equal_p (d
.op0
, d
.op1
))
21384 for (i
= 0; i
< nelt
; ++i
)
21385 d
.perm
[i
] &= nelt
- 1;
21387 d
.one_vector_p
= true;
21392 d
.one_vector_p
= true;
21396 ok
= mips_expand_vec_perm_const_1 (&d
);
21398 /* If we were given a two-vector permutation which just happened to
21399 have both input vectors equal, we folded this into a one-vector
21400 permutation. There are several loongson patterns that are matched
21401 via direct vec_select+vec_concat expansion, but we do not have
21402 support in mips_expand_vec_perm_const_1 to guess the adjustment
21403 that should be made for a single operand. Just try again with
21404 the original permutation. */
21405 if (!ok
&& which
== 3)
21407 d
.op0
= operands
[1];
21408 d
.op1
= operands
[2];
21409 d
.one_vector_p
= false;
21410 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
21411 ok
= mips_expand_vec_perm_const_1 (&d
);
21417 /* Implement TARGET_SCHED_REASSOCIATION_WIDTH. */
21420 mips_sched_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
21423 if (MSA_SUPPORTED_MODE_P (mode
))
21428 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
21431 mips_vectorize_vec_perm_const_ok (machine_mode vmode
,
21432 const unsigned char *sel
)
21434 struct expand_vec_perm_d d
;
21435 unsigned int i
, nelt
, which
;
21439 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
21440 d
.testing_p
= true;
21441 memcpy (d
.perm
, sel
, nelt
);
21443 /* Categorize the set of elements in the selector. */
21444 for (i
= which
= 0; i
< nelt
; ++i
)
21446 unsigned char e
= d
.perm
[i
];
21447 gcc_assert (e
< 2 * nelt
);
21448 which
|= (e
< nelt
? 1 : 2);
21451 /* For all elements from second vector, fold the elements to first. */
21453 for (i
= 0; i
< nelt
; ++i
)
21456 /* Check whether the mask can be applied to the vector type. */
21457 d
.one_vector_p
= (which
!= 3);
21459 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
21460 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
21461 if (!d
.one_vector_p
)
21462 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
21465 ret
= mips_expand_vec_perm_const_1 (&d
);
21471 /* Expand an integral vector unpack operation. */
21474 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
21476 machine_mode imode
= GET_MODE (operands
[1]);
21477 rtx (*unpack
) (rtx
, rtx
, rtx
);
21478 rtx (*cmpFunc
) (rtx
, rtx
, rtx
);
21479 rtx tmp
, dest
, zero
;
21486 if (BYTES_BIG_ENDIAN
!= high_p
)
21487 unpack
= gen_msa_ilvl_w
;
21489 unpack
= gen_msa_ilvr_w
;
21491 cmpFunc
= gen_msa_clt_s_w
;
21495 if (BYTES_BIG_ENDIAN
!= high_p
)
21496 unpack
= gen_msa_ilvl_h
;
21498 unpack
= gen_msa_ilvr_h
;
21500 cmpFunc
= gen_msa_clt_s_h
;
21504 if (BYTES_BIG_ENDIAN
!= high_p
)
21505 unpack
= gen_msa_ilvl_b
;
21507 unpack
= gen_msa_ilvr_b
;
21509 cmpFunc
= gen_msa_clt_s_b
;
21513 gcc_unreachable ();
21519 /* Extract sign extention for each element comparing each element
21520 with immediate zero. */
21521 tmp
= gen_reg_rtx (imode
);
21522 emit_insn (cmpFunc (tmp
, operands
[1], CONST0_RTX (imode
)));
21525 tmp
= force_reg (imode
, CONST0_RTX (imode
));
21527 dest
= gen_reg_rtx (imode
);
21529 emit_insn (unpack (dest
, operands
[1], tmp
));
21530 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
21538 unpack
= gen_loongson_punpckhbh
;
21540 unpack
= gen_loongson_punpcklbh
;
21541 cmpFunc
= gen_loongson_pcmpgtb
;
21545 unpack
= gen_loongson_punpckhhw
;
21547 unpack
= gen_loongson_punpcklhw
;
21548 cmpFunc
= gen_loongson_pcmpgth
;
21551 gcc_unreachable ();
21554 zero
= force_reg (imode
, CONST0_RTX (imode
));
21559 tmp
= gen_reg_rtx (imode
);
21560 emit_insn (cmpFunc (tmp
, zero
, operands
[1]));
21563 dest
= gen_reg_rtx (imode
);
21564 emit_insn (unpack (dest
, operands
[1], tmp
));
21566 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
21569 /* Construct and return PARALLEL RTX with CONST_INTs for HIGH (high_p == TRUE)
21570 or LOW (high_p == FALSE) half of a vector for mode MODE. */
21573 mips_msa_vec_parallel_const_half (machine_mode mode
, bool high_p
)
21575 int nunits
= GET_MODE_NUNITS (mode
);
21576 rtvec v
= rtvec_alloc (nunits
/ 2);
21580 if (BYTES_BIG_ENDIAN
)
21581 base
= high_p
? 0 : nunits
/ 2;
21583 base
= high_p
? nunits
/ 2 : 0;
21585 for (i
= 0; i
< nunits
/ 2; i
++)
21586 RTVEC_ELT (v
, i
) = GEN_INT (base
+ i
);
21588 return gen_rtx_PARALLEL (VOIDmode
, v
);
21591 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
21594 mips_constant_elt_p (rtx x
)
21596 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
21599 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
21602 mips_expand_vi_broadcast (machine_mode vmode
, rtx target
, rtx elt
)
21604 struct expand_vec_perm_d d
;
21608 if (elt
!= const0_rtx
)
21609 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
21611 elt
= gen_lowpart (DImode
, elt
);
21613 t1
= gen_reg_rtx (vmode
);
21617 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
21620 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
21623 gcc_unreachable ();
21626 memset (&d
, 0, sizeof (d
));
21631 d
.nelt
= GET_MODE_NUNITS (vmode
);
21632 d
.one_vector_p
= true;
21634 ok
= mips_expand_vec_perm_const_1 (&d
);
21638 /* Return a const_int vector of VAL with mode MODE. */
21641 mips_gen_const_int_vector (machine_mode mode
, HOST_WIDE_INT val
)
21643 int nunits
= GET_MODE_NUNITS (mode
);
21644 rtvec v
= rtvec_alloc (nunits
);
21647 for (i
= 0; i
< nunits
; i
++)
21648 RTVEC_ELT (v
, i
) = gen_int_mode (val
, GET_MODE_INNER (mode
));
21650 return gen_rtx_CONST_VECTOR (mode
, v
);
21653 /* Return a vector of repeated 4-element sets generated from
21654 immediate VAL in mode MODE. */
21657 mips_gen_const_int_vector_shuffle (machine_mode mode
, int val
)
21659 int nunits
= GET_MODE_NUNITS (mode
);
21660 int nsets
= nunits
/ 4;
21661 rtx elts
[MAX_VECT_LEN
];
21665 /* Generate a const_int vector replicating the same 4-element set
21666 from an immediate. */
21667 for (j
= 0; j
< nsets
; j
++, set
= 4 * j
)
21668 for (i
= 0; i
< 4; i
++)
21669 elts
[set
+ i
] = GEN_INT (set
+ ((val
>> (2 * i
)) & 0x3));
21671 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nunits
, elts
));
21674 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
21675 elements of VALS with zeros, copy the constant vector to TARGET. */
21678 mips_expand_vi_constant (machine_mode vmode
, unsigned nelt
,
21679 rtx target
, rtx vals
)
21681 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
21684 for (i
= 0; i
< nelt
; ++i
)
21686 rtx elem
= RTVEC_ELT (vec
, i
);
21687 if (!mips_constant_elt_p (elem
))
21688 RTVEC_ELT (vec
, i
) = CONST0_RTX (GET_MODE (elem
));
21691 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
21695 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
21698 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
21700 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
21702 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
21703 GEN_INT (one_var
)));
21706 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
21709 mips_expand_vi_general (machine_mode vmode
, machine_mode imode
,
21710 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
21712 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
21713 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
21716 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
21718 for (i
= 0; i
< nelt
; ++i
)
21720 rtx x
= XVECEXP (vals
, 0, i
);
21721 if (!mips_constant_elt_p (x
))
21722 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
21725 emit_move_insn (target
, mem
);
21728 /* Expand a vector initialization. */
21731 mips_expand_vector_init (rtx target
, rtx vals
)
21733 machine_mode vmode
= GET_MODE (target
);
21734 machine_mode imode
= GET_MODE_INNER (vmode
);
21735 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
21736 unsigned nvar
= 0, one_var
= -1u;
21737 bool all_same
= true;
21740 for (i
= 0; i
< nelt
; ++i
)
21742 x
= XVECEXP (vals
, 0, i
);
21743 if (!mips_constant_elt_p (x
))
21744 nvar
++, one_var
= i
;
21745 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
21753 rtx same
= XVECEXP (vals
, 0, 0);
21756 if (CONST_INT_P (same
) && nvar
== 0
21757 && mips_signed_immediate_p (INTVAL (same
), 10, 0))
21765 temp
= gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0));
21766 emit_move_insn (target
, temp
);
21770 gcc_unreachable ();
21773 temp
= gen_reg_rtx (imode
);
21774 if (imode
== GET_MODE (same
))
21776 else if (GET_MODE_SIZE (imode
) >= UNITS_PER_WORD
)
21777 temp2
= simplify_gen_subreg (imode
, same
, GET_MODE (same
), 0);
21779 temp2
= lowpart_subreg (imode
, same
, GET_MODE (same
));
21780 emit_move_insn (temp
, temp2
);
21788 mips_emit_move (target
, gen_rtx_VEC_DUPLICATE (vmode
, temp
));
21792 emit_insn (gen_msa_splati_w_f_scalar (target
, temp
));
21796 emit_insn (gen_msa_splati_d_f_scalar (target
, temp
));
21800 gcc_unreachable ();
21805 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
21807 for (i
= 0; i
< nelt
; ++i
)
21808 RTVEC_ELT (vec
, i
) = CONST0_RTX (imode
);
21810 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
21812 for (i
= 0; i
< nelt
; ++i
)
21814 rtx temp
= gen_reg_rtx (imode
);
21815 emit_move_insn (temp
, XVECEXP (vals
, 0, i
));
21819 emit_insn (gen_vec_setv16qi (target
, temp
, GEN_INT (i
)));
21823 emit_insn (gen_vec_setv8hi (target
, temp
, GEN_INT (i
)));
21827 emit_insn (gen_vec_setv4si (target
, temp
, GEN_INT (i
)));
21831 emit_insn (gen_vec_setv2di (target
, temp
, GEN_INT (i
)));
21835 emit_insn (gen_vec_setv4sf (target
, temp
, GEN_INT (i
)));
21839 emit_insn (gen_vec_setv2df (target
, temp
, GEN_INT (i
)));
21843 gcc_unreachable ();
21850 /* Load constants from the pool, or whatever's handy. */
21853 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
21857 /* For two-part initialization, always use CONCAT. */
21860 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
21861 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
21862 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
21863 emit_insn (gen_rtx_SET (target
, x
));
21867 /* Loongson is the only cpu with vectors with more elements. */
21868 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
21870 /* If all values are identical, broadcast the value. */
21873 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
21877 /* If we've only got one non-variable V4HImode, use PINSRH. */
21878 if (nvar
== 1 && vmode
== V4HImode
)
21880 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
21884 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
21887 /* Expand a vector reduction. */
21890 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
21892 machine_mode vmode
= GET_MODE (in
);
21893 unsigned char perm2
[2];
21894 rtx last
, next
, fold
, x
;
21898 fold
= gen_reg_rtx (vmode
);
21902 /* Use PUL/PLU to produce { L, H } op { H, L }.
21903 By reversing the pair order, rather than a pure interleave high,
21904 we avoid erroneous exceptional conditions that we might otherwise
21905 produce from the computation of H op H. */
21908 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
21913 /* Use interleave to produce { H, L } op { H, H }. */
21914 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
21918 /* Perform the first reduction with interleave,
21919 and subsequent reductions with shifts. */
21920 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
21922 next
= gen_reg_rtx (vmode
);
21923 emit_insn (gen (next
, last
, fold
));
21926 fold
= gen_reg_rtx (vmode
);
21927 x
= force_reg (SImode
, GEN_INT (16));
21928 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
21932 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
21934 next
= gen_reg_rtx (vmode
);
21935 emit_insn (gen (next
, last
, fold
));
21938 fold
= gen_reg_rtx (vmode
);
21939 x
= force_reg (SImode
, GEN_INT (16));
21940 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
21942 next
= gen_reg_rtx (vmode
);
21943 emit_insn (gen (next
, last
, fold
));
21946 fold
= gen_reg_rtx (vmode
);
21947 x
= force_reg (SImode
, GEN_INT (8));
21948 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
21952 gcc_unreachable ();
21955 emit_insn (gen (target
, last
, fold
));
21958 /* Expand a vector minimum/maximum. */
21961 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
21962 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
21964 machine_mode vmode
= GET_MODE (target
);
21967 tc
= gen_reg_rtx (vmode
);
21968 t0
= gen_reg_rtx (vmode
);
21969 t1
= gen_reg_rtx (vmode
);
21972 emit_insn (cmp (tc
, op0
, op1
));
21974 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
21975 emit_insn (gen_rtx_SET (t0
, x
));
21977 x
= gen_rtx_NOT (vmode
, tc
);
21978 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
21979 emit_insn (gen_rtx_SET (t1
, x
));
21981 x
= gen_rtx_IOR (vmode
, t0
, t1
);
21982 emit_insn (gen_rtx_SET (target
, x
));
21985 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
21988 mips_hard_regno_caller_save_mode (unsigned int regno
,
21989 unsigned int nregs
,
21992 /* For performance, avoid saving/restoring upper parts of a register
21993 by returning MODE as save mode when the mode is known. */
21994 if (mode
== VOIDmode
)
21995 return choose_hard_reg_mode (regno
, nregs
, false);
22000 /* Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and
22001 store the result -1 or 0 in DEST. */
22004 mips_expand_msa_cmp (rtx dest
, enum rtx_code cond
, rtx op0
, rtx op1
)
22006 machine_mode cmp_mode
= GET_MODE (op0
);
22008 bool negate
= false;
22019 cond
= reverse_condition (cond
);
22032 std::swap (op0
, op1
);
22033 cond
= swap_condition (cond
);
22036 gcc_unreachable ();
22038 mips_emit_binary (cond
, dest
, op0
, op1
);
22040 emit_move_insn (dest
, gen_rtx_NOT (GET_MODE (dest
), dest
));
22055 case LTGT
: cond
= NE
; break;
22056 case UNGE
: cond
= UNLE
; std::swap (op0
, op1
); break;
22057 case UNGT
: cond
= UNLT
; std::swap (op0
, op1
); break;
22058 case LE
: unspec
= UNSPEC_MSA_FSLE
; break;
22059 case LT
: unspec
= UNSPEC_MSA_FSLT
; break;
22060 case GE
: unspec
= UNSPEC_MSA_FSLE
; std::swap (op0
, op1
); break;
22061 case GT
: unspec
= UNSPEC_MSA_FSLT
; std::swap (op0
, op1
); break;
22063 gcc_unreachable ();
22066 mips_emit_binary (cond
, dest
, op0
, op1
);
22069 rtx x
= gen_rtx_UNSPEC (GET_MODE (dest
),
22070 gen_rtvec (2, op0
, op1
), unspec
);
22071 emit_insn (gen_rtx_SET (dest
, x
));
22076 gcc_unreachable ();
22081 /* Expand VEC_COND_EXPR, where:
22082 MODE is mode of the result
22083 VIMODE equivalent integer mode
22084 OPERANDS operands of VEC_COND_EXPR. */
22087 mips_expand_vec_cond_expr (machine_mode mode
, machine_mode vimode
,
22090 rtx cond
= operands
[3];
22091 rtx cmp_op0
= operands
[4];
22092 rtx cmp_op1
= operands
[5];
22093 rtx cmp_res
= gen_reg_rtx (vimode
);
22095 mips_expand_msa_cmp (cmp_res
, GET_CODE (cond
), cmp_op0
, cmp_op1
);
22097 /* We handle the following cases:
22098 1) r = a CMP b ? -1 : 0
22099 2) r = a CMP b ? -1 : v
22100 3) r = a CMP b ? v : 0
22101 4) r = a CMP b ? v1 : v2 */
22103 /* Case (1) above. We only move the results. */
22104 if (operands
[1] == CONSTM1_RTX (vimode
)
22105 && operands
[2] == CONST0_RTX (vimode
))
22106 emit_move_insn (operands
[0], cmp_res
);
22109 rtx src1
= gen_reg_rtx (vimode
);
22110 rtx src2
= gen_reg_rtx (vimode
);
22111 rtx mask
= gen_reg_rtx (vimode
);
22114 /* Move the vector result to use it as a mask. */
22115 emit_move_insn (mask
, cmp_res
);
22117 if (register_operand (operands
[1], mode
))
22119 rtx xop1
= operands
[1];
22120 if (mode
!= vimode
)
22122 xop1
= gen_reg_rtx (vimode
);
22123 emit_move_insn (xop1
, gen_rtx_SUBREG (vimode
, operands
[1], 0));
22125 emit_move_insn (src1
, xop1
);
22129 gcc_assert (operands
[1] == CONSTM1_RTX (vimode
));
22130 /* Case (2) if the below doesn't move the mask to src2. */
22131 emit_move_insn (src1
, mask
);
22134 if (register_operand (operands
[2], mode
))
22136 rtx xop2
= operands
[2];
22137 if (mode
!= vimode
)
22139 xop2
= gen_reg_rtx (vimode
);
22140 emit_move_insn (xop2
, gen_rtx_SUBREG (vimode
, operands
[2], 0));
22142 emit_move_insn (src2
, xop2
);
22146 gcc_assert (operands
[2] == CONST0_RTX (mode
));
22147 /* Case (3) if the above didn't move the mask to src1. */
22148 emit_move_insn (src2
, mask
);
22151 /* We deal with case (4) if the mask wasn't moved to either src1 or src2.
22152 In any case, we eventually do vector mask-based copy. */
22153 bsel
= gen_rtx_IOR (vimode
,
22154 gen_rtx_AND (vimode
,
22155 gen_rtx_NOT (vimode
, mask
), src2
),
22156 gen_rtx_AND (vimode
, mask
, src1
));
22157 /* The result is placed back to a register with the mask. */
22158 emit_insn (gen_rtx_SET (mask
, bsel
));
22159 emit_move_insn (operands
[0], gen_rtx_SUBREG (mode
, mask
, 0));
22163 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
22166 mips_case_values_threshold (void)
22168 /* In MIPS16 mode using a larger case threshold generates smaller code. */
22169 if (TARGET_MIPS16
&& optimize_size
)
22172 return default_case_values_threshold ();
22175 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
22178 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
22180 if (!TARGET_HARD_FLOAT_ABI
)
22182 tree exceptions_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22183 tree fcsr_orig_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22184 tree fcsr_mod_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22185 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
22186 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
22187 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
22188 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22189 fcsr_orig_var
, get_fcsr_hold_call
);
22190 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
22191 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
22192 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22193 fcsr_mod_var
, hold_mod_val
);
22194 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
22195 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
22196 hold_assign_orig
, hold_assign_mod
);
22197 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
22198 set_fcsr_hold_call
);
22200 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
22202 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
22203 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22204 exceptions_var
, get_fcsr_update_call
);
22205 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
22206 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
22207 set_fcsr_update_call
);
22208 tree atomic_feraiseexcept
22209 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
22210 tree int_exceptions_var
= fold_convert (integer_type_node
,
22212 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
22213 1, int_exceptions_var
);
22214 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
22215 atomic_feraiseexcept_call
);
22218 /* Implement TARGET_SPILL_CLASS. */
22221 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED
,
22222 machine_mode mode ATTRIBUTE_UNUSED
)
22229 /* Implement TARGET_LRA_P. */
22234 return mips_lra_flag
;
22237 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
22240 mips_ira_change_pseudo_allocno_class (int regno
, reg_class_t allocno_class
,
22241 reg_class_t best_class ATTRIBUTE_UNUSED
)
22243 /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
22244 to memory if an FPR is present in the allocno class. It is rare that
22245 we actually need to place an integer mode value in an FPR so where
22246 possible limit the allocation to GR_REGS. This will slightly pessimize
22247 code that involves integer to/from float conversions as these will have
22248 to reload into FPRs in LRA. Such reloads are sometimes eliminated and
22249 sometimes only partially eliminated. We choose to take this penalty
22250 in order to eliminate usage of FPRs in code that does not use floating
22253 This change has a similar effect to increasing the cost of FPR->GPR
22254 register moves for integer modes so that they are higher than the cost
22255 of memory but changing the allocno class is more reliable.
22257 This is also similar to forbidding integer mode values in FPRs entirely
22258 but this would lead to an inconsistency in the integer to/from float
22259 instructions that say integer mode values must be placed in FPRs. */
22260 if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno
)) && allocno_class
== ALL_REGS
)
22262 return allocno_class
;
22265 /* Implement TARGET_PROMOTE_FUNCTION_MODE */
22267 /* This function is equivalent to default_promote_function_mode_always_promote
22268 except that it returns a promoted mode even if type is NULL_TREE. This is
22269 needed by libcalls which have no type (only a mode) such as fixed conversion
22270 routines that take a signed or unsigned char/short argument and convert it
22271 to a fixed type. */
22273 static machine_mode
22274 mips_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
22276 int *punsignedp ATTRIBUTE_UNUSED
,
22277 const_tree fntype ATTRIBUTE_UNUSED
,
22278 int for_return ATTRIBUTE_UNUSED
)
22282 if (type
!= NULL_TREE
)
22283 return promote_mode (type
, mode
, punsignedp
);
22285 unsignedp
= *punsignedp
;
22286 PROMOTE_MODE (mode
, unsignedp
, type
);
22287 *punsignedp
= unsignedp
;
22291 /* Initialize the GCC target structure. */
22292 #undef TARGET_ASM_ALIGNED_HI_OP
22293 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
22294 #undef TARGET_ASM_ALIGNED_SI_OP
22295 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
22296 #undef TARGET_ASM_ALIGNED_DI_OP
22297 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
22299 #undef TARGET_OPTION_OVERRIDE
22300 #define TARGET_OPTION_OVERRIDE mips_option_override
22302 #undef TARGET_LEGITIMIZE_ADDRESS
22303 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
22305 #undef TARGET_ASM_FUNCTION_PROLOGUE
22306 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
22307 #undef TARGET_ASM_FUNCTION_EPILOGUE
22308 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
22309 #undef TARGET_ASM_SELECT_RTX_SECTION
22310 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
22311 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
22312 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
22314 #undef TARGET_SCHED_INIT
22315 #define TARGET_SCHED_INIT mips_sched_init
22316 #undef TARGET_SCHED_REORDER
22317 #define TARGET_SCHED_REORDER mips_sched_reorder
22318 #undef TARGET_SCHED_REORDER2
22319 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
22320 #undef TARGET_SCHED_VARIABLE_ISSUE
22321 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
22322 #undef TARGET_SCHED_ADJUST_COST
22323 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
22324 #undef TARGET_SCHED_ISSUE_RATE
22325 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
22326 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
22327 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
22328 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
22329 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
22330 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
22331 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
22332 mips_multipass_dfa_lookahead
22333 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
22334 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
22335 mips_small_register_classes_for_mode_p
22337 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
22338 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
22340 #undef TARGET_INSERT_ATTRIBUTES
22341 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
22342 #undef TARGET_MERGE_DECL_ATTRIBUTES
22343 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
22344 #undef TARGET_CAN_INLINE_P
22345 #define TARGET_CAN_INLINE_P mips_can_inline_p
22346 #undef TARGET_SET_CURRENT_FUNCTION
22347 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
22349 #undef TARGET_VALID_POINTER_MODE
22350 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
22351 #undef TARGET_REGISTER_MOVE_COST
22352 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
22353 #undef TARGET_REGISTER_PRIORITY
22354 #define TARGET_REGISTER_PRIORITY mips_register_priority
22355 #undef TARGET_MEMORY_MOVE_COST
22356 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
22357 #undef TARGET_RTX_COSTS
22358 #define TARGET_RTX_COSTS mips_rtx_costs
22359 #undef TARGET_ADDRESS_COST
22360 #define TARGET_ADDRESS_COST mips_address_cost
22362 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
22363 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P mips_no_speculation_in_delay_slots_p
22365 #undef TARGET_IN_SMALL_DATA_P
22366 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
22368 #undef TARGET_MACHINE_DEPENDENT_REORG
22369 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
22371 #undef TARGET_PREFERRED_RELOAD_CLASS
22372 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
22374 #undef TARGET_EXPAND_TO_RTL_HOOK
22375 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
22376 #undef TARGET_ASM_FILE_START
22377 #define TARGET_ASM_FILE_START mips_file_start
22378 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
22379 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
22380 #undef TARGET_ASM_CODE_END
22381 #define TARGET_ASM_CODE_END mips_code_end
22383 #undef TARGET_INIT_LIBFUNCS
22384 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
22386 #undef TARGET_BUILD_BUILTIN_VA_LIST
22387 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
22388 #undef TARGET_EXPAND_BUILTIN_VA_START
22389 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
22390 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
22391 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
22393 #undef TARGET_PROMOTE_FUNCTION_MODE
22394 #define TARGET_PROMOTE_FUNCTION_MODE mips_promote_function_mode
22395 #undef TARGET_FUNCTION_VALUE
22396 #define TARGET_FUNCTION_VALUE mips_function_value
22397 #undef TARGET_LIBCALL_VALUE
22398 #define TARGET_LIBCALL_VALUE mips_libcall_value
22399 #undef TARGET_FUNCTION_VALUE_REGNO_P
22400 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
22401 #undef TARGET_RETURN_IN_MEMORY
22402 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
22403 #undef TARGET_RETURN_IN_MSB
22404 #define TARGET_RETURN_IN_MSB mips_return_in_msb
22406 #undef TARGET_ASM_OUTPUT_MI_THUNK
22407 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
22408 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
22409 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
22411 #undef TARGET_PRINT_OPERAND
22412 #define TARGET_PRINT_OPERAND mips_print_operand
22413 #undef TARGET_PRINT_OPERAND_ADDRESS
22414 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
22415 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
22416 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
22418 #undef TARGET_SETUP_INCOMING_VARARGS
22419 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
22420 #undef TARGET_STRICT_ARGUMENT_NAMING
22421 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
22422 #undef TARGET_MUST_PASS_IN_STACK
22423 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
22424 #undef TARGET_PASS_BY_REFERENCE
22425 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
22426 #undef TARGET_CALLEE_COPIES
22427 #define TARGET_CALLEE_COPIES mips_callee_copies
22428 #undef TARGET_ARG_PARTIAL_BYTES
22429 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
22430 #undef TARGET_FUNCTION_ARG
22431 #define TARGET_FUNCTION_ARG mips_function_arg
22432 #undef TARGET_FUNCTION_ARG_ADVANCE
22433 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
22434 #undef TARGET_FUNCTION_ARG_BOUNDARY
22435 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
22436 #undef TARGET_GET_RAW_RESULT_MODE
22437 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
22438 #undef TARGET_GET_RAW_ARG_MODE
22439 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
22441 #undef TARGET_MODE_REP_EXTENDED
22442 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
22444 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
22445 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
22446 mips_builtin_vectorized_function
22447 #undef TARGET_VECTOR_MODE_SUPPORTED_P
22448 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
22450 #undef TARGET_SCALAR_MODE_SUPPORTED_P
22451 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
22453 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
22454 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
22455 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
22456 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
22457 mips_autovectorize_vector_sizes
22459 #undef TARGET_INIT_BUILTINS
22460 #define TARGET_INIT_BUILTINS mips_init_builtins
22461 #undef TARGET_BUILTIN_DECL
22462 #define TARGET_BUILTIN_DECL mips_builtin_decl
22463 #undef TARGET_EXPAND_BUILTIN
22464 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
22466 #undef TARGET_HAVE_TLS
22467 #define TARGET_HAVE_TLS HAVE_AS_TLS
22469 #undef TARGET_CANNOT_FORCE_CONST_MEM
22470 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
22472 #undef TARGET_LEGITIMATE_CONSTANT_P
22473 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
22475 #undef TARGET_ENCODE_SECTION_INFO
22476 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
22478 #undef TARGET_ATTRIBUTE_TABLE
22479 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
22480 /* All our function attributes are related to how out-of-line copies should
22481 be compiled or called. They don't in themselves prevent inlining. */
22482 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
22483 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
22485 #undef TARGET_EXTRA_LIVE_ON_ENTRY
22486 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
22488 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
22489 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
22490 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
22491 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
22493 #undef TARGET_COMP_TYPE_ATTRIBUTES
22494 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
22496 #ifdef HAVE_AS_DTPRELWORD
22497 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
22498 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
22500 #undef TARGET_DWARF_REGISTER_SPAN
22501 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
22502 #undef TARGET_DWARF_FRAME_REG_MODE
22503 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
22505 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
22506 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
22508 #undef TARGET_LEGITIMATE_ADDRESS_P
22509 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
22511 #undef TARGET_FRAME_POINTER_REQUIRED
22512 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
22514 #undef TARGET_CAN_ELIMINATE
22515 #define TARGET_CAN_ELIMINATE mips_can_eliminate
22517 #undef TARGET_CONDITIONAL_REGISTER_USAGE
22518 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
22520 #undef TARGET_TRAMPOLINE_INIT
22521 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
22523 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
22524 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
22526 #undef TARGET_SHIFT_TRUNCATION_MASK
22527 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
22529 #undef TARGET_PREPARE_PCH_SAVE
22530 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
22532 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
22533 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
22535 #undef TARGET_SCHED_REASSOCIATION_WIDTH
22536 #define TARGET_SCHED_REASSOCIATION_WIDTH mips_sched_reassociation_width
22538 #undef TARGET_CASE_VALUES_THRESHOLD
22539 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
22541 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
22542 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
22544 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
22545 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
22547 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
22548 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
22549 mips_use_by_pieces_infrastructure_p
22551 #undef TARGET_SPILL_CLASS
22552 #define TARGET_SPILL_CLASS mips_spill_class
22553 #undef TARGET_LRA_P
22554 #define TARGET_LRA_P mips_lra_p
22555 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
22556 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
22558 #undef TARGET_HARD_REGNO_SCRATCH_OK
22559 #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
22561 /* The architecture reserves bit 0 for MIPS16 so use bit 1 for descriptors. */
22562 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
22563 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2
22565 struct gcc_target targetm
= TARGET_INITIALIZER
;
22567 #include "gt-mips.h"