1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; I -- An 8-bit constant (0..255).
33 ;; J -- A 12-bit constant (0..4095).
34 ;; K -- A 16-bit constant (-32768..32767).
35 ;; L -- Value appropriate as displacement.
36 ;; (0..4095) for short displacement
37 ;; (-524288..524287) for long displacement
38 ;; M -- Constant integer with a value of 0x7fffffff.
39 ;; N -- Multiple letter constraint followed by 4 parameter letters.
40 ;; 0..9,x: number of the part counting from most to least significant
41 ;; H,Q: mode of the part
42 ;; D,S,H: mode of the containing operand
43 ;; 0,F: value of the other parts (F - all bits set)
45 ;; The constraint matches if the specified part of a constant
46 ;; has a value different from its other parts. If the letter x
47 ;; is specified instead of a part number, the constraint matches
48 ;; if there is any single part with non-default value.
49 ;; Q -- Memory reference without index register and with short displacement.
50 ;; R -- Memory reference with index register and short displacement.
51 ;; S -- Memory reference without index register but with long displacement.
52 ;; T -- Memory reference with index register and long displacement.
53 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
54 ;; Offsettable memory reference of type specified by second letter.
55 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
56 ;; Memory reference of the type specified by second letter that
57 ;; does *not* refer to a literal pool entry.
58 ;; U -- Pointer with short displacement.
59 ;; W -- Pointer with long displacement.
60 ;; Y -- Shift count operand.
62 ;; Special formats used for outputting 390 instructions.
64 ;; %C: print opcode suffix for branch condition.
65 ;; %D: print opcode suffix for inverse branch condition.
66 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
67 ;; %O: print only the displacement of a memory reference.
68 ;; %R: print only the base register of a memory reference.
69 ;; %S: print S-type memory reference (base+displacement).
70 ;; %N: print the second word of a DImode operand.
71 ;; %M: print the second word of a TImode operand.
73 ;; %b: print integer X as if it's an unsigned byte.
74 ;; %x: print integer X as if it's an unsigned word.
75 ;; %h: print integer X as if it's a signed word.
76 ;; %i: print the first nonzero HImode part of X
77 ;; %j: print the first HImode part unequal to 0xffff of X
80 ;; We have a special constraint for pattern matching.
82 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
95 ; GOT/PLT and lt-relative accesses
96 (UNSPEC_LTREL_OFFSET 100)
97 (UNSPEC_LTREL_BASE 101)
105 (UNSPEC_RELOAD_BASE 210)
106 (UNSPEC_MAIN_BASE 211)
111 ; TLS relocation specifiers
116 (UNSPEC_GOTNTPOFF 504)
117 (UNSPEC_INDNTPOFF 505)
120 (UNSPEC_TLSLDM_NTPOFF 511)
121 (UNSPEC_TLS_LOAD 512)
128 ;; UNSPEC_VOLATILE usage
136 (UNSPECV_TPF_PROLOGUE 20)
137 (UNSPECV_TPF_EPILOGUE 21)
141 (UNSPECV_POOL_SECTION 201)
142 (UNSPECV_POOL_ALIGN 202)
143 (UNSPECV_POOL_ENTRY 203)
144 (UNSPECV_MAIN_POOL 300)
156 ; Sibling call register.
158 ; Literal pool base register.
160 ; Return address register.
162 ; Condition code register.
164 ; Thread local storage pointer register.
169 ;; Instruction operand type as used in the Principles of Operation.
170 ;; Used to determine defaults for length and other attribute values.
172 (define_attr "op_type"
173 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
176 ;; Instruction type attribute used for scheduling.
178 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
180 imulhi,imulsi,imuldi,
181 branch,jsr,fsimpdf,fsimpsf,
182 floaddf,floadsf,fstoredf,fstoresf,
183 fmuldf,fmulsf,fdivdf,fdivsf,
184 ftoi,itof,fsqrtdf,fsqrtsf,
186 (cond [(eq_attr "op_type" "NN") (const_string "other")
187 (eq_attr "op_type" "SS") (const_string "cs")]
188 (const_string "integer")))
190 ;; Another attribute used for scheduling purposes:
191 ;; agen: Instruction uses the address generation unit
192 ;; reg: Instruction does not use the agen unit
194 (define_attr "atype" "agen,reg"
195 (cond [(eq_attr "op_type" "E") (const_string "reg")
196 (eq_attr "op_type" "RR") (const_string "reg")
197 (eq_attr "op_type" "RX") (const_string "agen")
198 (eq_attr "op_type" "RI") (const_string "reg")
199 (eq_attr "op_type" "RRE") (const_string "reg")
200 (eq_attr "op_type" "RS") (const_string "agen")
201 (eq_attr "op_type" "RSI") (const_string "agen")
202 (eq_attr "op_type" "S") (const_string "agen")
203 (eq_attr "op_type" "SI") (const_string "agen")
204 (eq_attr "op_type" "SS") (const_string "agen")
205 (eq_attr "op_type" "SSE") (const_string "agen")
206 (eq_attr "op_type" "RXE") (const_string "agen")
207 (eq_attr "op_type" "RSE") (const_string "agen")
208 (eq_attr "op_type" "RIL") (const_string "agen")
209 (eq_attr "op_type" "RXY") (const_string "agen")
210 (eq_attr "op_type" "RSY") (const_string "agen")
211 (eq_attr "op_type" "SIY") (const_string "agen")]
212 (const_string "agen")))
216 (define_attr "length" ""
217 (cond [(eq_attr "op_type" "E") (const_int 2)
218 (eq_attr "op_type" "RR") (const_int 2)
219 (eq_attr "op_type" "RX") (const_int 4)
220 (eq_attr "op_type" "RI") (const_int 4)
221 (eq_attr "op_type" "RRE") (const_int 4)
222 (eq_attr "op_type" "RS") (const_int 4)
223 (eq_attr "op_type" "RSI") (const_int 4)
224 (eq_attr "op_type" "S") (const_int 4)
225 (eq_attr "op_type" "SI") (const_int 4)
226 (eq_attr "op_type" "SS") (const_int 6)
227 (eq_attr "op_type" "SSE") (const_int 6)
228 (eq_attr "op_type" "RXE") (const_int 6)
229 (eq_attr "op_type" "RSE") (const_int 6)
230 (eq_attr "op_type" "RIL") (const_int 6)
231 (eq_attr "op_type" "RXY") (const_int 6)
232 (eq_attr "op_type" "RSY") (const_int 6)
233 (eq_attr "op_type" "SIY") (const_int 6)]
237 ;; Processor type. This attribute must exactly match the processor_type
238 ;; enumeration in s390.h. The current machine description does not
239 ;; distinguish between g5 and g6, but there are differences between the two
240 ;; CPUs could in theory be modeled.
242 (define_attr "cpu" "g5,g6,z900,z990"
243 (const (symbol_ref "s390_tune")))
245 ;; Pipeline description for z900. For lack of anything better,
246 ;; this description is also used for the g5 and g6.
249 ;; Pipeline description for z990.
253 (include "predicates.md")
258 ;; This mode macro allows DF and SF patterns to be generated from the
260 (define_mode_macro FPR [DF SF])
262 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
263 ;; from the same template.
264 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
265 (define_mode_macro DSI [DI SI])
267 ;; This mode macro allows :P to be used for patterns that operate on
268 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
269 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
271 ;; This mode macro allows the QI and HI patterns to be defined from
272 ;; the same template.
273 (define_mode_macro HQI [HI QI])
275 ;; This mode macro allows the integer patterns to be defined from the
277 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
279 ;; This macro allows to unify all 'bCOND' expander patterns.
280 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
281 ordered uneq unlt ungt unle unge ltgt])
283 ;; This macro allows to unify all 'sCOND' patterns.
284 (define_code_macro SCOND [ltu gtu leu geu])
286 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
287 ;; the same template.
288 (define_code_macro SHIFT [ashift lshiftrt])
291 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
292 ;; and "ltebr" in SFmode.
293 (define_mode_attr de [(DF "d") (SF "e")])
295 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
296 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
297 (define_mode_attr dee [(DF "d") (SF "ee")])
299 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
300 ;; 'ashift' and "srdl" in 'lshiftrt'.
301 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
303 ;; In SHIFT templates, this attribute holds the correct standard name for the
304 ;; pattern itself and the corresponding function calls.
305 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
307 ;; This attribute handles differences in the instruction 'type' and will result
308 ;; in "RRE" for DImode and "RR" for SImode.
309 (define_mode_attr E [(DI "E") (SI "")])
311 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
312 ;; and "lcr" in SImode.
313 (define_mode_attr g [(DI "g") (SI "")])
315 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
316 ;; and "cfdbr" in SImode.
317 (define_mode_attr gf [(DI "g") (SI "f")])
319 ;; ICM mask required to load MODE value into the highest subreg
320 ;; of a SImode register.
321 (define_mode_attr icm_hi [(HI "12") (QI "8")])
323 ;; ICM mask required to load MODE value into the lowest subreg
324 ;; of a SImode register.
325 (define_mode_attr icm_lo [(HI "3") (QI "1")])
327 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
328 ;; HImode and "llgc" in QImode.
329 (define_mode_attr hc [(HI "h") (QI "c")])
331 ;; Maximum unsigned integer that fits in MODE.
332 (define_mode_attr max_uint [(HI "65535") (QI "255")])
336 ;;- Compare instructions.
339 (define_expand "cmp<mode>"
340 [(set (reg:CC CC_REGNUM)
341 (compare:CC (match_operand:GPR 0 "register_operand" "")
342 (match_operand:GPR 1 "general_operand" "")))]
345 s390_compare_op0 = operands[0];
346 s390_compare_op1 = operands[1];
350 (define_expand "cmp<mode>"
351 [(set (reg:CC CC_REGNUM)
352 (compare:CC (match_operand:FPR 0 "register_operand" "")
353 (match_operand:FPR 1 "general_operand" "")))]
356 s390_compare_op0 = operands[0];
357 s390_compare_op1 = operands[1];
362 ; Test-under-Mask instructions
364 (define_insn "*tmqi_mem"
365 [(set (reg CC_REGNUM)
366 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
367 (match_operand:QI 1 "immediate_operand" "n,n"))
368 (match_operand:QI 2 "immediate_operand" "n,n")))]
369 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
373 [(set_attr "op_type" "SI,SIY")])
375 (define_insn "*tmdi_reg"
376 [(set (reg CC_REGNUM)
377 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
378 (match_operand:DI 1 "immediate_operand"
379 "N0HD0,N1HD0,N2HD0,N3HD0"))
380 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
382 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
383 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
389 [(set_attr "op_type" "RI")])
391 (define_insn "*tmsi_reg"
392 [(set (reg CC_REGNUM)
393 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
394 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
395 (match_operand:SI 2 "immediate_operand" "n,n")))]
396 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
397 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
401 [(set_attr "op_type" "RI")])
403 (define_insn "*tm<mode>_full"
404 [(set (reg CC_REGNUM)
405 (compare (match_operand:HQI 0 "register_operand" "d")
406 (match_operand:HQI 1 "immediate_operand" "n")))]
407 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
409 [(set_attr "op_type" "RI")])
412 ; Load-and-Test instructions
414 (define_insn "*tstdi_sign"
415 [(set (reg CC_REGNUM)
416 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
417 (const_int 32)) (const_int 32))
418 (match_operand:DI 1 "const0_operand" "")))
419 (set (match_operand:DI 2 "register_operand" "=d")
420 (sign_extend:DI (match_dup 0)))]
421 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
423 [(set_attr "op_type" "RRE")])
425 (define_insn "*tstdi"
426 [(set (reg CC_REGNUM)
427 (compare (match_operand:DI 0 "register_operand" "d")
428 (match_operand:DI 1 "const0_operand" "")))
429 (set (match_operand:DI 2 "register_operand" "=d")
431 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
433 [(set_attr "op_type" "RRE")])
435 (define_insn "*tstdi_cconly"
436 [(set (reg CC_REGNUM)
437 (compare (match_operand:DI 0 "register_operand" "d")
438 (match_operand:DI 1 "const0_operand" "")))]
439 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
441 [(set_attr "op_type" "RRE")])
443 (define_insn "*tstdi_cconly_31"
444 [(set (reg CC_REGNUM)
445 (compare (match_operand:DI 0 "register_operand" "d")
446 (match_operand:DI 1 "const0_operand" "")))]
447 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
449 [(set_attr "op_type" "RS")
450 (set_attr "atype" "reg")])
453 (define_insn "*tstsi"
454 [(set (reg CC_REGNUM)
455 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
456 (match_operand:SI 1 "const0_operand" "")))
457 (set (match_operand:SI 2 "register_operand" "=d,d,d")
459 "s390_match_ccmode(insn, CCSmode)"
464 [(set_attr "op_type" "RR,RS,RSY")])
466 (define_insn "*tstsi_cconly"
467 [(set (reg CC_REGNUM)
468 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
469 (match_operand:SI 1 "const0_operand" "")))
470 (clobber (match_scratch:SI 2 "=X,d,d"))]
471 "s390_match_ccmode(insn, CCSmode)"
476 [(set_attr "op_type" "RR,RS,RSY")])
478 (define_insn "*tstsi_cconly2"
479 [(set (reg CC_REGNUM)
480 (compare (match_operand:SI 0 "register_operand" "d")
481 (match_operand:SI 1 "const0_operand" "")))]
482 "s390_match_ccmode(insn, CCSmode)"
484 [(set_attr "op_type" "RR")])
486 (define_insn "*tst<mode>CCT"
487 [(set (reg CC_REGNUM)
488 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
489 (match_operand:HQI 1 "const0_operand" "")))
490 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
492 "s390_match_ccmode(insn, CCTmode)"
495 icmy\t%2,<icm_lo>,%S0
497 [(set_attr "op_type" "RS,RSY,RI")])
499 (define_insn "*tsthiCCT_cconly"
500 [(set (reg CC_REGNUM)
501 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
502 (match_operand:HI 1 "const0_operand" "")))
503 (clobber (match_scratch:HI 2 "=d,d,X"))]
504 "s390_match_ccmode(insn, CCTmode)"
509 [(set_attr "op_type" "RS,RSY,RI")])
511 (define_insn "*tstqiCCT_cconly"
512 [(set (reg CC_REGNUM)
513 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
514 (match_operand:QI 1 "const0_operand" "")))]
515 "s390_match_ccmode(insn, CCTmode)"
520 [(set_attr "op_type" "SI,SIY,RI")])
522 (define_insn "*tst<mode>"
523 [(set (reg CC_REGNUM)
524 (compare (match_operand:HQI 0 "s_operand" "Q,S")
525 (match_operand:HQI 1 "const0_operand" "")))
526 (set (match_operand:HQI 2 "register_operand" "=d,d")
528 "s390_match_ccmode(insn, CCSmode)"
531 icmy\t%2,<icm_lo>,%S0"
532 [(set_attr "op_type" "RS,RSY")])
534 (define_insn "*tst<mode>_cconly"
535 [(set (reg CC_REGNUM)
536 (compare (match_operand:HQI 0 "s_operand" "Q,S")
537 (match_operand:HQI 1 "const0_operand" "")))
538 (clobber (match_scratch:HQI 2 "=d,d"))]
539 "s390_match_ccmode(insn, CCSmode)"
542 icmy\t%2,<icm_lo>,%S0"
543 [(set_attr "op_type" "RS,RSY")])
546 ; Compare (equality) instructions
548 (define_insn "*cmpdi_cct"
549 [(set (reg CC_REGNUM)
550 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
551 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
552 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
558 [(set_attr "op_type" "RRE,RI,RXY,SS")])
560 (define_insn "*cmpsi_cct"
561 [(set (reg CC_REGNUM)
562 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
563 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
564 "s390_match_ccmode (insn, CCTmode)"
571 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
574 ; Compare (signed) instructions
576 (define_insn "*cmpdi_ccs_sign"
577 [(set (reg CC_REGNUM)
578 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
579 (match_operand:DI 0 "register_operand" "d,d")))]
580 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
584 [(set_attr "op_type" "RRE,RXY")])
586 (define_insn "*cmpdi_ccs"
587 [(set (reg CC_REGNUM)
588 (compare (match_operand:DI 0 "register_operand" "d,d,d")
589 (match_operand:DI 1 "general_operand" "d,K,m")))]
590 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
595 [(set_attr "op_type" "RRE,RI,RXY")])
597 (define_insn "*cmpsi_ccs_sign"
598 [(set (reg CC_REGNUM)
599 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
600 (match_operand:SI 0 "register_operand" "d,d")))]
601 "s390_match_ccmode(insn, CCSRmode)"
605 [(set_attr "op_type" "RX,RXY")])
607 (define_insn "*cmpsi_ccs"
608 [(set (reg CC_REGNUM)
609 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
610 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
611 "s390_match_ccmode(insn, CCSmode)"
617 [(set_attr "op_type" "RR,RI,RX,RXY")])
620 ; Compare (unsigned) instructions
622 (define_insn "*cmpdi_ccu_zero"
623 [(set (reg CC_REGNUM)
624 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
625 (match_operand:DI 0 "register_operand" "d,d")))]
626 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
630 [(set_attr "op_type" "RRE,RXY")])
632 (define_insn "*cmpdi_ccu"
633 [(set (reg CC_REGNUM)
634 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
635 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
636 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
642 [(set_attr "op_type" "RRE,RXY,SS,SS")])
644 (define_insn "*cmpsi_ccu"
645 [(set (reg CC_REGNUM)
646 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
647 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
648 "s390_match_ccmode (insn, CCUmode)"
655 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
657 (define_insn "*cmphi_ccu"
658 [(set (reg CC_REGNUM)
659 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
660 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
661 "s390_match_ccmode (insn, CCUmode)
662 && !register_operand (operands[1], HImode)"
668 [(set_attr "op_type" "RS,RSY,SS,SS")])
670 (define_insn "*cmpqi_ccu"
671 [(set (reg CC_REGNUM)
672 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
673 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
674 "s390_match_ccmode (insn, CCUmode)
675 && !register_operand (operands[1], QImode)"
683 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
686 ; Block compare (CLC) instruction patterns.
689 [(set (reg CC_REGNUM)
690 (compare (match_operand:BLK 0 "memory_operand" "Q")
691 (match_operand:BLK 1 "memory_operand" "Q")))
692 (use (match_operand 2 "const_int_operand" "n"))]
693 "s390_match_ccmode (insn, CCUmode)
694 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
695 "clc\t%O0(%2,%R0),%S1"
696 [(set_attr "op_type" "SS")])
699 [(set (reg CC_REGNUM)
700 (compare (match_operand 0 "memory_operand" "")
701 (match_operand 1 "memory_operand" "")))]
703 && s390_match_ccmode (insn, CCUmode)
704 && GET_MODE (operands[0]) == GET_MODE (operands[1])
705 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
707 [(set (match_dup 0) (match_dup 1))
708 (use (match_dup 2))])]
710 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
711 operands[0] = adjust_address (operands[0], BLKmode, 0);
712 operands[1] = adjust_address (operands[1], BLKmode, 0);
714 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
715 operands[0], operands[1]);
716 operands[0] = SET_DEST (PATTERN (curr_insn));
720 ; (DF|SF) instructions
722 (define_insn "*cmp<mode>_ccs_0"
723 [(set (reg CC_REGNUM)
724 (compare (match_operand:FPR 0 "register_operand" "f")
725 (match_operand:FPR 1 "const0_operand" "")))]
726 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
728 [(set_attr "op_type" "RRE")
729 (set_attr "type" "fsimp<mode>")])
731 (define_insn "*cmp<mode>_ccs_0_ibm"
732 [(set (reg CC_REGNUM)
733 (compare (match_operand:FPR 0 "register_operand" "f")
734 (match_operand:FPR 1 "const0_operand" "")))]
735 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
737 [(set_attr "op_type" "RR")
738 (set_attr "type" "fsimp<mode>")])
740 (define_insn "*cmp<mode>_ccs"
741 [(set (reg CC_REGNUM)
742 (compare (match_operand:FPR 0 "register_operand" "f,f")
743 (match_operand:FPR 1 "general_operand" "f,R")))]
744 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
748 [(set_attr "op_type" "RRE,RXE")
749 (set_attr "type" "fsimp<mode>")])
751 (define_insn "*cmp<mode>_ccs_ibm"
752 [(set (reg CC_REGNUM)
753 (compare (match_operand:FPR 0 "register_operand" "f,f")
754 (match_operand:FPR 1 "general_operand" "f,R")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
759 [(set_attr "op_type" "RR,RX")
760 (set_attr "type" "fsimp<mode>")])
764 ;;- Move instructions.
768 ; movti instruction pattern(s).
772 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
773 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
781 [(set_attr "op_type" "RSY,RSY,*,*,SS")
782 (set_attr "type" "lm,stm,*,*,*")])
785 [(set (match_operand:TI 0 "nonimmediate_operand" "")
786 (match_operand:TI 1 "general_operand" ""))]
787 "TARGET_64BIT && reload_completed
788 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
789 [(set (match_dup 2) (match_dup 4))
790 (set (match_dup 3) (match_dup 5))]
792 operands[2] = operand_subword (operands[0], 0, 0, TImode);
793 operands[3] = operand_subword (operands[0], 1, 0, TImode);
794 operands[4] = operand_subword (operands[1], 0, 0, TImode);
795 operands[5] = operand_subword (operands[1], 1, 0, TImode);
799 [(set (match_operand:TI 0 "nonimmediate_operand" "")
800 (match_operand:TI 1 "general_operand" ""))]
801 "TARGET_64BIT && reload_completed
802 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
803 [(set (match_dup 2) (match_dup 4))
804 (set (match_dup 3) (match_dup 5))]
806 operands[2] = operand_subword (operands[0], 1, 0, TImode);
807 operands[3] = operand_subword (operands[0], 0, 0, TImode);
808 operands[4] = operand_subword (operands[1], 1, 0, TImode);
809 operands[5] = operand_subword (operands[1], 0, 0, TImode);
813 [(set (match_operand:TI 0 "register_operand" "")
814 (match_operand:TI 1 "memory_operand" ""))]
815 "TARGET_64BIT && reload_completed
816 && !s_operand (operands[1], VOIDmode)"
817 [(set (match_dup 0) (match_dup 1))]
819 rtx addr = operand_subword (operands[0], 1, 0, TImode);
820 s390_load_address (addr, XEXP (operands[1], 0));
821 operands[1] = replace_equiv_address (operands[1], addr);
824 (define_expand "reload_outti"
825 [(parallel [(match_operand:TI 0 "" "")
826 (match_operand:TI 1 "register_operand" "d")
827 (match_operand:DI 2 "register_operand" "=&a")])]
830 gcc_assert (MEM_P (operands[0]));
831 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
832 operands[0] = replace_equiv_address (operands[0], operands[2]);
833 emit_move_insn (operands[0], operands[1]);
838 ; movdi instruction pattern(s).
841 (define_expand "movdi"
842 [(set (match_operand:DI 0 "general_operand" "")
843 (match_operand:DI 1 "general_operand" ""))]
846 /* Handle symbolic constants. */
847 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
848 emit_symbolic_move (operands);
851 (define_insn "*movdi_larl"
852 [(set (match_operand:DI 0 "register_operand" "=d")
853 (match_operand:DI 1 "larl_operand" "X"))]
855 && !FP_REG_P (operands[0])"
857 [(set_attr "op_type" "RIL")
858 (set_attr "type" "larl")])
860 (define_insn "*movdi_64"
861 [(set (match_operand:DI 0 "nonimmediate_operand"
862 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
863 (match_operand:DI 1 "general_operand"
864 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
886 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
887 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
888 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
889 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
892 [(set (match_operand:DI 0 "register_operand" "")
893 (match_operand:DI 1 "register_operand" ""))]
894 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
895 [(set (match_dup 2) (match_dup 3))
896 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
897 (set (strict_low_part (match_dup 2)) (match_dup 4))]
898 "operands[2] = gen_lowpart (SImode, operands[0]);
899 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
902 [(set (match_operand:DI 0 "register_operand" "")
903 (match_operand:DI 1 "register_operand" ""))]
904 "TARGET_64BIT && ACCESS_REG_P (operands[0])
905 && dead_or_set_p (insn, operands[1])"
906 [(set (match_dup 3) (match_dup 2))
907 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
908 (set (match_dup 4) (match_dup 2))]
909 "operands[2] = gen_lowpart (SImode, operands[1]);
910 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
913 [(set (match_operand:DI 0 "register_operand" "")
914 (match_operand:DI 1 "register_operand" ""))]
915 "TARGET_64BIT && ACCESS_REG_P (operands[0])
916 && !dead_or_set_p (insn, operands[1])"
917 [(set (match_dup 3) (match_dup 2))
918 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
919 (set (match_dup 4) (match_dup 2))
920 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
921 "operands[2] = gen_lowpart (SImode, operands[1]);
922 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
924 (define_insn "*movdi_31"
925 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
926 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
939 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
940 (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
943 [(set (match_operand:DI 0 "nonimmediate_operand" "")
944 (match_operand:DI 1 "general_operand" ""))]
945 "!TARGET_64BIT && reload_completed
946 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
947 [(set (match_dup 2) (match_dup 4))
948 (set (match_dup 3) (match_dup 5))]
950 operands[2] = operand_subword (operands[0], 0, 0, DImode);
951 operands[3] = operand_subword (operands[0], 1, 0, DImode);
952 operands[4] = operand_subword (operands[1], 0, 0, DImode);
953 operands[5] = operand_subword (operands[1], 1, 0, DImode);
957 [(set (match_operand:DI 0 "nonimmediate_operand" "")
958 (match_operand:DI 1 "general_operand" ""))]
959 "!TARGET_64BIT && reload_completed
960 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
961 [(set (match_dup 2) (match_dup 4))
962 (set (match_dup 3) (match_dup 5))]
964 operands[2] = operand_subword (operands[0], 1, 0, DImode);
965 operands[3] = operand_subword (operands[0], 0, 0, DImode);
966 operands[4] = operand_subword (operands[1], 1, 0, DImode);
967 operands[5] = operand_subword (operands[1], 0, 0, DImode);
971 [(set (match_operand:DI 0 "register_operand" "")
972 (match_operand:DI 1 "memory_operand" ""))]
973 "!TARGET_64BIT && reload_completed
974 && !FP_REG_P (operands[0])
975 && !s_operand (operands[1], VOIDmode)"
976 [(set (match_dup 0) (match_dup 1))]
978 rtx addr = operand_subword (operands[0], 1, 0, DImode);
979 s390_load_address (addr, XEXP (operands[1], 0));
980 operands[1] = replace_equiv_address (operands[1], addr);
983 (define_expand "reload_outdi"
984 [(parallel [(match_operand:DI 0 "" "")
985 (match_operand:DI 1 "register_operand" "d")
986 (match_operand:SI 2 "register_operand" "=&a")])]
989 gcc_assert (MEM_P (operands[0]));
990 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
991 operands[0] = replace_equiv_address (operands[0], operands[2]);
992 emit_move_insn (operands[0], operands[1]);
997 [(set (match_operand:DI 0 "register_operand" "")
998 (mem:DI (match_operand 1 "address_operand" "")))]
1000 && !FP_REG_P (operands[0])
1001 && GET_CODE (operands[1]) == SYMBOL_REF
1002 && CONSTANT_POOL_ADDRESS_P (operands[1])
1003 && get_pool_mode (operands[1]) == DImode
1004 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1005 [(set (match_dup 0) (match_dup 2))]
1006 "operands[2] = get_pool_constant (operands[1]);")
1008 (define_insn "*la_64"
1009 [(set (match_operand:DI 0 "register_operand" "=d,d")
1010 (match_operand:QI 1 "address_operand" "U,W"))]
1015 [(set_attr "op_type" "RX,RXY")
1016 (set_attr "type" "la")])
1020 [(set (match_operand:DI 0 "register_operand" "")
1021 (match_operand:QI 1 "address_operand" ""))
1022 (clobber (reg:CC CC_REGNUM))])]
1024 && preferred_la_operand_p (operands[1], const0_rtx)"
1025 [(set (match_dup 0) (match_dup 1))]
1029 [(set (match_operand:DI 0 "register_operand" "")
1030 (match_operand:DI 1 "register_operand" ""))
1033 (plus:DI (match_dup 0)
1034 (match_operand:DI 2 "nonmemory_operand" "")))
1035 (clobber (reg:CC CC_REGNUM))])]
1037 && !reg_overlap_mentioned_p (operands[0], operands[2])
1038 && preferred_la_operand_p (operands[1], operands[2])"
1039 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1042 (define_expand "reload_indi"
1043 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1044 (match_operand:DI 1 "s390_plus_operand" "")
1045 (match_operand:DI 2 "register_operand" "=&a")])]
1048 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1053 ; movsi instruction pattern(s).
1056 (define_expand "movsi"
1057 [(set (match_operand:SI 0 "general_operand" "")
1058 (match_operand:SI 1 "general_operand" ""))]
1061 /* Handle symbolic constants. */
1062 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1063 emit_symbolic_move (operands);
1066 (define_insn "*movsi_larl"
1067 [(set (match_operand:SI 0 "register_operand" "=d")
1068 (match_operand:SI 1 "larl_operand" "X"))]
1069 "!TARGET_64BIT && TARGET_CPU_ZARCH
1070 && !FP_REG_P (operands[0])"
1072 [(set_attr "op_type" "RIL")
1073 (set_attr "type" "larl")])
1075 (define_insn "*movsi_zarch"
1076 [(set (match_operand:SI 0 "nonimmediate_operand"
1077 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1078 (match_operand:SI 1 "general_operand"
1079 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1101 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1102 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1103 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1104 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1106 (define_insn "*movsi_esa"
1107 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1108 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1123 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1124 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1127 [(set (match_operand:SI 0 "register_operand" "")
1128 (mem:SI (match_operand 1 "address_operand" "")))]
1129 "!FP_REG_P (operands[0])
1130 && GET_CODE (operands[1]) == SYMBOL_REF
1131 && CONSTANT_POOL_ADDRESS_P (operands[1])
1132 && get_pool_mode (operands[1]) == SImode
1133 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1134 [(set (match_dup 0) (match_dup 2))]
1135 "operands[2] = get_pool_constant (operands[1]);")
1137 (define_insn "*la_31"
1138 [(set (match_operand:SI 0 "register_operand" "=d,d")
1139 (match_operand:QI 1 "address_operand" "U,W"))]
1140 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1144 [(set_attr "op_type" "RX,RXY")
1145 (set_attr "type" "la")])
1149 [(set (match_operand:SI 0 "register_operand" "")
1150 (match_operand:QI 1 "address_operand" ""))
1151 (clobber (reg:CC CC_REGNUM))])]
1153 && preferred_la_operand_p (operands[1], const0_rtx)"
1154 [(set (match_dup 0) (match_dup 1))]
1158 [(set (match_operand:SI 0 "register_operand" "")
1159 (match_operand:SI 1 "register_operand" ""))
1162 (plus:SI (match_dup 0)
1163 (match_operand:SI 2 "nonmemory_operand" "")))
1164 (clobber (reg:CC CC_REGNUM))])]
1166 && !reg_overlap_mentioned_p (operands[0], operands[2])
1167 && preferred_la_operand_p (operands[1], operands[2])"
1168 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1171 (define_insn "*la_31_and"
1172 [(set (match_operand:SI 0 "register_operand" "=d,d")
1173 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1174 (const_int 2147483647)))]
1179 [(set_attr "op_type" "RX,RXY")
1180 (set_attr "type" "la")])
1182 (define_insn_and_split "*la_31_and_cc"
1183 [(set (match_operand:SI 0 "register_operand" "=d")
1184 (and:SI (match_operand:QI 1 "address_operand" "p")
1185 (const_int 2147483647)))
1186 (clobber (reg:CC CC_REGNUM))]
1189 "&& reload_completed"
1191 (and:SI (match_dup 1) (const_int 2147483647)))]
1193 [(set_attr "op_type" "RX")
1194 (set_attr "type" "la")])
1196 (define_insn "force_la_31"
1197 [(set (match_operand:SI 0 "register_operand" "=d,d")
1198 (match_operand:QI 1 "address_operand" "U,W"))
1199 (use (const_int 0))]
1204 [(set_attr "op_type" "RX")
1205 (set_attr "type" "la")])
1207 (define_expand "reload_insi"
1208 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1209 (match_operand:SI 1 "s390_plus_operand" "")
1210 (match_operand:SI 2 "register_operand" "=&a")])]
1213 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1218 ; movhi instruction pattern(s).
1221 (define_expand "movhi"
1222 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1223 (match_operand:HI 1 "general_operand" ""))]
1226 /* Make it explicit that loading a register from memory
1227 always sign-extends (at least) to SImode. */
1228 if (optimize && !no_new_pseudos
1229 && register_operand (operands[0], VOIDmode)
1230 && GET_CODE (operands[1]) == MEM)
1232 rtx tmp = gen_reg_rtx (SImode);
1233 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1234 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1235 operands[1] = gen_lowpart (HImode, tmp);
1239 (define_insn "*movhi"
1240 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1241 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1251 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1252 (set_attr "type" "lr,*,*,*,store,store,*")])
1255 [(set (match_operand:HI 0 "register_operand" "")
1256 (mem:HI (match_operand 1 "address_operand" "")))]
1257 "GET_CODE (operands[1]) == SYMBOL_REF
1258 && CONSTANT_POOL_ADDRESS_P (operands[1])
1259 && get_pool_mode (operands[1]) == HImode
1260 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1261 [(set (match_dup 0) (match_dup 2))]
1262 "operands[2] = get_pool_constant (operands[1]);")
1265 ; movqi instruction pattern(s).
1268 (define_expand "movqi"
1269 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1270 (match_operand:QI 1 "general_operand" ""))]
1273 /* On z/Architecture, zero-extending from memory to register
1274 is just as fast as a QImode load. */
1275 if (TARGET_ZARCH && optimize && !no_new_pseudos
1276 && register_operand (operands[0], VOIDmode)
1277 && GET_CODE (operands[1]) == MEM)
1279 rtx tmp = gen_reg_rtx (word_mode);
1280 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1281 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1282 operands[1] = gen_lowpart (QImode, tmp);
1286 (define_insn "*movqi"
1287 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1288 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1300 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1301 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1304 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1305 (mem:QI (match_operand 1 "address_operand" "")))]
1306 "GET_CODE (operands[1]) == SYMBOL_REF
1307 && CONSTANT_POOL_ADDRESS_P (operands[1])
1308 && get_pool_mode (operands[1]) == QImode
1309 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1310 [(set (match_dup 0) (match_dup 2))]
1311 "operands[2] = get_pool_constant (operands[1]);")
1314 ; movstrictqi instruction pattern(s).
1317 (define_insn "*movstrictqi"
1318 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1319 (match_operand:QI 1 "memory_operand" "R,T"))]
1324 [(set_attr "op_type" "RX,RXY")])
1327 ; movstricthi instruction pattern(s).
1330 (define_insn "*movstricthi"
1331 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1332 (match_operand:HI 1 "memory_operand" "Q,S"))
1333 (clobber (reg:CC CC_REGNUM))]
1338 [(set_attr "op_type" "RS,RSY")])
1341 ; movstrictsi instruction pattern(s).
1344 (define_insn "movstrictsi"
1345 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1346 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1353 [(set_attr "op_type" "RR,RX,RXY,RRE")
1354 (set_attr "type" "lr,load,load,*")])
1357 ; movdf instruction pattern(s).
1360 (define_expand "movdf"
1361 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1362 (match_operand:DF 1 "general_operand" ""))]
1366 (define_insn "*movdf_64"
1367 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1368 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1380 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1381 (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1383 (define_insn "*movdf_31"
1384 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1385 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1398 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1399 (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
1402 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1403 (match_operand:DF 1 "general_operand" ""))]
1404 "!TARGET_64BIT && reload_completed
1405 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1406 [(set (match_dup 2) (match_dup 4))
1407 (set (match_dup 3) (match_dup 5))]
1409 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1410 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1411 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1412 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1416 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1417 (match_operand:DF 1 "general_operand" ""))]
1418 "!TARGET_64BIT && reload_completed
1419 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1420 [(set (match_dup 2) (match_dup 4))
1421 (set (match_dup 3) (match_dup 5))]
1423 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1424 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1425 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1426 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1430 [(set (match_operand:DF 0 "register_operand" "")
1431 (match_operand:DF 1 "memory_operand" ""))]
1432 "!TARGET_64BIT && reload_completed
1433 && !FP_REG_P (operands[0])
1434 && !s_operand (operands[1], VOIDmode)"
1435 [(set (match_dup 0) (match_dup 1))]
1437 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1438 s390_load_address (addr, XEXP (operands[1], 0));
1439 operands[1] = replace_equiv_address (operands[1], addr);
1442 (define_expand "reload_outdf"
1443 [(parallel [(match_operand:DF 0 "" "")
1444 (match_operand:DF 1 "register_operand" "d")
1445 (match_operand:SI 2 "register_operand" "=&a")])]
1448 gcc_assert (MEM_P (operands[0]));
1449 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1450 operands[0] = replace_equiv_address (operands[0], operands[2]);
1451 emit_move_insn (operands[0], operands[1]);
1456 ; movsf instruction pattern(s).
1459 (define_insn "movsf"
1460 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1461 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1475 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1476 (set_attr "type" "floadsf,floadsf,floadsf,fstoresf,fstoresf,
1477 lr,load,load,store,store,*")])
1480 ; movcc instruction pattern
1483 (define_insn "movcc"
1484 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1485 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1495 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1496 (set_attr "type" "lr,*,*,store,store,load,load")])
1499 ; Block move (MVC) patterns.
1503 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1504 (match_operand:BLK 1 "memory_operand" "Q"))
1505 (use (match_operand 2 "const_int_operand" "n"))]
1506 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1507 "mvc\t%O0(%2,%R0),%S1"
1508 [(set_attr "op_type" "SS")])
1511 [(set (match_operand 0 "memory_operand" "")
1512 (match_operand 1 "memory_operand" ""))]
1514 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1515 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1517 [(set (match_dup 0) (match_dup 1))
1518 (use (match_dup 2))])]
1520 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1521 operands[0] = adjust_address (operands[0], BLKmode, 0);
1522 operands[1] = adjust_address (operands[1], BLKmode, 0);
1527 [(set (match_operand:BLK 0 "memory_operand" "")
1528 (match_operand:BLK 1 "memory_operand" ""))
1529 (use (match_operand 2 "const_int_operand" ""))])
1531 [(set (match_operand:BLK 3 "memory_operand" "")
1532 (match_operand:BLK 4 "memory_operand" ""))
1533 (use (match_operand 5 "const_int_operand" ""))])]
1534 "s390_offset_p (operands[0], operands[3], operands[2])
1535 && s390_offset_p (operands[1], operands[4], operands[2])
1536 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1538 [(set (match_dup 6) (match_dup 7))
1539 (use (match_dup 8))])]
1540 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1541 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1542 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1546 ; load_multiple pattern(s).
1548 ; ??? Due to reload problems with replacing registers inside match_parallel
1549 ; we currently support load_multiple/store_multiple only after reload.
1552 (define_expand "load_multiple"
1553 [(match_par_dup 3 [(set (match_operand 0 "" "")
1554 (match_operand 1 "" ""))
1555 (use (match_operand 2 "" ""))])]
1558 enum machine_mode mode;
1564 /* Support only loading a constant number of fixed-point registers from
1565 memory and only bother with this if more than two */
1566 if (GET_CODE (operands[2]) != CONST_INT
1567 || INTVAL (operands[2]) < 2
1568 || INTVAL (operands[2]) > 16
1569 || GET_CODE (operands[1]) != MEM
1570 || GET_CODE (operands[0]) != REG
1571 || REGNO (operands[0]) >= 16)
1574 count = INTVAL (operands[2]);
1575 regno = REGNO (operands[0]);
1576 mode = GET_MODE (operands[0]);
1577 if (mode != SImode && mode != word_mode)
1580 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1583 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1585 from = XEXP (operands[1], 0);
1588 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1589 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1590 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1592 from = XEXP (XEXP (operands[1], 0), 0);
1593 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1600 from = force_reg (Pmode, XEXP (operands[1], 0));
1604 for (i = 0; i < count; i++)
1605 XVECEXP (operands[3], 0, i)
1606 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1607 change_address (operands[1], mode,
1608 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1611 (define_insn "*load_multiple_di"
1612 [(match_parallel 0 "load_multiple_operation"
1613 [(set (match_operand:DI 1 "register_operand" "=r")
1614 (match_operand:DI 2 "s_operand" "QS"))])]
1615 "reload_completed && word_mode == DImode"
1617 int words = XVECLEN (operands[0], 0);
1618 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1619 return "lmg\t%1,%0,%S2";
1621 [(set_attr "op_type" "RSY")
1622 (set_attr "type" "lm")])
1624 (define_insn "*load_multiple_si"
1625 [(match_parallel 0 "load_multiple_operation"
1626 [(set (match_operand:SI 1 "register_operand" "=r,r")
1627 (match_operand:SI 2 "s_operand" "Q,S"))])]
1630 int words = XVECLEN (operands[0], 0);
1631 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1632 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1634 [(set_attr "op_type" "RS,RSY")
1635 (set_attr "type" "lm")])
1638 ; store multiple pattern(s).
1641 (define_expand "store_multiple"
1642 [(match_par_dup 3 [(set (match_operand 0 "" "")
1643 (match_operand 1 "" ""))
1644 (use (match_operand 2 "" ""))])]
1647 enum machine_mode mode;
1653 /* Support only storing a constant number of fixed-point registers to
1654 memory and only bother with this if more than two. */
1655 if (GET_CODE (operands[2]) != CONST_INT
1656 || INTVAL (operands[2]) < 2
1657 || INTVAL (operands[2]) > 16
1658 || GET_CODE (operands[0]) != MEM
1659 || GET_CODE (operands[1]) != REG
1660 || REGNO (operands[1]) >= 16)
1663 count = INTVAL (operands[2]);
1664 regno = REGNO (operands[1]);
1665 mode = GET_MODE (operands[1]);
1666 if (mode != SImode && mode != word_mode)
1669 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1673 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1675 to = XEXP (operands[0], 0);
1678 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1679 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1680 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1682 to = XEXP (XEXP (operands[0], 0), 0);
1683 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1690 to = force_reg (Pmode, XEXP (operands[0], 0));
1694 for (i = 0; i < count; i++)
1695 XVECEXP (operands[3], 0, i)
1696 = gen_rtx_SET (VOIDmode,
1697 change_address (operands[0], mode,
1698 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1699 gen_rtx_REG (mode, regno + i));
1702 (define_insn "*store_multiple_di"
1703 [(match_parallel 0 "store_multiple_operation"
1704 [(set (match_operand:DI 1 "s_operand" "=QS")
1705 (match_operand:DI 2 "register_operand" "r"))])]
1706 "reload_completed && word_mode == DImode"
1708 int words = XVECLEN (operands[0], 0);
1709 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1710 return "stmg\t%2,%0,%S1";
1712 [(set_attr "op_type" "RSY")
1713 (set_attr "type" "stm")])
1716 (define_insn "*store_multiple_si"
1717 [(match_parallel 0 "store_multiple_operation"
1718 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1719 (match_operand:SI 2 "register_operand" "r,r"))])]
1722 int words = XVECLEN (operands[0], 0);
1723 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1724 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1726 [(set_attr "op_type" "RS,RSY")
1727 (set_attr "type" "stm")])
1730 ;; String instructions.
1733 (define_insn "*execute"
1734 [(match_parallel 0 ""
1735 [(unspec [(match_operand 1 "register_operand" "a")
1736 (match_operand:BLK 2 "memory_operand" "R")
1737 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1738 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1739 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1741 [(set_attr "op_type" "RX")
1742 (set_attr "type" "cs")])
1746 ; strlenM instruction pattern(s).
1749 (define_expand "strlen<mode>"
1750 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1753 (unspec:P [(const_int 0)
1754 (match_operand:BLK 1 "memory_operand" "")
1756 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1757 (clobber (scratch:P))
1758 (clobber (reg:CC CC_REGNUM))])
1760 [(set (match_operand:P 0 "register_operand" "")
1761 (minus:P (match_dup 4) (match_dup 5)))
1762 (clobber (reg:CC CC_REGNUM))])]
1765 operands[4] = gen_reg_rtx (Pmode);
1766 operands[5] = gen_reg_rtx (Pmode);
1767 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1768 operands[1] = replace_equiv_address (operands[1], operands[5]);
1771 (define_insn "*strlen<mode>"
1772 [(set (match_operand:P 0 "register_operand" "=a")
1773 (unspec:P [(match_operand:P 2 "general_operand" "0")
1774 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1776 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1777 (clobber (match_scratch:P 1 "=a"))
1778 (clobber (reg:CC CC_REGNUM))]
1780 "srst\t%0,%1\;jo\t.-4"
1781 [(set_attr "length" "8")
1782 (set_attr "type" "vs")])
1785 ; movmemM instruction pattern(s).
1788 (define_expand "movmem<mode>"
1789 [(set (match_operand:BLK 0 "memory_operand" "")
1790 (match_operand:BLK 1 "memory_operand" ""))
1791 (use (match_operand:GPR 2 "general_operand" ""))
1792 (match_operand 3 "" "")]
1794 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1796 ; Move a block that is up to 256 bytes in length.
1797 ; The block length is taken as (operands[2] % 256) + 1.
1799 (define_expand "movmem_short"
1801 [(set (match_operand:BLK 0 "memory_operand" "")
1802 (match_operand:BLK 1 "memory_operand" ""))
1803 (use (match_operand 2 "nonmemory_operand" ""))
1804 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1805 (clobber (match_dup 3))])]
1807 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1809 (define_insn "*movmem_short"
1810 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1811 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1812 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1813 (use (match_operand 3 "immediate_operand" "X,R,X"))
1814 (clobber (match_scratch 4 "=X,X,&a"))]
1815 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1816 && GET_MODE (operands[4]) == Pmode"
1818 [(set_attr "type" "cs")])
1821 [(set (match_operand:BLK 0 "memory_operand" "")
1822 (match_operand:BLK 1 "memory_operand" ""))
1823 (use (match_operand 2 "const_int_operand" ""))
1824 (use (match_operand 3 "immediate_operand" ""))
1825 (clobber (scratch))]
1828 [(set (match_dup 0) (match_dup 1))
1829 (use (match_dup 2))])]
1830 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1833 [(set (match_operand:BLK 0 "memory_operand" "")
1834 (match_operand:BLK 1 "memory_operand" ""))
1835 (use (match_operand 2 "register_operand" ""))
1836 (use (match_operand 3 "memory_operand" ""))
1837 (clobber (scratch))]
1840 [(unspec [(match_dup 2) (match_dup 3)
1841 (const_int 0)] UNSPEC_EXECUTE)
1842 (set (match_dup 0) (match_dup 1))
1843 (use (const_int 1))])]
1847 [(set (match_operand:BLK 0 "memory_operand" "")
1848 (match_operand:BLK 1 "memory_operand" ""))
1849 (use (match_operand 2 "register_operand" ""))
1850 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1851 (clobber (match_operand 3 "register_operand" ""))]
1852 "reload_completed && TARGET_CPU_ZARCH"
1853 [(set (match_dup 3) (label_ref (match_dup 4)))
1855 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1856 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1857 (set (match_dup 0) (match_dup 1))
1858 (use (const_int 1))])]
1859 "operands[4] = gen_label_rtx ();")
1861 ; Move a block of arbitrary length.
1863 (define_expand "movmem_long"
1865 [(clobber (match_dup 2))
1866 (clobber (match_dup 3))
1867 (set (match_operand:BLK 0 "memory_operand" "")
1868 (match_operand:BLK 1 "memory_operand" ""))
1869 (use (match_operand 2 "general_operand" ""))
1871 (clobber (reg:CC CC_REGNUM))])]
1874 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1875 rtx reg0 = gen_reg_rtx (dword_mode);
1876 rtx reg1 = gen_reg_rtx (dword_mode);
1877 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1878 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1879 rtx len0 = gen_lowpart (Pmode, reg0);
1880 rtx len1 = gen_lowpart (Pmode, reg1);
1882 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1883 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1884 emit_move_insn (len0, operands[2]);
1886 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1887 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1888 emit_move_insn (len1, operands[2]);
1890 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1891 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1896 (define_insn "*movmem_long_64"
1897 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1898 (clobber (match_operand:TI 1 "register_operand" "=d"))
1899 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1900 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1903 (clobber (reg:CC CC_REGNUM))]
1905 "mvcle\t%0,%1,0\;jo\t.-4"
1906 [(set_attr "length" "8")
1907 (set_attr "type" "vs")])
1909 (define_insn "*movmem_long_31"
1910 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1911 (clobber (match_operand:DI 1 "register_operand" "=d"))
1912 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1913 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1916 (clobber (reg:CC CC_REGNUM))]
1918 "mvcle\t%0,%1,0\;jo\t.-4"
1919 [(set_attr "length" "8")
1920 (set_attr "type" "vs")])
1923 ; clrmemM instruction pattern(s).
1926 (define_expand "clrmem<mode>"
1927 [(set (match_operand:BLK 0 "memory_operand" "")
1929 (use (match_operand:GPR 1 "general_operand" ""))
1930 (match_operand 2 "" "")]
1932 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1934 ; Clear a block that is up to 256 bytes in length.
1935 ; The block length is taken as (operands[1] % 256) + 1.
1937 (define_expand "clrmem_short"
1939 [(set (match_operand:BLK 0 "memory_operand" "")
1941 (use (match_operand 1 "nonmemory_operand" ""))
1942 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1943 (clobber (match_dup 2))
1944 (clobber (reg:CC CC_REGNUM))])]
1946 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1948 (define_insn "*clrmem_short"
1949 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1951 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1952 (use (match_operand 2 "immediate_operand" "X,R,X"))
1953 (clobber (match_scratch 3 "=X,X,&a"))
1954 (clobber (reg:CC CC_REGNUM))]
1955 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
1956 && GET_MODE (operands[3]) == Pmode"
1958 [(set_attr "type" "cs")])
1961 [(set (match_operand:BLK 0 "memory_operand" "")
1963 (use (match_operand 1 "const_int_operand" ""))
1964 (use (match_operand 2 "immediate_operand" ""))
1966 (clobber (reg:CC CC_REGNUM))]
1969 [(set (match_dup 0) (const_int 0))
1971 (clobber (reg:CC CC_REGNUM))])]
1972 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
1975 [(set (match_operand:BLK 0 "memory_operand" "")
1977 (use (match_operand 1 "register_operand" ""))
1978 (use (match_operand 2 "memory_operand" ""))
1980 (clobber (reg:CC CC_REGNUM))]
1983 [(unspec [(match_dup 1) (match_dup 2)
1984 (const_int 0)] UNSPEC_EXECUTE)
1985 (set (match_dup 0) (const_int 0))
1987 (clobber (reg:CC CC_REGNUM))])]
1991 [(set (match_operand:BLK 0 "memory_operand" "")
1993 (use (match_operand 1 "register_operand" ""))
1994 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1995 (clobber (match_operand 2 "register_operand" ""))
1996 (clobber (reg:CC CC_REGNUM))]
1997 "reload_completed && TARGET_CPU_ZARCH"
1998 [(set (match_dup 2) (label_ref (match_dup 3)))
2000 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2001 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2002 (set (match_dup 0) (const_int 0))
2004 (clobber (reg:CC CC_REGNUM))])]
2005 "operands[3] = gen_label_rtx ();")
2007 ; Clear a block of arbitrary length.
2009 (define_expand "clrmem_long"
2011 [(clobber (match_dup 1))
2012 (set (match_operand:BLK 0 "memory_operand" "")
2014 (use (match_operand 1 "general_operand" ""))
2016 (clobber (reg:CC CC_REGNUM))])]
2019 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2020 rtx reg0 = gen_reg_rtx (dword_mode);
2021 rtx reg1 = gen_reg_rtx (dword_mode);
2022 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2023 rtx len0 = gen_lowpart (Pmode, reg0);
2025 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2026 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2027 emit_move_insn (len0, operands[1]);
2029 emit_move_insn (reg1, const0_rtx);
2031 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2036 (define_insn "*clrmem_long_64"
2037 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2038 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2041 (use (match_operand:TI 1 "register_operand" "d"))
2042 (clobber (reg:CC CC_REGNUM))]
2044 "mvcle\t%0,%1,0\;jo\t.-4"
2045 [(set_attr "length" "8")
2046 (set_attr "type" "vs")])
2048 (define_insn "*clrmem_long_31"
2049 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2050 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2053 (use (match_operand:DI 1 "register_operand" "d"))
2054 (clobber (reg:CC CC_REGNUM))]
2056 "mvcle\t%0,%1,0\;jo\t.-4"
2057 [(set_attr "length" "8")
2058 (set_attr "type" "vs")])
2061 ; cmpmemM instruction pattern(s).
2064 (define_expand "cmpmemsi"
2065 [(set (match_operand:SI 0 "register_operand" "")
2066 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2067 (match_operand:BLK 2 "memory_operand" "") ) )
2068 (use (match_operand:SI 3 "general_operand" ""))
2069 (use (match_operand:SI 4 "" ""))]
2071 "s390_expand_cmpmem (operands[0], operands[1],
2072 operands[2], operands[3]); DONE;")
2074 ; Compare a block that is up to 256 bytes in length.
2075 ; The block length is taken as (operands[2] % 256) + 1.
2077 (define_expand "cmpmem_short"
2079 [(set (reg:CCU CC_REGNUM)
2080 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2081 (match_operand:BLK 1 "memory_operand" "")))
2082 (use (match_operand 2 "nonmemory_operand" ""))
2083 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2084 (clobber (match_dup 3))])]
2086 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2088 (define_insn "*cmpmem_short"
2089 [(set (reg:CCU CC_REGNUM)
2090 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2091 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2092 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2093 (use (match_operand 3 "immediate_operand" "X,R,X"))
2094 (clobber (match_scratch 4 "=X,X,&a"))]
2095 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2096 && GET_MODE (operands[4]) == Pmode"
2098 [(set_attr "type" "cs")])
2101 [(set (reg:CCU CC_REGNUM)
2102 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2103 (match_operand:BLK 1 "memory_operand" "")))
2104 (use (match_operand 2 "const_int_operand" ""))
2105 (use (match_operand 3 "immediate_operand" ""))
2106 (clobber (scratch))]
2109 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2110 (use (match_dup 2))])]
2111 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2114 [(set (reg:CCU CC_REGNUM)
2115 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2116 (match_operand:BLK 1 "memory_operand" "")))
2117 (use (match_operand 2 "register_operand" ""))
2118 (use (match_operand 3 "memory_operand" ""))
2119 (clobber (scratch))]
2122 [(unspec [(match_dup 2) (match_dup 3)
2123 (const_int 0)] UNSPEC_EXECUTE)
2124 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2125 (use (const_int 1))])]
2129 [(set (reg:CCU CC_REGNUM)
2130 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2131 (match_operand:BLK 1 "memory_operand" "")))
2132 (use (match_operand 2 "register_operand" ""))
2133 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2134 (clobber (match_operand 3 "register_operand" ""))]
2135 "reload_completed && TARGET_CPU_ZARCH"
2136 [(set (match_dup 3) (label_ref (match_dup 4)))
2138 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2139 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2140 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2141 (use (const_int 1))])]
2142 "operands[4] = gen_label_rtx ();")
2144 ; Compare a block of arbitrary length.
2146 (define_expand "cmpmem_long"
2148 [(clobber (match_dup 2))
2149 (clobber (match_dup 3))
2150 (set (reg:CCU CC_REGNUM)
2151 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2152 (match_operand:BLK 1 "memory_operand" "")))
2153 (use (match_operand 2 "general_operand" ""))
2154 (use (match_dup 3))])]
2157 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2158 rtx reg0 = gen_reg_rtx (dword_mode);
2159 rtx reg1 = gen_reg_rtx (dword_mode);
2160 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2161 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2162 rtx len0 = gen_lowpart (Pmode, reg0);
2163 rtx len1 = gen_lowpart (Pmode, reg1);
2165 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2166 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2167 emit_move_insn (len0, operands[2]);
2169 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2170 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2171 emit_move_insn (len1, operands[2]);
2173 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2174 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2179 (define_insn "*cmpmem_long_64"
2180 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2181 (clobber (match_operand:TI 1 "register_operand" "=d"))
2182 (set (reg:CCU CC_REGNUM)
2183 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2184 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2186 (use (match_dup 3))]
2188 "clcle\t%0,%1,0\;jo\t.-4"
2189 [(set_attr "length" "8")
2190 (set_attr "type" "vs")])
2192 (define_insn "*cmpmem_long_31"
2193 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2194 (clobber (match_operand:DI 1 "register_operand" "=d"))
2195 (set (reg:CCU CC_REGNUM)
2196 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2197 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2199 (use (match_dup 3))]
2201 "clcle\t%0,%1,0\;jo\t.-4"
2202 [(set_attr "length" "8")
2203 (set_attr "type" "vs")])
2205 ; Convert CCUmode condition code to integer.
2206 ; Result is zero if EQ, positive if LTU, negative if GTU.
2208 (define_insn_and_split "cmpint"
2209 [(set (match_operand:SI 0 "register_operand" "=d")
2210 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2212 (clobber (reg:CC CC_REGNUM))]
2216 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2218 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2219 (clobber (reg:CC CC_REGNUM))])])
2221 (define_insn_and_split "*cmpint_cc"
2222 [(set (reg CC_REGNUM)
2223 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2226 (set (match_operand:SI 0 "register_operand" "=d")
2227 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2228 "s390_match_ccmode (insn, CCSmode)"
2230 "&& reload_completed"
2231 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2233 [(set (match_dup 2) (match_dup 3))
2234 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2236 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2237 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2238 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2241 (define_insn_and_split "*cmpint_sign"
2242 [(set (match_operand:DI 0 "register_operand" "=d")
2243 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2245 (clobber (reg:CC CC_REGNUM))]
2248 "&& reload_completed"
2249 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2251 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2252 (clobber (reg:CC CC_REGNUM))])])
2254 (define_insn_and_split "*cmpint_sign_cc"
2255 [(set (reg CC_REGNUM)
2256 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2257 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2259 (const_int 32)) (const_int 32))
2261 (set (match_operand:DI 0 "register_operand" "=d")
2262 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2263 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2265 "&& reload_completed"
2266 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2268 [(set (match_dup 2) (match_dup 3))
2269 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2271 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2272 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2273 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2278 ;;- Conversion instructions.
2282 (define_insn "*sethigh<mode>si"
2283 [(set (match_operand:SI 0 "register_operand" "=d,d")
2284 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2285 (clobber (reg:CC CC_REGNUM))]
2288 icm\t%0,<icm_hi>,%S1
2289 icmy\t%0,<icm_hi>,%S1"
2290 [(set_attr "op_type" "RS,RSY")])
2292 (define_insn "*sethighqidi_64"
2293 [(set (match_operand:DI 0 "register_operand" "=d")
2294 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2295 (clobber (reg:CC CC_REGNUM))]
2298 [(set_attr "op_type" "RSY")])
2300 (define_insn "*sethighqidi_31"
2301 [(set (match_operand:DI 0 "register_operand" "=d,d")
2302 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2303 (clobber (reg:CC CC_REGNUM))]
2308 [(set_attr "op_type" "RS,RSY")])
2310 (define_insn_and_split "*extractqi"
2311 [(set (match_operand:SI 0 "register_operand" "=d")
2312 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2313 (match_operand 2 "const_int_operand" "n")
2315 (clobber (reg:CC CC_REGNUM))]
2317 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2319 "&& reload_completed"
2321 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2322 (clobber (reg:CC CC_REGNUM))])
2323 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2325 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2326 operands[1] = change_address (operands[1], QImode, 0);
2329 (define_insn_and_split "*extracthi"
2330 [(set (match_operand:SI 0 "register_operand" "=d")
2331 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2332 (match_operand 2 "const_int_operand" "n")
2334 (clobber (reg:CC CC_REGNUM))]
2336 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2338 "&& reload_completed"
2340 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2341 (clobber (reg:CC CC_REGNUM))])
2342 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2344 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2345 operands[1] = change_address (operands[1], HImode, 0);
2349 ; extendsidi2 instruction pattern(s).
2352 (define_expand "extendsidi2"
2353 [(set (match_operand:DI 0 "register_operand" "")
2354 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2360 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2361 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2362 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2363 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2369 (define_insn "*extendsidi2"
2370 [(set (match_operand:DI 0 "register_operand" "=d,d")
2371 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2376 [(set_attr "op_type" "RRE,RXY")])
2379 ; extend(hi|qi)di2 instruction pattern(s).
2382 (define_expand "extend<mode>di2"
2383 [(set (match_operand:DI 0 "register_operand" "")
2384 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2390 rtx tmp = gen_reg_rtx (SImode);
2391 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2392 emit_insn (gen_extendsidi2 (operands[0], tmp));
2397 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2398 GET_MODE_BITSIZE (<MODE>mode));
2399 operands[1] = gen_lowpart (DImode, operands[1]);
2400 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2401 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2407 (define_insn "*extendhidi2"
2408 [(set (match_operand:DI 0 "register_operand" "=d")
2409 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2412 [(set_attr "op_type" "RXY")])
2414 (define_insn "*extendqidi2"
2415 [(set (match_operand:DI 0 "register_operand" "=d")
2416 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2417 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2419 [(set_attr "op_type" "RXY")])
2421 (define_insn_and_split "*extendqidi2_short_displ"
2422 [(set (match_operand:DI 0 "register_operand" "=d")
2423 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2424 (clobber (reg:CC CC_REGNUM))]
2425 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2427 "&& reload_completed"
2429 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2430 (clobber (reg:CC CC_REGNUM))])
2432 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2433 (clobber (reg:CC CC_REGNUM))])]
2437 ; extend(hi|qi)si2 instruction pattern(s).
2440 (define_expand "extend<mode>si2"
2441 [(set (match_operand:SI 0 "register_operand" "")
2442 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2446 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2447 GET_MODE_BITSIZE(<MODE>mode));
2448 operands[1] = gen_lowpart (SImode, operands[1]);
2449 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2450 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2455 (define_insn "*extendhisi2"
2456 [(set (match_operand:SI 0 "register_operand" "=d,d")
2457 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2462 [(set_attr "op_type" "RX,RXY")])
2464 (define_insn "*extendqisi2"
2465 [(set (match_operand:SI 0 "register_operand" "=d")
2466 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2467 "TARGET_LONG_DISPLACEMENT"
2469 [(set_attr "op_type" "RXY")])
2471 (define_insn_and_split "*extendqisi2_short_displ"
2472 [(set (match_operand:SI 0 "register_operand" "=d")
2473 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2474 (clobber (reg:CC CC_REGNUM))]
2475 "!TARGET_LONG_DISPLACEMENT"
2477 "&& reload_completed"
2479 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2480 (clobber (reg:CC CC_REGNUM))])
2482 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2483 (clobber (reg:CC CC_REGNUM))])]
2487 ; extendqihi2 instruction pattern(s).
2492 ; zero_extendsidi2 instruction pattern(s).
2495 (define_expand "zero_extendsidi2"
2496 [(set (match_operand:DI 0 "register_operand" "")
2497 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2503 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2504 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2505 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2511 (define_insn "*zero_extendsidi2"
2512 [(set (match_operand:DI 0 "register_operand" "=d,d")
2513 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2518 [(set_attr "op_type" "RRE,RXY")])
2521 ; zero_extend(hi|qi)di2 instruction pattern(s).
2524 (define_expand "zero_extend<mode>di2"
2525 [(set (match_operand:DI 0 "register_operand" "")
2526 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2532 rtx tmp = gen_reg_rtx (SImode);
2533 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2534 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2539 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2540 GET_MODE_BITSIZE(<MODE>mode));
2541 operands[1] = gen_lowpart (DImode, operands[1]);
2542 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2543 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2549 (define_insn "*zero_extend<mode>di2"
2550 [(set (match_operand:DI 0 "register_operand" "=d")
2551 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2554 [(set_attr "op_type" "RXY")])
2557 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2560 (define_insn "*llgt_sidi"
2561 [(set (match_operand:DI 0 "register_operand" "=d")
2562 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2563 (const_int 2147483647)))]
2566 [(set_attr "op_type" "RXE")])
2568 (define_insn_and_split "*llgt_sidi_split"
2569 [(set (match_operand:DI 0 "register_operand" "=d")
2570 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2571 (const_int 2147483647)))
2572 (clobber (reg:CC CC_REGNUM))]
2575 "&& reload_completed"
2577 (and:DI (subreg:DI (match_dup 1) 0)
2578 (const_int 2147483647)))]
2581 (define_insn "*llgt_sisi"
2582 [(set (match_operand:SI 0 "register_operand" "=d,d")
2583 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2584 (const_int 2147483647)))]
2589 [(set_attr "op_type" "RRE,RXE")])
2591 (define_insn "*llgt_didi"
2592 [(set (match_operand:DI 0 "register_operand" "=d,d")
2593 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2594 (const_int 2147483647)))]
2599 [(set_attr "op_type" "RRE,RXE")])
2602 [(set (match_operand:GPR 0 "register_operand" "")
2603 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2604 (const_int 2147483647)))
2605 (clobber (reg:CC CC_REGNUM))]
2606 "TARGET_64BIT && reload_completed"
2608 (and:GPR (match_dup 1)
2609 (const_int 2147483647)))]
2613 ; zero_extend(hi|qi)si2 instruction pattern(s).
2616 (define_expand "zero_extend<mode>si2"
2617 [(set (match_operand:SI 0 "register_operand" "")
2618 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2622 operands[1] = gen_lowpart (SImode, operands[1]);
2623 emit_insn (gen_andsi3 (operands[0], operands[1],
2624 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2629 (define_insn "*zero_extend<mode>si2_64"
2630 [(set (match_operand:SI 0 "register_operand" "=d")
2631 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2634 [(set_attr "op_type" "RXY")])
2636 (define_insn_and_split "*zero_extendhisi2_31"
2637 [(set (match_operand:SI 0 "register_operand" "=&d")
2638 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2639 (clobber (reg:CC CC_REGNUM))]
2642 "&& reload_completed"
2643 [(set (match_dup 0) (const_int 0))
2645 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2646 (clobber (reg:CC CC_REGNUM))])]
2647 "operands[2] = gen_lowpart (HImode, operands[0]);")
2649 (define_insn_and_split "*zero_extendqisi2_31"
2650 [(set (match_operand:SI 0 "register_operand" "=&d")
2651 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2654 "&& reload_completed"
2655 [(set (match_dup 0) (const_int 0))
2656 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2657 "operands[2] = gen_lowpart (QImode, operands[0]);")
2660 ; zero_extendqihi2 instruction pattern(s).
2663 (define_expand "zero_extendqihi2"
2664 [(set (match_operand:HI 0 "register_operand" "")
2665 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2669 operands[1] = gen_lowpart (HImode, operands[1]);
2670 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2675 (define_insn "*zero_extendqihi2_64"
2676 [(set (match_operand:HI 0 "register_operand" "=d")
2677 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2680 [(set_attr "op_type" "RXY")])
2682 (define_insn_and_split "*zero_extendqihi2_31"
2683 [(set (match_operand:HI 0 "register_operand" "=&d")
2684 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2687 "&& reload_completed"
2688 [(set (match_dup 0) (const_int 0))
2689 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2690 "operands[2] = gen_lowpart (QImode, operands[0]);")
2694 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2697 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2698 [(set (match_operand:GPR 0 "register_operand" "")
2699 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2700 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2702 rtx label1 = gen_label_rtx ();
2703 rtx label2 = gen_label_rtx ();
2704 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2705 REAL_VALUE_TYPE cmp, sub;
2707 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2708 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2709 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2711 emit_insn (gen_cmp<FPR:mode> (operands[1],
2712 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2713 emit_jump_insn (gen_blt (label1));
2714 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2715 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2716 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2720 emit_label (label1);
2721 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2722 operands[1], GEN_INT(5)));
2723 emit_label (label2);
2727 (define_expand "fix_trunc<FPR:mode>di2"
2728 [(set (match_operand:DI 0 "register_operand" "")
2729 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2730 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2732 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2733 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2738 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2739 [(set (match_operand:GPR 0 "register_operand" "=d")
2740 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2741 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2742 (clobber (reg:CC CC_REGNUM))]
2743 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2744 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2745 [(set_attr "op_type" "RRE")
2746 (set_attr "type" "ftoi")])
2749 ; fix_truncdfsi2 instruction pattern(s).
2752 (define_expand "fix_truncdfsi2"
2753 [(set (match_operand:SI 0 "register_operand" "")
2754 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2757 if (TARGET_IBM_FLOAT)
2759 /* This is the algorithm from POP chapter A.5.7.2. */
2761 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2762 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2763 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2765 operands[1] = force_reg (DFmode, operands[1]);
2766 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2767 two31r, two32, temp));
2771 operands[1] = force_reg (DFmode, operands[1]);
2772 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2778 (define_insn "fix_truncdfsi2_ibm"
2779 [(set (match_operand:SI 0 "register_operand" "=d")
2780 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2781 (use (match_operand:DI 2 "immediate_operand" "m"))
2782 (use (match_operand:DI 3 "immediate_operand" "m"))
2783 (use (match_operand:BLK 4 "memory_operand" "m"))
2784 (clobber (reg:CC CC_REGNUM))]
2785 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2787 output_asm_insn ("sd\t%1,%2", operands);
2788 output_asm_insn ("aw\t%1,%3", operands);
2789 output_asm_insn ("std\t%1,%4", operands);
2790 output_asm_insn ("xi\t%N4,128", operands);
2793 [(set_attr "length" "20")])
2796 ; fix_truncsfsi2 instruction pattern(s).
2799 (define_expand "fix_truncsfsi2"
2800 [(set (match_operand:SI 0 "register_operand" "")
2801 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2804 if (TARGET_IBM_FLOAT)
2806 /* Convert to DFmode and then use the POP algorithm. */
2807 rtx temp = gen_reg_rtx (DFmode);
2808 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2809 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2813 operands[1] = force_reg (SFmode, operands[1]);
2814 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2821 ; floatdi(df|sf)2 instruction pattern(s).
2824 (define_insn "floatdi<mode>2"
2825 [(set (match_operand:FPR 0 "register_operand" "=f")
2826 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2827 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2829 [(set_attr "op_type" "RRE")
2830 (set_attr "type" "itof" )])
2833 ; floatsidf2 instruction pattern(s).
2836 (define_expand "floatsidf2"
2837 [(set (match_operand:DF 0 "register_operand" "")
2838 (float:DF (match_operand:SI 1 "register_operand" "")))]
2841 if (TARGET_IBM_FLOAT)
2843 /* This is the algorithm from POP chapter A.5.7.1. */
2845 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2846 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2848 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2853 (define_insn "floatsidf2_ieee"
2854 [(set (match_operand:DF 0 "register_operand" "=f")
2855 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2856 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2858 [(set_attr "op_type" "RRE")
2859 (set_attr "type" "itof" )])
2861 (define_insn "floatsidf2_ibm"
2862 [(set (match_operand:DF 0 "register_operand" "=f")
2863 (float:DF (match_operand:SI 1 "register_operand" "d")))
2864 (use (match_operand:DI 2 "immediate_operand" "m"))
2865 (use (match_operand:BLK 3 "memory_operand" "m"))
2866 (clobber (reg:CC CC_REGNUM))]
2867 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2869 output_asm_insn ("st\t%1,%N3", operands);
2870 output_asm_insn ("xi\t%N3,128", operands);
2871 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2872 output_asm_insn ("ld\t%0,%3", operands);
2875 [(set_attr "length" "20")])
2878 ; floatsisf2 instruction pattern(s).
2881 (define_expand "floatsisf2"
2882 [(set (match_operand:SF 0 "register_operand" "")
2883 (float:SF (match_operand:SI 1 "register_operand" "")))]
2886 if (TARGET_IBM_FLOAT)
2888 /* Use the POP algorithm to convert to DFmode and then truncate. */
2889 rtx temp = gen_reg_rtx (DFmode);
2890 emit_insn (gen_floatsidf2 (temp, operands[1]));
2891 emit_insn (gen_truncdfsf2 (operands[0], temp));
2896 (define_insn "floatsisf2_ieee"
2897 [(set (match_operand:SF 0 "register_operand" "=f")
2898 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2899 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2901 [(set_attr "op_type" "RRE")
2902 (set_attr "type" "itof" )])
2905 ; truncdfsf2 instruction pattern(s).
2908 (define_expand "truncdfsf2"
2909 [(set (match_operand:SF 0 "register_operand" "")
2910 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
2914 (define_insn "truncdfsf2_ieee"
2915 [(set (match_operand:SF 0 "register_operand" "=f")
2916 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2917 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2919 [(set_attr "op_type" "RRE")])
2921 (define_insn "truncdfsf2_ibm"
2922 [(set (match_operand:SF 0 "register_operand" "=f,f")
2923 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
2924 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2928 [(set_attr "op_type" "RR,RX")
2929 (set_attr "type" "floadsf")])
2932 ; extendsfdf2 instruction pattern(s).
2935 (define_expand "extendsfdf2"
2936 [(set (match_operand:DF 0 "register_operand" "")
2937 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2940 if (TARGET_IBM_FLOAT)
2942 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2947 (define_insn "extendsfdf2_ieee"
2948 [(set (match_operand:DF 0 "register_operand" "=f,f")
2949 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2950 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2954 [(set_attr "op_type" "RRE,RXE")
2955 (set_attr "type" "floadsf")])
2957 (define_insn "extendsfdf2_ibm"
2958 [(set (match_operand:DF 0 "register_operand" "=f,f")
2959 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2960 (clobber (reg:CC CC_REGNUM))]
2961 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2963 sdr\t%0,%0\;ler\t%0,%1
2964 sdr\t%0,%0\;le\t%0,%1"
2965 [(set_attr "length" "4,6")
2966 (set_attr "type" "floadsf")])
2970 ;; ARITHMETIC OPERATIONS
2972 ; arithmetic operations set the ConditionCode,
2973 ; because of unpredictable Bits in Register for Halfword and Byte
2974 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2977 ;;- Add instructions.
2981 ; addti3 instruction pattern(s).
2984 (define_insn_and_split "addti3"
2985 [(set (match_operand:TI 0 "register_operand" "=&d")
2986 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
2987 (match_operand:TI 2 "general_operand" "do") ) )
2988 (clobber (reg:CC CC_REGNUM))]
2991 "&& reload_completed"
2993 [(set (reg:CCL1 CC_REGNUM)
2994 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
2996 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
2998 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
2999 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3000 (clobber (reg:CC CC_REGNUM))])]
3001 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3002 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3003 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3004 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3005 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3006 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3009 ; adddi3 instruction pattern(s).
3012 (define_insn "*adddi3_sign"
3013 [(set (match_operand:DI 0 "register_operand" "=d,d")
3014 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3015 (match_operand:DI 1 "register_operand" "0,0")))
3016 (clobber (reg:CC CC_REGNUM))]
3021 [(set_attr "op_type" "RRE,RXY")])
3023 (define_insn "*adddi3_zero_cc"
3024 [(set (reg CC_REGNUM)
3025 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3026 (match_operand:DI 1 "register_operand" "0,0"))
3028 (set (match_operand:DI 0 "register_operand" "=d,d")
3029 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3030 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3034 [(set_attr "op_type" "RRE,RXY")])
3036 (define_insn "*adddi3_zero_cconly"
3037 [(set (reg CC_REGNUM)
3038 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3039 (match_operand:DI 1 "register_operand" "0,0"))
3041 (clobber (match_scratch:DI 0 "=d,d"))]
3042 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3046 [(set_attr "op_type" "RRE,RXY")])
3048 (define_insn "*adddi3_zero"
3049 [(set (match_operand:DI 0 "register_operand" "=d,d")
3050 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3051 (match_operand:DI 1 "register_operand" "0,0")))
3052 (clobber (reg:CC CC_REGNUM))]
3057 [(set_attr "op_type" "RRE,RXY")])
3059 (define_insn "*adddi3_imm_cc"
3060 [(set (reg CC_REGNUM)
3061 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3062 (match_operand:DI 2 "const_int_operand" "K"))
3064 (set (match_operand:DI 0 "register_operand" "=d")
3065 (plus:DI (match_dup 1) (match_dup 2)))]
3067 && s390_match_ccmode (insn, CCAmode)
3068 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3070 [(set_attr "op_type" "RI")])
3072 (define_insn "*adddi3_carry1_cc"
3073 [(set (reg CC_REGNUM)
3074 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3075 (match_operand:DI 2 "general_operand" "d,m"))
3077 (set (match_operand:DI 0 "register_operand" "=d,d")
3078 (plus:DI (match_dup 1) (match_dup 2)))]
3079 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3083 [(set_attr "op_type" "RRE,RXY")])
3085 (define_insn "*adddi3_carry1_cconly"
3086 [(set (reg CC_REGNUM)
3087 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3088 (match_operand:DI 2 "general_operand" "d,m"))
3090 (clobber (match_scratch:DI 0 "=d,d"))]
3091 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3095 [(set_attr "op_type" "RRE,RXY")])
3097 (define_insn "*adddi3_carry2_cc"
3098 [(set (reg CC_REGNUM)
3099 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3100 (match_operand:DI 2 "general_operand" "d,m"))
3102 (set (match_operand:DI 0 "register_operand" "=d,d")
3103 (plus:DI (match_dup 1) (match_dup 2)))]
3104 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3108 [(set_attr "op_type" "RRE,RXY")])
3110 (define_insn "*adddi3_carry2_cconly"
3111 [(set (reg CC_REGNUM)
3112 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3113 (match_operand:DI 2 "general_operand" "d,m"))
3115 (clobber (match_scratch:DI 0 "=d,d"))]
3116 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3120 [(set_attr "op_type" "RRE,RXY")])
3122 (define_insn "*adddi3_cc"
3123 [(set (reg CC_REGNUM)
3124 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3125 (match_operand:DI 2 "general_operand" "d,m"))
3127 (set (match_operand:DI 0 "register_operand" "=d,d")
3128 (plus:DI (match_dup 1) (match_dup 2)))]
3129 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3133 [(set_attr "op_type" "RRE,RXY")])
3135 (define_insn "*adddi3_cconly"
3136 [(set (reg CC_REGNUM)
3137 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3138 (match_operand:DI 2 "general_operand" "d,m"))
3140 (clobber (match_scratch:DI 0 "=d,d"))]
3141 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3145 [(set_attr "op_type" "RRE,RXY")])
3147 (define_insn "*adddi3_cconly2"
3148 [(set (reg CC_REGNUM)
3149 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3150 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3151 (clobber (match_scratch:DI 0 "=d,d"))]
3152 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3156 [(set_attr "op_type" "RRE,RXY")])
3158 (define_insn "*adddi3_64"
3159 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3160 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3161 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3162 (clobber (reg:CC CC_REGNUM))]
3168 [(set_attr "op_type" "RRE,RI,RXY")])
3170 (define_insn_and_split "*adddi3_31z"
3171 [(set (match_operand:DI 0 "register_operand" "=&d")
3172 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3173 (match_operand:DI 2 "general_operand" "do") ) )
3174 (clobber (reg:CC CC_REGNUM))]
3175 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3177 "&& reload_completed"
3179 [(set (reg:CCL1 CC_REGNUM)
3180 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3182 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3184 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3185 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3186 (clobber (reg:CC CC_REGNUM))])]
3187 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3188 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3189 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3190 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3191 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3192 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3194 (define_insn_and_split "*adddi3_31"
3195 [(set (match_operand:DI 0 "register_operand" "=&d")
3196 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3197 (match_operand:DI 2 "general_operand" "do") ) )
3198 (clobber (reg:CC CC_REGNUM))]
3201 "&& reload_completed"
3203 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3204 (clobber (reg:CC CC_REGNUM))])
3206 [(set (reg:CCL1 CC_REGNUM)
3207 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3209 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3211 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3213 (label_ref (match_dup 9))))
3215 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3216 (clobber (reg:CC CC_REGNUM))])
3218 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3219 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3220 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3221 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3222 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3223 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3224 operands[9] = gen_label_rtx ();")
3226 (define_expand "adddi3"
3228 [(set (match_operand:DI 0 "register_operand" "")
3229 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3230 (match_operand:DI 2 "general_operand" "")))
3231 (clobber (reg:CC CC_REGNUM))])]
3236 ; addsi3 instruction pattern(s).
3239 (define_insn "*addsi3_imm_cc"
3240 [(set (reg CC_REGNUM)
3241 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3242 (match_operand:SI 2 "const_int_operand" "K"))
3244 (set (match_operand:SI 0 "register_operand" "=d")
3245 (plus:SI (match_dup 1) (match_dup 2)))]
3246 "s390_match_ccmode (insn, CCAmode)
3247 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3249 [(set_attr "op_type" "RI")])
3251 (define_insn "*addsi3_carry1_cc"
3252 [(set (reg CC_REGNUM)
3253 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3254 (match_operand:SI 2 "general_operand" "d,R,T"))
3256 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3257 (plus:SI (match_dup 1) (match_dup 2)))]
3258 "s390_match_ccmode (insn, CCL1mode)"
3263 [(set_attr "op_type" "RR,RX,RXY")])
3265 (define_insn "*addsi3_carry1_cconly"
3266 [(set (reg CC_REGNUM)
3267 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3268 (match_operand:SI 2 "general_operand" "d,R,T"))
3270 (clobber (match_scratch:SI 0 "=d,d,d"))]
3271 "s390_match_ccmode (insn, CCL1mode)"
3276 [(set_attr "op_type" "RR,RX,RXY")])
3278 (define_insn "*addsi3_carry2_cc"
3279 [(set (reg CC_REGNUM)
3280 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3281 (match_operand:SI 2 "general_operand" "d,R,T"))
3283 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3284 (plus:SI (match_dup 1) (match_dup 2)))]
3285 "s390_match_ccmode (insn, CCL1mode)"
3290 [(set_attr "op_type" "RR,RX,RXY")])
3292 (define_insn "*addsi3_carry2_cconly"
3293 [(set (reg CC_REGNUM)
3294 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3295 (match_operand:SI 2 "general_operand" "d,R,T"))
3297 (clobber (match_scratch:SI 0 "=d,d,d"))]
3298 "s390_match_ccmode (insn, CCL1mode)"
3303 [(set_attr "op_type" "RR,RX,RXY")])
3305 (define_insn "*addsi3_cc"
3306 [(set (reg CC_REGNUM)
3307 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3308 (match_operand:SI 2 "general_operand" "d,R,T"))
3310 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3311 (plus:SI (match_dup 1) (match_dup 2)))]
3312 "s390_match_ccmode (insn, CCLmode)"
3317 [(set_attr "op_type" "RR,RX,RXY")])
3319 (define_insn "*addsi3_cconly"
3320 [(set (reg CC_REGNUM)
3321 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3322 (match_operand:SI 2 "general_operand" "d,R,T"))
3324 (clobber (match_scratch:SI 0 "=d,d,d"))]
3325 "s390_match_ccmode (insn, CCLmode)"
3330 [(set_attr "op_type" "RR,RX,RXY")])
3332 (define_insn "*addsi3_cconly2"
3333 [(set (reg CC_REGNUM)
3334 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3335 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3336 (clobber (match_scratch:SI 0 "=d,d,d"))]
3337 "s390_match_ccmode (insn, CCLmode)"
3342 [(set_attr "op_type" "RR,RX,RXY")])
3344 (define_insn "*addsi3_sign"
3345 [(set (match_operand:SI 0 "register_operand" "=d,d")
3346 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3347 (match_operand:SI 1 "register_operand" "0,0")))
3348 (clobber (reg:CC CC_REGNUM))]
3353 [(set_attr "op_type" "RX,RXY")])
3355 (define_insn "addsi3"
3356 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3357 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3358 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3359 (clobber (reg:CC CC_REGNUM))]
3366 [(set_attr "op_type" "RR,RI,RX,RXY")])
3369 ; add(df|sf)3 instruction pattern(s).
3372 (define_expand "add<mode>3"
3374 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3375 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3376 (match_operand:FPR 2 "general_operand" "f,R")))
3377 (clobber (reg:CC CC_REGNUM))])]
3381 (define_insn "*add<mode>3"
3382 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3383 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3384 (match_operand:FPR 2 "general_operand" "f,R")))
3385 (clobber (reg:CC CC_REGNUM))]
3386 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3390 [(set_attr "op_type" "RRE,RXE")
3391 (set_attr "type" "fsimp<mode>")])
3393 (define_insn "*add<mode>3_cc"
3394 [(set (reg CC_REGNUM)
3395 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3396 (match_operand:FPR 2 "general_operand" "f,R"))
3397 (match_operand:FPR 3 "const0_operand" "")))
3398 (set (match_operand:FPR 0 "register_operand" "=f,f")
3399 (plus:FPR (match_dup 1) (match_dup 2)))]
3400 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3404 [(set_attr "op_type" "RRE,RXE")
3405 (set_attr "type" "fsimp<mode>")])
3407 (define_insn "*add<mode>3_cconly"
3408 [(set (reg CC_REGNUM)
3409 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3410 (match_operand:FPR 2 "general_operand" "f,R"))
3411 (match_operand:FPR 3 "const0_operand" "")))
3412 (clobber (match_scratch:FPR 0 "=f,f"))]
3413 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3417 [(set_attr "op_type" "RRE,RXE")
3418 (set_attr "type" "fsimp<mode>")])
3420 (define_insn "*add<mode>3_ibm"
3421 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3422 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3423 (match_operand:FPR 2 "general_operand" "f,R")))
3424 (clobber (reg:CC CC_REGNUM))]
3425 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3429 [(set_attr "op_type" "RR,RX")
3430 (set_attr "type" "fsimp<mode>")])
3434 ;;- Subtract instructions.
3438 ; subti3 instruction pattern(s).
3441 (define_insn_and_split "subti3"
3442 [(set (match_operand:TI 0 "register_operand" "=&d")
3443 (minus:TI (match_operand:TI 1 "register_operand" "0")
3444 (match_operand:TI 2 "general_operand" "do") ) )
3445 (clobber (reg:CC CC_REGNUM))]
3448 "&& reload_completed"
3450 [(set (reg:CCL2 CC_REGNUM)
3451 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3453 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3455 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3456 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3457 (clobber (reg:CC CC_REGNUM))])]
3458 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3459 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3460 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3461 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3462 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3463 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3466 ; subdi3 instruction pattern(s).
3469 (define_insn "*subdi3_sign"
3470 [(set (match_operand:DI 0 "register_operand" "=d,d")
3471 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3472 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3473 (clobber (reg:CC CC_REGNUM))]
3478 [(set_attr "op_type" "RRE,RXY")])
3480 (define_insn "*subdi3_zero_cc"
3481 [(set (reg CC_REGNUM)
3482 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3483 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3485 (set (match_operand:DI 0 "register_operand" "=d,d")
3486 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3487 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3491 [(set_attr "op_type" "RRE,RXY")])
3493 (define_insn "*subdi3_zero_cconly"
3494 [(set (reg CC_REGNUM)
3495 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3496 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3498 (clobber (match_scratch:DI 0 "=d,d"))]
3499 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3503 [(set_attr "op_type" "RRE,RXY")])
3505 (define_insn "*subdi3_zero"
3506 [(set (match_operand:DI 0 "register_operand" "=d,d")
3507 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3508 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3509 (clobber (reg:CC CC_REGNUM))]
3514 [(set_attr "op_type" "RRE,RXY")])
3516 (define_insn "*subdi3_borrow_cc"
3517 [(set (reg CC_REGNUM)
3518 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3519 (match_operand:DI 2 "general_operand" "d,m"))
3521 (set (match_operand:DI 0 "register_operand" "=d,d")
3522 (minus:DI (match_dup 1) (match_dup 2)))]
3523 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3527 [(set_attr "op_type" "RRE,RXY")])
3529 (define_insn "*subdi3_borrow_cconly"
3530 [(set (reg CC_REGNUM)
3531 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3532 (match_operand:DI 2 "general_operand" "d,m"))
3534 (clobber (match_scratch:DI 0 "=d,d"))]
3535 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3539 [(set_attr "op_type" "RRE,RXY")])
3541 (define_insn "*subdi3_cc"
3542 [(set (reg CC_REGNUM)
3543 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3544 (match_operand:DI 2 "general_operand" "d,m"))
3546 (set (match_operand:DI 0 "register_operand" "=d,d")
3547 (minus:DI (match_dup 1) (match_dup 2)))]
3548 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3552 [(set_attr "op_type" "RRE,RXY")])
3554 (define_insn "*subdi3_cc2"
3555 [(set (reg CC_REGNUM)
3556 (compare (match_operand:DI 1 "register_operand" "0,0")
3557 (match_operand:DI 2 "general_operand" "d,m")))
3558 (set (match_operand:DI 0 "register_operand" "=d,d")
3559 (minus:DI (match_dup 1) (match_dup 2)))]
3560 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3564 [(set_attr "op_type" "RRE,RXY")])
3566 (define_insn "*subdi3_cconly"
3567 [(set (reg CC_REGNUM)
3568 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3569 (match_operand:DI 2 "general_operand" "d,m"))
3571 (clobber (match_scratch:DI 0 "=d,d"))]
3572 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3576 [(set_attr "op_type" "RRE,RXY")])
3578 (define_insn "*subdi3_cconly2"
3579 [(set (reg CC_REGNUM)
3580 (compare (match_operand:DI 1 "register_operand" "0,0")
3581 (match_operand:DI 2 "general_operand" "d,m")))
3582 (clobber (match_scratch:DI 0 "=d,d"))]
3583 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3587 [(set_attr "op_type" "RRE,RXY")])
3589 (define_insn "*subdi3_64"
3590 [(set (match_operand:DI 0 "register_operand" "=d,d")
3591 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3592 (match_operand:DI 2 "general_operand" "d,m") ) )
3593 (clobber (reg:CC CC_REGNUM))]
3598 [(set_attr "op_type" "RRE,RRE")])
3600 (define_insn_and_split "*subdi3_31z"
3601 [(set (match_operand:DI 0 "register_operand" "=&d")
3602 (minus:DI (match_operand:DI 1 "register_operand" "0")
3603 (match_operand:DI 2 "general_operand" "do") ) )
3604 (clobber (reg:CC CC_REGNUM))]
3605 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3607 "&& reload_completed"
3609 [(set (reg:CCL2 CC_REGNUM)
3610 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3612 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3614 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3615 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3616 (clobber (reg:CC CC_REGNUM))])]
3617 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3618 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3619 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3620 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3621 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3622 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3624 (define_insn_and_split "*subdi3_31"
3625 [(set (match_operand:DI 0 "register_operand" "=&d")
3626 (minus:DI (match_operand:DI 1 "register_operand" "0")
3627 (match_operand:DI 2 "general_operand" "do") ) )
3628 (clobber (reg:CC CC_REGNUM))]
3631 "&& reload_completed"
3633 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3634 (clobber (reg:CC CC_REGNUM))])
3636 [(set (reg:CCL2 CC_REGNUM)
3637 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3639 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3641 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3643 (label_ref (match_dup 9))))
3645 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3646 (clobber (reg:CC CC_REGNUM))])
3648 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3649 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3650 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3651 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3652 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3653 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3654 operands[9] = gen_label_rtx ();")
3656 (define_expand "subdi3"
3658 [(set (match_operand:DI 0 "register_operand" "")
3659 (minus:DI (match_operand:DI 1 "register_operand" "")
3660 (match_operand:DI 2 "general_operand" "")))
3661 (clobber (reg:CC CC_REGNUM))])]
3666 ; subsi3 instruction pattern(s).
3669 (define_insn "*subsi3_borrow_cc"
3670 [(set (reg CC_REGNUM)
3671 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3672 (match_operand:SI 2 "general_operand" "d,R,T"))
3674 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3675 (minus:SI (match_dup 1) (match_dup 2)))]
3676 "s390_match_ccmode (insn, CCL2mode)"
3681 [(set_attr "op_type" "RR,RX,RXY")])
3683 (define_insn "*subsi3_borrow_cconly"
3684 [(set (reg CC_REGNUM)
3685 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3686 (match_operand:SI 2 "general_operand" "d,R,T"))
3688 (clobber (match_scratch:SI 0 "=d,d,d"))]
3689 "s390_match_ccmode (insn, CCL2mode)"
3694 [(set_attr "op_type" "RR,RX,RXY")])
3696 (define_insn "*subsi3_cc"
3697 [(set (reg CC_REGNUM)
3698 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3699 (match_operand:SI 2 "general_operand" "d,R,T"))
3701 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3702 (minus:SI (match_dup 1) (match_dup 2)))]
3703 "s390_match_ccmode (insn, CCLmode)"
3708 [(set_attr "op_type" "RR,RX,RXY")])
3710 (define_insn "*subsi3_cc2"
3711 [(set (reg CC_REGNUM)
3712 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3713 (match_operand:SI 2 "general_operand" "d,R,T")))
3714 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3715 (minus:SI (match_dup 1) (match_dup 2)))]
3716 "s390_match_ccmode (insn, CCL3mode)"
3721 [(set_attr "op_type" "RR,RX,RXY")])
3723 (define_insn "*subsi3_cconly"
3724 [(set (reg CC_REGNUM)
3725 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3726 (match_operand:SI 2 "general_operand" "d,R,T"))
3728 (clobber (match_scratch:SI 0 "=d,d,d"))]
3729 "s390_match_ccmode (insn, CCLmode)"
3734 [(set_attr "op_type" "RR,RX,RXY")])
3736 (define_insn "*subsi3_cconly2"
3737 [(set (reg CC_REGNUM)
3738 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3739 (match_operand:SI 2 "general_operand" "d,R,T")))
3740 (clobber (match_scratch:SI 0 "=d,d,d"))]
3741 "s390_match_ccmode (insn, CCL3mode)"
3746 [(set_attr "op_type" "RR,RX,RXY")])
3748 (define_insn "*subsi3_sign"
3749 [(set (match_operand:SI 0 "register_operand" "=d,d")
3750 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3751 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3752 (clobber (reg:CC CC_REGNUM))]
3757 [(set_attr "op_type" "RX,RXY")])
3759 (define_insn "subsi3"
3760 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3761 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3762 (match_operand:SI 2 "general_operand" "d,R,T")))
3763 (clobber (reg:CC CC_REGNUM))]
3769 [(set_attr "op_type" "RR,RX,RXY")])
3773 ; sub(df|sf)3 instruction pattern(s).
3776 (define_expand "sub<mode>3"
3778 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3779 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3780 (match_operand:FPR 2 "general_operand" "f,R")))
3781 (clobber (reg:CC CC_REGNUM))])]
3785 (define_insn "*sub<mode>3"
3786 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3787 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3788 (match_operand:FPR 2 "general_operand" "f,R")))
3789 (clobber (reg:CC CC_REGNUM))]
3790 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3794 [(set_attr "op_type" "RRE,RXE")
3795 (set_attr "type" "fsimp<mode>")])
3797 (define_insn "*sub<mode>3_cc"
3798 [(set (reg CC_REGNUM)
3799 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3800 (match_operand:FPR 2 "general_operand" "f,R"))
3801 (match_operand:FPR 3 "const0_operand" "")))
3802 (set (match_operand:FPR 0 "register_operand" "=f,f")
3803 (minus:FPR (match_dup 1) (match_dup 2)))]
3804 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3808 [(set_attr "op_type" "RRE,RXE")
3809 (set_attr "type" "fsimp<mode>")])
3811 (define_insn "*sub<mode>3_cconly"
3812 [(set (reg CC_REGNUM)
3813 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3814 (match_operand:FPR 2 "general_operand" "f,R"))
3815 (match_operand:FPR 3 "const0_operand" "")))
3816 (clobber (match_scratch:FPR 0 "=f,f"))]
3817 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3821 [(set_attr "op_type" "RRE,RXE")
3822 (set_attr "type" "fsimp<mode>")])
3824 (define_insn "*sub<mode>3_ibm"
3825 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3826 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3827 (match_operand:FPR 2 "general_operand" "f,R")))
3828 (clobber (reg:CC CC_REGNUM))]
3829 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3833 [(set_attr "op_type" "RR,RX")
3834 (set_attr "type" "fsimp<mode>")])
3838 ;;- Conditional add/subtract instructions.
3842 ; add(di|si)cc instruction pattern(s).
3845 (define_insn "*add<mode>3_alc_cc"
3846 [(set (reg CC_REGNUM)
3848 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3849 (match_operand:GPR 2 "general_operand" "d,m"))
3850 (match_operand:GPR 3 "s390_alc_comparison" ""))
3852 (set (match_operand:GPR 0 "register_operand" "=d,d")
3853 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3854 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3858 [(set_attr "op_type" "RRE,RXY")])
3860 (define_insn "*add<mode>3_alc"
3861 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3862 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3863 (match_operand:GPR 2 "general_operand" "d,m"))
3864 (match_operand:GPR 3 "s390_alc_comparison" "")))
3865 (clobber (reg:CC CC_REGNUM))]
3870 [(set_attr "op_type" "RRE,RXY")])
3872 (define_insn "*sub<mode>3_slb_cc"
3873 [(set (reg CC_REGNUM)
3875 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3876 (match_operand:GPR 2 "general_operand" "d,m"))
3877 (match_operand:GPR 3 "s390_slb_comparison" ""))
3879 (set (match_operand:GPR 0 "register_operand" "=d,d")
3880 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3881 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3885 [(set_attr "op_type" "RRE,RXY")])
3887 (define_insn "*sub<mode>3_slb"
3888 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3889 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3890 (match_operand:GPR 2 "general_operand" "d,m"))
3891 (match_operand:GPR 3 "s390_slb_comparison" "")))
3892 (clobber (reg:CC CC_REGNUM))]
3897 [(set_attr "op_type" "RRE,RXY")])
3899 (define_expand "add<mode>cc"
3900 [(match_operand:GPR 0 "register_operand" "")
3901 (match_operand 1 "comparison_operator" "")
3902 (match_operand:GPR 2 "register_operand" "")
3903 (match_operand:GPR 3 "const_int_operand" "")]
3905 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3906 s390_compare_op0, s390_compare_op1,
3907 operands[0], operands[2],
3908 operands[3])) FAIL; DONE;")
3911 ; scond instruction pattern(s).
3914 (define_insn_and_split "*scond<mode>"
3915 [(set (match_operand:GPR 0 "register_operand" "=&d")
3916 (match_operand:GPR 1 "s390_alc_comparison" ""))
3917 (clobber (reg:CC CC_REGNUM))]
3920 "&& reload_completed"
3921 [(set (match_dup 0) (const_int 0))
3923 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
3925 (clobber (reg:CC CC_REGNUM))])]
3928 (define_insn_and_split "*scond<mode>_neg"
3929 [(set (match_operand:GPR 0 "register_operand" "=&d")
3930 (match_operand:GPR 1 "s390_slb_comparison" ""))
3931 (clobber (reg:CC CC_REGNUM))]
3934 "&& reload_completed"
3935 [(set (match_dup 0) (const_int 0))
3937 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
3939 (clobber (reg:CC CC_REGNUM))])
3941 [(set (match_dup 0) (neg:GPR (match_dup 0)))
3942 (clobber (reg:CC CC_REGNUM))])]
3946 (define_expand "s<code>"
3947 [(set (match_operand:SI 0 "register_operand" "")
3948 (SCOND (match_dup 0)
3951 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
3952 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
3956 ;;- Multiply instructions.
3960 ; muldi3 instruction pattern(s).
3963 (define_insn "*muldi3_sign"
3964 [(set (match_operand:DI 0 "register_operand" "=d,d")
3965 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3966 (match_operand:DI 1 "register_operand" "0,0")))]
3971 [(set_attr "op_type" "RRE,RXY")
3972 (set_attr "type" "imuldi")])
3974 (define_insn "muldi3"
3975 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3976 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3977 (match_operand:DI 2 "general_operand" "d,K,m")))]
3983 [(set_attr "op_type" "RRE,RI,RXY")
3984 (set_attr "type" "imuldi")])
3987 ; mulsi3 instruction pattern(s).
3990 (define_insn "*mulsi3_sign"
3991 [(set (match_operand:SI 0 "register_operand" "=d")
3992 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
3993 (match_operand:SI 1 "register_operand" "0")))]
3996 [(set_attr "op_type" "RX")
3997 (set_attr "type" "imulhi")])
3999 (define_insn "mulsi3"
4000 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4001 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4002 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4009 [(set_attr "op_type" "RRE,RI,RX,RXY")
4010 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4013 ; mulsidi3 instruction pattern(s).
4016 (define_insn "mulsidi3"
4017 [(set (match_operand:DI 0 "register_operand" "=d,d")
4018 (mult:DI (sign_extend:DI
4019 (match_operand:SI 1 "register_operand" "%0,0"))
4021 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4026 [(set_attr "op_type" "RR,RX")
4027 (set_attr "type" "imulsi")])
4030 ; umulsidi3 instruction pattern(s).
4033 (define_insn "umulsidi3"
4034 [(set (match_operand:DI 0 "register_operand" "=d,d")
4035 (mult:DI (zero_extend:DI
4036 (match_operand:SI 1 "register_operand" "%0,0"))
4038 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4039 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4043 [(set_attr "op_type" "RRE,RXY")
4044 (set_attr "type" "imulsi")])
4047 ; mul(df|sf)3 instruction pattern(s).
4050 (define_expand "mul<mode>3"
4051 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4052 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4053 (match_operand:FPR 2 "general_operand" "f,R")))]
4057 (define_insn "*mul<mode>3"
4058 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4059 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4060 (match_operand:FPR 2 "general_operand" "f,R")))]
4061 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4065 [(set_attr "op_type" "RRE,RXE")
4066 (set_attr "type" "fmul<mode>")])
4068 (define_insn "*mul<mode>3_ibm"
4069 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4070 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4071 (match_operand:FPR 2 "general_operand" "f,R")))]
4072 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4076 [(set_attr "op_type" "RR,RX")
4077 (set_attr "type" "fmul<mode>")])
4079 (define_insn "*fmadd<mode>"
4080 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4081 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4082 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4083 (match_operand:FPR 3 "register_operand" "0,0")))]
4084 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4088 [(set_attr "op_type" "RRE,RXE")
4089 (set_attr "type" "fmul<mode>")])
4091 (define_insn "*fmsub<mode>"
4092 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4093 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4094 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4095 (match_operand:FPR 3 "register_operand" "0,0")))]
4096 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4100 [(set_attr "op_type" "RRE,RXE")
4101 (set_attr "type" "fmul<mode>")])
4104 ;;- Divide and modulo instructions.
4108 ; divmoddi4 instruction pattern(s).
4111 (define_expand "divmoddi4"
4112 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4113 (div:DI (match_operand:DI 1 "register_operand" "")
4114 (match_operand:DI 2 "general_operand" "")))
4115 (set (match_operand:DI 3 "general_operand" "")
4116 (mod:DI (match_dup 1) (match_dup 2)))])
4117 (clobber (match_dup 4))]
4120 rtx insn, div_equal, mod_equal;
4122 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4123 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4125 operands[4] = gen_reg_rtx(TImode);
4126 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4128 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4130 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4132 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4134 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4139 (define_insn "divmodtidi3"
4140 [(set (match_operand:TI 0 "register_operand" "=d,d")
4144 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4145 (match_operand:DI 2 "general_operand" "d,m")))
4147 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4152 [(set_attr "op_type" "RRE,RXY")
4153 (set_attr "type" "idiv")])
4155 (define_insn "divmodtisi3"
4156 [(set (match_operand:TI 0 "register_operand" "=d,d")
4160 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4162 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4165 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4170 [(set_attr "op_type" "RRE,RXY")
4171 (set_attr "type" "idiv")])
4174 ; udivmoddi4 instruction pattern(s).
4177 (define_expand "udivmoddi4"
4178 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4179 (udiv:DI (match_operand:DI 1 "general_operand" "")
4180 (match_operand:DI 2 "nonimmediate_operand" "")))
4181 (set (match_operand:DI 3 "general_operand" "")
4182 (umod:DI (match_dup 1) (match_dup 2)))])
4183 (clobber (match_dup 4))]
4186 rtx insn, div_equal, mod_equal, equal;
4188 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4189 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4190 equal = gen_rtx_IOR (TImode,
4191 gen_rtx_ASHIFT (TImode,
4192 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4194 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4196 operands[4] = gen_reg_rtx(TImode);
4197 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4198 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4199 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4200 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4202 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4204 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4206 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4208 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4210 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4215 (define_insn "udivmodtidi3"
4216 [(set (match_operand:TI 0 "register_operand" "=d,d")
4221 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4223 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4227 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4232 [(set_attr "op_type" "RRE,RXY")
4233 (set_attr "type" "idiv")])
4236 ; divmodsi4 instruction pattern(s).
4239 (define_expand "divmodsi4"
4240 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4241 (div:SI (match_operand:SI 1 "general_operand" "")
4242 (match_operand:SI 2 "nonimmediate_operand" "")))
4243 (set (match_operand:SI 3 "general_operand" "")
4244 (mod:SI (match_dup 1) (match_dup 2)))])
4245 (clobber (match_dup 4))]
4248 rtx insn, div_equal, mod_equal, equal;
4250 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4251 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4252 equal = gen_rtx_IOR (DImode,
4253 gen_rtx_ASHIFT (DImode,
4254 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4256 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4258 operands[4] = gen_reg_rtx(DImode);
4259 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4260 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4262 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4264 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4266 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4268 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4270 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4275 (define_insn "divmoddisi3"
4276 [(set (match_operand:DI 0 "register_operand" "=d,d")
4281 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4283 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4287 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4292 [(set_attr "op_type" "RR,RX")
4293 (set_attr "type" "idiv")])
4296 ; udivsi3 and umodsi3 instruction pattern(s).
4299 (define_expand "udivmodsi4"
4300 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4301 (udiv:SI (match_operand:SI 1 "general_operand" "")
4302 (match_operand:SI 2 "nonimmediate_operand" "")))
4303 (set (match_operand:SI 3 "general_operand" "")
4304 (umod:SI (match_dup 1) (match_dup 2)))])
4305 (clobber (match_dup 4))]
4306 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4308 rtx insn, div_equal, mod_equal, equal;
4310 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4311 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4312 equal = gen_rtx_IOR (DImode,
4313 gen_rtx_ASHIFT (DImode,
4314 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4316 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4318 operands[4] = gen_reg_rtx(DImode);
4319 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4320 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4321 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4322 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4324 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4326 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4328 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4330 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4332 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4337 (define_insn "udivmoddisi3"
4338 [(set (match_operand:DI 0 "register_operand" "=d,d")
4343 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4345 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4349 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4350 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4354 [(set_attr "op_type" "RRE,RXY")
4355 (set_attr "type" "idiv")])
4357 (define_expand "udivsi3"
4358 [(set (match_operand:SI 0 "register_operand" "=d")
4359 (udiv:SI (match_operand:SI 1 "general_operand" "")
4360 (match_operand:SI 2 "general_operand" "")))
4361 (clobber (match_dup 3))]
4362 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4364 rtx insn, udiv_equal, umod_equal, equal;
4366 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4367 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4368 equal = gen_rtx_IOR (DImode,
4369 gen_rtx_ASHIFT (DImode,
4370 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4372 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4374 operands[3] = gen_reg_rtx (DImode);
4376 if (CONSTANT_P (operands[2]))
4378 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4380 rtx label1 = gen_label_rtx ();
4382 operands[1] = make_safe_from (operands[1], operands[0]);
4383 emit_move_insn (operands[0], const0_rtx);
4384 emit_insn (gen_cmpsi (operands[1], operands[2]));
4385 emit_jump_insn (gen_bltu (label1));
4386 emit_move_insn (operands[0], const1_rtx);
4387 emit_label (label1);
4391 operands[2] = force_reg (SImode, operands[2]);
4392 operands[2] = make_safe_from (operands[2], operands[0]);
4394 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4395 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4398 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4400 insn = emit_move_insn (operands[0],
4401 gen_lowpart (SImode, operands[3]));
4403 gen_rtx_EXPR_LIST (REG_EQUAL,
4404 udiv_equal, REG_NOTES (insn));
4409 rtx label1 = gen_label_rtx ();
4410 rtx label2 = gen_label_rtx ();
4411 rtx label3 = gen_label_rtx ();
4413 operands[1] = force_reg (SImode, operands[1]);
4414 operands[1] = make_safe_from (operands[1], operands[0]);
4415 operands[2] = force_reg (SImode, operands[2]);
4416 operands[2] = make_safe_from (operands[2], operands[0]);
4418 emit_move_insn (operands[0], const0_rtx);
4419 emit_insn (gen_cmpsi (operands[2], operands[1]));
4420 emit_jump_insn (gen_bgtu (label3));
4421 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4422 emit_jump_insn (gen_blt (label2));
4423 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4424 emit_jump_insn (gen_beq (label1));
4425 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4426 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4429 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4431 insn = emit_move_insn (operands[0],
4432 gen_lowpart (SImode, operands[3]));
4434 gen_rtx_EXPR_LIST (REG_EQUAL,
4435 udiv_equal, REG_NOTES (insn));
4437 emit_label (label1);
4438 emit_move_insn (operands[0], operands[1]);
4440 emit_label (label2);
4441 emit_move_insn (operands[0], const1_rtx);
4442 emit_label (label3);
4444 emit_move_insn (operands[0], operands[0]);
4448 (define_expand "umodsi3"
4449 [(set (match_operand:SI 0 "register_operand" "=d")
4450 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4451 (match_operand:SI 2 "nonimmediate_operand" "")))
4452 (clobber (match_dup 3))]
4453 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4455 rtx insn, udiv_equal, umod_equal, equal;
4457 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4458 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4459 equal = gen_rtx_IOR (DImode,
4460 gen_rtx_ASHIFT (DImode,
4461 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4463 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4465 operands[3] = gen_reg_rtx (DImode);
4467 if (CONSTANT_P (operands[2]))
4469 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4471 rtx label1 = gen_label_rtx ();
4473 operands[1] = make_safe_from (operands[1], operands[0]);
4474 emit_move_insn (operands[0], operands[1]);
4475 emit_insn (gen_cmpsi (operands[0], operands[2]));
4476 emit_jump_insn (gen_bltu (label1));
4477 emit_insn (gen_abssi2 (operands[0], operands[2]));
4478 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4479 emit_label (label1);
4483 operands[2] = force_reg (SImode, operands[2]);
4484 operands[2] = make_safe_from (operands[2], operands[0]);
4486 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4487 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4490 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4492 insn = emit_move_insn (operands[0],
4493 gen_highpart (SImode, operands[3]));
4495 gen_rtx_EXPR_LIST (REG_EQUAL,
4496 umod_equal, REG_NOTES (insn));
4501 rtx label1 = gen_label_rtx ();
4502 rtx label2 = gen_label_rtx ();
4503 rtx label3 = gen_label_rtx ();
4505 operands[1] = force_reg (SImode, operands[1]);
4506 operands[1] = make_safe_from (operands[1], operands[0]);
4507 operands[2] = force_reg (SImode, operands[2]);
4508 operands[2] = make_safe_from (operands[2], operands[0]);
4510 emit_move_insn(operands[0], operands[1]);
4511 emit_insn (gen_cmpsi (operands[2], operands[1]));
4512 emit_jump_insn (gen_bgtu (label3));
4513 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4514 emit_jump_insn (gen_blt (label2));
4515 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4516 emit_jump_insn (gen_beq (label1));
4517 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4518 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4521 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4523 insn = emit_move_insn (operands[0],
4524 gen_highpart (SImode, operands[3]));
4526 gen_rtx_EXPR_LIST (REG_EQUAL,
4527 umod_equal, REG_NOTES (insn));
4529 emit_label (label1);
4530 emit_move_insn (operands[0], const0_rtx);
4532 emit_label (label2);
4533 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4534 emit_label (label3);
4540 ; div(df|sf)3 instruction pattern(s).
4543 (define_expand "div<mode>3"
4544 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4545 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4546 (match_operand:FPR 2 "general_operand" "f,R")))]
4550 (define_insn "*div<mode>3"
4551 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4552 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4553 (match_operand:FPR 2 "general_operand" "f,R")))]
4554 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4558 [(set_attr "op_type" "RRE,RXE")
4559 (set_attr "type" "fdiv<mode>")])
4561 (define_insn "*div<mode>3_ibm"
4562 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4563 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4564 (match_operand:FPR 2 "general_operand" "f,R")))]
4565 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4569 [(set_attr "op_type" "RR,RX")
4570 (set_attr "type" "fdiv<mode>")])
4574 ;;- And instructions.
4577 (define_expand "and<mode>3"
4578 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4579 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4580 (match_operand:INT 2 "general_operand" "")))
4581 (clobber (reg:CC CC_REGNUM))]
4583 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4586 ; anddi3 instruction pattern(s).
4589 (define_insn "*anddi3_cc"
4590 [(set (reg CC_REGNUM)
4591 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4592 (match_operand:DI 2 "general_operand" "d,m"))
4594 (set (match_operand:DI 0 "register_operand" "=d,d")
4595 (and:DI (match_dup 1) (match_dup 2)))]
4596 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4600 [(set_attr "op_type" "RRE,RXY")])
4602 (define_insn "*anddi3_cconly"
4603 [(set (reg CC_REGNUM)
4604 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4605 (match_operand:DI 2 "general_operand" "d,m"))
4607 (clobber (match_scratch:DI 0 "=d,d"))]
4608 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4609 /* Do not steal TM patterns. */
4610 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4614 [(set_attr "op_type" "RRE,RXY")])
4616 (define_insn "*anddi3"
4617 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4618 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4619 "%d,o,0,0,0,0,0,0,0,0")
4620 (match_operand:DI 2 "general_operand"
4621 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4622 (clobber (reg:CC CC_REGNUM))]
4623 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4635 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4638 [(set (match_operand:DI 0 "s_operand" "")
4639 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4640 (clobber (reg:CC CC_REGNUM))]
4643 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4644 (clobber (reg:CC CC_REGNUM))])]
4645 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4649 ; andsi3 instruction pattern(s).
4652 (define_insn "*andsi3_cc"
4653 [(set (reg CC_REGNUM)
4654 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4655 (match_operand:SI 2 "general_operand" "d,R,T"))
4657 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4658 (and:SI (match_dup 1) (match_dup 2)))]
4659 "s390_match_ccmode(insn, CCTmode)"
4664 [(set_attr "op_type" "RR,RX,RXY")])
4666 (define_insn "*andsi3_cconly"
4667 [(set (reg CC_REGNUM)
4668 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4669 (match_operand:SI 2 "general_operand" "d,R,T"))
4671 (clobber (match_scratch:SI 0 "=d,d,d"))]
4672 "s390_match_ccmode(insn, CCTmode)
4673 /* Do not steal TM patterns. */
4674 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4679 [(set_attr "op_type" "RR,RX,RXY")])
4681 (define_insn "*andsi3_zarch"
4682 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4683 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4684 "%d,o,0,0,0,0,0,0,0")
4685 (match_operand:SI 2 "general_operand"
4686 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4687 (clobber (reg:CC CC_REGNUM))]
4688 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4699 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4701 (define_insn "*andsi3_esa"
4702 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4703 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4704 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4705 (clobber (reg:CC CC_REGNUM))]
4706 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4712 [(set_attr "op_type" "RR,RX,SI,SS")])
4715 [(set (match_operand:SI 0 "s_operand" "")
4716 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4717 (clobber (reg:CC CC_REGNUM))]
4720 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4721 (clobber (reg:CC CC_REGNUM))])]
4722 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4725 ; andhi3 instruction pattern(s).
4728 (define_insn "*andhi3_zarch"
4729 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4730 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4731 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4732 (clobber (reg:CC CC_REGNUM))]
4733 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4739 [(set_attr "op_type" "RR,RI,SI,SS")])
4741 (define_insn "*andhi3_esa"
4742 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4743 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4744 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4745 (clobber (reg:CC CC_REGNUM))]
4746 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4751 [(set_attr "op_type" "RR,SI,SS")])
4754 [(set (match_operand:HI 0 "s_operand" "")
4755 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4756 (clobber (reg:CC CC_REGNUM))]
4759 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4760 (clobber (reg:CC CC_REGNUM))])]
4761 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4764 ; andqi3 instruction pattern(s).
4767 (define_insn "*andqi3_zarch"
4768 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4769 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4770 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4771 (clobber (reg:CC CC_REGNUM))]
4772 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4779 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4781 (define_insn "*andqi3_esa"
4782 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4783 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4784 (match_operand:QI 2 "general_operand" "d,n,Q")))
4785 (clobber (reg:CC CC_REGNUM))]
4786 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4791 [(set_attr "op_type" "RR,SI,SS")])
4794 ; Block and (NC) patterns.
4798 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4799 (and:BLK (match_dup 0)
4800 (match_operand:BLK 1 "memory_operand" "Q")))
4801 (use (match_operand 2 "const_int_operand" "n"))
4802 (clobber (reg:CC CC_REGNUM))]
4803 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4804 "nc\t%O0(%2,%R0),%S1"
4805 [(set_attr "op_type" "SS")])
4808 [(set (match_operand 0 "memory_operand" "")
4810 (match_operand 1 "memory_operand" "")))
4811 (clobber (reg:CC CC_REGNUM))]
4813 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4814 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4816 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4818 (clobber (reg:CC CC_REGNUM))])]
4820 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4821 operands[0] = adjust_address (operands[0], BLKmode, 0);
4822 operands[1] = adjust_address (operands[1], BLKmode, 0);
4827 [(set (match_operand:BLK 0 "memory_operand" "")
4828 (and:BLK (match_dup 0)
4829 (match_operand:BLK 1 "memory_operand" "")))
4830 (use (match_operand 2 "const_int_operand" ""))
4831 (clobber (reg:CC CC_REGNUM))])
4833 [(set (match_operand:BLK 3 "memory_operand" "")
4834 (and:BLK (match_dup 3)
4835 (match_operand:BLK 4 "memory_operand" "")))
4836 (use (match_operand 5 "const_int_operand" ""))
4837 (clobber (reg:CC CC_REGNUM))])]
4838 "s390_offset_p (operands[0], operands[3], operands[2])
4839 && s390_offset_p (operands[1], operands[4], operands[2])
4840 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4842 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4844 (clobber (reg:CC CC_REGNUM))])]
4845 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4846 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4847 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4851 ;;- Bit set (inclusive or) instructions.
4854 (define_expand "ior<mode>3"
4855 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4856 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
4857 (match_operand:INT 2 "general_operand" "")))
4858 (clobber (reg:CC CC_REGNUM))]
4860 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
4863 ; iordi3 instruction pattern(s).
4866 (define_insn "*iordi3_cc"
4867 [(set (reg CC_REGNUM)
4868 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4869 (match_operand:DI 2 "general_operand" "d,m"))
4871 (set (match_operand:DI 0 "register_operand" "=d,d")
4872 (ior:DI (match_dup 1) (match_dup 2)))]
4873 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4877 [(set_attr "op_type" "RRE,RXY")])
4879 (define_insn "*iordi3_cconly"
4880 [(set (reg CC_REGNUM)
4881 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4882 (match_operand:DI 2 "general_operand" "d,m"))
4884 (clobber (match_scratch:DI 0 "=d,d"))]
4885 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4889 [(set_attr "op_type" "RRE,RXY")])
4891 (define_insn "*iordi3"
4892 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
4893 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
4894 (match_operand:DI 2 "general_operand"
4895 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
4896 (clobber (reg:CC CC_REGNUM))]
4897 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4907 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
4910 [(set (match_operand:DI 0 "s_operand" "")
4911 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4912 (clobber (reg:CC CC_REGNUM))]
4915 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4916 (clobber (reg:CC CC_REGNUM))])]
4917 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4920 ; iorsi3 instruction pattern(s).
4923 (define_insn "*iorsi3_cc"
4924 [(set (reg CC_REGNUM)
4925 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4926 (match_operand:SI 2 "general_operand" "d,R,T"))
4928 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4929 (ior:SI (match_dup 1) (match_dup 2)))]
4930 "s390_match_ccmode(insn, CCTmode)"
4935 [(set_attr "op_type" "RR,RX,RXY")])
4937 (define_insn "*iorsi3_cconly"
4938 [(set (reg CC_REGNUM)
4939 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4940 (match_operand:SI 2 "general_operand" "d,R,T"))
4942 (clobber (match_scratch:SI 0 "=d,d,d"))]
4943 "s390_match_ccmode(insn, CCTmode)"
4948 [(set_attr "op_type" "RR,RX,RXY")])
4950 (define_insn "*iorsi3_zarch"
4951 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
4952 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4953 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
4954 (clobber (reg:CC CC_REGNUM))]
4955 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4964 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
4966 (define_insn "*iorsi3_esa"
4967 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4968 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4969 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
4970 (clobber (reg:CC CC_REGNUM))]
4971 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4977 [(set_attr "op_type" "RR,RX,SI,SS")])
4980 [(set (match_operand:SI 0 "s_operand" "")
4981 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4982 (clobber (reg:CC CC_REGNUM))]
4985 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4986 (clobber (reg:CC CC_REGNUM))])]
4987 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4990 ; iorhi3 instruction pattern(s).
4993 (define_insn "*iorhi3_zarch"
4994 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4995 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4996 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
4997 (clobber (reg:CC CC_REGNUM))]
4998 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5004 [(set_attr "op_type" "RR,RI,SI,SS")])
5006 (define_insn "*iorhi3_esa"
5007 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5008 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5009 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5010 (clobber (reg:CC CC_REGNUM))]
5011 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5016 [(set_attr "op_type" "RR,SI,SS")])
5019 [(set (match_operand:HI 0 "s_operand" "")
5020 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5021 (clobber (reg:CC CC_REGNUM))]
5024 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5025 (clobber (reg:CC CC_REGNUM))])]
5026 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5029 ; iorqi3 instruction pattern(s).
5032 (define_insn "*iorqi3_zarch"
5033 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5034 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5035 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5036 (clobber (reg:CC CC_REGNUM))]
5037 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5044 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5046 (define_insn "*iorqi3_esa"
5047 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5048 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5049 (match_operand:QI 2 "general_operand" "d,n,Q")))
5050 (clobber (reg:CC CC_REGNUM))]
5051 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5056 [(set_attr "op_type" "RR,SI,SS")])
5059 ; Block inclusive or (OC) patterns.
5063 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5064 (ior:BLK (match_dup 0)
5065 (match_operand:BLK 1 "memory_operand" "Q")))
5066 (use (match_operand 2 "const_int_operand" "n"))
5067 (clobber (reg:CC CC_REGNUM))]
5068 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5069 "oc\t%O0(%2,%R0),%S1"
5070 [(set_attr "op_type" "SS")])
5073 [(set (match_operand 0 "memory_operand" "")
5075 (match_operand 1 "memory_operand" "")))
5076 (clobber (reg:CC CC_REGNUM))]
5078 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5079 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5081 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5083 (clobber (reg:CC CC_REGNUM))])]
5085 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5086 operands[0] = adjust_address (operands[0], BLKmode, 0);
5087 operands[1] = adjust_address (operands[1], BLKmode, 0);
5092 [(set (match_operand:BLK 0 "memory_operand" "")
5093 (ior:BLK (match_dup 0)
5094 (match_operand:BLK 1 "memory_operand" "")))
5095 (use (match_operand 2 "const_int_operand" ""))
5096 (clobber (reg:CC CC_REGNUM))])
5098 [(set (match_operand:BLK 3 "memory_operand" "")
5099 (ior:BLK (match_dup 3)
5100 (match_operand:BLK 4 "memory_operand" "")))
5101 (use (match_operand 5 "const_int_operand" ""))
5102 (clobber (reg:CC CC_REGNUM))])]
5103 "s390_offset_p (operands[0], operands[3], operands[2])
5104 && s390_offset_p (operands[1], operands[4], operands[2])
5105 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5107 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5109 (clobber (reg:CC CC_REGNUM))])]
5110 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5111 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5112 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5116 ;;- Xor instructions.
5119 (define_expand "xor<mode>3"
5120 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5121 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5122 (match_operand:INT 2 "general_operand" "")))
5123 (clobber (reg:CC CC_REGNUM))]
5125 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5128 ; xordi3 instruction pattern(s).
5131 (define_insn "*xordi3_cc"
5132 [(set (reg CC_REGNUM)
5133 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5134 (match_operand:DI 2 "general_operand" "d,m"))
5136 (set (match_operand:DI 0 "register_operand" "=d,d")
5137 (xor:DI (match_dup 1) (match_dup 2)))]
5138 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5142 [(set_attr "op_type" "RRE,RXY")])
5144 (define_insn "*xordi3_cconly"
5145 [(set (reg CC_REGNUM)
5146 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5147 (match_operand:DI 2 "general_operand" "d,m"))
5149 (clobber (match_scratch:DI 0 "=d,d"))]
5150 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5154 [(set_attr "op_type" "RRE,RXY")])
5156 (define_insn "*xordi3"
5157 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5158 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5159 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5160 (clobber (reg:CC CC_REGNUM))]
5161 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5167 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5170 [(set (match_operand:DI 0 "s_operand" "")
5171 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5172 (clobber (reg:CC CC_REGNUM))]
5175 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5176 (clobber (reg:CC CC_REGNUM))])]
5177 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5180 ; xorsi3 instruction pattern(s).
5183 (define_insn "*xorsi3_cc"
5184 [(set (reg CC_REGNUM)
5185 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5186 (match_operand:SI 2 "general_operand" "d,R,T"))
5188 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5189 (xor:SI (match_dup 1) (match_dup 2)))]
5190 "s390_match_ccmode(insn, CCTmode)"
5195 [(set_attr "op_type" "RR,RX,RXY")])
5197 (define_insn "*xorsi3_cconly"
5198 [(set (reg CC_REGNUM)
5199 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5200 (match_operand:SI 2 "general_operand" "d,R,T"))
5202 (clobber (match_scratch:SI 0 "=d,d,d"))]
5203 "s390_match_ccmode(insn, CCTmode)"
5208 [(set_attr "op_type" "RR,RX,RXY")])
5210 (define_insn "*xorsi3"
5211 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5212 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5213 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5214 (clobber (reg:CC CC_REGNUM))]
5215 "s390_logical_operator_ok_p (operands)"
5222 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5225 [(set (match_operand:SI 0 "s_operand" "")
5226 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5227 (clobber (reg:CC CC_REGNUM))]
5230 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5231 (clobber (reg:CC CC_REGNUM))])]
5232 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5235 ; xorhi3 instruction pattern(s).
5238 (define_insn "*xorhi3"
5239 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5240 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5241 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5242 (clobber (reg:CC CC_REGNUM))]
5243 "s390_logical_operator_ok_p (operands)"
5248 [(set_attr "op_type" "RR,SI,SS")])
5251 [(set (match_operand:HI 0 "s_operand" "")
5252 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5253 (clobber (reg:CC CC_REGNUM))]
5256 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5257 (clobber (reg:CC CC_REGNUM))])]
5258 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5261 ; xorqi3 instruction pattern(s).
5264 (define_insn "*xorqi3"
5265 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5266 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5267 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5268 (clobber (reg:CC CC_REGNUM))]
5269 "s390_logical_operator_ok_p (operands)"
5275 [(set_attr "op_type" "RR,SI,SIY,SS")])
5278 ; Block exclusive or (XC) patterns.
5282 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5283 (xor:BLK (match_dup 0)
5284 (match_operand:BLK 1 "memory_operand" "Q")))
5285 (use (match_operand 2 "const_int_operand" "n"))
5286 (clobber (reg:CC CC_REGNUM))]
5287 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5288 "xc\t%O0(%2,%R0),%S1"
5289 [(set_attr "op_type" "SS")])
5292 [(set (match_operand 0 "memory_operand" "")
5294 (match_operand 1 "memory_operand" "")))
5295 (clobber (reg:CC CC_REGNUM))]
5297 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5298 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5300 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5302 (clobber (reg:CC CC_REGNUM))])]
5304 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5305 operands[0] = adjust_address (operands[0], BLKmode, 0);
5306 operands[1] = adjust_address (operands[1], BLKmode, 0);
5311 [(set (match_operand:BLK 0 "memory_operand" "")
5312 (xor:BLK (match_dup 0)
5313 (match_operand:BLK 1 "memory_operand" "")))
5314 (use (match_operand 2 "const_int_operand" ""))
5315 (clobber (reg:CC CC_REGNUM))])
5317 [(set (match_operand:BLK 3 "memory_operand" "")
5318 (xor:BLK (match_dup 3)
5319 (match_operand:BLK 4 "memory_operand" "")))
5320 (use (match_operand 5 "const_int_operand" ""))
5321 (clobber (reg:CC CC_REGNUM))])]
5322 "s390_offset_p (operands[0], operands[3], operands[2])
5323 && s390_offset_p (operands[1], operands[4], operands[2])
5324 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5326 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5328 (clobber (reg:CC CC_REGNUM))])]
5329 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5330 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5331 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5334 ; Block xor (XC) patterns with src == dest.
5337 (define_insn "*xc_zero"
5338 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5340 (use (match_operand 1 "const_int_operand" "n"))
5341 (clobber (reg:CC CC_REGNUM))]
5342 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5343 "xc\t%O0(%1,%R0),%S0"
5344 [(set_attr "op_type" "SS")])
5348 [(set (match_operand:BLK 0 "memory_operand" "")
5350 (use (match_operand 1 "const_int_operand" ""))
5351 (clobber (reg:CC CC_REGNUM))])
5353 [(set (match_operand:BLK 2 "memory_operand" "")
5355 (use (match_operand 3 "const_int_operand" ""))
5356 (clobber (reg:CC CC_REGNUM))])]
5357 "s390_offset_p (operands[0], operands[2], operands[1])
5358 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5360 [(set (match_dup 4) (const_int 0))
5362 (clobber (reg:CC CC_REGNUM))])]
5363 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5364 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5368 ;;- Negate instructions.
5372 ; neg(di|si)2 instruction pattern(s).
5375 (define_expand "neg<mode>2"
5377 [(set (match_operand:DSI 0 "register_operand" "=d")
5378 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5379 (clobber (reg:CC CC_REGNUM))])]
5383 (define_insn "*negdi2_sign_cc"
5384 [(set (reg CC_REGNUM)
5385 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5386 (match_operand:SI 1 "register_operand" "d") 0)
5387 (const_int 32)) (const_int 32)))
5389 (set (match_operand:DI 0 "register_operand" "=d")
5390 (neg:DI (sign_extend:DI (match_dup 1))))]
5391 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5393 [(set_attr "op_type" "RRE")])
5395 (define_insn "*negdi2_sign"
5396 [(set (match_operand:DI 0 "register_operand" "=d")
5397 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5398 (clobber (reg:CC CC_REGNUM))]
5401 [(set_attr "op_type" "RRE")])
5403 (define_insn "*neg<mode>2_cc"
5404 [(set (reg CC_REGNUM)
5405 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5407 (set (match_operand:GPR 0 "register_operand" "=d")
5408 (neg:GPR (match_dup 1)))]
5409 "s390_match_ccmode (insn, CCAmode)"
5411 [(set_attr "op_type" "RR<E>")])
5413 (define_insn "*neg<mode>2_cconly"
5414 [(set (reg CC_REGNUM)
5415 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5417 (clobber (match_scratch:GPR 0 "=d"))]
5418 "s390_match_ccmode (insn, CCAmode)"
5420 [(set_attr "op_type" "RR<E>")])
5422 (define_insn "*neg<mode>2"
5423 [(set (match_operand:GPR 0 "register_operand" "=d")
5424 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5425 (clobber (reg:CC CC_REGNUM))]
5428 [(set_attr "op_type" "RR<E>")])
5430 (define_insn_and_split "*negdi2_31"
5431 [(set (match_operand:DI 0 "register_operand" "=d")
5432 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5433 (clobber (reg:CC CC_REGNUM))]
5436 "&& reload_completed"
5438 [(set (match_dup 2) (neg:SI (match_dup 3)))
5439 (clobber (reg:CC CC_REGNUM))])
5441 [(set (reg:CCAP CC_REGNUM)
5442 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5443 (set (match_dup 4) (neg:SI (match_dup 5)))])
5445 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5447 (label_ref (match_dup 6))))
5449 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5450 (clobber (reg:CC CC_REGNUM))])
5452 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5453 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5454 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5455 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5456 operands[6] = gen_label_rtx ();")
5459 ; neg(df|sf)2 instruction pattern(s).
5462 (define_expand "neg<mode>2"
5464 [(set (match_operand:FPR 0 "register_operand" "=f")
5465 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5466 (clobber (reg:CC CC_REGNUM))])]
5470 (define_insn "*neg<mode>2_cc"
5471 [(set (reg CC_REGNUM)
5472 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5473 (match_operand:FPR 2 "const0_operand" "")))
5474 (set (match_operand:FPR 0 "register_operand" "=f")
5475 (neg:FPR (match_dup 1)))]
5476 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5478 [(set_attr "op_type" "RRE")
5479 (set_attr "type" "fsimp<mode>")])
5481 (define_insn "*neg<mode>2_cconly"
5482 [(set (reg CC_REGNUM)
5483 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5484 (match_operand:FPR 2 "const0_operand" "")))
5485 (clobber (match_scratch:FPR 0 "=f"))]
5486 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5488 [(set_attr "op_type" "RRE")
5489 (set_attr "type" "fsimp<mode>")])
5491 (define_insn "*neg<mode>2"
5492 [(set (match_operand:FPR 0 "register_operand" "=f")
5493 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5494 (clobber (reg:CC CC_REGNUM))]
5495 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5497 [(set_attr "op_type" "RRE")
5498 (set_attr "type" "fsimp<mode>")])
5500 (define_insn "*neg<mode>2_ibm"
5501 [(set (match_operand:FPR 0 "register_operand" "=f")
5502 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5503 (clobber (reg:CC CC_REGNUM))]
5504 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5506 [(set_attr "op_type" "RR")
5507 (set_attr "type" "fsimp<mode>")])
5511 ;;- Absolute value instructions.
5515 ; abs(di|si)2 instruction pattern(s).
5518 (define_insn "*absdi2_sign_cc"
5519 [(set (reg CC_REGNUM)
5520 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5521 (match_operand:SI 1 "register_operand" "d") 0)
5522 (const_int 32)) (const_int 32)))
5524 (set (match_operand:DI 0 "register_operand" "=d")
5525 (abs:DI (sign_extend:DI (match_dup 1))))]
5526 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5528 [(set_attr "op_type" "RRE")])
5530 (define_insn "*absdi2_sign"
5531 [(set (match_operand:DI 0 "register_operand" "=d")
5532 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5533 (clobber (reg:CC CC_REGNUM))]
5536 [(set_attr "op_type" "RRE")])
5538 (define_insn "*abs<mode>2_cc"
5539 [(set (reg CC_REGNUM)
5540 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5542 (set (match_operand:GPR 0 "register_operand" "=d")
5543 (abs:GPR (match_dup 1)))]
5544 "s390_match_ccmode (insn, CCAmode)"
5546 [(set_attr "op_type" "RR<E>")])
5548 (define_insn "*abs<mode>2_cconly"
5549 [(set (reg CC_REGNUM)
5550 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5552 (clobber (match_scratch:GPR 0 "=d"))]
5553 "s390_match_ccmode (insn, CCAmode)"
5555 [(set_attr "op_type" "RR<E>")])
5557 (define_insn "abs<mode>2"
5558 [(set (match_operand:GPR 0 "register_operand" "=d")
5559 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5560 (clobber (reg:CC CC_REGNUM))]
5563 [(set_attr "op_type" "RR<E>")])
5566 ; abs(df|sf)2 instruction pattern(s).
5569 (define_expand "abs<mode>2"
5571 [(set (match_operand:FPR 0 "register_operand" "=f")
5572 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5573 (clobber (reg:CC CC_REGNUM))])]
5577 (define_insn "*abs<mode>2_cc"
5578 [(set (reg CC_REGNUM)
5579 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5580 (match_operand:FPR 2 "const0_operand" "")))
5581 (set (match_operand:FPR 0 "register_operand" "=f")
5582 (abs:FPR (match_dup 1)))]
5583 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5585 [(set_attr "op_type" "RRE")
5586 (set_attr "type" "fsimp<mode>")])
5588 (define_insn "*abs<mode>2_cconly"
5589 [(set (reg CC_REGNUM)
5590 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5591 (match_operand:FPR 2 "const0_operand" "")))
5592 (clobber (match_scratch:FPR 0 "=f"))]
5593 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5595 [(set_attr "op_type" "RRE")
5596 (set_attr "type" "fsimp<mode>")])
5598 (define_insn "*abs<mode>2"
5599 [(set (match_operand:FPR 0 "register_operand" "=f")
5600 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5601 (clobber (reg:CC CC_REGNUM))]
5602 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5604 [(set_attr "op_type" "RRE")
5605 (set_attr "type" "fsimp<mode>")])
5607 (define_insn "*abs<mode>2_ibm"
5608 [(set (match_operand:FPR 0 "register_operand" "=f")
5609 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5610 (clobber (reg:CC CC_REGNUM))]
5611 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5613 [(set_attr "op_type" "RR")
5614 (set_attr "type" "fsimp<mode>")])
5617 ;;- Negated absolute value instructions
5624 (define_insn "*negabsdi2_sign_cc"
5625 [(set (reg CC_REGNUM)
5626 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5627 (match_operand:SI 1 "register_operand" "d") 0)
5628 (const_int 32)) (const_int 32))))
5630 (set (match_operand:DI 0 "register_operand" "=d")
5631 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5632 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5634 [(set_attr "op_type" "RRE")])
5636 (define_insn "*negabsdi2_sign"
5637 [(set (match_operand:DI 0 "register_operand" "=d")
5638 (neg:DI (abs:DI (sign_extend:DI
5639 (match_operand:SI 1 "register_operand" "d")))))
5640 (clobber (reg:CC CC_REGNUM))]
5643 [(set_attr "op_type" "RRE")])
5645 (define_insn "*negabs<mode>2_cc"
5646 [(set (reg CC_REGNUM)
5647 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5649 (set (match_operand:GPR 0 "register_operand" "=d")
5650 (neg:GPR (abs:GPR (match_dup 1))))]
5651 "s390_match_ccmode (insn, CCAmode)"
5653 [(set_attr "op_type" "RR<E>")])
5655 (define_insn "*negabs<mode>2_cconly"
5656 [(set (reg CC_REGNUM)
5657 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5659 (clobber (match_scratch:GPR 0 "=d"))]
5660 "s390_match_ccmode (insn, CCAmode)"
5662 [(set_attr "op_type" "RR<E>")])
5664 (define_insn "*negabs<mode>2"
5665 [(set (match_operand:GPR 0 "register_operand" "=d")
5666 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5667 (clobber (reg:CC CC_REGNUM))]
5670 [(set_attr "op_type" "RR<E>")])
5676 (define_insn "*negabs<mode>2_cc"
5677 [(set (reg CC_REGNUM)
5678 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5679 (match_operand:FPR 2 "const0_operand" "")))
5680 (set (match_operand:FPR 0 "register_operand" "=f")
5681 (neg:FPR (abs:FPR (match_dup 1))))]
5682 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5684 [(set_attr "op_type" "RRE")
5685 (set_attr "type" "fsimp<mode>")])
5687 (define_insn "*negabs<mode>2_cconly"
5688 [(set (reg CC_REGNUM)
5689 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5690 (match_operand:FPR 2 "const0_operand" "")))
5691 (clobber (match_scratch:FPR 0 "=f"))]
5692 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5694 [(set_attr "op_type" "RRE")
5695 (set_attr "type" "fsimp<mode>")])
5697 (define_insn "*negabs<mode>2"
5698 [(set (match_operand:FPR 0 "register_operand" "=f")
5699 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5700 (clobber (reg:CC CC_REGNUM))]
5701 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5703 [(set_attr "op_type" "RRE")
5704 (set_attr "type" "fsimp<mode>")])
5707 ;;- Square root instructions.
5711 ; sqrt(df|sf)2 instruction pattern(s).
5714 (define_insn "sqrt<mode>2"
5715 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5716 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5717 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5721 [(set_attr "op_type" "RRE,RXE")
5722 (set_attr "type" "fsqrt<mode>")])
5726 ;;- One complement instructions.
5730 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5733 (define_expand "one_cmpl<mode>2"
5735 [(set (match_operand:INT 0 "register_operand" "")
5736 (xor:INT (match_operand:INT 1 "register_operand" "")
5738 (clobber (reg:CC CC_REGNUM))])]
5744 ;;- Rotate instructions.
5748 ; rotl(di|si)3 instruction pattern(s).
5751 (define_insn "rotl<mode>3"
5752 [(set (match_operand:GPR 0 "register_operand" "=d")
5753 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5754 (match_operand:SI 2 "shift_count_operand" "Y")))]
5757 [(set_attr "op_type" "RSE")
5758 (set_attr "atype" "reg")])
5762 ;;- Shift instructions.
5766 ; (ashl|lshr)di3 instruction pattern(s).
5769 (define_expand "<shift>di3"
5770 [(set (match_operand:DI 0 "register_operand" "")
5771 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5772 (match_operand:SI 2 "shift_count_operand" "")))]
5776 (define_insn "*<shift>di3_31"
5777 [(set (match_operand:DI 0 "register_operand" "=d")
5778 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5779 (match_operand:SI 2 "shift_count_operand" "Y")))]
5782 [(set_attr "op_type" "RS")
5783 (set_attr "atype" "reg")])
5785 (define_insn "*<shift>di3_64"
5786 [(set (match_operand:DI 0 "register_operand" "=d")
5787 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5788 (match_operand:SI 2 "shift_count_operand" "Y")))]
5790 "s<lr>lg\t%0,%1,%Y2"
5791 [(set_attr "op_type" "RSE")
5792 (set_attr "atype" "reg")])
5795 ; ashrdi3 instruction pattern(s).
5798 (define_expand "ashrdi3"
5800 [(set (match_operand:DI 0 "register_operand" "")
5801 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5802 (match_operand:SI 2 "shift_count_operand" "")))
5803 (clobber (reg:CC CC_REGNUM))])]
5807 (define_insn "*ashrdi3_cc_31"
5808 [(set (reg CC_REGNUM)
5809 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5810 (match_operand:SI 2 "shift_count_operand" "Y"))
5812 (set (match_operand:DI 0 "register_operand" "=d")
5813 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5814 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5816 [(set_attr "op_type" "RS")
5817 (set_attr "atype" "reg")])
5819 (define_insn "*ashrdi3_cconly_31"
5820 [(set (reg CC_REGNUM)
5821 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5822 (match_operand:SI 2 "shift_count_operand" "Y"))
5824 (clobber (match_scratch:DI 0 "=d"))]
5825 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5827 [(set_attr "op_type" "RS")
5828 (set_attr "atype" "reg")])
5830 (define_insn "*ashrdi3_31"
5831 [(set (match_operand:DI 0 "register_operand" "=d")
5832 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5833 (match_operand:SI 2 "shift_count_operand" "Y")))
5834 (clobber (reg:CC CC_REGNUM))]
5837 [(set_attr "op_type" "RS")
5838 (set_attr "atype" "reg")])
5840 (define_insn "*ashrdi3_cc_64"
5841 [(set (reg CC_REGNUM)
5842 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5843 (match_operand:SI 2 "shift_count_operand" "Y"))
5845 (set (match_operand:DI 0 "register_operand" "=d")
5846 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5847 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5849 [(set_attr "op_type" "RSE")
5850 (set_attr "atype" "reg")])
5852 (define_insn "*ashrdi3_cconly_64"
5853 [(set (reg CC_REGNUM)
5854 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5855 (match_operand:SI 2 "shift_count_operand" "Y"))
5857 (clobber (match_scratch:DI 0 "=d"))]
5858 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5860 [(set_attr "op_type" "RSE")
5861 (set_attr "atype" "reg")])
5863 (define_insn "*ashrdi3_64"
5864 [(set (match_operand:DI 0 "register_operand" "=d")
5865 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5866 (match_operand:SI 2 "shift_count_operand" "Y")))
5867 (clobber (reg:CC CC_REGNUM))]
5870 [(set_attr "op_type" "RSE")
5871 (set_attr "atype" "reg")])
5875 ; (ashl|lshr)si3 instruction pattern(s).
5878 (define_insn "<shift>si3"
5879 [(set (match_operand:SI 0 "register_operand" "=d")
5880 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
5881 (match_operand:SI 2 "shift_count_operand" "Y")))]
5884 [(set_attr "op_type" "RS")
5885 (set_attr "atype" "reg")])
5888 ; ashrsi3 instruction pattern(s).
5891 (define_insn "*ashrsi3_cc"
5892 [(set (reg CC_REGNUM)
5893 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5894 (match_operand:SI 2 "shift_count_operand" "Y"))
5896 (set (match_operand:SI 0 "register_operand" "=d")
5897 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5898 "s390_match_ccmode(insn, CCSmode)"
5900 [(set_attr "op_type" "RS")
5901 (set_attr "atype" "reg")])
5904 (define_insn "*ashrsi3_cconly"
5905 [(set (reg CC_REGNUM)
5906 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5907 (match_operand:SI 2 "shift_count_operand" "Y"))
5909 (clobber (match_scratch:SI 0 "=d"))]
5910 "s390_match_ccmode(insn, CCSmode)"
5912 [(set_attr "op_type" "RS")
5913 (set_attr "atype" "reg")])
5915 (define_insn "ashrsi3"
5916 [(set (match_operand:SI 0 "register_operand" "=d")
5917 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5918 (match_operand:SI 2 "shift_count_operand" "Y")))
5919 (clobber (reg:CC CC_REGNUM))]
5922 [(set_attr "op_type" "RS")
5923 (set_attr "atype" "reg")])
5927 ;; Branch instruction patterns.
5930 (define_expand "b<code>"
5932 (if_then_else (COMPARE (match_operand 0 "" "")
5937 "s390_emit_jump (operands[0],
5938 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
5942 ;;- Conditional jump instructions.
5945 (define_insn "*cjump_64"
5948 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5949 (label_ref (match_operand 0 "" ""))
5953 if (get_attr_length (insn) == 4)
5956 return "jg%C1\t%l0";
5958 [(set_attr "op_type" "RI")
5959 (set_attr "type" "branch")
5960 (set (attr "length")
5961 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5962 (const_int 4) (const_int 6)))])
5964 (define_insn "*cjump_31"
5967 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5968 (label_ref (match_operand 0 "" ""))
5972 gcc_assert (get_attr_length (insn) == 4);
5975 [(set_attr "op_type" "RI")
5976 (set_attr "type" "branch")
5977 (set (attr "length")
5978 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5979 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5980 (const_int 4) (const_int 6))
5981 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5982 (const_int 4) (const_int 8))))])
5984 (define_insn "*cjump_long"
5987 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5988 (match_operand 0 "address_operand" "U")
5992 if (get_attr_op_type (insn) == OP_TYPE_RR)
5997 [(set (attr "op_type")
5998 (if_then_else (match_operand 0 "register_operand" "")
5999 (const_string "RR") (const_string "RX")))
6000 (set_attr "type" "branch")
6001 (set_attr "atype" "agen")])
6005 ;;- Negated conditional jump instructions.
6008 (define_insn "*icjump_64"
6011 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6013 (label_ref (match_operand 0 "" ""))))]
6016 if (get_attr_length (insn) == 4)
6019 return "jg%D1\t%l0";
6021 [(set_attr "op_type" "RI")
6022 (set_attr "type" "branch")
6023 (set (attr "length")
6024 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6025 (const_int 4) (const_int 6)))])
6027 (define_insn "*icjump_31"
6030 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6032 (label_ref (match_operand 0 "" ""))))]
6035 gcc_assert (get_attr_length (insn) == 4);
6038 [(set_attr "op_type" "RI")
6039 (set_attr "type" "branch")
6040 (set (attr "length")
6041 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6042 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6043 (const_int 4) (const_int 6))
6044 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6045 (const_int 4) (const_int 8))))])
6047 (define_insn "*icjump_long"
6050 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6052 (match_operand 0 "address_operand" "U")))]
6055 if (get_attr_op_type (insn) == OP_TYPE_RR)
6060 [(set (attr "op_type")
6061 (if_then_else (match_operand 0 "register_operand" "")
6062 (const_string "RR") (const_string "RX")))
6063 (set_attr "type" "branch")
6064 (set_attr "atype" "agen")])
6067 ;;- Trap instructions.
6071 [(trap_if (const_int 1) (const_int 0))]
6074 [(set_attr "op_type" "RI")
6075 (set_attr "type" "branch")])
6077 (define_expand "conditional_trap"
6078 [(trap_if (match_operand 0 "comparison_operator" "")
6079 (match_operand 1 "general_operand" ""))]
6082 if (operands[1] != const0_rtx) FAIL;
6083 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6084 s390_compare_op0, s390_compare_op1);
6087 (define_insn "*trap"
6088 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6092 [(set_attr "op_type" "RI")
6093 (set_attr "type" "branch")])
6096 ;;- Loop instructions.
6098 ;; This is all complicated by the fact that since this is a jump insn
6099 ;; we must handle our own output reloads.
6101 (define_expand "doloop_end"
6102 [(use (match_operand 0 "" "")) ; loop pseudo
6103 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6104 (use (match_operand 2 "" "")) ; max iterations
6105 (use (match_operand 3 "" "")) ; loop level
6106 (use (match_operand 4 "" ""))] ; label
6109 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6110 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6111 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6112 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6113 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6114 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6121 (define_insn_and_split "doloop_si64"
6124 (ne (match_operand:SI 1 "register_operand" "d,d")
6126 (label_ref (match_operand 0 "" ""))
6128 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6129 (plus:SI (match_dup 1) (const_int -1)))
6130 (clobber (match_scratch:SI 3 "=X,&1"))
6131 (clobber (reg:CC CC_REGNUM))]
6134 if (which_alternative != 0)
6136 else if (get_attr_length (insn) == 4)
6137 return "brct\t%1,%l0";
6139 return "ahi\t%1,-1\;jgne\t%l0";
6141 "&& reload_completed
6142 && (! REG_P (operands[2])
6143 || ! rtx_equal_p (operands[1], operands[2]))"
6144 [(parallel [(set (reg:CCAN CC_REGNUM)
6145 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6147 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6148 (set (match_dup 2) (match_dup 3))
6149 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6150 (label_ref (match_dup 0))
6153 [(set_attr "op_type" "RI")
6154 (set_attr "type" "branch")
6155 (set (attr "length")
6156 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6157 (const_int 4) (const_int 10)))])
6159 (define_insn_and_split "doloop_si31"
6162 (ne (match_operand:SI 1 "register_operand" "d,d")
6164 (label_ref (match_operand 0 "" ""))
6166 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6167 (plus:SI (match_dup 1) (const_int -1)))
6168 (clobber (match_scratch:SI 3 "=X,&1"))
6169 (clobber (reg:CC CC_REGNUM))]
6172 if (which_alternative != 0)
6174 else if (get_attr_length (insn) == 4)
6175 return "brct\t%1,%l0";
6179 "&& reload_completed
6180 && (! REG_P (operands[2])
6181 || ! rtx_equal_p (operands[1], operands[2]))"
6182 [(parallel [(set (reg:CCAN CC_REGNUM)
6183 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6185 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6186 (set (match_dup 2) (match_dup 3))
6187 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6188 (label_ref (match_dup 0))
6191 [(set_attr "op_type" "RI")
6192 (set_attr "type" "branch")
6193 (set (attr "length")
6194 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6195 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6196 (const_int 4) (const_int 6))
6197 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6198 (const_int 4) (const_int 8))))])
6200 (define_insn "*doloop_si_long"
6203 (ne (match_operand:SI 1 "register_operand" "d,d")
6205 (match_operand 0 "address_operand" "U,U")
6207 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6208 (plus:SI (match_dup 1) (const_int -1)))
6209 (clobber (match_scratch:SI 3 "=X,&1"))
6210 (clobber (reg:CC CC_REGNUM))]
6213 if (get_attr_op_type (insn) == OP_TYPE_RR)
6214 return "bctr\t%1,%0";
6216 return "bct\t%1,%a0";
6218 [(set (attr "op_type")
6219 (if_then_else (match_operand 0 "register_operand" "")
6220 (const_string "RR") (const_string "RX")))
6221 (set_attr "type" "branch")
6222 (set_attr "atype" "agen")])
6224 (define_insn_and_split "doloop_di"
6227 (ne (match_operand:DI 1 "register_operand" "d,d")
6229 (label_ref (match_operand 0 "" ""))
6231 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6232 (plus:DI (match_dup 1) (const_int -1)))
6233 (clobber (match_scratch:DI 3 "=X,&1"))
6234 (clobber (reg:CC CC_REGNUM))]
6237 if (which_alternative != 0)
6239 else if (get_attr_length (insn) == 4)
6240 return "brctg\t%1,%l0";
6242 return "aghi\t%1,-1\;jgne\t%l0";
6244 "&& reload_completed
6245 && (! REG_P (operands[2])
6246 || ! rtx_equal_p (operands[1], operands[2]))"
6247 [(parallel [(set (reg:CCAN CC_REGNUM)
6248 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6250 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6251 (set (match_dup 2) (match_dup 3))
6252 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6253 (label_ref (match_dup 0))
6256 [(set_attr "op_type" "RI")
6257 (set_attr "type" "branch")
6258 (set (attr "length")
6259 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6260 (const_int 4) (const_int 10)))])
6263 ;;- Unconditional jump instructions.
6267 ; jump instruction pattern(s).
6270 (define_expand "jump"
6271 [(match_operand 0 "" "")]
6273 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6275 (define_insn "*jump64"
6276 [(set (pc) (label_ref (match_operand 0 "" "")))]
6279 if (get_attr_length (insn) == 4)
6284 [(set_attr "op_type" "RI")
6285 (set_attr "type" "branch")
6286 (set (attr "length")
6287 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6288 (const_int 4) (const_int 6)))])
6290 (define_insn "*jump31"
6291 [(set (pc) (label_ref (match_operand 0 "" "")))]
6294 gcc_assert (get_attr_length (insn) == 4);
6297 [(set_attr "op_type" "RI")
6298 (set_attr "type" "branch")
6299 (set (attr "length")
6300 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6301 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6302 (const_int 4) (const_int 6))
6303 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6304 (const_int 4) (const_int 8))))])
6307 ; indirect-jump instruction pattern(s).
6310 (define_insn "indirect_jump"
6311 [(set (pc) (match_operand 0 "address_operand" "U"))]
6314 if (get_attr_op_type (insn) == OP_TYPE_RR)
6319 [(set (attr "op_type")
6320 (if_then_else (match_operand 0 "register_operand" "")
6321 (const_string "RR") (const_string "RX")))
6322 (set_attr "type" "branch")
6323 (set_attr "atype" "agen")])
6326 ; casesi instruction pattern(s).
6329 (define_insn "casesi_jump"
6330 [(set (pc) (match_operand 0 "address_operand" "U"))
6331 (use (label_ref (match_operand 1 "" "")))]
6334 if (get_attr_op_type (insn) == OP_TYPE_RR)
6339 [(set (attr "op_type")
6340 (if_then_else (match_operand 0 "register_operand" "")
6341 (const_string "RR") (const_string "RX")))
6342 (set_attr "type" "branch")
6343 (set_attr "atype" "agen")])
6345 (define_expand "casesi"
6346 [(match_operand:SI 0 "general_operand" "")
6347 (match_operand:SI 1 "general_operand" "")
6348 (match_operand:SI 2 "general_operand" "")
6349 (label_ref (match_operand 3 "" ""))
6350 (label_ref (match_operand 4 "" ""))]
6353 rtx index = gen_reg_rtx (SImode);
6354 rtx base = gen_reg_rtx (Pmode);
6355 rtx target = gen_reg_rtx (Pmode);
6357 emit_move_insn (index, operands[0]);
6358 emit_insn (gen_subsi3 (index, index, operands[1]));
6359 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6362 if (Pmode != SImode)
6363 index = convert_to_mode (Pmode, index, 1);
6364 if (GET_CODE (index) != REG)
6365 index = copy_to_mode_reg (Pmode, index);
6368 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6370 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6372 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6374 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6375 emit_move_insn (target, index);
6378 target = gen_rtx_PLUS (Pmode, base, target);
6379 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6386 ;;- Jump to subroutine.
6391 ; untyped call instruction pattern(s).
6394 ;; Call subroutine returning any type.
6395 (define_expand "untyped_call"
6396 [(parallel [(call (match_operand 0 "" "")
6398 (match_operand 1 "" "")
6399 (match_operand 2 "" "")])]
6404 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6406 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6408 rtx set = XVECEXP (operands[2], 0, i);
6409 emit_move_insn (SET_DEST (set), SET_SRC (set));
6412 /* The optimizer does not know that the call sets the function value
6413 registers we stored in the result block. We avoid problems by
6414 claiming that all hard registers are used and clobbered at this
6416 emit_insn (gen_blockage ());
6421 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6422 ;; all of memory. This blocks insns from being moved across this point.
6424 (define_insn "blockage"
6425 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6428 [(set_attr "type" "none")
6429 (set_attr "length" "0")])
6435 (define_expand "sibcall"
6436 [(call (match_operand 0 "" "")
6437 (match_operand 1 "" ""))]
6440 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6444 (define_insn "*sibcall_br"
6445 [(call (mem:QI (reg SIBCALL_REGNUM))
6446 (match_operand 0 "const_int_operand" "n"))]
6447 "SIBLING_CALL_P (insn)
6448 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6450 [(set_attr "op_type" "RR")
6451 (set_attr "type" "branch")
6452 (set_attr "atype" "agen")])
6454 (define_insn "*sibcall_brc"
6455 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6456 (match_operand 1 "const_int_operand" "n"))]
6457 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6459 [(set_attr "op_type" "RI")
6460 (set_attr "type" "branch")])
6462 (define_insn "*sibcall_brcl"
6463 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6464 (match_operand 1 "const_int_operand" "n"))]
6465 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6467 [(set_attr "op_type" "RIL")
6468 (set_attr "type" "branch")])
6471 ; sibcall_value patterns
6474 (define_expand "sibcall_value"
6475 [(set (match_operand 0 "" "")
6476 (call (match_operand 1 "" "")
6477 (match_operand 2 "" "")))]
6480 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6484 (define_insn "*sibcall_value_br"
6485 [(set (match_operand 0 "" "")
6486 (call (mem:QI (reg SIBCALL_REGNUM))
6487 (match_operand 1 "const_int_operand" "n")))]
6488 "SIBLING_CALL_P (insn)
6489 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6491 [(set_attr "op_type" "RR")
6492 (set_attr "type" "branch")
6493 (set_attr "atype" "agen")])
6495 (define_insn "*sibcall_value_brc"
6496 [(set (match_operand 0 "" "")
6497 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6498 (match_operand 2 "const_int_operand" "n")))]
6499 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6501 [(set_attr "op_type" "RI")
6502 (set_attr "type" "branch")])
6504 (define_insn "*sibcall_value_brcl"
6505 [(set (match_operand 0 "" "")
6506 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6507 (match_operand 2 "const_int_operand" "n")))]
6508 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6510 [(set_attr "op_type" "RIL")
6511 (set_attr "type" "branch")])
6515 ; call instruction pattern(s).
6518 (define_expand "call"
6519 [(call (match_operand 0 "" "")
6520 (match_operand 1 "" ""))
6521 (use (match_operand 2 "" ""))]
6524 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6525 gen_rtx_REG (Pmode, RETURN_REGNUM));
6529 (define_insn "*bras"
6530 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6531 (match_operand 1 "const_int_operand" "n"))
6532 (clobber (match_operand 2 "register_operand" "=r"))]
6533 "!SIBLING_CALL_P (insn)
6534 && TARGET_SMALL_EXEC
6535 && GET_MODE (operands[2]) == Pmode"
6537 [(set_attr "op_type" "RI")
6538 (set_attr "type" "jsr")])
6540 (define_insn "*brasl"
6541 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6542 (match_operand 1 "const_int_operand" "n"))
6543 (clobber (match_operand 2 "register_operand" "=r"))]
6544 "!SIBLING_CALL_P (insn)
6546 && GET_MODE (operands[2]) == Pmode"
6548 [(set_attr "op_type" "RIL")
6549 (set_attr "type" "jsr")])
6551 (define_insn "*basr"
6552 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6553 (match_operand 1 "const_int_operand" "n"))
6554 (clobber (match_operand 2 "register_operand" "=r"))]
6555 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6557 if (get_attr_op_type (insn) == OP_TYPE_RR)
6558 return "basr\t%2,%0";
6560 return "bas\t%2,%a0";
6562 [(set (attr "op_type")
6563 (if_then_else (match_operand 0 "register_operand" "")
6564 (const_string "RR") (const_string "RX")))
6565 (set_attr "type" "jsr")
6566 (set_attr "atype" "agen")])
6569 ; call_value instruction pattern(s).
6572 (define_expand "call_value"
6573 [(set (match_operand 0 "" "")
6574 (call (match_operand 1 "" "")
6575 (match_operand 2 "" "")))
6576 (use (match_operand 3 "" ""))]
6579 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6580 gen_rtx_REG (Pmode, RETURN_REGNUM));
6584 (define_insn "*bras_r"
6585 [(set (match_operand 0 "" "")
6586 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6587 (match_operand:SI 2 "const_int_operand" "n")))
6588 (clobber (match_operand 3 "register_operand" "=r"))]
6589 "!SIBLING_CALL_P (insn)
6590 && TARGET_SMALL_EXEC
6591 && GET_MODE (operands[3]) == Pmode"
6593 [(set_attr "op_type" "RI")
6594 (set_attr "type" "jsr")])
6596 (define_insn "*brasl_r"
6597 [(set (match_operand 0 "" "")
6598 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6599 (match_operand 2 "const_int_operand" "n")))
6600 (clobber (match_operand 3 "register_operand" "=r"))]
6601 "!SIBLING_CALL_P (insn)
6603 && GET_MODE (operands[3]) == Pmode"
6605 [(set_attr "op_type" "RIL")
6606 (set_attr "type" "jsr")])
6608 (define_insn "*basr_r"
6609 [(set (match_operand 0 "" "")
6610 (call (mem:QI (match_operand 1 "address_operand" "U"))
6611 (match_operand 2 "const_int_operand" "n")))
6612 (clobber (match_operand 3 "register_operand" "=r"))]
6613 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6615 if (get_attr_op_type (insn) == OP_TYPE_RR)
6616 return "basr\t%3,%1";
6618 return "bas\t%3,%a1";
6620 [(set (attr "op_type")
6621 (if_then_else (match_operand 1 "register_operand" "")
6622 (const_string "RR") (const_string "RX")))
6623 (set_attr "type" "jsr")
6624 (set_attr "atype" "agen")])
6627 ;;- Thread-local storage support.
6630 (define_expand "get_tp_64"
6631 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6635 (define_expand "get_tp_31"
6636 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6640 (define_expand "set_tp_64"
6641 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6642 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6646 (define_expand "set_tp_31"
6647 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6648 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6652 (define_insn "*set_tp"
6653 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6656 [(set_attr "type" "none")
6657 (set_attr "length" "0")])
6659 (define_insn "*tls_load_64"
6660 [(set (match_operand:DI 0 "register_operand" "=d")
6661 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6662 (match_operand:DI 2 "" "")]
6666 [(set_attr "op_type" "RXE")])
6668 (define_insn "*tls_load_31"
6669 [(set (match_operand:SI 0 "register_operand" "=d,d")
6670 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6671 (match_operand:SI 2 "" "")]
6677 [(set_attr "op_type" "RX,RXY")])
6679 (define_insn "*bras_tls"
6680 [(set (match_operand 0 "" "")
6681 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6682 (match_operand 2 "const_int_operand" "n")))
6683 (clobber (match_operand 3 "register_operand" "=r"))
6684 (use (match_operand 4 "" ""))]
6685 "!SIBLING_CALL_P (insn)
6686 && TARGET_SMALL_EXEC
6687 && GET_MODE (operands[3]) == Pmode"
6689 [(set_attr "op_type" "RI")
6690 (set_attr "type" "jsr")])
6692 (define_insn "*brasl_tls"
6693 [(set (match_operand 0 "" "")
6694 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6695 (match_operand 2 "const_int_operand" "n")))
6696 (clobber (match_operand 3 "register_operand" "=r"))
6697 (use (match_operand 4 "" ""))]
6698 "!SIBLING_CALL_P (insn)
6700 && GET_MODE (operands[3]) == Pmode"
6702 [(set_attr "op_type" "RIL")
6703 (set_attr "type" "jsr")])
6705 (define_insn "*basr_tls"
6706 [(set (match_operand 0 "" "")
6707 (call (mem:QI (match_operand 1 "address_operand" "U"))
6708 (match_operand 2 "const_int_operand" "n")))
6709 (clobber (match_operand 3 "register_operand" "=r"))
6710 (use (match_operand 4 "" ""))]
6711 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6713 if (get_attr_op_type (insn) == OP_TYPE_RR)
6714 return "basr\t%3,%1%J4";
6716 return "bas\t%3,%a1%J4";
6718 [(set (attr "op_type")
6719 (if_then_else (match_operand 1 "register_operand" "")
6720 (const_string "RR") (const_string "RX")))
6721 (set_attr "type" "jsr")
6722 (set_attr "atype" "agen")])
6725 ;;- Miscellaneous instructions.
6729 ; allocate stack instruction pattern(s).
6732 (define_expand "allocate_stack"
6733 [(match_operand 0 "general_operand" "")
6734 (match_operand 1 "general_operand" "")]
6737 rtx temp = gen_reg_rtx (Pmode);
6739 emit_move_insn (temp, s390_back_chain_rtx ());
6740 anti_adjust_stack (operands[1]);
6741 emit_move_insn (s390_back_chain_rtx (), temp);
6743 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6749 ; setjmp instruction pattern.
6752 (define_expand "builtin_setjmp_receiver"
6753 [(match_operand 0 "" "")]
6756 emit_insn (s390_load_got ());
6757 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6761 ;; These patterns say how to save and restore the stack pointer. We need not
6762 ;; save the stack pointer at function level since we are careful to
6763 ;; preserve the backchain. At block level, we have to restore the backchain
6764 ;; when we restore the stack pointer.
6766 ;; For nonlocal gotos, we must save both the stack pointer and its
6767 ;; backchain and restore both. Note that in the nonlocal case, the
6768 ;; save area is a memory location.
6770 (define_expand "save_stack_function"
6771 [(match_operand 0 "general_operand" "")
6772 (match_operand 1 "general_operand" "")]
6776 (define_expand "restore_stack_function"
6777 [(match_operand 0 "general_operand" "")
6778 (match_operand 1 "general_operand" "")]
6782 (define_expand "restore_stack_block"
6783 [(match_operand 0 "register_operand" "")
6784 (match_operand 1 "register_operand" "")]
6787 rtx temp = gen_reg_rtx (Pmode);
6789 emit_move_insn (temp, s390_back_chain_rtx ());
6790 emit_move_insn (operands[0], operands[1]);
6791 emit_move_insn (s390_back_chain_rtx (), temp);
6796 (define_expand "save_stack_nonlocal"
6797 [(match_operand 0 "memory_operand" "")
6798 (match_operand 1 "register_operand" "")]
6801 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6802 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6804 /* Copy the backchain to the first word, sp to the second and the
6805 literal pool base to the third. */
6807 if (TARGET_BACKCHAIN)
6809 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6810 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6813 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6814 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6819 (define_expand "restore_stack_nonlocal"
6820 [(match_operand 0 "register_operand" "")
6821 (match_operand 1 "memory_operand" "")]
6824 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6825 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6826 rtx temp = NULL_RTX;
6828 /* Restore the backchain from the first word, sp from the second and the
6829 literal pool base from the third. */
6831 if (TARGET_BACKCHAIN)
6832 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
6834 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
6835 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
6838 emit_move_insn (s390_back_chain_rtx (), temp);
6840 emit_insn (gen_rtx_USE (VOIDmode, base));
6846 ; nop instruction pattern(s).
6853 [(set_attr "op_type" "RR")])
6857 ; Special literal pool access instruction pattern(s).
6860 (define_insn "*pool_entry"
6861 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
6862 UNSPECV_POOL_ENTRY)]
6865 enum machine_mode mode = GET_MODE (PATTERN (insn));
6866 unsigned int align = GET_MODE_BITSIZE (mode);
6867 s390_output_pool_entry (operands[0], mode, align);
6870 [(set (attr "length")
6871 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
6873 (define_insn "pool_align"
6874 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
6875 UNSPECV_POOL_ALIGN)]
6878 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6880 (define_insn "pool_section_start"
6881 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
6884 [(set_attr "length" "0")])
6886 (define_insn "pool_section_end"
6887 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
6890 [(set_attr "length" "0")])
6892 (define_insn "main_base_31_small"
6893 [(set (match_operand 0 "register_operand" "=a")
6894 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6895 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6897 [(set_attr "op_type" "RR")
6898 (set_attr "type" "la")])
6900 (define_insn "main_base_31_large"
6901 [(set (match_operand 0 "register_operand" "=a")
6902 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
6903 (set (pc) (label_ref (match_operand 2 "" "")))]
6904 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6906 [(set_attr "op_type" "RI")])
6908 (define_insn "main_base_64"
6909 [(set (match_operand 0 "register_operand" "=a")
6910 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6911 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6913 [(set_attr "op_type" "RIL")
6914 (set_attr "type" "larl")])
6916 (define_insn "main_pool"
6917 [(set (match_operand 0 "register_operand" "=a")
6918 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
6919 "GET_MODE (operands[0]) == Pmode"
6924 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
6925 (const_string "larl") (const_string "la")))])
6927 (define_insn "reload_base_31"
6928 [(set (match_operand 0 "register_operand" "=a")
6929 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6930 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6931 "basr\t%0,0\;la\t%0,%1-.(%0)"
6932 [(set_attr "length" "6")
6933 (set_attr "type" "la")])
6935 (define_insn "reload_base_64"
6936 [(set (match_operand 0 "register_operand" "=a")
6937 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6938 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6940 [(set_attr "op_type" "RIL")
6941 (set_attr "type" "larl")])
6944 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
6949 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6952 ;; Insns related to generating the function prologue and epilogue.
6956 (define_expand "prologue"
6957 [(use (const_int 0))]
6959 "s390_emit_prologue (); DONE;")
6961 (define_insn "prologue_tpf"
6962 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
6963 (clobber (reg:DI 1))]
6964 "TARGET_TPF_PROFILING"
6965 "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
6966 [(set_attr "length" "14")])
6968 (define_expand "epilogue"
6969 [(use (const_int 1))]
6971 "s390_emit_epilogue (false); DONE;")
6973 (define_insn "epilogue_tpf"
6974 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
6975 (clobber (reg:DI 1))]
6976 "TARGET_TPF_PROFILING"
6977 "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
6978 [(set_attr "length" "14")])
6980 (define_expand "sibcall_epilogue"
6981 [(use (const_int 0))]
6983 "s390_emit_epilogue (true); DONE;")
6985 (define_insn "*return"
6987 (use (match_operand 0 "register_operand" "a"))]
6988 "GET_MODE (operands[0]) == Pmode"
6990 [(set_attr "op_type" "RR")
6991 (set_attr "type" "jsr")
6992 (set_attr "atype" "agen")])
6995 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
6996 ;; pointer. This is used for compatibility.
6998 (define_expand "ptr_extend"
6999 [(set (match_operand:DI 0 "register_operand" "=r")
7000 (match_operand:SI 1 "register_operand" "r"))]
7003 emit_insn (gen_anddi3 (operands[0],
7004 gen_lowpart (DImode, operands[1]),
7005 GEN_INT (0x7fffffff)));
7009 ;; Instruction definition to expand eh_return macro to support
7010 ;; swapping in special linkage return addresses.
7012 (define_expand "eh_return"
7013 [(use (match_operand 0 "register_operand" ""))]
7016 s390_emit_tpf_eh_return (operands[0]);