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2011-03-27 Vladimir Makarov <vmakarov@redhat.com>
[official-gcc.git] / gcc / config / bfin / bfin.h
blob6ebaa44f5663ff589851cd68ba0b16a9139eb157
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Analog Devices.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef _BFIN_CONFIG
23 #define _BFIN_CONFIG
24
25 #ifndef BFIN_OPTS_H
26 #include "config/bfin/bfin-opts.h"
27 #endif
28
29 #define OBJECT_FORMAT_ELF
30
31 #define BRT 1
32 #define BRF 0
33
34 /* Print subsidiary information on the compiler version in use. */
35 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
36
37 /* Predefinition in the preprocessor for this target machine */
38 #ifndef TARGET_CPU_CPP_BUILTINS
39 #define TARGET_CPU_CPP_BUILTINS() \
40 do \
41 { \
42 builtin_define_std ("bfin"); \
43 builtin_define_std ("BFIN"); \
44 builtin_define ("__ADSPBLACKFIN__"); \
45 builtin_define ("__ADSPLPBLACKFIN__"); \
46 \
47 switch (bfin_cpu_type) \
48 { \
49 case BFIN_CPU_BF512: \
50 builtin_define ("__ADSPBF512__"); \
51 builtin_define ("__ADSPBF51x__"); \
52 break; \
53 case BFIN_CPU_BF514: \
54 builtin_define ("__ADSPBF514__"); \
55 builtin_define ("__ADSPBF51x__"); \
56 break; \
57 case BFIN_CPU_BF516: \
58 builtin_define ("__ADSPBF516__"); \
59 builtin_define ("__ADSPBF51x__"); \
60 break; \
61 case BFIN_CPU_BF518: \
62 builtin_define ("__ADSPBF518__"); \
63 builtin_define ("__ADSPBF51x__"); \
64 break; \
65 case BFIN_CPU_BF522: \
66 builtin_define ("__ADSPBF522__"); \
67 builtin_define ("__ADSPBF52x__"); \
68 break; \
69 case BFIN_CPU_BF523: \
70 builtin_define ("__ADSPBF523__"); \
71 builtin_define ("__ADSPBF52x__"); \
72 break; \
73 case BFIN_CPU_BF524: \
74 builtin_define ("__ADSPBF524__"); \
75 builtin_define ("__ADSPBF52x__"); \
76 break; \
77 case BFIN_CPU_BF525: \
78 builtin_define ("__ADSPBF525__"); \
79 builtin_define ("__ADSPBF52x__"); \
80 break; \
81 case BFIN_CPU_BF526: \
82 builtin_define ("__ADSPBF526__"); \
83 builtin_define ("__ADSPBF52x__"); \
84 break; \
85 case BFIN_CPU_BF527: \
86 builtin_define ("__ADSPBF527__"); \
87 builtin_define ("__ADSPBF52x__"); \
88 break; \
89 case BFIN_CPU_BF531: \
90 builtin_define ("__ADSPBF531__"); \
91 break; \
92 case BFIN_CPU_BF532: \
93 builtin_define ("__ADSPBF532__"); \
94 break; \
95 case BFIN_CPU_BF533: \
96 builtin_define ("__ADSPBF533__"); \
97 break; \
98 case BFIN_CPU_BF534: \
99 builtin_define ("__ADSPBF534__"); \
100 break; \
101 case BFIN_CPU_BF536: \
102 builtin_define ("__ADSPBF536__"); \
103 break; \
104 case BFIN_CPU_BF537: \
105 builtin_define ("__ADSPBF537__"); \
106 break; \
107 case BFIN_CPU_BF538: \
108 builtin_define ("__ADSPBF538__"); \
109 break; \
110 case BFIN_CPU_BF539: \
111 builtin_define ("__ADSPBF539__"); \
112 break; \
113 case BFIN_CPU_BF542M: \
114 builtin_define ("__ADSPBF542M__"); \
115 case BFIN_CPU_BF542: \
116 builtin_define ("__ADSPBF542__"); \
117 builtin_define ("__ADSPBF54x__"); \
118 break; \
119 case BFIN_CPU_BF544M: \
120 builtin_define ("__ADSPBF544M__"); \
121 case BFIN_CPU_BF544: \
122 builtin_define ("__ADSPBF544__"); \
123 builtin_define ("__ADSPBF54x__"); \
124 break; \
125 case BFIN_CPU_BF547M: \
126 builtin_define ("__ADSPBF547M__"); \
127 case BFIN_CPU_BF547: \
128 builtin_define ("__ADSPBF547__"); \
129 builtin_define ("__ADSPBF54x__"); \
130 break; \
131 case BFIN_CPU_BF548M: \
132 builtin_define ("__ADSPBF548M__"); \
133 case BFIN_CPU_BF548: \
134 builtin_define ("__ADSPBF548__"); \
135 builtin_define ("__ADSPBF54x__"); \
136 break; \
137 case BFIN_CPU_BF549M: \
138 builtin_define ("__ADSPBF549M__"); \
139 case BFIN_CPU_BF549: \
140 builtin_define ("__ADSPBF549__"); \
141 builtin_define ("__ADSPBF54x__"); \
142 break; \
143 case BFIN_CPU_BF561: \
144 builtin_define ("__ADSPBF561__"); \
145 break; \
146 } \
147 \
148 if (bfin_si_revision != -1) \
149 { \
150 /* space of 0xnnnn and a NUL */ \
151 char *buf = XALLOCAVEC (char, 7); \
152 \
153 sprintf (buf, "0x%04x", bfin_si_revision); \
154 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
155 } \
156 \
157 if (bfin_workarounds) \
158 builtin_define ("__WORKAROUNDS_ENABLED"); \
159 if (ENABLE_WA_SPECULATIVE_LOADS) \
160 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
161 if (ENABLE_WA_SPECULATIVE_SYNCS) \
162 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
163 if (ENABLE_WA_INDIRECT_CALLS) \
164 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
165 if (ENABLE_WA_RETS) \
166 builtin_define ("__WORKAROUND_RETS"); \
167 \
168 if (TARGET_FDPIC) \
169 { \
170 builtin_define ("__BFIN_FDPIC__"); \
171 builtin_define ("__FDPIC__"); \
172 } \
173 if (TARGET_ID_SHARED_LIBRARY \
174 && !TARGET_SEP_DATA) \
175 builtin_define ("__ID_SHARED_LIB__"); \
176 if (flag_no_builtin) \
177 builtin_define ("__NO_BUILTIN"); \
178 if (TARGET_MULTICORE) \
179 builtin_define ("__BFIN_MULTICORE"); \
180 if (TARGET_COREA) \
181 builtin_define ("__BFIN_COREA"); \
182 if (TARGET_COREB) \
183 builtin_define ("__BFIN_COREB"); \
184 if (TARGET_SDRAM) \
185 builtin_define ("__BFIN_SDRAM"); \
186 } \
187 while (0)
188 #endif
189
190 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
191 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
192 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
193 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
194 "
195 #ifndef SUBTARGET_DRIVER_SELF_SPECS
196 # define SUBTARGET_DRIVER_SELF_SPECS
197 #endif
198
199 #define LINK_GCC_C_SEQUENCE_SPEC "\
200 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
201 "
202
203 #undef ASM_SPEC
204 #define ASM_SPEC "\
205 %{mno-fdpic:-mnopic} %{mfdpic}"
206
207 #define LINK_SPEC "\
208 %{h*} %{v:-V} \
209 %{mfdpic:-melf32bfinfd -z text} \
210 %{static:-dn -Bstatic} \
211 %{shared:-G -Bdynamic} \
212 %{symbolic:-Bsymbolic} \
213 -init __init -fini __fini "
214
215 /* Generate DSP instructions, like DSP halfword loads */
216 #define TARGET_DSP (1)
217
218 #define TARGET_DEFAULT 0
219
220 /* Maximum number of library ids we permit */
221 #define MAX_LIBRARY_ID 255
222
223 extern const char *bfin_library_id_string;
224
225 #define FUNCTION_MODE SImode
226 #define Pmode SImode
227
228 /* store-condition-codes instructions store 0 for false
229 This is the value stored for true. */
230 #define STORE_FLAG_VALUE 1
231
232 /* Define this if pushing a word on the stack
233 makes the stack pointer a smaller address. */
234 #define STACK_GROWS_DOWNWARD
235
236 #define STACK_PUSH_CODE PRE_DEC
237
238 /* Define this to nonzero if the nominal address of the stack frame
239 is at the high-address end of the local variables;
240 that is, each additional local variable allocated
241 goes at a more negative offset in the frame. */
242 #define FRAME_GROWS_DOWNWARD 1
243
244 /* We define a dummy ARGP register; the parameters start at offset 0 from
245 it. */
246 #define FIRST_PARM_OFFSET(DECL) 0
247
248 /* Offset within stack frame to start allocating local variables at.
249 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
250 first local allocated. Otherwise, it is the offset to the BEGINNING
251 of the first local allocated. */
252 #define STARTING_FRAME_OFFSET 0
253
254 /* Register to use for pushing function arguments. */
255 #define STACK_POINTER_REGNUM REG_P6
256
257 /* Base register for access to local variables of the function. */
258 #define FRAME_POINTER_REGNUM REG_P7
259
260 /* A dummy register that will be eliminated to either FP or SP. */
261 #define ARG_POINTER_REGNUM REG_ARGP
262
263 /* `PIC_OFFSET_TABLE_REGNUM'
264 The register number of the register used to address a table of
265 static data addresses in memory. In some cases this register is
266 defined by a processor's "application binary interface" (ABI).
267 When this macro is defined, RTL is generated for this register
268 once, as with the stack pointer and frame pointer registers. If
269 this macro is not defined, it is up to the machine-dependent files
270 to allocate such a register (if necessary). */
271 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
272
273 #define FDPIC_FPTR_REGNO REG_P1
274 #define FDPIC_REGNO REG_P3
275 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
276
277 /* A static chain register for nested functions. We need to use a
278 call-clobbered register for this. */
279 #define STATIC_CHAIN_REGNUM REG_P2
280
281 /* Define this if functions should assume that stack space has been
282 allocated for arguments even when their values are passed in
283 registers.
284
285 The value of this macro is the size, in bytes, of the area reserved for
286 arguments passed in registers.
287
288 This space can either be allocated by the caller or be a part of the
289 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
290 says which. */
291 #define FIXED_STACK_AREA 12
292 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
293
294 /* Define this if the above stack space is to be considered part of the
295 * space allocated by the caller. */
296 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
297
298 /* Define this if the maximum size of all the outgoing args is to be
299 accumulated and pushed during the prologue. The amount can be
300 found in the variable crtl->outgoing_args_size. */
301 #define ACCUMULATE_OUTGOING_ARGS 1
302
303 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
304
305 /* If defined, a C expression to compute the alignment for a local
306 variable. TYPE is the data type, and ALIGN is the alignment that
307 the object would ordinarily have. The value of this macro is used
308 instead of that alignment to align the object.
309
310 If this macro is not defined, then ALIGN is used.
311
312 One use of this macro is to increase alignment of medium-size
313 data to make it all fit in fewer cache lines. */
314
315 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
316
317 /* Make strings word-aligned so strcpy from constants will be faster. */
318 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
319 (TREE_CODE (EXP) == STRING_CST \
320 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
321
322 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
323 \f
324 /* Definitions for register eliminations.
325
326 This is an array of structures. Each structure initializes one pair
327 of eliminable registers. The "from" register number is given first,
328 followed by "to". Eliminations of the same "from" register are listed
329 in order of preference.
330
331 There are two registers that can always be eliminated on the i386.
332 The frame pointer and the arg pointer can be replaced by either the
333 hard frame pointer or to the stack pointer, depending upon the
334 circumstances. The hard frame pointer is not used before reload and
335 so it is not eligible for elimination. */
336
337 #define ELIMINABLE_REGS \
338 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
339 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
340 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
341
342 /* Define the offset between two registers, one to be eliminated, and the other
343 its replacement, at the start of a routine. */
344
345 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
346 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
347 \f
348 /* This processor has
349 8 data register for doing arithmetic
350 8 pointer register for doing addressing, including
351 1 stack pointer P6
352 1 frame pointer P7
353 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
354 1 condition code flag register CC
355 5 return address registers RETS/I/X/N/E
356 1 arithmetic status register (ASTAT). */
357
358 #define FIRST_PSEUDO_REGISTER 50
359
360 #define D_REGNO_P(X) ((X) <= REG_R7)
361 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
362 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
363 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
364 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
365 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
366 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
367 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
368 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
369
370 #define REGISTER_NAMES { \
371 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
372 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
373 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
374 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
375 "A0", "A1", \
376 "CC", \
377 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
378 "ARGP", \
379 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
380 }
381
382 #define SHORT_REGISTER_NAMES { \
383 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
384 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
385 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
386 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
387
388 #define HIGH_REGISTER_NAMES { \
389 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
390 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
391 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
392 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
393
394 #define DREGS_PAIR_NAMES { \
395 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
396
397 #define BYTE_REGISTER_NAMES { \
398 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
399
400
401 /* 1 for registers that have pervasive standard uses
402 and are not available for the register allocator. */
403
404 #define FIXED_REGISTERS \
405 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
406 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
407 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
408 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
409 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
410 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
411 /*lb0/1 */ \
412 1, 1 \
413 }
414
415 /* 1 for registers not available across function calls.
416 These must include the FIXED_REGISTERS and also any
417 registers that can be used without being saved.
418 The latter must include the registers where values are returned
419 and the register where structure-value addresses are passed.
420 Aside from that, you can include as many other registers as you like. */
421
422 #define CALL_USED_REGISTERS \
423 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
424 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
425 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
426 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
427 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
428 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
429 /*lb0/1 */ \
430 1, 1 \
431 }
432
433 /* Order in which to allocate registers. Each register must be
434 listed once, even those in FIXED_REGISTERS. List frame pointer
435 late and fixed registers last. Note that, in general, we prefer
436 registers listed in CALL_USED_REGISTERS, keeping the others
437 available for storage of persistent values. */
438
439 #define REG_ALLOC_ORDER \
440 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
441 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
442 REG_A0, REG_A1, \
443 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
444 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
445 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
446 REG_ASTAT, REG_SEQSTAT, REG_USP, \
447 REG_CC, REG_ARGP, \
448 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
449 }
450
451 /* Define the classes of registers for register constraints in the
452 machine description. Also define ranges of constants.
453
454 One of the classes must always be named ALL_REGS and include all hard regs.
455 If there is more than one class, another class must be named NO_REGS
456 and contain no registers.
457
458 The name GENERAL_REGS must be the name of a class (or an alias for
459 another name such as ALL_REGS). This is the class of registers
460 that is allowed by "g" or "r" in a register constraint.
461 Also, registers outside this class are allocated only when
462 instructions express preferences for them.
463
464 The classes must be numbered in nondecreasing order; that is,
465 a larger-numbered class must never be contained completely
466 in a smaller-numbered class.
467
468 For any two classes, it is very desirable that there be another
469 class that represents their union. */
470
471
472 enum reg_class
473 {
474 NO_REGS,
475 IREGS,
476 BREGS,
477 LREGS,
478 MREGS,
479 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
480 DAGREGS,
481 EVEN_AREGS,
482 ODD_AREGS,
483 AREGS,
484 CCREGS,
485 EVEN_DREGS,
486 ODD_DREGS,
487 D0REGS,
488 D1REGS,
489 D2REGS,
490 D3REGS,
491 D4REGS,
492 D5REGS,
493 D6REGS,
494 D7REGS,
495 DREGS,
496 P0REGS,
497 FDPIC_REGS,
498 FDPIC_FPTR_REGS,
499 PREGS_CLOBBERED,
500 PREGS,
501 IPREGS,
502 DPREGS,
503 MOST_REGS,
504 LT_REGS,
505 LC_REGS,
506 LB_REGS,
507 PROLOGUE_REGS,
508 NON_A_CC_REGS,
509 ALL_REGS, LIM_REG_CLASSES
510 };
511
512 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
513
514 #define GENERAL_REGS DPREGS
515
516 /* Give names of register classes as strings for dump file. */
517
518 #define REG_CLASS_NAMES \
519 { "NO_REGS", \
520 "IREGS", \
521 "BREGS", \
522 "LREGS", \
523 "MREGS", \
524 "CIRCREGS", \
525 "DAGREGS", \
526 "EVEN_AREGS", \
527 "ODD_AREGS", \
528 "AREGS", \
529 "CCREGS", \
530 "EVEN_DREGS", \
531 "ODD_DREGS", \
532 "D0REGS", \
533 "D1REGS", \
534 "D2REGS", \
535 "D3REGS", \
536 "D4REGS", \
537 "D5REGS", \
538 "D6REGS", \
539 "D7REGS", \
540 "DREGS", \
541 "P0REGS", \
542 "FDPIC_REGS", \
543 "FDPIC_FPTR_REGS", \
544 "PREGS_CLOBBERED", \
545 "PREGS", \
546 "IPREGS", \
547 "DPREGS", \
548 "MOST_REGS", \
549 "LT_REGS", \
550 "LC_REGS", \
551 "LB_REGS", \
552 "PROLOGUE_REGS", \
553 "NON_A_CC_REGS", \
554 "ALL_REGS" }
555
556 /* An initializer containing the contents of the register classes, as integers
557 which are bit masks. The Nth integer specifies the contents of class N.
558 The way the integer MASK is interpreted is that register R is in the class
559 if `MASK & (1 << R)' is 1.
560
561 When the machine has more than 32 registers, an integer does not suffice.
562 Then the integers are replaced by sub-initializers, braced groupings
563 containing several integers. Each sub-initializer must be suitable as an
564 initializer for the type `HARD_REG_SET' which is defined in
565 `hard-reg-set.h'. */
566
567 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
568 MOST_REGS as the union of DPREGS and DAGREGS. */
569
570 #define REG_CLASS_CONTENTS \
571 /* 31 - 0 63-32 */ \
572 { { 0x00000000, 0 }, /* NO_REGS */ \
573 { 0x000f0000, 0 }, /* IREGS */ \
574 { 0x00f00000, 0 }, /* BREGS */ \
575 { 0x0f000000, 0 }, /* LREGS */ \
576 { 0xf0000000, 0 }, /* MREGS */ \
577 { 0x0fff0000, 0 }, /* CIRCREGS */ \
578 { 0xffff0000, 0 }, /* DAGREGS */ \
579 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
580 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
581 { 0x00000000, 0x3 }, /* AREGS */ \
582 { 0x00000000, 0x4 }, /* CCREGS */ \
583 { 0x00000055, 0 }, /* EVEN_DREGS */ \
584 { 0x000000aa, 0 }, /* ODD_DREGS */ \
585 { 0x00000001, 0 }, /* D0REGS */ \
586 { 0x00000002, 0 }, /* D1REGS */ \
587 { 0x00000004, 0 }, /* D2REGS */ \
588 { 0x00000008, 0 }, /* D3REGS */ \
589 { 0x00000010, 0 }, /* D4REGS */ \
590 { 0x00000020, 0 }, /* D5REGS */ \
591 { 0x00000040, 0 }, /* D6REGS */ \
592 { 0x00000080, 0 }, /* D7REGS */ \
593 { 0x000000ff, 0 }, /* DREGS */ \
594 { 0x00000100, 0x000 }, /* P0REGS */ \
595 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
596 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
597 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
598 { 0x0000ff00, 0x800 }, /* PREGS */ \
599 { 0x000fff00, 0x800 }, /* IPREGS */ \
600 { 0x0000ffff, 0x800 }, /* DPREGS */ \
601 { 0xffffffff, 0x800 }, /* MOST_REGS */\
602 { 0x00000000, 0x3000 }, /* LT_REGS */\
603 { 0x00000000, 0xc000 }, /* LC_REGS */\
604 { 0x00000000, 0x30000 }, /* LB_REGS */\
605 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
606 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
607 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
608
609 #define IREG_POSSIBLE_P(OUTER) \
610 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
611 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
612 || (OUTER) == MEM || (OUTER) == ADDRESS)
613
614 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
615 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
616
617 #define INDEX_REG_CLASS PREGS
618
619 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
620 (P_REGNO_P (X) || (X) == REG_ARGP \
621 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
622 && I_REGNO_P (X)))
623
624 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
625 ((X) >= FIRST_PSEUDO_REGISTER \
626 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
627
628 #ifdef REG_OK_STRICT
629 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
630 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
631 #else
632 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
633 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
634 #endif
635
636 #define REGNO_OK_FOR_INDEX_P(X) 0
637
638 /* The same information, inverted:
639 Return the class number of the smallest class containing
640 reg number REGNO. This could be a conditional expression
641 or could index an array. */
642
643 #define REGNO_REG_CLASS(REGNO) \
644 ((REGNO) == REG_R0 ? D0REGS \
645 : (REGNO) == REG_R1 ? D1REGS \
646 : (REGNO) == REG_R2 ? D2REGS \
647 : (REGNO) == REG_R3 ? D3REGS \
648 : (REGNO) == REG_R4 ? D4REGS \
649 : (REGNO) == REG_R5 ? D5REGS \
650 : (REGNO) == REG_R6 ? D6REGS \
651 : (REGNO) == REG_R7 ? D7REGS \
652 : (REGNO) == REG_P0 ? P0REGS \
653 : (REGNO) < REG_I0 ? PREGS \
654 : (REGNO) == REG_ARGP ? PREGS \
655 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
656 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
657 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
658 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
659 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
660 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
661 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
662 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
663 : (REGNO) == REG_CC ? CCREGS \
664 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
665 : NO_REGS)
666
667 /* When this hook returns true for MODE, the compiler allows
668 registers explicitly used in the rtl to be used as spill registers
669 but prevents the compiler from extending the lifetime of these
670 registers. */
671 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
672
673 /* Do not allow to store a value in REG_CC for any mode */
674 /* Do not allow to store value in pregs if mode is not SI*/
675 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
676
677 /* Return the maximum number of consecutive registers
678 needed to represent mode MODE in a register of class CLASS. */
679 #define CLASS_MAX_NREGS(CLASS, MODE) \
680 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
681 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
682
683 #define HARD_REGNO_NREGS(REGNO, MODE) \
684 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
685 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
686 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
687
688 /* A C expression that is nonzero if hard register TO can be
689 considered for use as a rename register for FROM register */
690 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
691
692 /* A C expression that is nonzero if it is desirable to choose
693 register allocation so as to avoid move instructions between a
694 value of mode MODE1 and a value of mode MODE2.
695
696 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
697 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
698 MODE2)' must be zero. */
699 #define MODES_TIEABLE_P(MODE1, MODE2) \
700 ((MODE1) == (MODE2) \
701 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
702 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
703 && (GET_MODE_CLASS (MODE2) == MODE_INT \
704 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
705 && (MODE1) != BImode && (MODE2) != BImode \
706 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
707 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
708
709 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
710 A C expression that places additional restrictions on the register
711 class to use when it is necessary to copy value X into a register
712 in class CLASS. The value is a register class; perhaps CLASS, or
713 perhaps another, smaller class. */
714 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
715 (GET_CODE (X) == POST_INC \
716 || GET_CODE (X) == POST_DEC \
717 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
718
719 /* Function Calling Conventions. */
720
721 /* The type of the current function; normal functions are of type
722 SUBROUTINE. */
723 typedef enum {
724 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
725 } e_funkind;
726 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
727
728 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
729
730 /* Flags for the call/call_value rtl operations set up by function_arg */
731 #define CALL_NORMAL 0x00000000 /* no special processing */
732 #define CALL_LONG 0x00000001 /* always call indirect */
733 #define CALL_SHORT 0x00000002 /* always call by symbol */
734
735 typedef struct {
736 int words; /* # words passed so far */
737 int nregs; /* # registers available for passing */
738 int *arg_regs; /* array of register -1 terminated */
739 int call_cookie; /* Do special things for this call */
740 } CUMULATIVE_ARGS;
741
742 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
743
744
745 /* Initialize a variable CUM of type CUMULATIVE_ARGS
746 for a call to a function whose data type is FNTYPE.
747 For a library call, FNTYPE is 0. */
748 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
749 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
750
751 /* Define how to find the value returned by a function.
752 VALTYPE is the data type of the value (as a tree).
753 If the precise function being called is known, FUNC is its FUNCTION_DECL;
754 otherwise, FUNC is 0.
755 */
756
757 #define VALUE_REGNO(MODE) (REG_R0)
758
759 #define FUNCTION_VALUE(VALTYPE, FUNC) \
760 gen_rtx_REG (TYPE_MODE (VALTYPE), \
761 VALUE_REGNO(TYPE_MODE(VALTYPE)))
762
763 /* Define how to find the value returned by a library function
764 assuming the value has mode MODE. */
765
766 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
767
768 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
769
770 #define DEFAULT_PCC_STRUCT_RETURN 0
771
772 /* Before the prologue, the return address is in the RETS register. */
773 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
774
775 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
776
777 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
778
779 /* Call instructions don't modify the stack pointer on the Blackfin. */
780 #define INCOMING_FRAME_SP_OFFSET 0
781
782 /* Describe how we implement __builtin_eh_return. */
783 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
784 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
785 #define EH_RETURN_HANDLER_RTX \
786 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
787
788 /* Addressing Modes */
789
790 /* Nonzero if the constant value X is a legitimate general operand.
791 symbol_ref are not legitimate and will be put into constant pool.
792 See force_const_mem().
793 If -mno-pool, all constants are legitimate.
794 */
795 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
796
797 /* A number, the maximum number of registers that can appear in a
798 valid memory address. Note that it is up to you to specify a
799 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
800 would ever accept. */
801 #define MAX_REGS_PER_ADDRESS 1
802
803 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
804 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
805
806 #define HAVE_POST_INCREMENT 1
807 #define HAVE_POST_DECREMENT 1
808 #define HAVE_PRE_DECREMENT 1
809
810 /* `LEGITIMATE_PIC_OPERAND_P (X)'
811 A C expression that is nonzero if X is a legitimate immediate
812 operand on the target machine when generating position independent
813 code. You can assume that X satisfies `CONSTANT_P', so you need
814 not check this. You can also assume FLAG_PIC is true, so you need
815 not check it either. You need not define this macro if all
816 constants (including `SYMBOL_REF') can be immediate operands when
817 generating position independent code. */
818 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
819
820 #define SYMBOLIC_CONST(X) \
821 (GET_CODE (X) == SYMBOL_REF \
822 || GET_CODE (X) == LABEL_REF \
823 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
824
825 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
826
827 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
828 is done just by pretending it is already truncated. */
829 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
830
831 /* Max number of bytes we can move from memory to memory
832 in one reasonably fast instruction. */
833 #define MOVE_MAX UNITS_PER_WORD
834
835 /* If a memory-to-memory move would take MOVE_RATIO or more simple
836 move-instruction pairs, we will do a movmem or libcall instead. */
837
838 #define MOVE_RATIO(speed) 5
839
840 /* STORAGE LAYOUT: target machine storage layout
841 Define this macro as a C expression which is nonzero if accessing
842 less than a word of memory (i.e. a `char' or a `short') is no
843 faster than accessing a word of memory, i.e., if such access
844 require more than one instruction or if there is no difference in
845 cost between byte and (aligned) word loads.
846
847 When this macro is not defined, the compiler will access a field by
848 finding the smallest containing object; when it is defined, a
849 fullword load will be used if alignment permits. Unless bytes
850 accesses are faster than word accesses, using word accesses is
851 preferable since it may eliminate subsequent memory access if
852 subsequent accesses occur to other fields in the same word of the
853 structure, but to different bytes. */
854 #define SLOW_BYTE_ACCESS 0
855 #define SLOW_SHORT_ACCESS 0
856
857 /* Define this if most significant bit is lowest numbered
858 in instructions that operate on numbered bit-fields. */
859 #define BITS_BIG_ENDIAN 0
860
861 /* Define this if most significant byte of a word is the lowest numbered.
862 We can't access bytes but if we could we would in the Big Endian order. */
863 #define BYTES_BIG_ENDIAN 0
864
865 /* Define this if most significant word of a multiword number is numbered. */
866 #define WORDS_BIG_ENDIAN 0
867
868 /* number of bits in an addressable storage unit */
869 #define BITS_PER_UNIT 8
870
871 /* Width in bits of a "word", which is the contents of a machine register.
872 Note that this is not necessarily the width of data type `int';
873 if using 16-bit ints on a 68000, this would still be 32.
874 But on a machine with 16-bit registers, this would be 16. */
875 #define BITS_PER_WORD 32
876
877 /* Width of a word, in units (bytes). */
878 #define UNITS_PER_WORD 4
879
880 /* Width in bits of a pointer.
881 See also the macro `Pmode1' defined below. */
882 #define POINTER_SIZE 32
883
884 /* Allocation boundary (in *bits*) for storing pointers in memory. */
885 #define POINTER_BOUNDARY 32
886
887 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
888 #define PARM_BOUNDARY 32
889
890 /* Boundary (in *bits*) on which stack pointer should be aligned. */
891 #define STACK_BOUNDARY 32
892
893 /* Allocation boundary (in *bits*) for the code of a function. */
894 #define FUNCTION_BOUNDARY 32
895
896 /* Alignment of field after `int : 0' in a structure. */
897 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
898
899 /* No data type wants to be aligned rounder than this. */
900 #define BIGGEST_ALIGNMENT 32
901
902 /* Define this if move instructions will actually fail to work
903 when given unaligned data. */
904 #define STRICT_ALIGNMENT 1
905
906 /* (shell-command "rm c-decl.o stor-layout.o")
907 * never define PCC_BITFIELD_TYPE_MATTERS
908 * really cause some alignment problem
909 */
910
911 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
912 BITS_PER_UNIT)
913
914 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
915 BITS_PER_UNIT)
916
917
918 /* what is the 'type' of size_t */
919 #define SIZE_TYPE "long unsigned int"
920
921 /* Define this as 1 if `char' should by default be signed; else as 0. */
922 #define DEFAULT_SIGNED_CHAR 1
923 #define FLOAT_TYPE_SIZE BITS_PER_WORD
924 #define SHORT_TYPE_SIZE 16
925 #define CHAR_TYPE_SIZE 8
926 #define INT_TYPE_SIZE 32
927 #define LONG_TYPE_SIZE 32
928 #define LONG_LONG_TYPE_SIZE 64
929
930 /* Note: Fix this to depend on target switch. -- lev */
931
932 /* Note: Try to implement double and force long double. -- tonyko
933 * #define __DOUBLES_ARE_FLOATS__
934 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
935 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
936 * #define DOUBLES_ARE_FLOATS 1
937 */
938
939 #define DOUBLE_TYPE_SIZE 64
940 #define LONG_DOUBLE_TYPE_SIZE 64
941
942 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
943 A macro to update M and UNSIGNEDP when an object whose type is
944 TYPE and which has the specified mode and signedness is to be
945 stored in a register. This macro is only called when TYPE is a
946 scalar type.
947
948 On most RISC machines, which only have operations that operate on
949 a full register, define this macro to set M to `word_mode' if M is
950 an integer mode narrower than `BITS_PER_WORD'. In most cases,
951 only integer modes should be widened because wider-precision
952 floating-point operations are usually more expensive than their
953 narrower counterparts.
954
955 For most machines, the macro definition does not change UNSIGNEDP.
956 However, some machines, have instructions that preferentially
957 handle either signed or unsigned quantities of certain modes. For
958 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
959 instructions sign-extend the result to 64 bits. On such machines,
960 set UNSIGNEDP according to which kind of extension is more
961 efficient.
962
963 Do not define this macro if it would never modify M.*/
964
965 #define BFIN_PROMOTE_MODE_P(MODE) \
966 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
967 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
968
969 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
970 if (BFIN_PROMOTE_MODE_P(MODE)) \
971 { \
972 if (MODE == QImode) \
973 UNSIGNEDP = 1; \
974 else if (MODE == HImode) \
975 UNSIGNEDP = 0; \
976 (MODE) = SImode; \
977 }
978
979 /* Describing Relative Costs of Operations */
980
981 /* Do not put function addr into constant pool */
982 #define NO_FUNCTION_CSE 1
983
984 /* A C expression for the cost of moving data from a register in class FROM to
985 one in class TO. The classes are expressed using the enumeration values
986 such as `GENERAL_REGS'. A value of 2 is the default; other values are
987 interpreted relative to that.
988
989 It is not required that the cost always equal 2 when FROM is the same as TO;
990 on some machines it is expensive to move between registers if they are not
991 general registers. */
992
993 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
994 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
995
996 /* A C expression for the cost of moving data of mode M between a
997 register and memory. A value of 2 is the default; this cost is
998 relative to those in `REGISTER_MOVE_COST'.
999
1000 If moving between registers and memory is more expensive than
1001 between two registers, you should define this macro to express the
1002 relative cost. */
1003
1004 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1005 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1006
1007 /* Specify the machine mode that this machine uses
1008 for the index in the tablejump instruction. */
1009 #define CASE_VECTOR_MODE SImode
1010
1011 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1012
1013 /* Define if operations between registers always perform the operation
1014 on the full register even if a narrower mode is specified.
1015 #define WORD_REGISTER_OPERATIONS
1016 */
1017
1018 /* Evaluates to true if A and B are mac flags that can be used
1019 together in a single multiply insn. That is the case if they are
1020 both the same flag not involving M, or if one is a combination of
1021 the other with M. */
1022 #define MACFLAGS_MATCH_P(A, B) \
1023 ((A) == (B) \
1024 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1025 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1026 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1027 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1028
1029 /* Switch into a generic section. */
1030 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1031
1032 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1033 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1034
1035 typedef enum sections {
1036 CODE_DIR,
1037 DATA_DIR,
1038 LAST_SECT_NM
1039 } SECT_ENUM_T;
1040
1041 typedef enum directives {
1042 LONG_CONST_DIR,
1043 SHORT_CONST_DIR,
1044 BYTE_CONST_DIR,
1045 SPACE_DIR,
1046 INIT_DIR,
1047 LAST_DIR_NM
1048 } DIR_ENUM_T;
1049
1050 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1051 ((C) == ';' \
1052 || ((C) == '|' && (STR)[1] == '|'))
1053
1054 #define TEXT_SECTION_ASM_OP ".text;"
1055 #define DATA_SECTION_ASM_OP ".data;"
1056
1057 #define ASM_APP_ON ""
1058 #define ASM_APP_OFF ""
1059
1060 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1061 do { fputs (".global ", FILE); \
1062 assemble_name (FILE, NAME); \
1063 fputc (';',FILE); \
1064 fputc ('\n',FILE); \
1065 } while (0)
1066
1067 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1068 do { \
1069 fputs (".type ", FILE); \
1070 assemble_name (FILE, NAME); \
1071 fputs (", STT_FUNC", FILE); \
1072 fputc (';',FILE); \
1073 fputc ('\n',FILE); \
1074 ASM_OUTPUT_LABEL(FILE, NAME); \
1075 } while (0)
1076
1077 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1078 do { assemble_name (FILE, NAME); \
1079 fputs (":\n",FILE); \
1080 } while (0)
1081
1082 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1083 do { fprintf (FILE, "_%s", NAME); \
1084 } while (0)
1085
1086 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1087 do { char __buf[256]; \
1088 fprintf (FILE, "\t.dd\t"); \
1089 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1090 assemble_name (FILE, __buf); \
1091 fputc (';', FILE); \
1092 fputc ('\n', FILE); \
1093 } while (0)
1094
1095 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1096 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1097
1098 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1099 do { \
1100 char __buf[256]; \
1101 fprintf (FILE, "\t.dd\t"); \
1102 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1103 assemble_name (FILE, __buf); \
1104 fputs (" - ", FILE); \
1105 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1106 assemble_name (FILE, __buf); \
1107 fputc (';', FILE); \
1108 fputc ('\n', FILE); \
1109 } while (0)
1110
1111 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1112 do { \
1113 if ((LOG) != 0) \
1114 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1115 } while (0)
1116
1117 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1118 do { \
1119 asm_output_skip (FILE, SIZE); \
1120 } while (0)
1121
1122 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1123 do { \
1124 switch_to_section (data_section); \
1125 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1126 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1127 ASM_OUTPUT_LABEL (FILE, NAME); \
1128 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1129 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1130 } while (0)
1131
1132 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1133 do { \
1134 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1135 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1136
1137 #define ASM_COMMENT_START "//"
1138
1139 #define FUNCTION_PROFILER(FILE, LABELNO) \
1140 do { \
1141 fprintf (FILE, "\tCALL __mcount;\n"); \
1142 } while(0)
1143
1144 #undef NO_PROFILE_COUNTERS
1145 #define NO_PROFILE_COUNTERS 1
1146
1147 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1148 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1149
1150 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1151
1152 /* This works for GAS and some other assemblers. */
1153 #define SET_ASM_OP ".set "
1154
1155 /* DBX register number for a given compiler register number */
1156 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1157
1158 #define SIZE_ASM_OP "\t.size\t"
1159
1160 extern int splitting_for_sched, splitting_loops;
1161
1162 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1163
1164 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1165 #define TARGET_SUPPORTS_SYNC_CALLS 0
1166 #endif
1167
1168 #endif /* _BFIN_CONFIG */
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