gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 88, 92-98, 1999, 2000 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_regnotes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "rtl.h"
  80 #include "tm_p.h"
  81 #include "flags.h"
  82 #include "regs.h"
  83 #include "hard-reg-set.h"
  84 #include "basic-block.h"
  85 #include "insn-config.h"
  86 #include "function.h"
  87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
  88 #include "expr.h"
  89 #include "insn-flags.h"
  90 #include "insn-codes.h"
  91 #include "insn-attr.h"
  92 #include "recog.h"
  93 #include "real.h"
  94 #include "toplev.h"
  95
  96 /* It is not safe to use ordinary gen_lowpart in combine.
  97    Use gen_lowpart_for_combine instead.  See comments there.  */
  98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
  99
 100 /* Number of attempts to combine instructions in this function.  */
 101
 102 static int combine_attempts;
 103
 104 /* Number of attempts that got as far as substitution in this function.  */
 105
 106 static int combine_merges;
 107
 108 /* Number of instructions combined with added SETs in this function.  */
 109
 110 static int combine_extras;
 111
 112 /* Number of instructions combined in this function.  */
 113
 114 static int combine_successes;
 115
 116 /* Totals over entire compilation.  */
 117
 118 static int total_attempts, total_merges, total_extras, total_successes;
 119
 120 /* Define a default value for REVERSIBLE_CC_MODE.
 121    We can never assume that a condition code mode is safe to reverse unless
 122    the md tells us so.  */
 123 #ifndef REVERSIBLE_CC_MODE
 124 #define REVERSIBLE_CC_MODE(MODE) 0
 125 #endif
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* Maximum register number, which is the size of the tables below.  */
 143
 144 static int combine_max_regno;
 145
 146 /* Record last point of death of (hard or pseudo) register n.  */
 147
 148 static rtx *reg_last_death;
 149
 150 /* Record last point of modification of (hard or pseudo) register n.  */
 151
 152 static rtx *reg_last_set;
 153
 154 /* Record the cuid of the last insn that invalidated memory
 155    (anything that writes memory, and subroutine calls, but not pushes).  */
 156
 157 static int mem_last_set;
 158
 159 /* Record the cuid of the last CALL_INSN
 160    so we can tell whether a potential combination crosses any calls.  */
 161
 162 static int last_call_cuid;
 163
 164 /* When `subst' is called, this is the insn that is being modified
 165    (by combining in a previous insn).  The PATTERN of this insn
 166    is still the old pattern partially modified and it should not be
 167    looked at, but this may be used to examine the successors of the insn
 168    to judge whether a simplification is valid.  */
 169
 170 static rtx subst_insn;
 171
 172 /* This is an insn that belongs before subst_insn, but is not currently
 173    on the insn chain.  */
 174
 175 static rtx subst_prev_insn;
 176
 177 /* This is the lowest CUID that `subst' is currently dealing with.
 178    get_last_value will not return a value if the register was set at or
 179    after this CUID.  If not for this mechanism, we could get confused if
 180    I2 or I1 in try_combine were an insn that used the old value of a register
 181    to obtain a new value.  In that case, we might erroneously get the
 182    new value of the register when we wanted the old one.  */
 183
 184 static int subst_low_cuid;
 185
 186 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 187    must consider all these registers to be always live.  */
 188
 189 static HARD_REG_SET newpat_used_regs;
 190
 191 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 192    insn is the earlier than I2 or I3, combine should rescan starting at
 193    that location.  */
 194
 195 static rtx added_links_insn;
 196
 197 /* Basic block number of the block in which we are performing combines.  */
 198 static int this_basic_block;
 199
 200 /* A bitmap indicating which blocks had registers go dead at entry.
 201    After combine, we'll need to re-do global life analysis with
 202    those blocks as starting points.  */
 203 static sbitmap refresh_blocks;
 204 static int need_refresh;
 205 \f
 206 /* The next group of arrays allows the recording of the last value assigned
 207    to (hard or pseudo) register n.  We use this information to see if a
 208    operation being processed is redundant given a prior operation performed
 209    on the register.  For example, an `and' with a constant is redundant if
 210    all the zero bits are already known to be turned off.
 211
 212    We use an approach similar to that used by cse, but change it in the
 213    following ways:
 214
 215    (1) We do not want to reinitialize at each label.
 216    (2) It is useful, but not critical, to know the actual value assigned
 217        to a register.  Often just its form is helpful.
 218
 219    Therefore, we maintain the following arrays:
 220
 221    reg_last_set_value           the last value assigned
 222    reg_last_set_label           records the value of label_tick when the
 223                                 register was assigned
 224    reg_last_set_table_tick      records the value of label_tick when a
 225                                 value using the register is assigned
 226    reg_last_set_invalid         set to non-zero when it is not valid
 227                                 to use the value of this register in some
 228                                 register's value
 229
 230    To understand the usage of these tables, it is important to understand
 231    the distinction between the value in reg_last_set_value being valid
 232    and the register being validly contained in some other expression in the
 233    table.
 234
 235    Entry I in reg_last_set_value is valid if it is non-zero, and either
 236    reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
 237
 238    Register I may validly appear in any expression returned for the value
 239    of another register if reg_n_sets[i] is 1.  It may also appear in the
 240    value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
 241    reg_last_set_invalid[j] is zero.
 242
 243    If an expression is found in the table containing a register which may
 244    not validly appear in an expression, the register is replaced by
 245    something that won't match, (clobber (const_int 0)).
 246
 247    reg_last_set_invalid[i] is set non-zero when register I is being assigned
 248    to and reg_last_set_table_tick[i] == label_tick.  */
 249
 250 /* Record last value assigned to (hard or pseudo) register n.  */
 251
 252 static rtx *reg_last_set_value;
 253
 254 /* Record the value of label_tick when the value for register n is placed in
 255    reg_last_set_value[n].  */
 256
 257 static int *reg_last_set_label;
 258
 259 /* Record the value of label_tick when an expression involving register n
 260    is placed in reg_last_set_value.  */
 261
 262 static int *reg_last_set_table_tick;
 263
 264 /* Set non-zero if references to register n in expressions should not be
 265    used.  */
 266
 267 static char *reg_last_set_invalid;
 268
 269 /* Incremented for each label.  */
 270
 271 static int label_tick;
 272
 273 /* Some registers that are set more than once and used in more than one
 274    basic block are nevertheless always set in similar ways.  For example,
 275    a QImode register may be loaded from memory in two places on a machine
 276    where byte loads zero extend.
 277
 278    We record in the following array what we know about the nonzero
 279    bits of a register, specifically which bits are known to be zero.
 280
 281    If an entry is zero, it means that we don't know anything special.  */
 282
 283 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
 284
 285 /* Mode used to compute significance in reg_nonzero_bits.  It is the largest
 286    integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 287
 288 static enum machine_mode nonzero_bits_mode;
 289
 290 /* Nonzero if we know that a register has some leading bits that are always
 291    equal to the sign bit.  */
 292
 293 static char *reg_sign_bit_copies;
 294
 295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
 296    It is zero while computing them and after combine has completed.  This
 297    former test prevents propagating values based on previously set values,
 298    which can be incorrect if a variable is modified in a loop.  */
 299
 300 static int nonzero_sign_valid;
 301
 302 /* These arrays are maintained in parallel with reg_last_set_value
 303    and are used to store the mode in which the register was last set,
 304    the bits that were known to be zero when it was last set, and the
 305    number of sign bits copies it was known to have when it was last set.  */
 306
 307 static enum machine_mode *reg_last_set_mode;
 308 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
 309 static char *reg_last_set_sign_bit_copies;
 310 \f
 311 /* Record one modification to rtl structure
 312    to be undone by storing old_contents into *where.
 313    is_int is 1 if the contents are an int.  */
 314
 315 struct undo
 316 {
 317   struct undo *next;
 318   int is_int;
 319   union {rtx r; int i;} old_contents;
 320   union {rtx *r; int *i;} where;
 321 };
 322
 323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 324    num_undo says how many are currently recorded.
 325
 326    storage is nonzero if we must undo the allocation of new storage.
 327    The value of storage is what to pass to obfree.
 328
 329    other_insn is nonzero if we have modified some other insn in the process
 330    of working on subst_insn.  It must be verified too.
 331
 332    previous_undos is the value of undobuf.undos when we started processing
 333    this substitution.  This will prevent gen_rtx_combine from re-used a piece
 334    from the previous expression.  Doing so can produce circular rtl
 335    structures.  */
 336
 337 struct undobuf
 338 {
 339   char *storage;
 340   struct undo *undos;
 341   struct undo *frees;
 342   struct undo *previous_undos;
 343   rtx other_insn;
 344 };
 345
 346 static struct undobuf undobuf;
 347
 348 /* Number of times the pseudo being substituted for
 349    was found and replaced.  */
 350
 351 static int n_occurrences;
 352
 353 static void do_SUBST                    PARAMS ((rtx *, rtx));
 354 static void do_SUBST_INT                PARAMS ((int *, int));
 355 static void init_reg_last_arrays        PARAMS ((void));
 356 static void setup_incoming_promotions   PARAMS ((void));
 357 static void set_nonzero_bits_and_sign_copies  PARAMS ((rtx, rtx, void *));
 358 static int can_combine_p        PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
 359 static int sets_function_arg_p  PARAMS ((rtx));
 360 static int combinable_i3pat     PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
 361 static int contains_muldiv      PARAMS ((rtx));
 362 static rtx try_combine          PARAMS ((rtx, rtx, rtx));
 363 static void undo_all            PARAMS ((void));
 364 static void undo_commit         PARAMS ((void));
 365 static rtx *find_split_point    PARAMS ((rtx *, rtx));
 366 static rtx subst                PARAMS ((rtx, rtx, rtx, int, int));
 367 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
 368 static rtx simplify_if_then_else  PARAMS ((rtx));
 369 static rtx simplify_set         PARAMS ((rtx));
 370 static rtx simplify_logical     PARAMS ((rtx, int));
 371 static rtx expand_compound_operation  PARAMS ((rtx));
 372 static rtx expand_field_assignment  PARAMS ((rtx));
 373 static rtx make_extraction      PARAMS ((enum machine_mode, rtx, int, rtx, int,
 374                                          int, int, int));
 375 static rtx extract_left_shift   PARAMS ((rtx, int));
 376 static rtx make_compound_operation  PARAMS ((rtx, enum rtx_code));
 377 static int get_pos_from_mask    PARAMS ((unsigned HOST_WIDE_INT, int *));
 378 static rtx force_to_mode        PARAMS ((rtx, enum machine_mode,
 379                                          unsigned HOST_WIDE_INT, rtx, int));
 380 static rtx if_then_else_cond    PARAMS ((rtx, rtx *, rtx *));
 381 static rtx known_cond           PARAMS ((rtx, enum rtx_code, rtx, rtx));
 382 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
 383 static rtx make_field_assignment  PARAMS ((rtx));
 384 static rtx apply_distributive_law  PARAMS ((rtx));
 385 static rtx simplify_and_const_int  PARAMS ((rtx, enum machine_mode, rtx,
 386                                             unsigned HOST_WIDE_INT));
 387 static unsigned HOST_WIDE_INT nonzero_bits  PARAMS ((rtx, enum machine_mode));
 388 static int num_sign_bit_copies  PARAMS ((rtx, enum machine_mode));
 389 static int merge_outer_ops      PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
 390                                          enum rtx_code, HOST_WIDE_INT,
 391                                          enum machine_mode, int *));
 392 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
 393                                          rtx, int));
 394 static int recog_for_combine    PARAMS ((rtx *, rtx, rtx *));
 395 static rtx gen_lowpart_for_combine  PARAMS ((enum machine_mode, rtx));
 396 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
 397                                     ...));
 398 static rtx gen_binary           PARAMS ((enum rtx_code, enum machine_mode,
 399                                          rtx, rtx));
 400 static rtx gen_unary            PARAMS ((enum rtx_code, enum machine_mode,
 401                                          enum machine_mode, rtx));
 402 static enum rtx_code simplify_comparison  PARAMS ((enum rtx_code, rtx *, rtx *));
 403 static int reversible_comparison_p  PARAMS ((rtx));
 404 static void update_table_tick   PARAMS ((rtx));
 405 static void record_value_for_reg  PARAMS ((rtx, rtx, rtx));
 406 static void check_promoted_subreg PARAMS ((rtx, rtx));
 407 static void record_dead_and_set_regs_1  PARAMS ((rtx, rtx, void *));
 408 static void record_dead_and_set_regs  PARAMS ((rtx));
 409 static int get_last_value_validate  PARAMS ((rtx *, rtx, int, int));
 410 static rtx get_last_value       PARAMS ((rtx));
 411 static int use_crosses_set_p    PARAMS ((rtx, int));
 412 static void reg_dead_at_p_1     PARAMS ((rtx, rtx, void *));
 413 static int reg_dead_at_p        PARAMS ((rtx, rtx));
 414 static void move_deaths         PARAMS ((rtx, rtx, int, rtx, rtx *));
 415 static int reg_bitfield_target_p  PARAMS ((rtx, rtx));
 416 static void distribute_notes    PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
 417 static void distribute_links    PARAMS ((rtx));
 418 static void mark_used_regs_combine PARAMS ((rtx));
 419 static int insn_cuid            PARAMS ((rtx));
 420 static void record_promoted_value PARAMS ((rtx, rtx));
 421 \f
 422 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 423    insn.  The substitution can be undone by undo_all.  If INTO is already
 424    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 425    also call SUBST, we have to compute it before we put anything into
 426    the undo table.  */
 427
 428 static void
 429 do_SUBST(into, newval)
 430      rtx *into, newval;
 431 {
 432   struct undo *buf;
 433   rtx oldval = *into;
 434
 435   if (oldval == newval)
 436     return;
 437
 438   if (undobuf.frees)
 439     buf = undobuf.frees, undobuf.frees = buf->next;
 440   else
 441     buf = (struct undo *) xmalloc (sizeof (struct undo));
 442
 443   buf->is_int = 0;
 444   buf->where.r = into;
 445   buf->old_contents.r = oldval;
 446   *into = newval;
 447
 448   buf->next = undobuf.undos, undobuf.undos = buf;
 449 }
 450
 451 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 452
 453 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 454    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 455    not safe.  */
 456
 457 static void
 458 do_SUBST_INT(into, newval)
 459      int *into, newval;
 460 {
 461   struct undo *buf;
 462   int oldval = *into;
 463
 464   if (oldval == newval)
 465     return;
 466
 467   if (undobuf.frees)
 468     buf = undobuf.frees, undobuf.frees = buf->next;
 469   else
 470     buf = (struct undo *) xmalloc (sizeof (struct undo));
 471
 472   buf->is_int = 1;
 473   buf->where.i = into;
 474   buf->old_contents.i = oldval;
 475   *into = newval;
 476
 477   buf->next = undobuf.undos, undobuf.undos = buf;
 478 }
 479
 480 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 481 \f
 482 /* Main entry point for combiner.  F is the first insn of the function.
 483    NREGS is the first unused pseudo-reg number.  */
 484
 485 void
 486 combine_instructions (f, nregs)
 487      rtx f;
 488      int nregs;
 489 {
 490   register rtx insn, next;
 491 #ifdef HAVE_cc0
 492   register rtx prev;
 493 #endif
 494   register int i;
 495   register rtx links, nextlinks;
 496
 497   combine_attempts = 0;
 498   combine_merges = 0;
 499   combine_extras = 0;
 500   combine_successes = 0;
 501
 502   combine_max_regno = nregs;
 503
 504   reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
 505                       xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
 506   reg_sign_bit_copies = (char *) xcalloc (nregs, sizeof (char));
 507
 508   reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
 509   reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
 510   reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
 511   reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
 512   reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
 513   reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
 514   reg_last_set_mode
 515     = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
 516   reg_last_set_nonzero_bits
 517     = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
 518   reg_last_set_sign_bit_copies
 519     = (char *) xmalloc (nregs * sizeof (char));
 520
 521   init_reg_last_arrays ();
 522
 523   init_recog_no_volatile ();
 524
 525   /* Compute maximum uid value so uid_cuid can be allocated.  */
 526
 527   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 528     if (INSN_UID (insn) > i)
 529       i = INSN_UID (insn);
 530
 531   uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
 532   max_uid_cuid = i;
 533
 534   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 535
 536   /* Don't use reg_nonzero_bits when computing it.  This can cause problems
 537      when, for example, we have j <<= 1 in a loop.  */
 538
 539   nonzero_sign_valid = 0;
 540
 541   /* Compute the mapping from uids to cuids.
 542      Cuids are numbers assigned to insns, like uids,
 543      except that cuids increase monotonically through the code.
 544
 545      Scan all SETs and see if we can deduce anything about what
 546      bits are known to be zero for some registers and how many copies
 547      of the sign bit are known to exist for those registers.
 548
 549      Also set any known values so that we can use it while searching
 550      for what bits are known to be set.  */
 551
 552   label_tick = 1;
 553
 554   /* We need to initialize it here, because record_dead_and_set_regs may call
 555      get_last_value.  */
 556   subst_prev_insn = NULL_RTX;
 557
 558   setup_incoming_promotions ();
 559
 560   refresh_blocks = sbitmap_alloc (n_basic_blocks);
 561   sbitmap_zero (refresh_blocks);
 562   need_refresh = 0;
 563
 564   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 565     {
 566       uid_cuid[INSN_UID (insn)] = ++i;
 567       subst_low_cuid = i;
 568       subst_insn = insn;
 569
 570       if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 571         {
 572           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 573                        NULL);
 574           record_dead_and_set_regs (insn);
 575
 576 #ifdef AUTO_INC_DEC
 577           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 578             if (REG_NOTE_KIND (links) == REG_INC)
 579               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 580                                                 NULL);
 581 #endif
 582         }
 583
 584       if (GET_CODE (insn) == CODE_LABEL)
 585         label_tick++;
 586     }
 587
 588   nonzero_sign_valid = 1;
 589
 590   /* Now scan all the insns in forward order.  */
 591
 592   this_basic_block = -1;
 593   label_tick = 1;
 594   last_call_cuid = 0;
 595   mem_last_set = 0;
 596   init_reg_last_arrays ();
 597   setup_incoming_promotions ();
 598
 599   for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
 600     {
 601       next = 0;
 602
 603       /* If INSN starts a new basic block, update our basic block number.  */
 604       if (this_basic_block + 1 < n_basic_blocks
 605           && BLOCK_HEAD (this_basic_block + 1) == insn)
 606         this_basic_block++;
 607
 608       if (GET_CODE (insn) == CODE_LABEL)
 609         label_tick++;
 610
 611       else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 612         {
 613           /* See if we know about function return values before this
 614              insn based upon SUBREG flags.  */
 615           check_promoted_subreg (insn, PATTERN (insn));
 616
 617           /* Try this insn with each insn it links back to.  */
 618
 619           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 620             if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
 621               goto retry;
 622
 623           /* Try each sequence of three linked insns ending with this one.  */
 624
 625           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 626             for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
 627                  nextlinks = XEXP (nextlinks, 1))
 628               if ((next = try_combine (insn, XEXP (links, 0),
 629                                        XEXP (nextlinks, 0))) != 0)
 630                 goto retry;
 631
 632 #ifdef HAVE_cc0
 633           /* Try to combine a jump insn that uses CC0
 634              with a preceding insn that sets CC0, and maybe with its
 635              logical predecessor as well.
 636              This is how we make decrement-and-branch insns.
 637              We need this special code because data flow connections
 638              via CC0 do not get entered in LOG_LINKS.  */
 639
 640           if (GET_CODE (insn) == JUMP_INSN
 641               && (prev = prev_nonnote_insn (insn)) != 0
 642               && GET_CODE (prev) == INSN
 643               && sets_cc0_p (PATTERN (prev)))
 644             {
 645               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 646                 goto retry;
 647
 648               for (nextlinks = LOG_LINKS (prev); nextlinks;
 649                    nextlinks = XEXP (nextlinks, 1))
 650                 if ((next = try_combine (insn, prev,
 651                                          XEXP (nextlinks, 0))) != 0)
 652                   goto retry;
 653             }
 654
 655           /* Do the same for an insn that explicitly references CC0.  */
 656           if (GET_CODE (insn) == INSN
 657               && (prev = prev_nonnote_insn (insn)) != 0
 658               && GET_CODE (prev) == INSN
 659               && sets_cc0_p (PATTERN (prev))
 660               && GET_CODE (PATTERN (insn)) == SET
 661               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 662             {
 663               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 664                 goto retry;
 665
 666               for (nextlinks = LOG_LINKS (prev); nextlinks;
 667                    nextlinks = XEXP (nextlinks, 1))
 668                 if ((next = try_combine (insn, prev,
 669                                          XEXP (nextlinks, 0))) != 0)
 670                   goto retry;
 671             }
 672
 673           /* Finally, see if any of the insns that this insn links to
 674              explicitly references CC0.  If so, try this insn, that insn,
 675              and its predecessor if it sets CC0.  */
 676           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 677             if (GET_CODE (XEXP (links, 0)) == INSN
 678                 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 679                 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 680                 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 681                 && GET_CODE (prev) == INSN
 682                 && sets_cc0_p (PATTERN (prev))
 683                 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
 684               goto retry;
 685 #endif
 686
 687           /* Try combining an insn with two different insns whose results it
 688              uses.  */
 689           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 690             for (nextlinks = XEXP (links, 1); nextlinks;
 691                  nextlinks = XEXP (nextlinks, 1))
 692               if ((next = try_combine (insn, XEXP (links, 0),
 693                                        XEXP (nextlinks, 0))) != 0)
 694                 goto retry;
 695
 696           if (GET_CODE (insn) != NOTE)
 697             record_dead_and_set_regs (insn);
 698
 699         retry:
 700           ;
 701         }
 702     }
 703
 704   if (need_refresh)
 705     {
 706       compute_bb_for_insn (get_max_uid ());
 707       update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
 708                         PROP_DEATH_NOTES);
 709     }
 710
 711   /* Clean up.  */
 712   sbitmap_free (refresh_blocks);
 713   free (reg_nonzero_bits);
 714   free (reg_sign_bit_copies);
 715   free (reg_last_death);
 716   free (reg_last_set);
 717   free (reg_last_set_value);
 718   free (reg_last_set_table_tick);
 719   free (reg_last_set_label);
 720   free (reg_last_set_invalid);
 721   free (reg_last_set_mode);
 722   free (reg_last_set_nonzero_bits);
 723   free (reg_last_set_sign_bit_copies);
 724   free (uid_cuid);
 725
 726   {
 727     struct undo *undo, *next;
 728     for (undo = undobuf.frees; undo; undo = next)
 729       {
 730         next = undo->next;
 731         free (undo);
 732       }
 733     undobuf.frees = 0;
 734   }
 735
 736   total_attempts += combine_attempts;
 737   total_merges += combine_merges;
 738   total_extras += combine_extras;
 739   total_successes += combine_successes;
 740
 741   nonzero_sign_valid = 0;
 742
 743   /* Make recognizer allow volatile MEMs again.  */
 744   init_recog ();
 745 }
 746
 747 /* Wipe the reg_last_xxx arrays in preparation for another pass.  */
 748
 749 static void
 750 init_reg_last_arrays ()
 751 {
 752   int nregs = combine_max_regno;
 753
 754   bzero ((char *) reg_last_death, nregs * sizeof (rtx));
 755   bzero ((char *) reg_last_set, nregs * sizeof (rtx));
 756   bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
 757   bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
 758   bzero ((char *) reg_last_set_label, nregs * sizeof (int));
 759   bzero (reg_last_set_invalid, nregs * sizeof (char));
 760   bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
 761   bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 762   bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
 763 }
 764 \f
 765 /* Set up any promoted values for incoming argument registers.  */
 766
 767 static void
 768 setup_incoming_promotions ()
 769 {
 770 #ifdef PROMOTE_FUNCTION_ARGS
 771   int regno;
 772   rtx reg;
 773   enum machine_mode mode;
 774   int unsignedp;
 775   rtx first = get_insns ();
 776
 777 #ifndef OUTGOING_REGNO
 778 #define OUTGOING_REGNO(N) N
 779 #endif
 780   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 781     /* Check whether this register can hold an incoming pointer
 782        argument.  FUNCTION_ARG_REGNO_P tests outgoing register
 783        numbers, so translate if necessary due to register windows.  */
 784     if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
 785         && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 786       {
 787         record_value_for_reg
 788           (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
 789                                        : SIGN_EXTEND),
 790                                       GET_MODE (reg),
 791                                       gen_rtx_CLOBBER (mode, const0_rtx)));
 792       }
 793 #endif
 794 }
 795 \f
 796 /* Called via note_stores.  If X is a pseudo that is narrower than
 797    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 798
 799    If we are setting only a portion of X and we can't figure out what
 800    portion, assume all bits will be used since we don't know what will
 801    be happening.
 802
 803    Similarly, set how many bits of X are known to be copies of the sign bit
 804    at all locations in the function.  This is the smallest number implied
 805    by any set of X.  */
 806
 807 static void
 808 set_nonzero_bits_and_sign_copies (x, set, data)
 809      rtx x;
 810      rtx set;
 811      void *data ATTRIBUTE_UNUSED;
 812 {
 813   int num;
 814
 815   if (GET_CODE (x) == REG
 816       && REGNO (x) >= FIRST_PSEUDO_REGISTER
 817       /* If this register is undefined at the start of the file, we can't
 818          say what its contents were.  */
 819       && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
 820       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
 821     {
 822       if (set == 0 || GET_CODE (set) == CLOBBER)
 823         {
 824           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 825           reg_sign_bit_copies[REGNO (x)] = 1;
 826           return;
 827         }
 828
 829       /* If this is a complex assignment, see if we can convert it into a
 830          simple assignment.  */
 831       set = expand_field_assignment (set);
 832
 833       /* If this is a simple assignment, or we have a paradoxical SUBREG,
 834          set what we know about X.  */
 835
 836       if (SET_DEST (set) == x
 837           || (GET_CODE (SET_DEST (set)) == SUBREG
 838               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
 839                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
 840               && SUBREG_REG (SET_DEST (set)) == x))
 841         {
 842           rtx src = SET_SRC (set);
 843
 844 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
 845           /* If X is narrower than a word and SRC is a non-negative
 846              constant that would appear negative in the mode of X,
 847              sign-extend it for use in reg_nonzero_bits because some
 848              machines (maybe most) will actually do the sign-extension
 849              and this is the conservative approach.
 850
 851              ??? For 2.5, try to tighten up the MD files in this regard
 852              instead of this kludge.  */
 853
 854           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
 855               && GET_CODE (src) == CONST_INT
 856               && INTVAL (src) > 0
 857               && 0 != (INTVAL (src)
 858                        & ((HOST_WIDE_INT) 1
 859                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 860             src = GEN_INT (INTVAL (src)
 861                            | ((HOST_WIDE_INT) (-1)
 862                               << GET_MODE_BITSIZE (GET_MODE (x))));
 863 #endif
 864
 865           reg_nonzero_bits[REGNO (x)]
 866             |= nonzero_bits (src, nonzero_bits_mode);
 867           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
 868           if (reg_sign_bit_copies[REGNO (x)] == 0
 869               || reg_sign_bit_copies[REGNO (x)] > num)
 870             reg_sign_bit_copies[REGNO (x)] = num;
 871         }
 872       else
 873         {
 874           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 875           reg_sign_bit_copies[REGNO (x)] = 1;
 876         }
 877     }
 878 }
 879 \f
 880 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
 881    insns that were previously combined into I3 or that will be combined
 882    into the merger of INSN and I3.
 883
 884    Return 0 if the combination is not allowed for any reason.
 885
 886    If the combination is allowed, *PDEST will be set to the single
 887    destination of INSN and *PSRC to the single source, and this function
 888    will return 1.  */
 889
 890 static int
 891 can_combine_p (insn, i3, pred, succ, pdest, psrc)
 892      rtx insn;
 893      rtx i3;
 894      rtx pred ATTRIBUTE_UNUSED;
 895      rtx succ;
 896      rtx *pdest, *psrc;
 897 {
 898   int i;
 899   rtx set = 0, src, dest;
 900   rtx p;
 901 #ifdef AUTO_INC_DEC
 902   rtx link;
 903 #endif
 904   int all_adjacent = (succ ? (next_active_insn (insn) == succ
 905                               && next_active_insn (succ) == i3)
 906                       : next_active_insn (insn) == i3);
 907
 908   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
 909      or a PARALLEL consisting of such a SET and CLOBBERs.
 910
 911      If INSN has CLOBBER parallel parts, ignore them for our processing.
 912      By definition, these happen during the execution of the insn.  When it
 913      is merged with another insn, all bets are off.  If they are, in fact,
 914      needed and aren't also supplied in I3, they may be added by
 915      recog_for_combine.  Otherwise, it won't match.
 916
 917      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
 918      note.
 919
 920      Get the source and destination of INSN.  If more than one, can't
 921      combine.  */
 922
 923   if (GET_CODE (PATTERN (insn)) == SET)
 924     set = PATTERN (insn);
 925   else if (GET_CODE (PATTERN (insn)) == PARALLEL
 926            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
 927     {
 928       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 929         {
 930           rtx elt = XVECEXP (PATTERN (insn), 0, i);
 931
 932           switch (GET_CODE (elt))
 933             {
 934             /* This is important to combine floating point insns
 935                for the SH4 port.  */
 936             case USE:
 937               /* Combining an isolated USE doesn't make sense.
 938                  We depend here on combinable_i3_pat to reject them.  */
 939               /* The code below this loop only verifies that the inputs of
 940                  the SET in INSN do not change.  We call reg_set_between_p
 941                  to verify that the REG in the USE does not change betweeen
 942                  I3 and INSN.
 943                  If the USE in INSN was for a pseudo register, the matching
 944                  insn pattern will likely match any register; combining this
 945                  with any other USE would only be safe if we knew that the
 946                  used registers have identical values, or if there was
 947                  something to tell them apart, e.g. different modes.  For
 948                  now, we forgo such compilcated tests and simply disallow
 949                  combining of USES of pseudo registers with any other USE.  */
 950               if (GET_CODE (XEXP (elt, 0)) == REG
 951                   && GET_CODE (PATTERN (i3)) == PARALLEL)
 952                 {
 953                   rtx i3pat = PATTERN (i3);
 954                   int i = XVECLEN (i3pat, 0) - 1;
 955                   int regno = REGNO (XEXP (elt, 0));
 956                   do
 957                     {
 958                       rtx i3elt = XVECEXP (i3pat, 0, i);
 959                       if (GET_CODE (i3elt) == USE
 960                           && GET_CODE (XEXP (i3elt, 0)) == REG
 961                           && (REGNO (XEXP (i3elt, 0)) == regno
 962                               ? reg_set_between_p (XEXP (elt, 0),
 963                                                    PREV_INSN (insn), i3)
 964                               : regno >= FIRST_PSEUDO_REGISTER))
 965                         return 0;
 966                     }
 967                   while (--i >= 0);
 968                 }
 969               break;
 970
 971               /* We can ignore CLOBBERs.  */
 972             case CLOBBER:
 973               break;
 974
 975             case SET:
 976               /* Ignore SETs whose result isn't used but not those that
 977                  have side-effects.  */
 978               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
 979                   && ! side_effects_p (elt))
 980                 break;
 981
 982               /* If we have already found a SET, this is a second one and
 983                  so we cannot combine with this insn.  */
 984               if (set)
 985                 return 0;
 986
 987               set = elt;
 988               break;
 989
 990             default:
 991               /* Anything else means we can't combine.  */
 992               return 0;
 993             }
 994         }
 995
 996       if (set == 0
 997           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
 998              so don't do anything with it.  */
 999           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1000         return 0;
1001     }
1002   else
1003     return 0;
1004
1005   if (set == 0)
1006     return 0;
1007
1008   set = expand_field_assignment (set);
1009   src = SET_SRC (set), dest = SET_DEST (set);
1010
1011   /* Don't eliminate a store in the stack pointer.  */
1012   if (dest == stack_pointer_rtx
1013       /* If we couldn't eliminate a field assignment, we can't combine.  */
1014       || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1015       /* Don't combine with an insn that sets a register to itself if it has
1016          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1017       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1018       /* Can't merge a function call.  */
1019       || GET_CODE (src) == CALL
1020       /* Don't eliminate a function call argument.  */
1021       || (GET_CODE (i3) == CALL_INSN
1022           && (find_reg_fusage (i3, USE, dest)
1023               || (GET_CODE (dest) == REG
1024                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1025                   && global_regs[REGNO (dest)])))
1026       /* Don't substitute into an incremented register.  */
1027       || FIND_REG_INC_NOTE (i3, dest)
1028       || (succ && FIND_REG_INC_NOTE (succ, dest))
1029 #if 0
1030       /* Don't combine the end of a libcall into anything.  */
1031       /* ??? This gives worse code, and appears to be unnecessary, since no
1032          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1033          use REG_RETVAL notes for noconflict blocks, but other code here
1034          makes sure that those insns don't disappear.  */
1035       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1036 #endif
1037       /* Make sure that DEST is not used after SUCC but before I3.  */
1038       || (succ && ! all_adjacent
1039           && reg_used_between_p (dest, succ, i3))
1040       /* Make sure that the value that is to be substituted for the register
1041          does not use any registers whose values alter in between.  However,
1042          If the insns are adjacent, a use can't cross a set even though we
1043          think it might (this can happen for a sequence of insns each setting
1044          the same destination; reg_last_set of that register might point to
1045          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1046          equivalent to the memory so the substitution is valid even if there
1047          are intervening stores.  Also, don't move a volatile asm or
1048          UNSPEC_VOLATILE across any other insns.  */
1049       || (! all_adjacent
1050           && (((GET_CODE (src) != MEM
1051                 || ! find_reg_note (insn, REG_EQUIV, src))
1052                && use_crosses_set_p (src, INSN_CUID (insn)))
1053               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1054               || GET_CODE (src) == UNSPEC_VOLATILE))
1055       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1056          better register allocation by not doing the combine.  */
1057       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1058       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1059       /* Don't combine across a CALL_INSN, because that would possibly
1060          change whether the life span of some REGs crosses calls or not,
1061          and it is a pain to update that information.
1062          Exception: if source is a constant, moving it later can't hurt.
1063          Accept that special case, because it helps -fforce-addr a lot.  */
1064       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1065     return 0;
1066
1067   /* DEST must either be a REG or CC0.  */
1068   if (GET_CODE (dest) == REG)
1069     {
1070       /* If register alignment is being enforced for multi-word items in all
1071          cases except for parameters, it is possible to have a register copy
1072          insn referencing a hard register that is not allowed to contain the
1073          mode being copied and which would not be valid as an operand of most
1074          insns.  Eliminate this problem by not combining with such an insn.
1075
1076          Also, on some machines we don't want to extend the life of a hard
1077          register.
1078
1079          This is the same test done in can_combine except that we don't test
1080          if SRC is a CALL operation to permit a hard register with
1081          SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1082          into account.  */
1083
1084       if (GET_CODE (src) == REG
1085           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1086                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1087               /* Don't extend the life of a hard register unless it is
1088                  user variable (if we have few registers) or it can't
1089                  fit into the desired register (meaning something special
1090                  is going on).
1091                  Also avoid substituting a return register into I3, because
1092                  reload can't handle a conflict with constraints of other
1093                  inputs.  */
1094               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1095                   && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1096                       || (SMALL_REGISTER_CLASSES
1097                           && ((! all_adjacent && ! REG_USERVAR_P (src))
1098                               || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1099                                   && ! REG_USERVAR_P (src))))))))
1100         return 0;
1101     }
1102   else if (GET_CODE (dest) != CC0)
1103     return 0;
1104
1105   /* Don't substitute for a register intended as a clobberable operand.
1106      Similarly, don't substitute an expression containing a register that
1107      will be clobbered in I3.  */
1108   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1109     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1110       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1111           && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1112                                        src)
1113               || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1114         return 0;
1115
1116   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1117      or not), reject, unless nothing volatile comes between it and I3 */
1118
1119   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1120     {
1121       /* Make sure succ doesn't contain a volatile reference.  */
1122       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1123         return 0;
1124
1125       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1126         if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1127           && p != succ && volatile_refs_p (PATTERN (p)))
1128         return 0;
1129     }
1130
1131   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1132      to be an explicit register variable, and was chosen for a reason.  */
1133
1134   if (GET_CODE (src) == ASM_OPERANDS
1135       && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1136     return 0;
1137
1138   /* If there are any volatile insns between INSN and I3, reject, because
1139      they might affect machine state.  */
1140
1141   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1142     if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1143         && p != succ && volatile_insn_p (PATTERN (p)))
1144       return 0;
1145
1146   /* If INSN or I2 contains an autoincrement or autodecrement,
1147      make sure that register is not used between there and I3,
1148      and not already used in I3 either.
1149      Also insist that I3 not be a jump; if it were one
1150      and the incremented register were spilled, we would lose.  */
1151
1152 #ifdef AUTO_INC_DEC
1153   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1154     if (REG_NOTE_KIND (link) == REG_INC
1155         && (GET_CODE (i3) == JUMP_INSN
1156             || reg_used_between_p (XEXP (link, 0), insn, i3)
1157             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1158       return 0;
1159 #endif
1160
1161 #ifdef HAVE_cc0
1162   /* Don't combine an insn that follows a CC0-setting insn.
1163      An insn that uses CC0 must not be separated from the one that sets it.
1164      We do, however, allow I2 to follow a CC0-setting insn if that insn
1165      is passed as I1; in that case it will be deleted also.
1166      We also allow combining in this case if all the insns are adjacent
1167      because that would leave the two CC0 insns adjacent as well.
1168      It would be more logical to test whether CC0 occurs inside I1 or I2,
1169      but that would be much slower, and this ought to be equivalent.  */
1170
1171   p = prev_nonnote_insn (insn);
1172   if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1173       && ! all_adjacent)
1174     return 0;
1175 #endif
1176
1177   /* If we get here, we have passed all the tests and the combination is
1178      to be allowed.  */
1179
1180   *pdest = dest;
1181   *psrc = src;
1182
1183   return 1;
1184 }
1185 \f
1186 /* Check if PAT is an insn - or a part of it - used to set up an
1187    argument for a function in a hard register.  */
1188
1189 static int
1190 sets_function_arg_p (pat)
1191      rtx pat;
1192 {
1193   int i;
1194   rtx inner_dest;
1195
1196   switch (GET_CODE (pat))
1197     {
1198     case INSN:
1199       return sets_function_arg_p (PATTERN (pat));
1200
1201     case PARALLEL:
1202       for (i = XVECLEN (pat, 0); --i >= 0;)
1203         if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1204           return 1;
1205
1206       break;
1207
1208     case SET:
1209       inner_dest = SET_DEST (pat);
1210       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1211              || GET_CODE (inner_dest) == SUBREG
1212              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1213         inner_dest = XEXP (inner_dest, 0);
1214
1215       return (GET_CODE (inner_dest) == REG
1216               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1217               && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1218
1219     default:
1220       break;
1221     }
1222
1223   return 0;
1224 }
1225
1226 /* LOC is the location within I3 that contains its pattern or the component
1227    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1228
1229    One problem is if I3 modifies its output, as opposed to replacing it
1230    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1231    so would produce an insn that is not equivalent to the original insns.
1232
1233    Consider:
1234
1235          (set (reg:DI 101) (reg:DI 100))
1236          (set (subreg:SI (reg:DI 101) 0) <foo>)
1237
1238    This is NOT equivalent to:
1239
1240          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1241                     (set (reg:DI 101) (reg:DI 100))])
1242
1243    Not only does this modify 100 (in which case it might still be valid
1244    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1245
1246    We can also run into a problem if I2 sets a register that I1
1247    uses and I1 gets directly substituted into I3 (not via I2).  In that
1248    case, we would be getting the wrong value of I2DEST into I3, so we
1249    must reject the combination.  This case occurs when I2 and I1 both
1250    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1251    If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1252    of a SET must prevent combination from occurring.
1253
1254    On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1255    if the destination of a SET is a hard register that isn't a user
1256    variable.
1257
1258    Before doing the above check, we first try to expand a field assignment
1259    into a set of logical operations.
1260
1261    If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1262    we place a register that is both set and used within I3.  If more than one
1263    such register is detected, we fail.
1264
1265    Return 1 if the combination is valid, zero otherwise.  */
1266
1267 static int
1268 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1269      rtx i3;
1270      rtx *loc;
1271      rtx i2dest;
1272      rtx i1dest;
1273      int i1_not_in_src;
1274      rtx *pi3dest_killed;
1275 {
1276   rtx x = *loc;
1277
1278   if (GET_CODE (x) == SET)
1279     {
1280       rtx set = expand_field_assignment (x);
1281       rtx dest = SET_DEST (set);
1282       rtx src = SET_SRC (set);
1283       rtx inner_dest = dest;
1284
1285 #if 0
1286       rtx inner_src = src;
1287 #endif
1288
1289       SUBST (*loc, set);
1290
1291       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1292              || GET_CODE (inner_dest) == SUBREG
1293              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1294         inner_dest = XEXP (inner_dest, 0);
1295
1296   /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1297      was added.  */
1298 #if 0
1299       while (GET_CODE (inner_src) == STRICT_LOW_PART
1300              || GET_CODE (inner_src) == SUBREG
1301              || GET_CODE (inner_src) == ZERO_EXTRACT)
1302         inner_src = XEXP (inner_src, 0);
1303
1304       /* If it is better that two different modes keep two different pseudos,
1305          avoid combining them.  This avoids producing the following pattern
1306          on a 386:
1307           (set (subreg:SI (reg/v:QI 21) 0)
1308                (lshiftrt:SI (reg/v:SI 20)
1309                    (const_int 24)))
1310          If that were made, reload could not handle the pair of
1311          reg 20/21, since it would try to get any GENERAL_REGS
1312          but some of them don't handle QImode.  */
1313
1314       if (rtx_equal_p (inner_src, i2dest)
1315           && GET_CODE (inner_dest) == REG
1316           && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1317         return 0;
1318 #endif
1319
1320       /* Check for the case where I3 modifies its output, as
1321          discussed above.  */
1322       if ((inner_dest != dest
1323            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1324                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1325
1326           /* This is the same test done in can_combine_p except that we
1327              allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1328              CALL operation. Moreover, we can't test all_adjacent; we don't
1329              have to, since this instruction will stay in place, thus we are
1330              not considering increasing the lifetime of INNER_DEST.
1331
1332              Also, if this insn sets a function argument, combining it with
1333              something that might need a spill could clobber a previous
1334              function argument; the all_adjacent test in can_combine_p also
1335              checks this; here, we do a more specific test for this case.  */
1336
1337           || (GET_CODE (inner_dest) == REG
1338               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1339               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1340                                         GET_MODE (inner_dest))
1341                  || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1342                      && ! REG_USERVAR_P (inner_dest)
1343                      && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1344                          || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1345                              && i3 != 0
1346                              && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1347           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1348         return 0;
1349
1350       /* If DEST is used in I3, it is being killed in this insn,
1351          so record that for later.
1352          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1353          STACK_POINTER_REGNUM, since these are always considered to be
1354          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1355       if (pi3dest_killed && GET_CODE (dest) == REG
1356           && reg_referenced_p (dest, PATTERN (i3))
1357           && REGNO (dest) != FRAME_POINTER_REGNUM
1358 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1359           && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1360 #endif
1361 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1362           && (REGNO (dest) != ARG_POINTER_REGNUM
1363               || ! fixed_regs [REGNO (dest)])
1364 #endif
1365           && REGNO (dest) != STACK_POINTER_REGNUM)
1366         {
1367           if (*pi3dest_killed)
1368             return 0;
1369
1370           *pi3dest_killed = dest;
1371         }
1372     }
1373
1374   else if (GET_CODE (x) == PARALLEL)
1375     {
1376       int i;
1377
1378       for (i = 0; i < XVECLEN (x, 0); i++)
1379         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1380                                 i1_not_in_src, pi3dest_killed))
1381           return 0;
1382     }
1383
1384   return 1;
1385 }
1386 \f
1387 /* Return 1 if X is an arithmetic expression that contains a multiplication
1388    and division.  We don't count multiplications by powers of two here.  */
1389
1390 static int
1391 contains_muldiv (x)
1392      rtx x;
1393 {
1394   switch (GET_CODE (x))
1395     {
1396     case MOD:  case DIV:  case UMOD:  case UDIV:
1397       return 1;
1398
1399     case MULT:
1400       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1401                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1402     default:
1403       switch (GET_RTX_CLASS (GET_CODE (x)))
1404         {
1405         case 'c':  case '<':  case '2':
1406           return contains_muldiv (XEXP (x, 0))
1407             || contains_muldiv (XEXP (x, 1));
1408
1409         case '1':
1410           return contains_muldiv (XEXP (x, 0));
1411
1412         default:
1413           return 0;
1414         }
1415     }
1416 }
1417 \f
1418 /* Try to combine the insns I1 and I2 into I3.
1419    Here I1 and I2 appear earlier than I3.
1420    I1 can be zero; then we combine just I2 into I3.
1421
1422    It we are combining three insns and the resulting insn is not recognized,
1423    try splitting it into two insns.  If that happens, I2 and I3 are retained
1424    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1425    are pseudo-deleted.
1426
1427    Return 0 if the combination does not work.  Then nothing is changed.
1428    If we did the combination, return the insn at which combine should
1429    resume scanning.  */
1430
1431 static rtx
1432 try_combine (i3, i2, i1)
1433      register rtx i3, i2, i1;
1434 {
1435   /* New patterns for I3 and I3, respectively.  */
1436   rtx newpat, newi2pat = 0;
1437   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1438   int added_sets_1, added_sets_2;
1439   /* Total number of SETs to put into I3.  */
1440   int total_sets;
1441   /* Nonzero is I2's body now appears in I3.  */
1442   int i2_is_used;
1443   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1444   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1445   /* Contains I3 if the destination of I3 is used in its source, which means
1446      that the old life of I3 is being killed.  If that usage is placed into
1447      I2 and not in I3, a REG_DEAD note must be made.  */
1448   rtx i3dest_killed = 0;
1449   /* SET_DEST and SET_SRC of I2 and I1.  */
1450   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1451   /* PATTERN (I2), or a copy of it in certain cases.  */
1452   rtx i2pat;
1453   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1454   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1455   int i1_feeds_i3 = 0;
1456   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1457   rtx new_i3_notes, new_i2_notes;
1458   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1459   int i3_subst_into_i2 = 0;
1460   /* Notes that I1, I2 or I3 is a MULT operation.  */
1461   int have_mult = 0;
1462
1463   int maxreg;
1464   rtx temp;
1465   register rtx link;
1466   int i;
1467
1468   /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1469      This can occur when flow deletes an insn that it has merged into an
1470      auto-increment address.  We also can't do anything if I3 has a
1471      REG_LIBCALL note since we don't want to disrupt the contiguity of a
1472      libcall.  */
1473
1474   if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1475       || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1476       || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1477 #if 0
1478       /* ??? This gives worse code, and appears to be unnecessary, since no
1479          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1480       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1481 #endif
1482 )
1483     return 0;
1484
1485   combine_attempts++;
1486   undobuf.other_insn = 0;
1487
1488   /* Save the current high-water-mark so we can free storage if we didn't
1489      accept this combination.  */
1490   undobuf.storage = (char *) oballoc (0);
1491
1492   /* Reset the hard register usage information.  */
1493   CLEAR_HARD_REG_SET (newpat_used_regs);
1494
1495   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1496      code below, set I1 to be the earlier of the two insns.  */
1497   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1498     temp = i1, i1 = i2, i2 = temp;
1499
1500   added_links_insn = 0;
1501
1502   /* First check for one important special-case that the code below will
1503      not handle.  Namely, the case where I1 is zero, I2 has multiple sets,
1504      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1505      we may be able to replace that destination with the destination of I3.
1506      This occurs in the common code where we compute both a quotient and
1507      remainder into a structure, in which case we want to do the computation
1508      directly into the structure to avoid register-register copies.
1509
1510      We make very conservative checks below and only try to handle the
1511      most common cases of this.  For example, we only handle the case
1512      where I2 and I3 are adjacent to avoid making difficult register
1513      usage tests.  */
1514
1515   if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1516       && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1517       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1518       && (! SMALL_REGISTER_CLASSES
1519           || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1520               || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1521               || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1522       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1523       && GET_CODE (PATTERN (i2)) == PARALLEL
1524       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1525       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1526          below would need to check what is inside (and reg_overlap_mentioned_p
1527          doesn't support those codes anyway).  Don't allow those destinations;
1528          the resulting insn isn't likely to be recognized anyway.  */
1529       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1530       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1531       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1532                                     SET_DEST (PATTERN (i3)))
1533       && next_real_insn (i2) == i3)
1534     {
1535       rtx p2 = PATTERN (i2);
1536
1537       /* Make sure that the destination of I3,
1538          which we are going to substitute into one output of I2,
1539          is not used within another output of I2.  We must avoid making this:
1540          (parallel [(set (mem (reg 69)) ...)
1541                     (set (reg 69) ...)])
1542          which is not well-defined as to order of actions.
1543          (Besides, reload can't handle output reloads for this.)
1544
1545          The problem can also happen if the dest of I3 is a memory ref,
1546          if another dest in I2 is an indirect memory ref.  */
1547       for (i = 0; i < XVECLEN (p2, 0); i++)
1548         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1549              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1550             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1551                                         SET_DEST (XVECEXP (p2, 0, i))))
1552           break;
1553
1554       if (i == XVECLEN (p2, 0))
1555         for (i = 0; i < XVECLEN (p2, 0); i++)
1556           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1557                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1558               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1559             {
1560               combine_merges++;
1561
1562               subst_insn = i3;
1563               subst_low_cuid = INSN_CUID (i2);
1564
1565               added_sets_2 = added_sets_1 = 0;
1566               i2dest = SET_SRC (PATTERN (i3));
1567
1568               /* Replace the dest in I2 with our dest and make the resulting
1569                  insn the new pattern for I3.  Then skip to where we
1570                  validate the pattern.  Everything was set up above.  */
1571               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1572                      SET_DEST (PATTERN (i3)));
1573
1574               newpat = p2;
1575               i3_subst_into_i2 = 1;
1576               goto validate_replacement;
1577             }
1578     }
1579
1580   /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1581      one of those words to another constant, merge them by making a new
1582      constant.  */
1583   if (i1 == 0
1584       && (temp = single_set (i2)) != 0
1585       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1586           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1587       && GET_CODE (SET_DEST (temp)) == REG
1588       && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1589       && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1590       && GET_CODE (PATTERN (i3)) == SET
1591       && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1592       && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1593       && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1594       && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1595       && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1596     {
1597       HOST_WIDE_INT lo, hi;
1598
1599       if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1600         lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1601       else
1602         {
1603           lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1604           hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1605         }
1606
1607       if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1608         lo = INTVAL (SET_SRC (PATTERN (i3)));
1609       else
1610         hi = INTVAL (SET_SRC (PATTERN (i3)));
1611
1612       combine_merges++;
1613       subst_insn = i3;
1614       subst_low_cuid = INSN_CUID (i2);
1615       added_sets_2 = added_sets_1 = 0;
1616       i2dest = SET_DEST (temp);
1617
1618       SUBST (SET_SRC (temp),
1619              immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1620
1621       newpat = PATTERN (i2);
1622       i3_subst_into_i2 = 1;
1623       goto validate_replacement;
1624     }
1625
1626 #ifndef HAVE_cc0
1627   /* If we have no I1 and I2 looks like:
1628         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1629                    (set Y OP)])
1630      make up a dummy I1 that is
1631         (set Y OP)
1632      and change I2 to be
1633         (set (reg:CC X) (compare:CC Y (const_int 0)))
1634
1635      (We can ignore any trailing CLOBBERs.)
1636
1637      This undoes a previous combination and allows us to match a branch-and-
1638      decrement insn.  */
1639
1640   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1641       && XVECLEN (PATTERN (i2), 0) >= 2
1642       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1643       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1644           == MODE_CC)
1645       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1646       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1647       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1648       && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1649       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1650                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1651     {
1652       for (i =  XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1653         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1654           break;
1655
1656       if (i == 1)
1657         {
1658           /* We make I1 with the same INSN_UID as I2.  This gives it
1659              the same INSN_CUID for value tracking.  Our fake I1 will
1660              never appear in the insn stream so giving it the same INSN_UID
1661              as I2 will not cause a problem.  */
1662
1663           subst_prev_insn = i1
1664             = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1665                             XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1666                             NULL_RTX);
1667
1668           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1669           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1670                  SET_DEST (PATTERN (i1)));
1671         }
1672     }
1673 #endif
1674
1675   /* Verify that I2 and I1 are valid for combining.  */
1676   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1677       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1678     {
1679       undo_all ();
1680       return 0;
1681     }
1682
1683   /* Record whether I2DEST is used in I2SRC and similarly for the other
1684      cases.  Knowing this will help in register status updating below.  */
1685   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1686   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1687   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1688
1689   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
1690      in I2SRC.  */
1691   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1692
1693   /* Ensure that I3's pattern can be the destination of combines.  */
1694   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1695                           i1 && i2dest_in_i1src && i1_feeds_i3,
1696                           &i3dest_killed))
1697     {
1698       undo_all ();
1699       return 0;
1700     }
1701
1702   /* See if any of the insns is a MULT operation.  Unless one is, we will
1703      reject a combination that is, since it must be slower.  Be conservative
1704      here.  */
1705   if (GET_CODE (i2src) == MULT
1706       || (i1 != 0 && GET_CODE (i1src) == MULT)
1707       || (GET_CODE (PATTERN (i3)) == SET
1708           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1709     have_mult = 1;
1710
1711   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1712      We used to do this EXCEPT in one case: I3 has a post-inc in an
1713      output operand.  However, that exception can give rise to insns like
1714         mov r3,(r3)+
1715      which is a famous insn on the PDP-11 where the value of r3 used as the
1716      source was model-dependent.  Avoid this sort of thing.  */
1717
1718 #if 0
1719   if (!(GET_CODE (PATTERN (i3)) == SET
1720         && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1721         && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1722         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1723             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1724     /* It's not the exception.  */
1725 #endif
1726 #ifdef AUTO_INC_DEC
1727     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1728       if (REG_NOTE_KIND (link) == REG_INC
1729           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1730               || (i1 != 0
1731                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1732         {
1733           undo_all ();
1734           return 0;
1735         }
1736 #endif
1737
1738   /* See if the SETs in I1 or I2 need to be kept around in the merged
1739      instruction: whenever the value set there is still needed past I3.
1740      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1741
1742      For the SET in I1, we have two cases:  If I1 and I2 independently
1743      feed into I3, the set in I1 needs to be kept around if I1DEST dies
1744      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
1745      in I1 needs to be kept around unless I1DEST dies or is set in either
1746      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
1747      I1DEST.  If so, we know I1 feeds into I2.  */
1748
1749   added_sets_2 = ! dead_or_set_p (i3, i2dest);
1750
1751   added_sets_1
1752     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1753                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1754
1755   /* If the set in I2 needs to be kept around, we must make a copy of
1756      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1757      PATTERN (I2), we are only substituting for the original I1DEST, not into
1758      an already-substituted copy.  This also prevents making self-referential
1759      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1760      I2DEST.  */
1761
1762   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1763            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1764            : PATTERN (i2));
1765
1766   if (added_sets_2)
1767     i2pat = copy_rtx (i2pat);
1768
1769   combine_merges++;
1770
1771   /* Substitute in the latest insn for the regs set by the earlier ones.  */
1772
1773   maxreg = max_reg_num ();
1774
1775   subst_insn = i3;
1776
1777   /* It is possible that the source of I2 or I1 may be performing an
1778      unneeded operation, such as a ZERO_EXTEND of something that is known
1779      to have the high part zero.  Handle that case by letting subst look at
1780      the innermost one of them.
1781
1782      Another way to do this would be to have a function that tries to
1783      simplify a single insn instead of merging two or more insns.  We don't
1784      do this because of the potential of infinite loops and because
1785      of the potential extra memory required.  However, doing it the way
1786      we are is a bit of a kludge and doesn't catch all cases.
1787
1788      But only do this if -fexpensive-optimizations since it slows things down
1789      and doesn't usually win.  */
1790
1791   if (flag_expensive_optimizations)
1792     {
1793       /* Pass pc_rtx so no substitutions are done, just simplifications.
1794          The cases that we are interested in here do not involve the few
1795          cases were is_replaced is checked.  */
1796       if (i1)
1797         {
1798           subst_low_cuid = INSN_CUID (i1);
1799           i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1800         }
1801       else
1802         {
1803           subst_low_cuid = INSN_CUID (i2);
1804           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1805         }
1806
1807       undobuf.previous_undos = undobuf.undos;
1808     }
1809
1810 #ifndef HAVE_cc0
1811   /* Many machines that don't use CC0 have insns that can both perform an
1812      arithmetic operation and set the condition code.  These operations will
1813      be represented as a PARALLEL with the first element of the vector
1814      being a COMPARE of an arithmetic operation with the constant zero.
1815      The second element of the vector will set some pseudo to the result
1816      of the same arithmetic operation.  If we simplify the COMPARE, we won't
1817      match such a pattern and so will generate an extra insn.   Here we test
1818      for this case, where both the comparison and the operation result are
1819      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1820      I2SRC.  Later we will make the PARALLEL that contains I2.  */
1821
1822   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1823       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1824       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1825       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1826     {
1827 #ifdef EXTRA_CC_MODES
1828       rtx *cc_use;
1829       enum machine_mode compare_mode;
1830 #endif
1831
1832       newpat = PATTERN (i3);
1833       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1834
1835       i2_is_used = 1;
1836
1837 #ifdef EXTRA_CC_MODES
1838       /* See if a COMPARE with the operand we substituted in should be done
1839          with the mode that is currently being used.  If not, do the same
1840          processing we do in `subst' for a SET; namely, if the destination
1841          is used only once, try to replace it with a register of the proper
1842          mode and also replace the COMPARE.  */
1843       if (undobuf.other_insn == 0
1844           && (cc_use = find_single_use (SET_DEST (newpat), i3,
1845                                         &undobuf.other_insn))
1846           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1847                                               i2src, const0_rtx))
1848               != GET_MODE (SET_DEST (newpat))))
1849         {
1850           int regno = REGNO (SET_DEST (newpat));
1851           rtx new_dest = gen_rtx_REG (compare_mode, regno);
1852
1853           if (regno < FIRST_PSEUDO_REGISTER
1854               || (REG_N_SETS (regno) == 1 && ! added_sets_2
1855                   && ! REG_USERVAR_P (SET_DEST (newpat))))
1856             {
1857               if (regno >= FIRST_PSEUDO_REGISTER)
1858                 SUBST (regno_reg_rtx[regno], new_dest);
1859
1860               SUBST (SET_DEST (newpat), new_dest);
1861               SUBST (XEXP (*cc_use, 0), new_dest);
1862               SUBST (SET_SRC (newpat),
1863                      gen_rtx_combine (COMPARE, compare_mode,
1864                                       i2src, const0_rtx));
1865             }
1866           else
1867             undobuf.other_insn = 0;
1868         }
1869 #endif
1870     }
1871   else
1872 #endif
1873     {
1874       n_occurrences = 0;                /* `subst' counts here */
1875
1876       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1877          need to make a unique copy of I2SRC each time we substitute it
1878          to avoid self-referential rtl.  */
1879
1880       subst_low_cuid = INSN_CUID (i2);
1881       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1882                       ! i1_feeds_i3 && i1dest_in_i1src);
1883       undobuf.previous_undos = undobuf.undos;
1884
1885       /* Record whether i2's body now appears within i3's body.  */
1886       i2_is_used = n_occurrences;
1887     }
1888
1889   /* If we already got a failure, don't try to do more.  Otherwise,
1890      try to substitute in I1 if we have it.  */
1891
1892   if (i1 && GET_CODE (newpat) != CLOBBER)
1893     {
1894       /* Before we can do this substitution, we must redo the test done
1895          above (see detailed comments there) that ensures  that I1DEST
1896          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
1897
1898       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1899                               0, NULL_PTR))
1900         {
1901           undo_all ();
1902           return 0;
1903         }
1904
1905       n_occurrences = 0;
1906       subst_low_cuid = INSN_CUID (i1);
1907       newpat = subst (newpat, i1dest, i1src, 0, 0);
1908       undobuf.previous_undos = undobuf.undos;
1909     }
1910
1911   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
1912      to count all the ways that I2SRC and I1SRC can be used.  */
1913   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1914        && i2_is_used + added_sets_2 > 1)
1915       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1916           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1917               > 1))
1918       /* Fail if we tried to make a new register (we used to abort, but there's
1919          really no reason to).  */
1920       || max_reg_num () != maxreg
1921       /* Fail if we couldn't do something and have a CLOBBER.  */
1922       || GET_CODE (newpat) == CLOBBER
1923       /* Fail if this new pattern is a MULT and we didn't have one before
1924          at the outer level.  */
1925       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1926           && ! have_mult))
1927     {
1928       undo_all ();
1929       return 0;
1930     }
1931
1932   /* If the actions of the earlier insns must be kept
1933      in addition to substituting them into the latest one,
1934      we must make a new PARALLEL for the latest insn
1935      to hold additional the SETs.  */
1936
1937   if (added_sets_1 || added_sets_2)
1938     {
1939       combine_extras++;
1940
1941       if (GET_CODE (newpat) == PARALLEL)
1942         {
1943           rtvec old = XVEC (newpat, 0);
1944           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1945           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1946           bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1947                  sizeof (old->elem[0]) * old->num_elem);
1948         }
1949       else
1950         {
1951           rtx old = newpat;
1952           total_sets = 1 + added_sets_1 + added_sets_2;
1953           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1954           XVECEXP (newpat, 0, 0) = old;
1955         }
1956
1957      if (added_sets_1)
1958        XVECEXP (newpat, 0, --total_sets)
1959          = (GET_CODE (PATTERN (i1)) == PARALLEL
1960             ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1961
1962      if (added_sets_2)
1963        {
1964          /* If there is no I1, use I2's body as is.  We used to also not do
1965             the subst call below if I2 was substituted into I3,
1966             but that could lose a simplification.  */
1967          if (i1 == 0)
1968            XVECEXP (newpat, 0, --total_sets) = i2pat;
1969          else
1970            /* See comment where i2pat is assigned.  */
1971            XVECEXP (newpat, 0, --total_sets)
1972              = subst (i2pat, i1dest, i1src, 0, 0);
1973        }
1974     }
1975
1976   /* We come here when we are replacing a destination in I2 with the
1977      destination of I3.  */
1978  validate_replacement:
1979
1980   /* Note which hard regs this insn has as inputs.  */
1981   mark_used_regs_combine (newpat);
1982
1983   /* Is the result of combination a valid instruction?  */
1984   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1985
1986   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1987      the second SET's destination is a register that is unused.  In that case,
1988      we just need the first SET.   This can occur when simplifying a divmod
1989      insn.  We *must* test for this case here because the code below that
1990      splits two independent SETs doesn't handle this case correctly when it
1991      updates the register status.  Also check the case where the first
1992      SET's destination is unused.  That would not cause incorrect code, but
1993      does cause an unneeded insn to remain.  */
1994
1995   if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1996       && XVECLEN (newpat, 0) == 2
1997       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1998       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1999       && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2000       && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2001       && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2002       && asm_noperands (newpat) < 0)
2003     {
2004       newpat = XVECEXP (newpat, 0, 0);
2005       insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2006     }
2007
2008   else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2009            && XVECLEN (newpat, 0) == 2
2010            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2011            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2012            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2013            && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2014            && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2015            && asm_noperands (newpat) < 0)
2016     {
2017       newpat = XVECEXP (newpat, 0, 1);
2018       insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2019     }
2020
2021   /* If we were combining three insns and the result is a simple SET
2022      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2023      insns.  There are two ways to do this.  It can be split using a
2024      machine-specific method (like when you have an addition of a large
2025      constant) or by combine in the function find_split_point.  */
2026
2027   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2028       && asm_noperands (newpat) < 0)
2029     {
2030       rtx m_split, *split;
2031       rtx ni2dest = i2dest;
2032
2033       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2034          use I2DEST as a scratch register will help.  In the latter case,
2035          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2036
2037       m_split = split_insns (newpat, i3);
2038
2039       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2040          inputs of NEWPAT.  */
2041
2042       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2043          possible to try that as a scratch reg.  This would require adding
2044          more code to make it work though.  */
2045
2046       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2047         {
2048           /* If I2DEST is a hard register or the only use of a pseudo,
2049              we can change its mode.  */
2050           if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2051               && GET_MODE (SET_DEST (newpat)) != VOIDmode
2052               && GET_CODE (i2dest) == REG
2053               && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2054                   || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2055                       && ! REG_USERVAR_P (i2dest))))
2056             ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2057                                    REGNO (i2dest));
2058
2059           m_split = split_insns (gen_rtx_PARALLEL
2060                                  (VOIDmode,
2061                                   gen_rtvec (2, newpat,
2062                                              gen_rtx_CLOBBER (VOIDmode,
2063                                                               ni2dest))),
2064                                  i3);
2065         }
2066
2067       if (m_split && GET_CODE (m_split) == SEQUENCE
2068           && XVECLEN (m_split, 0) == 2
2069           && (next_real_insn (i2) == i3
2070               || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2071                                       INSN_CUID (i2))))
2072         {
2073           rtx i2set, i3set;
2074           rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2075           newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2076
2077           i3set = single_set (XVECEXP (m_split, 0, 1));
2078           i2set = single_set (XVECEXP (m_split, 0, 0));
2079
2080           /* In case we changed the mode of I2DEST, replace it in the
2081              pseudo-register table here.  We can't do it above in case this
2082              code doesn't get executed and we do a split the other way.  */
2083
2084           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2085             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2086
2087           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2088
2089           /* If I2 or I3 has multiple SETs, we won't know how to track
2090              register status, so don't use these insns.  If I2's destination
2091              is used between I2 and I3, we also can't use these insns.  */
2092
2093           if (i2_code_number >= 0 && i2set && i3set
2094               && (next_real_insn (i2) == i3
2095                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2096             insn_code_number = recog_for_combine (&newi3pat, i3,
2097                                                   &new_i3_notes);
2098           if (insn_code_number >= 0)
2099             newpat = newi3pat;
2100
2101           /* It is possible that both insns now set the destination of I3.
2102              If so, we must show an extra use of it.  */
2103
2104           if (insn_code_number >= 0)
2105             {
2106               rtx new_i3_dest = SET_DEST (i3set);
2107               rtx new_i2_dest = SET_DEST (i2set);
2108
2109               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2110                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2111                      || GET_CODE (new_i3_dest) == SUBREG)
2112                 new_i3_dest = XEXP (new_i3_dest, 0);
2113
2114               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2115                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2116                      || GET_CODE (new_i2_dest) == SUBREG)
2117                 new_i2_dest = XEXP (new_i2_dest, 0);
2118
2119               if (GET_CODE (new_i3_dest) == REG
2120                   && GET_CODE (new_i2_dest) == REG
2121                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2122                 REG_N_SETS (REGNO (new_i2_dest))++;
2123             }
2124         }
2125
2126       /* If we can split it and use I2DEST, go ahead and see if that
2127          helps things be recognized.  Verify that none of the registers
2128          are set between I2 and I3.  */
2129       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2130 #ifdef HAVE_cc0
2131           && GET_CODE (i2dest) == REG
2132 #endif
2133           /* We need I2DEST in the proper mode.  If it is a hard register
2134              or the only use of a pseudo, we can change its mode.  */
2135           && (GET_MODE (*split) == GET_MODE (i2dest)
2136               || GET_MODE (*split) == VOIDmode
2137               || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2138               || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2139                   && ! REG_USERVAR_P (i2dest)))
2140           && (next_real_insn (i2) == i3
2141               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2142           /* We can't overwrite I2DEST if its value is still used by
2143              NEWPAT.  */
2144           && ! reg_referenced_p (i2dest, newpat))
2145         {
2146           rtx newdest = i2dest;
2147           enum rtx_code split_code = GET_CODE (*split);
2148           enum machine_mode split_mode = GET_MODE (*split);
2149
2150           /* Get NEWDEST as a register in the proper mode.  We have already
2151              validated that we can do this.  */
2152           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2153             {
2154               newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2155
2156               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2157                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2158             }
2159
2160           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2161              an ASHIFT.  This can occur if it was inside a PLUS and hence
2162              appeared to be a memory address.  This is a kludge.  */
2163           if (split_code == MULT
2164               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2165               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2166             {
2167               SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2168                                               XEXP (*split, 0), GEN_INT (i)));
2169               /* Update split_code because we may not have a multiply
2170                  anymore.  */
2171               split_code = GET_CODE (*split);
2172             }
2173
2174 #ifdef INSN_SCHEDULING
2175           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2176              be written as a ZERO_EXTEND.  */
2177           if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2178             SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2179                                             XEXP (*split, 0)));
2180 #endif
2181
2182           newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2183           SUBST (*split, newdest);
2184           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2185
2186           /* If the split point was a MULT and we didn't have one before,
2187              don't use one now.  */
2188           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2189             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2190         }
2191     }
2192
2193   /* Check for a case where we loaded from memory in a narrow mode and
2194      then sign extended it, but we need both registers.  In that case,
2195      we have a PARALLEL with both loads from the same memory location.
2196      We can split this into a load from memory followed by a register-register
2197      copy.  This saves at least one insn, more if register allocation can
2198      eliminate the copy.
2199
2200      We cannot do this if the destination of the second assignment is
2201      a register that we have already assumed is zero-extended.  Similarly
2202      for a SUBREG of such a register.  */
2203
2204   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2205            && GET_CODE (newpat) == PARALLEL
2206            && XVECLEN (newpat, 0) == 2
2207            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2208            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2209            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2210            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2211                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2212            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2213                                    INSN_CUID (i2))
2214            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2215            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2216            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2217                  (GET_CODE (temp) == REG
2218                   && reg_nonzero_bits[REGNO (temp)] != 0
2219                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2220                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2221                   && (reg_nonzero_bits[REGNO (temp)]
2222                       != GET_MODE_MASK (word_mode))))
2223            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2224                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2225                      (GET_CODE (temp) == REG
2226                       && reg_nonzero_bits[REGNO (temp)] != 0
2227                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2228                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2229                       && (reg_nonzero_bits[REGNO (temp)]
2230                           != GET_MODE_MASK (word_mode)))))
2231            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2232                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2233            && ! find_reg_note (i3, REG_UNUSED,
2234                                SET_DEST (XVECEXP (newpat, 0, 0))))
2235     {
2236       rtx ni2dest;
2237
2238       newi2pat = XVECEXP (newpat, 0, 0);
2239       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2240       newpat = XVECEXP (newpat, 0, 1);
2241       SUBST (SET_SRC (newpat),
2242              gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2243       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2244
2245       if (i2_code_number >= 0)
2246         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2247
2248       if (insn_code_number >= 0)
2249         {
2250           rtx insn;
2251           rtx link;
2252
2253           /* If we will be able to accept this, we have made a change to the
2254              destination of I3.  This can invalidate a LOG_LINKS pointing
2255              to I3.  No other part of combine.c makes such a transformation.
2256
2257              The new I3 will have a destination that was previously the
2258              destination of I1 or I2 and which was used in i2 or I3.  Call
2259              distribute_links to make a LOG_LINK from the next use of
2260              that destination.  */
2261
2262           PATTERN (i3) = newpat;
2263           distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2264
2265           /* I3 now uses what used to be its destination and which is
2266              now I2's destination.  That means we need a LOG_LINK from
2267              I3 to I2.  But we used to have one, so we still will.
2268
2269              However, some later insn might be using I2's dest and have
2270              a LOG_LINK pointing at I3.  We must remove this link.
2271              The simplest way to remove the link is to point it at I1,
2272              which we know will be a NOTE.  */
2273
2274           for (insn = NEXT_INSN (i3);
2275                insn && (this_basic_block == n_basic_blocks - 1
2276                         || insn != BLOCK_HEAD (this_basic_block + 1));
2277                insn = NEXT_INSN (insn))
2278             {
2279               if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2280                   && reg_referenced_p (ni2dest, PATTERN (insn)))
2281                 {
2282                   for (link = LOG_LINKS (insn); link;
2283                        link = XEXP (link, 1))
2284                     if (XEXP (link, 0) == i3)
2285                       XEXP (link, 0) = i1;
2286
2287                   break;
2288                 }
2289             }
2290         }
2291     }
2292
2293   /* Similarly, check for a case where we have a PARALLEL of two independent
2294      SETs but we started with three insns.  In this case, we can do the sets
2295      as two separate insns.  This case occurs when some SET allows two
2296      other insns to combine, but the destination of that SET is still live.  */
2297
2298   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2299            && GET_CODE (newpat) == PARALLEL
2300            && XVECLEN (newpat, 0) == 2
2301            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2302            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2303            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2304            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2305            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2306            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2307            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2308                                    INSN_CUID (i2))
2309            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2310            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2311            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2312            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2313                                   XVECEXP (newpat, 0, 0))
2314            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2315                                   XVECEXP (newpat, 0, 1))
2316            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2317                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2318     {
2319       /* Normally, it doesn't matter which of the two is done first,
2320          but it does if one references cc0.  In that case, it has to
2321          be first.  */
2322 #ifdef HAVE_cc0
2323       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2324         {
2325           newi2pat = XVECEXP (newpat, 0, 0);
2326           newpat = XVECEXP (newpat, 0, 1);
2327         }
2328       else
2329 #endif
2330         {
2331           newi2pat = XVECEXP (newpat, 0, 1);
2332           newpat = XVECEXP (newpat, 0, 0);
2333         }
2334
2335       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2336
2337       if (i2_code_number >= 0)
2338         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2339     }
2340
2341   /* If it still isn't recognized, fail and change things back the way they
2342      were.  */
2343   if ((insn_code_number < 0
2344        /* Is the result a reasonable ASM_OPERANDS?  */
2345        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2346     {
2347       undo_all ();
2348       return 0;
2349     }
2350
2351   /* If we had to change another insn, make sure it is valid also.  */
2352   if (undobuf.other_insn)
2353     {
2354       rtx other_pat = PATTERN (undobuf.other_insn);
2355       rtx new_other_notes;
2356       rtx note, next;
2357
2358       CLEAR_HARD_REG_SET (newpat_used_regs);
2359
2360       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2361                                              &new_other_notes);
2362
2363       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2364         {
2365           undo_all ();
2366           return 0;
2367         }
2368
2369       PATTERN (undobuf.other_insn) = other_pat;
2370
2371       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2372          are still valid.  Then add any non-duplicate notes added by
2373          recog_for_combine.  */
2374       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2375         {
2376           next = XEXP (note, 1);
2377
2378           if (REG_NOTE_KIND (note) == REG_UNUSED
2379               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2380             {
2381               if (GET_CODE (XEXP (note, 0)) == REG)
2382                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2383
2384               remove_note (undobuf.other_insn, note);
2385             }
2386         }
2387
2388       for (note = new_other_notes; note; note = XEXP (note, 1))
2389         if (GET_CODE (XEXP (note, 0)) == REG)
2390           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2391
2392       distribute_notes (new_other_notes, undobuf.other_insn,
2393                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2394     }
2395 #ifdef HAVE_cc0
2396   /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2397      they are adjacent to each other or not. */
2398   {
2399     rtx p = prev_nonnote_insn (i3);
2400     if (p && p != i2 && GET_CODE (p) == INSN && newi2pat && sets_cc0_p (newi2pat))
2401       {
2402         undo_all ();
2403         return 0;
2404       }
2405     }
2406 #endif
2407
2408   /* We now know that we can do this combination.  Merge the insns and
2409      update the status of registers and LOG_LINKS.  */
2410
2411   {
2412     rtx i3notes, i2notes, i1notes = 0;
2413     rtx i3links, i2links, i1links = 0;
2414     rtx midnotes = 0;
2415     register int regno;
2416     /* Compute which registers we expect to eliminate.  newi2pat may be setting
2417        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
2418        same as i3dest, in which case newi2pat may be setting i1dest.  */
2419     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2420                    || i2dest_in_i2src || i2dest_in_i1src
2421                    ? 0 : i2dest);
2422     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2423                    || (newi2pat && reg_set_p (i1dest, newi2pat))
2424                    ? 0 : i1dest);
2425
2426     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2427        clear them.  */
2428     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2429     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2430     if (i1)
2431       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2432
2433     /* Ensure that we do not have something that should not be shared but
2434        occurs multiple times in the new insns.  Check this by first
2435        resetting all the `used' flags and then copying anything is shared.  */
2436
2437     reset_used_flags (i3notes);
2438     reset_used_flags (i2notes);
2439     reset_used_flags (i1notes);
2440     reset_used_flags (newpat);
2441     reset_used_flags (newi2pat);
2442     if (undobuf.other_insn)
2443       reset_used_flags (PATTERN (undobuf.other_insn));
2444
2445     i3notes = copy_rtx_if_shared (i3notes);
2446     i2notes = copy_rtx_if_shared (i2notes);
2447     i1notes = copy_rtx_if_shared (i1notes);
2448     newpat = copy_rtx_if_shared (newpat);
2449     newi2pat = copy_rtx_if_shared (newi2pat);
2450     if (undobuf.other_insn)
2451       reset_used_flags (PATTERN (undobuf.other_insn));
2452
2453     INSN_CODE (i3) = insn_code_number;
2454     PATTERN (i3) = newpat;
2455     if (undobuf.other_insn)
2456       INSN_CODE (undobuf.other_insn) = other_code_number;
2457
2458     /* We had one special case above where I2 had more than one set and
2459        we replaced a destination of one of those sets with the destination
2460        of I3.  In that case, we have to update LOG_LINKS of insns later
2461        in this basic block.  Note that this (expensive) case is rare.
2462
2463        Also, in this case, we must pretend that all REG_NOTEs for I2
2464        actually came from I3, so that REG_UNUSED notes from I2 will be
2465        properly handled.  */
2466
2467     if (i3_subst_into_i2)
2468       {
2469         if (GET_CODE (PATTERN (i2)) == PARALLEL)
2470           {
2471             for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2472               if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2473                   && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2474                   && ! find_reg_note (i2, REG_UNUSED,
2475                                       SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2476                 for (temp = NEXT_INSN (i2);
2477                      temp && (this_basic_block == n_basic_blocks - 1
2478                               || BLOCK_HEAD (this_basic_block) != temp);
2479                      temp = NEXT_INSN (temp))
2480                   if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2481                     for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2482                       if (XEXP (link, 0) == i2)
2483                         XEXP (link, 0) = i3;
2484           }
2485
2486         if (i3notes)
2487           {
2488             rtx link = i3notes;
2489             while (XEXP (link, 1))
2490               link = XEXP (link, 1);
2491             XEXP (link, 1) = i2notes;
2492           }
2493         else
2494           i3notes = i2notes;
2495         i2notes = 0;
2496       }
2497
2498     LOG_LINKS (i3) = 0;
2499     REG_NOTES (i3) = 0;
2500     LOG_LINKS (i2) = 0;
2501     REG_NOTES (i2) = 0;
2502
2503     if (newi2pat)
2504       {
2505         INSN_CODE (i2) = i2_code_number;
2506         PATTERN (i2) = newi2pat;
2507       }
2508     else
2509       {
2510         PUT_CODE (i2, NOTE);
2511         NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2512         NOTE_SOURCE_FILE (i2) = 0;
2513       }
2514
2515     if (i1)
2516       {
2517         LOG_LINKS (i1) = 0;
2518         REG_NOTES (i1) = 0;
2519         PUT_CODE (i1, NOTE);
2520         NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2521         NOTE_SOURCE_FILE (i1) = 0;
2522       }
2523
2524     /* Get death notes for everything that is now used in either I3 or
2525        I2 and used to die in a previous insn.  If we built two new
2526        patterns, move from I1 to I2 then I2 to I3 so that we get the
2527        proper movement on registers that I2 modifies.  */
2528
2529     if (newi2pat)
2530       {
2531         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2532         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2533       }
2534     else
2535       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2536                    i3, &midnotes);
2537
2538     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
2539     if (i3notes)
2540       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2541                         elim_i2, elim_i1);
2542     if (i2notes)
2543       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2544                         elim_i2, elim_i1);
2545     if (i1notes)
2546       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2547                         elim_i2, elim_i1);
2548     if (midnotes)
2549       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2550                         elim_i2, elim_i1);
2551
2552     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
2553        know these are REG_UNUSED and want them to go to the desired insn,
2554        so we always pass it as i3.  We have not counted the notes in
2555        reg_n_deaths yet, so we need to do so now.  */
2556
2557     if (newi2pat && new_i2_notes)
2558       {
2559         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2560           if (GET_CODE (XEXP (temp, 0)) == REG)
2561             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2562
2563         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2564       }
2565
2566     if (new_i3_notes)
2567       {
2568         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2569           if (GET_CODE (XEXP (temp, 0)) == REG)
2570             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2571
2572         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2573       }
2574
2575     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
2576        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
2577        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
2578        in that case, it might delete I2.  Similarly for I2 and I1.
2579        Show an additional death due to the REG_DEAD note we make here.  If
2580        we discard it in distribute_notes, we will decrement it again.  */
2581
2582     if (i3dest_killed)
2583       {
2584         if (GET_CODE (i3dest_killed) == REG)
2585           REG_N_DEATHS (REGNO (i3dest_killed))++;
2586
2587         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2588           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2589                                                NULL_RTX),
2590                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2591         else
2592           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2593                                                NULL_RTX),
2594                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2595                             elim_i2, elim_i1);
2596       }
2597
2598     if (i2dest_in_i2src)
2599       {
2600         if (GET_CODE (i2dest) == REG)
2601           REG_N_DEATHS (REGNO (i2dest))++;
2602
2603         if (newi2pat && reg_set_p (i2dest, newi2pat))
2604           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2605                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2606         else
2607           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2608                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2609                             NULL_RTX, NULL_RTX);
2610       }
2611
2612     if (i1dest_in_i1src)
2613       {
2614         if (GET_CODE (i1dest) == REG)
2615           REG_N_DEATHS (REGNO (i1dest))++;
2616
2617         if (newi2pat && reg_set_p (i1dest, newi2pat))
2618           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2619                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2620         else
2621           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2622                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2623                             NULL_RTX, NULL_RTX);
2624       }
2625
2626     distribute_links (i3links);
2627     distribute_links (i2links);
2628     distribute_links (i1links);
2629
2630     if (GET_CODE (i2dest) == REG)
2631       {
2632         rtx link;
2633         rtx i2_insn = 0, i2_val = 0, set;
2634
2635         /* The insn that used to set this register doesn't exist, and
2636            this life of the register may not exist either.  See if one of
2637            I3's links points to an insn that sets I2DEST.  If it does,
2638            that is now the last known value for I2DEST. If we don't update
2639            this and I2 set the register to a value that depended on its old
2640            contents, we will get confused.  If this insn is used, thing
2641            will be set correctly in combine_instructions.  */
2642
2643         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2644           if ((set = single_set (XEXP (link, 0))) != 0
2645               && rtx_equal_p (i2dest, SET_DEST (set)))
2646             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2647
2648         record_value_for_reg (i2dest, i2_insn, i2_val);
2649
2650         /* If the reg formerly set in I2 died only once and that was in I3,
2651            zero its use count so it won't make `reload' do any work.  */
2652         if (! added_sets_2
2653             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2654             && ! i2dest_in_i2src)
2655           {
2656             regno = REGNO (i2dest);
2657             REG_N_SETS (regno)--;
2658           }
2659       }
2660
2661     if (i1 && GET_CODE (i1dest) == REG)
2662       {
2663         rtx link;
2664         rtx i1_insn = 0, i1_val = 0, set;
2665
2666         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2667           if ((set = single_set (XEXP (link, 0))) != 0
2668               && rtx_equal_p (i1dest, SET_DEST (set)))
2669             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2670
2671         record_value_for_reg (i1dest, i1_insn, i1_val);
2672
2673         regno = REGNO (i1dest);
2674         if (! added_sets_1 && ! i1dest_in_i1src)
2675           {
2676             REG_N_SETS (regno)--;
2677           }
2678       }
2679
2680     /* Update reg_nonzero_bits et al for any changes that may have been made
2681        to this insn.  */
2682
2683     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2684     if (newi2pat)
2685       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2686
2687     /* If I3 is now an unconditional jump, ensure that it has a
2688        BARRIER following it since it may have initially been a
2689        conditional jump.  It may also be the last nonnote insn.  */
2690
2691     if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2692         && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2693             || GET_CODE (temp) != BARRIER))
2694       emit_barrier_after (i3);
2695   }
2696
2697   combine_successes++;
2698   undo_commit ();
2699
2700   /* Clear this here, so that subsequent get_last_value calls are not
2701      affected.  */
2702   subst_prev_insn = NULL_RTX;
2703
2704   if (added_links_insn
2705       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2706       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2707     return added_links_insn;
2708   else
2709     return newi2pat ? i2 : i3;
2710 }
2711 \f
2712 /* Undo all the modifications recorded in undobuf.  */
2713
2714 static void
2715 undo_all ()
2716 {
2717   struct undo *undo, *next;
2718
2719   for (undo = undobuf.undos; undo; undo = next)
2720     {
2721       next = undo->next;
2722       if (undo->is_int)
2723         *undo->where.i = undo->old_contents.i;
2724       else
2725         *undo->where.r = undo->old_contents.r;
2726
2727       undo->next = undobuf.frees;
2728       undobuf.frees = undo;
2729     }
2730
2731   obfree (undobuf.storage);
2732   undobuf.undos = undobuf.previous_undos = 0;
2733
2734   /* Clear this here, so that subsequent get_last_value calls are not
2735      affected.  */
2736   subst_prev_insn = NULL_RTX;
2737 }
2738
2739 /* We've committed to accepting the changes we made.  Move all
2740    of the undos to the free list.  */
2741
2742 static void
2743 undo_commit ()
2744 {
2745   struct undo *undo, *next;
2746
2747   for (undo = undobuf.undos; undo; undo = next)
2748     {
2749       next = undo->next;
2750       undo->next = undobuf.frees;
2751       undobuf.frees = undo;
2752     }
2753   undobuf.undos = undobuf.previous_undos = 0;
2754 }
2755
2756 \f
2757 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2758    where we have an arithmetic expression and return that point.  LOC will
2759    be inside INSN.
2760
2761    try_combine will call this function to see if an insn can be split into
2762    two insns.  */
2763
2764 static rtx *
2765 find_split_point (loc, insn)
2766      rtx *loc;
2767      rtx insn;
2768 {
2769   rtx x = *loc;
2770   enum rtx_code code = GET_CODE (x);
2771   rtx *split;
2772   int len = 0, pos = 0, unsignedp = 0;
2773   rtx inner = NULL_RTX;
2774
2775   /* First special-case some codes.  */
2776   switch (code)
2777     {
2778     case SUBREG:
2779 #ifdef INSN_SCHEDULING
2780       /* If we are making a paradoxical SUBREG invalid, it becomes a split
2781          point.  */
2782       if (GET_CODE (SUBREG_REG (x)) == MEM)
2783         return loc;
2784 #endif
2785       return find_split_point (&SUBREG_REG (x), insn);
2786
2787     case MEM:
2788 #ifdef HAVE_lo_sum
2789       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2790          using LO_SUM and HIGH.  */
2791       if (GET_CODE (XEXP (x, 0)) == CONST
2792           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2793         {
2794           SUBST (XEXP (x, 0),
2795                  gen_rtx_combine (LO_SUM, Pmode,
2796                                   gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2797                                   XEXP (x, 0)));
2798           return &XEXP (XEXP (x, 0), 0);
2799         }
2800 #endif
2801
2802       /* If we have a PLUS whose second operand is a constant and the
2803          address is not valid, perhaps will can split it up using
2804          the machine-specific way to split large constants.  We use
2805          the first pseudo-reg (one of the virtual regs) as a placeholder;
2806          it will not remain in the result.  */
2807       if (GET_CODE (XEXP (x, 0)) == PLUS
2808           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2809           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2810         {
2811           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2812           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2813                                  subst_insn);
2814
2815           /* This should have produced two insns, each of which sets our
2816              placeholder.  If the source of the second is a valid address,
2817              we can make put both sources together and make a split point
2818              in the middle.  */
2819
2820           if (seq && XVECLEN (seq, 0) == 2
2821               && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2822               && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2823               && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2824               && ! reg_mentioned_p (reg,
2825                                     SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2826               && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2827               && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2828               && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2829               && memory_address_p (GET_MODE (x),
2830                                    SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2831             {
2832               rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2833               rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2834
2835               /* Replace the placeholder in SRC2 with SRC1.  If we can
2836                  find where in SRC2 it was placed, that can become our
2837                  split point and we can replace this address with SRC2.
2838                  Just try two obvious places.  */
2839
2840               src2 = replace_rtx (src2, reg, src1);
2841               split = 0;
2842               if (XEXP (src2, 0) == src1)
2843                 split = &XEXP (src2, 0);
2844               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2845                        && XEXP (XEXP (src2, 0), 0) == src1)
2846                 split = &XEXP (XEXP (src2, 0), 0);
2847
2848               if (split)
2849                 {
2850                   SUBST (XEXP (x, 0), src2);
2851                   return split;
2852                 }
2853             }
2854
2855           /* If that didn't work, perhaps the first operand is complex and
2856              needs to be computed separately, so make a split point there.
2857              This will occur on machines that just support REG + CONST
2858              and have a constant moved through some previous computation.  */
2859
2860           else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2861                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2862                          && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2863                              == 'o')))
2864             return &XEXP (XEXP (x, 0), 0);
2865         }
2866       break;
2867
2868     case SET:
2869 #ifdef HAVE_cc0
2870       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2871          ZERO_EXTRACT, the most likely reason why this doesn't match is that
2872          we need to put the operand into a register.  So split at that
2873          point.  */
2874
2875       if (SET_DEST (x) == cc0_rtx
2876           && GET_CODE (SET_SRC (x)) != COMPARE
2877           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2878           && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2879           && ! (GET_CODE (SET_SRC (x)) == SUBREG
2880                 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2881         return &SET_SRC (x);
2882 #endif
2883
2884       /* See if we can split SET_SRC as it stands.  */
2885       split = find_split_point (&SET_SRC (x), insn);
2886       if (split && split != &SET_SRC (x))
2887         return split;
2888
2889       /* See if we can split SET_DEST as it stands.  */
2890       split = find_split_point (&SET_DEST (x), insn);
2891       if (split && split != &SET_DEST (x))
2892         return split;
2893
2894       /* See if this is a bitfield assignment with everything constant.  If
2895          so, this is an IOR of an AND, so split it into that.  */
2896       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2897           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2898               <= HOST_BITS_PER_WIDE_INT)
2899           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2900           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2901           && GET_CODE (SET_SRC (x)) == CONST_INT
2902           && ((INTVAL (XEXP (SET_DEST (x), 1))
2903               + INTVAL (XEXP (SET_DEST (x), 2)))
2904               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2905           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2906         {
2907           int pos = INTVAL (XEXP (SET_DEST (x), 2));
2908           int len = INTVAL (XEXP (SET_DEST (x), 1));
2909           int src = INTVAL (SET_SRC (x));
2910           rtx dest = XEXP (SET_DEST (x), 0);
2911           enum machine_mode mode = GET_MODE (dest);
2912           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2913
2914           if (BITS_BIG_ENDIAN)
2915             pos = GET_MODE_BITSIZE (mode) - len - pos;
2916
2917           if ((unsigned HOST_WIDE_INT) src == mask)
2918             SUBST (SET_SRC (x),
2919                    gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2920           else
2921             SUBST (SET_SRC (x),
2922                    gen_binary (IOR, mode,
2923                                gen_binary (AND, mode, dest,
2924                                            GEN_INT (~ (mask << pos)
2925                                                     & GET_MODE_MASK (mode))),
2926                                GEN_INT (src << pos)));
2927
2928           SUBST (SET_DEST (x), dest);
2929
2930           split = find_split_point (&SET_SRC (x), insn);
2931           if (split && split != &SET_SRC (x))
2932             return split;
2933         }
2934
2935       /* Otherwise, see if this is an operation that we can split into two.
2936          If so, try to split that.  */
2937       code = GET_CODE (SET_SRC (x));
2938
2939       switch (code)
2940         {
2941         case AND:
2942           /* If we are AND'ing with a large constant that is only a single
2943              bit and the result is only being used in a context where we
2944              need to know if it is zero or non-zero, replace it with a bit
2945              extraction.  This will avoid the large constant, which might
2946              have taken more than one insn to make.  If the constant were
2947              not a valid argument to the AND but took only one insn to make,
2948              this is no worse, but if it took more than one insn, it will
2949              be better.  */
2950
2951           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2952               && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2953               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2954               && GET_CODE (SET_DEST (x)) == REG
2955               && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2956               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2957               && XEXP (*split, 0) == SET_DEST (x)
2958               && XEXP (*split, 1) == const0_rtx)
2959             {
2960               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2961                                                 XEXP (SET_SRC (x), 0),
2962                                                 pos, NULL_RTX, 1, 1, 0, 0);
2963               if (extraction != 0)
2964                 {
2965                   SUBST (SET_SRC (x), extraction);
2966                   return find_split_point (loc, insn);
2967                 }
2968             }
2969           break;
2970
2971         case NE:
2972           /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2973              is known to be on, this can be converted into a NEG of a shift. */
2974           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2975               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2976               && 1 <= (pos = exact_log2
2977                        (nonzero_bits (XEXP (SET_SRC (x), 0),
2978                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
2979             {
2980               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2981
2982               SUBST (SET_SRC (x),
2983                      gen_rtx_combine (NEG, mode,
2984                                       gen_rtx_combine (LSHIFTRT, mode,
2985                                                        XEXP (SET_SRC (x), 0),
2986                                                        GEN_INT (pos))));
2987
2988               split = find_split_point (&SET_SRC (x), insn);
2989               if (split && split != &SET_SRC (x))
2990                 return split;
2991             }
2992           break;
2993
2994         case SIGN_EXTEND:
2995           inner = XEXP (SET_SRC (x), 0);
2996
2997           /* We can't optimize if either mode is a partial integer
2998              mode as we don't know how many bits are significant
2999              in those modes.  */
3000           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3001               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3002             break;
3003
3004           pos = 0;
3005           len = GET_MODE_BITSIZE (GET_MODE (inner));
3006           unsignedp = 0;
3007           break;
3008
3009         case SIGN_EXTRACT:
3010         case ZERO_EXTRACT:
3011           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3012               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3013             {
3014               inner = XEXP (SET_SRC (x), 0);
3015               len = INTVAL (XEXP (SET_SRC (x), 1));
3016               pos = INTVAL (XEXP (SET_SRC (x), 2));
3017
3018               if (BITS_BIG_ENDIAN)
3019                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3020               unsignedp = (code == ZERO_EXTRACT);
3021             }
3022           break;
3023
3024         default:
3025           break;
3026         }
3027
3028       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3029         {
3030           enum machine_mode mode = GET_MODE (SET_SRC (x));
3031
3032           /* For unsigned, we have a choice of a shift followed by an
3033              AND or two shifts.  Use two shifts for field sizes where the
3034              constant might be too large.  We assume here that we can
3035              always at least get 8-bit constants in an AND insn, which is
3036              true for every current RISC.  */
3037
3038           if (unsignedp && len <= 8)
3039             {
3040               SUBST (SET_SRC (x),
3041                      gen_rtx_combine
3042                      (AND, mode,
3043                       gen_rtx_combine (LSHIFTRT, mode,
3044                                        gen_lowpart_for_combine (mode, inner),
3045                                        GEN_INT (pos)),
3046                       GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3047
3048               split = find_split_point (&SET_SRC (x), insn);
3049               if (split && split != &SET_SRC (x))
3050                 return split;
3051             }
3052           else
3053             {
3054               SUBST (SET_SRC (x),
3055                      gen_rtx_combine
3056                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3057                       gen_rtx_combine (ASHIFT, mode,
3058                                        gen_lowpart_for_combine (mode, inner),
3059                                        GEN_INT (GET_MODE_BITSIZE (mode)
3060                                                 - len - pos)),
3061                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3062
3063               split = find_split_point (&SET_SRC (x), insn);
3064               if (split && split != &SET_SRC (x))
3065                 return split;
3066             }
3067         }
3068
3069       /* See if this is a simple operation with a constant as the second
3070          operand.  It might be that this constant is out of range and hence
3071          could be used as a split point.  */
3072       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3073            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3074            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3075           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3076           && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3077               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3078                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3079                       == 'o'))))
3080         return &XEXP (SET_SRC (x), 1);
3081
3082       /* Finally, see if this is a simple operation with its first operand
3083          not in a register.  The operation might require this operand in a
3084          register, so return it as a split point.  We can always do this
3085          because if the first operand were another operation, we would have
3086          already found it as a split point.  */
3087       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3088            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3089            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3090            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3091           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3092         return &XEXP (SET_SRC (x), 0);
3093
3094       return 0;
3095
3096     case AND:
3097     case IOR:
3098       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3099          it is better to write this as (not (ior A B)) so we can split it.
3100          Similarly for IOR.  */
3101       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3102         {
3103           SUBST (*loc,
3104                  gen_rtx_combine (NOT, GET_MODE (x),
3105                                   gen_rtx_combine (code == IOR ? AND : IOR,
3106                                                    GET_MODE (x),
3107                                                    XEXP (XEXP (x, 0), 0),
3108                                                    XEXP (XEXP (x, 1), 0))));
3109           return find_split_point (loc, insn);
3110         }
3111
3112       /* Many RISC machines have a large set of logical insns.  If the
3113          second operand is a NOT, put it first so we will try to split the
3114          other operand first.  */
3115       if (GET_CODE (XEXP (x, 1)) == NOT)
3116         {
3117           rtx tem = XEXP (x, 0);
3118           SUBST (XEXP (x, 0), XEXP (x, 1));
3119           SUBST (XEXP (x, 1), tem);
3120         }
3121       break;
3122
3123     default:
3124       break;
3125     }
3126
3127   /* Otherwise, select our actions depending on our rtx class.  */
3128   switch (GET_RTX_CLASS (code))
3129     {
3130     case 'b':                   /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3131     case '3':
3132       split = find_split_point (&XEXP (x, 2), insn);
3133       if (split)
3134         return split;
3135       /* ... fall through ...  */
3136     case '2':
3137     case 'c':
3138     case '<':
3139       split = find_split_point (&XEXP (x, 1), insn);
3140       if (split)
3141         return split;
3142       /* ... fall through ...  */
3143     case '1':
3144       /* Some machines have (and (shift ...) ...) insns.  If X is not
3145          an AND, but XEXP (X, 0) is, use it as our split point.  */
3146       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3147         return &XEXP (x, 0);
3148
3149       split = find_split_point (&XEXP (x, 0), insn);
3150       if (split)
3151         return split;
3152       return loc;
3153     }
3154
3155   /* Otherwise, we don't have a split point.  */
3156   return 0;
3157 }
3158 \f
3159 /* Throughout X, replace FROM with TO, and return the result.
3160    The result is TO if X is FROM;
3161    otherwise the result is X, but its contents may have been modified.
3162    If they were modified, a record was made in undobuf so that
3163    undo_all will (among other things) return X to its original state.
3164
3165    If the number of changes necessary is too much to record to undo,
3166    the excess changes are not made, so the result is invalid.
3167    The changes already made can still be undone.
3168    undobuf.num_undo is incremented for such changes, so by testing that
3169    the caller can tell whether the result is valid.
3170
3171    `n_occurrences' is incremented each time FROM is replaced.
3172
3173    IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3174
3175    UNIQUE_COPY is non-zero if each substitution must be unique.  We do this
3176    by copying if `n_occurrences' is non-zero.  */
3177
3178 static rtx
3179 subst (x, from, to, in_dest, unique_copy)
3180      register rtx x, from, to;
3181      int in_dest;
3182      int unique_copy;
3183 {
3184   register enum rtx_code code = GET_CODE (x);
3185   enum machine_mode op0_mode = VOIDmode;
3186   register const char *fmt;
3187   register int len, i;
3188   rtx new;
3189
3190 /* Two expressions are equal if they are identical copies of a shared
3191    RTX or if they are both registers with the same register number
3192    and mode.  */
3193
3194 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3195   ((X) == (Y)                                           \
3196    || (GET_CODE (X) == REG && GET_CODE (Y) == REG       \
3197        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3198
3199   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3200     {
3201       n_occurrences++;
3202       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3203     }
3204
3205   /* If X and FROM are the same register but different modes, they will
3206      not have been seen as equal above.  However, flow.c will make a
3207      LOG_LINKS entry for that case.  If we do nothing, we will try to
3208      rerecognize our original insn and, when it succeeds, we will
3209      delete the feeding insn, which is incorrect.
3210
3211      So force this insn not to match in this (rare) case.  */
3212   if (! in_dest && code == REG && GET_CODE (from) == REG
3213       && REGNO (x) == REGNO (from))
3214     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3215
3216   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3217      of which may contain things that can be combined.  */
3218   if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3219     return x;
3220
3221   /* It is possible to have a subexpression appear twice in the insn.
3222      Suppose that FROM is a register that appears within TO.
3223      Then, after that subexpression has been scanned once by `subst',
3224      the second time it is scanned, TO may be found.  If we were
3225      to scan TO here, we would find FROM within it and create a
3226      self-referent rtl structure which is completely wrong.  */
3227   if (COMBINE_RTX_EQUAL_P (x, to))
3228     return to;
3229
3230   /* Parallel asm_operands need special attention because all of the
3231      inputs are shared across the arms.  Furthermore, unsharing the
3232      rtl results in recognition failures.  Failure to handle this case
3233      specially can result in circular rtl.
3234
3235      Solve this by doing a normal pass across the first entry of the
3236      parallel, and only processing the SET_DESTs of the subsequent
3237      entries.  Ug.  */
3238
3239   if (code == PARALLEL
3240       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3241       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3242     {
3243       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3244
3245       /* If this substitution failed, this whole thing fails.  */
3246       if (GET_CODE (new) == CLOBBER
3247           && XEXP (new, 0) == const0_rtx)
3248         return new;
3249
3250       SUBST (XVECEXP (x, 0, 0), new);
3251
3252       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3253         {
3254           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3255
3256           if (GET_CODE (dest) != REG
3257               && GET_CODE (dest) != CC0
3258               && GET_CODE (dest) != PC)
3259             {
3260               new = subst (dest, from, to, 0, unique_copy);
3261
3262               /* If this substitution failed, this whole thing fails.  */
3263               if (GET_CODE (new) == CLOBBER
3264                   && XEXP (new, 0) == const0_rtx)
3265                 return new;
3266
3267               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3268             }
3269         }
3270     }
3271   else
3272     {
3273       len = GET_RTX_LENGTH (code);
3274       fmt = GET_RTX_FORMAT (code);
3275
3276       /* We don't need to process a SET_DEST that is a register, CC0,
3277          or PC, so set up to skip this common case.  All other cases
3278          where we want to suppress replacing something inside a
3279          SET_SRC are handled via the IN_DEST operand.  */
3280       if (code == SET
3281           && (GET_CODE (SET_DEST (x)) == REG
3282               || GET_CODE (SET_DEST (x)) == CC0
3283               || GET_CODE (SET_DEST (x)) == PC))
3284         fmt = "ie";
3285
3286       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3287          constant.  */
3288       if (fmt[0] == 'e')
3289         op0_mode = GET_MODE (XEXP (x, 0));
3290
3291       for (i = 0; i < len; i++)
3292         {
3293           if (fmt[i] == 'E')
3294             {
3295               register int j;
3296               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3297                 {
3298                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3299                     {
3300                       new = (unique_copy && n_occurrences
3301                              ? copy_rtx (to) : to);
3302                       n_occurrences++;
3303                     }
3304                   else
3305                     {
3306                       new = subst (XVECEXP (x, i, j), from, to, 0,
3307                                    unique_copy);
3308
3309                       /* If this substitution failed, this whole thing
3310                          fails.  */
3311                       if (GET_CODE (new) == CLOBBER
3312                           && XEXP (new, 0) == const0_rtx)
3313                         return new;
3314                     }
3315
3316                   SUBST (XVECEXP (x, i, j), new);
3317                 }
3318             }
3319           else if (fmt[i] == 'e')
3320             {
3321               if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3322                 {
3323                   /* In general, don't install a subreg involving two
3324                      modes not tieable.  It can worsen register
3325                      allocation, and can even make invalid reload
3326                      insns, since the reg inside may need to be copied
3327                      from in the outside mode, and that may be invalid
3328                      if it is an fp reg copied in integer mode.
3329
3330                      We allow two exceptions to this: It is valid if
3331                      it is inside another SUBREG and the mode of that
3332                      SUBREG and the mode of the inside of TO is
3333                      tieable and it is valid if X is a SET that copies
3334                      FROM to CC0.  */
3335
3336                   if (GET_CODE (to) == SUBREG
3337                       && ! MODES_TIEABLE_P (GET_MODE (to),
3338                                             GET_MODE (SUBREG_REG (to)))
3339                       && ! (code == SUBREG
3340                             && MODES_TIEABLE_P (GET_MODE (x),
3341                                                 GET_MODE (SUBREG_REG (to))))
3342 #ifdef HAVE_cc0
3343                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3344 #endif
3345                       )
3346                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3347
3348                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3349                   n_occurrences++;
3350                 }
3351               else
3352                 /* If we are in a SET_DEST, suppress most cases unless we
3353                    have gone inside a MEM, in which case we want to
3354                    simplify the address.  We assume here that things that
3355                    are actually part of the destination have their inner
3356                    parts in the first expression.  This is true for SUBREG,
3357                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3358                    things aside from REG and MEM that should appear in a
3359                    SET_DEST.  */
3360                 new = subst (XEXP (x, i), from, to,
3361                              (((in_dest
3362                                 && (code == SUBREG || code == STRICT_LOW_PART
3363                                     || code == ZERO_EXTRACT))
3364                                || code == SET)
3365                               && i == 0), unique_copy);
3366
3367               /* If we found that we will have to reject this combination,
3368                  indicate that by returning the CLOBBER ourselves, rather than
3369                  an expression containing it.  This will speed things up as
3370                  well as prevent accidents where two CLOBBERs are considered
3371                  to be equal, thus producing an incorrect simplification.  */
3372
3373               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3374                 return new;
3375
3376               SUBST (XEXP (x, i), new);
3377             }
3378         }
3379     }
3380
3381   /* Try to simplify X.  If the simplification changed the code, it is likely
3382      that further simplification will help, so loop, but limit the number
3383      of repetitions that will be performed.  */
3384
3385   for (i = 0; i < 4; i++)
3386     {
3387       /* If X is sufficiently simple, don't bother trying to do anything
3388          with it.  */
3389       if (code != CONST_INT && code != REG && code != CLOBBER)
3390         x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3391
3392       if (GET_CODE (x) == code)
3393         break;
3394
3395       code = GET_CODE (x);
3396
3397       /* We no longer know the original mode of operand 0 since we
3398          have changed the form of X)  */
3399       op0_mode = VOIDmode;
3400     }
3401
3402   return x;
3403 }
3404 \f
3405 /* Simplify X, a piece of RTL.  We just operate on the expression at the
3406    outer level; call `subst' to simplify recursively.  Return the new
3407    expression.
3408
3409    OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3410    will be the iteration even if an expression with a code different from
3411    X is returned; IN_DEST is nonzero if we are inside a SET_DEST.  */
3412
3413 static rtx
3414 combine_simplify_rtx (x, op0_mode, last, in_dest)
3415      rtx x;
3416      enum machine_mode op0_mode;
3417      int last;
3418      int in_dest;
3419 {
3420   enum rtx_code code = GET_CODE (x);
3421   enum machine_mode mode = GET_MODE (x);
3422   rtx temp;
3423   int i;
3424
3425   /* If this is a commutative operation, put a constant last and a complex
3426      expression first.  We don't need to do this for comparisons here.  */
3427   if (GET_RTX_CLASS (code) == 'c'
3428       && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3429           || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3430               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3431           || (GET_CODE (XEXP (x, 0)) == SUBREG
3432               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3433               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3434     {
3435       temp = XEXP (x, 0);
3436       SUBST (XEXP (x, 0), XEXP (x, 1));
3437       SUBST (XEXP (x, 1), temp);
3438     }
3439
3440   /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3441      sign extension of a PLUS with a constant, reverse the order of the sign
3442      extension and the addition. Note that this not the same as the original
3443      code, but overflow is undefined for signed values.  Also note that the
3444      PLUS will have been partially moved "inside" the sign-extension, so that
3445      the first operand of X will really look like:
3446          (ashiftrt (plus (ashift A C4) C5) C4).
3447      We convert this to
3448          (plus (ashiftrt (ashift A C4) C2) C4)
3449      and replace the first operand of X with that expression.  Later parts
3450      of this function may simplify the expression further.
3451
3452      For example, if we start with (mult (sign_extend (plus A C1)) C2),
3453      we swap the SIGN_EXTEND and PLUS.  Later code will apply the
3454      distributive law to produce (plus (mult (sign_extend X) C1) C3).
3455
3456      We do this to simplify address expressions.  */
3457
3458   if ((code == PLUS || code == MINUS || code == MULT)
3459       && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3460       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3461       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3462       && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3463       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3464       && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3465       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3466       && (temp = simplify_binary_operation (ASHIFTRT, mode,
3467                                             XEXP (XEXP (XEXP (x, 0), 0), 1),
3468                                             XEXP (XEXP (x, 0), 1))) != 0)
3469     {
3470       rtx new
3471         = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3472                                 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3473                                 INTVAL (XEXP (XEXP (x, 0), 1)));
3474
3475       new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3476                                   INTVAL (XEXP (XEXP (x, 0), 1)));
3477
3478       SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3479     }
3480
3481   /* If this is a simple operation applied to an IF_THEN_ELSE, try
3482      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
3483      things.  Check for cases where both arms are testing the same
3484      condition.
3485
3486      Don't do anything if all operands are very simple.  */
3487
3488   if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3489         || GET_RTX_CLASS (code) == '<')
3490        && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3491             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3492                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3493                       == 'o')))
3494            || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3495                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3496                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3497                          == 'o')))))
3498       || (GET_RTX_CLASS (code) == '1'
3499           && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3500                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3501                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3502                          == 'o'))))))
3503     {
3504       rtx cond, true, false;
3505
3506       cond = if_then_else_cond (x, &true, &false);
3507       if (cond != 0
3508           /* If everything is a comparison, what we have is highly unlikely
3509              to be simpler, so don't use it.  */
3510           && ! (GET_RTX_CLASS (code) == '<'
3511                 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3512                     || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3513         {
3514           rtx cop1 = const0_rtx;
3515           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3516
3517           if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3518             return x;
3519
3520           /* Simplify the alternative arms; this may collapse the true and
3521              false arms to store-flag values.  */
3522           true = subst (true, pc_rtx, pc_rtx, 0, 0);
3523           false = subst (false, pc_rtx, pc_rtx, 0, 0);
3524
3525           /* Restarting if we generate a store-flag expression will cause
3526              us to loop.  Just drop through in this case.  */
3527
3528           /* If the result values are STORE_FLAG_VALUE and zero, we can
3529              just make the comparison operation.  */
3530           if (true == const_true_rtx && false == const0_rtx)
3531             x = gen_binary (cond_code, mode, cond, cop1);
3532           else if (true == const0_rtx && false == const_true_rtx)
3533             x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3534
3535           /* Likewise, we can make the negate of a comparison operation
3536              if the result values are - STORE_FLAG_VALUE and zero.  */
3537           else if (GET_CODE (true) == CONST_INT
3538                    && INTVAL (true) == - STORE_FLAG_VALUE
3539                    && false == const0_rtx)
3540             x = gen_unary (NEG, mode, mode,
3541                            gen_binary (cond_code, mode, cond, cop1));
3542           else if (GET_CODE (false) == CONST_INT
3543                    && INTVAL (false) == - STORE_FLAG_VALUE
3544                    && true == const0_rtx)
3545             x = gen_unary (NEG, mode, mode,
3546                            gen_binary (reverse_condition (cond_code),
3547                                        mode, cond, cop1));
3548           else
3549             return gen_rtx_IF_THEN_ELSE (mode,
3550                                          gen_binary (cond_code, VOIDmode,
3551                                                      cond, cop1),
3552                                          true, false);
3553
3554           code = GET_CODE (x);
3555           op0_mode = VOIDmode;
3556         }
3557     }
3558
3559   /* Try to fold this expression in case we have constants that weren't
3560      present before.  */
3561   temp = 0;
3562   switch (GET_RTX_CLASS (code))
3563     {
3564     case '1':
3565       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3566       break;
3567     case '<':
3568       temp = simplify_relational_operation (code, op0_mode,
3569                                             XEXP (x, 0), XEXP (x, 1));
3570 #ifdef FLOAT_STORE_FLAG_VALUE
3571       if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3572         {
3573           if (temp == const0_rtx)
3574             temp = CONST0_RTX (mode);
3575           else
3576             temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3577         }
3578 #endif
3579       break;
3580     case 'c':
3581     case '2':
3582       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3583       break;
3584     case 'b':
3585     case '3':
3586       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3587                                          XEXP (x, 1), XEXP (x, 2));
3588       break;
3589     }
3590
3591   if (temp)
3592     x = temp, code = GET_CODE (temp);
3593
3594   /* First see if we can apply the inverse distributive law.  */
3595   if (code == PLUS || code == MINUS
3596       || code == AND || code == IOR || code == XOR)
3597     {
3598       x = apply_distributive_law (x);
3599       code = GET_CODE (x);
3600     }
3601
3602   /* If CODE is an associative operation not otherwise handled, see if we
3603      can associate some operands.  This can win if they are constants or
3604      if they are logically related (i.e. (a & b) & a.  */
3605   if ((code == PLUS || code == MINUS
3606        || code == MULT || code == AND || code == IOR || code == XOR
3607        || code == DIV || code == UDIV
3608        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3609       && INTEGRAL_MODE_P (mode))
3610     {
3611       if (GET_CODE (XEXP (x, 0)) == code)
3612         {
3613           rtx other = XEXP (XEXP (x, 0), 0);
3614           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3615           rtx inner_op1 = XEXP (x, 1);
3616           rtx inner;
3617
3618           /* Make sure we pass the constant operand if any as the second
3619              one if this is a commutative operation.  */
3620           if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3621             {
3622               rtx tem = inner_op0;
3623               inner_op0 = inner_op1;
3624               inner_op1 = tem;
3625             }
3626           inner = simplify_binary_operation (code == MINUS ? PLUS
3627                                              : code == DIV ? MULT
3628                                              : code == UDIV ? MULT
3629                                              : code,
3630                                              mode, inner_op0, inner_op1);
3631
3632           /* For commutative operations, try the other pair if that one
3633              didn't simplify.  */
3634           if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3635             {
3636               other = XEXP (XEXP (x, 0), 1);
3637               inner = simplify_binary_operation (code, mode,
3638                                                  XEXP (XEXP (x, 0), 0),
3639                                                  XEXP (x, 1));
3640             }
3641
3642           if (inner)
3643             return gen_binary (code, mode, other, inner);
3644         }
3645     }
3646
3647   /* A little bit of algebraic simplification here.  */
3648   switch (code)
3649     {
3650     case MEM:
3651       /* Ensure that our address has any ASHIFTs converted to MULT in case
3652          address-recognizing predicates are called later.  */
3653       temp = make_compound_operation (XEXP (x, 0), MEM);
3654       SUBST (XEXP (x, 0), temp);
3655       break;
3656
3657     case SUBREG:
3658       /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3659          is paradoxical.  If we can't do that safely, then it becomes
3660          something nonsensical so that this combination won't take place.  */
3661
3662       if (GET_CODE (SUBREG_REG (x)) == MEM
3663           && (GET_MODE_SIZE (mode)
3664               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3665         {
3666           rtx inner = SUBREG_REG (x);
3667           int endian_offset = 0;
3668           /* Don't change the mode of the MEM
3669              if that would change the meaning of the address.  */
3670           if (MEM_VOLATILE_P (SUBREG_REG (x))
3671               || mode_dependent_address_p (XEXP (inner, 0)))
3672             return gen_rtx_CLOBBER (mode, const0_rtx);
3673
3674           if (BYTES_BIG_ENDIAN)
3675             {
3676               if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3677                 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3678               if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3679                 endian_offset -= (UNITS_PER_WORD
3680                                   - GET_MODE_SIZE (GET_MODE (inner)));
3681             }
3682           /* Note if the plus_constant doesn't make a valid address
3683              then this combination won't be accepted.  */
3684           x = gen_rtx_MEM (mode,
3685                            plus_constant (XEXP (inner, 0),
3686                                           (SUBREG_WORD (x) * UNITS_PER_WORD
3687                                            + endian_offset)));
3688           RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3689           MEM_COPY_ATTRIBUTES (x, inner);
3690           return x;
3691         }
3692
3693       /* If we are in a SET_DEST, these other cases can't apply.  */
3694       if (in_dest)
3695         return x;
3696
3697       /* Changing mode twice with SUBREG => just change it once,
3698          or not at all if changing back to starting mode.  */
3699       if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3700         {
3701           if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3702               && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3703             return SUBREG_REG (SUBREG_REG (x));
3704
3705           SUBST_INT (SUBREG_WORD (x),
3706                      SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3707           SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3708         }
3709
3710       /* SUBREG of a hard register => just change the register number
3711          and/or mode.  If the hard register is not valid in that mode,
3712          suppress this combination.  If the hard register is the stack,
3713          frame, or argument pointer, leave this as a SUBREG.  */
3714
3715       if (GET_CODE (SUBREG_REG (x)) == REG
3716           && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3717           && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3718 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3719           && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3720 #endif
3721 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3722           && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3723 #endif
3724           && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3725         {
3726           if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3727                                   mode))
3728             return gen_rtx_REG (mode,
3729                                 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3730           else
3731             return gen_rtx_CLOBBER (mode, const0_rtx);
3732         }
3733
3734       /* For a constant, try to pick up the part we want.  Handle a full
3735          word and low-order part.  Only do this if we are narrowing
3736          the constant; if it is being widened, we have no idea what
3737          the extra bits will have been set to.  */
3738
3739       if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3740           && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3741           && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3742           && GET_MODE_CLASS (mode) == MODE_INT)
3743         {
3744           temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3745                                   0, op0_mode);
3746           if (temp)
3747             return temp;
3748         }
3749
3750       /* If we want a subreg of a constant, at offset 0,
3751          take the low bits.  On a little-endian machine, that's
3752          always valid.  On a big-endian machine, it's valid
3753          only if the constant's mode fits in one word.   Note that we
3754          cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode.  */
3755       if (CONSTANT_P (SUBREG_REG (x))
3756           && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3757               || ! WORDS_BIG_ENDIAN)
3758               ? SUBREG_WORD (x) == 0
3759               : (SUBREG_WORD (x)
3760                  == ((GET_MODE_SIZE (op0_mode)
3761                       - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3762                      / UNITS_PER_WORD)))
3763           && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3764           && (! WORDS_BIG_ENDIAN
3765               || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3766         return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3767
3768       /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3769          since we are saying that the high bits don't matter.  */
3770       if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3771           && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3772         {
3773           if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3774               && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3775             return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3776           return SUBREG_REG (x);
3777         }
3778
3779       /* Note that we cannot do any narrowing for non-constants since
3780          we might have been counting on using the fact that some bits were
3781          zero.  We now do this in the SET.  */
3782
3783       break;
3784
3785     case NOT:
3786       /* (not (plus X -1)) can become (neg X).  */
3787       if (GET_CODE (XEXP (x, 0)) == PLUS
3788           && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3789         return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3790
3791       /* Similarly, (not (neg X)) is (plus X -1).  */
3792       if (GET_CODE (XEXP (x, 0)) == NEG)
3793         return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3794                                 constm1_rtx);
3795
3796       /* (not (xor X C)) for C constant is (xor X D) with D = ~ C.  */
3797       if (GET_CODE (XEXP (x, 0)) == XOR
3798           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3799           && (temp = simplify_unary_operation (NOT, mode,
3800                                                XEXP (XEXP (x, 0), 1),
3801                                                mode)) != 0)
3802         return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3803
3804       /* (not (ashift 1 X)) is (rotate ~1 X).  We used to do this for operands
3805          other than 1, but that is not valid.  We could do a similar
3806          simplification for (not (lshiftrt C X)) where C is just the sign bit,
3807          but this doesn't seem common enough to bother with.  */
3808       if (GET_CODE (XEXP (x, 0)) == ASHIFT
3809           && XEXP (XEXP (x, 0), 0) == const1_rtx)
3810         return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3811                                XEXP (XEXP (x, 0), 1));
3812
3813       if (GET_CODE (XEXP (x, 0)) == SUBREG
3814           && subreg_lowpart_p (XEXP (x, 0))
3815           && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3816               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3817           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3818           && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3819         {
3820           enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3821
3822           x = gen_rtx_ROTATE (inner_mode,
3823                               gen_unary (NOT, inner_mode, inner_mode,
3824                                          const1_rtx),
3825                               XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3826           return gen_lowpart_for_combine (mode, x);
3827         }
3828
3829       /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3830          reversing the comparison code if valid.  */
3831       if (STORE_FLAG_VALUE == -1
3832           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3833           && reversible_comparison_p (XEXP (x, 0)))
3834         return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3835                                 mode, XEXP (XEXP (x, 0), 0),
3836                                 XEXP (XEXP (x, 0), 1));
3837
3838       /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3839          is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3840          perform the above simplification.  */
3841
3842       if (STORE_FLAG_VALUE == -1
3843           && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3844           && XEXP (x, 1) == const1_rtx
3845           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3846           && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3847         return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3848
3849       /* Apply De Morgan's laws to reduce number of patterns for machines
3850          with negating logical insns (and-not, nand, etc.).  If result has
3851          only one NOT, put it first, since that is how the patterns are
3852          coded.  */
3853
3854       if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3855         {
3856          rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3857
3858          if (GET_CODE (in1) == NOT)
3859            in1 = XEXP (in1, 0);
3860          else
3861            in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3862
3863          if (GET_CODE (in2) == NOT)
3864            in2 = XEXP (in2, 0);
3865          else if (GET_CODE (in2) == CONST_INT
3866                   && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3867            in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3868          else
3869            in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3870
3871          if (GET_CODE (in2) == NOT)
3872            {
3873              rtx tem = in2;
3874              in2 = in1; in1 = tem;
3875            }
3876
3877          return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3878                                  mode, in1, in2);
3879        }
3880       break;
3881
3882     case NEG:
3883       /* (neg (plus X 1)) can become (not X).  */
3884       if (GET_CODE (XEXP (x, 0)) == PLUS
3885           && XEXP (XEXP (x, 0), 1) == const1_rtx)
3886         return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3887
3888       /* Similarly, (neg (not X)) is (plus X 1).  */
3889       if (GET_CODE (XEXP (x, 0)) == NOT)
3890         return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3891
3892       /* (neg (minus X Y)) can become (minus Y X).  */
3893       if (GET_CODE (XEXP (x, 0)) == MINUS
3894           && (! FLOAT_MODE_P (mode)
3895               /* x-y != -(y-x) with IEEE floating point.  */
3896               || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3897               || flag_fast_math))
3898         return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3899                            XEXP (XEXP (x, 0), 0));
3900
3901       /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
3902       if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3903           && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3904         return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3905
3906       /* NEG commutes with ASHIFT since it is multiplication.  Only do this
3907          if we can then eliminate the NEG (e.g.,
3908          if the operand is a constant).  */
3909
3910       if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3911         {
3912           temp = simplify_unary_operation (NEG, mode,
3913                                            XEXP (XEXP (x, 0), 0), mode);
3914           if (temp)
3915             {
3916               SUBST (XEXP (XEXP (x, 0), 0), temp);
3917               return XEXP (x, 0);
3918             }
3919         }
3920
3921       temp = expand_compound_operation (XEXP (x, 0));
3922
3923       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3924          replaced by (lshiftrt X C).  This will convert
3925          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
3926
3927       if (GET_CODE (temp) == ASHIFTRT
3928           && GET_CODE (XEXP (temp, 1)) == CONST_INT
3929           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3930         return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3931                                      INTVAL (XEXP (temp, 1)));
3932
3933       /* If X has only a single bit that might be nonzero, say, bit I, convert
3934          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3935          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
3936          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
3937          or a SUBREG of one since we'd be making the expression more
3938          complex if it was just a register.  */
3939
3940       if (GET_CODE (temp) != REG
3941           && ! (GET_CODE (temp) == SUBREG
3942                 && GET_CODE (SUBREG_REG (temp)) == REG)
3943           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3944         {
3945           rtx temp1 = simplify_shift_const
3946             (NULL_RTX, ASHIFTRT, mode,
3947              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3948                                    GET_MODE_BITSIZE (mode) - 1 - i),
3949              GET_MODE_BITSIZE (mode) - 1 - i);
3950
3951           /* If all we did was surround TEMP with the two shifts, we
3952              haven't improved anything, so don't use it.  Otherwise,
3953              we are better off with TEMP1.  */
3954           if (GET_CODE (temp1) != ASHIFTRT
3955               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3956               || XEXP (XEXP (temp1, 0), 0) != temp)
3957             return temp1;
3958         }
3959       break;
3960
3961     case TRUNCATE:
3962       /* We can't handle truncation to a partial integer mode here
3963          because we don't know the real bitsize of the partial
3964          integer mode.  */
3965       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3966         break;
3967
3968       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3969           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3970                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3971         SUBST (XEXP (x, 0),
3972                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3973                               GET_MODE_MASK (mode), NULL_RTX, 0));
3974
3975       /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
3976       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3977            || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3978           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3979         return XEXP (XEXP (x, 0), 0);
3980
3981       /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3982          (OP:SI foo:SI) if OP is NEG or ABS.  */
3983       if ((GET_CODE (XEXP (x, 0)) == ABS
3984            || GET_CODE (XEXP (x, 0)) == NEG)
3985           && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3986               || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3987           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3988         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3989                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3990
3991       /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3992          (truncate:SI x).  */
3993       if (GET_CODE (XEXP (x, 0)) == SUBREG
3994           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3995           && subreg_lowpart_p (XEXP (x, 0)))
3996         return SUBREG_REG (XEXP (x, 0));
3997
3998       /* If we know that the value is already truncated, we can
3999          replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4000          is nonzero for the corresponding modes.  But don't do this
4001          for an (LSHIFTRT (MULT ...)) since this will cause problems
4002          with the umulXi3_highpart patterns.  */
4003       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4004                                  GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4005           && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4006              >= GET_MODE_BITSIZE (mode) + 1
4007           && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4008                 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4009         return gen_lowpart_for_combine (mode, XEXP (x, 0));
4010
4011       /* A truncate of a comparison can be replaced with a subreg if
4012          STORE_FLAG_VALUE permits.  This is like the previous test,
4013          but it works even if the comparison is done in a mode larger
4014          than HOST_BITS_PER_WIDE_INT.  */
4015       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4016           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4017           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
4018         return gen_lowpart_for_combine (mode, XEXP (x, 0));
4019
4020       /* Similarly, a truncate of a register whose value is a
4021          comparison can be replaced with a subreg if STORE_FLAG_VALUE
4022          permits.  */
4023       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4024           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
4025           && (temp = get_last_value (XEXP (x, 0)))
4026           && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4027         return gen_lowpart_for_combine (mode, XEXP (x, 0));
4028
4029       break;
4030
4031     case FLOAT_TRUNCATE:
4032       /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
4033       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4034           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4035         return XEXP (XEXP (x, 0), 0);
4036
4037       /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4038          (OP:SF foo:SF) if OP is NEG or ABS.  */
4039       if ((GET_CODE (XEXP (x, 0)) == ABS
4040            || GET_CODE (XEXP (x, 0)) == NEG)
4041           && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4042           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4043         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4044                           XEXP (XEXP (XEXP (x, 0), 0), 0));
4045
4046       /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4047          is (float_truncate:SF x).  */
4048       if (GET_CODE (XEXP (x, 0)) == SUBREG
4049           && subreg_lowpart_p (XEXP (x, 0))
4050           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4051         return SUBREG_REG (XEXP (x, 0));
4052       break;
4053
4054 #ifdef HAVE_cc0
4055     case COMPARE:
4056       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4057          using cc0, in which case we want to leave it as a COMPARE
4058          so we can distinguish it from a register-register-copy.  */
4059       if (XEXP (x, 1) == const0_rtx)
4060         return XEXP (x, 0);
4061
4062       /* In IEEE floating point, x-0 is not the same as x.  */
4063       if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4064            || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4065            || flag_fast_math)
4066           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4067         return XEXP (x, 0);
4068       break;
4069 #endif
4070
4071     case CONST:
4072       /* (const (const X)) can become (const X).  Do it this way rather than
4073          returning the inner CONST since CONST can be shared with a
4074          REG_EQUAL note.  */
4075       if (GET_CODE (XEXP (x, 0)) == CONST)
4076         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4077       break;
4078
4079 #ifdef HAVE_lo_sum
4080     case LO_SUM:
4081       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4082          can add in an offset.  find_split_point will split this address up
4083          again if it doesn't match.  */
4084       if (GET_CODE (XEXP (x, 0)) == HIGH
4085           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4086         return XEXP (x, 1);
4087       break;
4088 #endif
4089
4090     case PLUS:
4091       /* If we have (plus (plus (A const) B)), associate it so that CONST is
4092          outermost.  That's because that's the way indexed addresses are
4093          supposed to appear.  This code used to check many more cases, but
4094          they are now checked elsewhere.  */
4095       if (GET_CODE (XEXP (x, 0)) == PLUS
4096           && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4097         return gen_binary (PLUS, mode,
4098                            gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4099                                        XEXP (x, 1)),
4100                            XEXP (XEXP (x, 0), 1));
4101
4102       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4103          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4104          bit-field and can be replaced by either a sign_extend or a
4105          sign_extract.  The `and' may be a zero_extend and the two
4106          <c>, -<c> constants may be reversed.  */
4107       if (GET_CODE (XEXP (x, 0)) == XOR
4108           && GET_CODE (XEXP (x, 1)) == CONST_INT
4109           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4110           && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
4111           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4112               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4113           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4114           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4115                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4116                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4117                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4118               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4119                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4120                       == i + 1))))
4121         return simplify_shift_const
4122           (NULL_RTX, ASHIFTRT, mode,
4123            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4124                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4125                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4126            GET_MODE_BITSIZE (mode) - (i + 1));
4127
4128       /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4129          C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4130          is 1.  This produces better code than the alternative immediately
4131          below.  */
4132       if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4133           && reversible_comparison_p (XEXP (x, 0))
4134           && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4135               || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4136         return
4137           gen_unary (NEG, mode, mode,
4138                      gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4139                                  mode, XEXP (XEXP (x, 0), 0),
4140                                  XEXP (XEXP (x, 0), 1)));
4141
4142       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4143          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4144          the bitsize of the mode - 1.  This allows simplification of
4145          "a = (b & 8) == 0;"  */
4146       if (XEXP (x, 1) == constm1_rtx
4147           && GET_CODE (XEXP (x, 0)) != REG
4148           && ! (GET_CODE (XEXP (x,0)) == SUBREG
4149                 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4150           && nonzero_bits (XEXP (x, 0), mode) == 1)
4151         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4152            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4153                                  gen_rtx_combine (XOR, mode,
4154                                                   XEXP (x, 0), const1_rtx),
4155                                  GET_MODE_BITSIZE (mode) - 1),
4156            GET_MODE_BITSIZE (mode) - 1);
4157
4158       /* If we are adding two things that have no bits in common, convert
4159          the addition into an IOR.  This will often be further simplified,
4160          for example in cases like ((a & 1) + (a & 2)), which can
4161          become a & 3.  */
4162
4163       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4164           && (nonzero_bits (XEXP (x, 0), mode)
4165               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4166         return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4167       break;
4168
4169     case MINUS:
4170       /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4171          by reversing the comparison code if valid.  */
4172       if (STORE_FLAG_VALUE == 1
4173           && XEXP (x, 0) == const1_rtx
4174           && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4175           && reversible_comparison_p (XEXP (x, 1)))
4176         return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4177                            mode, XEXP (XEXP (x, 1), 0),
4178                                 XEXP (XEXP (x, 1), 1));
4179
4180       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4181          (and <foo> (const_int pow2-1))  */
4182       if (GET_CODE (XEXP (x, 1)) == AND
4183           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4184           && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4185           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4186         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4187                                        - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4188
4189       /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4190          integers.  */
4191       if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4192         return gen_binary (MINUS, mode,
4193                            gen_binary (MINUS, mode, XEXP (x, 0),
4194                                        XEXP (XEXP (x, 1), 0)),
4195                            XEXP (XEXP (x, 1), 1));
4196       break;
4197
4198     case MULT:
4199       /* If we have (mult (plus A B) C), apply the distributive law and then
4200          the inverse distributive law to see if things simplify.  This
4201          occurs mostly in addresses, often when unrolling loops.  */
4202
4203       if (GET_CODE (XEXP (x, 0)) == PLUS)
4204         {
4205           x = apply_distributive_law
4206             (gen_binary (PLUS, mode,
4207                          gen_binary (MULT, mode,
4208                                      XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4209                          gen_binary (MULT, mode,
4210                                      XEXP (XEXP (x, 0), 1),
4211                                      copy_rtx (XEXP (x, 1)))));
4212
4213           if (GET_CODE (x) != MULT)
4214             return x;
4215         }
4216       break;
4217
4218     case UDIV:
4219       /* If this is a divide by a power of two, treat it as a shift if
4220          its first operand is a shift.  */
4221       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4222           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4223           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4224               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4225               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4226               || GET_CODE (XEXP (x, 0)) == ROTATE
4227               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4228         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4229       break;
4230
4231     case EQ:  case NE:
4232     case GT:  case GTU:  case GE:  case GEU:
4233     case LT:  case LTU:  case LE:  case LEU:
4234       /* If the first operand is a condition code, we can't do anything
4235          with it.  */
4236       if (GET_CODE (XEXP (x, 0)) == COMPARE
4237           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4238 #ifdef HAVE_cc0
4239               && XEXP (x, 0) != cc0_rtx
4240 #endif
4241                ))
4242         {
4243           rtx op0 = XEXP (x, 0);
4244           rtx op1 = XEXP (x, 1);
4245           enum rtx_code new_code;
4246
4247           if (GET_CODE (op0) == COMPARE)
4248             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4249
4250           /* Simplify our comparison, if possible.  */
4251           new_code = simplify_comparison (code, &op0, &op1);
4252
4253           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4254              if only the low-order bit is possibly nonzero in X (such as when
4255              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4256              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4257              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4258              (plus X 1).
4259
4260              Remove any ZERO_EXTRACT we made when thinking this was a
4261              comparison.  It may now be simpler to use, e.g., an AND.  If a
4262              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4263              the call to make_compound_operation in the SET case.  */
4264
4265           if (STORE_FLAG_VALUE == 1
4266               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4267               && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4268             return gen_lowpart_for_combine (mode,
4269                                             expand_compound_operation (op0));
4270
4271           else if (STORE_FLAG_VALUE == 1
4272                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4273                    && op1 == const0_rtx
4274                    && (num_sign_bit_copies (op0, mode)
4275                        == GET_MODE_BITSIZE (mode)))
4276             {
4277               op0 = expand_compound_operation (op0);
4278               return gen_unary (NEG, mode, mode,
4279                                 gen_lowpart_for_combine (mode, op0));
4280             }
4281
4282           else if (STORE_FLAG_VALUE == 1
4283                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4284                    && op1 == const0_rtx
4285                    && nonzero_bits (op0, mode) == 1)
4286             {
4287               op0 = expand_compound_operation (op0);
4288               return gen_binary (XOR, mode,
4289                                  gen_lowpart_for_combine (mode, op0),
4290                                  const1_rtx);
4291             }
4292
4293           else if (STORE_FLAG_VALUE == 1
4294                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4295                    && op1 == const0_rtx
4296                    && (num_sign_bit_copies (op0, mode)
4297                        == GET_MODE_BITSIZE (mode)))
4298             {
4299               op0 = expand_compound_operation (op0);
4300               return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4301             }
4302
4303           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4304              those above.  */
4305           if (STORE_FLAG_VALUE == -1
4306               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4307               && op1 == const0_rtx
4308               && (num_sign_bit_copies (op0, mode)
4309                   == GET_MODE_BITSIZE (mode)))
4310             return gen_lowpart_for_combine (mode,
4311                                             expand_compound_operation (op0));
4312
4313           else if (STORE_FLAG_VALUE == -1
4314                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4315                    && op1 == const0_rtx
4316                    && nonzero_bits (op0, mode) == 1)
4317             {
4318               op0 = expand_compound_operation (op0);
4319               return gen_unary (NEG, mode, mode,
4320                                 gen_lowpart_for_combine (mode, op0));
4321             }
4322
4323           else if (STORE_FLAG_VALUE == -1
4324                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4325                    && op1 == const0_rtx
4326                    && (num_sign_bit_copies (op0, mode)
4327                        == GET_MODE_BITSIZE (mode)))
4328             {
4329               op0 = expand_compound_operation (op0);
4330               return gen_unary (NOT, mode, mode,
4331                                 gen_lowpart_for_combine (mode, op0));
4332             }
4333
4334           /* If X is 0/1, (eq X 0) is X-1.  */
4335           else if (STORE_FLAG_VALUE == -1
4336                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4337                    && op1 == const0_rtx
4338                    && nonzero_bits (op0, mode) == 1)
4339             {
4340               op0 = expand_compound_operation (op0);
4341               return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4342             }
4343
4344           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4345              one bit that might be nonzero, we can convert (ne x 0) to
4346              (ashift x c) where C puts the bit in the sign bit.  Remove any
4347              AND with STORE_FLAG_VALUE when we are done, since we are only
4348              going to test the sign bit.  */
4349           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4350               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4351               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4352                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4353               && op1 == const0_rtx
4354               && mode == GET_MODE (op0)
4355               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4356             {
4357               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4358                                         expand_compound_operation (op0),
4359                                         GET_MODE_BITSIZE (mode) - 1 - i);
4360               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4361                 return XEXP (x, 0);
4362               else
4363                 return x;
4364             }
4365
4366           /* If the code changed, return a whole new comparison.  */
4367           if (new_code != code)
4368             return gen_rtx_combine (new_code, mode, op0, op1);
4369
4370           /* Otherwise, keep this operation, but maybe change its operands.
4371              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4372           SUBST (XEXP (x, 0), op0);
4373           SUBST (XEXP (x, 1), op1);
4374         }
4375       break;
4376
4377     case IF_THEN_ELSE:
4378       return simplify_if_then_else (x);
4379
4380     case ZERO_EXTRACT:
4381     case SIGN_EXTRACT:
4382     case ZERO_EXTEND:
4383     case SIGN_EXTEND:
4384       /* If we are processing SET_DEST, we are done.  */
4385       if (in_dest)
4386         return x;
4387
4388       return expand_compound_operation (x);
4389
4390     case SET:
4391       return simplify_set (x);
4392
4393     case AND:
4394     case IOR:
4395     case XOR:
4396       return simplify_logical (x, last);
4397
4398     case ABS:
4399       /* (abs (neg <foo>)) -> (abs <foo>) */
4400       if (GET_CODE (XEXP (x, 0)) == NEG)
4401         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4402
4403       /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4404          do nothing.  */
4405       if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4406         break;
4407
4408       /* If operand is something known to be positive, ignore the ABS.  */
4409       if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4410           || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4411                <= HOST_BITS_PER_WIDE_INT)
4412               && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4413                    & ((HOST_WIDE_INT) 1
4414                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4415                   == 0)))
4416         return XEXP (x, 0);
4417
4418
4419       /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
4420       if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4421         return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4422
4423       break;
4424
4425     case FFS:
4426       /* (ffs (*_extend <X>)) = (ffs <X>) */
4427       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4428           || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4429         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4430       break;
4431
4432     case FLOAT:
4433       /* (float (sign_extend <X>)) = (float <X>).  */
4434       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4435         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4436       break;
4437
4438     case ASHIFT:
4439     case LSHIFTRT:
4440     case ASHIFTRT:
4441     case ROTATE:
4442     case ROTATERT:
4443       /* If this is a shift by a constant amount, simplify it.  */
4444       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4445         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4446                                      INTVAL (XEXP (x, 1)));
4447
4448 #ifdef SHIFT_COUNT_TRUNCATED
4449       else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4450         SUBST (XEXP (x, 1),
4451                force_to_mode (XEXP (x, 1), GET_MODE (x),
4452                               ((HOST_WIDE_INT) 1
4453                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4454                               - 1,
4455                               NULL_RTX, 0));
4456 #endif
4457
4458       break;
4459
4460     default:
4461       break;
4462     }
4463
4464   return x;
4465 }
4466 \f
4467 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4468
4469 static rtx
4470 simplify_if_then_else (x)
4471      rtx x;
4472 {
4473   enum machine_mode mode = GET_MODE (x);
4474   rtx cond = XEXP (x, 0);
4475   rtx true = XEXP (x, 1);
4476   rtx false = XEXP (x, 2);
4477   enum rtx_code true_code = GET_CODE (cond);
4478   int comparison_p = GET_RTX_CLASS (true_code) == '<';
4479   rtx temp;
4480   int i;
4481
4482   /* Simplify storing of the truth value.  */
4483   if (comparison_p && true == const_true_rtx && false == const0_rtx)
4484     return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4485
4486   /* Also when the truth value has to be reversed.  */
4487   if (comparison_p && reversible_comparison_p (cond)
4488       && true == const0_rtx && false == const_true_rtx)
4489     return gen_binary (reverse_condition (true_code),
4490                        mode, XEXP (cond, 0), XEXP (cond, 1));
4491
4492   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4493      in it is being compared against certain values.  Get the true and false
4494      comparisons and see if that says anything about the value of each arm.  */
4495
4496   if (comparison_p && reversible_comparison_p (cond)
4497       && GET_CODE (XEXP (cond, 0)) == REG)
4498     {
4499       HOST_WIDE_INT nzb;
4500       rtx from = XEXP (cond, 0);
4501       enum rtx_code false_code = reverse_condition (true_code);
4502       rtx true_val = XEXP (cond, 1);
4503       rtx false_val = true_val;
4504       int swapped = 0;
4505
4506       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4507
4508       if (false_code == EQ)
4509         {
4510           swapped = 1, true_code = EQ, false_code = NE;
4511           temp = true, true = false, false = temp;
4512         }
4513
4514       /* If we are comparing against zero and the expression being tested has
4515          only a single bit that might be nonzero, that is its value when it is
4516          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4517
4518       if (true_code == EQ && true_val == const0_rtx
4519           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4520         false_code = EQ, false_val = GEN_INT (nzb);
4521       else if (true_code == EQ && true_val == const0_rtx
4522                && (num_sign_bit_copies (from, GET_MODE (from))
4523                    == GET_MODE_BITSIZE (GET_MODE (from))))
4524         false_code = EQ, false_val = constm1_rtx;
4525
4526       /* Now simplify an arm if we know the value of the register in the
4527          branch and it is used in the arm.  Be careful due to the potential
4528          of locally-shared RTL.  */
4529
4530       if (reg_mentioned_p (from, true))
4531         true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4532                       pc_rtx, pc_rtx, 0, 0);
4533       if (reg_mentioned_p (from, false))
4534         false = subst (known_cond (copy_rtx (false), false_code,
4535                                    from, false_val),
4536                        pc_rtx, pc_rtx, 0, 0);
4537
4538       SUBST (XEXP (x, 1), swapped ? false : true);
4539       SUBST (XEXP (x, 2), swapped ? true : false);
4540
4541       true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4542     }
4543
4544   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4545      reversed, do so to avoid needing two sets of patterns for
4546      subtract-and-branch insns.  Similarly if we have a constant in the true
4547      arm, the false arm is the same as the first operand of the comparison, or
4548      the false arm is more complicated than the true arm.  */
4549
4550   if (comparison_p && reversible_comparison_p (cond)
4551       && (true == pc_rtx
4552           || (CONSTANT_P (true)
4553               && GET_CODE (false) != CONST_INT && false != pc_rtx)
4554           || true == const0_rtx
4555           || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4556               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4557           || (GET_CODE (true) == SUBREG
4558               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4559               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4560           || reg_mentioned_p (true, false)
4561           || rtx_equal_p (false, XEXP (cond, 0))))
4562     {
4563       true_code = reverse_condition (true_code);
4564       SUBST (XEXP (x, 0),
4565              gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4566                          XEXP (cond, 1)));
4567
4568       SUBST (XEXP (x, 1), false);
4569       SUBST (XEXP (x, 2), true);
4570
4571       temp = true, true = false, false = temp, cond = XEXP (x, 0);
4572
4573       /* It is possible that the conditional has been simplified out.  */
4574       true_code = GET_CODE (cond);
4575       comparison_p = GET_RTX_CLASS (true_code) == '<';
4576     }
4577
4578   /* If the two arms are identical, we don't need the comparison.  */
4579
4580   if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4581     return true;
4582
4583   /* Convert a == b ? b : a to "a".  */
4584   if (true_code == EQ && ! side_effects_p (cond)
4585       && rtx_equal_p (XEXP (cond, 0), false)
4586       && rtx_equal_p (XEXP (cond, 1), true))
4587     return false;
4588   else if (true_code == NE && ! side_effects_p (cond)
4589            && rtx_equal_p (XEXP (cond, 0), true)
4590            && rtx_equal_p (XEXP (cond, 1), false))
4591     return true;
4592
4593   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4594
4595   if (GET_MODE_CLASS (mode) == MODE_INT
4596       && GET_CODE (false) == NEG
4597       && rtx_equal_p (true, XEXP (false, 0))
4598       && comparison_p
4599       && rtx_equal_p (true, XEXP (cond, 0))
4600       && ! side_effects_p (true))
4601     switch (true_code)
4602       {
4603       case GT:
4604       case GE:
4605         return gen_unary (ABS, mode, mode, true);
4606       case LT:
4607       case LE:
4608         return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4609     default:
4610       break;
4611       }
4612
4613   /* Look for MIN or MAX.  */
4614
4615   if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4616       && comparison_p
4617       && rtx_equal_p (XEXP (cond, 0), true)
4618       && rtx_equal_p (XEXP (cond, 1), false)
4619       && ! side_effects_p (cond))
4620     switch (true_code)
4621       {
4622       case GE:
4623       case GT:
4624         return gen_binary (SMAX, mode, true, false);
4625       case LE:
4626       case LT:
4627         return gen_binary (SMIN, mode, true, false);
4628       case GEU:
4629       case GTU:
4630         return gen_binary (UMAX, mode, true, false);
4631       case LEU:
4632       case LTU:
4633         return gen_binary (UMIN, mode, true, false);
4634       default:
4635         break;
4636       }
4637
4638   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4639      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4640      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4641      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4642      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4643      neither 1 or -1, but it isn't worth checking for.  */
4644
4645   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4646       && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4647     {
4648       rtx t = make_compound_operation (true, SET);
4649       rtx f = make_compound_operation (false, SET);
4650       rtx cond_op0 = XEXP (cond, 0);
4651       rtx cond_op1 = XEXP (cond, 1);
4652       enum rtx_code op = NIL, extend_op = NIL;
4653       enum machine_mode m = mode;
4654       rtx z = 0, c1 = NULL_RTX;
4655
4656       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4657            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4658            || GET_CODE (t) == ASHIFT
4659            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4660           && rtx_equal_p (XEXP (t, 0), f))
4661         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4662
4663       /* If an identity-zero op is commutative, check whether there
4664          would be a match if we swapped the operands.  */
4665       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4666                 || GET_CODE (t) == XOR)
4667                && rtx_equal_p (XEXP (t, 1), f))
4668         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4669       else if (GET_CODE (t) == SIGN_EXTEND
4670                && (GET_CODE (XEXP (t, 0)) == PLUS
4671                    || GET_CODE (XEXP (t, 0)) == MINUS
4672                    || GET_CODE (XEXP (t, 0)) == IOR
4673                    || GET_CODE (XEXP (t, 0)) == XOR
4674                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4675                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4676                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4677                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4678                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4679                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4680                && (num_sign_bit_copies (f, GET_MODE (f))
4681                    > (GET_MODE_BITSIZE (mode)
4682                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4683         {
4684           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4685           extend_op = SIGN_EXTEND;
4686           m = GET_MODE (XEXP (t, 0));
4687         }
4688       else if (GET_CODE (t) == SIGN_EXTEND
4689                && (GET_CODE (XEXP (t, 0)) == PLUS
4690                    || GET_CODE (XEXP (t, 0)) == IOR
4691                    || GET_CODE (XEXP (t, 0)) == XOR)
4692                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4693                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4694                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4695                && (num_sign_bit_copies (f, GET_MODE (f))
4696                    > (GET_MODE_BITSIZE (mode)
4697                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4698         {
4699           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4700           extend_op = SIGN_EXTEND;
4701           m = GET_MODE (XEXP (t, 0));
4702         }
4703       else if (GET_CODE (t) == ZERO_EXTEND
4704                && (GET_CODE (XEXP (t, 0)) == PLUS
4705                    || GET_CODE (XEXP (t, 0)) == MINUS
4706                    || GET_CODE (XEXP (t, 0)) == IOR
4707                    || GET_CODE (XEXP (t, 0)) == XOR
4708                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4709                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4710                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4711                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4712                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4713                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4714                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4715                && ((nonzero_bits (f, GET_MODE (f))
4716                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4717                    == 0))
4718         {
4719           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4720           extend_op = ZERO_EXTEND;
4721           m = GET_MODE (XEXP (t, 0));
4722         }
4723       else if (GET_CODE (t) == ZERO_EXTEND
4724                && (GET_CODE (XEXP (t, 0)) == PLUS
4725                    || GET_CODE (XEXP (t, 0)) == IOR
4726                    || GET_CODE (XEXP (t, 0)) == XOR)
4727                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4728                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4729                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4730                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4731                && ((nonzero_bits (f, GET_MODE (f))
4732                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4733                    == 0))
4734         {
4735           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4736           extend_op = ZERO_EXTEND;
4737           m = GET_MODE (XEXP (t, 0));
4738         }
4739
4740       if (z)
4741         {
4742           temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4743                         pc_rtx, pc_rtx, 0, 0);
4744           temp = gen_binary (MULT, m, temp,
4745                              gen_binary (MULT, m, c1, const_true_rtx));
4746           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4747           temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4748
4749           if (extend_op != NIL)
4750             temp = gen_unary (extend_op, mode, m, temp);
4751
4752           return temp;
4753         }
4754     }
4755
4756   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4757      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4758      negation of a single bit, we can convert this operation to a shift.  We
4759      can actually do this more generally, but it doesn't seem worth it.  */
4760
4761   if (true_code == NE && XEXP (cond, 1) == const0_rtx
4762       && false == const0_rtx && GET_CODE (true) == CONST_INT
4763       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4764            && (i = exact_log2 (INTVAL (true))) >= 0)
4765           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4766                == GET_MODE_BITSIZE (mode))
4767               && (i = exact_log2 (- INTVAL (true))) >= 0)))
4768     return
4769       simplify_shift_const (NULL_RTX, ASHIFT, mode,
4770                             gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4771
4772   return x;
4773 }
4774 \f
4775 /* Simplify X, a SET expression.  Return the new expression.  */
4776
4777 static rtx
4778 simplify_set (x)
4779      rtx x;
4780 {
4781   rtx src = SET_SRC (x);
4782   rtx dest = SET_DEST (x);
4783   enum machine_mode mode
4784     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4785   rtx other_insn;
4786   rtx *cc_use;
4787
4788   /* (set (pc) (return)) gets written as (return).  */
4789   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4790     return src;
4791
4792   /* Now that we know for sure which bits of SRC we are using, see if we can
4793      simplify the expression for the object knowing that we only need the
4794      low-order bits.  */
4795
4796   if (GET_MODE_CLASS (mode) == MODE_INT)
4797     {
4798       src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4799       SUBST (SET_SRC (x), src);
4800     }
4801
4802   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4803      the comparison result and try to simplify it unless we already have used
4804      undobuf.other_insn.  */
4805   if ((GET_CODE (src) == COMPARE
4806 #ifdef HAVE_cc0
4807        || dest == cc0_rtx
4808 #endif
4809        )
4810       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4811       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4812       && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4813       && rtx_equal_p (XEXP (*cc_use, 0), dest))
4814     {
4815       enum rtx_code old_code = GET_CODE (*cc_use);
4816       enum rtx_code new_code;
4817       rtx op0, op1;
4818       int other_changed = 0;
4819       enum machine_mode compare_mode = GET_MODE (dest);
4820
4821       if (GET_CODE (src) == COMPARE)
4822         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4823       else
4824         op0 = src, op1 = const0_rtx;
4825
4826       /* Simplify our comparison, if possible.  */
4827       new_code = simplify_comparison (old_code, &op0, &op1);
4828
4829 #ifdef EXTRA_CC_MODES
4830       /* If this machine has CC modes other than CCmode, check to see if we
4831          need to use a different CC mode here.  */
4832       compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4833 #endif /* EXTRA_CC_MODES */
4834
4835 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4836       /* If the mode changed, we have to change SET_DEST, the mode in the
4837          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
4838          a hard register, just build new versions with the proper mode.  If it
4839          is a pseudo, we lose unless it is only time we set the pseudo, in
4840          which case we can safely change its mode.  */
4841       if (compare_mode != GET_MODE (dest))
4842         {
4843           int regno = REGNO (dest);
4844           rtx new_dest = gen_rtx_REG (compare_mode, regno);
4845
4846           if (regno < FIRST_PSEUDO_REGISTER
4847               || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4848             {
4849               if (regno >= FIRST_PSEUDO_REGISTER)
4850                 SUBST (regno_reg_rtx[regno], new_dest);
4851
4852               SUBST (SET_DEST (x), new_dest);
4853               SUBST (XEXP (*cc_use, 0), new_dest);
4854               other_changed = 1;
4855
4856               dest = new_dest;
4857             }
4858         }
4859 #endif
4860
4861       /* If the code changed, we have to build a new comparison in
4862          undobuf.other_insn.  */
4863       if (new_code != old_code)
4864         {
4865           unsigned HOST_WIDE_INT mask;
4866
4867           SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4868                                            dest, const0_rtx));
4869
4870           /* If the only change we made was to change an EQ into an NE or
4871              vice versa, OP0 has only one bit that might be nonzero, and OP1
4872              is zero, check if changing the user of the condition code will
4873              produce a valid insn.  If it won't, we can keep the original code
4874              in that insn by surrounding our operation with an XOR.  */
4875
4876           if (((old_code == NE && new_code == EQ)
4877                || (old_code == EQ && new_code == NE))
4878               && ! other_changed && op1 == const0_rtx
4879               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4880               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4881             {
4882               rtx pat = PATTERN (other_insn), note = 0;
4883
4884               if ((recog_for_combine (&pat, other_insn, &note) < 0
4885                    && ! check_asm_operands (pat)))
4886                 {
4887                   PUT_CODE (*cc_use, old_code);
4888                   other_insn = 0;
4889
4890                   op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4891                 }
4892             }
4893
4894           other_changed = 1;
4895         }
4896
4897       if (other_changed)
4898         undobuf.other_insn = other_insn;
4899
4900 #ifdef HAVE_cc0
4901       /* If we are now comparing against zero, change our source if
4902          needed.  If we do not use cc0, we always have a COMPARE.  */
4903       if (op1 == const0_rtx && dest == cc0_rtx)
4904         {
4905           SUBST (SET_SRC (x), op0);
4906           src = op0;
4907         }
4908       else
4909 #endif
4910
4911       /* Otherwise, if we didn't previously have a COMPARE in the
4912          correct mode, we need one.  */
4913       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4914         {
4915           SUBST (SET_SRC (x),
4916                  gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4917           src = SET_SRC (x);
4918         }
4919       else
4920         {
4921           /* Otherwise, update the COMPARE if needed.  */
4922           SUBST (XEXP (src, 0), op0);
4923           SUBST (XEXP (src, 1), op1);
4924         }
4925     }
4926   else
4927     {
4928       /* Get SET_SRC in a form where we have placed back any
4929          compound expressions.  Then do the checks below.  */
4930       src = make_compound_operation (src, SET);
4931       SUBST (SET_SRC (x), src);
4932     }
4933
4934   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4935      and X being a REG or (subreg (reg)), we may be able to convert this to
4936      (set (subreg:m2 x) (op)).
4937
4938      We can always do this if M1 is narrower than M2 because that means that
4939      we only care about the low bits of the result.
4940
4941      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4942      perform a narrower operation than requested since the high-order bits will
4943      be undefined.  On machine where it is defined, this transformation is safe
4944      as long as M1 and M2 have the same number of words.  */
4945
4946   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4947       && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4948       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4949            / UNITS_PER_WORD)
4950           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4951                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4952 #ifndef WORD_REGISTER_OPERATIONS
4953       && (GET_MODE_SIZE (GET_MODE (src))
4954           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4955 #endif
4956 #ifdef CLASS_CANNOT_CHANGE_SIZE
4957       && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4958             && (TEST_HARD_REG_BIT
4959                 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4960                  REGNO (dest)))
4961             && (GET_MODE_SIZE (GET_MODE (src))
4962                 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4963 #endif
4964       && (GET_CODE (dest) == REG
4965           || (GET_CODE (dest) == SUBREG
4966               && GET_CODE (SUBREG_REG (dest)) == REG)))
4967     {
4968       SUBST (SET_DEST (x),
4969              gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4970                                       dest));
4971       SUBST (SET_SRC (x), SUBREG_REG (src));
4972
4973       src = SET_SRC (x), dest = SET_DEST (x);
4974     }
4975
4976 #ifdef LOAD_EXTEND_OP
4977   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4978      would require a paradoxical subreg.  Replace the subreg with a
4979      zero_extend to avoid the reload that would otherwise be required.  */
4980
4981   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4982       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4983       && SUBREG_WORD (src) == 0
4984       && (GET_MODE_SIZE (GET_MODE (src))
4985           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4986       && GET_CODE (SUBREG_REG (src)) == MEM)
4987     {
4988       SUBST (SET_SRC (x),
4989              gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4990                               GET_MODE (src), XEXP (src, 0)));
4991
4992       src = SET_SRC (x);
4993     }
4994 #endif
4995
4996   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4997      are comparing an item known to be 0 or -1 against 0, use a logical
4998      operation instead. Check for one of the arms being an IOR of the other
4999      arm with some value.  We compute three terms to be IOR'ed together.  In
5000      practice, at most two will be nonzero.  Then we do the IOR's.  */
5001
5002   if (GET_CODE (dest) != PC
5003       && GET_CODE (src) == IF_THEN_ELSE
5004       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5005       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5006       && XEXP (XEXP (src, 0), 1) == const0_rtx
5007       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5008 #ifdef HAVE_conditional_move
5009       && ! can_conditionally_move_p (GET_MODE (src))
5010 #endif
5011       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5012                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5013           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5014       && ! side_effects_p (src))
5015     {
5016       rtx true = (GET_CODE (XEXP (src, 0)) == NE
5017                       ? XEXP (src, 1) : XEXP (src, 2));
5018       rtx false = (GET_CODE (XEXP (src, 0)) == NE
5019                    ? XEXP (src, 2) : XEXP (src, 1));
5020       rtx term1 = const0_rtx, term2, term3;
5021
5022       if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5023         term1 = false, true = XEXP (true, 1), false = const0_rtx;
5024       else if (GET_CODE (true) == IOR
5025                && rtx_equal_p (XEXP (true, 1), false))
5026         term1 = false, true = XEXP (true, 0), false = const0_rtx;
5027       else if (GET_CODE (false) == IOR
5028                && rtx_equal_p (XEXP (false, 0), true))
5029         term1 = true, false = XEXP (false, 1), true = const0_rtx;
5030       else if (GET_CODE (false) == IOR
5031                && rtx_equal_p (XEXP (false, 1), true))
5032         term1 = true, false = XEXP (false, 0), true = const0_rtx;
5033
5034       term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5035       term3 = gen_binary (AND, GET_MODE (src),
5036                           gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5037                                      XEXP (XEXP (src, 0), 0)),
5038                           false);
5039
5040       SUBST (SET_SRC (x),
5041              gen_binary (IOR, GET_MODE (src),
5042                          gen_binary (IOR, GET_MODE (src), term1, term2),
5043                          term3));
5044
5045       src = SET_SRC (x);
5046     }
5047
5048 #ifdef HAVE_conditional_arithmetic
5049   /* If we have conditional arithmetic and the operand of a SET is
5050      a conditional expression, replace this with an IF_THEN_ELSE.
5051      We can either have a conditional expression or a MULT of that expression
5052      with a constant.  */
5053   if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5054        || GET_RTX_CLASS (GET_CODE (src)) == '2'
5055        || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5056       && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5057           || (GET_CODE (XEXP (src, 0)) == MULT
5058               && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5059               && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5060     {
5061       rtx cond = XEXP (src, 0);
5062       rtx true_val = const1_rtx;
5063       rtx false_arm, true_arm;
5064
5065       if (GET_CODE (cond) == MULT)
5066         {
5067           true_val = XEXP (cond, 1);
5068           cond = XEXP (cond, 0);
5069         }
5070
5071       if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5072         {
5073           true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5074                                 GET_MODE (XEXP (src, 0)), true_val);
5075           false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5076                                  GET_MODE (XEXP (src, 0)), const0_rtx);
5077         }
5078       else
5079         {
5080           true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5081                                  true_val, XEXP (src, 1));
5082           false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5083                                   const0_rtx, XEXP (src, 1));
5084         }
5085
5086       /* Canonicalize if true_arm is the simpler one.  */
5087       if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5088           && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5089           && reversible_comparison_p (cond))
5090         {
5091           rtx temp = true_arm;
5092
5093           true_arm = false_arm;
5094           false_arm = temp;
5095
5096           cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5097                                   GET_MODE (cond), XEXP (cond, 0),
5098                                   XEXP (cond, 1));
5099         }
5100
5101       src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5102                              gen_rtx_combine (GET_CODE (cond), VOIDmode,
5103                                               XEXP (cond, 0),
5104                                               XEXP (cond, 1)),
5105                              true_arm, false_arm);
5106       SUBST (SET_SRC (x), src);
5107     }
5108 #endif
5109
5110   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5111      whole thing fail.  */
5112   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5113     return src;
5114   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5115     return dest;
5116   else
5117     /* Convert this into a field assignment operation, if possible.  */
5118     return make_field_assignment (x);
5119 }
5120 \f
5121 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5122    result.  LAST is nonzero if this is the last retry.  */
5123
5124 static rtx
5125 simplify_logical (x, last)
5126      rtx x;
5127      int last;
5128 {
5129   enum machine_mode mode = GET_MODE (x);
5130   rtx op0 = XEXP (x, 0);
5131   rtx op1 = XEXP (x, 1);
5132
5133   switch (GET_CODE (x))
5134     {
5135     case AND:
5136       /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5137          insn (and may simplify more).  */
5138       if (GET_CODE (op0) == XOR
5139           && rtx_equal_p (XEXP (op0, 0), op1)
5140           && ! side_effects_p (op1))
5141         x = gen_binary (AND, mode,
5142                         gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5143
5144       if (GET_CODE (op0) == XOR
5145           && rtx_equal_p (XEXP (op0, 1), op1)
5146           && ! side_effects_p (op1))
5147         x = gen_binary (AND, mode,
5148                         gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5149
5150       /* Similarly for (~ (A ^ B)) & A.  */
5151       if (GET_CODE (op0) == NOT
5152           && GET_CODE (XEXP (op0, 0)) == XOR
5153           && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5154           && ! side_effects_p (op1))
5155         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5156
5157       if (GET_CODE (op0) == NOT
5158           && GET_CODE (XEXP (op0, 0)) == XOR
5159           && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5160           && ! side_effects_p (op1))
5161         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5162
5163       /* We can call simplify_and_const_int only if we don't lose
5164          any (sign) bits when converting INTVAL (op1) to
5165          "unsigned HOST_WIDE_INT".  */
5166       if (GET_CODE (op1) == CONST_INT
5167           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5168               || INTVAL (op1) > 0))
5169         {
5170           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5171
5172           /* If we have (ior (and (X C1) C2)) and the next restart would be
5173              the last, simplify this by making C1 as small as possible
5174              and then exit.  */
5175           if (last
5176               && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5177               && GET_CODE (XEXP (op0, 1)) == CONST_INT
5178               && GET_CODE (op1) == CONST_INT)
5179             return gen_binary (IOR, mode,
5180                                gen_binary (AND, mode, XEXP (op0, 0),
5181                                            GEN_INT (INTVAL (XEXP (op0, 1))
5182                                                     & ~ INTVAL (op1))), op1);
5183
5184           if (GET_CODE (x) != AND)
5185             return x;
5186
5187           if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5188               || GET_RTX_CLASS (GET_CODE (x)) == '2')
5189             op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5190         }
5191
5192       /* Convert (A | B) & A to A.  */
5193       if (GET_CODE (op0) == IOR
5194           && (rtx_equal_p (XEXP (op0, 0), op1)
5195               || rtx_equal_p (XEXP (op0, 1), op1))
5196           && ! side_effects_p (XEXP (op0, 0))
5197           && ! side_effects_p (XEXP (op0, 1)))
5198         return op1;
5199
5200       /* In the following group of tests (and those in case IOR below),
5201          we start with some combination of logical operations and apply
5202          the distributive law followed by the inverse distributive law.
5203          Most of the time, this results in no change.  However, if some of
5204          the operands are the same or inverses of each other, simplifications
5205          will result.
5206
5207          For example, (and (ior A B) (not B)) can occur as the result of
5208          expanding a bit field assignment.  When we apply the distributive
5209          law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5210          which then simplifies to (and (A (not B))).
5211
5212          If we have (and (ior A B) C), apply the distributive law and then
5213          the inverse distributive law to see if things simplify.  */
5214
5215       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5216         {
5217           x = apply_distributive_law
5218             (gen_binary (GET_CODE (op0), mode,
5219                          gen_binary (AND, mode, XEXP (op0, 0), op1),
5220                          gen_binary (AND, mode, XEXP (op0, 1),
5221                                      copy_rtx (op1))));
5222           if (GET_CODE (x) != AND)
5223             return x;
5224         }
5225
5226       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5227         return apply_distributive_law
5228           (gen_binary (GET_CODE (op1), mode,
5229                        gen_binary (AND, mode, XEXP (op1, 0), op0),
5230                        gen_binary (AND, mode, XEXP (op1, 1),
5231                                    copy_rtx (op0))));
5232
5233       /* Similarly, taking advantage of the fact that
5234          (and (not A) (xor B C)) == (xor (ior A B) (ior A C))  */
5235
5236       if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5237         return apply_distributive_law
5238           (gen_binary (XOR, mode,
5239                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5240                        gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5241                                    XEXP (op1, 1))));
5242
5243       else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5244         return apply_distributive_law
5245           (gen_binary (XOR, mode,
5246                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5247                        gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5248       break;
5249
5250     case IOR:
5251       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
5252       if (GET_CODE (op1) == CONST_INT
5253           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5254           && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5255         return op1;
5256
5257       /* Convert (A & B) | A to A.  */
5258       if (GET_CODE (op0) == AND
5259           && (rtx_equal_p (XEXP (op0, 0), op1)
5260               || rtx_equal_p (XEXP (op0, 1), op1))
5261           && ! side_effects_p (XEXP (op0, 0))
5262           && ! side_effects_p (XEXP (op0, 1)))
5263         return op1;
5264
5265       /* If we have (ior (and A B) C), apply the distributive law and then
5266          the inverse distributive law to see if things simplify.  */
5267
5268       if (GET_CODE (op0) == AND)
5269         {
5270           x = apply_distributive_law
5271             (gen_binary (AND, mode,
5272                          gen_binary (IOR, mode, XEXP (op0, 0), op1),
5273                          gen_binary (IOR, mode, XEXP (op0, 1),
5274                                      copy_rtx (op1))));
5275
5276           if (GET_CODE (x) != IOR)
5277             return x;
5278         }
5279
5280       if (GET_CODE (op1) == AND)
5281         {
5282           x = apply_distributive_law
5283             (gen_binary (AND, mode,
5284                          gen_binary (IOR, mode, XEXP (op1, 0), op0),
5285                          gen_binary (IOR, mode, XEXP (op1, 1),
5286                                      copy_rtx (op0))));
5287
5288           if (GET_CODE (x) != IOR)
5289             return x;
5290         }
5291
5292       /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5293          mode size to (rotate A CX).  */
5294
5295       if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5296            || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5297           && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5298           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5299           && GET_CODE (XEXP (op1, 1)) == CONST_INT
5300           && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5301               == GET_MODE_BITSIZE (mode)))
5302         return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5303                                (GET_CODE (op0) == ASHIFT
5304                                 ? XEXP (op0, 1) : XEXP (op1, 1)));
5305
5306       /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5307          a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
5308          does not affect any of the bits in OP1, it can really be done
5309          as a PLUS and we can associate.  We do this by seeing if OP1
5310          can be safely shifted left C bits.  */
5311       if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5312           && GET_CODE (XEXP (op0, 0)) == PLUS
5313           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5314           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5315           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5316         {
5317           int count = INTVAL (XEXP (op0, 1));
5318           HOST_WIDE_INT mask = INTVAL (op1) << count;
5319
5320           if (mask >> count == INTVAL (op1)
5321               && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5322             {
5323               SUBST (XEXP (XEXP (op0, 0), 1),
5324                      GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5325               return op0;
5326             }
5327         }
5328       break;
5329
5330     case XOR:
5331       /* If we are XORing two things that have no bits in common,
5332          convert them into an IOR.  This helps to detect rotation encoded
5333          using those methods and possibly other simplifications.  */
5334
5335       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5336           && (nonzero_bits (op0, mode)
5337               & nonzero_bits (op1, mode)) == 0)
5338         return (gen_binary (IOR, mode, op0, op1));
5339
5340       /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5341          Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5342          (NOT y).  */
5343       {
5344         int num_negated = 0;
5345
5346         if (GET_CODE (op0) == NOT)
5347           num_negated++, op0 = XEXP (op0, 0);
5348         if (GET_CODE (op1) == NOT)
5349           num_negated++, op1 = XEXP (op1, 0);
5350
5351         if (num_negated == 2)
5352           {
5353             SUBST (XEXP (x, 0), op0);
5354             SUBST (XEXP (x, 1), op1);
5355           }
5356         else if (num_negated == 1)
5357           return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5358       }
5359
5360       /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
5361          correspond to a machine insn or result in further simplifications
5362          if B is a constant.  */
5363
5364       if (GET_CODE (op0) == AND
5365           && rtx_equal_p (XEXP (op0, 1), op1)
5366           && ! side_effects_p (op1))
5367         return gen_binary (AND, mode,
5368                            gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5369                            op1);
5370
5371       else if (GET_CODE (op0) == AND
5372                && rtx_equal_p (XEXP (op0, 0), op1)
5373                && ! side_effects_p (op1))
5374         return gen_binary (AND, mode,
5375                            gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5376                            op1);
5377
5378       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5379          comparison if STORE_FLAG_VALUE is 1.  */
5380       if (STORE_FLAG_VALUE == 1
5381           && op1 == const1_rtx
5382           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5383           && reversible_comparison_p (op0))
5384         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5385                                 mode, XEXP (op0, 0), XEXP (op0, 1));
5386
5387       /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5388          is (lt foo (const_int 0)), so we can perform the above
5389          simplification if STORE_FLAG_VALUE is 1.  */
5390
5391       if (STORE_FLAG_VALUE == 1
5392           && op1 == const1_rtx
5393           && GET_CODE (op0) == LSHIFTRT
5394           && GET_CODE (XEXP (op0, 1)) == CONST_INT
5395           && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5396         return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5397
5398       /* (xor (comparison foo bar) (const_int sign-bit))
5399          when STORE_FLAG_VALUE is the sign bit.  */
5400       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5401           && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5402               == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5403           && op1 == const_true_rtx
5404           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5405           && reversible_comparison_p (op0))
5406         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5407                                 mode, XEXP (op0, 0), XEXP (op0, 1));
5408
5409       break;
5410
5411     default:
5412       abort ();
5413     }
5414
5415   return x;
5416 }
5417 \f
5418 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5419    operations" because they can be replaced with two more basic operations.
5420    ZERO_EXTEND is also considered "compound" because it can be replaced with
5421    an AND operation, which is simpler, though only one operation.
5422
5423    The function expand_compound_operation is called with an rtx expression
5424    and will convert it to the appropriate shifts and AND operations,
5425    simplifying at each stage.
5426
5427    The function make_compound_operation is called to convert an expression
5428    consisting of shifts and ANDs into the equivalent compound expression.
5429    It is the inverse of this function, loosely speaking.  */
5430
5431 static rtx
5432 expand_compound_operation (x)
5433      rtx x;
5434 {
5435   int pos = 0, len;
5436   int unsignedp = 0;
5437   int modewidth;
5438   rtx tem;
5439
5440   switch (GET_CODE (x))
5441     {
5442     case ZERO_EXTEND:
5443       unsignedp = 1;
5444     case SIGN_EXTEND:
5445       /* We can't necessarily use a const_int for a multiword mode;
5446          it depends on implicitly extending the value.
5447          Since we don't know the right way to extend it,
5448          we can't tell whether the implicit way is right.
5449
5450          Even for a mode that is no wider than a const_int,
5451          we can't win, because we need to sign extend one of its bits through
5452          the rest of it, and we don't know which bit.  */
5453       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5454         return x;
5455
5456       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5457          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5458          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5459          reloaded. If not for that, MEM's would very rarely be safe.
5460
5461          Reject MODEs bigger than a word, because we might not be able
5462          to reference a two-register group starting with an arbitrary register
5463          (and currently gen_lowpart might crash for a SUBREG).  */
5464
5465       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5466         return x;
5467
5468       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5469       /* If the inner object has VOIDmode (the only way this can happen
5470          is if it is a ASM_OPERANDS), we can't do anything since we don't
5471          know how much masking to do.  */
5472       if (len == 0)
5473         return x;
5474
5475       break;
5476
5477     case ZERO_EXTRACT:
5478       unsignedp = 1;
5479     case SIGN_EXTRACT:
5480       /* If the operand is a CLOBBER, just return it.  */
5481       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5482         return XEXP (x, 0);
5483
5484       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5485           || GET_CODE (XEXP (x, 2)) != CONST_INT
5486           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5487         return x;
5488
5489       len = INTVAL (XEXP (x, 1));
5490       pos = INTVAL (XEXP (x, 2));
5491
5492       /* If this goes outside the object being extracted, replace the object
5493          with a (use (mem ...)) construct that only combine understands
5494          and is used only for this purpose.  */
5495       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5496         SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5497
5498       if (BITS_BIG_ENDIAN)
5499         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5500
5501       break;
5502
5503     default:
5504       return x;
5505     }
5506   /* Convert sign extension to zero extension, if we know that the high
5507      bit is not set, as this is easier to optimize.  It will be converted
5508      back to cheaper alternative in make_extraction.  */
5509   if (GET_CODE (x) == SIGN_EXTEND
5510       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5511           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5512                 & ~ (((unsigned HOST_WIDE_INT)
5513                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5514                      >> 1))
5515                == 0)))
5516     {
5517       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5518       return expand_compound_operation (temp);
5519     }
5520
5521   /* We can optimize some special cases of ZERO_EXTEND.  */
5522   if (GET_CODE (x) == ZERO_EXTEND)
5523     {
5524       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5525          know that the last value didn't have any inappropriate bits
5526          set.  */
5527       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5528           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5529           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5530           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5531               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5532         return XEXP (XEXP (x, 0), 0);
5533
5534       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5535       if (GET_CODE (XEXP (x, 0)) == SUBREG
5536           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5537           && subreg_lowpart_p (XEXP (x, 0))
5538           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5539           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5540               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5541         return SUBREG_REG (XEXP (x, 0));
5542
5543       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5544          is a comparison and STORE_FLAG_VALUE permits.  This is like
5545          the first case, but it works even when GET_MODE (x) is larger
5546          than HOST_WIDE_INT.  */
5547       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5548           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5549           && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5550           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5551               <= HOST_BITS_PER_WIDE_INT)
5552           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5553               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5554         return XEXP (XEXP (x, 0), 0);
5555
5556       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5557       if (GET_CODE (XEXP (x, 0)) == SUBREG
5558           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5559           && subreg_lowpart_p (XEXP (x, 0))
5560           && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5561           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5562               <= HOST_BITS_PER_WIDE_INT)
5563           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5564               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5565         return SUBREG_REG (XEXP (x, 0));
5566
5567     }
5568
5569   /* If we reach here, we want to return a pair of shifts.  The inner
5570      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5571      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5572      logical depending on the value of UNSIGNEDP.
5573
5574      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5575      converted into an AND of a shift.
5576
5577      We must check for the case where the left shift would have a negative
5578      count.  This can happen in a case like (x >> 31) & 255 on machines
5579      that can't shift by a constant.  On those machines, we would first
5580      combine the shift with the AND to produce a variable-position
5581      extraction.  Then the constant of 31 would be substituted in to produce
5582      a such a position.  */
5583
5584   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5585   if (modewidth >= pos - len)
5586     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5587                                 GET_MODE (x),
5588                                 simplify_shift_const (NULL_RTX, ASHIFT,
5589                                                       GET_MODE (x),
5590                                                       XEXP (x, 0),
5591                                                       modewidth - pos - len),
5592                                 modewidth - len);
5593
5594   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5595     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5596                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5597                                                         GET_MODE (x),
5598                                                         XEXP (x, 0), pos),
5599                                   ((HOST_WIDE_INT) 1 << len) - 1);
5600   else
5601     /* Any other cases we can't handle.  */
5602     return x;
5603
5604
5605   /* If we couldn't do this for some reason, return the original
5606      expression.  */
5607   if (GET_CODE (tem) == CLOBBER)
5608     return x;
5609
5610   return tem;
5611 }
5612 \f
5613 /* X is a SET which contains an assignment of one object into
5614    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5615    or certain SUBREGS). If possible, convert it into a series of
5616    logical operations.
5617
5618    We half-heartedly support variable positions, but do not at all
5619    support variable lengths.  */
5620
5621 static rtx
5622 expand_field_assignment (x)
5623      rtx x;
5624 {
5625   rtx inner;
5626   rtx pos;                      /* Always counts from low bit.  */
5627   int len;
5628   rtx mask;
5629   enum machine_mode compute_mode;
5630
5631   /* Loop until we find something we can't simplify.  */
5632   while (1)
5633     {
5634       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5635           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5636         {
5637           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5638           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5639           pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5640         }
5641       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5642                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5643         {
5644           inner = XEXP (SET_DEST (x), 0);
5645           len = INTVAL (XEXP (SET_DEST (x), 1));
5646           pos = XEXP (SET_DEST (x), 2);
5647
5648           /* If the position is constant and spans the width of INNER,
5649              surround INNER  with a USE to indicate this.  */
5650           if (GET_CODE (pos) == CONST_INT
5651               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5652             inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5653
5654           if (BITS_BIG_ENDIAN)
5655             {
5656               if (GET_CODE (pos) == CONST_INT)
5657                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5658                                - INTVAL (pos));
5659               else if (GET_CODE (pos) == MINUS
5660                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5661                        && (INTVAL (XEXP (pos, 1))
5662                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5663                 /* If position is ADJUST - X, new position is X.  */
5664                 pos = XEXP (pos, 0);
5665               else
5666                 pos = gen_binary (MINUS, GET_MODE (pos),
5667                                   GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5668                                            - len),
5669                                   pos);
5670             }
5671         }
5672
5673       /* A SUBREG between two modes that occupy the same numbers of words
5674          can be done by moving the SUBREG to the source.  */
5675       else if (GET_CODE (SET_DEST (x)) == SUBREG
5676                /* We need SUBREGs to compute nonzero_bits properly.  */
5677                && nonzero_sign_valid
5678                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5679                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5680                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5681                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5682         {
5683           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5684                            gen_lowpart_for_combine
5685                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5686                             SET_SRC (x)));
5687           continue;
5688         }
5689       else
5690         break;
5691
5692       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5693         inner = SUBREG_REG (inner);
5694
5695       compute_mode = GET_MODE (inner);
5696
5697       /* Don't attempt bitwise arithmetic on non-integral modes.  */
5698       if (! INTEGRAL_MODE_P (compute_mode))
5699         {
5700           enum machine_mode imode;
5701
5702           /* Something is probably seriously wrong if this matches.  */
5703           if (! FLOAT_MODE_P (compute_mode))
5704             break;
5705
5706           /* Try to find an integral mode to pun with.  */
5707           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5708           if (imode == BLKmode)
5709             break;
5710
5711           compute_mode = imode;
5712           inner = gen_lowpart_for_combine (imode, inner);
5713         }
5714
5715       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5716       if (len < HOST_BITS_PER_WIDE_INT)
5717         mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5718       else
5719         break;
5720
5721       /* Now compute the equivalent expression.  Make a copy of INNER
5722          for the SET_DEST in case it is a MEM into which we will substitute;
5723          we don't want shared RTL in that case.  */
5724       x = gen_rtx_SET
5725         (VOIDmode, copy_rtx (inner),
5726          gen_binary (IOR, compute_mode,
5727                      gen_binary (AND, compute_mode,
5728                                  gen_unary (NOT, compute_mode,
5729                                             compute_mode,
5730                                             gen_binary (ASHIFT,
5731                                                         compute_mode,
5732                                                         mask, pos)),
5733                                  inner),
5734                      gen_binary (ASHIFT, compute_mode,
5735                                  gen_binary (AND, compute_mode,
5736                                              gen_lowpart_for_combine
5737                                              (compute_mode, SET_SRC (x)),
5738                                              mask),
5739                                  pos)));
5740     }
5741
5742   return x;
5743 }
5744 \f
5745 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5746    it is an RTX that represents a variable starting position; otherwise,
5747    POS is the (constant) starting bit position (counted from the LSB).
5748
5749    INNER may be a USE.  This will occur when we started with a bitfield
5750    that went outside the boundary of the object in memory, which is
5751    allowed on most machines.  To isolate this case, we produce a USE
5752    whose mode is wide enough and surround the MEM with it.  The only
5753    code that understands the USE is this routine.  If it is not removed,
5754    it will cause the resulting insn not to match.
5755
5756    UNSIGNEDP is non-zero for an unsigned reference and zero for a
5757    signed reference.
5758
5759    IN_DEST is non-zero if this is a reference in the destination of a
5760    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If non-zero,
5761    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5762    be used.
5763
5764    IN_COMPARE is non-zero if we are in a COMPARE.  This means that a
5765    ZERO_EXTRACT should be built even for bits starting at bit 0.
5766
5767    MODE is the desired mode of the result (if IN_DEST == 0).
5768
5769    The result is an RTX for the extraction or NULL_RTX if the target
5770    can't handle it.  */
5771
5772 static rtx
5773 make_extraction (mode, inner, pos, pos_rtx, len,
5774                  unsignedp, in_dest, in_compare)
5775      enum machine_mode mode;
5776      rtx inner;
5777      int pos;
5778      rtx pos_rtx;
5779      int len;
5780      int unsignedp;
5781      int in_dest, in_compare;
5782 {
5783   /* This mode describes the size of the storage area
5784      to fetch the overall value from.  Within that, we
5785      ignore the POS lowest bits, etc.  */
5786   enum machine_mode is_mode = GET_MODE (inner);
5787   enum machine_mode inner_mode;
5788   enum machine_mode wanted_inner_mode = byte_mode;
5789   enum machine_mode wanted_inner_reg_mode = word_mode;
5790   enum machine_mode pos_mode = word_mode;
5791   enum machine_mode extraction_mode = word_mode;
5792   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5793   int spans_byte = 0;
5794   rtx new = 0;
5795   rtx orig_pos_rtx = pos_rtx;
5796   int orig_pos;
5797
5798   /* Get some information about INNER and get the innermost object.  */
5799   if (GET_CODE (inner) == USE)
5800     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5801     /* We don't need to adjust the position because we set up the USE
5802        to pretend that it was a full-word object.  */
5803     spans_byte = 1, inner = XEXP (inner, 0);
5804   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5805     {
5806       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5807          consider just the QI as the memory to extract from.
5808          The subreg adds or removes high bits; its mode is
5809          irrelevant to the meaning of this extraction,
5810          since POS and LEN count from the lsb.  */
5811       if (GET_CODE (SUBREG_REG (inner)) == MEM)
5812         is_mode = GET_MODE (SUBREG_REG (inner));
5813       inner = SUBREG_REG (inner);
5814     }
5815
5816   inner_mode = GET_MODE (inner);
5817
5818   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5819     pos = INTVAL (pos_rtx), pos_rtx = 0;
5820
5821   /* See if this can be done without an extraction.  We never can if the
5822      width of the field is not the same as that of some integer mode. For
5823      registers, we can only avoid the extraction if the position is at the
5824      low-order bit and this is either not in the destination or we have the
5825      appropriate STRICT_LOW_PART operation available.
5826
5827      For MEM, we can avoid an extract if the field starts on an appropriate
5828      boundary and we can change the mode of the memory reference.  However,
5829      we cannot directly access the MEM if we have a USE and the underlying
5830      MEM is not TMODE.  This combination means that MEM was being used in a
5831      context where bits outside its mode were being referenced; that is only
5832      valid in bit-field insns.  */
5833
5834   if (tmode != BLKmode
5835       && ! (spans_byte && inner_mode != tmode)
5836       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5837            && GET_CODE (inner) != MEM
5838            && (! in_dest
5839                || (GET_CODE (inner) == REG
5840                    && (movstrict_optab->handlers[(int) tmode].insn_code
5841                        != CODE_FOR_nothing))))
5842           || (GET_CODE (inner) == MEM && pos_rtx == 0
5843               && (pos
5844                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5845                      : BITS_PER_UNIT)) == 0
5846               /* We can't do this if we are widening INNER_MODE (it
5847                  may not be aligned, for one thing).  */
5848               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5849               && (inner_mode == tmode
5850                   || (! mode_dependent_address_p (XEXP (inner, 0))
5851                       && ! MEM_VOLATILE_P (inner))))))
5852     {
5853       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5854          field.  If the original and current mode are the same, we need not
5855          adjust the offset.  Otherwise, we do if bytes big endian.
5856
5857          If INNER is not a MEM, get a piece consisting of just the field
5858          of interest (in this case POS % BITS_PER_WORD must be 0).  */
5859
5860       if (GET_CODE (inner) == MEM)
5861         {
5862           int offset;
5863           /* POS counts from lsb, but make OFFSET count in memory order.  */
5864           if (BYTES_BIG_ENDIAN)
5865             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5866           else
5867             offset = pos / BITS_PER_UNIT;
5868
5869           new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5870           RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5871           MEM_COPY_ATTRIBUTES (new, inner);
5872         }
5873       else if (GET_CODE (inner) == REG)
5874         {
5875           /* We can't call gen_lowpart_for_combine here since we always want
5876              a SUBREG and it would sometimes return a new hard register.  */
5877           if (tmode != inner_mode)
5878             new = gen_rtx_SUBREG (tmode, inner,
5879                                   (WORDS_BIG_ENDIAN
5880                                    && (GET_MODE_SIZE (inner_mode)
5881                                        > UNITS_PER_WORD)
5882                                    ? (((GET_MODE_SIZE (inner_mode)
5883                                         - GET_MODE_SIZE (tmode))
5884                                        / UNITS_PER_WORD)
5885                                       - pos / BITS_PER_WORD)
5886                                    : pos / BITS_PER_WORD));
5887           else
5888             new = inner;
5889         }
5890       else
5891         new = force_to_mode (inner, tmode,
5892                              len >= HOST_BITS_PER_WIDE_INT
5893                              ? GET_MODE_MASK (tmode)
5894                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5895                              NULL_RTX, 0);
5896
5897       /* If this extraction is going into the destination of a SET,
5898          make a STRICT_LOW_PART unless we made a MEM.  */
5899
5900       if (in_dest)
5901         return (GET_CODE (new) == MEM ? new
5902                 : (GET_CODE (new) != SUBREG
5903                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
5904                    : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5905
5906       if (mode == tmode)
5907         return new;
5908
5909       /* If we know that no extraneous bits are set, and that the high
5910          bit is not set, convert the extraction to the cheaper of
5911          sign and zero extension, that are equivalent in these cases.  */
5912       if (flag_expensive_optimizations
5913           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5914               && ((nonzero_bits (new, tmode)
5915                    & ~ (((unsigned HOST_WIDE_INT)
5916                          GET_MODE_MASK (tmode))
5917                         >> 1))
5918                   == 0)))
5919         {
5920           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5921           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5922
5923           /* Prefer ZERO_EXTENSION, since it gives more information to
5924              backends.  */
5925           if (rtx_cost (temp, SET) < rtx_cost (temp1, SET))
5926             return temp;
5927           return temp1;
5928         }
5929
5930       /* Otherwise, sign- or zero-extend unless we already are in the
5931          proper mode.  */
5932
5933       return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5934                                mode, new));
5935     }
5936
5937   /* Unless this is a COMPARE or we have a funny memory reference,
5938      don't do anything with zero-extending field extracts starting at
5939      the low-order bit since they are simple AND operations.  */
5940   if (pos_rtx == 0 && pos == 0 && ! in_dest
5941       && ! in_compare && ! spans_byte && unsignedp)
5942     return 0;
5943
5944   /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5945      we would be spanning bytes or if the position is not a constant and the
5946      length is not 1.  In all other cases, we would only be going outside
5947      our object in cases when an original shift would have been
5948      undefined.  */
5949   if (! spans_byte && GET_CODE (inner) == MEM
5950       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5951           || (pos_rtx != 0 && len != 1)))
5952     return 0;
5953
5954   /* Get the mode to use should INNER not be a MEM, the mode for the position,
5955      and the mode for the result.  */
5956 #ifdef HAVE_insv
5957   if (in_dest)
5958     {
5959       wanted_inner_reg_mode
5960         = insn_data[(int) CODE_FOR_insv].operand[0].mode;
5961       if (wanted_inner_reg_mode == VOIDmode)
5962         wanted_inner_reg_mode = word_mode;
5963
5964       pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
5965       if (pos_mode == VOIDmode)
5966         pos_mode = word_mode;
5967
5968       extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
5969       if (extraction_mode == VOIDmode)
5970         extraction_mode = word_mode;
5971     }
5972 #endif
5973
5974 #ifdef HAVE_extzv
5975   if (! in_dest && unsignedp)
5976     {
5977       wanted_inner_reg_mode
5978         = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
5979       if (wanted_inner_reg_mode == VOIDmode)
5980         wanted_inner_reg_mode = word_mode;
5981
5982       pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
5983       if (pos_mode == VOIDmode)
5984         pos_mode = word_mode;
5985
5986       extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
5987       if (extraction_mode == VOIDmode)
5988         extraction_mode = word_mode;
5989     }
5990 #endif
5991
5992 #ifdef HAVE_extv
5993   if (! in_dest && ! unsignedp)
5994     {
5995       wanted_inner_reg_mode
5996         = insn_data[(int) CODE_FOR_extv].operand[1].mode;
5997       if (wanted_inner_reg_mode == VOIDmode)
5998         wanted_inner_reg_mode = word_mode;
5999
6000       pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6001       if (pos_mode == VOIDmode)
6002         pos_mode = word_mode;
6003
6004       extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6005       if (extraction_mode == VOIDmode)
6006         extraction_mode = word_mode;
6007     }
6008 #endif
6009
6010   /* Never narrow an object, since that might not be safe.  */
6011
6012   if (mode != VOIDmode
6013       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6014     extraction_mode = mode;
6015
6016   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6017       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6018     pos_mode = GET_MODE (pos_rtx);
6019
6020   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6021      if we have to change the mode of memory and cannot, the desired mode is
6022      EXTRACTION_MODE.  */
6023   if (GET_CODE (inner) != MEM)
6024     wanted_inner_mode = wanted_inner_reg_mode;
6025   else if (inner_mode != wanted_inner_mode
6026            && (mode_dependent_address_p (XEXP (inner, 0))
6027                || MEM_VOLATILE_P (inner)))
6028     wanted_inner_mode = extraction_mode;
6029
6030   orig_pos = pos;
6031
6032   if (BITS_BIG_ENDIAN)
6033     {
6034       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6035          BITS_BIG_ENDIAN style.  If position is constant, compute new
6036          position.  Otherwise, build subtraction.
6037          Note that POS is relative to the mode of the original argument.
6038          If it's a MEM we need to recompute POS relative to that.
6039          However, if we're extracting from (or inserting into) a register,
6040          we want to recompute POS relative to wanted_inner_mode.  */
6041       int width = (GET_CODE (inner) == MEM
6042                    ? GET_MODE_BITSIZE (is_mode)
6043                    : GET_MODE_BITSIZE (wanted_inner_mode));
6044
6045       if (pos_rtx == 0)
6046         pos = width - len - pos;
6047       else
6048         pos_rtx
6049           = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6050                              GEN_INT (width - len), pos_rtx);
6051       /* POS may be less than 0 now, but we check for that below.
6052          Note that it can only be less than 0 if GET_CODE (inner) != MEM.  */
6053     }
6054
6055   /* If INNER has a wider mode, make it smaller.  If this is a constant
6056      extract, try to adjust the byte to point to the byte containing
6057      the value.  */
6058   if (wanted_inner_mode != VOIDmode
6059       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6060       && ((GET_CODE (inner) == MEM
6061            && (inner_mode == wanted_inner_mode
6062                || (! mode_dependent_address_p (XEXP (inner, 0))
6063                    && ! MEM_VOLATILE_P (inner))))))
6064     {
6065       int offset = 0;
6066
6067       /* The computations below will be correct if the machine is big
6068          endian in both bits and bytes or little endian in bits and bytes.
6069          If it is mixed, we must adjust.  */
6070
6071       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6072          adjust OFFSET to compensate.  */
6073       if (BYTES_BIG_ENDIAN
6074           && ! spans_byte
6075           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6076         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6077
6078       /* If this is a constant position, we can move to the desired byte.  */
6079       if (pos_rtx == 0)
6080         {
6081           offset += pos / BITS_PER_UNIT;
6082           pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6083         }
6084
6085       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6086           && ! spans_byte
6087           && is_mode != wanted_inner_mode)
6088         offset = (GET_MODE_SIZE (is_mode)
6089                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6090
6091       if (offset != 0 || inner_mode != wanted_inner_mode)
6092         {
6093           rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6094                                     plus_constant (XEXP (inner, 0), offset));
6095           RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
6096           MEM_COPY_ATTRIBUTES (newmem, inner);
6097           inner = newmem;
6098         }
6099     }
6100
6101   /* If INNER is not memory, we can always get it into the proper mode.  If we
6102      are changing its mode, POS must be a constant and smaller than the size
6103      of the new mode.  */
6104   else if (GET_CODE (inner) != MEM)
6105     {
6106       if (GET_MODE (inner) != wanted_inner_mode
6107           && (pos_rtx != 0
6108               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6109         return 0;
6110
6111       inner = force_to_mode (inner, wanted_inner_mode,
6112                              pos_rtx
6113                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6114                              ? GET_MODE_MASK (wanted_inner_mode)
6115                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6116                                 << orig_pos),
6117                              NULL_RTX, 0);
6118     }
6119
6120   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6121      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6122   if (pos_rtx != 0
6123       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6124     {
6125       rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6126
6127       /* If we know that no extraneous bits are set, and that the high
6128          bit is not set, convert extraction to cheaper one - eighter
6129          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6130          cases.  */
6131       if (flag_expensive_optimizations
6132           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6133               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6134                    & ~ (((unsigned HOST_WIDE_INT)
6135                          GET_MODE_MASK (GET_MODE (pos_rtx)))
6136                         >> 1))
6137                   == 0)))
6138         {
6139           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6140
6141           /* Preffer ZERO_EXTENSION, since it gives more information to
6142              backends.  */
6143           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6144             temp = temp1;
6145         }
6146       pos_rtx = temp;
6147     }
6148   else if (pos_rtx != 0
6149            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6150     pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6151
6152   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6153      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6154      be a CONST_INT.  */
6155   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6156     pos_rtx = orig_pos_rtx;
6157
6158   else if (pos_rtx == 0)
6159     pos_rtx = GEN_INT (pos);
6160
6161   /* Make the required operation.  See if we can use existing rtx.  */
6162   new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6163                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6164   if (! in_dest)
6165     new = gen_lowpart_for_combine (mode, new);
6166
6167   return new;
6168 }
6169 \f
6170 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6171    with any other operations in X.  Return X without that shift if so.  */
6172
6173 static rtx
6174 extract_left_shift (x, count)
6175      rtx x;
6176      int count;
6177 {
6178   enum rtx_code code = GET_CODE (x);
6179   enum machine_mode mode = GET_MODE (x);
6180   rtx tem;
6181
6182   switch (code)
6183     {
6184     case ASHIFT:
6185       /* This is the shift itself.  If it is wide enough, we will return
6186          either the value being shifted if the shift count is equal to
6187          COUNT or a shift for the difference.  */
6188       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6189           && INTVAL (XEXP (x, 1)) >= count)
6190         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6191                                      INTVAL (XEXP (x, 1)) - count);
6192       break;
6193
6194     case NEG:  case NOT:
6195       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6196         return gen_unary (code, mode, mode, tem);
6197
6198       break;
6199
6200     case PLUS:  case IOR:  case XOR:  case AND:
6201       /* If we can safely shift this constant and we find the inner shift,
6202          make a new operation.  */
6203       if (GET_CODE (XEXP (x,1)) == CONST_INT
6204           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6205           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6206         return gen_binary (code, mode, tem,
6207                            GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6208
6209       break;
6210
6211     default:
6212       break;
6213     }
6214
6215   return 0;
6216 }
6217 \f
6218 /* Look at the expression rooted at X.  Look for expressions
6219    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6220    Form these expressions.
6221
6222    Return the new rtx, usually just X.
6223
6224    Also, for machines like the Vax that don't have logical shift insns,
6225    try to convert logical to arithmetic shift operations in cases where
6226    they are equivalent.  This undoes the canonicalizations to logical
6227    shifts done elsewhere.
6228
6229    We try, as much as possible, to re-use rtl expressions to save memory.
6230
6231    IN_CODE says what kind of expression we are processing.  Normally, it is
6232    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6233    being kludges), it is MEM.  When processing the arguments of a comparison
6234    or a COMPARE against zero, it is COMPARE.  */
6235
6236 static rtx
6237 make_compound_operation (x, in_code)
6238      rtx x;
6239      enum rtx_code in_code;
6240 {
6241   enum rtx_code code = GET_CODE (x);
6242   enum machine_mode mode = GET_MODE (x);
6243   int mode_width = GET_MODE_BITSIZE (mode);
6244   rtx rhs, lhs;
6245   enum rtx_code next_code;
6246   int i;
6247   rtx new = 0;
6248   rtx tem;
6249   const char *fmt;
6250
6251   /* Select the code to be used in recursive calls.  Once we are inside an
6252      address, we stay there.  If we have a comparison, set to COMPARE,
6253      but once inside, go back to our default of SET.  */
6254
6255   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6256                : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6257                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6258                : in_code == COMPARE ? SET : in_code);
6259
6260   /* Process depending on the code of this operation.  If NEW is set
6261      non-zero, it will be returned.  */
6262
6263   switch (code)
6264     {
6265     case ASHIFT:
6266       /* Convert shifts by constants into multiplications if inside
6267          an address.  */
6268       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6269           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6270           && INTVAL (XEXP (x, 1)) >= 0)
6271         {
6272           new = make_compound_operation (XEXP (x, 0), next_code);
6273           new = gen_rtx_combine (MULT, mode, new,
6274                                  GEN_INT ((HOST_WIDE_INT) 1
6275                                           << INTVAL (XEXP (x, 1))));
6276         }
6277       break;
6278
6279     case AND:
6280       /* If the second operand is not a constant, we can't do anything
6281          with it.  */
6282       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6283         break;
6284
6285       /* If the constant is a power of two minus one and the first operand
6286          is a logical right shift, make an extraction.  */
6287       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6288           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6289         {
6290           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6291           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6292                                  0, in_code == COMPARE);
6293         }
6294
6295       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6296       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6297                && subreg_lowpart_p (XEXP (x, 0))
6298                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6299                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6300         {
6301           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6302                                          next_code);
6303           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6304                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6305                                  0, in_code == COMPARE);
6306         }
6307       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6308       else if ((GET_CODE (XEXP (x, 0)) == XOR
6309                 || GET_CODE (XEXP (x, 0)) == IOR)
6310                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6311                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6312                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6313         {
6314           /* Apply the distributive law, and then try to make extractions.  */
6315           new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6316                                  gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6317                                               XEXP (x, 1)),
6318                                  gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6319                                               XEXP (x, 1)));
6320           new = make_compound_operation (new, in_code);
6321         }
6322
6323       /* If we are have (and (rotate X C) M) and C is larger than the number
6324          of bits in M, this is an extraction.  */
6325
6326       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6327                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6328                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6329                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6330         {
6331           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6332           new = make_extraction (mode, new,
6333                                  (GET_MODE_BITSIZE (mode)
6334                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6335                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6336         }
6337
6338       /* On machines without logical shifts, if the operand of the AND is
6339          a logical shift and our mask turns off all the propagated sign
6340          bits, we can replace the logical shift with an arithmetic shift.  */
6341       else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6342                && (lshr_optab->handlers[(int) mode].insn_code
6343                    == CODE_FOR_nothing)
6344                && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6345                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6346                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6347                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6348                && mode_width <= HOST_BITS_PER_WIDE_INT)
6349         {
6350           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6351
6352           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6353           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6354             SUBST (XEXP (x, 0),
6355                    gen_rtx_combine (ASHIFTRT, mode,
6356                                     make_compound_operation (XEXP (XEXP (x, 0), 0),
6357                                                              next_code),
6358                                     XEXP (XEXP (x, 0), 1)));
6359         }
6360
6361       /* If the constant is one less than a power of two, this might be
6362          representable by an extraction even if no shift is present.
6363          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6364          we are in a COMPARE.  */
6365       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6366         new = make_extraction (mode,
6367                                make_compound_operation (XEXP (x, 0),
6368                                                         next_code),
6369                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6370
6371       /* If we are in a comparison and this is an AND with a power of two,
6372          convert this into the appropriate bit extract.  */
6373       else if (in_code == COMPARE
6374                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6375         new = make_extraction (mode,
6376                                make_compound_operation (XEXP (x, 0),
6377                                                         next_code),
6378                                i, NULL_RTX, 1, 1, 0, 1);
6379
6380       break;
6381
6382     case LSHIFTRT:
6383       /* If the sign bit is known to be zero, replace this with an
6384          arithmetic shift.  */
6385       if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6386           && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6387           && mode_width <= HOST_BITS_PER_WIDE_INT
6388           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6389         {
6390           new = gen_rtx_combine (ASHIFTRT, mode,
6391                                  make_compound_operation (XEXP (x, 0),
6392                                                           next_code),
6393                                  XEXP (x, 1));
6394           break;
6395         }
6396
6397       /* ... fall through ...  */
6398
6399     case ASHIFTRT:
6400       lhs = XEXP (x, 0);
6401       rhs = XEXP (x, 1);
6402
6403       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6404          this is a SIGN_EXTRACT.  */
6405       if (GET_CODE (rhs) == CONST_INT
6406           && GET_CODE (lhs) == ASHIFT
6407           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6408           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6409         {
6410           new = make_compound_operation (XEXP (lhs, 0), next_code);
6411           new = make_extraction (mode, new,
6412                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6413                                  NULL_RTX, mode_width - INTVAL (rhs),
6414                                  code == LSHIFTRT, 0, in_code == COMPARE);
6415         }
6416
6417       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6418          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6419          also do this for some cases of SIGN_EXTRACT, but it doesn't
6420          seem worth the effort; the case checked for occurs on Alpha.  */
6421
6422       if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6423           && ! (GET_CODE (lhs) == SUBREG
6424                 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6425           && GET_CODE (rhs) == CONST_INT
6426           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6427           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6428         new = make_extraction (mode, make_compound_operation (new, next_code),
6429                                0, NULL_RTX, mode_width - INTVAL (rhs),
6430                                code == LSHIFTRT, 0, in_code == COMPARE);
6431
6432       break;
6433
6434     case SUBREG:
6435       /* Call ourselves recursively on the inner expression.  If we are
6436          narrowing the object and it has a different RTL code from
6437          what it originally did, do this SUBREG as a force_to_mode.  */
6438
6439       tem = make_compound_operation (SUBREG_REG (x), in_code);
6440       if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6441           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6442           && subreg_lowpart_p (x))
6443         {
6444           rtx newer = force_to_mode (tem, mode,
6445                                      GET_MODE_MASK (mode), NULL_RTX, 0);
6446
6447           /* If we have something other than a SUBREG, we might have
6448              done an expansion, so rerun outselves.  */
6449           if (GET_CODE (newer) != SUBREG)
6450             newer = make_compound_operation (newer, in_code);
6451
6452           return newer;
6453         }
6454
6455       /* If this is a paradoxical subreg, and the new code is a sign or
6456          zero extension, omit the subreg and widen the extension.  If it
6457          is a regular subreg, we can still get rid of the subreg by not
6458          widening so much, or in fact removing the extension entirely.  */
6459       if ((GET_CODE (tem) == SIGN_EXTEND
6460            || GET_CODE (tem) == ZERO_EXTEND)
6461           && subreg_lowpart_p (x))
6462         {
6463           if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6464               || (GET_MODE_SIZE (mode) >
6465                   GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6466             tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6467           else
6468             tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6469           return tem;
6470         }
6471       break;
6472
6473     default:
6474       break;
6475     }
6476
6477   if (new)
6478     {
6479       x = gen_lowpart_for_combine (mode, new);
6480       code = GET_CODE (x);
6481     }
6482
6483   /* Now recursively process each operand of this operation.  */
6484   fmt = GET_RTX_FORMAT (code);
6485   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6486     if (fmt[i] == 'e')
6487       {
6488         new = make_compound_operation (XEXP (x, i), next_code);
6489         SUBST (XEXP (x, i), new);
6490       }
6491
6492   return x;
6493 }
6494 \f
6495 /* Given M see if it is a value that would select a field of bits
6496     within an item, but not the entire word.  Return -1 if not.
6497     Otherwise, return the starting position of the field, where 0 is the
6498     low-order bit.
6499
6500    *PLEN is set to the length of the field.  */
6501
6502 static int
6503 get_pos_from_mask (m, plen)
6504      unsigned HOST_WIDE_INT m;
6505      int *plen;
6506 {
6507   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6508   int pos = exact_log2 (m & - m);
6509
6510   if (pos < 0)
6511     return -1;
6512
6513   /* Now shift off the low-order zero bits and see if we have a power of
6514      two minus 1.  */
6515   *plen = exact_log2 ((m >> pos) + 1);
6516
6517   if (*plen <= 0)
6518     return -1;
6519
6520   return pos;
6521 }
6522 \f
6523 /* See if X can be simplified knowing that we will only refer to it in
6524    MODE and will only refer to those bits that are nonzero in MASK.
6525    If other bits are being computed or if masking operations are done
6526    that select a superset of the bits in MASK, they can sometimes be
6527    ignored.
6528
6529    Return a possibly simplified expression, but always convert X to
6530    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6531
6532    Also, if REG is non-zero and X is a register equal in value to REG,
6533    replace X with REG.
6534
6535    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6536    are all off in X.  This is used when X will be complemented, by either
6537    NOT, NEG, or XOR.  */
6538
6539 static rtx
6540 force_to_mode (x, mode, mask, reg, just_select)
6541      rtx x;
6542      enum machine_mode mode;
6543      unsigned HOST_WIDE_INT mask;
6544      rtx reg;
6545      int just_select;
6546 {
6547   enum rtx_code code = GET_CODE (x);
6548   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6549   enum machine_mode op_mode;
6550   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6551   rtx op0, op1, temp;
6552
6553   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6554      code below will do the wrong thing since the mode of such an
6555      expression is VOIDmode.
6556
6557      Also do nothing if X is a CLOBBER; this can happen if X was
6558      the return value from a call to gen_lowpart_for_combine.  */
6559   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6560     return x;
6561
6562   /* We want to perform the operation is its present mode unless we know
6563      that the operation is valid in MODE, in which case we do the operation
6564      in MODE.  */
6565   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6566               && code_to_optab[(int) code] != 0
6567               && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6568                   != CODE_FOR_nothing))
6569              ? mode : GET_MODE (x));
6570
6571   /* It is not valid to do a right-shift in a narrower mode
6572      than the one it came in with.  */
6573   if ((code == LSHIFTRT || code == ASHIFTRT)
6574       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6575     op_mode = GET_MODE (x);
6576
6577   /* Truncate MASK to fit OP_MODE.  */
6578   if (op_mode)
6579     mask &= GET_MODE_MASK (op_mode);
6580
6581   /* When we have an arithmetic operation, or a shift whose count we
6582      do not know, we need to assume that all bit the up to the highest-order
6583      bit in MASK will be needed.  This is how we form such a mask.  */
6584   if (op_mode)
6585     fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6586                    ? GET_MODE_MASK (op_mode)
6587                    : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6588                       - 1));
6589   else
6590     fuller_mask = ~ (HOST_WIDE_INT) 0;
6591
6592   /* Determine what bits of X are guaranteed to be (non)zero.  */
6593   nonzero = nonzero_bits (x, mode);
6594
6595   /* If none of the bits in X are needed, return a zero.  */
6596   if (! just_select && (nonzero & mask) == 0)
6597     return const0_rtx;
6598
6599   /* If X is a CONST_INT, return a new one.  Do this here since the
6600      test below will fail.  */
6601   if (GET_CODE (x) == CONST_INT)
6602     {
6603       HOST_WIDE_INT cval = INTVAL (x) & mask;
6604       int width = GET_MODE_BITSIZE (mode);
6605
6606       /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6607          number, sign extend it.  */
6608       if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6609           && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6610         cval |= (HOST_WIDE_INT) -1 << width;
6611
6612       return GEN_INT (cval);
6613     }
6614
6615   /* If X is narrower than MODE and we want all the bits in X's mode, just
6616      get X in the proper mode.  */
6617   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6618       && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6619     return gen_lowpart_for_combine (mode, x);
6620
6621   /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6622      MASK are already known to be zero in X, we need not do anything.  */
6623   if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6624     return x;
6625
6626   switch (code)
6627     {
6628     case CLOBBER:
6629       /* If X is a (clobber (const_int)), return it since we know we are
6630          generating something that won't match.  */
6631       return x;
6632
6633     case USE:
6634       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6635          spanned the boundary of the MEM.  If we are now masking so it is
6636          within that boundary, we don't need the USE any more.  */
6637       if (! BITS_BIG_ENDIAN
6638           && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6639         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6640       break;
6641
6642     case SIGN_EXTEND:
6643     case ZERO_EXTEND:
6644     case ZERO_EXTRACT:
6645     case SIGN_EXTRACT:
6646       x = expand_compound_operation (x);
6647       if (GET_CODE (x) != code)
6648         return force_to_mode (x, mode, mask, reg, next_select);
6649       break;
6650
6651     case REG:
6652       if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6653                        || rtx_equal_p (reg, get_last_value (x))))
6654         x = reg;
6655       break;
6656
6657     case SUBREG:
6658       if (subreg_lowpart_p (x)
6659           /* We can ignore the effect of this SUBREG if it narrows the mode or
6660              if the constant masks to zero all the bits the mode doesn't
6661              have.  */
6662           && ((GET_MODE_SIZE (GET_MODE (x))
6663                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6664               || (0 == (mask
6665                         & GET_MODE_MASK (GET_MODE (x))
6666                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6667         return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6668       break;
6669
6670     case AND:
6671       /* If this is an AND with a constant, convert it into an AND
6672          whose constant is the AND of that constant with MASK.  If it
6673          remains an AND of MASK, delete it since it is redundant.  */
6674
6675       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6676         {
6677           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6678                                       mask & INTVAL (XEXP (x, 1)));
6679
6680           /* If X is still an AND, see if it is an AND with a mask that
6681              is just some low-order bits.  If so, and it is MASK, we don't
6682              need it.  */
6683
6684           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6685               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6686             x = XEXP (x, 0);
6687
6688           /* If it remains an AND, try making another AND with the bits
6689              in the mode mask that aren't in MASK turned on.  If the
6690              constant in the AND is wide enough, this might make a
6691              cheaper constant.  */
6692
6693           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6694               && GET_MODE_MASK (GET_MODE (x)) != mask
6695               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6696             {
6697               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6698                                     | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6699               int width = GET_MODE_BITSIZE (GET_MODE (x));
6700               rtx y;
6701
6702               /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6703                  number, sign extend it.  */
6704               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6705                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6706                 cval |= (HOST_WIDE_INT) -1 << width;
6707
6708               y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6709               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6710                 x = y;
6711             }
6712
6713           break;
6714         }
6715
6716       goto binop;
6717
6718     case PLUS:
6719       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6720          low-order bits (as in an alignment operation) and FOO is already
6721          aligned to that boundary, mask C1 to that boundary as well.
6722          This may eliminate that PLUS and, later, the AND.  */
6723
6724       {
6725         int width = GET_MODE_BITSIZE (mode);
6726         unsigned HOST_WIDE_INT smask = mask;
6727
6728         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6729            number, sign extend it.  */
6730
6731         if (width < HOST_BITS_PER_WIDE_INT
6732             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6733           smask |= (HOST_WIDE_INT) -1 << width;
6734
6735         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6736             && exact_log2 (- smask) >= 0)
6737           {
6738 #ifdef STACK_BIAS
6739             if (STACK_BIAS
6740                 && (XEXP (x, 0) == stack_pointer_rtx
6741                     || XEXP (x, 0) == frame_pointer_rtx))
6742               {
6743                 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6744                 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6745
6746                 sp_mask &= ~ (sp_alignment - 1);
6747                 if ((sp_mask & ~ smask) == 0
6748                     && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6749                   return force_to_mode (plus_constant (XEXP (x, 0),
6750                                                        ((INTVAL (XEXP (x, 1)) -
6751                                                          STACK_BIAS) & smask)
6752                                                        + STACK_BIAS),
6753                                         mode, smask, reg, next_select);
6754               }
6755 #endif
6756             if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6757                 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6758               return force_to_mode (plus_constant (XEXP (x, 0),
6759                                                    (INTVAL (XEXP (x, 1))
6760                                                     & smask)),
6761                                     mode, smask, reg, next_select);
6762           }
6763       }
6764
6765       /* ... fall through ...  */
6766
6767     case MINUS:
6768     case MULT:
6769       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6770          most significant bit in MASK since carries from those bits will
6771          affect the bits we are interested in.  */
6772       mask = fuller_mask;
6773       goto binop;
6774
6775     case IOR:
6776     case XOR:
6777       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6778          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6779          operation which may be a bitfield extraction.  Ensure that the
6780          constant we form is not wider than the mode of X.  */
6781
6782       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6783           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6784           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6785           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6786           && GET_CODE (XEXP (x, 1)) == CONST_INT
6787           && ((INTVAL (XEXP (XEXP (x, 0), 1))
6788                + floor_log2 (INTVAL (XEXP (x, 1))))
6789               < GET_MODE_BITSIZE (GET_MODE (x)))
6790           && (INTVAL (XEXP (x, 1))
6791               & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6792         {
6793           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6794                               << INTVAL (XEXP (XEXP (x, 0), 1)));
6795           temp = gen_binary (GET_CODE (x), GET_MODE (x),
6796                              XEXP (XEXP (x, 0), 0), temp);
6797           x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6798                           XEXP (XEXP (x, 0), 1));
6799           return force_to_mode (x, mode, mask, reg, next_select);
6800         }
6801
6802     binop:
6803       /* For most binary operations, just propagate into the operation and
6804          change the mode if we have an operation of that mode.   */
6805
6806       op0 = gen_lowpart_for_combine (op_mode,
6807                                      force_to_mode (XEXP (x, 0), mode, mask,
6808                                                     reg, next_select));
6809       op1 = gen_lowpart_for_combine (op_mode,
6810                                      force_to_mode (XEXP (x, 1), mode, mask,
6811                                                     reg, next_select));
6812
6813       /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6814          MASK since OP1 might have been sign-extended but we never want
6815          to turn on extra bits, since combine might have previously relied
6816          on them being off.  */
6817       if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6818           && (INTVAL (op1) & mask) != 0)
6819         op1 = GEN_INT (INTVAL (op1) & mask);
6820
6821       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6822         x = gen_binary (code, op_mode, op0, op1);
6823       break;
6824
6825     case ASHIFT:
6826       /* For left shifts, do the same, but just for the first operand.
6827          However, we cannot do anything with shifts where we cannot
6828          guarantee that the counts are smaller than the size of the mode
6829          because such a count will have a different meaning in a
6830          wider mode.  */
6831
6832       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6833              && INTVAL (XEXP (x, 1)) >= 0
6834              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6835           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6836                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6837                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6838         break;
6839
6840       /* If the shift count is a constant and we can do arithmetic in
6841          the mode of the shift, refine which bits we need.  Otherwise, use the
6842          conservative form of the mask.  */
6843       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6844           && INTVAL (XEXP (x, 1)) >= 0
6845           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6846           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6847         mask >>= INTVAL (XEXP (x, 1));
6848       else
6849         mask = fuller_mask;
6850
6851       op0 = gen_lowpart_for_combine (op_mode,
6852                                      force_to_mode (XEXP (x, 0), op_mode,
6853                                                     mask, reg, next_select));
6854
6855       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6856         x =  gen_binary (code, op_mode, op0, XEXP (x, 1));
6857       break;
6858
6859     case LSHIFTRT:
6860       /* Here we can only do something if the shift count is a constant,
6861          this shift constant is valid for the host, and we can do arithmetic
6862          in OP_MODE.  */
6863
6864       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6865           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6866           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6867         {
6868           rtx inner = XEXP (x, 0);
6869           unsigned HOST_WIDE_INT inner_mask;
6870
6871           /* Select the mask of the bits we need for the shift operand.  */
6872           inner_mask = mask << INTVAL (XEXP (x, 1));
6873
6874           /* We can only change the mode of the shift if we can do arithmetic
6875              in the mode of the shift and INNER_MASK is no wider than the
6876              width of OP_MODE.  */
6877           if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6878               || (inner_mask & ~ GET_MODE_MASK (op_mode)) != 0)
6879             op_mode = GET_MODE (x);
6880
6881           inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6882
6883           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6884             x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6885         }
6886
6887       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6888          shift and AND produces only copies of the sign bit (C2 is one less
6889          than a power of two), we can do this with just a shift.  */
6890
6891       if (GET_CODE (x) == LSHIFTRT
6892           && GET_CODE (XEXP (x, 1)) == CONST_INT
6893           && ((INTVAL (XEXP (x, 1))
6894                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6895               >= GET_MODE_BITSIZE (GET_MODE (x)))
6896           && exact_log2 (mask + 1) >= 0
6897           && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6898               >= exact_log2 (mask + 1)))
6899         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6900                         GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6901                                  - exact_log2 (mask + 1)));
6902
6903       goto shiftrt;
6904
6905     case ASHIFTRT:
6906       /* If we are just looking for the sign bit, we don't need this shift at
6907          all, even if it has a variable count.  */
6908       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6909           && (mask == ((unsigned HOST_WIDE_INT) 1
6910                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6911         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6912
6913       /* If this is a shift by a constant, get a mask that contains those bits
6914          that are not copies of the sign bit.  We then have two cases:  If
6915          MASK only includes those bits, this can be a logical shift, which may
6916          allow simplifications.  If MASK is a single-bit field not within
6917          those bits, we are requesting a copy of the sign bit and hence can
6918          shift the sign bit to the appropriate location.  */
6919
6920       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6921           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6922         {
6923           int i = -1;
6924
6925           /* If the considered data is wider then HOST_WIDE_INT, we can't
6926              represent a mask for all its bits in a single scalar.
6927              But we only care about the lower bits, so calculate these.  */
6928
6929           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6930             {
6931               nonzero = ~ (HOST_WIDE_INT) 0;
6932
6933               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6934                  is the number of bits a full-width mask would have set.
6935                  We need only shift if these are fewer than nonzero can
6936                  hold.  If not, we must keep all bits set in nonzero.  */
6937
6938               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6939                   < HOST_BITS_PER_WIDE_INT)
6940                 nonzero >>= INTVAL (XEXP (x, 1))
6941                             + HOST_BITS_PER_WIDE_INT
6942                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
6943             }
6944           else
6945             {
6946               nonzero = GET_MODE_MASK (GET_MODE (x));
6947               nonzero >>= INTVAL (XEXP (x, 1));
6948             }
6949
6950           if ((mask & ~ nonzero) == 0
6951               || (i = exact_log2 (mask)) >= 0)
6952             {
6953               x = simplify_shift_const
6954                 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6955                  i < 0 ? INTVAL (XEXP (x, 1))
6956                  : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6957
6958               if (GET_CODE (x) != ASHIFTRT)
6959                 return force_to_mode (x, mode, mask, reg, next_select);
6960             }
6961         }
6962
6963       /* If MASK is 1, convert this to a LSHIFTRT.  This can be done
6964          even if the shift count isn't a constant.  */
6965       if (mask == 1)
6966         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6967
6968     shiftrt:
6969
6970       /* If this is a zero- or sign-extension operation that just affects bits
6971          we don't care about, remove it.  Be sure the call above returned
6972          something that is still a shift.  */
6973
6974       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6975           && GET_CODE (XEXP (x, 1)) == CONST_INT
6976           && INTVAL (XEXP (x, 1)) >= 0
6977           && (INTVAL (XEXP (x, 1))
6978               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6979           && GET_CODE (XEXP (x, 0)) == ASHIFT
6980           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6981           && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6982         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6983                               reg, next_select);
6984
6985       break;
6986
6987     case ROTATE:
6988     case ROTATERT:
6989       /* If the shift count is constant and we can do computations
6990          in the mode of X, compute where the bits we care about are.
6991          Otherwise, we can't do anything.  Don't change the mode of
6992          the shift or propagate MODE into the shift, though.  */
6993       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6994           && INTVAL (XEXP (x, 1)) >= 0)
6995         {
6996           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6997                                             GET_MODE (x), GEN_INT (mask),
6998                                             XEXP (x, 1));
6999           if (temp && GET_CODE(temp) == CONST_INT)
7000             SUBST (XEXP (x, 0),
7001                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7002                                   INTVAL (temp), reg, next_select));
7003         }
7004       break;
7005
7006     case NEG:
7007       /* If we just want the low-order bit, the NEG isn't needed since it
7008          won't change the low-order bit.    */
7009       if (mask == 1)
7010         return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7011
7012       /* We need any bits less significant than the most significant bit in
7013          MASK since carries from those bits will affect the bits we are
7014          interested in.  */
7015       mask = fuller_mask;
7016       goto unop;
7017
7018     case NOT:
7019       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7020          same as the XOR case above.  Ensure that the constant we form is not
7021          wider than the mode of X.  */
7022
7023       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7024           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7025           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7026           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7027               < GET_MODE_BITSIZE (GET_MODE (x)))
7028           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7029         {
7030           temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7031           temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7032           x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7033
7034           return force_to_mode (x, mode, mask, reg, next_select);
7035         }
7036
7037       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7038          use the full mask inside the NOT.  */
7039       mask = fuller_mask;
7040
7041     unop:
7042       op0 = gen_lowpart_for_combine (op_mode,
7043                                      force_to_mode (XEXP (x, 0), mode, mask,
7044                                                     reg, next_select));
7045       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7046         x = gen_unary (code, op_mode, op_mode, op0);
7047       break;
7048
7049     case NE:
7050       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7051          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7052          which is equal to STORE_FLAG_VALUE.  */
7053       if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7054           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7055           && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7056         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7057
7058       break;
7059
7060     case IF_THEN_ELSE:
7061       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7062          written in a narrower mode.  We play it safe and do not do so.  */
7063
7064       SUBST (XEXP (x, 1),
7065              gen_lowpart_for_combine (GET_MODE (x),
7066                                       force_to_mode (XEXP (x, 1), mode,
7067                                                      mask, reg, next_select)));
7068       SUBST (XEXP (x, 2),
7069              gen_lowpart_for_combine (GET_MODE (x),
7070                                       force_to_mode (XEXP (x, 2), mode,
7071                                                      mask, reg,next_select)));
7072       break;
7073
7074     default:
7075       break;
7076     }
7077
7078   /* Ensure we return a value of the proper mode.  */
7079   return gen_lowpart_for_combine (mode, x);
7080 }
7081 \f
7082 /* Return nonzero if X is an expression that has one of two values depending on
7083    whether some other value is zero or nonzero.  In that case, we return the
7084    value that is being tested, *PTRUE is set to the value if the rtx being
7085    returned has a nonzero value, and *PFALSE is set to the other alternative.
7086
7087    If we return zero, we set *PTRUE and *PFALSE to X.  */
7088
7089 static rtx
7090 if_then_else_cond (x, ptrue, pfalse)
7091      rtx x;
7092      rtx *ptrue, *pfalse;
7093 {
7094   enum machine_mode mode = GET_MODE (x);
7095   enum rtx_code code = GET_CODE (x);
7096   int size = GET_MODE_BITSIZE (mode);
7097   rtx cond0, cond1, true0, true1, false0, false1;
7098   unsigned HOST_WIDE_INT nz;
7099
7100   /* If we are comparing a value against zero, we are done.  */
7101   if ((code == NE || code == EQ)
7102       && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7103     {
7104       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7105       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7106       return XEXP (x, 0);
7107     }
7108
7109   /* If this is a unary operation whose operand has one of two values, apply
7110      our opcode to compute those values.  */
7111   else if (GET_RTX_CLASS (code) == '1'
7112            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7113     {
7114       *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7115       *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7116       return cond0;
7117     }
7118
7119   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7120      make can't possibly match and would suppress other optimizations.  */
7121   else if (code == COMPARE)
7122     ;
7123
7124   /* If this is a binary operation, see if either side has only one of two
7125      values.  If either one does or if both do and they are conditional on
7126      the same value, compute the new true and false values.  */
7127   else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7128            || GET_RTX_CLASS (code) == '<')
7129     {
7130       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7131       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7132
7133       if ((cond0 != 0 || cond1 != 0)
7134           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7135         {
7136           /* If if_then_else_cond returned zero, then true/false are the
7137              same rtl.  We must copy one of them to prevent invalid rtl
7138              sharing.  */
7139           if (cond0 == 0)
7140             true0 = copy_rtx (true0);
7141           else if (cond1 == 0)
7142             true1 = copy_rtx (true1);
7143
7144           *ptrue = gen_binary (code, mode, true0, true1);
7145           *pfalse = gen_binary (code, mode, false0, false1);
7146           return cond0 ? cond0 : cond1;
7147         }
7148
7149       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7150          operands is zero when the other is non-zero, and vice-versa,
7151          and STORE_FLAG_VALUE is 1 or -1.  */
7152
7153       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7154           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7155            || code == UMAX)
7156           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7157         {
7158           rtx op0 = XEXP (XEXP (x, 0), 1);
7159           rtx op1 = XEXP (XEXP (x, 1), 1);
7160
7161           cond0 = XEXP (XEXP (x, 0), 0);
7162           cond1 = XEXP (XEXP (x, 1), 0);
7163
7164           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7165               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7166               && reversible_comparison_p (cond1)
7167               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7168                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7169                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7170                   || ((swap_condition (GET_CODE (cond0))
7171                        == reverse_condition (GET_CODE (cond1)))
7172                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7173                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7174               && ! side_effects_p (x))
7175             {
7176               *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7177               *pfalse = gen_binary (MULT, mode,
7178                                     (code == MINUS
7179                                      ? gen_unary (NEG, mode, mode, op1) : op1),
7180                                     const_true_rtx);
7181               return cond0;
7182             }
7183         }
7184
7185       /* Similarly for MULT, AND and UMIN, execpt that for these the result
7186          is always zero.  */
7187       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7188           && (code == MULT || code == AND || code == UMIN)
7189           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7190         {
7191           cond0 = XEXP (XEXP (x, 0), 0);
7192           cond1 = XEXP (XEXP (x, 1), 0);
7193
7194           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7195               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7196               && reversible_comparison_p (cond1)
7197               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7198                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7199                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7200                   || ((swap_condition (GET_CODE (cond0))
7201                        == reverse_condition (GET_CODE (cond1)))
7202                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7203                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7204               && ! side_effects_p (x))
7205             {
7206               *ptrue = *pfalse = const0_rtx;
7207               return cond0;
7208             }
7209         }
7210     }
7211
7212   else if (code == IF_THEN_ELSE)
7213     {
7214       /* If we have IF_THEN_ELSE already, extract the condition and
7215          canonicalize it if it is NE or EQ.  */
7216       cond0 = XEXP (x, 0);
7217       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7218       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7219         return XEXP (cond0, 0);
7220       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7221         {
7222           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7223           return XEXP (cond0, 0);
7224         }
7225       else
7226         return cond0;
7227     }
7228
7229   /* If X is a normal SUBREG with both inner and outer modes integral,
7230      we can narrow both the true and false values of the inner expression,
7231      if there is a condition.  */
7232   else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7233            && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7234            && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7235            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7236                                                &true0, &false0)))
7237     {
7238       if ((GET_CODE (SUBREG_REG (x)) == REG
7239            || GET_CODE (SUBREG_REG (x)) == MEM
7240            || CONSTANT_P (SUBREG_REG (x)))
7241           && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7242           && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7243         {
7244           true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7245           false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7246         }
7247       *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7248       *pfalse
7249         = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7250
7251       return cond0;
7252     }
7253
7254   /* If X is a constant, this isn't special and will cause confusions
7255      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7256   else if (CONSTANT_P (x)
7257            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7258     ;
7259
7260   /* If X is known to be either 0 or -1, those are the true and
7261      false values when testing X.  */
7262   else if (num_sign_bit_copies (x, mode) == size)
7263     {
7264       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7265       return x;
7266     }
7267
7268   /* Likewise for 0 or a single bit.  */
7269   else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7270     {
7271       *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7272       return x;
7273     }
7274
7275   /* Otherwise fail; show no condition with true and false values the same.  */
7276   *ptrue = *pfalse = x;
7277   return 0;
7278 }
7279 \f
7280 /* Return the value of expression X given the fact that condition COND
7281    is known to be true when applied to REG as its first operand and VAL
7282    as its second.  X is known to not be shared and so can be modified in
7283    place.
7284
7285    We only handle the simplest cases, and specifically those cases that
7286    arise with IF_THEN_ELSE expressions.  */
7287
7288 static rtx
7289 known_cond (x, cond, reg, val)
7290      rtx x;
7291      enum rtx_code cond;
7292      rtx reg, val;
7293 {
7294   enum rtx_code code = GET_CODE (x);
7295   rtx temp;
7296   const char *fmt;
7297   int i, j;
7298
7299   if (side_effects_p (x))
7300     return x;
7301
7302   if (cond == EQ && rtx_equal_p (x, reg))
7303     return val;
7304
7305   /* If X is (abs REG) and we know something about REG's relationship
7306      with zero, we may be able to simplify this.  */
7307
7308   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7309     switch (cond)
7310       {
7311       case GE:  case GT:  case EQ:
7312         return XEXP (x, 0);
7313       case LT:  case LE:
7314         return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7315                           XEXP (x, 0));
7316       default:
7317         break;
7318       }
7319
7320   /* The only other cases we handle are MIN, MAX, and comparisons if the
7321      operands are the same as REG and VAL.  */
7322
7323   else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7324     {
7325       if (rtx_equal_p (XEXP (x, 0), val))
7326         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7327
7328       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7329         {
7330           if (GET_RTX_CLASS (code) == '<')
7331             {
7332               if (comparison_dominates_p (cond, code))
7333                 return const_true_rtx;
7334
7335               code = reverse_condition (code);
7336               if (code != UNKNOWN
7337                   && comparison_dominates_p (cond, code))
7338                 return const0_rtx;
7339               else
7340                 return x;
7341             }
7342           else if (code == SMAX || code == SMIN
7343                    || code == UMIN || code == UMAX)
7344             {
7345               int unsignedp = (code == UMIN || code == UMAX);
7346
7347               if (code == SMAX || code == UMAX)
7348                 cond = reverse_condition (cond);
7349
7350               switch (cond)
7351                 {
7352                 case GE:   case GT:
7353                   return unsignedp ? x : XEXP (x, 1);
7354                 case LE:   case LT:
7355                   return unsignedp ? x : XEXP (x, 0);
7356                 case GEU:  case GTU:
7357                   return unsignedp ? XEXP (x, 1) : x;
7358                 case LEU:  case LTU:
7359                   return unsignedp ? XEXP (x, 0) : x;
7360                 default:
7361                   break;
7362                 }
7363             }
7364         }
7365     }
7366
7367   fmt = GET_RTX_FORMAT (code);
7368   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7369     {
7370       if (fmt[i] == 'e')
7371         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7372       else if (fmt[i] == 'E')
7373         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7374           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7375                                                 cond, reg, val));
7376     }
7377
7378   return x;
7379 }
7380 \f
7381 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7382    assignment as a field assignment.  */
7383
7384 static int
7385 rtx_equal_for_field_assignment_p (x, y)
7386      rtx x;
7387      rtx y;
7388 {
7389   if (x == y || rtx_equal_p (x, y))
7390     return 1;
7391
7392   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7393     return 0;
7394
7395   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7396      Note that all SUBREGs of MEM are paradoxical; otherwise they
7397      would have been rewritten.  */
7398   if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7399       && GET_CODE (SUBREG_REG (y)) == MEM
7400       && rtx_equal_p (SUBREG_REG (y),
7401                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7402     return 1;
7403
7404   if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7405       && GET_CODE (SUBREG_REG (x)) == MEM
7406       && rtx_equal_p (SUBREG_REG (x),
7407                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7408     return 1;
7409
7410   /* We used to see if get_last_value of X and Y were the same but that's
7411      not correct.  In one direction, we'll cause the assignment to have
7412      the wrong destination and in the case, we'll import a register into this
7413      insn that might have already have been dead.   So fail if none of the
7414      above cases are true.  */
7415   return 0;
7416 }
7417 \f
7418 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7419    Return that assignment if so.
7420
7421    We only handle the most common cases.  */
7422
7423 static rtx
7424 make_field_assignment (x)
7425      rtx x;
7426 {
7427   rtx dest = SET_DEST (x);
7428   rtx src = SET_SRC (x);
7429   rtx assign;
7430   rtx rhs, lhs;
7431   HOST_WIDE_INT c1;
7432   int pos, len;
7433   rtx other;
7434   enum machine_mode mode;
7435
7436   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7437      a clear of a one-bit field.  We will have changed it to
7438      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7439      for a SUBREG.  */
7440
7441   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7442       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7443       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7444       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7445     {
7446       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7447                                 1, 1, 1, 0);
7448       if (assign != 0)
7449         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7450       return x;
7451     }
7452
7453   else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7454            && subreg_lowpart_p (XEXP (src, 0))
7455            && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7456                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7457            && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7458            && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7459            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7460     {
7461       assign = make_extraction (VOIDmode, dest, 0,
7462                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7463                                 1, 1, 1, 0);
7464       if (assign != 0)
7465         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7466       return x;
7467     }
7468
7469   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7470      one-bit field.  */
7471   else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7472            && XEXP (XEXP (src, 0), 0) == const1_rtx
7473            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7474     {
7475       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7476                                 1, 1, 1, 0);
7477       if (assign != 0)
7478         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7479       return x;
7480     }
7481
7482   /* The other case we handle is assignments into a constant-position
7483      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7484      a mask that has all one bits except for a group of zero bits and
7485      OTHER is known to have zeros where C1 has ones, this is such an
7486      assignment.  Compute the position and length from C1.  Shift OTHER
7487      to the appropriate position, force it to the required mode, and
7488      make the extraction.  Check for the AND in both operands.  */
7489
7490   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7491     return x;
7492
7493   rhs = expand_compound_operation (XEXP (src, 0));
7494   lhs = expand_compound_operation (XEXP (src, 1));
7495
7496   if (GET_CODE (rhs) == AND
7497       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7498       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7499     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7500   else if (GET_CODE (lhs) == AND
7501            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7502            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7503     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7504   else
7505     return x;
7506
7507   pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7508   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7509       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7510       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7511     return x;
7512
7513   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7514   if (assign == 0)
7515     return x;
7516
7517   /* The mode to use for the source is the mode of the assignment, or of
7518      what is inside a possible STRICT_LOW_PART.  */
7519   mode = (GET_CODE (assign) == STRICT_LOW_PART
7520           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7521
7522   /* Shift OTHER right POS places and make it the source, restricting it
7523      to the proper length and mode.  */
7524
7525   src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7526                                              GET_MODE (src), other, pos),
7527                        mode,
7528                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7529                        ? GET_MODE_MASK (mode)
7530                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7531                        dest, 0);
7532
7533   return gen_rtx_combine (SET, VOIDmode, assign, src);
7534 }
7535 \f
7536 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7537    if so.  */
7538
7539 static rtx
7540 apply_distributive_law (x)
7541      rtx x;
7542 {
7543   enum rtx_code code = GET_CODE (x);
7544   rtx lhs, rhs, other;
7545   rtx tem;
7546   enum rtx_code inner_code;
7547
7548   /* Distributivity is not true for floating point.
7549      It can change the value.  So don't do it.
7550      -- rms and moshier@world.std.com.  */
7551   if (FLOAT_MODE_P (GET_MODE (x)))
7552     return x;
7553
7554   /* The outer operation can only be one of the following:  */
7555   if (code != IOR && code != AND && code != XOR
7556       && code != PLUS && code != MINUS)
7557     return x;
7558
7559   lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7560
7561   /* If either operand is a primitive we can't do anything, so get out
7562      fast.  */
7563   if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7564       || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7565     return x;
7566
7567   lhs = expand_compound_operation (lhs);
7568   rhs = expand_compound_operation (rhs);
7569   inner_code = GET_CODE (lhs);
7570   if (inner_code != GET_CODE (rhs))
7571     return x;
7572
7573   /* See if the inner and outer operations distribute.  */
7574   switch (inner_code)
7575     {
7576     case LSHIFTRT:
7577     case ASHIFTRT:
7578     case AND:
7579     case IOR:
7580       /* These all distribute except over PLUS.  */
7581       if (code == PLUS || code == MINUS)
7582         return x;
7583       break;
7584
7585     case MULT:
7586       if (code != PLUS && code != MINUS)
7587         return x;
7588       break;
7589
7590     case ASHIFT:
7591       /* This is also a multiply, so it distributes over everything.  */
7592       break;
7593
7594     case SUBREG:
7595       /* Non-paradoxical SUBREGs distributes over all operations, provided
7596          the inner modes and word numbers are the same, this is an extraction
7597          of a low-order part, we don't convert an fp operation to int or
7598          vice versa, and we would not be converting a single-word
7599          operation into a multi-word operation.  The latter test is not
7600          required, but it prevents generating unneeded multi-word operations.
7601          Some of the previous tests are redundant given the latter test, but
7602          are retained because they are required for correctness.
7603
7604          We produce the result slightly differently in this case.  */
7605
7606       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7607           || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7608           || ! subreg_lowpart_p (lhs)
7609           || (GET_MODE_CLASS (GET_MODE (lhs))
7610               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7611           || (GET_MODE_SIZE (GET_MODE (lhs))
7612               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7613           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7614         return x;
7615
7616       tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7617                         SUBREG_REG (lhs), SUBREG_REG (rhs));
7618       return gen_lowpart_for_combine (GET_MODE (x), tem);
7619
7620     default:
7621       return x;
7622     }
7623
7624   /* Set LHS and RHS to the inner operands (A and B in the example
7625      above) and set OTHER to the common operand (C in the example).
7626      These is only one way to do this unless the inner operation is
7627      commutative.  */
7628   if (GET_RTX_CLASS (inner_code) == 'c'
7629       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7630     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7631   else if (GET_RTX_CLASS (inner_code) == 'c'
7632            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7633     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7634   else if (GET_RTX_CLASS (inner_code) == 'c'
7635            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7636     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7637   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7638     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7639   else
7640     return x;
7641
7642   /* Form the new inner operation, seeing if it simplifies first.  */
7643   tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7644
7645   /* There is one exception to the general way of distributing:
7646      (a ^ b) | (a ^ c) -> (~a) & (b ^ c)  */
7647   if (code == XOR && inner_code == IOR)
7648     {
7649       inner_code = AND;
7650       other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7651     }
7652
7653   /* We may be able to continuing distributing the result, so call
7654      ourselves recursively on the inner operation before forming the
7655      outer operation, which we return.  */
7656   return gen_binary (inner_code, GET_MODE (x),
7657                      apply_distributive_law (tem), other);
7658 }
7659 \f
7660 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7661    in MODE.
7662
7663    Return an equivalent form, if different from X.  Otherwise, return X.  If
7664    X is zero, we are to always construct the equivalent form.  */
7665
7666 static rtx
7667 simplify_and_const_int (x, mode, varop, constop)
7668      rtx x;
7669      enum machine_mode mode;
7670      rtx varop;
7671      unsigned HOST_WIDE_INT constop;
7672 {
7673   unsigned HOST_WIDE_INT nonzero;
7674   int i;
7675
7676   /* Simplify VAROP knowing that we will be only looking at some of the
7677      bits in it.  */
7678   varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7679
7680   /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7681      CONST_INT, we are done.  */
7682   if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7683     return varop;
7684
7685   /* See what bits may be nonzero in VAROP.  Unlike the general case of
7686      a call to nonzero_bits, here we don't care about bits outside
7687      MODE.  */
7688
7689   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7690   nonzero = trunc_int_for_mode (nonzero, mode);
7691
7692   /* Turn off all bits in the constant that are known to already be zero.
7693      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7694      which is tested below.  */
7695
7696   constop &= nonzero;
7697
7698   /* If we don't have any bits left, return zero.  */
7699   if (constop == 0)
7700     return const0_rtx;
7701
7702   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7703      a power of two, we can replace this with a ASHIFT.  */
7704   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7705       && (i = exact_log2 (constop)) >= 0)
7706     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7707
7708   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7709      or XOR, then try to apply the distributive law.  This may eliminate
7710      operations if either branch can be simplified because of the AND.
7711      It may also make some cases more complex, but those cases probably
7712      won't match a pattern either with or without this.  */
7713
7714   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7715     return
7716       gen_lowpart_for_combine
7717         (mode,
7718          apply_distributive_law
7719          (gen_binary (GET_CODE (varop), GET_MODE (varop),
7720                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7721                                               XEXP (varop, 0), constop),
7722                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7723                                               XEXP (varop, 1), constop))));
7724
7725   /* Get VAROP in MODE.  Try to get a SUBREG if not.  Don't make a new SUBREG
7726      if we already had one (just check for the simplest cases).  */
7727   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7728       && GET_MODE (XEXP (x, 0)) == mode
7729       && SUBREG_REG (XEXP (x, 0)) == varop)
7730     varop = XEXP (x, 0);
7731   else
7732     varop = gen_lowpart_for_combine (mode, varop);
7733
7734   /* If we can't make the SUBREG, try to return what we were given.  */
7735   if (GET_CODE (varop) == CLOBBER)
7736     return x ? x : varop;
7737
7738   /* If we are only masking insignificant bits, return VAROP.  */
7739   if (constop == nonzero)
7740     x = varop;
7741
7742   /* Otherwise, return an AND.  See how much, if any, of X we can use.  */
7743   else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7744     x = gen_binary (AND, mode, varop, GEN_INT (constop));
7745
7746   else
7747     {
7748       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7749           || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7750         SUBST (XEXP (x, 1), GEN_INT (constop));
7751
7752       SUBST (XEXP (x, 0), varop);
7753     }
7754
7755   return x;
7756 }
7757 \f
7758 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7759    We don't let nonzero_bits recur into num_sign_bit_copies, because that
7760    is less useful.  We can't allow both, because that results in exponential
7761    run time recursion.  There is a nullstone testcase that triggered
7762    this.  This macro avoids accidental uses of num_sign_bit_copies.  */
7763 #define num_sign_bit_copies()
7764
7765 /* Given an expression, X, compute which bits in X can be non-zero.
7766    We don't care about bits outside of those defined in MODE.
7767
7768    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7769    a shift, AND, or zero_extract, we can do better.  */
7770
7771 static unsigned HOST_WIDE_INT
7772 nonzero_bits (x, mode)
7773      rtx x;
7774      enum machine_mode mode;
7775 {
7776   unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7777   unsigned HOST_WIDE_INT inner_nz;
7778   enum rtx_code code;
7779   int mode_width = GET_MODE_BITSIZE (mode);
7780   rtx tem;
7781
7782   /* For floating-point values, assume all bits are needed.  */
7783   if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7784     return nonzero;
7785
7786   /* If X is wider than MODE, use its mode instead.  */
7787   if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7788     {
7789       mode = GET_MODE (x);
7790       nonzero = GET_MODE_MASK (mode);
7791       mode_width = GET_MODE_BITSIZE (mode);
7792     }
7793
7794   if (mode_width > HOST_BITS_PER_WIDE_INT)
7795     /* Our only callers in this case look for single bit values.  So
7796        just return the mode mask.  Those tests will then be false.  */
7797     return nonzero;
7798
7799 #ifndef WORD_REGISTER_OPERATIONS
7800   /* If MODE is wider than X, but both are a single word for both the host
7801      and target machines, we can compute this from which bits of the
7802      object might be nonzero in its own mode, taking into account the fact
7803      that on many CISC machines, accessing an object in a wider mode
7804      causes the high-order bits to become undefined.  So they are
7805      not known to be zero.  */
7806
7807   if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7808       && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7809       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7810       && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7811     {
7812       nonzero &= nonzero_bits (x, GET_MODE (x));
7813       nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7814       return nonzero;
7815     }
7816 #endif
7817
7818   code = GET_CODE (x);
7819   switch (code)
7820     {
7821     case REG:
7822 #ifdef POINTERS_EXTEND_UNSIGNED
7823       /* If pointers extend unsigned and this is a pointer in Pmode, say that
7824          all the bits above ptr_mode are known to be zero.  */
7825       if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7826           && REGNO_POINTER_FLAG (REGNO (x)))
7827         nonzero &= GET_MODE_MASK (ptr_mode);
7828 #endif
7829
7830 #ifdef STACK_BOUNDARY
7831       /* If this is the stack pointer, we may know something about its
7832          alignment.  If PUSH_ROUNDING is defined, it is possible for the
7833          stack to be momentarily aligned only to that amount, so we pick
7834          the least alignment.  */
7835
7836       /* We can't check for arg_pointer_rtx here, because it is not
7837          guaranteed to have as much alignment as the stack pointer.
7838          In particular, in the Irix6 n64 ABI, the stack has 128 bit
7839          alignment but the argument pointer has only 64 bit alignment.  */
7840
7841       if ((x == frame_pointer_rtx
7842            || x == stack_pointer_rtx
7843            || x == hard_frame_pointer_rtx
7844            || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7845                && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7846 #ifdef STACK_BIAS
7847           && !STACK_BIAS
7848 #endif
7849               )
7850         {
7851           int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7852
7853 #ifdef PUSH_ROUNDING
7854           if (REGNO (x) == STACK_POINTER_REGNUM)
7855             sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7856 #endif
7857
7858           /* We must return here, otherwise we may get a worse result from
7859              one of the choices below.  There is nothing useful below as
7860              far as the stack pointer is concerned.  */
7861           return nonzero &= ~ (sp_alignment - 1);
7862         }
7863 #endif
7864
7865       /* If X is a register whose nonzero bits value is current, use it.
7866          Otherwise, if X is a register whose value we can find, use that
7867          value.  Otherwise, use the previously-computed global nonzero bits
7868          for this register.  */
7869
7870       if (reg_last_set_value[REGNO (x)] != 0
7871           && reg_last_set_mode[REGNO (x)] == mode
7872           && (reg_last_set_label[REGNO (x)] == label_tick
7873               || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7874                   && REG_N_SETS (REGNO (x)) == 1
7875                   && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7876                                         REGNO (x))))
7877           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7878         return reg_last_set_nonzero_bits[REGNO (x)];
7879
7880       tem = get_last_value (x);
7881
7882       if (tem)
7883         {
7884 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7885           /* If X is narrower than MODE and TEM is a non-negative
7886              constant that would appear negative in the mode of X,
7887              sign-extend it for use in reg_nonzero_bits because some
7888              machines (maybe most) will actually do the sign-extension
7889              and this is the conservative approach.
7890
7891              ??? For 2.5, try to tighten up the MD files in this regard
7892              instead of this kludge.  */
7893
7894           if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7895               && GET_CODE (tem) == CONST_INT
7896               && INTVAL (tem) > 0
7897               && 0 != (INTVAL (tem)
7898                        & ((HOST_WIDE_INT) 1
7899                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7900             tem = GEN_INT (INTVAL (tem)
7901                            | ((HOST_WIDE_INT) (-1)
7902                               << GET_MODE_BITSIZE (GET_MODE (x))));
7903 #endif
7904           return nonzero_bits (tem, mode);
7905         }
7906       else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7907         return reg_nonzero_bits[REGNO (x)] & nonzero;
7908       else
7909         return nonzero;
7910
7911     case CONST_INT:
7912 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7913       /* If X is negative in MODE, sign-extend the value.  */
7914       if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7915           && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7916         return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7917 #endif
7918
7919       return INTVAL (x);
7920
7921     case MEM:
7922 #ifdef LOAD_EXTEND_OP
7923       /* In many, if not most, RISC machines, reading a byte from memory
7924          zeros the rest of the register.  Noticing that fact saves a lot
7925          of extra zero-extends.  */
7926       if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7927         nonzero &= GET_MODE_MASK (GET_MODE (x));
7928 #endif
7929       break;
7930
7931     case EQ:  case NE:
7932     case GT:  case GTU:
7933     case LT:  case LTU:
7934     case GE:  case GEU:
7935     case LE:  case LEU:
7936
7937       /* If this produces an integer result, we know which bits are set.
7938          Code here used to clear bits outside the mode of X, but that is
7939          now done above.  */
7940
7941       if (GET_MODE_CLASS (mode) == MODE_INT
7942           && mode_width <= HOST_BITS_PER_WIDE_INT)
7943         nonzero = STORE_FLAG_VALUE;
7944       break;
7945
7946     case NEG:
7947 #if 0
7948       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7949          and num_sign_bit_copies.  */
7950       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7951           == GET_MODE_BITSIZE (GET_MODE (x)))
7952         nonzero = 1;
7953 #endif
7954
7955       if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7956         nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7957       break;
7958
7959     case ABS:
7960 #if 0
7961       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7962          and num_sign_bit_copies.  */
7963       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7964           == GET_MODE_BITSIZE (GET_MODE (x)))
7965         nonzero = 1;
7966 #endif
7967       break;
7968
7969     case TRUNCATE:
7970       nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7971       break;
7972
7973     case ZERO_EXTEND:
7974       nonzero &= nonzero_bits (XEXP (x, 0), mode);
7975       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7976         nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7977       break;
7978
7979     case SIGN_EXTEND:
7980       /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7981          Otherwise, show all the bits in the outer mode but not the inner
7982          may be non-zero.  */
7983       inner_nz = nonzero_bits (XEXP (x, 0), mode);
7984       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7985         {
7986           inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7987           if (inner_nz
7988               & (((HOST_WIDE_INT) 1
7989                   << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7990             inner_nz |= (GET_MODE_MASK (mode)
7991                           & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7992         }
7993
7994       nonzero &= inner_nz;
7995       break;
7996
7997     case AND:
7998       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7999                   & nonzero_bits (XEXP (x, 1), mode));
8000       break;
8001
8002     case XOR:   case IOR:
8003     case UMIN:  case UMAX:  case SMIN:  case SMAX:
8004       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8005                   | nonzero_bits (XEXP (x, 1), mode));
8006       break;
8007
8008     case PLUS:  case MINUS:
8009     case MULT:
8010     case DIV:   case UDIV:
8011     case MOD:   case UMOD:
8012       /* We can apply the rules of arithmetic to compute the number of
8013          high- and low-order zero bits of these operations.  We start by
8014          computing the width (position of the highest-order non-zero bit)
8015          and the number of low-order zero bits for each value.  */
8016       {
8017         unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8018         unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8019         int width0 = floor_log2 (nz0) + 1;
8020         int width1 = floor_log2 (nz1) + 1;
8021         int low0 = floor_log2 (nz0 & -nz0);
8022         int low1 = floor_log2 (nz1 & -nz1);
8023         HOST_WIDE_INT op0_maybe_minusp
8024           = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8025         HOST_WIDE_INT op1_maybe_minusp
8026           = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8027         int result_width = mode_width;
8028         int result_low = 0;
8029
8030         switch (code)
8031           {
8032           case PLUS:
8033 #ifdef STACK_BIAS
8034             if (STACK_BIAS
8035                 && (XEXP (x, 0) == stack_pointer_rtx
8036                     || XEXP (x, 0) == frame_pointer_rtx)
8037                 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8038               {
8039                 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8040
8041                 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
8042                 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8043                 width0 = floor_log2 (nz0) + 1;
8044                 width1 = floor_log2 (nz1) + 1;
8045                 low0 = floor_log2 (nz0 & -nz0);
8046                 low1 = floor_log2 (nz1 & -nz1);
8047               }
8048 #endif
8049             result_width = MAX (width0, width1) + 1;
8050             result_low = MIN (low0, low1);
8051             break;
8052           case MINUS:
8053             result_low = MIN (low0, low1);
8054             break;
8055           case MULT:
8056             result_width = width0 + width1;
8057             result_low = low0 + low1;
8058             break;
8059           case DIV:
8060             if (! op0_maybe_minusp && ! op1_maybe_minusp)
8061               result_width = width0;
8062             break;
8063           case UDIV:
8064             result_width = width0;
8065             break;
8066           case MOD:
8067             if (! op0_maybe_minusp && ! op1_maybe_minusp)
8068               result_width = MIN (width0, width1);
8069             result_low = MIN (low0, low1);
8070             break;
8071           case UMOD:
8072             result_width = MIN (width0, width1);
8073             result_low = MIN (low0, low1);
8074             break;
8075           default:
8076             abort ();
8077           }
8078
8079         if (result_width < mode_width)
8080           nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8081
8082         if (result_low > 0)
8083           nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
8084       }
8085       break;
8086
8087     case ZERO_EXTRACT:
8088       if (GET_CODE (XEXP (x, 1)) == CONST_INT
8089           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8090         nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8091       break;
8092
8093     case SUBREG:
8094       /* If this is a SUBREG formed for a promoted variable that has
8095          been zero-extended, we know that at least the high-order bits
8096          are zero, though others might be too.  */
8097
8098       if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8099         nonzero = (GET_MODE_MASK (GET_MODE (x))
8100                    & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8101
8102       /* If the inner mode is a single word for both the host and target
8103          machines, we can compute this from which bits of the inner
8104          object might be nonzero.  */
8105       if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8106           && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8107               <= HOST_BITS_PER_WIDE_INT))
8108         {
8109           nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8110
8111 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8112           /* If this is a typical RISC machine, we only have to worry
8113              about the way loads are extended.  */
8114           if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8115               ? (((nonzero
8116                    & (((unsigned HOST_WIDE_INT) 1
8117                        << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8118                   != 0))
8119               : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8120 #endif
8121             {
8122               /* On many CISC machines, accessing an object in a wider mode
8123                  causes the high-order bits to become undefined.  So they are
8124                  not known to be zero.  */
8125               if (GET_MODE_SIZE (GET_MODE (x))
8126                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8127                 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8128                             & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8129             }
8130         }
8131       break;
8132
8133     case ASHIFTRT:
8134     case LSHIFTRT:
8135     case ASHIFT:
8136     case ROTATE:
8137       /* The nonzero bits are in two classes: any bits within MODE
8138          that aren't in GET_MODE (x) are always significant.  The rest of the
8139          nonzero bits are those that are significant in the operand of
8140          the shift when shifted the appropriate number of bits.  This
8141          shows that high-order bits are cleared by the right shift and
8142          low-order bits by left shifts.  */
8143       if (GET_CODE (XEXP (x, 1)) == CONST_INT
8144           && INTVAL (XEXP (x, 1)) >= 0
8145           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8146         {
8147           enum machine_mode inner_mode = GET_MODE (x);
8148           int width = GET_MODE_BITSIZE (inner_mode);
8149           int count = INTVAL (XEXP (x, 1));
8150           unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8151           unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8152           unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8153           unsigned HOST_WIDE_INT outer = 0;
8154
8155           if (mode_width > width)
8156             outer = (op_nonzero & nonzero & ~ mode_mask);
8157
8158           if (code == LSHIFTRT)
8159             inner >>= count;
8160           else if (code == ASHIFTRT)
8161             {
8162               inner >>= count;
8163
8164               /* If the sign bit may have been nonzero before the shift, we
8165                  need to mark all the places it could have been copied to
8166                  by the shift as possibly nonzero.  */
8167               if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8168                 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8169             }
8170           else if (code == ASHIFT)
8171             inner <<= count;
8172           else
8173             inner = ((inner << (count % width)
8174                       | (inner >> (width - (count % width)))) & mode_mask);
8175
8176           nonzero &= (outer | inner);
8177         }
8178       break;
8179
8180     case FFS:
8181       /* This is at most the number of bits in the mode.  */
8182       nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8183       break;
8184
8185     case IF_THEN_ELSE:
8186       nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8187                   | nonzero_bits (XEXP (x, 2), mode));
8188       break;
8189
8190     default:
8191       break;
8192     }
8193
8194   return nonzero;
8195 }
8196
8197 /* See the macro definition above.  */
8198 #undef num_sign_bit_copies
8199 \f
8200 /* Return the number of bits at the high-order end of X that are known to
8201    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8202    VOIDmode, X will be used in its own mode.  The returned value  will always
8203    be between 1 and the number of bits in MODE.  */
8204
8205 static int
8206 num_sign_bit_copies (x, mode)
8207      rtx x;
8208      enum machine_mode mode;
8209 {
8210   enum rtx_code code = GET_CODE (x);
8211   int bitwidth;
8212   int num0, num1, result;
8213   unsigned HOST_WIDE_INT nonzero;
8214   rtx tem;
8215
8216   /* If we weren't given a mode, use the mode of X.  If the mode is still
8217      VOIDmode, we don't know anything.  Likewise if one of the modes is
8218      floating-point.  */
8219
8220   if (mode == VOIDmode)
8221     mode = GET_MODE (x);
8222
8223   if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8224     return 1;
8225
8226   bitwidth = GET_MODE_BITSIZE (mode);
8227
8228   /* For a smaller object, just ignore the high bits.  */
8229   if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8230     return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
8231                     - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
8232
8233   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8234     {
8235 #ifndef WORD_REGISTER_OPERATIONS
8236   /* If this machine does not do all register operations on the entire
8237      register and MODE is wider than the mode of X, we can say nothing
8238      at all about the high-order bits.  */
8239       return 1;
8240 #else
8241       /* Likewise on machines that do, if the mode of the object is smaller
8242          than a word and loads of that size don't sign extend, we can say
8243          nothing about the high order bits.  */
8244       if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8245 #ifdef LOAD_EXTEND_OP
8246           && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8247 #endif
8248           )
8249         return 1;
8250 #endif
8251     }
8252
8253   switch (code)
8254     {
8255     case REG:
8256
8257 #ifdef POINTERS_EXTEND_UNSIGNED
8258       /* If pointers extend signed and this is a pointer in Pmode, say that
8259          all the bits above ptr_mode are known to be sign bit copies.  */
8260       if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8261           && REGNO_POINTER_FLAG (REGNO (x)))
8262         return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8263 #endif
8264
8265       if (reg_last_set_value[REGNO (x)] != 0
8266           && reg_last_set_mode[REGNO (x)] == mode
8267           && (reg_last_set_label[REGNO (x)] == label_tick
8268               || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8269                   && REG_N_SETS (REGNO (x)) == 1
8270                   && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8271                                         REGNO (x))))
8272           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8273         return reg_last_set_sign_bit_copies[REGNO (x)];
8274
8275       tem =  get_last_value (x);
8276       if (tem != 0)
8277         return num_sign_bit_copies (tem, mode);
8278
8279       if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8280         return reg_sign_bit_copies[REGNO (x)];
8281       break;
8282
8283     case MEM:
8284 #ifdef LOAD_EXTEND_OP
8285       /* Some RISC machines sign-extend all loads of smaller than a word.  */
8286       if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8287         return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
8288 #endif
8289       break;
8290
8291     case CONST_INT:
8292       /* If the constant is negative, take its 1's complement and remask.
8293          Then see how many zero bits we have.  */
8294       nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8295       if (bitwidth <= HOST_BITS_PER_WIDE_INT
8296           && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8297         nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8298
8299       return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8300
8301     case SUBREG:
8302       /* If this is a SUBREG for a promoted object that is sign-extended
8303          and we are looking at it in a wider mode, we know that at least the
8304          high-order bits are known to be sign bit copies.  */
8305
8306       if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8307         return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8308                     num_sign_bit_copies (SUBREG_REG (x), mode));
8309
8310       /* For a smaller object, just ignore the high bits.  */
8311       if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8312         {
8313           num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8314           return MAX (1, (num0
8315                           - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8316                              - bitwidth)));
8317         }
8318
8319 #ifdef WORD_REGISTER_OPERATIONS
8320 #ifdef LOAD_EXTEND_OP
8321       /* For paradoxical SUBREGs on machines where all register operations
8322          affect the entire register, just look inside.  Note that we are
8323          passing MODE to the recursive call, so the number of sign bit copies
8324          will remain relative to that mode, not the inner mode.  */
8325
8326       /* This works only if loads sign extend.  Otherwise, if we get a
8327          reload for the inner part, it may be loaded from the stack, and
8328          then we lose all sign bit copies that existed before the store
8329          to the stack.  */
8330
8331       if ((GET_MODE_SIZE (GET_MODE (x))
8332            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8333           && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8334         return num_sign_bit_copies (SUBREG_REG (x), mode);
8335 #endif
8336 #endif
8337       break;
8338
8339     case SIGN_EXTRACT:
8340       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8341         return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
8342       break;
8343
8344     case SIGN_EXTEND:
8345       return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8346               + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8347
8348     case TRUNCATE:
8349       /* For a smaller object, just ignore the high bits.  */
8350       num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8351       return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8352                               - bitwidth)));
8353
8354     case NOT:
8355       return num_sign_bit_copies (XEXP (x, 0), mode);
8356
8357     case ROTATE:       case ROTATERT:
8358       /* If we are rotating left by a number of bits less than the number
8359          of sign bit copies, we can just subtract that amount from the
8360          number.  */
8361       if (GET_CODE (XEXP (x, 1)) == CONST_INT
8362           && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8363         {
8364           num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8365           return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8366                                  : bitwidth - INTVAL (XEXP (x, 1))));
8367         }
8368       break;
8369
8370     case NEG:
8371       /* In general, this subtracts one sign bit copy.  But if the value
8372          is known to be positive, the number of sign bit copies is the
8373          same as that of the input.  Finally, if the input has just one bit
8374          that might be nonzero, all the bits are copies of the sign bit.  */
8375       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8376       if (bitwidth > HOST_BITS_PER_WIDE_INT)
8377         return num0 > 1 ? num0 - 1 : 1;
8378
8379       nonzero = nonzero_bits (XEXP (x, 0), mode);
8380       if (nonzero == 1)
8381         return bitwidth;
8382
8383       if (num0 > 1
8384           && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8385         num0--;
8386
8387       return num0;
8388
8389     case IOR:   case AND:   case XOR:
8390     case SMIN:  case SMAX:  case UMIN:  case UMAX:
8391       /* Logical operations will preserve the number of sign-bit copies.
8392          MIN and MAX operations always return one of the operands.  */
8393       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8394       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8395       return MIN (num0, num1);
8396
8397     case PLUS:  case MINUS:
8398       /* For addition and subtraction, we can have a 1-bit carry.  However,
8399          if we are subtracting 1 from a positive number, there will not
8400          be such a carry.  Furthermore, if the positive number is known to
8401          be 0 or 1, we know the result is either -1 or 0.  */
8402
8403       if (code == PLUS && XEXP (x, 1) == constm1_rtx
8404           && bitwidth <= HOST_BITS_PER_WIDE_INT)
8405         {
8406           nonzero = nonzero_bits (XEXP (x, 0), mode);
8407           if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8408             return (nonzero == 1 || nonzero == 0 ? bitwidth
8409                     : bitwidth - floor_log2 (nonzero) - 1);
8410         }
8411
8412       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8413       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8414       return MAX (1, MIN (num0, num1) - 1);
8415
8416     case MULT:
8417       /* The number of bits of the product is the sum of the number of
8418          bits of both terms.  However, unless one of the terms if known
8419          to be positive, we must allow for an additional bit since negating
8420          a negative number can remove one sign bit copy.  */
8421
8422       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8423       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8424
8425       result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8426       if (result > 0
8427           && (bitwidth > HOST_BITS_PER_WIDE_INT
8428               || (((nonzero_bits (XEXP (x, 0), mode)
8429                     & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8430                   && ((nonzero_bits (XEXP (x, 1), mode)
8431                        & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8432         result--;
8433
8434       return MAX (1, result);
8435
8436     case UDIV:
8437       /* The result must be <= the first operand.  If the first operand
8438          has the high bit set, we know nothing about the number of sign
8439          bit copies.  */
8440       if (bitwidth > HOST_BITS_PER_WIDE_INT)
8441         return 1;
8442       else if ((nonzero_bits (XEXP (x, 0), mode)
8443                 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8444         return 1;
8445       else
8446         return num_sign_bit_copies (XEXP (x, 0), mode);
8447
8448     case UMOD:
8449       /* The result must be <= the scond operand.  */
8450       return num_sign_bit_copies (XEXP (x, 1), mode);
8451
8452     case DIV:
8453       /* Similar to unsigned division, except that we have to worry about
8454          the case where the divisor is negative, in which case we have
8455          to add 1.  */
8456       result = num_sign_bit_copies (XEXP (x, 0), mode);
8457       if (result > 1
8458           && (bitwidth > HOST_BITS_PER_WIDE_INT
8459               || (nonzero_bits (XEXP (x, 1), mode)
8460                   & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8461         result--;
8462
8463       return result;
8464
8465     case MOD:
8466       result = num_sign_bit_copies (XEXP (x, 1), mode);
8467       if (result > 1
8468           && (bitwidth > HOST_BITS_PER_WIDE_INT
8469               || (nonzero_bits (XEXP (x, 1), mode)
8470                   & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8471         result--;
8472
8473       return result;
8474
8475     case ASHIFTRT:
8476       /* Shifts by a constant add to the number of bits equal to the
8477          sign bit.  */
8478       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8479       if (GET_CODE (XEXP (x, 1)) == CONST_INT
8480           && INTVAL (XEXP (x, 1)) > 0)
8481         num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8482
8483       return num0;
8484
8485     case ASHIFT:
8486       /* Left shifts destroy copies.  */
8487       if (GET_CODE (XEXP (x, 1)) != CONST_INT
8488           || INTVAL (XEXP (x, 1)) < 0
8489           || INTVAL (XEXP (x, 1)) >= bitwidth)
8490         return 1;
8491
8492       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8493       return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8494
8495     case IF_THEN_ELSE:
8496       num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8497       num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8498       return MIN (num0, num1);
8499
8500     case EQ:  case NE:  case GE:  case GT:  case LE:  case LT:
8501     case GEU: case GTU: case LEU: case LTU:
8502       if (STORE_FLAG_VALUE == -1)
8503         return bitwidth;
8504       break;
8505
8506     default:
8507       break;
8508     }
8509
8510   /* If we haven't been able to figure it out by one of the above rules,
8511      see if some of the high-order bits are known to be zero.  If so,
8512      count those bits and return one less than that amount.  If we can't
8513      safely compute the mask for this mode, always return BITWIDTH.  */
8514
8515   if (bitwidth > HOST_BITS_PER_WIDE_INT)
8516     return 1;
8517
8518   nonzero = nonzero_bits (x, mode);
8519   return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8520           ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8521 }
8522 \f
8523 /* Return the number of "extended" bits there are in X, when interpreted
8524    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8525    unsigned quantities, this is the number of high-order zero bits.
8526    For signed quantities, this is the number of copies of the sign bit
8527    minus 1.  In both case, this function returns the number of "spare"
8528    bits.  For example, if two quantities for which this function returns
8529    at least 1 are added, the addition is known not to overflow.
8530
8531    This function will always return 0 unless called during combine, which
8532    implies that it must be called from a define_split.  */
8533
8534 int
8535 extended_count (x, mode, unsignedp)
8536      rtx x;
8537      enum machine_mode mode;
8538      int unsignedp;
8539 {
8540   if (nonzero_sign_valid == 0)
8541     return 0;
8542
8543   return (unsignedp
8544           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8545              && (GET_MODE_BITSIZE (mode) - 1
8546                  - floor_log2 (nonzero_bits (x, mode))))
8547           : num_sign_bit_copies (x, mode) - 1);
8548 }
8549 \f
8550 /* This function is called from `simplify_shift_const' to merge two
8551    outer operations.  Specifically, we have already found that we need
8552    to perform operation *POP0 with constant *PCONST0 at the outermost
8553    position.  We would now like to also perform OP1 with constant CONST1
8554    (with *POP0 being done last).
8555
8556    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8557    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8558    complement the innermost operand, otherwise it is unchanged.
8559
8560    MODE is the mode in which the operation will be done.  No bits outside
8561    the width of this mode matter.  It is assumed that the width of this mode
8562    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8563
8564    If *POP0 or OP1 are NIL, it means no operation is required.  Only NEG, PLUS,
8565    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8566    result is simply *PCONST0.
8567
8568    If the resulting operation cannot be expressed as one operation, we
8569    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8570
8571 static int
8572 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8573      enum rtx_code *pop0;
8574      HOST_WIDE_INT *pconst0;
8575      enum rtx_code op1;
8576      HOST_WIDE_INT const1;
8577      enum machine_mode mode;
8578      int *pcomp_p;
8579 {
8580   enum rtx_code op0 = *pop0;
8581   HOST_WIDE_INT const0 = *pconst0;
8582
8583   const0 &= GET_MODE_MASK (mode);
8584   const1 &= GET_MODE_MASK (mode);
8585
8586   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8587   if (op0 == AND)
8588     const1 &= const0;
8589
8590   /* If OP0 or OP1 is NIL, this is easy.  Similarly if they are the same or
8591      if OP0 is SET.  */
8592
8593   if (op1 == NIL || op0 == SET)
8594     return 1;
8595
8596   else if (op0 == NIL)
8597     op0 = op1, const0 = const1;
8598
8599   else if (op0 == op1)
8600     {
8601       switch (op0)
8602         {
8603         case AND:
8604           const0 &= const1;
8605           break;
8606         case IOR:
8607           const0 |= const1;
8608           break;
8609         case XOR:
8610           const0 ^= const1;
8611           break;
8612         case PLUS:
8613           const0 += const1;
8614           break;
8615         case NEG:
8616           op0 = NIL;
8617           break;
8618         default:
8619           break;
8620         }
8621     }
8622
8623   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8624   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8625     return 0;
8626
8627   /* If the two constants aren't the same, we can't do anything.  The
8628      remaining six cases can all be done.  */
8629   else if (const0 != const1)
8630     return 0;
8631
8632   else
8633     switch (op0)
8634       {
8635       case IOR:
8636         if (op1 == AND)
8637           /* (a & b) | b == b */
8638           op0 = SET;
8639         else /* op1 == XOR */
8640           /* (a ^ b) | b == a | b */
8641           {;}
8642         break;
8643
8644       case XOR:
8645         if (op1 == AND)
8646           /* (a & b) ^ b == (~a) & b */
8647           op0 = AND, *pcomp_p = 1;
8648         else /* op1 == IOR */
8649           /* (a | b) ^ b == a & ~b */
8650           op0 = AND, *pconst0 = ~ const0;
8651         break;
8652
8653       case AND:
8654         if (op1 == IOR)
8655           /* (a | b) & b == b */
8656         op0 = SET;
8657         else /* op1 == XOR */
8658           /* (a ^ b) & b) == (~a) & b */
8659           *pcomp_p = 1;
8660         break;
8661       default:
8662         break;
8663       }
8664
8665   /* Check for NO-OP cases.  */
8666   const0 &= GET_MODE_MASK (mode);
8667   if (const0 == 0
8668       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8669     op0 = NIL;
8670   else if (const0 == 0 && op0 == AND)
8671     op0 = SET;
8672   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8673            && op0 == AND)
8674     op0 = NIL;
8675
8676   /* ??? Slightly redundant with the above mask, but not entirely.
8677      Moving this above means we'd have to sign-extend the mode mask
8678      for the final test.  */
8679   const0 = trunc_int_for_mode (const0, mode);
8680
8681   *pop0 = op0;
8682   *pconst0 = const0;
8683
8684   return 1;
8685 }
8686 \f
8687 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8688    The result of the shift is RESULT_MODE.  X, if non-zero, is an expression
8689    that we started with.
8690
8691    The shift is normally computed in the widest mode we find in VAROP, as
8692    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8693    are ASHIFTRT and ROTATE, which are always done in their original mode,  */
8694
8695 static rtx
8696 simplify_shift_const (x, code, result_mode, varop, count)
8697      rtx x;
8698      enum rtx_code code;
8699      enum machine_mode result_mode;
8700      rtx varop;
8701      int count;
8702 {
8703   enum rtx_code orig_code = code;
8704   int orig_count = count;
8705   enum machine_mode mode = result_mode;
8706   enum machine_mode shift_mode, tmode;
8707   int mode_words
8708     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8709   /* We form (outer_op (code varop count) (outer_const)).  */
8710   enum rtx_code outer_op = NIL;
8711   HOST_WIDE_INT outer_const = 0;
8712   rtx const_rtx;
8713   int complement_p = 0;
8714   rtx new;
8715
8716   /* If we were given an invalid count, don't do anything except exactly
8717      what was requested.  */
8718
8719   if (count < 0 || count > GET_MODE_BITSIZE (mode))
8720     {
8721       if (x)
8722         return x;
8723
8724       return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8725     }
8726
8727   /* Unless one of the branches of the `if' in this loop does a `continue',
8728      we will `break' the loop after the `if'.  */
8729
8730   while (count != 0)
8731     {
8732       /* If we have an operand of (clobber (const_int 0)), just return that
8733          value.  */
8734       if (GET_CODE (varop) == CLOBBER)
8735         return varop;
8736
8737       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8738          here would cause an infinite loop.  */
8739       if (complement_p)
8740         break;
8741
8742       /* Convert ROTATERT to ROTATE.  */
8743       if (code == ROTATERT)
8744         code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8745
8746       /* We need to determine what mode we will do the shift in.  If the
8747          shift is a right shift or a ROTATE, we must always do it in the mode
8748          it was originally done in.  Otherwise, we can do it in MODE, the
8749          widest mode encountered.  */
8750       shift_mode
8751         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8752            ? result_mode : mode);
8753
8754       /* Handle cases where the count is greater than the size of the mode
8755          minus 1.  For ASHIFT, use the size minus one as the count (this can
8756          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8757          take the count modulo the size.  For other shifts, the result is
8758          zero.
8759
8760          Since these shifts are being produced by the compiler by combining
8761          multiple operations, each of which are defined, we know what the
8762          result is supposed to be.  */
8763
8764       if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8765         {
8766           if (code == ASHIFTRT)
8767             count = GET_MODE_BITSIZE (shift_mode) - 1;
8768           else if (code == ROTATE || code == ROTATERT)
8769             count %= GET_MODE_BITSIZE (shift_mode);
8770           else
8771             {
8772               /* We can't simply return zero because there may be an
8773                  outer op.  */
8774               varop = const0_rtx;
8775               count = 0;
8776               break;
8777             }
8778         }
8779
8780       /* Negative counts are invalid and should not have been made (a
8781          programmer-specified negative count should have been handled
8782          above).  */
8783       else if (count < 0)
8784         abort ();
8785
8786       /* An arithmetic right shift of a quantity known to be -1 or 0
8787          is a no-op.  */
8788       if (code == ASHIFTRT
8789           && (num_sign_bit_copies (varop, shift_mode)
8790               == GET_MODE_BITSIZE (shift_mode)))
8791         {
8792           count = 0;
8793           break;
8794         }
8795
8796       /* If we are doing an arithmetic right shift and discarding all but
8797          the sign bit copies, this is equivalent to doing a shift by the
8798          bitsize minus one.  Convert it into that shift because it will often
8799          allow other simplifications.  */
8800
8801       if (code == ASHIFTRT
8802           && (count + num_sign_bit_copies (varop, shift_mode)
8803               >= GET_MODE_BITSIZE (shift_mode)))
8804         count = GET_MODE_BITSIZE (shift_mode) - 1;
8805
8806       /* We simplify the tests below and elsewhere by converting
8807          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8808          `make_compound_operation' will convert it to a ASHIFTRT for
8809          those machines (such as Vax) that don't have a LSHIFTRT.  */
8810       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8811           && code == ASHIFTRT
8812           && ((nonzero_bits (varop, shift_mode)
8813                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8814               == 0))
8815         code = LSHIFTRT;
8816
8817       switch (GET_CODE (varop))
8818         {
8819         case SIGN_EXTEND:
8820         case ZERO_EXTEND:
8821         case SIGN_EXTRACT:
8822         case ZERO_EXTRACT:
8823           new = expand_compound_operation (varop);
8824           if (new != varop)
8825             {
8826               varop = new;
8827               continue;
8828             }
8829           break;
8830
8831         case MEM:
8832           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8833              minus the width of a smaller mode, we can do this with a
8834              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8835           if ((code == ASHIFTRT || code == LSHIFTRT)
8836               && ! mode_dependent_address_p (XEXP (varop, 0))
8837               && ! MEM_VOLATILE_P (varop)
8838               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8839                                          MODE_INT, 1)) != BLKmode)
8840             {
8841               if (BYTES_BIG_ENDIAN)
8842                 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8843               else
8844                 new = gen_rtx_MEM (tmode,
8845                                    plus_constant (XEXP (varop, 0),
8846                                                   count / BITS_PER_UNIT));
8847               RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8848               MEM_COPY_ATTRIBUTES (new, varop);
8849               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8850                                        : ZERO_EXTEND, mode, new);
8851               count = 0;
8852               continue;
8853             }
8854           break;
8855
8856         case USE:
8857           /* Similar to the case above, except that we can only do this if
8858              the resulting mode is the same as that of the underlying
8859              MEM and adjust the address depending on the *bits* endianness
8860              because of the way that bit-field extract insns are defined.  */
8861           if ((code == ASHIFTRT || code == LSHIFTRT)
8862               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8863                                          MODE_INT, 1)) != BLKmode
8864               && tmode == GET_MODE (XEXP (varop, 0)))
8865             {
8866               if (BITS_BIG_ENDIAN)
8867                 new = XEXP (varop, 0);
8868               else
8869                 {
8870                   new = copy_rtx (XEXP (varop, 0));
8871                   SUBST (XEXP (new, 0),
8872                          plus_constant (XEXP (new, 0),
8873                                         count / BITS_PER_UNIT));
8874                 }
8875
8876               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8877                                        : ZERO_EXTEND, mode, new);
8878               count = 0;
8879               continue;
8880             }
8881           break;
8882
8883         case SUBREG:
8884           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8885              the same number of words as what we've seen so far.  Then store
8886              the widest mode in MODE.  */
8887           if (subreg_lowpart_p (varop)
8888               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8889                   > GET_MODE_SIZE (GET_MODE (varop)))
8890               && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8891                     + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8892                   == mode_words))
8893             {
8894               varop = SUBREG_REG (varop);
8895               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8896                 mode = GET_MODE (varop);
8897               continue;
8898             }
8899           break;
8900
8901         case MULT:
8902           /* Some machines use MULT instead of ASHIFT because MULT
8903              is cheaper.  But it is still better on those machines to
8904              merge two shifts into one.  */
8905           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8906               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8907             {
8908               varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8909                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8910               continue;
8911             }
8912           break;
8913
8914         case UDIV:
8915           /* Similar, for when divides are cheaper.  */
8916           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8917               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8918             {
8919               varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8920                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8921               continue;
8922             }
8923           break;
8924
8925         case ASHIFTRT:
8926           /* If we are extracting just the sign bit of an arithmetic right
8927              shift, that shift is not needed.  */
8928           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8929             {
8930               varop = XEXP (varop, 0);
8931               continue;
8932             }
8933
8934           /* ... fall through ...  */
8935
8936         case LSHIFTRT:
8937         case ASHIFT:
8938         case ROTATE:
8939           /* Here we have two nested shifts.  The result is usually the
8940              AND of a new shift with a mask.  We compute the result below.  */
8941           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8942               && INTVAL (XEXP (varop, 1)) >= 0
8943               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8944               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8945               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8946             {
8947               enum rtx_code first_code = GET_CODE (varop);
8948               int first_count = INTVAL (XEXP (varop, 1));
8949               unsigned HOST_WIDE_INT mask;
8950               rtx mask_rtx;
8951
8952               /* We have one common special case.  We can't do any merging if
8953                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8954                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8955                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8956                  we can convert it to
8957                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8958                  This simplifies certain SIGN_EXTEND operations.  */
8959               if (code == ASHIFT && first_code == ASHIFTRT
8960                   && (GET_MODE_BITSIZE (result_mode)
8961                       - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8962                 {
8963                   /* C3 has the low-order C1 bits zero.  */
8964
8965                   mask = (GET_MODE_MASK (mode)
8966                           & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8967
8968                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8969                                                   XEXP (varop, 0), mask);
8970                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8971                                                 varop, count);
8972                   count = first_count;
8973                   code = ASHIFTRT;
8974                   continue;
8975                 }
8976
8977               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8978                  than C1 high-order bits equal to the sign bit, we can convert
8979                  this to either an ASHIFT or a ASHIFTRT depending on the
8980                  two counts.
8981
8982                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8983
8984               if (code == ASHIFTRT && first_code == ASHIFT
8985                   && GET_MODE (varop) == shift_mode
8986                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8987                       > first_count))
8988                 {
8989                   count -= first_count;
8990                   if (count < 0)
8991                     count = - count, code = ASHIFT;
8992                   varop = XEXP (varop, 0);
8993                   continue;
8994                 }
8995
8996               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8997                  we can only do this if FIRST_CODE is also ASHIFTRT.
8998
8999                  We can't do the case when CODE is ROTATE and FIRST_CODE is
9000                  ASHIFTRT.
9001
9002                  If the mode of this shift is not the mode of the outer shift,
9003                  we can't do this if either shift is a right shift or ROTATE.
9004
9005                  Finally, we can't do any of these if the mode is too wide
9006                  unless the codes are the same.
9007
9008                  Handle the case where the shift codes are the same
9009                  first.  */
9010
9011               if (code == first_code)
9012                 {
9013                   if (GET_MODE (varop) != result_mode
9014                       && (code == ASHIFTRT || code == LSHIFTRT
9015                           || code == ROTATE))
9016                     break;
9017
9018                   count += first_count;
9019                   varop = XEXP (varop, 0);
9020                   continue;
9021                 }
9022
9023               if (code == ASHIFTRT
9024                   || (code == ROTATE && first_code == ASHIFTRT)
9025                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9026                   || (GET_MODE (varop) != result_mode
9027                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
9028                           || first_code == ROTATE
9029                           || code == ROTATE)))
9030                 break;
9031
9032               /* To compute the mask to apply after the shift, shift the
9033                  nonzero bits of the inner shift the same way the
9034                  outer shift will.  */
9035
9036               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9037
9038               mask_rtx
9039                 = simplify_binary_operation (code, result_mode, mask_rtx,
9040                                              GEN_INT (count));
9041
9042               /* Give up if we can't compute an outer operation to use.  */
9043               if (mask_rtx == 0
9044                   || GET_CODE (mask_rtx) != CONST_INT
9045                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
9046                                         INTVAL (mask_rtx),
9047                                         result_mode, &complement_p))
9048                 break;
9049
9050               /* If the shifts are in the same direction, we add the
9051                  counts.  Otherwise, we subtract them.  */
9052               if ((code == ASHIFTRT || code == LSHIFTRT)
9053                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9054                 count += first_count;
9055               else
9056                 count -= first_count;
9057
9058               /* If COUNT is positive, the new shift is usually CODE,
9059                  except for the two exceptions below, in which case it is
9060                  FIRST_CODE.  If the count is negative, FIRST_CODE should
9061                  always be used  */
9062               if (count > 0
9063                   && ((first_code == ROTATE && code == ASHIFT)
9064                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
9065                 code = first_code;
9066               else if (count < 0)
9067                 code = first_code, count = - count;
9068
9069               varop = XEXP (varop, 0);
9070               continue;
9071             }
9072
9073           /* If we have (A << B << C) for any shift, we can convert this to
9074              (A << C << B).  This wins if A is a constant.  Only try this if
9075              B is not a constant.  */
9076
9077           else if (GET_CODE (varop) == code
9078                    && GET_CODE (XEXP (varop, 1)) != CONST_INT
9079                    && 0 != (new
9080                             = simplify_binary_operation (code, mode,
9081                                                          XEXP (varop, 0),
9082                                                          GEN_INT (count))))
9083             {
9084               varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9085               count = 0;
9086               continue;
9087             }
9088           break;
9089
9090         case NOT:
9091           /* Make this fit the case below.  */
9092           varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9093                                    GEN_INT (GET_MODE_MASK (mode)));
9094           continue;
9095
9096         case IOR:
9097         case AND:
9098         case XOR:
9099           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9100              with C the size of VAROP - 1 and the shift is logical if
9101              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9102              we have an (le X 0) operation.   If we have an arithmetic shift
9103              and STORE_FLAG_VALUE is 1 or we have a logical shift with
9104              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
9105
9106           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9107               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9108               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9109               && (code == LSHIFTRT || code == ASHIFTRT)
9110               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9111               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9112             {
9113               count = 0;
9114               varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9115                                        const0_rtx);
9116
9117               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9118                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9119
9120               continue;
9121             }
9122
9123           /* If we have (shift (logical)), move the logical to the outside
9124              to allow it to possibly combine with another logical and the
9125              shift to combine with another shift.  This also canonicalizes to
9126              what a ZERO_EXTRACT looks like.  Also, some machines have
9127              (and (shift)) insns.  */
9128
9129           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9130               && (new = simplify_binary_operation (code, result_mode,
9131                                                    XEXP (varop, 1),
9132                                                    GEN_INT (count))) != 0
9133               && GET_CODE(new) == CONST_INT
9134               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9135                                   INTVAL (new), result_mode, &complement_p))
9136             {
9137               varop = XEXP (varop, 0);
9138               continue;
9139             }
9140
9141           /* If we can't do that, try to simplify the shift in each arm of the
9142              logical expression, make a new logical expression, and apply
9143              the inverse distributive law.  */
9144           {
9145             rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9146                                             XEXP (varop, 0), count);
9147             rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9148                                             XEXP (varop, 1), count);
9149
9150             varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9151             varop = apply_distributive_law (varop);
9152
9153             count = 0;
9154           }
9155           break;
9156
9157         case EQ:
9158           /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9159              says that the sign bit can be tested, FOO has mode MODE, C is
9160              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9161              that may be nonzero.  */
9162           if (code == LSHIFTRT
9163               && XEXP (varop, 1) == const0_rtx
9164               && GET_MODE (XEXP (varop, 0)) == result_mode
9165               && count == GET_MODE_BITSIZE (result_mode) - 1
9166               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9167               && ((STORE_FLAG_VALUE
9168                    & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
9169               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9170               && merge_outer_ops (&outer_op, &outer_const, XOR,
9171                                   (HOST_WIDE_INT) 1, result_mode,
9172                                   &complement_p))
9173             {
9174               varop = XEXP (varop, 0);
9175               count = 0;
9176               continue;
9177             }
9178           break;
9179
9180         case NEG:
9181           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9182              than the number of bits in the mode is equivalent to A.  */
9183           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9184               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9185             {
9186               varop = XEXP (varop, 0);
9187               count = 0;
9188               continue;
9189             }
9190
9191           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9192              NEG outside to allow shifts to combine.  */
9193           if (code == ASHIFT
9194               && merge_outer_ops (&outer_op, &outer_const, NEG,
9195                                   (HOST_WIDE_INT) 0, result_mode,
9196                                   &complement_p))
9197             {
9198               varop = XEXP (varop, 0);
9199               continue;
9200             }
9201           break;
9202
9203         case PLUS:
9204           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9205              is one less than the number of bits in the mode is
9206              equivalent to (xor A 1).  */
9207           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9208               && XEXP (varop, 1) == constm1_rtx
9209               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9210               && merge_outer_ops (&outer_op, &outer_const, XOR,
9211                                   (HOST_WIDE_INT) 1, result_mode,
9212                                   &complement_p))
9213             {
9214               count = 0;
9215               varop = XEXP (varop, 0);
9216               continue;
9217             }
9218
9219           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9220              that might be nonzero in BAR are those being shifted out and those
9221              bits are known zero in FOO, we can replace the PLUS with FOO.
9222              Similarly in the other operand order.  This code occurs when
9223              we are computing the size of a variable-size array.  */
9224
9225           if ((code == ASHIFTRT || code == LSHIFTRT)
9226               && count < HOST_BITS_PER_WIDE_INT
9227               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9228               && (nonzero_bits (XEXP (varop, 1), result_mode)
9229                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9230             {
9231               varop = XEXP (varop, 0);
9232               continue;
9233             }
9234           else if ((code == ASHIFTRT || code == LSHIFTRT)
9235                    && count < HOST_BITS_PER_WIDE_INT
9236                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9237                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9238                             >> count)
9239                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9240                             & nonzero_bits (XEXP (varop, 1),
9241                                                  result_mode)))
9242             {
9243               varop = XEXP (varop, 1);
9244               continue;
9245             }
9246
9247           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9248           if (code == ASHIFT
9249               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9250               && (new = simplify_binary_operation (ASHIFT, result_mode,
9251                                                    XEXP (varop, 1),
9252                                                    GEN_INT (count))) != 0
9253               && GET_CODE(new) == CONST_INT
9254               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9255                                   INTVAL (new), result_mode, &complement_p))
9256             {
9257               varop = XEXP (varop, 0);
9258               continue;
9259             }
9260           break;
9261
9262         case MINUS:
9263           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9264              with C the size of VAROP - 1 and the shift is logical if
9265              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9266              we have a (gt X 0) operation.  If the shift is arithmetic with
9267              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9268              we have a (neg (gt X 0)) operation.  */
9269
9270           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9271               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9272               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9273               && (code == LSHIFTRT || code == ASHIFTRT)
9274               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9275               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9276               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9277             {
9278               count = 0;
9279               varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9280                                        const0_rtx);
9281
9282               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9283                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9284
9285               continue;
9286             }
9287           break;
9288
9289         case TRUNCATE:
9290           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9291              if the truncate does not affect the value.  */
9292           if (code == LSHIFTRT
9293               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9294               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9295               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9296                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9297                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9298             {
9299               rtx varop_inner = XEXP (varop, 0);
9300
9301               varop_inner = gen_rtx_combine (LSHIFTRT,
9302                                              GET_MODE (varop_inner),
9303                                              XEXP (varop_inner, 0),
9304                                              GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
9305               varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9306                                        varop_inner);
9307               count = 0;
9308               continue;
9309             }
9310           break;
9311
9312         default:
9313           break;
9314         }
9315
9316       break;
9317     }
9318
9319   /* We need to determine what mode to do the shift in.  If the shift is
9320      a right shift or ROTATE, we must always do it in the mode it was
9321      originally done in.  Otherwise, we can do it in MODE, the widest mode
9322      encountered.  The code we care about is that of the shift that will
9323      actually be done, not the shift that was originally requested.  */
9324   shift_mode
9325     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9326        ? result_mode : mode);
9327
9328   /* We have now finished analyzing the shift.  The result should be
9329      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9330      OUTER_OP is non-NIL, it is an operation that needs to be applied
9331      to the result of the shift.  OUTER_CONST is the relevant constant,
9332      but we must turn off all bits turned off in the shift.
9333
9334      If we were passed a value for X, see if we can use any pieces of
9335      it.  If not, make new rtx.  */
9336
9337   if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9338       && GET_CODE (XEXP (x, 1)) == CONST_INT
9339       && INTVAL (XEXP (x, 1)) == count)
9340     const_rtx = XEXP (x, 1);
9341   else
9342     const_rtx = GEN_INT (count);
9343
9344   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9345       && GET_MODE (XEXP (x, 0)) == shift_mode
9346       && SUBREG_REG (XEXP (x, 0)) == varop)
9347     varop = XEXP (x, 0);
9348   else if (GET_MODE (varop) != shift_mode)
9349     varop = gen_lowpart_for_combine (shift_mode, varop);
9350
9351   /* If we can't make the SUBREG, try to return what we were given.  */
9352   if (GET_CODE (varop) == CLOBBER)
9353     return x ? x : varop;
9354
9355   new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9356   if (new != 0)
9357     x = new;
9358   else
9359     {
9360       if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9361         x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9362
9363       SUBST (XEXP (x, 0), varop);
9364       SUBST (XEXP (x, 1), const_rtx);
9365     }
9366
9367   /* If we have an outer operation and we just made a shift, it is
9368      possible that we could have simplified the shift were it not
9369      for the outer operation.  So try to do the simplification
9370      recursively.  */
9371
9372   if (outer_op != NIL && GET_CODE (x) == code
9373       && GET_CODE (XEXP (x, 1)) == CONST_INT)
9374     x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9375                               INTVAL (XEXP (x, 1)));
9376
9377   /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9378      turn off all the bits that the shift would have turned off.  */
9379   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9380     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9381                                 GET_MODE_MASK (result_mode) >> orig_count);
9382
9383   /* Do the remainder of the processing in RESULT_MODE.  */
9384   x = gen_lowpart_for_combine (result_mode, x);
9385
9386   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9387      operation.  */
9388   if (complement_p)
9389     x = gen_unary (NOT, result_mode, result_mode, x);
9390
9391   if (outer_op != NIL)
9392     {
9393       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9394         outer_const = trunc_int_for_mode (outer_const, result_mode);
9395
9396       if (outer_op == AND)
9397         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9398       else if (outer_op == SET)
9399         /* This means that we have determined that the result is
9400            equivalent to a constant.  This should be rare.  */
9401         x = GEN_INT (outer_const);
9402       else if (GET_RTX_CLASS (outer_op) == '1')
9403         x = gen_unary (outer_op, result_mode, result_mode, x);
9404       else
9405         x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9406     }
9407
9408   return x;
9409 }
9410 \f
9411 /* Like recog, but we receive the address of a pointer to a new pattern.
9412    We try to match the rtx that the pointer points to.
9413    If that fails, we may try to modify or replace the pattern,
9414    storing the replacement into the same pointer object.
9415
9416    Modifications include deletion or addition of CLOBBERs.
9417
9418    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9419    the CLOBBERs are placed.
9420
9421    The value is the final insn code from the pattern ultimately matched,
9422    or -1.  */
9423
9424 static int
9425 recog_for_combine (pnewpat, insn, pnotes)
9426      rtx *pnewpat;
9427      rtx insn;
9428      rtx *pnotes;
9429 {
9430   register rtx pat = *pnewpat;
9431   int insn_code_number;
9432   int num_clobbers_to_add = 0;
9433   int i;
9434   rtx notes = 0;
9435
9436   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9437      we use to indicate that something didn't match.  If we find such a
9438      thing, force rejection.  */
9439   if (GET_CODE (pat) == PARALLEL)
9440     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9441       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9442           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9443         return -1;
9444
9445   /* Is the result of combination a valid instruction?  */
9446   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9447
9448   /* If it isn't, there is the possibility that we previously had an insn
9449      that clobbered some register as a side effect, but the combined
9450      insn doesn't need to do that.  So try once more without the clobbers
9451      unless this represents an ASM insn.  */
9452
9453   if (insn_code_number < 0 && ! check_asm_operands (pat)
9454       && GET_CODE (pat) == PARALLEL)
9455     {
9456       int pos;
9457
9458       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9459         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9460           {
9461             if (i != pos)
9462               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9463             pos++;
9464           }
9465
9466       SUBST_INT (XVECLEN (pat, 0), pos);
9467
9468       if (pos == 1)
9469         pat = XVECEXP (pat, 0, 0);
9470
9471       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9472     }
9473
9474   /* If we had any clobbers to add, make a new pattern than contains
9475      them.  Then check to make sure that all of them are dead.  */
9476   if (num_clobbers_to_add)
9477     {
9478       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9479                                      gen_rtvec (GET_CODE (pat) == PARALLEL
9480                                                 ? (XVECLEN (pat, 0)
9481                                                    + num_clobbers_to_add)
9482                                                 : num_clobbers_to_add + 1));
9483
9484       if (GET_CODE (pat) == PARALLEL)
9485         for (i = 0; i < XVECLEN (pat, 0); i++)
9486           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9487       else
9488         XVECEXP (newpat, 0, 0) = pat;
9489
9490       add_clobbers (newpat, insn_code_number);
9491
9492       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9493            i < XVECLEN (newpat, 0); i++)
9494         {
9495           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9496               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9497             return -1;
9498           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9499                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9500         }
9501       pat = newpat;
9502     }
9503
9504   *pnewpat = pat;
9505   *pnotes = notes;
9506
9507   return insn_code_number;
9508 }
9509 \f
9510 /* Like gen_lowpart but for use by combine.  In combine it is not possible
9511    to create any new pseudoregs.  However, it is safe to create
9512    invalid memory addresses, because combine will try to recognize
9513    them and all they will do is make the combine attempt fail.
9514
9515    If for some reason this cannot do its job, an rtx
9516    (clobber (const_int 0)) is returned.
9517    An insn containing that will not be recognized.  */
9518
9519 #undef gen_lowpart
9520
9521 static rtx
9522 gen_lowpart_for_combine (mode, x)
9523      enum machine_mode mode;
9524      register rtx x;
9525 {
9526   rtx result;
9527
9528   if (GET_MODE (x) == mode)
9529     return x;
9530
9531   /* We can only support MODE being wider than a word if X is a
9532      constant integer or has a mode the same size.  */
9533
9534   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9535       && ! ((GET_MODE (x) == VOIDmode
9536              && (GET_CODE (x) == CONST_INT
9537                  || GET_CODE (x) == CONST_DOUBLE))
9538             || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9539     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9540
9541   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9542      won't know what to do.  So we will strip off the SUBREG here and
9543      process normally.  */
9544   if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9545     {
9546       x = SUBREG_REG (x);
9547       if (GET_MODE (x) == mode)
9548         return x;
9549     }
9550
9551   result = gen_lowpart_common (mode, x);
9552   if (result != 0
9553       && GET_CODE (result) == SUBREG
9554       && GET_CODE (SUBREG_REG (result)) == REG
9555       && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9556       && (GET_MODE_SIZE (GET_MODE (result))
9557           != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9558     REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9559
9560   if (result)
9561     return result;
9562
9563   if (GET_CODE (x) == MEM)
9564     {
9565       register int offset = 0;
9566       rtx new;
9567
9568       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9569          address.  */
9570       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9571         return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9572
9573       /* If we want to refer to something bigger than the original memref,
9574          generate a perverse subreg instead.  That will force a reload
9575          of the original memref X.  */
9576       if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9577         return gen_rtx_SUBREG (mode, x, 0);
9578
9579       if (WORDS_BIG_ENDIAN)
9580         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9581                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9582
9583       if (BYTES_BIG_ENDIAN)
9584         {
9585           /* Adjust the address so that the address-after-the-data is
9586              unchanged.  */
9587           offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9588                      - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9589         }
9590       new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9591       RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9592       MEM_COPY_ATTRIBUTES (new, x);
9593       return new;
9594     }
9595
9596   /* If X is a comparison operator, rewrite it in a new mode.  This
9597      probably won't match, but may allow further simplifications.  */
9598   else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9599     return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9600
9601   /* If we couldn't simplify X any other way, just enclose it in a
9602      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9603      include an explicit SUBREG or we may simplify it further in combine.  */
9604   else
9605     {
9606       int word = 0;
9607
9608       if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9609         word = ((GET_MODE_SIZE (GET_MODE (x))
9610                  - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9611                 / UNITS_PER_WORD);
9612       return gen_rtx_SUBREG (mode, x, word);
9613     }
9614 }
9615 \f
9616 /* Make an rtx expression.  This is a subset of gen_rtx and only supports
9617    expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9618
9619    If the identical expression was previously in the insn (in the undobuf),
9620    it will be returned.  Only if it is not found will a new expression
9621    be made.  */
9622
9623 /*VARARGS2*/
9624 static rtx
9625 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9626 {
9627 #ifndef ANSI_PROTOTYPES
9628   enum rtx_code code;
9629   enum machine_mode mode;
9630 #endif
9631   va_list p;
9632   int n_args;
9633   rtx args[3];
9634   int j;
9635   const char *fmt;
9636   rtx rt;
9637   struct undo *undo;
9638
9639   VA_START (p, mode);
9640
9641 #ifndef ANSI_PROTOTYPES
9642   code = va_arg (p, enum rtx_code);
9643   mode = va_arg (p, enum machine_mode);
9644 #endif
9645
9646   n_args = GET_RTX_LENGTH (code);
9647   fmt = GET_RTX_FORMAT (code);
9648
9649   if (n_args == 0 || n_args > 3)
9650     abort ();
9651
9652   /* Get each arg and verify that it is supposed to be an expression.  */
9653   for (j = 0; j < n_args; j++)
9654     {
9655       if (*fmt++ != 'e')
9656         abort ();
9657
9658       args[j] = va_arg (p, rtx);
9659     }
9660
9661   va_end (p);
9662
9663   /* See if this is in undobuf.  Be sure we don't use objects that came
9664      from another insn; this could produce circular rtl structures.  */
9665
9666   for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9667     if (!undo->is_int
9668         && GET_CODE (undo->old_contents.r) == code
9669         && GET_MODE (undo->old_contents.r) == mode)
9670       {
9671         for (j = 0; j < n_args; j++)
9672           if (XEXP (undo->old_contents.r, j) != args[j])
9673             break;
9674
9675         if (j == n_args)
9676           return undo->old_contents.r;
9677       }
9678
9679   /* Otherwise make a new rtx.  We know we have 1, 2, or 3 args.
9680      Use rtx_alloc instead of gen_rtx because it's faster on RISC.  */
9681   rt = rtx_alloc (code);
9682   PUT_MODE (rt, mode);
9683   XEXP (rt, 0) = args[0];
9684   if (n_args > 1)
9685     {
9686       XEXP (rt, 1) = args[1];
9687       if (n_args > 2)
9688         XEXP (rt, 2) = args[2];
9689     }
9690   return rt;
9691 }
9692
9693 /* These routines make binary and unary operations by first seeing if they
9694    fold; if not, a new expression is allocated.  */
9695
9696 static rtx
9697 gen_binary (code, mode, op0, op1)
9698      enum rtx_code code;
9699      enum machine_mode mode;
9700      rtx op0, op1;
9701 {
9702   rtx result;
9703   rtx tem;
9704
9705   if (GET_RTX_CLASS (code) == 'c'
9706       && (GET_CODE (op0) == CONST_INT
9707           || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9708     tem = op0, op0 = op1, op1 = tem;
9709
9710   if (GET_RTX_CLASS (code) == '<')
9711     {
9712       enum machine_mode op_mode = GET_MODE (op0);
9713
9714       /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9715          just (REL_OP X Y).  */
9716       if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9717         {
9718           op1 = XEXP (op0, 1);
9719           op0 = XEXP (op0, 0);
9720           op_mode = GET_MODE (op0);
9721         }
9722
9723       if (op_mode == VOIDmode)
9724         op_mode = GET_MODE (op1);
9725       result = simplify_relational_operation (code, op_mode, op0, op1);
9726     }
9727   else
9728     result = simplify_binary_operation (code, mode, op0, op1);
9729
9730   if (result)
9731     return result;
9732
9733   /* Put complex operands first and constants second.  */
9734   if (GET_RTX_CLASS (code) == 'c'
9735       && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9736           || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9737               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9738           || (GET_CODE (op0) == SUBREG
9739               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9740               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9741     return gen_rtx_combine (code, mode, op1, op0);
9742
9743   /* If we are turning off bits already known off in OP0, we need not do
9744      an AND.  */
9745   else if (code == AND && GET_CODE (op1) == CONST_INT
9746            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9747            && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9748     return op0;
9749
9750   return gen_rtx_combine (code, mode, op0, op1);
9751 }
9752
9753 static rtx
9754 gen_unary (code, mode, op0_mode, op0)
9755      enum rtx_code code;
9756      enum machine_mode mode, op0_mode;
9757      rtx op0;
9758 {
9759   rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9760
9761   if (result)
9762     return result;
9763
9764   return gen_rtx_combine (code, mode, op0);
9765 }
9766 \f
9767 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9768    comparison code that will be tested.
9769
9770    The result is a possibly different comparison code to use.  *POP0 and
9771    *POP1 may be updated.
9772
9773    It is possible that we might detect that a comparison is either always
9774    true or always false.  However, we do not perform general constant
9775    folding in combine, so this knowledge isn't useful.  Such tautologies
9776    should have been detected earlier.  Hence we ignore all such cases.  */
9777
9778 static enum rtx_code
9779 simplify_comparison (code, pop0, pop1)
9780      enum rtx_code code;
9781      rtx *pop0;
9782      rtx *pop1;
9783 {
9784   rtx op0 = *pop0;
9785   rtx op1 = *pop1;
9786   rtx tem, tem1;
9787   int i;
9788   enum machine_mode mode, tmode;
9789
9790   /* Try a few ways of applying the same transformation to both operands.  */
9791   while (1)
9792     {
9793 #ifndef WORD_REGISTER_OPERATIONS
9794       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9795          so check specially.  */
9796       if (code != GTU && code != GEU && code != LTU && code != LEU
9797           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9798           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9799           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9800           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9801           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9802           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9803               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9804           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9805           && GET_CODE (XEXP (op1, 1)) == CONST_INT
9806           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9807           && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9808           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9809           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9810           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9811           && (INTVAL (XEXP (op0, 1))
9812               == (GET_MODE_BITSIZE (GET_MODE (op0))
9813                   - (GET_MODE_BITSIZE
9814                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9815         {
9816           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9817           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9818         }
9819 #endif
9820
9821       /* If both operands are the same constant shift, see if we can ignore the
9822          shift.  We can if the shift is a rotate or if the bits shifted out of
9823          this shift are known to be zero for both inputs and if the type of
9824          comparison is compatible with the shift.  */
9825       if (GET_CODE (op0) == GET_CODE (op1)
9826           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9827           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9828               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9829                   && (code != GT && code != LT && code != GE && code != LE))
9830               || (GET_CODE (op0) == ASHIFTRT
9831                   && (code != GTU && code != LTU
9832                       && code != GEU && code != GEU)))
9833           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9834           && INTVAL (XEXP (op0, 1)) >= 0
9835           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9836           && XEXP (op0, 1) == XEXP (op1, 1))
9837         {
9838           enum machine_mode mode = GET_MODE (op0);
9839           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9840           int shift_count = INTVAL (XEXP (op0, 1));
9841
9842           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9843             mask &= (mask >> shift_count) << shift_count;
9844           else if (GET_CODE (op0) == ASHIFT)
9845             mask = (mask & (mask << shift_count)) >> shift_count;
9846
9847           if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9848               && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9849             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9850           else
9851             break;
9852         }
9853
9854       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9855          SUBREGs are of the same mode, and, in both cases, the AND would
9856          be redundant if the comparison was done in the narrower mode,
9857          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9858          and the operand's possibly nonzero bits are 0xffffff01; in that case
9859          if we only care about QImode, we don't need the AND).  This case
9860          occurs if the output mode of an scc insn is not SImode and
9861          STORE_FLAG_VALUE == 1 (e.g., the 386).
9862
9863          Similarly, check for a case where the AND's are ZERO_EXTEND
9864          operations from some narrower mode even though a SUBREG is not
9865          present.  */
9866
9867       else if  (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9868                 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9869                 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9870         {
9871           rtx inner_op0 = XEXP (op0, 0);
9872           rtx inner_op1 = XEXP (op1, 0);
9873           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9874           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9875           int changed = 0;
9876
9877           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9878               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9879                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9880               && (GET_MODE (SUBREG_REG (inner_op0))
9881                   == GET_MODE (SUBREG_REG (inner_op1)))
9882               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9883                   <= HOST_BITS_PER_WIDE_INT)
9884               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9885                                              GET_MODE (SUBREG_REG (inner_op0)))))
9886               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9887                                              GET_MODE (SUBREG_REG (inner_op1))))))
9888             {
9889               op0 = SUBREG_REG (inner_op0);
9890               op1 = SUBREG_REG (inner_op1);
9891
9892               /* The resulting comparison is always unsigned since we masked
9893                  off the original sign bit.  */
9894               code = unsigned_condition (code);
9895
9896               changed = 1;
9897             }
9898
9899           else if (c0 == c1)
9900             for (tmode = GET_CLASS_NARROWEST_MODE
9901                  (GET_MODE_CLASS (GET_MODE (op0)));
9902                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9903               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9904                 {
9905                   op0 = gen_lowpart_for_combine (tmode, inner_op0);
9906                   op1 = gen_lowpart_for_combine (tmode, inner_op1);
9907                   code = unsigned_condition (code);
9908                   changed = 1;
9909                   break;
9910                 }
9911
9912           if (! changed)
9913             break;
9914         }
9915
9916       /* If both operands are NOT, we can strip off the outer operation
9917          and adjust the comparison code for swapped operands; similarly for
9918          NEG, except that this must be an equality comparison.  */
9919       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9920                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9921                    && (code == EQ || code == NE)))
9922         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9923
9924       else
9925         break;
9926     }
9927
9928   /* If the first operand is a constant, swap the operands and adjust the
9929      comparison code appropriately, but don't do this if the second operand
9930      is already a constant integer.  */
9931   if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9932     {
9933       tem = op0, op0 = op1, op1 = tem;
9934       code = swap_condition (code);
9935     }
9936
9937   /* We now enter a loop during which we will try to simplify the comparison.
9938      For the most part, we only are concerned with comparisons with zero,
9939      but some things may really be comparisons with zero but not start
9940      out looking that way.  */
9941
9942   while (GET_CODE (op1) == CONST_INT)
9943     {
9944       enum machine_mode mode = GET_MODE (op0);
9945       int mode_width = GET_MODE_BITSIZE (mode);
9946       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9947       int equality_comparison_p;
9948       int sign_bit_comparison_p;
9949       int unsigned_comparison_p;
9950       HOST_WIDE_INT const_op;
9951
9952       /* We only want to handle integral modes.  This catches VOIDmode,
9953          CCmode, and the floating-point modes.  An exception is that we
9954          can handle VOIDmode if OP0 is a COMPARE or a comparison
9955          operation.  */
9956
9957       if (GET_MODE_CLASS (mode) != MODE_INT
9958           && ! (mode == VOIDmode
9959                 && (GET_CODE (op0) == COMPARE
9960                     || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9961         break;
9962
9963       /* Get the constant we are comparing against and turn off all bits
9964          not on in our mode.  */
9965       const_op = INTVAL (op1);
9966       if (mode_width <= HOST_BITS_PER_WIDE_INT)
9967         const_op &= mask;
9968
9969       /* If we are comparing against a constant power of two and the value
9970          being compared can only have that single bit nonzero (e.g., it was
9971          `and'ed with that bit), we can replace this with a comparison
9972          with zero.  */
9973       if (const_op
9974           && (code == EQ || code == NE || code == GE || code == GEU
9975               || code == LT || code == LTU)
9976           && mode_width <= HOST_BITS_PER_WIDE_INT
9977           && exact_log2 (const_op) >= 0
9978           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9979         {
9980           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9981           op1 = const0_rtx, const_op = 0;
9982         }
9983
9984       /* Similarly, if we are comparing a value known to be either -1 or
9985          0 with -1, change it to the opposite comparison against zero.  */
9986
9987       if (const_op == -1
9988           && (code == EQ || code == NE || code == GT || code == LE
9989               || code == GEU || code == LTU)
9990           && num_sign_bit_copies (op0, mode) == mode_width)
9991         {
9992           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9993           op1 = const0_rtx, const_op = 0;
9994         }
9995
9996       /* Do some canonicalizations based on the comparison code.  We prefer
9997          comparisons against zero and then prefer equality comparisons.
9998          If we can reduce the size of a constant, we will do that too.  */
9999
10000       switch (code)
10001         {
10002         case LT:
10003           /* < C is equivalent to <= (C - 1) */
10004           if (const_op > 0)
10005             {
10006               const_op -= 1;
10007               op1 = GEN_INT (const_op);
10008               code = LE;
10009               /* ... fall through to LE case below.  */
10010             }
10011           else
10012             break;
10013
10014         case LE:
10015           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10016           if (const_op < 0)
10017             {
10018               const_op += 1;
10019               op1 = GEN_INT (const_op);
10020               code = LT;
10021             }
10022
10023           /* If we are doing a <= 0 comparison on a value known to have
10024              a zero sign bit, we can replace this with == 0.  */
10025           else if (const_op == 0
10026                    && mode_width <= HOST_BITS_PER_WIDE_INT
10027                    && (nonzero_bits (op0, mode)
10028                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10029             code = EQ;
10030           break;
10031
10032         case GE:
10033           /* >= C is equivalent to > (C - 1).  */
10034           if (const_op > 0)
10035             {
10036               const_op -= 1;
10037               op1 = GEN_INT (const_op);
10038               code = GT;
10039               /* ... fall through to GT below.  */
10040             }
10041           else
10042             break;
10043
10044         case GT:
10045           /* > C is equivalent to >= (C + 1); we do this for C < 0*/
10046           if (const_op < 0)
10047             {
10048               const_op += 1;
10049               op1 = GEN_INT (const_op);
10050               code = GE;
10051             }
10052
10053           /* If we are doing a > 0 comparison on a value known to have
10054              a zero sign bit, we can replace this with != 0.  */
10055           else if (const_op == 0
10056                    && mode_width <= HOST_BITS_PER_WIDE_INT
10057                    && (nonzero_bits (op0, mode)
10058                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10059             code = NE;
10060           break;
10061
10062         case LTU:
10063           /* < C is equivalent to <= (C - 1).  */
10064           if (const_op > 0)
10065             {
10066               const_op -= 1;
10067               op1 = GEN_INT (const_op);
10068               code = LEU;
10069               /* ... fall through ...  */
10070             }
10071
10072           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10073           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10074                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10075             {
10076               const_op = 0, op1 = const0_rtx;
10077               code = GE;
10078               break;
10079             }
10080           else
10081             break;
10082
10083         case LEU:
10084           /* unsigned <= 0 is equivalent to == 0 */
10085           if (const_op == 0)
10086             code = EQ;
10087
10088           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10089           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10090                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10091             {
10092               const_op = 0, op1 = const0_rtx;
10093               code = GE;
10094             }
10095           break;
10096
10097         case GEU:
10098           /* >= C is equivalent to < (C - 1).  */
10099           if (const_op > 1)
10100             {
10101               const_op -= 1;
10102               op1 = GEN_INT (const_op);
10103               code = GTU;
10104               /* ... fall through ...  */
10105             }
10106
10107           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10108           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10109                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10110             {
10111               const_op = 0, op1 = const0_rtx;
10112               code = LT;
10113               break;
10114             }
10115           else
10116             break;
10117
10118         case GTU:
10119           /* unsigned > 0 is equivalent to != 0 */
10120           if (const_op == 0)
10121             code = NE;
10122
10123           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10124           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10125                     && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10126             {
10127               const_op = 0, op1 = const0_rtx;
10128               code = LT;
10129             }
10130           break;
10131
10132         default:
10133           break;
10134         }
10135
10136       /* Compute some predicates to simplify code below.  */
10137
10138       equality_comparison_p = (code == EQ || code == NE);
10139       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10140       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10141                                || code == GEU);
10142
10143       /* If this is a sign bit comparison and we can do arithmetic in
10144          MODE, say that we will only be needing the sign bit of OP0.  */
10145       if (sign_bit_comparison_p
10146           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10147         op0 = force_to_mode (op0, mode,
10148                              ((HOST_WIDE_INT) 1
10149                               << (GET_MODE_BITSIZE (mode) - 1)),
10150                              NULL_RTX, 0);
10151
10152       /* Now try cases based on the opcode of OP0.  If none of the cases
10153          does a "continue", we exit this loop immediately after the
10154          switch.  */
10155
10156       switch (GET_CODE (op0))
10157         {
10158         case ZERO_EXTRACT:
10159           /* If we are extracting a single bit from a variable position in
10160              a constant that has only a single bit set and are comparing it
10161              with zero, we can convert this into an equality comparison
10162              between the position and the location of the single bit.  */
10163
10164           if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10165               && XEXP (op0, 1) == const1_rtx
10166               && equality_comparison_p && const_op == 0
10167               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10168             {
10169               if (BITS_BIG_ENDIAN)
10170                 {
10171 #ifdef HAVE_extzv
10172                   mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10173                   if (mode == VOIDmode)
10174                     mode = word_mode;
10175                   i = (GET_MODE_BITSIZE (mode) - 1 - i);
10176 #else
10177                   i = BITS_PER_WORD - 1 - i;
10178 #endif
10179                 }
10180
10181               op0 = XEXP (op0, 2);
10182               op1 = GEN_INT (i);
10183               const_op = i;
10184
10185               /* Result is nonzero iff shift count is equal to I.  */
10186               code = reverse_condition (code);
10187               continue;
10188             }
10189
10190           /* ... fall through ...  */
10191
10192         case SIGN_EXTRACT:
10193           tem = expand_compound_operation (op0);
10194           if (tem != op0)
10195             {
10196               op0 = tem;
10197               continue;
10198             }
10199           break;
10200
10201         case NOT:
10202           /* If testing for equality, we can take the NOT of the constant.  */
10203           if (equality_comparison_p
10204               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10205             {
10206               op0 = XEXP (op0, 0);
10207               op1 = tem;
10208               continue;
10209             }
10210
10211           /* If just looking at the sign bit, reverse the sense of the
10212              comparison.  */
10213           if (sign_bit_comparison_p)
10214             {
10215               op0 = XEXP (op0, 0);
10216               code = (code == GE ? LT : GE);
10217               continue;
10218             }
10219           break;
10220
10221         case NEG:
10222           /* If testing for equality, we can take the NEG of the constant.  */
10223           if (equality_comparison_p
10224               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10225             {
10226               op0 = XEXP (op0, 0);
10227               op1 = tem;
10228               continue;
10229             }
10230
10231           /* The remaining cases only apply to comparisons with zero.  */
10232           if (const_op != 0)
10233             break;
10234
10235           /* When X is ABS or is known positive,
10236              (neg X) is < 0 if and only if X != 0.  */
10237
10238           if (sign_bit_comparison_p
10239               && (GET_CODE (XEXP (op0, 0)) == ABS
10240                   || (mode_width <= HOST_BITS_PER_WIDE_INT
10241                       && (nonzero_bits (XEXP (op0, 0), mode)
10242                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10243             {
10244               op0 = XEXP (op0, 0);
10245               code = (code == LT ? NE : EQ);
10246               continue;
10247             }
10248
10249           /* If we have NEG of something whose two high-order bits are the
10250              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
10251           if (num_sign_bit_copies (op0, mode) >= 2)
10252             {
10253               op0 = XEXP (op0, 0);
10254               code = swap_condition (code);
10255               continue;
10256             }
10257           break;
10258
10259         case ROTATE:
10260           /* If we are testing equality and our count is a constant, we
10261              can perform the inverse operation on our RHS.  */
10262           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10263               && (tem = simplify_binary_operation (ROTATERT, mode,
10264                                                    op1, XEXP (op0, 1))) != 0)
10265             {
10266               op0 = XEXP (op0, 0);
10267               op1 = tem;
10268               continue;
10269             }
10270
10271           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10272              a particular bit.  Convert it to an AND of a constant of that
10273              bit.  This will be converted into a ZERO_EXTRACT.  */
10274           if (const_op == 0 && sign_bit_comparison_p
10275               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10276               && mode_width <= HOST_BITS_PER_WIDE_INT)
10277             {
10278               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10279                                             ((HOST_WIDE_INT) 1
10280                                              << (mode_width - 1
10281                                                  - INTVAL (XEXP (op0, 1)))));
10282               code = (code == LT ? NE : EQ);
10283               continue;
10284             }
10285
10286           /* ... fall through ...  */
10287
10288         case ABS:
10289           /* ABS is ignorable inside an equality comparison with zero.  */
10290           if (const_op == 0 && equality_comparison_p)
10291             {
10292               op0 = XEXP (op0, 0);
10293               continue;
10294             }
10295           break;
10296
10297
10298         case SIGN_EXTEND:
10299           /* Can simplify (compare (zero/sign_extend FOO) CONST)
10300              to (compare FOO CONST) if CONST fits in FOO's mode and we
10301              are either testing inequality or have an unsigned comparison
10302              with ZERO_EXTEND or a signed comparison with SIGN_EXTEND.  */
10303           if (! unsigned_comparison_p
10304               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10305                   <= HOST_BITS_PER_WIDE_INT)
10306               && ((unsigned HOST_WIDE_INT) const_op
10307                   < (((unsigned HOST_WIDE_INT) 1
10308                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10309             {
10310               op0 = XEXP (op0, 0);
10311               continue;
10312             }
10313           break;
10314
10315         case SUBREG:
10316           /* Check for the case where we are comparing A - C1 with C2,
10317              both constants are smaller than 1/2 the maximum positive
10318              value in MODE, and the comparison is equality or unsigned.
10319              In that case, if A is either zero-extended to MODE or has
10320              sufficient sign bits so that the high-order bit in MODE
10321              is a copy of the sign in the inner mode, we can prove that it is
10322              safe to do the operation in the wider mode.  This simplifies
10323              many range checks.  */
10324
10325           if (mode_width <= HOST_BITS_PER_WIDE_INT
10326               && subreg_lowpart_p (op0)
10327               && GET_CODE (SUBREG_REG (op0)) == PLUS
10328               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10329               && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10330               && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10331                   < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10332               && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10333               && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10334                                       GET_MODE (SUBREG_REG (op0)))
10335                         & ~ GET_MODE_MASK (mode))
10336                   || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10337                                            GET_MODE (SUBREG_REG (op0)))
10338                       > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10339                          - GET_MODE_BITSIZE (mode)))))
10340             {
10341               op0 = SUBREG_REG (op0);
10342               continue;
10343             }
10344
10345           /* If the inner mode is narrower and we are extracting the low part,
10346              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10347           if (subreg_lowpart_p (op0)
10348               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10349             /* Fall through */ ;
10350           else
10351             break;
10352
10353           /* ... fall through ...  */
10354
10355         case ZERO_EXTEND:
10356           if ((unsigned_comparison_p || equality_comparison_p)
10357               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10358                   <= HOST_BITS_PER_WIDE_INT)
10359               && ((unsigned HOST_WIDE_INT) const_op
10360                   < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10361             {
10362               op0 = XEXP (op0, 0);
10363               continue;
10364             }
10365           break;
10366
10367         case PLUS:
10368           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10369              this for equality comparisons due to pathological cases involving
10370              overflows.  */
10371           if (equality_comparison_p
10372               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10373                                                         op1, XEXP (op0, 1))))
10374             {
10375               op0 = XEXP (op0, 0);
10376               op1 = tem;
10377               continue;
10378             }
10379
10380           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10381           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10382               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10383             {
10384               op0 = XEXP (XEXP (op0, 0), 0);
10385               code = (code == LT ? EQ : NE);
10386               continue;
10387             }
10388           break;
10389
10390         case MINUS:
10391           /* (op (minus A B) 0) -> (op A B) */
10392           if (op1 == const0_rtx)
10393             {
10394               op1 = XEXP (op0, 1);
10395               op0 = XEXP (op0, 0);
10396               continue;
10397             }
10398
10399           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10400              (eq B (minus A C)), whichever simplifies.  We can only do
10401              this for equality comparisons due to pathological cases involving
10402              overflows.  */
10403           if (equality_comparison_p
10404               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10405                                                         XEXP (op0, 1), op1)))
10406             {
10407               op0 = XEXP (op0, 0);
10408               op1 = tem;
10409               continue;
10410             }
10411
10412           if (equality_comparison_p
10413               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10414                                                         XEXP (op0, 0), op1)))
10415             {
10416               op0 = XEXP (op0, 1);
10417               op1 = tem;
10418               continue;
10419             }
10420
10421           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10422              of bits in X minus 1, is one iff X > 0.  */
10423           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10424               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10425               && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10426               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10427             {
10428               op0 = XEXP (op0, 1);
10429               code = (code == GE ? LE : GT);
10430               continue;
10431             }
10432           break;
10433
10434         case XOR:
10435           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10436              if C is zero or B is a constant.  */
10437           if (equality_comparison_p
10438               && 0 != (tem = simplify_binary_operation (XOR, mode,
10439                                                         XEXP (op0, 1), op1)))
10440             {
10441               op0 = XEXP (op0, 0);
10442               op1 = tem;
10443               continue;
10444             }
10445           break;
10446
10447         case EQ:  case NE:
10448         case LT:  case LTU:  case LE:  case LEU:
10449         case GT:  case GTU:  case GE:  case GEU:
10450           /* We can't do anything if OP0 is a condition code value, rather
10451              than an actual data value.  */
10452           if (const_op != 0
10453 #ifdef HAVE_cc0
10454               || XEXP (op0, 0) == cc0_rtx
10455 #endif
10456               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10457             break;
10458
10459           /* Get the two operands being compared.  */
10460           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10461             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10462           else
10463             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10464
10465           /* Check for the cases where we simply want the result of the
10466              earlier test or the opposite of that result.  */
10467           if (code == NE
10468               || (code == EQ && reversible_comparison_p (op0))
10469               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10470                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10471                   && (STORE_FLAG_VALUE
10472                       & (((HOST_WIDE_INT) 1
10473                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10474                   && (code == LT
10475                       || (code == GE && reversible_comparison_p (op0)))))
10476             {
10477               code = (code == LT || code == NE
10478                       ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10479               op0 = tem, op1 = tem1;
10480               continue;
10481             }
10482           break;
10483
10484         case IOR:
10485           /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10486              iff X <= 0.  */
10487           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10488               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10489               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10490             {
10491               op0 = XEXP (op0, 1);
10492               code = (code == GE ? GT : LE);
10493               continue;
10494             }
10495           break;
10496
10497         case AND:
10498           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10499              will be converted to a ZERO_EXTRACT later.  */
10500           if (const_op == 0 && equality_comparison_p
10501               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10502               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10503             {
10504               op0 = simplify_and_const_int
10505                 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10506                                              XEXP (op0, 1),
10507                                              XEXP (XEXP (op0, 0), 1)),
10508                  (HOST_WIDE_INT) 1);
10509               continue;
10510             }
10511
10512           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10513              zero and X is a comparison and C1 and C2 describe only bits set
10514              in STORE_FLAG_VALUE, we can compare with X.  */
10515           if (const_op == 0 && equality_comparison_p
10516               && mode_width <= HOST_BITS_PER_WIDE_INT
10517               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10518               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10519               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10520               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10521               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10522             {
10523               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10524                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10525               if ((~ STORE_FLAG_VALUE & mask) == 0
10526                   && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10527                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10528                           && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10529                 {
10530                   op0 = XEXP (XEXP (op0, 0), 0);
10531                   continue;
10532                 }
10533             }
10534
10535           /* If we are doing an equality comparison of an AND of a bit equal
10536              to the sign bit, replace this with a LT or GE comparison of
10537              the underlying value.  */
10538           if (equality_comparison_p
10539               && const_op == 0
10540               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10541               && mode_width <= HOST_BITS_PER_WIDE_INT
10542               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10543                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10544             {
10545               op0 = XEXP (op0, 0);
10546               code = (code == EQ ? GE : LT);
10547               continue;
10548             }
10549
10550           /* If this AND operation is really a ZERO_EXTEND from a narrower
10551              mode, the constant fits within that mode, and this is either an
10552              equality or unsigned comparison, try to do this comparison in
10553              the narrower mode.  */
10554           if ((equality_comparison_p || unsigned_comparison_p)
10555               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10556               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10557                                    & GET_MODE_MASK (mode))
10558                                   + 1)) >= 0
10559               && const_op >> i == 0
10560               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10561             {
10562               op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10563               continue;
10564             }
10565
10566           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10567              in both M1 and M2 and the SUBREG is either paradoxical or
10568              represents the low part, permute the SUBREG and the AND and
10569              try again.  */
10570           if (GET_CODE (XEXP (op0, 0)) == SUBREG
10571               && (0
10572 #ifdef WORD_REGISTER_OPERATIONS
10573                   || ((mode_width
10574                        > (GET_MODE_BITSIZE
10575                            (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10576                       && mode_width <= BITS_PER_WORD)
10577 #endif
10578                   || ((mode_width
10579                        <= (GET_MODE_BITSIZE
10580                            (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10581                       && subreg_lowpart_p (XEXP (op0, 0))))
10582 #ifndef WORD_REGISTER_OPERATIONS
10583               /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10584                  is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10585                  As originally written the upper bits have a defined value
10586                  due to the AND operation.  However, if we commute the AND
10587                  inside the SUBREG then they no longer have defined values
10588                  and the meaning of the code has been changed.  */
10589               && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10590                   <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10591 #endif
10592               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10593               && mode_width <= HOST_BITS_PER_WIDE_INT
10594               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10595                   <= HOST_BITS_PER_WIDE_INT)
10596               && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10597               && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10598                        & INTVAL (XEXP (op0, 1)))
10599               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10600               && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10601                   != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10602
10603             {
10604               op0
10605                 = gen_lowpart_for_combine
10606                   (mode,
10607                    gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10608                                SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10609               continue;
10610             }
10611
10612           break;
10613
10614         case ASHIFT:
10615           /* If we have (compare (ashift FOO N) (const_int C)) and
10616              the high order N bits of FOO (N+1 if an inequality comparison)
10617              are known to be zero, we can do this by comparing FOO with C
10618              shifted right N bits so long as the low-order N bits of C are
10619              zero.  */
10620           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10621               && INTVAL (XEXP (op0, 1)) >= 0
10622               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10623                   < HOST_BITS_PER_WIDE_INT)
10624               && ((const_op
10625                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10626               && mode_width <= HOST_BITS_PER_WIDE_INT
10627               && (nonzero_bits (XEXP (op0, 0), mode)
10628                   & ~ (mask >> (INTVAL (XEXP (op0, 1))
10629                                 + ! equality_comparison_p))) == 0)
10630             {
10631               /* We must perform a logical shift, not an arithmetic one,
10632                  as we want the top N bits of C to be zero.  */
10633               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10634
10635               temp >>= INTVAL (XEXP (op0, 1));
10636               op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10637               op0 = XEXP (op0, 0);
10638               continue;
10639             }
10640
10641           /* If we are doing a sign bit comparison, it means we are testing
10642              a particular bit.  Convert it to the appropriate AND.  */
10643           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10644               && mode_width <= HOST_BITS_PER_WIDE_INT)
10645             {
10646               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10647                                             ((HOST_WIDE_INT) 1
10648                                              << (mode_width - 1
10649                                                  - INTVAL (XEXP (op0, 1)))));
10650               code = (code == LT ? NE : EQ);
10651               continue;
10652             }
10653
10654           /* If this an equality comparison with zero and we are shifting
10655              the low bit to the sign bit, we can convert this to an AND of the
10656              low-order bit.  */
10657           if (const_op == 0 && equality_comparison_p
10658               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10659               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10660             {
10661               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10662                                             (HOST_WIDE_INT) 1);
10663               continue;
10664             }
10665           break;
10666
10667         case ASHIFTRT:
10668           /* If this is an equality comparison with zero, we can do this
10669              as a logical shift, which might be much simpler.  */
10670           if (equality_comparison_p && const_op == 0
10671               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10672             {
10673               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10674                                           XEXP (op0, 0),
10675                                           INTVAL (XEXP (op0, 1)));
10676               continue;
10677             }
10678
10679           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10680              do the comparison in a narrower mode.  */
10681           if (! unsigned_comparison_p
10682               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10683               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10684               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10685               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10686                                          MODE_INT, 1)) != BLKmode
10687               && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10688                   || ((unsigned HOST_WIDE_INT) - const_op
10689                       <= GET_MODE_MASK (tmode))))
10690             {
10691               op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10692               continue;
10693             }
10694
10695           /* Likewise if OP0 is a PLUS of a sign extension with a
10696              constant, which is usually represented with the PLUS
10697              between the shifts.  */
10698           if (! unsigned_comparison_p
10699               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10700               && GET_CODE (XEXP (op0, 0)) == PLUS
10701               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10702               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10703               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10704               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10705                                          MODE_INT, 1)) != BLKmode
10706               && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10707                   || ((unsigned HOST_WIDE_INT) - const_op
10708                       <= GET_MODE_MASK (tmode))))
10709             {
10710               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10711               rtx add_const = XEXP (XEXP (op0, 0), 1);
10712               rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10713                                           XEXP (op0, 1));
10714
10715               op0 = gen_binary (PLUS, tmode,
10716                                 gen_lowpart_for_combine (tmode, inner),
10717                                 new_const);
10718               continue;
10719             }
10720
10721           /* ... fall through ...  */
10722         case LSHIFTRT:
10723           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10724              the low order N bits of FOO are known to be zero, we can do this
10725              by comparing FOO with C shifted left N bits so long as no
10726              overflow occurs.  */
10727           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10728               && INTVAL (XEXP (op0, 1)) >= 0
10729               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10730               && mode_width <= HOST_BITS_PER_WIDE_INT
10731               && (nonzero_bits (XEXP (op0, 0), mode)
10732                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10733               && (const_op == 0
10734                   || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10735                       < mode_width)))
10736             {
10737               const_op <<= INTVAL (XEXP (op0, 1));
10738               op1 = GEN_INT (const_op);
10739               op0 = XEXP (op0, 0);
10740               continue;
10741             }
10742
10743           /* If we are using this shift to extract just the sign bit, we
10744              can replace this with an LT or GE comparison.  */
10745           if (const_op == 0
10746               && (equality_comparison_p || sign_bit_comparison_p)
10747               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10748               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10749             {
10750               op0 = XEXP (op0, 0);
10751               code = (code == NE || code == GT ? LT : GE);
10752               continue;
10753             }
10754           break;
10755
10756         default:
10757           break;
10758         }
10759
10760       break;
10761     }
10762
10763   /* Now make any compound operations involved in this comparison.  Then,
10764      check for an outmost SUBREG on OP0 that is not doing anything or is
10765      paradoxical.  The latter case can only occur when it is known that the
10766      "extra" bits will be zero.  Therefore, it is safe to remove the SUBREG.
10767      We can never remove a SUBREG for a non-equality comparison because the
10768      sign bit is in a different place in the underlying object.  */
10769
10770   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10771   op1 = make_compound_operation (op1, SET);
10772
10773   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10774       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10775       && (code == NE || code == EQ)
10776       && ((GET_MODE_SIZE (GET_MODE (op0))
10777            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10778     {
10779       op0 = SUBREG_REG (op0);
10780       op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10781     }
10782
10783   else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10784            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10785            && (code == NE || code == EQ)
10786            && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10787                <= HOST_BITS_PER_WIDE_INT)
10788            && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10789                & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10790            && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10791                                               op1),
10792                (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10793                 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10794     op0 = SUBREG_REG (op0), op1 = tem;
10795
10796   /* We now do the opposite procedure: Some machines don't have compare
10797      insns in all modes.  If OP0's mode is an integer mode smaller than a
10798      word and we can't do a compare in that mode, see if there is a larger
10799      mode for which we can do the compare.  There are a number of cases in
10800      which we can use the wider mode.  */
10801
10802   mode = GET_MODE (op0);
10803   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10804       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10805       && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10806     for (tmode = GET_MODE_WIDER_MODE (mode);
10807          (tmode != VOIDmode
10808           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10809          tmode = GET_MODE_WIDER_MODE (tmode))
10810       if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10811         {
10812           /* If the only nonzero bits in OP0 and OP1 are those in the
10813              narrower mode and this is an equality or unsigned comparison,
10814              we can use the wider mode.  Similarly for sign-extended
10815              values, in which case it is true for all comparisons.  */
10816           if (((code == EQ || code == NE
10817                 || code == GEU || code == GTU || code == LEU || code == LTU)
10818                && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10819                && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10820               || ((num_sign_bit_copies (op0, tmode)
10821                    > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10822                   && (num_sign_bit_copies (op1, tmode)
10823                       > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10824             {
10825               /* If OP0 is an AND and we don't have an AND in MODE either,
10826                  make a new AND in the proper mode.  */
10827               if (GET_CODE (op0) == AND
10828                   && (add_optab->handlers[(int) mode].insn_code
10829                       == CODE_FOR_nothing))
10830                 op0 = gen_binary (AND, tmode,
10831                                   gen_lowpart_for_combine (tmode,
10832                                                            XEXP (op0, 0)),
10833                                   gen_lowpart_for_combine (tmode,
10834                                                            XEXP (op0, 1)));
10835
10836               op0 = gen_lowpart_for_combine (tmode, op0);
10837               op1 = gen_lowpart_for_combine (tmode, op1);
10838               break;
10839             }
10840
10841           /* If this is a test for negative, we can make an explicit
10842              test of the sign bit.  */
10843
10844           if (op1 == const0_rtx && (code == LT || code == GE)
10845               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10846             {
10847               op0 = gen_binary (AND, tmode,
10848                                 gen_lowpart_for_combine (tmode, op0),
10849                                 GEN_INT ((HOST_WIDE_INT) 1
10850                                          << (GET_MODE_BITSIZE (mode) - 1)));
10851               code = (code == LT) ? NE : EQ;
10852               break;
10853             }
10854         }
10855
10856 #ifdef CANONICALIZE_COMPARISON
10857   /* If this machine only supports a subset of valid comparisons, see if we
10858      can convert an unsupported one into a supported one.  */
10859   CANONICALIZE_COMPARISON (code, op0, op1);
10860 #endif
10861
10862   *pop0 = op0;
10863   *pop1 = op1;
10864
10865   return code;
10866 }
10867 \f
10868 /* Return 1 if we know that X, a comparison operation, is not operating
10869    on a floating-point value or is EQ or NE, meaning that we can safely
10870    reverse it.  */
10871
10872 static int
10873 reversible_comparison_p (x)
10874      rtx x;
10875 {
10876   if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10877       || flag_fast_math
10878       || GET_CODE (x) == NE || GET_CODE (x) == EQ
10879       || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
10880     return 1;
10881
10882   switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10883     {
10884     case MODE_INT:
10885     case MODE_PARTIAL_INT:
10886     case MODE_COMPLEX_INT:
10887       return 1;
10888
10889     case MODE_CC:
10890       /* If the mode of the condition codes tells us that this is safe,
10891          we need look no further.  */
10892       if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10893         return 1;
10894
10895       /* Otherwise try and find where the condition codes were last set and
10896          use that.  */
10897       x = get_last_value (XEXP (x, 0));
10898       return (x && GET_CODE (x) == COMPARE
10899               && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10900
10901     default:
10902       return 0;
10903     }
10904 }
10905 \f
10906 /* Utility function for following routine.  Called when X is part of a value
10907    being stored into reg_last_set_value.  Sets reg_last_set_table_tick
10908    for each register mentioned.  Similar to mention_regs in cse.c  */
10909
10910 static void
10911 update_table_tick (x)
10912      rtx x;
10913 {
10914   register enum rtx_code code = GET_CODE (x);
10915   register const char *fmt = GET_RTX_FORMAT (code);
10916   register int i;
10917
10918   if (code == REG)
10919     {
10920       int regno = REGNO (x);
10921       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10922                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10923
10924       for (i = regno; i < endregno; i++)
10925         reg_last_set_table_tick[i] = label_tick;
10926
10927       return;
10928     }
10929
10930   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10931     /* Note that we can't have an "E" in values stored; see
10932        get_last_value_validate.  */
10933     if (fmt[i] == 'e')
10934       update_table_tick (XEXP (x, i));
10935 }
10936
10937 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10938    are saying that the register is clobbered and we no longer know its
10939    value.  If INSN is zero, don't update reg_last_set; this is only permitted
10940    with VALUE also zero and is used to invalidate the register.  */
10941
10942 static void
10943 record_value_for_reg (reg, insn, value)
10944      rtx reg;
10945      rtx insn;
10946      rtx value;
10947 {
10948   int regno = REGNO (reg);
10949   int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10950                           ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10951   int i;
10952
10953   /* If VALUE contains REG and we have a previous value for REG, substitute
10954      the previous value.  */
10955   if (value && insn && reg_overlap_mentioned_p (reg, value))
10956     {
10957       rtx tem;
10958
10959       /* Set things up so get_last_value is allowed to see anything set up to
10960          our insn.  */
10961       subst_low_cuid = INSN_CUID (insn);
10962       tem = get_last_value (reg);
10963
10964       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10965          it isn't going to be useful and will take a lot of time to process,
10966          so just use the CLOBBER.  */
10967
10968       if (tem)
10969         {
10970           if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
10971                || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
10972               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10973               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10974             tem = XEXP (tem, 0);
10975
10976           value = replace_rtx (copy_rtx (value), reg, tem);
10977         }
10978     }
10979
10980   /* For each register modified, show we don't know its value, that
10981      we don't know about its bitwise content, that its value has been
10982      updated, and that we don't know the location of the death of the
10983      register.  */
10984   for (i = regno; i < endregno; i ++)
10985     {
10986       if (insn)
10987         reg_last_set[i] = insn;
10988       reg_last_set_value[i] = 0;
10989       reg_last_set_mode[i] = 0;
10990       reg_last_set_nonzero_bits[i] = 0;
10991       reg_last_set_sign_bit_copies[i] = 0;
10992       reg_last_death[i] = 0;
10993     }
10994
10995   /* Mark registers that are being referenced in this value.  */
10996   if (value)
10997     update_table_tick (value);
10998
10999   /* Now update the status of each register being set.
11000      If someone is using this register in this block, set this register
11001      to invalid since we will get confused between the two lives in this
11002      basic block.  This makes using this register always invalid.  In cse, we
11003      scan the table to invalidate all entries using this register, but this
11004      is too much work for us.  */
11005
11006   for (i = regno; i < endregno; i++)
11007     {
11008       reg_last_set_label[i] = label_tick;
11009       if (value && reg_last_set_table_tick[i] == label_tick)
11010         reg_last_set_invalid[i] = 1;
11011       else
11012         reg_last_set_invalid[i] = 0;
11013     }
11014
11015   /* The value being assigned might refer to X (like in "x++;").  In that
11016      case, we must replace it with (clobber (const_int 0)) to prevent
11017      infinite loops.  */
11018   if (value && ! get_last_value_validate (&value, insn,
11019                                           reg_last_set_label[regno], 0))
11020     {
11021       value = copy_rtx (value);
11022       if (! get_last_value_validate (&value, insn,
11023                                      reg_last_set_label[regno], 1))
11024         value = 0;
11025     }
11026
11027   /* For the main register being modified, update the value, the mode, the
11028      nonzero bits, and the number of sign bit copies.  */
11029
11030   reg_last_set_value[regno] = value;
11031
11032   if (value)
11033     {
11034       subst_low_cuid = INSN_CUID (insn);
11035       reg_last_set_mode[regno] = GET_MODE (reg);
11036       reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11037       reg_last_set_sign_bit_copies[regno]
11038         = num_sign_bit_copies (value, GET_MODE (reg));
11039     }
11040 }
11041
11042 /* Called via note_stores from record_dead_and_set_regs to handle one
11043    SET or CLOBBER in an insn.  DATA is the instruction in which the
11044    set is occurring.  */
11045
11046 static void
11047 record_dead_and_set_regs_1 (dest, setter, data)
11048      rtx dest, setter;
11049      void *data;
11050 {
11051   rtx record_dead_insn = (rtx) data;
11052
11053   if (GET_CODE (dest) == SUBREG)
11054     dest = SUBREG_REG (dest);
11055
11056   if (GET_CODE (dest) == REG)
11057     {
11058       /* If we are setting the whole register, we know its value.  Otherwise
11059          show that we don't know the value.  We can handle SUBREG in
11060          some cases.  */
11061       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11062         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11063       else if (GET_CODE (setter) == SET
11064                && GET_CODE (SET_DEST (setter)) == SUBREG
11065                && SUBREG_REG (SET_DEST (setter)) == dest
11066                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11067                && subreg_lowpart_p (SET_DEST (setter)))
11068         record_value_for_reg (dest, record_dead_insn,
11069                               gen_lowpart_for_combine (GET_MODE (dest),
11070                                                        SET_SRC (setter)));
11071       else
11072         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11073     }
11074   else if (GET_CODE (dest) == MEM
11075            /* Ignore pushes, they clobber nothing.  */
11076            && ! push_operand (dest, GET_MODE (dest)))
11077     mem_last_set = INSN_CUID (record_dead_insn);
11078 }
11079
11080 /* Update the records of when each REG was most recently set or killed
11081    for the things done by INSN.  This is the last thing done in processing
11082    INSN in the combiner loop.
11083
11084    We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11085    reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11086    and also the similar information mem_last_set (which insn most recently
11087    modified memory) and last_call_cuid (which insn was the most recent
11088    subroutine call).  */
11089
11090 static void
11091 record_dead_and_set_regs (insn)
11092      rtx insn;
11093 {
11094   register rtx link;
11095   int i;
11096
11097   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11098     {
11099       if (REG_NOTE_KIND (link) == REG_DEAD
11100           && GET_CODE (XEXP (link, 0)) == REG)
11101         {
11102           int regno = REGNO (XEXP (link, 0));
11103           int endregno
11104             = regno + (regno < FIRST_PSEUDO_REGISTER
11105                        ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11106                        : 1);
11107
11108           for (i = regno; i < endregno; i++)
11109             reg_last_death[i] = insn;
11110         }
11111       else if (REG_NOTE_KIND (link) == REG_INC)
11112         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11113     }
11114
11115   if (GET_CODE (insn) == CALL_INSN)
11116     {
11117       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11118         if (call_used_regs[i])
11119           {
11120             reg_last_set_value[i] = 0;
11121             reg_last_set_mode[i] = 0;
11122             reg_last_set_nonzero_bits[i] = 0;
11123             reg_last_set_sign_bit_copies[i] = 0;
11124             reg_last_death[i] = 0;
11125           }
11126
11127       last_call_cuid = mem_last_set = INSN_CUID (insn);
11128     }
11129
11130   note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11131 }
11132
11133 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11134    register present in the SUBREG, so for each such SUBREG go back and
11135    adjust nonzero and sign bit information of the registers that are
11136    known to have some zero/sign bits set.
11137
11138    This is needed because when combine blows the SUBREGs away, the
11139    information on zero/sign bits is lost and further combines can be
11140    missed because of that.  */
11141
11142 static void
11143 record_promoted_value (insn, subreg)
11144     rtx insn;
11145     rtx subreg;
11146 {
11147   rtx links, set;
11148   int regno = REGNO (SUBREG_REG (subreg));
11149   enum machine_mode mode = GET_MODE (subreg);
11150
11151   if (GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT)
11152     return;
11153
11154   for (links = LOG_LINKS (insn); links; )
11155     {
11156       insn = XEXP (links, 0);
11157       set = single_set (insn);
11158
11159       if (! set || GET_CODE (SET_DEST (set)) != REG
11160           || REGNO (SET_DEST (set)) != regno
11161           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11162         {
11163           links = XEXP (links, 1);
11164           continue;
11165         }
11166
11167       if (reg_last_set [regno] == insn)
11168         {
11169           if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11170             reg_last_set_nonzero_bits [regno] &= GET_MODE_MASK (mode);
11171         }
11172
11173       if (GET_CODE (SET_SRC (set)) == REG)
11174         {
11175           regno = REGNO (SET_SRC (set));
11176           links = LOG_LINKS (insn);
11177         }
11178       else
11179         break;
11180     }
11181 }
11182
11183 /* Scan X for promoted SUBREGs.  For each one found,
11184    note what it implies to the registers used in it.  */
11185
11186 static void
11187 check_promoted_subreg (insn, x)
11188     rtx insn;
11189     rtx x;
11190 {
11191   if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11192       && GET_CODE (SUBREG_REG (x)) == REG)
11193     record_promoted_value (insn, x);
11194   else
11195     {
11196       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11197       int i, j;
11198
11199       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11200         switch (format [i])
11201           {
11202           case 'e':
11203             check_promoted_subreg (insn, XEXP (x, i));
11204             break;
11205           case 'V':
11206           case 'E':
11207             if (XVEC (x, i) != 0)
11208               for (j = 0; j < XVECLEN (x, i); j++)
11209                 check_promoted_subreg (insn, XVECEXP (x, i, j));
11210             break;
11211           }
11212     }
11213 }
11214 \f
11215 /* Utility routine for the following function.  Verify that all the registers
11216    mentioned in *LOC are valid when *LOC was part of a value set when
11217    label_tick == TICK.  Return 0 if some are not.
11218
11219    If REPLACE is non-zero, replace the invalid reference with
11220    (clobber (const_int 0)) and return 1.  This replacement is useful because
11221    we often can get useful information about the form of a value (e.g., if
11222    it was produced by a shift that always produces -1 or 0) even though
11223    we don't know exactly what registers it was produced from.  */
11224
11225 static int
11226 get_last_value_validate (loc, insn, tick, replace)
11227      rtx *loc;
11228      rtx insn;
11229      int tick;
11230      int replace;
11231 {
11232   rtx x = *loc;
11233   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11234   int len = GET_RTX_LENGTH (GET_CODE (x));
11235   int i;
11236
11237   if (GET_CODE (x) == REG)
11238     {
11239       int regno = REGNO (x);
11240       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11241                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11242       int j;
11243
11244       for (j = regno; j < endregno; j++)
11245         if (reg_last_set_invalid[j]
11246             /* If this is a pseudo-register that was only set once and not
11247                live at the beginning of the function, it is always valid.  */
11248             || (! (regno >= FIRST_PSEUDO_REGISTER
11249                    && REG_N_SETS (regno) == 1
11250                    && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))
11251                 && reg_last_set_label[j] > tick))
11252           {
11253             if (replace)
11254               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11255             return replace;
11256           }
11257
11258       return 1;
11259     }
11260   /* If this is a memory reference, make sure that there were
11261      no stores after it that might have clobbered the value.  We don't
11262      have alias info, so we assume any store invalidates it.  */
11263   else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11264            && INSN_CUID (insn) <= mem_last_set)
11265     {
11266       if (replace)
11267         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11268       return replace;
11269     }
11270
11271   for (i = 0; i < len; i++)
11272     if ((fmt[i] == 'e'
11273          && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11274         /* Don't bother with these.  They shouldn't occur anyway.  */
11275         || fmt[i] == 'E')
11276       return 0;
11277
11278   /* If we haven't found a reason for it to be invalid, it is valid.  */
11279   return 1;
11280 }
11281
11282 /* Get the last value assigned to X, if known.  Some registers
11283    in the value may be replaced with (clobber (const_int 0)) if their value
11284    is known longer known reliably.  */
11285
11286 static rtx
11287 get_last_value (x)
11288      rtx x;
11289 {
11290   int regno;
11291   rtx value;
11292
11293   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11294      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11295      we cannot predict what values the "extra" bits might have.  */
11296   if (GET_CODE (x) == SUBREG
11297       && subreg_lowpart_p (x)
11298       && (GET_MODE_SIZE (GET_MODE (x))
11299           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11300       && (value = get_last_value (SUBREG_REG (x))) != 0)
11301     return gen_lowpart_for_combine (GET_MODE (x), value);
11302
11303   if (GET_CODE (x) != REG)
11304     return 0;
11305
11306   regno = REGNO (x);
11307   value = reg_last_set_value[regno];
11308
11309   /* If we don't have a value, or if it isn't for this basic block and
11310      it's either a hard register, set more than once, or it's a live
11311      at the beginning of the function, return 0.
11312
11313      Because if it's not live at the beginnning of the function then the reg
11314      is always set before being used (is never used without being set).
11315      And, if it's set only once, and it's always set before use, then all
11316      uses must have the same last value, even if it's not from this basic
11317      block.  */
11318
11319   if (value == 0
11320       || (reg_last_set_label[regno] != label_tick
11321           && (regno < FIRST_PSEUDO_REGISTER
11322               || REG_N_SETS (regno) != 1
11323               || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))))
11324     return 0;
11325
11326   /* If the value was set in a later insn than the ones we are processing,
11327      we can't use it even if the register was only set once.  */
11328   if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11329     return 0;
11330
11331   /* If the value has all its registers valid, return it.  */
11332   if (get_last_value_validate (&value, reg_last_set[regno],
11333                                reg_last_set_label[regno], 0))
11334     return value;
11335
11336   /* Otherwise, make a copy and replace any invalid register with
11337      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11338
11339   value = copy_rtx (value);
11340   if (get_last_value_validate (&value, reg_last_set[regno],
11341                                reg_last_set_label[regno], 1))
11342     return value;
11343
11344   return 0;
11345 }
11346 \f
11347 /* Return nonzero if expression X refers to a REG or to memory
11348    that is set in an instruction more recent than FROM_CUID.  */
11349
11350 static int
11351 use_crosses_set_p (x, from_cuid)
11352      register rtx x;
11353      int from_cuid;
11354 {
11355   register const char *fmt;
11356   register int i;
11357   register enum rtx_code code = GET_CODE (x);
11358
11359   if (code == REG)
11360     {
11361       register int regno = REGNO (x);
11362       int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11363                             ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11364
11365 #ifdef PUSH_ROUNDING
11366       /* Don't allow uses of the stack pointer to be moved,
11367          because we don't know whether the move crosses a push insn.  */
11368       if (regno == STACK_POINTER_REGNUM)
11369         return 1;
11370 #endif
11371       for (;regno < endreg; regno++)
11372         if (reg_last_set[regno]
11373             && INSN_CUID (reg_last_set[regno]) > from_cuid)
11374           return 1;
11375       return 0;
11376     }
11377
11378   if (code == MEM && mem_last_set > from_cuid)
11379     return 1;
11380
11381   fmt = GET_RTX_FORMAT (code);
11382
11383   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11384     {
11385       if (fmt[i] == 'E')
11386         {
11387           register int j;
11388           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11389             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11390               return 1;
11391         }
11392       else if (fmt[i] == 'e'
11393                && use_crosses_set_p (XEXP (x, i), from_cuid))
11394         return 1;
11395     }
11396   return 0;
11397 }
11398 \f
11399 /* Define three variables used for communication between the following
11400    routines.  */
11401
11402 static int reg_dead_regno, reg_dead_endregno;
11403 static int reg_dead_flag;
11404
11405 /* Function called via note_stores from reg_dead_at_p.
11406
11407    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11408    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11409
11410 static void
11411 reg_dead_at_p_1 (dest, x, data)
11412      rtx dest;
11413      rtx x;
11414      void *data ATTRIBUTE_UNUSED;
11415 {
11416   int regno, endregno;
11417
11418   if (GET_CODE (dest) != REG)
11419     return;
11420
11421   regno = REGNO (dest);
11422   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11423                       ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11424
11425   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11426     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11427 }
11428
11429 /* Return non-zero if REG is known to be dead at INSN.
11430
11431    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11432    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11433    live.  Otherwise, see if it is live or dead at the start of the basic
11434    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11435    must be assumed to be always live.  */
11436
11437 static int
11438 reg_dead_at_p (reg, insn)
11439      rtx reg;
11440      rtx insn;
11441 {
11442   int block, i;
11443
11444   /* Set variables for reg_dead_at_p_1.  */
11445   reg_dead_regno = REGNO (reg);
11446   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11447                                         ? HARD_REGNO_NREGS (reg_dead_regno,
11448                                                             GET_MODE (reg))
11449                                         : 1);
11450
11451   reg_dead_flag = 0;
11452
11453   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  */
11454   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11455     {
11456       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11457         if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11458           return 0;
11459     }
11460
11461   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11462      beginning of function.  */
11463   for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11464        insn = prev_nonnote_insn (insn))
11465     {
11466       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11467       if (reg_dead_flag)
11468         return reg_dead_flag == 1 ? 1 : 0;
11469
11470       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11471         return 1;
11472     }
11473
11474   /* Get the basic block number that we were in.  */
11475   if (insn == 0)
11476     block = 0;
11477   else
11478     {
11479       for (block = 0; block < n_basic_blocks; block++)
11480         if (insn == BLOCK_HEAD (block))
11481           break;
11482
11483       if (block == n_basic_blocks)
11484         return 0;
11485     }
11486
11487   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11488     if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11489       return 0;
11490
11491   return 1;
11492 }
11493 \f
11494 /* Note hard registers in X that are used.  This code is similar to
11495    that in flow.c, but much simpler since we don't care about pseudos.  */
11496
11497 static void
11498 mark_used_regs_combine (x)
11499      rtx x;
11500 {
11501   register RTX_CODE code = GET_CODE (x);
11502   register int regno;
11503   int i;
11504
11505   switch (code)
11506     {
11507     case LABEL_REF:
11508     case SYMBOL_REF:
11509     case CONST_INT:
11510     case CONST:
11511     case CONST_DOUBLE:
11512     case PC:
11513     case ADDR_VEC:
11514     case ADDR_DIFF_VEC:
11515     case ASM_INPUT:
11516 #ifdef HAVE_cc0
11517     /* CC0 must die in the insn after it is set, so we don't need to take
11518        special note of it here.  */
11519     case CC0:
11520 #endif
11521       return;
11522
11523     case CLOBBER:
11524       /* If we are clobbering a MEM, mark any hard registers inside the
11525          address as used.  */
11526       if (GET_CODE (XEXP (x, 0)) == MEM)
11527         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11528       return;
11529
11530     case REG:
11531       regno = REGNO (x);
11532       /* A hard reg in a wide mode may really be multiple registers.
11533          If so, mark all of them just like the first.  */
11534       if (regno < FIRST_PSEUDO_REGISTER)
11535         {
11536           /* None of this applies to the stack, frame or arg pointers */
11537           if (regno == STACK_POINTER_REGNUM
11538 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11539               || regno == HARD_FRAME_POINTER_REGNUM
11540 #endif
11541 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11542               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11543 #endif
11544               || regno == FRAME_POINTER_REGNUM)
11545             return;
11546
11547           i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11548           while (i-- > 0)
11549             SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11550         }
11551       return;
11552
11553     case SET:
11554       {
11555         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11556            the address.  */
11557         register rtx testreg = SET_DEST (x);
11558
11559         while (GET_CODE (testreg) == SUBREG
11560                || GET_CODE (testreg) == ZERO_EXTRACT
11561                || GET_CODE (testreg) == SIGN_EXTRACT
11562                || GET_CODE (testreg) == STRICT_LOW_PART)
11563           testreg = XEXP (testreg, 0);
11564
11565         if (GET_CODE (testreg) == MEM)
11566           mark_used_regs_combine (XEXP (testreg, 0));
11567
11568         mark_used_regs_combine (SET_SRC (x));
11569       }
11570       return;
11571
11572     default:
11573       break;
11574     }
11575
11576   /* Recursively scan the operands of this expression.  */
11577
11578   {
11579     register const char *fmt = GET_RTX_FORMAT (code);
11580
11581     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11582       {
11583         if (fmt[i] == 'e')
11584           mark_used_regs_combine (XEXP (x, i));
11585         else if (fmt[i] == 'E')
11586           {
11587             register int j;
11588
11589             for (j = 0; j < XVECLEN (x, i); j++)
11590               mark_used_regs_combine (XVECEXP (x, i, j));
11591           }
11592       }
11593   }
11594 }
11595
11596 \f
11597 /* Remove register number REGNO from the dead registers list of INSN.
11598
11599    Return the note used to record the death, if there was one.  */
11600
11601 rtx
11602 remove_death (regno, insn)
11603      int regno;
11604      rtx insn;
11605 {
11606   register rtx note = find_regno_note (insn, REG_DEAD, regno);
11607
11608   if (note)
11609     {
11610       REG_N_DEATHS (regno)--;
11611       remove_note (insn, note);
11612     }
11613
11614   return note;
11615 }
11616
11617 /* For each register (hardware or pseudo) used within expression X, if its
11618    death is in an instruction with cuid between FROM_CUID (inclusive) and
11619    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11620    list headed by PNOTES.
11621
11622    That said, don't move registers killed by maybe_kill_insn.
11623
11624    This is done when X is being merged by combination into TO_INSN.  These
11625    notes will then be distributed as needed.  */
11626
11627 static void
11628 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11629      rtx x;
11630      rtx maybe_kill_insn;
11631      int from_cuid;
11632      rtx to_insn;
11633      rtx *pnotes;
11634 {
11635   register const char *fmt;
11636   register int len, i;
11637   register enum rtx_code code = GET_CODE (x);
11638
11639   if (code == REG)
11640     {
11641       register int regno = REGNO (x);
11642       register rtx where_dead = reg_last_death[regno];
11643       register rtx before_dead, after_dead;
11644
11645       /* Don't move the register if it gets killed in between from and to */
11646       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11647           && !reg_referenced_p (x, maybe_kill_insn))
11648         return;
11649
11650       /* WHERE_DEAD could be a USE insn made by combine, so first we
11651          make sure that we have insns with valid INSN_CUID values.  */
11652       before_dead = where_dead;
11653       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11654         before_dead = PREV_INSN (before_dead);
11655       after_dead = where_dead;
11656       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11657         after_dead = NEXT_INSN (after_dead);
11658
11659       if (before_dead && after_dead
11660           && INSN_CUID (before_dead) >= from_cuid
11661           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11662               || (where_dead != after_dead
11663                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11664         {
11665           rtx note = remove_death (regno, where_dead);
11666
11667           /* It is possible for the call above to return 0.  This can occur
11668              when reg_last_death points to I2 or I1 that we combined with.
11669              In that case make a new note.
11670
11671              We must also check for the case where X is a hard register
11672              and NOTE is a death note for a range of hard registers
11673              including X.  In that case, we must put REG_DEAD notes for
11674              the remaining registers in place of NOTE.  */
11675
11676           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11677               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11678                   > GET_MODE_SIZE (GET_MODE (x))))
11679             {
11680               int deadregno = REGNO (XEXP (note, 0));
11681               int deadend
11682                 = (deadregno + HARD_REGNO_NREGS (deadregno,
11683                                                  GET_MODE (XEXP (note, 0))));
11684               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11685               int i;
11686
11687               for (i = deadregno; i < deadend; i++)
11688                 if (i < regno || i >= ourend)
11689                   REG_NOTES (where_dead)
11690                     = gen_rtx_EXPR_LIST (REG_DEAD,
11691                                          gen_rtx_REG (reg_raw_mode[i], i),
11692                                          REG_NOTES (where_dead));
11693             }
11694           /* If we didn't find any note, or if we found a REG_DEAD note that
11695              covers only part of the given reg, and we have a multi-reg hard
11696              register, then to be safe we must check for REG_DEAD notes
11697              for each register other than the first.  They could have
11698              their own REG_DEAD notes lying around.  */
11699           else if ((note == 0
11700                     || (note != 0
11701                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11702                             < GET_MODE_SIZE (GET_MODE (x)))))
11703                    && regno < FIRST_PSEUDO_REGISTER
11704                    && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11705             {
11706               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11707               int i, offset;
11708               rtx oldnotes = 0;
11709
11710               if (note)
11711                 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11712               else
11713                 offset = 1;
11714
11715               for (i = regno + offset; i < ourend; i++)
11716                 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11717                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11718             }
11719
11720           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11721             {
11722               XEXP (note, 1) = *pnotes;
11723               *pnotes = note;
11724             }
11725           else
11726             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11727
11728           REG_N_DEATHS (regno)++;
11729         }
11730
11731       return;
11732     }
11733
11734   else if (GET_CODE (x) == SET)
11735     {
11736       rtx dest = SET_DEST (x);
11737
11738       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11739
11740       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11741          that accesses one word of a multi-word item, some
11742          piece of everything register in the expression is used by
11743          this insn, so remove any old death.  */
11744
11745       if (GET_CODE (dest) == ZERO_EXTRACT
11746           || GET_CODE (dest) == STRICT_LOW_PART
11747           || (GET_CODE (dest) == SUBREG
11748               && (((GET_MODE_SIZE (GET_MODE (dest))
11749                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11750                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11751                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11752         {
11753           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11754           return;
11755         }
11756
11757       /* If this is some other SUBREG, we know it replaces the entire
11758          value, so use that as the destination.  */
11759       if (GET_CODE (dest) == SUBREG)
11760         dest = SUBREG_REG (dest);
11761
11762       /* If this is a MEM, adjust deaths of anything used in the address.
11763          For a REG (the only other possibility), the entire value is
11764          being replaced so the old value is not used in this insn.  */
11765
11766       if (GET_CODE (dest) == MEM)
11767         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11768                      to_insn, pnotes);
11769       return;
11770     }
11771
11772   else if (GET_CODE (x) == CLOBBER)
11773     return;
11774
11775   len = GET_RTX_LENGTH (code);
11776   fmt = GET_RTX_FORMAT (code);
11777
11778   for (i = 0; i < len; i++)
11779     {
11780       if (fmt[i] == 'E')
11781         {
11782           register int j;
11783           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11784             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11785                          to_insn, pnotes);
11786         }
11787       else if (fmt[i] == 'e')
11788         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11789     }
11790 }
11791 \f
11792 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11793    pattern of an insn.  X must be a REG.  */
11794
11795 static int
11796 reg_bitfield_target_p (x, body)
11797      rtx x;
11798      rtx body;
11799 {
11800   int i;
11801
11802   if (GET_CODE (body) == SET)
11803     {
11804       rtx dest = SET_DEST (body);
11805       rtx target;
11806       int regno, tregno, endregno, endtregno;
11807
11808       if (GET_CODE (dest) == ZERO_EXTRACT)
11809         target = XEXP (dest, 0);
11810       else if (GET_CODE (dest) == STRICT_LOW_PART)
11811         target = SUBREG_REG (XEXP (dest, 0));
11812       else
11813         return 0;
11814
11815       if (GET_CODE (target) == SUBREG)
11816         target = SUBREG_REG (target);
11817
11818       if (GET_CODE (target) != REG)
11819         return 0;
11820
11821       tregno = REGNO (target), regno = REGNO (x);
11822       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11823         return target == x;
11824
11825       endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11826       endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11827
11828       return endregno > tregno && regno < endtregno;
11829     }
11830
11831   else if (GET_CODE (body) == PARALLEL)
11832     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11833       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11834         return 1;
11835
11836   return 0;
11837 }
11838 \f
11839 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11840    as appropriate.  I3 and I2 are the insns resulting from the combination
11841    insns including FROM (I2 may be zero).
11842
11843    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11844    not need REG_DEAD notes because they are being substituted for.  This
11845    saves searching in the most common cases.
11846
11847    Each note in the list is either ignored or placed on some insns, depending
11848    on the type of note.  */
11849
11850 static void
11851 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11852      rtx notes;
11853      rtx from_insn;
11854      rtx i3, i2;
11855      rtx elim_i2, elim_i1;
11856 {
11857   rtx note, next_note;
11858   rtx tem;
11859
11860   for (note = notes; note; note = next_note)
11861     {
11862       rtx place = 0, place2 = 0;
11863
11864       /* If this NOTE references a pseudo register, ensure it references
11865          the latest copy of that register.  */
11866       if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11867           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11868         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11869
11870       next_note = XEXP (note, 1);
11871       switch (REG_NOTE_KIND (note))
11872         {
11873         case REG_BR_PROB:
11874         case REG_EXEC_COUNT:
11875           /* Doesn't matter much where we put this, as long as it's somewhere.
11876              It is preferable to keep these notes on branches, which is most
11877              likely to be i3.  */
11878           place = i3;
11879           break;
11880
11881         case REG_EH_REGION:
11882         case REG_EH_RETHROW:
11883           /* These notes must remain with the call.  It should not be
11884              possible for both I2 and I3 to be a call.  */
11885           if (GET_CODE (i3) == CALL_INSN)
11886             place = i3;
11887           else if (i2 && GET_CODE (i2) == CALL_INSN)
11888             place = i2;
11889           else
11890             abort ();
11891           break;
11892
11893         case REG_UNUSED:
11894           /* Any clobbers for i3 may still exist, and so we must process
11895              REG_UNUSED notes from that insn.
11896
11897              Any clobbers from i2 or i1 can only exist if they were added by
11898              recog_for_combine.  In that case, recog_for_combine created the
11899              necessary REG_UNUSED notes.  Trying to keep any original
11900              REG_UNUSED notes from these insns can cause incorrect output
11901              if it is for the same register as the original i3 dest.
11902              In that case, we will notice that the register is set in i3,
11903              and then add a REG_UNUSED note for the destination of i3, which
11904              is wrong.  However, it is possible to have REG_UNUSED notes from
11905              i2 or i1 for register which were both used and clobbered, so
11906              we keep notes from i2 or i1 if they will turn into REG_DEAD
11907              notes.  */
11908
11909           /* If this register is set or clobbered in I3, put the note there
11910              unless there is one already.  */
11911           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11912             {
11913               if (from_insn != i3)
11914                 break;
11915
11916               if (! (GET_CODE (XEXP (note, 0)) == REG
11917                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11918                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11919                 place = i3;
11920             }
11921           /* Otherwise, if this register is used by I3, then this register
11922              now dies here, so we must put a REG_DEAD note here unless there
11923              is one already.  */
11924           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11925                    && ! (GET_CODE (XEXP (note, 0)) == REG
11926                          ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11927                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11928             {
11929               PUT_REG_NOTE_KIND (note, REG_DEAD);
11930               place = i3;
11931             }
11932           break;
11933
11934         case REG_EQUAL:
11935         case REG_EQUIV:
11936         case REG_NONNEG:
11937         case REG_NOALIAS:
11938           /* These notes say something about results of an insn.  We can
11939              only support them if they used to be on I3 in which case they
11940              remain on I3.  Otherwise they are ignored.
11941
11942              If the note refers to an expression that is not a constant, we
11943              must also ignore the note since we cannot tell whether the
11944              equivalence is still true.  It might be possible to do
11945              slightly better than this (we only have a problem if I2DEST
11946              or I1DEST is present in the expression), but it doesn't
11947              seem worth the trouble.  */
11948
11949           if (from_insn == i3
11950               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11951             place = i3;
11952           break;
11953
11954         case REG_INC:
11955         case REG_NO_CONFLICT:
11956           /* These notes say something about how a register is used.  They must
11957              be present on any use of the register in I2 or I3.  */
11958           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11959             place = i3;
11960
11961           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11962             {
11963               if (place)
11964                 place2 = i2;
11965               else
11966                 place = i2;
11967             }
11968           break;
11969
11970         case REG_LABEL:
11971           /* This can show up in several ways -- either directly in the
11972              pattern, or hidden off in the constant pool with (or without?)
11973              a REG_EQUAL note.  */
11974           /* ??? Ignore the without-reg_equal-note problem for now.  */
11975           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11976               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11977                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11978                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11979             place = i3;
11980
11981           if (i2
11982               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11983                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11984                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11985                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11986             {
11987               if (place)
11988                 place2 = i2;
11989               else
11990                 place = i2;
11991             }
11992           break;
11993
11994         case REG_WAS_0:
11995           /* It is too much trouble to try to see if this note is still
11996              correct in all situations.  It is better to simply delete it.  */
11997           break;
11998
11999         case REG_RETVAL:
12000           /* If the insn previously containing this note still exists,
12001              put it back where it was.  Otherwise move it to the previous
12002              insn.  Adjust the corresponding REG_LIBCALL note.  */
12003           if (GET_CODE (from_insn) != NOTE)
12004             place = from_insn;
12005           else
12006             {
12007               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12008               place = prev_real_insn (from_insn);
12009               if (tem && place)
12010                 XEXP (tem, 0) = place;
12011             }
12012           break;
12013
12014         case REG_LIBCALL:
12015           /* This is handled similarly to REG_RETVAL.  */
12016           if (GET_CODE (from_insn) != NOTE)
12017             place = from_insn;
12018           else
12019             {
12020               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12021               place = next_real_insn (from_insn);
12022               if (tem && place)
12023                 XEXP (tem, 0) = place;
12024             }
12025           break;
12026
12027         case REG_DEAD:
12028           /* If the register is used as an input in I3, it dies there.
12029              Similarly for I2, if it is non-zero and adjacent to I3.
12030
12031              If the register is not used as an input in either I3 or I2
12032              and it is not one of the registers we were supposed to eliminate,
12033              there are two possibilities.  We might have a non-adjacent I2
12034              or we might have somehow eliminated an additional register
12035              from a computation.  For example, we might have had A & B where
12036              we discover that B will always be zero.  In this case we will
12037              eliminate the reference to A.
12038
12039              In both cases, we must search to see if we can find a previous
12040              use of A and put the death note there.  */
12041
12042           if (from_insn
12043               && GET_CODE (from_insn) == CALL_INSN
12044               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12045             place = from_insn;
12046           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12047             place = i3;
12048           else if (i2 != 0 && next_nonnote_insn (i2) == i3
12049                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12050             place = i2;
12051
12052           if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12053             break;
12054
12055           if (place == 0)
12056             {
12057               basic_block bb = BASIC_BLOCK (this_basic_block);
12058
12059               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12060                 {
12061                   if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
12062                     {
12063                       if (tem == bb->head)
12064                         break;
12065                       continue;
12066                     }
12067
12068                   /* If the register is being set at TEM, see if that is all
12069                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12070                      into a REG_UNUSED note instead.  */
12071                   if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12072                     {
12073                       rtx set = single_set (tem);
12074                       rtx inner_dest = 0;
12075 #ifdef HAVE_cc0
12076                       rtx cc0_setter = NULL_RTX;
12077 #endif
12078
12079                       if (set != 0)
12080                         for (inner_dest = SET_DEST (set);
12081                              GET_CODE (inner_dest) == STRICT_LOW_PART
12082                                || GET_CODE (inner_dest) == SUBREG
12083                                || GET_CODE (inner_dest) == ZERO_EXTRACT;
12084                              inner_dest = XEXP (inner_dest, 0))
12085                           ;
12086
12087                       /* Verify that it was the set, and not a clobber that
12088                          modified the register.
12089
12090                          CC0 targets must be careful to maintain setter/user
12091                          pairs.  If we cannot delete the setter due to side
12092                          effects, mark the user with an UNUSED note instead
12093                          of deleting it.  */
12094
12095                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12096                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12097 #ifdef HAVE_cc0
12098                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12099                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12100                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12101 #endif
12102                           )
12103                         {
12104                           /* Move the notes and links of TEM elsewhere.
12105                              This might delete other dead insns recursively.
12106                              First set the pattern to something that won't use
12107                              any register.  */
12108
12109                           PATTERN (tem) = pc_rtx;
12110
12111                           distribute_notes (REG_NOTES (tem), tem, tem,
12112                                             NULL_RTX, NULL_RTX, NULL_RTX);
12113                           distribute_links (LOG_LINKS (tem));
12114
12115                           PUT_CODE (tem, NOTE);
12116                           NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12117                           NOTE_SOURCE_FILE (tem) = 0;
12118
12119 #ifdef HAVE_cc0
12120                           /* Delete the setter too.  */
12121                           if (cc0_setter)
12122                             {
12123                               PATTERN (cc0_setter) = pc_rtx;
12124
12125                               distribute_notes (REG_NOTES (cc0_setter),
12126                                                 cc0_setter, cc0_setter,
12127                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12128                               distribute_links (LOG_LINKS (cc0_setter));
12129
12130                               PUT_CODE (cc0_setter, NOTE);
12131                               NOTE_LINE_NUMBER (cc0_setter)
12132                                 = NOTE_INSN_DELETED;
12133                               NOTE_SOURCE_FILE (cc0_setter) = 0;
12134                             }
12135 #endif
12136                         }
12137                       /* If the register is both set and used here, put the
12138                          REG_DEAD note here, but place a REG_UNUSED note
12139                          here too unless there already is one.  */
12140                       else if (reg_referenced_p (XEXP (note, 0),
12141                                                  PATTERN (tem)))
12142                         {
12143                           place = tem;
12144
12145                           if (! find_regno_note (tem, REG_UNUSED,
12146                                                  REGNO (XEXP (note, 0))))
12147                             REG_NOTES (tem)
12148                               = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12149                                                    REG_NOTES (tem));
12150                         }
12151                       else
12152                         {
12153                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12154
12155                           /*  If there isn't already a REG_UNUSED note, put one
12156                               here.  */
12157                           if (! find_regno_note (tem, REG_UNUSED,
12158                                                  REGNO (XEXP (note, 0))))
12159                             place = tem;
12160                           break;
12161                         }
12162                     }
12163                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12164                            || (GET_CODE (tem) == CALL_INSN
12165                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12166                     {
12167                       place = tem;
12168
12169                       /* If we are doing a 3->2 combination, and we have a
12170                          register which formerly died in i3 and was not used
12171                          by i2, which now no longer dies in i3 and is used in
12172                          i2 but does not die in i2, and place is between i2
12173                          and i3, then we may need to move a link from place to
12174                          i2.  */
12175                       if (i2 && INSN_UID (place) <= max_uid_cuid
12176                           && INSN_CUID (place) > INSN_CUID (i2)
12177                           && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
12178                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12179                         {
12180                           rtx links = LOG_LINKS (place);
12181                           LOG_LINKS (place) = 0;
12182                           distribute_links (links);
12183                         }
12184                       break;
12185                     }
12186
12187                   if (tem == bb->head)
12188                     break;
12189                 }
12190
12191               /* We haven't found an insn for the death note and it
12192                  is still a REG_DEAD note, but we have hit the beginning
12193                  of the block.  If the existing life info says the reg
12194                  was dead, there's nothing left to do.  Otherwise, we'll
12195                  need to do a global life update after combine.  */
12196               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0)
12197                 {
12198                   int regno = REGNO (XEXP (note, 0));
12199                   if (REGNO_REG_SET_P (bb->global_live_at_start, regno))
12200                     {
12201                       SET_BIT (refresh_blocks, this_basic_block);
12202                       need_refresh = 1;
12203                     }
12204                 }
12205             }
12206
12207           /* If the register is set or already dead at PLACE, we needn't do
12208              anything with this note if it is still a REG_DEAD note.
12209              We can here if it is set at all, not if is it totally replace,
12210              which is what `dead_or_set_p' checks, so also check for it being
12211              set partially.  */
12212
12213           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12214             {
12215               int regno = REGNO (XEXP (note, 0));
12216
12217               if (dead_or_set_p (place, XEXP (note, 0))
12218                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12219                 {
12220                   /* Unless the register previously died in PLACE, clear
12221                      reg_last_death.  [I no longer understand why this is
12222                      being done.] */
12223                   if (reg_last_death[regno] != place)
12224                     reg_last_death[regno] = 0;
12225                   place = 0;
12226                 }
12227               else
12228                 reg_last_death[regno] = place;
12229
12230               /* If this is a death note for a hard reg that is occupying
12231                  multiple registers, ensure that we are still using all
12232                  parts of the object.  If we find a piece of the object
12233                  that is unused, we must add a USE for that piece before
12234                  PLACE and put the appropriate REG_DEAD note on it.
12235
12236                  An alternative would be to put a REG_UNUSED for the pieces
12237                  on the insn that set the register, but that can't be done if
12238                  it is not in the same block.  It is simpler, though less
12239                  efficient, to add the USE insns.  */
12240
12241               if (place && regno < FIRST_PSEUDO_REGISTER
12242                   && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12243                 {
12244                   int endregno
12245                     = regno + HARD_REGNO_NREGS (regno,
12246                                                 GET_MODE (XEXP (note, 0)));
12247                   int all_used = 1;
12248                   int i;
12249
12250                   for (i = regno; i < endregno; i++)
12251                     if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12252                         && ! find_regno_fusage (place, USE, i))
12253                       {
12254                         rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12255                         rtx p;
12256
12257                         /* See if we already placed a USE note for this
12258                            register in front of PLACE.  */
12259                         for (p = place;
12260                              GET_CODE (PREV_INSN (p)) == INSN
12261                              && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12262                              p = PREV_INSN (p))
12263                           if (rtx_equal_p (piece,
12264                                            XEXP (PATTERN (PREV_INSN (p)), 0)))
12265                             {
12266                               p = 0;
12267                               break;
12268                             }
12269
12270                         if (p)
12271                           {
12272                             rtx use_insn
12273                               = emit_insn_before (gen_rtx_USE (VOIDmode,
12274                                                                piece),
12275                                                   p);
12276                             REG_NOTES (use_insn)
12277                               = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12278                                                    REG_NOTES (use_insn));
12279                           }
12280
12281                         all_used = 0;
12282                       }
12283
12284                   /* Check for the case where the register dying partially
12285                      overlaps the register set by this insn.  */
12286                   if (all_used)
12287                     for (i = regno; i < endregno; i++)
12288                       if (dead_or_set_regno_p (place, i))
12289                           {
12290                             all_used = 0;
12291                             break;
12292                           }
12293
12294                   if (! all_used)
12295                     {
12296                       /* Put only REG_DEAD notes for pieces that are
12297                          still used and that are not already dead or set.  */
12298
12299                       for (i = regno; i < endregno; i++)
12300                         {
12301                           rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12302
12303                           if ((reg_referenced_p (piece, PATTERN (place))
12304                                || (GET_CODE (place) == CALL_INSN
12305                                    && find_reg_fusage (place, USE, piece)))
12306                               && ! dead_or_set_p (place, piece)
12307                               && ! reg_bitfield_target_p (piece,
12308                                                           PATTERN (place)))
12309                             REG_NOTES (place)
12310                               = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12311                                                    REG_NOTES (place));
12312                         }
12313
12314                       place = 0;
12315                     }
12316                 }
12317             }
12318           break;
12319
12320         default:
12321           /* Any other notes should not be present at this point in the
12322              compilation.  */
12323           abort ();
12324         }
12325
12326       if (place)
12327         {
12328           XEXP (note, 1) = REG_NOTES (place);
12329           REG_NOTES (place) = note;
12330         }
12331       else if ((REG_NOTE_KIND (note) == REG_DEAD
12332                 || REG_NOTE_KIND (note) == REG_UNUSED)
12333                && GET_CODE (XEXP (note, 0)) == REG)
12334         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12335
12336       if (place2)
12337         {
12338           if ((REG_NOTE_KIND (note) == REG_DEAD
12339                || REG_NOTE_KIND (note) == REG_UNUSED)
12340               && GET_CODE (XEXP (note, 0)) == REG)
12341             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12342
12343           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12344                                                REG_NOTE_KIND (note),
12345                                                XEXP (note, 0),
12346                                                REG_NOTES (place2));
12347         }
12348     }
12349 }
12350 \f
12351 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12352    I3, I2, and I1 to new locations.  This is also called in one case to
12353    add a link pointing at I3 when I3's destination is changed.  */
12354
12355 static void
12356 distribute_links (links)
12357      rtx links;
12358 {
12359   rtx link, next_link;
12360
12361   for (link = links; link; link = next_link)
12362     {
12363       rtx place = 0;
12364       rtx insn;
12365       rtx set, reg;
12366
12367       next_link = XEXP (link, 1);
12368
12369       /* If the insn that this link points to is a NOTE or isn't a single
12370          set, ignore it.  In the latter case, it isn't clear what we
12371          can do other than ignore the link, since we can't tell which
12372          register it was for.  Such links wouldn't be used by combine
12373          anyway.
12374
12375          It is not possible for the destination of the target of the link to
12376          have been changed by combine.  The only potential of this is if we
12377          replace I3, I2, and I1 by I3 and I2.  But in that case the
12378          destination of I2 also remains unchanged.  */
12379
12380       if (GET_CODE (XEXP (link, 0)) == NOTE
12381           || (set = single_set (XEXP (link, 0))) == 0)
12382         continue;
12383
12384       reg = SET_DEST (set);
12385       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12386              || GET_CODE (reg) == SIGN_EXTRACT
12387              || GET_CODE (reg) == STRICT_LOW_PART)
12388         reg = XEXP (reg, 0);
12389
12390       /* A LOG_LINK is defined as being placed on the first insn that uses
12391          a register and points to the insn that sets the register.  Start
12392          searching at the next insn after the target of the link and stop
12393          when we reach a set of the register or the end of the basic block.
12394
12395          Note that this correctly handles the link that used to point from
12396          I3 to I2.  Also note that not much searching is typically done here
12397          since most links don't point very far away.  */
12398
12399       for (insn = NEXT_INSN (XEXP (link, 0));
12400            (insn && (this_basic_block == n_basic_blocks - 1
12401                      || BLOCK_HEAD (this_basic_block + 1) != insn));
12402            insn = NEXT_INSN (insn))
12403         if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12404             && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12405           {
12406             if (reg_referenced_p (reg, PATTERN (insn)))
12407               place = insn;
12408             break;
12409           }
12410         else if (GET_CODE (insn) == CALL_INSN
12411               && find_reg_fusage (insn, USE, reg))
12412           {
12413             place = insn;
12414             break;
12415           }
12416
12417       /* If we found a place to put the link, place it there unless there
12418          is already a link to the same insn as LINK at that point.  */
12419
12420       if (place)
12421         {
12422           rtx link2;
12423
12424           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12425             if (XEXP (link2, 0) == XEXP (link, 0))
12426               break;
12427
12428           if (link2 == 0)
12429             {
12430               XEXP (link, 1) = LOG_LINKS (place);
12431               LOG_LINKS (place) = link;
12432
12433               /* Set added_links_insn to the earliest insn we added a
12434                  link to.  */
12435               if (added_links_insn == 0
12436                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12437                 added_links_insn = place;
12438             }
12439         }
12440     }
12441 }
12442 \f
12443 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12444
12445 static int
12446 insn_cuid (insn)
12447      rtx insn;
12448 {
12449   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12450          && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12451     insn = NEXT_INSN (insn);
12452
12453   if (INSN_UID (insn) > max_uid_cuid)
12454     abort ();
12455
12456   return INSN_CUID (insn);
12457 }
12458 \f
12459 void
12460 dump_combine_stats (file)
12461      FILE *file;
12462 {
12463   fnotice
12464     (file,
12465      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12466      combine_attempts, combine_merges, combine_extras, combine_successes);
12467 }
12468
12469 void
12470 dump_combine_total_stats (file)
12471      FILE *file;
12472 {
12473   fnotice
12474     (file,
12475      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12476      total_attempts, total_merges, total_extras, total_successes);
12477 }