1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
101 #include "tree-pass.h"
103 #include "valtrack.h"
107 /* Number of attempts to combine instructions in this function. */
109 static int combine_attempts
;
111 /* Number of attempts that got as far as substitution in this function. */
113 static int combine_merges
;
115 /* Number of instructions combined with added SETs in this function. */
117 static int combine_extras
;
119 /* Number of instructions combined in this function. */
121 static int combine_successes
;
123 /* Totals over entire compilation. */
125 static int total_attempts
, total_merges
, total_extras
, total_successes
;
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
138 static rtx i2mod_old_rhs
;
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
142 static rtx i2mod_new_rhs
;
144 typedef struct reg_stat_struct
{
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
201 int last_set_table_tick
;
203 /* Record the value of label_tick when the value for register n is placed in
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
213 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
214 char last_set_sign_bit_copies
;
215 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
221 char last_set_invalid
;
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
233 If an entry is zero, it means that we don't know anything special. */
235 unsigned char sign_bit_copies
;
237 unsigned HOST_WIDE_INT nonzero_bits
;
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
243 int truncation_label
;
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
250 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
253 DEF_VEC_O(reg_stat_type
);
254 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
256 static VEC(reg_stat_type
,heap
) *reg_stat
;
258 /* Record the luid of the last insn that invalidated memory
259 (anything that writes memory, and subroutine calls, but not pushes). */
261 static int mem_last_set
;
263 /* Record the luid of the last CALL_INSN
264 so we can tell whether a potential combination crosses any calls. */
266 static int last_call_luid
;
268 /* When `subst' is called, this is the insn that is being modified
269 (by combining in a previous insn). The PATTERN of this insn
270 is still the old pattern partially modified and it should not be
271 looked at, but this may be used to examine the successors of the insn
272 to judge whether a simplification is valid. */
274 static rtx subst_insn
;
276 /* This is the lowest LUID that `subst' is currently dealing with.
277 get_last_value will not return a value if the register was set at or
278 after this LUID. If not for this mechanism, we could get confused if
279 I2 or I1 in try_combine were an insn that used the old value of a register
280 to obtain a new value. In that case, we might erroneously get the
281 new value of the register when we wanted the old one. */
283 static int subst_low_luid
;
285 /* This contains any hard registers that are used in newpat; reg_dead_at_p
286 must consider all these registers to be always live. */
288 static HARD_REG_SET newpat_used_regs
;
290 /* This is an insn to which a LOG_LINKS entry has been added. If this
291 insn is the earlier than I2 or I3, combine should rescan starting at
294 static rtx added_links_insn
;
296 /* Basic block in which we are performing combines. */
297 static basic_block this_basic_block
;
298 static bool optimize_this_for_speed_p
;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int max_uid_known
;
305 /* The following array records the insn_rtx_cost for every insn
306 in the instruction stream. */
308 static int *uid_insn_cost
;
310 /* The following array records the LOG_LINKS for every insn in the
311 instruction stream as struct insn_link pointers. */
315 struct insn_link
*next
;
318 static struct insn_link
**uid_log_links
;
320 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
321 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
323 #define FOR_EACH_LOG_LINK(L, INSN) \
324 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
326 /* Links for LOG_LINKS are allocated from this obstack. */
328 static struct obstack insn_link_obstack
;
330 /* Allocate a link. */
332 static inline struct insn_link
*
333 alloc_insn_link (rtx insn
, struct insn_link
*next
)
336 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
337 sizeof (struct insn_link
));
343 /* Incremented for each basic block. */
345 static int label_tick
;
347 /* Reset to label_tick for each extended basic block in scanning order. */
349 static int label_tick_ebb_start
;
351 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
352 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
354 static enum machine_mode nonzero_bits_mode
;
356 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
357 be safely used. It is zero while computing them and after combine has
358 completed. This former test prevents propagating values based on
359 previously set values, which can be incorrect if a variable is modified
362 static int nonzero_sign_valid
;
365 /* Record one modification to rtl structure
366 to be undone by storing old_contents into *where. */
368 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
374 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
375 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
378 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
379 num_undo says how many are currently recorded.
381 other_insn is nonzero if we have modified some other insn in the process
382 of working on subst_insn. It must be verified too. */
391 static struct undobuf undobuf
;
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences
;
398 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
400 unsigned HOST_WIDE_INT
,
401 unsigned HOST_WIDE_INT
*);
402 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
404 unsigned int, unsigned int *);
405 static void do_SUBST (rtx
*, rtx
);
406 static void do_SUBST_INT (int *, int);
407 static void init_reg_last (void);
408 static void setup_incoming_promotions (rtx
);
409 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
410 static int cant_combine_insn_p (rtx
);
411 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
412 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
413 static int contains_muldiv (rtx
);
414 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
415 static void undo_all (void);
416 static void undo_commit (void);
417 static rtx
*find_split_point (rtx
*, rtx
, bool);
418 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
419 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
420 static rtx
simplify_if_then_else (rtx
);
421 static rtx
simplify_set (rtx
);
422 static rtx
simplify_logical (rtx
);
423 static rtx
expand_compound_operation (rtx
);
424 static const_rtx
expand_field_assignment (const_rtx
);
425 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
426 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
427 static rtx
extract_left_shift (rtx
, int);
428 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
429 unsigned HOST_WIDE_INT
*);
430 static rtx
canon_reg_for_combine (rtx
, rtx
);
431 static rtx
force_to_mode (rtx
, enum machine_mode
,
432 unsigned HOST_WIDE_INT
, int);
433 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
434 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
435 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
436 static rtx
make_field_assignment (rtx
);
437 static rtx
apply_distributive_law (rtx
);
438 static rtx
distribute_and_simplify_rtx (rtx
, int);
439 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
440 unsigned HOST_WIDE_INT
);
441 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
442 unsigned HOST_WIDE_INT
);
443 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
444 HOST_WIDE_INT
, enum machine_mode
, int *);
445 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
446 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
448 static int recog_for_combine (rtx
*, rtx
, rtx
*);
449 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
450 static enum rtx_code
simplify_compare_const (enum rtx_code
, rtx
, rtx
*);
451 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
452 static void update_table_tick (rtx
);
453 static void record_value_for_reg (rtx
, rtx
, rtx
);
454 static void check_promoted_subreg (rtx
, rtx
);
455 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
456 static void record_dead_and_set_regs (rtx
);
457 static int get_last_value_validate (rtx
*, rtx
, int, int);
458 static rtx
get_last_value (const_rtx
);
459 static int use_crosses_set_p (const_rtx
, int);
460 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
461 static int reg_dead_at_p (rtx
, rtx
);
462 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
463 static int reg_bitfield_target_p (rtx
, rtx
);
464 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
465 static void distribute_links (struct insn_link
*);
466 static void mark_used_regs_combine (rtx
);
467 static void record_promoted_value (rtx
, rtx
);
468 static int unmentioned_reg_p_1 (rtx
*, void *);
469 static bool unmentioned_reg_p (rtx
, rtx
);
470 static int record_truncated_value (rtx
*, void *);
471 static void record_truncated_values (rtx
*, void *);
472 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
473 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
476 /* It is not safe to use ordinary gen_lowpart in combine.
477 See comments in gen_lowpart_for_combine. */
478 #undef RTL_HOOKS_GEN_LOWPART
479 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
481 /* Our implementation of gen_lowpart never emits a new pseudo. */
482 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
483 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
485 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
486 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
488 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
489 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
491 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
492 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
494 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
497 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
498 PATTERN can not be split. Otherwise, it returns an insn sequence.
499 This is a wrapper around split_insns which ensures that the
500 reg_stat vector is made larger if the splitter creates a new
504 combine_split_insns (rtx pattern
, rtx insn
)
509 ret
= split_insns (pattern
, insn
);
510 nregs
= max_reg_num ();
511 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
512 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
516 /* This is used by find_single_use to locate an rtx in LOC that
517 contains exactly one use of DEST, which is typically either a REG
518 or CC0. It returns a pointer to the innermost rtx expression
519 containing DEST. Appearances of DEST that are being used to
520 totally replace it are not counted. */
523 find_single_use_1 (rtx dest
, rtx
*loc
)
526 enum rtx_code code
= GET_CODE (x
);
542 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
543 of a REG that occupies all of the REG, the insn uses DEST if
544 it is mentioned in the destination or the source. Otherwise, we
545 need just check the source. */
546 if (GET_CODE (SET_DEST (x
)) != CC0
547 && GET_CODE (SET_DEST (x
)) != PC
548 && !REG_P (SET_DEST (x
))
549 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
550 && REG_P (SUBREG_REG (SET_DEST (x
)))
551 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
552 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
553 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
554 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
557 return find_single_use_1 (dest
, &SET_SRC (x
));
561 return find_single_use_1 (dest
, &XEXP (x
, 0));
567 /* If it wasn't one of the common cases above, check each expression and
568 vector of this code. Look for a unique usage of DEST. */
570 fmt
= GET_RTX_FORMAT (code
);
571 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
575 if (dest
== XEXP (x
, i
)
576 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
577 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
580 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
583 result
= this_result
;
584 else if (this_result
)
585 /* Duplicate usage. */
588 else if (fmt
[i
] == 'E')
592 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
594 if (XVECEXP (x
, i
, j
) == dest
596 && REG_P (XVECEXP (x
, i
, j
))
597 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
600 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
603 result
= this_result
;
604 else if (this_result
)
614 /* See if DEST, produced in INSN, is used only a single time in the
615 sequel. If so, return a pointer to the innermost rtx expression in which
618 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
620 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
621 care about REG_DEAD notes or LOG_LINKS.
623 Otherwise, we find the single use by finding an insn that has a
624 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
625 only referenced once in that insn, we know that it must be the first
626 and last insn referencing DEST. */
629 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
634 struct insn_link
*link
;
639 next
= NEXT_INSN (insn
);
641 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
644 result
= find_single_use_1 (dest
, &PATTERN (next
));
654 bb
= BLOCK_FOR_INSN (insn
);
655 for (next
= NEXT_INSN (insn
);
656 next
&& BLOCK_FOR_INSN (next
) == bb
;
657 next
= NEXT_INSN (next
))
658 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
660 FOR_EACH_LOG_LINK (link
, next
)
661 if (link
->insn
== insn
)
666 result
= find_single_use_1 (dest
, &PATTERN (next
));
676 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
677 insn. The substitution can be undone by undo_all. If INTO is already
678 set to NEWVAL, do not record this change. Because computing NEWVAL might
679 also call SUBST, we have to compute it before we put anything into
683 do_SUBST (rtx
*into
, rtx newval
)
688 if (oldval
== newval
)
691 /* We'd like to catch as many invalid transformations here as
692 possible. Unfortunately, there are way too many mode changes
693 that are perfectly valid, so we'd waste too much effort for
694 little gain doing the checks here. Focus on catching invalid
695 transformations involving integer constants. */
696 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
697 && CONST_INT_P (newval
))
699 /* Sanity check that we're replacing oldval with a CONST_INT
700 that is a valid sign-extension for the original mode. */
701 gcc_assert (INTVAL (newval
)
702 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
704 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
705 CONST_INT is not valid, because after the replacement, the
706 original mode would be gone. Unfortunately, we can't tell
707 when do_SUBST is called to replace the operand thereof, so we
708 perform this test on oldval instead, checking whether an
709 invalid replacement took place before we got here. */
710 gcc_assert (!(GET_CODE (oldval
) == SUBREG
711 && CONST_INT_P (SUBREG_REG (oldval
))));
712 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
713 && CONST_INT_P (XEXP (oldval
, 0))));
717 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
719 buf
= XNEW (struct undo
);
721 buf
->kind
= UNDO_RTX
;
723 buf
->old_contents
.r
= oldval
;
726 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
729 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
731 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
732 for the value of a HOST_WIDE_INT value (including CONST_INT) is
736 do_SUBST_INT (int *into
, int newval
)
741 if (oldval
== newval
)
745 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
747 buf
= XNEW (struct undo
);
749 buf
->kind
= UNDO_INT
;
751 buf
->old_contents
.i
= oldval
;
754 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
757 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
759 /* Similar to SUBST, but just substitute the mode. This is used when
760 changing the mode of a pseudo-register, so that any other
761 references to the entry in the regno_reg_rtx array will change as
765 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
768 enum machine_mode oldval
= GET_MODE (*into
);
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_MODE
;
780 buf
->old_contents
.m
= oldval
;
781 adjust_reg_mode (*into
, newval
);
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
789 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
792 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
795 struct insn_link
* oldval
= *into
;
797 if (oldval
== newval
)
801 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
803 buf
= XNEW (struct undo
);
805 buf
->kind
= UNDO_LINKS
;
807 buf
->old_contents
.l
= oldval
;
810 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
813 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
816 /* Subroutine of try_combine. Determine whether the replacement patterns
817 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
818 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
819 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
820 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
821 of all the instructions can be estimated and the replacements are more
822 expensive than the original sequence. */
825 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
826 rtx newi2pat
, rtx newotherpat
)
828 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
829 int new_i2_cost
, new_i3_cost
;
830 int old_cost
, new_cost
;
832 /* Lookup the original insn_rtx_costs. */
833 i2_cost
= INSN_COST (i2
);
834 i3_cost
= INSN_COST (i3
);
838 i1_cost
= INSN_COST (i1
);
841 i0_cost
= INSN_COST (i0
);
842 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
843 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
847 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
848 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
854 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
855 i1_cost
= i0_cost
= 0;
858 /* Calculate the replacement insn_rtx_costs. */
859 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
862 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
863 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
864 ? new_i2_cost
+ new_i3_cost
: 0;
868 new_cost
= new_i3_cost
;
872 if (undobuf
.other_insn
)
874 int old_other_cost
, new_other_cost
;
876 old_other_cost
= INSN_COST (undobuf
.other_insn
);
877 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
878 if (old_other_cost
> 0 && new_other_cost
> 0)
880 old_cost
+= old_other_cost
;
881 new_cost
+= new_other_cost
;
887 /* Disallow this combination if both new_cost and old_cost are greater than
888 zero, and new_cost is greater than old cost. */
889 if (old_cost
> 0 && new_cost
> old_cost
)
896 "rejecting combination of insns %d, %d, %d and %d\n",
897 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
899 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
900 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
905 "rejecting combination of insns %d, %d and %d\n",
906 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
907 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
908 i1_cost
, i2_cost
, i3_cost
, old_cost
);
913 "rejecting combination of insns %d and %d\n",
914 INSN_UID (i2
), INSN_UID (i3
));
915 fprintf (dump_file
, "original costs %d + %d = %d\n",
916 i2_cost
, i3_cost
, old_cost
);
921 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
922 new_i2_cost
, new_i3_cost
, new_cost
);
925 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
931 /* Update the uid_insn_cost array with the replacement costs. */
932 INSN_COST (i2
) = new_i2_cost
;
933 INSN_COST (i3
) = new_i3_cost
;
945 /* Delete any insns that copy a register to itself. */
948 delete_noop_moves (void)
955 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
957 next
= NEXT_INSN (insn
);
958 if (INSN_P (insn
) && noop_move_p (insn
))
961 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
963 delete_insn_and_edges (insn
);
970 /* Fill in log links field for all insns. */
973 create_log_links (void)
977 df_ref
*def_vec
, *use_vec
;
979 next_use
= XCNEWVEC (rtx
, max_reg_num ());
981 /* Pass through each block from the end, recording the uses of each
982 register and establishing log links when def is encountered.
983 Note that we do not clear next_use array in order to save time,
984 so we have to test whether the use is in the same basic block as def.
986 There are a few cases below when we do not consider the definition or
987 usage -- these are taken from original flow.c did. Don't ask me why it is
988 done this way; I don't know and if it works, I don't want to know. */
992 FOR_BB_INSNS_REVERSE (bb
, insn
)
994 if (!NONDEBUG_INSN_P (insn
))
997 /* Log links are created only once. */
998 gcc_assert (!LOG_LINKS (insn
));
1000 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
1002 df_ref def
= *def_vec
;
1003 int regno
= DF_REF_REGNO (def
);
1006 if (!next_use
[regno
])
1009 /* Do not consider if it is pre/post modification in MEM. */
1010 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1013 /* Do not make the log link for frame pointer. */
1014 if ((regno
== FRAME_POINTER_REGNUM
1015 && (! reload_completed
|| frame_pointer_needed
))
1016 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1017 || (regno
== HARD_FRAME_POINTER_REGNUM
1018 && (! reload_completed
|| frame_pointer_needed
))
1020 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1021 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1026 use_insn
= next_use
[regno
];
1027 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1031 We don't build a LOG_LINK for hard registers contained
1032 in ASM_OPERANDs. If these registers get replaced,
1033 we might wind up changing the semantics of the insn,
1034 even if reload can make what appear to be valid
1035 assignments later. */
1036 if (regno
>= FIRST_PSEUDO_REGISTER
1037 || asm_noperands (PATTERN (use_insn
)) < 0)
1039 /* Don't add duplicate links between instructions. */
1040 struct insn_link
*links
;
1041 FOR_EACH_LOG_LINK (links
, use_insn
)
1042 if (insn
== links
->insn
)
1046 LOG_LINKS (use_insn
)
1047 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1050 next_use
[regno
] = NULL_RTX
;
1053 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1055 df_ref use
= *use_vec
;
1056 int regno
= DF_REF_REGNO (use
);
1058 /* Do not consider the usage of the stack pointer
1059 by function call. */
1060 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1063 next_use
[regno
] = insn
;
1071 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1072 true if we found a LOG_LINK that proves that A feeds B. This only works
1073 if there are no instructions between A and B which could have a link
1074 depending on A, since in that case we would not record a link for B.
1075 We also check the implicit dependency created by a cc0 setter/user
1079 insn_a_feeds_b (rtx a
, rtx b
)
1081 struct insn_link
*links
;
1082 FOR_EACH_LOG_LINK (links
, b
)
1083 if (links
->insn
== a
)
1092 /* Main entry point for combiner. F is the first insn of the function.
1093 NREGS is the first unused pseudo-reg number.
1095 Return nonzero if the combiner has turned an indirect jump
1096 instruction into a direct jump. */
1098 combine_instructions (rtx f
, unsigned int nregs
)
1104 struct insn_link
*links
, *nextlinks
;
1106 basic_block last_bb
;
1108 int new_direct_jump_p
= 0;
1110 for (first
= f
; first
&& !INSN_P (first
); )
1111 first
= NEXT_INSN (first
);
1115 combine_attempts
= 0;
1118 combine_successes
= 0;
1120 rtl_hooks
= combine_rtl_hooks
;
1122 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1124 init_recog_no_volatile ();
1126 /* Allocate array for insn info. */
1127 max_uid_known
= get_max_uid ();
1128 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1129 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1130 gcc_obstack_init (&insn_link_obstack
);
1132 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1134 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1135 problems when, for example, we have j <<= 1 in a loop. */
1137 nonzero_sign_valid
= 0;
1138 label_tick
= label_tick_ebb_start
= 1;
1140 /* Scan all SETs and see if we can deduce anything about what
1141 bits are known to be zero for some registers and how many copies
1142 of the sign bit are known to exist for those registers.
1144 Also set any known values so that we can use it while searching
1145 for what bits are known to be set. */
1147 setup_incoming_promotions (first
);
1148 /* Allow the entry block and the first block to fall into the same EBB.
1149 Conceptually the incoming promotions are assigned to the entry block. */
1150 last_bb
= ENTRY_BLOCK_PTR
;
1152 create_log_links ();
1153 FOR_EACH_BB (this_basic_block
)
1155 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1160 if (!single_pred_p (this_basic_block
)
1161 || single_pred (this_basic_block
) != last_bb
)
1162 label_tick_ebb_start
= label_tick
;
1163 last_bb
= this_basic_block
;
1165 FOR_BB_INSNS (this_basic_block
, insn
)
1166 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1172 subst_low_luid
= DF_INSN_LUID (insn
);
1175 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1177 record_dead_and_set_regs (insn
);
1180 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1181 if (REG_NOTE_KIND (links
) == REG_INC
)
1182 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1186 /* Record the current insn_rtx_cost of this instruction. */
1187 if (NONJUMP_INSN_P (insn
))
1188 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1189 optimize_this_for_speed_p
);
1191 fprintf(dump_file
, "insn_cost %d: %d\n",
1192 INSN_UID (insn
), INSN_COST (insn
));
1196 nonzero_sign_valid
= 1;
1198 /* Now scan all the insns in forward order. */
1199 label_tick
= label_tick_ebb_start
= 1;
1201 setup_incoming_promotions (first
);
1202 last_bb
= ENTRY_BLOCK_PTR
;
1204 FOR_EACH_BB (this_basic_block
)
1206 rtx last_combined_insn
= NULL_RTX
;
1207 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1212 if (!single_pred_p (this_basic_block
)
1213 || single_pred (this_basic_block
) != last_bb
)
1214 label_tick_ebb_start
= label_tick
;
1215 last_bb
= this_basic_block
;
1217 rtl_profile_for_bb (this_basic_block
);
1218 for (insn
= BB_HEAD (this_basic_block
);
1219 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1220 insn
= next
? next
: NEXT_INSN (insn
))
1223 if (NONDEBUG_INSN_P (insn
))
1225 while (last_combined_insn
1226 && INSN_DELETED_P (last_combined_insn
))
1227 last_combined_insn
= PREV_INSN (last_combined_insn
);
1228 if (last_combined_insn
== NULL_RTX
1229 || BARRIER_P (last_combined_insn
)
1230 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1231 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1232 last_combined_insn
= insn
;
1234 /* See if we know about function return values before this
1235 insn based upon SUBREG flags. */
1236 check_promoted_subreg (insn
, PATTERN (insn
));
1238 /* See if we can find hardregs and subreg of pseudos in
1239 narrower modes. This could help turning TRUNCATEs
1241 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1243 /* Try this insn with each insn it links back to. */
1245 FOR_EACH_LOG_LINK (links
, insn
)
1246 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1247 NULL_RTX
, &new_direct_jump_p
,
1248 last_combined_insn
)) != 0)
1251 /* Try each sequence of three linked insns ending with this one. */
1253 FOR_EACH_LOG_LINK (links
, insn
)
1255 rtx link
= links
->insn
;
1257 /* If the linked insn has been replaced by a note, then there
1258 is no point in pursuing this chain any further. */
1262 FOR_EACH_LOG_LINK (nextlinks
, link
)
1263 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1264 NULL_RTX
, &new_direct_jump_p
,
1265 last_combined_insn
)) != 0)
1270 /* Try to combine a jump insn that uses CC0
1271 with a preceding insn that sets CC0, and maybe with its
1272 logical predecessor as well.
1273 This is how we make decrement-and-branch insns.
1274 We need this special code because data flow connections
1275 via CC0 do not get entered in LOG_LINKS. */
1278 && (prev
= prev_nonnote_insn (insn
)) != 0
1279 && NONJUMP_INSN_P (prev
)
1280 && sets_cc0_p (PATTERN (prev
)))
1282 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1284 last_combined_insn
)) != 0)
1287 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1288 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1289 NULL_RTX
, &new_direct_jump_p
,
1290 last_combined_insn
)) != 0)
1294 /* Do the same for an insn that explicitly references CC0. */
1295 if (NONJUMP_INSN_P (insn
)
1296 && (prev
= prev_nonnote_insn (insn
)) != 0
1297 && NONJUMP_INSN_P (prev
)
1298 && sets_cc0_p (PATTERN (prev
))
1299 && GET_CODE (PATTERN (insn
)) == SET
1300 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1302 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1304 last_combined_insn
)) != 0)
1307 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1308 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1309 NULL_RTX
, &new_direct_jump_p
,
1310 last_combined_insn
)) != 0)
1314 /* Finally, see if any of the insns that this insn links to
1315 explicitly references CC0. If so, try this insn, that insn,
1316 and its predecessor if it sets CC0. */
1317 FOR_EACH_LOG_LINK (links
, insn
)
1318 if (NONJUMP_INSN_P (links
->insn
)
1319 && GET_CODE (PATTERN (links
->insn
)) == SET
1320 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1321 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1322 && NONJUMP_INSN_P (prev
)
1323 && sets_cc0_p (PATTERN (prev
))
1324 && (next
= try_combine (insn
, links
->insn
,
1325 prev
, NULL_RTX
, &new_direct_jump_p
,
1326 last_combined_insn
)) != 0)
1330 /* Try combining an insn with two different insns whose results it
1332 FOR_EACH_LOG_LINK (links
, insn
)
1333 for (nextlinks
= links
->next
; nextlinks
;
1334 nextlinks
= nextlinks
->next
)
1335 if ((next
= try_combine (insn
, links
->insn
,
1336 nextlinks
->insn
, NULL_RTX
,
1338 last_combined_insn
)) != 0)
1341 /* Try four-instruction combinations. */
1342 FOR_EACH_LOG_LINK (links
, insn
)
1344 struct insn_link
*next1
;
1345 rtx link
= links
->insn
;
1347 /* If the linked insn has been replaced by a note, then there
1348 is no point in pursuing this chain any further. */
1352 FOR_EACH_LOG_LINK (next1
, link
)
1354 rtx link1
= next1
->insn
;
1357 /* I0 -> I1 -> I2 -> I3. */
1358 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1359 if ((next
= try_combine (insn
, link
, link1
,
1362 last_combined_insn
)) != 0)
1364 /* I0, I1 -> I2, I2 -> I3. */
1365 for (nextlinks
= next1
->next
; nextlinks
;
1366 nextlinks
= nextlinks
->next
)
1367 if ((next
= try_combine (insn
, link
, link1
,
1370 last_combined_insn
)) != 0)
1374 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1376 rtx link1
= next1
->insn
;
1379 /* I0 -> I2; I1, I2 -> I3. */
1380 FOR_EACH_LOG_LINK (nextlinks
, link
)
1381 if ((next
= try_combine (insn
, link
, link1
,
1384 last_combined_insn
)) != 0)
1386 /* I0 -> I1; I1, I2 -> I3. */
1387 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1388 if ((next
= try_combine (insn
, link
, link1
,
1391 last_combined_insn
)) != 0)
1396 /* Try this insn with each REG_EQUAL note it links back to. */
1397 FOR_EACH_LOG_LINK (links
, insn
)
1400 rtx temp
= links
->insn
;
1401 if ((set
= single_set (temp
)) != 0
1402 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1403 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1404 /* Avoid using a register that may already been marked
1405 dead by an earlier instruction. */
1406 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1407 && (GET_MODE (note
) == VOIDmode
1408 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1409 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1411 /* Temporarily replace the set's source with the
1412 contents of the REG_EQUAL note. The insn will
1413 be deleted or recognized by try_combine. */
1414 rtx orig
= SET_SRC (set
);
1415 SET_SRC (set
) = note
;
1417 i2mod_old_rhs
= copy_rtx (orig
);
1418 i2mod_new_rhs
= copy_rtx (note
);
1419 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1421 last_combined_insn
);
1425 SET_SRC (set
) = orig
;
1430 record_dead_and_set_regs (insn
);
1438 default_rtl_profile ();
1440 new_direct_jump_p
|= purge_all_dead_edges ();
1441 delete_noop_moves ();
1444 obstack_free (&insn_link_obstack
, NULL
);
1445 free (uid_log_links
);
1446 free (uid_insn_cost
);
1447 VEC_free (reg_stat_type
, heap
, reg_stat
);
1450 struct undo
*undo
, *next
;
1451 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1459 total_attempts
+= combine_attempts
;
1460 total_merges
+= combine_merges
;
1461 total_extras
+= combine_extras
;
1462 total_successes
+= combine_successes
;
1464 nonzero_sign_valid
= 0;
1465 rtl_hooks
= general_rtl_hooks
;
1467 /* Make recognizer allow volatile MEMs again. */
1470 return new_direct_jump_p
;
1473 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1476 init_reg_last (void)
1481 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1482 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1485 /* Set up any promoted values for incoming argument registers. */
1488 setup_incoming_promotions (rtx first
)
1491 bool strictly_local
= false;
1493 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1494 arg
= DECL_CHAIN (arg
))
1496 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1498 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1500 /* Only continue if the incoming argument is in a register. */
1504 /* Determine, if possible, whether all call sites of the current
1505 function lie within the current compilation unit. (This does
1506 take into account the exporting of a function via taking its
1507 address, and so forth.) */
1508 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1510 /* The mode and signedness of the argument before any promotions happen
1511 (equal to the mode of the pseudo holding it at that stage). */
1512 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1513 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1515 /* The mode and signedness of the argument after any source language and
1516 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1517 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1518 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1520 /* The mode and signedness of the argument as it is actually passed,
1521 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1522 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1523 TREE_TYPE (cfun
->decl
), 0);
1525 /* The mode of the register in which the argument is being passed. */
1526 mode4
= GET_MODE (reg
);
1528 /* Eliminate sign extensions in the callee when:
1529 (a) A mode promotion has occurred; */
1532 /* (b) The mode of the register is the same as the mode of
1533 the argument as it is passed; */
1536 /* (c) There's no language level extension; */
1539 /* (c.1) All callers are from the current compilation unit. If that's
1540 the case we don't have to rely on an ABI, we only have to know
1541 what we're generating right now, and we know that we will do the
1542 mode1 to mode2 promotion with the given sign. */
1543 else if (!strictly_local
)
1545 /* (c.2) The combination of the two promotions is useful. This is
1546 true when the signs match, or if the first promotion is unsigned.
1547 In the later case, (sign_extend (zero_extend x)) is the same as
1548 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1554 /* Record that the value was promoted from mode1 to mode3,
1555 so that any sign extension at the head of the current
1556 function may be eliminated. */
1557 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1558 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1559 record_value_for_reg (reg
, first
, x
);
1563 /* Called via note_stores. If X is a pseudo that is narrower than
1564 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1566 If we are setting only a portion of X and we can't figure out what
1567 portion, assume all bits will be used since we don't know what will
1570 Similarly, set how many bits of X are known to be copies of the sign bit
1571 at all locations in the function. This is the smallest number implied
1575 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1577 rtx insn
= (rtx
) data
;
1581 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1582 /* If this register is undefined at the start of the file, we can't
1583 say what its contents were. */
1584 && ! REGNO_REG_SET_P
1585 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1586 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1588 reg_stat_type
*rsp
= &VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1590 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1592 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1593 rsp
->sign_bit_copies
= 1;
1597 /* If this register is being initialized using itself, and the
1598 register is uninitialized in this basic block, and there are
1599 no LOG_LINKS which set the register, then part of the
1600 register is uninitialized. In that case we can't assume
1601 anything about the number of nonzero bits.
1603 ??? We could do better if we checked this in
1604 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1605 could avoid making assumptions about the insn which initially
1606 sets the register, while still using the information in other
1607 insns. We would have to be careful to check every insn
1608 involved in the combination. */
1611 && reg_referenced_p (x
, PATTERN (insn
))
1612 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1615 struct insn_link
*link
;
1617 FOR_EACH_LOG_LINK (link
, insn
)
1618 if (dead_or_set_p (link
->insn
, x
))
1622 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1623 rsp
->sign_bit_copies
= 1;
1628 /* If this is a complex assignment, see if we can convert it into a
1629 simple assignment. */
1630 set
= expand_field_assignment (set
);
1632 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1633 set what we know about X. */
1635 if (SET_DEST (set
) == x
1636 || (paradoxical_subreg_p (SET_DEST (set
))
1637 && SUBREG_REG (SET_DEST (set
)) == x
))
1639 rtx src
= SET_SRC (set
);
1641 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1642 /* If X is narrower than a word and SRC is a non-negative
1643 constant that would appear negative in the mode of X,
1644 sign-extend it for use in reg_stat[].nonzero_bits because some
1645 machines (maybe most) will actually do the sign-extension
1646 and this is the conservative approach.
1648 ??? For 2.5, try to tighten up the MD files in this regard
1649 instead of this kludge. */
1651 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1652 && CONST_INT_P (src
)
1654 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1655 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1658 /* Don't call nonzero_bits if it cannot change anything. */
1659 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1660 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1661 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1662 if (rsp
->sign_bit_copies
== 0
1663 || rsp
->sign_bit_copies
> num
)
1664 rsp
->sign_bit_copies
= num
;
1668 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1669 rsp
->sign_bit_copies
= 1;
1674 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1675 optionally insns that were previously combined into I3 or that will be
1676 combined into the merger of INSN and I3. The order is PRED, PRED2,
1677 INSN, SUCC, SUCC2, I3.
1679 Return 0 if the combination is not allowed for any reason.
1681 If the combination is allowed, *PDEST will be set to the single
1682 destination of INSN and *PSRC to the single source, and this function
1686 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1687 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1688 rtx
*pdest
, rtx
*psrc
)
1697 bool all_adjacent
= true;
1698 int (*is_volatile_p
) (const_rtx
);
1704 if (next_active_insn (succ2
) != i3
)
1705 all_adjacent
= false;
1706 if (next_active_insn (succ
) != succ2
)
1707 all_adjacent
= false;
1709 else if (next_active_insn (succ
) != i3
)
1710 all_adjacent
= false;
1711 if (next_active_insn (insn
) != succ
)
1712 all_adjacent
= false;
1714 else if (next_active_insn (insn
) != i3
)
1715 all_adjacent
= false;
1717 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1718 or a PARALLEL consisting of such a SET and CLOBBERs.
1720 If INSN has CLOBBER parallel parts, ignore them for our processing.
1721 By definition, these happen during the execution of the insn. When it
1722 is merged with another insn, all bets are off. If they are, in fact,
1723 needed and aren't also supplied in I3, they may be added by
1724 recog_for_combine. Otherwise, it won't match.
1726 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1729 Get the source and destination of INSN. If more than one, can't
1732 if (GET_CODE (PATTERN (insn
)) == SET
)
1733 set
= PATTERN (insn
);
1734 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1735 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1737 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1739 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1741 switch (GET_CODE (elt
))
1743 /* This is important to combine floating point insns
1744 for the SH4 port. */
1746 /* Combining an isolated USE doesn't make sense.
1747 We depend here on combinable_i3pat to reject them. */
1748 /* The code below this loop only verifies that the inputs of
1749 the SET in INSN do not change. We call reg_set_between_p
1750 to verify that the REG in the USE does not change between
1752 If the USE in INSN was for a pseudo register, the matching
1753 insn pattern will likely match any register; combining this
1754 with any other USE would only be safe if we knew that the
1755 used registers have identical values, or if there was
1756 something to tell them apart, e.g. different modes. For
1757 now, we forgo such complicated tests and simply disallow
1758 combining of USES of pseudo registers with any other USE. */
1759 if (REG_P (XEXP (elt
, 0))
1760 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1762 rtx i3pat
= PATTERN (i3
);
1763 int i
= XVECLEN (i3pat
, 0) - 1;
1764 unsigned int regno
= REGNO (XEXP (elt
, 0));
1768 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1770 if (GET_CODE (i3elt
) == USE
1771 && REG_P (XEXP (i3elt
, 0))
1772 && (REGNO (XEXP (i3elt
, 0)) == regno
1773 ? reg_set_between_p (XEXP (elt
, 0),
1774 PREV_INSN (insn
), i3
)
1775 : regno
>= FIRST_PSEUDO_REGISTER
))
1782 /* We can ignore CLOBBERs. */
1787 /* Ignore SETs whose result isn't used but not those that
1788 have side-effects. */
1789 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1790 && insn_nothrow_p (insn
)
1791 && !side_effects_p (elt
))
1794 /* If we have already found a SET, this is a second one and
1795 so we cannot combine with this insn. */
1803 /* Anything else means we can't combine. */
1809 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1810 so don't do anything with it. */
1811 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1820 /* The simplification in expand_field_assignment may call back to
1821 get_last_value, so set safe guard here. */
1822 subst_low_luid
= DF_INSN_LUID (insn
);
1824 set
= expand_field_assignment (set
);
1825 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1827 /* Don't eliminate a store in the stack pointer. */
1828 if (dest
== stack_pointer_rtx
1829 /* Don't combine with an insn that sets a register to itself if it has
1830 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1831 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1832 /* Can't merge an ASM_OPERANDS. */
1833 || GET_CODE (src
) == ASM_OPERANDS
1834 /* Can't merge a function call. */
1835 || GET_CODE (src
) == CALL
1836 /* Don't eliminate a function call argument. */
1838 && (find_reg_fusage (i3
, USE
, dest
)
1840 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1841 && global_regs
[REGNO (dest
)])))
1842 /* Don't substitute into an incremented register. */
1843 || FIND_REG_INC_NOTE (i3
, dest
)
1844 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1845 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1846 /* Don't substitute into a non-local goto, this confuses CFG. */
1847 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1848 /* Make sure that DEST is not used after SUCC but before I3. */
1851 && (reg_used_between_p (dest
, succ2
, i3
)
1852 || reg_used_between_p (dest
, succ
, succ2
)))
1853 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1854 /* Make sure that the value that is to be substituted for the register
1855 does not use any registers whose values alter in between. However,
1856 If the insns are adjacent, a use can't cross a set even though we
1857 think it might (this can happen for a sequence of insns each setting
1858 the same destination; last_set of that register might point to
1859 a NOTE). If INSN has a REG_EQUIV note, the register is always
1860 equivalent to the memory so the substitution is valid even if there
1861 are intervening stores. Also, don't move a volatile asm or
1862 UNSPEC_VOLATILE across any other insns. */
1865 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1866 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1867 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1868 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1869 /* Don't combine across a CALL_INSN, because that would possibly
1870 change whether the life span of some REGs crosses calls or not,
1871 and it is a pain to update that information.
1872 Exception: if source is a constant, moving it later can't hurt.
1873 Accept that as a special case. */
1874 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1877 /* DEST must either be a REG or CC0. */
1880 /* If register alignment is being enforced for multi-word items in all
1881 cases except for parameters, it is possible to have a register copy
1882 insn referencing a hard register that is not allowed to contain the
1883 mode being copied and which would not be valid as an operand of most
1884 insns. Eliminate this problem by not combining with such an insn.
1886 Also, on some machines we don't want to extend the life of a hard
1890 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1891 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1892 /* Don't extend the life of a hard register unless it is
1893 user variable (if we have few registers) or it can't
1894 fit into the desired register (meaning something special
1896 Also avoid substituting a return register into I3, because
1897 reload can't handle a conflict with constraints of other
1899 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1900 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1903 else if (GET_CODE (dest
) != CC0
)
1907 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1908 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1909 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1911 /* Don't substitute for a register intended as a clobberable
1913 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1914 if (rtx_equal_p (reg
, dest
))
1917 /* If the clobber represents an earlyclobber operand, we must not
1918 substitute an expression containing the clobbered register.
1919 As we do not analyze the constraint strings here, we have to
1920 make the conservative assumption. However, if the register is
1921 a fixed hard reg, the clobber cannot represent any operand;
1922 we leave it up to the machine description to either accept or
1923 reject use-and-clobber patterns. */
1925 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1926 || !fixed_regs
[REGNO (reg
)])
1927 if (reg_overlap_mentioned_p (reg
, src
))
1931 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1932 or not), reject, unless nothing volatile comes between it and I3 */
1934 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1936 /* Make sure neither succ nor succ2 contains a volatile reference. */
1937 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1939 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1941 /* We'll check insns between INSN and I3 below. */
1944 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1945 to be an explicit register variable, and was chosen for a reason. */
1947 if (GET_CODE (src
) == ASM_OPERANDS
1948 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1951 /* If INSN contains volatile references (specifically volatile MEMs),
1952 we cannot combine across any other volatile references.
1953 Even if INSN doesn't contain volatile references, any intervening
1954 volatile insn might affect machine state. */
1956 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
1960 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1961 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
1964 /* If INSN contains an autoincrement or autodecrement, make sure that
1965 register is not used between there and I3, and not already used in
1966 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1967 Also insist that I3 not be a jump; if it were one
1968 and the incremented register were spilled, we would lose. */
1971 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1972 if (REG_NOTE_KIND (link
) == REG_INC
1974 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1975 || (pred
!= NULL_RTX
1976 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1977 || (pred2
!= NULL_RTX
1978 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1979 || (succ
!= NULL_RTX
1980 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1981 || (succ2
!= NULL_RTX
1982 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1983 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1988 /* Don't combine an insn that follows a CC0-setting insn.
1989 An insn that uses CC0 must not be separated from the one that sets it.
1990 We do, however, allow I2 to follow a CC0-setting insn if that insn
1991 is passed as I1; in that case it will be deleted also.
1992 We also allow combining in this case if all the insns are adjacent
1993 because that would leave the two CC0 insns adjacent as well.
1994 It would be more logical to test whether CC0 occurs inside I1 or I2,
1995 but that would be much slower, and this ought to be equivalent. */
1997 p
= prev_nonnote_insn (insn
);
1998 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2003 /* If we get here, we have passed all the tests and the combination is
2012 /* LOC is the location within I3 that contains its pattern or the component
2013 of a PARALLEL of the pattern. We validate that it is valid for combining.
2015 One problem is if I3 modifies its output, as opposed to replacing it
2016 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2017 doing so would produce an insn that is not equivalent to the original insns.
2021 (set (reg:DI 101) (reg:DI 100))
2022 (set (subreg:SI (reg:DI 101) 0) <foo>)
2024 This is NOT equivalent to:
2026 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2027 (set (reg:DI 101) (reg:DI 100))])
2029 Not only does this modify 100 (in which case it might still be valid
2030 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2032 We can also run into a problem if I2 sets a register that I1
2033 uses and I1 gets directly substituted into I3 (not via I2). In that
2034 case, we would be getting the wrong value of I2DEST into I3, so we
2035 must reject the combination. This case occurs when I2 and I1 both
2036 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2037 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2038 of a SET must prevent combination from occurring. The same situation
2039 can occur for I0, in which case I0_NOT_IN_SRC is set.
2041 Before doing the above check, we first try to expand a field assignment
2042 into a set of logical operations.
2044 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2045 we place a register that is both set and used within I3. If more than one
2046 such register is detected, we fail.
2048 Return 1 if the combination is valid, zero otherwise. */
2051 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2052 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2056 if (GET_CODE (x
) == SET
)
2059 rtx dest
= SET_DEST (set
);
2060 rtx src
= SET_SRC (set
);
2061 rtx inner_dest
= dest
;
2064 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2065 || GET_CODE (inner_dest
) == SUBREG
2066 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2067 inner_dest
= XEXP (inner_dest
, 0);
2069 /* Check for the case where I3 modifies its output, as discussed
2070 above. We don't want to prevent pseudos from being combined
2071 into the address of a MEM, so only prevent the combination if
2072 i1 or i2 set the same MEM. */
2073 if ((inner_dest
!= dest
&&
2074 (!MEM_P (inner_dest
)
2075 || rtx_equal_p (i2dest
, inner_dest
)
2076 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2077 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2078 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2079 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2080 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2082 /* This is the same test done in can_combine_p except we can't test
2083 all_adjacent; we don't have to, since this instruction will stay
2084 in place, thus we are not considering increasing the lifetime of
2087 Also, if this insn sets a function argument, combining it with
2088 something that might need a spill could clobber a previous
2089 function argument; the all_adjacent test in can_combine_p also
2090 checks this; here, we do a more specific test for this case. */
2092 || (REG_P (inner_dest
)
2093 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2094 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2095 GET_MODE (inner_dest
))))
2096 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2097 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2100 /* If DEST is used in I3, it is being killed in this insn, so
2101 record that for later. We have to consider paradoxical
2102 subregs here, since they kill the whole register, but we
2103 ignore partial subregs, STRICT_LOW_PART, etc.
2104 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2105 STACK_POINTER_REGNUM, since these are always considered to be
2106 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2108 if (GET_CODE (subdest
) == SUBREG
2109 && (GET_MODE_SIZE (GET_MODE (subdest
))
2110 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2111 subdest
= SUBREG_REG (subdest
);
2114 && reg_referenced_p (subdest
, PATTERN (i3
))
2115 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2116 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2117 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2119 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2120 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2121 || ! fixed_regs
[REGNO (subdest
)])
2123 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2125 if (*pi3dest_killed
)
2128 *pi3dest_killed
= subdest
;
2132 else if (GET_CODE (x
) == PARALLEL
)
2136 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2137 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2138 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2145 /* Return 1 if X is an arithmetic expression that contains a multiplication
2146 and division. We don't count multiplications by powers of two here. */
2149 contains_muldiv (rtx x
)
2151 switch (GET_CODE (x
))
2153 case MOD
: case DIV
: case UMOD
: case UDIV
:
2157 return ! (CONST_INT_P (XEXP (x
, 1))
2158 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2161 return contains_muldiv (XEXP (x
, 0))
2162 || contains_muldiv (XEXP (x
, 1));
2165 return contains_muldiv (XEXP (x
, 0));
2171 /* Determine whether INSN can be used in a combination. Return nonzero if
2172 not. This is used in try_combine to detect early some cases where we
2173 can't perform combinations. */
2176 cant_combine_insn_p (rtx insn
)
2181 /* If this isn't really an insn, we can't do anything.
2182 This can occur when flow deletes an insn that it has merged into an
2183 auto-increment address. */
2184 if (! INSN_P (insn
))
2187 /* Never combine loads and stores involving hard regs that are likely
2188 to be spilled. The register allocator can usually handle such
2189 reg-reg moves by tying. If we allow the combiner to make
2190 substitutions of likely-spilled regs, reload might die.
2191 As an exception, we allow combinations involving fixed regs; these are
2192 not available to the register allocator so there's no risk involved. */
2194 set
= single_set (insn
);
2197 src
= SET_SRC (set
);
2198 dest
= SET_DEST (set
);
2199 if (GET_CODE (src
) == SUBREG
)
2200 src
= SUBREG_REG (src
);
2201 if (GET_CODE (dest
) == SUBREG
)
2202 dest
= SUBREG_REG (dest
);
2203 if (REG_P (src
) && REG_P (dest
)
2204 && ((HARD_REGISTER_P (src
)
2205 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2206 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2207 || (HARD_REGISTER_P (dest
)
2208 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2209 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2215 struct likely_spilled_retval_info
2217 unsigned regno
, nregs
;
2221 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2222 hard registers that are known to be written to / clobbered in full. */
2224 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2226 struct likely_spilled_retval_info
*const info
=
2227 (struct likely_spilled_retval_info
*) data
;
2228 unsigned regno
, nregs
;
2231 if (!REG_P (XEXP (set
, 0)))
2234 if (regno
>= info
->regno
+ info
->nregs
)
2236 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2237 if (regno
+ nregs
<= info
->regno
)
2239 new_mask
= (2U << (nregs
- 1)) - 1;
2240 if (regno
< info
->regno
)
2241 new_mask
>>= info
->regno
- regno
;
2243 new_mask
<<= regno
- info
->regno
;
2244 info
->mask
&= ~new_mask
;
2247 /* Return nonzero iff part of the return value is live during INSN, and
2248 it is likely spilled. This can happen when more than one insn is needed
2249 to copy the return value, e.g. when we consider to combine into the
2250 second copy insn for a complex value. */
2253 likely_spilled_retval_p (rtx insn
)
2255 rtx use
= BB_END (this_basic_block
);
2257 unsigned regno
, nregs
;
2258 /* We assume here that no machine mode needs more than
2259 32 hard registers when the value overlaps with a register
2260 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2262 struct likely_spilled_retval_info info
;
2264 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2266 reg
= XEXP (PATTERN (use
), 0);
2267 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2269 regno
= REGNO (reg
);
2270 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2273 mask
= (2U << (nregs
- 1)) - 1;
2275 /* Disregard parts of the return value that are set later. */
2279 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2281 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2284 /* Check if any of the (probably) live return value registers is
2289 if ((mask
& 1 << nregs
)
2290 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2296 /* Adjust INSN after we made a change to its destination.
2298 Changing the destination can invalidate notes that say something about
2299 the results of the insn and a LOG_LINK pointing to the insn. */
2302 adjust_for_new_dest (rtx insn
)
2304 /* For notes, be conservative and simply remove them. */
2305 remove_reg_equal_equiv_notes (insn
);
2307 /* The new insn will have a destination that was previously the destination
2308 of an insn just above it. Call distribute_links to make a LOG_LINK from
2309 the next use of that destination. */
2310 distribute_links (alloc_insn_link (insn
, NULL
));
2312 df_insn_rescan (insn
);
2315 /* Return TRUE if combine can reuse reg X in mode MODE.
2316 ADDED_SETS is nonzero if the original set is still required. */
2318 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2326 /* Allow hard registers if the new mode is legal, and occupies no more
2327 registers than the old mode. */
2328 if (regno
< FIRST_PSEUDO_REGISTER
)
2329 return (HARD_REGNO_MODE_OK (regno
, mode
)
2330 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2331 >= hard_regno_nregs
[regno
][mode
]));
2333 /* Or a pseudo that is only used once. */
2334 return (REG_N_SETS (regno
) == 1 && !added_sets
2335 && !REG_USERVAR_P (x
));
2339 /* Check whether X, the destination of a set, refers to part of
2340 the register specified by REG. */
2343 reg_subword_p (rtx x
, rtx reg
)
2345 /* Check that reg is an integer mode register. */
2346 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2349 if (GET_CODE (x
) == STRICT_LOW_PART
2350 || GET_CODE (x
) == ZERO_EXTRACT
)
2353 return GET_CODE (x
) == SUBREG
2354 && SUBREG_REG (x
) == reg
2355 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2358 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2359 Note that the INSN should be deleted *after* removing dead edges, so
2360 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2361 but not for a (set (pc) (label_ref FOO)). */
2364 update_cfg_for_uncondjump (rtx insn
)
2366 basic_block bb
= BLOCK_FOR_INSN (insn
);
2367 gcc_assert (BB_END (bb
) == insn
);
2369 purge_dead_edges (bb
);
2372 if (EDGE_COUNT (bb
->succs
) == 1)
2376 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2378 /* Remove barriers from the footer if there are any. */
2379 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2380 if (BARRIER_P (insn
))
2382 if (PREV_INSN (insn
))
2383 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2385 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2386 if (NEXT_INSN (insn
))
2387 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2389 else if (LABEL_P (insn
))
2394 /* Try to combine the insns I0, I1 and I2 into I3.
2395 Here I0, I1 and I2 appear earlier than I3.
2396 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2399 If we are combining more than two insns and the resulting insn is not
2400 recognized, try splitting it into two insns. If that happens, I2 and I3
2401 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2402 Otherwise, I0, I1 and I2 are pseudo-deleted.
2404 Return 0 if the combination does not work. Then nothing is changed.
2405 If we did the combination, return the insn at which combine should
2408 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2409 new direct jump instruction.
2411 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2412 been I3 passed to an earlier try_combine within the same basic
2416 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2417 rtx last_combined_insn
)
2419 /* New patterns for I3 and I2, respectively. */
2420 rtx newpat
, newi2pat
= 0;
2421 rtvec newpat_vec_with_clobbers
= 0;
2422 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2423 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2425 int added_sets_0
, added_sets_1
, added_sets_2
;
2426 /* Total number of SETs to put into I3. */
2428 /* Nonzero if I2's or I1's body now appears in I3. */
2429 int i2_is_used
= 0, i1_is_used
= 0;
2430 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2431 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2432 /* Contains I3 if the destination of I3 is used in its source, which means
2433 that the old life of I3 is being killed. If that usage is placed into
2434 I2 and not in I3, a REG_DEAD note must be made. */
2435 rtx i3dest_killed
= 0;
2436 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2437 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2438 /* Copy of SET_SRC of I1 and I0, if needed. */
2439 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2440 /* Set if I2DEST was reused as a scratch register. */
2441 bool i2scratch
= false;
2442 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2443 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2444 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2445 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2446 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2447 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2448 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2449 /* Notes that must be added to REG_NOTES in I3 and I2. */
2450 rtx new_i3_notes
, new_i2_notes
;
2451 /* Notes that we substituted I3 into I2 instead of the normal case. */
2452 int i3_subst_into_i2
= 0;
2453 /* Notes that I1, I2 or I3 is a MULT operation. */
2456 int changed_i3_dest
= 0;
2460 struct insn_link
*link
;
2462 rtx new_other_notes
;
2465 /* Only try four-insn combinations when there's high likelihood of
2466 success. Look for simple insns, such as loads of constants or
2467 binary operations involving a constant. */
2474 if (!flag_expensive_optimizations
)
2477 for (i
= 0; i
< 4; i
++)
2479 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2480 rtx set
= single_set (insn
);
2484 src
= SET_SRC (set
);
2485 if (CONSTANT_P (src
))
2490 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2492 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2493 || GET_CODE (src
) == LSHIFTRT
)
2496 if (ngood
< 2 && nshift
< 2)
2500 /* Exit early if one of the insns involved can't be used for
2502 if (cant_combine_insn_p (i3
)
2503 || cant_combine_insn_p (i2
)
2504 || (i1
&& cant_combine_insn_p (i1
))
2505 || (i0
&& cant_combine_insn_p (i0
))
2506 || likely_spilled_retval_p (i3
))
2510 undobuf
.other_insn
= 0;
2512 /* Reset the hard register usage information. */
2513 CLEAR_HARD_REG_SET (newpat_used_regs
);
2515 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2518 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2519 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2521 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2522 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2524 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2525 INSN_UID (i2
), INSN_UID (i3
));
2528 /* If multiple insns feed into one of I2 or I3, they can be in any
2529 order. To simplify the code below, reorder them in sequence. */
2530 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2531 temp
= i2
, i2
= i0
, i0
= temp
;
2532 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2533 temp
= i1
, i1
= i0
, i0
= temp
;
2534 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2535 temp
= i1
, i1
= i2
, i2
= temp
;
2537 added_links_insn
= 0;
2539 /* First check for one important special case that the code below will
2540 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2541 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2542 we may be able to replace that destination with the destination of I3.
2543 This occurs in the common code where we compute both a quotient and
2544 remainder into a structure, in which case we want to do the computation
2545 directly into the structure to avoid register-register copies.
2547 Note that this case handles both multiple sets in I2 and also cases
2548 where I2 has a number of CLOBBERs inside the PARALLEL.
2550 We make very conservative checks below and only try to handle the
2551 most common cases of this. For example, we only handle the case
2552 where I2 and I3 are adjacent to avoid making difficult register
2555 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2556 && REG_P (SET_SRC (PATTERN (i3
)))
2557 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2558 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2559 && GET_CODE (PATTERN (i2
)) == PARALLEL
2560 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2561 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2562 below would need to check what is inside (and reg_overlap_mentioned_p
2563 doesn't support those codes anyway). Don't allow those destinations;
2564 the resulting insn isn't likely to be recognized anyway. */
2565 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2566 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2567 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2568 SET_DEST (PATTERN (i3
)))
2569 && next_active_insn (i2
) == i3
)
2571 rtx p2
= PATTERN (i2
);
2573 /* Make sure that the destination of I3,
2574 which we are going to substitute into one output of I2,
2575 is not used within another output of I2. We must avoid making this:
2576 (parallel [(set (mem (reg 69)) ...)
2577 (set (reg 69) ...)])
2578 which is not well-defined as to order of actions.
2579 (Besides, reload can't handle output reloads for this.)
2581 The problem can also happen if the dest of I3 is a memory ref,
2582 if another dest in I2 is an indirect memory ref. */
2583 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2584 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2585 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2586 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2587 SET_DEST (XVECEXP (p2
, 0, i
))))
2590 if (i
== XVECLEN (p2
, 0))
2591 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2592 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2593 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2598 subst_low_luid
= DF_INSN_LUID (i2
);
2600 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2601 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2602 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2603 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2605 /* Replace the dest in I2 with our dest and make the resulting
2606 insn the new pattern for I3. Then skip to where we validate
2607 the pattern. Everything was set up above. */
2608 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2610 i3_subst_into_i2
= 1;
2611 goto validate_replacement
;
2615 /* If I2 is setting a pseudo to a constant and I3 is setting some
2616 sub-part of it to another constant, merge them by making a new
2619 && (temp
= single_set (i2
)) != 0
2620 && (CONST_INT_P (SET_SRC (temp
))
2621 || CONST_DOUBLE_AS_INT_P (SET_SRC (temp
)))
2622 && GET_CODE (PATTERN (i3
)) == SET
2623 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2624 || CONST_DOUBLE_AS_INT_P (SET_SRC (PATTERN (i3
))))
2625 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2627 rtx dest
= SET_DEST (PATTERN (i3
));
2631 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2633 if (CONST_INT_P (XEXP (dest
, 1))
2634 && CONST_INT_P (XEXP (dest
, 2)))
2636 width
= INTVAL (XEXP (dest
, 1));
2637 offset
= INTVAL (XEXP (dest
, 2));
2638 dest
= XEXP (dest
, 0);
2639 if (BITS_BIG_ENDIAN
)
2640 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2645 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2646 dest
= XEXP (dest
, 0);
2647 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2653 /* If this is the low part, we're done. */
2654 if (subreg_lowpart_p (dest
))
2656 /* Handle the case where inner is twice the size of outer. */
2657 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2658 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2659 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2660 /* Otherwise give up for now. */
2666 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2667 <= HOST_BITS_PER_DOUBLE_INT
))
2670 rtx inner
= SET_SRC (PATTERN (i3
));
2671 rtx outer
= SET_SRC (temp
);
2673 o
= rtx_to_double_int (outer
);
2674 i
= rtx_to_double_int (inner
);
2676 m
= double_int::mask (width
);
2678 m
= m
.llshift (offset
, HOST_BITS_PER_DOUBLE_INT
);
2679 i
= i
.llshift (offset
, HOST_BITS_PER_DOUBLE_INT
);
2680 o
= o
.and_not (m
) | i
;
2684 subst_low_luid
= DF_INSN_LUID (i2
);
2685 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2686 i2dest
= SET_DEST (temp
);
2687 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2689 /* Replace the source in I2 with the new constant and make the
2690 resulting insn the new pattern for I3. Then skip to where we
2691 validate the pattern. Everything was set up above. */
2692 SUBST (SET_SRC (temp
),
2693 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2695 newpat
= PATTERN (i2
);
2697 /* The dest of I3 has been replaced with the dest of I2. */
2698 changed_i3_dest
= 1;
2699 goto validate_replacement
;
2704 /* If we have no I1 and I2 looks like:
2705 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2707 make up a dummy I1 that is
2710 (set (reg:CC X) (compare:CC Y (const_int 0)))
2712 (We can ignore any trailing CLOBBERs.)
2714 This undoes a previous combination and allows us to match a branch-and-
2717 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2718 && XVECLEN (PATTERN (i2
), 0) >= 2
2719 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2720 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2722 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2723 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2724 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2725 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2726 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2727 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2729 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2730 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2735 /* We make I1 with the same INSN_UID as I2. This gives it
2736 the same DF_INSN_LUID for value tracking. Our fake I1 will
2737 never appear in the insn stream so giving it the same INSN_UID
2738 as I2 will not cause a problem. */
2740 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2741 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2742 INSN_LOCATION (i2
), -1, NULL_RTX
);
2744 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2745 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2746 SET_DEST (PATTERN (i1
)));
2747 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2752 /* Verify that I2 and I1 are valid for combining. */
2753 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2754 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2756 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2763 /* Record whether I2DEST is used in I2SRC and similarly for the other
2764 cases. Knowing this will help in register status updating below. */
2765 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2766 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2767 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2768 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2769 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2770 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2771 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2772 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2773 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2775 /* For the earlier insns, determine which of the subsequent ones they
2777 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2778 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2779 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2780 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2781 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2783 /* Ensure that I3's pattern can be the destination of combines. */
2784 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2785 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2786 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2787 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2794 /* See if any of the insns is a MULT operation. Unless one is, we will
2795 reject a combination that is, since it must be slower. Be conservative
2797 if (GET_CODE (i2src
) == MULT
2798 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2799 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2800 || (GET_CODE (PATTERN (i3
)) == SET
2801 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2805 We used to do this EXCEPT in one case: I3 has a post-inc in an
2806 output operand. However, that exception can give rise to insns like
2808 which is a famous insn on the PDP-11 where the value of r3 used as the
2809 source was model-dependent. Avoid this sort of thing. */
2812 if (!(GET_CODE (PATTERN (i3
)) == SET
2813 && REG_P (SET_SRC (PATTERN (i3
)))
2814 && MEM_P (SET_DEST (PATTERN (i3
)))
2815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2817 /* It's not the exception. */
2822 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2823 if (REG_NOTE_KIND (link
) == REG_INC
2824 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2826 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2834 /* See if the SETs in I1 or I2 need to be kept around in the merged
2835 instruction: whenever the value set there is still needed past I3.
2836 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2838 For the SET in I1, we have two cases: If I1 and I2 independently
2839 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2840 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2841 in I1 needs to be kept around unless I1DEST dies or is set in either
2842 I2 or I3. The same consideration applies to I0. */
2844 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2847 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2848 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2853 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2854 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
2855 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
2859 /* We are about to copy insns for the case where they need to be kept
2860 around. Check that they can be copied in the merged instruction. */
2862 if (targetm
.cannot_copy_insn_p
2863 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2864 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2865 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2871 /* If the set in I2 needs to be kept around, we must make a copy of
2872 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2873 PATTERN (I2), we are only substituting for the original I1DEST, not into
2874 an already-substituted copy. This also prevents making self-referential
2875 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2880 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2881 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2883 i2pat
= copy_rtx (PATTERN (i2
));
2888 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2889 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2891 i1pat
= copy_rtx (PATTERN (i1
));
2896 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2897 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2899 i0pat
= copy_rtx (PATTERN (i0
));
2904 /* Substitute in the latest insn for the regs set by the earlier ones. */
2906 maxreg
= max_reg_num ();
2911 /* Many machines that don't use CC0 have insns that can both perform an
2912 arithmetic operation and set the condition code. These operations will
2913 be represented as a PARALLEL with the first element of the vector
2914 being a COMPARE of an arithmetic operation with the constant zero.
2915 The second element of the vector will set some pseudo to the result
2916 of the same arithmetic operation. If we simplify the COMPARE, we won't
2917 match such a pattern and so will generate an extra insn. Here we test
2918 for this case, where both the comparison and the operation result are
2919 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2920 I2SRC. Later we will make the PARALLEL that contains I2. */
2922 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2923 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2924 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2925 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2928 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
2929 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2930 enum machine_mode compare_mode
, orig_compare_mode
;
2931 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2933 newpat
= PATTERN (i3
);
2934 newpat_dest
= SET_DEST (newpat
);
2935 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2937 if (undobuf
.other_insn
== 0
2938 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2941 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2942 compare_code
= simplify_compare_const (compare_code
,
2944 #ifdef CANONICALIZE_COMPARISON
2945 CANONICALIZE_COMPARISON (compare_code
, op0
, op1
);
2949 /* Do the rest only if op1 is const0_rtx, which may be the
2950 result of simplification. */
2951 if (op1
== const0_rtx
)
2953 /* If a single use of the CC is found, prepare to modify it
2954 when SELECT_CC_MODE returns a new CC-class mode, or when
2955 the above simplify_compare_const() returned a new comparison
2956 operator. undobuf.other_insn is assigned the CC use insn
2957 when modifying it. */
2960 #ifdef SELECT_CC_MODE
2961 enum machine_mode new_mode
2962 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2963 if (new_mode
!= orig_compare_mode
2964 && can_change_dest_mode (SET_DEST (newpat
),
2965 added_sets_2
, new_mode
))
2967 unsigned int regno
= REGNO (newpat_dest
);
2968 compare_mode
= new_mode
;
2969 if (regno
< FIRST_PSEUDO_REGISTER
)
2970 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
2973 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2974 newpat_dest
= regno_reg_rtx
[regno
];
2978 /* Cases for modifying the CC-using comparison. */
2979 if (compare_code
!= orig_compare_code
2980 /* ??? Do we need to verify the zero rtx? */
2981 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
2983 /* Replace cc_use_loc with entire new RTX. */
2985 gen_rtx_fmt_ee (compare_code
, compare_mode
,
2986 newpat_dest
, const0_rtx
));
2987 undobuf
.other_insn
= cc_use_insn
;
2989 else if (compare_mode
!= orig_compare_mode
)
2991 /* Just replace the CC reg with a new mode. */
2992 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
2993 undobuf
.other_insn
= cc_use_insn
;
2997 /* Now we modify the current newpat:
2998 First, SET_DEST(newpat) is updated if the CC mode has been
2999 altered. For targets without SELECT_CC_MODE, this should be
3001 if (compare_mode
!= orig_compare_mode
)
3002 SUBST (SET_DEST (newpat
), newpat_dest
);
3003 /* This is always done to propagate i2src into newpat. */
3004 SUBST (SET_SRC (newpat
),
3005 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3006 /* Create new version of i2pat if needed; the below PARALLEL
3007 creation needs this to work correctly. */
3008 if (! rtx_equal_p (i2src
, op0
))
3009 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3015 if (i2_is_used
== 0)
3017 /* It is possible that the source of I2 or I1 may be performing
3018 an unneeded operation, such as a ZERO_EXTEND of something
3019 that is known to have the high part zero. Handle that case
3020 by letting subst look at the inner insns.
3022 Another way to do this would be to have a function that tries
3023 to simplify a single insn instead of merging two or more
3024 insns. We don't do this because of the potential of infinite
3025 loops and because of the potential extra memory required.
3026 However, doing it the way we are is a bit of a kludge and
3027 doesn't catch all cases.
3029 But only do this if -fexpensive-optimizations since it slows
3030 things down and doesn't usually win.
3032 This is not done in the COMPARE case above because the
3033 unmodified I2PAT is used in the PARALLEL and so a pattern
3034 with a modified I2SRC would not match. */
3036 if (flag_expensive_optimizations
)
3038 /* Pass pc_rtx so no substitutions are done, just
3042 subst_low_luid
= DF_INSN_LUID (i1
);
3043 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3046 subst_low_luid
= DF_INSN_LUID (i2
);
3047 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3050 n_occurrences
= 0; /* `subst' counts here */
3051 subst_low_luid
= DF_INSN_LUID (i2
);
3053 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3054 copy of I2SRC each time we substitute it, in order to avoid creating
3055 self-referential RTL when we will be substituting I1SRC for I1DEST
3056 later. Likewise if I0 feeds into I2, either directly or indirectly
3057 through I1, and I0DEST is in I0SRC. */
3058 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3059 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3060 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3061 && i0dest_in_i0src
));
3064 /* Record whether I2's body now appears within I3's body. */
3065 i2_is_used
= n_occurrences
;
3068 /* If we already got a failure, don't try to do more. Otherwise, try to
3069 substitute I1 if we have it. */
3071 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3073 /* Check that an autoincrement side-effect on I1 has not been lost.
3074 This happens if I1DEST is mentioned in I2 and dies there, and
3075 has disappeared from the new pattern. */
3076 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3078 && dead_or_set_p (i2
, i1dest
)
3079 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3080 /* Before we can do this substitution, we must redo the test done
3081 above (see detailed comments there) that ensures I1DEST isn't
3082 mentioned in any SETs in NEWPAT that are field assignments. */
3083 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3091 subst_low_luid
= DF_INSN_LUID (i1
);
3093 /* If the following substitution will modify I1SRC, make a copy of it
3094 for the case where it is substituted for I1DEST in I2PAT later. */
3095 if (added_sets_2
&& i1_feeds_i2_n
)
3096 i1src_copy
= copy_rtx (i1src
);
3098 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3099 copy of I1SRC each time we substitute it, in order to avoid creating
3100 self-referential RTL when we will be substituting I0SRC for I0DEST
3102 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3103 i0_feeds_i1_n
&& i0dest_in_i0src
);
3106 /* Record whether I1's body now appears within I3's body. */
3107 i1_is_used
= n_occurrences
;
3110 /* Likewise for I0 if we have it. */
3112 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3114 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3115 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3116 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3117 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3118 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3125 /* If the following substitution will modify I0SRC, make a copy of it
3126 for the case where it is substituted for I0DEST in I1PAT later. */
3127 if (added_sets_1
&& i0_feeds_i1_n
)
3128 i0src_copy
= copy_rtx (i0src
);
3129 /* And a copy for I0DEST in I2PAT substitution. */
3130 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3131 || (i0_feeds_i2_n
)))
3132 i0src_copy2
= copy_rtx (i0src
);
3135 subst_low_luid
= DF_INSN_LUID (i0
);
3136 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3140 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3141 to count all the ways that I2SRC and I1SRC can be used. */
3142 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3143 && i2_is_used
+ added_sets_2
> 1)
3144 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3145 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3147 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3148 && (n_occurrences
+ added_sets_0
3149 + (added_sets_1
&& i0_feeds_i1_n
)
3150 + (added_sets_2
&& i0_feeds_i2_n
)
3152 /* Fail if we tried to make a new register. */
3153 || max_reg_num () != maxreg
3154 /* Fail if we couldn't do something and have a CLOBBER. */
3155 || GET_CODE (newpat
) == CLOBBER
3156 /* Fail if this new pattern is a MULT and we didn't have one before
3157 at the outer level. */
3158 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3165 /* If the actions of the earlier insns must be kept
3166 in addition to substituting them into the latest one,
3167 we must make a new PARALLEL for the latest insn
3168 to hold additional the SETs. */
3170 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3172 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3175 if (GET_CODE (newpat
) == PARALLEL
)
3177 rtvec old
= XVEC (newpat
, 0);
3178 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3179 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3180 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3181 sizeof (old
->elem
[0]) * old
->num_elem
);
3186 total_sets
= 1 + extra_sets
;
3187 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3188 XVECEXP (newpat
, 0, 0) = old
;
3192 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3198 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3200 XVECEXP (newpat
, 0, --total_sets
) = t
;
3206 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3207 i0_feeds_i1_n
&& i0dest_in_i0src
);
3208 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3209 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3211 XVECEXP (newpat
, 0, --total_sets
) = t
;
3215 validate_replacement
:
3217 /* Note which hard regs this insn has as inputs. */
3218 mark_used_regs_combine (newpat
);
3220 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3221 consider splitting this pattern, we might need these clobbers. */
3222 if (i1
&& GET_CODE (newpat
) == PARALLEL
3223 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3225 int len
= XVECLEN (newpat
, 0);
3227 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3228 for (i
= 0; i
< len
; i
++)
3229 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3232 /* Is the result of combination a valid instruction? */
3233 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3235 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3236 the second SET's destination is a register that is unused and isn't
3237 marked as an instruction that might trap in an EH region. In that case,
3238 we just need the first SET. This can occur when simplifying a divmod
3239 insn. We *must* test for this case here because the code below that
3240 splits two independent SETs doesn't handle this case correctly when it
3241 updates the register status.
3243 It's pointless doing this if we originally had two sets, one from
3244 i3, and one from i2. Combining then splitting the parallel results
3245 in the original i2 again plus an invalid insn (which we delete).
3246 The net effect is only to move instructions around, which makes
3247 debug info less accurate.
3249 Also check the case where the first SET's destination is unused.
3250 That would not cause incorrect code, but does cause an unneeded
3253 if (insn_code_number
< 0
3254 && !(added_sets_2
&& i1
== 0)
3255 && GET_CODE (newpat
) == PARALLEL
3256 && XVECLEN (newpat
, 0) == 2
3257 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3258 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3259 && asm_noperands (newpat
) < 0)
3261 rtx set0
= XVECEXP (newpat
, 0, 0);
3262 rtx set1
= XVECEXP (newpat
, 0, 1);
3264 if (((REG_P (SET_DEST (set1
))
3265 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3266 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3267 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3268 && insn_nothrow_p (i3
)
3269 && !side_effects_p (SET_SRC (set1
)))
3272 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3275 else if (((REG_P (SET_DEST (set0
))
3276 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3277 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3278 && find_reg_note (i3
, REG_UNUSED
,
3279 SUBREG_REG (SET_DEST (set0
)))))
3280 && insn_nothrow_p (i3
)
3281 && !side_effects_p (SET_SRC (set0
)))
3284 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3286 if (insn_code_number
>= 0)
3287 changed_i3_dest
= 1;
3291 /* If we were combining three insns and the result is a simple SET
3292 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3293 insns. There are two ways to do this. It can be split using a
3294 machine-specific method (like when you have an addition of a large
3295 constant) or by combine in the function find_split_point. */
3297 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3298 && asm_noperands (newpat
) < 0)
3300 rtx parallel
, m_split
, *split
;
3302 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3303 use I2DEST as a scratch register will help. In the latter case,
3304 convert I2DEST to the mode of the source of NEWPAT if we can. */
3306 m_split
= combine_split_insns (newpat
, i3
);
3308 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3309 inputs of NEWPAT. */
3311 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3312 possible to try that as a scratch reg. This would require adding
3313 more code to make it work though. */
3315 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3317 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3319 /* First try to split using the original register as a
3320 scratch register. */
3321 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3322 gen_rtvec (2, newpat
,
3323 gen_rtx_CLOBBER (VOIDmode
,
3325 m_split
= combine_split_insns (parallel
, i3
);
3327 /* If that didn't work, try changing the mode of I2DEST if
3330 && new_mode
!= GET_MODE (i2dest
)
3331 && new_mode
!= VOIDmode
3332 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3334 enum machine_mode old_mode
= GET_MODE (i2dest
);
3337 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3338 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3341 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3342 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3345 parallel
= (gen_rtx_PARALLEL
3347 gen_rtvec (2, newpat
,
3348 gen_rtx_CLOBBER (VOIDmode
,
3350 m_split
= combine_split_insns (parallel
, i3
);
3353 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3357 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3358 buf
= undobuf
.undos
;
3359 undobuf
.undos
= buf
->next
;
3360 buf
->next
= undobuf
.frees
;
3361 undobuf
.frees
= buf
;
3365 i2scratch
= m_split
!= 0;
3368 /* If recog_for_combine has discarded clobbers, try to use them
3369 again for the split. */
3370 if (m_split
== 0 && newpat_vec_with_clobbers
)
3372 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3373 m_split
= combine_split_insns (parallel
, i3
);
3376 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3378 m_split
= PATTERN (m_split
);
3379 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3380 if (insn_code_number
>= 0)
3383 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3384 && (next_nonnote_nondebug_insn (i2
) == i3
3385 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3388 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3389 newi2pat
= PATTERN (m_split
);
3391 i3set
= single_set (NEXT_INSN (m_split
));
3392 i2set
= single_set (m_split
);
3394 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3396 /* If I2 or I3 has multiple SETs, we won't know how to track
3397 register status, so don't use these insns. If I2's destination
3398 is used between I2 and I3, we also can't use these insns. */
3400 if (i2_code_number
>= 0 && i2set
&& i3set
3401 && (next_nonnote_nondebug_insn (i2
) == i3
3402 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3403 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3405 if (insn_code_number
>= 0)
3408 /* It is possible that both insns now set the destination of I3.
3409 If so, we must show an extra use of it. */
3411 if (insn_code_number
>= 0)
3413 rtx new_i3_dest
= SET_DEST (i3set
);
3414 rtx new_i2_dest
= SET_DEST (i2set
);
3416 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3417 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3418 || GET_CODE (new_i3_dest
) == SUBREG
)
3419 new_i3_dest
= XEXP (new_i3_dest
, 0);
3421 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3422 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3423 || GET_CODE (new_i2_dest
) == SUBREG
)
3424 new_i2_dest
= XEXP (new_i2_dest
, 0);
3426 if (REG_P (new_i3_dest
)
3427 && REG_P (new_i2_dest
)
3428 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3429 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3433 /* If we can split it and use I2DEST, go ahead and see if that
3434 helps things be recognized. Verify that none of the registers
3435 are set between I2 and I3. */
3436 if (insn_code_number
< 0
3437 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3441 /* We need I2DEST in the proper mode. If it is a hard register
3442 or the only use of a pseudo, we can change its mode.
3443 Make sure we don't change a hard register to have a mode that
3444 isn't valid for it, or change the number of registers. */
3445 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3446 || GET_MODE (*split
) == VOIDmode
3447 || can_change_dest_mode (i2dest
, added_sets_2
,
3449 && (next_nonnote_nondebug_insn (i2
) == i3
3450 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3451 /* We can't overwrite I2DEST if its value is still used by
3453 && ! reg_referenced_p (i2dest
, newpat
))
3455 rtx newdest
= i2dest
;
3456 enum rtx_code split_code
= GET_CODE (*split
);
3457 enum machine_mode split_mode
= GET_MODE (*split
);
3458 bool subst_done
= false;
3459 newi2pat
= NULL_RTX
;
3463 /* *SPLIT may be part of I2SRC, so make sure we have the
3464 original expression around for later debug processing.
3465 We should not need I2SRC any more in other cases. */
3466 if (MAY_HAVE_DEBUG_INSNS
)
3467 i2src
= copy_rtx (i2src
);
3471 /* Get NEWDEST as a register in the proper mode. We have already
3472 validated that we can do this. */
3473 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3475 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3476 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3479 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3480 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3484 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3485 an ASHIFT. This can occur if it was inside a PLUS and hence
3486 appeared to be a memory address. This is a kludge. */
3487 if (split_code
== MULT
3488 && CONST_INT_P (XEXP (*split
, 1))
3489 && INTVAL (XEXP (*split
, 1)) > 0
3490 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3492 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3493 XEXP (*split
, 0), GEN_INT (i
)));
3494 /* Update split_code because we may not have a multiply
3496 split_code
= GET_CODE (*split
);
3499 #ifdef INSN_SCHEDULING
3500 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3501 be written as a ZERO_EXTEND. */
3502 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3504 #ifdef LOAD_EXTEND_OP
3505 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3506 what it really is. */
3507 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3509 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3510 SUBREG_REG (*split
)));
3513 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3514 SUBREG_REG (*split
)));
3518 /* Attempt to split binary operators using arithmetic identities. */
3519 if (BINARY_P (SET_SRC (newpat
))
3520 && split_mode
== GET_MODE (SET_SRC (newpat
))
3521 && ! side_effects_p (SET_SRC (newpat
)))
3523 rtx setsrc
= SET_SRC (newpat
);
3524 enum machine_mode mode
= GET_MODE (setsrc
);
3525 enum rtx_code code
= GET_CODE (setsrc
);
3526 rtx src_op0
= XEXP (setsrc
, 0);
3527 rtx src_op1
= XEXP (setsrc
, 1);
3529 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3530 if (rtx_equal_p (src_op0
, src_op1
))
3532 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3533 SUBST (XEXP (setsrc
, 0), newdest
);
3534 SUBST (XEXP (setsrc
, 1), newdest
);
3537 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3538 else if ((code
== PLUS
|| code
== MULT
)
3539 && GET_CODE (src_op0
) == code
3540 && GET_CODE (XEXP (src_op0
, 0)) == code
3541 && (INTEGRAL_MODE_P (mode
)
3542 || (FLOAT_MODE_P (mode
)
3543 && flag_unsafe_math_optimizations
)))
3545 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3546 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3547 rtx r
= XEXP (src_op0
, 1);
3550 /* Split both "((X op Y) op X) op Y" and
3551 "((X op Y) op Y) op X" as "T op T" where T is
3553 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3554 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3556 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3558 SUBST (XEXP (setsrc
, 0), newdest
);
3559 SUBST (XEXP (setsrc
, 1), newdest
);
3562 /* Split "((X op X) op Y) op Y)" as "T op T" where
3564 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3566 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3567 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3568 SUBST (XEXP (setsrc
, 0), newdest
);
3569 SUBST (XEXP (setsrc
, 1), newdest
);
3577 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3578 SUBST (*split
, newdest
);
3581 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3583 /* recog_for_combine might have added CLOBBERs to newi2pat.
3584 Make sure NEWPAT does not depend on the clobbered regs. */
3585 if (GET_CODE (newi2pat
) == PARALLEL
)
3586 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3587 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3589 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3590 if (reg_overlap_mentioned_p (reg
, newpat
))
3597 /* If the split point was a MULT and we didn't have one before,
3598 don't use one now. */
3599 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3600 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3604 /* Check for a case where we loaded from memory in a narrow mode and
3605 then sign extended it, but we need both registers. In that case,
3606 we have a PARALLEL with both loads from the same memory location.
3607 We can split this into a load from memory followed by a register-register
3608 copy. This saves at least one insn, more if register allocation can
3611 We cannot do this if the destination of the first assignment is a
3612 condition code register or cc0. We eliminate this case by making sure
3613 the SET_DEST and SET_SRC have the same mode.
3615 We cannot do this if the destination of the second assignment is
3616 a register that we have already assumed is zero-extended. Similarly
3617 for a SUBREG of such a register. */
3619 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3620 && GET_CODE (newpat
) == PARALLEL
3621 && XVECLEN (newpat
, 0) == 2
3622 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3623 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3624 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3625 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3626 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3627 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3628 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3629 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3631 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3632 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3633 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3635 && VEC_index (reg_stat_type
, reg_stat
,
3636 REGNO (temp
)).nonzero_bits
!= 0
3637 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3638 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3639 && (VEC_index (reg_stat_type
, reg_stat
,
3640 REGNO (temp
)).nonzero_bits
3641 != GET_MODE_MASK (word_mode
))))
3642 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3643 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3645 && VEC_index (reg_stat_type
, reg_stat
,
3646 REGNO (temp
)).nonzero_bits
!= 0
3647 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3648 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3649 && (VEC_index (reg_stat_type
, reg_stat
,
3650 REGNO (temp
)).nonzero_bits
3651 != GET_MODE_MASK (word_mode
)))))
3652 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3653 SET_SRC (XVECEXP (newpat
, 0, 1)))
3654 && ! find_reg_note (i3
, REG_UNUSED
,
3655 SET_DEST (XVECEXP (newpat
, 0, 0))))
3659 newi2pat
= XVECEXP (newpat
, 0, 0);
3660 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3661 newpat
= XVECEXP (newpat
, 0, 1);
3662 SUBST (SET_SRC (newpat
),
3663 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3664 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3666 if (i2_code_number
>= 0)
3667 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3669 if (insn_code_number
>= 0)
3673 /* Similarly, check for a case where we have a PARALLEL of two independent
3674 SETs but we started with three insns. In this case, we can do the sets
3675 as two separate insns. This case occurs when some SET allows two
3676 other insns to combine, but the destination of that SET is still live. */
3678 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3679 && GET_CODE (newpat
) == PARALLEL
3680 && XVECLEN (newpat
, 0) == 2
3681 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3682 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3683 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3684 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3685 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3686 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3687 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3688 XVECEXP (newpat
, 0, 0))
3689 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3690 XVECEXP (newpat
, 0, 1))
3691 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3692 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3694 /* Normally, it doesn't matter which of the two is done first,
3695 but the one that references cc0 can't be the second, and
3696 one which uses any regs/memory set in between i2 and i3 can't
3698 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3701 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3705 newi2pat
= XVECEXP (newpat
, 0, 1);
3706 newpat
= XVECEXP (newpat
, 0, 0);
3708 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3711 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3715 newi2pat
= XVECEXP (newpat
, 0, 0);
3716 newpat
= XVECEXP (newpat
, 0, 1);
3724 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3726 if (i2_code_number
>= 0)
3728 /* recog_for_combine might have added CLOBBERs to newi2pat.
3729 Make sure NEWPAT does not depend on the clobbered regs. */
3730 if (GET_CODE (newi2pat
) == PARALLEL
)
3732 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3733 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3735 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3736 if (reg_overlap_mentioned_p (reg
, newpat
))
3744 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3748 /* If it still isn't recognized, fail and change things back the way they
3750 if ((insn_code_number
< 0
3751 /* Is the result a reasonable ASM_OPERANDS? */
3752 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3758 /* If we had to change another insn, make sure it is valid also. */
3759 if (undobuf
.other_insn
)
3761 CLEAR_HARD_REG_SET (newpat_used_regs
);
3763 other_pat
= PATTERN (undobuf
.other_insn
);
3764 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3767 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3775 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3776 they are adjacent to each other or not. */
3778 rtx p
= prev_nonnote_insn (i3
);
3779 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3780 && sets_cc0_p (newi2pat
))
3788 /* Only allow this combination if insn_rtx_costs reports that the
3789 replacement instructions are cheaper than the originals. */
3790 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3796 if (MAY_HAVE_DEBUG_INSNS
)
3800 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3801 if (undo
->kind
== UNDO_MODE
)
3803 rtx reg
= *undo
->where
.r
;
3804 enum machine_mode new_mode
= GET_MODE (reg
);
3805 enum machine_mode old_mode
= undo
->old_contents
.m
;
3807 /* Temporarily revert mode back. */
3808 adjust_reg_mode (reg
, old_mode
);
3810 if (reg
== i2dest
&& i2scratch
)
3812 /* If we used i2dest as a scratch register with a
3813 different mode, substitute it for the original
3814 i2src while its original mode is temporarily
3815 restored, and then clear i2scratch so that we don't
3816 do it again later. */
3817 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3820 /* Put back the new mode. */
3821 adjust_reg_mode (reg
, new_mode
);
3825 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3831 last
= last_combined_insn
;
3836 last
= undobuf
.other_insn
;
3838 if (DF_INSN_LUID (last
)
3839 < DF_INSN_LUID (last_combined_insn
))
3840 last
= last_combined_insn
;
3843 /* We're dealing with a reg that changed mode but not
3844 meaning, so we want to turn it into a subreg for
3845 the new mode. However, because of REG sharing and
3846 because its mode had already changed, we have to do
3847 it in two steps. First, replace any debug uses of
3848 reg, with its original mode temporarily restored,
3849 with this copy we have created; then, replace the
3850 copy with the SUBREG of the original shared reg,
3851 once again changed to the new mode. */
3852 propagate_for_debug (first
, last
, reg
, tempreg
,
3854 adjust_reg_mode (reg
, new_mode
);
3855 propagate_for_debug (first
, last
, tempreg
,
3856 lowpart_subreg (old_mode
, reg
, new_mode
),
3862 /* If we will be able to accept this, we have made a
3863 change to the destination of I3. This requires us to
3864 do a few adjustments. */
3866 if (changed_i3_dest
)
3868 PATTERN (i3
) = newpat
;
3869 adjust_for_new_dest (i3
);
3872 /* We now know that we can do this combination. Merge the insns and
3873 update the status of registers and LOG_LINKS. */
3875 if (undobuf
.other_insn
)
3879 PATTERN (undobuf
.other_insn
) = other_pat
;
3881 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3882 are still valid. Then add any non-duplicate notes added by
3883 recog_for_combine. */
3884 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3886 next
= XEXP (note
, 1);
3888 if (REG_NOTE_KIND (note
) == REG_UNUSED
3889 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3890 remove_note (undobuf
.other_insn
, note
);
3893 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3894 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3901 struct insn_link
*link
;
3904 /* I3 now uses what used to be its destination and which is now
3905 I2's destination. This requires us to do a few adjustments. */
3906 PATTERN (i3
) = newpat
;
3907 adjust_for_new_dest (i3
);
3909 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3912 However, some later insn might be using I2's dest and have
3913 a LOG_LINK pointing at I3. We must remove this link.
3914 The simplest way to remove the link is to point it at I1,
3915 which we know will be a NOTE. */
3917 /* newi2pat is usually a SET here; however, recog_for_combine might
3918 have added some clobbers. */
3919 if (GET_CODE (newi2pat
) == PARALLEL
)
3920 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3922 ni2dest
= SET_DEST (newi2pat
);
3924 for (insn
= NEXT_INSN (i3
);
3925 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3926 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3927 insn
= NEXT_INSN (insn
))
3929 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3931 FOR_EACH_LOG_LINK (link
, insn
)
3932 if (link
->insn
== i3
)
3941 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3942 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
3945 /* Compute which registers we expect to eliminate. newi2pat may be setting
3946 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3947 same as i3dest, in which case newi2pat may be setting i1dest. */
3948 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3949 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3952 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3953 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3956 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3957 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3961 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3963 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3964 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3966 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3968 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3970 /* Ensure that we do not have something that should not be shared but
3971 occurs multiple times in the new insns. Check this by first
3972 resetting all the `used' flags and then copying anything is shared. */
3974 reset_used_flags (i3notes
);
3975 reset_used_flags (i2notes
);
3976 reset_used_flags (i1notes
);
3977 reset_used_flags (i0notes
);
3978 reset_used_flags (newpat
);
3979 reset_used_flags (newi2pat
);
3980 if (undobuf
.other_insn
)
3981 reset_used_flags (PATTERN (undobuf
.other_insn
));
3983 i3notes
= copy_rtx_if_shared (i3notes
);
3984 i2notes
= copy_rtx_if_shared (i2notes
);
3985 i1notes
= copy_rtx_if_shared (i1notes
);
3986 i0notes
= copy_rtx_if_shared (i0notes
);
3987 newpat
= copy_rtx_if_shared (newpat
);
3988 newi2pat
= copy_rtx_if_shared (newi2pat
);
3989 if (undobuf
.other_insn
)
3990 reset_used_flags (PATTERN (undobuf
.other_insn
));
3992 INSN_CODE (i3
) = insn_code_number
;
3993 PATTERN (i3
) = newpat
;
3995 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3997 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
3999 reset_used_flags (call_usage
);
4000 call_usage
= copy_rtx (call_usage
);
4004 /* I2SRC must still be meaningful at this point. Some splitting
4005 operations can invalidate I2SRC, but those operations do not
4008 replace_rtx (call_usage
, i2dest
, i2src
);
4012 replace_rtx (call_usage
, i1dest
, i1src
);
4014 replace_rtx (call_usage
, i0dest
, i0src
);
4016 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4019 if (undobuf
.other_insn
)
4020 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4022 /* We had one special case above where I2 had more than one set and
4023 we replaced a destination of one of those sets with the destination
4024 of I3. In that case, we have to update LOG_LINKS of insns later
4025 in this basic block. Note that this (expensive) case is rare.
4027 Also, in this case, we must pretend that all REG_NOTEs for I2
4028 actually came from I3, so that REG_UNUSED notes from I2 will be
4029 properly handled. */
4031 if (i3_subst_into_i2
)
4033 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4034 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4035 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4036 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4037 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4038 && ! find_reg_note (i2
, REG_UNUSED
,
4039 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4040 for (temp
= NEXT_INSN (i2
);
4041 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4042 || BB_HEAD (this_basic_block
) != temp
);
4043 temp
= NEXT_INSN (temp
))
4044 if (temp
!= i3
&& INSN_P (temp
))
4045 FOR_EACH_LOG_LINK (link
, temp
)
4046 if (link
->insn
== i2
)
4052 while (XEXP (link
, 1))
4053 link
= XEXP (link
, 1);
4054 XEXP (link
, 1) = i2notes
;
4061 LOG_LINKS (i3
) = NULL
;
4063 LOG_LINKS (i2
) = NULL
;
4068 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4069 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4071 INSN_CODE (i2
) = i2_code_number
;
4072 PATTERN (i2
) = newi2pat
;
4076 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4077 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4079 SET_INSN_DELETED (i2
);
4084 LOG_LINKS (i1
) = NULL
;
4086 if (MAY_HAVE_DEBUG_INSNS
)
4087 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4089 SET_INSN_DELETED (i1
);
4094 LOG_LINKS (i0
) = NULL
;
4096 if (MAY_HAVE_DEBUG_INSNS
)
4097 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4099 SET_INSN_DELETED (i0
);
4102 /* Get death notes for everything that is now used in either I3 or
4103 I2 and used to die in a previous insn. If we built two new
4104 patterns, move from I1 to I2 then I2 to I3 so that we get the
4105 proper movement on registers that I2 modifies. */
4108 from_luid
= DF_INSN_LUID (i0
);
4110 from_luid
= DF_INSN_LUID (i1
);
4112 from_luid
= DF_INSN_LUID (i2
);
4114 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4115 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4117 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4119 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4120 elim_i2
, elim_i1
, elim_i0
);
4122 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4123 elim_i2
, elim_i1
, elim_i0
);
4125 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4126 elim_i2
, elim_i1
, elim_i0
);
4128 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4129 elim_i2
, elim_i1
, elim_i0
);
4131 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4132 elim_i2
, elim_i1
, elim_i0
);
4134 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4135 know these are REG_UNUSED and want them to go to the desired insn,
4136 so we always pass it as i3. */
4138 if (newi2pat
&& new_i2_notes
)
4139 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4143 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4146 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4147 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4148 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4149 in that case, it might delete I2. Similarly for I2 and I1.
4150 Show an additional death due to the REG_DEAD note we make here. If
4151 we discard it in distribute_notes, we will decrement it again. */
4155 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4156 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4158 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4160 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4162 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4163 elim_i2
, elim_i1
, elim_i0
);
4166 if (i2dest_in_i2src
)
4168 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4169 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4170 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4171 NULL_RTX
, NULL_RTX
);
4173 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4174 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4177 if (i1dest_in_i1src
)
4179 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4180 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4181 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4182 NULL_RTX
, NULL_RTX
);
4184 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4185 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4188 if (i0dest_in_i0src
)
4190 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4191 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4192 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4193 NULL_RTX
, NULL_RTX
);
4195 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4196 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4199 distribute_links (i3links
);
4200 distribute_links (i2links
);
4201 distribute_links (i1links
);
4202 distribute_links (i0links
);
4206 struct insn_link
*link
;
4207 rtx i2_insn
= 0, i2_val
= 0, set
;
4209 /* The insn that used to set this register doesn't exist, and
4210 this life of the register may not exist either. See if one of
4211 I3's links points to an insn that sets I2DEST. If it does,
4212 that is now the last known value for I2DEST. If we don't update
4213 this and I2 set the register to a value that depended on its old
4214 contents, we will get confused. If this insn is used, thing
4215 will be set correctly in combine_instructions. */
4216 FOR_EACH_LOG_LINK (link
, i3
)
4217 if ((set
= single_set (link
->insn
)) != 0
4218 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4219 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4221 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4223 /* If the reg formerly set in I2 died only once and that was in I3,
4224 zero its use count so it won't make `reload' do any work. */
4226 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4227 && ! i2dest_in_i2src
)
4228 INC_REG_N_SETS (REGNO (i2dest
), -1);
4231 if (i1
&& REG_P (i1dest
))
4233 struct insn_link
*link
;
4234 rtx i1_insn
= 0, i1_val
= 0, set
;
4236 FOR_EACH_LOG_LINK (link
, i3
)
4237 if ((set
= single_set (link
->insn
)) != 0
4238 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4239 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4241 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4243 if (! added_sets_1
&& ! i1dest_in_i1src
)
4244 INC_REG_N_SETS (REGNO (i1dest
), -1);
4247 if (i0
&& REG_P (i0dest
))
4249 struct insn_link
*link
;
4250 rtx i0_insn
= 0, i0_val
= 0, set
;
4252 FOR_EACH_LOG_LINK (link
, i3
)
4253 if ((set
= single_set (link
->insn
)) != 0
4254 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4255 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4257 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4259 if (! added_sets_0
&& ! i0dest_in_i0src
)
4260 INC_REG_N_SETS (REGNO (i0dest
), -1);
4263 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4264 been made to this insn. The order of
4265 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4266 can affect nonzero_bits of newpat */
4268 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4269 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4272 if (undobuf
.other_insn
!= NULL_RTX
)
4276 fprintf (dump_file
, "modifying other_insn ");
4277 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4279 df_insn_rescan (undobuf
.other_insn
);
4282 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4286 fprintf (dump_file
, "modifying insn i1 ");
4287 dump_insn_slim (dump_file
, i0
);
4289 df_insn_rescan (i0
);
4292 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4296 fprintf (dump_file
, "modifying insn i1 ");
4297 dump_insn_slim (dump_file
, i1
);
4299 df_insn_rescan (i1
);
4302 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4306 fprintf (dump_file
, "modifying insn i2 ");
4307 dump_insn_slim (dump_file
, i2
);
4309 df_insn_rescan (i2
);
4312 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4316 fprintf (dump_file
, "modifying insn i3 ");
4317 dump_insn_slim (dump_file
, i3
);
4319 df_insn_rescan (i3
);
4322 /* Set new_direct_jump_p if a new return or simple jump instruction
4323 has been created. Adjust the CFG accordingly. */
4325 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4327 *new_direct_jump_p
= 1;
4328 mark_jump_label (PATTERN (i3
), i3
, 0);
4329 update_cfg_for_uncondjump (i3
);
4332 if (undobuf
.other_insn
!= NULL_RTX
4333 && (returnjump_p (undobuf
.other_insn
)
4334 || any_uncondjump_p (undobuf
.other_insn
)))
4336 *new_direct_jump_p
= 1;
4337 update_cfg_for_uncondjump (undobuf
.other_insn
);
4340 /* A noop might also need cleaning up of CFG, if it comes from the
4341 simplification of a jump. */
4343 && GET_CODE (newpat
) == SET
4344 && SET_SRC (newpat
) == pc_rtx
4345 && SET_DEST (newpat
) == pc_rtx
)
4347 *new_direct_jump_p
= 1;
4348 update_cfg_for_uncondjump (i3
);
4351 if (undobuf
.other_insn
!= NULL_RTX
4352 && JUMP_P (undobuf
.other_insn
)
4353 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4354 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4355 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4357 *new_direct_jump_p
= 1;
4358 update_cfg_for_uncondjump (undobuf
.other_insn
);
4361 combine_successes
++;
4364 if (added_links_insn
4365 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4366 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4367 return added_links_insn
;
4369 return newi2pat
? i2
: i3
;
4372 /* Undo all the modifications recorded in undobuf. */
4377 struct undo
*undo
, *next
;
4379 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4385 *undo
->where
.r
= undo
->old_contents
.r
;
4388 *undo
->where
.i
= undo
->old_contents
.i
;
4391 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4394 *undo
->where
.l
= undo
->old_contents
.l
;
4400 undo
->next
= undobuf
.frees
;
4401 undobuf
.frees
= undo
;
4407 /* We've committed to accepting the changes we made. Move all
4408 of the undos to the free list. */
4413 struct undo
*undo
, *next
;
4415 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4418 undo
->next
= undobuf
.frees
;
4419 undobuf
.frees
= undo
;
4424 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4425 where we have an arithmetic expression and return that point. LOC will
4428 try_combine will call this function to see if an insn can be split into
4432 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4435 enum rtx_code code
= GET_CODE (x
);
4437 unsigned HOST_WIDE_INT len
= 0;
4438 HOST_WIDE_INT pos
= 0;
4440 rtx inner
= NULL_RTX
;
4442 /* First special-case some codes. */
4446 #ifdef INSN_SCHEDULING
4447 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4449 if (MEM_P (SUBREG_REG (x
)))
4452 return find_split_point (&SUBREG_REG (x
), insn
, false);
4456 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4457 using LO_SUM and HIGH. */
4458 if (GET_CODE (XEXP (x
, 0)) == CONST
4459 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4461 enum machine_mode address_mode
= get_address_mode (x
);
4464 gen_rtx_LO_SUM (address_mode
,
4465 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4467 return &XEXP (XEXP (x
, 0), 0);
4471 /* If we have a PLUS whose second operand is a constant and the
4472 address is not valid, perhaps will can split it up using
4473 the machine-specific way to split large constants. We use
4474 the first pseudo-reg (one of the virtual regs) as a placeholder;
4475 it will not remain in the result. */
4476 if (GET_CODE (XEXP (x
, 0)) == PLUS
4477 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4478 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4479 MEM_ADDR_SPACE (x
)))
4481 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4482 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4486 /* This should have produced two insns, each of which sets our
4487 placeholder. If the source of the second is a valid address,
4488 we can make put both sources together and make a split point
4492 && NEXT_INSN (seq
) != NULL_RTX
4493 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4494 && NONJUMP_INSN_P (seq
)
4495 && GET_CODE (PATTERN (seq
)) == SET
4496 && SET_DEST (PATTERN (seq
)) == reg
4497 && ! reg_mentioned_p (reg
,
4498 SET_SRC (PATTERN (seq
)))
4499 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4500 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4501 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4502 && memory_address_addr_space_p
4503 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4504 MEM_ADDR_SPACE (x
)))
4506 rtx src1
= SET_SRC (PATTERN (seq
));
4507 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4509 /* Replace the placeholder in SRC2 with SRC1. If we can
4510 find where in SRC2 it was placed, that can become our
4511 split point and we can replace this address with SRC2.
4512 Just try two obvious places. */
4514 src2
= replace_rtx (src2
, reg
, src1
);
4516 if (XEXP (src2
, 0) == src1
)
4517 split
= &XEXP (src2
, 0);
4518 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4519 && XEXP (XEXP (src2
, 0), 0) == src1
)
4520 split
= &XEXP (XEXP (src2
, 0), 0);
4524 SUBST (XEXP (x
, 0), src2
);
4529 /* If that didn't work, perhaps the first operand is complex and
4530 needs to be computed separately, so make a split point there.
4531 This will occur on machines that just support REG + CONST
4532 and have a constant moved through some previous computation. */
4534 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4535 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4536 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4537 return &XEXP (XEXP (x
, 0), 0);
4540 /* If we have a PLUS whose first operand is complex, try computing it
4541 separately by making a split there. */
4542 if (GET_CODE (XEXP (x
, 0)) == PLUS
4543 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4545 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4546 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4547 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4548 return &XEXP (XEXP (x
, 0), 0);
4553 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4554 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4555 we need to put the operand into a register. So split at that
4558 if (SET_DEST (x
) == cc0_rtx
4559 && GET_CODE (SET_SRC (x
)) != COMPARE
4560 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4561 && !OBJECT_P (SET_SRC (x
))
4562 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4563 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4564 return &SET_SRC (x
);
4567 /* See if we can split SET_SRC as it stands. */
4568 split
= find_split_point (&SET_SRC (x
), insn
, true);
4569 if (split
&& split
!= &SET_SRC (x
))
4572 /* See if we can split SET_DEST as it stands. */
4573 split
= find_split_point (&SET_DEST (x
), insn
, false);
4574 if (split
&& split
!= &SET_DEST (x
))
4577 /* See if this is a bitfield assignment with everything constant. If
4578 so, this is an IOR of an AND, so split it into that. */
4579 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4580 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4581 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4582 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4583 && CONST_INT_P (SET_SRC (x
))
4584 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4585 + INTVAL (XEXP (SET_DEST (x
), 2)))
4586 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4587 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4589 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4590 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4591 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4592 rtx dest
= XEXP (SET_DEST (x
), 0);
4593 enum machine_mode mode
= GET_MODE (dest
);
4594 unsigned HOST_WIDE_INT mask
4595 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4598 if (BITS_BIG_ENDIAN
)
4599 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4601 or_mask
= gen_int_mode (src
<< pos
, mode
);
4604 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4607 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4609 simplify_gen_binary (IOR
, mode
,
4610 simplify_gen_binary (AND
, mode
,
4615 SUBST (SET_DEST (x
), dest
);
4617 split
= find_split_point (&SET_SRC (x
), insn
, true);
4618 if (split
&& split
!= &SET_SRC (x
))
4622 /* Otherwise, see if this is an operation that we can split into two.
4623 If so, try to split that. */
4624 code
= GET_CODE (SET_SRC (x
));
4629 /* If we are AND'ing with a large constant that is only a single
4630 bit and the result is only being used in a context where we
4631 need to know if it is zero or nonzero, replace it with a bit
4632 extraction. This will avoid the large constant, which might
4633 have taken more than one insn to make. If the constant were
4634 not a valid argument to the AND but took only one insn to make,
4635 this is no worse, but if it took more than one insn, it will
4638 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4639 && REG_P (XEXP (SET_SRC (x
), 0))
4640 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4641 && REG_P (SET_DEST (x
))
4642 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4643 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4644 && XEXP (*split
, 0) == SET_DEST (x
)
4645 && XEXP (*split
, 1) == const0_rtx
)
4647 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4648 XEXP (SET_SRC (x
), 0),
4649 pos
, NULL_RTX
, 1, 1, 0, 0);
4650 if (extraction
!= 0)
4652 SUBST (SET_SRC (x
), extraction
);
4653 return find_split_point (loc
, insn
, false);
4659 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4660 is known to be on, this can be converted into a NEG of a shift. */
4661 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4662 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4663 && 1 <= (pos
= exact_log2
4664 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4665 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4667 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4671 gen_rtx_LSHIFTRT (mode
,
4672 XEXP (SET_SRC (x
), 0),
4675 split
= find_split_point (&SET_SRC (x
), insn
, true);
4676 if (split
&& split
!= &SET_SRC (x
))
4682 inner
= XEXP (SET_SRC (x
), 0);
4684 /* We can't optimize if either mode is a partial integer
4685 mode as we don't know how many bits are significant
4687 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4688 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4692 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4698 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4699 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4701 inner
= XEXP (SET_SRC (x
), 0);
4702 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4703 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4705 if (BITS_BIG_ENDIAN
)
4706 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4707 unsignedp
= (code
== ZERO_EXTRACT
);
4716 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4718 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4720 /* For unsigned, we have a choice of a shift followed by an
4721 AND or two shifts. Use two shifts for field sizes where the
4722 constant might be too large. We assume here that we can
4723 always at least get 8-bit constants in an AND insn, which is
4724 true for every current RISC. */
4726 if (unsignedp
&& len
<= 8)
4731 (mode
, gen_lowpart (mode
, inner
),
4733 GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
)
4736 split
= find_split_point (&SET_SRC (x
), insn
, true);
4737 if (split
&& split
!= &SET_SRC (x
))
4744 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4745 gen_rtx_ASHIFT (mode
,
4746 gen_lowpart (mode
, inner
),
4747 GEN_INT (GET_MODE_PRECISION (mode
)
4749 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4751 split
= find_split_point (&SET_SRC (x
), insn
, true);
4752 if (split
&& split
!= &SET_SRC (x
))
4757 /* See if this is a simple operation with a constant as the second
4758 operand. It might be that this constant is out of range and hence
4759 could be used as a split point. */
4760 if (BINARY_P (SET_SRC (x
))
4761 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4762 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4763 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4764 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4765 return &XEXP (SET_SRC (x
), 1);
4767 /* Finally, see if this is a simple operation with its first operand
4768 not in a register. The operation might require this operand in a
4769 register, so return it as a split point. We can always do this
4770 because if the first operand were another operation, we would have
4771 already found it as a split point. */
4772 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4773 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4774 return &XEXP (SET_SRC (x
), 0);
4780 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4781 it is better to write this as (not (ior A B)) so we can split it.
4782 Similarly for IOR. */
4783 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4786 gen_rtx_NOT (GET_MODE (x
),
4787 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4789 XEXP (XEXP (x
, 0), 0),
4790 XEXP (XEXP (x
, 1), 0))));
4791 return find_split_point (loc
, insn
, set_src
);
4794 /* Many RISC machines have a large set of logical insns. If the
4795 second operand is a NOT, put it first so we will try to split the
4796 other operand first. */
4797 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4799 rtx tem
= XEXP (x
, 0);
4800 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4801 SUBST (XEXP (x
, 1), tem
);
4807 /* Canonicalization can produce (minus A (mult B C)), where C is a
4808 constant. It may be better to try splitting (plus (mult B -C) A)
4809 instead if this isn't a multiply by a power of two. */
4810 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4811 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4812 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4814 enum machine_mode mode
= GET_MODE (x
);
4815 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4816 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4817 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4818 XEXP (XEXP (x
, 1), 0),
4819 GEN_INT (other_int
)),
4821 return find_split_point (loc
, insn
, set_src
);
4824 /* Split at a multiply-accumulate instruction. However if this is
4825 the SET_SRC, we likely do not have such an instruction and it's
4826 worthless to try this split. */
4827 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4834 /* Otherwise, select our actions depending on our rtx class. */
4835 switch (GET_RTX_CLASS (code
))
4837 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4839 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4842 /* ... fall through ... */
4844 case RTX_COMM_ARITH
:
4846 case RTX_COMM_COMPARE
:
4847 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4850 /* ... fall through ... */
4852 /* Some machines have (and (shift ...) ...) insns. If X is not
4853 an AND, but XEXP (X, 0) is, use it as our split point. */
4854 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4855 return &XEXP (x
, 0);
4857 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4863 /* Otherwise, we don't have a split point. */
4868 /* Throughout X, replace FROM with TO, and return the result.
4869 The result is TO if X is FROM;
4870 otherwise the result is X, but its contents may have been modified.
4871 If they were modified, a record was made in undobuf so that
4872 undo_all will (among other things) return X to its original state.
4874 If the number of changes necessary is too much to record to undo,
4875 the excess changes are not made, so the result is invalid.
4876 The changes already made can still be undone.
4877 undobuf.num_undo is incremented for such changes, so by testing that
4878 the caller can tell whether the result is valid.
4880 `n_occurrences' is incremented each time FROM is replaced.
4882 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4884 IN_COND is nonzero if we are at the top level of a condition.
4886 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4887 by copying if `n_occurrences' is nonzero. */
4890 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4892 enum rtx_code code
= GET_CODE (x
);
4893 enum machine_mode op0_mode
= VOIDmode
;
4898 /* Two expressions are equal if they are identical copies of a shared
4899 RTX or if they are both registers with the same register number
4902 #define COMBINE_RTX_EQUAL_P(X,Y) \
4904 || (REG_P (X) && REG_P (Y) \
4905 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4907 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4910 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4913 /* If X and FROM are the same register but different modes, they
4914 will not have been seen as equal above. However, the log links code
4915 will make a LOG_LINKS entry for that case. If we do nothing, we
4916 will try to rerecognize our original insn and, when it succeeds,
4917 we will delete the feeding insn, which is incorrect.
4919 So force this insn not to match in this (rare) case. */
4920 if (! in_dest
&& code
== REG
&& REG_P (from
)
4921 && reg_overlap_mentioned_p (x
, from
))
4922 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4924 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4925 of which may contain things that can be combined. */
4926 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4929 /* It is possible to have a subexpression appear twice in the insn.
4930 Suppose that FROM is a register that appears within TO.
4931 Then, after that subexpression has been scanned once by `subst',
4932 the second time it is scanned, TO may be found. If we were
4933 to scan TO here, we would find FROM within it and create a
4934 self-referent rtl structure which is completely wrong. */
4935 if (COMBINE_RTX_EQUAL_P (x
, to
))
4938 /* Parallel asm_operands need special attention because all of the
4939 inputs are shared across the arms. Furthermore, unsharing the
4940 rtl results in recognition failures. Failure to handle this case
4941 specially can result in circular rtl.
4943 Solve this by doing a normal pass across the first entry of the
4944 parallel, and only processing the SET_DESTs of the subsequent
4947 if (code
== PARALLEL
4948 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4949 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4951 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
4953 /* If this substitution failed, this whole thing fails. */
4954 if (GET_CODE (new_rtx
) == CLOBBER
4955 && XEXP (new_rtx
, 0) == const0_rtx
)
4958 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4960 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4962 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4965 && GET_CODE (dest
) != CC0
4966 && GET_CODE (dest
) != PC
)
4968 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
4970 /* If this substitution failed, this whole thing fails. */
4971 if (GET_CODE (new_rtx
) == CLOBBER
4972 && XEXP (new_rtx
, 0) == const0_rtx
)
4975 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4981 len
= GET_RTX_LENGTH (code
);
4982 fmt
= GET_RTX_FORMAT (code
);
4984 /* We don't need to process a SET_DEST that is a register, CC0,
4985 or PC, so set up to skip this common case. All other cases
4986 where we want to suppress replacing something inside a
4987 SET_SRC are handled via the IN_DEST operand. */
4989 && (REG_P (SET_DEST (x
))
4990 || GET_CODE (SET_DEST (x
)) == CC0
4991 || GET_CODE (SET_DEST (x
)) == PC
))
4994 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4997 op0_mode
= GET_MODE (XEXP (x
, 0));
4999 for (i
= 0; i
< len
; i
++)
5004 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5006 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5008 new_rtx
= (unique_copy
&& n_occurrences
5009 ? copy_rtx (to
) : to
);
5014 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5017 /* If this substitution failed, this whole thing
5019 if (GET_CODE (new_rtx
) == CLOBBER
5020 && XEXP (new_rtx
, 0) == const0_rtx
)
5024 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5027 else if (fmt
[i
] == 'e')
5029 /* If this is a register being set, ignore it. */
5030 new_rtx
= XEXP (x
, i
);
5033 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5035 || code
== STRICT_LOW_PART
))
5038 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5040 /* In general, don't install a subreg involving two
5041 modes not tieable. It can worsen register
5042 allocation, and can even make invalid reload
5043 insns, since the reg inside may need to be copied
5044 from in the outside mode, and that may be invalid
5045 if it is an fp reg copied in integer mode.
5047 We allow two exceptions to this: It is valid if
5048 it is inside another SUBREG and the mode of that
5049 SUBREG and the mode of the inside of TO is
5050 tieable and it is valid if X is a SET that copies
5053 if (GET_CODE (to
) == SUBREG
5054 && ! MODES_TIEABLE_P (GET_MODE (to
),
5055 GET_MODE (SUBREG_REG (to
)))
5056 && ! (code
== SUBREG
5057 && MODES_TIEABLE_P (GET_MODE (x
),
5058 GET_MODE (SUBREG_REG (to
))))
5060 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5063 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5065 #ifdef CANNOT_CHANGE_MODE_CLASS
5068 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5069 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5072 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5075 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5079 /* If we are in a SET_DEST, suppress most cases unless we
5080 have gone inside a MEM, in which case we want to
5081 simplify the address. We assume here that things that
5082 are actually part of the destination have their inner
5083 parts in the first expression. This is true for SUBREG,
5084 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5085 things aside from REG and MEM that should appear in a
5087 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5089 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5090 || code
== ZERO_EXTRACT
))
5093 code
== IF_THEN_ELSE
&& i
== 0,
5096 /* If we found that we will have to reject this combination,
5097 indicate that by returning the CLOBBER ourselves, rather than
5098 an expression containing it. This will speed things up as
5099 well as prevent accidents where two CLOBBERs are considered
5100 to be equal, thus producing an incorrect simplification. */
5102 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5105 if (GET_CODE (x
) == SUBREG
5106 && (CONST_INT_P (new_rtx
) || CONST_DOUBLE_AS_INT_P (new_rtx
)))
5108 enum machine_mode mode
= GET_MODE (x
);
5110 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5111 GET_MODE (SUBREG_REG (x
)),
5114 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5116 else if (CONST_INT_P (new_rtx
)
5117 && GET_CODE (x
) == ZERO_EXTEND
)
5119 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5120 new_rtx
, GET_MODE (XEXP (x
, 0)));
5124 SUBST (XEXP (x
, i
), new_rtx
);
5129 /* Check if we are loading something from the constant pool via float
5130 extension; in this case we would undo compress_float_constant
5131 optimization and degenerate constant load to an immediate value. */
5132 if (GET_CODE (x
) == FLOAT_EXTEND
5133 && MEM_P (XEXP (x
, 0))
5134 && MEM_READONLY_P (XEXP (x
, 0)))
5136 rtx tmp
= avoid_constant_pool_reference (x
);
5141 /* Try to simplify X. If the simplification changed the code, it is likely
5142 that further simplification will help, so loop, but limit the number
5143 of repetitions that will be performed. */
5145 for (i
= 0; i
< 4; i
++)
5147 /* If X is sufficiently simple, don't bother trying to do anything
5149 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5150 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5152 if (GET_CODE (x
) == code
)
5155 code
= GET_CODE (x
);
5157 /* We no longer know the original mode of operand 0 since we
5158 have changed the form of X) */
5159 op0_mode
= VOIDmode
;
5165 /* Simplify X, a piece of RTL. We just operate on the expression at the
5166 outer level; call `subst' to simplify recursively. Return the new
5169 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5170 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5174 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5177 enum rtx_code code
= GET_CODE (x
);
5178 enum machine_mode mode
= GET_MODE (x
);
5182 /* If this is a commutative operation, put a constant last and a complex
5183 expression first. We don't need to do this for comparisons here. */
5184 if (COMMUTATIVE_ARITH_P (x
)
5185 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5188 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5189 SUBST (XEXP (x
, 1), temp
);
5192 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5193 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5194 things. Check for cases where both arms are testing the same
5197 Don't do anything if all operands are very simple. */
5200 && ((!OBJECT_P (XEXP (x
, 0))
5201 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5202 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5203 || (!OBJECT_P (XEXP (x
, 1))
5204 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5205 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5207 && (!OBJECT_P (XEXP (x
, 0))
5208 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5209 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5211 rtx cond
, true_rtx
, false_rtx
;
5213 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5215 /* If everything is a comparison, what we have is highly unlikely
5216 to be simpler, so don't use it. */
5217 && ! (COMPARISON_P (x
)
5218 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5220 rtx cop1
= const0_rtx
;
5221 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5223 if (cond_code
== NE
&& COMPARISON_P (cond
))
5226 /* Simplify the alternative arms; this may collapse the true and
5227 false arms to store-flag values. Be careful to use copy_rtx
5228 here since true_rtx or false_rtx might share RTL with x as a
5229 result of the if_then_else_cond call above. */
5230 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5231 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5233 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5234 is unlikely to be simpler. */
5235 if (general_operand (true_rtx
, VOIDmode
)
5236 && general_operand (false_rtx
, VOIDmode
))
5238 enum rtx_code reversed
;
5240 /* Restarting if we generate a store-flag expression will cause
5241 us to loop. Just drop through in this case. */
5243 /* If the result values are STORE_FLAG_VALUE and zero, we can
5244 just make the comparison operation. */
5245 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5246 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5248 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5249 && ((reversed
= reversed_comparison_code_parts
5250 (cond_code
, cond
, cop1
, NULL
))
5252 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5255 /* Likewise, we can make the negate of a comparison operation
5256 if the result values are - STORE_FLAG_VALUE and zero. */
5257 else if (CONST_INT_P (true_rtx
)
5258 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5259 && false_rtx
== const0_rtx
)
5260 x
= simplify_gen_unary (NEG
, mode
,
5261 simplify_gen_relational (cond_code
,
5265 else if (CONST_INT_P (false_rtx
)
5266 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5267 && true_rtx
== const0_rtx
5268 && ((reversed
= reversed_comparison_code_parts
5269 (cond_code
, cond
, cop1
, NULL
))
5271 x
= simplify_gen_unary (NEG
, mode
,
5272 simplify_gen_relational (reversed
,
5277 return gen_rtx_IF_THEN_ELSE (mode
,
5278 simplify_gen_relational (cond_code
,
5283 true_rtx
, false_rtx
);
5285 code
= GET_CODE (x
);
5286 op0_mode
= VOIDmode
;
5291 /* Try to fold this expression in case we have constants that weren't
5294 switch (GET_RTX_CLASS (code
))
5297 if (op0_mode
== VOIDmode
)
5298 op0_mode
= GET_MODE (XEXP (x
, 0));
5299 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5302 case RTX_COMM_COMPARE
:
5304 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5305 if (cmp_mode
== VOIDmode
)
5307 cmp_mode
= GET_MODE (XEXP (x
, 1));
5308 if (cmp_mode
== VOIDmode
)
5309 cmp_mode
= op0_mode
;
5311 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5312 XEXP (x
, 0), XEXP (x
, 1));
5315 case RTX_COMM_ARITH
:
5317 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5319 case RTX_BITFIELD_OPS
:
5321 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5322 XEXP (x
, 1), XEXP (x
, 2));
5331 code
= GET_CODE (temp
);
5332 op0_mode
= VOIDmode
;
5333 mode
= GET_MODE (temp
);
5336 /* First see if we can apply the inverse distributive law. */
5337 if (code
== PLUS
|| code
== MINUS
5338 || code
== AND
|| code
== IOR
|| code
== XOR
)
5340 x
= apply_distributive_law (x
);
5341 code
= GET_CODE (x
);
5342 op0_mode
= VOIDmode
;
5345 /* If CODE is an associative operation not otherwise handled, see if we
5346 can associate some operands. This can win if they are constants or
5347 if they are logically related (i.e. (a & b) & a). */
5348 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5349 || code
== AND
|| code
== IOR
|| code
== XOR
5350 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5351 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5352 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5354 if (GET_CODE (XEXP (x
, 0)) == code
)
5356 rtx other
= XEXP (XEXP (x
, 0), 0);
5357 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5358 rtx inner_op1
= XEXP (x
, 1);
5361 /* Make sure we pass the constant operand if any as the second
5362 one if this is a commutative operation. */
5363 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5365 rtx tem
= inner_op0
;
5366 inner_op0
= inner_op1
;
5369 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5370 : code
== DIV
? MULT
5372 mode
, inner_op0
, inner_op1
);
5374 /* For commutative operations, try the other pair if that one
5376 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5378 other
= XEXP (XEXP (x
, 0), 1);
5379 inner
= simplify_binary_operation (code
, mode
,
5380 XEXP (XEXP (x
, 0), 0),
5385 return simplify_gen_binary (code
, mode
, other
, inner
);
5389 /* A little bit of algebraic simplification here. */
5393 /* Ensure that our address has any ASHIFTs converted to MULT in case
5394 address-recognizing predicates are called later. */
5395 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5396 SUBST (XEXP (x
, 0), temp
);
5400 if (op0_mode
== VOIDmode
)
5401 op0_mode
= GET_MODE (SUBREG_REG (x
));
5403 /* See if this can be moved to simplify_subreg. */
5404 if (CONSTANT_P (SUBREG_REG (x
))
5405 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5406 /* Don't call gen_lowpart if the inner mode
5407 is VOIDmode and we cannot simplify it, as SUBREG without
5408 inner mode is invalid. */
5409 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5410 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5411 return gen_lowpart (mode
, SUBREG_REG (x
));
5413 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5417 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5423 /* Don't change the mode of the MEM if that would change the meaning
5425 if (MEM_P (SUBREG_REG (x
))
5426 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5427 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5428 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5429 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5431 /* Note that we cannot do any narrowing for non-constants since
5432 we might have been counting on using the fact that some bits were
5433 zero. We now do this in the SET. */
5438 temp
= expand_compound_operation (XEXP (x
, 0));
5440 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5441 replaced by (lshiftrt X C). This will convert
5442 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5444 if (GET_CODE (temp
) == ASHIFTRT
5445 && CONST_INT_P (XEXP (temp
, 1))
5446 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5447 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5448 INTVAL (XEXP (temp
, 1)));
5450 /* If X has only a single bit that might be nonzero, say, bit I, convert
5451 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5452 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5453 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5454 or a SUBREG of one since we'd be making the expression more
5455 complex if it was just a register. */
5458 && ! (GET_CODE (temp
) == SUBREG
5459 && REG_P (SUBREG_REG (temp
)))
5460 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5462 rtx temp1
= simplify_shift_const
5463 (NULL_RTX
, ASHIFTRT
, mode
,
5464 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5465 GET_MODE_PRECISION (mode
) - 1 - i
),
5466 GET_MODE_PRECISION (mode
) - 1 - i
);
5468 /* If all we did was surround TEMP with the two shifts, we
5469 haven't improved anything, so don't use it. Otherwise,
5470 we are better off with TEMP1. */
5471 if (GET_CODE (temp1
) != ASHIFTRT
5472 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5473 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5479 /* We can't handle truncation to a partial integer mode here
5480 because we don't know the real bitsize of the partial
5482 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5485 if (HWI_COMPUTABLE_MODE_P (mode
))
5487 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5488 GET_MODE_MASK (mode
), 0));
5490 /* We can truncate a constant value and return it. */
5491 if (CONST_INT_P (XEXP (x
, 0)))
5492 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5494 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5495 whose value is a comparison can be replaced with a subreg if
5496 STORE_FLAG_VALUE permits. */
5497 if (HWI_COMPUTABLE_MODE_P (mode
)
5498 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5499 && (temp
= get_last_value (XEXP (x
, 0)))
5500 && COMPARISON_P (temp
))
5501 return gen_lowpart (mode
, XEXP (x
, 0));
5505 /* (const (const X)) can become (const X). Do it this way rather than
5506 returning the inner CONST since CONST can be shared with a
5508 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5509 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5514 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5515 can add in an offset. find_split_point will split this address up
5516 again if it doesn't match. */
5517 if (GET_CODE (XEXP (x
, 0)) == HIGH
5518 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5524 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5525 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5526 bit-field and can be replaced by either a sign_extend or a
5527 sign_extract. The `and' may be a zero_extend and the two
5528 <c>, -<c> constants may be reversed. */
5529 if (GET_CODE (XEXP (x
, 0)) == XOR
5530 && CONST_INT_P (XEXP (x
, 1))
5531 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5532 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5533 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5534 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5535 && HWI_COMPUTABLE_MODE_P (mode
)
5536 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5537 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5538 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5539 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5540 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5541 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5542 == (unsigned int) i
+ 1))))
5543 return simplify_shift_const
5544 (NULL_RTX
, ASHIFTRT
, mode
,
5545 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5546 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5547 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5548 GET_MODE_PRECISION (mode
) - (i
+ 1));
5550 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5551 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5552 the bitsize of the mode - 1. This allows simplification of
5553 "a = (b & 8) == 0;" */
5554 if (XEXP (x
, 1) == constm1_rtx
5555 && !REG_P (XEXP (x
, 0))
5556 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5557 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5558 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5559 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5560 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5561 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5562 GET_MODE_PRECISION (mode
) - 1),
5563 GET_MODE_PRECISION (mode
) - 1);
5565 /* If we are adding two things that have no bits in common, convert
5566 the addition into an IOR. This will often be further simplified,
5567 for example in cases like ((a & 1) + (a & 2)), which can
5570 if (HWI_COMPUTABLE_MODE_P (mode
)
5571 && (nonzero_bits (XEXP (x
, 0), mode
)
5572 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5574 /* Try to simplify the expression further. */
5575 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5576 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5578 /* If we could, great. If not, do not go ahead with the IOR
5579 replacement, since PLUS appears in many special purpose
5580 address arithmetic instructions. */
5581 if (GET_CODE (temp
) != CLOBBER
5582 && (GET_CODE (temp
) != IOR
5583 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5584 || XEXP (temp
, 1) != XEXP (x
, 1))
5585 && (XEXP (temp
, 0) != XEXP (x
, 1)
5586 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5592 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5593 (and <foo> (const_int pow2-1)) */
5594 if (GET_CODE (XEXP (x
, 1)) == AND
5595 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5596 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5597 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5598 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5599 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5603 /* If we have (mult (plus A B) C), apply the distributive law and then
5604 the inverse distributive law to see if things simplify. This
5605 occurs mostly in addresses, often when unrolling loops. */
5607 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5609 rtx result
= distribute_and_simplify_rtx (x
, 0);
5614 /* Try simplify a*(b/c) as (a*b)/c. */
5615 if (FLOAT_MODE_P (mode
) && flag_associative_math
5616 && GET_CODE (XEXP (x
, 0)) == DIV
)
5618 rtx tem
= simplify_binary_operation (MULT
, mode
,
5619 XEXP (XEXP (x
, 0), 0),
5622 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5627 /* If this is a divide by a power of two, treat it as a shift if
5628 its first operand is a shift. */
5629 if (CONST_INT_P (XEXP (x
, 1))
5630 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5631 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5632 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5633 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5634 || GET_CODE (XEXP (x
, 0)) == ROTATE
5635 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5636 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5640 case GT
: case GTU
: case GE
: case GEU
:
5641 case LT
: case LTU
: case LE
: case LEU
:
5642 case UNEQ
: case LTGT
:
5643 case UNGT
: case UNGE
:
5644 case UNLT
: case UNLE
:
5645 case UNORDERED
: case ORDERED
:
5646 /* If the first operand is a condition code, we can't do anything
5648 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5649 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5650 && ! CC0_P (XEXP (x
, 0))))
5652 rtx op0
= XEXP (x
, 0);
5653 rtx op1
= XEXP (x
, 1);
5654 enum rtx_code new_code
;
5656 if (GET_CODE (op0
) == COMPARE
)
5657 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5659 /* Simplify our comparison, if possible. */
5660 new_code
= simplify_comparison (code
, &op0
, &op1
);
5662 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5663 if only the low-order bit is possibly nonzero in X (such as when
5664 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5665 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5666 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5669 Remove any ZERO_EXTRACT we made when thinking this was a
5670 comparison. It may now be simpler to use, e.g., an AND. If a
5671 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5672 the call to make_compound_operation in the SET case.
5674 Don't apply these optimizations if the caller would
5675 prefer a comparison rather than a value.
5676 E.g., for the condition in an IF_THEN_ELSE most targets need
5677 an explicit comparison. */
5682 else if (STORE_FLAG_VALUE
== 1
5683 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5684 && op1
== const0_rtx
5685 && mode
== GET_MODE (op0
)
5686 && nonzero_bits (op0
, mode
) == 1)
5687 return gen_lowpart (mode
,
5688 expand_compound_operation (op0
));
5690 else if (STORE_FLAG_VALUE
== 1
5691 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5692 && op1
== const0_rtx
5693 && mode
== GET_MODE (op0
)
5694 && (num_sign_bit_copies (op0
, mode
)
5695 == GET_MODE_PRECISION (mode
)))
5697 op0
= expand_compound_operation (op0
);
5698 return simplify_gen_unary (NEG
, mode
,
5699 gen_lowpart (mode
, op0
),
5703 else if (STORE_FLAG_VALUE
== 1
5704 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5705 && op1
== const0_rtx
5706 && mode
== GET_MODE (op0
)
5707 && nonzero_bits (op0
, mode
) == 1)
5709 op0
= expand_compound_operation (op0
);
5710 return simplify_gen_binary (XOR
, mode
,
5711 gen_lowpart (mode
, op0
),
5715 else if (STORE_FLAG_VALUE
== 1
5716 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5717 && op1
== const0_rtx
5718 && mode
== GET_MODE (op0
)
5719 && (num_sign_bit_copies (op0
, mode
)
5720 == GET_MODE_PRECISION (mode
)))
5722 op0
= expand_compound_operation (op0
);
5723 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5726 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5731 else if (STORE_FLAG_VALUE
== -1
5732 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5733 && op1
== const0_rtx
5734 && (num_sign_bit_copies (op0
, mode
)
5735 == GET_MODE_PRECISION (mode
)))
5736 return gen_lowpart (mode
,
5737 expand_compound_operation (op0
));
5739 else if (STORE_FLAG_VALUE
== -1
5740 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5741 && op1
== const0_rtx
5742 && mode
== GET_MODE (op0
)
5743 && nonzero_bits (op0
, mode
) == 1)
5745 op0
= expand_compound_operation (op0
);
5746 return simplify_gen_unary (NEG
, mode
,
5747 gen_lowpart (mode
, op0
),
5751 else if (STORE_FLAG_VALUE
== -1
5752 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5753 && op1
== const0_rtx
5754 && mode
== GET_MODE (op0
)
5755 && (num_sign_bit_copies (op0
, mode
)
5756 == GET_MODE_PRECISION (mode
)))
5758 op0
= expand_compound_operation (op0
);
5759 return simplify_gen_unary (NOT
, mode
,
5760 gen_lowpart (mode
, op0
),
5764 /* If X is 0/1, (eq X 0) is X-1. */
5765 else if (STORE_FLAG_VALUE
== -1
5766 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5767 && op1
== const0_rtx
5768 && mode
== GET_MODE (op0
)
5769 && nonzero_bits (op0
, mode
) == 1)
5771 op0
= expand_compound_operation (op0
);
5772 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5775 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5776 one bit that might be nonzero, we can convert (ne x 0) to
5777 (ashift x c) where C puts the bit in the sign bit. Remove any
5778 AND with STORE_FLAG_VALUE when we are done, since we are only
5779 going to test the sign bit. */
5780 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5781 && HWI_COMPUTABLE_MODE_P (mode
)
5782 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5783 && op1
== const0_rtx
5784 && mode
== GET_MODE (op0
)
5785 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5787 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5788 expand_compound_operation (op0
),
5789 GET_MODE_PRECISION (mode
) - 1 - i
);
5790 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5796 /* If the code changed, return a whole new comparison. */
5797 if (new_code
!= code
)
5798 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5800 /* Otherwise, keep this operation, but maybe change its operands.
5801 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5802 SUBST (XEXP (x
, 0), op0
);
5803 SUBST (XEXP (x
, 1), op1
);
5808 return simplify_if_then_else (x
);
5814 /* If we are processing SET_DEST, we are done. */
5818 return expand_compound_operation (x
);
5821 return simplify_set (x
);
5825 return simplify_logical (x
);
5832 /* If this is a shift by a constant amount, simplify it. */
5833 if (CONST_INT_P (XEXP (x
, 1)))
5834 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5835 INTVAL (XEXP (x
, 1)));
5837 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5839 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5840 ((unsigned HOST_WIDE_INT
) 1
5841 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5853 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5856 simplify_if_then_else (rtx x
)
5858 enum machine_mode mode
= GET_MODE (x
);
5859 rtx cond
= XEXP (x
, 0);
5860 rtx true_rtx
= XEXP (x
, 1);
5861 rtx false_rtx
= XEXP (x
, 2);
5862 enum rtx_code true_code
= GET_CODE (cond
);
5863 int comparison_p
= COMPARISON_P (cond
);
5866 enum rtx_code false_code
;
5869 /* Simplify storing of the truth value. */
5870 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5871 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5872 XEXP (cond
, 0), XEXP (cond
, 1));
5874 /* Also when the truth value has to be reversed. */
5876 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5877 && (reversed
= reversed_comparison (cond
, mode
)))
5880 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5881 in it is being compared against certain values. Get the true and false
5882 comparisons and see if that says anything about the value of each arm. */
5885 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5887 && REG_P (XEXP (cond
, 0)))
5890 rtx from
= XEXP (cond
, 0);
5891 rtx true_val
= XEXP (cond
, 1);
5892 rtx false_val
= true_val
;
5895 /* If FALSE_CODE is EQ, swap the codes and arms. */
5897 if (false_code
== EQ
)
5899 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5900 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5903 /* If we are comparing against zero and the expression being tested has
5904 only a single bit that might be nonzero, that is its value when it is
5905 not equal to zero. Similarly if it is known to be -1 or 0. */
5907 if (true_code
== EQ
&& true_val
== const0_rtx
5908 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5911 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5913 else if (true_code
== EQ
&& true_val
== const0_rtx
5914 && (num_sign_bit_copies (from
, GET_MODE (from
))
5915 == GET_MODE_PRECISION (GET_MODE (from
))))
5918 false_val
= constm1_rtx
;
5921 /* Now simplify an arm if we know the value of the register in the
5922 branch and it is used in the arm. Be careful due to the potential
5923 of locally-shared RTL. */
5925 if (reg_mentioned_p (from
, true_rtx
))
5926 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5928 pc_rtx
, pc_rtx
, 0, 0, 0);
5929 if (reg_mentioned_p (from
, false_rtx
))
5930 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5932 pc_rtx
, pc_rtx
, 0, 0, 0);
5934 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5935 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5937 true_rtx
= XEXP (x
, 1);
5938 false_rtx
= XEXP (x
, 2);
5939 true_code
= GET_CODE (cond
);
5942 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5943 reversed, do so to avoid needing two sets of patterns for
5944 subtract-and-branch insns. Similarly if we have a constant in the true
5945 arm, the false arm is the same as the first operand of the comparison, or
5946 the false arm is more complicated than the true arm. */
5949 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5950 && (true_rtx
== pc_rtx
5951 || (CONSTANT_P (true_rtx
)
5952 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5953 || true_rtx
== const0_rtx
5954 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5955 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5956 && !OBJECT_P (false_rtx
))
5957 || reg_mentioned_p (true_rtx
, false_rtx
)
5958 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5960 true_code
= reversed_comparison_code (cond
, NULL
);
5961 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5962 SUBST (XEXP (x
, 1), false_rtx
);
5963 SUBST (XEXP (x
, 2), true_rtx
);
5965 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5968 /* It is possible that the conditional has been simplified out. */
5969 true_code
= GET_CODE (cond
);
5970 comparison_p
= COMPARISON_P (cond
);
5973 /* If the two arms are identical, we don't need the comparison. */
5975 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5978 /* Convert a == b ? b : a to "a". */
5979 if (true_code
== EQ
&& ! side_effects_p (cond
)
5980 && !HONOR_NANS (mode
)
5981 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5982 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5984 else if (true_code
== NE
&& ! side_effects_p (cond
)
5985 && !HONOR_NANS (mode
)
5986 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5987 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5990 /* Look for cases where we have (abs x) or (neg (abs X)). */
5992 if (GET_MODE_CLASS (mode
) == MODE_INT
5994 && XEXP (cond
, 1) == const0_rtx
5995 && GET_CODE (false_rtx
) == NEG
5996 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5997 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5998 && ! side_effects_p (true_rtx
))
6003 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6007 simplify_gen_unary (NEG
, mode
,
6008 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6014 /* Look for MIN or MAX. */
6016 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6018 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6019 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6020 && ! side_effects_p (cond
))
6025 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6028 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6031 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6034 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6039 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6040 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6041 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6042 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6043 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6044 neither 1 or -1, but it isn't worth checking for. */
6046 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6048 && GET_MODE_CLASS (mode
) == MODE_INT
6049 && ! side_effects_p (x
))
6051 rtx t
= make_compound_operation (true_rtx
, SET
);
6052 rtx f
= make_compound_operation (false_rtx
, SET
);
6053 rtx cond_op0
= XEXP (cond
, 0);
6054 rtx cond_op1
= XEXP (cond
, 1);
6055 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6056 enum machine_mode m
= mode
;
6057 rtx z
= 0, c1
= NULL_RTX
;
6059 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6060 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6061 || GET_CODE (t
) == ASHIFT
6062 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6063 && rtx_equal_p (XEXP (t
, 0), f
))
6064 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6066 /* If an identity-zero op is commutative, check whether there
6067 would be a match if we swapped the operands. */
6068 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6069 || GET_CODE (t
) == XOR
)
6070 && rtx_equal_p (XEXP (t
, 1), f
))
6071 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6072 else if (GET_CODE (t
) == SIGN_EXTEND
6073 && (GET_CODE (XEXP (t
, 0)) == PLUS
6074 || GET_CODE (XEXP (t
, 0)) == MINUS
6075 || GET_CODE (XEXP (t
, 0)) == IOR
6076 || GET_CODE (XEXP (t
, 0)) == XOR
6077 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6078 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6079 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6080 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6081 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6082 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6083 && (num_sign_bit_copies (f
, GET_MODE (f
))
6085 (GET_MODE_PRECISION (mode
)
6086 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6088 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6089 extend_op
= SIGN_EXTEND
;
6090 m
= GET_MODE (XEXP (t
, 0));
6092 else if (GET_CODE (t
) == SIGN_EXTEND
6093 && (GET_CODE (XEXP (t
, 0)) == PLUS
6094 || GET_CODE (XEXP (t
, 0)) == IOR
6095 || GET_CODE (XEXP (t
, 0)) == XOR
)
6096 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6097 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6098 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6099 && (num_sign_bit_copies (f
, GET_MODE (f
))
6101 (GET_MODE_PRECISION (mode
)
6102 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6104 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6105 extend_op
= SIGN_EXTEND
;
6106 m
= GET_MODE (XEXP (t
, 0));
6108 else if (GET_CODE (t
) == ZERO_EXTEND
6109 && (GET_CODE (XEXP (t
, 0)) == PLUS
6110 || GET_CODE (XEXP (t
, 0)) == MINUS
6111 || GET_CODE (XEXP (t
, 0)) == IOR
6112 || GET_CODE (XEXP (t
, 0)) == XOR
6113 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6114 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6115 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6116 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6117 && HWI_COMPUTABLE_MODE_P (mode
)
6118 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6119 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6120 && ((nonzero_bits (f
, GET_MODE (f
))
6121 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6124 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6125 extend_op
= ZERO_EXTEND
;
6126 m
= GET_MODE (XEXP (t
, 0));
6128 else if (GET_CODE (t
) == ZERO_EXTEND
6129 && (GET_CODE (XEXP (t
, 0)) == PLUS
6130 || GET_CODE (XEXP (t
, 0)) == IOR
6131 || GET_CODE (XEXP (t
, 0)) == XOR
)
6132 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6133 && HWI_COMPUTABLE_MODE_P (mode
)
6134 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6135 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6136 && ((nonzero_bits (f
, GET_MODE (f
))
6137 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6140 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6141 extend_op
= ZERO_EXTEND
;
6142 m
= GET_MODE (XEXP (t
, 0));
6147 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6148 cond_op0
, cond_op1
),
6149 pc_rtx
, pc_rtx
, 0, 0, 0);
6150 temp
= simplify_gen_binary (MULT
, m
, temp
,
6151 simplify_gen_binary (MULT
, m
, c1
,
6153 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6154 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6156 if (extend_op
!= UNKNOWN
)
6157 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6163 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6164 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6165 negation of a single bit, we can convert this operation to a shift. We
6166 can actually do this more generally, but it doesn't seem worth it. */
6168 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6169 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6170 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6171 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6172 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6173 == GET_MODE_PRECISION (mode
))
6174 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6176 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6177 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6179 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6180 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6181 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6182 && GET_MODE (XEXP (cond
, 0)) == mode
6183 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6184 == nonzero_bits (XEXP (cond
, 0), mode
)
6185 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6186 return XEXP (cond
, 0);
6191 /* Simplify X, a SET expression. Return the new expression. */
6194 simplify_set (rtx x
)
6196 rtx src
= SET_SRC (x
);
6197 rtx dest
= SET_DEST (x
);
6198 enum machine_mode mode
6199 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6203 /* (set (pc) (return)) gets written as (return). */
6204 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6207 /* Now that we know for sure which bits of SRC we are using, see if we can
6208 simplify the expression for the object knowing that we only need the
6211 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6213 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6214 SUBST (SET_SRC (x
), src
);
6217 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6218 the comparison result and try to simplify it unless we already have used
6219 undobuf.other_insn. */
6220 if ((GET_MODE_CLASS (mode
) == MODE_CC
6221 || GET_CODE (src
) == COMPARE
6223 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6224 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6225 && COMPARISON_P (*cc_use
)
6226 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6228 enum rtx_code old_code
= GET_CODE (*cc_use
);
6229 enum rtx_code new_code
;
6231 int other_changed
= 0;
6232 rtx inner_compare
= NULL_RTX
;
6233 enum machine_mode compare_mode
= GET_MODE (dest
);
6235 if (GET_CODE (src
) == COMPARE
)
6237 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6238 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6240 inner_compare
= op0
;
6241 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6245 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6247 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6250 new_code
= old_code
;
6251 else if (!CONSTANT_P (tmp
))
6253 new_code
= GET_CODE (tmp
);
6254 op0
= XEXP (tmp
, 0);
6255 op1
= XEXP (tmp
, 1);
6259 rtx pat
= PATTERN (other_insn
);
6260 undobuf
.other_insn
= other_insn
;
6261 SUBST (*cc_use
, tmp
);
6263 /* Attempt to simplify CC user. */
6264 if (GET_CODE (pat
) == SET
)
6266 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6267 if (new_rtx
!= NULL_RTX
)
6268 SUBST (SET_SRC (pat
), new_rtx
);
6271 /* Convert X into a no-op move. */
6272 SUBST (SET_DEST (x
), pc_rtx
);
6273 SUBST (SET_SRC (x
), pc_rtx
);
6277 /* Simplify our comparison, if possible. */
6278 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6280 #ifdef SELECT_CC_MODE
6281 /* If this machine has CC modes other than CCmode, check to see if we
6282 need to use a different CC mode here. */
6283 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6284 compare_mode
= GET_MODE (op0
);
6285 else if (inner_compare
6286 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6287 && new_code
== old_code
6288 && op0
== XEXP (inner_compare
, 0)
6289 && op1
== XEXP (inner_compare
, 1))
6290 compare_mode
= GET_MODE (inner_compare
);
6292 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6295 /* If the mode changed, we have to change SET_DEST, the mode in the
6296 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6297 a hard register, just build new versions with the proper mode. If it
6298 is a pseudo, we lose unless it is only time we set the pseudo, in
6299 which case we can safely change its mode. */
6300 if (compare_mode
!= GET_MODE (dest
))
6302 if (can_change_dest_mode (dest
, 0, compare_mode
))
6304 unsigned int regno
= REGNO (dest
);
6307 if (regno
< FIRST_PSEUDO_REGISTER
)
6308 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6311 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6312 new_dest
= regno_reg_rtx
[regno
];
6315 SUBST (SET_DEST (x
), new_dest
);
6316 SUBST (XEXP (*cc_use
, 0), new_dest
);
6323 #endif /* SELECT_CC_MODE */
6325 /* If the code changed, we have to build a new comparison in
6326 undobuf.other_insn. */
6327 if (new_code
!= old_code
)
6329 int other_changed_previously
= other_changed
;
6330 unsigned HOST_WIDE_INT mask
;
6331 rtx old_cc_use
= *cc_use
;
6333 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6337 /* If the only change we made was to change an EQ into an NE or
6338 vice versa, OP0 has only one bit that might be nonzero, and OP1
6339 is zero, check if changing the user of the condition code will
6340 produce a valid insn. If it won't, we can keep the original code
6341 in that insn by surrounding our operation with an XOR. */
6343 if (((old_code
== NE
&& new_code
== EQ
)
6344 || (old_code
== EQ
&& new_code
== NE
))
6345 && ! other_changed_previously
&& op1
== const0_rtx
6346 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6347 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6349 rtx pat
= PATTERN (other_insn
), note
= 0;
6351 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6352 && ! check_asm_operands (pat
)))
6354 *cc_use
= old_cc_use
;
6357 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6358 op0
, GEN_INT (mask
));
6364 undobuf
.other_insn
= other_insn
;
6366 /* Otherwise, if we didn't previously have a COMPARE in the
6367 correct mode, we need one. */
6368 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6370 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6373 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6375 SUBST (SET_SRC (x
), op0
);
6378 /* Otherwise, update the COMPARE if needed. */
6379 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6381 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6387 /* Get SET_SRC in a form where we have placed back any
6388 compound expressions. Then do the checks below. */
6389 src
= make_compound_operation (src
, SET
);
6390 SUBST (SET_SRC (x
), src
);
6393 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6394 and X being a REG or (subreg (reg)), we may be able to convert this to
6395 (set (subreg:m2 x) (op)).
6397 We can always do this if M1 is narrower than M2 because that means that
6398 we only care about the low bits of the result.
6400 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6401 perform a narrower operation than requested since the high-order bits will
6402 be undefined. On machine where it is defined, this transformation is safe
6403 as long as M1 and M2 have the same number of words. */
6405 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6406 && !OBJECT_P (SUBREG_REG (src
))
6407 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6409 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6410 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6411 #ifndef WORD_REGISTER_OPERATIONS
6412 && (GET_MODE_SIZE (GET_MODE (src
))
6413 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6415 #ifdef CANNOT_CHANGE_MODE_CLASS
6416 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6417 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6418 GET_MODE (SUBREG_REG (src
)),
6422 || (GET_CODE (dest
) == SUBREG
6423 && REG_P (SUBREG_REG (dest
)))))
6425 SUBST (SET_DEST (x
),
6426 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6428 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6430 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6434 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6437 && GET_CODE (src
) == SUBREG
6438 && subreg_lowpart_p (src
)
6439 && (GET_MODE_PRECISION (GET_MODE (src
))
6440 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6442 rtx inner
= SUBREG_REG (src
);
6443 enum machine_mode inner_mode
= GET_MODE (inner
);
6445 /* Here we make sure that we don't have a sign bit on. */
6446 if (val_signbit_known_clear_p (GET_MODE (src
),
6447 nonzero_bits (inner
, inner_mode
)))
6449 SUBST (SET_SRC (x
), inner
);
6455 #ifdef LOAD_EXTEND_OP
6456 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6457 would require a paradoxical subreg. Replace the subreg with a
6458 zero_extend to avoid the reload that would otherwise be required. */
6460 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6461 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6462 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6463 && SUBREG_BYTE (src
) == 0
6464 && paradoxical_subreg_p (src
)
6465 && MEM_P (SUBREG_REG (src
)))
6468 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6469 GET_MODE (src
), SUBREG_REG (src
)));
6475 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6476 are comparing an item known to be 0 or -1 against 0, use a logical
6477 operation instead. Check for one of the arms being an IOR of the other
6478 arm with some value. We compute three terms to be IOR'ed together. In
6479 practice, at most two will be nonzero. Then we do the IOR's. */
6481 if (GET_CODE (dest
) != PC
6482 && GET_CODE (src
) == IF_THEN_ELSE
6483 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6484 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6485 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6486 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6487 #ifdef HAVE_conditional_move
6488 && ! can_conditionally_move_p (GET_MODE (src
))
6490 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6491 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6492 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6493 && ! side_effects_p (src
))
6495 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6496 ? XEXP (src
, 1) : XEXP (src
, 2));
6497 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6498 ? XEXP (src
, 2) : XEXP (src
, 1));
6499 rtx term1
= const0_rtx
, term2
, term3
;
6501 if (GET_CODE (true_rtx
) == IOR
6502 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6503 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6504 else if (GET_CODE (true_rtx
) == IOR
6505 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6506 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6507 else if (GET_CODE (false_rtx
) == IOR
6508 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6509 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6510 else if (GET_CODE (false_rtx
) == IOR
6511 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6512 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6514 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6515 XEXP (XEXP (src
, 0), 0), true_rtx
);
6516 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6517 simplify_gen_unary (NOT
, GET_MODE (src
),
6518 XEXP (XEXP (src
, 0), 0),
6523 simplify_gen_binary (IOR
, GET_MODE (src
),
6524 simplify_gen_binary (IOR
, GET_MODE (src
),
6531 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6532 whole thing fail. */
6533 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6535 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6538 /* Convert this into a field assignment operation, if possible. */
6539 return make_field_assignment (x
);
6542 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6546 simplify_logical (rtx x
)
6548 enum machine_mode mode
= GET_MODE (x
);
6549 rtx op0
= XEXP (x
, 0);
6550 rtx op1
= XEXP (x
, 1);
6552 switch (GET_CODE (x
))
6555 /* We can call simplify_and_const_int only if we don't lose
6556 any (sign) bits when converting INTVAL (op1) to
6557 "unsigned HOST_WIDE_INT". */
6558 if (CONST_INT_P (op1
)
6559 && (HWI_COMPUTABLE_MODE_P (mode
)
6560 || INTVAL (op1
) > 0))
6562 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6563 if (GET_CODE (x
) != AND
)
6570 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6571 apply the distributive law and then the inverse distributive
6572 law to see if things simplify. */
6573 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6575 rtx result
= distribute_and_simplify_rtx (x
, 0);
6579 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6581 rtx result
= distribute_and_simplify_rtx (x
, 1);
6588 /* If we have (ior (and A B) C), apply the distributive law and then
6589 the inverse distributive law to see if things simplify. */
6591 if (GET_CODE (op0
) == AND
)
6593 rtx result
= distribute_and_simplify_rtx (x
, 0);
6598 if (GET_CODE (op1
) == AND
)
6600 rtx result
= distribute_and_simplify_rtx (x
, 1);
6613 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6614 operations" because they can be replaced with two more basic operations.
6615 ZERO_EXTEND is also considered "compound" because it can be replaced with
6616 an AND operation, which is simpler, though only one operation.
6618 The function expand_compound_operation is called with an rtx expression
6619 and will convert it to the appropriate shifts and AND operations,
6620 simplifying at each stage.
6622 The function make_compound_operation is called to convert an expression
6623 consisting of shifts and ANDs into the equivalent compound expression.
6624 It is the inverse of this function, loosely speaking. */
6627 expand_compound_operation (rtx x
)
6629 unsigned HOST_WIDE_INT pos
= 0, len
;
6631 unsigned int modewidth
;
6634 switch (GET_CODE (x
))
6639 /* We can't necessarily use a const_int for a multiword mode;
6640 it depends on implicitly extending the value.
6641 Since we don't know the right way to extend it,
6642 we can't tell whether the implicit way is right.
6644 Even for a mode that is no wider than a const_int,
6645 we can't win, because we need to sign extend one of its bits through
6646 the rest of it, and we don't know which bit. */
6647 if (CONST_INT_P (XEXP (x
, 0)))
6650 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6651 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6652 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6653 reloaded. If not for that, MEM's would very rarely be safe.
6655 Reject MODEs bigger than a word, because we might not be able
6656 to reference a two-register group starting with an arbitrary register
6657 (and currently gen_lowpart might crash for a SUBREG). */
6659 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6662 /* Reject MODEs that aren't scalar integers because turning vector
6663 or complex modes into shifts causes problems. */
6665 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6668 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6669 /* If the inner object has VOIDmode (the only way this can happen
6670 is if it is an ASM_OPERANDS), we can't do anything since we don't
6671 know how much masking to do. */
6680 /* ... fall through ... */
6683 /* If the operand is a CLOBBER, just return it. */
6684 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6687 if (!CONST_INT_P (XEXP (x
, 1))
6688 || !CONST_INT_P (XEXP (x
, 2))
6689 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6692 /* Reject MODEs that aren't scalar integers because turning vector
6693 or complex modes into shifts causes problems. */
6695 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6698 len
= INTVAL (XEXP (x
, 1));
6699 pos
= INTVAL (XEXP (x
, 2));
6701 /* This should stay within the object being extracted, fail otherwise. */
6702 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6705 if (BITS_BIG_ENDIAN
)
6706 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6713 /* Convert sign extension to zero extension, if we know that the high
6714 bit is not set, as this is easier to optimize. It will be converted
6715 back to cheaper alternative in make_extraction. */
6716 if (GET_CODE (x
) == SIGN_EXTEND
6717 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6718 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6719 & ~(((unsigned HOST_WIDE_INT
)
6720 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6724 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6725 rtx temp2
= expand_compound_operation (temp
);
6727 /* Make sure this is a profitable operation. */
6728 if (set_src_cost (x
, optimize_this_for_speed_p
)
6729 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6731 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6732 > set_src_cost (temp
, optimize_this_for_speed_p
))
6738 /* We can optimize some special cases of ZERO_EXTEND. */
6739 if (GET_CODE (x
) == ZERO_EXTEND
)
6741 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6742 know that the last value didn't have any inappropriate bits
6744 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6745 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6746 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6747 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6748 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6749 return XEXP (XEXP (x
, 0), 0);
6751 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6752 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6753 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6754 && subreg_lowpart_p (XEXP (x
, 0))
6755 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6756 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6757 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6758 return SUBREG_REG (XEXP (x
, 0));
6760 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6761 is a comparison and STORE_FLAG_VALUE permits. This is like
6762 the first case, but it works even when GET_MODE (x) is larger
6763 than HOST_WIDE_INT. */
6764 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6765 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6766 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6767 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6768 <= HOST_BITS_PER_WIDE_INT
)
6769 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6770 return XEXP (XEXP (x
, 0), 0);
6772 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6773 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6774 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6775 && subreg_lowpart_p (XEXP (x
, 0))
6776 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6777 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6778 <= HOST_BITS_PER_WIDE_INT
)
6779 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6780 return SUBREG_REG (XEXP (x
, 0));
6784 /* If we reach here, we want to return a pair of shifts. The inner
6785 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6786 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6787 logical depending on the value of UNSIGNEDP.
6789 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6790 converted into an AND of a shift.
6792 We must check for the case where the left shift would have a negative
6793 count. This can happen in a case like (x >> 31) & 255 on machines
6794 that can't shift by a constant. On those machines, we would first
6795 combine the shift with the AND to produce a variable-position
6796 extraction. Then the constant of 31 would be substituted in
6797 to produce such a position. */
6799 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6800 if (modewidth
>= pos
+ len
)
6802 enum machine_mode mode
= GET_MODE (x
);
6803 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6804 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6806 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6807 tem
, modewidth
- pos
- len
);
6808 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6809 mode
, tem
, modewidth
- len
);
6811 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6812 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6813 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6816 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6818 /* Any other cases we can't handle. */
6821 /* If we couldn't do this for some reason, return the original
6823 if (GET_CODE (tem
) == CLOBBER
)
6829 /* X is a SET which contains an assignment of one object into
6830 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6831 or certain SUBREGS). If possible, convert it into a series of
6834 We half-heartedly support variable positions, but do not at all
6835 support variable lengths. */
6838 expand_field_assignment (const_rtx x
)
6841 rtx pos
; /* Always counts from low bit. */
6843 rtx mask
, cleared
, masked
;
6844 enum machine_mode compute_mode
;
6846 /* Loop until we find something we can't simplify. */
6849 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6850 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6852 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6853 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6854 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6856 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6857 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6859 inner
= XEXP (SET_DEST (x
), 0);
6860 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6861 pos
= XEXP (SET_DEST (x
), 2);
6863 /* A constant position should stay within the width of INNER. */
6864 if (CONST_INT_P (pos
)
6865 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6868 if (BITS_BIG_ENDIAN
)
6870 if (CONST_INT_P (pos
))
6871 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6873 else if (GET_CODE (pos
) == MINUS
6874 && CONST_INT_P (XEXP (pos
, 1))
6875 && (INTVAL (XEXP (pos
, 1))
6876 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6877 /* If position is ADJUST - X, new position is X. */
6878 pos
= XEXP (pos
, 0);
6880 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6881 GEN_INT (GET_MODE_PRECISION (
6888 /* A SUBREG between two modes that occupy the same numbers of words
6889 can be done by moving the SUBREG to the source. */
6890 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6891 /* We need SUBREGs to compute nonzero_bits properly. */
6892 && nonzero_sign_valid
6893 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6894 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6895 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6896 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6898 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6900 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6907 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6908 inner
= SUBREG_REG (inner
);
6910 compute_mode
= GET_MODE (inner
);
6912 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6913 if (! SCALAR_INT_MODE_P (compute_mode
))
6915 enum machine_mode imode
;
6917 /* Don't do anything for vector or complex integral types. */
6918 if (! FLOAT_MODE_P (compute_mode
))
6921 /* Try to find an integral mode to pun with. */
6922 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6923 if (imode
== BLKmode
)
6926 compute_mode
= imode
;
6927 inner
= gen_lowpart (imode
, inner
);
6930 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6931 if (len
>= HOST_BITS_PER_WIDE_INT
)
6934 /* Now compute the equivalent expression. Make a copy of INNER
6935 for the SET_DEST in case it is a MEM into which we will substitute;
6936 we don't want shared RTL in that case. */
6937 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6938 cleared
= simplify_gen_binary (AND
, compute_mode
,
6939 simplify_gen_unary (NOT
, compute_mode
,
6940 simplify_gen_binary (ASHIFT
,
6945 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6946 simplify_gen_binary (
6948 gen_lowpart (compute_mode
, SET_SRC (x
)),
6952 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6953 simplify_gen_binary (IOR
, compute_mode
,
6960 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6961 it is an RTX that represents a variable starting position; otherwise,
6962 POS is the (constant) starting bit position (counted from the LSB).
6964 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6967 IN_DEST is nonzero if this is a reference in the destination of a
6968 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6969 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6972 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6973 ZERO_EXTRACT should be built even for bits starting at bit 0.
6975 MODE is the desired mode of the result (if IN_DEST == 0).
6977 The result is an RTX for the extraction or NULL_RTX if the target
6981 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6982 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6983 int in_dest
, int in_compare
)
6985 /* This mode describes the size of the storage area
6986 to fetch the overall value from. Within that, we
6987 ignore the POS lowest bits, etc. */
6988 enum machine_mode is_mode
= GET_MODE (inner
);
6989 enum machine_mode inner_mode
;
6990 enum machine_mode wanted_inner_mode
;
6991 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6992 enum machine_mode pos_mode
= word_mode
;
6993 enum machine_mode extraction_mode
= word_mode
;
6994 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6996 rtx orig_pos_rtx
= pos_rtx
;
6997 HOST_WIDE_INT orig_pos
;
6999 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7001 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7002 consider just the QI as the memory to extract from.
7003 The subreg adds or removes high bits; its mode is
7004 irrelevant to the meaning of this extraction,
7005 since POS and LEN count from the lsb. */
7006 if (MEM_P (SUBREG_REG (inner
)))
7007 is_mode
= GET_MODE (SUBREG_REG (inner
));
7008 inner
= SUBREG_REG (inner
);
7010 else if (GET_CODE (inner
) == ASHIFT
7011 && CONST_INT_P (XEXP (inner
, 1))
7012 && pos_rtx
== 0 && pos
== 0
7013 && len
> UINTVAL (XEXP (inner
, 1)))
7015 /* We're extracting the least significant bits of an rtx
7016 (ashift X (const_int C)), where LEN > C. Extract the
7017 least significant (LEN - C) bits of X, giving an rtx
7018 whose mode is MODE, then shift it left C times. */
7019 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7020 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7021 unsignedp
, in_dest
, in_compare
);
7023 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7026 inner_mode
= GET_MODE (inner
);
7028 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7029 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7031 /* See if this can be done without an extraction. We never can if the
7032 width of the field is not the same as that of some integer mode. For
7033 registers, we can only avoid the extraction if the position is at the
7034 low-order bit and this is either not in the destination or we have the
7035 appropriate STRICT_LOW_PART operation available.
7037 For MEM, we can avoid an extract if the field starts on an appropriate
7038 boundary and we can change the mode of the memory reference. */
7040 if (tmode
!= BLKmode
7041 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7043 && (inner_mode
== tmode
7045 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7046 || reg_truncated_to_mode (tmode
, inner
))
7049 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7050 || (MEM_P (inner
) && pos_rtx
== 0
7052 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7053 : BITS_PER_UNIT
)) == 0
7054 /* We can't do this if we are widening INNER_MODE (it
7055 may not be aligned, for one thing). */
7056 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7057 && (inner_mode
== tmode
7058 || (! mode_dependent_address_p (XEXP (inner
, 0),
7059 MEM_ADDR_SPACE (inner
))
7060 && ! MEM_VOLATILE_P (inner
))))))
7062 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7063 field. If the original and current mode are the same, we need not
7064 adjust the offset. Otherwise, we do if bytes big endian.
7066 If INNER is not a MEM, get a piece consisting of just the field
7067 of interest (in this case POS % BITS_PER_WORD must be 0). */
7071 HOST_WIDE_INT offset
;
7073 /* POS counts from lsb, but make OFFSET count in memory order. */
7074 if (BYTES_BIG_ENDIAN
)
7075 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7077 offset
= pos
/ BITS_PER_UNIT
;
7079 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7081 else if (REG_P (inner
))
7083 if (tmode
!= inner_mode
)
7085 /* We can't call gen_lowpart in a DEST since we
7086 always want a SUBREG (see below) and it would sometimes
7087 return a new hard register. */
7090 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7092 if (WORDS_BIG_ENDIAN
7093 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7094 final_word
= ((GET_MODE_SIZE (inner_mode
)
7095 - GET_MODE_SIZE (tmode
))
7096 / UNITS_PER_WORD
) - final_word
;
7098 final_word
*= UNITS_PER_WORD
;
7099 if (BYTES_BIG_ENDIAN
&&
7100 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7101 final_word
+= (GET_MODE_SIZE (inner_mode
)
7102 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7104 /* Avoid creating invalid subregs, for example when
7105 simplifying (x>>32)&255. */
7106 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7109 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7112 new_rtx
= gen_lowpart (tmode
, inner
);
7118 new_rtx
= force_to_mode (inner
, tmode
,
7119 len
>= HOST_BITS_PER_WIDE_INT
7120 ? ~(unsigned HOST_WIDE_INT
) 0
7121 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7124 /* If this extraction is going into the destination of a SET,
7125 make a STRICT_LOW_PART unless we made a MEM. */
7128 return (MEM_P (new_rtx
) ? new_rtx
7129 : (GET_CODE (new_rtx
) != SUBREG
7130 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7131 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7136 if (CONST_INT_P (new_rtx
) || CONST_DOUBLE_AS_INT_P (new_rtx
))
7137 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7138 mode
, new_rtx
, tmode
);
7140 /* If we know that no extraneous bits are set, and that the high
7141 bit is not set, convert the extraction to the cheaper of
7142 sign and zero extension, that are equivalent in these cases. */
7143 if (flag_expensive_optimizations
7144 && (HWI_COMPUTABLE_MODE_P (tmode
)
7145 && ((nonzero_bits (new_rtx
, tmode
)
7146 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7149 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7150 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7152 /* Prefer ZERO_EXTENSION, since it gives more information to
7154 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7155 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7160 /* Otherwise, sign- or zero-extend unless we already are in the
7163 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7167 /* Unless this is a COMPARE or we have a funny memory reference,
7168 don't do anything with zero-extending field extracts starting at
7169 the low-order bit since they are simple AND operations. */
7170 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7171 && ! in_compare
&& unsignedp
)
7174 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7175 if the position is not a constant and the length is not 1. In all
7176 other cases, we would only be going outside our object in cases when
7177 an original shift would have been undefined. */
7179 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7180 || (pos_rtx
!= 0 && len
!= 1)))
7183 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7184 and the mode for the result. */
7185 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7187 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7188 pos_mode
= mode_for_extraction (EP_insv
, 2);
7189 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7192 if (! in_dest
&& unsignedp
7193 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7195 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7196 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7197 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7200 if (! in_dest
&& ! unsignedp
7201 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7203 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7204 pos_mode
= mode_for_extraction (EP_extv
, 3);
7205 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7208 /* Never narrow an object, since that might not be safe. */
7210 if (mode
!= VOIDmode
7211 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7212 extraction_mode
= mode
;
7214 /* If this is not from memory, the desired mode is the preferred mode
7215 for an extraction pattern's first input operand, or word_mode if there
7218 wanted_inner_mode
= wanted_inner_reg_mode
;
7221 /* Be careful not to go beyond the extracted object and maintain the
7222 natural alignment of the memory. */
7223 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7224 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7225 > GET_MODE_BITSIZE (wanted_inner_mode
))
7227 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7228 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7234 if (BITS_BIG_ENDIAN
)
7236 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7237 BITS_BIG_ENDIAN style. If position is constant, compute new
7238 position. Otherwise, build subtraction.
7239 Note that POS is relative to the mode of the original argument.
7240 If it's a MEM we need to recompute POS relative to that.
7241 However, if we're extracting from (or inserting into) a register,
7242 we want to recompute POS relative to wanted_inner_mode. */
7243 int width
= (MEM_P (inner
)
7244 ? GET_MODE_BITSIZE (is_mode
)
7245 : GET_MODE_BITSIZE (wanted_inner_mode
));
7248 pos
= width
- len
- pos
;
7251 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7252 /* POS may be less than 0 now, but we check for that below.
7253 Note that it can only be less than 0 if !MEM_P (inner). */
7256 /* If INNER has a wider mode, and this is a constant extraction, try to
7257 make it smaller and adjust the byte to point to the byte containing
7259 if (wanted_inner_mode
!= VOIDmode
7260 && inner_mode
!= wanted_inner_mode
7262 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7264 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7265 && ! MEM_VOLATILE_P (inner
))
7269 /* The computations below will be correct if the machine is big
7270 endian in both bits and bytes or little endian in bits and bytes.
7271 If it is mixed, we must adjust. */
7273 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7274 adjust OFFSET to compensate. */
7275 if (BYTES_BIG_ENDIAN
7276 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7277 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7279 /* We can now move to the desired byte. */
7280 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7281 * GET_MODE_SIZE (wanted_inner_mode
);
7282 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7284 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7285 && is_mode
!= wanted_inner_mode
)
7286 offset
= (GET_MODE_SIZE (is_mode
)
7287 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7289 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7292 /* If INNER is not memory, get it into the proper mode. If we are changing
7293 its mode, POS must be a constant and smaller than the size of the new
7295 else if (!MEM_P (inner
))
7297 /* On the LHS, don't create paradoxical subregs implicitely truncating
7298 the register unless TRULY_NOOP_TRUNCATION. */
7300 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7304 if (GET_MODE (inner
) != wanted_inner_mode
7306 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7312 inner
= force_to_mode (inner
, wanted_inner_mode
,
7314 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7315 ? ~(unsigned HOST_WIDE_INT
) 0
7316 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7321 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7322 have to zero extend. Otherwise, we can just use a SUBREG. */
7324 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7326 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7328 /* If we know that no extraneous bits are set, and that the high
7329 bit is not set, convert extraction to cheaper one - either
7330 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7332 if (flag_expensive_optimizations
7333 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7334 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7335 & ~(((unsigned HOST_WIDE_INT
)
7336 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7340 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7342 /* Prefer ZERO_EXTENSION, since it gives more information to
7344 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7345 < set_src_cost (temp
, optimize_this_for_speed_p
))
7351 /* Make POS_RTX unless we already have it and it is correct. If we don't
7352 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7354 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7355 pos_rtx
= orig_pos_rtx
;
7357 else if (pos_rtx
== 0)
7358 pos_rtx
= GEN_INT (pos
);
7360 /* Make the required operation. See if we can use existing rtx. */
7361 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7362 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7364 new_rtx
= gen_lowpart (mode
, new_rtx
);
7369 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7370 with any other operations in X. Return X without that shift if so. */
7373 extract_left_shift (rtx x
, int count
)
7375 enum rtx_code code
= GET_CODE (x
);
7376 enum machine_mode mode
= GET_MODE (x
);
7382 /* This is the shift itself. If it is wide enough, we will return
7383 either the value being shifted if the shift count is equal to
7384 COUNT or a shift for the difference. */
7385 if (CONST_INT_P (XEXP (x
, 1))
7386 && INTVAL (XEXP (x
, 1)) >= count
)
7387 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7388 INTVAL (XEXP (x
, 1)) - count
);
7392 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7393 return simplify_gen_unary (code
, mode
, tem
, mode
);
7397 case PLUS
: case IOR
: case XOR
: case AND
:
7398 /* If we can safely shift this constant and we find the inner shift,
7399 make a new operation. */
7400 if (CONST_INT_P (XEXP (x
, 1))
7401 && (UINTVAL (XEXP (x
, 1))
7402 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7403 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7404 return simplify_gen_binary (code
, mode
, tem
,
7405 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7416 /* Look at the expression rooted at X. Look for expressions
7417 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7418 Form these expressions.
7420 Return the new rtx, usually just X.
7422 Also, for machines like the VAX that don't have logical shift insns,
7423 try to convert logical to arithmetic shift operations in cases where
7424 they are equivalent. This undoes the canonicalizations to logical
7425 shifts done elsewhere.
7427 We try, as much as possible, to re-use rtl expressions to save memory.
7429 IN_CODE says what kind of expression we are processing. Normally, it is
7430 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7431 being kludges), it is MEM. When processing the arguments of a comparison
7432 or a COMPARE against zero, it is COMPARE. */
7435 make_compound_operation (rtx x
, enum rtx_code in_code
)
7437 enum rtx_code code
= GET_CODE (x
);
7438 enum machine_mode mode
= GET_MODE (x
);
7439 int mode_width
= GET_MODE_PRECISION (mode
);
7441 enum rtx_code next_code
;
7447 /* Select the code to be used in recursive calls. Once we are inside an
7448 address, we stay there. If we have a comparison, set to COMPARE,
7449 but once inside, go back to our default of SET. */
7451 next_code
= (code
== MEM
? MEM
7452 : ((code
== PLUS
|| code
== MINUS
)
7453 && SCALAR_INT_MODE_P (mode
)) ? MEM
7454 : ((code
== COMPARE
|| COMPARISON_P (x
))
7455 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7456 : in_code
== COMPARE
? SET
: in_code
);
7458 /* Process depending on the code of this operation. If NEW is set
7459 nonzero, it will be returned. */
7464 /* Convert shifts by constants into multiplications if inside
7466 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7467 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7468 && INTVAL (XEXP (x
, 1)) >= 0
7469 && SCALAR_INT_MODE_P (mode
))
7471 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7472 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7474 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7475 if (GET_CODE (new_rtx
) == NEG
)
7477 new_rtx
= XEXP (new_rtx
, 0);
7480 multval
= trunc_int_for_mode (multval
, mode
);
7481 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7488 lhs
= make_compound_operation (lhs
, next_code
);
7489 rhs
= make_compound_operation (rhs
, next_code
);
7490 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7491 && SCALAR_INT_MODE_P (mode
))
7493 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7495 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7497 else if (GET_CODE (lhs
) == MULT
7498 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7500 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7501 simplify_gen_unary (NEG
, mode
,
7504 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7508 SUBST (XEXP (x
, 0), lhs
);
7509 SUBST (XEXP (x
, 1), rhs
);
7512 x
= gen_lowpart (mode
, new_rtx
);
7518 lhs
= make_compound_operation (lhs
, next_code
);
7519 rhs
= make_compound_operation (rhs
, next_code
);
7520 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7521 && SCALAR_INT_MODE_P (mode
))
7523 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7525 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7527 else if (GET_CODE (rhs
) == MULT
7528 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7530 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7531 simplify_gen_unary (NEG
, mode
,
7534 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7538 SUBST (XEXP (x
, 0), lhs
);
7539 SUBST (XEXP (x
, 1), rhs
);
7542 return gen_lowpart (mode
, new_rtx
);
7545 /* If the second operand is not a constant, we can't do anything
7547 if (!CONST_INT_P (XEXP (x
, 1)))
7550 /* If the constant is a power of two minus one and the first operand
7551 is a logical right shift, make an extraction. */
7552 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7553 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7555 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7556 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7557 0, in_code
== COMPARE
);
7560 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7561 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7562 && subreg_lowpart_p (XEXP (x
, 0))
7563 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7564 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7566 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7568 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7569 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7570 0, in_code
== COMPARE
);
7572 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7573 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7574 || GET_CODE (XEXP (x
, 0)) == IOR
)
7575 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7576 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7577 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7579 /* Apply the distributive law, and then try to make extractions. */
7580 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7581 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7583 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7585 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7588 /* If we are have (and (rotate X C) M) and C is larger than the number
7589 of bits in M, this is an extraction. */
7591 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7592 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7593 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7594 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7596 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7597 new_rtx
= make_extraction (mode
, new_rtx
,
7598 (GET_MODE_PRECISION (mode
)
7599 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7600 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7603 /* On machines without logical shifts, if the operand of the AND is
7604 a logical shift and our mask turns off all the propagated sign
7605 bits, we can replace the logical shift with an arithmetic shift. */
7606 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7607 && !have_insn_for (LSHIFTRT
, mode
)
7608 && have_insn_for (ASHIFTRT
, mode
)
7609 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7610 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7611 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7612 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7614 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7616 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7617 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7619 gen_rtx_ASHIFTRT (mode
,
7620 make_compound_operation
7621 (XEXP (XEXP (x
, 0), 0), next_code
),
7622 XEXP (XEXP (x
, 0), 1)));
7625 /* If the constant is one less than a power of two, this might be
7626 representable by an extraction even if no shift is present.
7627 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7628 we are in a COMPARE. */
7629 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7630 new_rtx
= make_extraction (mode
,
7631 make_compound_operation (XEXP (x
, 0),
7633 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7635 /* If we are in a comparison and this is an AND with a power of two,
7636 convert this into the appropriate bit extract. */
7637 else if (in_code
== COMPARE
7638 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7639 new_rtx
= make_extraction (mode
,
7640 make_compound_operation (XEXP (x
, 0),
7642 i
, NULL_RTX
, 1, 1, 0, 1);
7647 /* If the sign bit is known to be zero, replace this with an
7648 arithmetic shift. */
7649 if (have_insn_for (ASHIFTRT
, mode
)
7650 && ! have_insn_for (LSHIFTRT
, mode
)
7651 && mode_width
<= HOST_BITS_PER_WIDE_INT
7652 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7654 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7655 make_compound_operation (XEXP (x
, 0),
7661 /* ... fall through ... */
7667 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7668 this is a SIGN_EXTRACT. */
7669 if (CONST_INT_P (rhs
)
7670 && GET_CODE (lhs
) == ASHIFT
7671 && CONST_INT_P (XEXP (lhs
, 1))
7672 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7673 && INTVAL (XEXP (lhs
, 1)) >= 0
7674 && INTVAL (rhs
) < mode_width
)
7676 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7677 new_rtx
= make_extraction (mode
, new_rtx
,
7678 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7679 NULL_RTX
, mode_width
- INTVAL (rhs
),
7680 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7684 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7685 If so, try to merge the shifts into a SIGN_EXTEND. We could
7686 also do this for some cases of SIGN_EXTRACT, but it doesn't
7687 seem worth the effort; the case checked for occurs on Alpha. */
7690 && ! (GET_CODE (lhs
) == SUBREG
7691 && (OBJECT_P (SUBREG_REG (lhs
))))
7692 && CONST_INT_P (rhs
)
7693 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7694 && INTVAL (rhs
) < mode_width
7695 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7696 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7697 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7698 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7703 /* Call ourselves recursively on the inner expression. If we are
7704 narrowing the object and it has a different RTL code from
7705 what it originally did, do this SUBREG as a force_to_mode. */
7707 rtx inner
= SUBREG_REG (x
), simplified
;
7709 tem
= make_compound_operation (inner
, in_code
);
7712 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7716 if (GET_CODE (tem
) != GET_CODE (inner
)
7717 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7718 && subreg_lowpart_p (x
))
7721 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7723 /* If we have something other than a SUBREG, we might have
7724 done an expansion, so rerun ourselves. */
7725 if (GET_CODE (newer
) != SUBREG
)
7726 newer
= make_compound_operation (newer
, in_code
);
7728 /* force_to_mode can expand compounds. If it just re-expanded the
7729 compound, use gen_lowpart to convert to the desired mode. */
7730 if (rtx_equal_p (newer
, x
)
7731 /* Likewise if it re-expanded the compound only partially.
7732 This happens for SUBREG of ZERO_EXTRACT if they extract
7733 the same number of bits. */
7734 || (GET_CODE (newer
) == SUBREG
7735 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7736 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7737 && GET_CODE (inner
) == AND
7738 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7739 return gen_lowpart (GET_MODE (x
), tem
);
7755 x
= gen_lowpart (mode
, new_rtx
);
7756 code
= GET_CODE (x
);
7759 /* Now recursively process each operand of this operation. We need to
7760 handle ZERO_EXTEND specially so that we don't lose track of the
7762 if (GET_CODE (x
) == ZERO_EXTEND
)
7764 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7765 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7766 new_rtx
, GET_MODE (XEXP (x
, 0)));
7769 SUBST (XEXP (x
, 0), new_rtx
);
7773 fmt
= GET_RTX_FORMAT (code
);
7774 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7777 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7778 SUBST (XEXP (x
, i
), new_rtx
);
7780 else if (fmt
[i
] == 'E')
7781 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7783 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7784 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7788 /* If this is a commutative operation, the changes to the operands
7789 may have made it noncanonical. */
7790 if (COMMUTATIVE_ARITH_P (x
)
7791 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7794 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7795 SUBST (XEXP (x
, 1), tem
);
7801 /* Given M see if it is a value that would select a field of bits
7802 within an item, but not the entire word. Return -1 if not.
7803 Otherwise, return the starting position of the field, where 0 is the
7806 *PLEN is set to the length of the field. */
7809 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7811 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7812 int pos
= m
? ctz_hwi (m
) : -1;
7816 /* Now shift off the low-order zero bits and see if we have a
7817 power of two minus 1. */
7818 len
= exact_log2 ((m
>> pos
) + 1);
7827 /* If X refers to a register that equals REG in value, replace these
7828 references with REG. */
7830 canon_reg_for_combine (rtx x
, rtx reg
)
7837 enum rtx_code code
= GET_CODE (x
);
7838 switch (GET_RTX_CLASS (code
))
7841 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7842 if (op0
!= XEXP (x
, 0))
7843 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7848 case RTX_COMM_ARITH
:
7849 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7850 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7851 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7852 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7856 case RTX_COMM_COMPARE
:
7857 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7858 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7859 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7860 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7861 GET_MODE (op0
), op0
, op1
);
7865 case RTX_BITFIELD_OPS
:
7866 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7867 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7868 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7869 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7870 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7871 GET_MODE (op0
), op0
, op1
, op2
);
7876 if (rtx_equal_p (get_last_value (reg
), x
)
7877 || rtx_equal_p (reg
, get_last_value (x
)))
7886 fmt
= GET_RTX_FORMAT (code
);
7888 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7891 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7892 if (op
!= XEXP (x
, i
))
7902 else if (fmt
[i
] == 'E')
7905 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7907 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7908 if (op
!= XVECEXP (x
, i
, j
))
7915 XVECEXP (x
, i
, j
) = op
;
7926 /* Return X converted to MODE. If the value is already truncated to
7927 MODE we can just return a subreg even though in the general case we
7928 would need an explicit truncation. */
7931 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7933 if (!CONST_INT_P (x
)
7934 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7935 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
7936 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7938 /* Bit-cast X into an integer mode. */
7939 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7940 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7941 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7945 return gen_lowpart (mode
, x
);
7948 /* See if X can be simplified knowing that we will only refer to it in
7949 MODE and will only refer to those bits that are nonzero in MASK.
7950 If other bits are being computed or if masking operations are done
7951 that select a superset of the bits in MASK, they can sometimes be
7954 Return a possibly simplified expression, but always convert X to
7955 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7957 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7958 are all off in X. This is used when X will be complemented, by either
7959 NOT, NEG, or XOR. */
7962 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7965 enum rtx_code code
= GET_CODE (x
);
7966 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7967 enum machine_mode op_mode
;
7968 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7971 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7972 code below will do the wrong thing since the mode of such an
7973 expression is VOIDmode.
7975 Also do nothing if X is a CLOBBER; this can happen if X was
7976 the return value from a call to gen_lowpart. */
7977 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7980 /* We want to perform the operation is its present mode unless we know
7981 that the operation is valid in MODE, in which case we do the operation
7983 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7984 && have_insn_for (code
, mode
))
7985 ? mode
: GET_MODE (x
));
7987 /* It is not valid to do a right-shift in a narrower mode
7988 than the one it came in with. */
7989 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7990 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
7991 op_mode
= GET_MODE (x
);
7993 /* Truncate MASK to fit OP_MODE. */
7995 mask
&= GET_MODE_MASK (op_mode
);
7997 /* When we have an arithmetic operation, or a shift whose count we
7998 do not know, we need to assume that all bits up to the highest-order
7999 bit in MASK will be needed. This is how we form such a mask. */
8000 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8001 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8003 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8006 /* Determine what bits of X are guaranteed to be (non)zero. */
8007 nonzero
= nonzero_bits (x
, mode
);
8009 /* If none of the bits in X are needed, return a zero. */
8010 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8013 /* If X is a CONST_INT, return a new one. Do this here since the
8014 test below will fail. */
8015 if (CONST_INT_P (x
))
8017 if (SCALAR_INT_MODE_P (mode
))
8018 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8021 x
= GEN_INT (INTVAL (x
) & mask
);
8022 return gen_lowpart_common (mode
, x
);
8026 /* If X is narrower than MODE and we want all the bits in X's mode, just
8027 get X in the proper mode. */
8028 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8029 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8030 return gen_lowpart (mode
, x
);
8032 /* We can ignore the effect of a SUBREG if it narrows the mode or
8033 if the constant masks to zero all the bits the mode doesn't have. */
8034 if (GET_CODE (x
) == SUBREG
8035 && subreg_lowpart_p (x
)
8036 && ((GET_MODE_SIZE (GET_MODE (x
))
8037 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8039 & GET_MODE_MASK (GET_MODE (x
))
8040 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8041 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8043 /* The arithmetic simplifications here only work for scalar integer modes. */
8044 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8045 return gen_lowpart_or_truncate (mode
, x
);
8050 /* If X is a (clobber (const_int)), return it since we know we are
8051 generating something that won't match. */
8058 x
= expand_compound_operation (x
);
8059 if (GET_CODE (x
) != code
)
8060 return force_to_mode (x
, mode
, mask
, next_select
);
8064 /* Similarly for a truncate. */
8065 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8068 /* If this is an AND with a constant, convert it into an AND
8069 whose constant is the AND of that constant with MASK. If it
8070 remains an AND of MASK, delete it since it is redundant. */
8072 if (CONST_INT_P (XEXP (x
, 1)))
8074 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8075 mask
& INTVAL (XEXP (x
, 1)));
8077 /* If X is still an AND, see if it is an AND with a mask that
8078 is just some low-order bits. If so, and it is MASK, we don't
8081 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8082 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8086 /* If it remains an AND, try making another AND with the bits
8087 in the mode mask that aren't in MASK turned on. If the
8088 constant in the AND is wide enough, this might make a
8089 cheaper constant. */
8091 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8092 && GET_MODE_MASK (GET_MODE (x
)) != mask
8093 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8095 unsigned HOST_WIDE_INT cval
8096 = UINTVAL (XEXP (x
, 1))
8097 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8098 int width
= GET_MODE_PRECISION (GET_MODE (x
));
8101 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8102 number, sign extend it. */
8103 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8104 && (cval
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8105 cval
|= (unsigned HOST_WIDE_INT
) -1 << width
;
8107 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8108 XEXP (x
, 0), GEN_INT (cval
));
8109 if (set_src_cost (y
, optimize_this_for_speed_p
)
8110 < set_src_cost (x
, optimize_this_for_speed_p
))
8120 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8121 low-order bits (as in an alignment operation) and FOO is already
8122 aligned to that boundary, mask C1 to that boundary as well.
8123 This may eliminate that PLUS and, later, the AND. */
8126 unsigned int width
= GET_MODE_PRECISION (mode
);
8127 unsigned HOST_WIDE_INT smask
= mask
;
8129 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8130 number, sign extend it. */
8132 if (width
< HOST_BITS_PER_WIDE_INT
8133 && (smask
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8134 smask
|= (unsigned HOST_WIDE_INT
) (-1) << width
;
8136 if (CONST_INT_P (XEXP (x
, 1))
8137 && exact_log2 (- smask
) >= 0
8138 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8139 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8140 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8141 (INTVAL (XEXP (x
, 1)) & smask
)),
8142 mode
, smask
, next_select
);
8145 /* ... fall through ... */
8148 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8149 most significant bit in MASK since carries from those bits will
8150 affect the bits we are interested in. */
8155 /* If X is (minus C Y) where C's least set bit is larger than any bit
8156 in the mask, then we may replace with (neg Y). */
8157 if (CONST_INT_P (XEXP (x
, 0))
8158 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8159 & -INTVAL (XEXP (x
, 0))))
8162 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8164 return force_to_mode (x
, mode
, mask
, next_select
);
8167 /* Similarly, if C contains every bit in the fuller_mask, then we may
8168 replace with (not Y). */
8169 if (CONST_INT_P (XEXP (x
, 0))
8170 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8172 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8173 XEXP (x
, 1), GET_MODE (x
));
8174 return force_to_mode (x
, mode
, mask
, next_select
);
8182 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8183 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8184 operation which may be a bitfield extraction. Ensure that the
8185 constant we form is not wider than the mode of X. */
8187 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8188 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8189 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8190 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8191 && CONST_INT_P (XEXP (x
, 1))
8192 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8193 + floor_log2 (INTVAL (XEXP (x
, 1))))
8194 < GET_MODE_PRECISION (GET_MODE (x
)))
8195 && (UINTVAL (XEXP (x
, 1))
8196 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8198 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8199 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8200 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8201 XEXP (XEXP (x
, 0), 0), temp
);
8202 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8203 XEXP (XEXP (x
, 0), 1));
8204 return force_to_mode (x
, mode
, mask
, next_select
);
8208 /* For most binary operations, just propagate into the operation and
8209 change the mode if we have an operation of that mode. */
8211 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8212 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8214 /* If we ended up truncating both operands, truncate the result of the
8215 operation instead. */
8216 if (GET_CODE (op0
) == TRUNCATE
8217 && GET_CODE (op1
) == TRUNCATE
)
8219 op0
= XEXP (op0
, 0);
8220 op1
= XEXP (op1
, 0);
8223 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8224 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8226 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8227 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8231 /* For left shifts, do the same, but just for the first operand.
8232 However, we cannot do anything with shifts where we cannot
8233 guarantee that the counts are smaller than the size of the mode
8234 because such a count will have a different meaning in a
8237 if (! (CONST_INT_P (XEXP (x
, 1))
8238 && INTVAL (XEXP (x
, 1)) >= 0
8239 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8240 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8241 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8242 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8245 /* If the shift count is a constant and we can do arithmetic in
8246 the mode of the shift, refine which bits we need. Otherwise, use the
8247 conservative form of the mask. */
8248 if (CONST_INT_P (XEXP (x
, 1))
8249 && INTVAL (XEXP (x
, 1)) >= 0
8250 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8251 && HWI_COMPUTABLE_MODE_P (op_mode
))
8252 mask
>>= INTVAL (XEXP (x
, 1));
8256 op0
= gen_lowpart_or_truncate (op_mode
,
8257 force_to_mode (XEXP (x
, 0), op_mode
,
8258 mask
, next_select
));
8260 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8261 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8265 /* Here we can only do something if the shift count is a constant,
8266 this shift constant is valid for the host, and we can do arithmetic
8269 if (CONST_INT_P (XEXP (x
, 1))
8270 && INTVAL (XEXP (x
, 1)) >= 0
8271 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8272 && HWI_COMPUTABLE_MODE_P (op_mode
))
8274 rtx inner
= XEXP (x
, 0);
8275 unsigned HOST_WIDE_INT inner_mask
;
8277 /* Select the mask of the bits we need for the shift operand. */
8278 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8280 /* We can only change the mode of the shift if we can do arithmetic
8281 in the mode of the shift and INNER_MASK is no wider than the
8282 width of X's mode. */
8283 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8284 op_mode
= GET_MODE (x
);
8286 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8288 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8289 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8292 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8293 shift and AND produces only copies of the sign bit (C2 is one less
8294 than a power of two), we can do this with just a shift. */
8296 if (GET_CODE (x
) == LSHIFTRT
8297 && CONST_INT_P (XEXP (x
, 1))
8298 /* The shift puts one of the sign bit copies in the least significant
8300 && ((INTVAL (XEXP (x
, 1))
8301 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8302 >= GET_MODE_PRECISION (GET_MODE (x
)))
8303 && exact_log2 (mask
+ 1) >= 0
8304 /* Number of bits left after the shift must be more than the mask
8306 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8307 <= GET_MODE_PRECISION (GET_MODE (x
)))
8308 /* Must be more sign bit copies than the mask needs. */
8309 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8310 >= exact_log2 (mask
+ 1)))
8311 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8312 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8313 - exact_log2 (mask
+ 1)));
8318 /* If we are just looking for the sign bit, we don't need this shift at
8319 all, even if it has a variable count. */
8320 if (val_signbit_p (GET_MODE (x
), mask
))
8321 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8323 /* If this is a shift by a constant, get a mask that contains those bits
8324 that are not copies of the sign bit. We then have two cases: If
8325 MASK only includes those bits, this can be a logical shift, which may
8326 allow simplifications. If MASK is a single-bit field not within
8327 those bits, we are requesting a copy of the sign bit and hence can
8328 shift the sign bit to the appropriate location. */
8330 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8331 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8335 /* If the considered data is wider than HOST_WIDE_INT, we can't
8336 represent a mask for all its bits in a single scalar.
8337 But we only care about the lower bits, so calculate these. */
8339 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8341 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8343 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8344 is the number of bits a full-width mask would have set.
8345 We need only shift if these are fewer than nonzero can
8346 hold. If not, we must keep all bits set in nonzero. */
8348 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8349 < HOST_BITS_PER_WIDE_INT
)
8350 nonzero
>>= INTVAL (XEXP (x
, 1))
8351 + HOST_BITS_PER_WIDE_INT
8352 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8356 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8357 nonzero
>>= INTVAL (XEXP (x
, 1));
8360 if ((mask
& ~nonzero
) == 0)
8362 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8363 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8364 if (GET_CODE (x
) != ASHIFTRT
)
8365 return force_to_mode (x
, mode
, mask
, next_select
);
8368 else if ((i
= exact_log2 (mask
)) >= 0)
8370 x
= simplify_shift_const
8371 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8372 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8374 if (GET_CODE (x
) != ASHIFTRT
)
8375 return force_to_mode (x
, mode
, mask
, next_select
);
8379 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8380 even if the shift count isn't a constant. */
8382 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8383 XEXP (x
, 0), XEXP (x
, 1));
8387 /* If this is a zero- or sign-extension operation that just affects bits
8388 we don't care about, remove it. Be sure the call above returned
8389 something that is still a shift. */
8391 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8392 && CONST_INT_P (XEXP (x
, 1))
8393 && INTVAL (XEXP (x
, 1)) >= 0
8394 && (INTVAL (XEXP (x
, 1))
8395 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8396 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8397 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8398 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8405 /* If the shift count is constant and we can do computations
8406 in the mode of X, compute where the bits we care about are.
8407 Otherwise, we can't do anything. Don't change the mode of
8408 the shift or propagate MODE into the shift, though. */
8409 if (CONST_INT_P (XEXP (x
, 1))
8410 && INTVAL (XEXP (x
, 1)) >= 0)
8412 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8413 GET_MODE (x
), GEN_INT (mask
),
8415 if (temp
&& CONST_INT_P (temp
))
8417 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8418 INTVAL (temp
), next_select
));
8423 /* If we just want the low-order bit, the NEG isn't needed since it
8424 won't change the low-order bit. */
8426 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8428 /* We need any bits less significant than the most significant bit in
8429 MASK since carries from those bits will affect the bits we are
8435 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8436 same as the XOR case above. Ensure that the constant we form is not
8437 wider than the mode of X. */
8439 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8440 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8441 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8442 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8443 < GET_MODE_PRECISION (GET_MODE (x
)))
8444 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8446 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8448 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8449 XEXP (XEXP (x
, 0), 0), temp
);
8450 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8451 temp
, XEXP (XEXP (x
, 0), 1));
8453 return force_to_mode (x
, mode
, mask
, next_select
);
8456 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8457 use the full mask inside the NOT. */
8461 op0
= gen_lowpart_or_truncate (op_mode
,
8462 force_to_mode (XEXP (x
, 0), mode
, mask
,
8464 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8465 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8469 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8470 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8471 which is equal to STORE_FLAG_VALUE. */
8472 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8473 && XEXP (x
, 1) == const0_rtx
8474 && GET_MODE (XEXP (x
, 0)) == mode
8475 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8476 && (nonzero_bits (XEXP (x
, 0), mode
)
8477 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8478 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8483 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8484 written in a narrower mode. We play it safe and do not do so. */
8487 gen_lowpart_or_truncate (GET_MODE (x
),
8488 force_to_mode (XEXP (x
, 1), mode
,
8489 mask
, next_select
)));
8491 gen_lowpart_or_truncate (GET_MODE (x
),
8492 force_to_mode (XEXP (x
, 2), mode
,
8493 mask
, next_select
)));
8500 /* Ensure we return a value of the proper mode. */
8501 return gen_lowpart_or_truncate (mode
, x
);
8504 /* Return nonzero if X is an expression that has one of two values depending on
8505 whether some other value is zero or nonzero. In that case, we return the
8506 value that is being tested, *PTRUE is set to the value if the rtx being
8507 returned has a nonzero value, and *PFALSE is set to the other alternative.
8509 If we return zero, we set *PTRUE and *PFALSE to X. */
8512 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8514 enum machine_mode mode
= GET_MODE (x
);
8515 enum rtx_code code
= GET_CODE (x
);
8516 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8517 unsigned HOST_WIDE_INT nz
;
8519 /* If we are comparing a value against zero, we are done. */
8520 if ((code
== NE
|| code
== EQ
)
8521 && XEXP (x
, 1) == const0_rtx
)
8523 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8524 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8528 /* If this is a unary operation whose operand has one of two values, apply
8529 our opcode to compute those values. */
8530 else if (UNARY_P (x
)
8531 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8533 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8534 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8535 GET_MODE (XEXP (x
, 0)));
8539 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8540 make can't possibly match and would suppress other optimizations. */
8541 else if (code
== COMPARE
)
8544 /* If this is a binary operation, see if either side has only one of two
8545 values. If either one does or if both do and they are conditional on
8546 the same value, compute the new true and false values. */
8547 else if (BINARY_P (x
))
8549 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8550 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8552 if ((cond0
!= 0 || cond1
!= 0)
8553 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8555 /* If if_then_else_cond returned zero, then true/false are the
8556 same rtl. We must copy one of them to prevent invalid rtl
8559 true0
= copy_rtx (true0
);
8560 else if (cond1
== 0)
8561 true1
= copy_rtx (true1
);
8563 if (COMPARISON_P (x
))
8565 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8567 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8572 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8573 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8576 return cond0
? cond0
: cond1
;
8579 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8580 operands is zero when the other is nonzero, and vice-versa,
8581 and STORE_FLAG_VALUE is 1 or -1. */
8583 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8584 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8586 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8588 rtx op0
= XEXP (XEXP (x
, 0), 1);
8589 rtx op1
= XEXP (XEXP (x
, 1), 1);
8591 cond0
= XEXP (XEXP (x
, 0), 0);
8592 cond1
= XEXP (XEXP (x
, 1), 0);
8594 if (COMPARISON_P (cond0
)
8595 && COMPARISON_P (cond1
)
8596 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8597 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8598 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8599 || ((swap_condition (GET_CODE (cond0
))
8600 == reversed_comparison_code (cond1
, NULL
))
8601 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8602 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8603 && ! side_effects_p (x
))
8605 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8606 *pfalse
= simplify_gen_binary (MULT
, mode
,
8608 ? simplify_gen_unary (NEG
, mode
,
8616 /* Similarly for MULT, AND and UMIN, except that for these the result
8618 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8619 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8620 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8622 cond0
= XEXP (XEXP (x
, 0), 0);
8623 cond1
= XEXP (XEXP (x
, 1), 0);
8625 if (COMPARISON_P (cond0
)
8626 && COMPARISON_P (cond1
)
8627 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8628 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8629 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8630 || ((swap_condition (GET_CODE (cond0
))
8631 == reversed_comparison_code (cond1
, NULL
))
8632 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8633 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8634 && ! side_effects_p (x
))
8636 *ptrue
= *pfalse
= const0_rtx
;
8642 else if (code
== IF_THEN_ELSE
)
8644 /* If we have IF_THEN_ELSE already, extract the condition and
8645 canonicalize it if it is NE or EQ. */
8646 cond0
= XEXP (x
, 0);
8647 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8648 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8649 return XEXP (cond0
, 0);
8650 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8652 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8653 return XEXP (cond0
, 0);
8659 /* If X is a SUBREG, we can narrow both the true and false values
8660 if the inner expression, if there is a condition. */
8661 else if (code
== SUBREG
8662 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8665 true0
= simplify_gen_subreg (mode
, true0
,
8666 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8667 false0
= simplify_gen_subreg (mode
, false0
,
8668 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8669 if (true0
&& false0
)
8677 /* If X is a constant, this isn't special and will cause confusions
8678 if we treat it as such. Likewise if it is equivalent to a constant. */
8679 else if (CONSTANT_P (x
)
8680 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8683 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8684 will be least confusing to the rest of the compiler. */
8685 else if (mode
== BImode
)
8687 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8691 /* If X is known to be either 0 or -1, those are the true and
8692 false values when testing X. */
8693 else if (x
== constm1_rtx
|| x
== const0_rtx
8694 || (mode
!= VOIDmode
8695 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8697 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8701 /* Likewise for 0 or a single bit. */
8702 else if (HWI_COMPUTABLE_MODE_P (mode
)
8703 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8705 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8709 /* Otherwise fail; show no condition with true and false values the same. */
8710 *ptrue
= *pfalse
= x
;
8714 /* Return the value of expression X given the fact that condition COND
8715 is known to be true when applied to REG as its first operand and VAL
8716 as its second. X is known to not be shared and so can be modified in
8719 We only handle the simplest cases, and specifically those cases that
8720 arise with IF_THEN_ELSE expressions. */
8723 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8725 enum rtx_code code
= GET_CODE (x
);
8730 if (side_effects_p (x
))
8733 /* If either operand of the condition is a floating point value,
8734 then we have to avoid collapsing an EQ comparison. */
8736 && rtx_equal_p (x
, reg
)
8737 && ! FLOAT_MODE_P (GET_MODE (x
))
8738 && ! FLOAT_MODE_P (GET_MODE (val
)))
8741 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8744 /* If X is (abs REG) and we know something about REG's relationship
8745 with zero, we may be able to simplify this. */
8747 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8750 case GE
: case GT
: case EQ
:
8753 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8755 GET_MODE (XEXP (x
, 0)));
8760 /* The only other cases we handle are MIN, MAX, and comparisons if the
8761 operands are the same as REG and VAL. */
8763 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8765 if (rtx_equal_p (XEXP (x
, 0), val
))
8766 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8768 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8770 if (COMPARISON_P (x
))
8772 if (comparison_dominates_p (cond
, code
))
8773 return const_true_rtx
;
8775 code
= reversed_comparison_code (x
, NULL
);
8777 && comparison_dominates_p (cond
, code
))
8782 else if (code
== SMAX
|| code
== SMIN
8783 || code
== UMIN
|| code
== UMAX
)
8785 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8787 /* Do not reverse the condition when it is NE or EQ.
8788 This is because we cannot conclude anything about
8789 the value of 'SMAX (x, y)' when x is not equal to y,
8790 but we can when x equals y. */
8791 if ((code
== SMAX
|| code
== UMAX
)
8792 && ! (cond
== EQ
|| cond
== NE
))
8793 cond
= reverse_condition (cond
);
8798 return unsignedp
? x
: XEXP (x
, 1);
8800 return unsignedp
? x
: XEXP (x
, 0);
8802 return unsignedp
? XEXP (x
, 1) : x
;
8804 return unsignedp
? XEXP (x
, 0) : x
;
8811 else if (code
== SUBREG
)
8813 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8814 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8816 if (SUBREG_REG (x
) != r
)
8818 /* We must simplify subreg here, before we lose track of the
8819 original inner_mode. */
8820 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8821 inner_mode
, SUBREG_BYTE (x
));
8825 SUBST (SUBREG_REG (x
), r
);
8830 /* We don't have to handle SIGN_EXTEND here, because even in the
8831 case of replacing something with a modeless CONST_INT, a
8832 CONST_INT is already (supposed to be) a valid sign extension for
8833 its narrower mode, which implies it's already properly
8834 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8835 story is different. */
8836 else if (code
== ZERO_EXTEND
)
8838 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8839 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8841 if (XEXP (x
, 0) != r
)
8843 /* We must simplify the zero_extend here, before we lose
8844 track of the original inner_mode. */
8845 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8850 SUBST (XEXP (x
, 0), r
);
8856 fmt
= GET_RTX_FORMAT (code
);
8857 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8860 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8861 else if (fmt
[i
] == 'E')
8862 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8863 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8870 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8871 assignment as a field assignment. */
8874 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8876 if (x
== y
|| rtx_equal_p (x
, y
))
8879 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8882 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8883 Note that all SUBREGs of MEM are paradoxical; otherwise they
8884 would have been rewritten. */
8885 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8886 && MEM_P (SUBREG_REG (y
))
8887 && rtx_equal_p (SUBREG_REG (y
),
8888 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8891 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8892 && MEM_P (SUBREG_REG (x
))
8893 && rtx_equal_p (SUBREG_REG (x
),
8894 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8897 /* We used to see if get_last_value of X and Y were the same but that's
8898 not correct. In one direction, we'll cause the assignment to have
8899 the wrong destination and in the case, we'll import a register into this
8900 insn that might have already have been dead. So fail if none of the
8901 above cases are true. */
8905 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8906 Return that assignment if so.
8908 We only handle the most common cases. */
8911 make_field_assignment (rtx x
)
8913 rtx dest
= SET_DEST (x
);
8914 rtx src
= SET_SRC (x
);
8919 unsigned HOST_WIDE_INT len
;
8921 enum machine_mode mode
;
8923 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8924 a clear of a one-bit field. We will have changed it to
8925 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8928 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8929 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8930 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8931 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8933 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8936 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8940 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8941 && subreg_lowpart_p (XEXP (src
, 0))
8942 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8943 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8944 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8945 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8946 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8947 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8949 assign
= make_extraction (VOIDmode
, dest
, 0,
8950 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8953 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8957 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8959 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8960 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8961 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8963 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8966 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8970 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8971 SRC is an AND with all bits of that field set, then we can discard
8973 if (GET_CODE (dest
) == ZERO_EXTRACT
8974 && CONST_INT_P (XEXP (dest
, 1))
8975 && GET_CODE (src
) == AND
8976 && CONST_INT_P (XEXP (src
, 1)))
8978 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8979 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8980 unsigned HOST_WIDE_INT ze_mask
;
8982 if (width
>= HOST_BITS_PER_WIDE_INT
)
8985 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8987 /* Complete overlap. We can remove the source AND. */
8988 if ((and_mask
& ze_mask
) == ze_mask
)
8989 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8991 /* Partial overlap. We can reduce the source AND. */
8992 if ((and_mask
& ze_mask
) != and_mask
)
8994 mode
= GET_MODE (src
);
8995 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8996 gen_int_mode (and_mask
& ze_mask
, mode
));
8997 return gen_rtx_SET (VOIDmode
, dest
, src
);
9001 /* The other case we handle is assignments into a constant-position
9002 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9003 a mask that has all one bits except for a group of zero bits and
9004 OTHER is known to have zeros where C1 has ones, this is such an
9005 assignment. Compute the position and length from C1. Shift OTHER
9006 to the appropriate position, force it to the required mode, and
9007 make the extraction. Check for the AND in both operands. */
9009 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9012 rhs
= expand_compound_operation (XEXP (src
, 0));
9013 lhs
= expand_compound_operation (XEXP (src
, 1));
9015 if (GET_CODE (rhs
) == AND
9016 && CONST_INT_P (XEXP (rhs
, 1))
9017 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9018 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9019 else if (GET_CODE (lhs
) == AND
9020 && CONST_INT_P (XEXP (lhs
, 1))
9021 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9022 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9026 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9027 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9028 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9029 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9032 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9036 /* The mode to use for the source is the mode of the assignment, or of
9037 what is inside a possible STRICT_LOW_PART. */
9038 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9039 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9041 /* Shift OTHER right POS places and make it the source, restricting it
9042 to the proper length and mode. */
9044 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9048 src
= force_to_mode (src
, mode
,
9049 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9050 ? ~(unsigned HOST_WIDE_INT
) 0
9051 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9054 /* If SRC is masked by an AND that does not make a difference in
9055 the value being stored, strip it. */
9056 if (GET_CODE (assign
) == ZERO_EXTRACT
9057 && CONST_INT_P (XEXP (assign
, 1))
9058 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9059 && GET_CODE (src
) == AND
9060 && CONST_INT_P (XEXP (src
, 1))
9061 && UINTVAL (XEXP (src
, 1))
9062 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9063 src
= XEXP (src
, 0);
9065 return gen_rtx_SET (VOIDmode
, assign
, src
);
9068 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9072 apply_distributive_law (rtx x
)
9074 enum rtx_code code
= GET_CODE (x
);
9075 enum rtx_code inner_code
;
9076 rtx lhs
, rhs
, other
;
9079 /* Distributivity is not true for floating point as it can change the
9080 value. So we don't do it unless -funsafe-math-optimizations. */
9081 if (FLOAT_MODE_P (GET_MODE (x
))
9082 && ! flag_unsafe_math_optimizations
)
9085 /* The outer operation can only be one of the following: */
9086 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9087 && code
!= PLUS
&& code
!= MINUS
)
9093 /* If either operand is a primitive we can't do anything, so get out
9095 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9098 lhs
= expand_compound_operation (lhs
);
9099 rhs
= expand_compound_operation (rhs
);
9100 inner_code
= GET_CODE (lhs
);
9101 if (inner_code
!= GET_CODE (rhs
))
9104 /* See if the inner and outer operations distribute. */
9111 /* These all distribute except over PLUS. */
9112 if (code
== PLUS
|| code
== MINUS
)
9117 if (code
!= PLUS
&& code
!= MINUS
)
9122 /* This is also a multiply, so it distributes over everything. */
9125 /* This used to handle SUBREG, but this turned out to be counter-
9126 productive, since (subreg (op ...)) usually is not handled by
9127 insn patterns, and this "optimization" therefore transformed
9128 recognizable patterns into unrecognizable ones. Therefore the
9129 SUBREG case was removed from here.
9131 It is possible that distributing SUBREG over arithmetic operations
9132 leads to an intermediate result than can then be optimized further,
9133 e.g. by moving the outer SUBREG to the other side of a SET as done
9134 in simplify_set. This seems to have been the original intent of
9135 handling SUBREGs here.
9137 However, with current GCC this does not appear to actually happen,
9138 at least on major platforms. If some case is found where removing
9139 the SUBREG case here prevents follow-on optimizations, distributing
9140 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9146 /* Set LHS and RHS to the inner operands (A and B in the example
9147 above) and set OTHER to the common operand (C in the example).
9148 There is only one way to do this unless the inner operation is
9150 if (COMMUTATIVE_ARITH_P (lhs
)
9151 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9152 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9153 else if (COMMUTATIVE_ARITH_P (lhs
)
9154 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9155 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9156 else if (COMMUTATIVE_ARITH_P (lhs
)
9157 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9158 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9159 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9160 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9164 /* Form the new inner operation, seeing if it simplifies first. */
9165 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9167 /* There is one exception to the general way of distributing:
9168 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9169 if (code
== XOR
&& inner_code
== IOR
)
9172 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9175 /* We may be able to continuing distributing the result, so call
9176 ourselves recursively on the inner operation before forming the
9177 outer operation, which we return. */
9178 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9179 apply_distributive_law (tem
), other
);
9182 /* See if X is of the form (* (+ A B) C), and if so convert to
9183 (+ (* A C) (* B C)) and try to simplify.
9185 Most of the time, this results in no change. However, if some of
9186 the operands are the same or inverses of each other, simplifications
9189 For example, (and (ior A B) (not B)) can occur as the result of
9190 expanding a bit field assignment. When we apply the distributive
9191 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9192 which then simplifies to (and (A (not B))).
9194 Note that no checks happen on the validity of applying the inverse
9195 distributive law. This is pointless since we can do it in the
9196 few places where this routine is called.
9198 N is the index of the term that is decomposed (the arithmetic operation,
9199 i.e. (+ A B) in the first example above). !N is the index of the term that
9200 is distributed, i.e. of C in the first example above. */
9202 distribute_and_simplify_rtx (rtx x
, int n
)
9204 enum machine_mode mode
;
9205 enum rtx_code outer_code
, inner_code
;
9206 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9208 /* Distributivity is not true for floating point as it can change the
9209 value. So we don't do it unless -funsafe-math-optimizations. */
9210 if (FLOAT_MODE_P (GET_MODE (x
))
9211 && ! flag_unsafe_math_optimizations
)
9214 decomposed
= XEXP (x
, n
);
9215 if (!ARITHMETIC_P (decomposed
))
9218 mode
= GET_MODE (x
);
9219 outer_code
= GET_CODE (x
);
9220 distributed
= XEXP (x
, !n
);
9222 inner_code
= GET_CODE (decomposed
);
9223 inner_op0
= XEXP (decomposed
, 0);
9224 inner_op1
= XEXP (decomposed
, 1);
9226 /* Special case (and (xor B C) (not A)), which is equivalent to
9227 (xor (ior A B) (ior A C)) */
9228 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9230 distributed
= XEXP (distributed
, 0);
9236 /* Distribute the second term. */
9237 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9238 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9242 /* Distribute the first term. */
9243 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9244 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9247 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9249 if (GET_CODE (tmp
) != outer_code
9250 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9251 < set_src_cost (x
, optimize_this_for_speed_p
)))
9257 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9258 in MODE. Return an equivalent form, if different from (and VAROP
9259 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9262 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9263 unsigned HOST_WIDE_INT constop
)
9265 unsigned HOST_WIDE_INT nonzero
;
9266 unsigned HOST_WIDE_INT orig_constop
;
9271 orig_constop
= constop
;
9272 if (GET_CODE (varop
) == CLOBBER
)
9275 /* Simplify VAROP knowing that we will be only looking at some of the
9278 Note by passing in CONSTOP, we guarantee that the bits not set in
9279 CONSTOP are not significant and will never be examined. We must
9280 ensure that is the case by explicitly masking out those bits
9281 before returning. */
9282 varop
= force_to_mode (varop
, mode
, constop
, 0);
9284 /* If VAROP is a CLOBBER, we will fail so return it. */
9285 if (GET_CODE (varop
) == CLOBBER
)
9288 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9289 to VAROP and return the new constant. */
9290 if (CONST_INT_P (varop
))
9291 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9293 /* See what bits may be nonzero in VAROP. Unlike the general case of
9294 a call to nonzero_bits, here we don't care about bits outside
9297 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9299 /* Turn off all bits in the constant that are known to already be zero.
9300 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9301 which is tested below. */
9305 /* If we don't have any bits left, return zero. */
9309 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9310 a power of two, we can replace this with an ASHIFT. */
9311 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9312 && (i
= exact_log2 (constop
)) >= 0)
9313 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9315 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9316 or XOR, then try to apply the distributive law. This may eliminate
9317 operations if either branch can be simplified because of the AND.
9318 It may also make some cases more complex, but those cases probably
9319 won't match a pattern either with or without this. */
9321 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9325 apply_distributive_law
9326 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9327 simplify_and_const_int (NULL_RTX
,
9331 simplify_and_const_int (NULL_RTX
,
9336 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9337 the AND and see if one of the operands simplifies to zero. If so, we
9338 may eliminate it. */
9340 if (GET_CODE (varop
) == PLUS
9341 && exact_log2 (constop
+ 1) >= 0)
9345 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9346 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9347 if (o0
== const0_rtx
)
9349 if (o1
== const0_rtx
)
9353 /* Make a SUBREG if necessary. If we can't make it, fail. */
9354 varop
= gen_lowpart (mode
, varop
);
9355 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9358 /* If we are only masking insignificant bits, return VAROP. */
9359 if (constop
== nonzero
)
9362 if (varop
== orig_varop
&& constop
== orig_constop
)
9365 /* Otherwise, return an AND. */
9366 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9370 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9373 Return an equivalent form, if different from X. Otherwise, return X. If
9374 X is zero, we are to always construct the equivalent form. */
9377 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9378 unsigned HOST_WIDE_INT constop
)
9380 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9385 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9386 gen_int_mode (constop
, mode
));
9387 if (GET_MODE (x
) != mode
)
9388 x
= gen_lowpart (mode
, x
);
9392 /* Given a REG, X, compute which bits in X can be nonzero.
9393 We don't care about bits outside of those defined in MODE.
9395 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9396 a shift, AND, or zero_extract, we can do better. */
9399 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9400 const_rtx known_x ATTRIBUTE_UNUSED
,
9401 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9402 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9403 unsigned HOST_WIDE_INT
*nonzero
)
9408 /* If X is a register whose nonzero bits value is current, use it.
9409 Otherwise, if X is a register whose value we can find, use that
9410 value. Otherwise, use the previously-computed global nonzero bits
9411 for this register. */
9413 rsp
= &VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9414 if (rsp
->last_set_value
!= 0
9415 && (rsp
->last_set_mode
== mode
9416 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9417 && GET_MODE_CLASS (mode
) == MODE_INT
))
9418 && ((rsp
->last_set_label
>= label_tick_ebb_start
9419 && rsp
->last_set_label
< label_tick
)
9420 || (rsp
->last_set_label
== label_tick
9421 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9422 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9423 && REG_N_SETS (REGNO (x
)) == 1
9425 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9427 *nonzero
&= rsp
->last_set_nonzero_bits
;
9431 tem
= get_last_value (x
);
9435 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9436 /* If X is narrower than MODE and TEM is a non-negative
9437 constant that would appear negative in the mode of X,
9438 sign-extend it for use in reg_nonzero_bits because some
9439 machines (maybe most) will actually do the sign-extension
9440 and this is the conservative approach.
9442 ??? For 2.5, try to tighten up the MD files in this regard
9443 instead of this kludge. */
9445 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9446 && CONST_INT_P (tem
)
9448 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9449 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9453 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9455 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9457 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9458 /* We don't know anything about the upper bits. */
9459 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9466 /* Return the number of bits at the high-order end of X that are known to
9467 be equal to the sign bit. X will be used in mode MODE; if MODE is
9468 VOIDmode, X will be used in its own mode. The returned value will always
9469 be between 1 and the number of bits in MODE. */
9472 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9473 const_rtx known_x ATTRIBUTE_UNUSED
,
9474 enum machine_mode known_mode
9476 unsigned int known_ret ATTRIBUTE_UNUSED
,
9477 unsigned int *result
)
9482 rsp
= &VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9483 if (rsp
->last_set_value
!= 0
9484 && rsp
->last_set_mode
== mode
9485 && ((rsp
->last_set_label
>= label_tick_ebb_start
9486 && rsp
->last_set_label
< label_tick
)
9487 || (rsp
->last_set_label
== label_tick
9488 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9489 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9490 && REG_N_SETS (REGNO (x
)) == 1
9492 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9494 *result
= rsp
->last_set_sign_bit_copies
;
9498 tem
= get_last_value (x
);
9502 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9503 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9504 *result
= rsp
->sign_bit_copies
;
9509 /* Return the number of "extended" bits there are in X, when interpreted
9510 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9511 unsigned quantities, this is the number of high-order zero bits.
9512 For signed quantities, this is the number of copies of the sign bit
9513 minus 1. In both case, this function returns the number of "spare"
9514 bits. For example, if two quantities for which this function returns
9515 at least 1 are added, the addition is known not to overflow.
9517 This function will always return 0 unless called during combine, which
9518 implies that it must be called from a define_split. */
9521 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9523 if (nonzero_sign_valid
== 0)
9527 ? (HWI_COMPUTABLE_MODE_P (mode
)
9528 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9529 - floor_log2 (nonzero_bits (x
, mode
)))
9531 : num_sign_bit_copies (x
, mode
) - 1);
9534 /* This function is called from `simplify_shift_const' to merge two
9535 outer operations. Specifically, we have already found that we need
9536 to perform operation *POP0 with constant *PCONST0 at the outermost
9537 position. We would now like to also perform OP1 with constant CONST1
9538 (with *POP0 being done last).
9540 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9541 the resulting operation. *PCOMP_P is set to 1 if we would need to
9542 complement the innermost operand, otherwise it is unchanged.
9544 MODE is the mode in which the operation will be done. No bits outside
9545 the width of this mode matter. It is assumed that the width of this mode
9546 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9548 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9549 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9550 result is simply *PCONST0.
9552 If the resulting operation cannot be expressed as one operation, we
9553 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9556 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9558 enum rtx_code op0
= *pop0
;
9559 HOST_WIDE_INT const0
= *pconst0
;
9561 const0
&= GET_MODE_MASK (mode
);
9562 const1
&= GET_MODE_MASK (mode
);
9564 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9568 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9571 if (op1
== UNKNOWN
|| op0
== SET
)
9574 else if (op0
== UNKNOWN
)
9575 op0
= op1
, const0
= const1
;
9577 else if (op0
== op1
)
9601 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9602 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9605 /* If the two constants aren't the same, we can't do anything. The
9606 remaining six cases can all be done. */
9607 else if (const0
!= const1
)
9615 /* (a & b) | b == b */
9617 else /* op1 == XOR */
9618 /* (a ^ b) | b == a | b */
9624 /* (a & b) ^ b == (~a) & b */
9625 op0
= AND
, *pcomp_p
= 1;
9626 else /* op1 == IOR */
9627 /* (a | b) ^ b == a & ~b */
9628 op0
= AND
, const0
= ~const0
;
9633 /* (a | b) & b == b */
9635 else /* op1 == XOR */
9636 /* (a ^ b) & b) == (~a) & b */
9643 /* Check for NO-OP cases. */
9644 const0
&= GET_MODE_MASK (mode
);
9646 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9648 else if (const0
== 0 && op0
== AND
)
9650 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9656 /* ??? Slightly redundant with the above mask, but not entirely.
9657 Moving this above means we'd have to sign-extend the mode mask
9658 for the final test. */
9659 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9660 *pconst0
= trunc_int_for_mode (const0
, mode
);
9665 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9666 the shift in. The original shift operation CODE is performed on OP in
9667 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9668 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9669 result of the shift is subject to operation OUTER_CODE with operand
9672 static enum machine_mode
9673 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9674 enum machine_mode orig_mode
, enum machine_mode mode
,
9675 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9677 if (orig_mode
== mode
)
9679 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9681 /* In general we can't perform in wider mode for right shift and rotate. */
9685 /* We can still widen if the bits brought in from the left are identical
9686 to the sign bit of ORIG_MODE. */
9687 if (num_sign_bit_copies (op
, mode
)
9688 > (unsigned) (GET_MODE_PRECISION (mode
)
9689 - GET_MODE_PRECISION (orig_mode
)))
9694 /* Similarly here but with zero bits. */
9695 if (HWI_COMPUTABLE_MODE_P (mode
)
9696 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9699 /* We can also widen if the bits brought in will be masked off. This
9700 operation is performed in ORIG_MODE. */
9701 if (outer_code
== AND
)
9703 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9706 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9722 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9723 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9724 if we cannot simplify it. Otherwise, return a simplified value.
9726 The shift is normally computed in the widest mode we find in VAROP, as
9727 long as it isn't a different number of words than RESULT_MODE. Exceptions
9728 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9731 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9732 rtx varop
, int orig_count
)
9734 enum rtx_code orig_code
= code
;
9735 rtx orig_varop
= varop
;
9737 enum machine_mode mode
= result_mode
;
9738 enum machine_mode shift_mode
, tmode
;
9739 unsigned int mode_words
9740 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9741 /* We form (outer_op (code varop count) (outer_const)). */
9742 enum rtx_code outer_op
= UNKNOWN
;
9743 HOST_WIDE_INT outer_const
= 0;
9744 int complement_p
= 0;
9747 /* Make sure and truncate the "natural" shift on the way in. We don't
9748 want to do this inside the loop as it makes it more difficult to
9750 if (SHIFT_COUNT_TRUNCATED
)
9751 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9753 /* If we were given an invalid count, don't do anything except exactly
9754 what was requested. */
9756 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9761 /* Unless one of the branches of the `if' in this loop does a `continue',
9762 we will `break' the loop after the `if'. */
9766 /* If we have an operand of (clobber (const_int 0)), fail. */
9767 if (GET_CODE (varop
) == CLOBBER
)
9770 /* Convert ROTATERT to ROTATE. */
9771 if (code
== ROTATERT
)
9773 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9775 if (VECTOR_MODE_P (result_mode
))
9776 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9778 count
= bitsize
- count
;
9781 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9782 mode
, outer_op
, outer_const
);
9784 /* Handle cases where the count is greater than the size of the mode
9785 minus 1. For ASHIFT, use the size minus one as the count (this can
9786 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9787 take the count modulo the size. For other shifts, the result is
9790 Since these shifts are being produced by the compiler by combining
9791 multiple operations, each of which are defined, we know what the
9792 result is supposed to be. */
9794 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9796 if (code
== ASHIFTRT
)
9797 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9798 else if (code
== ROTATE
|| code
== ROTATERT
)
9799 count
%= GET_MODE_PRECISION (shift_mode
);
9802 /* We can't simply return zero because there may be an
9810 /* If we discovered we had to complement VAROP, leave. Making a NOT
9811 here would cause an infinite loop. */
9815 /* An arithmetic right shift of a quantity known to be -1 or 0
9817 if (code
== ASHIFTRT
9818 && (num_sign_bit_copies (varop
, shift_mode
)
9819 == GET_MODE_PRECISION (shift_mode
)))
9825 /* If we are doing an arithmetic right shift and discarding all but
9826 the sign bit copies, this is equivalent to doing a shift by the
9827 bitsize minus one. Convert it into that shift because it will often
9828 allow other simplifications. */
9830 if (code
== ASHIFTRT
9831 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9832 >= GET_MODE_PRECISION (shift_mode
)))
9833 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9835 /* We simplify the tests below and elsewhere by converting
9836 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9837 `make_compound_operation' will convert it to an ASHIFTRT for
9838 those machines (such as VAX) that don't have an LSHIFTRT. */
9839 if (code
== ASHIFTRT
9840 && val_signbit_known_clear_p (shift_mode
,
9841 nonzero_bits (varop
, shift_mode
)))
9844 if (((code
== LSHIFTRT
9845 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9846 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9848 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9849 && !((nonzero_bits (varop
, shift_mode
) << count
)
9850 & GET_MODE_MASK (shift_mode
))))
9851 && !side_effects_p (varop
))
9854 switch (GET_CODE (varop
))
9860 new_rtx
= expand_compound_operation (varop
);
9861 if (new_rtx
!= varop
)
9869 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9870 minus the width of a smaller mode, we can do this with a
9871 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9872 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9873 && ! mode_dependent_address_p (XEXP (varop
, 0),
9874 MEM_ADDR_SPACE (varop
))
9875 && ! MEM_VOLATILE_P (varop
)
9876 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9877 MODE_INT
, 1)) != BLKmode
)
9879 new_rtx
= adjust_address_nv (varop
, tmode
,
9880 BYTES_BIG_ENDIAN
? 0
9881 : count
/ BITS_PER_UNIT
);
9883 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9884 : ZERO_EXTEND
, mode
, new_rtx
);
9891 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9892 the same number of words as what we've seen so far. Then store
9893 the widest mode in MODE. */
9894 if (subreg_lowpart_p (varop
)
9895 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9896 > GET_MODE_SIZE (GET_MODE (varop
)))
9897 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9898 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9900 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9901 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9903 varop
= SUBREG_REG (varop
);
9904 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9905 mode
= GET_MODE (varop
);
9911 /* Some machines use MULT instead of ASHIFT because MULT
9912 is cheaper. But it is still better on those machines to
9913 merge two shifts into one. */
9914 if (CONST_INT_P (XEXP (varop
, 1))
9915 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9918 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9920 GEN_INT (exact_log2 (
9921 UINTVAL (XEXP (varop
, 1)))));
9927 /* Similar, for when divides are cheaper. */
9928 if (CONST_INT_P (XEXP (varop
, 1))
9929 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9932 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9934 GEN_INT (exact_log2 (
9935 UINTVAL (XEXP (varop
, 1)))));
9941 /* If we are extracting just the sign bit of an arithmetic
9942 right shift, that shift is not needed. However, the sign
9943 bit of a wider mode may be different from what would be
9944 interpreted as the sign bit in a narrower mode, so, if
9945 the result is narrower, don't discard the shift. */
9946 if (code
== LSHIFTRT
9947 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9948 && (GET_MODE_BITSIZE (result_mode
)
9949 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9951 varop
= XEXP (varop
, 0);
9955 /* ... fall through ... */
9960 /* Here we have two nested shifts. The result is usually the
9961 AND of a new shift with a mask. We compute the result below. */
9962 if (CONST_INT_P (XEXP (varop
, 1))
9963 && INTVAL (XEXP (varop
, 1)) >= 0
9964 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
9965 && HWI_COMPUTABLE_MODE_P (result_mode
)
9966 && HWI_COMPUTABLE_MODE_P (mode
)
9967 && !VECTOR_MODE_P (result_mode
))
9969 enum rtx_code first_code
= GET_CODE (varop
);
9970 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9971 unsigned HOST_WIDE_INT mask
;
9974 /* We have one common special case. We can't do any merging if
9975 the inner code is an ASHIFTRT of a smaller mode. However, if
9976 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9977 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9978 we can convert it to
9979 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
9980 This simplifies certain SIGN_EXTEND operations. */
9981 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9982 && count
== (GET_MODE_PRECISION (result_mode
)
9983 - GET_MODE_PRECISION (GET_MODE (varop
))))
9985 /* C3 has the low-order C1 bits zero. */
9987 mask
= GET_MODE_MASK (mode
)
9988 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
9990 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9991 XEXP (varop
, 0), mask
);
9992 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9994 count
= first_count
;
9999 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10000 than C1 high-order bits equal to the sign bit, we can convert
10001 this to either an ASHIFT or an ASHIFTRT depending on the
10004 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10006 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10007 && GET_MODE (varop
) == shift_mode
10008 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10011 varop
= XEXP (varop
, 0);
10012 count
-= first_count
;
10022 /* There are some cases we can't do. If CODE is ASHIFTRT,
10023 we can only do this if FIRST_CODE is also ASHIFTRT.
10025 We can't do the case when CODE is ROTATE and FIRST_CODE is
10028 If the mode of this shift is not the mode of the outer shift,
10029 we can't do this if either shift is a right shift or ROTATE.
10031 Finally, we can't do any of these if the mode is too wide
10032 unless the codes are the same.
10034 Handle the case where the shift codes are the same
10037 if (code
== first_code
)
10039 if (GET_MODE (varop
) != result_mode
10040 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10041 || code
== ROTATE
))
10044 count
+= first_count
;
10045 varop
= XEXP (varop
, 0);
10049 if (code
== ASHIFTRT
10050 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10051 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10052 || (GET_MODE (varop
) != result_mode
10053 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10054 || first_code
== ROTATE
10055 || code
== ROTATE
)))
10058 /* To compute the mask to apply after the shift, shift the
10059 nonzero bits of the inner shift the same way the
10060 outer shift will. */
10062 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10065 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10068 /* Give up if we can't compute an outer operation to use. */
10070 || !CONST_INT_P (mask_rtx
)
10071 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10073 result_mode
, &complement_p
))
10076 /* If the shifts are in the same direction, we add the
10077 counts. Otherwise, we subtract them. */
10078 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10079 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10080 count
+= first_count
;
10082 count
-= first_count
;
10084 /* If COUNT is positive, the new shift is usually CODE,
10085 except for the two exceptions below, in which case it is
10086 FIRST_CODE. If the count is negative, FIRST_CODE should
10089 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10090 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10092 else if (count
< 0)
10093 code
= first_code
, count
= -count
;
10095 varop
= XEXP (varop
, 0);
10099 /* If we have (A << B << C) for any shift, we can convert this to
10100 (A << C << B). This wins if A is a constant. Only try this if
10101 B is not a constant. */
10103 else if (GET_CODE (varop
) == code
10104 && CONST_INT_P (XEXP (varop
, 0))
10105 && !CONST_INT_P (XEXP (varop
, 1)))
10107 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10110 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10117 if (VECTOR_MODE_P (mode
))
10120 /* Make this fit the case below. */
10121 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10127 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10128 with C the size of VAROP - 1 and the shift is logical if
10129 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10130 we have an (le X 0) operation. If we have an arithmetic shift
10131 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10132 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10134 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10135 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10136 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10137 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10138 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10139 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10142 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10145 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10146 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10151 /* If we have (shift (logical)), move the logical to the outside
10152 to allow it to possibly combine with another logical and the
10153 shift to combine with another shift. This also canonicalizes to
10154 what a ZERO_EXTRACT looks like. Also, some machines have
10155 (and (shift)) insns. */
10157 if (CONST_INT_P (XEXP (varop
, 1))
10158 /* We can't do this if we have (ashiftrt (xor)) and the
10159 constant has its sign bit set in shift_mode. */
10160 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10161 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10163 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10165 GEN_INT (count
))) != 0
10166 && CONST_INT_P (new_rtx
)
10167 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10168 INTVAL (new_rtx
), result_mode
, &complement_p
))
10170 varop
= XEXP (varop
, 0);
10174 /* If we can't do that, try to simplify the shift in each arm of the
10175 logical expression, make a new logical expression, and apply
10176 the inverse distributive law. This also can't be done
10177 for some (ashiftrt (xor)). */
10178 if (CONST_INT_P (XEXP (varop
, 1))
10179 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10180 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10183 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10184 XEXP (varop
, 0), count
);
10185 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10186 XEXP (varop
, 1), count
);
10188 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10190 varop
= apply_distributive_law (varop
);
10198 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10199 says that the sign bit can be tested, FOO has mode MODE, C is
10200 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10201 that may be nonzero. */
10202 if (code
== LSHIFTRT
10203 && XEXP (varop
, 1) == const0_rtx
10204 && GET_MODE (XEXP (varop
, 0)) == result_mode
10205 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10206 && HWI_COMPUTABLE_MODE_P (result_mode
)
10207 && STORE_FLAG_VALUE
== -1
10208 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10209 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10212 varop
= XEXP (varop
, 0);
10219 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10220 than the number of bits in the mode is equivalent to A. */
10221 if (code
== LSHIFTRT
10222 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10223 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10225 varop
= XEXP (varop
, 0);
10230 /* NEG commutes with ASHIFT since it is multiplication. Move the
10231 NEG outside to allow shifts to combine. */
10233 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10236 varop
= XEXP (varop
, 0);
10242 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10243 is one less than the number of bits in the mode is
10244 equivalent to (xor A 1). */
10245 if (code
== LSHIFTRT
10246 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10247 && XEXP (varop
, 1) == constm1_rtx
10248 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10249 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10253 varop
= XEXP (varop
, 0);
10257 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10258 that might be nonzero in BAR are those being shifted out and those
10259 bits are known zero in FOO, we can replace the PLUS with FOO.
10260 Similarly in the other operand order. This code occurs when
10261 we are computing the size of a variable-size array. */
10263 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10264 && count
< HOST_BITS_PER_WIDE_INT
10265 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10266 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10267 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10269 varop
= XEXP (varop
, 0);
10272 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10273 && count
< HOST_BITS_PER_WIDE_INT
10274 && HWI_COMPUTABLE_MODE_P (result_mode
)
10275 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10277 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10278 & nonzero_bits (XEXP (varop
, 1),
10281 varop
= XEXP (varop
, 1);
10285 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10287 && CONST_INT_P (XEXP (varop
, 1))
10288 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10290 GEN_INT (count
))) != 0
10291 && CONST_INT_P (new_rtx
)
10292 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10293 INTVAL (new_rtx
), result_mode
, &complement_p
))
10295 varop
= XEXP (varop
, 0);
10299 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10300 signbit', and attempt to change the PLUS to an XOR and move it to
10301 the outer operation as is done above in the AND/IOR/XOR case
10302 leg for shift(logical). See details in logical handling above
10303 for reasoning in doing so. */
10304 if (code
== LSHIFTRT
10305 && CONST_INT_P (XEXP (varop
, 1))
10306 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10307 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10309 GEN_INT (count
))) != 0
10310 && CONST_INT_P (new_rtx
)
10311 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10312 INTVAL (new_rtx
), result_mode
, &complement_p
))
10314 varop
= XEXP (varop
, 0);
10321 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10322 with C the size of VAROP - 1 and the shift is logical if
10323 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10324 we have a (gt X 0) operation. If the shift is arithmetic with
10325 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10326 we have a (neg (gt X 0)) operation. */
10328 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10329 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10330 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10331 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10332 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10333 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10334 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10337 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10340 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10341 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10348 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10349 if the truncate does not affect the value. */
10350 if (code
== LSHIFTRT
10351 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10352 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10353 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10354 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10355 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10357 rtx varop_inner
= XEXP (varop
, 0);
10360 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10361 XEXP (varop_inner
, 0),
10363 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10364 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10377 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10378 outer_op
, outer_const
);
10380 /* We have now finished analyzing the shift. The result should be
10381 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10382 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10383 to the result of the shift. OUTER_CONST is the relevant constant,
10384 but we must turn off all bits turned off in the shift. */
10386 if (outer_op
== UNKNOWN
10387 && orig_code
== code
&& orig_count
== count
10388 && varop
== orig_varop
10389 && shift_mode
== GET_MODE (varop
))
10392 /* Make a SUBREG if necessary. If we can't make it, fail. */
10393 varop
= gen_lowpart (shift_mode
, varop
);
10394 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10397 /* If we have an outer operation and we just made a shift, it is
10398 possible that we could have simplified the shift were it not
10399 for the outer operation. So try to do the simplification
10402 if (outer_op
!= UNKNOWN
)
10403 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10408 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10410 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10411 turn off all the bits that the shift would have turned off. */
10412 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10413 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10414 GET_MODE_MASK (result_mode
) >> orig_count
);
10416 /* Do the remainder of the processing in RESULT_MODE. */
10417 x
= gen_lowpart_or_truncate (result_mode
, x
);
10419 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10422 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10424 if (outer_op
!= UNKNOWN
)
10426 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10427 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10428 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10430 if (outer_op
== AND
)
10431 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10432 else if (outer_op
== SET
)
10434 /* This means that we have determined that the result is
10435 equivalent to a constant. This should be rare. */
10436 if (!side_effects_p (x
))
10437 x
= GEN_INT (outer_const
);
10439 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10440 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10442 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10443 GEN_INT (outer_const
));
10449 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10450 The result of the shift is RESULT_MODE. If we cannot simplify it,
10451 return X or, if it is NULL, synthesize the expression with
10452 simplify_gen_binary. Otherwise, return a simplified value.
10454 The shift is normally computed in the widest mode we find in VAROP, as
10455 long as it isn't a different number of words than RESULT_MODE. Exceptions
10456 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10459 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10460 rtx varop
, int count
)
10462 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10467 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10468 if (GET_MODE (x
) != result_mode
)
10469 x
= gen_lowpart (result_mode
, x
);
10474 /* Like recog, but we receive the address of a pointer to a new pattern.
10475 We try to match the rtx that the pointer points to.
10476 If that fails, we may try to modify or replace the pattern,
10477 storing the replacement into the same pointer object.
10479 Modifications include deletion or addition of CLOBBERs.
10481 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10482 the CLOBBERs are placed.
10484 The value is the final insn code from the pattern ultimately matched,
10488 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10490 rtx pat
= *pnewpat
;
10491 rtx pat_without_clobbers
;
10492 int insn_code_number
;
10493 int num_clobbers_to_add
= 0;
10495 rtx notes
= NULL_RTX
;
10496 rtx old_notes
, old_pat
;
10499 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10500 we use to indicate that something didn't match. If we find such a
10501 thing, force rejection. */
10502 if (GET_CODE (pat
) == PARALLEL
)
10503 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10504 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10505 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10508 old_pat
= PATTERN (insn
);
10509 old_notes
= REG_NOTES (insn
);
10510 PATTERN (insn
) = pat
;
10511 REG_NOTES (insn
) = NULL_RTX
;
10513 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10514 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10516 if (insn_code_number
< 0)
10517 fputs ("Failed to match this instruction:\n", dump_file
);
10519 fputs ("Successfully matched this instruction:\n", dump_file
);
10520 print_rtl_single (dump_file
, pat
);
10523 /* If it isn't, there is the possibility that we previously had an insn
10524 that clobbered some register as a side effect, but the combined
10525 insn doesn't need to do that. So try once more without the clobbers
10526 unless this represents an ASM insn. */
10528 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10529 && GET_CODE (pat
) == PARALLEL
)
10533 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10534 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10537 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10541 SUBST_INT (XVECLEN (pat
, 0), pos
);
10544 pat
= XVECEXP (pat
, 0, 0);
10546 PATTERN (insn
) = pat
;
10547 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10548 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10550 if (insn_code_number
< 0)
10551 fputs ("Failed to match this instruction:\n", dump_file
);
10553 fputs ("Successfully matched this instruction:\n", dump_file
);
10554 print_rtl_single (dump_file
, pat
);
10558 pat_without_clobbers
= pat
;
10560 PATTERN (insn
) = old_pat
;
10561 REG_NOTES (insn
) = old_notes
;
10563 /* Recognize all noop sets, these will be killed by followup pass. */
10564 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10565 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10567 /* If we had any clobbers to add, make a new pattern than contains
10568 them. Then check to make sure that all of them are dead. */
10569 if (num_clobbers_to_add
)
10571 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10572 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10573 ? (XVECLEN (pat
, 0)
10574 + num_clobbers_to_add
)
10575 : num_clobbers_to_add
+ 1));
10577 if (GET_CODE (pat
) == PARALLEL
)
10578 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10579 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10581 XVECEXP (newpat
, 0, 0) = pat
;
10583 add_clobbers (newpat
, insn_code_number
);
10585 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10586 i
< XVECLEN (newpat
, 0); i
++)
10588 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10589 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10591 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10593 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10594 notes
= alloc_reg_note (REG_UNUSED
,
10595 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10601 if (insn_code_number
>= 0
10602 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10604 old_pat
= PATTERN (insn
);
10605 old_notes
= REG_NOTES (insn
);
10606 old_icode
= INSN_CODE (insn
);
10607 PATTERN (insn
) = pat
;
10608 REG_NOTES (insn
) = notes
;
10610 /* Allow targets to reject combined insn. */
10611 if (!targetm
.legitimate_combined_insn (insn
))
10613 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10614 fputs ("Instruction not appropriate for target.",
10617 /* Callers expect recog_for_combine to strip
10618 clobbers from the pattern on failure. */
10619 pat
= pat_without_clobbers
;
10622 insn_code_number
= -1;
10625 PATTERN (insn
) = old_pat
;
10626 REG_NOTES (insn
) = old_notes
;
10627 INSN_CODE (insn
) = old_icode
;
10633 return insn_code_number
;
10636 /* Like gen_lowpart_general but for use by combine. In combine it
10637 is not possible to create any new pseudoregs. However, it is
10638 safe to create invalid memory addresses, because combine will
10639 try to recognize them and all they will do is make the combine
10642 If for some reason this cannot do its job, an rtx
10643 (clobber (const_int 0)) is returned.
10644 An insn containing that will not be recognized. */
10647 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10649 enum machine_mode imode
= GET_MODE (x
);
10650 unsigned int osize
= GET_MODE_SIZE (omode
);
10651 unsigned int isize
= GET_MODE_SIZE (imode
);
10654 if (omode
== imode
)
10657 /* We can only support MODE being wider than a word if X is a
10658 constant integer or has a mode the same size. */
10659 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10660 && ! ((CONST_INT_P (x
) || CONST_DOUBLE_AS_INT_P (x
))
10661 || isize
== osize
))
10664 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10665 won't know what to do. So we will strip off the SUBREG here and
10666 process normally. */
10667 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10669 x
= SUBREG_REG (x
);
10671 /* For use in case we fall down into the address adjustments
10672 further below, we need to adjust the known mode and size of
10673 x; imode and isize, since we just adjusted x. */
10674 imode
= GET_MODE (x
);
10676 if (imode
== omode
)
10679 isize
= GET_MODE_SIZE (imode
);
10682 result
= gen_lowpart_common (omode
, x
);
10691 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10693 if (MEM_VOLATILE_P (x
)
10694 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10697 /* If we want to refer to something bigger than the original memref,
10698 generate a paradoxical subreg instead. That will force a reload
10699 of the original memref X. */
10701 return gen_rtx_SUBREG (omode
, x
, 0);
10703 if (WORDS_BIG_ENDIAN
)
10704 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10706 /* Adjust the address so that the address-after-the-data is
10708 if (BYTES_BIG_ENDIAN
)
10709 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10711 return adjust_address_nv (x
, omode
, offset
);
10714 /* If X is a comparison operator, rewrite it in a new mode. This
10715 probably won't match, but may allow further simplifications. */
10716 else if (COMPARISON_P (x
))
10717 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10719 /* If we couldn't simplify X any other way, just enclose it in a
10720 SUBREG. Normally, this SUBREG won't match, but some patterns may
10721 include an explicit SUBREG or we may simplify it further in combine. */
10727 offset
= subreg_lowpart_offset (omode
, imode
);
10728 if (imode
== VOIDmode
)
10730 imode
= int_mode_for_mode (omode
);
10731 x
= gen_lowpart_common (imode
, x
);
10735 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10741 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10744 /* Try to simplify a comparison between OP0 and a constant OP1,
10745 where CODE is the comparison code that will be tested, into a
10746 (CODE OP0 const0_rtx) form.
10748 The result is a possibly different comparison code to use.
10749 *POP1 may be updated. */
10751 static enum rtx_code
10752 simplify_compare_const (enum rtx_code code
, rtx op0
, rtx
*pop1
)
10754 enum machine_mode mode
= GET_MODE (op0
);
10755 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10756 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10758 /* Get the constant we are comparing against and turn off all bits
10759 not on in our mode. */
10760 if (mode
!= VOIDmode
)
10761 const_op
= trunc_int_for_mode (const_op
, mode
);
10763 /* If we are comparing against a constant power of two and the value
10764 being compared can only have that single bit nonzero (e.g., it was
10765 `and'ed with that bit), we can replace this with a comparison
10768 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10769 || code
== LT
|| code
== LTU
)
10770 && mode_width
<= HOST_BITS_PER_WIDE_INT
10771 && exact_log2 (const_op
) >= 0
10772 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10774 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10778 /* Similarly, if we are comparing a value known to be either -1 or
10779 0 with -1, change it to the opposite comparison against zero. */
10781 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10782 || code
== GEU
|| code
== LTU
)
10783 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10785 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10789 /* Do some canonicalizations based on the comparison code. We prefer
10790 comparisons against zero and then prefer equality comparisons.
10791 If we can reduce the size of a constant, we will do that too. */
10795 /* < C is equivalent to <= (C - 1) */
10800 /* ... fall through to LE case below. */
10806 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10813 /* If we are doing a <= 0 comparison on a value known to have
10814 a zero sign bit, we can replace this with == 0. */
10815 else if (const_op
== 0
10816 && mode_width
<= HOST_BITS_PER_WIDE_INT
10817 && (nonzero_bits (op0
, mode
)
10818 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10824 /* >= C is equivalent to > (C - 1). */
10829 /* ... fall through to GT below. */
10835 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10842 /* If we are doing a > 0 comparison on a value known to have
10843 a zero sign bit, we can replace this with != 0. */
10844 else if (const_op
== 0
10845 && mode_width
<= HOST_BITS_PER_WIDE_INT
10846 && (nonzero_bits (op0
, mode
)
10847 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10853 /* < C is equivalent to <= (C - 1). */
10858 /* ... fall through ... */
10860 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10861 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10862 && (unsigned HOST_WIDE_INT
) const_op
10863 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10873 /* unsigned <= 0 is equivalent to == 0 */
10876 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10877 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10878 && (unsigned HOST_WIDE_INT
) const_op
10879 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10887 /* >= C is equivalent to > (C - 1). */
10892 /* ... fall through ... */
10895 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10896 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10897 && (unsigned HOST_WIDE_INT
) const_op
10898 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10908 /* unsigned > 0 is equivalent to != 0 */
10911 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10912 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10913 && (unsigned HOST_WIDE_INT
) const_op
10914 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10925 *pop1
= GEN_INT (const_op
);
10929 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10930 comparison code that will be tested.
10932 The result is a possibly different comparison code to use. *POP0 and
10933 *POP1 may be updated.
10935 It is possible that we might detect that a comparison is either always
10936 true or always false. However, we do not perform general constant
10937 folding in combine, so this knowledge isn't useful. Such tautologies
10938 should have been detected earlier. Hence we ignore all such cases. */
10940 static enum rtx_code
10941 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10947 enum machine_mode mode
, tmode
;
10949 /* Try a few ways of applying the same transformation to both operands. */
10952 #ifndef WORD_REGISTER_OPERATIONS
10953 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10954 so check specially. */
10955 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10956 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10957 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10958 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10959 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10960 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10961 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10962 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10963 && CONST_INT_P (XEXP (op0
, 1))
10964 && XEXP (op0
, 1) == XEXP (op1
, 1)
10965 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10966 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10967 && (INTVAL (XEXP (op0
, 1))
10968 == (GET_MODE_PRECISION (GET_MODE (op0
))
10969 - (GET_MODE_PRECISION
10970 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10972 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10973 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10977 /* If both operands are the same constant shift, see if we can ignore the
10978 shift. We can if the shift is a rotate or if the bits shifted out of
10979 this shift are known to be zero for both inputs and if the type of
10980 comparison is compatible with the shift. */
10981 if (GET_CODE (op0
) == GET_CODE (op1
)
10982 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0
))
10983 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10984 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10985 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10986 || (GET_CODE (op0
) == ASHIFTRT
10987 && (code
!= GTU
&& code
!= LTU
10988 && code
!= GEU
&& code
!= LEU
)))
10989 && CONST_INT_P (XEXP (op0
, 1))
10990 && INTVAL (XEXP (op0
, 1)) >= 0
10991 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10992 && XEXP (op0
, 1) == XEXP (op1
, 1))
10994 enum machine_mode mode
= GET_MODE (op0
);
10995 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10996 int shift_count
= INTVAL (XEXP (op0
, 1));
10998 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10999 mask
&= (mask
>> shift_count
) << shift_count
;
11000 else if (GET_CODE (op0
) == ASHIFT
)
11001 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11003 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11004 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11005 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11010 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11011 SUBREGs are of the same mode, and, in both cases, the AND would
11012 be redundant if the comparison was done in the narrower mode,
11013 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11014 and the operand's possibly nonzero bits are 0xffffff01; in that case
11015 if we only care about QImode, we don't need the AND). This case
11016 occurs if the output mode of an scc insn is not SImode and
11017 STORE_FLAG_VALUE == 1 (e.g., the 386).
11019 Similarly, check for a case where the AND's are ZERO_EXTEND
11020 operations from some narrower mode even though a SUBREG is not
11023 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11024 && CONST_INT_P (XEXP (op0
, 1))
11025 && CONST_INT_P (XEXP (op1
, 1)))
11027 rtx inner_op0
= XEXP (op0
, 0);
11028 rtx inner_op1
= XEXP (op1
, 0);
11029 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11030 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11033 if (paradoxical_subreg_p (inner_op0
)
11034 && GET_CODE (inner_op1
) == SUBREG
11035 && (GET_MODE (SUBREG_REG (inner_op0
))
11036 == GET_MODE (SUBREG_REG (inner_op1
)))
11037 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11038 <= HOST_BITS_PER_WIDE_INT
)
11039 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11040 GET_MODE (SUBREG_REG (inner_op0
)))))
11041 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11042 GET_MODE (SUBREG_REG (inner_op1
))))))
11044 op0
= SUBREG_REG (inner_op0
);
11045 op1
= SUBREG_REG (inner_op1
);
11047 /* The resulting comparison is always unsigned since we masked
11048 off the original sign bit. */
11049 code
= unsigned_condition (code
);
11055 for (tmode
= GET_CLASS_NARROWEST_MODE
11056 (GET_MODE_CLASS (GET_MODE (op0
)));
11057 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11058 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11060 op0
= gen_lowpart (tmode
, inner_op0
);
11061 op1
= gen_lowpart (tmode
, inner_op1
);
11062 code
= unsigned_condition (code
);
11071 /* If both operands are NOT, we can strip off the outer operation
11072 and adjust the comparison code for swapped operands; similarly for
11073 NEG, except that this must be an equality comparison. */
11074 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11075 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11076 && (code
== EQ
|| code
== NE
)))
11077 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11083 /* If the first operand is a constant, swap the operands and adjust the
11084 comparison code appropriately, but don't do this if the second operand
11085 is already a constant integer. */
11086 if (swap_commutative_operands_p (op0
, op1
))
11088 tem
= op0
, op0
= op1
, op1
= tem
;
11089 code
= swap_condition (code
);
11092 /* We now enter a loop during which we will try to simplify the comparison.
11093 For the most part, we only are concerned with comparisons with zero,
11094 but some things may really be comparisons with zero but not start
11095 out looking that way. */
11097 while (CONST_INT_P (op1
))
11099 enum machine_mode mode
= GET_MODE (op0
);
11100 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11101 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11102 int equality_comparison_p
;
11103 int sign_bit_comparison_p
;
11104 int unsigned_comparison_p
;
11105 HOST_WIDE_INT const_op
;
11107 /* We only want to handle integral modes. This catches VOIDmode,
11108 CCmode, and the floating-point modes. An exception is that we
11109 can handle VOIDmode if OP0 is a COMPARE or a comparison
11112 if (GET_MODE_CLASS (mode
) != MODE_INT
11113 && ! (mode
== VOIDmode
11114 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11117 /* Try to simplify the compare to constant, possibly changing the
11118 comparison op, and/or changing op1 to zero. */
11119 code
= simplify_compare_const (code
, op0
, &op1
);
11120 const_op
= INTVAL (op1
);
11122 /* Compute some predicates to simplify code below. */
11124 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11125 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11126 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11129 /* If this is a sign bit comparison and we can do arithmetic in
11130 MODE, say that we will only be needing the sign bit of OP0. */
11131 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11132 op0
= force_to_mode (op0
, mode
,
11133 (unsigned HOST_WIDE_INT
) 1
11134 << (GET_MODE_PRECISION (mode
) - 1),
11137 /* Now try cases based on the opcode of OP0. If none of the cases
11138 does a "continue", we exit this loop immediately after the
11141 switch (GET_CODE (op0
))
11144 /* If we are extracting a single bit from a variable position in
11145 a constant that has only a single bit set and are comparing it
11146 with zero, we can convert this into an equality comparison
11147 between the position and the location of the single bit. */
11148 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11149 have already reduced the shift count modulo the word size. */
11150 if (!SHIFT_COUNT_TRUNCATED
11151 && CONST_INT_P (XEXP (op0
, 0))
11152 && XEXP (op0
, 1) == const1_rtx
11153 && equality_comparison_p
&& const_op
== 0
11154 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11156 if (BITS_BIG_ENDIAN
)
11157 i
= BITS_PER_WORD
- 1 - i
;
11159 op0
= XEXP (op0
, 2);
11163 /* Result is nonzero iff shift count is equal to I. */
11164 code
= reverse_condition (code
);
11168 /* ... fall through ... */
11171 tem
= expand_compound_operation (op0
);
11180 /* If testing for equality, we can take the NOT of the constant. */
11181 if (equality_comparison_p
11182 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11184 op0
= XEXP (op0
, 0);
11189 /* If just looking at the sign bit, reverse the sense of the
11191 if (sign_bit_comparison_p
)
11193 op0
= XEXP (op0
, 0);
11194 code
= (code
== GE
? LT
: GE
);
11200 /* If testing for equality, we can take the NEG of the constant. */
11201 if (equality_comparison_p
11202 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11204 op0
= XEXP (op0
, 0);
11209 /* The remaining cases only apply to comparisons with zero. */
11213 /* When X is ABS or is known positive,
11214 (neg X) is < 0 if and only if X != 0. */
11216 if (sign_bit_comparison_p
11217 && (GET_CODE (XEXP (op0
, 0)) == ABS
11218 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11219 && (nonzero_bits (XEXP (op0
, 0), mode
)
11220 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11223 op0
= XEXP (op0
, 0);
11224 code
= (code
== LT
? NE
: EQ
);
11228 /* If we have NEG of something whose two high-order bits are the
11229 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11230 if (num_sign_bit_copies (op0
, mode
) >= 2)
11232 op0
= XEXP (op0
, 0);
11233 code
= swap_condition (code
);
11239 /* If we are testing equality and our count is a constant, we
11240 can perform the inverse operation on our RHS. */
11241 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11242 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11243 op1
, XEXP (op0
, 1))) != 0)
11245 op0
= XEXP (op0
, 0);
11250 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11251 a particular bit. Convert it to an AND of a constant of that
11252 bit. This will be converted into a ZERO_EXTRACT. */
11253 if (const_op
== 0 && sign_bit_comparison_p
11254 && CONST_INT_P (XEXP (op0
, 1))
11255 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11257 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11258 ((unsigned HOST_WIDE_INT
) 1
11260 - INTVAL (XEXP (op0
, 1)))));
11261 code
= (code
== LT
? NE
: EQ
);
11265 /* Fall through. */
11268 /* ABS is ignorable inside an equality comparison with zero. */
11269 if (const_op
== 0 && equality_comparison_p
)
11271 op0
= XEXP (op0
, 0);
11277 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11278 (compare FOO CONST) if CONST fits in FOO's mode and we
11279 are either testing inequality or have an unsigned
11280 comparison with ZERO_EXTEND or a signed comparison with
11281 SIGN_EXTEND. But don't do it if we don't have a compare
11282 insn of the given mode, since we'd have to revert it
11283 later on, and then we wouldn't know whether to sign- or
11285 mode
= GET_MODE (XEXP (op0
, 0));
11286 if (GET_MODE_CLASS (mode
) == MODE_INT
11287 && ! unsigned_comparison_p
11288 && HWI_COMPUTABLE_MODE_P (mode
)
11289 && trunc_int_for_mode (const_op
, mode
) == const_op
11290 && have_insn_for (COMPARE
, mode
))
11292 op0
= XEXP (op0
, 0);
11298 /* Check for the case where we are comparing A - C1 with C2, that is
11300 (subreg:MODE (plus (A) (-C1))) op (C2)
11302 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11303 comparison in the wider mode. One of the following two conditions
11304 must be true in order for this to be valid:
11306 1. The mode extension results in the same bit pattern being added
11307 on both sides and the comparison is equality or unsigned. As
11308 C2 has been truncated to fit in MODE, the pattern can only be
11311 2. The mode extension results in the sign bit being copied on
11314 The difficulty here is that we have predicates for A but not for
11315 (A - C1) so we need to check that C1 is within proper bounds so
11316 as to perturbate A as little as possible. */
11318 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11319 && subreg_lowpart_p (op0
)
11320 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11321 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11322 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11324 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11325 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11326 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11329 && (unsigned HOST_WIDE_INT
) c1
11330 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11331 && (equality_comparison_p
|| unsigned_comparison_p
)
11332 /* (A - C1) zero-extends if it is positive and sign-extends
11333 if it is negative, C2 both zero- and sign-extends. */
11334 && ((0 == (nonzero_bits (a
, inner_mode
)
11335 & ~GET_MODE_MASK (mode
))
11337 /* (A - C1) sign-extends if it is positive and 1-extends
11338 if it is negative, C2 both sign- and 1-extends. */
11339 || (num_sign_bit_copies (a
, inner_mode
)
11340 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11343 || ((unsigned HOST_WIDE_INT
) c1
11344 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11345 /* (A - C1) always sign-extends, like C2. */
11346 && num_sign_bit_copies (a
, inner_mode
)
11347 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11348 - (mode_width
- 1))))
11350 op0
= SUBREG_REG (op0
);
11355 /* If the inner mode is narrower and we are extracting the low part,
11356 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11357 if (subreg_lowpart_p (op0
)
11358 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11359 /* Fall through */ ;
11363 /* ... fall through ... */
11366 mode
= GET_MODE (XEXP (op0
, 0));
11367 if (GET_MODE_CLASS (mode
) == MODE_INT
11368 && (unsigned_comparison_p
|| equality_comparison_p
)
11369 && HWI_COMPUTABLE_MODE_P (mode
)
11370 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11372 && have_insn_for (COMPARE
, mode
))
11374 op0
= XEXP (op0
, 0);
11380 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11381 this for equality comparisons due to pathological cases involving
11383 if (equality_comparison_p
11384 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11385 op1
, XEXP (op0
, 1))))
11387 op0
= XEXP (op0
, 0);
11392 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11393 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11394 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11396 op0
= XEXP (XEXP (op0
, 0), 0);
11397 code
= (code
== LT
? EQ
: NE
);
11403 /* We used to optimize signed comparisons against zero, but that
11404 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11405 arrive here as equality comparisons, or (GEU, LTU) are
11406 optimized away. No need to special-case them. */
11408 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11409 (eq B (minus A C)), whichever simplifies. We can only do
11410 this for equality comparisons due to pathological cases involving
11412 if (equality_comparison_p
11413 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11414 XEXP (op0
, 1), op1
)))
11416 op0
= XEXP (op0
, 0);
11421 if (equality_comparison_p
11422 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11423 XEXP (op0
, 0), op1
)))
11425 op0
= XEXP (op0
, 1);
11430 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11431 of bits in X minus 1, is one iff X > 0. */
11432 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11433 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11434 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11435 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11437 op0
= XEXP (op0
, 1);
11438 code
= (code
== GE
? LE
: GT
);
11444 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11445 if C is zero or B is a constant. */
11446 if (equality_comparison_p
11447 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11448 XEXP (op0
, 1), op1
)))
11450 op0
= XEXP (op0
, 0);
11457 case UNEQ
: case LTGT
:
11458 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11459 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11460 case UNORDERED
: case ORDERED
:
11461 /* We can't do anything if OP0 is a condition code value, rather
11462 than an actual data value. */
11464 || CC0_P (XEXP (op0
, 0))
11465 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11468 /* Get the two operands being compared. */
11469 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11470 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11472 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11474 /* Check for the cases where we simply want the result of the
11475 earlier test or the opposite of that result. */
11476 if (code
== NE
|| code
== EQ
11477 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11478 && (code
== LT
|| code
== GE
)))
11480 enum rtx_code new_code
;
11481 if (code
== LT
|| code
== NE
)
11482 new_code
= GET_CODE (op0
);
11484 new_code
= reversed_comparison_code (op0
, NULL
);
11486 if (new_code
!= UNKNOWN
)
11497 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11499 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11500 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11501 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11503 op0
= XEXP (op0
, 1);
11504 code
= (code
== GE
? GT
: LE
);
11510 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11511 will be converted to a ZERO_EXTRACT later. */
11512 if (const_op
== 0 && equality_comparison_p
11513 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11514 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11516 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11517 XEXP (XEXP (op0
, 0), 1));
11518 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11522 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11523 zero and X is a comparison and C1 and C2 describe only bits set
11524 in STORE_FLAG_VALUE, we can compare with X. */
11525 if (const_op
== 0 && equality_comparison_p
11526 && mode_width
<= HOST_BITS_PER_WIDE_INT
11527 && CONST_INT_P (XEXP (op0
, 1))
11528 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11529 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11530 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11531 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11533 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11534 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11535 if ((~STORE_FLAG_VALUE
& mask
) == 0
11536 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11537 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11538 && COMPARISON_P (tem
))))
11540 op0
= XEXP (XEXP (op0
, 0), 0);
11545 /* If we are doing an equality comparison of an AND of a bit equal
11546 to the sign bit, replace this with a LT or GE comparison of
11547 the underlying value. */
11548 if (equality_comparison_p
11550 && CONST_INT_P (XEXP (op0
, 1))
11551 && mode_width
<= HOST_BITS_PER_WIDE_INT
11552 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11553 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11555 op0
= XEXP (op0
, 0);
11556 code
= (code
== EQ
? GE
: LT
);
11560 /* If this AND operation is really a ZERO_EXTEND from a narrower
11561 mode, the constant fits within that mode, and this is either an
11562 equality or unsigned comparison, try to do this comparison in
11567 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11568 -> (ne:DI (reg:SI 4) (const_int 0))
11570 unless TRULY_NOOP_TRUNCATION allows it or the register is
11571 known to hold a value of the required mode the
11572 transformation is invalid. */
11573 if ((equality_comparison_p
|| unsigned_comparison_p
)
11574 && CONST_INT_P (XEXP (op0
, 1))
11575 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11576 & GET_MODE_MASK (mode
))
11578 && const_op
>> i
== 0
11579 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11580 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11581 || (REG_P (XEXP (op0
, 0))
11582 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11584 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11588 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11589 fits in both M1 and M2 and the SUBREG is either paradoxical
11590 or represents the low part, permute the SUBREG and the AND
11592 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11594 unsigned HOST_WIDE_INT c1
;
11595 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11596 /* Require an integral mode, to avoid creating something like
11598 if (SCALAR_INT_MODE_P (tmode
)
11599 /* It is unsafe to commute the AND into the SUBREG if the
11600 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11601 not defined. As originally written the upper bits
11602 have a defined value due to the AND operation.
11603 However, if we commute the AND inside the SUBREG then
11604 they no longer have defined values and the meaning of
11605 the code has been changed. */
11607 #ifdef WORD_REGISTER_OPERATIONS
11608 || (mode_width
> GET_MODE_PRECISION (tmode
)
11609 && mode_width
<= BITS_PER_WORD
)
11611 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11612 && subreg_lowpart_p (XEXP (op0
, 0))))
11613 && CONST_INT_P (XEXP (op0
, 1))
11614 && mode_width
<= HOST_BITS_PER_WIDE_INT
11615 && HWI_COMPUTABLE_MODE_P (tmode
)
11616 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11617 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11619 && c1
!= GET_MODE_MASK (tmode
))
11621 op0
= simplify_gen_binary (AND
, tmode
,
11622 SUBREG_REG (XEXP (op0
, 0)),
11623 gen_int_mode (c1
, tmode
));
11624 op0
= gen_lowpart (mode
, op0
);
11629 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11630 if (const_op
== 0 && equality_comparison_p
11631 && XEXP (op0
, 1) == const1_rtx
11632 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11634 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11635 XEXP (XEXP (op0
, 0), 0), 1);
11636 code
= (code
== NE
? EQ
: NE
);
11640 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11641 (eq (and (lshiftrt X) 1) 0).
11642 Also handle the case where (not X) is expressed using xor. */
11643 if (const_op
== 0 && equality_comparison_p
11644 && XEXP (op0
, 1) == const1_rtx
11645 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11647 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11648 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11650 if (GET_CODE (shift_op
) == NOT
11651 || (GET_CODE (shift_op
) == XOR
11652 && CONST_INT_P (XEXP (shift_op
, 1))
11653 && CONST_INT_P (shift_count
)
11654 && HWI_COMPUTABLE_MODE_P (mode
)
11655 && (UINTVAL (XEXP (shift_op
, 1))
11656 == (unsigned HOST_WIDE_INT
) 1
11657 << INTVAL (shift_count
))))
11660 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11661 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11662 code
= (code
== NE
? EQ
: NE
);
11669 /* If we have (compare (ashift FOO N) (const_int C)) and
11670 the high order N bits of FOO (N+1 if an inequality comparison)
11671 are known to be zero, we can do this by comparing FOO with C
11672 shifted right N bits so long as the low-order N bits of C are
11674 if (CONST_INT_P (XEXP (op0
, 1))
11675 && INTVAL (XEXP (op0
, 1)) >= 0
11676 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11677 < HOST_BITS_PER_WIDE_INT
)
11678 && (((unsigned HOST_WIDE_INT
) const_op
11679 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11681 && mode_width
<= HOST_BITS_PER_WIDE_INT
11682 && (nonzero_bits (XEXP (op0
, 0), mode
)
11683 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11684 + ! equality_comparison_p
))) == 0)
11686 /* We must perform a logical shift, not an arithmetic one,
11687 as we want the top N bits of C to be zero. */
11688 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11690 temp
>>= INTVAL (XEXP (op0
, 1));
11691 op1
= gen_int_mode (temp
, mode
);
11692 op0
= XEXP (op0
, 0);
11696 /* If we are doing a sign bit comparison, it means we are testing
11697 a particular bit. Convert it to the appropriate AND. */
11698 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11699 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11701 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11702 ((unsigned HOST_WIDE_INT
) 1
11704 - INTVAL (XEXP (op0
, 1)))));
11705 code
= (code
== LT
? NE
: EQ
);
11709 /* If this an equality comparison with zero and we are shifting
11710 the low bit to the sign bit, we can convert this to an AND of the
11712 if (const_op
== 0 && equality_comparison_p
11713 && CONST_INT_P (XEXP (op0
, 1))
11714 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11716 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11722 /* If this is an equality comparison with zero, we can do this
11723 as a logical shift, which might be much simpler. */
11724 if (equality_comparison_p
&& const_op
== 0
11725 && CONST_INT_P (XEXP (op0
, 1)))
11727 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11729 INTVAL (XEXP (op0
, 1)));
11733 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11734 do the comparison in a narrower mode. */
11735 if (! unsigned_comparison_p
11736 && CONST_INT_P (XEXP (op0
, 1))
11737 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11738 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11739 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11740 MODE_INT
, 1)) != BLKmode
11741 && (((unsigned HOST_WIDE_INT
) const_op
11742 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11743 <= GET_MODE_MASK (tmode
)))
11745 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11749 /* Likewise if OP0 is a PLUS of a sign extension with a
11750 constant, which is usually represented with the PLUS
11751 between the shifts. */
11752 if (! unsigned_comparison_p
11753 && CONST_INT_P (XEXP (op0
, 1))
11754 && GET_CODE (XEXP (op0
, 0)) == PLUS
11755 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11756 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11757 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11758 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11759 MODE_INT
, 1)) != BLKmode
11760 && (((unsigned HOST_WIDE_INT
) const_op
11761 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11762 <= GET_MODE_MASK (tmode
)))
11764 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11765 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11766 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11767 add_const
, XEXP (op0
, 1));
11769 op0
= simplify_gen_binary (PLUS
, tmode
,
11770 gen_lowpart (tmode
, inner
),
11775 /* ... fall through ... */
11777 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11778 the low order N bits of FOO are known to be zero, we can do this
11779 by comparing FOO with C shifted left N bits so long as no
11780 overflow occurs. Even if the low order N bits of FOO aren't known
11781 to be zero, if the comparison is >= or < we can use the same
11782 optimization and for > or <= by setting all the low
11783 order N bits in the comparison constant. */
11784 if (CONST_INT_P (XEXP (op0
, 1))
11785 && INTVAL (XEXP (op0
, 1)) > 0
11786 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11787 && mode_width
<= HOST_BITS_PER_WIDE_INT
11788 && (((unsigned HOST_WIDE_INT
) const_op
11789 + (GET_CODE (op0
) != LSHIFTRT
11790 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11793 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11795 unsigned HOST_WIDE_INT low_bits
11796 = (nonzero_bits (XEXP (op0
, 0), mode
)
11797 & (((unsigned HOST_WIDE_INT
) 1
11798 << INTVAL (XEXP (op0
, 1))) - 1));
11799 if (low_bits
== 0 || !equality_comparison_p
)
11801 /* If the shift was logical, then we must make the condition
11803 if (GET_CODE (op0
) == LSHIFTRT
)
11804 code
= unsigned_condition (code
);
11806 const_op
<<= INTVAL (XEXP (op0
, 1));
11808 && (code
== GT
|| code
== GTU
11809 || code
== LE
|| code
== LEU
))
11811 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11812 op1
= GEN_INT (const_op
);
11813 op0
= XEXP (op0
, 0);
11818 /* If we are using this shift to extract just the sign bit, we
11819 can replace this with an LT or GE comparison. */
11821 && (equality_comparison_p
|| sign_bit_comparison_p
)
11822 && CONST_INT_P (XEXP (op0
, 1))
11823 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11825 op0
= XEXP (op0
, 0);
11826 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11838 /* Now make any compound operations involved in this comparison. Then,
11839 check for an outmost SUBREG on OP0 that is not doing anything or is
11840 paradoxical. The latter transformation must only be performed when
11841 it is known that the "extra" bits will be the same in op0 and op1 or
11842 that they don't matter. There are three cases to consider:
11844 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11845 care bits and we can assume they have any convenient value. So
11846 making the transformation is safe.
11848 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11849 In this case the upper bits of op0 are undefined. We should not make
11850 the simplification in that case as we do not know the contents of
11853 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11854 UNKNOWN. In that case we know those bits are zeros or ones. We must
11855 also be sure that they are the same as the upper bits of op1.
11857 We can never remove a SUBREG for a non-equality comparison because
11858 the sign bit is in a different place in the underlying object. */
11860 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11861 op1
= make_compound_operation (op1
, SET
);
11863 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11864 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11865 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11866 && (code
== NE
|| code
== EQ
))
11868 if (paradoxical_subreg_p (op0
))
11870 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11872 if (REG_P (SUBREG_REG (op0
)))
11874 op0
= SUBREG_REG (op0
);
11875 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11878 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11879 <= HOST_BITS_PER_WIDE_INT
)
11880 && (nonzero_bits (SUBREG_REG (op0
),
11881 GET_MODE (SUBREG_REG (op0
)))
11882 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11884 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11886 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11887 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11888 op0
= SUBREG_REG (op0
), op1
= tem
;
11892 /* We now do the opposite procedure: Some machines don't have compare
11893 insns in all modes. If OP0's mode is an integer mode smaller than a
11894 word and we can't do a compare in that mode, see if there is a larger
11895 mode for which we can do the compare. There are a number of cases in
11896 which we can use the wider mode. */
11898 mode
= GET_MODE (op0
);
11899 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11900 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11901 && ! have_insn_for (COMPARE
, mode
))
11902 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11903 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
11904 tmode
= GET_MODE_WIDER_MODE (tmode
))
11905 if (have_insn_for (COMPARE
, tmode
))
11909 /* If this is a test for negative, we can make an explicit
11910 test of the sign bit. Test this first so we can use
11911 a paradoxical subreg to extend OP0. */
11913 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11914 && HWI_COMPUTABLE_MODE_P (mode
))
11916 op0
= simplify_gen_binary (AND
, tmode
,
11917 gen_lowpart (tmode
, op0
),
11918 GEN_INT ((unsigned HOST_WIDE_INT
) 1
11919 << (GET_MODE_BITSIZE (mode
)
11921 code
= (code
== LT
) ? NE
: EQ
;
11925 /* If the only nonzero bits in OP0 and OP1 are those in the
11926 narrower mode and this is an equality or unsigned comparison,
11927 we can use the wider mode. Similarly for sign-extended
11928 values, in which case it is true for all comparisons. */
11929 zero_extended
= ((code
== EQ
|| code
== NE
11930 || code
== GEU
|| code
== GTU
11931 || code
== LEU
|| code
== LTU
)
11932 && (nonzero_bits (op0
, tmode
)
11933 & ~GET_MODE_MASK (mode
)) == 0
11934 && ((CONST_INT_P (op1
)
11935 || (nonzero_bits (op1
, tmode
)
11936 & ~GET_MODE_MASK (mode
)) == 0)));
11939 || ((num_sign_bit_copies (op0
, tmode
)
11940 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11941 - GET_MODE_PRECISION (mode
)))
11942 && (num_sign_bit_copies (op1
, tmode
)
11943 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11944 - GET_MODE_PRECISION (mode
)))))
11946 /* If OP0 is an AND and we don't have an AND in MODE either,
11947 make a new AND in the proper mode. */
11948 if (GET_CODE (op0
) == AND
11949 && !have_insn_for (AND
, mode
))
11950 op0
= simplify_gen_binary (AND
, tmode
,
11951 gen_lowpart (tmode
,
11953 gen_lowpart (tmode
,
11959 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11960 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11964 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11965 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11972 #ifdef CANONICALIZE_COMPARISON
11973 /* If this machine only supports a subset of valid comparisons, see if we
11974 can convert an unsupported one into a supported one. */
11975 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11984 /* Utility function for record_value_for_reg. Count number of
11989 enum rtx_code code
= GET_CODE (x
);
11993 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
11994 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
11996 rtx x0
= XEXP (x
, 0);
11997 rtx x1
= XEXP (x
, 1);
12000 return 1 + 2 * count_rtxs (x0
);
12002 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12003 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12004 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12005 return 2 + 2 * count_rtxs (x0
)
12006 + count_rtxs (x
== XEXP (x1
, 0)
12007 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12009 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12010 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12011 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12012 return 2 + 2 * count_rtxs (x1
)
12013 + count_rtxs (x
== XEXP (x0
, 0)
12014 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12017 fmt
= GET_RTX_FORMAT (code
);
12018 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12020 ret
+= count_rtxs (XEXP (x
, i
));
12021 else if (fmt
[i
] == 'E')
12022 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12023 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12028 /* Utility function for following routine. Called when X is part of a value
12029 being stored into last_set_value. Sets last_set_table_tick
12030 for each register mentioned. Similar to mention_regs in cse.c */
12033 update_table_tick (rtx x
)
12035 enum rtx_code code
= GET_CODE (x
);
12036 const char *fmt
= GET_RTX_FORMAT (code
);
12041 unsigned int regno
= REGNO (x
);
12042 unsigned int endregno
= END_REGNO (x
);
12045 for (r
= regno
; r
< endregno
; r
++)
12047 reg_stat_type
*rsp
= &VEC_index (reg_stat_type
, reg_stat
, r
);
12048 rsp
->last_set_table_tick
= label_tick
;
12054 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12057 /* Check for identical subexpressions. If x contains
12058 identical subexpression we only have to traverse one of
12060 if (i
== 0 && ARITHMETIC_P (x
))
12062 /* Note that at this point x1 has already been
12064 rtx x0
= XEXP (x
, 0);
12065 rtx x1
= XEXP (x
, 1);
12067 /* If x0 and x1 are identical then there is no need to
12072 /* If x0 is identical to a subexpression of x1 then while
12073 processing x1, x0 has already been processed. Thus we
12074 are done with x. */
12075 if (ARITHMETIC_P (x1
)
12076 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12079 /* If x1 is identical to a subexpression of x0 then we
12080 still have to process the rest of x0. */
12081 if (ARITHMETIC_P (x0
)
12082 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12084 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12089 update_table_tick (XEXP (x
, i
));
12091 else if (fmt
[i
] == 'E')
12092 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12093 update_table_tick (XVECEXP (x
, i
, j
));
12096 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12097 are saying that the register is clobbered and we no longer know its
12098 value. If INSN is zero, don't update reg_stat[].last_set; this is
12099 only permitted with VALUE also zero and is used to invalidate the
12103 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12105 unsigned int regno
= REGNO (reg
);
12106 unsigned int endregno
= END_REGNO (reg
);
12108 reg_stat_type
*rsp
;
12110 /* If VALUE contains REG and we have a previous value for REG, substitute
12111 the previous value. */
12112 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12116 /* Set things up so get_last_value is allowed to see anything set up to
12118 subst_low_luid
= DF_INSN_LUID (insn
);
12119 tem
= get_last_value (reg
);
12121 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12122 it isn't going to be useful and will take a lot of time to process,
12123 so just use the CLOBBER. */
12127 if (ARITHMETIC_P (tem
)
12128 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12129 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12130 tem
= XEXP (tem
, 0);
12131 else if (count_occurrences (value
, reg
, 1) >= 2)
12133 /* If there are two or more occurrences of REG in VALUE,
12134 prevent the value from growing too much. */
12135 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12136 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12139 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12143 /* For each register modified, show we don't know its value, that
12144 we don't know about its bitwise content, that its value has been
12145 updated, and that we don't know the location of the death of the
12147 for (i
= regno
; i
< endregno
; i
++)
12149 rsp
= &VEC_index (reg_stat_type
, reg_stat
, i
);
12152 rsp
->last_set
= insn
;
12154 rsp
->last_set_value
= 0;
12155 rsp
->last_set_mode
= VOIDmode
;
12156 rsp
->last_set_nonzero_bits
= 0;
12157 rsp
->last_set_sign_bit_copies
= 0;
12158 rsp
->last_death
= 0;
12159 rsp
->truncated_to_mode
= VOIDmode
;
12162 /* Mark registers that are being referenced in this value. */
12164 update_table_tick (value
);
12166 /* Now update the status of each register being set.
12167 If someone is using this register in this block, set this register
12168 to invalid since we will get confused between the two lives in this
12169 basic block. This makes using this register always invalid. In cse, we
12170 scan the table to invalidate all entries using this register, but this
12171 is too much work for us. */
12173 for (i
= regno
; i
< endregno
; i
++)
12175 rsp
= &VEC_index (reg_stat_type
, reg_stat
, i
);
12176 rsp
->last_set_label
= label_tick
;
12178 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12179 rsp
->last_set_invalid
= 1;
12181 rsp
->last_set_invalid
= 0;
12184 /* The value being assigned might refer to X (like in "x++;"). In that
12185 case, we must replace it with (clobber (const_int 0)) to prevent
12187 rsp
= &VEC_index (reg_stat_type
, reg_stat
, regno
);
12188 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12190 value
= copy_rtx (value
);
12191 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12195 /* For the main register being modified, update the value, the mode, the
12196 nonzero bits, and the number of sign bit copies. */
12198 rsp
->last_set_value
= value
;
12202 enum machine_mode mode
= GET_MODE (reg
);
12203 subst_low_luid
= DF_INSN_LUID (insn
);
12204 rsp
->last_set_mode
= mode
;
12205 if (GET_MODE_CLASS (mode
) == MODE_INT
12206 && HWI_COMPUTABLE_MODE_P (mode
))
12207 mode
= nonzero_bits_mode
;
12208 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12209 rsp
->last_set_sign_bit_copies
12210 = num_sign_bit_copies (value
, GET_MODE (reg
));
12214 /* Called via note_stores from record_dead_and_set_regs to handle one
12215 SET or CLOBBER in an insn. DATA is the instruction in which the
12216 set is occurring. */
12219 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12221 rtx record_dead_insn
= (rtx
) data
;
12223 if (GET_CODE (dest
) == SUBREG
)
12224 dest
= SUBREG_REG (dest
);
12226 if (!record_dead_insn
)
12229 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12235 /* If we are setting the whole register, we know its value. Otherwise
12236 show that we don't know the value. We can handle SUBREG in
12238 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12239 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12240 else if (GET_CODE (setter
) == SET
12241 && GET_CODE (SET_DEST (setter
)) == SUBREG
12242 && SUBREG_REG (SET_DEST (setter
)) == dest
12243 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12244 && subreg_lowpart_p (SET_DEST (setter
)))
12245 record_value_for_reg (dest
, record_dead_insn
,
12246 gen_lowpart (GET_MODE (dest
),
12247 SET_SRC (setter
)));
12249 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12251 else if (MEM_P (dest
)
12252 /* Ignore pushes, they clobber nothing. */
12253 && ! push_operand (dest
, GET_MODE (dest
)))
12254 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12257 /* Update the records of when each REG was most recently set or killed
12258 for the things done by INSN. This is the last thing done in processing
12259 INSN in the combiner loop.
12261 We update reg_stat[], in particular fields last_set, last_set_value,
12262 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12263 last_death, and also the similar information mem_last_set (which insn
12264 most recently modified memory) and last_call_luid (which insn was the
12265 most recent subroutine call). */
12268 record_dead_and_set_regs (rtx insn
)
12273 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12275 if (REG_NOTE_KIND (link
) == REG_DEAD
12276 && REG_P (XEXP (link
, 0)))
12278 unsigned int regno
= REGNO (XEXP (link
, 0));
12279 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12281 for (i
= regno
; i
< endregno
; i
++)
12283 reg_stat_type
*rsp
;
12285 rsp
= &VEC_index (reg_stat_type
, reg_stat
, i
);
12286 rsp
->last_death
= insn
;
12289 else if (REG_NOTE_KIND (link
) == REG_INC
)
12290 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12295 hard_reg_set_iterator hrsi
;
12296 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12298 reg_stat_type
*rsp
;
12300 rsp
= &VEC_index (reg_stat_type
, reg_stat
, i
);
12301 rsp
->last_set_invalid
= 1;
12302 rsp
->last_set
= insn
;
12303 rsp
->last_set_value
= 0;
12304 rsp
->last_set_mode
= VOIDmode
;
12305 rsp
->last_set_nonzero_bits
= 0;
12306 rsp
->last_set_sign_bit_copies
= 0;
12307 rsp
->last_death
= 0;
12308 rsp
->truncated_to_mode
= VOIDmode
;
12311 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12313 /* We can't combine into a call pattern. Remember, though, that
12314 the return value register is set at this LUID. We could
12315 still replace a register with the return value from the
12316 wrong subroutine call! */
12317 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12320 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12323 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12324 register present in the SUBREG, so for each such SUBREG go back and
12325 adjust nonzero and sign bit information of the registers that are
12326 known to have some zero/sign bits set.
12328 This is needed because when combine blows the SUBREGs away, the
12329 information on zero/sign bits is lost and further combines can be
12330 missed because of that. */
12333 record_promoted_value (rtx insn
, rtx subreg
)
12335 struct insn_link
*links
;
12337 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12338 enum machine_mode mode
= GET_MODE (subreg
);
12340 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12343 for (links
= LOG_LINKS (insn
); links
;)
12345 reg_stat_type
*rsp
;
12347 insn
= links
->insn
;
12348 set
= single_set (insn
);
12350 if (! set
|| !REG_P (SET_DEST (set
))
12351 || REGNO (SET_DEST (set
)) != regno
12352 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12354 links
= links
->next
;
12358 rsp
= &VEC_index (reg_stat_type
, reg_stat
, regno
);
12359 if (rsp
->last_set
== insn
)
12361 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12362 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12365 if (REG_P (SET_SRC (set
)))
12367 regno
= REGNO (SET_SRC (set
));
12368 links
= LOG_LINKS (insn
);
12375 /* Check if X, a register, is known to contain a value already
12376 truncated to MODE. In this case we can use a subreg to refer to
12377 the truncated value even though in the generic case we would need
12378 an explicit truncation. */
12381 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12383 reg_stat_type
*rsp
= &VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12384 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12387 || rsp
->truncation_label
< label_tick_ebb_start
)
12389 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12391 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12396 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12397 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12398 might be able to turn a truncate into a subreg using this information.
12399 Return -1 if traversing *P is complete or 0 otherwise. */
12402 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12405 enum machine_mode truncated_mode
;
12406 reg_stat_type
*rsp
;
12408 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12410 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12411 truncated_mode
= GET_MODE (x
);
12413 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12416 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12419 x
= SUBREG_REG (x
);
12421 /* ??? For hard-regs we now record everything. We might be able to
12422 optimize this using last_set_mode. */
12423 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12424 truncated_mode
= GET_MODE (x
);
12428 rsp
= &VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12429 if (rsp
->truncated_to_mode
== 0
12430 || rsp
->truncation_label
< label_tick_ebb_start
12431 || (GET_MODE_SIZE (truncated_mode
)
12432 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12434 rsp
->truncated_to_mode
= truncated_mode
;
12435 rsp
->truncation_label
= label_tick
;
12441 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12442 the modes they are used in. This can help truning TRUNCATEs into
12446 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12448 for_each_rtx (x
, record_truncated_value
, NULL
);
12451 /* Scan X for promoted SUBREGs. For each one found,
12452 note what it implies to the registers used in it. */
12455 check_promoted_subreg (rtx insn
, rtx x
)
12457 if (GET_CODE (x
) == SUBREG
12458 && SUBREG_PROMOTED_VAR_P (x
)
12459 && REG_P (SUBREG_REG (x
)))
12460 record_promoted_value (insn
, x
);
12463 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12466 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12470 check_promoted_subreg (insn
, XEXP (x
, i
));
12474 if (XVEC (x
, i
) != 0)
12475 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12476 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12482 /* Verify that all the registers and memory references mentioned in *LOC are
12483 still valid. *LOC was part of a value set in INSN when label_tick was
12484 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12485 the invalid references with (clobber (const_int 0)) and return 1. This
12486 replacement is useful because we often can get useful information about
12487 the form of a value (e.g., if it was produced by a shift that always
12488 produces -1 or 0) even though we don't know exactly what registers it
12489 was produced from. */
12492 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12495 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12496 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12501 unsigned int regno
= REGNO (x
);
12502 unsigned int endregno
= END_REGNO (x
);
12505 for (j
= regno
; j
< endregno
; j
++)
12507 reg_stat_type
*rsp
= &VEC_index (reg_stat_type
, reg_stat
, j
);
12508 if (rsp
->last_set_invalid
12509 /* If this is a pseudo-register that was only set once and not
12510 live at the beginning of the function, it is always valid. */
12511 || (! (regno
>= FIRST_PSEUDO_REGISTER
12512 && REG_N_SETS (regno
) == 1
12513 && (!REGNO_REG_SET_P
12514 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12515 && rsp
->last_set_label
> tick
))
12518 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12525 /* If this is a memory reference, make sure that there were no stores after
12526 it that might have clobbered the value. We don't have alias info, so we
12527 assume any store invalidates it. Moreover, we only have local UIDs, so
12528 we also assume that there were stores in the intervening basic blocks. */
12529 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12530 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12533 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12537 for (i
= 0; i
< len
; i
++)
12541 /* Check for identical subexpressions. If x contains
12542 identical subexpression we only have to traverse one of
12544 if (i
== 1 && ARITHMETIC_P (x
))
12546 /* Note that at this point x0 has already been checked
12547 and found valid. */
12548 rtx x0
= XEXP (x
, 0);
12549 rtx x1
= XEXP (x
, 1);
12551 /* If x0 and x1 are identical then x is also valid. */
12555 /* If x1 is identical to a subexpression of x0 then
12556 while checking x0, x1 has already been checked. Thus
12557 it is valid and so as x. */
12558 if (ARITHMETIC_P (x0
)
12559 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12562 /* If x0 is identical to a subexpression of x1 then x is
12563 valid iff the rest of x1 is valid. */
12564 if (ARITHMETIC_P (x1
)
12565 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12567 get_last_value_validate (&XEXP (x1
,
12568 x0
== XEXP (x1
, 0) ? 1 : 0),
12569 insn
, tick
, replace
);
12572 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12576 else if (fmt
[i
] == 'E')
12577 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12578 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12579 insn
, tick
, replace
) == 0)
12583 /* If we haven't found a reason for it to be invalid, it is valid. */
12587 /* Get the last value assigned to X, if known. Some registers
12588 in the value may be replaced with (clobber (const_int 0)) if their value
12589 is known longer known reliably. */
12592 get_last_value (const_rtx x
)
12594 unsigned int regno
;
12596 reg_stat_type
*rsp
;
12598 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12599 then convert it to the desired mode. If this is a paradoxical SUBREG,
12600 we cannot predict what values the "extra" bits might have. */
12601 if (GET_CODE (x
) == SUBREG
12602 && subreg_lowpart_p (x
)
12603 && !paradoxical_subreg_p (x
)
12604 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12605 return gen_lowpart (GET_MODE (x
), value
);
12611 rsp
= &VEC_index (reg_stat_type
, reg_stat
, regno
);
12612 value
= rsp
->last_set_value
;
12614 /* If we don't have a value, or if it isn't for this basic block and
12615 it's either a hard register, set more than once, or it's a live
12616 at the beginning of the function, return 0.
12618 Because if it's not live at the beginning of the function then the reg
12619 is always set before being used (is never used without being set).
12620 And, if it's set only once, and it's always set before use, then all
12621 uses must have the same last value, even if it's not from this basic
12625 || (rsp
->last_set_label
< label_tick_ebb_start
12626 && (regno
< FIRST_PSEUDO_REGISTER
12627 || REG_N_SETS (regno
) != 1
12629 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12632 /* If the value was set in a later insn than the ones we are processing,
12633 we can't use it even if the register was only set once. */
12634 if (rsp
->last_set_label
== label_tick
12635 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12638 /* If the value has all its registers valid, return it. */
12639 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12642 /* Otherwise, make a copy and replace any invalid register with
12643 (clobber (const_int 0)). If that fails for some reason, return 0. */
12645 value
= copy_rtx (value
);
12646 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12652 /* Return nonzero if expression X refers to a REG or to memory
12653 that is set in an instruction more recent than FROM_LUID. */
12656 use_crosses_set_p (const_rtx x
, int from_luid
)
12660 enum rtx_code code
= GET_CODE (x
);
12664 unsigned int regno
= REGNO (x
);
12665 unsigned endreg
= END_REGNO (x
);
12667 #ifdef PUSH_ROUNDING
12668 /* Don't allow uses of the stack pointer to be moved,
12669 because we don't know whether the move crosses a push insn. */
12670 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12673 for (; regno
< endreg
; regno
++)
12675 reg_stat_type
*rsp
= &VEC_index (reg_stat_type
, reg_stat
, regno
);
12677 && rsp
->last_set_label
== label_tick
12678 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12684 if (code
== MEM
&& mem_last_set
> from_luid
)
12687 fmt
= GET_RTX_FORMAT (code
);
12689 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12694 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12695 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12698 else if (fmt
[i
] == 'e'
12699 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12705 /* Define three variables used for communication between the following
12708 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12709 static int reg_dead_flag
;
12711 /* Function called via note_stores from reg_dead_at_p.
12713 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12714 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12717 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12719 unsigned int regno
, endregno
;
12724 regno
= REGNO (dest
);
12725 endregno
= END_REGNO (dest
);
12726 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12727 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12730 /* Return nonzero if REG is known to be dead at INSN.
12732 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12733 referencing REG, it is dead. If we hit a SET referencing REG, it is
12734 live. Otherwise, see if it is live or dead at the start of the basic
12735 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12736 must be assumed to be always live. */
12739 reg_dead_at_p (rtx reg
, rtx insn
)
12744 /* Set variables for reg_dead_at_p_1. */
12745 reg_dead_regno
= REGNO (reg
);
12746 reg_dead_endregno
= END_REGNO (reg
);
12750 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12751 we allow the machine description to decide whether use-and-clobber
12752 patterns are OK. */
12753 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12755 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12756 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12760 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12761 beginning of basic block. */
12762 block
= BLOCK_FOR_INSN (insn
);
12767 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12769 return reg_dead_flag
== 1 ? 1 : 0;
12771 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12775 if (insn
== BB_HEAD (block
))
12778 insn
= PREV_INSN (insn
);
12781 /* Look at live-in sets for the basic block that we were in. */
12782 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12783 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12789 /* Note hard registers in X that are used. */
12792 mark_used_regs_combine (rtx x
)
12794 RTX_CODE code
= GET_CODE (x
);
12795 unsigned int regno
;
12806 case ADDR_DIFF_VEC
:
12809 /* CC0 must die in the insn after it is set, so we don't need to take
12810 special note of it here. */
12816 /* If we are clobbering a MEM, mark any hard registers inside the
12817 address as used. */
12818 if (MEM_P (XEXP (x
, 0)))
12819 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12824 /* A hard reg in a wide mode may really be multiple registers.
12825 If so, mark all of them just like the first. */
12826 if (regno
< FIRST_PSEUDO_REGISTER
)
12828 /* None of this applies to the stack, frame or arg pointers. */
12829 if (regno
== STACK_POINTER_REGNUM
12830 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12831 || regno
== HARD_FRAME_POINTER_REGNUM
12833 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12834 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12836 || regno
== FRAME_POINTER_REGNUM
)
12839 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12845 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12847 rtx testreg
= SET_DEST (x
);
12849 while (GET_CODE (testreg
) == SUBREG
12850 || GET_CODE (testreg
) == ZERO_EXTRACT
12851 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12852 testreg
= XEXP (testreg
, 0);
12854 if (MEM_P (testreg
))
12855 mark_used_regs_combine (XEXP (testreg
, 0));
12857 mark_used_regs_combine (SET_SRC (x
));
12865 /* Recursively scan the operands of this expression. */
12868 const char *fmt
= GET_RTX_FORMAT (code
);
12870 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12873 mark_used_regs_combine (XEXP (x
, i
));
12874 else if (fmt
[i
] == 'E')
12878 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12879 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12885 /* Remove register number REGNO from the dead registers list of INSN.
12887 Return the note used to record the death, if there was one. */
12890 remove_death (unsigned int regno
, rtx insn
)
12892 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12895 remove_note (insn
, note
);
12900 /* For each register (hardware or pseudo) used within expression X, if its
12901 death is in an instruction with luid between FROM_LUID (inclusive) and
12902 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12903 list headed by PNOTES.
12905 That said, don't move registers killed by maybe_kill_insn.
12907 This is done when X is being merged by combination into TO_INSN. These
12908 notes will then be distributed as needed. */
12911 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12916 enum rtx_code code
= GET_CODE (x
);
12920 unsigned int regno
= REGNO (x
);
12921 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
).last_death
;
12923 /* Don't move the register if it gets killed in between from and to. */
12924 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12925 && ! reg_referenced_p (x
, maybe_kill_insn
))
12929 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12930 && DF_INSN_LUID (where_dead
) >= from_luid
12931 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12933 rtx note
= remove_death (regno
, where_dead
);
12935 /* It is possible for the call above to return 0. This can occur
12936 when last_death points to I2 or I1 that we combined with.
12937 In that case make a new note.
12939 We must also check for the case where X is a hard register
12940 and NOTE is a death note for a range of hard registers
12941 including X. In that case, we must put REG_DEAD notes for
12942 the remaining registers in place of NOTE. */
12944 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12945 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12946 > GET_MODE_SIZE (GET_MODE (x
))))
12948 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12949 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12950 unsigned int ourend
= END_HARD_REGNO (x
);
12953 for (i
= deadregno
; i
< deadend
; i
++)
12954 if (i
< regno
|| i
>= ourend
)
12955 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12958 /* If we didn't find any note, or if we found a REG_DEAD note that
12959 covers only part of the given reg, and we have a multi-reg hard
12960 register, then to be safe we must check for REG_DEAD notes
12961 for each register other than the first. They could have
12962 their own REG_DEAD notes lying around. */
12963 else if ((note
== 0
12965 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12966 < GET_MODE_SIZE (GET_MODE (x
)))))
12967 && regno
< FIRST_PSEUDO_REGISTER
12968 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12970 unsigned int ourend
= END_HARD_REGNO (x
);
12971 unsigned int i
, offset
;
12975 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12979 for (i
= regno
+ offset
; i
< ourend
; i
++)
12980 move_deaths (regno_reg_rtx
[i
],
12981 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12984 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12986 XEXP (note
, 1) = *pnotes
;
12990 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
12996 else if (GET_CODE (x
) == SET
)
12998 rtx dest
= SET_DEST (x
);
13000 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13002 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13003 that accesses one word of a multi-word item, some
13004 piece of everything register in the expression is used by
13005 this insn, so remove any old death. */
13006 /* ??? So why do we test for equality of the sizes? */
13008 if (GET_CODE (dest
) == ZERO_EXTRACT
13009 || GET_CODE (dest
) == STRICT_LOW_PART
13010 || (GET_CODE (dest
) == SUBREG
13011 && (((GET_MODE_SIZE (GET_MODE (dest
))
13012 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13013 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13014 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13016 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13020 /* If this is some other SUBREG, we know it replaces the entire
13021 value, so use that as the destination. */
13022 if (GET_CODE (dest
) == SUBREG
)
13023 dest
= SUBREG_REG (dest
);
13025 /* If this is a MEM, adjust deaths of anything used in the address.
13026 For a REG (the only other possibility), the entire value is
13027 being replaced so the old value is not used in this insn. */
13030 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13035 else if (GET_CODE (x
) == CLOBBER
)
13038 len
= GET_RTX_LENGTH (code
);
13039 fmt
= GET_RTX_FORMAT (code
);
13041 for (i
= 0; i
< len
; i
++)
13046 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13047 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13050 else if (fmt
[i
] == 'e')
13051 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13055 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13056 pattern of an insn. X must be a REG. */
13059 reg_bitfield_target_p (rtx x
, rtx body
)
13063 if (GET_CODE (body
) == SET
)
13065 rtx dest
= SET_DEST (body
);
13067 unsigned int regno
, tregno
, endregno
, endtregno
;
13069 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13070 target
= XEXP (dest
, 0);
13071 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13072 target
= SUBREG_REG (XEXP (dest
, 0));
13076 if (GET_CODE (target
) == SUBREG
)
13077 target
= SUBREG_REG (target
);
13079 if (!REG_P (target
))
13082 tregno
= REGNO (target
), regno
= REGNO (x
);
13083 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13084 return target
== x
;
13086 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13087 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13089 return endregno
> tregno
&& regno
< endtregno
;
13092 else if (GET_CODE (body
) == PARALLEL
)
13093 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13094 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13100 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13101 as appropriate. I3 and I2 are the insns resulting from the combination
13102 insns including FROM (I2 may be zero).
13104 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13105 not need REG_DEAD notes because they are being substituted for. This
13106 saves searching in the most common cases.
13108 Each note in the list is either ignored or placed on some insns, depending
13109 on the type of note. */
13112 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13113 rtx elim_i1
, rtx elim_i0
)
13115 rtx note
, next_note
;
13118 for (note
= notes
; note
; note
= next_note
)
13120 rtx place
= 0, place2
= 0;
13122 next_note
= XEXP (note
, 1);
13123 switch (REG_NOTE_KIND (note
))
13127 /* Doesn't matter much where we put this, as long as it's somewhere.
13128 It is preferable to keep these notes on branches, which is most
13129 likely to be i3. */
13133 case REG_NON_LOCAL_GOTO
:
13138 gcc_assert (i2
&& JUMP_P (i2
));
13143 case REG_EH_REGION
:
13144 /* These notes must remain with the call or trapping instruction. */
13147 else if (i2
&& CALL_P (i2
))
13151 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13152 if (may_trap_p (i3
))
13154 else if (i2
&& may_trap_p (i2
))
13156 /* ??? Otherwise assume we've combined things such that we
13157 can now prove that the instructions can't trap. Drop the
13158 note in this case. */
13162 case REG_ARGS_SIZE
:
13163 /* ??? How to distribute between i3-i1. Assume i3 contains the
13164 entire adjustment. Assert i3 contains at least some adjust. */
13165 if (!noop_move_p (i3
))
13167 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13168 /* fixup_args_size_notes looks at REG_NORETURN note,
13169 so ensure the note is placed there first. */
13173 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13174 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13178 XEXP (n
, 1) = REG_NOTES (i3
);
13179 REG_NOTES (i3
) = n
;
13183 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13184 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13185 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13186 gcc_assert (old_size
!= args_size
13188 && !ACCUMULATE_OUTGOING_ARGS
13189 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13196 /* These notes must remain with the call. It should not be
13197 possible for both I2 and I3 to be a call. */
13202 gcc_assert (i2
&& CALL_P (i2
));
13208 /* Any clobbers for i3 may still exist, and so we must process
13209 REG_UNUSED notes from that insn.
13211 Any clobbers from i2 or i1 can only exist if they were added by
13212 recog_for_combine. In that case, recog_for_combine created the
13213 necessary REG_UNUSED notes. Trying to keep any original
13214 REG_UNUSED notes from these insns can cause incorrect output
13215 if it is for the same register as the original i3 dest.
13216 In that case, we will notice that the register is set in i3,
13217 and then add a REG_UNUSED note for the destination of i3, which
13218 is wrong. However, it is possible to have REG_UNUSED notes from
13219 i2 or i1 for register which were both used and clobbered, so
13220 we keep notes from i2 or i1 if they will turn into REG_DEAD
13223 /* If this register is set or clobbered in I3, put the note there
13224 unless there is one already. */
13225 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13227 if (from_insn
!= i3
)
13230 if (! (REG_P (XEXP (note
, 0))
13231 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13232 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13235 /* Otherwise, if this register is used by I3, then this register
13236 now dies here, so we must put a REG_DEAD note here unless there
13238 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13239 && ! (REG_P (XEXP (note
, 0))
13240 ? find_regno_note (i3
, REG_DEAD
,
13241 REGNO (XEXP (note
, 0)))
13242 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13244 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13252 /* These notes say something about results of an insn. We can
13253 only support them if they used to be on I3 in which case they
13254 remain on I3. Otherwise they are ignored.
13256 If the note refers to an expression that is not a constant, we
13257 must also ignore the note since we cannot tell whether the
13258 equivalence is still true. It might be possible to do
13259 slightly better than this (we only have a problem if I2DEST
13260 or I1DEST is present in the expression), but it doesn't
13261 seem worth the trouble. */
13263 if (from_insn
== i3
13264 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13269 /* These notes say something about how a register is used. They must
13270 be present on any use of the register in I2 or I3. */
13271 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13274 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13283 case REG_LABEL_TARGET
:
13284 case REG_LABEL_OPERAND
:
13285 /* This can show up in several ways -- either directly in the
13286 pattern, or hidden off in the constant pool with (or without?)
13287 a REG_EQUAL note. */
13288 /* ??? Ignore the without-reg_equal-note problem for now. */
13289 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13290 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13291 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13292 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13296 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13297 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13298 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13299 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13307 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13308 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13310 if (place
&& JUMP_P (place
)
13311 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13312 && (JUMP_LABEL (place
) == NULL
13313 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13315 rtx label
= JUMP_LABEL (place
);
13318 JUMP_LABEL (place
) = XEXP (note
, 0);
13319 else if (LABEL_P (label
))
13320 LABEL_NUSES (label
)--;
13323 if (place2
&& JUMP_P (place2
)
13324 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13325 && (JUMP_LABEL (place2
) == NULL
13326 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13328 rtx label
= JUMP_LABEL (place2
);
13331 JUMP_LABEL (place2
) = XEXP (note
, 0);
13332 else if (LABEL_P (label
))
13333 LABEL_NUSES (label
)--;
13339 /* This note says something about the value of a register prior
13340 to the execution of an insn. It is too much trouble to see
13341 if the note is still correct in all situations. It is better
13342 to simply delete it. */
13346 /* If we replaced the right hand side of FROM_INSN with a
13347 REG_EQUAL note, the original use of the dying register
13348 will not have been combined into I3 and I2. In such cases,
13349 FROM_INSN is guaranteed to be the first of the combined
13350 instructions, so we simply need to search back before
13351 FROM_INSN for the previous use or set of this register,
13352 then alter the notes there appropriately.
13354 If the register is used as an input in I3, it dies there.
13355 Similarly for I2, if it is nonzero and adjacent to I3.
13357 If the register is not used as an input in either I3 or I2
13358 and it is not one of the registers we were supposed to eliminate,
13359 there are two possibilities. We might have a non-adjacent I2
13360 or we might have somehow eliminated an additional register
13361 from a computation. For example, we might have had A & B where
13362 we discover that B will always be zero. In this case we will
13363 eliminate the reference to A.
13365 In both cases, we must search to see if we can find a previous
13366 use of A and put the death note there. */
13369 && from_insn
== i2mod
13370 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13375 && CALL_P (from_insn
)
13376 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13378 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13380 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13381 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13383 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13385 && reg_overlap_mentioned_p (XEXP (note
, 0),
13387 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13388 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13395 basic_block bb
= this_basic_block
;
13397 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13399 if (!NONDEBUG_INSN_P (tem
))
13401 if (tem
== BB_HEAD (bb
))
13406 /* If the register is being set at TEM, see if that is all
13407 TEM is doing. If so, delete TEM. Otherwise, make this
13408 into a REG_UNUSED note instead. Don't delete sets to
13409 global register vars. */
13410 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13411 || !global_regs
[REGNO (XEXP (note
, 0))])
13412 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13414 rtx set
= single_set (tem
);
13415 rtx inner_dest
= 0;
13417 rtx cc0_setter
= NULL_RTX
;
13421 for (inner_dest
= SET_DEST (set
);
13422 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13423 || GET_CODE (inner_dest
) == SUBREG
13424 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13425 inner_dest
= XEXP (inner_dest
, 0))
13428 /* Verify that it was the set, and not a clobber that
13429 modified the register.
13431 CC0 targets must be careful to maintain setter/user
13432 pairs. If we cannot delete the setter due to side
13433 effects, mark the user with an UNUSED note instead
13436 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13437 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13439 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13440 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13441 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13445 /* Move the notes and links of TEM elsewhere.
13446 This might delete other dead insns recursively.
13447 First set the pattern to something that won't use
13449 rtx old_notes
= REG_NOTES (tem
);
13451 PATTERN (tem
) = pc_rtx
;
13452 REG_NOTES (tem
) = NULL
;
13454 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13455 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13456 distribute_links (LOG_LINKS (tem
));
13458 SET_INSN_DELETED (tem
);
13463 /* Delete the setter too. */
13466 PATTERN (cc0_setter
) = pc_rtx
;
13467 old_notes
= REG_NOTES (cc0_setter
);
13468 REG_NOTES (cc0_setter
) = NULL
;
13470 distribute_notes (old_notes
, cc0_setter
,
13471 cc0_setter
, NULL_RTX
,
13472 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13473 distribute_links (LOG_LINKS (cc0_setter
));
13475 SET_INSN_DELETED (cc0_setter
);
13476 if (cc0_setter
== i2
)
13483 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13485 /* If there isn't already a REG_UNUSED note, put one
13486 here. Do not place a REG_DEAD note, even if
13487 the register is also used here; that would not
13488 match the algorithm used in lifetime analysis
13489 and can cause the consistency check in the
13490 scheduler to fail. */
13491 if (! find_regno_note (tem
, REG_UNUSED
,
13492 REGNO (XEXP (note
, 0))))
13497 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13499 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13503 /* If we are doing a 3->2 combination, and we have a
13504 register which formerly died in i3 and was not used
13505 by i2, which now no longer dies in i3 and is used in
13506 i2 but does not die in i2, and place is between i2
13507 and i3, then we may need to move a link from place to
13509 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13511 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13512 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13514 struct insn_link
*links
= LOG_LINKS (place
);
13515 LOG_LINKS (place
) = NULL
;
13516 distribute_links (links
);
13521 if (tem
== BB_HEAD (bb
))
13527 /* If the register is set or already dead at PLACE, we needn't do
13528 anything with this note if it is still a REG_DEAD note.
13529 We check here if it is set at all, not if is it totally replaced,
13530 which is what `dead_or_set_p' checks, so also check for it being
13533 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13535 unsigned int regno
= REGNO (XEXP (note
, 0));
13536 reg_stat_type
*rsp
= &VEC_index (reg_stat_type
, reg_stat
, regno
);
13538 if (dead_or_set_p (place
, XEXP (note
, 0))
13539 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13541 /* Unless the register previously died in PLACE, clear
13542 last_death. [I no longer understand why this is
13544 if (rsp
->last_death
!= place
)
13545 rsp
->last_death
= 0;
13549 rsp
->last_death
= place
;
13551 /* If this is a death note for a hard reg that is occupying
13552 multiple registers, ensure that we are still using all
13553 parts of the object. If we find a piece of the object
13554 that is unused, we must arrange for an appropriate REG_DEAD
13555 note to be added for it. However, we can't just emit a USE
13556 and tag the note to it, since the register might actually
13557 be dead; so we recourse, and the recursive call then finds
13558 the previous insn that used this register. */
13560 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13561 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13563 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13567 for (i
= regno
; i
< endregno
; i
++)
13568 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13569 && ! find_regno_fusage (place
, USE
, i
))
13570 || dead_or_set_regno_p (place
, i
))
13575 /* Put only REG_DEAD notes for pieces that are
13576 not already dead or set. */
13578 for (i
= regno
; i
< endregno
;
13579 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13581 rtx piece
= regno_reg_rtx
[i
];
13582 basic_block bb
= this_basic_block
;
13584 if (! dead_or_set_p (place
, piece
)
13585 && ! reg_bitfield_target_p (piece
,
13588 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13591 distribute_notes (new_note
, place
, place
,
13592 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13595 else if (! refers_to_regno_p (i
, i
+ 1,
13596 PATTERN (place
), 0)
13597 && ! find_regno_fusage (place
, USE
, i
))
13598 for (tem
= PREV_INSN (place
); ;
13599 tem
= PREV_INSN (tem
))
13601 if (!NONDEBUG_INSN_P (tem
))
13603 if (tem
== BB_HEAD (bb
))
13607 if (dead_or_set_p (tem
, piece
)
13608 || reg_bitfield_target_p (piece
,
13611 add_reg_note (tem
, REG_UNUSED
, piece
);
13625 /* Any other notes should not be present at this point in the
13627 gcc_unreachable ();
13632 XEXP (note
, 1) = REG_NOTES (place
);
13633 REG_NOTES (place
) = note
;
13637 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13641 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13642 I3, I2, and I1 to new locations. This is also called to add a link
13643 pointing at I3 when I3's destination is changed. */
13646 distribute_links (struct insn_link
*links
)
13648 struct insn_link
*link
, *next_link
;
13650 for (link
= links
; link
; link
= next_link
)
13656 next_link
= link
->next
;
13658 /* If the insn that this link points to is a NOTE or isn't a single
13659 set, ignore it. In the latter case, it isn't clear what we
13660 can do other than ignore the link, since we can't tell which
13661 register it was for. Such links wouldn't be used by combine
13664 It is not possible for the destination of the target of the link to
13665 have been changed by combine. The only potential of this is if we
13666 replace I3, I2, and I1 by I3 and I2. But in that case the
13667 destination of I2 also remains unchanged. */
13669 if (NOTE_P (link
->insn
)
13670 || (set
= single_set (link
->insn
)) == 0)
13673 reg
= SET_DEST (set
);
13674 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13675 || GET_CODE (reg
) == STRICT_LOW_PART
)
13676 reg
= XEXP (reg
, 0);
13678 /* A LOG_LINK is defined as being placed on the first insn that uses
13679 a register and points to the insn that sets the register. Start
13680 searching at the next insn after the target of the link and stop
13681 when we reach a set of the register or the end of the basic block.
13683 Note that this correctly handles the link that used to point from
13684 I3 to I2. Also note that not much searching is typically done here
13685 since most links don't point very far away. */
13687 for (insn
= NEXT_INSN (link
->insn
);
13688 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13689 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13690 insn
= NEXT_INSN (insn
))
13691 if (DEBUG_INSN_P (insn
))
13693 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13695 if (reg_referenced_p (reg
, PATTERN (insn
)))
13699 else if (CALL_P (insn
)
13700 && find_reg_fusage (insn
, USE
, reg
))
13705 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13708 /* If we found a place to put the link, place it there unless there
13709 is already a link to the same insn as LINK at that point. */
13713 struct insn_link
*link2
;
13715 FOR_EACH_LOG_LINK (link2
, place
)
13716 if (link2
->insn
== link
->insn
)
13721 link
->next
= LOG_LINKS (place
);
13722 LOG_LINKS (place
) = link
;
13724 /* Set added_links_insn to the earliest insn we added a
13726 if (added_links_insn
== 0
13727 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13728 added_links_insn
= place
;
13734 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13735 Check whether the expression pointer to by LOC is a register or
13736 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13737 Otherwise return zero. */
13740 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13745 && (REG_P (x
) || MEM_P (x
))
13746 && ! reg_mentioned_p (x
, (rtx
) expr
))
13751 /* Check for any register or memory mentioned in EQUIV that is not
13752 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13753 of EXPR where some registers may have been replaced by constants. */
13756 unmentioned_reg_p (rtx equiv
, rtx expr
)
13758 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13761 DEBUG_FUNCTION
void
13762 dump_combine_stats (FILE *file
)
13766 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13767 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13771 dump_combine_total_stats (FILE *file
)
13775 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13776 total_attempts
, total_merges
, total_extras
, total_successes
);
13780 gate_handle_combine (void)
13782 return (optimize
> 0);
13785 /* Try combining insns through substitution. */
13786 static unsigned int
13787 rest_of_handle_combine (void)
13789 int rebuild_jump_labels_after_combine
;
13791 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13792 df_note_add_problem ();
13795 regstat_init_n_sets_and_refs ();
13797 rebuild_jump_labels_after_combine
13798 = combine_instructions (get_insns (), max_reg_num ());
13800 /* Combining insns may have turned an indirect jump into a
13801 direct jump. Rebuild the JUMP_LABEL fields of jumping
13803 if (rebuild_jump_labels_after_combine
)
13805 timevar_push (TV_JUMP
);
13806 rebuild_jump_labels (get_insns ());
13808 timevar_pop (TV_JUMP
);
13811 regstat_free_n_sets_and_refs ();
13815 struct rtl_opt_pass pass_combine
=
13819 "combine", /* name */
13820 gate_handle_combine
, /* gate */
13821 rest_of_handle_combine
, /* execute */
13824 0, /* static_pass_number */
13825 TV_COMBINE
, /* tv_id */
13826 PROP_cfglayout
, /* properties_required */
13827 0, /* properties_provided */
13828 0, /* properties_destroyed */
13829 0, /* todo_flags_start */
13830 TODO_df_finish
| TODO_verify_rtl_sharing
|
13831 TODO_ggc_collect
, /* todo_flags_finish */