1 ; Options of Andes NDS32 cpu for GNU compiler
2 ; Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 ; Contributed by Andes Technology Corporation.
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8 ; under the terms of the GNU General Public License as published
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15 ; License for more details.
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22 config/nds32/nds32-opts.h
24 ; ---------------------------------------------------------------
25 ; The following options are designed for aliasing and compatibility options.
28 Target RejectNegative Alias(mbig-endian)
29 Generate code in big-endian mode.
32 Target RejectNegative Alias(mlittle-endian)
33 Generate code in little-endian mode.
36 ; ---------------------------------------------------------------
39 Target RejectNegative Joined Enum(abi_type) Var(nds32_abi) Init(TARGET_DEFAULT_ABI)
40 Specify which ABI type to generate code for: 2, 2fp+.
43 Name(abi_type) Type(enum abi_type)
44 Known ABIs (for use with the -mabi= option):
47 Enum(abi_type) String(2) Value(NDS32_ABI_V2)
50 Enum(abi_type) String(2fp+) Value(NDS32_ABI_V2_FP_PLUS)
53 Target RejectNegative Alias(mabi=, 2)
54 Specify use soft floating point ABI which mean alias to -mabi=2.
57 Target RejectNegative Alias(mabi=, 2fp+)
58 Specify use soft floating point ABI which mean alias to -mabi=2fp+.
60 ; ---------------------------------------------------------------
63 Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
64 Use reduced-set registers for register allocation.
67 Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
68 Use full-set registers for register allocation.
70 ; ---------------------------------------------------------------
73 Target Mask(ALWAYS_ALIGN)
74 Always align function entry, jump target and return address.
77 Target Mask(ALIGN_FUNCTION)
78 Align function entry to 4 byte.
81 Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
82 Generate code in big-endian mode.
85 Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
86 Generate code in little-endian mode.
90 Target Report Mask(CMOV)
91 Generate conditional move instructions.
94 Target Report Mask(EXT_PERF)
95 Generate performance extension instructions.
98 Target Report Mask(EXT_PERF2)
99 Generate performance extension version 2 instructions.
102 Target Report Mask(EXT_STRING)
103 Generate string extension instructions.
106 Target Report Mask(V3PUSH)
107 Generate v3 push25/pop25 instructions.
110 Target Report Mask(16_BIT)
111 Generate 16-bit instructions.
114 Target Report Mask(RELAX_HINT)
115 Insert relax hint for linker to do relaxation.
118 Target Report Mask(VH)
119 Enable Virtual Hosting support.
122 Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
123 Specify the size of each interrupt vector, which must be 4 or 16.
126 Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
127 Specify the size of each cache block, which must be a power of 2 between 4 and 512.
130 Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
131 Specify the name of the target architecture.
134 Name(nds32_arch_type) Type(enum nds32_arch_type)
135 Known arch types (for use with the -march= option):
138 Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
141 Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
144 Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
147 Enum(nds32_arch_type) String(v3f) Value(ARCH_V3F)
150 Enum(nds32_arch_type) String(v3s) Value(ARCH_V3S)
153 Target RejectNegative Joined Enum(nds32_cmodel_type) Var(nds32_cmodel_option) Init(CMODEL_LARGE)
154 Specify the address generation strategy for code model.
157 Name(nds32_cmodel_type) Type(enum nds32_cmodel_type)
158 Known cmodel types (for use with the -mcmodel= option):
161 Enum(nds32_cmodel_type) String(small) Value(CMODEL_SMALL)
164 Enum(nds32_cmodel_type) String(medium) Value(CMODEL_MEDIUM)
167 Enum(nds32_cmodel_type) String(large) Value(CMODEL_LARGE)
170 Target RejectNegative Joined Enum(nds32_cpu_type) Var(nds32_cpu_option) Init(CPU_N9)
171 Specify the cpu for pipeline model.
174 Name(nds32_cpu_type) Type(enum nds32_cpu_type)
175 Known cpu types (for use with the -mcpu= option):
178 Enum(nds32_cpu_type) String(n6) Value(CPU_N6)
181 Enum(nds32_cpu_type) String(n650) Value(CPU_N6)
184 Enum(nds32_cpu_type) String(n7) Value(CPU_N7)
187 Enum(nds32_cpu_type) String(n705) Value(CPU_N7)
190 Enum(nds32_cpu_type) String(n8) Value(CPU_N8)
193 Enum(nds32_cpu_type) String(n801) Value(CPU_N8)
196 Enum(nds32_cpu_type) String(sn8) Value(CPU_N8)
199 Enum(nds32_cpu_type) String(sn801) Value(CPU_N8)
202 Enum(nds32_cpu_type) String(s8) Value(CPU_N8)
205 Enum(nds32_cpu_type) String(s801) Value(CPU_N8)
208 Enum(nds32_cpu_type) String(e8) Value(CPU_E8)
211 Enum(nds32_cpu_type) String(e801) Value(CPU_E8)
214 Enum(nds32_cpu_type) String(n820) Value(CPU_E8)
217 Enum(nds32_cpu_type) String(s830) Value(CPU_E8)
220 Enum(nds32_cpu_type) String(e830) Value(CPU_E8)
223 Enum(nds32_cpu_type) String(n9) Value(CPU_N9)
226 Enum(nds32_cpu_type) String(n903) Value(CPU_N9)
229 Enum(nds32_cpu_type) String(n903a) Value(CPU_N9)
232 Enum(nds32_cpu_type) String(n968) Value(CPU_N9)
235 Enum(nds32_cpu_type) String(n968a) Value(CPU_N9)
238 Enum(nds32_cpu_type) String(simple) Value(CPU_SIMPLE)
241 Target RejectNegative Joined Enum(float_reg_number) Var(nds32_fp_regnum) Init(TARGET_CONFIG_FPU_DEFAULT)
242 Specify a fpu configuration value from 0 to 7; 0-3 is as FPU spec says, and 4-7 is corresponding to 0-3.
245 Name(float_reg_number) Type(enum float_reg_number)
246 Known floating-point number of registers (for use with the -mconfig-fpu= option):
249 Enum(float_reg_number) String(0) Value(NDS32_CONFIG_FPU_0)
252 Enum(float_reg_number) String(1) Value(NDS32_CONFIG_FPU_1)
255 Enum(float_reg_number) String(2) Value(NDS32_CONFIG_FPU_2)
258 Enum(float_reg_number) String(3) Value(NDS32_CONFIG_FPU_3)
261 Enum(float_reg_number) String(4) Value(NDS32_CONFIG_FPU_4)
264 Enum(float_reg_number) String(5) Value(NDS32_CONFIG_FPU_5)
267 Enum(float_reg_number) String(6) Value(NDS32_CONFIG_FPU_6)
270 Enum(float_reg_number) String(7) Value(NDS32_CONFIG_FPU_7)
273 Target RejectNegative Joined Enum(nds32_mul_type) Var(nds32_mul_config) Init(MUL_TYPE_FAST_1)
274 Specify configuration of instruction mul: fast1, fast2 or slow. The default is fast1.
277 Name(nds32_mul_type) Type(enum nds32_mul_type)
280 Enum(nds32_mul_type) String(fast) Value(MUL_TYPE_FAST_1)
283 Enum(nds32_mul_type) String(fast1) Value(MUL_TYPE_FAST_1)
286 Enum(nds32_mul_type) String(fast2) Value(MUL_TYPE_FAST_2)
289 Enum(nds32_mul_type) String(slow) Value(MUL_TYPE_SLOW)
291 mconfig-register-ports=
292 Target RejectNegative Joined Enum(nds32_register_ports) Var(nds32_register_ports_config) Init(REG_PORT_3R2W)
293 Specify how many read/write ports for n9/n10 cores. The value should be 3r2w or 2r1w.
296 Name(nds32_register_ports) Type(enum nds32_register_ports)
299 Enum(nds32_register_ports) String(3r2w) Value(REG_PORT_3R2W)
302 Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)
306 Enable constructor/destructor feature.
310 Guide linker to relax instructions.
313 Target Report Mask(EXT_FPU_FMA)
314 Generate floating-point multiply-accumulation instructions.
317 Target Report Mask(FPU_SINGLE)
318 Generate single-precision floating-point instructions.
321 Target Report Mask(FPU_DOUBLE)
322 Generate double-precision floating-point instructions.
325 Target Report Var(flag_unaligned_access) Init(0)
326 Enable unaligned word and halfword accesses to packed data.