1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (STACK_POINTER_REGNUM 1)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
38 (ARG_POINTER_REGNUM 67)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
55 (FRAME_POINTER_REGNUM 113)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
114 UNSPEC_MACHOPIC_OFFSET
126 UNSPEC_P8V_RELOAD_FROM_GPR
129 UNSPEC_P8V_RELOAD_FROM_VSX
144 ;; UNSPEC_VOLATILE usage
147 (define_c_enum "unspecv"
149 UNSPECV_LL ; load-locked
150 UNSPECV_SC ; store-conditional
151 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
152 UNSPECV_EH_RR ; eh_reg_restore
153 UNSPECV_ISYNC ; isync instruction
154 UNSPECV_MFTB ; move from time base
155 UNSPECV_NLGR ; non-local goto receiver
156 UNSPECV_MFFS ; Move from FPSCR
157 UNSPECV_MTFSF ; Move to FPSCR Fields
161 ;; Define an insn type attribute. This is used in function unit delay
165 add,logical,shift,insert,
167 exts,cntlz,popcnt,isel,
168 load,store,fpload,fpstore,vecload,vecstore,
170 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
172 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
173 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
175 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
176 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
178 (const_string "integer"))
180 ;; What data size does this instruction work on?
181 ;; This is used for insert, mul.
182 (define_attr "size" "8,16,32,64" (const_string "32"))
184 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
185 ;; This is used for add, logical, shift, exts, mul.
186 (define_attr "dot" "no,yes" (const_string "no"))
188 ;; Does this instruction sign-extend its result?
189 ;; This is used for load insns.
190 (define_attr "sign_extend" "no,yes" (const_string "no"))
192 ;; Does this instruction use indexed (that is, reg+reg) addressing?
193 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
194 ;; it is automatically set based on that. If a load or store instruction
195 ;; has fewer than two operands it needs to set this attribute manually
196 ;; or the compiler will crash.
197 (define_attr "indexed" "no,yes"
198 (if_then_else (ior (match_operand 0 "indexed_address_mem")
199 (match_operand 1 "indexed_address_mem"))
201 (const_string "no")))
203 ;; Does this instruction use update addressing?
204 ;; This is used for load and store insns. See the comments for "indexed".
205 (define_attr "update" "no,yes"
206 (if_then_else (ior (match_operand 0 "update_address_mem")
207 (match_operand 1 "update_address_mem"))
209 (const_string "no")))
211 ;; Is this instruction using operands[2] as shift amount, and can that be a
213 ;; This is used for shift insns.
214 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
216 ;; Is this instruction using a shift amount from a register?
217 ;; This is used for shift insns.
218 (define_attr "var_shift" "no,yes"
219 (if_then_else (and (eq_attr "type" "shift")
220 (eq_attr "maybe_var_shift" "yes"))
221 (if_then_else (match_operand 2 "gpc_reg_operand")
224 (const_string "no")))
226 ;; Define floating point instruction sub-types for use with Xfpu.md
227 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
229 ;; Length (in bytes).
230 ; '(pc)' in the following doesn't include the instruction itself; it is
231 ; calculated as if the instruction had zero size.
232 (define_attr "length" ""
233 (if_then_else (eq_attr "type" "branch")
234 (if_then_else (and (ge (minus (match_dup 0) (pc))
236 (lt (minus (match_dup 0) (pc))
242 ;; Processor type -- this attribute must exactly match the processor_type
243 ;; enumeration in rs6000-opts.h.
245 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
246 ppc750,ppc7400,ppc7450,
247 ppc403,ppc405,ppc440,ppc476,
248 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
249 power4,power5,power6,power7,power8,
250 rs64a,mpccore,cell,ppca2,titan"
251 (const (symbol_ref "rs6000_cpu_attr")))
254 ;; If this instruction is microcoded on the CELL processor
255 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
256 (define_attr "cell_micro" "not,conditional,always"
257 (if_then_else (ior (eq_attr "type" "compare")
258 (and (eq_attr "type" "shift,exts,mul")
259 (eq_attr "dot" "yes"))
260 (and (eq_attr "type" "load")
261 (eq_attr "sign_extend" "yes"))
262 (and (eq_attr "type" "shift")
263 (eq_attr "var_shift" "yes")))
264 (const_string "always")
265 (const_string "not")))
267 (automata_option "ndfa")
280 (include "e300c2c3.md")
281 (include "e500mc.md")
282 (include "e500mc64.md")
285 (include "power4.md")
286 (include "power5.md")
287 (include "power6.md")
288 (include "power7.md")
289 (include "power8.md")
295 (include "predicates.md")
296 (include "constraints.md")
298 (include "darwin.md")
303 ; This mode iterator allows :GPR to be used to indicate the allowable size
304 ; of whole values in GPRs.
305 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
307 ; Any supported integer mode.
308 (define_mode_iterator INT [QI HI SI DI TI PTI])
310 ; Any supported integer mode that fits in one register.
311 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
313 ; Everything we can extend QImode to.
314 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
316 ; Everything we can extend HImode to.
317 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
319 ; Everything we can extend SImode to.
320 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
322 ; QImode or HImode for small atomic ops
323 (define_mode_iterator QHI [QI HI])
325 ; HImode or SImode for sign extended fusion ops
326 (define_mode_iterator HSI [HI SI])
328 ; SImode or DImode, even if DImode doesn't fit in GPRs.
329 (define_mode_iterator SDI [SI DI])
331 ; The size of a pointer. Also, the size of the value that a record-condition
332 ; (one with a '.') will compare; and the size used for arithmetic carries.
333 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
335 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
336 ; PTImode is GPR only)
337 (define_mode_iterator TI2 [TI PTI])
339 ; Any hardware-supported floating-point mode
340 (define_mode_iterator FP [
341 (SF "TARGET_HARD_FLOAT
342 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
343 (DF "TARGET_HARD_FLOAT
344 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
345 (TF "!TARGET_IEEEQUAD
347 && (TARGET_FPRS || TARGET_E500_DOUBLE)
348 && TARGET_LONG_DOUBLE_128")
352 ; Any fma capable floating-point mode.
353 (define_mode_iterator FMA_F [
354 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
355 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
356 || VECTOR_UNIT_VSX_P (DFmode)")
357 (V2SF "TARGET_PAIRED_FLOAT")
358 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
359 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
362 ; Floating point move iterators to combine binary and decimal moves
363 (define_mode_iterator FMOVE32 [SF SD])
364 (define_mode_iterator FMOVE64 [DF DD])
365 (define_mode_iterator FMOVE64X [DI DF DD])
366 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
367 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
369 ; Iterators for 128 bit types for direct move
370 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
379 ; Whether a floating point move is ok, don't allow SD without hardware FP
380 (define_mode_attr fmove_ok [(SF "")
382 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
385 ; Convert REAL_VALUE to the appropriate bits
386 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
387 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
388 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
389 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
391 ; Definitions for load to 32-bit fpr register
392 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
393 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
394 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
395 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
397 ; Definitions for store from 32-bit fpr register
398 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
399 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
400 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
401 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
403 ; Definitions for 32-bit fpr direct move
404 ; At present, the decimal modes are not allowed in the traditional altivec
405 ; registers, so restrict the constraints to just the traditional FPRs.
406 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
408 ; Definitions for 32-bit VSX
409 (define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
411 ; Definitions for 32-bit use of altivec registers
412 (define_mode_attr f32_av [(SF "wu") (SD "wn")])
414 ; Definitions for 64-bit VSX
415 (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
417 ; Definitions for 64-bit direct move
418 (define_mode_attr f64_dm [(DF "wk") (DD "wh")])
420 ; Definitions for 64-bit use of altivec registers
421 (define_mode_attr f64_av [(DF "wv") (DD "wn")])
423 ; These modes do not fit in integer registers in 32-bit mode.
424 ; but on e500v2, the gpr are 64 bit registers
425 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
427 ; Iterator for reciprocal estimate instructions
428 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
430 ; Iterator for just SF/DF
431 (define_mode_iterator SFDF [SF DF])
433 ; SF/DF suffix for traditional floating instructions
434 (define_mode_attr Ftrad [(SF "s") (DF "")])
436 ; SF/DF suffix for VSX instructions
437 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
439 ; SF/DF constraint for arithmetic on traditional floating point registers
440 (define_mode_attr Ff [(SF "f") (DF "d")])
442 ; SF/DF constraint for arithmetic on VSX registers
443 (define_mode_attr Fv [(SF "wy") (DF "ws")])
445 ; SF/DF constraint for arithmetic on altivec registers
446 (define_mode_attr Fa [(SF "wu") (DF "wv")])
448 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
449 (define_mode_attr Fs [(SF "s") (DF "d")])
452 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
453 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
455 ; Conditional returns.
456 (define_code_iterator any_return [return simple_return])
457 (define_code_attr return_pred [(return "direct_return ()")
458 (simple_return "1")])
459 (define_code_attr return_str [(return "") (simple_return "simple_")])
462 (define_code_iterator iorxor [ior xor])
464 ; Signed/unsigned variants of ops.
465 (define_code_iterator any_extend [sign_extend zero_extend])
466 (define_code_attr u [(sign_extend "") (zero_extend "u")])
467 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
469 ; Various instructions that come in SI and DI forms.
470 ; A generic w/d attribute, for things like cmpw/cmpd.
471 (define_mode_attr wd [(QI "b")
480 ;; How many bits in this mode?
481 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
484 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
486 ;; ISEL/ISEL64 target selection
487 (define_mode_attr sel [(SI "") (DI "64")])
489 ;; Bitmask for shift instructions
490 (define_mode_attr hH [(SI "h") (DI "H")])
492 ;; A mode twice the size of the given mode
493 (define_mode_attr dmode [(SI "di") (DI "ti")])
494 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
496 ;; Suffix for reload patterns
497 (define_mode_attr ptrsize [(SI "32bit")
500 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
501 (DI "TARGET_64BIT")])
503 (define_mode_attr mptrsize [(SI "si")
506 (define_mode_attr ptrload [(SI "lwz")
509 (define_mode_attr ptrm [(SI "m")
512 (define_mode_attr rreg [(SF "f")
519 (define_mode_attr rreg2 [(SF "f")
522 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
523 (DF "TARGET_FCFID")])
525 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
526 (DF "TARGET_E500_DOUBLE")])
528 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
529 (DF "TARGET_DOUBLE_FLOAT")])
531 ;; Mode iterator for logical operations on 128-bit types
532 (define_mode_iterator BOOL_128 [TI
534 (V16QI "TARGET_ALTIVEC")
535 (V8HI "TARGET_ALTIVEC")
536 (V4SI "TARGET_ALTIVEC")
537 (V4SF "TARGET_ALTIVEC")
538 (V2DI "TARGET_ALTIVEC")
539 (V2DF "TARGET_ALTIVEC")
540 (V1TI "TARGET_ALTIVEC")])
542 ;; For the GPRs we use 3 constraints for register outputs, two that are the
543 ;; same as the output register, and a third where the output register is an
544 ;; early clobber, so we don't have to deal with register overlaps. For the
545 ;; vector types, we prefer to use the vector registers. For TI mode, allow
548 ;; Mode attribute for boolean operation register constraints for output
549 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
551 (V16QI "wa,v,&?r,?r,?r")
552 (V8HI "wa,v,&?r,?r,?r")
553 (V4SI "wa,v,&?r,?r,?r")
554 (V4SF "wa,v,&?r,?r,?r")
555 (V2DI "wa,v,&?r,?r,?r")
556 (V2DF "wa,v,&?r,?r,?r")
557 (V1TI "wa,v,&?r,?r,?r")])
559 ;; Mode attribute for boolean operation register constraints for operand1
560 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
568 (V1TI "wa,v,r,0,r")])
570 ;; Mode attribute for boolean operation register constraints for operand2
571 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
579 (V1TI "wa,v,r,r,0")])
581 ;; Mode attribute for boolean operation register constraints for operand1
582 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
583 ;; is used for operand1 or operand2
584 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
592 (V1TI "wa,v,r,0,0")])
594 ;; Reload iterator for creating the function to allocate a base register to
595 ;; supplement addressing modes.
596 (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
597 SF SD SI DF DD DI TI PTI])
600 ;; Start with fixed-point load and store insns. Here we put only the more
601 ;; complex forms. Basic data transfer is done later.
603 (define_insn "zero_extendqi<mode>2"
604 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
605 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
610 [(set_attr "type" "load,shift")])
612 (define_insn_and_split "*zero_extendqi<mode>2_dot"
613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
614 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
616 (clobber (match_scratch:EXTQI 0 "=r,r"))]
617 "rs6000_gen_cell_microcode"
621 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
623 (zero_extend:EXTQI (match_dup 1)))
625 (compare:CC (match_dup 0)
628 [(set_attr "type" "logical")
629 (set_attr "dot" "yes")
630 (set_attr "length" "4,8")])
632 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
633 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
634 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
636 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
637 (zero_extend:EXTQI (match_dup 1)))]
638 "rs6000_gen_cell_microcode"
642 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
644 (zero_extend:EXTQI (match_dup 1)))
646 (compare:CC (match_dup 0)
649 [(set_attr "type" "logical")
650 (set_attr "dot" "yes")
651 (set_attr "length" "4,8")])
654 (define_insn "zero_extendhi<mode>2"
655 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
656 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
660 rlwinm %0,%1,0,0xffff"
661 [(set_attr "type" "load,shift")])
663 (define_insn_and_split "*zero_extendhi<mode>2_dot"
664 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
665 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
667 (clobber (match_scratch:EXTHI 0 "=r,r"))]
668 "rs6000_gen_cell_microcode"
672 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
674 (zero_extend:EXTHI (match_dup 1)))
676 (compare:CC (match_dup 0)
679 [(set_attr "type" "logical")
680 (set_attr "dot" "yes")
681 (set_attr "length" "4,8")])
683 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
684 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
685 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
687 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
688 (zero_extend:EXTHI (match_dup 1)))]
689 "rs6000_gen_cell_microcode"
693 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
695 (zero_extend:EXTHI (match_dup 1)))
697 (compare:CC (match_dup 0)
700 [(set_attr "type" "logical")
701 (set_attr "dot" "yes")
702 (set_attr "length" "4,8")])
705 (define_insn "zero_extendsi<mode>2"
706 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
707 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
715 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
717 (define_insn_and_split "*zero_extendsi<mode>2_dot"
718 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
719 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
721 (clobber (match_scratch:EXTSI 0 "=r,r"))]
722 "rs6000_gen_cell_microcode"
726 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
728 (zero_extend:DI (match_dup 1)))
730 (compare:CC (match_dup 0)
733 [(set_attr "type" "shift")
734 (set_attr "dot" "yes")
735 (set_attr "length" "4,8")])
737 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
738 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
739 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
741 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
742 (zero_extend:EXTSI (match_dup 1)))]
743 "rs6000_gen_cell_microcode"
747 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
749 (zero_extend:EXTSI (match_dup 1)))
751 (compare:CC (match_dup 0)
754 [(set_attr "type" "shift")
755 (set_attr "dot" "yes")
756 (set_attr "length" "4,8")])
759 (define_insn "extendqi<mode>2"
760 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
761 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
764 [(set_attr "type" "exts")])
766 (define_insn_and_split "*extendqi<mode>2_dot"
767 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
768 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
770 (clobber (match_scratch:EXTQI 0 "=r,r"))]
771 "rs6000_gen_cell_microcode"
775 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
777 (sign_extend:EXTQI (match_dup 1)))
779 (compare:CC (match_dup 0)
782 [(set_attr "type" "exts")
783 (set_attr "dot" "yes")
784 (set_attr "length" "4,8")])
786 (define_insn_and_split "*extendqi<mode>2_dot2"
787 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
788 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
790 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
791 (sign_extend:EXTQI (match_dup 1)))]
792 "rs6000_gen_cell_microcode"
796 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
798 (sign_extend:EXTQI (match_dup 1)))
800 (compare:CC (match_dup 0)
803 [(set_attr "type" "exts")
804 (set_attr "dot" "yes")
805 (set_attr "length" "4,8")])
808 (define_expand "extendhi<mode>2"
809 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
810 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
814 (define_insn "*extendhi<mode>2"
815 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
816 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
817 "rs6000_gen_cell_microcode"
821 [(set_attr "type" "load,exts")
822 (set_attr "sign_extend" "yes")])
824 (define_insn "*extendhi<mode>2_noload"
825 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
826 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
827 "!rs6000_gen_cell_microcode"
829 [(set_attr "type" "exts")])
831 (define_insn_and_split "*extendhi<mode>2_dot"
832 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
833 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
835 (clobber (match_scratch:EXTHI 0 "=r,r"))]
836 "rs6000_gen_cell_microcode"
840 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
842 (sign_extend:EXTHI (match_dup 1)))
844 (compare:CC (match_dup 0)
847 [(set_attr "type" "exts")
848 (set_attr "dot" "yes")
849 (set_attr "length" "4,8")])
851 (define_insn_and_split "*extendhi<mode>2_dot2"
852 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
853 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
855 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
856 (sign_extend:EXTHI (match_dup 1)))]
857 "rs6000_gen_cell_microcode"
861 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
863 (sign_extend:EXTHI (match_dup 1)))
865 (compare:CC (match_dup 0)
868 [(set_attr "type" "exts")
869 (set_attr "dot" "yes")
870 (set_attr "length" "4,8")])
873 (define_insn "extendsi<mode>2"
874 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
875 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
883 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
884 (set_attr "sign_extend" "yes")])
886 (define_insn_and_split "*extendsi<mode>2_dot"
887 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
888 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
890 (clobber (match_scratch:EXTSI 0 "=r,r"))]
891 "rs6000_gen_cell_microcode"
895 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
897 (sign_extend:EXTSI (match_dup 1)))
899 (compare:CC (match_dup 0)
902 [(set_attr "type" "exts")
903 (set_attr "dot" "yes")
904 (set_attr "length" "4,8")])
906 (define_insn_and_split "*extendsi<mode>2_dot2"
907 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
908 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
910 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
911 (sign_extend:EXTSI (match_dup 1)))]
912 "rs6000_gen_cell_microcode"
916 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
918 (sign_extend:EXTSI (match_dup 1)))
920 (compare:CC (match_dup 0)
923 [(set_attr "type" "exts")
924 (set_attr "dot" "yes")
925 (set_attr "length" "4,8")])
927 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
929 (define_insn "*macchwc"
930 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
931 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
932 (match_operand:SI 2 "gpc_reg_operand" "r")
935 (match_operand:HI 1 "gpc_reg_operand" "r")))
936 (match_operand:SI 4 "gpc_reg_operand" "0"))
938 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
939 (plus:SI (mult:SI (ashiftrt:SI
947 [(set_attr "type" "halfmul")])
949 (define_insn "*macchw"
950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
951 (plus:SI (mult:SI (ashiftrt:SI
952 (match_operand:SI 2 "gpc_reg_operand" "r")
955 (match_operand:HI 1 "gpc_reg_operand" "r")))
956 (match_operand:SI 3 "gpc_reg_operand" "0")))]
959 [(set_attr "type" "halfmul")])
961 (define_insn "*macchwuc"
962 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
963 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
964 (match_operand:SI 2 "gpc_reg_operand" "r")
967 (match_operand:HI 1 "gpc_reg_operand" "r")))
968 (match_operand:SI 4 "gpc_reg_operand" "0"))
970 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
971 (plus:SI (mult:SI (lshiftrt:SI
979 [(set_attr "type" "halfmul")])
981 (define_insn "*macchwu"
982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
983 (plus:SI (mult:SI (lshiftrt:SI
984 (match_operand:SI 2 "gpc_reg_operand" "r")
987 (match_operand:HI 1 "gpc_reg_operand" "r")))
988 (match_operand:SI 3 "gpc_reg_operand" "0")))]
991 [(set_attr "type" "halfmul")])
993 (define_insn "*machhwc"
994 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
995 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
996 (match_operand:SI 1 "gpc_reg_operand" "%r")
999 (match_operand:SI 2 "gpc_reg_operand" "r")
1001 (match_operand:SI 4 "gpc_reg_operand" "0"))
1003 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1004 (plus:SI (mult:SI (ashiftrt:SI
1013 [(set_attr "type" "halfmul")])
1015 (define_insn "*machhw"
1016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1017 (plus:SI (mult:SI (ashiftrt:SI
1018 (match_operand:SI 1 "gpc_reg_operand" "%r")
1021 (match_operand:SI 2 "gpc_reg_operand" "r")
1023 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1026 [(set_attr "type" "halfmul")])
1028 (define_insn "*machhwuc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1036 (match_operand:SI 4 "gpc_reg_operand" "0"))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1039 (plus:SI (mult:SI (lshiftrt:SI
1048 [(set_attr "type" "halfmul")])
1050 (define_insn "*machhwu"
1051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (lshiftrt:SI
1053 (match_operand:SI 1 "gpc_reg_operand" "%r")
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1058 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1061 [(set_attr "type" "halfmul")])
1063 (define_insn "*maclhwc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1066 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1068 (match_operand:HI 2 "gpc_reg_operand" "r")))
1069 (match_operand:SI 4 "gpc_reg_operand" "0"))
1071 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1072 (plus:SI (mult:SI (sign_extend:SI
1079 [(set_attr "type" "halfmul")])
1081 (define_insn "*maclhw"
1082 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1083 (plus:SI (mult:SI (sign_extend:SI
1084 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1086 (match_operand:HI 2 "gpc_reg_operand" "r")))
1087 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1090 [(set_attr "type" "halfmul")])
1092 (define_insn "*maclhwuc"
1093 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1094 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1095 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1097 (match_operand:HI 2 "gpc_reg_operand" "r")))
1098 (match_operand:SI 4 "gpc_reg_operand" "0"))
1100 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (zero_extend:SI
1108 [(set_attr "type" "halfmul")])
1110 (define_insn "*maclhwu"
1111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1112 (plus:SI (mult:SI (zero_extend:SI
1113 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1115 (match_operand:HI 2 "gpc_reg_operand" "r")))
1116 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1119 [(set_attr "type" "halfmul")])
1121 (define_insn "*nmacchwc"
1122 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1123 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1124 (mult:SI (ashiftrt:SI
1125 (match_operand:SI 2 "gpc_reg_operand" "r")
1128 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1130 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (minus:SI (match_dup 4)
1132 (mult:SI (ashiftrt:SI
1139 [(set_attr "type" "halfmul")])
1141 (define_insn "*nmacchw"
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1143 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1144 (mult:SI (ashiftrt:SI
1145 (match_operand:SI 2 "gpc_reg_operand" "r")
1148 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1151 [(set_attr "type" "halfmul")])
1153 (define_insn "*nmachhwc"
1154 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1155 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1156 (mult:SI (ashiftrt:SI
1157 (match_operand:SI 1 "gpc_reg_operand" "%r")
1160 (match_operand:SI 2 "gpc_reg_operand" "r")
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (minus:SI (match_dup 4)
1165 (mult:SI (ashiftrt:SI
1173 [(set_attr "type" "halfmul")])
1175 (define_insn "*nmachhw"
1176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1177 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1178 (mult:SI (ashiftrt:SI
1179 (match_operand:SI 1 "gpc_reg_operand" "%r")
1182 (match_operand:SI 2 "gpc_reg_operand" "r")
1186 [(set_attr "type" "halfmul")])
1188 (define_insn "*nmaclhwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1191 (mult:SI (sign_extend:SI
1192 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1194 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1196 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1197 (minus:SI (match_dup 4)
1198 (mult:SI (sign_extend:SI
1204 [(set_attr "type" "halfmul")])
1206 (define_insn "*nmaclhw"
1207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1208 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1209 (mult:SI (sign_extend:SI
1210 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1212 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1215 [(set_attr "type" "halfmul")])
1217 (define_insn "*mulchwc"
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1219 (compare:CC (mult:SI (ashiftrt:SI
1220 (match_operand:SI 2 "gpc_reg_operand" "r")
1223 (match_operand:HI 1 "gpc_reg_operand" "r")))
1225 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (mult:SI (ashiftrt:SI
1233 [(set_attr "type" "halfmul")])
1235 (define_insn "*mulchw"
1236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1237 (mult:SI (ashiftrt:SI
1238 (match_operand:SI 2 "gpc_reg_operand" "r")
1241 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1244 [(set_attr "type" "halfmul")])
1246 (define_insn "*mulchwuc"
1247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248 (compare:CC (mult:SI (lshiftrt:SI
1249 (match_operand:SI 2 "gpc_reg_operand" "r")
1252 (match_operand:HI 1 "gpc_reg_operand" "r")))
1254 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (lshiftrt:SI
1262 [(set_attr "type" "halfmul")])
1264 (define_insn "*mulchwu"
1265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (mult:SI (lshiftrt:SI
1267 (match_operand:SI 2 "gpc_reg_operand" "r")
1270 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1273 [(set_attr "type" "halfmul")])
1275 (define_insn "*mulhhwc"
1276 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1277 (compare:CC (mult:SI (ashiftrt:SI
1278 (match_operand:SI 1 "gpc_reg_operand" "%r")
1281 (match_operand:SI 2 "gpc_reg_operand" "r")
1284 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1285 (mult:SI (ashiftrt:SI
1293 [(set_attr "type" "halfmul")])
1295 (define_insn "*mulhhw"
1296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (mult:SI (ashiftrt:SI
1298 (match_operand:SI 1 "gpc_reg_operand" "%r")
1301 (match_operand:SI 2 "gpc_reg_operand" "r")
1305 [(set_attr "type" "halfmul")])
1307 (define_insn "*mulhhwuc"
1308 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1309 (compare:CC (mult:SI (lshiftrt:SI
1310 (match_operand:SI 1 "gpc_reg_operand" "%r")
1313 (match_operand:SI 2 "gpc_reg_operand" "r")
1316 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1317 (mult:SI (lshiftrt:SI
1325 [(set_attr "type" "halfmul")])
1327 (define_insn "*mulhhwu"
1328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1329 (mult:SI (lshiftrt:SI
1330 (match_operand:SI 1 "gpc_reg_operand" "%r")
1333 (match_operand:SI 2 "gpc_reg_operand" "r")
1337 [(set_attr "type" "halfmul")])
1339 (define_insn "*mullhwc"
1340 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1341 (compare:CC (mult:SI (sign_extend:SI
1342 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1344 (match_operand:HI 2 "gpc_reg_operand" "r")))
1346 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1347 (mult:SI (sign_extend:SI
1353 [(set_attr "type" "halfmul")])
1355 (define_insn "*mullhw"
1356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (mult:SI (sign_extend:SI
1358 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1360 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1363 [(set_attr "type" "halfmul")])
1365 (define_insn "*mullhwuc"
1366 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1367 (compare:CC (mult:SI (zero_extend:SI
1368 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1370 (match_operand:HI 2 "gpc_reg_operand" "r")))
1372 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1373 (mult:SI (zero_extend:SI
1379 [(set_attr "type" "halfmul")])
1381 (define_insn "*mullhwu"
1382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1383 (mult:SI (zero_extend:SI
1384 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1386 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1389 [(set_attr "type" "halfmul")])
1391 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1392 (define_insn "dlmzb"
1393 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1394 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1395 (match_operand:SI 2 "gpc_reg_operand" "r")]
1397 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1398 (unspec:SI [(match_dup 1)
1404 (define_expand "strlensi"
1405 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1406 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1407 (match_operand:QI 2 "const_int_operand" "")
1408 (match_operand 3 "const_int_operand" "")]
1409 UNSPEC_DLMZB_STRLEN))
1410 (clobber (match_scratch:CC 4 "=x"))]
1411 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1413 rtx result = operands[0];
1414 rtx src = operands[1];
1415 rtx search_char = operands[2];
1416 rtx align = operands[3];
1417 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1418 rtx loop_label, end_label, mem, cr0, cond;
1419 if (search_char != const0_rtx
1420 || GET_CODE (align) != CONST_INT
1421 || INTVAL (align) < 8)
1423 word1 = gen_reg_rtx (SImode);
1424 word2 = gen_reg_rtx (SImode);
1425 scratch_dlmzb = gen_reg_rtx (SImode);
1426 scratch_string = gen_reg_rtx (Pmode);
1427 loop_label = gen_label_rtx ();
1428 end_label = gen_label_rtx ();
1429 addr = force_reg (Pmode, XEXP (src, 0));
1430 emit_move_insn (scratch_string, addr);
1431 emit_label (loop_label);
1432 mem = change_address (src, SImode, scratch_string);
1433 emit_move_insn (word1, mem);
1434 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1435 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1436 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1437 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1438 emit_jump_insn (gen_rtx_SET (VOIDmode,
1440 gen_rtx_IF_THEN_ELSE (VOIDmode,
1446 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1447 emit_jump_insn (gen_rtx_SET (VOIDmode,
1449 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1451 emit_label (end_label);
1452 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1453 emit_insn (gen_subsi3 (result, scratch_string, addr));
1454 emit_insn (gen_addsi3 (result, result, constm1_rtx));
1458 ;; Fixed-point arithmetic insns.
1460 (define_expand "add<mode>3"
1461 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1462 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1463 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1466 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1468 if (non_short_cint_operand (operands[2], DImode))
1471 else if (GET_CODE (operands[2]) == CONST_INT
1472 && ! add_operand (operands[2], <MODE>mode))
1474 rtx tmp = ((!can_create_pseudo_p ()
1475 || rtx_equal_p (operands[0], operands[1]))
1476 ? operands[0] : gen_reg_rtx (<MODE>mode));
1478 HOST_WIDE_INT val = INTVAL (operands[2]);
1479 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1480 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1482 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1485 /* The ordering here is important for the prolog expander.
1486 When space is allocated from the stack, adding 'low' first may
1487 produce a temporary deallocation (which would be bad). */
1488 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1489 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1494 ;; Discourage ai/addic because of carry but provide it in an alternative
1495 ;; allowing register zero as source.
1496 (define_insn "*add<mode>3_internal1"
1497 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1498 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1499 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1500 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1506 [(set_attr "type" "add")])
1508 (define_insn "addsi3_high"
1509 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1510 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1511 (high:SI (match_operand 2 "" ""))))]
1512 "TARGET_MACHO && !TARGET_64BIT"
1513 "addis %0,%1,ha16(%2)"
1514 [(set_attr "type" "add")])
1516 (define_insn "*add<mode>3_internal2"
1517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1518 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1519 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1521 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1528 [(set_attr "type" "add,compare,compare,compare")
1529 (set_attr "dot" "yes")
1530 (set_attr "length" "4,4,8,8")])
1533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1534 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1535 (match_operand:GPR 2 "reg_or_short_operand" ""))
1537 (clobber (match_scratch:GPR 3 ""))]
1540 (plus:GPR (match_dup 1)
1543 (compare:CC (match_dup 3)
1547 (define_insn "*add<mode>3_internal3"
1548 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1549 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1550 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1552 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1553 (plus:P (match_dup 1)
1561 [(set_attr "type" "add,compare,compare,compare")
1562 (set_attr "dot" "yes")
1563 (set_attr "length" "4,4,8,8")])
1566 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1568 (match_operand:P 2 "reg_or_short_operand" ""))
1570 (set (match_operand:P 0 "gpc_reg_operand" "")
1571 (plus:P (match_dup 1) (match_dup 2)))]
1574 (plus:P (match_dup 1)
1577 (compare:CC (match_dup 0)
1581 ;; Split an add that we can't do in one insn into two insns, each of which
1582 ;; does one 16-bit part. This is used by combine. Note that the low-order
1583 ;; add should be last in case the result gets used in an address.
1586 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1587 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1588 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1590 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1591 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1593 HOST_WIDE_INT val = INTVAL (operands[2]);
1594 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1595 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1597 operands[4] = GEN_INT (low);
1598 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1599 operands[3] = GEN_INT (rest);
1600 else if (can_create_pseudo_p ())
1602 operands[3] = gen_reg_rtx (DImode);
1603 emit_move_insn (operands[3], operands[2]);
1604 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1611 (define_expand "one_cmpl<mode>2"
1612 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1613 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1616 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1618 rs6000_split_logical (operands, NOT, false, false, false);
1623 (define_insn "*one_cmpl<mode>2"
1624 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1625 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1629 (define_insn_and_split "*one_cmpl<mode>2_dot"
1630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1631 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1633 (clobber (match_scratch:GPR 0 "=r,r"))]
1634 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1638 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1640 (not:GPR (match_dup 1)))
1642 (compare:CC (match_dup 0)
1645 [(set_attr "type" "logical")
1646 (set_attr "dot" "yes")
1647 (set_attr "length" "4,8")])
1649 (define_insn_and_split "*one_cmpl<mode>2_dot2"
1650 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1651 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1653 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1654 (not:GPR (match_dup 1)))]
1655 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1659 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1661 (not:GPR (match_dup 1)))
1663 (compare:CC (match_dup 0)
1666 [(set_attr "type" "logical")
1667 (set_attr "dot" "yes")
1668 (set_attr "length" "4,8")])
1671 (define_expand "sub<mode>3"
1672 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1673 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1674 (match_operand:SDI 2 "gpc_reg_operand" "")))]
1677 if (short_cint_operand (operands[1], <MODE>mode)
1678 && !(<MODE>mode == DImode && !TARGET_POWERPC64))
1680 emit_insn (gen_subf<mode>3_imm (operands[0], operands[2], operands[1]));
1685 (define_insn "*subf<mode>3"
1686 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1687 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")
1688 (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1691 [(set_attr "type" "add")])
1693 (define_insn_and_split "*subf<mode>3_dot"
1694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1695 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1696 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1698 (clobber (match_scratch:GPR 0 "=r,r"))]
1699 "<MODE>mode == Pmode"
1703 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1705 (minus:GPR (match_dup 2)
1708 (compare:CC (match_dup 0)
1711 [(set_attr "type" "add")
1712 (set_attr "dot" "yes")
1713 (set_attr "length" "4,8")])
1715 (define_insn_and_split "*subf<mode>3_dot2"
1716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1717 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1718 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1720 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1721 (minus:GPR (match_dup 2)
1723 "<MODE>mode == Pmode"
1727 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1729 (minus:GPR (match_dup 2)
1732 (compare:CC (match_dup 0)
1735 [(set_attr "type" "add")
1736 (set_attr "dot" "yes")
1737 (set_attr "length" "4,8")])
1739 (define_insn "subf<mode>3_imm"
1740 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1741 (minus:GPR (match_operand:GPR 2 "short_cint_operand" "I")
1742 (match_operand:GPR 1 "gpc_reg_operand" "r")))
1743 (clobber (reg:GPR CA_REGNO))]
1746 [(set_attr "type" "add")])
1749 (define_expand "neg<mode>2"
1750 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1751 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1755 (define_insn "*neg<mode>2"
1756 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1757 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1760 [(set_attr "type" "add")])
1762 (define_insn_and_split "*neg<mode>2_dot"
1763 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1764 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1766 (clobber (match_scratch:GPR 0 "=r,r"))]
1767 "<MODE>mode == Pmode"
1771 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1773 (neg:GPR (match_dup 1)))
1775 (compare:CC (match_dup 0)
1778 [(set_attr "type" "add")
1779 (set_attr "dot" "yes")
1780 (set_attr "length" "4,8")])
1782 (define_insn_and_split "*neg<mode>2_dot2"
1783 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1784 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1786 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1787 (neg:GPR (match_dup 1)))]
1788 "<MODE>mode == Pmode"
1792 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1794 (neg:GPR (match_dup 1)))
1796 (compare:CC (match_dup 0)
1799 [(set_attr "type" "add")
1800 (set_attr "dot" "yes")
1801 (set_attr "length" "4,8")])
1804 (define_insn "clz<mode>2"
1805 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1806 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1809 [(set_attr "type" "cntlz")])
1811 (define_expand "ctz<mode>2"
1813 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1815 (and:GPR (match_dup 1)
1818 (clz:GPR (match_dup 3)))
1819 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1820 (minus:GPR (match_dup 5)
1822 (clobber (reg:GPR CA_REGNO))])]
1825 operands[2] = gen_reg_rtx (<MODE>mode);
1826 operands[3] = gen_reg_rtx (<MODE>mode);
1827 operands[4] = gen_reg_rtx (<MODE>mode);
1828 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1831 (define_expand "ffs<mode>2"
1833 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1835 (and:GPR (match_dup 1)
1838 (clz:GPR (match_dup 3)))
1839 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1840 (minus:GPR (match_dup 5)
1842 (clobber (reg:GPR CA_REGNO))])]
1845 operands[2] = gen_reg_rtx (<MODE>mode);
1846 operands[3] = gen_reg_rtx (<MODE>mode);
1847 operands[4] = gen_reg_rtx (<MODE>mode);
1848 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1852 (define_expand "popcount<mode>2"
1853 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1854 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1855 "TARGET_POPCNTB || TARGET_POPCNTD"
1857 rs6000_emit_popcount (operands[0], operands[1]);
1861 (define_insn "popcntb<mode>2"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1863 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1867 [(set_attr "type" "popcnt")])
1869 (define_insn "popcntd<mode>2"
1870 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1871 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1874 [(set_attr "type" "popcnt")])
1877 (define_expand "parity<mode>2"
1878 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1879 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1882 rs6000_emit_parity (operands[0], operands[1]);
1886 (define_insn "parity<mode>2_cmpb"
1887 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1888 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1889 "TARGET_CMPB && TARGET_POPCNTB"
1891 [(set_attr "type" "popcnt")])
1894 ;; Since the hardware zeros the upper part of the register, save generating the
1895 ;; AND immediate if we are converting to unsigned
1896 (define_insn "*bswaphi2_extenddi"
1897 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1899 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1902 [(set_attr "length" "4")
1903 (set_attr "type" "load")])
1905 (define_insn "*bswaphi2_extendsi"
1906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1908 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1911 [(set_attr "length" "4")
1912 (set_attr "type" "load")])
1914 (define_expand "bswaphi2"
1915 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1917 (match_operand:HI 1 "reg_or_mem_operand" "")))
1918 (clobber (match_scratch:SI 2 ""))])]
1921 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1922 operands[1] = force_reg (HImode, operands[1]);
1925 (define_insn "bswaphi2_internal"
1926 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1928 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1929 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1935 [(set_attr "length" "4,4,12")
1936 (set_attr "type" "load,store,*")])
1938 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
1939 ;; correct for -mlittle as well as -mbig.
1941 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1942 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1943 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1946 (zero_extract:SI (match_dup 4)
1950 (and:SI (ashift:SI (match_dup 4)
1952 (const_int 65280))) ;; 0xff00
1954 (ior:SI (match_dup 3)
1958 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
1959 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
1962 (define_insn "*bswapsi2_extenddi"
1963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1965 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
1968 [(set_attr "length" "4")
1969 (set_attr "type" "load")])
1971 (define_expand "bswapsi2"
1972 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1974 (match_operand:SI 1 "reg_or_mem_operand" "")))]
1977 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1978 operands[1] = force_reg (SImode, operands[1]);
1981 (define_insn "*bswapsi2_internal"
1982 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
1984 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
1990 [(set_attr "length" "4,4,12")
1991 (set_attr "type" "load,store,*")])
1993 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
1994 ;; zero_extract insns do not change for -mlittle.
1996 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1997 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2000 (rotate:SI (match_dup 1) (const_int 8)))
2001 (set (zero_extract:SI (match_dup 0)
2005 (set (zero_extract:SI (match_dup 0)
2008 (rotate:SI (match_dup 1)
2012 (define_expand "bswapdi2"
2013 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2015 (match_operand:DI 1 "reg_or_mem_operand" "")))
2016 (clobber (match_scratch:DI 2 ""))
2017 (clobber (match_scratch:DI 3 ""))
2018 (clobber (match_scratch:DI 4 ""))])]
2021 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2022 operands[1] = force_reg (DImode, operands[1]);
2024 if (!TARGET_POWERPC64)
2026 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2027 that uses 64-bit registers needs the same scratch registers as 64-bit
2029 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2034 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2035 (define_insn "*bswapdi2_ldbrx"
2036 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2037 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2038 (clobber (match_scratch:DI 2 "=X,X,&r"))
2039 (clobber (match_scratch:DI 3 "=X,X,&r"))
2040 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2041 "TARGET_POWERPC64 && TARGET_LDBRX
2042 && (REG_P (operands[0]) || REG_P (operands[1]))"
2047 [(set_attr "length" "4,4,36")
2048 (set_attr "type" "load,store,*")])
2050 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2051 (define_insn "*bswapdi2_64bit"
2052 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2053 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2054 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2055 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2056 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2057 "TARGET_POWERPC64 && !TARGET_LDBRX
2058 && (REG_P (operands[0]) || REG_P (operands[1]))
2059 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2060 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2062 [(set_attr "length" "16,12,36")])
2065 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2066 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2067 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2068 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2069 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2070 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2074 rtx dest = operands[0];
2075 rtx src = operands[1];
2076 rtx op2 = operands[2];
2077 rtx op3 = operands[3];
2078 rtx op4 = operands[4];
2079 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2080 BYTES_BIG_ENDIAN ? 4 : 0);
2081 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2082 BYTES_BIG_ENDIAN ? 4 : 0);
2088 addr1 = XEXP (src, 0);
2089 if (GET_CODE (addr1) == PLUS)
2091 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2092 if (TARGET_AVOID_XFORM)
2094 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2098 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2100 else if (TARGET_AVOID_XFORM)
2102 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2107 emit_move_insn (op2, GEN_INT (4));
2108 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2111 if (BYTES_BIG_ENDIAN)
2113 word_high = change_address (src, SImode, addr1);
2114 word_low = change_address (src, SImode, addr2);
2118 word_high = change_address (src, SImode, addr2);
2119 word_low = change_address (src, SImode, addr1);
2122 emit_insn (gen_bswapsi2 (op3_32, word_low));
2123 emit_insn (gen_bswapsi2 (op4_32, word_high));
2124 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2125 emit_insn (gen_iordi3 (dest, dest, op4));
2130 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2131 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2132 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2133 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2134 (clobber (match_operand:DI 4 "" ""))]
2135 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2139 rtx dest = operands[0];
2140 rtx src = operands[1];
2141 rtx op2 = operands[2];
2142 rtx op3 = operands[3];
2143 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2144 BYTES_BIG_ENDIAN ? 4 : 0);
2145 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2146 BYTES_BIG_ENDIAN ? 4 : 0);
2152 addr1 = XEXP (dest, 0);
2153 if (GET_CODE (addr1) == PLUS)
2155 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2156 if (TARGET_AVOID_XFORM)
2158 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2162 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2164 else if (TARGET_AVOID_XFORM)
2166 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2171 emit_move_insn (op2, GEN_INT (4));
2172 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2175 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2176 if (BYTES_BIG_ENDIAN)
2178 word_high = change_address (dest, SImode, addr1);
2179 word_low = change_address (dest, SImode, addr2);
2183 word_high = change_address (dest, SImode, addr2);
2184 word_low = change_address (dest, SImode, addr1);
2186 emit_insn (gen_bswapsi2 (word_high, src_si));
2187 emit_insn (gen_bswapsi2 (word_low, op3_si));
2192 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2193 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2194 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2195 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2196 (clobber (match_operand:DI 4 "" ""))]
2197 "TARGET_POWERPC64 && reload_completed"
2201 rtx dest = operands[0];
2202 rtx src = operands[1];
2203 rtx op2 = operands[2];
2204 rtx op3 = operands[3];
2205 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2206 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2207 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2208 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2209 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2211 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2212 emit_insn (gen_bswapsi2 (dest_si, src_si));
2213 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2214 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2215 emit_insn (gen_iordi3 (dest, dest, op3));
2219 (define_insn "bswapdi2_32bit"
2220 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2221 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2222 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2223 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2225 [(set_attr "length" "16,12,36")])
2228 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2229 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2230 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2231 "!TARGET_POWERPC64 && reload_completed"
2235 rtx dest = operands[0];
2236 rtx src = operands[1];
2237 rtx op2 = operands[2];
2238 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2239 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2245 addr1 = XEXP (src, 0);
2246 if (GET_CODE (addr1) == PLUS)
2248 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2249 if (TARGET_AVOID_XFORM)
2251 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2255 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2257 else if (TARGET_AVOID_XFORM)
2259 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2264 emit_move_insn (op2, GEN_INT (4));
2265 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2268 word1 = change_address (src, SImode, addr1);
2269 word2 = change_address (src, SImode, addr2);
2271 emit_insn (gen_bswapsi2 (dest2, word1));
2272 emit_insn (gen_bswapsi2 (dest1, word2));
2277 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2278 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2279 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2280 "!TARGET_POWERPC64 && reload_completed"
2284 rtx dest = operands[0];
2285 rtx src = operands[1];
2286 rtx op2 = operands[2];
2287 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2288 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2294 addr1 = XEXP (dest, 0);
2295 if (GET_CODE (addr1) == PLUS)
2297 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2298 if (TARGET_AVOID_XFORM)
2300 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2304 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2306 else if (TARGET_AVOID_XFORM)
2308 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2313 emit_move_insn (op2, GEN_INT (4));
2314 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2317 word1 = change_address (dest, SImode, addr1);
2318 word2 = change_address (dest, SImode, addr2);
2320 emit_insn (gen_bswapsi2 (word2, src1));
2321 emit_insn (gen_bswapsi2 (word1, src2));
2326 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2327 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2328 (clobber (match_operand:SI 2 "" ""))]
2329 "!TARGET_POWERPC64 && reload_completed"
2333 rtx dest = operands[0];
2334 rtx src = operands[1];
2335 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2336 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2337 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2338 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2340 emit_insn (gen_bswapsi2 (dest1, src2));
2341 emit_insn (gen_bswapsi2 (dest2, src1));
2346 (define_insn "mul<mode>3"
2347 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2348 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2349 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2354 [(set_attr "type" "mul")
2356 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2358 (match_operand:GPR 2 "short_cint_operand" "")
2359 (const_string "16")]
2360 (const_string "<bits>")))])
2362 (define_insn_and_split "*mul<mode>3_dot"
2363 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2364 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2365 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2367 (clobber (match_scratch:GPR 0 "=r,r"))]
2368 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2372 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2374 (mult:GPR (match_dup 1)
2377 (compare:CC (match_dup 0)
2380 [(set_attr "type" "mul")
2381 (set_attr "size" "<bits>")
2382 (set_attr "dot" "yes")
2383 (set_attr "length" "4,8")])
2385 (define_insn_and_split "*mul<mode>3_dot2"
2386 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2387 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2388 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2390 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2391 (mult:GPR (match_dup 1)
2393 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2397 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2399 (mult:GPR (match_dup 1)
2402 (compare:CC (match_dup 0)
2405 [(set_attr "type" "mul")
2406 (set_attr "size" "<bits>")
2407 (set_attr "dot" "yes")
2408 (set_attr "length" "4,8")])
2411 (define_expand "<su>mul<mode>3_highpart"
2412 [(set (match_operand:GPR 0 "gpc_reg_operand")
2414 (mult:<DMODE> (any_extend:<DMODE>
2415 (match_operand:GPR 1 "gpc_reg_operand"))
2417 (match_operand:GPR 2 "gpc_reg_operand")))
2421 if (<MODE>mode == SImode && TARGET_POWERPC64)
2423 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2428 if (!WORDS_BIG_ENDIAN)
2430 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2436 (define_insn "*<su>mul<mode>3_highpart"
2437 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2439 (mult:<DMODE> (any_extend:<DMODE>
2440 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2442 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2444 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2445 "mulh<wd><u> %0,%1,%2"
2446 [(set_attr "type" "mul")
2447 (set_attr "size" "<bits>")])
2449 (define_insn "<su>mulsi3_highpart_le"
2450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2452 (mult:DI (any_extend:DI
2453 (match_operand:SI 1 "gpc_reg_operand" "r"))
2455 (match_operand:SI 2 "gpc_reg_operand" "r")))
2457 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2459 [(set_attr "type" "mul")])
2461 (define_insn "<su>muldi3_highpart_le"
2462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2464 (mult:TI (any_extend:TI
2465 (match_operand:DI 1 "gpc_reg_operand" "r"))
2467 (match_operand:DI 2 "gpc_reg_operand" "r")))
2469 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2471 [(set_attr "type" "mul")
2472 (set_attr "size" "64")])
2474 (define_insn "<su>mulsi3_highpart_64"
2475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2478 (mult:DI (any_extend:DI
2479 (match_operand:SI 1 "gpc_reg_operand" "r"))
2481 (match_operand:SI 2 "gpc_reg_operand" "r")))
2485 [(set_attr "type" "mul")])
2487 (define_expand "<u>mul<mode><dmode>3"
2488 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2489 (mult:<DMODE> (any_extend:<DMODE>
2490 (match_operand:GPR 1 "gpc_reg_operand"))
2492 (match_operand:GPR 2 "gpc_reg_operand"))))]
2493 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2495 rtx l = gen_reg_rtx (<MODE>mode);
2496 rtx h = gen_reg_rtx (<MODE>mode);
2497 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2498 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2499 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2500 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2505 (define_insn "udiv<mode>3"
2506 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2507 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2508 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2511 [(set_attr "type" "div")
2512 (set_attr "size" "<bits>")])
2515 ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
2516 ;; modulus. If it isn't a power of two, force operands into register and do
2518 (define_expand "div<mode>3"
2519 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2520 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2521 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2524 if (CONST_INT_P (operands[2])
2525 && INTVAL (operands[2]) > 0
2526 && exact_log2 (INTVAL (operands[2])) >= 0)
2528 emit_insn (gen_div<mode>3_sra (operands[0], operands[1], operands[2]));
2532 operands[2] = force_reg (<MODE>mode, operands[2]);
2535 (define_insn "*div<mode>3"
2536 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2537 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2538 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2541 [(set_attr "type" "div")
2542 (set_attr "size" "<bits>")])
2544 (define_insn "div<mode>3_sra"
2545 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2546 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2547 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))
2548 (clobber (reg:GPR CA_REGNO))]
2550 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2551 [(set_attr "type" "two")
2552 (set_attr "length" "8")])
2554 (define_insn_and_split "*div<mode>3_sra_dot"
2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2556 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2557 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2559 (clobber (match_scratch:GPR 0 "=r,r"))
2560 (clobber (reg:GPR CA_REGNO))]
2561 "<MODE>mode == Pmode"
2563 sra<wd>i %0,%1,%p2\;addze. %0,%0
2565 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2566 [(parallel [(set (match_dup 0)
2567 (div:GPR (match_dup 1)
2569 (clobber (reg:GPR CA_REGNO))])
2571 (compare:CC (match_dup 0)
2574 [(set_attr "type" "two")
2575 (set_attr "length" "8,12")
2576 (set_attr "cell_micro" "not")])
2578 (define_insn_and_split "*div<mode>3_sra_dot2"
2579 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2580 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2581 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2583 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2584 (div:GPR (match_dup 1)
2586 (clobber (reg:GPR CA_REGNO))]
2587 "<MODE>mode == Pmode"
2589 sra<wd>i %0,%1,%p2\;addze. %0,%0
2591 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2592 [(parallel [(set (match_dup 0)
2593 (div:GPR (match_dup 1)
2595 (clobber (reg:GPR CA_REGNO))])
2597 (compare:CC (match_dup 0)
2600 [(set_attr "type" "two")
2601 (set_attr "length" "8,12")
2602 (set_attr "cell_micro" "not")])
2604 (define_expand "mod<mode>3"
2605 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2606 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2607 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2614 if (GET_CODE (operands[2]) != CONST_INT
2615 || INTVAL (operands[2]) <= 0
2616 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2619 temp1 = gen_reg_rtx (<MODE>mode);
2620 temp2 = gen_reg_rtx (<MODE>mode);
2622 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2623 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2624 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2628 ;; Logical instructions
2629 ;; The logical instructions are mostly combined by using match_operator,
2630 ;; but the plain AND insns are somewhat different because there is no
2631 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2632 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2634 (define_expand "and<mode>3"
2635 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2636 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2637 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2640 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2642 rs6000_split_logical (operands, AND, false, false, false);
2646 if (logical_const_operand (operands[2], <MODE>mode)
2647 && !any_mask_operand (operands[2], <MODE>mode))
2649 if (rs6000_gen_cell_microcode)
2651 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2655 operands[2] = force_reg (<MODE>mode, operands[2]);
2658 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2659 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2660 operands[2] = force_reg (<MODE>mode, operands[2]);
2664 (define_insn "and<mode>3_imm"
2665 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2666 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2667 (match_operand:GPR 2 "logical_const_operand" "n")))
2668 (clobber (match_scratch:CC 3 "=x"))]
2669 "rs6000_gen_cell_microcode
2670 && !any_mask_operand (operands[2], <MODE>mode)"
2671 "andi%e2. %0,%1,%u2"
2672 [(set_attr "type" "logical")
2673 (set_attr "dot" "yes")])
2675 (define_insn_and_split "*and<mode>3_imm_dot"
2676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2677 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2678 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2680 (clobber (match_scratch:GPR 0 "=r,r"))
2681 (clobber (match_scratch:CC 4 "=X,x"))]
2682 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2683 && rs6000_gen_cell_microcode
2684 && !any_mask_operand (operands[2], <MODE>mode)"
2688 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2689 [(parallel [(set (match_dup 0)
2690 (and:GPR (match_dup 1)
2692 (clobber (match_dup 4))])
2694 (compare:CC (match_dup 0)
2697 [(set_attr "type" "logical")
2698 (set_attr "dot" "yes")
2699 (set_attr "length" "4,8")])
2701 (define_insn_and_split "*and<mode>3_imm_dot2"
2702 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2703 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2704 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2706 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2707 (and:GPR (match_dup 1)
2709 (clobber (match_scratch:CC 4 "=X,x"))]
2710 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2711 && rs6000_gen_cell_microcode
2712 && !any_mask_operand (operands[2], <MODE>mode)"
2716 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2717 [(parallel [(set (match_dup 0)
2718 (and:GPR (match_dup 1)
2720 (clobber (match_dup 4))])
2722 (compare:CC (match_dup 0)
2725 [(set_attr "type" "logical")
2726 (set_attr "dot" "yes")
2727 (set_attr "length" "4,8")])
2729 (define_insn_and_split "*and<mode>3_imm_mask_dot"
2730 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2731 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2732 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2734 (clobber (match_scratch:GPR 0 "=r,r"))]
2735 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2736 && rs6000_gen_cell_microcode
2737 && any_mask_operand (operands[2], <MODE>mode)"
2741 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2743 (and:GPR (match_dup 1)
2746 (compare:CC (match_dup 0)
2749 [(set_attr "type" "logical")
2750 (set_attr "dot" "yes")
2751 (set_attr "length" "4,8")])
2753 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
2754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2755 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2756 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2758 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2759 (and:GPR (match_dup 1)
2761 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2762 && rs6000_gen_cell_microcode
2763 && any_mask_operand (operands[2], <MODE>mode)"
2767 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2769 (and:GPR (match_dup 1)
2772 (compare:CC (match_dup 0)
2775 [(set_attr "type" "logical")
2776 (set_attr "dot" "yes")
2777 (set_attr "length" "4,8")])
2780 (define_insn "*and<mode>3_mask"
2781 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2782 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2783 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
2786 rldic%B2 %0,%1,0,%S2
2787 rlwinm %0,%1,0,%m2,%M2"
2788 [(set_attr "type" "shift")])
2790 (define_insn_and_split "*and<mode>3_mask_dot"
2791 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2792 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2793 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2795 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
2796 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2797 && rs6000_gen_cell_microcode
2798 && !logical_const_operand (operands[2], <MODE>mode)"
2800 rldic%B2. %0,%1,0,%S2
2801 rlwinm. %0,%1,0,%m2,%M2
2804 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2806 (and:GPR (match_dup 1)
2809 (compare:CC (match_dup 0)
2812 [(set_attr "type" "shift")
2813 (set_attr "dot" "yes")
2814 (set_attr "length" "4,4,8,8")])
2816 (define_insn_and_split "*and<mode>3_mask_dot2"
2817 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2818 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2819 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2821 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
2822 (and:GPR (match_dup 1)
2824 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2825 && rs6000_gen_cell_microcode
2826 && !logical_const_operand (operands[2], <MODE>mode)"
2828 rldic%B2. %0,%1,0,%S2
2829 rlwinm. %0,%1,0,%m2,%M2
2832 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2834 (and:GPR (match_dup 1)
2837 (compare:CC (match_dup 0)
2840 [(set_attr "type" "shift")
2841 (set_attr "dot" "yes")
2842 (set_attr "length" "4,4,8,8")])
2846 (define_insn "andsi3_internal0_nomc"
2847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2848 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2849 (match_operand:SI 2 "and_operand" "?r,T")))]
2850 "!rs6000_gen_cell_microcode"
2853 rlwinm %0,%1,0,%m2,%M2"
2854 [(set_attr "type" "logical,shift")])
2857 ;; Handle the PowerPC64 rlwinm corner case
2859 (define_insn_and_split "*andsi3_internal6"
2860 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2861 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2862 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2867 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2870 (rotate:SI (match_dup 0) (match_dup 5)))]
2873 int mb = extract_MB (operands[2]);
2874 int me = extract_ME (operands[2]);
2875 operands[3] = GEN_INT (me + 1);
2876 operands[5] = GEN_INT (32 - (me + 1));
2877 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2879 [(set_attr "length" "8")])
2882 (define_expand "<code><mode>3"
2883 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2884 (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2885 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2888 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2890 rs6000_split_logical (operands, <CODE>, false, false, false);
2894 if (non_logical_cint_operand (operands[2], <MODE>mode))
2896 rtx tmp = ((!can_create_pseudo_p ()
2897 || rtx_equal_p (operands[0], operands[1]))
2898 ? operands[0] : gen_reg_rtx (<MODE>mode));
2900 HOST_WIDE_INT value = INTVAL (operands[2]);
2901 HOST_WIDE_INT lo = value & 0xffff;
2902 HOST_WIDE_INT hi = value - lo;
2904 emit_insn (gen_<code><mode>3 (tmp, operands[1], GEN_INT (hi)));
2905 emit_insn (gen_<code><mode>3 (operands[0], tmp, GEN_INT (lo)));
2909 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2910 operands[2] = force_reg (<MODE>mode, operands[2]);
2914 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2915 (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2916 (match_operand:GPR 2 "non_logical_cint_operand" "")))]
2919 (iorxor:GPR (match_dup 1)
2922 (iorxor:GPR (match_dup 3)
2925 operands[3] = ((!can_create_pseudo_p ()
2926 || rtx_equal_p (operands[0], operands[1]))
2927 ? operands[0] : gen_reg_rtx (<MODE>mode));
2929 HOST_WIDE_INT value = INTVAL (operands[2]);
2930 HOST_WIDE_INT lo = value & 0xffff;
2931 HOST_WIDE_INT hi = value - lo;
2933 operands[4] = GEN_INT (hi);
2934 operands[5] = GEN_INT (lo);
2937 (define_insn "*bool<mode>3_imm"
2938 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2939 (match_operator:GPR 3 "boolean_or_operator"
2940 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
2941 (match_operand:GPR 2 "logical_const_operand" "n")]))]
2944 [(set_attr "type" "logical")])
2946 (define_insn "*bool<mode>3"
2947 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2948 (match_operator:GPR 3 "boolean_operator"
2949 [(match_operand:GPR 1 "gpc_reg_operand" "r")
2950 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
2953 [(set_attr "type" "logical")])
2955 (define_insn_and_split "*bool<mode>3_dot"
2956 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2957 (compare:CC (match_operator:GPR 3 "boolean_operator"
2958 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2959 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2961 (clobber (match_scratch:GPR 0 "=r,r"))]
2962 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2966 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2970 (compare:CC (match_dup 0)
2973 [(set_attr "type" "logical")
2974 (set_attr "dot" "yes")
2975 (set_attr "length" "4,8")])
2977 (define_insn_and_split "*bool<mode>3_dot2"
2978 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2979 (compare:CC (match_operator:GPR 3 "boolean_operator"
2980 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2981 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2983 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2985 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2989 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2993 (compare:CC (match_dup 0)
2996 [(set_attr "type" "logical")
2997 (set_attr "dot" "yes")
2998 (set_attr "length" "4,8")])
3001 (define_insn "*boolc<mode>3"
3002 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3003 (match_operator:GPR 3 "boolean_operator"
3004 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3005 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3008 [(set_attr "type" "logical")])
3010 (define_insn_and_split "*boolc<mode>3_dot"
3011 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3012 (compare:CC (match_operator:GPR 3 "boolean_operator"
3013 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3014 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3016 (clobber (match_scratch:GPR 0 "=r,r"))]
3017 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3021 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3025 (compare:CC (match_dup 0)
3028 [(set_attr "type" "logical")
3029 (set_attr "dot" "yes")
3030 (set_attr "length" "4,8")])
3032 (define_insn_and_split "*boolc<mode>3_dot2"
3033 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3034 (compare:CC (match_operator:GPR 3 "boolean_operator"
3035 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3036 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3038 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3040 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3044 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3048 (compare:CC (match_dup 0)
3051 [(set_attr "type" "logical")
3052 (set_attr "dot" "yes")
3053 (set_attr "length" "4,8")])
3056 (define_insn "*boolcc<mode>3"
3057 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3058 (match_operator:GPR 3 "boolean_operator"
3059 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3060 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3063 [(set_attr "type" "logical")])
3065 (define_insn_and_split "*boolcc<mode>3_dot"
3066 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3067 (compare:CC (match_operator:GPR 3 "boolean_operator"
3068 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3069 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3071 (clobber (match_scratch:GPR 0 "=r,r"))]
3072 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3076 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3080 (compare:CC (match_dup 0)
3083 [(set_attr "type" "logical")
3084 (set_attr "dot" "yes")
3085 (set_attr "length" "4,8")])
3087 (define_insn_and_split "*boolcc<mode>3_dot2"
3088 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3089 (compare:CC (match_operator:GPR 3 "boolean_operator"
3090 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3091 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3093 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3095 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3099 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3103 (compare:CC (match_dup 0)
3106 [(set_attr "type" "logical")
3107 (set_attr "dot" "yes")
3108 (set_attr "length" "4,8")])
3111 ;; TODO: Should have dots of this as well.
3112 (define_insn "*eqv<mode>3"
3113 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3114 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3115 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3118 [(set_attr "type" "logical")])
3120 ;; Rotate and shift insns, in all their variants. These support shifts,
3121 ;; field inserts and extracts, and various combinations thereof.
3122 (define_expand "insv"
3123 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3124 (match_operand:SI 1 "const_int_operand" "")
3125 (match_operand:SI 2 "const_int_operand" ""))
3126 (match_operand 3 "gpc_reg_operand" ""))]
3130 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3131 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3132 compiler if the address of the structure is taken later. Likewise, do
3133 not handle invalid E500 subregs. */
3134 if (GET_CODE (operands[0]) == SUBREG
3135 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3136 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3137 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3140 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3141 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3144 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3149 (define_insn "insvsi_internal"
3150 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3151 (match_operand:SI 1 "const_int_operand" "i")
3152 (match_operand:SI 2 "const_int_operand" "i"))
3153 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3157 int start = INTVAL (operands[2]) & 31;
3158 int size = INTVAL (operands[1]) & 31;
3160 operands[4] = GEN_INT (32 - start - size);
3161 operands[1] = GEN_INT (start + size - 1);
3162 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3164 [(set_attr "type" "insert")])
3166 (define_insn "*insvsi_internal1"
3167 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3168 (match_operand:SI 1 "const_int_operand" "i")
3169 (match_operand:SI 2 "const_int_operand" "i"))
3170 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3171 (match_operand:SI 4 "const_int_operand" "i")))]
3172 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3175 int shift = INTVAL (operands[4]) & 31;
3176 int start = INTVAL (operands[2]) & 31;
3177 int size = INTVAL (operands[1]) & 31;
3179 operands[4] = GEN_INT (shift - start - size);
3180 operands[1] = GEN_INT (start + size - 1);
3181 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3183 [(set_attr "type" "insert")])
3185 (define_insn "*insvsi_internal2"
3186 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3187 (match_operand:SI 1 "const_int_operand" "i")
3188 (match_operand:SI 2 "const_int_operand" "i"))
3189 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3190 (match_operand:SI 4 "const_int_operand" "i")))]
3191 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3194 int shift = INTVAL (operands[4]) & 31;
3195 int start = INTVAL (operands[2]) & 31;
3196 int size = INTVAL (operands[1]) & 31;
3198 operands[4] = GEN_INT (32 - shift - start - size);
3199 operands[1] = GEN_INT (start + size - 1);
3200 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3202 [(set_attr "type" "insert")])
3204 (define_insn "*insvsi_internal3"
3205 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3206 (match_operand:SI 1 "const_int_operand" "i")
3207 (match_operand:SI 2 "const_int_operand" "i"))
3208 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3209 (match_operand:SI 4 "const_int_operand" "i")))]
3210 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3213 int shift = INTVAL (operands[4]) & 31;
3214 int start = INTVAL (operands[2]) & 31;
3215 int size = INTVAL (operands[1]) & 31;
3217 operands[4] = GEN_INT (32 - shift - start - size);
3218 operands[1] = GEN_INT (start + size - 1);
3219 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3221 [(set_attr "type" "insert")])
3223 (define_insn "*insvsi_internal4"
3224 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3225 (match_operand:SI 1 "const_int_operand" "i")
3226 (match_operand:SI 2 "const_int_operand" "i"))
3227 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3228 (match_operand:SI 4 "const_int_operand" "i")
3229 (match_operand:SI 5 "const_int_operand" "i")))]
3230 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3233 int extract_start = INTVAL (operands[5]) & 31;
3234 int extract_size = INTVAL (operands[4]) & 31;
3235 int insert_start = INTVAL (operands[2]) & 31;
3236 int insert_size = INTVAL (operands[1]) & 31;
3238 /* Align extract field with insert field */
3239 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3240 operands[1] = GEN_INT (insert_start + insert_size - 1);
3241 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3243 [(set_attr "type" "insert")])
3245 ;; combine patterns for rlwimi
3246 (define_insn "*insvsi_internal5"
3247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3248 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3249 (match_operand:SI 1 "mask_operand" "i"))
3250 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3251 (match_operand:SI 2 "const_int_operand" "i"))
3252 (match_operand:SI 5 "mask_operand" "i"))))]
3253 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3256 int me = extract_ME(operands[5]);
3257 int mb = extract_MB(operands[5]);
3258 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3259 operands[2] = GEN_INT(mb);
3260 operands[1] = GEN_INT(me);
3261 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3263 [(set_attr "type" "insert")])
3265 (define_insn "*insvsi_internal6"
3266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3267 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3268 (match_operand:SI 2 "const_int_operand" "i"))
3269 (match_operand:SI 5 "mask_operand" "i"))
3270 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3271 (match_operand:SI 1 "mask_operand" "i"))))]
3272 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3275 int me = extract_ME(operands[5]);
3276 int mb = extract_MB(operands[5]);
3277 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3278 operands[2] = GEN_INT(mb);
3279 operands[1] = GEN_INT(me);
3280 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3282 [(set_attr "type" "insert")])
3284 (define_insn "insvdi_internal"
3285 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3286 (match_operand:SI 1 "const_int_operand" "i")
3287 (match_operand:SI 2 "const_int_operand" "i"))
3288 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3292 int start = INTVAL (operands[2]) & 63;
3293 int size = INTVAL (operands[1]) & 63;
3295 operands[1] = GEN_INT (64 - start - size);
3296 return \"rldimi %0,%3,%H1,%H2\";
3298 [(set_attr "type" "insert")
3299 (set_attr "size" "64")])
3301 (define_insn "*insvdi_internal2"
3302 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3303 (match_operand:SI 1 "const_int_operand" "i")
3304 (match_operand:SI 2 "const_int_operand" "i"))
3305 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3306 (match_operand:SI 4 "const_int_operand" "i")))]
3308 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3311 int shift = INTVAL (operands[4]) & 63;
3312 int start = (INTVAL (operands[2]) & 63) - 32;
3313 int size = INTVAL (operands[1]) & 63;
3315 operands[4] = GEN_INT (64 - shift - start - size);
3316 operands[2] = GEN_INT (start);
3317 operands[1] = GEN_INT (start + size - 1);
3318 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3321 (define_insn "*insvdi_internal3"
3322 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3323 (match_operand:SI 1 "const_int_operand" "i")
3324 (match_operand:SI 2 "const_int_operand" "i"))
3325 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3326 (match_operand:SI 4 "const_int_operand" "i")))]
3328 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3331 int shift = INTVAL (operands[4]) & 63;
3332 int start = (INTVAL (operands[2]) & 63) - 32;
3333 int size = INTVAL (operands[1]) & 63;
3335 operands[4] = GEN_INT (64 - shift - start - size);
3336 operands[2] = GEN_INT (start);
3337 operands[1] = GEN_INT (start + size - 1);
3338 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3341 (define_expand "extzv"
3342 [(set (match_operand 0 "gpc_reg_operand" "")
3343 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3344 (match_operand:SI 2 "const_int_operand" "")
3345 (match_operand:SI 3 "const_int_operand" "")))]
3349 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3350 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3351 compiler if the address of the structure is taken later. */
3352 if (GET_CODE (operands[0]) == SUBREG
3353 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3356 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3357 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3360 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3365 (define_insn "extzvsi_internal"
3366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3367 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3368 (match_operand:SI 2 "const_int_operand" "i")
3369 (match_operand:SI 3 "const_int_operand" "i")))]
3373 int start = INTVAL (operands[3]) & 31;
3374 int size = INTVAL (operands[2]) & 31;
3376 if (start + size >= 32)
3377 operands[3] = const0_rtx;
3379 operands[3] = GEN_INT (start + size);
3380 return \"rlwinm %0,%1,%3,%s2,31\";
3382 [(set_attr "type" "shift")])
3384 (define_insn "*extzvsi_internal1"
3385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3386 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3387 (match_operand:SI 2 "const_int_operand" "i,i")
3388 (match_operand:SI 3 "const_int_operand" "i,i"))
3390 (clobber (match_scratch:SI 4 "=r,r"))]
3394 int start = INTVAL (operands[3]) & 31;
3395 int size = INTVAL (operands[2]) & 31;
3397 /* Force split for non-cc0 compare. */
3398 if (which_alternative == 1)
3401 /* If the bit-field being tested fits in the upper or lower half of a
3402 word, it is possible to use andiu. or andil. to test it. This is
3403 useful because the condition register set-use delay is smaller for
3404 andi[ul]. than for rlinm. This doesn't work when the starting bit
3405 position is 0 because the LT and GT bits may be set wrong. */
3407 if ((start > 0 && start + size <= 16) || start >= 16)
3409 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3410 - (1 << (16 - (start & 15) - size))));
3412 return \"andis. %4,%1,%3\";
3414 return \"andi. %4,%1,%3\";
3417 if (start + size >= 32)
3418 operands[3] = const0_rtx;
3420 operands[3] = GEN_INT (start + size);
3421 return \"rlwinm. %4,%1,%3,%s2,31\";
3423 [(set_attr "type" "shift")
3424 (set_attr "dot" "yes")
3425 (set_attr "length" "4,8")])
3428 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3429 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3430 (match_operand:SI 2 "const_int_operand" "")
3431 (match_operand:SI 3 "const_int_operand" ""))
3433 (clobber (match_scratch:SI 4 ""))]
3436 (zero_extract:SI (match_dup 1) (match_dup 2)
3439 (compare:CC (match_dup 4)
3443 (define_insn "*extzvsi_internal2"
3444 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3445 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3446 (match_operand:SI 2 "const_int_operand" "i,i")
3447 (match_operand:SI 3 "const_int_operand" "i,i"))
3449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3450 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3454 int start = INTVAL (operands[3]) & 31;
3455 int size = INTVAL (operands[2]) & 31;
3457 /* Force split for non-cc0 compare. */
3458 if (which_alternative == 1)
3461 /* Since we are using the output value, we can't ignore any need for
3462 a shift. The bit-field must end at the LSB. */
3463 if (start >= 16 && start + size == 32)
3465 operands[3] = GEN_INT ((1 << size) - 1);
3466 return \"andi. %0,%1,%3\";
3469 if (start + size >= 32)
3470 operands[3] = const0_rtx;
3472 operands[3] = GEN_INT (start + size);
3473 return \"rlwinm. %0,%1,%3,%s2,31\";
3475 [(set_attr "type" "shift")
3476 (set_attr "dot" "yes")
3477 (set_attr "length" "4,8")])
3480 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3481 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3482 (match_operand:SI 2 "const_int_operand" "")
3483 (match_operand:SI 3 "const_int_operand" ""))
3485 (set (match_operand:SI 0 "gpc_reg_operand" "")
3486 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3489 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3491 (compare:CC (match_dup 0)
3495 (define_insn "extzvdi_internal"
3496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3497 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3498 (match_operand:SI 2 "const_int_operand" "i")
3499 (match_operand:SI 3 "const_int_operand" "i")))]
3503 int start = INTVAL (operands[3]) & 63;
3504 int size = INTVAL (operands[2]) & 63;
3506 if (start + size >= 64)
3507 operands[3] = const0_rtx;
3509 operands[3] = GEN_INT (start + size);
3510 operands[2] = GEN_INT (64 - size);
3511 return \"rldicl %0,%1,%3,%2\";
3513 [(set_attr "type" "shift")])
3515 (define_insn "*extzvdi_internal1"
3516 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3517 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3518 (match_operand:SI 2 "const_int_operand" "i")
3519 (match_operand:SI 3 "const_int_operand" "i"))
3521 (clobber (match_scratch:DI 4 "=r"))]
3522 "TARGET_64BIT && rs6000_gen_cell_microcode"
3525 int start = INTVAL (operands[3]) & 63;
3526 int size = INTVAL (operands[2]) & 63;
3528 if (start + size >= 64)
3529 operands[3] = const0_rtx;
3531 operands[3] = GEN_INT (start + size);
3532 operands[2] = GEN_INT (64 - size);
3533 return \"rldicl. %4,%1,%3,%2\";
3535 [(set_attr "type" "shift")
3536 (set_attr "dot" "yes")])
3538 (define_insn "*extzvdi_internal2"
3539 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3540 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3541 (match_operand:SI 2 "const_int_operand" "i")
3542 (match_operand:SI 3 "const_int_operand" "i"))
3544 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3545 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3546 "TARGET_64BIT && rs6000_gen_cell_microcode"
3549 int start = INTVAL (operands[3]) & 63;
3550 int size = INTVAL (operands[2]) & 63;
3552 if (start + size >= 64)
3553 operands[3] = const0_rtx;
3555 operands[3] = GEN_INT (start + size);
3556 operands[2] = GEN_INT (64 - size);
3557 return \"rldicl. %0,%1,%3,%2\";
3559 [(set_attr "type" "shift")
3560 (set_attr "dot" "yes")])
3563 (define_insn "rotl<mode>3"
3564 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3565 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3566 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3568 "rotl<wd>%I2 %0,%1,%<hH>2"
3569 [(set_attr "type" "shift")
3570 (set_attr "maybe_var_shift" "yes")])
3572 (define_insn "*rotlsi3_64"
3573 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3575 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3576 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3578 "rotlw%I2 %0,%1,%h2"
3579 [(set_attr "type" "shift")
3580 (set_attr "maybe_var_shift" "yes")])
3582 (define_insn_and_split "*rotl<mode>3_dot"
3583 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3584 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3585 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3587 (clobber (match_scratch:GPR 0 "=r,r"))]
3588 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3590 rotl<wd>%I2. %0,%1,%<hH>2
3592 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3594 (rotate:GPR (match_dup 1)
3597 (compare:CC (match_dup 0)
3600 [(set_attr "type" "shift")
3601 (set_attr "maybe_var_shift" "yes")
3602 (set_attr "dot" "yes")
3603 (set_attr "length" "4,8")])
3605 (define_insn_and_split "*rotl<mode>3_dot2"
3606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3607 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3608 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3610 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3611 (rotate:GPR (match_dup 1)
3613 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3615 rotl<wd>%I2. %0,%1,%<hH>2
3617 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3619 (rotate:GPR (match_dup 1)
3622 (compare:CC (match_dup 0)
3625 [(set_attr "type" "shift")
3626 (set_attr "maybe_var_shift" "yes")
3627 (set_attr "dot" "yes")
3628 (set_attr "length" "4,8")])
3631 (define_insn "*rotlsi3_internal4"
3632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3633 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3634 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3635 (match_operand:SI 3 "mask_operand" "n")))]
3637 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3638 [(set_attr "type" "shift")
3639 (set_attr "maybe_var_shift" "yes")])
3641 (define_insn "*rotlsi3_internal5"
3642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3644 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3645 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3646 (match_operand:SI 3 "mask_operand" "n,n"))
3648 (clobber (match_scratch:SI 4 "=r,r"))]
3651 rlw%I2nm. %4,%1,%h2,%m3,%M3
3653 [(set_attr "type" "shift")
3654 (set_attr "maybe_var_shift" "yes")
3655 (set_attr "dot" "yes")
3656 (set_attr "length" "4,8")])
3659 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3661 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3662 (match_operand:SI 2 "reg_or_cint_operand" ""))
3663 (match_operand:SI 3 "mask_operand" ""))
3665 (clobber (match_scratch:SI 4 ""))]
3668 (and:SI (rotate:SI (match_dup 1)
3672 (compare:CC (match_dup 4)
3676 (define_insn "*rotlsi3_internal6"
3677 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3679 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3680 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3681 (match_operand:SI 3 "mask_operand" "n,n"))
3683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3684 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3687 rlw%I2nm. %0,%1,%h2,%m3,%M3
3689 [(set_attr "type" "shift")
3690 (set_attr "maybe_var_shift" "yes")
3691 (set_attr "dot" "yes")
3692 (set_attr "length" "4,8")])
3695 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3697 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3698 (match_operand:SI 2 "reg_or_cint_operand" ""))
3699 (match_operand:SI 3 "mask_operand" ""))
3701 (set (match_operand:SI 0 "gpc_reg_operand" "")
3702 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3705 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3707 (compare:CC (match_dup 0)
3711 (define_insn "*rotlsi3_internal7le"
3712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3715 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3716 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3718 "rlw%I2nm %0,%1,%h2,0xff"
3719 [(set (attr "cell_micro")
3720 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3721 (const_string "not")
3722 (const_string "always")))
3723 (set_attr "type" "shift")])
3725 (define_insn "*rotlsi3_internal7be"
3726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3729 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3730 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3732 "rlw%I2nm %0,%1,%h2,0xff"
3733 [(set (attr "cell_micro")
3734 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3735 (const_string "not")
3736 (const_string "always")))
3737 (set_attr "type" "shift")])
3739 (define_insn "*rotlsi3_internal8le"
3740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3741 (compare:CC (zero_extend:SI
3743 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3744 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3746 (clobber (match_scratch:SI 3 "=r,r"))]
3749 rlw%I2nm. %3,%1,%h2,0xff
3751 [(set_attr "type" "shift")
3752 (set_attr "maybe_var_shift" "yes")
3753 (set_attr "dot" "yes")
3754 (set_attr "length" "4,8")])
3756 (define_insn "*rotlsi3_internal8be"
3757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3758 (compare:CC (zero_extend:SI
3760 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3761 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3763 (clobber (match_scratch:SI 3 "=r,r"))]
3766 rlw%I2nm. %3,%1,%h2,0xff
3768 [(set_attr "type" "shift")
3769 (set_attr "maybe_var_shift" "yes")
3770 (set_attr "dot" "yes")
3771 (set_attr "length" "4,8")])
3774 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3775 (compare:CC (zero_extend:SI
3777 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3778 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3780 (clobber (match_scratch:SI 3 ""))]
3781 "!BYTES_BIG_ENDIAN && reload_completed"
3783 (zero_extend:SI (subreg:QI
3784 (rotate:SI (match_dup 1)
3787 (compare:CC (match_dup 3)
3792 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3793 (compare:CC (zero_extend:SI
3795 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3796 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3798 (clobber (match_scratch:SI 3 ""))]
3799 "BYTES_BIG_ENDIAN && reload_completed"
3801 (zero_extend:SI (subreg:QI
3802 (rotate:SI (match_dup 1)
3805 (compare:CC (match_dup 3)
3809 (define_insn "*rotlsi3_internal9le"
3810 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3811 (compare:CC (zero_extend:SI
3813 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3814 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3816 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3817 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3820 rlw%I2nm. %0,%1,%h2,0xff
3822 [(set_attr "type" "shift")
3823 (set_attr "maybe_var_shift" "yes")
3824 (set_attr "dot" "yes")
3825 (set_attr "length" "4,8")])
3827 (define_insn "*rotlsi3_internal9be"
3828 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3829 (compare:CC (zero_extend:SI
3831 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3832 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3835 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3838 rlw%I2nm. %0,%1,%h2,0xff
3840 [(set_attr "type" "shift")
3841 (set_attr "maybe_var_shift" "yes")
3842 (set_attr "dot" "yes")
3843 (set_attr "length" "4,8")])
3846 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3847 (compare:CC (zero_extend:SI
3849 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3850 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3852 (set (match_operand:SI 0 "gpc_reg_operand" "")
3853 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3854 "!BYTES_BIG_ENDIAN && reload_completed"
3856 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3858 (compare:CC (match_dup 0)
3863 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3864 (compare:CC (zero_extend:SI
3866 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3867 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3869 (set (match_operand:SI 0 "gpc_reg_operand" "")
3870 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3871 "BYTES_BIG_ENDIAN && reload_completed"
3873 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3875 (compare:CC (match_dup 0)
3879 (define_insn "*rotlsi3_internal10le"
3880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3883 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3884 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
3886 "rlw%I2nm %0,%1,%h2,0xffff"
3887 [(set_attr "type" "shift")
3888 (set_attr "maybe_var_shift" "yes")])
3890 (define_insn "*rotlsi3_internal10be"
3891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3894 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3895 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
3897 "rlw%I2nm %0,%1,%h2,0xffff"
3898 [(set_attr "type" "shift")
3899 (set_attr "maybe_var_shift" "yes")])
3901 (define_insn "*rotlsi3_internal11le"
3902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3903 (compare:CC (zero_extend:SI
3905 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3906 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3908 (clobber (match_scratch:SI 3 "=r,r"))]
3911 rlw%I2nm. %3,%1,%h2,0xffff
3913 [(set_attr "type" "shift")
3914 (set_attr "maybe_var_shift" "yes")
3915 (set_attr "dot" "yes")
3916 (set_attr "length" "4,8")])
3918 (define_insn "*rotlsi3_internal11be"
3919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3920 (compare:CC (zero_extend:SI
3922 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3925 (clobber (match_scratch:SI 3 "=r,r"))]
3928 rlw%I2nm. %3,%1,%h2,0xffff
3930 [(set_attr "type" "shift")
3931 (set_attr "maybe_var_shift" "yes")
3932 (set_attr "dot" "yes")
3933 (set_attr "length" "4,8")])
3936 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3937 (compare:CC (zero_extend:SI
3939 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3940 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3942 (clobber (match_scratch:SI 3 ""))]
3943 "!BYTES_BIG_ENDIAN && reload_completed"
3945 (zero_extend:SI (subreg:HI
3946 (rotate:SI (match_dup 1)
3949 (compare:CC (match_dup 3)
3954 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3955 (compare:CC (zero_extend:SI
3957 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3958 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
3960 (clobber (match_scratch:SI 3 ""))]
3961 "BYTES_BIG_ENDIAN && reload_completed"
3963 (zero_extend:SI (subreg:HI
3964 (rotate:SI (match_dup 1)
3967 (compare:CC (match_dup 3)
3971 (define_insn "*rotlsi3_internal12le"
3972 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3973 (compare:CC (zero_extend:SI
3975 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3976 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3978 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3979 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3982 rlw%I2nm. %0,%1,%h2,0xffff
3984 [(set_attr "type" "shift")
3985 (set_attr "maybe_var_shift" "yes")
3986 (set_attr "dot" "yes")
3987 (set_attr "length" "4,8")])
3989 (define_insn "*rotlsi3_internal12be"
3990 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3991 (compare:CC (zero_extend:SI
3993 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3994 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3996 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3997 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4000 rlw%I2nm. %0,%1,%h2,0xffff
4002 [(set_attr "type" "shift")
4003 (set_attr "maybe_var_shift" "yes")
4004 (set_attr "dot" "yes")
4005 (set_attr "length" "4,8")])
4008 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4009 (compare:CC (zero_extend:SI
4011 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4016 "!BYTES_BIG_ENDIAN && reload_completed"
4018 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4020 (compare:CC (match_dup 0)
4025 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4026 (compare:CC (zero_extend:SI
4028 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4029 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4031 (set (match_operand:SI 0 "gpc_reg_operand" "")
4032 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4033 "BYTES_BIG_ENDIAN && reload_completed"
4035 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4037 (compare:CC (match_dup 0)
4042 (define_insn "ashl<mode>3"
4043 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4044 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4045 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4047 "sl<wd>%I2 %0,%1,%<hH>2"
4048 [(set_attr "type" "shift")
4049 (set_attr "maybe_var_shift" "yes")])
4051 (define_insn "*ashlsi3_64"
4052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4054 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4055 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4058 [(set_attr "type" "shift")
4059 (set_attr "maybe_var_shift" "yes")])
4061 (define_insn_and_split "*ashl<mode>3_dot"
4062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4063 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4064 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4066 (clobber (match_scratch:GPR 0 "=r,r"))]
4067 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4069 sl<wd>%I2. %0,%1,%<hH>2
4071 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4073 (ashift:GPR (match_dup 1)
4076 (compare:CC (match_dup 0)
4079 [(set_attr "type" "shift")
4080 (set_attr "maybe_var_shift" "yes")
4081 (set_attr "dot" "yes")
4082 (set_attr "length" "4,8")])
4084 (define_insn_and_split "*ashl<mode>3_dot2"
4085 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4086 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4087 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4089 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4090 (ashift:GPR (match_dup 1)
4092 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4094 sl<wd>%I2. %0,%1,%<hH>2
4096 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4098 (ashift:GPR (match_dup 1)
4101 (compare:CC (match_dup 0)
4104 [(set_attr "type" "shift")
4105 (set_attr "maybe_var_shift" "yes")
4106 (set_attr "dot" "yes")
4107 (set_attr "length" "4,8")])
4110 (define_insn "rlwinm"
4111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4112 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4113 (match_operand:SI 2 "const_int_operand" "i"))
4114 (match_operand:SI 3 "mask_operand" "n")))]
4115 "includes_lshift_p (operands[2], operands[3])"
4116 "rlwinm %0,%1,%h2,%m3,%M3"
4117 [(set_attr "type" "shift")])
4120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4122 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4123 (match_operand:SI 2 "const_int_operand" "i,i"))
4124 (match_operand:SI 3 "mask_operand" "n,n"))
4126 (clobber (match_scratch:SI 4 "=r,r"))]
4127 "includes_lshift_p (operands[2], operands[3])"
4129 rlwinm. %4,%1,%h2,%m3,%M3
4131 [(set_attr "type" "shift")
4132 (set_attr "dot" "yes")
4133 (set_attr "length" "4,8")])
4136 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4138 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4139 (match_operand:SI 2 "const_int_operand" ""))
4140 (match_operand:SI 3 "mask_operand" ""))
4142 (clobber (match_scratch:SI 4 ""))]
4143 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4145 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4148 (compare:CC (match_dup 4)
4153 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4155 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4156 (match_operand:SI 2 "const_int_operand" "i,i"))
4157 (match_operand:SI 3 "mask_operand" "n,n"))
4159 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4160 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4161 "includes_lshift_p (operands[2], operands[3])"
4163 rlwinm. %0,%1,%h2,%m3,%M3
4165 [(set_attr "type" "shift")
4166 (set_attr "dot" "yes")
4167 (set_attr "length" "4,8")])
4170 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4172 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4173 (match_operand:SI 2 "const_int_operand" ""))
4174 (match_operand:SI 3 "mask_operand" ""))
4176 (set (match_operand:SI 0 "gpc_reg_operand" "")
4177 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4178 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4180 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4182 (compare:CC (match_dup 0)
4187 (define_insn "lshr<mode>3"
4188 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4189 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4190 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4192 "sr<wd>%I2 %0,%1,%<hH>2"
4193 [(set_attr "type" "shift")
4194 (set_attr "maybe_var_shift" "yes")])
4196 (define_insn "*lshrsi3_64"
4197 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4199 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4200 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4203 [(set_attr "type" "shift")
4204 (set_attr "maybe_var_shift" "yes")])
4206 (define_insn_and_split "*lshr<mode>3_dot"
4207 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4208 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4209 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4211 (clobber (match_scratch:GPR 0 "=r,r"))]
4212 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4214 sr<wd>%I2. %0,%1,%<hH>2
4216 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4218 (lshiftrt:GPR (match_dup 1)
4221 (compare:CC (match_dup 0)
4224 [(set_attr "type" "shift")
4225 (set_attr "maybe_var_shift" "yes")
4226 (set_attr "dot" "yes")
4227 (set_attr "length" "4,8")])
4229 (define_insn_and_split "*lshr<mode>3_dot2"
4230 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4231 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4232 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4234 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4235 (lshiftrt:GPR (match_dup 1)
4237 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4239 sr<wd>%I2. %0,%1,%<hH>2
4241 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4243 (lshiftrt:GPR (match_dup 1)
4246 (compare:CC (match_dup 0)
4249 [(set_attr "type" "shift")
4250 (set_attr "maybe_var_shift" "yes")
4251 (set_attr "dot" "yes")
4252 (set_attr "length" "4,8")])
4256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4257 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4258 (match_operand:SI 2 "const_int_operand" "i"))
4259 (match_operand:SI 3 "mask_operand" "n")))]
4260 "includes_rshift_p (operands[2], operands[3])"
4261 "rlwinm %0,%1,%s2,%m3,%M3"
4262 [(set_attr "type" "shift")])
4265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4267 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4268 (match_operand:SI 2 "const_int_operand" "i,i"))
4269 (match_operand:SI 3 "mask_operand" "n,n"))
4271 (clobber (match_scratch:SI 4 "=r,r"))]
4272 "includes_rshift_p (operands[2], operands[3])"
4274 rlwinm. %4,%1,%s2,%m3,%M3
4276 [(set_attr "type" "shift")
4277 (set_attr "dot" "yes")
4278 (set_attr "length" "4,8")])
4281 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4283 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4284 (match_operand:SI 2 "const_int_operand" ""))
4285 (match_operand:SI 3 "mask_operand" ""))
4287 (clobber (match_scratch:SI 4 ""))]
4288 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4290 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4293 (compare:CC (match_dup 4)
4298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4300 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4301 (match_operand:SI 2 "const_int_operand" "i,i"))
4302 (match_operand:SI 3 "mask_operand" "n,n"))
4304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4305 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4306 "includes_rshift_p (operands[2], operands[3])"
4308 rlwinm. %0,%1,%s2,%m3,%M3
4310 [(set_attr "type" "shift")
4311 (set_attr "dot" "yes")
4312 (set_attr "length" "4,8")])
4315 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4317 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4318 (match_operand:SI 2 "const_int_operand" ""))
4319 (match_operand:SI 3 "mask_operand" ""))
4321 (set (match_operand:SI 0 "gpc_reg_operand" "")
4322 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4323 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4325 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4327 (compare:CC (match_dup 0)
4331 (define_insn "*lshiftrt_internal1le"
4332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4335 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4336 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4337 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4338 "rlwinm %0,%1,%s2,0xff"
4339 [(set_attr "type" "shift")])
4341 (define_insn "*lshiftrt_internal1be"
4342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4345 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4346 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4347 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4348 "rlwinm %0,%1,%s2,0xff"
4349 [(set_attr "type" "shift")])
4351 (define_insn "*lshiftrt_internal2le"
4352 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4356 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4357 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4359 (clobber (match_scratch:SI 3 "=r,r"))]
4360 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4362 rlwinm. %3,%1,%s2,0xff
4364 [(set_attr "type" "shift")
4365 (set_attr "dot" "yes")
4366 (set_attr "length" "4,8")])
4368 (define_insn "*lshiftrt_internal2be"
4369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4373 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4374 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4376 (clobber (match_scratch:SI 3 "=r,r"))]
4377 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4379 rlwinm. %3,%1,%s2,0xff
4381 [(set_attr "type" "shift")
4382 (set_attr "dot" "yes")
4383 (set_attr "length" "4,8")])
4386 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4390 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4391 (match_operand:SI 2 "const_int_operand" "")) 0))
4393 (clobber (match_scratch:SI 3 ""))]
4394 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4396 (zero_extend:SI (subreg:QI
4397 (lshiftrt:SI (match_dup 1)
4400 (compare:CC (match_dup 3)
4405 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4409 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4410 (match_operand:SI 2 "const_int_operand" "")) 3))
4412 (clobber (match_scratch:SI 3 ""))]
4413 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4415 (zero_extend:SI (subreg:QI
4416 (lshiftrt:SI (match_dup 1)
4419 (compare:CC (match_dup 3)
4423 (define_insn "*lshiftrt_internal3le"
4424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4428 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4429 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4431 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4432 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4433 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4435 rlwinm. %0,%1,%s2,0xff
4437 [(set_attr "type" "shift")
4438 (set_attr "dot" "yes")
4439 (set_attr "length" "4,8")])
4441 (define_insn "*lshiftrt_internal3be"
4442 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4446 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4447 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4450 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4451 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4453 rlwinm. %0,%1,%s2,0xff
4455 [(set_attr "type" "shift")
4456 (set_attr "dot" "yes")
4457 (set_attr "length" "4,8")])
4460 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4464 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4465 (match_operand:SI 2 "const_int_operand" "")) 0))
4467 (set (match_operand:SI 0 "gpc_reg_operand" "")
4468 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4469 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4471 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4473 (compare:CC (match_dup 0)
4478 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4482 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4483 (match_operand:SI 2 "const_int_operand" "")) 3))
4485 (set (match_operand:SI 0 "gpc_reg_operand" "")
4486 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4487 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4489 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4491 (compare:CC (match_dup 0)
4495 (define_insn "*lshiftrt_internal4le"
4496 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4499 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4500 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4501 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4502 "rlwinm %0,%1,%s2,0xffff"
4503 [(set_attr "type" "shift")])
4505 (define_insn "*lshiftrt_internal4be"
4506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4509 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4510 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4511 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4512 "rlwinm %0,%1,%s2,0xffff"
4513 [(set_attr "type" "shift")])
4515 (define_insn "*lshiftrt_internal5le"
4516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4520 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4521 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4523 (clobber (match_scratch:SI 3 "=r,r"))]
4524 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4526 rlwinm. %3,%1,%s2,0xffff
4528 [(set_attr "type" "shift")
4529 (set_attr "dot" "yes")
4530 (set_attr "length" "4,8")])
4532 (define_insn "*lshiftrt_internal5be"
4533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4537 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4538 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4540 (clobber (match_scratch:SI 3 "=r,r"))]
4541 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4543 rlwinm. %3,%1,%s2,0xffff
4545 [(set_attr "type" "shift")
4546 (set_attr "dot" "yes")
4547 (set_attr "length" "4,8")])
4550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4554 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4555 (match_operand:SI 2 "const_int_operand" "")) 0))
4557 (clobber (match_scratch:SI 3 ""))]
4558 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4560 (zero_extend:SI (subreg:HI
4561 (lshiftrt:SI (match_dup 1)
4564 (compare:CC (match_dup 3)
4569 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4573 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4574 (match_operand:SI 2 "const_int_operand" "")) 2))
4576 (clobber (match_scratch:SI 3 ""))]
4577 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4579 (zero_extend:SI (subreg:HI
4580 (lshiftrt:SI (match_dup 1)
4583 (compare:CC (match_dup 3)
4587 (define_insn "*lshiftrt_internal5le"
4588 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4592 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4593 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4596 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4597 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4599 rlwinm. %0,%1,%s2,0xffff
4601 [(set_attr "type" "shift")
4602 (set_attr "dot" "yes")
4603 (set_attr "length" "4,8")])
4605 (define_insn "*lshiftrt_internal5be"
4606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4610 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4611 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4613 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4614 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4615 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4617 rlwinm. %0,%1,%s2,0xffff
4619 [(set_attr "type" "shift")
4620 (set_attr "dot" "yes")
4621 (set_attr "length" "4,8")])
4624 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4628 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4629 (match_operand:SI 2 "const_int_operand" "")) 0))
4631 (set (match_operand:SI 0 "gpc_reg_operand" "")
4632 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4633 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4635 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4637 (compare:CC (match_dup 0)
4642 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4646 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4647 (match_operand:SI 2 "const_int_operand" "")) 2))
4649 (set (match_operand:SI 0 "gpc_reg_operand" "")
4650 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4651 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4653 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4655 (compare:CC (match_dup 0)
4660 (define_expand "ashr<mode>3"
4661 [(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4662 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4663 (match_operand:SI 2 "reg_or_cint_operand" "")))
4664 (clobber (reg:GPR CA_REGNO))])]
4667 /* The generic code does not generate optimal code for the low word
4668 (it should be a rlwimi and a rot). Until we have target code to
4669 solve this generically, keep this expander. */
4671 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4673 if (CONST_INT_P (operands[2]))
4675 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4683 (define_insn "*ashr<mode>3"
4684 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4685 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4686 (match_operand:SI 2 "reg_or_cint_operand" "rn")))
4687 (clobber (reg:GPR CA_REGNO))]
4689 "sra<wd>%I2 %0,%1,%<hH>2"
4690 [(set_attr "type" "shift")
4691 (set_attr "maybe_var_shift" "yes")])
4693 (define_insn "*ashrsi3_64"
4694 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4696 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4697 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))
4698 (clobber (reg:SI CA_REGNO))]
4701 [(set_attr "type" "shift")
4702 (set_attr "maybe_var_shift" "yes")])
4704 (define_insn_and_split "*ashr<mode>3_dot"
4705 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4706 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4707 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4709 (clobber (match_scratch:GPR 0 "=r,r"))
4710 (clobber (reg:GPR CA_REGNO))]
4711 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4713 sra<wd>%I2. %0,%1,%<hH>2
4715 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4716 [(parallel [(set (match_dup 0)
4717 (ashiftrt:GPR (match_dup 1)
4719 (clobber (reg:GPR CA_REGNO))])
4721 (compare:CC (match_dup 0)
4724 [(set_attr "type" "shift")
4725 (set_attr "maybe_var_shift" "yes")
4726 (set_attr "dot" "yes")
4727 (set_attr "length" "4,8")])
4729 (define_insn_and_split "*ashr<mode>3_dot2"
4730 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4731 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4732 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4734 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4735 (ashiftrt:GPR (match_dup 1)
4737 (clobber (reg:GPR CA_REGNO))]
4738 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4740 sra<wd>%I2. %0,%1,%<hH>2
4742 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4743 [(parallel [(set (match_dup 0)
4744 (ashiftrt:GPR (match_dup 1)
4746 (clobber (reg:GPR CA_REGNO))])
4748 (compare:CC (match_dup 0)
4751 [(set_attr "type" "shift")
4752 (set_attr "maybe_var_shift" "yes")
4753 (set_attr "dot" "yes")
4754 (set_attr "length" "4,8")])
4756 ;; Builtins to replace a division to generate FRE reciprocal estimate
4757 ;; instructions and the necessary fixup instructions
4758 (define_expand "recip<mode>3"
4759 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4760 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4761 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4762 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4764 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4768 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4769 ;; hardware division. This is only done before register allocation and with
4770 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4772 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4773 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4774 (match_operand 2 "gpc_reg_operand" "")))]
4775 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4776 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4777 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4780 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4784 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4785 ;; appropriate fixup.
4786 (define_expand "rsqrt<mode>2"
4787 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4788 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4789 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4791 rs6000_emit_swrsqrt (operands[0], operands[1]);
4795 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4796 ;; modes here, and also add in conditional vsx/power8-vector support to access
4797 ;; values in the traditional Altivec registers if the appropriate
4798 ;; -mupper-regs-{df,sf} option is enabled.
4800 (define_expand "abs<mode>2"
4801 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4802 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4803 "TARGET_<MODE>_INSN"
4806 (define_insn "*abs<mode>2_fpr"
4807 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4808 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4813 [(set_attr "type" "fp")
4814 (set_attr "fp_type" "fp_addsub_<Fs>")])
4816 (define_insn "*nabs<mode>2_fpr"
4817 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4820 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4825 [(set_attr "type" "fp")
4826 (set_attr "fp_type" "fp_addsub_<Fs>")])
4828 (define_expand "neg<mode>2"
4829 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4830 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4831 "TARGET_<MODE>_INSN"
4834 (define_insn "*neg<mode>2_fpr"
4835 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4836 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4841 [(set_attr "type" "fp")
4842 (set_attr "fp_type" "fp_addsub_<Fs>")])
4844 (define_expand "add<mode>3"
4845 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4846 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4847 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4848 "TARGET_<MODE>_INSN"
4851 (define_insn "*add<mode>3_fpr"
4852 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4853 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4854 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4857 fadd<Ftrad> %0,%1,%2
4858 xsadd<Fvsx> %x0,%x1,%x2"
4859 [(set_attr "type" "fp")
4860 (set_attr "fp_type" "fp_addsub_<Fs>")])
4862 (define_expand "sub<mode>3"
4863 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4864 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4865 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4866 "TARGET_<MODE>_INSN"
4869 (define_insn "*sub<mode>3_fpr"
4870 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4871 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4872 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4875 fsub<Ftrad> %0,%1,%2
4876 xssub<Fvsx> %x0,%x1,%x2"
4877 [(set_attr "type" "fp")
4878 (set_attr "fp_type" "fp_addsub_<Fs>")])
4880 (define_expand "mul<mode>3"
4881 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4882 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4883 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4884 "TARGET_<MODE>_INSN"
4887 (define_insn "*mul<mode>3_fpr"
4888 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4889 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4890 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4893 fmul<Ftrad> %0,%1,%2
4894 xsmul<Fvsx> %x0,%x1,%x2"
4895 [(set_attr "type" "dmul")
4896 (set_attr "fp_type" "fp_mul_<Fs>")])
4898 (define_expand "div<mode>3"
4899 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4900 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4901 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4902 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4905 (define_insn "*div<mode>3_fpr"
4906 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4907 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4908 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4909 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4911 fdiv<Ftrad> %0,%1,%2
4912 xsdiv<Fvsx> %x0,%x1,%x2"
4913 [(set_attr "type" "<Fs>div")
4914 (set_attr "fp_type" "fp_div_<Fs>")])
4916 (define_insn "sqrt<mode>2"
4917 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4918 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4919 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4920 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4923 xssqrt<Fvsx> %x0,%x1"
4924 [(set_attr "type" "<Fs>sqrt")
4925 (set_attr "fp_type" "fp_sqrt_<Fs>")])
4927 ;; Floating point reciprocal approximation
4928 (define_insn "fre<Fs>"
4929 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4930 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4936 [(set_attr "type" "fp")])
4938 (define_insn "*rsqrt<mode>2"
4939 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4940 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4942 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4944 frsqrte<Ftrad> %0,%1
4945 xsrsqrte<Fvsx> %x0,%x1"
4946 [(set_attr "type" "fp")])
4948 ;; Floating point comparisons
4949 (define_insn "*cmp<mode>_fpr"
4950 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
4951 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4952 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4956 xscmpudp %0,%x1,%x2"
4957 [(set_attr "type" "fpcompare")])
4959 ;; Floating point conversions
4960 (define_expand "extendsfdf2"
4961 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4962 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4963 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4966 (define_insn_and_split "*extendsfdf2_fpr"
4967 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu")
4968 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
4969 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4977 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4980 emit_note (NOTE_INSN_DELETED);
4983 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
4985 (define_expand "truncdfsf2"
4986 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4987 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4988 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4991 (define_insn "*truncdfsf2_fpr"
4992 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4993 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4994 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4996 [(set_attr "type" "fp")])
4998 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
4999 ;; builtins.c and optabs.c that are not correct for IBM long double
5000 ;; when little-endian.
5001 (define_expand "signbittf2"
5003 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5005 (subreg:DI (match_dup 2) 0))
5008 (set (match_operand:SI 0 "gpc_reg_operand" "")
5011 && TARGET_HARD_FLOAT
5012 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5013 && TARGET_LONG_DOUBLE_128"
5015 operands[2] = gen_reg_rtx (DFmode);
5016 operands[3] = gen_reg_rtx (DImode);
5017 if (TARGET_POWERPC64)
5019 operands[4] = gen_reg_rtx (DImode);
5020 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5021 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5022 WORDS_BIG_ENDIAN ? 4 : 0);
5026 operands[4] = gen_reg_rtx (SImode);
5027 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5028 WORDS_BIG_ENDIAN ? 0 : 4);
5029 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5033 (define_expand "copysign<mode>3"
5035 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5037 (neg:SFDF (abs:SFDF (match_dup 1))))
5038 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5039 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5043 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5044 && ((TARGET_PPC_GFXOPT
5045 && !HONOR_NANS (<MODE>mode)
5046 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5048 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5050 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5052 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5057 operands[3] = gen_reg_rtx (<MODE>mode);
5058 operands[4] = gen_reg_rtx (<MODE>mode);
5059 operands[5] = CONST0_RTX (<MODE>mode);
5062 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5063 ;; compiler from optimizing -0.0
5064 (define_insn "copysign<mode>3_fcpsgn"
5065 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5066 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5067 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5069 "TARGET_<MODE>_FPR && TARGET_CMPB"
5072 xscpsgndp %x0,%x2,%x1"
5073 [(set_attr "type" "fp")])
5075 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5076 ;; fsel instruction and some auxiliary computations. Then we just have a
5077 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5079 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5080 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5081 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5082 ;; define_splits to make them if made by combine. On VSX machines we have the
5083 ;; min/max instructions.
5085 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5086 ;; to allow either DF/SF to use only traditional registers.
5088 (define_expand "smax<mode>3"
5089 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5090 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5091 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5094 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5096 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5100 (define_insn "*smax<mode>3_vsx"
5101 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5102 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5103 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5104 "TARGET_<MODE>_FPR && TARGET_VSX"
5105 "xsmaxdp %x0,%x1,%x2"
5106 [(set_attr "type" "fp")])
5108 (define_expand "smin<mode>3"
5109 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5110 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5111 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5114 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5116 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5120 (define_insn "*smin<mode>3_vsx"
5121 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5122 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5123 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5124 "TARGET_<MODE>_FPR && TARGET_VSX"
5125 "xsmindp %x0,%x1,%x2"
5126 [(set_attr "type" "fp")])
5129 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5130 (match_operator:SFDF 3 "min_max_operator"
5131 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5132 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5133 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5137 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5143 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5144 (match_operator:SF 3 "min_max_operator"
5145 [(match_operand:SF 1 "gpc_reg_operand" "")
5146 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5147 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5148 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5151 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5152 operands[1], operands[2]);
5156 (define_expand "mov<mode>cc"
5157 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5158 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5159 (match_operand:GPR 2 "gpc_reg_operand" "")
5160 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5164 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5170 ;; We use the BASE_REGS for the isel input operands because, if rA is
5171 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5172 ;; because we may switch the operands and rB may end up being rA.
5174 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5175 ;; leave out the mode in operand 4 and use one pattern, but reload can
5176 ;; change the mode underneath our feet and then gets confused trying
5177 ;; to reload the value.
5178 (define_insn "isel_signed_<mode>"
5179 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5181 (match_operator 1 "scc_comparison_operator"
5182 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5184 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5185 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5188 { return output_isel (operands); }"
5189 [(set_attr "type" "isel")
5190 (set_attr "length" "4")])
5192 (define_insn "isel_unsigned_<mode>"
5193 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5195 (match_operator 1 "scc_comparison_operator"
5196 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5198 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5199 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5202 { return output_isel (operands); }"
5203 [(set_attr "type" "isel")
5204 (set_attr "length" "4")])
5206 ;; These patterns can be useful for combine; they let combine know that
5207 ;; isel can handle reversed comparisons so long as the operands are
5210 (define_insn "*isel_reversed_signed_<mode>"
5211 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5213 (match_operator 1 "scc_rev_comparison_operator"
5214 [(match_operand:CC 4 "cc_reg_operand" "y")
5216 (match_operand:GPR 2 "gpc_reg_operand" "b")
5217 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5220 { return output_isel (operands); }"
5221 [(set_attr "type" "isel")
5222 (set_attr "length" "4")])
5224 (define_insn "*isel_reversed_unsigned_<mode>"
5225 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5227 (match_operator 1 "scc_rev_comparison_operator"
5228 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5230 (match_operand:GPR 2 "gpc_reg_operand" "b")
5231 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5234 { return output_isel (operands); }"
5235 [(set_attr "type" "isel")
5236 (set_attr "length" "4")])
5238 (define_expand "movsfcc"
5239 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5240 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5241 (match_operand:SF 2 "gpc_reg_operand" "")
5242 (match_operand:SF 3 "gpc_reg_operand" "")))]
5243 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5246 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5252 (define_insn "*fselsfsf4"
5253 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5254 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5255 (match_operand:SF 4 "zero_fp_constant" "F"))
5256 (match_operand:SF 2 "gpc_reg_operand" "f")
5257 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5258 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5260 [(set_attr "type" "fp")])
5262 (define_insn "*fseldfsf4"
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5265 (match_operand:DF 4 "zero_fp_constant" "F"))
5266 (match_operand:SF 2 "gpc_reg_operand" "f")
5267 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5268 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5270 [(set_attr "type" "fp")])
5272 ;; The conditional move instructions allow us to perform max and min
5273 ;; operations even when
5276 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5277 (match_operator:DF 3 "min_max_operator"
5278 [(match_operand:DF 1 "gpc_reg_operand" "")
5279 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5280 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5281 && !flag_trapping_math"
5284 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5285 operands[1], operands[2]);
5289 (define_expand "movdfcc"
5290 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5291 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5292 (match_operand:DF 2 "gpc_reg_operand" "")
5293 (match_operand:DF 3 "gpc_reg_operand" "")))]
5294 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5297 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5303 (define_insn "*fseldfdf4"
5304 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5305 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5306 (match_operand:DF 4 "zero_fp_constant" "F"))
5307 (match_operand:DF 2 "gpc_reg_operand" "d")
5308 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5309 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5311 [(set_attr "type" "fp")])
5313 (define_insn "*fselsfdf4"
5314 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5315 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5316 (match_operand:SF 4 "zero_fp_constant" "F"))
5317 (match_operand:DF 2 "gpc_reg_operand" "d")
5318 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5319 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5321 [(set_attr "type" "fp")])
5323 ;; Conversions to and from floating-point.
5325 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5326 ; don't want to support putting SImode in FPR registers.
5327 (define_insn "lfiwax"
5328 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5329 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5331 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5336 [(set_attr "type" "fpload,fpload,mffgpr")])
5338 ; This split must be run before register allocation because it allocates the
5339 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5340 ; it earlier to allow for the combiner to merge insns together where it might
5341 ; not be needed and also in case the insns are deleted as dead code.
5343 (define_insn_and_split "floatsi<mode>2_lfiwax"
5344 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5345 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5346 (clobber (match_scratch:DI 2 "=wj"))]
5347 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5348 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5354 rtx dest = operands[0];
5355 rtx src = operands[1];
5358 if (!MEM_P (src) && TARGET_POWERPC64
5359 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5360 tmp = convert_to_mode (DImode, src, false);
5364 if (GET_CODE (tmp) == SCRATCH)
5365 tmp = gen_reg_rtx (DImode);
5368 src = rs6000_address_for_fpconvert (src);
5369 emit_insn (gen_lfiwax (tmp, src));
5373 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5374 emit_move_insn (stack, src);
5375 emit_insn (gen_lfiwax (tmp, stack));
5378 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5381 [(set_attr "length" "12")
5382 (set_attr "type" "fpload")])
5384 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5385 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5388 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5389 (clobber (match_scratch:DI 2 "=0,d"))]
5390 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5397 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5398 if (GET_CODE (operands[2]) == SCRATCH)
5399 operands[2] = gen_reg_rtx (DImode);
5400 emit_insn (gen_lfiwax (operands[2], operands[1]));
5401 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5404 [(set_attr "length" "8")
5405 (set_attr "type" "fpload")])
5407 (define_insn "lfiwzx"
5408 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5409 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5411 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5416 [(set_attr "type" "fpload,fpload,mftgpr")])
5418 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5419 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5420 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5421 (clobber (match_scratch:DI 2 "=wj"))]
5422 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5429 rtx dest = operands[0];
5430 rtx src = operands[1];
5433 if (!MEM_P (src) && TARGET_POWERPC64
5434 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5435 tmp = convert_to_mode (DImode, src, true);
5439 if (GET_CODE (tmp) == SCRATCH)
5440 tmp = gen_reg_rtx (DImode);
5443 src = rs6000_address_for_fpconvert (src);
5444 emit_insn (gen_lfiwzx (tmp, src));
5448 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5449 emit_move_insn (stack, src);
5450 emit_insn (gen_lfiwzx (tmp, stack));
5453 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5456 [(set_attr "length" "12")
5457 (set_attr "type" "fpload")])
5459 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5460 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5461 (unsigned_float:SFDF
5463 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5464 (clobber (match_scratch:DI 2 "=0,d"))]
5465 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5472 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5473 if (GET_CODE (operands[2]) == SCRATCH)
5474 operands[2] = gen_reg_rtx (DImode);
5475 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5476 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5479 [(set_attr "length" "8")
5480 (set_attr "type" "fpload")])
5482 ; For each of these conversions, there is a define_expand, a define_insn
5483 ; with a '#' template, and a define_split (with C code). The idea is
5484 ; to allow constant folding with the template of the define_insn,
5485 ; then to have the insns split later (between sched1 and final).
5487 (define_expand "floatsidf2"
5488 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5489 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5492 (clobber (match_dup 4))
5493 (clobber (match_dup 5))
5494 (clobber (match_dup 6))])]
5496 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5499 if (TARGET_E500_DOUBLE)
5501 if (!REG_P (operands[1]))
5502 operands[1] = force_reg (SImode, operands[1]);
5503 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5506 else if (TARGET_LFIWAX && TARGET_FCFID)
5508 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5511 else if (TARGET_FCFID)
5513 rtx dreg = operands[1];
5515 dreg = force_reg (SImode, dreg);
5516 dreg = convert_to_mode (DImode, dreg, false);
5517 emit_insn (gen_floatdidf2 (operands[0], dreg));
5521 if (!REG_P (operands[1]))
5522 operands[1] = force_reg (SImode, operands[1]);
5523 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5524 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5525 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5526 operands[5] = gen_reg_rtx (DFmode);
5527 operands[6] = gen_reg_rtx (SImode);
5530 (define_insn_and_split "*floatsidf2_internal"
5531 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5532 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5533 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5534 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5535 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5536 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5537 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5538 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5544 rtx lowword, highword;
5545 gcc_assert (MEM_P (operands[4]));
5546 highword = adjust_address (operands[4], SImode, 0);
5547 lowword = adjust_address (operands[4], SImode, 4);
5548 if (! WORDS_BIG_ENDIAN)
5549 std::swap (lowword, highword);
5551 emit_insn (gen_xorsi3 (operands[6], operands[1],
5552 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5553 emit_move_insn (lowword, operands[6]);
5554 emit_move_insn (highword, operands[2]);
5555 emit_move_insn (operands[5], operands[4]);
5556 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5559 [(set_attr "length" "24")
5560 (set_attr "type" "fp")])
5562 ;; If we don't have a direct conversion to single precision, don't enable this
5563 ;; conversion for 32-bit without fast math, because we don't have the insn to
5564 ;; generate the fixup swizzle to avoid double rounding problems.
5565 (define_expand "floatunssisf2"
5566 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5567 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5568 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5571 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5572 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5573 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5578 if (!REG_P (operands[1]))
5579 operands[1] = force_reg (SImode, operands[1]);
5581 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5583 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5588 rtx dreg = operands[1];
5590 dreg = force_reg (SImode, dreg);
5591 dreg = convert_to_mode (DImode, dreg, true);
5592 emit_insn (gen_floatdisf2 (operands[0], dreg));
5597 (define_expand "floatunssidf2"
5598 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5599 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5602 (clobber (match_dup 4))
5603 (clobber (match_dup 5))])]
5605 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5608 if (TARGET_E500_DOUBLE)
5610 if (!REG_P (operands[1]))
5611 operands[1] = force_reg (SImode, operands[1]);
5612 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5615 else if (TARGET_LFIWZX && TARGET_FCFID)
5617 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5620 else if (TARGET_FCFID)
5622 rtx dreg = operands[1];
5624 dreg = force_reg (SImode, dreg);
5625 dreg = convert_to_mode (DImode, dreg, true);
5626 emit_insn (gen_floatdidf2 (operands[0], dreg));
5630 if (!REG_P (operands[1]))
5631 operands[1] = force_reg (SImode, operands[1]);
5632 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5633 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5634 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5635 operands[5] = gen_reg_rtx (DFmode);
5638 (define_insn_and_split "*floatunssidf2_internal"
5639 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5640 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5641 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5642 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5643 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5644 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5645 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5646 && !(TARGET_FCFID && TARGET_POWERPC64)"
5652 rtx lowword, highword;
5653 gcc_assert (MEM_P (operands[4]));
5654 highword = adjust_address (operands[4], SImode, 0);
5655 lowword = adjust_address (operands[4], SImode, 4);
5656 if (! WORDS_BIG_ENDIAN)
5657 std::swap (lowword, highword);
5659 emit_move_insn (lowword, operands[1]);
5660 emit_move_insn (highword, operands[2]);
5661 emit_move_insn (operands[5], operands[4]);
5662 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5665 [(set_attr "length" "20")
5666 (set_attr "type" "fp")])
5668 (define_expand "fix_trunc<mode>si2"
5669 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5670 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5671 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5674 if (!<E500_CONVERT>)
5679 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5682 tmp = gen_reg_rtx (DImode);
5683 stack = rs6000_allocate_stack_temp (DImode, true, false);
5684 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5691 ; Like the convert to float patterns, this insn must be split before
5692 ; register allocation so that it can allocate the memory slot if it
5694 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5695 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5696 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5697 (clobber (match_scratch:DI 2 "=d"))]
5698 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5699 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5700 && TARGET_STFIWX && can_create_pseudo_p ()"
5705 rtx dest = operands[0];
5706 rtx src = operands[1];
5707 rtx tmp = operands[2];
5709 if (GET_CODE (tmp) == SCRATCH)
5710 tmp = gen_reg_rtx (DImode);
5712 emit_insn (gen_fctiwz_<mode> (tmp, src));
5715 dest = rs6000_address_for_fpconvert (dest);
5716 emit_insn (gen_stfiwx (dest, tmp));
5719 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5721 dest = gen_lowpart (DImode, dest);
5722 emit_move_insn (dest, tmp);
5727 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5728 emit_insn (gen_stfiwx (stack, tmp));
5729 emit_move_insn (dest, stack);
5733 [(set_attr "length" "12")
5734 (set_attr "type" "fp")])
5736 (define_insn_and_split "fix_trunc<mode>si2_internal"
5737 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5738 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5739 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5740 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5741 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5748 gcc_assert (MEM_P (operands[3]));
5749 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5751 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5752 emit_move_insn (operands[3], operands[2]);
5753 emit_move_insn (operands[0], lowword);
5756 [(set_attr "length" "16")
5757 (set_attr "type" "fp")])
5759 (define_expand "fix_trunc<mode>di2"
5760 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5761 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5762 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5766 (define_insn "*fix_trunc<mode>di2_fctidz"
5767 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5768 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
5769 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5774 [(set_attr "type" "fp")])
5776 (define_expand "fixuns_trunc<mode>si2"
5777 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5778 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5780 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5784 if (!<E500_CONVERT>)
5786 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5791 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5792 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5793 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5794 (clobber (match_scratch:DI 2 "=d"))]
5795 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5796 && TARGET_STFIWX && can_create_pseudo_p ()"
5801 rtx dest = operands[0];
5802 rtx src = operands[1];
5803 rtx tmp = operands[2];
5805 if (GET_CODE (tmp) == SCRATCH)
5806 tmp = gen_reg_rtx (DImode);
5808 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5811 dest = rs6000_address_for_fpconvert (dest);
5812 emit_insn (gen_stfiwx (dest, tmp));
5815 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5817 dest = gen_lowpart (DImode, dest);
5818 emit_move_insn (dest, tmp);
5823 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5824 emit_insn (gen_stfiwx (stack, tmp));
5825 emit_move_insn (dest, stack);
5829 [(set_attr "length" "12")
5830 (set_attr "type" "fp")])
5832 (define_expand "fixuns_trunc<mode>di2"
5833 [(set (match_operand:DI 0 "register_operand" "")
5834 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5835 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5838 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5839 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5840 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
5841 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5846 [(set_attr "type" "fp")])
5848 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5849 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5850 ; because the first makes it clear that operand 0 is not live
5851 ; before the instruction.
5852 (define_insn "fctiwz_<mode>"
5853 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5854 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5856 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5860 [(set_attr "type" "fp")])
5862 (define_insn "fctiwuz_<mode>"
5863 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5864 (unspec:DI [(unsigned_fix:SI
5865 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5867 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5871 [(set_attr "type" "fp")])
5873 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5874 ;; since the friz instruction does not truncate the value if the floating
5875 ;; point value is < LONG_MIN or > LONG_MAX.
5876 (define_insn "*friz"
5877 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5878 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
5879 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5880 && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
5884 [(set_attr "type" "fp")])
5886 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5887 ;; load to properly sign extend the value, but at least doing a store, load
5888 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5889 ;; if we have 32-bit memory ops
5890 (define_insn_and_split "*round32<mode>2_fprs"
5891 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5893 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5894 (clobber (match_scratch:DI 2 "=d"))
5895 (clobber (match_scratch:DI 3 "=d"))]
5896 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5897 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5898 && can_create_pseudo_p ()"
5903 rtx dest = operands[0];
5904 rtx src = operands[1];
5905 rtx tmp1 = operands[2];
5906 rtx tmp2 = operands[3];
5907 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5909 if (GET_CODE (tmp1) == SCRATCH)
5910 tmp1 = gen_reg_rtx (DImode);
5911 if (GET_CODE (tmp2) == SCRATCH)
5912 tmp2 = gen_reg_rtx (DImode);
5914 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5915 emit_insn (gen_stfiwx (stack, tmp1));
5916 emit_insn (gen_lfiwax (tmp2, stack));
5917 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5920 [(set_attr "type" "fpload")
5921 (set_attr "length" "16")])
5923 (define_insn_and_split "*roundu32<mode>2_fprs"
5924 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5925 (unsigned_float:SFDF
5926 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5927 (clobber (match_scratch:DI 2 "=d"))
5928 (clobber (match_scratch:DI 3 "=d"))]
5929 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5930 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5931 && can_create_pseudo_p ()"
5936 rtx dest = operands[0];
5937 rtx src = operands[1];
5938 rtx tmp1 = operands[2];
5939 rtx tmp2 = operands[3];
5940 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5942 if (GET_CODE (tmp1) == SCRATCH)
5943 tmp1 = gen_reg_rtx (DImode);
5944 if (GET_CODE (tmp2) == SCRATCH)
5945 tmp2 = gen_reg_rtx (DImode);
5947 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5948 emit_insn (gen_stfiwx (stack, tmp1));
5949 emit_insn (gen_lfiwzx (tmp2, stack));
5950 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5953 [(set_attr "type" "fpload")
5954 (set_attr "length" "16")])
5956 ;; No VSX equivalent to fctid
5957 (define_insn "lrint<mode>di2"
5958 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5959 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5961 "TARGET_<MODE>_FPR && TARGET_FPRND"
5963 [(set_attr "type" "fp")])
5965 (define_insn "btrunc<mode>2"
5966 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5967 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5969 "TARGET_<MODE>_FPR && TARGET_FPRND"
5973 [(set_attr "type" "fp")
5974 (set_attr "fp_type" "fp_addsub_<Fs>")])
5976 (define_insn "ceil<mode>2"
5977 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5978 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5980 "TARGET_<MODE>_FPR && TARGET_FPRND"
5984 [(set_attr "type" "fp")
5985 (set_attr "fp_type" "fp_addsub_<Fs>")])
5987 (define_insn "floor<mode>2"
5988 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5989 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5991 "TARGET_<MODE>_FPR && TARGET_FPRND"
5995 [(set_attr "type" "fp")
5996 (set_attr "fp_type" "fp_addsub_<Fs>")])
5998 ;; No VSX equivalent to frin
5999 (define_insn "round<mode>2"
6000 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6001 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6003 "TARGET_<MODE>_FPR && TARGET_FPRND"
6005 [(set_attr "type" "fp")
6006 (set_attr "fp_type" "fp_addsub_<Fs>")])
6008 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6009 (define_insn "stfiwx"
6010 [(set (match_operand:SI 0 "memory_operand" "=Z")
6011 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6015 [(set_attr "type" "fpstore")])
6017 ;; If we don't have a direct conversion to single precision, don't enable this
6018 ;; conversion for 32-bit without fast math, because we don't have the insn to
6019 ;; generate the fixup swizzle to avoid double rounding problems.
6020 (define_expand "floatsisf2"
6021 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6022 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6023 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6026 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6027 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6028 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6033 if (!REG_P (operands[1]))
6034 operands[1] = force_reg (SImode, operands[1]);
6036 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6038 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6041 else if (TARGET_FCFID && TARGET_LFIWAX)
6043 rtx dfreg = gen_reg_rtx (DFmode);
6044 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6045 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6050 rtx dreg = operands[1];
6052 dreg = force_reg (SImode, dreg);
6053 dreg = convert_to_mode (DImode, dreg, false);
6054 emit_insn (gen_floatdisf2 (operands[0], dreg));
6059 (define_expand "floatdidf2"
6060 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6061 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6062 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6065 (define_insn "*floatdidf2_fpr"
6066 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6067 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6068 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6072 [(set_attr "type" "fp")])
6074 ; Allow the combiner to merge source memory operands to the conversion so that
6075 ; the optimizer/register allocator doesn't try to load the value too early in a
6076 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6077 ; hit. We will split after reload to avoid the trip through the GPRs
6079 (define_insn_and_split "*floatdidf2_mem"
6080 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6081 (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6082 (clobber (match_scratch:DI 2 "=d,wi"))]
6083 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6085 "&& reload_completed"
6086 [(set (match_dup 2) (match_dup 1))
6087 (set (match_dup 0) (float:DF (match_dup 2)))]
6089 [(set_attr "length" "8")
6090 (set_attr "type" "fpload")])
6092 (define_expand "floatunsdidf2"
6093 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6095 (match_operand:DI 1 "gpc_reg_operand" "")))]
6096 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6099 (define_insn "*floatunsdidf2_fcfidu"
6100 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6101 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6102 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6106 [(set_attr "type" "fp")
6107 (set_attr "length" "4")])
6109 (define_insn_and_split "*floatunsdidf2_mem"
6110 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6111 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6112 (clobber (match_scratch:DI 2 "=d,wi"))]
6113 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6115 "&& reload_completed"
6116 [(set (match_dup 2) (match_dup 1))
6117 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6119 [(set_attr "length" "8")
6120 (set_attr "type" "fpload")])
6122 (define_expand "floatdisf2"
6123 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6124 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6125 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6126 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6131 rtx val = operands[1];
6132 if (!flag_unsafe_math_optimizations)
6134 rtx label = gen_label_rtx ();
6135 val = gen_reg_rtx (DImode);
6136 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6139 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6144 (define_insn "floatdisf2_fcfids"
6145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
6146 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6147 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6148 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6152 [(set_attr "type" "fp")])
6154 (define_insn_and_split "*floatdisf2_mem"
6155 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6156 (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6157 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6158 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6159 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6161 "&& reload_completed"
6165 emit_move_insn (operands[2], operands[1]);
6166 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6169 [(set_attr "length" "8")])
6171 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6172 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6173 ;; from double rounding.
6174 ;; Instead of creating a new cpu type for two FP operations, just use fp
6175 (define_insn_and_split "floatdisf2_internal1"
6176 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6177 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6178 (clobber (match_scratch:DF 2 "=d"))]
6179 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6182 "&& reload_completed"
6184 (float:DF (match_dup 1)))
6186 (float_truncate:SF (match_dup 2)))]
6188 [(set_attr "length" "8")
6189 (set_attr "type" "fp")])
6191 ;; Twiddles bits to avoid double rounding.
6192 ;; Bits that might be truncated when converting to DFmode are replaced
6193 ;; by a bit that won't be lost at that stage, but is below the SFmode
6194 ;; rounding position.
6195 (define_expand "floatdisf2_internal2"
6196 [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6198 (clobber (reg:DI CA_REGNO))])
6199 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6201 (set (match_dup 3) (plus:DI (match_dup 3)
6203 (set (match_dup 0) (plus:DI (match_dup 0)
6205 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6207 (set (match_dup 0) (ior:DI (match_dup 0)
6209 (set (match_dup 0) (and:DI (match_dup 0)
6211 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6212 (label_ref (match_operand:DI 2 "" ""))
6214 (set (match_dup 0) (match_dup 1))]
6215 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6219 operands[3] = gen_reg_rtx (DImode);
6220 operands[4] = gen_reg_rtx (CCUNSmode);
6223 (define_expand "floatunsdisf2"
6224 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6225 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6226 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6227 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6230 (define_insn "floatunsdisf2_fcfidus"
6231 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
6232 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6233 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6234 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6238 [(set_attr "type" "fp")])
6240 (define_insn_and_split "*floatunsdisf2_mem"
6241 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6242 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6243 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6244 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6245 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6247 "&& reload_completed"
6251 emit_move_insn (operands[2], operands[1]);
6252 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6255 [(set_attr "length" "8")
6256 (set_attr "type" "fpload")])
6258 ;; Define the TImode operations that can be done in a small number
6259 ;; of instructions. The & constraints are to prevent the register
6260 ;; allocator from allocating registers that overlap with the inputs
6261 ;; (for example, having an input in 7,8 and an output in 6,7). We
6262 ;; also allow for the output being the same as one of the inputs.
6264 (define_insn "addti3"
6265 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6266 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6267 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6270 if (WORDS_BIG_ENDIAN)
6271 return (GET_CODE (operands[2])) != CONST_INT
6272 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6273 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6275 return (GET_CODE (operands[2])) != CONST_INT
6276 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6277 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6279 [(set_attr "type" "two")
6280 (set_attr "length" "8")])
6282 (define_insn "subti3"
6283 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6284 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6285 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6288 if (WORDS_BIG_ENDIAN)
6289 return (GET_CODE (operands[1]) != CONST_INT)
6290 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6291 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6293 return (GET_CODE (operands[1]) != CONST_INT)
6294 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6295 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6297 [(set_attr "type" "two")
6298 (set_attr "length" "8")])
6301 ;; Define the DImode operations that can be done in a small number
6302 ;; of instructions. The & constraints are to prevent the register
6303 ;; allocator from allocating registers that overlap with the inputs
6304 ;; (for example, having an input in 7,8 and an output in 6,7). We
6305 ;; also allow for the output being the same as one of the inputs.
6307 (define_insn "*adddi3_noppc64"
6308 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6309 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6310 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6311 "! TARGET_POWERPC64"
6314 if (WORDS_BIG_ENDIAN)
6315 return (GET_CODE (operands[2])) != CONST_INT
6316 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6317 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6319 return (GET_CODE (operands[2])) != CONST_INT
6320 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6321 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6323 [(set_attr "type" "two")
6324 (set_attr "length" "8")])
6326 (define_insn "*subdi3_noppc64"
6327 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6328 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6329 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6330 "! TARGET_POWERPC64"
6333 if (WORDS_BIG_ENDIAN)
6334 return (GET_CODE (operands[1]) != CONST_INT)
6335 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6336 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6338 return (GET_CODE (operands[1]) != CONST_INT)
6339 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6340 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6342 [(set_attr "type" "two")
6343 (set_attr "length" "8")])
6345 (define_insn "*negdi2_noppc64"
6346 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6347 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6348 "! TARGET_POWERPC64"
6351 return (WORDS_BIG_ENDIAN)
6352 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6353 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6355 [(set_attr "type" "two")
6356 (set_attr "length" "8")])
6359 ;; Shift by a variable amount is too complex to be worth open-coding. We
6360 ;; just handle shifts by constants.
6361 (define_insn "ashrdi3_no_power"
6362 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6363 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6364 (match_operand:SI 2 "const_int_operand" "M,i")))
6365 (clobber (reg:SI CA_REGNO))]
6368 switch (which_alternative)
6373 if (WORDS_BIG_ENDIAN)
6374 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6376 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6378 if (WORDS_BIG_ENDIAN)
6379 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6381 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6384 [(set_attr "type" "two,three")
6385 (set_attr "length" "8,12")])
6387 (define_insn "*ashrdisi3_noppc64be"
6388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6389 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6390 (const_int 32)) 4))]
6391 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6394 if (REGNO (operands[0]) == REGNO (operands[1]))
6397 return \"mr %0,%1\";
6399 [(set_attr "length" "4")])
6402 ;; PowerPC64 DImode operations.
6404 (define_insn "*rotldi3_internal4"
6405 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6406 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6407 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6408 (match_operand:DI 3 "mask64_operand" "n")))]
6410 "rld%I2c%B3 %0,%1,%H2,%S3"
6411 [(set_attr "type" "shift")
6412 (set_attr "maybe_var_shift" "yes")])
6414 (define_insn "*rotldi3_internal5"
6415 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6417 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6418 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6419 (match_operand:DI 3 "mask64_operand" "n,n"))
6421 (clobber (match_scratch:DI 4 "=r,r"))]
6424 rld%I2c%B3. %4,%1,%H2,%S3
6426 [(set_attr "type" "shift")
6427 (set_attr "maybe_var_shift" "yes")
6428 (set_attr "dot" "yes")
6429 (set_attr "length" "4,8")])
6432 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6434 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6435 (match_operand:DI 2 "reg_or_cint_operand" ""))
6436 (match_operand:DI 3 "mask64_operand" ""))
6438 (clobber (match_scratch:DI 4 ""))]
6439 "TARGET_POWERPC64 && reload_completed"
6441 (and:DI (rotate:DI (match_dup 1)
6445 (compare:CC (match_dup 4)
6449 (define_insn "*rotldi3_internal6"
6450 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6452 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6453 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6454 (match_operand:DI 3 "mask64_operand" "n,n"))
6456 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6457 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6460 rld%I2c%B3. %0,%1,%H2,%S3
6462 [(set_attr "type" "shift")
6463 (set_attr "maybe_var_shift" "yes")
6464 (set_attr "dot" "yes")
6465 (set_attr "length" "4,8")])
6468 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6470 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6471 (match_operand:DI 2 "reg_or_cint_operand" ""))
6472 (match_operand:DI 3 "mask64_operand" ""))
6474 (set (match_operand:DI 0 "gpc_reg_operand" "")
6475 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6476 "TARGET_POWERPC64 && reload_completed"
6478 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6480 (compare:CC (match_dup 0)
6484 (define_insn "*rotldi3_internal7le"
6485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6488 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6489 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6490 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6491 "rld%I2cl %0,%1,%H2,56"
6492 [(set_attr "type" "shift")
6493 (set_attr "maybe_var_shift" "yes")])
6495 (define_insn "*rotldi3_internal7be"
6496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6499 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6500 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6501 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6502 "rld%I2cl %0,%1,%H2,56"
6503 [(set_attr "type" "shift")
6504 (set_attr "maybe_var_shift" "yes")])
6506 (define_insn "*rotldi3_internal8le"
6507 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6508 (compare:CC (zero_extend:DI
6510 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6511 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6513 (clobber (match_scratch:DI 3 "=r,r"))]
6514 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6516 rld%I2cl. %3,%1,%H2,56
6518 [(set_attr "type" "shift")
6519 (set_attr "maybe_var_shift" "yes")
6520 (set_attr "dot" "yes")
6521 (set_attr "length" "4,8")])
6523 (define_insn "*rotldi3_internal8be"
6524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6525 (compare:CC (zero_extend:DI
6527 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6528 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6530 (clobber (match_scratch:DI 3 "=r,r"))]
6531 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6533 rld%I2cl. %3,%1,%H2,56
6535 [(set_attr "type" "shift")
6536 (set_attr "maybe_var_shift" "yes")
6537 (set_attr "dot" "yes")
6538 (set_attr "length" "4,8")])
6541 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6542 (compare:CC (zero_extend:DI
6544 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6545 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6547 (clobber (match_scratch:DI 3 ""))]
6548 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6550 (zero_extend:DI (subreg:QI
6551 (rotate:DI (match_dup 1)
6554 (compare:CC (match_dup 3)
6559 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6560 (compare:CC (zero_extend:DI
6562 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6563 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6565 (clobber (match_scratch:DI 3 ""))]
6566 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6568 (zero_extend:DI (subreg:QI
6569 (rotate:DI (match_dup 1)
6572 (compare:CC (match_dup 3)
6576 (define_insn "*rotldi3_internal9le"
6577 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6578 (compare:CC (zero_extend:DI
6580 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6581 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6583 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6584 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6585 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6587 rld%I2cl. %0,%1,%H2,56
6589 [(set_attr "type" "shift")
6590 (set_attr "maybe_var_shift" "yes")
6591 (set_attr "dot" "yes")
6592 (set_attr "length" "4,8")])
6594 (define_insn "*rotldi3_internal9be"
6595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6596 (compare:CC (zero_extend:DI
6598 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6599 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6601 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6602 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6603 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6605 rld%I2cl. %0,%1,%H2,56
6607 [(set_attr "type" "shift")
6608 (set_attr "maybe_var_shift" "yes")
6609 (set_attr "dot" "yes")
6610 (set_attr "length" "4,8")])
6613 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6614 (compare:CC (zero_extend:DI
6616 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6617 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6619 (set (match_operand:DI 0 "gpc_reg_operand" "")
6620 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6621 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6623 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6625 (compare:CC (match_dup 0)
6630 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6631 (compare:CC (zero_extend:DI
6633 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6634 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6636 (set (match_operand:DI 0 "gpc_reg_operand" "")
6637 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6638 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6640 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6642 (compare:CC (match_dup 0)
6646 (define_insn "*rotldi3_internal10le"
6647 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6650 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6651 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6652 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6653 "rld%I2cl %0,%1,%H2,48"
6654 [(set_attr "type" "shift")
6655 (set_attr "maybe_var_shift" "yes")])
6657 (define_insn "*rotldi3_internal10be"
6658 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6661 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6662 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6663 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6664 "rld%I2cl %0,%1,%H2,48"
6665 [(set_attr "type" "shift")
6666 (set_attr "maybe_var_shift" "yes")])
6668 (define_insn "*rotldi3_internal11le"
6669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6670 (compare:CC (zero_extend:DI
6672 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6673 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6675 (clobber (match_scratch:DI 3 "=r,r"))]
6676 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6678 rld%I2cl. %3,%1,%H2,48
6680 [(set_attr "type" "shift")
6681 (set_attr "maybe_var_shift" "yes")
6682 (set_attr "dot" "yes")
6683 (set_attr "length" "4,8")])
6685 (define_insn "*rotldi3_internal11be"
6686 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6687 (compare:CC (zero_extend:DI
6689 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6690 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6692 (clobber (match_scratch:DI 3 "=r,r"))]
6693 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6695 rld%I2cl. %3,%1,%H2,48
6697 [(set_attr "type" "shift")
6698 (set_attr "maybe_var_shift" "yes")
6699 (set_attr "dot" "yes")
6700 (set_attr "length" "4,8")])
6703 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6704 (compare:CC (zero_extend:DI
6706 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6707 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6709 (clobber (match_scratch:DI 3 ""))]
6710 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6712 (zero_extend:DI (subreg:HI
6713 (rotate:DI (match_dup 1)
6716 (compare:CC (match_dup 3)
6721 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6722 (compare:CC (zero_extend:DI
6724 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6725 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6727 (clobber (match_scratch:DI 3 ""))]
6728 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6730 (zero_extend:DI (subreg:HI
6731 (rotate:DI (match_dup 1)
6734 (compare:CC (match_dup 3)
6738 (define_insn "*rotldi3_internal12le"
6739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6740 (compare:CC (zero_extend:DI
6742 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6743 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6745 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6746 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6747 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6749 rld%I2cl. %0,%1,%H2,48
6751 [(set_attr "type" "shift")
6752 (set_attr "maybe_var_shift" "yes")
6753 (set_attr "dot" "yes")
6754 (set_attr "length" "4,8")])
6756 (define_insn "*rotldi3_internal12be"
6757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6758 (compare:CC (zero_extend:DI
6760 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6761 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6763 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6764 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6765 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6767 rld%I2cl. %0,%1,%H2,48
6769 [(set_attr "type" "shift")
6770 (set_attr "maybe_var_shift" "yes")
6771 (set_attr "dot" "yes")
6772 (set_attr "length" "4,8")])
6775 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6776 (compare:CC (zero_extend:DI
6778 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6779 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6781 (set (match_operand:DI 0 "gpc_reg_operand" "")
6782 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6783 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6785 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6787 (compare:CC (match_dup 0)
6792 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6793 (compare:CC (zero_extend:DI
6795 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6796 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6798 (set (match_operand:DI 0 "gpc_reg_operand" "")
6799 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6800 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6802 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
6804 (compare:CC (match_dup 0)
6808 (define_insn "*rotldi3_internal13le"
6809 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6812 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6813 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6814 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6815 "rld%I2cl %0,%1,%H2,32"
6816 [(set_attr "type" "shift")
6817 (set_attr "maybe_var_shift" "yes")])
6819 (define_insn "*rotldi3_internal13be"
6820 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6823 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6824 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
6825 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6826 "rld%I2cl %0,%1,%H2,32"
6827 [(set_attr "type" "shift")
6828 (set_attr "maybe_var_shift" "yes")])
6830 (define_insn "*rotldi3_internal14le"
6831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6832 (compare:CC (zero_extend:DI
6834 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6835 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6837 (clobber (match_scratch:DI 3 "=r,r"))]
6838 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6840 rld%I2cl. %3,%1,%H2,32
6842 [(set_attr "type" "shift")
6843 (set_attr "maybe_var_shift" "yes")
6844 (set_attr "dot" "yes")
6845 (set_attr "length" "4,8")])
6847 (define_insn "*rotldi3_internal14be"
6848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6849 (compare:CC (zero_extend:DI
6851 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6852 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6854 (clobber (match_scratch:DI 3 "=r,r"))]
6855 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6857 rld%I2cl. %3,%1,%H2,32
6859 [(set_attr "type" "shift")
6860 (set_attr "maybe_var_shift" "yes")
6861 (set_attr "dot" "yes")
6862 (set_attr "length" "4,8")])
6865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6866 (compare:CC (zero_extend:DI
6868 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6869 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6871 (clobber (match_scratch:DI 3 ""))]
6872 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6874 (zero_extend:DI (subreg:SI
6875 (rotate:DI (match_dup 1)
6878 (compare:CC (match_dup 3)
6883 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6884 (compare:CC (zero_extend:DI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6887 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6889 (clobber (match_scratch:DI 3 ""))]
6890 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6892 (zero_extend:DI (subreg:SI
6893 (rotate:DI (match_dup 1)
6896 (compare:CC (match_dup 3)
6900 (define_insn "*rotldi3_internal15le"
6901 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6902 (compare:CC (zero_extend:DI
6904 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6905 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6907 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6908 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6909 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6911 rld%I2cl. %0,%1,%H2,32
6913 [(set_attr "type" "shift")
6914 (set_attr "maybe_var_shift" "yes")
6915 (set_attr "dot" "yes")
6916 (set_attr "length" "4,8")])
6918 (define_insn "*rotldi3_internal15be"
6919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6920 (compare:CC (zero_extend:DI
6922 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6923 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6926 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6927 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6929 rld%I2cl. %0,%1,%H2,32
6931 [(set_attr "type" "shift")
6932 (set_attr "maybe_var_shift" "yes")
6933 (set_attr "dot" "yes")
6934 (set_attr "length" "4,8")])
6937 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6938 (compare:CC (zero_extend:DI
6940 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6941 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6943 (set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6945 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6947 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6949 (compare:CC (match_dup 0)
6954 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6955 (compare:CC (zero_extend:DI
6957 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6958 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6960 (set (match_operand:DI 0 "gpc_reg_operand" "")
6961 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6962 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6964 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
6966 (compare:CC (match_dup 0)
6970 (define_insn "*ashldi3_internal4"
6971 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6972 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6973 (match_operand:SI 2 "const_int_operand" "i"))
6974 (match_operand:DI 3 "const_int_operand" "n")))]
6975 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6976 "rldic %0,%1,%H2,%W3"
6977 [(set_attr "type" "shift")])
6979 (define_insn "ashldi3_internal5"
6980 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6982 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6983 (match_operand:SI 2 "const_int_operand" "i,i"))
6984 (match_operand:DI 3 "const_int_operand" "n,n"))
6986 (clobber (match_scratch:DI 4 "=r,r"))]
6987 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6989 rldic. %4,%1,%H2,%W3
6991 [(set_attr "type" "shift")
6992 (set_attr "dot" "yes")
6993 (set_attr "length" "4,8")])
6996 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6998 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6999 (match_operand:SI 2 "const_int_operand" ""))
7000 (match_operand:DI 3 "const_int_operand" ""))
7002 (clobber (match_scratch:DI 4 ""))]
7003 "TARGET_POWERPC64 && reload_completed
7004 && includes_rldic_lshift_p (operands[2], operands[3])"
7006 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7009 (compare:CC (match_dup 4)
7013 (define_insn "*ashldi3_internal6"
7014 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7016 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7017 (match_operand:SI 2 "const_int_operand" "i,i"))
7018 (match_operand:DI 3 "const_int_operand" "n,n"))
7020 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7021 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7022 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7024 rldic. %0,%1,%H2,%W3
7026 [(set_attr "type" "shift")
7027 (set_attr "dot" "yes")
7028 (set_attr "length" "4,8")])
7031 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7033 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7034 (match_operand:SI 2 "const_int_operand" ""))
7035 (match_operand:DI 3 "const_int_operand" ""))
7037 (set (match_operand:DI 0 "gpc_reg_operand" "")
7038 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7039 "TARGET_POWERPC64 && reload_completed
7040 && includes_rldic_lshift_p (operands[2], operands[3])"
7042 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7045 (compare:CC (match_dup 0)
7049 (define_insn "*ashldi3_internal7"
7050 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7051 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7052 (match_operand:SI 2 "const_int_operand" "i"))
7053 (match_operand:DI 3 "mask64_operand" "n")))]
7054 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7055 "rldicr %0,%1,%H2,%S3"
7056 [(set_attr "type" "shift")])
7058 (define_insn "ashldi3_internal8"
7059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7061 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7062 (match_operand:SI 2 "const_int_operand" "i,i"))
7063 (match_operand:DI 3 "mask64_operand" "n,n"))
7065 (clobber (match_scratch:DI 4 "=r,r"))]
7066 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7068 rldicr. %4,%1,%H2,%S3
7070 [(set_attr "type" "shift")
7071 (set_attr "dot" "yes")
7072 (set_attr "length" "4,8")])
7075 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7077 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:SI 2 "const_int_operand" ""))
7079 (match_operand:DI 3 "mask64_operand" ""))
7081 (clobber (match_scratch:DI 4 ""))]
7082 "TARGET_POWERPC64 && reload_completed
7083 && includes_rldicr_lshift_p (operands[2], operands[3])"
7085 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7088 (compare:CC (match_dup 4)
7092 (define_insn "*ashldi3_internal9"
7093 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7095 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7096 (match_operand:SI 2 "const_int_operand" "i,i"))
7097 (match_operand:DI 3 "mask64_operand" "n,n"))
7099 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7100 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7101 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7103 rldicr. %0,%1,%H2,%S3
7105 [(set_attr "type" "shift")
7106 (set_attr "dot" "yes")
7107 (set_attr "length" "4,8")])
7110 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7112 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7113 (match_operand:SI 2 "const_int_operand" ""))
7114 (match_operand:DI 3 "mask64_operand" ""))
7116 (set (match_operand:DI 0 "gpc_reg_operand" "")
7117 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7118 "TARGET_POWERPC64 && reload_completed
7119 && includes_rldicr_lshift_p (operands[2], operands[3])"
7121 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7124 (compare:CC (match_dup 0)
7129 (define_insn_and_split "*anddi3_2rld"
7130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7131 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7132 (match_operand:DI 2 "and_2rld_operand" "n")))]
7137 (and:DI (rotate:DI (match_dup 1)
7141 (and:DI (rotate:DI (match_dup 0)
7145 build_mask64_2_operands (operands[2], &operands[4]);
7147 [(set_attr "length" "8")])
7149 (define_insn_and_split "*anddi3_2rld_dot"
7150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7151 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7152 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7154 (clobber (match_scratch:DI 0 "=r,r"))]
7155 "TARGET_64BIT && rs6000_gen_cell_microcode"
7159 "&& reload_completed"
7161 (and:DI (rotate:DI (match_dup 1)
7164 (parallel [(set (match_dup 3)
7165 (compare:CC (and:DI (rotate:DI (match_dup 0)
7169 (clobber (match_dup 0))])]
7171 build_mask64_2_operands (operands[2], &operands[4]);
7173 [(set_attr "type" "compare")
7174 (set_attr "dot" "yes")
7175 (set_attr "length" "8,12")])
7177 (define_insn_and_split "*anddi3_2rld_dot2"
7178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7179 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7180 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7182 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7183 (and:DI (match_dup 1)
7185 "TARGET_64BIT && rs6000_gen_cell_microcode"
7189 "&& reload_completed"
7191 (and:DI (rotate:DI (match_dup 1)
7194 (parallel [(set (match_dup 3)
7195 (compare:CC (and:DI (rotate:DI (match_dup 0)
7200 (and:DI (rotate:DI (match_dup 0)
7204 build_mask64_2_operands (operands[2], &operands[4]);
7206 [(set_attr "type" "compare")
7207 (set_attr "dot" "yes")
7208 (set_attr "length" "8,12")])
7210 ;; 128-bit logical operations expanders
7212 (define_expand "and<mode>3"
7213 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7214 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7215 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7219 (define_expand "ior<mode>3"
7220 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7221 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7222 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7226 (define_expand "xor<mode>3"
7227 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7228 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7229 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7233 (define_expand "one_cmpl<mode>2"
7234 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7235 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7239 (define_expand "nor<mode>3"
7240 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7242 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7243 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7247 (define_expand "andc<mode>3"
7248 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7250 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7251 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7255 ;; Power8 vector logical instructions.
7256 (define_expand "eqv<mode>3"
7257 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7259 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7260 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7261 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7264 ;; Rewrite nand into canonical form
7265 (define_expand "nand<mode>3"
7266 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7268 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7269 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7270 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7273 ;; The canonical form is to have the negated element first, so we need to
7274 ;; reverse arguments.
7275 (define_expand "orc<mode>3"
7276 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7278 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7279 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7280 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7283 ;; 128-bit logical operations insns and split operations
7284 (define_insn_and_split "*and<mode>3_internal"
7285 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7287 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7288 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7291 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7292 return "xxland %x0,%x1,%x2";
7294 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7295 return "vand %0,%1,%2";
7299 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7302 rs6000_split_logical (operands, AND, false, false, false);
7307 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7308 (const_string "vecsimple")
7309 (const_string "integer")))
7310 (set (attr "length")
7312 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7315 (match_test "TARGET_POWERPC64")
7317 (const_string "16"))))])
7320 (define_insn_and_split "*bool<mode>3_internal"
7321 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7322 (match_operator:BOOL_128 3 "boolean_or_operator"
7323 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7324 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7327 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7328 return "xxl%q3 %x0,%x1,%x2";
7330 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7331 return "v%q3 %0,%1,%2";
7335 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7338 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7343 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7344 (const_string "vecsimple")
7345 (const_string "integer")))
7346 (set (attr "length")
7348 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7351 (match_test "TARGET_POWERPC64")
7353 (const_string "16"))))])
7356 (define_insn_and_split "*boolc<mode>3_internal1"
7357 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7358 (match_operator:BOOL_128 3 "boolean_operator"
7360 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
7361 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7362 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7364 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7365 return "xxl%q3 %x0,%x1,%x2";
7367 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7368 return "v%q3 %0,%1,%2";
7372 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7373 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7376 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7381 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7382 (const_string "vecsimple")
7383 (const_string "integer")))
7384 (set (attr "length")
7386 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7389 (match_test "TARGET_POWERPC64")
7391 (const_string "16"))))])
7393 (define_insn_and_split "*boolc<mode>3_internal2"
7394 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7395 (match_operator:TI2 3 "boolean_operator"
7397 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7398 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
7399 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7401 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7404 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7407 [(set_attr "type" "integer")
7408 (set (attr "length")
7410 (match_test "TARGET_POWERPC64")
7412 (const_string "16")))])
7415 (define_insn_and_split "*boolcc<mode>3_internal1"
7416 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7417 (match_operator:BOOL_128 3 "boolean_operator"
7419 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7421 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7422 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7424 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7425 return "xxl%q3 %x0,%x1,%x2";
7427 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7428 return "v%q3 %0,%1,%2";
7432 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7433 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7436 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7441 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7442 (const_string "vecsimple")
7443 (const_string "integer")))
7444 (set (attr "length")
7446 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7449 (match_test "TARGET_POWERPC64")
7451 (const_string "16"))))])
7453 (define_insn_and_split "*boolcc<mode>3_internal2"
7454 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7455 (match_operator:TI2 3 "boolean_operator"
7457 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7459 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7460 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7462 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7465 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7468 [(set_attr "type" "integer")
7469 (set (attr "length")
7471 (match_test "TARGET_POWERPC64")
7473 (const_string "16")))])
7477 (define_insn_and_split "*eqv<mode>3_internal1"
7478 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7481 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7482 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7485 if (vsx_register_operand (operands[0], <MODE>mode))
7486 return "xxleqv %x0,%x1,%x2";
7490 "TARGET_P8_VECTOR && reload_completed
7491 && int_reg_operand (operands[0], <MODE>mode)"
7494 rs6000_split_logical (operands, XOR, true, false, false);
7499 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7500 (const_string "vecsimple")
7501 (const_string "integer")))
7502 (set (attr "length")
7504 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7507 (match_test "TARGET_POWERPC64")
7509 (const_string "16"))))])
7511 (define_insn_and_split "*eqv<mode>3_internal2"
7512 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7515 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7516 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7519 "reload_completed && !TARGET_P8_VECTOR"
7522 rs6000_split_logical (operands, XOR, true, false, false);
7525 [(set_attr "type" "integer")
7526 (set (attr "length")
7528 (match_test "TARGET_POWERPC64")
7530 (const_string "16")))])
7532 ;; 128-bit one's complement
7533 (define_insn_and_split "*one_cmpl<mode>3_internal"
7534 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7536 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7539 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7540 return "xxlnor %x0,%x1,%x1";
7542 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7543 return "vnor %0,%1,%1";
7547 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7550 rs6000_split_logical (operands, NOT, false, false, false);
7555 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7556 (const_string "vecsimple")
7557 (const_string "integer")))
7558 (set (attr "length")
7560 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7563 (match_test "TARGET_POWERPC64")
7565 (const_string "16"))))])
7568 ;; Now define ways of moving data around.
7570 ;; Set up a register with a value from the GOT table
7572 (define_expand "movsi_got"
7573 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7574 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7575 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7576 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7579 if (GET_CODE (operands[1]) == CONST)
7581 rtx offset = const0_rtx;
7582 HOST_WIDE_INT value;
7584 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7585 value = INTVAL (offset);
7588 rtx tmp = (!can_create_pseudo_p ()
7590 : gen_reg_rtx (Pmode));
7591 emit_insn (gen_movsi_got (tmp, operands[1]));
7592 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7597 operands[2] = rs6000_got_register (operands[1]);
7600 (define_insn "*movsi_got_internal"
7601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7602 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7603 (match_operand:SI 2 "gpc_reg_operand" "b")]
7605 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7606 "lwz %0,%a1@got(%2)"
7607 [(set_attr "type" "load")])
7609 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7610 ;; didn't get allocated to a hard register.
7612 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7613 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7614 (match_operand:SI 2 "memory_operand" "")]
7616 "DEFAULT_ABI == ABI_V4
7618 && (reload_in_progress || reload_completed)"
7619 [(set (match_dup 0) (match_dup 2))
7620 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7624 ;; For SI, we special-case integers that can't be loaded in one insn. We
7625 ;; do the load 16-bits at a time. We could do this by loading from memory,
7626 ;; and this is even supposed to be faster, but it is simpler not to get
7627 ;; integers in the TOC.
7628 (define_insn "movsi_low"
7629 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7630 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7631 (match_operand 2 "" ""))))]
7632 "TARGET_MACHO && ! TARGET_64BIT"
7633 "lwz %0,lo16(%2)(%1)"
7634 [(set_attr "type" "load")
7635 (set_attr "length" "4")])
7637 (define_insn "*movsi_internal1"
7638 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7639 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7640 "!TARGET_SINGLE_FPU &&
7641 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7654 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7655 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7657 (define_insn "*movsi_internal1_single"
7658 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7659 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7660 "TARGET_SINGLE_FPU &&
7661 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7676 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7677 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7679 ;; Split a load of a large constant into the appropriate two-insn
7683 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7684 (match_operand:SI 1 "const_int_operand" ""))]
7685 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7686 && (INTVAL (operands[1]) & 0xffff) != 0"
7690 (ior:SI (match_dup 0)
7694 if (rs6000_emit_set_const (operands[0], operands[1]))
7700 (define_insn "*mov<mode>_internal2"
7701 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7702 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7704 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7710 [(set_attr "type" "cmp,logical,cmp")
7711 (set_attr "dot" "yes")
7712 (set_attr "length" "4,4,8")])
7715 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7716 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7718 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7720 [(set (match_dup 0) (match_dup 1))
7722 (compare:CC (match_dup 0)
7726 (define_insn "*movhi_internal"
7727 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7728 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7729 "gpc_reg_operand (operands[0], HImode)
7730 || gpc_reg_operand (operands[1], HImode)"
7739 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7741 (define_expand "mov<mode>"
7742 [(set (match_operand:INT 0 "general_operand" "")
7743 (match_operand:INT 1 "any_operand" ""))]
7745 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7747 (define_insn "*movqi_internal"
7748 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7749 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7750 "gpc_reg_operand (operands[0], QImode)
7751 || gpc_reg_operand (operands[1], QImode)"
7760 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7762 ;; Here is how to move condition codes around. When we store CC data in
7763 ;; an integer register or memory, we store just the high-order 4 bits.
7764 ;; This lets us not shift in the most common case of CR0.
7765 (define_expand "movcc"
7766 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7767 (match_operand:CC 1 "nonimmediate_operand" ""))]
7771 (define_insn "*movcc_internal1"
7772 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7773 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7774 "register_operand (operands[0], CCmode)
7775 || register_operand (operands[1], CCmode)"
7779 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7782 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7790 (cond [(eq_attr "alternative" "0,3")
7791 (const_string "cr_logical")
7792 (eq_attr "alternative" "1,2")
7793 (const_string "mtcr")
7794 (eq_attr "alternative" "6,7")
7795 (const_string "integer")
7796 (eq_attr "alternative" "8")
7797 (const_string "mfjmpr")
7798 (eq_attr "alternative" "9")
7799 (const_string "mtjmpr")
7800 (eq_attr "alternative" "10")
7801 (const_string "load")
7802 (eq_attr "alternative" "11")
7803 (const_string "store")
7804 (match_test "TARGET_MFCRF")
7805 (const_string "mfcrf")
7807 (const_string "mfcr")))
7808 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7810 ;; For floating-point, we normally deal with the floating-point registers
7811 ;; unless -msoft-float is used. The sole exception is that parameter passing
7812 ;; can produce floating-point values in fixed-point registers. Unless the
7813 ;; value is a simple constant or already in memory, we deal with this by
7814 ;; allocating memory and copying the value explicitly via that memory location.
7816 ;; Move 32-bit binary/decimal floating point
7817 (define_expand "mov<mode>"
7818 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
7819 (match_operand:FMOVE32 1 "any_operand" ""))]
7821 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7824 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
7825 (match_operand:FMOVE32 1 "const_double_operand" ""))]
7827 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7828 || (GET_CODE (operands[0]) == SUBREG
7829 && GET_CODE (SUBREG_REG (operands[0])) == REG
7830 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7831 [(set (match_dup 2) (match_dup 3))]
7837 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7838 <real_value_to_target> (rv, l);
7840 if (! TARGET_POWERPC64)
7841 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
7843 operands[2] = gen_lowpart (SImode, operands[0]);
7845 operands[3] = gen_int_mode (l, SImode);
7848 (define_insn "mov<mode>_hardfloat"
7849 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
7850 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0,G,Fn"))]
7851 "(gpc_reg_operand (operands[0], <MODE>mode)
7852 || gpc_reg_operand (operands[1], <MODE>mode))
7853 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7872 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
7873 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
7875 (define_insn "*mov<mode>_softfloat"
7876 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7877 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7878 "(gpc_reg_operand (operands[0], <MODE>mode)
7879 || gpc_reg_operand (operands[1], <MODE>mode))
7880 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7892 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7893 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7896 ;; Move 64-bit binary/decimal floating point
7897 (define_expand "mov<mode>"
7898 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
7899 (match_operand:FMOVE64 1 "any_operand" ""))]
7901 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7904 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7905 (match_operand:FMOVE64 1 "const_int_operand" ""))]
7906 "! TARGET_POWERPC64 && reload_completed
7907 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7908 || (GET_CODE (operands[0]) == SUBREG
7909 && GET_CODE (SUBREG_REG (operands[0])) == REG
7910 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7911 [(set (match_dup 2) (match_dup 4))
7912 (set (match_dup 3) (match_dup 1))]
7915 int endian = (WORDS_BIG_ENDIAN == 0);
7916 HOST_WIDE_INT value = INTVAL (operands[1]);
7918 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7919 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7920 operands[4] = GEN_INT (value >> 32);
7921 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7925 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7926 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7927 "! TARGET_POWERPC64 && reload_completed
7928 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7929 || (GET_CODE (operands[0]) == SUBREG
7930 && GET_CODE (SUBREG_REG (operands[0])) == REG
7931 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7932 [(set (match_dup 2) (match_dup 4))
7933 (set (match_dup 3) (match_dup 5))]
7936 int endian = (WORDS_BIG_ENDIAN == 0);
7940 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7941 <real_value_to_target> (rv, l);
7943 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7944 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7945 operands[4] = gen_int_mode (l[endian], SImode);
7946 operands[5] = gen_int_mode (l[1 - endian], SImode);
7950 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7951 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7952 "TARGET_POWERPC64 && reload_completed
7953 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7954 || (GET_CODE (operands[0]) == SUBREG
7955 && GET_CODE (SUBREG_REG (operands[0])) == REG
7956 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7957 [(set (match_dup 2) (match_dup 3))]
7960 int endian = (WORDS_BIG_ENDIAN == 0);
7965 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7966 <real_value_to_target> (rv, l);
7968 operands[2] = gen_lowpart (DImode, operands[0]);
7969 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7970 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7971 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7973 operands[3] = gen_int_mode (val, DImode);
7976 ;; Don't have reload use general registers to load a constant. It is
7977 ;; less efficient than loading the constant into an FP register, since
7978 ;; it will probably be used there.
7980 ;; The move constraints are ordered to prefer floating point registers before
7981 ;; general purpose registers to avoid doing a store and a load to get the value
7982 ;; into a floating point register when it is needed for a floating point
7983 ;; operation. Prefer traditional floating point registers over VSX registers,
7984 ;; since the D-form version of the memory instructions does not need a GPR for
7987 (define_insn "*mov<mode>_hardfloat32"
7988 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r")
7989 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))]
7990 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7991 && (gpc_reg_operand (operands[0], <MODE>mode)
7992 || gpc_reg_operand (operands[1], <MODE>mode))"
8007 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8008 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8010 (define_insn "*mov<mode>_softfloat32"
8011 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8012 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8014 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8015 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8016 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8017 && (gpc_reg_operand (operands[0], <MODE>mode)
8018 || gpc_reg_operand (operands[1], <MODE>mode))"
8020 [(set_attr "type" "store,load,two,*,*,*")
8021 (set_attr "length" "8,8,8,8,12,16")])
8023 ; ld/std require word-aligned displacements -> 'Y' constraint.
8024 ; List Y->r and r->Y before r->r for reload.
8025 (define_insn "*mov<mode>_hardfloat64"
8026 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>")
8027 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))]
8028 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8029 && (gpc_reg_operand (operands[0], <MODE>mode)
8030 || gpc_reg_operand (operands[1], <MODE>mode))"
8052 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8053 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8055 (define_insn "*mov<mode>_softfloat64"
8056 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8057 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8058 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8059 && (gpc_reg_operand (operands[0], <MODE>mode)
8060 || gpc_reg_operand (operands[1], <MODE>mode))"
8071 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8072 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8074 (define_expand "mov<mode>"
8075 [(set (match_operand:FMOVE128 0 "general_operand" "")
8076 (match_operand:FMOVE128 1 "any_operand" ""))]
8078 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8080 ;; It's important to list Y->r and r->Y before r->r because otherwise
8081 ;; reload, given m->r, will try to pick r->r and reload it, which
8082 ;; doesn't make progress.
8084 ;; We can't split little endian direct moves of TDmode, because the words are
8085 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8086 ;; problematical. Don't allow direct move for this case.
8088 (define_insn_and_split "*mov<mode>_64bit_dm"
8089 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
8090 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
8091 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8092 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8093 && (gpc_reg_operand (operands[0], <MODE>mode)
8094 || gpc_reg_operand (operands[1], <MODE>mode))"
8096 "&& reload_completed"
8098 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8099 [(set_attr "length" "8,8,8,12,12,8,8,8")])
8101 (define_insn_and_split "*movtd_64bit_nodm"
8102 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8103 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
8104 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8105 && (gpc_reg_operand (operands[0], TDmode)
8106 || gpc_reg_operand (operands[1], TDmode))"
8108 "&& reload_completed"
8110 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8111 [(set_attr "length" "8,8,8,12,12,8")])
8113 (define_insn_and_split "*mov<mode>_32bit"
8114 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8115 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
8116 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8117 && (gpc_reg_operand (operands[0], <MODE>mode)
8118 || gpc_reg_operand (operands[1], <MODE>mode))"
8120 "&& reload_completed"
8122 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8123 [(set_attr "length" "8,8,8,20,20,16")])
8125 (define_insn_and_split "*mov<mode>_softfloat"
8126 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8127 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8128 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8129 && (gpc_reg_operand (operands[0], <MODE>mode)
8130 || gpc_reg_operand (operands[1], <MODE>mode))"
8132 "&& reload_completed"
8134 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8135 [(set_attr "length" "20,20,16")])
8137 ;; If we are using -ffast-math, easy_fp_constant assumes all constants are
8138 ;; 'easy' in order to allow for reciprocal estimation. Make sure the constant
8139 ;; is in the constant pool before reload occurs. This simplifies accessing
8140 ;; scalars in the traditional Altivec registers.
8143 [(set (match_operand:SFDF 0 "register_operand" "")
8144 (match_operand:SFDF 1 "memory_fp_constant" ""))]
8145 "TARGET_<MODE>_FPR && flag_unsafe_math_optimizations
8146 && !reload_in_progress && !reload_completed && !lra_in_progress"
8147 [(set (match_dup 0) (match_dup 2))]
8149 operands[2] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
8152 (define_expand "extenddftf2"
8153 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8154 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8156 && TARGET_HARD_FLOAT
8157 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8158 && TARGET_LONG_DOUBLE_128"
8160 if (TARGET_E500_DOUBLE)
8161 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8163 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8167 (define_expand "extenddftf2_fprs"
8168 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8169 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8170 (use (match_dup 2))])]
8172 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8173 && TARGET_LONG_DOUBLE_128"
8175 operands[2] = CONST0_RTX (DFmode);
8176 /* Generate GOT reference early for SVR4 PIC. */
8177 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8178 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8181 (define_insn_and_split "*extenddftf2_internal"
8182 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8183 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8184 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8186 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8187 && TARGET_LONG_DOUBLE_128"
8189 "&& reload_completed"
8192 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8193 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8194 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8196 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8201 (define_expand "extendsftf2"
8202 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8203 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8205 && TARGET_HARD_FLOAT
8206 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8207 && TARGET_LONG_DOUBLE_128"
8209 rtx tmp = gen_reg_rtx (DFmode);
8210 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8211 emit_insn (gen_extenddftf2 (operands[0], tmp));
8215 (define_expand "trunctfdf2"
8216 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8217 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8219 && TARGET_HARD_FLOAT
8220 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8221 && TARGET_LONG_DOUBLE_128"
8224 (define_insn_and_split "trunctfdf2_internal1"
8225 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8226 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8227 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8228 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8232 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8235 emit_note (NOTE_INSN_DELETED);
8238 [(set_attr "type" "fp")])
8240 (define_insn "trunctfdf2_internal2"
8241 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8242 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8243 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8244 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8245 && TARGET_LONG_DOUBLE_128"
8247 [(set_attr "type" "fp")
8248 (set_attr "fp_type" "fp_addsub_d")])
8250 (define_expand "trunctfsf2"
8251 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8252 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8254 && TARGET_HARD_FLOAT
8255 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8256 && TARGET_LONG_DOUBLE_128"
8258 if (TARGET_E500_DOUBLE)
8259 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8261 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8265 (define_insn_and_split "trunctfsf2_fprs"
8266 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8267 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8268 (clobber (match_scratch:DF 2 "=d"))]
8270 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8271 && TARGET_LONG_DOUBLE_128"
8273 "&& reload_completed"
8275 (float_truncate:DF (match_dup 1)))
8277 (float_truncate:SF (match_dup 2)))]
8280 (define_expand "floatsitf2"
8281 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8282 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8284 && TARGET_HARD_FLOAT
8285 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8286 && TARGET_LONG_DOUBLE_128"
8288 rtx tmp = gen_reg_rtx (DFmode);
8289 expand_float (tmp, operands[1], false);
8290 emit_insn (gen_extenddftf2 (operands[0], tmp));
8294 ; fadd, but rounding towards zero.
8295 ; This is probably not the optimal code sequence.
8296 (define_insn "fix_trunc_helper"
8297 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8298 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8299 UNSPEC_FIX_TRUNC_TF))
8300 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8301 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8302 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8303 [(set_attr "type" "fp")
8304 (set_attr "length" "20")])
8306 (define_expand "fix_trunctfsi2"
8307 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8308 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8309 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8310 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8312 if (TARGET_E500_DOUBLE)
8313 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8315 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8319 (define_expand "fix_trunctfsi2_fprs"
8320 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8321 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8322 (clobber (match_dup 2))
8323 (clobber (match_dup 3))
8324 (clobber (match_dup 4))
8325 (clobber (match_dup 5))])]
8327 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8329 operands[2] = gen_reg_rtx (DFmode);
8330 operands[3] = gen_reg_rtx (DFmode);
8331 operands[4] = gen_reg_rtx (DImode);
8332 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8335 (define_insn_and_split "*fix_trunctfsi2_internal"
8336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8337 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8338 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8339 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8340 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8341 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8343 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8349 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8351 gcc_assert (MEM_P (operands[5]));
8352 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8354 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8355 emit_move_insn (operands[5], operands[4]);
8356 emit_move_insn (operands[0], lowword);
8360 (define_expand "negtf2"
8361 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8362 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8364 && TARGET_HARD_FLOAT
8365 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8366 && TARGET_LONG_DOUBLE_128"
8369 (define_insn "negtf2_internal"
8370 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8371 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8373 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8376 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8377 return \"fneg %L0,%L1\;fneg %0,%1\";
8379 return \"fneg %0,%1\;fneg %L0,%L1\";
8381 [(set_attr "type" "fp")
8382 (set_attr "length" "8")])
8384 (define_expand "abstf2"
8385 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8386 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8388 && TARGET_HARD_FLOAT
8389 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8390 && TARGET_LONG_DOUBLE_128"
8393 rtx label = gen_label_rtx ();
8394 if (TARGET_E500_DOUBLE)
8396 if (flag_finite_math_only && !flag_trapping_math)
8397 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8399 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8402 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8407 (define_expand "abstf2_internal"
8408 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8409 (match_operand:TF 1 "gpc_reg_operand" ""))
8410 (set (match_dup 3) (match_dup 5))
8411 (set (match_dup 5) (abs:DF (match_dup 5)))
8412 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8413 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8414 (label_ref (match_operand 2 "" ""))
8416 (set (match_dup 6) (neg:DF (match_dup 6)))]
8418 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8419 && TARGET_LONG_DOUBLE_128"
8422 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8423 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8424 operands[3] = gen_reg_rtx (DFmode);
8425 operands[4] = gen_reg_rtx (CCFPmode);
8426 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8427 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8430 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8431 ;; must have 3 arguments, and scratch register constraint must be a single
8434 ;; Reload patterns to support gpr load/store with misaligned mem.
8435 ;; and multiple gpr load/store at offset >= 0xfffc
8436 (define_expand "reload_<mode>_store"
8437 [(parallel [(match_operand 0 "memory_operand" "=m")
8438 (match_operand 1 "gpc_reg_operand" "r")
8439 (match_operand:GPR 2 "register_operand" "=&b")])]
8442 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8446 (define_expand "reload_<mode>_load"
8447 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8448 (match_operand 1 "memory_operand" "m")
8449 (match_operand:GPR 2 "register_operand" "=b")])]
8452 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8457 ;; Reload patterns for various types using the vector registers. We may need
8458 ;; an additional base register to convert the reg+offset addressing to reg+reg
8459 ;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
8460 ;; index register for gpr registers.
8461 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
8462 [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
8463 (match_operand:RELOAD 1 "gpc_reg_operand" "wa")
8464 (match_operand:P 2 "register_operand" "=b")])]
8467 rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
8471 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
8472 [(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
8473 (match_operand:RELOAD 1 "memory_operand" "m")
8474 (match_operand:P 2 "register_operand" "=b")])]
8477 rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
8482 ;; Reload sometimes tries to move the address to a GPR, and can generate
8483 ;; invalid RTL for addresses involving AND -16. Allow addresses involving
8484 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
8486 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
8487 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
8488 (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
8489 (match_operand:P 2 "reg_or_cint_operand" "rI"))
8491 "TARGET_ALTIVEC && (reload_in_progress || reload_completed)"
8493 "&& reload_completed"
8495 (plus:P (match_dup 1)
8498 (and:P (match_dup 0)
8501 ;; Power8 merge instructions to allow direct move to/from floating point
8502 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8503 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8504 ;; value, since it is allocated in reload and not all of the flow information
8505 ;; is setup for it. We have two patterns to do the two moves between gprs and
8506 ;; fprs. There isn't a dependancy between the two, but we could potentially
8507 ;; schedule other instructions between the two instructions. TFmode is
8508 ;; currently limited to traditional FPR registers. If/when this is changed, we
8509 ;; will need to revist %L to make sure it works with VSX registers, or add an
8510 ;; %x version of %L.
8512 (define_insn "p8_fmrgow_<mode>"
8513 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8514 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8515 UNSPEC_P8V_FMRGOW))]
8516 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8518 [(set_attr "type" "vecperm")])
8520 (define_insn "p8_mtvsrwz_1"
8521 [(set (match_operand:TF 0 "register_operand" "=d")
8522 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8523 UNSPEC_P8V_MTVSRWZ))]
8524 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8526 [(set_attr "type" "mftgpr")])
8528 (define_insn "p8_mtvsrwz_2"
8529 [(set (match_operand:TF 0 "register_operand" "+d")
8530 (unspec:TF [(match_dup 0)
8531 (match_operand:SI 1 "register_operand" "r")]
8532 UNSPEC_P8V_MTVSRWZ))]
8533 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8535 [(set_attr "type" "mftgpr")])
8537 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8538 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8539 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8540 UNSPEC_P8V_RELOAD_FROM_GPR))
8541 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8542 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8544 "&& reload_completed"
8547 rtx dest = operands[0];
8548 rtx src = operands[1];
8549 rtx tmp = operands[2];
8550 rtx gpr_hi_reg = gen_highpart (SImode, src);
8551 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8553 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8554 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8555 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8558 [(set_attr "length" "12")
8559 (set_attr "type" "three")])
8561 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8562 (define_insn "p8_mtvsrd_1"
8563 [(set (match_operand:TF 0 "register_operand" "=ws")
8564 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8565 UNSPEC_P8V_MTVSRD))]
8566 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8568 [(set_attr "type" "mftgpr")])
8570 (define_insn "p8_mtvsrd_2"
8571 [(set (match_operand:TF 0 "register_operand" "+ws")
8572 (unspec:TF [(match_dup 0)
8573 (match_operand:DI 1 "register_operand" "r")]
8574 UNSPEC_P8V_MTVSRD))]
8575 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8577 [(set_attr "type" "mftgpr")])
8579 (define_insn "p8_xxpermdi_<mode>"
8580 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8581 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8582 UNSPEC_P8V_XXPERMDI))]
8583 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8584 "xxpermdi %x0,%1,%L1,0"
8585 [(set_attr "type" "vecperm")])
8587 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8588 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8589 (unspec:FMOVE128_GPR
8590 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8591 UNSPEC_P8V_RELOAD_FROM_GPR))
8592 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8593 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8595 "&& reload_completed"
8598 rtx dest = operands[0];
8599 rtx src = operands[1];
8600 rtx tmp = operands[2];
8601 rtx gpr_hi_reg = gen_highpart (DImode, src);
8602 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8604 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8605 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8606 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8608 [(set_attr "length" "12")
8609 (set_attr "type" "three")])
8612 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8613 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8615 && (int_reg_operand (operands[0], <MODE>mode)
8616 || int_reg_operand (operands[1], <MODE>mode))"
8618 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8620 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8621 ;; type is stored internally as double precision in the VSX registers, we have
8622 ;; to convert it from the vector format.
8624 (define_insn_and_split "reload_vsx_from_gprsf"
8625 [(set (match_operand:SF 0 "register_operand" "=wa")
8626 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8627 UNSPEC_P8V_RELOAD_FROM_GPR))
8628 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8629 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8631 "&& reload_completed"
8634 rtx op0 = operands[0];
8635 rtx op1 = operands[1];
8636 rtx op2 = operands[2];
8637 /* Also use the destination register to hold the unconverted DImode value.
8638 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8639 rather than simplify_gen_subreg. */
8640 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8641 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8643 /* Move SF value to upper 32-bits for xscvspdpn. */
8644 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8645 emit_move_insn (op0_di, op2);
8646 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8649 [(set_attr "length" "8")
8650 (set_attr "type" "two")])
8652 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8653 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8654 ;; and then doing a move of that.
8655 (define_insn "p8_mfvsrd_3_<mode>"
8656 [(set (match_operand:DF 0 "register_operand" "=r")
8657 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8658 UNSPEC_P8V_RELOAD_FROM_VSX))]
8659 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8661 [(set_attr "type" "mftgpr")])
8663 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8664 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8665 (unspec:FMOVE128_GPR
8666 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8667 UNSPEC_P8V_RELOAD_FROM_VSX))
8668 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8669 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8671 "&& reload_completed"
8674 rtx dest = operands[0];
8675 rtx src = operands[1];
8676 rtx tmp = operands[2];
8677 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8678 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8680 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8681 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8682 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8684 [(set_attr "length" "12")
8685 (set_attr "type" "three")])
8687 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8688 ;; type is stored internally as double precision, we have to convert it to the
8691 (define_insn_and_split "reload_gpr_from_vsxsf"
8692 [(set (match_operand:SF 0 "register_operand" "=r")
8693 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8694 UNSPEC_P8V_RELOAD_FROM_VSX))
8695 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8696 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8698 "&& reload_completed"
8701 rtx op0 = operands[0];
8702 rtx op1 = operands[1];
8703 rtx op2 = operands[2];
8704 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8706 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8707 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8708 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8711 [(set_attr "length" "12")
8712 (set_attr "type" "three")])
8714 (define_insn "p8_mfvsrd_4_disf"
8715 [(set (match_operand:DI 0 "register_operand" "=r")
8716 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8717 UNSPEC_P8V_RELOAD_FROM_VSX))]
8718 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8720 [(set_attr "type" "mftgpr")])
8723 ;; Next come the multi-word integer load and store and the load and store
8726 ;; List r->r after r->Y, otherwise reload will try to reload a
8727 ;; non-offsettable address by using r->r which won't make progress.
8728 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8729 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8730 (define_insn "*movdi_internal32"
8731 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8732 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8734 && (gpc_reg_operand (operands[0], DImode)
8735 || gpc_reg_operand (operands[1], DImode))"
8744 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8747 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8748 (match_operand:DI 1 "const_int_operand" ""))]
8749 "! TARGET_POWERPC64 && reload_completed
8750 && gpr_or_gpr_p (operands[0], operands[1])
8751 && !direct_move_p (operands[0], operands[1])"
8752 [(set (match_dup 2) (match_dup 4))
8753 (set (match_dup 3) (match_dup 1))]
8756 HOST_WIDE_INT value = INTVAL (operands[1]);
8757 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8759 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8761 operands[4] = GEN_INT (value >> 32);
8762 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8766 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8767 (match_operand:DIFD 1 "input_operand" ""))]
8768 "reload_completed && !TARGET_POWERPC64
8769 && gpr_or_gpr_p (operands[0], operands[1])
8770 && !direct_move_p (operands[0], operands[1])"
8772 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8774 (define_insn "*movdi_internal64"
8775 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8776 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8778 && (gpc_reg_operand (operands[0], DImode)
8779 || gpc_reg_operand (operands[1], DImode))"
8798 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
8799 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
8801 ;; Generate all one-bits and clear left or right.
8802 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8804 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8805 (match_operand:DI 1 "mask64_operand" ""))]
8806 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8807 [(set (match_dup 0) (const_int -1))
8809 (and:DI (rotate:DI (match_dup 0)
8814 ;; Split a load of a large constant into the appropriate five-instruction
8815 ;; sequence. Handle anything in a constant number of insns.
8816 ;; When non-easy constants can go in the TOC, this should use
8817 ;; easy_fp_constant predicate.
8819 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8820 (match_operand:DI 1 "const_int_operand" ""))]
8821 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8822 [(set (match_dup 0) (match_dup 2))
8823 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8826 if (rs6000_emit_set_const (operands[0], operands[1]))
8833 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8834 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8835 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8836 [(set (match_dup 0) (match_dup 2))
8837 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8840 if (rs6000_emit_set_const (operands[0], operands[1]))
8846 ;; TImode/PTImode is similar, except that we usually want to compute the
8847 ;; address into a register and use lsi/stsi (the exception is during reload).
8849 (define_insn "*mov<mode>_string"
8850 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8851 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8853 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8854 && (gpc_reg_operand (operands[0], <MODE>mode)
8855 || gpc_reg_operand (operands[1], <MODE>mode))"
8858 switch (which_alternative)
8864 return \"stswi %1,%P0,16\";
8868 /* If the address is not used in the output, we can use lsi. Otherwise,
8869 fall through to generating four loads. */
8871 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8872 return \"lswi %0,%P1,16\";
8873 /* ... fall through ... */
8880 [(set_attr "type" "store,store,load,load,*,*")
8881 (set_attr "update" "yes")
8882 (set_attr "indexed" "yes")
8883 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8884 (const_string "always")
8885 (const_string "conditional")))])
8887 (define_insn "*mov<mode>_ppc64"
8888 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8889 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8890 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8891 && (gpc_reg_operand (operands[0], <MODE>mode)
8892 || gpc_reg_operand (operands[1], <MODE>mode)))"
8894 return rs6000_output_move_128bit (operands);
8896 [(set_attr "type" "store,store,load,load,*,*")
8897 (set_attr "length" "8")])
8900 [(set (match_operand:TI2 0 "int_reg_operand" "")
8901 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8903 && (VECTOR_MEM_NONE_P (<MODE>mode)
8904 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8905 [(set (match_dup 2) (match_dup 4))
8906 (set (match_dup 3) (match_dup 5))]
8909 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8911 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8913 if (CONST_WIDE_INT_P (operands[1]))
8915 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8916 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8918 else if (CONST_INT_P (operands[1]))
8920 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8921 operands[5] = operands[1];
8928 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8929 (match_operand:TI2 1 "input_operand" ""))]
8931 && gpr_or_gpr_p (operands[0], operands[1])
8932 && !direct_move_p (operands[0], operands[1])
8933 && !quad_load_store_p (operands[0], operands[1])"
8935 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8937 (define_expand "load_multiple"
8938 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8939 (match_operand:SI 1 "" ""))
8940 (use (match_operand:SI 2 "" ""))])]
8941 "TARGET_STRING && !TARGET_POWERPC64"
8949 /* Support only loading a constant number of fixed-point registers from
8950 memory and only bother with this if more than two; the machine
8951 doesn't support more than eight. */
8952 if (GET_CODE (operands[2]) != CONST_INT
8953 || INTVAL (operands[2]) <= 2
8954 || INTVAL (operands[2]) > 8
8955 || GET_CODE (operands[1]) != MEM
8956 || GET_CODE (operands[0]) != REG
8957 || REGNO (operands[0]) >= 32)
8960 count = INTVAL (operands[2]);
8961 regno = REGNO (operands[0]);
8963 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8964 op1 = replace_equiv_address (operands[1],
8965 force_reg (SImode, XEXP (operands[1], 0)));
8967 for (i = 0; i < count; i++)
8968 XVECEXP (operands[3], 0, i)
8969 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8970 adjust_address_nv (op1, SImode, i * 4));
8973 (define_insn "*ldmsi8"
8974 [(match_parallel 0 "load_multiple_operation"
8975 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8976 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8977 (set (match_operand:SI 3 "gpc_reg_operand" "")
8978 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8979 (set (match_operand:SI 4 "gpc_reg_operand" "")
8980 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8981 (set (match_operand:SI 5 "gpc_reg_operand" "")
8982 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8983 (set (match_operand:SI 6 "gpc_reg_operand" "")
8984 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8985 (set (match_operand:SI 7 "gpc_reg_operand" "")
8986 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8987 (set (match_operand:SI 8 "gpc_reg_operand" "")
8988 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8989 (set (match_operand:SI 9 "gpc_reg_operand" "")
8990 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8991 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8993 { return rs6000_output_load_multiple (operands); }"
8994 [(set_attr "type" "load")
8995 (set_attr "update" "yes")
8996 (set_attr "indexed" "yes")
8997 (set_attr "length" "32")])
8999 (define_insn "*ldmsi7"
9000 [(match_parallel 0 "load_multiple_operation"
9001 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9002 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9003 (set (match_operand:SI 3 "gpc_reg_operand" "")
9004 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9005 (set (match_operand:SI 4 "gpc_reg_operand" "")
9006 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9007 (set (match_operand:SI 5 "gpc_reg_operand" "")
9008 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9009 (set (match_operand:SI 6 "gpc_reg_operand" "")
9010 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9011 (set (match_operand:SI 7 "gpc_reg_operand" "")
9012 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9013 (set (match_operand:SI 8 "gpc_reg_operand" "")
9014 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9015 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9017 { return rs6000_output_load_multiple (operands); }"
9018 [(set_attr "type" "load")
9019 (set_attr "update" "yes")
9020 (set_attr "indexed" "yes")
9021 (set_attr "length" "32")])
9023 (define_insn "*ldmsi6"
9024 [(match_parallel 0 "load_multiple_operation"
9025 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9026 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9027 (set (match_operand:SI 3 "gpc_reg_operand" "")
9028 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9029 (set (match_operand:SI 4 "gpc_reg_operand" "")
9030 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9031 (set (match_operand:SI 5 "gpc_reg_operand" "")
9032 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9033 (set (match_operand:SI 6 "gpc_reg_operand" "")
9034 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9035 (set (match_operand:SI 7 "gpc_reg_operand" "")
9036 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9037 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9039 { return rs6000_output_load_multiple (operands); }"
9040 [(set_attr "type" "load")
9041 (set_attr "update" "yes")
9042 (set_attr "indexed" "yes")
9043 (set_attr "length" "32")])
9045 (define_insn "*ldmsi5"
9046 [(match_parallel 0 "load_multiple_operation"
9047 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9048 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9049 (set (match_operand:SI 3 "gpc_reg_operand" "")
9050 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9051 (set (match_operand:SI 4 "gpc_reg_operand" "")
9052 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9053 (set (match_operand:SI 5 "gpc_reg_operand" "")
9054 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9055 (set (match_operand:SI 6 "gpc_reg_operand" "")
9056 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9057 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9059 { return rs6000_output_load_multiple (operands); }"
9060 [(set_attr "type" "load")
9061 (set_attr "update" "yes")
9062 (set_attr "indexed" "yes")
9063 (set_attr "length" "32")])
9065 (define_insn "*ldmsi4"
9066 [(match_parallel 0 "load_multiple_operation"
9067 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9068 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9069 (set (match_operand:SI 3 "gpc_reg_operand" "")
9070 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9071 (set (match_operand:SI 4 "gpc_reg_operand" "")
9072 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9073 (set (match_operand:SI 5 "gpc_reg_operand" "")
9074 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9075 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9077 { return rs6000_output_load_multiple (operands); }"
9078 [(set_attr "type" "load")
9079 (set_attr "update" "yes")
9080 (set_attr "indexed" "yes")
9081 (set_attr "length" "32")])
9083 (define_insn "*ldmsi3"
9084 [(match_parallel 0 "load_multiple_operation"
9085 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9086 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9087 (set (match_operand:SI 3 "gpc_reg_operand" "")
9088 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9089 (set (match_operand:SI 4 "gpc_reg_operand" "")
9090 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9091 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9093 { return rs6000_output_load_multiple (operands); }"
9094 [(set_attr "type" "load")
9095 (set_attr "update" "yes")
9096 (set_attr "indexed" "yes")
9097 (set_attr "length" "32")])
9099 (define_expand "store_multiple"
9100 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9101 (match_operand:SI 1 "" ""))
9102 (clobber (scratch:SI))
9103 (use (match_operand:SI 2 "" ""))])]
9104 "TARGET_STRING && !TARGET_POWERPC64"
9113 /* Support only storing a constant number of fixed-point registers to
9114 memory and only bother with this if more than two; the machine
9115 doesn't support more than eight. */
9116 if (GET_CODE (operands[2]) != CONST_INT
9117 || INTVAL (operands[2]) <= 2
9118 || INTVAL (operands[2]) > 8
9119 || GET_CODE (operands[0]) != MEM
9120 || GET_CODE (operands[1]) != REG
9121 || REGNO (operands[1]) >= 32)
9124 count = INTVAL (operands[2]);
9125 regno = REGNO (operands[1]);
9127 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9128 to = force_reg (SImode, XEXP (operands[0], 0));
9129 op0 = replace_equiv_address (operands[0], to);
9131 XVECEXP (operands[3], 0, 0)
9132 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9133 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9134 gen_rtx_SCRATCH (SImode));
9136 for (i = 1; i < count; i++)
9137 XVECEXP (operands[3], 0, i + 1)
9138 = gen_rtx_SET (VOIDmode,
9139 adjust_address_nv (op0, SImode, i * 4),
9140 gen_rtx_REG (SImode, regno + i));
9143 (define_insn "*stmsi8"
9144 [(match_parallel 0 "store_multiple_operation"
9145 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9146 (match_operand:SI 2 "gpc_reg_operand" "r"))
9147 (clobber (match_scratch:SI 3 "=X"))
9148 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9149 (match_operand:SI 4 "gpc_reg_operand" "r"))
9150 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9151 (match_operand:SI 5 "gpc_reg_operand" "r"))
9152 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9153 (match_operand:SI 6 "gpc_reg_operand" "r"))
9154 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9155 (match_operand:SI 7 "gpc_reg_operand" "r"))
9156 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9157 (match_operand:SI 8 "gpc_reg_operand" "r"))
9158 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9159 (match_operand:SI 9 "gpc_reg_operand" "r"))
9160 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9161 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9162 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9164 [(set_attr "type" "store")
9165 (set_attr "update" "yes")
9166 (set_attr "indexed" "yes")
9167 (set_attr "cell_micro" "always")])
9169 (define_insn "*stmsi7"
9170 [(match_parallel 0 "store_multiple_operation"
9171 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9172 (match_operand:SI 2 "gpc_reg_operand" "r"))
9173 (clobber (match_scratch:SI 3 "=X"))
9174 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9175 (match_operand:SI 4 "gpc_reg_operand" "r"))
9176 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9177 (match_operand:SI 5 "gpc_reg_operand" "r"))
9178 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9179 (match_operand:SI 6 "gpc_reg_operand" "r"))
9180 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9181 (match_operand:SI 7 "gpc_reg_operand" "r"))
9182 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9183 (match_operand:SI 8 "gpc_reg_operand" "r"))
9184 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9185 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9186 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9188 [(set_attr "type" "store")
9189 (set_attr "update" "yes")
9190 (set_attr "indexed" "yes")
9191 (set_attr "cell_micro" "always")])
9193 (define_insn "*stmsi6"
9194 [(match_parallel 0 "store_multiple_operation"
9195 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9196 (match_operand:SI 2 "gpc_reg_operand" "r"))
9197 (clobber (match_scratch:SI 3 "=X"))
9198 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9199 (match_operand:SI 4 "gpc_reg_operand" "r"))
9200 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9201 (match_operand:SI 5 "gpc_reg_operand" "r"))
9202 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9203 (match_operand:SI 6 "gpc_reg_operand" "r"))
9204 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9205 (match_operand:SI 7 "gpc_reg_operand" "r"))
9206 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9207 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9208 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9210 [(set_attr "type" "store")
9211 (set_attr "update" "yes")
9212 (set_attr "indexed" "yes")
9213 (set_attr "cell_micro" "always")])
9215 (define_insn "*stmsi5"
9216 [(match_parallel 0 "store_multiple_operation"
9217 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9218 (match_operand:SI 2 "gpc_reg_operand" "r"))
9219 (clobber (match_scratch:SI 3 "=X"))
9220 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9221 (match_operand:SI 4 "gpc_reg_operand" "r"))
9222 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9223 (match_operand:SI 5 "gpc_reg_operand" "r"))
9224 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9225 (match_operand:SI 6 "gpc_reg_operand" "r"))
9226 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9227 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9228 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9230 [(set_attr "type" "store")
9231 (set_attr "update" "yes")
9232 (set_attr "indexed" "yes")
9233 (set_attr "cell_micro" "always")])
9235 (define_insn "*stmsi4"
9236 [(match_parallel 0 "store_multiple_operation"
9237 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9238 (match_operand:SI 2 "gpc_reg_operand" "r"))
9239 (clobber (match_scratch:SI 3 "=X"))
9240 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9241 (match_operand:SI 4 "gpc_reg_operand" "r"))
9242 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9243 (match_operand:SI 5 "gpc_reg_operand" "r"))
9244 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9245 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9246 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9248 [(set_attr "type" "store")
9249 (set_attr "update" "yes")
9250 (set_attr "indexed" "yes")
9251 (set_attr "cell_micro" "always")])
9253 (define_insn "*stmsi3"
9254 [(match_parallel 0 "store_multiple_operation"
9255 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9256 (match_operand:SI 2 "gpc_reg_operand" "r"))
9257 (clobber (match_scratch:SI 3 "=X"))
9258 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9259 (match_operand:SI 4 "gpc_reg_operand" "r"))
9260 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9261 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9262 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9264 [(set_attr "type" "store")
9265 (set_attr "update" "yes")
9266 (set_attr "indexed" "yes")
9267 (set_attr "cell_micro" "always")])
9269 (define_expand "setmemsi"
9270 [(parallel [(set (match_operand:BLK 0 "" "")
9271 (match_operand 2 "const_int_operand" ""))
9272 (use (match_operand:SI 1 "" ""))
9273 (use (match_operand:SI 3 "" ""))])]
9277 /* If value to set is not zero, use the library routine. */
9278 if (operands[2] != const0_rtx)
9281 if (expand_block_clear (operands))
9287 ;; String/block move insn.
9288 ;; Argument 0 is the destination
9289 ;; Argument 1 is the source
9290 ;; Argument 2 is the length
9291 ;; Argument 3 is the alignment
9293 (define_expand "movmemsi"
9294 [(parallel [(set (match_operand:BLK 0 "" "")
9295 (match_operand:BLK 1 "" ""))
9296 (use (match_operand:SI 2 "" ""))
9297 (use (match_operand:SI 3 "" ""))])]
9301 if (expand_block_move (operands))
9307 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9308 ;; register allocator doesn't have a clue about allocating 8 word registers.
9309 ;; rD/rS = r5 is preferred, efficient form.
9310 (define_expand "movmemsi_8reg"
9311 [(parallel [(set (match_operand 0 "" "")
9312 (match_operand 1 "" ""))
9313 (use (match_operand 2 "" ""))
9314 (use (match_operand 3 "" ""))
9315 (clobber (reg:SI 5))
9316 (clobber (reg:SI 6))
9317 (clobber (reg:SI 7))
9318 (clobber (reg:SI 8))
9319 (clobber (reg:SI 9))
9320 (clobber (reg:SI 10))
9321 (clobber (reg:SI 11))
9322 (clobber (reg:SI 12))
9323 (clobber (match_scratch:SI 4 ""))])]
9328 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9329 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9330 (use (match_operand:SI 2 "immediate_operand" "i"))
9331 (use (match_operand:SI 3 "immediate_operand" "i"))
9332 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9333 (clobber (reg:SI 6))
9334 (clobber (reg:SI 7))
9335 (clobber (reg:SI 8))
9336 (clobber (reg:SI 9))
9337 (clobber (reg:SI 10))
9338 (clobber (reg:SI 11))
9339 (clobber (reg:SI 12))
9340 (clobber (match_scratch:SI 5 "=X"))]
9342 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9343 || INTVAL (operands[2]) == 0)
9344 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9345 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9346 && REGNO (operands[4]) == 5"
9347 "lswi %4,%1,%2\;stswi %4,%0,%2"
9348 [(set_attr "type" "store")
9349 (set_attr "update" "yes")
9350 (set_attr "indexed" "yes")
9351 (set_attr "cell_micro" "always")
9352 (set_attr "length" "8")])
9354 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9355 ;; register allocator doesn't have a clue about allocating 6 word registers.
9356 ;; rD/rS = r5 is preferred, efficient form.
9357 (define_expand "movmemsi_6reg"
9358 [(parallel [(set (match_operand 0 "" "")
9359 (match_operand 1 "" ""))
9360 (use (match_operand 2 "" ""))
9361 (use (match_operand 3 "" ""))
9362 (clobber (reg:SI 5))
9363 (clobber (reg:SI 6))
9364 (clobber (reg:SI 7))
9365 (clobber (reg:SI 8))
9366 (clobber (reg:SI 9))
9367 (clobber (reg:SI 10))
9368 (clobber (match_scratch:SI 4 ""))])]
9373 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9374 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9375 (use (match_operand:SI 2 "immediate_operand" "i"))
9376 (use (match_operand:SI 3 "immediate_operand" "i"))
9377 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9378 (clobber (reg:SI 6))
9379 (clobber (reg:SI 7))
9380 (clobber (reg:SI 8))
9381 (clobber (reg:SI 9))
9382 (clobber (reg:SI 10))
9383 (clobber (match_scratch:SI 5 "=X"))]
9385 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9386 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9387 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9388 && REGNO (operands[4]) == 5"
9389 "lswi %4,%1,%2\;stswi %4,%0,%2"
9390 [(set_attr "type" "store")
9391 (set_attr "update" "yes")
9392 (set_attr "indexed" "yes")
9393 (set_attr "cell_micro" "always")
9394 (set_attr "length" "8")])
9396 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9397 ;; problems with TImode.
9398 ;; rD/rS = r5 is preferred, efficient form.
9399 (define_expand "movmemsi_4reg"
9400 [(parallel [(set (match_operand 0 "" "")
9401 (match_operand 1 "" ""))
9402 (use (match_operand 2 "" ""))
9403 (use (match_operand 3 "" ""))
9404 (clobber (reg:SI 5))
9405 (clobber (reg:SI 6))
9406 (clobber (reg:SI 7))
9407 (clobber (reg:SI 8))
9408 (clobber (match_scratch:SI 4 ""))])]
9413 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9414 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9415 (use (match_operand:SI 2 "immediate_operand" "i"))
9416 (use (match_operand:SI 3 "immediate_operand" "i"))
9417 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9418 (clobber (reg:SI 6))
9419 (clobber (reg:SI 7))
9420 (clobber (reg:SI 8))
9421 (clobber (match_scratch:SI 5 "=X"))]
9423 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9424 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9425 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9426 && REGNO (operands[4]) == 5"
9427 "lswi %4,%1,%2\;stswi %4,%0,%2"
9428 [(set_attr "type" "store")
9429 (set_attr "update" "yes")
9430 (set_attr "indexed" "yes")
9431 (set_attr "cell_micro" "always")
9432 (set_attr "length" "8")])
9434 ;; Move up to 8 bytes at a time.
9435 (define_expand "movmemsi_2reg"
9436 [(parallel [(set (match_operand 0 "" "")
9437 (match_operand 1 "" ""))
9438 (use (match_operand 2 "" ""))
9439 (use (match_operand 3 "" ""))
9440 (clobber (match_scratch:DI 4 ""))
9441 (clobber (match_scratch:SI 5 ""))])]
9442 "TARGET_STRING && ! TARGET_POWERPC64"
9446 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9447 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9448 (use (match_operand:SI 2 "immediate_operand" "i"))
9449 (use (match_operand:SI 3 "immediate_operand" "i"))
9450 (clobber (match_scratch:DI 4 "=&r"))
9451 (clobber (match_scratch:SI 5 "=X"))]
9452 "TARGET_STRING && ! TARGET_POWERPC64
9453 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9454 "lswi %4,%1,%2\;stswi %4,%0,%2"
9455 [(set_attr "type" "store")
9456 (set_attr "update" "yes")
9457 (set_attr "indexed" "yes")
9458 (set_attr "cell_micro" "always")
9459 (set_attr "length" "8")])
9461 ;; Move up to 4 bytes at a time.
9462 (define_expand "movmemsi_1reg"
9463 [(parallel [(set (match_operand 0 "" "")
9464 (match_operand 1 "" ""))
9465 (use (match_operand 2 "" ""))
9466 (use (match_operand 3 "" ""))
9467 (clobber (match_scratch:SI 4 ""))
9468 (clobber (match_scratch:SI 5 ""))])]
9473 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9474 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9475 (use (match_operand:SI 2 "immediate_operand" "i"))
9476 (use (match_operand:SI 3 "immediate_operand" "i"))
9477 (clobber (match_scratch:SI 4 "=&r"))
9478 (clobber (match_scratch:SI 5 "=X"))]
9479 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9480 "lswi %4,%1,%2\;stswi %4,%0,%2"
9481 [(set_attr "type" "store")
9482 (set_attr "update" "yes")
9483 (set_attr "indexed" "yes")
9484 (set_attr "cell_micro" "always")
9485 (set_attr "length" "8")])
9487 ;; Define insns that do load or store with update. Some of these we can
9488 ;; get by using pre-decrement or pre-increment, but the hardware can also
9489 ;; do cases where the increment is not the size of the object.
9491 ;; In all these cases, we use operands 0 and 1 for the register being
9492 ;; incremented because those are the operands that local-alloc will
9493 ;; tie and these are the pair most likely to be tieable (and the ones
9494 ;; that will benefit the most).
9496 (define_insn "*movdi_update1"
9497 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9498 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9499 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9500 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9501 (plus:DI (match_dup 1) (match_dup 2)))]
9502 "TARGET_POWERPC64 && TARGET_UPDATE
9503 && (!avoiding_indexed_address_p (DImode)
9504 || !gpc_reg_operand (operands[2], DImode))"
9508 [(set_attr "type" "load")
9509 (set_attr "update" "yes")
9510 (set_attr "indexed" "yes,no")])
9512 (define_insn "movdi_<mode>_update"
9513 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9514 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9515 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9516 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9517 (plus:P (match_dup 1) (match_dup 2)))]
9518 "TARGET_POWERPC64 && TARGET_UPDATE
9519 && (!avoiding_indexed_address_p (Pmode)
9520 || !gpc_reg_operand (operands[2], Pmode)
9521 || (REG_P (operands[0])
9522 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9526 [(set_attr "type" "store")
9527 (set_attr "update" "yes")
9528 (set_attr "indexed" "yes,no")])
9530 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9531 ;; needed for stack allocation, even if the user passes -mno-update.
9532 (define_insn "movdi_<mode>_update_stack"
9533 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9534 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9535 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9536 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9537 (plus:P (match_dup 1) (match_dup 2)))]
9542 [(set_attr "type" "store")
9543 (set_attr "update" "yes")
9544 (set_attr "indexed" "yes,no")])
9546 (define_insn "*movsi_update1"
9547 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9548 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9549 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9550 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9551 (plus:SI (match_dup 1) (match_dup 2)))]
9553 && (!avoiding_indexed_address_p (SImode)
9554 || !gpc_reg_operand (operands[2], SImode))"
9558 [(set_attr "type" "load")
9559 (set_attr "update" "yes")
9560 (set_attr "indexed" "yes,no")])
9562 (define_insn "*movsi_update2"
9563 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9565 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9566 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9567 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9568 (plus:DI (match_dup 1) (match_dup 2)))]
9569 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9570 && !avoiding_indexed_address_p (DImode)"
9572 [(set_attr "type" "load")
9573 (set_attr "sign_extend" "yes")
9574 (set_attr "update" "yes")
9575 (set_attr "indexed" "yes")])
9577 (define_insn "movsi_update"
9578 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9579 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9580 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9581 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9582 (plus:SI (match_dup 1) (match_dup 2)))]
9584 && (!avoiding_indexed_address_p (SImode)
9585 || !gpc_reg_operand (operands[2], SImode)
9586 || (REG_P (operands[0])
9587 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9591 [(set_attr "type" "store")
9592 (set_attr "update" "yes")
9593 (set_attr "indexed" "yes,no")])
9595 ;; This is an unconditional pattern; needed for stack allocation, even
9596 ;; if the user passes -mno-update.
9597 (define_insn "movsi_update_stack"
9598 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9599 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9600 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9601 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9602 (plus:SI (match_dup 1) (match_dup 2)))]
9607 [(set_attr "type" "store")
9608 (set_attr "update" "yes")
9609 (set_attr "indexed" "yes,no")])
9611 (define_insn "*movhi_update1"
9612 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9613 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9614 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9615 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9616 (plus:SI (match_dup 1) (match_dup 2)))]
9618 && (!avoiding_indexed_address_p (SImode)
9619 || !gpc_reg_operand (operands[2], SImode))"
9623 [(set_attr "type" "load")
9624 (set_attr "update" "yes")
9625 (set_attr "indexed" "yes,no")])
9627 (define_insn "*movhi_update2"
9628 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9630 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9631 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9632 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9633 (plus:SI (match_dup 1) (match_dup 2)))]
9635 && (!avoiding_indexed_address_p (SImode)
9636 || !gpc_reg_operand (operands[2], SImode))"
9640 [(set_attr "type" "load")
9641 (set_attr "update" "yes")
9642 (set_attr "indexed" "yes,no")])
9644 (define_insn "*movhi_update3"
9645 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9647 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9648 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9649 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9650 (plus:SI (match_dup 1) (match_dup 2)))]
9651 "TARGET_UPDATE && rs6000_gen_cell_microcode
9652 && (!avoiding_indexed_address_p (SImode)
9653 || !gpc_reg_operand (operands[2], SImode))"
9657 [(set_attr "type" "load")
9658 (set_attr "sign_extend" "yes")
9659 (set_attr "update" "yes")
9660 (set_attr "indexed" "yes,no")])
9662 (define_insn "*movhi_update4"
9663 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9664 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9665 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9666 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9667 (plus:SI (match_dup 1) (match_dup 2)))]
9669 && (!avoiding_indexed_address_p (SImode)
9670 || !gpc_reg_operand (operands[2], SImode))"
9674 [(set_attr "type" "store")
9675 (set_attr "update" "yes")
9676 (set_attr "indexed" "yes,no")])
9678 (define_insn "*movqi_update1"
9679 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9680 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9681 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9682 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9683 (plus:SI (match_dup 1) (match_dup 2)))]
9685 && (!avoiding_indexed_address_p (SImode)
9686 || !gpc_reg_operand (operands[2], SImode))"
9690 [(set_attr "type" "load")
9691 (set_attr "update" "yes")
9692 (set_attr "indexed" "yes,no")])
9694 (define_insn "*movqi_update2"
9695 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9697 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9698 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9699 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9700 (plus:SI (match_dup 1) (match_dup 2)))]
9702 && (!avoiding_indexed_address_p (SImode)
9703 || !gpc_reg_operand (operands[2], SImode))"
9707 [(set_attr "type" "load")
9708 (set_attr "update" "yes")
9709 (set_attr "indexed" "yes,no")])
9711 (define_insn "*movqi_update3"
9712 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9713 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9714 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9715 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9716 (plus:SI (match_dup 1) (match_dup 2)))]
9718 && (!avoiding_indexed_address_p (SImode)
9719 || !gpc_reg_operand (operands[2], SImode))"
9723 [(set_attr "type" "store")
9724 (set_attr "update" "yes")
9725 (set_attr "indexed" "yes,no")])
9727 (define_insn "*movsf_update1"
9728 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9729 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9730 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9731 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9732 (plus:SI (match_dup 1) (match_dup 2)))]
9733 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9734 && (!avoiding_indexed_address_p (SImode)
9735 || !gpc_reg_operand (operands[2], SImode))"
9739 [(set_attr "type" "fpload")
9740 (set_attr "update" "yes")
9741 (set_attr "indexed" "yes,no")])
9743 (define_insn "*movsf_update2"
9744 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9745 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9746 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9747 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9748 (plus:SI (match_dup 1) (match_dup 2)))]
9749 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9750 && (!avoiding_indexed_address_p (SImode)
9751 || !gpc_reg_operand (operands[2], SImode))"
9755 [(set_attr "type" "fpstore")
9756 (set_attr "update" "yes")
9757 (set_attr "indexed" "yes,no")])
9759 (define_insn "*movsf_update3"
9760 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9761 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9762 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9763 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9764 (plus:SI (match_dup 1) (match_dup 2)))]
9765 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9766 && (!avoiding_indexed_address_p (SImode)
9767 || !gpc_reg_operand (operands[2], SImode))"
9771 [(set_attr "type" "load")
9772 (set_attr "update" "yes")
9773 (set_attr "indexed" "yes,no")])
9775 (define_insn "*movsf_update4"
9776 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9777 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9778 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9779 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9780 (plus:SI (match_dup 1) (match_dup 2)))]
9781 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9782 && (!avoiding_indexed_address_p (SImode)
9783 || !gpc_reg_operand (operands[2], SImode))"
9787 [(set_attr "type" "store")
9788 (set_attr "update" "yes")
9789 (set_attr "indexed" "yes,no")])
9791 (define_insn "*movdf_update1"
9792 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9793 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9794 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9795 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9796 (plus:SI (match_dup 1) (match_dup 2)))]
9797 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9798 && (!avoiding_indexed_address_p (SImode)
9799 || !gpc_reg_operand (operands[2], SImode))"
9803 [(set_attr "type" "fpload")
9804 (set_attr "update" "yes")
9805 (set_attr "indexed" "yes,no")])
9807 (define_insn "*movdf_update2"
9808 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9809 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9810 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9811 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9812 (plus:SI (match_dup 1) (match_dup 2)))]
9813 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9814 && (!avoiding_indexed_address_p (SImode)
9815 || !gpc_reg_operand (operands[2], SImode))"
9819 [(set_attr "type" "fpstore")
9820 (set_attr "update" "yes")
9821 (set_attr "indexed" "yes,no")])
9824 ;; After inserting conditional returns we can sometimes have
9825 ;; unnecessary register moves. Unfortunately we cannot have a
9826 ;; modeless peephole here, because some single SImode sets have early
9827 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9828 ;; sequences, using get_attr_length here will smash the operands
9829 ;; array. Neither is there an early_cobbler_p predicate.
9830 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9831 ;; Also this optimization interferes with scalars going into
9832 ;; altivec registers (the code does reloading through the FPRs).
9834 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9835 (match_operand:DF 1 "any_operand" ""))
9836 (set (match_operand:DF 2 "gpc_reg_operand" "")
9838 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9839 && !TARGET_UPPER_REGS_DF
9840 && peep2_reg_dead_p (2, operands[0])"
9841 [(set (match_dup 2) (match_dup 1))])
9844 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9845 (match_operand:SF 1 "any_operand" ""))
9846 (set (match_operand:SF 2 "gpc_reg_operand" "")
9848 "!TARGET_UPPER_REGS_SF
9849 && peep2_reg_dead_p (2, operands[0])"
9850 [(set (match_dup 2) (match_dup 1))])
9855 ;; Mode attributes for different ABIs.
9856 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9857 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9858 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9859 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9861 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9862 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9863 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9864 (match_operand 4 "" "g")))
9865 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9866 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9868 (clobber (reg:SI LR_REGNO))]
9869 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9871 if (TARGET_CMODEL != CMODEL_SMALL)
9872 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9875 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9877 "&& TARGET_TLS_MARKERS"
9879 (unspec:TLSmode [(match_dup 1)
9882 (parallel [(set (match_dup 0)
9883 (call (mem:TLSmode (match_dup 3))
9885 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9886 (clobber (reg:SI LR_REGNO))])]
9888 [(set_attr "type" "two")
9889 (set (attr "length")
9890 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9894 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9895 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9896 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9897 (match_operand 4 "" "g")))
9898 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9899 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9901 (clobber (reg:SI LR_REGNO))]
9902 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9906 if (TARGET_SECURE_PLT && flag_pic == 2)
9907 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9909 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9912 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9914 "&& TARGET_TLS_MARKERS"
9916 (unspec:TLSmode [(match_dup 1)
9919 (parallel [(set (match_dup 0)
9920 (call (mem:TLSmode (match_dup 3))
9922 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9923 (clobber (reg:SI LR_REGNO))])]
9925 [(set_attr "type" "two")
9926 (set_attr "length" "8")])
9928 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9929 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9930 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9931 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9933 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9934 "addi %0,%1,%2@got@tlsgd"
9935 "&& TARGET_CMODEL != CMODEL_SMALL"
9938 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9940 (lo_sum:TLSmode (match_dup 3)
9941 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9944 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9946 [(set (attr "length")
9947 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9951 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9952 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9954 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9955 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9957 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9958 "addis %0,%1,%2@got@tlsgd@ha"
9959 [(set_attr "length" "4")])
9961 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9962 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9963 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9964 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9965 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9967 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9968 "addi %0,%1,%2@got@tlsgd@l"
9969 [(set_attr "length" "4")])
9971 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9972 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9973 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9974 (match_operand 2 "" "g")))
9975 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9977 (clobber (reg:SI LR_REGNO))]
9978 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9979 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9980 "bl %z1(%3@tlsgd)\;nop"
9981 [(set_attr "type" "branch")
9982 (set_attr "length" "8")])
9984 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9985 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9986 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9987 (match_operand 2 "" "g")))
9988 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9990 (clobber (reg:SI LR_REGNO))]
9991 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9995 if (TARGET_SECURE_PLT && flag_pic == 2)
9996 return "bl %z1+32768(%3@tlsgd)@plt";
9997 return "bl %z1(%3@tlsgd)@plt";
9999 return "bl %z1(%3@tlsgd)";
10001 [(set_attr "type" "branch")
10002 (set_attr "length" "4")])
10004 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10005 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10006 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10007 (match_operand 3 "" "g")))
10008 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10010 (clobber (reg:SI LR_REGNO))]
10011 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10013 if (TARGET_CMODEL != CMODEL_SMALL)
10014 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10017 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10019 "&& TARGET_TLS_MARKERS"
10020 [(set (match_dup 0)
10021 (unspec:TLSmode [(match_dup 1)]
10023 (parallel [(set (match_dup 0)
10024 (call (mem:TLSmode (match_dup 2))
10026 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10027 (clobber (reg:SI LR_REGNO))])]
10029 [(set_attr "type" "two")
10030 (set (attr "length")
10031 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10035 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10036 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10037 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10038 (match_operand 3 "" "g")))
10039 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10041 (clobber (reg:SI LR_REGNO))]
10042 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10046 if (TARGET_SECURE_PLT && flag_pic == 2)
10047 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10049 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10052 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10054 "&& TARGET_TLS_MARKERS"
10055 [(set (match_dup 0)
10056 (unspec:TLSmode [(match_dup 1)]
10058 (parallel [(set (match_dup 0)
10059 (call (mem:TLSmode (match_dup 2))
10061 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10062 (clobber (reg:SI LR_REGNO))])]
10064 [(set_attr "length" "8")])
10066 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10067 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10068 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10070 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10071 "addi %0,%1,%&@got@tlsld"
10072 "&& TARGET_CMODEL != CMODEL_SMALL"
10073 [(set (match_dup 2)
10075 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10077 (lo_sum:TLSmode (match_dup 2)
10078 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10081 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10083 [(set (attr "length")
10084 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10088 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10089 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10091 (unspec:TLSmode [(const_int 0)
10092 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10094 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10095 "addis %0,%1,%&@got@tlsld@ha"
10096 [(set_attr "length" "4")])
10098 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10099 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10100 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10101 (unspec:TLSmode [(const_int 0)
10102 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10104 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10105 "addi %0,%1,%&@got@tlsld@l"
10106 [(set_attr "length" "4")])
10108 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10109 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10110 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10111 (match_operand 2 "" "g")))
10112 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10113 (clobber (reg:SI LR_REGNO))]
10114 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10115 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10116 "bl %z1(%&@tlsld)\;nop"
10117 [(set_attr "type" "branch")
10118 (set_attr "length" "8")])
10120 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10121 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10122 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10123 (match_operand 2 "" "g")))
10124 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10125 (clobber (reg:SI LR_REGNO))]
10126 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10130 if (TARGET_SECURE_PLT && flag_pic == 2)
10131 return "bl %z1+32768(%&@tlsld)@plt";
10132 return "bl %z1(%&@tlsld)@plt";
10134 return "bl %z1(%&@tlsld)";
10136 [(set_attr "type" "branch")
10137 (set_attr "length" "4")])
10139 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10140 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10141 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10142 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10143 UNSPEC_TLSDTPREL))]
10145 "addi %0,%1,%2@dtprel")
10147 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10148 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10149 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10150 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10151 UNSPEC_TLSDTPRELHA))]
10153 "addis %0,%1,%2@dtprel@ha")
10155 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10156 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10157 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10158 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10159 UNSPEC_TLSDTPRELLO))]
10161 "addi %0,%1,%2@dtprel@l")
10163 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10164 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10165 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10166 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10167 UNSPEC_TLSGOTDTPREL))]
10169 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10170 "&& TARGET_CMODEL != CMODEL_SMALL"
10171 [(set (match_dup 3)
10173 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10175 (lo_sum:TLSmode (match_dup 3)
10176 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10179 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10181 [(set (attr "length")
10182 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10186 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10187 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10189 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10190 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10191 UNSPEC_TLSGOTDTPREL)))]
10192 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10193 "addis %0,%1,%2@got@dtprel@ha"
10194 [(set_attr "length" "4")])
10196 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10197 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10198 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10199 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10200 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10201 UNSPEC_TLSGOTDTPREL)))]
10202 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10203 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10204 [(set_attr "length" "4")])
10206 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10208 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10209 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10212 "addi %0,%1,%2@tprel")
10214 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10215 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10216 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10217 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10218 UNSPEC_TLSTPRELHA))]
10220 "addis %0,%1,%2@tprel@ha")
10222 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10223 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10224 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10225 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10226 UNSPEC_TLSTPRELLO))]
10228 "addi %0,%1,%2@tprel@l")
10230 ;; "b" output constraint here and on tls_tls input to support linker tls
10231 ;; optimization. The linker may edit the instructions emitted by a
10232 ;; tls_got_tprel/tls_tls pair to addis,addi.
10233 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10234 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10235 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10236 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10237 UNSPEC_TLSGOTTPREL))]
10239 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10240 "&& TARGET_CMODEL != CMODEL_SMALL"
10241 [(set (match_dup 3)
10243 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10245 (lo_sum:TLSmode (match_dup 3)
10246 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10249 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10251 [(set (attr "length")
10252 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10256 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10257 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10259 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10260 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10261 UNSPEC_TLSGOTTPREL)))]
10262 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10263 "addis %0,%1,%2@got@tprel@ha"
10264 [(set_attr "length" "4")])
10266 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10267 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10268 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10269 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10270 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10271 UNSPEC_TLSGOTTPREL)))]
10272 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10273 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10274 [(set_attr "length" "4")])
10276 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10277 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10278 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10279 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10281 "TARGET_ELF && HAVE_AS_TLS"
10282 "add %0,%1,%2@tls")
10284 (define_expand "tls_get_tpointer"
10285 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10286 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10287 "TARGET_XCOFF && HAVE_AS_TLS"
10290 emit_insn (gen_tls_get_tpointer_internal ());
10291 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10295 (define_insn "tls_get_tpointer_internal"
10297 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10298 (clobber (reg:SI LR_REGNO))]
10299 "TARGET_XCOFF && HAVE_AS_TLS"
10300 "bla __get_tpointer")
10302 (define_expand "tls_get_addr<mode>"
10303 [(set (match_operand:P 0 "gpc_reg_operand" "")
10304 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10305 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10306 "TARGET_XCOFF && HAVE_AS_TLS"
10309 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10310 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10311 emit_insn (gen_tls_get_addr_internal<mode> ());
10312 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10316 (define_insn "tls_get_addr_internal<mode>"
10318 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10319 (clobber (reg:P 0))
10320 (clobber (reg:P 4))
10321 (clobber (reg:P 5))
10322 (clobber (reg:P 11))
10323 (clobber (reg:CC CR0_REGNO))
10324 (clobber (reg:P LR_REGNO))]
10325 "TARGET_XCOFF && HAVE_AS_TLS"
10326 "bla __tls_get_addr")
10328 ;; Next come insns related to the calling sequence.
10330 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10331 ;; We move the back-chain and decrement the stack pointer.
10333 (define_expand "allocate_stack"
10334 [(set (match_operand 0 "gpc_reg_operand" "")
10335 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10337 (minus (reg 1) (match_dup 1)))]
10340 { rtx chain = gen_reg_rtx (Pmode);
10341 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10343 rtx insn, par, set, mem;
10345 emit_move_insn (chain, stack_bot);
10347 /* Check stack bounds if necessary. */
10348 if (crtl->limit_stack)
10351 available = expand_binop (Pmode, sub_optab,
10352 stack_pointer_rtx, stack_limit_rtx,
10353 NULL_RTX, 1, OPTAB_WIDEN);
10354 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10357 if (GET_CODE (operands[1]) != CONST_INT
10358 || INTVAL (operands[1]) < -32767
10359 || INTVAL (operands[1]) > 32768)
10361 neg_op0 = gen_reg_rtx (Pmode);
10363 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10365 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10368 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10370 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10371 : gen_movdi_di_update_stack))
10372 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10374 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10375 it now and set the alias set/attributes. The above gen_*_update
10376 calls will generate a PARALLEL with the MEM set being the first
10378 par = PATTERN (insn);
10379 gcc_assert (GET_CODE (par) == PARALLEL);
10380 set = XVECEXP (par, 0, 0);
10381 gcc_assert (GET_CODE (set) == SET);
10382 mem = SET_DEST (set);
10383 gcc_assert (MEM_P (mem));
10384 MEM_NOTRAP_P (mem) = 1;
10385 set_mem_alias_set (mem, get_frame_alias_set ());
10387 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10391 ;; These patterns say how to save and restore the stack pointer. We need not
10392 ;; save the stack pointer at function level since we are careful to
10393 ;; preserve the backchain. At block level, we have to restore the backchain
10394 ;; when we restore the stack pointer.
10396 ;; For nonlocal gotos, we must save both the stack pointer and its
10397 ;; backchain and restore both. Note that in the nonlocal case, the
10398 ;; save area is a memory location.
10400 (define_expand "save_stack_function"
10401 [(match_operand 0 "any_operand" "")
10402 (match_operand 1 "any_operand" "")]
10406 (define_expand "restore_stack_function"
10407 [(match_operand 0 "any_operand" "")
10408 (match_operand 1 "any_operand" "")]
10412 ;; Adjust stack pointer (op0) to a new value (op1).
10413 ;; First copy old stack backchain to new location, and ensure that the
10414 ;; scheduler won't reorder the sp assignment before the backchain write.
10415 (define_expand "restore_stack_block"
10416 [(set (match_dup 2) (match_dup 3))
10417 (set (match_dup 4) (match_dup 2))
10419 (set (match_operand 0 "register_operand" "")
10420 (match_operand 1 "register_operand" ""))]
10426 operands[1] = force_reg (Pmode, operands[1]);
10427 operands[2] = gen_reg_rtx (Pmode);
10428 operands[3] = gen_frame_mem (Pmode, operands[0]);
10429 operands[4] = gen_frame_mem (Pmode, operands[1]);
10430 p = rtvec_alloc (1);
10431 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10432 gen_frame_mem (BLKmode, operands[0]),
10434 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10437 (define_expand "save_stack_nonlocal"
10438 [(set (match_dup 3) (match_dup 4))
10439 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10440 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10444 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10446 /* Copy the backchain to the first word, sp to the second. */
10447 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10448 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10449 operands[3] = gen_reg_rtx (Pmode);
10450 operands[4] = gen_frame_mem (Pmode, operands[1]);
10453 (define_expand "restore_stack_nonlocal"
10454 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10455 (set (match_dup 3) (match_dup 4))
10456 (set (match_dup 5) (match_dup 2))
10458 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10462 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10465 /* Restore the backchain from the first word, sp from the second. */
10466 operands[2] = gen_reg_rtx (Pmode);
10467 operands[3] = gen_reg_rtx (Pmode);
10468 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10469 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10470 operands[5] = gen_frame_mem (Pmode, operands[3]);
10471 p = rtvec_alloc (1);
10472 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10473 gen_frame_mem (BLKmode, operands[0]),
10475 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10478 ;; TOC register handling.
10480 ;; Code to initialize the TOC register...
10482 (define_insn "load_toc_aix_si"
10483 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10484 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10485 (use (reg:SI 2))])]
10486 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10490 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10491 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10492 operands[2] = gen_rtx_REG (Pmode, 2);
10493 return \"lwz %0,%1(%2)\";
10495 [(set_attr "type" "load")
10496 (set_attr "update" "no")
10497 (set_attr "indexed" "no")])
10499 (define_insn "load_toc_aix_di"
10500 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10501 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10502 (use (reg:DI 2))])]
10503 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10507 #ifdef TARGET_RELOCATABLE
10508 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10509 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10511 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10514 strcat (buf, \"@toc\");
10515 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10516 operands[2] = gen_rtx_REG (Pmode, 2);
10517 return \"ld %0,%1(%2)\";
10519 [(set_attr "type" "load")
10520 (set_attr "update" "no")
10521 (set_attr "indexed" "no")])
10523 (define_insn "load_toc_v4_pic_si"
10524 [(set (reg:SI LR_REGNO)
10525 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10526 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10527 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10528 [(set_attr "type" "branch")
10529 (set_attr "length" "4")])
10531 (define_expand "load_toc_v4_PIC_1"
10532 [(parallel [(set (reg:SI LR_REGNO)
10533 (match_operand:SI 0 "immediate_operand" "s"))
10534 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10535 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10536 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10539 (define_insn "load_toc_v4_PIC_1_normal"
10540 [(set (reg:SI LR_REGNO)
10541 (match_operand:SI 0 "immediate_operand" "s"))
10542 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10543 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10544 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10545 "bcl 20,31,%0\\n%0:"
10546 [(set_attr "type" "branch")
10547 (set_attr "length" "4")])
10549 (define_insn "load_toc_v4_PIC_1_476"
10550 [(set (reg:SI LR_REGNO)
10551 (match_operand:SI 0 "immediate_operand" "s"))
10552 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10553 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10554 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10558 static char templ[32];
10560 get_ppc476_thunk_name (name);
10561 sprintf (templ, \"bl %s\\n%%0:\", name);
10564 [(set_attr "type" "branch")
10565 (set_attr "length" "4")])
10567 (define_expand "load_toc_v4_PIC_1b"
10568 [(parallel [(set (reg:SI LR_REGNO)
10569 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10570 (label_ref (match_operand 1 "" ""))]
10573 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10576 (define_insn "load_toc_v4_PIC_1b_normal"
10577 [(set (reg:SI LR_REGNO)
10578 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10579 (label_ref (match_operand 1 "" ""))]
10582 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10583 "bcl 20,31,$+8\;.long %0-$"
10584 [(set_attr "type" "branch")
10585 (set_attr "length" "8")])
10587 (define_insn "load_toc_v4_PIC_1b_476"
10588 [(set (reg:SI LR_REGNO)
10589 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10590 (label_ref (match_operand 1 "" ""))]
10593 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10597 static char templ[32];
10599 get_ppc476_thunk_name (name);
10600 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10603 [(set_attr "type" "branch")
10604 (set_attr "length" "16")])
10606 (define_insn "load_toc_v4_PIC_2"
10607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10608 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10609 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10610 (match_operand:SI 3 "immediate_operand" "s")))))]
10611 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10613 [(set_attr "type" "load")])
10615 (define_insn "load_toc_v4_PIC_3b"
10616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10617 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10619 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10620 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10621 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10622 "addis %0,%1,%2-%3@ha")
10624 (define_insn "load_toc_v4_PIC_3c"
10625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10626 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10627 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10628 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10629 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10630 "addi %0,%1,%2-%3@l")
10632 ;; If the TOC is shared over a translation unit, as happens with all
10633 ;; the kinds of PIC that we support, we need to restore the TOC
10634 ;; pointer only when jumping over units of translation.
10635 ;; On Darwin, we need to reload the picbase.
10637 (define_expand "builtin_setjmp_receiver"
10638 [(use (label_ref (match_operand 0 "" "")))]
10639 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10640 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10641 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10645 if (DEFAULT_ABI == ABI_DARWIN)
10647 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10648 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10652 crtl->uses_pic_offset_table = 1;
10653 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10654 CODE_LABEL_NUMBER (operands[0]));
10655 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10657 emit_insn (gen_load_macho_picbase (tmplabrtx));
10658 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10659 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10663 rs6000_emit_load_toc_table (FALSE);
10667 ;; Largetoc support
10668 (define_insn "*largetoc_high"
10669 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10671 (unspec [(match_operand:DI 1 "" "")
10672 (match_operand:DI 2 "gpc_reg_operand" "b")]
10674 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10675 "addis %0,%2,%1@toc@ha")
10677 (define_insn "*largetoc_high_aix<mode>"
10678 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10680 (unspec [(match_operand:P 1 "" "")
10681 (match_operand:P 2 "gpc_reg_operand" "b")]
10683 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10684 "addis %0,%1@u(%2)")
10686 (define_insn "*largetoc_high_plus"
10687 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10690 (unspec [(match_operand:DI 1 "" "")
10691 (match_operand:DI 2 "gpc_reg_operand" "b")]
10693 (match_operand:DI 3 "add_cint_operand" "n"))))]
10694 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10695 "addis %0,%2,%1+%3@toc@ha")
10697 (define_insn "*largetoc_high_plus_aix<mode>"
10698 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10701 (unspec [(match_operand:P 1 "" "")
10702 (match_operand:P 2 "gpc_reg_operand" "b")]
10704 (match_operand:P 3 "add_cint_operand" "n"))))]
10705 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10706 "addis %0,%1+%3@u(%2)")
10708 (define_insn "*largetoc_low"
10709 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10710 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10711 (match_operand:DI 2 "" "")))]
10712 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10717 (define_insn "*largetoc_low_aix<mode>"
10718 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10719 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10720 (match_operand:P 2 "" "")))]
10721 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10724 (define_insn_and_split "*tocref<mode>"
10725 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10726 (match_operand:P 1 "small_toc_ref" "R"))]
10729 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10730 [(set (match_dup 0) (high:P (match_dup 1)))
10731 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10733 ;; Elf specific ways of loading addresses for non-PIC code.
10734 ;; The output of this could be r0, but we make a very strong
10735 ;; preference for a base register because it will usually
10736 ;; be needed there.
10737 (define_insn "elf_high"
10738 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10739 (high:SI (match_operand 1 "" "")))]
10740 "TARGET_ELF && ! TARGET_64BIT"
10743 (define_insn "elf_low"
10744 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10745 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10746 (match_operand 2 "" "")))]
10747 "TARGET_ELF && ! TARGET_64BIT"
10752 ;; Call and call_value insns
10753 (define_expand "call"
10754 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10755 (match_operand 1 "" ""))
10756 (use (match_operand 2 "" ""))
10757 (clobber (reg:SI LR_REGNO))])]
10762 if (MACHOPIC_INDIRECT)
10763 operands[0] = machopic_indirect_call_target (operands[0]);
10766 gcc_assert (GET_CODE (operands[0]) == MEM);
10767 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10769 operands[0] = XEXP (operands[0], 0);
10771 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10773 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10777 if (GET_CODE (operands[0]) != SYMBOL_REF
10778 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10780 if (INTVAL (operands[2]) & CALL_LONG)
10781 operands[0] = rs6000_longcall_ref (operands[0]);
10783 switch (DEFAULT_ABI)
10787 operands[0] = force_reg (Pmode, operands[0]);
10791 gcc_unreachable ();
10796 (define_expand "call_value"
10797 [(parallel [(set (match_operand 0 "" "")
10798 (call (mem:SI (match_operand 1 "address_operand" ""))
10799 (match_operand 2 "" "")))
10800 (use (match_operand 3 "" ""))
10801 (clobber (reg:SI LR_REGNO))])]
10806 if (MACHOPIC_INDIRECT)
10807 operands[1] = machopic_indirect_call_target (operands[1]);
10810 gcc_assert (GET_CODE (operands[1]) == MEM);
10811 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10813 operands[1] = XEXP (operands[1], 0);
10815 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10817 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10821 if (GET_CODE (operands[1]) != SYMBOL_REF
10822 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10824 if (INTVAL (operands[3]) & CALL_LONG)
10825 operands[1] = rs6000_longcall_ref (operands[1]);
10827 switch (DEFAULT_ABI)
10831 operands[1] = force_reg (Pmode, operands[1]);
10835 gcc_unreachable ();
10840 ;; Call to function in current module. No TOC pointer reload needed.
10841 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10842 ;; either the function was not prototyped, or it was prototyped as a
10843 ;; variable argument function. It is > 0 if FP registers were passed
10844 ;; and < 0 if they were not.
10846 (define_insn "*call_local32"
10847 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10848 (match_operand 1 "" "g,g"))
10849 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10850 (clobber (reg:SI LR_REGNO))]
10851 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10854 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10855 output_asm_insn (\"crxor 6,6,6\", operands);
10857 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10858 output_asm_insn (\"creqv 6,6,6\", operands);
10860 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10862 [(set_attr "type" "branch")
10863 (set_attr "length" "4,8")])
10865 (define_insn "*call_local64"
10866 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10867 (match_operand 1 "" "g,g"))
10868 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10869 (clobber (reg:SI LR_REGNO))]
10870 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10873 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10874 output_asm_insn (\"crxor 6,6,6\", operands);
10876 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10877 output_asm_insn (\"creqv 6,6,6\", operands);
10879 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10881 [(set_attr "type" "branch")
10882 (set_attr "length" "4,8")])
10884 (define_insn "*call_value_local32"
10885 [(set (match_operand 0 "" "")
10886 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10887 (match_operand 2 "" "g,g")))
10888 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10889 (clobber (reg:SI LR_REGNO))]
10890 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10893 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10894 output_asm_insn (\"crxor 6,6,6\", operands);
10896 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10897 output_asm_insn (\"creqv 6,6,6\", operands);
10899 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10901 [(set_attr "type" "branch")
10902 (set_attr "length" "4,8")])
10905 (define_insn "*call_value_local64"
10906 [(set (match_operand 0 "" "")
10907 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10908 (match_operand 2 "" "g,g")))
10909 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10910 (clobber (reg:SI LR_REGNO))]
10911 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10914 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10915 output_asm_insn (\"crxor 6,6,6\", operands);
10917 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10918 output_asm_insn (\"creqv 6,6,6\", operands);
10920 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10922 [(set_attr "type" "branch")
10923 (set_attr "length" "4,8")])
10926 ;; A function pointer under System V is just a normal pointer
10927 ;; operands[0] is the function pointer
10928 ;; operands[1] is the stack size to clean up
10929 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10930 ;; which indicates how to set cr1
10932 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10933 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10934 (match_operand 1 "" "g,g,g,g"))
10935 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10936 (clobber (reg:SI LR_REGNO))]
10937 "DEFAULT_ABI == ABI_V4
10938 || DEFAULT_ABI == ABI_DARWIN"
10940 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10941 output_asm_insn ("crxor 6,6,6", operands);
10943 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10944 output_asm_insn ("creqv 6,6,6", operands);
10948 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10949 (set_attr "length" "4,4,8,8")])
10951 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10952 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10953 (match_operand 1 "" "g,g"))
10954 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10955 (clobber (reg:SI LR_REGNO))]
10956 "(DEFAULT_ABI == ABI_DARWIN
10957 || (DEFAULT_ABI == ABI_V4
10958 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10960 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10961 output_asm_insn ("crxor 6,6,6", operands);
10963 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10964 output_asm_insn ("creqv 6,6,6", operands);
10967 return output_call(insn, operands, 0, 2);
10969 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10971 gcc_assert (!TARGET_SECURE_PLT);
10972 return "bl %z0@plt";
10978 "DEFAULT_ABI == ABI_V4
10979 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10980 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10981 [(parallel [(call (mem:SI (match_dup 0))
10983 (use (match_dup 2))
10984 (use (match_dup 3))
10985 (clobber (reg:SI LR_REGNO))])]
10987 operands[3] = pic_offset_table_rtx;
10989 [(set_attr "type" "branch,branch")
10990 (set_attr "length" "4,8")])
10992 (define_insn "*call_nonlocal_sysv_secure<mode>"
10993 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10994 (match_operand 1 "" "g,g"))
10995 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10996 (use (match_operand:SI 3 "register_operand" "r,r"))
10997 (clobber (reg:SI LR_REGNO))]
10998 "(DEFAULT_ABI == ABI_V4
10999 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11000 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11002 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11003 output_asm_insn ("crxor 6,6,6", operands);
11005 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11006 output_asm_insn ("creqv 6,6,6", operands);
11009 /* The magic 32768 offset here and in the other sysv call insns
11010 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11011 See sysv4.h:toc_section. */
11012 return "bl %z0+32768@plt";
11014 return "bl %z0@plt";
11016 [(set_attr "type" "branch,branch")
11017 (set_attr "length" "4,8")])
11019 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11020 [(set (match_operand 0 "" "")
11021 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11022 (match_operand 2 "" "g,g,g,g")))
11023 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11024 (clobber (reg:SI LR_REGNO))]
11025 "DEFAULT_ABI == ABI_V4
11026 || DEFAULT_ABI == ABI_DARWIN"
11028 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11029 output_asm_insn ("crxor 6,6,6", operands);
11031 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11032 output_asm_insn ("creqv 6,6,6", operands);
11036 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11037 (set_attr "length" "4,4,8,8")])
11039 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11040 [(set (match_operand 0 "" "")
11041 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11042 (match_operand 2 "" "g,g")))
11043 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11044 (clobber (reg:SI LR_REGNO))]
11045 "(DEFAULT_ABI == ABI_DARWIN
11046 || (DEFAULT_ABI == ABI_V4
11047 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11049 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11050 output_asm_insn ("crxor 6,6,6", operands);
11052 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11053 output_asm_insn ("creqv 6,6,6", operands);
11056 return output_call(insn, operands, 1, 3);
11058 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11060 gcc_assert (!TARGET_SECURE_PLT);
11061 return "bl %z1@plt";
11067 "DEFAULT_ABI == ABI_V4
11068 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11069 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11070 [(parallel [(set (match_dup 0)
11071 (call (mem:SI (match_dup 1))
11073 (use (match_dup 3))
11074 (use (match_dup 4))
11075 (clobber (reg:SI LR_REGNO))])]
11077 operands[4] = pic_offset_table_rtx;
11079 [(set_attr "type" "branch,branch")
11080 (set_attr "length" "4,8")])
11082 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11083 [(set (match_operand 0 "" "")
11084 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11085 (match_operand 2 "" "g,g")))
11086 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11087 (use (match_operand:SI 4 "register_operand" "r,r"))
11088 (clobber (reg:SI LR_REGNO))]
11089 "(DEFAULT_ABI == ABI_V4
11090 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11091 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11093 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11094 output_asm_insn ("crxor 6,6,6", operands);
11096 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11097 output_asm_insn ("creqv 6,6,6", operands);
11100 return "bl %z1+32768@plt";
11102 return "bl %z1@plt";
11104 [(set_attr "type" "branch,branch")
11105 (set_attr "length" "4,8")])
11108 ;; Call to AIX abi function in the same module.
11110 (define_insn "*call_local_aix<mode>"
11111 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11112 (match_operand 1 "" "g"))
11113 (clobber (reg:P LR_REGNO))]
11114 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11116 [(set_attr "type" "branch")
11117 (set_attr "length" "4")])
11119 (define_insn "*call_value_local_aix<mode>"
11120 [(set (match_operand 0 "" "")
11121 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11122 (match_operand 2 "" "g")))
11123 (clobber (reg:P LR_REGNO))]
11124 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11126 [(set_attr "type" "branch")
11127 (set_attr "length" "4")])
11129 ;; Call to AIX abi function which may be in another module.
11130 ;; Restore the TOC pointer (r2) after the call.
11132 (define_insn "*call_nonlocal_aix<mode>"
11133 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11134 (match_operand 1 "" "g"))
11135 (clobber (reg:P LR_REGNO))]
11136 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11138 [(set_attr "type" "branch")
11139 (set_attr "length" "8")])
11141 (define_insn "*call_value_nonlocal_aix<mode>"
11142 [(set (match_operand 0 "" "")
11143 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11144 (match_operand 2 "" "g")))
11145 (clobber (reg:P LR_REGNO))]
11146 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11148 [(set_attr "type" "branch")
11149 (set_attr "length" "8")])
11151 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11152 ;; Operand0 is the addresss of the function to call
11153 ;; Operand2 is the location in the function descriptor to load r2 from
11154 ;; Operand3 is the stack location to hold the current TOC pointer
11156 (define_insn "*call_indirect_aix<mode>"
11157 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11158 (match_operand 1 "" "g,g"))
11159 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11160 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11161 (clobber (reg:P LR_REGNO))]
11162 "DEFAULT_ABI == ABI_AIX"
11163 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11164 [(set_attr "type" "jmpreg")
11165 (set_attr "length" "12")])
11167 (define_insn "*call_value_indirect_aix<mode>"
11168 [(set (match_operand 0 "" "")
11169 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11170 (match_operand 2 "" "g,g")))
11171 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11172 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11173 (clobber (reg:P LR_REGNO))]
11174 "DEFAULT_ABI == ABI_AIX"
11175 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11176 [(set_attr "type" "jmpreg")
11177 (set_attr "length" "12")])
11179 ;; Call to indirect functions with the ELFv2 ABI.
11180 ;; Operand0 is the addresss of the function to call
11181 ;; Operand2 is the stack location to hold the current TOC pointer
11183 (define_insn "*call_indirect_elfv2<mode>"
11184 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11185 (match_operand 1 "" "g,g"))
11186 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11187 (clobber (reg:P LR_REGNO))]
11188 "DEFAULT_ABI == ABI_ELFv2"
11189 "b%T0l\;<ptrload> 2,%2"
11190 [(set_attr "type" "jmpreg")
11191 (set_attr "length" "8")])
11193 (define_insn "*call_value_indirect_elfv2<mode>"
11194 [(set (match_operand 0 "" "")
11195 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11196 (match_operand 2 "" "g,g")))
11197 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11198 (clobber (reg:P LR_REGNO))]
11199 "DEFAULT_ABI == ABI_ELFv2"
11200 "b%T1l\;<ptrload> 2,%3"
11201 [(set_attr "type" "jmpreg")
11202 (set_attr "length" "8")])
11205 ;; Call subroutine returning any type.
11206 (define_expand "untyped_call"
11207 [(parallel [(call (match_operand 0 "" "")
11209 (match_operand 1 "" "")
11210 (match_operand 2 "" "")])]
11216 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11218 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11220 rtx set = XVECEXP (operands[2], 0, i);
11221 emit_move_insn (SET_DEST (set), SET_SRC (set));
11224 /* The optimizer does not know that the call sets the function value
11225 registers we stored in the result block. We avoid problems by
11226 claiming that all hard registers are used and clobbered at this
11228 emit_insn (gen_blockage ());
11233 ;; sibling call patterns
11234 (define_expand "sibcall"
11235 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11236 (match_operand 1 "" ""))
11237 (use (match_operand 2 "" ""))
11238 (use (reg:SI LR_REGNO))
11244 if (MACHOPIC_INDIRECT)
11245 operands[0] = machopic_indirect_call_target (operands[0]);
11248 gcc_assert (GET_CODE (operands[0]) == MEM);
11249 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11251 operands[0] = XEXP (operands[0], 0);
11253 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11255 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11260 (define_expand "sibcall_value"
11261 [(parallel [(set (match_operand 0 "register_operand" "")
11262 (call (mem:SI (match_operand 1 "address_operand" ""))
11263 (match_operand 2 "" "")))
11264 (use (match_operand 3 "" ""))
11265 (use (reg:SI LR_REGNO))
11271 if (MACHOPIC_INDIRECT)
11272 operands[1] = machopic_indirect_call_target (operands[1]);
11275 gcc_assert (GET_CODE (operands[1]) == MEM);
11276 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11278 operands[1] = XEXP (operands[1], 0);
11280 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11282 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11287 ;; this and similar patterns must be marked as using LR, otherwise
11288 ;; dataflow will try to delete the store into it. This is true
11289 ;; even when the actual reg to jump to is in CTR, when LR was
11290 ;; saved and restored around the PIC-setting BCL.
11291 (define_insn "*sibcall_local32"
11292 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11293 (match_operand 1 "" "g,g"))
11294 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11295 (use (reg:SI LR_REGNO))
11297 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11300 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11301 output_asm_insn (\"crxor 6,6,6\", operands);
11303 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11304 output_asm_insn (\"creqv 6,6,6\", operands);
11306 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11308 [(set_attr "type" "branch")
11309 (set_attr "length" "4,8")])
11311 (define_insn "*sibcall_local64"
11312 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11313 (match_operand 1 "" "g,g"))
11314 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11315 (use (reg:SI LR_REGNO))
11317 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11320 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11321 output_asm_insn (\"crxor 6,6,6\", operands);
11323 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11324 output_asm_insn (\"creqv 6,6,6\", operands);
11326 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11328 [(set_attr "type" "branch")
11329 (set_attr "length" "4,8")])
11331 (define_insn "*sibcall_value_local32"
11332 [(set (match_operand 0 "" "")
11333 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11334 (match_operand 2 "" "g,g")))
11335 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11336 (use (reg:SI LR_REGNO))
11338 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11341 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11342 output_asm_insn (\"crxor 6,6,6\", operands);
11344 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11345 output_asm_insn (\"creqv 6,6,6\", operands);
11347 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11349 [(set_attr "type" "branch")
11350 (set_attr "length" "4,8")])
11352 (define_insn "*sibcall_value_local64"
11353 [(set (match_operand 0 "" "")
11354 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11355 (match_operand 2 "" "g,g")))
11356 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11357 (use (reg:SI LR_REGNO))
11359 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11362 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11363 output_asm_insn (\"crxor 6,6,6\", operands);
11365 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11366 output_asm_insn (\"creqv 6,6,6\", operands);
11368 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11370 [(set_attr "type" "branch")
11371 (set_attr "length" "4,8")])
11373 (define_insn "*sibcall_nonlocal_sysv<mode>"
11374 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11375 (match_operand 1 "" ""))
11376 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11377 (use (reg:SI LR_REGNO))
11379 "(DEFAULT_ABI == ABI_DARWIN
11380 || DEFAULT_ABI == ABI_V4)
11381 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11384 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11385 output_asm_insn (\"crxor 6,6,6\", operands);
11387 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11388 output_asm_insn (\"creqv 6,6,6\", operands);
11390 if (which_alternative >= 2)
11392 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11394 gcc_assert (!TARGET_SECURE_PLT);
11395 return \"b %z0@plt\";
11400 [(set_attr "type" "branch")
11401 (set_attr "length" "4,8,4,8")])
11403 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11404 [(set (match_operand 0 "" "")
11405 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11406 (match_operand 2 "" "")))
11407 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11408 (use (reg:SI LR_REGNO))
11410 "(DEFAULT_ABI == ABI_DARWIN
11411 || DEFAULT_ABI == ABI_V4)
11412 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11415 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11416 output_asm_insn (\"crxor 6,6,6\", operands);
11418 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11419 output_asm_insn (\"creqv 6,6,6\", operands);
11421 if (which_alternative >= 2)
11423 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11425 gcc_assert (!TARGET_SECURE_PLT);
11426 return \"b %z1@plt\";
11431 [(set_attr "type" "branch")
11432 (set_attr "length" "4,8,4,8")])
11434 ;; AIX ABI sibling call patterns.
11436 (define_insn "*sibcall_aix<mode>"
11437 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11438 (match_operand 1 "" "g,g"))
11440 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11444 [(set_attr "type" "branch")
11445 (set_attr "length" "4")])
11447 (define_insn "*sibcall_value_aix<mode>"
11448 [(set (match_operand 0 "" "")
11449 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11450 (match_operand 2 "" "g,g")))
11452 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11456 [(set_attr "type" "branch")
11457 (set_attr "length" "4")])
11459 (define_expand "sibcall_epilogue"
11460 [(use (const_int 0))]
11463 if (!TARGET_SCHED_PROLOG)
11464 emit_insn (gen_blockage ());
11465 rs6000_emit_epilogue (TRUE);
11469 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11470 ;; all of memory. This blocks insns from being moved across this point.
11472 (define_insn "blockage"
11473 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11477 (define_expand "probe_stack"
11478 [(set (match_operand 0 "memory_operand" "=m")
11479 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11483 emit_insn (gen_probe_stack_di (operands[0]));
11485 emit_insn (gen_probe_stack_si (operands[0]));
11489 (define_insn "probe_stack_<mode>"
11490 [(set (match_operand:P 0 "memory_operand" "=m")
11491 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11494 operands[1] = gen_rtx_REG (Pmode, 0);
11495 return "st<wd>%U0%X0 %1,%0";
11497 [(set_attr "type" "store")
11498 (set (attr "update")
11499 (if_then_else (match_operand 0 "update_address_mem")
11500 (const_string "yes")
11501 (const_string "no")))
11502 (set (attr "indexed")
11503 (if_then_else (match_operand 0 "indexed_address_mem")
11504 (const_string "yes")
11505 (const_string "no")))
11506 (set_attr "length" "4")])
11508 (define_insn "probe_stack_range<P:mode>"
11509 [(set (match_operand:P 0 "register_operand" "=r")
11510 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11511 (match_operand:P 2 "register_operand" "r")]
11512 UNSPECV_PROBE_STACK_RANGE))]
11514 "* return output_probe_stack_range (operands[0], operands[2]);"
11515 [(set_attr "type" "three")])
11517 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11518 ;; signed & unsigned, and one type of branch.
11520 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11521 ;; insns, and branches.
11523 (define_expand "cbranch<mode>4"
11524 [(use (match_operator 0 "rs6000_cbranch_operator"
11525 [(match_operand:GPR 1 "gpc_reg_operand" "")
11526 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11527 (use (match_operand 3 ""))]
11531 /* Take care of the possibility that operands[2] might be negative but
11532 this might be a logical operation. That insn doesn't exist. */
11533 if (GET_CODE (operands[2]) == CONST_INT
11534 && INTVAL (operands[2]) < 0)
11536 operands[2] = force_reg (<MODE>mode, operands[2]);
11537 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11538 GET_MODE (operands[0]),
11539 operands[1], operands[2]);
11542 rs6000_emit_cbranch (<MODE>mode, operands);
11546 (define_expand "cbranch<mode>4"
11547 [(use (match_operator 0 "rs6000_cbranch_operator"
11548 [(match_operand:FP 1 "gpc_reg_operand" "")
11549 (match_operand:FP 2 "gpc_reg_operand" "")]))
11550 (use (match_operand 3 ""))]
11554 rs6000_emit_cbranch (<MODE>mode, operands);
11558 (define_expand "cstore<mode>4"
11559 [(use (match_operator 1 "rs6000_cbranch_operator"
11560 [(match_operand:GPR 2 "gpc_reg_operand" "")
11561 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11562 (clobber (match_operand:SI 0 "register_operand"))]
11566 /* Take care of the possibility that operands[3] might be negative but
11567 this might be a logical operation. That insn doesn't exist. */
11568 if (GET_CODE (operands[3]) == CONST_INT
11569 && INTVAL (operands[3]) < 0)
11571 operands[3] = force_reg (<MODE>mode, operands[3]);
11572 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11573 GET_MODE (operands[1]),
11574 operands[2], operands[3]);
11577 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11578 For SEQ, likewise, except that comparisons with zero should be done
11579 with an scc insns. However, due to the order that combine see the
11580 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11581 the cases we don't want to handle or are best handled by portable
11583 if (GET_CODE (operands[1]) == NE)
11585 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11586 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11587 && operands[3] == const0_rtx)
11589 rs6000_emit_sCOND (<MODE>mode, operands);
11593 (define_expand "cstore<mode>4"
11594 [(use (match_operator 1 "rs6000_cbranch_operator"
11595 [(match_operand:FP 2 "gpc_reg_operand" "")
11596 (match_operand:FP 3 "gpc_reg_operand" "")]))
11597 (clobber (match_operand:SI 0 "register_operand"))]
11601 rs6000_emit_sCOND (<MODE>mode, operands);
11606 (define_expand "stack_protect_set"
11607 [(match_operand 0 "memory_operand" "")
11608 (match_operand 1 "memory_operand" "")]
11611 #ifdef TARGET_THREAD_SSP_OFFSET
11612 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11613 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11614 operands[1] = gen_rtx_MEM (Pmode, addr);
11617 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11619 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11623 (define_insn "stack_protect_setsi"
11624 [(set (match_operand:SI 0 "memory_operand" "=m")
11625 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11626 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11628 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11629 [(set_attr "type" "three")
11630 (set_attr "length" "12")])
11632 (define_insn "stack_protect_setdi"
11633 [(set (match_operand:DI 0 "memory_operand" "=Y")
11634 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11635 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11637 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11638 [(set_attr "type" "three")
11639 (set_attr "length" "12")])
11641 (define_expand "stack_protect_test"
11642 [(match_operand 0 "memory_operand" "")
11643 (match_operand 1 "memory_operand" "")
11644 (match_operand 2 "" "")]
11647 rtx test, op0, op1;
11648 #ifdef TARGET_THREAD_SSP_OFFSET
11649 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11650 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11651 operands[1] = gen_rtx_MEM (Pmode, addr);
11654 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11655 test = gen_rtx_EQ (VOIDmode, op0, op1);
11656 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11660 (define_insn "stack_protect_testsi"
11661 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11662 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11663 (match_operand:SI 2 "memory_operand" "m,m")]
11665 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11666 (clobber (match_scratch:SI 3 "=&r,&r"))]
11669 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11670 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11671 [(set_attr "length" "16,20")])
11673 (define_insn "stack_protect_testdi"
11674 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11675 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11676 (match_operand:DI 2 "memory_operand" "Y,Y")]
11678 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11679 (clobber (match_scratch:DI 3 "=&r,&r"))]
11682 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11683 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11684 [(set_attr "length" "16,20")])
11687 ;; Here are the actual compare insns.
11688 (define_insn "*cmp<mode>_internal1"
11689 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11690 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11691 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11693 "cmp<wd>%I2 %0,%1,%2"
11694 [(set_attr "type" "cmp")])
11696 ;; If we are comparing a register for equality with a large constant,
11697 ;; we can do this with an XOR followed by a compare. But this is profitable
11698 ;; only if the large constant is only used for the comparison (and in this
11699 ;; case we already have a register to reuse as scratch).
11701 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11702 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11705 [(set (match_operand:SI 0 "register_operand")
11706 (match_operand:SI 1 "logical_const_operand" ""))
11707 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11709 (match_operand:SI 2 "logical_const_operand" "")]))
11710 (set (match_operand:CC 4 "cc_reg_operand" "")
11711 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11714 (if_then_else (match_operator 6 "equality_operator"
11715 [(match_dup 4) (const_int 0)])
11716 (match_operand 7 "" "")
11717 (match_operand 8 "" "")))]
11718 "peep2_reg_dead_p (3, operands[0])
11719 && peep2_reg_dead_p (4, operands[4])"
11720 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11721 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11722 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11725 /* Get the constant we are comparing against, and see what it looks like
11726 when sign-extended from 16 to 32 bits. Then see what constant we could
11727 XOR with SEXTC to get the sign-extended value. */
11728 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11730 operands[1], operands[2]);
11731 HOST_WIDE_INT c = INTVAL (cnst);
11732 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11733 HOST_WIDE_INT xorv = c ^ sextc;
11735 operands[9] = GEN_INT (xorv);
11736 operands[10] = GEN_INT (sextc);
11739 (define_insn "*cmpsi_internal2"
11740 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11741 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11742 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11744 "cmplw%I2 %0,%1,%b2"
11745 [(set_attr "type" "cmp")])
11747 (define_insn "*cmpdi_internal2"
11748 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11749 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11750 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11752 "cmpld%I2 %0,%1,%b2"
11753 [(set_attr "type" "cmp")])
11755 ;; The following two insns don't exist as single insns, but if we provide
11756 ;; them, we can swap an add and compare, which will enable us to overlap more
11757 ;; of the required delay between a compare and branch. We generate code for
11758 ;; them by splitting.
11761 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11762 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11763 (match_operand:SI 2 "short_cint_operand" "i")))
11764 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11765 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11768 [(set_attr "length" "8")])
11771 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11772 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11773 (match_operand:SI 2 "u_short_cint_operand" "i")))
11774 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11775 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11778 [(set_attr "length" "8")])
11781 [(set (match_operand:CC 3 "cc_reg_operand" "")
11782 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11783 (match_operand:SI 2 "short_cint_operand" "")))
11784 (set (match_operand:SI 0 "gpc_reg_operand" "")
11785 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11787 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11788 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11791 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11792 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11793 (match_operand:SI 2 "u_short_cint_operand" "")))
11794 (set (match_operand:SI 0 "gpc_reg_operand" "")
11795 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11797 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11798 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11800 ;; Only need to compare second words if first words equal
11801 (define_insn "*cmptf_internal1"
11802 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11803 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11804 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11805 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11806 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11807 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11808 [(set_attr "type" "fpcompare")
11809 (set_attr "length" "12")])
11811 (define_insn_and_split "*cmptf_internal2"
11812 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11813 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11814 (match_operand:TF 2 "gpc_reg_operand" "d")))
11815 (clobber (match_scratch:DF 3 "=d"))
11816 (clobber (match_scratch:DF 4 "=d"))
11817 (clobber (match_scratch:DF 5 "=d"))
11818 (clobber (match_scratch:DF 6 "=d"))
11819 (clobber (match_scratch:DF 7 "=d"))
11820 (clobber (match_scratch:DF 8 "=d"))
11821 (clobber (match_scratch:DF 9 "=d"))
11822 (clobber (match_scratch:DF 10 "=d"))
11823 (clobber (match_scratch:GPR 11 "=b"))]
11824 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11825 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11827 "&& reload_completed"
11828 [(set (match_dup 3) (match_dup 14))
11829 (set (match_dup 4) (match_dup 15))
11830 (set (match_dup 9) (abs:DF (match_dup 5)))
11831 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11832 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11833 (label_ref (match_dup 12))
11835 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11836 (set (pc) (label_ref (match_dup 13)))
11838 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11839 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11840 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11841 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11844 REAL_VALUE_TYPE rv;
11845 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11846 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11848 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11849 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11850 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11851 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11852 operands[12] = gen_label_rtx ();
11853 operands[13] = gen_label_rtx ();
11855 operands[14] = force_const_mem (DFmode,
11856 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11857 operands[15] = force_const_mem (DFmode,
11858 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11863 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11864 operands[14] = gen_const_mem (DFmode, tocref);
11865 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11866 operands[15] = gen_const_mem (DFmode, tocref);
11867 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11868 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11872 ;; Now we have the scc insns. We can do some combinations because of the
11873 ;; way the machine works.
11875 ;; Note that this is probably faster if we can put an insn between the
11876 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11877 ;; cases the insns below which don't use an intermediate CR field will
11878 ;; be used instead.
11880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11881 (match_operator:SI 1 "scc_comparison_operator"
11882 [(match_operand 2 "cc_reg_operand" "y")
11885 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11886 [(set (attr "type")
11887 (cond [(match_test "TARGET_MFCRF")
11888 (const_string "mfcrf")
11890 (const_string "mfcr")))
11891 (set_attr "length" "8")])
11893 ;; Same as above, but get the GT bit.
11894 (define_insn "move_from_CR_gt_bit"
11895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11896 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11897 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11898 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11899 [(set_attr "type" "mfcr")
11900 (set_attr "length" "8")])
11902 ;; Same as above, but get the OV/ORDERED bit.
11903 (define_insn "move_from_CR_ov_bit"
11904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11905 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11908 "mfcr %0\;rlwinm %0,%0,%t1,1"
11909 [(set_attr "type" "mfcr")
11910 (set_attr "length" "8")])
11913 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11914 (match_operator:DI 1 "scc_comparison_operator"
11915 [(match_operand 2 "cc_reg_operand" "y")
11918 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11919 [(set (attr "type")
11920 (cond [(match_test "TARGET_MFCRF")
11921 (const_string "mfcrf")
11923 (const_string "mfcr")))
11924 (set_attr "length" "8")])
11927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11928 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11929 [(match_operand 2 "cc_reg_operand" "y,y")
11932 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11933 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11936 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11938 [(set_attr "type" "shift")
11939 (set_attr "dot" "yes")
11940 (set_attr "length" "8,16")])
11943 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11944 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11945 [(match_operand 2 "cc_reg_operand" "")
11948 (set (match_operand:SI 3 "gpc_reg_operand" "")
11949 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11950 "TARGET_32BIT && reload_completed"
11951 [(set (match_dup 3)
11952 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11954 (compare:CC (match_dup 3)
11959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11960 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11961 [(match_operand 2 "cc_reg_operand" "y")
11963 (match_operand:SI 3 "const_int_operand" "n")))]
11967 int is_bit = ccr_bit (operands[1], 1);
11968 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11971 if (is_bit >= put_bit)
11972 count = is_bit - put_bit;
11974 count = 32 - (put_bit - is_bit);
11976 operands[4] = GEN_INT (count);
11977 operands[5] = GEN_INT (put_bit);
11979 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11981 [(set (attr "type")
11982 (cond [(match_test "TARGET_MFCRF")
11983 (const_string "mfcrf")
11985 (const_string "mfcr")))
11986 (set_attr "length" "8")])
11989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11991 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11992 [(match_operand 2 "cc_reg_operand" "y,y")
11994 (match_operand:SI 3 "const_int_operand" "n,n"))
11996 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11997 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12002 int is_bit = ccr_bit (operands[1], 1);
12003 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12006 /* Force split for non-cc0 compare. */
12007 if (which_alternative == 1)
12010 if (is_bit >= put_bit)
12011 count = is_bit - put_bit;
12013 count = 32 - (put_bit - is_bit);
12015 operands[5] = GEN_INT (count);
12016 operands[6] = GEN_INT (put_bit);
12018 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12020 [(set_attr "type" "shift")
12021 (set_attr "dot" "yes")
12022 (set_attr "length" "8,16")])
12025 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12027 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12028 [(match_operand 2 "cc_reg_operand" "")
12030 (match_operand:SI 3 "const_int_operand" ""))
12032 (set (match_operand:SI 4 "gpc_reg_operand" "")
12033 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12036 [(set (match_dup 4)
12037 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12040 (compare:CC (match_dup 4)
12044 ;; There is a 3 cycle delay between consecutive mfcr instructions
12045 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12048 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12049 (match_operator:SI 1 "scc_comparison_operator"
12050 [(match_operand 2 "cc_reg_operand" "y")
12052 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12053 (match_operator:SI 4 "scc_comparison_operator"
12054 [(match_operand 5 "cc_reg_operand" "y")
12056 "REGNO (operands[2]) != REGNO (operands[5])"
12057 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12058 [(set_attr "type" "mfcr")
12059 (set_attr "length" "12")])
12062 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12063 (match_operator:DI 1 "scc_comparison_operator"
12064 [(match_operand 2 "cc_reg_operand" "y")
12066 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12067 (match_operator:DI 4 "scc_comparison_operator"
12068 [(match_operand 5 "cc_reg_operand" "y")
12070 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12071 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12072 [(set_attr "type" "mfcr")
12073 (set_attr "length" "12")])
12075 ;; There are some scc insns that can be done directly, without a compare.
12076 ;; These are faster because they don't involve the communications between
12077 ;; the FXU and branch units. In fact, we will be replacing all of the
12078 ;; integer scc insns here or in the portable methods in emit_store_flag.
12080 ;; Also support (neg (scc ..)) since that construct is used to replace
12081 ;; branches, (plus (scc ..) ..) since that construct is common and
12082 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12083 ;; cases where it is no more expensive than (neg (scc ..)).
12085 ;; Have reload force a constant into a register for the simple insns that
12086 ;; otherwise won't accept constants. We do this because it is faster than
12087 ;; the cmp/mfcr sequence we would otherwise generate.
12089 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12092 (define_insn_and_split "*eq<mode>"
12093 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12094 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12095 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12099 [(set (match_dup 0)
12100 (clz:GPR (match_dup 3)))
12102 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12104 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12106 /* Use output operand as intermediate. */
12107 operands[3] = operands[0];
12109 if (logical_operand (operands[2], <MODE>mode))
12110 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12111 gen_rtx_XOR (<MODE>mode,
12112 operands[1], operands[2])));
12114 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12115 gen_rtx_PLUS (<MODE>mode, operands[1],
12116 negate_rtx (<MODE>mode,
12120 operands[3] = operands[1];
12122 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12125 (define_insn_and_split "*eq<mode>_compare"
12126 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12128 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12129 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12131 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12132 (eq:P (match_dup 1) (match_dup 2)))]
12136 [(set (match_dup 0)
12137 (clz:P (match_dup 4)))
12138 (parallel [(set (match_dup 3)
12139 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12142 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12144 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12146 /* Use output operand as intermediate. */
12147 operands[4] = operands[0];
12149 if (logical_operand (operands[2], <MODE>mode))
12150 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12151 gen_rtx_XOR (<MODE>mode,
12152 operands[1], operands[2])));
12154 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12155 gen_rtx_PLUS (<MODE>mode, operands[1],
12156 negate_rtx (<MODE>mode,
12160 operands[4] = operands[1];
12162 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12165 ;; We have insns of the form shown by the first define_insn below. If
12166 ;; there is something inside the comparison operation, we must split it.
12168 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12169 (plus:SI (match_operator 1 "comparison_operator"
12170 [(match_operand:SI 2 "" "")
12171 (match_operand:SI 3
12172 "reg_or_cint_operand" "")])
12173 (match_operand:SI 4 "gpc_reg_operand" "")))
12174 (clobber (match_operand:SI 5 "register_operand" ""))]
12175 "! gpc_reg_operand (operands[2], SImode)"
12176 [(set (match_dup 5) (match_dup 2))
12177 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12180 (define_insn "*plus_eqsi"
12181 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12182 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12183 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12184 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12187 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12188 subfic %0,%1,0\;addze %0,%3
12189 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12190 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12191 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12192 [(set_attr "type" "three,two,three,three,three")
12193 (set_attr "length" "12,8,12,12,12")])
12195 (define_insn "*compare_plus_eqsi"
12196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12199 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12200 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12201 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12203 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12204 "TARGET_32BIT && optimize_size"
12206 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12207 subfic %4,%1,0\;addze. %4,%3
12208 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12209 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12210 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12216 [(set_attr "type" "compare")
12217 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12220 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12223 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12224 (match_operand:SI 2 "scc_eq_operand" ""))
12225 (match_operand:SI 3 "gpc_reg_operand" ""))
12227 (clobber (match_scratch:SI 4 ""))]
12228 "TARGET_32BIT && optimize_size && reload_completed"
12229 [(set (match_dup 4)
12230 (plus:SI (eq:SI (match_dup 1)
12234 (compare:CC (match_dup 4)
12238 (define_insn "*plus_eqsi_compare"
12239 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12242 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12243 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12244 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12246 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12247 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12248 "TARGET_32BIT && optimize_size"
12250 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12251 subfic %0,%1,0\;addze. %0,%3
12252 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12253 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12254 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12260 [(set_attr "type" "compare")
12261 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12264 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12267 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12268 (match_operand:SI 2 "scc_eq_operand" ""))
12269 (match_operand:SI 3 "gpc_reg_operand" ""))
12271 (set (match_operand:SI 0 "gpc_reg_operand" "")
12272 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12273 "TARGET_32BIT && optimize_size && reload_completed"
12274 [(set (match_dup 0)
12275 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12277 (compare:CC (match_dup 0)
12281 (define_insn "*neg_eq0<mode>"
12282 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12283 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12286 "addic %0,%1,-1\;subfe %0,%0,%0"
12287 [(set_attr "type" "two")
12288 (set_attr "length" "8")])
12290 (define_insn_and_split "*neg_eq<mode>"
12291 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12292 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12293 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12297 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12299 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12301 /* Use output operand as intermediate. */
12302 operands[3] = operands[0];
12304 if (logical_operand (operands[2], <MODE>mode))
12305 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12306 gen_rtx_XOR (<MODE>mode,
12307 operands[1], operands[2])));
12309 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12310 gen_rtx_PLUS (<MODE>mode, operands[1],
12311 negate_rtx (<MODE>mode,
12315 operands[3] = operands[1];
12318 (define_insn "*ne0_<mode>"
12319 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12320 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12322 (clobber (match_scratch:P 2 "=&r"))]
12323 "!(TARGET_32BIT && TARGET_ISEL)"
12324 "addic %2,%1,-1\;subfe %0,%2,%1"
12325 [(set_attr "type" "two")
12326 (set_attr "length" "8")])
12328 (define_insn "*plus_ne0_<mode>"
12329 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12330 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12332 (match_operand:P 2 "gpc_reg_operand" "r")))
12333 (clobber (match_scratch:P 3 "=&r"))]
12335 "addic %3,%1,-1\;addze %0,%2"
12336 [(set_attr "type" "two")
12337 (set_attr "length" "8")])
12339 (define_insn "*compare_plus_ne0_<mode>"
12340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12341 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12343 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12345 (clobber (match_scratch:P 3 "=&r,&r"))
12346 (clobber (match_scratch:P 4 "=X,&r"))]
12349 addic %3,%1,-1\;addze. %3,%2
12351 [(set_attr "type" "compare")
12352 (set_attr "length" "8,12")])
12355 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12356 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12358 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12359 (clobber (match_scratch:P 3 ""))
12360 (clobber (match_scratch:P 4 ""))]
12362 [(parallel [(set (match_dup 3)
12363 (plus:P (ne:P (match_dup 1)
12366 (clobber (match_dup 4))])
12368 (compare:CC (match_dup 3)
12373 (define_insn "*compare_plus_ne0_<mode>_1"
12374 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12375 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12377 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12378 (clobber (match_scratch:P 3 "=&r,&r"))
12379 (clobber (match_scratch:P 4 "=X,&r"))]
12382 addic %3,%1,-1\;addze. %3,%2
12384 [(set_attr "type" "compare")
12385 (set_attr "length" "8,12")])
12388 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12389 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12391 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12392 (clobber (match_scratch:P 3 ""))
12393 (clobber (match_scratch:P 4 ""))]
12395 [(parallel [(set (match_dup 3)
12396 (plus:P (ne:P (match_dup 1)
12399 (clobber (match_dup 4))])
12401 (compare:CC (match_dup 3)
12405 (define_insn "*plus_ne0_<mode>_compare"
12406 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12408 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12410 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12412 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12413 (plus:P (ne:P (match_dup 1)
12416 (clobber (match_scratch:P 3 "=&r,&r"))]
12419 addic %3,%1,-1\;addze. %0,%2
12421 [(set_attr "type" "compare")
12422 (set_attr "length" "8,12")])
12425 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12427 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12429 (match_operand:P 2 "gpc_reg_operand" ""))
12431 (set (match_operand:P 0 "gpc_reg_operand" "")
12432 (plus:P (ne:P (match_dup 1)
12435 (clobber (match_scratch:P 3 ""))]
12437 [(parallel [(set (match_dup 0)
12438 (plus:P (ne:P (match_dup 1)
12441 (clobber (match_dup 3))])
12443 (compare:CC (match_dup 0)
12447 (define_insn "*leu<mode>"
12448 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12449 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12450 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12452 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12453 [(set_attr "type" "three")
12454 (set_attr "length" "12")])
12456 (define_insn "*leu<mode>_compare"
12457 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12459 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12460 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12462 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12463 (leu:P (match_dup 1) (match_dup 2)))]
12466 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12468 [(set_attr "type" "compare")
12469 (set_attr "length" "12,16")])
12472 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12474 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12475 (match_operand:P 2 "reg_or_short_operand" ""))
12477 (set (match_operand:P 0 "gpc_reg_operand" "")
12478 (leu:P (match_dup 1) (match_dup 2)))]
12480 [(set (match_dup 0)
12481 (leu:P (match_dup 1) (match_dup 2)))
12483 (compare:CC (match_dup 0)
12487 (define_insn "*plus_leu<mode>"
12488 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12489 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12490 (match_operand:P 2 "reg_or_short_operand" "rI"))
12491 (match_operand:P 3 "gpc_reg_operand" "r")))]
12493 "subf%I2c %0,%1,%2\;addze %0,%3"
12494 [(set_attr "type" "two")
12495 (set_attr "length" "8")])
12498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12500 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12501 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12502 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12504 (clobber (match_scratch:SI 4 "=&r,&r"))]
12507 subf%I2c %4,%1,%2\;addze. %4,%3
12509 [(set_attr "type" "compare")
12510 (set_attr "length" "8,12")])
12513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12515 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12516 (match_operand:SI 2 "reg_or_short_operand" ""))
12517 (match_operand:SI 3 "gpc_reg_operand" ""))
12519 (clobber (match_scratch:SI 4 ""))]
12520 "TARGET_32BIT && reload_completed"
12521 [(set (match_dup 4)
12522 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12525 (compare:CC (match_dup 4)
12530 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12532 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12533 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12534 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12536 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12537 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12540 subf%I2c %0,%1,%2\;addze. %0,%3
12542 [(set_attr "type" "compare")
12543 (set_attr "length" "8,12")])
12546 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12548 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12549 (match_operand:SI 2 "reg_or_short_operand" ""))
12550 (match_operand:SI 3 "gpc_reg_operand" ""))
12552 (set (match_operand:SI 0 "gpc_reg_operand" "")
12553 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12554 "TARGET_32BIT && reload_completed"
12555 [(set (match_dup 0)
12556 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12558 (compare:CC (match_dup 0)
12562 (define_insn "*neg_leu<mode>"
12563 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12564 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12565 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12567 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12568 [(set_attr "type" "three")
12569 (set_attr "length" "12")])
12571 (define_insn "*and_neg_leu<mode>"
12572 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12574 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12575 (match_operand:P 2 "reg_or_short_operand" "rI")))
12576 (match_operand:P 3 "gpc_reg_operand" "r")))]
12578 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12579 [(set_attr "type" "three")
12580 (set_attr "length" "12")])
12583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12586 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12587 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12588 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12590 (clobber (match_scratch:SI 4 "=&r,&r"))]
12593 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12595 [(set_attr "type" "compare")
12596 (set_attr "length" "12,16")])
12599 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12602 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12603 (match_operand:SI 2 "reg_or_short_operand" "")))
12604 (match_operand:SI 3 "gpc_reg_operand" ""))
12606 (clobber (match_scratch:SI 4 ""))]
12607 "TARGET_32BIT && reload_completed"
12608 [(set (match_dup 4)
12609 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12612 (compare:CC (match_dup 4)
12617 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12620 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12621 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12622 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12624 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12625 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12628 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12630 [(set_attr "type" "compare")
12631 (set_attr "length" "12,16")])
12634 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12637 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12638 (match_operand:SI 2 "reg_or_short_operand" "")))
12639 (match_operand:SI 3 "gpc_reg_operand" ""))
12641 (set (match_operand:SI 0 "gpc_reg_operand" "")
12642 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12643 "TARGET_32BIT && reload_completed"
12644 [(set (match_dup 0)
12645 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12648 (compare:CC (match_dup 0)
12652 (define_insn_and_split "*ltu<mode>"
12653 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12654 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12655 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12659 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12660 (set (match_dup 0) (neg:P (match_dup 0)))]
12663 (define_insn_and_split "*ltu<mode>_compare"
12664 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12666 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12667 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12669 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12670 (ltu:P (match_dup 1) (match_dup 2)))]
12674 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12675 (parallel [(set (match_dup 3)
12676 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12677 (set (match_dup 0) (neg:P (match_dup 0)))])]
12680 (define_insn_and_split "*plus_ltu<mode>"
12681 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12682 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12683 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12684 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12687 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12688 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12689 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12692 (define_insn_and_split "*plus_ltu<mode>_1"
12693 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12694 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12695 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12696 (match_operand:P 3 "short_cint_operand" "I,I")))]
12699 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12700 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12701 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
12702 (clobber (reg:P CA_REGNO))])]
12705 (define_insn_and_split "*plus_ltu<mode>_compare"
12706 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12708 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12709 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12710 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12712 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12713 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12716 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12717 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12718 (parallel [(set (match_dup 4)
12719 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12721 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12724 (define_insn "*neg_ltu<mode>"
12725 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12726 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12727 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12730 subfc %0,%2,%1\;subfe %0,%0,%0
12731 addic %0,%1,%n2\;subfe %0,%0,%0"
12732 [(set_attr "type" "two")
12733 (set_attr "length" "8")])
12735 (define_insn "*geu<mode>"
12736 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12737 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12738 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12741 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12742 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12743 [(set_attr "type" "three")
12744 (set_attr "length" "12")])
12746 (define_insn "*geu<mode>_compare"
12747 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12749 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12750 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12752 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12753 (geu:P (match_dup 1) (match_dup 2)))]
12756 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12757 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12760 [(set_attr "type" "compare")
12761 (set_attr "length" "12,12,16,16")])
12764 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12766 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12767 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12769 (set (match_operand:P 0 "gpc_reg_operand" "")
12770 (geu:P (match_dup 1) (match_dup 2)))]
12772 [(set (match_dup 0)
12773 (geu:P (match_dup 1) (match_dup 2)))
12775 (compare:CC (match_dup 0)
12779 (define_insn "*plus_geu<mode>"
12780 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12781 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12782 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12783 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12786 subfc %0,%2,%1\;addze %0,%3
12787 addic %0,%1,%n2\;addze %0,%3"
12788 [(set_attr "type" "two")
12789 (set_attr "length" "8")])
12792 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12794 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12795 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12796 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12798 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12801 subfc %4,%2,%1\;addze. %4,%3
12802 addic %4,%1,%n2\;addze. %4,%3
12805 [(set_attr "type" "compare")
12806 (set_attr "length" "8,8,12,12")])
12809 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12811 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12812 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12813 (match_operand:SI 3 "gpc_reg_operand" ""))
12815 (clobber (match_scratch:SI 4 ""))]
12816 "TARGET_32BIT && reload_completed"
12817 [(set (match_dup 4)
12818 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12821 (compare:CC (match_dup 4)
12826 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12828 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12829 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12830 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12832 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12833 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12836 subfc %0,%2,%1\;addze. %0,%3
12837 addic %0,%1,%n2\;addze. %0,%3
12840 [(set_attr "type" "compare")
12841 (set_attr "length" "8,8,12,12")])
12844 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12846 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12847 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12848 (match_operand:SI 3 "gpc_reg_operand" ""))
12850 (set (match_operand:SI 0 "gpc_reg_operand" "")
12851 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12852 "TARGET_32BIT && reload_completed"
12853 [(set (match_dup 0)
12854 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12856 (compare:CC (match_dup 0)
12860 (define_insn "*neg_geu<mode>"
12861 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12862 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12863 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12866 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12867 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12868 [(set_attr "type" "three")
12869 (set_attr "length" "12")])
12871 (define_insn "*and_neg_geu<mode>"
12872 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12874 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12875 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12876 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12879 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12880 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12881 [(set_attr "type" "three")
12882 (set_attr "length" "12")])
12885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12888 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12889 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12890 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12892 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12895 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12896 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12899 [(set_attr "type" "compare")
12900 (set_attr "length" "12,12,16,16")])
12903 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12906 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12907 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12908 (match_operand:SI 3 "gpc_reg_operand" ""))
12910 (clobber (match_scratch:SI 4 ""))]
12911 "TARGET_32BIT && reload_completed"
12912 [(set (match_dup 4)
12913 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12916 (compare:CC (match_dup 4)
12921 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12924 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12925 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12926 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12928 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12929 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12932 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12933 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12936 [(set_attr "type" "compare")
12937 (set_attr "length" "12,12,16,16")])
12940 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12943 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12944 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12945 (match_operand:SI 3 "gpc_reg_operand" ""))
12947 (set (match_operand:SI 0 "gpc_reg_operand" "")
12948 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12949 "TARGET_32BIT && reload_completed"
12950 [(set (match_dup 0)
12951 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12953 (compare:CC (match_dup 0)
12957 (define_insn "*plus_gt0<mode>"
12958 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12959 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12961 (match_operand:P 2 "gpc_reg_operand" "r")))]
12963 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12964 [(set_attr "type" "three")
12965 (set_attr "length" "12")])
12968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12970 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12972 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12974 (clobber (match_scratch:SI 3 "=&r,&r"))]
12977 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12979 [(set_attr "type" "compare")
12980 (set_attr "length" "12,16")])
12983 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12985 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12987 (match_operand:SI 2 "gpc_reg_operand" ""))
12989 (clobber (match_scratch:SI 3 ""))]
12990 "TARGET_32BIT && reload_completed"
12991 [(set (match_dup 3)
12992 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12995 (compare:CC (match_dup 3)
13000 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13002 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13004 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13006 (clobber (match_scratch:DI 3 "=&r,&r"))]
13009 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13011 [(set_attr "type" "compare")
13012 (set_attr "length" "12,16")])
13015 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13017 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13019 (match_operand:DI 2 "gpc_reg_operand" ""))
13021 (clobber (match_scratch:DI 3 ""))]
13022 "TARGET_64BIT && reload_completed"
13023 [(set (match_dup 3)
13024 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13027 (compare:CC (match_dup 3)
13032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13034 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13036 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13038 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13039 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13042 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13044 [(set_attr "type" "compare")
13045 (set_attr "length" "12,16")])
13048 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13050 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13052 (match_operand:SI 2 "gpc_reg_operand" ""))
13054 (set (match_operand:SI 0 "gpc_reg_operand" "")
13055 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13056 "TARGET_32BIT && reload_completed"
13057 [(set (match_dup 0)
13058 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13060 (compare:CC (match_dup 0)
13065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13067 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13069 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13071 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13072 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13075 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13077 [(set_attr "type" "compare")
13078 (set_attr "length" "12,16")])
13081 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13083 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13085 (match_operand:DI 2 "gpc_reg_operand" ""))
13087 (set (match_operand:DI 0 "gpc_reg_operand" "")
13088 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13089 "TARGET_64BIT && reload_completed"
13090 [(set (match_dup 0)
13091 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13093 (compare:CC (match_dup 0)
13097 (define_insn_and_split "*gtu<mode>"
13098 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13099 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13100 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13104 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13105 (set (match_dup 0) (neg:P (match_dup 0)))]
13108 (define_insn_and_split "*gtu<mode>_compare"
13109 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13111 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13112 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13114 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13115 (gtu:P (match_dup 1) (match_dup 2)))]
13119 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13120 (parallel [(set (match_dup 3)
13121 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13122 (set (match_dup 0) (neg:P (match_dup 0)))])]
13125 (define_insn_and_split "*plus_gtu<mode>"
13126 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13127 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13128 (match_operand:P 2 "reg_or_short_operand" "rI"))
13129 (match_operand:P 3 "gpc_reg_operand" "r")))]
13132 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13133 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13134 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13137 (define_insn_and_split "*plus_gtu<mode>_1"
13138 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13139 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13140 (match_operand:P 2 "reg_or_short_operand" "rI"))
13141 (match_operand:P 3 "short_cint_operand" "I")))]
13144 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13145 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13146 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
13147 (clobber (reg:P CA_REGNO))])]
13150 (define_insn_and_split "*plus_gtu<mode>_compare"
13151 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13153 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13154 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13155 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13157 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13158 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13161 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13162 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13163 (parallel [(set (match_dup 4)
13164 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13166 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13169 (define_insn "*neg_gtu<mode>"
13170 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13171 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13172 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13174 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13175 [(set_attr "type" "two")
13176 (set_attr "length" "8")])
13179 ;; Define both directions of branch and return. If we need a reload
13180 ;; register, we'd rather use CR0 since it is much easier to copy a
13181 ;; register CC value to there.
13185 (if_then_else (match_operator 1 "branch_comparison_operator"
13187 "cc_reg_operand" "y")
13189 (label_ref (match_operand 0 "" ""))
13194 return output_cbranch (operands[1], \"%l0\", 0, insn);
13196 [(set_attr "type" "branch")])
13200 (if_then_else (match_operator 0 "branch_comparison_operator"
13202 "cc_reg_operand" "y")
13209 return output_cbranch (operands[0], NULL, 0, insn);
13211 [(set_attr "type" "jmpreg")
13212 (set_attr "length" "4")])
13216 (if_then_else (match_operator 1 "branch_comparison_operator"
13218 "cc_reg_operand" "y")
13221 (label_ref (match_operand 0 "" ""))))]
13225 return output_cbranch (operands[1], \"%l0\", 1, insn);
13227 [(set_attr "type" "branch")])
13231 (if_then_else (match_operator 0 "branch_comparison_operator"
13233 "cc_reg_operand" "y")
13240 return output_cbranch (operands[0], NULL, 1, insn);
13242 [(set_attr "type" "jmpreg")
13243 (set_attr "length" "4")])
13245 ;; Logic on condition register values.
13247 ; This pattern matches things like
13248 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13249 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13251 ; which are generated by the branch logic.
13252 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13254 (define_insn "*cceq_ior_compare"
13255 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13256 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13257 [(match_operator:SI 2
13258 "branch_positive_comparison_operator"
13260 "cc_reg_operand" "y,y")
13262 (match_operator:SI 4
13263 "branch_positive_comparison_operator"
13265 "cc_reg_operand" "0,y")
13269 "cr%q1 %E0,%j2,%j4"
13270 [(set_attr "type" "cr_logical,delayed_cr")])
13272 ; Why is the constant -1 here, but 1 in the previous pattern?
13273 ; Because ~1 has all but the low bit set.
13275 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13276 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13277 [(not:SI (match_operator:SI 2
13278 "branch_positive_comparison_operator"
13280 "cc_reg_operand" "y,y")
13282 (match_operator:SI 4
13283 "branch_positive_comparison_operator"
13285 "cc_reg_operand" "0,y")
13289 "cr%q1 %E0,%j2,%j4"
13290 [(set_attr "type" "cr_logical,delayed_cr")])
13292 (define_insn "*cceq_rev_compare"
13293 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13294 (compare:CCEQ (match_operator:SI 1
13295 "branch_positive_comparison_operator"
13297 "cc_reg_operand" "0,y")
13302 [(set_attr "type" "cr_logical,delayed_cr")])
13304 ;; If we are comparing the result of two comparisons, this can be done
13305 ;; using creqv or crxor.
13307 (define_insn_and_split ""
13308 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13309 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13310 [(match_operand 2 "cc_reg_operand" "y")
13312 (match_operator 3 "branch_comparison_operator"
13313 [(match_operand 4 "cc_reg_operand" "y")
13318 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13322 int positive_1, positive_2;
13324 positive_1 = branch_positive_comparison_operator (operands[1],
13325 GET_MODE (operands[1]));
13326 positive_2 = branch_positive_comparison_operator (operands[3],
13327 GET_MODE (operands[3]));
13330 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13331 GET_CODE (operands[1])),
13333 operands[2], const0_rtx);
13334 else if (GET_MODE (operands[1]) != SImode)
13335 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13336 operands[2], const0_rtx);
13339 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13340 GET_CODE (operands[3])),
13342 operands[4], const0_rtx);
13343 else if (GET_MODE (operands[3]) != SImode)
13344 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13345 operands[4], const0_rtx);
13347 if (positive_1 == positive_2)
13349 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13350 operands[5] = constm1_rtx;
13354 operands[5] = const1_rtx;
13358 ;; Unconditional branch and return.
13360 (define_insn "jump"
13362 (label_ref (match_operand 0 "" "")))]
13365 [(set_attr "type" "branch")])
13367 (define_insn "<return_str>return"
13371 [(set_attr "type" "jmpreg")])
13373 (define_expand "indirect_jump"
13374 [(set (pc) (match_operand 0 "register_operand" ""))])
13376 (define_insn "*indirect_jump<mode>"
13377 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13382 [(set_attr "type" "jmpreg")])
13384 ;; Table jump for switch statements:
13385 (define_expand "tablejump"
13386 [(use (match_operand 0 "" ""))
13387 (use (label_ref (match_operand 1 "" "")))]
13392 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13394 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13398 (define_expand "tablejumpsi"
13399 [(set (match_dup 3)
13400 (plus:SI (match_operand:SI 0 "" "")
13402 (parallel [(set (pc) (match_dup 3))
13403 (use (label_ref (match_operand 1 "" "")))])]
13406 { operands[0] = force_reg (SImode, operands[0]);
13407 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13408 operands[3] = gen_reg_rtx (SImode);
13411 (define_expand "tablejumpdi"
13412 [(set (match_dup 4)
13413 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13415 (plus:DI (match_dup 4)
13417 (parallel [(set (pc) (match_dup 3))
13418 (use (label_ref (match_operand 1 "" "")))])]
13421 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13422 operands[3] = gen_reg_rtx (DImode);
13423 operands[4] = gen_reg_rtx (DImode);
13426 (define_insn "*tablejump<mode>_internal1"
13428 (match_operand:P 0 "register_operand" "c,*l"))
13429 (use (label_ref (match_operand 1 "" "")))]
13434 [(set_attr "type" "jmpreg")])
13441 (define_insn "group_ending_nop"
13442 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13446 if (rs6000_cpu_attr == CPU_POWER6)
13447 return \"ori 1,1,0\";
13448 return \"ori 2,2,0\";
13451 ;; Define the subtract-one-and-jump insns, starting with the template
13452 ;; so loop.c knows what to generate.
13454 (define_expand "doloop_end"
13455 [(use (match_operand 0 "" "")) ; loop pseudo
13456 (use (match_operand 1 "" ""))] ; label
13462 if (GET_MODE (operands[0]) != DImode)
13464 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
13468 if (GET_MODE (operands[0]) != SImode)
13470 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
13475 (define_expand "ctr<mode>"
13476 [(parallel [(set (pc)
13477 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13479 (label_ref (match_operand 1 "" ""))
13482 (plus:P (match_dup 0)
13484 (clobber (match_scratch:CC 2 ""))
13485 (clobber (match_scratch:P 3 ""))])]
13489 ;; We need to be able to do this for any operand, including MEM, or we
13490 ;; will cause reload to blow up since we don't allow output reloads on
13492 ;; For the length attribute to be calculated correctly, the
13493 ;; label MUST be operand 0.
13495 (define_insn "*ctr<mode>_internal1"
13497 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13499 (label_ref (match_operand 0 "" ""))
13501 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13502 (plus:P (match_dup 1)
13504 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13505 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13509 if (which_alternative != 0)
13511 else if (get_attr_length (insn) == 4)
13512 return \"bdnz %l0\";
13514 return \"bdz $+8\;b %l0\";
13516 [(set_attr "type" "branch")
13517 (set_attr "length" "*,12,16,16")])
13519 (define_insn "*ctr<mode>_internal2"
13521 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13524 (label_ref (match_operand 0 "" ""))))
13525 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13526 (plus:P (match_dup 1)
13528 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13529 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13533 if (which_alternative != 0)
13535 else if (get_attr_length (insn) == 4)
13536 return \"bdz %l0\";
13538 return \"bdnz $+8\;b %l0\";
13540 [(set_attr "type" "branch")
13541 (set_attr "length" "*,12,16,16")])
13543 ;; Similar but use EQ
13545 (define_insn "*ctr<mode>_internal5"
13547 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13549 (label_ref (match_operand 0 "" ""))
13551 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13552 (plus:P (match_dup 1)
13554 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13555 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13559 if (which_alternative != 0)
13561 else if (get_attr_length (insn) == 4)
13562 return \"bdz %l0\";
13564 return \"bdnz $+8\;b %l0\";
13566 [(set_attr "type" "branch")
13567 (set_attr "length" "*,12,16,16")])
13569 (define_insn "*ctr<mode>_internal6"
13571 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13574 (label_ref (match_operand 0 "" ""))))
13575 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13576 (plus:P (match_dup 1)
13578 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13579 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13583 if (which_alternative != 0)
13585 else if (get_attr_length (insn) == 4)
13586 return \"bdnz %l0\";
13588 return \"bdz $+8\;b %l0\";
13590 [(set_attr "type" "branch")
13591 (set_attr "length" "*,12,16,16")])
13593 ;; Now the splitters if we could not allocate the CTR register
13597 (if_then_else (match_operator 2 "comparison_operator"
13598 [(match_operand:P 1 "gpc_reg_operand" "")
13600 (match_operand 5 "" "")
13601 (match_operand 6 "" "")))
13602 (set (match_operand:P 0 "gpc_reg_operand" "")
13603 (plus:P (match_dup 1) (const_int -1)))
13604 (clobber (match_scratch:CC 3 ""))
13605 (clobber (match_scratch:P 4 ""))]
13607 [(parallel [(set (match_dup 3)
13608 (compare:CC (plus:P (match_dup 1)
13612 (plus:P (match_dup 1)
13614 (set (pc) (if_then_else (match_dup 7)
13618 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13619 operands[3], const0_rtx); }")
13623 (if_then_else (match_operator 2 "comparison_operator"
13624 [(match_operand:P 1 "gpc_reg_operand" "")
13626 (match_operand 5 "" "")
13627 (match_operand 6 "" "")))
13628 (set (match_operand:P 0 "nonimmediate_operand" "")
13629 (plus:P (match_dup 1) (const_int -1)))
13630 (clobber (match_scratch:CC 3 ""))
13631 (clobber (match_scratch:P 4 ""))]
13632 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13633 [(parallel [(set (match_dup 3)
13634 (compare:CC (plus:P (match_dup 1)
13638 (plus:P (match_dup 1)
13642 (set (pc) (if_then_else (match_dup 7)
13646 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13647 operands[3], const0_rtx); }")
13649 (define_insn "trap"
13650 [(trap_if (const_int 1) (const_int 0))]
13653 [(set_attr "type" "trap")])
13655 (define_expand "ctrap<mode>4"
13656 [(trap_if (match_operator 0 "ordered_comparison_operator"
13657 [(match_operand:GPR 1 "register_operand")
13658 (match_operand:GPR 2 "reg_or_short_operand")])
13659 (match_operand 3 "zero_constant" ""))]
13664 [(trap_if (match_operator 0 "ordered_comparison_operator"
13665 [(match_operand:GPR 1 "register_operand" "r")
13666 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13669 "t<wd>%V0%I2 %1,%2"
13670 [(set_attr "type" "trap")])
13672 ;; Insns related to generating the function prologue and epilogue.
13674 (define_expand "prologue"
13675 [(use (const_int 0))]
13678 rs6000_emit_prologue ();
13679 if (!TARGET_SCHED_PROLOG)
13680 emit_insn (gen_blockage ());
13684 (define_insn "*movesi_from_cr_one"
13685 [(match_parallel 0 "mfcr_operation"
13686 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13687 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13688 (match_operand 3 "immediate_operand" "n")]
13689 UNSPEC_MOVESI_FROM_CR))])]
13695 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13697 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13698 operands[4] = GEN_INT (mask);
13699 output_asm_insn (\"mfcr %1,%4\", operands);
13703 [(set_attr "type" "mfcrf")])
13705 (define_insn "movesi_from_cr"
13706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13707 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13708 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13709 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13710 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13711 UNSPEC_MOVESI_FROM_CR))]
13714 [(set_attr "type" "mfcr")])
13716 (define_insn "*crsave"
13717 [(match_parallel 0 "crsave_operation"
13718 [(set (match_operand:SI 1 "memory_operand" "=m")
13719 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13722 [(set_attr "type" "store")])
13724 (define_insn "*stmw"
13725 [(match_parallel 0 "stmw_operation"
13726 [(set (match_operand:SI 1 "memory_operand" "=m")
13727 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13730 [(set_attr "type" "store")
13731 (set_attr "update" "yes")
13732 (set_attr "indexed" "yes")])
13734 ; The following comment applies to:
13738 ; return_and_restore_gpregs*
13739 ; return_and_restore_fpregs*
13740 ; return_and_restore_fpregs_aix*
13742 ; The out-of-line save / restore functions expects one input argument.
13743 ; Since those are not standard call_insn's, we must avoid using
13744 ; MATCH_OPERAND for that argument. That way the register rename
13745 ; optimization will not try to rename this register.
13746 ; Each pattern is repeated for each possible register number used in
13747 ; various ABIs (r11, r1, and for some functions r12)
13749 (define_insn "*save_gpregs_<mode>_r11"
13750 [(match_parallel 0 "any_parallel_operand"
13751 [(clobber (reg:P 65))
13752 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13754 (set (match_operand:P 2 "memory_operand" "=m")
13755 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13758 [(set_attr "type" "branch")
13759 (set_attr "length" "4")])
13761 (define_insn "*save_gpregs_<mode>_r12"
13762 [(match_parallel 0 "any_parallel_operand"
13763 [(clobber (reg:P 65))
13764 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13766 (set (match_operand:P 2 "memory_operand" "=m")
13767 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13770 [(set_attr "type" "branch")
13771 (set_attr "length" "4")])
13773 (define_insn "*save_gpregs_<mode>_r1"
13774 [(match_parallel 0 "any_parallel_operand"
13775 [(clobber (reg:P 65))
13776 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13778 (set (match_operand:P 2 "memory_operand" "=m")
13779 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13782 [(set_attr "type" "branch")
13783 (set_attr "length" "4")])
13785 (define_insn "*save_fpregs_<mode>_r11"
13786 [(match_parallel 0 "any_parallel_operand"
13787 [(clobber (reg:P 65))
13788 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13790 (set (match_operand:DF 2 "memory_operand" "=m")
13791 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13794 [(set_attr "type" "branch")
13795 (set_attr "length" "4")])
13797 (define_insn "*save_fpregs_<mode>_r12"
13798 [(match_parallel 0 "any_parallel_operand"
13799 [(clobber (reg:P 65))
13800 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13802 (set (match_operand:DF 2 "memory_operand" "=m")
13803 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13806 [(set_attr "type" "branch")
13807 (set_attr "length" "4")])
13809 (define_insn "*save_fpregs_<mode>_r1"
13810 [(match_parallel 0 "any_parallel_operand"
13811 [(clobber (reg:P 65))
13812 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13814 (set (match_operand:DF 2 "memory_operand" "=m")
13815 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13818 [(set_attr "type" "branch")
13819 (set_attr "length" "4")])
13821 ; This is to explain that changes to the stack pointer should
13822 ; not be moved over loads from or stores to stack memory.
13823 (define_insn "stack_tie"
13824 [(match_parallel 0 "tie_operand"
13825 [(set (mem:BLK (reg 1)) (const_int 0))])]
13828 [(set_attr "length" "0")])
13830 (define_expand "epilogue"
13831 [(use (const_int 0))]
13834 if (!TARGET_SCHED_PROLOG)
13835 emit_insn (gen_blockage ());
13836 rs6000_emit_epilogue (FALSE);
13840 ; On some processors, doing the mtcrf one CC register at a time is
13841 ; faster (like on the 604e). On others, doing them all at once is
13842 ; faster; for instance, on the 601 and 750.
13844 (define_expand "movsi_to_cr_one"
13845 [(set (match_operand:CC 0 "cc_reg_operand" "")
13846 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13847 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13849 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13851 (define_insn "*movsi_to_cr"
13852 [(match_parallel 0 "mtcrf_operation"
13853 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13854 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13855 (match_operand 3 "immediate_operand" "n")]
13856 UNSPEC_MOVESI_TO_CR))])]
13862 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13863 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13864 operands[4] = GEN_INT (mask);
13865 return \"mtcrf %4,%2\";
13867 [(set_attr "type" "mtcr")])
13869 (define_insn "*mtcrfsi"
13870 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13871 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13872 (match_operand 2 "immediate_operand" "n")]
13873 UNSPEC_MOVESI_TO_CR))]
13874 "GET_CODE (operands[0]) == REG
13875 && CR_REGNO_P (REGNO (operands[0]))
13876 && GET_CODE (operands[2]) == CONST_INT
13877 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13879 [(set_attr "type" "mtcr")])
13881 ; The load-multiple instructions have similar properties.
13882 ; Note that "load_multiple" is a name known to the machine-independent
13883 ; code that actually corresponds to the PowerPC load-string.
13885 (define_insn "*lmw"
13886 [(match_parallel 0 "lmw_operation"
13887 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13888 (match_operand:SI 2 "memory_operand" "m"))])]
13891 [(set_attr "type" "load")
13892 (set_attr "update" "yes")
13893 (set_attr "indexed" "yes")
13894 (set_attr "cell_micro" "always")])
13896 (define_insn "*return_internal_<mode>"
13898 (use (match_operand:P 0 "register_operand" "lc"))]
13901 [(set_attr "type" "jmpreg")])
13903 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13904 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13906 ; The following comment applies to:
13910 ; return_and_restore_gpregs*
13911 ; return_and_restore_fpregs*
13912 ; return_and_restore_fpregs_aix*
13914 ; The out-of-line save / restore functions expects one input argument.
13915 ; Since those are not standard call_insn's, we must avoid using
13916 ; MATCH_OPERAND for that argument. That way the register rename
13917 ; optimization will not try to rename this register.
13918 ; Each pattern is repeated for each possible register number used in
13919 ; various ABIs (r11, r1, and for some functions r12)
13921 (define_insn "*restore_gpregs_<mode>_r11"
13922 [(match_parallel 0 "any_parallel_operand"
13923 [(clobber (match_operand:P 1 "register_operand" "=l"))
13924 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13926 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13927 (match_operand:P 4 "memory_operand" "m"))])]
13930 [(set_attr "type" "branch")
13931 (set_attr "length" "4")])
13933 (define_insn "*restore_gpregs_<mode>_r12"
13934 [(match_parallel 0 "any_parallel_operand"
13935 [(clobber (match_operand:P 1 "register_operand" "=l"))
13936 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13938 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13939 (match_operand:P 4 "memory_operand" "m"))])]
13942 [(set_attr "type" "branch")
13943 (set_attr "length" "4")])
13945 (define_insn "*restore_gpregs_<mode>_r1"
13946 [(match_parallel 0 "any_parallel_operand"
13947 [(clobber (match_operand:P 1 "register_operand" "=l"))
13948 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13950 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13951 (match_operand:P 4 "memory_operand" "m"))])]
13954 [(set_attr "type" "branch")
13955 (set_attr "length" "4")])
13957 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13958 [(match_parallel 0 "any_parallel_operand"
13960 (clobber (match_operand:P 1 "register_operand" "=l"))
13961 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13963 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13964 (match_operand:P 4 "memory_operand" "m"))])]
13967 [(set_attr "type" "branch")
13968 (set_attr "length" "4")])
13970 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13971 [(match_parallel 0 "any_parallel_operand"
13973 (clobber (match_operand:P 1 "register_operand" "=l"))
13974 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13976 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13977 (match_operand:P 4 "memory_operand" "m"))])]
13980 [(set_attr "type" "branch")
13981 (set_attr "length" "4")])
13983 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13984 [(match_parallel 0 "any_parallel_operand"
13986 (clobber (match_operand:P 1 "register_operand" "=l"))
13987 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13989 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13990 (match_operand:P 4 "memory_operand" "m"))])]
13993 [(set_attr "type" "branch")
13994 (set_attr "length" "4")])
13996 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13997 [(match_parallel 0 "any_parallel_operand"
13999 (clobber (match_operand:P 1 "register_operand" "=l"))
14000 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14002 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14003 (match_operand:DF 4 "memory_operand" "m"))])]
14006 [(set_attr "type" "branch")
14007 (set_attr "length" "4")])
14009 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14010 [(match_parallel 0 "any_parallel_operand"
14012 (clobber (match_operand:P 1 "register_operand" "=l"))
14013 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14015 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14016 (match_operand:DF 4 "memory_operand" "m"))])]
14019 [(set_attr "type" "branch")
14020 (set_attr "length" "4")])
14022 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14023 [(match_parallel 0 "any_parallel_operand"
14025 (clobber (match_operand:P 1 "register_operand" "=l"))
14026 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14028 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14029 (match_operand:DF 4 "memory_operand" "m"))])]
14032 [(set_attr "type" "branch")
14033 (set_attr "length" "4")])
14035 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14036 [(match_parallel 0 "any_parallel_operand"
14038 (use (match_operand:P 1 "register_operand" "l"))
14039 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14041 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14042 (match_operand:DF 4 "memory_operand" "m"))])]
14045 [(set_attr "type" "branch")
14046 (set_attr "length" "4")])
14048 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14049 [(match_parallel 0 "any_parallel_operand"
14051 (use (match_operand:P 1 "register_operand" "l"))
14052 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14054 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14055 (match_operand:DF 4 "memory_operand" "m"))])]
14058 [(set_attr "type" "branch")
14059 (set_attr "length" "4")])
14061 ; This is used in compiling the unwind routines.
14062 (define_expand "eh_return"
14063 [(use (match_operand 0 "general_operand" ""))]
14068 emit_insn (gen_eh_set_lr_si (operands[0]));
14070 emit_insn (gen_eh_set_lr_di (operands[0]));
14074 ; We can't expand this before we know where the link register is stored.
14075 (define_insn "eh_set_lr_<mode>"
14076 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14078 (clobber (match_scratch:P 1 "=&b"))]
14083 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14084 (clobber (match_scratch 1 ""))]
14089 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14093 (define_insn "prefetch"
14094 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14095 (match_operand:SI 1 "const_int_operand" "n")
14096 (match_operand:SI 2 "const_int_operand" "n"))]
14100 if (GET_CODE (operands[0]) == REG)
14101 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14102 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14104 [(set_attr "type" "load")])
14106 (define_insn "bpermd_<mode>"
14107 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14108 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14109 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14112 [(set_attr "type" "popcnt")])
14115 ;; Builtin fma support. Handle
14116 ;; Note that the conditions for expansion are in the FMA_F iterator.
14118 (define_expand "fma<mode>4"
14119 [(set (match_operand:FMA_F 0 "register_operand" "")
14121 (match_operand:FMA_F 1 "register_operand" "")
14122 (match_operand:FMA_F 2 "register_operand" "")
14123 (match_operand:FMA_F 3 "register_operand" "")))]
14127 (define_insn "*fma<mode>4_fpr"
14128 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14130 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14131 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14132 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14133 "TARGET_<MODE>_FPR"
14135 fmadd<Ftrad> %0,%1,%2,%3
14136 xsmadda<Fvsx> %x0,%x1,%x2
14137 xsmaddm<Fvsx> %x0,%x1,%x3"
14138 [(set_attr "type" "fp")
14139 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14141 ; Altivec only has fma and nfms.
14142 (define_expand "fms<mode>4"
14143 [(set (match_operand:FMA_F 0 "register_operand" "")
14145 (match_operand:FMA_F 1 "register_operand" "")
14146 (match_operand:FMA_F 2 "register_operand" "")
14147 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14148 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14151 (define_insn "*fms<mode>4_fpr"
14152 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14154 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14155 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14156 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14157 "TARGET_<MODE>_FPR"
14159 fmsub<Ftrad> %0,%1,%2,%3
14160 xsmsuba<Fvsx> %x0,%x1,%x2
14161 xsmsubm<Fvsx> %x0,%x1,%x3"
14162 [(set_attr "type" "fp")
14163 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14165 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14166 (define_expand "fnma<mode>4"
14167 [(set (match_operand:FMA_F 0 "register_operand" "")
14170 (match_operand:FMA_F 1 "register_operand" "")
14171 (match_operand:FMA_F 2 "register_operand" "")
14172 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14173 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14176 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14177 (define_expand "fnms<mode>4"
14178 [(set (match_operand:FMA_F 0 "register_operand" "")
14181 (match_operand:FMA_F 1 "register_operand" "")
14182 (match_operand:FMA_F 2 "register_operand" "")
14183 (match_operand:FMA_F 3 "register_operand" ""))))]
14184 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14187 ; Not an official optab name, but used from builtins.
14188 (define_expand "nfma<mode>4"
14189 [(set (match_operand:FMA_F 0 "register_operand" "")
14192 (match_operand:FMA_F 1 "register_operand" "")
14193 (match_operand:FMA_F 2 "register_operand" "")
14194 (match_operand:FMA_F 3 "register_operand" ""))))]
14195 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14198 (define_insn "*nfma<mode>4_fpr"
14199 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14202 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14203 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14204 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14205 "TARGET_<MODE>_FPR"
14207 fnmadd<Ftrad> %0,%1,%2,%3
14208 xsnmadda<Fvsx> %x0,%x1,%x2
14209 xsnmaddm<Fvsx> %x0,%x1,%x3"
14210 [(set_attr "type" "fp")
14211 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14213 ; Not an official optab name, but used from builtins.
14214 (define_expand "nfms<mode>4"
14215 [(set (match_operand:FMA_F 0 "register_operand" "")
14218 (match_operand:FMA_F 1 "register_operand" "")
14219 (match_operand:FMA_F 2 "register_operand" "")
14220 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14224 (define_insn "*nfmssf4_fpr"
14225 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14228 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14229 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14231 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14232 "TARGET_<MODE>_FPR"
14234 fnmsub<Ftrad> %0,%1,%2,%3
14235 xsnmsuba<Fvsx> %x0,%x1,%x2
14236 xsnmsubm<Fvsx> %x0,%x1,%x3"
14237 [(set_attr "type" "fp")
14238 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14241 (define_expand "rs6000_get_timebase"
14242 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14245 if (TARGET_POWERPC64)
14246 emit_insn (gen_rs6000_mftb_di (operands[0]));
14248 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14252 (define_insn "rs6000_get_timebase_ppc32"
14253 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14254 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14255 (clobber (match_scratch:SI 1 "=r"))
14256 (clobber (match_scratch:CC 2 "=y"))]
14257 "!TARGET_POWERPC64"
14259 if (WORDS_BIG_ENDIAN)
14262 return "mfspr %0,269\;"
14270 return "mftbu %0\;"
14279 return "mfspr %L0,269\;"
14287 return "mftbu %L0\;"
14294 [(set_attr "length" "20")])
14296 (define_insn "rs6000_mftb_<mode>"
14297 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
14298 (unspec_volatile:GPR [(const_int 0)] UNSPECV_MFTB))]
14302 return "mfspr %0,268";
14308 (define_insn "rs6000_mffs"
14309 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
14310 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
14311 "TARGET_HARD_FLOAT && TARGET_FPRS"
14314 (define_insn "rs6000_mtfsf"
14315 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
14316 (match_operand:DF 1 "gpc_reg_operand" "d")]
14318 "TARGET_HARD_FLOAT && TARGET_FPRS"
14322 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14323 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14324 ;; register that is being loaded. The fused ops must be physically adjacent.
14326 ;; Find cases where the addis that feeds into a load instruction is either used
14327 ;; once or is the same as the target register, and replace it with the fusion
14331 [(set (match_operand:P 0 "base_reg_operand" "")
14332 (match_operand:P 1 "fusion_gpr_addis" ""))
14333 (set (match_operand:INT1 2 "base_reg_operand" "")
14334 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14336 && fusion_gpr_load_p (operands[0], operands[1], operands[2],
14340 expand_fusion_gpr_load (operands);
14344 ;; Fusion insn, created by the define_peephole2 above (and eventually by
14347 (define_insn "fusion_gpr_load_<mode>"
14348 [(set (match_operand:INT1 0 "base_reg_operand" "=&b")
14349 (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")]
14350 UNSPEC_FUSION_GPR))]
14353 return emit_fusion_gpr_load (operands[0], operands[1]);
14355 [(set_attr "type" "load")
14356 (set_attr "length" "8")])
14359 ;; Miscellaneous ISA 2.06 (power7) instructions
14360 (define_insn "addg6s"
14361 [(set (match_operand:SI 0 "register_operand" "=r")
14362 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
14363 (match_operand:SI 2 "register_operand" "r")]
14367 [(set_attr "type" "integer")
14368 (set_attr "length" "4")])
14370 (define_insn "cdtbcd"
14371 [(set (match_operand:SI 0 "register_operand" "=r")
14372 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14376 [(set_attr "type" "integer")
14377 (set_attr "length" "4")])
14379 (define_insn "cbcdtd"
14380 [(set (match_operand:SI 0 "register_operand" "=r")
14381 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14385 [(set_attr "type" "integer")
14386 (set_attr "length" "4")])
14388 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14393 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14394 (UNSPEC_DIVEO "eo")
14395 (UNSPEC_DIVEU "eu")
14396 (UNSPEC_DIVEUO "euo")])
14398 (define_insn "div<div_extend>_<mode>"
14399 [(set (match_operand:GPR 0 "register_operand" "=r")
14400 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
14401 (match_operand:GPR 2 "register_operand" "r")]
14402 UNSPEC_DIV_EXTEND))]
14404 "div<wd><div_extend> %0,%1,%2"
14405 [(set_attr "type" "div")
14406 (set_attr "size" "<bits>")])
14409 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
14411 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
14412 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
14414 (define_expand "unpack<mode>"
14415 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
14417 [(match_operand:FMOVE128 1 "register_operand" "")
14418 (match_operand:QI 2 "const_0_to_1_operand" "")]
14419 UNSPEC_UNPACK_128BIT))]
14423 (define_insn_and_split "unpack<mode>_dm"
14424 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
14426 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
14427 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
14428 UNSPEC_UNPACK_128BIT))]
14429 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
14431 "&& reload_completed"
14432 [(set (match_dup 0) (match_dup 3))]
14434 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14436 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14438 emit_note (NOTE_INSN_DELETED);
14442 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14444 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
14445 (set_attr "length" "4")])
14447 (define_insn_and_split "unpack<mode>_nodm"
14448 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
14450 [(match_operand:FMOVE128 1 "register_operand" "d,d")
14451 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
14452 UNSPEC_UNPACK_128BIT))]
14453 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
14455 "&& reload_completed"
14456 [(set (match_dup 0) (match_dup 3))]
14458 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14460 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14462 emit_note (NOTE_INSN_DELETED);
14466 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14468 [(set_attr "type" "fp,fpstore")
14469 (set_attr "length" "4")])
14471 (define_insn_and_split "pack<mode>"
14472 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
14474 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
14475 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
14476 UNSPEC_PACK_128BIT))]
14481 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
14482 [(set (match_dup 3) (match_dup 1))
14483 (set (match_dup 4) (match_dup 2))]
14485 unsigned dest_hi = REGNO (operands[0]);
14486 unsigned dest_lo = dest_hi + 1;
14488 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
14489 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
14491 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14492 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14494 [(set_attr "type" "fp,fp")
14495 (set_attr "length" "4,8")])
14497 (define_insn "unpackv1ti"
14498 [(set (match_operand:DI 0 "register_operand" "=d,d")
14499 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
14500 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
14501 UNSPEC_UNPACK_128BIT))]
14504 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
14505 return ASM_COMMENT_START " xxpermdi to same register";
14507 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
14508 return "xxpermdi %x0,%x1,%x1,%3";
14510 [(set_attr "type" "vecperm")
14511 (set_attr "length" "4")])
14513 (define_insn "packv1ti"
14514 [(set (match_operand:V1TI 0 "register_operand" "=wa")
14516 [(match_operand:DI 1 "register_operand" "d")
14517 (match_operand:DI 2 "register_operand" "d")]
14518 UNSPEC_PACK_128BIT))]
14520 "xxpermdi %x0,%x1,%x2,0"
14521 [(set_attr "type" "vecperm")
14522 (set_attr "length" "4")])
14526 (include "sync.md")
14527 (include "vector.md")
14529 (include "altivec.md")
14532 (include "paired.md")
14533 (include "crypto.md")