PR inline-asm/84742
[official-gcc.git] / gcc / testsuite / gcc.target / i386 / sse4_2-pcmpistrm-1.c
blobb8ec890cbd48c77dee14a2046ee1deeda6ae0c33
1 /* { dg-do run } */
2 /* { dg-require-effective-target sse4 } */
3 /* { dg-options "-O2 -msse4.2" } */
5 #ifndef CHECK_H
6 #define CHECK_H "sse4_2-check.h"
7 #endif
9 #ifndef TEST
10 #define TEST sse4_2_test
11 #endif
13 #include CHECK_H
15 #include "sse4_2-pcmpstr.h"
17 #define NUM 1024
19 #define IMM_VAL0 \
20 (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
21 #define IMM_VAL1 \
22 (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
23 | _SIDD_BIT_MASK)
24 #define IMM_VAL2 \
25 (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
26 #define IMM_VAL3 \
27 (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
28 | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK)
31 static void
32 TEST (void)
34 union
36 __m128i x[NUM];
37 char c[NUM *16];
38 } src1, src2;
39 __m128i res, correct;
40 int i;
42 for (i = 0; i < NUM *16; i++)
44 src1.c[i] = rand ();
45 src2.c[i] = rand ();
48 for (i = 0; i < NUM; i++)
50 switch((rand() % 4))
52 case 0:
53 res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL0);
54 correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL0, NULL);
55 break;
57 case 1:
58 res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL1);
59 correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL1, NULL);
60 break;
62 case 2:
63 res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL2);
64 correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL2, NULL);
65 break;
67 default:
68 res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL3);
69 correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL3, NULL);
70 break;
73 if (memcmp (&correct, &res, sizeof (res)))
74 abort ();