1 ;; Machine description for FT32
2 ;; Copyright (C) 2015-2018 Free Software Foundation, Inc.
3 ;; Contributed by FTDI <support@ftdi.com>
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; -------------------------------------------------------------------------
22 ;; FT32 specific constraints, predicates and attributes
23 ;; -------------------------------------------------------------------------
25 (include "constraints.md")
26 (include "predicates.md")
34 (define_c_enum "unspec"
53 ;; -------------------------------------------------------------------------
55 ;; -------------------------------------------------------------------------
62 ;; -------------------------------------------------------------------------
63 ;; Arithmetic instructions
64 ;; -------------------------------------------------------------------------
67 [(set (match_operand:SI 0 "register_operand" "=r,r")
69 (match_operand:SI 1 "register_operand" "r,r")
70 (match_operand:SI 2 "ft32_rimm_operand" "KA,r")))
76 [(set (match_operand:SI 0 "register_operand" "=r,r")
78 (match_operand:SI 1 "register_operand" "r,r")
79 (match_operand:SI 2 "ft32_rimm_operand" "KA,r")))]
84 [(set (match_operand:SI 0 "register_operand" "=r,r")
86 (match_operand:SI 1 "register_operand" "r,r")
87 (match_operand:SI 2 "ft32_rimm_operand" "KA,r")))]
91 (define_insn "umulsidi3"
92 [(set (match_operand:DI 0 "register_operand" "=r,r")
93 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
94 (zero_extend:DI (match_operand:SI 2 "ft32_rimm_operand" "r,KA"))))
95 (clobber (reg:CC CC_REG))]
97 "mul.l $cc,%1,%2\;muluh.l %h0,%1,%2\;move.l %0,$cc")
100 [(set (match_operand:SI 0 "register_operand" "=r,r")
102 (match_operand:SI 1 "register_operand" "r,r")
103 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
107 (define_insn "modsi3"
108 [(set (match_operand:SI 0 "register_operand" "=r,r")
110 (match_operand:SI 1 "register_operand" "r,r")
111 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
115 (define_insn "udivsi3"
116 [(set (match_operand:SI 0 "register_operand" "=r,r")
118 (match_operand:SI 1 "register_operand" "r,r")
119 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
123 (define_insn "umodsi3"
124 [(set (match_operand:SI 0 "register_operand" "=r,r")
126 (match_operand:SI 1 "register_operand" "r,r")
127 (match_operand:SI 2 "register_operand" "r,KA")))]
131 (define_insn "extvsi"
132 [(set (match_operand:SI 0 "register_operand" "=r")
133 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
134 (match_operand:SI 2 "ft32_bwidth_operand" "b")
135 (match_operand:SI 3 "const_int_operand" "i")))]
137 "bexts.l %0,%1,((15 & %2) << 5) | (%3)")
139 (define_insn "extzvsi"
140 [(set (match_operand:SI 0 "register_operand" "=r")
141 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
142 (match_operand:SI 2 "ft32_bwidth_operand" "b")
143 (match_operand:SI 3 "const_int_operand" "i")))]
145 "bextu.l %0,%1,((15 & %2) << 5) | (%3)")
147 (define_insn "insvsi"
148 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
149 (match_operand:SI 1 "ft32_bwidth_operand" "b,b")
150 (match_operand:SI 2 "const_int_operand" "i,i"))
151 (match_operand:SI 3 "general_operand" "r,O"))
152 (clobber (match_scratch:SI 4 "=&r,r"))]
155 if (which_alternative == 0)
157 return \"ldl.l %4,%3,((%1&15)<<5)|(%2)\;bins.l %0,%0,%4\";
161 if ((INTVAL(operands[3]) == 0) || (INTVAL(operands[1]) == 1))
162 return \"bins.l %0,%0,(%3<<9)|((%1&15)<<5)|(%2)\";
164 return \"ldk.l %4,(%3<<10)|((%1&15)<<5)|(%2)\;bins.l %0,%0,%4\";
168 ;; -------------------------------------------------------------------------
169 ;; Unary arithmetic instructions
170 ;; -------------------------------------------------------------------------
172 (define_insn "one_cmplsi2"
173 [(set (match_operand:SI 0 "register_operand" "=r")
174 (not:SI (match_operand:SI 1 "register_operand" "r")))]
178 ;; -------------------------------------------------------------------------
180 ;; -------------------------------------------------------------------------
182 (define_insn "andsi3"
183 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
184 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
185 (match_operand:SI 2 "general_operand" "r,x,KA")))]
192 (define_insn "andqi3"
193 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
194 (and:QI (match_operand:QI 1 "register_operand" "r,r,r")
195 (match_operand:QI 2 "general_operand" "r,x,KA")))]
202 (define_insn "xorsi3"
203 [(set (match_operand:SI 0 "register_operand" "=r,r")
204 (xor:SI (match_operand:SI 1 "register_operand" "r,r")
205 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
208 return "xor.l %0,%1,%2";
211 (define_insn "iorsi3"
212 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
213 (ior:SI (match_operand:SI 1 "register_operand" "r,r,r")
214 (match_operand:SI 2 "general_operand" "r,w,KA")))]
221 ;; -------------------------------------------------------------------------
223 ;; -------------------------------------------------------------------------
225 (define_insn "ashlsi3"
226 [(set (match_operand:SI 0 "register_operand" "=r,r")
227 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
228 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
231 return "ashl.l %0,%1,%2";
234 (define_insn "ashrsi3"
235 [(set (match_operand:SI 0 "register_operand" "=r,r")
236 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
237 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
240 return "ashr.l %0,%1,%2";
243 (define_insn "lshrsi3"
244 [(set (match_operand:SI 0 "register_operand" "=r,r")
245 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
246 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
249 return "lshr.l %0,%1,%2";
252 ;; -------------------------------------------------------------------------
254 ;; -------------------------------------------------------------------------
259 [(set (match_operand:SI 0 "register_operand" "=r")
262 "bextu.l %0,$cc,32|0\;xor.l %0,%0,-1"
265 ;; Push a register onto the stack
266 (define_insn "movsi_push"
267 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
268 (match_operand:SI 0 "register_operand" "r"))]
272 ;; Pop a register from the stack
273 (define_insn "movsi_pop"
274 [(set (match_operand:SI 0 "register_operand" "=r")
275 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
279 (define_expand "movsi"
280 [(set (match_operand:SI 0 "general_operand" "")
281 (match_operand:SI 1 "general_operand" ""))]
284 /* If this is a store, force the value into a register. */
285 if (!(reload_in_progress || reload_completed))
287 if (MEM_P (operands[0]))
289 operands[1] = force_reg (SImode, operands[1]);
290 if (MEM_P (XEXP (operands[0], 0)))
291 operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
295 if (MEM_P (operands[1]) && MEM_P (XEXP (operands[1], 0)))
296 operands[1] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[1], 0)));
299 if (MEM_P (operands[0])) {
300 rtx o = XEXP (operands[0], 0);
303 GET_CODE(o) != SYMBOL_REF &&
304 GET_CODE(o) != LABEL_REF) {
305 operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
312 (define_insn "*rtestsi"
313 [(set (reg:SI CC_REG)
314 (match_operand:SI 0 "register_operand" "r"))]
319 (define_insn "*rtestqi"
320 [(set (reg:QI CC_REG)
321 (match_operand:QI 0 "register_operand" "r"))]
326 (define_insn "*movsi"
327 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,BW,r,r,r,r,A,r,r")
328 (match_operand:SI 1 "ft32_general_movsrc_operand" "r,r,BW,A,S,i,r,e,f"))]
329 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
336 *return ft32_load_immediate(operands[0], INTVAL(operands[1]));
342 (define_expand "movqi"
343 [(set (match_operand:QI 0 "general_operand" "")
344 (match_operand:QI 1 "general_operand" ""))]
347 /* If this is a store, force the value into a register. */
348 if (!(reload_in_progress || reload_completed))
350 if (MEM_P (operands[0]))
352 operands[1] = force_reg (QImode, operands[1]);
353 if (MEM_P (XEXP (operands[0], 0)))
354 operands[0] = gen_rtx_MEM (QImode, force_reg (SImode, XEXP (operands[0], 0)));
358 if (MEM_P (operands[1]) && MEM_P (XEXP (operands[1], 0)))
359 operands[1] = gen_rtx_MEM (QImode, force_reg (SImode, XEXP (operands[1], 0)));
361 if (MEM_P (operands[0]) && !REG_P(XEXP (operands[0], 0)))
363 operands[0] = gen_rtx_MEM (QImode, force_reg (SImode, XEXP (operands[0], 0)));
368 (define_insn "zero_extendqisi2"
369 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r")
370 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "BW,r,f")))]
378 (define_insn "extendqisi2"
379 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
380 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r")))]
382 "bexts.l %0,%1,(8<<5)|0"
385 (define_insn "zero_extendhisi2"
386 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r")
387 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "BW,r,f")))]
391 bextu.l %0,%1,(0<<5)|0
395 (define_insn "extendhisi2"
396 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
397 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))]
399 "bexts.l %0,%1,(0<<5)|0"
402 (define_insn "*movqi"
403 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
404 (match_operand:QI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
405 "register_operand (operands[0], QImode)
406 || register_operand (operands[1], QImode)"
418 (define_expand "movhi"
419 [(set (match_operand:HI 0 "general_operand" "")
420 (match_operand:HI 1 "general_operand" ""))]
423 /* If this is a store, force the value into a register. */
424 if (!(reload_in_progress || reload_completed))
426 if (MEM_P (operands[0]))
428 operands[1] = force_reg (HImode, operands[1]);
429 if (MEM_P (XEXP (operands[0], 0)))
430 operands[0] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[0], 0)));
434 if (MEM_P (operands[1]) && MEM_P (XEXP (operands[1], 0)))
435 operands[1] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[1], 0)));
437 if (MEM_P (operands[0]))
439 rtx o = XEXP (operands[0], 0);
442 GET_CODE(o) != SYMBOL_REF &&
443 GET_CODE(o) != LABEL_REF) {
444 operands[0] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[0], 0)));
450 (define_insn "*movhi"
451 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
452 (match_operand:HI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
453 "(register_operand (operands[0], HImode)
454 || register_operand (operands[1], HImode))"
466 (define_expand "movsf"
467 [(set (match_operand:SF 0 "general_operand" "")
468 (match_operand:SF 1 "general_operand" ""))]
471 /* If this is a store, force the value into a register. */
472 if (MEM_P (operands[0]))
473 operands[1] = force_reg (SFmode, operands[1]);
474 if (CONST_DOUBLE_P(operands[1]))
475 operands[1] = force_const_mem(SFmode, operands[1]);
478 (define_insn "*movsf"
479 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r")
480 (match_operand:SF 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,f"))]
481 "(register_operand (operands[0], SFmode)
482 || register_operand (operands[1], SFmode))"
493 ;; -------------------------------------------------------------------------
494 ;; Compare instructions
495 ;; -------------------------------------------------------------------------
497 (define_expand "cbranchsi4"
498 [(set (reg:CC CC_REG)
500 (match_operand:SI 1 "register_operand" "")
501 (match_operand:SI 2 "ft32_rimm_operand" "")))
503 (if_then_else (match_operator 0 "comparison_operator"
504 [(reg:CC CC_REG) (const_int 0)])
505 (label_ref (match_operand 3 "" ""))
511 [(set (reg:CC CC_REG)
513 (match_operand:SI 0 "register_operand" "r,r")
514 (match_operand:SI 1 "ft32_rimm_operand" "r,KA")))]
521 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
523 (match_operand:SI 1 "const_int_operand" "i"))
525 (label_ref (match_operand 2 "" ""))
527 (clobber (reg:CC CC_REG))]
529 "btst.l %0,(1<<5)|%1\;jmpc nz,%l2")
534 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
536 (match_operand:SI 1 "const_int_operand" "i"))
538 (label_ref (match_operand 2 "" ""))
540 (clobber (reg:CC CC_REG))]
542 "btst.l %0,(1<<5)|%1\;jmpc z,%l2")
544 (define_expand "cbranchqi4"
545 [(set (reg:CC CC_REG)
547 (match_operand:QI 1 "register_operand" "")
548 (match_operand:QI 2 "ft32_rimm_operand" "")))
550 (if_then_else (match_operator 0 "comparison_operator"
551 [(reg:CC CC_REG) (const_int 0)])
552 (label_ref (match_operand 3 "" ""))
557 (define_insn "*cmpqi"
558 [(set (reg:CC CC_REG)
560 (match_operand:QI 0 "register_operand" "r,r")
561 (match_operand:QI 1 "ft32_rimm_operand" "r,KA")))]
565 ;; -------------------------------------------------------------------------
566 ;; Branch instructions
567 ;; -------------------------------------------------------------------------
569 (define_code_iterator cond [ne eq lt ltu gt gtu ge le geu leu])
570 (define_code_attr CC [(ne "nz") (eq "z") (lt "lt") (ltu "b")
571 (gt "gt") (gtu "a") (ge "gte") (le "lte")
572 (geu "ae") (leu "be") ])
573 (define_code_attr rCC [(ne "z") (eq "nz") (lt "gte") (ltu "ae")
574 (gt "lte") (gtu "be") (ge "lt") (le "gt")
575 (geu "b") (leu "a") ])
577 (define_insn "*b<cond:code>"
579 (if_then_else (cond (reg:CC CC_REG)
581 (label_ref (match_operand 0 "" ""))
585 return "jmpc <CC>,%l0";
589 (define_expand "cstoresi4"
590 [(set (reg:CC CC_REG)
591 (compare:CC (match_operand:SI 2 "register_operand" "r,r")
592 (match_operand:SI 3 "ft32_rimm_operand" "r,KA")))
593 (set (match_operand:SI 0 "register_operand")
594 (match_operator:SI 1 "ordered_comparison_operator"
595 [(reg:CC CC_REG) (const_int 0)]))]
600 switch (GET_CODE (operands[1])) {
606 test = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
607 SImode, operands[2], operands[3]);
608 emit_insn(gen_cstoresi4(operands[0], test, operands[2], operands[3]));
609 emit_insn(gen_xorsi3(operands[0], operands[0], gen_int_mode(1, SImode)));
617 [(set (match_operand:SI 0 "register_operand" "=r")
618 (eq:SI (reg CC_REG) (const_int 0)))]
620 "bextu.l %0,$cc,32|0"
624 [(set (match_operand:SI 0 "register_operand" "=r")
625 (ltu:SI (reg CC_REG) (const_int 0)))]
627 "bextu.l %0,$cc,32|1"
631 [(set (match_operand:SI 0 "register_operand" "=r")
632 (ge:SI (reg CC_REG) (const_int 0)))]
634 "bextu.l %0,$cc,32|4"
638 [(set (match_operand:SI 0 "register_operand" "=r")
639 (gt:SI (reg CC_REG) (const_int 0)))]
641 "bextu.l %0,$cc,32|5"
645 [(set (match_operand:SI 0 "register_operand" "=r")
646 (gtu:SI (reg CC_REG) (const_int 0)))]
648 "bextu.l %0,$cc,32|6"
651 ;; -------------------------------------------------------------------------
652 ;; Call and Jump instructions
653 ;; -------------------------------------------------------------------------
655 (define_expand "call"
656 [(call (match_operand:QI 0 "memory_operand" "")
657 (match_operand 1 "general_operand" ""))]
660 gcc_assert (MEM_P (operands[0]));
664 [(call (mem:QI (match_operand:SI
665 0 "nonmemory_operand" "i,r"))
666 (match_operand 1 "" ""))]
673 (define_expand "call_value"
674 [(set (match_operand 0 "" "")
675 (call (match_operand:QI 1 "memory_operand" "")
676 (match_operand 2 "" "")))]
679 gcc_assert (MEM_P (operands[1]));
682 (define_insn "*call_value"
683 [(set (match_operand 0 "register_operand" "=r")
684 (call (mem:QI (match_operand:SI
685 1 "immediate_operand" "i"))
686 (match_operand 2 "" "")))]
691 (define_insn "*call_value_indirect"
692 [(set (match_operand 0 "register_operand" "=r")
693 (call (mem:QI (match_operand:SI
694 1 "register_operand" "r"))
695 (match_operand 2 "" "")))]
700 (define_insn "indirect_jump"
701 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
707 (label_ref (match_operand 0 "" "")))]
712 (define_insn "call_prolog"
713 [(unspec:SI [(match_operand 0 "" "")]
719 (define_insn "jump_epilog"
720 [(unspec:SI [(match_operand 0 "" "")]
726 (define_insn "jump_epilog24"
727 [(unspec:SI [(match_operand 0 "" "")]
728 UNSPEC_JMP_EPILOG24)]
734 ;; Subroutines of "casesi".
735 ;; operand 0 is index
736 ;; operand 1 is the minimum bound
737 ;; operand 2 is the maximum bound - minimum bound + 1
738 ;; operand 3 is CODE_LABEL for the table;
739 ;; operand 4 is the CODE_LABEL to go to if index out of range.
741 (define_expand "casesi"
742 [(match_operand:SI 0 "general_operand" "")
743 (match_operand:SI 1 "const_int_operand" "")
744 (match_operand:SI 2 "const_int_operand" "")
745 (match_operand 3 "" "")
746 (match_operand 4 "" "")]
750 if (GET_CODE (operands[0]) != REG)
751 operands[0] = force_reg (SImode, operands[0]);
753 if (operands[1] != const0_rtx)
755 rtx index = gen_reg_rtx (SImode);
756 rtx offset = gen_reg_rtx (SImode);
758 emit_insn (gen_movsi (offset, operands[1]));
759 emit_insn (gen_subsi3 (index, operands[0], offset));
764 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
765 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
768 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
772 (define_insn "casesi0"
773 [(set (pc) (mem:SI (plus:SI
774 (mult:SI (match_operand:SI 0 "register_operand" "r")
776 (label_ref (match_operand 1 "" "")))))
777 (clobber (match_scratch:SI 2 "=&r"))
782 return \"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;ldi.l\t%2,%2,0\;jmpi\t%2\";
784 return \"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;lpmi.l\t%2,%2,0\;jmpi\t%2\";
787 ;; -------------------------------------------------------------------------
788 ;; Atomic exchange instruction
789 ;; -------------------------------------------------------------------------
791 (define_insn "atomic_exchangesi"
792 [(set (match_operand:SI 0 "register_operand" "=&r,r") ;; output
793 (match_operand:SI 1 "memory_operand" "+BW,A")) ;; memory
796 [(match_operand:SI 2 "register_operand" "0,0") ;; input
797 (match_operand:SI 3 "const_int_operand")] ;; model
804 (define_insn "atomic_exchangehi"
805 [(set (match_operand:HI 0 "register_operand" "=&r,r") ;; output
806 (match_operand:HI 1 "memory_operand" "+BW,A")) ;; memory
809 [(match_operand:HI 2 "register_operand" "0,0") ;; input
810 (match_operand:HI 3 "const_int_operand")] ;; model
817 (define_insn "atomic_exchangeqi"
818 [(set (match_operand:QI 0 "register_operand" "=&r,r") ;; output
819 (match_operand:QI 1 "memory_operand" "+BW,A")) ;; memory
822 [(match_operand:QI 2 "register_operand" "0,0") ;; input
823 (match_operand:QI 3 "const_int_operand")] ;; model
830 ;; -------------------------------------------------------------------------
831 ;; String instructions
832 ;; -------------------------------------------------------------------------
834 (define_insn "cmpstrsi"
835 [(set (match_operand:SI 0 "register_operand" "=r,r")
836 (compare:SI (match_operand:BLK 1 "memory_operand" "W,BW")
837 (match_operand:BLK 2 "memory_operand" "W,BW")))
838 (clobber (match_operand:SI 3))
841 "strcmp.%d3 %0,%b1,%b2"
844 (define_insn "movstr"
845 [(set (match_operand:BLK 1 "memory_operand" "=W")
846 (match_operand:BLK 2 "memory_operand" "W"))
847 (use (match_operand:SI 0))
848 (clobber (match_dup 0))
851 "stpcpy %b1,%b2 # %0 %b1 %b2"
854 (define_insn "movmemsi"
855 [(set (match_operand:BLK 0 "memory_operand" "=W,BW")
856 (match_operand:BLK 1 "memory_operand" "W,BW"))
857 (use (match_operand:SI 2 "ft32_imm_operand" "KA,KA"))
858 (use (match_operand:SI 3))
861 "memcpy.%d3 %b0,%b1,%2 "
864 (define_insn "setmemsi"
865 [(set (match_operand:BLK 0 "memory_operand" "=BW") (unspec:BLK [
866 (use (match_operand:QI 2 "register_operand" "r"))
867 (use (match_operand:SI 1 "ft32_imm_operand" "KA"))
869 (use (match_operand:SI 3))
872 "memset.%d3 %b0,%2,%1"
875 (define_insn "strlensi"
876 [(set (match_operand:SI 0 "register_operand" "=r")
877 (unspec:SI [(match_operand:BLK 1 "memory_operand" "W")
878 (match_operand:QI 2 "const_int_operand" "")
879 (match_operand:SI 3 "ft32_rimm_operand" "")]
882 "strlen.%d3 %0,%b1 # %2 %3"
885 ;; -------------------------------------------------------------------------
886 ;; Prologue & Epilogue
887 ;; -------------------------------------------------------------------------
889 (define_expand "prologue"
890 [(clobber (const_int 0))]
893 extern void ft32_expand_prologue();
894 ft32_expand_prologue ();
899 (define_expand "epilogue"
903 extern void ft32_expand_epilogue();
904 ft32_expand_epilogue ();
910 ;; (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
912 (set (match_operand:SI 0)
915 (plus:SI (reg:SI SP_REG)
916 (match_operand:SI 1 "general_operand" "L")))]
921 (define_insn "unlink"
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
931 (define_insn "returner"
936 (define_insn "pretend_returner"
937 [(set (reg:SI SP_REG)
938 (plus:SI (reg:SI SP_REG)
939 (match_operand:SI 0)))
942 "pop.l $cc\;add.l $sp,$sp,%0\;jmpi $cc")
944 (define_insn "returner24"