1 ;; Scheduling description for IBM POWER5 processor.
2 ;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 2, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to the
18 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19 ;; MA 02110-1301, USA.
21 ;; Sources: IBM Red Book and White Paper on POWER5
23 ;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
24 ;; Instructions that update more than one register get broken into two
25 ;; (split) or more internal ops. The chip can issue up to 5
26 ;; internal ops per cycle.
28 (define_automaton "power5iu,power5fpu,power5misc")
30 (define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
31 (define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
32 (define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
33 (define_cpu_unit "bpu_power5,cru_power5" "power5misc")
34 (define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
37 (define_reservation "lsq_power5"
38 "(du1_power5,lsu1_power5)\
39 |(du2_power5,lsu2_power5)\
40 |(du3_power5,lsu2_power5)\
41 |(du4_power5,lsu1_power5)")
43 (define_reservation "iq_power5"
44 "(du1_power5,iu1_power5)\
45 |(du2_power5,iu2_power5)\
46 |(du3_power5,iu2_power5)\
47 |(du4_power5,iu1_power5)")
49 (define_reservation "fpq_power5"
50 "(du1_power5,fpu1_power5)\
51 |(du2_power5,fpu2_power5)\
52 |(du3_power5,fpu2_power5)\
53 |(du4_power5,fpu1_power5)")
55 ; Dispatch slots are allocated in order conforming to program order.
56 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
57 (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
58 (absence_set "du3_power5" "du4_power5,du5_power5")
59 (absence_set "du4_power5" "du5_power5")
63 (define_insn_reservation "power5-load" 4 ; 3
64 (and (eq_attr "type" "load")
65 (eq_attr "cpu" "power5"))
68 (define_insn_reservation "power5-load-ext" 5
69 (and (eq_attr "type" "load_ext")
70 (eq_attr "cpu" "power5"))
71 "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
73 (define_insn_reservation "power5-load-ext-update" 5
74 (and (eq_attr "type" "load_ext_u")
75 (eq_attr "cpu" "power5"))
76 "du1_power5+du2_power5+du3_power5+du4_power5,\
77 lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
79 (define_insn_reservation "power5-load-ext-update-indexed" 5
80 (and (eq_attr "type" "load_ext_ux")
81 (eq_attr "cpu" "power5"))
82 "du1_power5+du2_power5+du3_power5+du4_power5,\
83 iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
85 (define_insn_reservation "power5-load-update-indexed" 3
86 (and (eq_attr "type" "load_ux")
87 (eq_attr "cpu" "power5"))
88 "du1_power5+du2_power5+du3_power5+du4_power5,\
89 iu1_power5,lsu2_power5+iu2_power5")
91 (define_insn_reservation "power5-load-update" 4 ; 3
92 (and (eq_attr "type" "load_u")
93 (eq_attr "cpu" "power5"))
94 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
96 (define_insn_reservation "power5-fpload" 6 ; 5
97 (and (eq_attr "type" "fpload")
98 (eq_attr "cpu" "power5"))
101 (define_insn_reservation "power5-fpload-update" 6 ; 5
102 (and (eq_attr "type" "fpload_u,fpload_ux")
103 (eq_attr "cpu" "power5"))
104 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
106 (define_insn_reservation "power5-store" 12
107 (and (eq_attr "type" "store")
108 (eq_attr "cpu" "power5"))
109 "(du1_power5,lsu1_power5,iu1_power5)\
110 |(du2_power5,lsu2_power5,iu2_power5)\
111 |(du3_power5,lsu2_power5,iu2_power5)\
112 |(du4_power5,lsu1_power5,iu1_power5)")
114 (define_insn_reservation "power5-store-update" 12
115 (and (eq_attr "type" "store_u")
116 (eq_attr "cpu" "power5"))
117 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
119 (define_insn_reservation "power5-store-update-indexed" 12
120 (and (eq_attr "type" "store_ux")
121 (eq_attr "cpu" "power5"))
122 "du1_power5+du2_power5+du3_power5+du4_power5,\
123 iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
125 (define_insn_reservation "power5-fpstore" 12
126 (and (eq_attr "type" "fpstore")
127 (eq_attr "cpu" "power5"))
128 "(du1_power5,lsu1_power5,fpu1_power5)\
129 |(du2_power5,lsu2_power5,fpu2_power5)\
130 |(du3_power5,lsu2_power5,fpu2_power5)\
131 |(du4_power5,lsu1_power5,fpu1_power5)")
133 (define_insn_reservation "power5-fpstore-update" 12
134 (and (eq_attr "type" "fpstore_u,fpstore_ux")
135 (eq_attr "cpu" "power5"))
136 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
138 (define_insn_reservation "power5-llsc" 11
139 (and (eq_attr "type" "load_l,store_c,sync")
140 (eq_attr "cpu" "power5"))
141 "du1_power5+du2_power5+du3_power5+du4_power5,\
145 ; Integer latency is 2 cycles
146 (define_insn_reservation "power5-integer" 2
147 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
148 var_shift_rotate,cntlz,exts")
149 (eq_attr "cpu" "power5"))
152 (define_insn_reservation "power5-two" 2
153 (and (eq_attr "type" "two")
154 (eq_attr "cpu" "power5"))
155 "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
156 |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
157 |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
158 |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
160 (define_insn_reservation "power5-three" 2
161 (and (eq_attr "type" "three")
162 (eq_attr "cpu" "power5"))
163 "(du1_power5+du2_power5+du3_power5,\
164 iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
165 |(du2_power5+du3_power5+du4_power5,\
166 iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
167 |(du3_power5+du4_power5+du1_power5,\
168 iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
169 |(du4_power5+du1_power5+du2_power5,\
170 iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
172 (define_insn_reservation "power5-insert" 4
173 (and (eq_attr "type" "insert_word")
174 (eq_attr "cpu" "power5"))
175 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
177 (define_insn_reservation "power5-cmp" 3
178 (and (eq_attr "type" "cmp,fast_compare")
179 (eq_attr "cpu" "power5"))
182 (define_insn_reservation "power5-compare" 2
183 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
184 (eq_attr "cpu" "power5"))
185 "du1_power5+du2_power5,iu1_power5,iu2_power5")
187 (define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
189 (define_insn_reservation "power5-lmul-cmp" 7
190 (and (eq_attr "type" "lmul_compare")
191 (eq_attr "cpu" "power5"))
192 "du1_power5+du2_power5,iu1_power5*6,iu2_power5")
194 (define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
196 (define_insn_reservation "power5-imul-cmp" 5
197 (and (eq_attr "type" "imul_compare")
198 (eq_attr "cpu" "power5"))
199 "du1_power5+du2_power5,iu1_power5*4,iu2_power5")
201 (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
203 (define_insn_reservation "power5-lmul" 7
204 (and (eq_attr "type" "lmul")
205 (eq_attr "cpu" "power5"))
206 "(du1_power5,iu1_power5*6)\
207 |(du2_power5,iu2_power5*6)\
208 |(du3_power5,iu2_power5*6)\
209 |(du4_power5,iu1_power5*6)")
211 (define_insn_reservation "power5-imul" 5
212 (and (eq_attr "type" "imul")
213 (eq_attr "cpu" "power5"))
214 "(du1_power5,iu1_power5*4)\
215 |(du2_power5,iu2_power5*4)\
216 |(du3_power5,iu2_power5*4)\
217 |(du4_power5,iu1_power5*4)")
219 (define_insn_reservation "power5-imul3" 4
220 (and (eq_attr "type" "imul2,imul3")
221 (eq_attr "cpu" "power5"))
222 "(du1_power5,iu1_power5*3)\
223 |(du2_power5,iu2_power5*3)\
224 |(du3_power5,iu2_power5*3)\
225 |(du4_power5,iu1_power5*3)")
228 ; SPR move only executes in first IU.
229 ; Integer division only executes in second IU.
230 (define_insn_reservation "power5-idiv" 36
231 (and (eq_attr "type" "idiv")
232 (eq_attr "cpu" "power5"))
233 "du1_power5+du2_power5,iu2_power5*35")
235 (define_insn_reservation "power5-ldiv" 68
236 (and (eq_attr "type" "ldiv")
237 (eq_attr "cpu" "power5"))
238 "du1_power5+du2_power5,iu2_power5*67")
241 (define_insn_reservation "power5-mtjmpr" 3
242 (and (eq_attr "type" "mtjmpr,mfjmpr")
243 (eq_attr "cpu" "power5"))
244 "du1_power5,bpu_power5")
247 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
248 ; grabbing previous dispatch slots once this is assigned.
249 (define_insn_reservation "power5-branch" 2
250 (and (eq_attr "type" "jmpreg,branch")
251 (eq_attr "cpu" "power5"))
253 |du4_power5+du5_power5\
254 |du3_power5+du4_power5+du5_power5\
255 |du2_power5+du3_power5+du4_power5+du5_power5\
256 |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
259 ; Condition Register logical ops are split if non-destructive (RT != RB)
260 (define_insn_reservation "power5-crlogical" 2
261 (and (eq_attr "type" "cr_logical")
262 (eq_attr "cpu" "power5"))
263 "du1_power5,cru_power5")
265 (define_insn_reservation "power5-delayedcr" 4
266 (and (eq_attr "type" "delayed_cr")
267 (eq_attr "cpu" "power5"))
268 "du1_power5+du2_power5,cru_power5,cru_power5")
270 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
271 (define_insn_reservation "power5-mfcr" 6
272 (and (eq_attr "type" "mfcr")
273 (eq_attr "cpu" "power5"))
274 "du1_power5+du2_power5+du3_power5+du4_power5,\
275 du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
276 cru_power5,cru_power5,cru_power5")
279 (define_insn_reservation "power5-mfcrf" 3
280 (and (eq_attr "type" "mfcrf")
281 (eq_attr "cpu" "power5"))
282 "du1_power5,cru_power5")
285 (define_insn_reservation "power5-mtcr" 4
286 (and (eq_attr "type" "mtcr")
287 (eq_attr "cpu" "power5"))
288 "du1_power5,iu1_power5")
290 ; Basic FP latency is 6 cycles
291 (define_insn_reservation "power5-fp" 6
292 (and (eq_attr "type" "fp,dmul")
293 (eq_attr "cpu" "power5"))
296 (define_insn_reservation "power5-fpcompare" 5
297 (and (eq_attr "type" "fpcompare")
298 (eq_attr "cpu" "power5"))
301 (define_insn_reservation "power5-sdiv" 33
302 (and (eq_attr "type" "sdiv,ddiv")
303 (eq_attr "cpu" "power5"))
304 "(du1_power5,fpu1_power5*28)\
305 |(du2_power5,fpu2_power5*28)\
306 |(du3_power5,fpu2_power5*28)\
307 |(du4_power5,fpu1_power5*28)")
309 (define_insn_reservation "power5-sqrt" 40
310 (and (eq_attr "type" "ssqrt,dsqrt")
311 (eq_attr "cpu" "power5"))
312 "(du1_power5,fpu1_power5*35)\
313 |(du2_power5,fpu2_power5*35)\
314 |(du3_power5,fpu2_power5*35)\
315 |(du4_power5,fpu2_power5*35)")
317 (define_insn_reservation "power5-isync" 2
318 (and (eq_attr "type" "isync")
319 (eq_attr "cpu" "power5"))
320 "du1_power5+du2_power5+du3_power5+du4_power5,\