| blob | af14b990794fb8c61aa4cbdc6d1742cc8cfe6e16 |
1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2014 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
45 #if SWITCHABLE_TARGET
47 #endif
53 rtx);
56 rtx);
61 rtx);
75 /* Return a constant integer mask value of mode MODE with BITSIZE ones
76 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
77 The mask is truncated if necessary to the width of mode MODE. The
78 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
82 {
83 return immed_wide_int_const
86 }
88 /* Test whether a value is zero of a power of two. */
89 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
90 (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0)
92 struct init_expmed_rtl
93 {
94 rtx reg;
95 rtx plus;
96 rtx neg;
97 rtx mult;
98 rtx sdiv;
99 rtx udiv;
100 rtx sdiv_32;
101 rtx smod_32;
102 rtx wide_mult;
103 rtx wide_lshr;
104 rtx wide_trunc;
105 rtx shift;
106 rtx shift_mult;
107 rtx shift_add;
108 rtx shift_sub0;
109 rtx shift_sub1;
110 rtx zext;
111 rtx trunc;
115 };
117 static void
120 {
122 rtx which;
127 /* Most partial integers have a precision less than the "full"
128 integer it requires for storage. In case one doesn't, for
129 comparison purposes here, reduce the bit size by one in that
130 case. */
133 to_size --;
136 from_size --;
138 /* Assume cost of zero-extend and sign-extend is the same. */
143 }
145 static void
148 {
150 machine_mode mode_from;
183 {
188 }
192 {
200 }
203 {
207 }
209 {
212 {
222 }
223 }
224 }
226 void
228 {
235 {
238 }
240 /* Avoid using hard regs in ways which may be unsupported. */
261 {
278 }
281 {
284 }
285 else
307 }
309 /* Return an rtx representing minus the value of X.
310 MODE is the intended mode of the result,
311 useful if X is a CONST_INT. */
313 rtx
315 {
322 }
324 /* Adjust bitfield memory MEM so that it points to the first unit of mode
325 MODE that contains a bitfield of size BITSIZE at bit position BITNUM.
326 If MODE is BLKmode, return a reference to every byte in the bitfield.
327 Set *NEW_BITNUM to the bit position of the field within the new memory. */
329 static rtx
334 {
336 {
342 }
343 else
344 {
349 }
350 }
352 /* The caller wants to perform insertion or extraction PATTERN on a
353 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
354 BITREGION_START and BITREGION_END are as for store_bit_field
355 and FIELDMODE is the natural mode of the field.
357 Search for a mode that is compatible with the memory access
358 restrictions and (where applicable) with a register insertion or
359 extraction. Return the new memory on success, storing the adjusted
360 bit position in *NEW_BITNUM. Return null otherwise. */
362 static rtx
365 HOST_WIDE_INT bitnum,
368 machine_mode fieldmode,
370 {
374 machine_mode best_mode;
376 {
377 /* We can use a memory in BEST_MODE. See whether this is true for
378 any wider modes. All other things being equal, we prefer to
379 use the widest mode possible because it tends to expose more
380 CSE opportunities. */
382 {
383 /* Limit the search to the mode required by the corresponding
384 register insertion or extraction instruction, if any. */
386 extraction_insn insn;
389 fieldmode))
392 machine_mode wider_mode;
396 }
398 new_bitnum);
399 }
401 }
403 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
404 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
405 offset is then BITNUM / BITS_PER_UNIT. */
407 static bool
410 machine_mode struct_mode)
411 {
416 else
418 }
420 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
421 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
422 Return false if the access would touch memory outside the range
423 BITREGION_START to BITREGION_END for conformance to the C++ memory
424 model. */
426 static bool
429 machine_mode fieldmode,
432 {
435 /* -fstrict-volatile-bitfields must be enabled and we must have a
436 volatile MEM. */
442 /* Non-integral modes likely only happen with packed structures.
443 Punt. */
447 /* The bit size must not be larger than the field mode, and
448 the field mode must not be larger than a word. */
452 /* Check for cases of unaligned fields that must be split. */
454 || (STRICT_ALIGNMENT
458 /* Check for cases where the C++ memory model applies. */
465 }
467 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
468 bit number BITNUM can be treated as a simple value of mode MODE. */
470 static bool
473 {
480 }
481 \f
482 /* Try to use instruction INSV to store VALUE into a field of OP0.
483 BITSIZE and BITNUM are as for store_bit_field. */
485 static bool
489 rtx value)
490 {
492 rtx value1;
503 /* Get a reference to the first byte of the field. */
506 else
507 {
508 /* Convert from counting within OP0 to counting in OP_MODE. */
512 /* If xop0 is a register, we need it in OP_MODE
513 to make it acceptable to the format of insv. */
515 /* We can't just change the mode, because this might clobber op0,
516 and we will need the original value of op0 if insv fails. */
520 }
522 /* If the destination is a paradoxical subreg such that we need a
523 truncate to the inner mode, perform the insertion on a temporary and
524 truncate the result to the original destination. Note that we can't
525 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
526 X) 0)) is (reg:N X). */
530 op_mode))
531 {
536 }
538 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
539 "backwards" from the size of the unit we are inserting into.
540 Otherwise, we count bits from the most significant on a
541 BYTES/BITS_BIG_ENDIAN machine. */
546 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
549 {
551 {
552 /* Optimization: Don't bother really extending VALUE
553 if it has all the bits we will actually use. However,
554 if we must narrow it, be sure we do it correctly. */
557 {
558 rtx tmp;
564 value1),
567 }
568 else
570 }
573 else
574 /* Parse phase is supposed to make VALUE's data type
575 match that of the component reference, which is a type
576 at least as wide as the field; so VALUE should have
577 a mode that corresponds to that type. */
579 }
586 {
590 }
593 }
595 /* A subroutine of store_bit_field, with the same arguments. Return true
596 if the operation could be implemented.
598 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
599 no other way of implementing the operation. If FALLBACK_P is false,
600 return false instead. */
602 static bool
607 machine_mode fieldmode,
609 {
611 rtx orig_value;
614 {
615 /* The following line once was done only if WORDS_BIG_ENDIAN,
616 but I think that is a mistake. WORDS_BIG_ENDIAN is
617 meaningful at a much higher level; when structures are copied
618 between memory and regs, the higher-numbered regs
619 always get higher addresses. */
624 /* Paradoxical subregs need special handling on big endian machines. */
626 {
633 }
634 else
639 }
641 /* No action is needed if the target is a register and if the field
642 lies completely outside that register. This can occur if the source
643 code contains an out-of-bounds access to a small array. */
647 /* Use vec_set patterns for inserting parts of vectors whenever
648 available. */
655 {
667 }
669 /* If the target is a register, overwriting the entire object, or storing
670 a full-word or multi-word field can be done with just a SUBREG. */
675 {
676 /* Use the subreg machinery either to narrow OP0 to the required
677 words or to cope with mode punning between equal-sized modes.
678 In the latter case, use subreg on the rhs side, not lhs. */
679 rtx sub;
682 {
685 {
688 }
689 }
690 else
691 {
695 {
698 }
699 }
700 }
702 /* If the target is memory, storing any naturally aligned field can be
703 done with a simple store. For targets that support fast unaligned
704 memory, any naturally sized, unit aligned field can be done directly. */
706 {
710 }
712 /* Make sure we are playing with integral modes. Pun with subregs
713 if we aren't. This must come after the entire register case above,
714 since that case is valid for any mode. The following cases are only
715 valid for integral modes. */
716 {
719 {
722 else
723 {
726 }
727 }
728 }
730 /* Storing an lsb-aligned field in a register
731 can be done with a movstrict instruction. */
737 {
744 {
745 /* Else we've got some float mode source being extracted into
746 a different float mode destination -- this combination of
747 subregs results in Severe Tire Damage. */
752 }
756 {
760 /* Shrink the source operand to FIELDMODE. */
764 }
765 }
767 /* Handle fields bigger than a word. */
770 {
771 /* Here we transfer the words of the field
772 in the order least significant first.
773 This is because the most significant word is the one which may
774 be less than full.
775 However, only do that if the value is not BLKmode. */
782 /* This is the mode we must force value to, so that there will be enough
783 subwords to extract. Note that fieldmode will often (always?) be
784 VOIDmode, because that is what store_field uses to indicate that this
785 is a bit field, but passing VOIDmode to operand_subword_force
786 is not allowed. */
793 {
794 /* If I is 0, use the low-order word in both field and target;
795 if I is 1, use the next to lowest word; and so on. */
809 /* If the remaining chunk doesn't have full wordsize we have
810 to make sure that for big endian machines the higher order
811 bits are used. */
814 value_word,
818 OPTAB_LIB_WIDEN);
823 word_mode,
825 {
828 }
829 }
831 }
833 /* If VALUE has a floating-point or complex mode, access it as an
834 integer of the corresponding size. This can occur on a machine
835 with 64 bit registers that uses SFmode for float. It can also
836 occur for unaligned float or complex fields. */
841 {
844 }
846 /* If OP0 is a multi-word register, narrow it to the affected word.
847 If the region spans two words, defer to store_split_bit_field. */
849 {
855 {
862 }
863 }
865 /* From here on we can assume that the field to be stored in fits
866 within a word. If the destination is a register, it too fits
867 in a word. */
869 extraction_insn insv;
873 fieldmode)
877 /* If OP0 is a memory, try copying it to a register and seeing if a
878 cheap register alternative is available. */
880 {
882 fieldmode)
888 /* Try loading part of OP0 into a register, inserting the bitfield
889 into that, and then copying the result back to OP0. */
895 {
900 {
903 }
905 }
906 }
914 }
916 /* Generate code to store value from rtx VALUE
917 into a bit-field within structure STR_RTX
918 containing BITSIZE bits starting at bit BITNUM.
920 BITREGION_START is bitpos of the first bitfield in this region.
921 BITREGION_END is the bitpos of the ending bitfield in this region.
922 These two fields are 0, if the C++ memory model does not apply,
923 or we are not interested in keeping track of bitfield regions.
925 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
927 void
932 machine_mode fieldmode,
933 rtx value)
934 {
935 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
938 {
939 /* Storing any naturally aligned field can be done with a simple
940 store. For targets that support fast unaligned memory, any
941 naturally sized, unit aligned field can be done directly. */
943 {
947 }
948 else
949 {
952 /* Explicitly override the C/C++ memory model; ignore the
953 bit range so that we can do the access in the mode mandated
954 by -fstrict-volatile-bitfields instead. */
956 }
959 }
961 /* Under the C++0x memory model, we must not touch bits outside the
962 bit region. Adjust the address to start at the beginning of the
963 bit region. */
965 {
966 machine_mode bestmode;
981 }
987 }
988 \f
989 /* Use shifts and boolean operations to store VALUE into a bit field of
990 width BITSIZE in OP0, starting at bit BITNUM. */
992 static void
997 rtx value)
998 {
999 /* There is a case not handled here:
1000 a structure with a known alignment of just a halfword
1001 and a field split across two aligned halfwords within the structure.
1002 Or likewise a structure with a known alignment of just a byte
1003 and a field split across two bytes.
1004 Such cases are not supposed to be able to occur. */
1007 {
1016 {
1017 /* The only way this should occur is if the field spans word
1018 boundaries. */
1022 }
1025 }
1028 }
1030 /* Helper function for store_fixed_bit_field, stores
1031 the bit field always using the MODE of OP0. */
1033 static void
1036 rtx value)
1037 {
1038 machine_mode mode;
1039 rtx temp;
1046 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1047 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1050 /* BITNUM is the distance between our msb
1051 and that of the containing datum.
1052 Convert it to the distance from the lsb. */
1055 /* Now BITNUM is always the distance between our lsb
1056 and that of OP0. */
1058 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1059 we must first convert its mode to MODE. */
1062 {
1077 }
1078 else
1079 {
1093 }
1095 /* Now clear the chosen bits in OP0,
1096 except that if VALUE is -1 we need not bother. */
1097 /* We keep the intermediates in registers to allow CSE to combine
1098 consecutive bitfield assignments. */
1103 {
1108 }
1110 /* Now logical-or VALUE into OP0, unless it is zero. */
1113 {
1117 }
1120 {
1123 }
1124 }
1125 \f
1126 /* Store a bit field that is split across multiple accessible memory objects.
1128 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1129 BITSIZE is the field width; BITPOS the position of its first bit
1130 (within the word).
1131 VALUE is the value to store.
1133 This does not yet handle fields wider than BITS_PER_WORD. */
1135 static void
1140 rtx value)
1141 {
1145 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1146 much at a time. */
1149 else
1152 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1153 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1154 again, and we will mutually recurse forever. */
1158 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1159 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1160 that VALUE might be a floating-point constant. */
1162 {
1167 else
1172 }
1175 {
1184 /* When region of bytes we can touch is restricted, decrease
1185 UNIT close to the end of the region as needed. If op0 is a REG
1186 or SUBREG of REG, don't do this, as there can't be data races
1187 on a register and we can expand shorter code in some cases. */
1193 {
1196 }
1198 /* THISSIZE must not overrun a word boundary. Otherwise,
1199 store_fixed_bit_field will call us again, and we will mutually
1200 recurse forever. */
1205 {
1206 /* Fetch successively less significant portions. */
1211 else
1212 {
1214 /* The args are chosen so that the last part includes the
1215 lsb. Give extract_bit_field the value it needs (with
1216 endianness compensation) to fetch the piece we want. */
1220 }
1221 }
1222 else
1223 {
1224 /* Fetch successively more significant portions. */
1229 else
1232 }
1234 /* If OP0 is a register, then handle OFFSET here.
1236 When handling multiword bitfields, extract_bit_field may pass
1237 down a word_mode SUBREG of a larger REG for a bitfield that actually
1238 crosses a word boundary. Thus, for a SUBREG, we must find
1239 the current word starting from the base register. */
1241 {
1247 else
1251 }
1253 {
1257 else
1261 }
1262 else
1265 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1266 it is just an out-of-bounds access. Ignore it. */
1271 }
1272 }
1273 \f
1274 /* A subroutine of extract_bit_field_1 that converts return value X
1275 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1276 to extract_bit_field. */
1278 static rtx
1281 {
1285 /* If the x mode is not a scalar integral, first convert to the
1286 integer mode of that size and then access it as a floating-point
1287 value via a SUBREG. */
1289 {
1290 machine_mode smode;
1296 }
1299 }
1301 /* Try to use an ext(z)v pattern to extract a field from OP0.
1302 Return the extracted value on success, otherwise return null.
1303 EXT_MODE is the mode of the extraction and the other arguments
1304 are as for extract_bit_field. */
1306 static rtx
1312 {
1323 /* Get a reference to the first byte of the field. */
1326 else
1327 {
1328 /* Convert from counting within OP0 to counting in EXT_MODE. */
1332 /* If op0 is a register, we need it in EXT_MODE to make it
1333 acceptable to the format of ext(z)v. */
1338 }
1340 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1341 "backwards" from the size of the unit we are extracting from.
1342 Otherwise, we count bits from the most significant on a
1343 BYTES/BITS_BIG_ENDIAN machine. */
1352 {
1353 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1354 between the mode of the extraction (word_mode) and the target
1355 mode. Instead, create a temporary and use convert_move to set
1356 the target. */
1359 {
1364 }
1365 else
1367 }
1374 {
1381 }
1383 }
1385 /* A subroutine of extract_bit_field, with the same arguments.
1386 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1387 if we can find no other means of implementing the operation.
1388 if FALLBACK_P is false, return NULL instead. */
1390 static rtx
1395 {
1397 machine_mode int_mode;
1398 machine_mode mode1;
1404 {
1407 }
1409 /* If we have an out-of-bounds access to a register, just return an
1410 uninitialized register of the required mode. This can occur if the
1411 source code contains an out-of-bounds access to a small array. */
1419 {
1420 /* We're trying to extract a full register from itself. */
1422 }
1424 /* See if we can get a better vector mode before extracting. */
1428 {
1429 machine_mode new_mode;
1441 else
1450 }
1452 /* Use vec_extract patterns for extracting parts of vectors whenever
1453 available. */
1459 {
1470 {
1475 }
1476 }
1478 /* Make sure we are playing with integral modes. Pun with subregs
1479 if we aren't. */
1480 {
1483 {
1487 {
1490 /* If we got a SUBREG, force it into a register since we
1491 aren't going to be able to do another SUBREG on it. */
1494 }
1496 {
1499 MODE_INT);
1505 }
1506 else
1507 {
1512 }
1513 }
1514 }
1516 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1517 If that's wrong, the solution is to test for it and set TARGET to 0
1518 if needed. */
1520 /* Get the mode of the field to use for atomic access or subreg
1521 conversion. */
1524 {
1529 }
1532 /* Extraction of a full MODE1 value can be done with a subreg as long
1533 as the least significant bit of the value is the least significant
1534 bit of either OP0 or a word of OP0. */
1539 {
1544 }
1546 /* Extraction of a full MODE1 value can be done with a load as long as
1547 the field is on a byte boundary and is sufficiently aligned. */
1549 {
1552 }
1554 /* Handle fields bigger than a word. */
1557 {
1558 /* Here we transfer the words of the field
1559 in the order least significant first.
1560 This is because the most significant word is the one which may
1561 be less than full. */
1571 /* Indicate for flow that the entire target reg is being set. */
1576 {
1577 /* If I is 0, use the low-order word in both field and target;
1578 if I is 1, use the next to lowest word; and so on. */
1579 /* Word number in TARGET to use. */
1580 unsigned int wordnum
1581 = (backwards
1584 /* Offset from start of field in OP0. */
1591 rtx result_part
1599 {
1602 }
1606 }
1609 {
1610 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1611 need to be zero'd out. */
1613 {
1618 emit_move_insn
1622 const0_rtx);
1623 }
1625 }
1627 /* Signed bit field: sign-extend with two arithmetic shifts. */
1632 }
1634 /* If OP0 is a multi-word register, narrow it to the affected word.
1635 If the region spans two words, defer to extract_split_bit_field. */
1637 {
1642 {
1647 }
1648 }
1650 /* From here on we know the desired field is smaller than a word.
1651 If OP0 is a register, it too fits within a word. */
1653 extraction_insn extv;
1655 /* ??? We could limit the structure size to the part of OP0 that
1656 contains the field, with appropriate checks for endianness
1657 and TRULY_NOOP_TRUNCATION. */
1660 tmode))
1661 {
1664 tmode);
1667 }
1669 /* If OP0 is a memory, try copying it to a register and seeing if a
1670 cheap register alternative is available. */
1672 {
1674 tmode))
1675 {
1679 tmode);
1682 }
1686 /* Try loading part of OP0 into a register and extracting the
1687 bitfield from that. */
1692 {
1700 }
1701 }
1706 /* Find a correspondingly-sized integer field, so we can apply
1707 shifts and masks to it. */
1711 /* Should probably push op0 out to memory and then do a load. */
1717 }
1719 /* Generate code to extract a byte-field from STR_RTX
1720 containing BITSIZE bits, starting at BITNUM,
1721 and put it in TARGET if possible (if TARGET is nonzero).
1722 Regardless of TARGET, we return the rtx for where the value is placed.
1724 STR_RTX is the structure containing the byte (a REG or MEM).
1725 UNSIGNEDP is nonzero if this is an unsigned bit field.
1726 MODE is the natural mode of the field value once extracted.
1727 TMODE is the mode the caller would like the value to have;
1728 but the value may be returned with type MODE instead.
1730 If a TARGET is specified and we can store in it at no extra cost,
1731 we do so, and return TARGET.
1732 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1733 if they are equally easy. */
1735 rtx
1739 {
1740 machine_mode mode1;
1742 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1747 else
1751 {
1752 rtx result;
1754 /* Extraction of a full MODE1 value can be done with a load as long as
1755 the field is on a byte boundary and is sufficiently aligned. */
1759 else
1760 {
1765 }
1768 }
1772 }
1773 \f
1774 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1775 from bit BITNUM of OP0.
1777 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1778 If TARGET is nonzero, attempts to store the value there
1779 and return TARGET, but this is not guaranteed.
1780 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1782 static rtx
1787 {
1789 {
1790 machine_mode mode
1795 /* The only way this should occur is if the field spans word
1796 boundaries. */
1800 }
1804 }
1806 /* Helper function for extract_fixed_bit_field, extracts
1807 the bit field always using the MODE of OP0. */
1809 static rtx
1814 {
1818 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1819 for invalid input, such as extract equivalent of f5 from
1820 gcc.dg/pr48335-2.c. */
1823 /* BITNUM is the distance between our msb and that of OP0.
1824 Convert it to the distance from the lsb. */
1827 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1828 We have reduced the big-endian case to the little-endian case. */
1831 {
1833 {
1834 /* If the field does not already start at the lsb,
1835 shift it so it does. */
1836 /* Maybe propagate the target for the shift. */
1841 }
1842 /* Convert the value to the desired mode. */
1846 /* Unless the msb of the field used to be the msb when we shifted,
1847 mask out the upper bits. */
1854 }
1856 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1857 then arithmetic-shift its lsb to the lsb of the word. */
1860 /* Find the narrowest integer mode that contains the field. */
1865 {
1868 }
1874 {
1876 /* Maybe propagate the target for the shift. */
1879 }
1883 }
1885 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1886 VALUE << BITPOS. */
1888 static rtx
1891 {
1893 }
1894 \f
1895 /* Extract a bit field that is split across two words
1896 and return an RTX for the result.
1898 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1899 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1900 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1902 static rtx
1905 {
1911 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1912 much at a time. */
1915 else
1919 {
1928 /* THISSIZE must not overrun a word boundary. Otherwise,
1929 extract_fixed_bit_field will call us again, and we will mutually
1930 recurse forever. */
1934 /* If OP0 is a register, then handle OFFSET here.
1936 When handling multiword bitfields, extract_bit_field may pass
1937 down a word_mode SUBREG of a larger REG for a bitfield that actually
1938 crosses a word boundary. Thus, for a SUBREG, we must find
1939 the current word starting from the base register. */
1941 {
1946 }
1948 {
1951 }
1952 else
1955 /* Extract the parts in bit-counting order,
1956 whose meaning is determined by BYTES_PER_UNIT.
1957 OFFSET is in UNITs, and UNIT is in bits. */
1962 /* Shift this part into place for the result. */
1964 {
1968 }
1969 else
1970 {
1974 }
1978 else
1979 /* Combine the parts with bitwise or. This works
1980 because we extracted each part as an unsigned bit field. */
1982 OPTAB_LIB_WIDEN);
1985 }
1987 /* Unsigned bit field: we are done. */
1990 /* Signed bit field: sign-extend with two arithmetic shifts. */
1995 }
1996 \f
1997 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
1998 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
1999 MODE, fill the upper bits with zeros. Fail if the layout of either
2000 mode is unknown (as for CC modes) or if the extraction would involve
2001 unprofitable mode punning. Return the value on success, otherwise
2002 return null.
2004 This is different from gen_lowpart* in these respects:
2006 - the returned value must always be considered an rvalue
2008 - when MODE is wider than SRC_MODE, the extraction involves
2009 a zero extension
2011 - when MODE is smaller than SRC_MODE, the extraction involves
2012 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2014 In other words, this routine performs a computation, whereas the
2015 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2016 operations. */
2018 rtx
2020 {
2027 {
2028 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2029 fails, it will happily create (subreg (symbol_ref)) or similar
2030 invalid SUBREGs. */
2042 }
2049 {
2053 }
2069 }
2070 \f
2071 /* Add INC into TARGET. */
2073 void
2075 {
2081 }
2083 /* Subtract DEC from TARGET. */
2085 void
2087 {
2093 }
2094 \f
2095 /* Output a shift instruction for expression code CODE,
2096 with SHIFTED being the rtx for the value to shift,
2097 and AMOUNT the rtx for the amount to shift by.
2098 Store the result in the rtx TARGET, if that is convenient.
2099 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2100 Return the rtx for where the value is. */
2102 static rtx
2105 {
2114 machine_mode op1_mode;
2124 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2125 shift amount is a vector, use the vector/vector shift patterns. */
2127 {
2133 }
2135 /* Previously detected shift-counts computed by NEGATE_EXPR
2136 and shifted in the other direction; but that does not work
2137 on all machines. */
2140 {
2151 }
2153 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2154 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2155 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2156 amount instead. */
2161 {
2165 }
2170 /* Check whether its cheaper to implement a left shift by a constant
2171 bit count by a sequence of additions. */
2180 {
2183 {
2187 }
2189 }
2192 {
2199 else
2203 {
2204 /* Widening does not work for rotation. */
2208 {
2209 /* If we have been unable to open-code this by a rotation,
2210 do it as the IOR of two shifts. I.e., to rotate A
2211 by N bits, compute
2212 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2213 where C is the bitsize of A.
2215 It is theoretically possible that the target machine might
2216 not be able to perform either shift and hence we would
2217 be making two libcalls rather than just the one for the
2218 shift (similarly if IOR could not be done). We will allow
2219 this extremely unlikely lossage to avoid complicating the
2220 code below. */
2224 rtx temp1;
2232 else
2233 {
2234 other_amount
2238 other_amount
2241 }
2252 }
2257 }
2263 /* Do arithmetic shifts.
2264 Also, if we are going to widen the operand, we can just as well
2265 use an arithmetic right-shift instead of a logical one. */
2268 {
2271 /* If trying to widen a log shift to an arithmetic shift,
2272 don't accept an arithmetic shift of the same size. */
2276 /* Arithmetic shift */
2281 }
2283 /* We used to try extzv here for logical right shifts, but that was
2284 only useful for one machine, the VAX, and caused poor code
2285 generation there for lshrdi3, so the code was deleted and a
2286 define_expand for lshrsi3 was added to vax.md. */
2287 }
2291 }
2293 /* Output a shift instruction for expression code CODE,
2294 with SHIFTED being the rtx for the value to shift,
2295 and AMOUNT the amount to shift by.
2296 Store the result in the rtx TARGET, if that is convenient.
2297 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2298 Return the rtx for where the value is. */
2300 rtx
2303 {
2306 }
2308 /* Output a shift instruction for expression code CODE,
2309 with SHIFTED being the rtx for the value to shift,
2310 and AMOUNT the tree for the amount to shift by.
2311 Store the result in the rtx TARGET, if that is convenient.
2312 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2313 Return the rtx for where the value is. */
2315 rtx
2318 {
2321 }
2323 \f
2324 /* Indicates the type of fixup needed after a constant multiplication.
2325 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2326 the result should be negated, and ADD_VARIANT means that the
2327 multiplicand should be added to the result. */
2341 /* Compute and return the best algorithm for multiplying by T.
2342 The algorithm must cost less than cost_limit
2343 If retval.cost >= COST_LIMIT, no algorithm was found and all
2344 other field of the returned struct are undefined.
2345 MODE is the machine mode of the multiplication. */
2347 static void
2350 {
2362 machine_mode imode;
2365 /* Indicate that no algorithm is yet found. If no algorithm
2366 is found, this value will be returned and indicate failure. */
2374 /* Be prepared for vector modes. */
2381 /* Restrict the bits of "t" to the multiplication's mode. */
2384 /* t == 1 can be done in zero cost. */
2386 {
2392 }
2394 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2395 fail now. */
2397 {
2400 else
2401 {
2407 }
2408 }
2410 /* We'll be needing a couple extra algorithm structures now. */
2416 /* Compute the hash index. */
2419 /* See if we already know what to do for T. */
2426 {
2430 {
2431 /* The cache tells us that it's impossible to synthesize
2432 multiplication by T within entry_ptr->cost. */
2434 /* COST_LIMIT is at least as restrictive as the one
2435 recorded in the hash table, in which case we have no
2436 hope of synthesizing a multiplication. Just
2437 return. */
2440 /* If we get here, COST_LIMIT is less restrictive than the
2441 one recorded in the hash table, so we may be able to
2442 synthesize a multiplication. Proceed as if we didn't
2443 have the cache entry. */
2444 }
2445 else
2446 {
2448 /* The cached algorithm shows that this multiplication
2449 requires more cost than COST_LIMIT. Just return. This
2450 way, we don't clobber this cache entry with
2451 alg_impossible but retain useful information. */
2457 {
2477 }
2478 }
2479 }
2481 /* If we have a group of zero bits at the low-order part of T, try
2482 multiplying by the remaining bits and then doing a shift. */
2485 {
2486 do_alg_shift:
2489 {
2491 /* The function expand_shift will choose between a shift and
2492 a sequence of additions, so the observed cost is given as
2493 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2504 {
2510 }
2512 /* See if treating ORIG_T as a signed number yields a better
2513 sequence. Try this sequence only for a negative ORIG_T
2514 as it would be useless for a non-negative ORIG_T. */
2516 {
2517 /* Shift ORIG_T as follows because a right shift of a
2518 negative-valued signed type is implementation
2519 defined. */
2521 /* The function expand_shift will choose between a shift
2522 and a sequence of additions, so the observed cost is
2523 given as MIN (m * add_cost(speed, mode),
2524 shift_cost(speed, mode, m)). */
2535 {
2541 }
2542 }
2543 }
2546 }
2548 /* If we have an odd number, add or subtract one. */
2550 {
2553 do_alg_addsub_t_m2:
2555 ;
2556 /* If T was -1, then W will be zero after the loop. This is another
2557 case where T ends with ...111. Handling this with (T + 1) and
2558 subtract 1 produces slightly better code and results in algorithm
2559 selection much faster than treating it like the ...0111 case
2560 below. */
2563 /* Reject the case where t is 3.
2564 Thus we prefer addition in that case. */
2566 {
2567 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2577 {
2583 }
2584 }
2585 else
2586 {
2587 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2597 {
2603 }
2604 }
2606 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2607 quickly with a - a * n for some appropriate constant n. */
2610 {
2620 {
2626 }
2627 }
2631 }
2633 /* Look for factors of t of the form
2634 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2635 If we find such a factor, we can multiply by t using an algorithm that
2636 multiplies by q, shift the result by m and add/subtract it to itself.
2638 We search for large factors first and loop down, even if large factors
2639 are less probable than small; if we find a large factor we will find a
2640 good sequence quickly, and therefore be able to prune (by decreasing
2641 COST_LIMIT) the search. */
2643 do_alg_addsub_factor:
2645 {
2651 {
2652 /* If the target has a cheap shift-and-add instruction use
2653 that in preference to a shift insn followed by an add insn.
2654 Assume that the shift-and-add is "atomic" with a latency
2655 equal to its cost, otherwise assume that on superscalar
2656 hardware the shift may be executed concurrently with the
2657 earlier steps in the algorithm. */
2660 {
2663 }
2664 else
2676 {
2682 }
2683 /* Other factors will have been taken care of in the recursion. */
2685 }
2690 {
2691 /* If the target has a cheap shift-and-subtract insn use
2692 that in preference to a shift insn followed by a sub insn.
2693 Assume that the shift-and-sub is "atomic" with a latency
2694 equal to it's cost, otherwise assume that on superscalar
2695 hardware the shift may be executed concurrently with the
2696 earlier steps in the algorithm. */
2699 {
2702 }
2703 else
2715 {
2721 }
2723 }
2724 }
2728 /* Try shift-and-add (load effective address) instructions,
2729 i.e. do a*3, a*5, a*9. */
2731 {
2732 do_alg_add_t2_m:
2737 {
2746 {
2752 }
2753 }
2757 do_alg_sub_t2_m:
2762 {
2771 {
2777 }
2778 }
2781 }
2783 done:
2784 /* If best_cost has not decreased, we have not found any algorithm. */
2786 {
2787 /* We failed to find an algorithm. Record alg_impossible for
2788 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2789 we are asked to find an algorithm for T within the same or
2790 lower COST_LIMIT, we can immediately return to the
2791 caller. */
2798 }
2800 /* Cache the result. */
2802 {
2809 }
2811 /* If we are getting a too long sequence for `struct algorithm'
2812 to record, make this search fail. */
2816 /* Copy the algorithm from temporary space to the space at alg_out.
2817 We avoid using structure assignment because the majority of
2818 best_alg is normally undefined, and this is a critical function. */
2825 }
2826 \f
2827 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2828 Try three variations:
2830 - a shift/add sequence based on VAL itself
2831 - a shift/add sequence based on -VAL, followed by a negation
2832 - a shift/add sequence based on VAL - 1, followed by an addition.
2834 Return true if the cheapest of these cost less than MULT_COST,
2835 describing the algorithm in *ALG and final fixup in *VARIANT. */
2837 static bool
2841 {
2847 /* Fail quickly for impossible bounds. */
2851 /* Ensure that mult_cost provides a reasonable upper bound.
2852 Any constant multiplication can be performed with less
2853 than 2 * bits additions. */
2863 /* This works only if the inverted value actually fits in an
2864 `unsigned int' */
2866 {
2869 {
2872 }
2873 else
2874 {
2877 }
2884 }
2886 /* This proves very useful for division-by-constant. */
2889 {
2892 }
2893 else
2894 {
2897 }
2906 }
2908 /* A subroutine of expand_mult, used for constant multiplications.
2909 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2910 convenient. Use the shift/add sequence described by ALG and apply
2911 the final fixup specified by VARIANT. */
2913 static rtx
2917 {
2918 HOST_WIDE_INT val_so_far;
2922 machine_mode nmode;
2924 /* Avoid referencing memory over and over and invalid sharing
2925 on SUBREGs. */
2928 /* ACCUM starts out either as OP0 or as a zero, depending on
2929 the first operation. */
2932 {
2935 }
2937 {
2940 }
2941 else
2945 {
2948 rtx add_target
2953 rtx accum_inner;
2956 {
2959 /* REG_EQUAL note will be attached to the following insn. */
3004 (add_target
3011 }
3014 {
3015 /* Write a REG_EQUAL note on the last insn so that we can cse
3016 multiplication sequences. Note that if ACCUM is a SUBREG,
3017 we've set the inner register and must properly indicate that. */
3021 {
3025 }
3031 accum_inner);
3032 }
3033 }
3036 {
3039 }
3041 {
3044 }
3046 /* Compare only the bits of val and val_so_far that are significant
3047 in the result mode, to avoid sign-/zero-extension confusion. */
3056 }
3058 /* Perform a multiplication and return an rtx for the result.
3059 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3060 TARGET is a suggestion for where to store the result (an rtx).
3062 We check specially for a constant integer as OP1.
3063 If you want this check for OP0 as well, then before calling
3064 you should swap the two operands if OP0 would be constant. */
3066 rtx
3069 {
3072 rtx scalar_op1;
3078 {
3082 }
3084 /* For vectors, there are several simplifications that can be made if
3085 all elements of the vector constant are identical. */
3088 {
3094 }
3097 {
3098 rtx fake_reg;
3099 HOST_WIDE_INT coeff;
3114 /* If mode is integer vector mode, check if the backend supports
3115 vector lshift (by scalar or vector) at all. If not, we can't use
3116 synthetized multiply. */
3122 /* These are the operations that are potentially turned into
3123 a sequence of shifts and additions. */
3126 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3127 less than or equal in size to `unsigned int' this doesn't matter.
3128 If the mode is larger than `unsigned int', then synth_mult works
3129 only if the constant value exactly fits in an `unsigned int' without
3130 any truncation. This means that multiplying by negative values does
3131 not work; results are off by 2^32 on a 32 bit machine. */
3133 {
3136 }
3137 #if TARGET_SUPPORTS_WIDE_INT
3139 #else
3141 #endif
3142 {
3144 /* Perfect power of 2 (other than 1, which is handled above). */
3148 else
3150 }
3151 else
3154 /* We used to test optimize here, on the grounds that it's better to
3155 produce a smaller program when -O is not used. But this causes
3156 such a terrible slowdown sometimes that it seems better to always
3157 use synth_mult. */
3159 /* Special case powers of two. */
3167 /* Attempt to handle multiplication of DImode values by negative
3168 coefficients, by performing the multiplication by a positive
3169 multiplier and then inverting the result. */
3171 {
3172 /* Its safe to use -coeff even for INT_MIN, as the
3173 result is interpreted as an unsigned coefficient.
3174 Exclude cost of op0 from max_cost to match the cost
3175 calculation of the synth_mult. */
3182 /* Special case powers of two. */
3184 {
3188 }
3191 max_cost))
3192 {
3196 }
3198 }
3200 /* Exclude cost of op0 from max_cost to match the cost
3201 calculation of the synth_mult. */
3206 }
3207 skip_synth:
3209 /* Expand x*2.0 as x+x. */
3211 {
3212 REAL_VALUE_TYPE d;
3216 {
3220 }
3221 }
3222 skip_scalar:
3224 /* This used to use umul_optab if unsigned, but for non-widening multiply
3225 there is no difference between signed and unsigned. */
3230 }
3232 /* Return a cost estimate for multiplying a register by the given
3233 COEFFicient in the given MODE and SPEED. */
3235 int
3237 {
3246 else
3248 }
3250 /* Perform a widening multiplication and return an rtx for the result.
3251 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3252 TARGET is a suggestion for where to store the result (an rtx).
3253 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3254 or smul_widen_optab.
3256 We check specially for a constant integer as OP1, comparing the
3257 cost of a widening multiply against the cost of a sequence of shifts
3258 and adds. */
3260 rtx
3263 {
3265 rtx cop1;
3274 {
3280 /* Special case powers of two. */
3282 {
3286 }
3288 /* Exclude cost of op0 from max_cost to match the cost
3289 calculation of the synth_mult. */
3292 max_cost))
3293 {
3297 }
3298 }
3301 }
3302 \f
3303 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3304 replace division by D, and put the least significant N bits of the result
3305 in *MULTIPLIER_PTR and return the most significant bit.
3307 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3308 needed precision is in PRECISION (should be <= N).
3310 PRECISION should be as small as possible so this function can choose
3311 multiplier more freely.
3313 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3314 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3316 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3317 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3319 unsigned HOST_WIDE_INT
3323 {
3327 /* lgup = ceil(log2(divisor)); */
3335 /* mlow = 2^(N + lgup)/d */
3339 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3343 /* If precision == N, then mlow, mhigh exceed 2^N
3344 (but they do not exceed 2^(N+1)). */
3346 /* Reduce to lowest terms. */
3348 {
3350 HOST_BITS_PER_WIDE_INT);
3352 HOST_BITS_PER_WIDE_INT);
3358 }
3363 {
3367 }
3368 else
3369 {
3372 }
3373 }
3375 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3376 congruent to 1 (mod 2**N). */
3378 static unsigned HOST_WIDE_INT
3380 {
3381 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3383 /* The algorithm notes that the choice y = x satisfies
3384 x*y == 1 mod 2^3, since x is assumed odd.
3385 Each iteration doubles the number of bits of significance in y. */
3396 {
3399 }
3401 }
3403 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3404 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3405 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3406 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3407 become signed.
3409 The result is put in TARGET if that is convenient.
3411 MODE is the mode of operation. */
3413 rtx
3416 {
3417 rtx tem;
3423 adj_operand
3425 adj_operand);
3431 target);
3434 }
3436 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3438 static rtx
3440 {
3441 machine_mode wider_mode;
3452 }
3454 /* Like expmed_mult_highpart, but only consider using a multiplication
3455 optab. OP1 is an rtx for the constant operand. */
3457 static rtx
3460 {
3462 machine_mode wider_mode;
3463 optab moptab;
3464 rtx tem;
3473 /* Firstly, try using a multiplication insn that only generates the needed
3474 high part of the product, and in the sign flavor of unsignedp. */
3476 {
3482 }
3484 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3485 Need to adjust the result after the multiplication. */
3490 {
3495 /* We used the wrong signedness. Adjust the result. */
3498 }
3500 /* Try widening multiplication. */
3504 {
3509 }
3511 /* Try widening the mode and perform a non-widening multiplication. */
3516 {
3520 /* We need to widen the operands, for example to ensure the
3521 constant multiplier is correctly sign or zero extended.
3522 Use a sequence to clean-up any instructions emitted by
3523 the conversions if things don't work out. */
3533 {
3536 }
3537 }
3539 /* Try widening multiplication of opposite signedness, and adjust. */
3546 {
3550 {
3552 /* We used the wrong signedness. Adjust the result. */
3555 }
3556 }
3559 }
3561 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3562 putting the high half of the result in TARGET if that is convenient,
3563 and return where the result is. If the operation can not be performed,
3564 0 is returned.
3566 MODE is the mode of operation and result.
3568 UNSIGNEDP nonzero means unsigned multiply.
3570 MAX_COST is the total allowed cost for the expanded RTL. */
3572 static rtx
3575 {
3582 rtx tem;
3586 /* We can't support modes wider than HOST_BITS_PER_INT. */
3591 /* We can't optimize modes wider than BITS_PER_WORD.
3592 ??? We might be able to perform double-word arithmetic if
3593 mode == word_mode, however all the cost calculations in
3594 synth_mult etc. assume single-word operations. */
3601 /* Check whether we try to multiply by a negative constant. */
3603 {
3606 }
3608 /* See whether shift/add multiplication is cheap enough. */
3611 {
3612 /* See whether the specialized multiplication optabs are
3613 cheaper than the shift/add version. */
3623 /* Adjust result for signedness. */
3628 }
3631 }
3634 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3636 static rtx
3638 {
3647 /* Avoid conditional branches when they're expensive. */
3650 {
3654 {
3659 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3660 which instruction sequence to use. If logical right shifts
3661 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3662 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3668 {
3680 }
3681 else
3682 {
3694 }
3696 }
3697 }
3699 /* Mask contains the mode's signbit and the significant bits of the
3700 modulus. By including the signbit in the operation, many targets
3701 can avoid an explicit compare operation in the following comparison
3702 against zero. */
3728 }
3730 /* Expand signed division of OP0 by a power of two D in mode MODE.
3731 This routine is only called for positive values of D. */
3733 static rtx
3735 {
3736 rtx temp;
3745 {
3751 }
3753 #ifdef HAVE_conditional_move
3756 {
3757 rtx temp2;
3765 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3769 {
3774 }
3776 }
3777 #endif
3781 {
3791 else
3797 }
3805 }
3806 \f
3807 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3808 if that is convenient, and returning where the result is.
3809 You may request either the quotient or the remainder as the result;
3810 specify REM_FLAG nonzero to get the remainder.
3812 CODE is the expression code for which kind of division this is;
3813 it controls how rounding is done. MODE is the machine mode to use.
3814 UNSIGNEDP nonzero means do unsigned division. */
3816 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3817 and then correct it by or'ing in missing high bits
3818 if result of ANDI is nonzero.
3819 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3820 This could optimize to a bfexts instruction.
3821 But C doesn't use these operations, so their optimizations are
3822 left for later. */
3823 /* ??? For modulo, we don't actually need the highpart of the first product,
3824 the low part will do nicely. And for small divisors, the second multiply
3825 can also be a low-part only multiply or even be completely left out.
3826 E.g. to calculate the remainder of a division by 3 with a 32 bit
3827 multiply, multiply with 0x55555556 and extract the upper two bits;
3828 the result is exact for inputs up to 0x1fffffff.
3829 The input range can be reduced by using cross-sum rules.
3830 For odd divisors >= 3, the following table gives right shift counts
3831 so that if a number is shifted by an integer multiple of the given
3832 amount, the remainder stays the same:
3833 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3834 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3835 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3836 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3837 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3839 Cross-sum rules for even numbers can be derived by leaving as many bits
3840 to the right alone as the divisor has zeros to the right.
3841 E.g. if x is an unsigned 32 bit number:
3842 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3843 */
3845 rtx
3848 {
3849 machine_mode compute_mode;
3850 rtx tquotient;
3863 {
3869 }
3871 /*
3872 This is the structure of expand_divmod:
3874 First comes code to fix up the operands so we can perform the operations
3875 correctly and efficiently.
3877 Second comes a switch statement with code specific for each rounding mode.
3878 For some special operands this code emits all RTL for the desired
3879 operation, for other cases, it generates only a quotient and stores it in
3880 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3881 to indicate that it has not done anything.
3883 Last comes code that finishes the operation. If QUOTIENT is set and
3884 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3885 QUOTIENT is not set, it is computed using trunc rounding.
3887 We try to generate special code for division and remainder when OP1 is a
3888 constant. If |OP1| = 2**n we can use shifts and some other fast
3889 operations. For other values of OP1, we compute a carefully selected
3890 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3891 by m.
3893 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3894 half of the product. Different strategies for generating the product are
3895 implemented in expmed_mult_highpart.
3897 If what we actually want is the remainder, we generate that by another
3898 by-constant multiplication and a subtraction. */
3900 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3901 code below will malfunction if we are, so check here and handle
3902 the special case if so. */
3906 /* When dividing by -1, we could get an overflow.
3907 negv_optab can handle overflows. */
3909 {
3914 }
3917 /* Don't use the function value register as a target
3918 since we have to read it as well as write it,
3919 and function-inlining gets confused by this. */
3921 /* Don't clobber an operand while doing a multi-step calculation. */
3929 /* Get the mode in which to perform this computation. Normally it will
3930 be MODE, but sometimes we can't do the desired operation in MODE.
3931 If so, pick a wider mode in which we can do the operation. Convert
3932 to that mode at the start to avoid repeated conversions.
3934 First see what operations we need. These depend on the expression
3935 we are evaluating. (We assume that divxx3 insns exist under the
3936 same conditions that modxx3 insns and that these insns don't normally
3937 fail. If these assumptions are not correct, we may generate less
3938 efficient code in some cases.)
3940 Then see if we find a mode in which we can open-code that operation
3941 (either a division, modulus, or shift). Finally, check for the smallest
3942 mode for which we can do the operation with a library call. */
3944 /* We might want to refine this now that we have division-by-constant
3945 optimization. Since expmed_mult_highpart tries so many variants, it is
3946 not straightforward to generalize this. Maybe we should make an array
3947 of possible modes in init_expmed? Save this for GCC 2.7. */
3953 ? optab1
3969 /* If we still couldn't find a mode, use MODE, but expand_binop will
3970 probably die. */
3976 else
3980 #if 0
3981 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3982 (mode), and thereby get better code when OP1 is a constant. Do that
3983 later. It will require going over all usages of SIZE below. */
3985 #endif
3987 /* Only deduct something for a REM if the last divide done was
3988 for a different constant. Then set the constant of the last
3989 divide. */
3990 max_cost = (unsignedp
4000 /* Now convert to the best mode to use. */
4002 {
4006 /* convert_modes may have placed op1 into a register, so we
4007 must recompute the following. */
4009 op1_is_pow2 = (op1_is_constant
4011 || (! unsignedp
4013 }
4015 /* If one of the operands is a volatile MEM, copy it into a register. */
4022 /* If we need the remainder or if OP1 is constant, we need to
4023 put OP0 in a register in case it has any queued subexpressions. */
4029 /* Promote floor rounding to trunc rounding for unsigned operations. */
4031 {
4038 }
4042 {
4046 {
4048 {
4056 {
4059 {
4060 unsigned HOST_WIDE_INT mask
4062 remainder
4066 OPTAB_LIB_WIDEN);
4069 }
4072 }
4074 {
4076 {
4077 /* Most significant bit of divisor is set; emit an scc
4078 insn. */
4081 }
4082 else
4083 {
4084 /* Find a suitable multiplier and right shift count
4085 instead of multiplying with D. */
4090 /* If the suggested multiplier is more than SIZE bits,
4091 we can do better for even divisors, using an
4092 initial right shift. */
4094 {
4100 }
4101 else
4105 {
4111 extra_cost
4115 t1 = expmed_mult_highpart
4123 NULL_RTX);
4128 NULL_RTX);
4129 quotient = expand_shift
4132 }
4133 else
4134 {
4141 t1 = expand_shift
4144 extra_cost
4147 t2 = expmed_mult_highpart
4153 quotient = expand_shift
4156 }
4157 }
4158 }
4166 quotient);
4167 }
4169 {
4172 rtx mlr;
4176 /* Since d might be INT_MIN, we have to cast to
4177 unsigned HOST_WIDE_INT before negating to avoid
4178 undefined signed overflow. */
4183 /* n rem d = n rem -d */
4185 {
4188 }
4197 {
4198 /* This case is not handled correctly below. */
4203 }
4205 && (rem_flag
4208 /* We assume that cheap metric is true if the
4209 optab has an expander for this mode. */
4212 compute_mode)
4215 compute_mode)
4217 ;
4219 {
4221 {
4225 }
4235 compute_mode),
4237 else
4240 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4241 negate the quotient. */
4243 {
4250 gen_int_mode
4252 compute_mode)),
4253 quotient);
4257 }
4258 }
4260 {
4264 {
4274 t1 = expmed_mult_highpart
4279 t2 = expand_shift
4282 t3 = expand_shift
4286 quotient
4289 tquotient);
4290 else
4291 quotient
4294 tquotient);
4295 }
4296 else
4297 {
4316 NULL_RTX);
4317 t3 = expand_shift
4320 t4 = expand_shift
4324 quotient
4327 tquotient);
4328 else
4329 quotient
4332 tquotient);
4333 }
4334 }
4342 quotient);
4343 }
4345 }
4346 fail1:
4352 /* We will come here only for signed operations. */
4354 {
4360 {
4361 /* We could just as easily deal with negative constants here,
4362 but it does not seem worth the trouble for GCC 2.6. */
4364 {
4367 {
4368 unsigned HOST_WIDE_INT mask
4370 remainder = expand_binop
4376 }
4377 quotient = expand_shift
4380 }
4381 else
4382 {
4391 {
4392 t1 = expand_shift
4400 t3 = expmed_mult_highpart
4404 {
4405 t4 = expand_shift
4410 OPTAB_WIDEN);
4411 }
4412 }
4413 }
4414 }
4415 else
4416 {
4422 nsign = expand_shift
4426 NULL_RTX);
4430 {
4431 rtx t5;
4436 tquotient);
4437 }
4438 }
4439 }
4445 /* Try using an instruction that produces both the quotient and
4446 remainder, using truncation. We can easily compensate the quotient
4447 or remainder to get floor rounding, once we have the remainder.
4448 Notice that we compute also the final remainder value here,
4449 and return the result right away. */
4454 {
4455 remainder
4458 }
4459 else
4460 {
4461 quotient
4464 }
4468 {
4469 /* This could be computed with a branch-less sequence.
4470 Save that for later. */
4471 rtx tem;
4481 }
4483 /* No luck with division elimination or divmod. Have to do it
4484 by conditionally adjusting op0 *and* the result. */
4485 {
4487 rtx adjusted_op0;
4488 rtx tem;
4526 }
4532 {
4534 {
4546 {
4553 }
4554 else
4557 tquotient);
4559 }
4561 /* Try using an instruction that produces both the quotient and
4562 remainder, using truncation. We can easily compensate the
4563 quotient or remainder to get ceiling rounding, once we have the
4564 remainder. Notice that we compute also the final remainder
4565 value here, and return the result right away. */
4570 {
4574 }
4575 else
4576 {
4580 }
4584 {
4585 /* This could be computed with a branch-less sequence.
4586 Save that for later. */
4594 }
4596 /* No luck with division elimination or divmod. Have to do it
4597 by conditionally adjusting op0 *and* the result. */
4598 {
4619 }
4620 }
4622 {
4625 {
4626 /* This is extremely similar to the code for the unsigned case
4627 above. For 2.7 we should merge these variants, but for
4628 2.6.1 I don't want to touch the code for unsigned since that
4629 get used in C. The signed case will only be used by other
4630 languages (Ada). */
4643 {
4650 }
4651 else
4654 tquotient);
4656 }
4658 /* Try using an instruction that produces both the quotient and
4659 remainder, using truncation. We can easily compensate the
4660 quotient or remainder to get ceiling rounding, once we have the
4661 remainder. Notice that we compute also the final remainder
4662 value here, and return the result right away. */
4666 {
4670 }
4671 else
4672 {
4676 }
4680 {
4681 /* This could be computed with a branch-less sequence.
4682 Save that for later. */
4683 rtx tem;
4694 }
4696 /* No luck with division elimination or divmod. Have to do it
4697 by conditionally adjusting op0 *and* the result. */
4698 {
4700 rtx adjusted_op0;
4701 rtx tem;
4741 }
4742 }
4747 {
4751 rtx t1;
4765 quotient);
4766 }
4772 {
4773 rtx tem;
4779 {
4780 rtx tem;
4786 }
4793 }
4794 else
4795 {
4802 {
4803 rtx tem;
4809 }
4830 }
4835 }
4838 {
4843 {
4844 /* Try to produce the remainder without producing the quotient.
4845 If we seem to have a divmod pattern that does not require widening,
4846 don't try widening here. We should really have a WIDEN argument
4847 to expand_twoval_binop, since what we'd really like to do here is
4848 1) try a mod insn in compute_mode
4849 2) try a divmod insn in compute_mode
4850 3) try a div insn in compute_mode and multiply-subtract to get
4851 remainder
4852 4) try the same things with widening allowed. */
4853 remainder
4856 unsignedp,
4861 {
4862 /* No luck there. Can we do remainder and divide at once
4863 without a library call? */
4866 ? udivmod_optab
4871 }
4875 }
4877 /* Produce the quotient. Try a quotient insn, but not a library call.
4878 If we have a divmod in this mode, use it in preference to widening
4879 the div (for this test we assume it will not fail). Note that optab2
4880 is set to the one of the two optabs that the call below will use. */
4881 quotient
4884 unsignedp,
4890 {
4891 /* No luck there. Try a quotient-and-remainder insn,
4892 keeping the quotient alone. */
4897 {
4900 /* Still no luck. If we are not computing the remainder,
4901 use a library call for the quotient. */
4906 }
4907 }
4908 }
4911 {
4916 {
4917 /* No divide instruction either. Use library for remainder. */
4921 /* No remainder function. Try a quotient-and-remainder
4922 function, keeping the remainder. */
4924 {
4932 }
4933 }
4934 else
4935 {
4936 /* We divided. Now finish doing X - Y * (X / Y). */
4941 OPTAB_LIB_WIDEN);
4942 }
4943 }
4946 }
4947 \f
4948 /* Return a tree node with data type TYPE, describing the value of X.
4949 Usually this is an VAR_DECL, if there is no obvious better choice.
4950 X may be an expression, however we only support those expressions
4951 generated by loop.c. */
4953 tree
4955 {
4956 tree t;
4959 {
4971 else
4972 {
4973 REAL_VALUE_TYPE d;
4977 }
4982 {
4988 /* Build a tree with vector elements. */
4991 {
4994 }
4997 }
5033 else
5058 /* else fall through. */
5063 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5064 address mode to pointer mode. */
5066 x = convert_memory_address_addr_space
5069 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5070 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5074 }
5075 }
5076 \f
5077 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5078 and returning TARGET.
5080 If TARGET is 0, a pseudo-register or constant is returned. */
5082 rtx
5084 {
5097 }
5099 /* Helper function for emit_store_flag. */
5100 static rtx
5104 machine_mode target_mode)
5105 {
5115 {
5118 }
5132 {
5135 }
5138 /* If we are converting to a wider mode, first convert to
5139 TARGET_MODE, then normalize. This produces better combining
5140 opportunities on machines that have a SIGN_EXTRACT when we are
5141 testing a single bit. This mostly benefits the 68k.
5143 If STORE_FLAG_VALUE does not have the sign bit set when
5144 interpreted in MODE, we can do this conversion as unsigned, which
5145 is usually more efficient. */
5147 {
5150 STORE_FLAG_VALUE));
5153 }
5154 else
5157 /* If we want to keep subexpressions around, don't reuse our last
5158 target. */
5162 /* Now normalize to the proper value in MODE. Sometimes we don't
5163 have to do anything. */
5165 ;
5166 /* STORE_FLAG_VALUE might be the most negative number, so write
5167 the comparison this way to avoid a compiler-time warning. */
5171 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5172 it hard to use a value of just the sign bit due to ANSI integer
5173 constant typing rules. */
5178 else
5179 {
5185 }
5187 /* If we were converting to a smaller mode, do the conversion now. */
5189 {
5192 }
5193 else
5195 }
5198 /* A subroutine of emit_store_flag only including "tricks" that do not
5199 need a recursive call. These are kept separate to avoid infinite
5200 loops. */
5202 static rtx
5205 machine_mode target_mode)
5206 {
5207 rtx subtarget;
5209 machine_mode compare_mode;
5212 rtx tem;
5218 /* If one operand is constant, make it the second one. Only do this
5219 if the other operand is not constant as well. */
5222 {
5227 }
5232 /* For some comparisons with 1 and -1, we can convert this to
5233 comparisons with zero. This will often produce more opportunities for
5234 store-flag insns. */
5237 {
5264 }
5266 /* If we are comparing a double-word integer with zero or -1, we can
5267 convert the comparison into one involving a single word. */
5271 {
5274 {
5277 /* Do a logical OR or AND of the two words and compare the
5278 result. */
5284 OPTAB_DIRECT);
5289 }
5291 {
5292 rtx op0h;
5294 /* If testing the sign bit, can just test on high word. */
5297 mode));
5300 }
5301 else
5305 {
5316 }
5317 }
5319 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5320 complement of A (for GE) and shifting the sign bit to the low bit. */
5325 {
5331 /* If the result is to be wider than OP0, it is best to convert it
5332 first. If it is to be narrower, it is *incorrect* to convert it
5333 first. */
5335 {
5338 }
5349 /* If we are supposed to produce a 0/1 value, we want to do
5350 a logical shift from the sign bit to the low-order bit; for
5351 a -1/0 value, we do an arithmetic shift. */
5360 }
5365 {
5369 {
5377 {
5382 }
5384 }
5385 }
5388 }
5390 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5391 and storing in TARGET. Normally return TARGET.
5392 Return 0 if that cannot be done.
5394 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5395 it is VOIDmode, they cannot both be CONST_INT.
5397 UNSIGNEDP is for the case where we have to widen the operands
5398 to perform the operation. It says to use zero-extension.
5400 NORMALIZEP is 1 if we should convert the result to be either zero
5401 or one. Normalize is -1 if we should convert the result to be
5402 either zero or -1. If NORMALIZEP is zero, the result will be left
5403 "raw" out of the scc insn. */
5405 rtx
5408 {
5411 rtx subtarget;
5415 /* If we compare constants, we shouldn't use a store-flag operation,
5416 but a constant load. We can get there via the vanilla route that
5417 usually generates a compare-branch sequence, but will in this case
5418 fold the comparison to a constant, and thus elide the branch. */
5423 target_mode);
5427 /* If we reached here, we can't do this with a scc insn, however there
5428 are some comparisons that can be done in other ways. Don't do any
5429 of these cases if branches are very cheap. */
5433 /* See what we need to return. We can only return a 1, -1, or the
5434 sign bit. */
5437 {
5442 ;
5443 else
5445 }
5449 /* If optimizing, use different pseudo registers for each insn, instead
5450 of reusing the same pseudo. This leads to better CSE, but slows
5451 down the compiler, since there are more pseudos */
5452 subtarget = (!optimize
5456 /* For floating-point comparisons, try the reverse comparison or try
5457 changing the "orderedness" of the comparison. */
5459 {
5468 {
5472 /* For the reverse comparison, use either an addition or a XOR. */
5476 {
5483 }
5487 {
5493 }
5494 }
5498 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5504 /* If there are no NaNs, the first comparison should always fall through.
5505 Effectively change the comparison to the other one. */
5507 {
5510 target_mode);
5511 }
5513 #ifdef HAVE_conditional_move
5514 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5515 conditional move. */
5524 else
5531 #else
5533 #endif
5534 }
5536 /* The remaining tricks only apply to integer comparisons. */
5541 /* If this is an equality comparison of integers, we can try to exclusive-or
5542 (or subtract) the two operands and use a recursive call to try the
5543 comparison with zero. Don't do any of these cases if branches are
5544 very cheap. */
5547 {
5549 OPTAB_WIDEN);
5553 OPTAB_WIDEN);
5561 }
5563 /* For integer comparisons, try the reverse comparison. However, for
5564 small X and if we'd have anyway to extend, implementing "X != 0"
5565 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5572 {
5576 /* Again, for the reverse comparison, use either an addition or a XOR. */
5580 {
5587 }
5591 {
5597 }
5602 }
5604 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5605 the constant zero. Reject all other comparisons at this point. Only
5606 do LE and GT if branches are expensive since they are expensive on
5607 2-operand machines. */
5615 /* Try to put the result of the comparison in the sign bit. Assume we can't
5616 do the necessary operation below. */
5620 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5621 the sign bit set. */
5624 {
5625 /* This is destructive, so SUBTARGET can't be OP0. */
5630 OPTAB_WIDEN);
5633 OPTAB_WIDEN);
5634 }
5636 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5637 number of bits in the mode of OP0, minus one. */
5640 {
5648 OPTAB_WIDEN);
5649 }
5652 {
5653 /* For EQ or NE, one way to do the comparison is to apply an operation
5654 that converts the operand into a positive number if it is nonzero
5655 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5656 for NE we negate. This puts the result in the sign bit. Then we
5657 normalize with a shift, if needed.
5659 Two operations that can do the above actions are ABS and FFS, so try
5660 them. If that doesn't work, and MODE is smaller than a full word,
5661 we can use zero-extension to the wider mode (an unsigned conversion)
5662 as the operation. */
5664 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5665 that is compensated by the subsequent overflow when subtracting
5666 one / negating. */
5673 {
5676 }
5679 {
5683 else
5685 }
5687 /* If we couldn't do it that way, for NE we can "or" the two's complement
5688 of the value with itself. For EQ, we take the one's complement of
5689 that "or", which is an extra insn, so we only handle EQ if branches
5690 are expensive. */
5696 {
5702 OPTAB_WIDEN);
5706 }
5707 }
5715 {
5717 ;
5719 {
5722 }
5724 {
5727 }
5728 }
5729 else
5733 }
5735 /* Like emit_store_flag, but always succeeds. */
5737 rtx
5740 {
5741 rtx tem;
5745 /* First see if emit_store_flag can do the job. */
5753 /* If this failed, we have to do this with set/compare/jump/set code.
5754 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5761 {
5768 }
5774 /* Jump in the right direction if the target cannot implement CODE
5775 but can jump on its reverse condition. */
5782 {
5786 else
5789 /* Canonicalize to UNORDERED for the libcall. */
5792 {
5796 }
5797 }
5808 }
5809 \f
5810 /* Perform possibly multi-word comparison and conditional jump to LABEL
5811 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5812 now a thin wrapper around do_compare_rtx_and_jump. */
5814 static void
5817 {
5821 }