1 ;; Constraint definitions for ARM and Thumb
2 ;; Copyright (C) 2006-2013 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The following register constraints have been used:
22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
23 ;; - in Thumb state: h, b
24 ;; - in both states: l, c, k, q
25 ;; In ARM state, 'l' is an alias for 'r'
26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
28 ;; The following normal constraints have been used:
29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
30 ;; in Thumb-1 state: I, J, K, L, M, N, O
31 ;; 'H' was previously used for FPA.
33 ;; The following multi-letter normal constraints have been used:
34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dz
35 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
36 ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
38 ;; The following memory constraints have been used:
39 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
41 ;; in Thumb state: Uu, Uw
44 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
45 "The VFP registers @code{s0}-@code{s31}.")
47 (define_register_constraint "w"
48 "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
49 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
51 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
52 "The VFP registers @code{d0}-@code{d7}.")
54 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
55 "The Intel iWMMX co-processor registers.")
57 (define_register_constraint "z"
58 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
59 "The Intel iWMMX GR registers.")
61 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
62 "In Thumb state the core registers @code{r0}-@code{r7}.")
64 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
65 "In Thumb state the core registers @code{r8}-@code{r15}.")
67 (define_constraint "j"
68 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
69 (and (match_test "TARGET_32BIT && arm_arch_thumb2")
70 (ior (match_code "high")
71 (and (match_code "const_int")
72 (match_test "(ival & 0xffff0000) == 0")))))
74 (define_constraint "Pj"
75 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
76 (and (match_code "const_int")
77 (and (match_test "TARGET_THUMB2")
78 (match_test "(ival & 0xfffff000) == 0"))))
80 (define_constraint "PJ"
81 "@internal A constant that satisfies the Pj constrant if negated."
82 (and (match_code "const_int")
83 (and (match_test "TARGET_THUMB2")
84 (match_test "((-ival) & 0xfffff000) == 0"))))
86 (define_register_constraint "k" "STACK_REG"
87 "@internal The stack register.")
89 (define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
90 "@internal In ARM state with LDRD support, core registers, otherwise general registers.")
92 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
94 Thumb only. The union of the low registers and the stack register.")
96 (define_register_constraint "c" "CC_REG"
97 "@internal The condition code register.")
99 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
100 "@internal The caller save registers. Useful for sibcalls.")
102 (define_constraint "I"
103 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
104 Data Processing instruction. In Thumb-1 state a constant in the range
106 (and (match_code "const_int")
107 (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
108 : ival >= 0 && ival <= 255")))
110 (define_constraint "J"
111 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
112 state a constant in the range @minus{}255-@minus{}1."
113 (and (match_code "const_int")
114 (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
115 : (ival >= -255 && ival <= -1)")))
117 (define_constraint "K"
118 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
119 inverted. In Thumb-1 state a constant that satisfies the @code{I}
120 constraint multiplied by any power of 2."
121 (and (match_code "const_int")
122 (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
123 : thumb_shiftable_const (ival)")))
125 (define_constraint "L"
126 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
127 negated. In Thumb-1 state a constant in the range @minus{}7-7."
128 (and (match_code "const_int")
129 (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
130 : (ival >= -7 && ival <= 7)")))
132 ;; The ARM state version is internal...
133 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
135 (define_constraint "M"
136 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
137 (and (match_code "const_int")
138 (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
139 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
140 : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
142 (define_constraint "N"
143 "Thumb-1 state a constant in the range 0-31."
144 (and (match_code "const_int")
145 (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
147 (define_constraint "O"
148 "In Thumb-1 state a constant that is a multiple of 4 in the range
150 (and (match_code "const_int")
151 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
152 && ((ival & 3) == 0)")))
154 (define_constraint "Pa"
155 "@internal In Thumb-1 state a constant in the range -510 to +510"
156 (and (match_code "const_int")
157 (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
158 && (ival > 255 || ival < -255)")))
160 (define_constraint "Pb"
161 "@internal In Thumb-1 state a constant in the range -262 to +262"
162 (and (match_code "const_int")
163 (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
164 && (ival > 255 || ival < -255)")))
166 (define_constraint "Pc"
167 "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
168 (and (match_code "const_int")
169 (match_test "TARGET_THUMB1
170 && ival > 1020 && ival <= 1275")))
172 (define_constraint "Pd"
173 "@internal In Thumb-1 state a constant in the range 0 to 7"
174 (and (match_code "const_int")
175 (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
177 (define_constraint "Pe"
178 "@internal In Thumb-1 state a constant in the range 256 to +510"
179 (and (match_code "const_int")
180 (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
182 (define_constraint "Ps"
183 "@internal In Thumb-2 state a constant in the range -255 to +255"
184 (and (match_code "const_int")
185 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
187 (define_constraint "Pt"
188 "@internal In Thumb-2 state a constant in the range -7 to +7"
189 (and (match_code "const_int")
190 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
192 (define_constraint "Pu"
193 "@internal In Thumb-2 state a constant in the range +1 to +8"
194 (and (match_code "const_int")
195 (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
197 (define_constraint "Pv"
198 "@internal In Thumb-2 state a constant in the range -255 to 0"
199 (and (match_code "const_int")
200 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
202 (define_constraint "Pw"
203 "@internal In Thumb-2 state a constant in the range -255 to -1"
204 (and (match_code "const_int")
205 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
207 (define_constraint "Px"
208 "@internal In Thumb-2 state a constant in the range -7 to -1"
209 (and (match_code "const_int")
210 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
212 (define_constraint "Py"
213 "@internal In Thumb-2 state a constant in the range 0 to 255"
214 (and (match_code "const_int")
215 (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
217 (define_constraint "G"
218 "In ARM/Thumb-2 state the floating-point constant 0."
219 (and (match_code "const_double")
220 (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
222 (define_constraint "Dz"
224 In ARM/Thumb-2 state a vector of constant zeros."
225 (and (match_code "const_vector")
226 (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
228 (define_constraint "Da"
230 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
231 be generated with two Data Processing insns."
232 (and (match_code "const_double,const_int,const_vector")
233 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
235 (define_constraint "Db"
237 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
238 be generated with three Data Processing insns."
239 (and (match_code "const_double,const_int,const_vector")
240 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
242 (define_constraint "Dc"
244 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
245 be generated with four Data Processing insns. This pattern is disabled
246 if optimizing for space or when we have load-delay slots to fill."
247 (and (match_code "const_double,const_int,const_vector")
248 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
249 && !(optimize_size || arm_ld_sched)")))
251 (define_constraint "Dd"
253 In ARM/Thumb-2 state a const_int that can be used by insn adddi."
254 (and (match_code "const_int")
255 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
257 (define_constraint "De"
259 In ARM/Thumb-2 state a const_int that can be used by insn anddi."
260 (and (match_code "const_int")
261 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))
263 (define_constraint "Df"
265 In ARM/Thumb-2 state a const_int that can be used by insn iordi."
266 (and (match_code "const_int")
267 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))
269 (define_constraint "Dg"
271 In ARM/Thumb-2 state a const_int that can be used by insn xordi."
272 (and (match_code "const_int")
273 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))
275 (define_constraint "Di"
277 In ARM/Thumb-2 state a const_int or const_double where both the high
278 and low SImode words can be generated as immediates in 32-bit instructions."
279 (and (match_code "const_double,const_int")
280 (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
282 (define_constraint "Dn"
284 In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
285 Neon vmov immediate instruction."
286 (and (match_code "const_vector,const_int")
287 (match_test "TARGET_32BIT
288 && imm_for_neon_mov_operand (op, GET_MODE (op))")))
290 (define_constraint "Dl"
292 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
294 (and (match_code "const_vector")
295 (match_test "TARGET_32BIT
296 && imm_for_neon_logic_operand (op, GET_MODE (op))")))
298 (define_constraint "DL"
300 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
302 (and (match_code "const_vector")
303 (match_test "TARGET_32BIT
304 && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
306 (define_constraint "Do"
308 In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
309 (and (match_code "const_int")
310 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
312 (define_constraint "Dv"
314 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
316 (and (match_code "const_double")
317 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
319 (define_constraint "Dy"
321 In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
323 (and (match_code "const_double")
324 (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
326 (define_constraint "Dt"
328 In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
329 (and (match_code "const_double")
330 (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
332 (define_memory_constraint "Ua"
334 An address valid for loading/storing register exclusive"
335 (match_operand 0 "mem_noofs_operand"))
337 (define_memory_constraint "Ut"
339 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
340 types wider than TImode."
341 (and (match_code "mem")
342 (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
344 (define_memory_constraint "Uv"
346 In ARM/Thumb-2 state a valid VFP load/store address."
347 (and (match_code "mem")
348 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
350 (define_memory_constraint "Uy"
352 In ARM/Thumb-2 state a valid iWMMX load/store address."
353 (and (match_code "mem")
354 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
356 (define_memory_constraint "Un"
358 In ARM/Thumb-2 state a valid address for Neon doubleword vector
359 load/store instructions."
360 (and (match_code "mem")
361 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
363 (define_memory_constraint "Um"
365 In ARM/Thumb-2 state a valid address for Neon element and structure
366 load/store instructions."
367 (and (match_code "mem")
368 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
370 (define_memory_constraint "Us"
372 In ARM/Thumb-2 state a valid address for non-offset loads/stores of
373 quad-word values in four ARM registers."
374 (and (match_code "mem")
375 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
377 (define_memory_constraint "Uq"
379 In ARM state an address valid in ldrsb instructions."
380 (and (match_code "mem")
381 (match_test "TARGET_ARM
382 && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
385 (define_memory_constraint "Q"
387 In ARM/Thumb-2 state an address that is a single base register."
388 (and (match_code "mem")
389 (match_test "REG_P (XEXP (op, 0))")))
391 (define_memory_constraint "Uu"
393 In Thumb state an address that is valid in 16bit encoding."
394 (and (match_code "mem")
395 (match_test "TARGET_THUMB
396 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
399 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
400 ; are actually LDM/STM instructions, so cannot be used to access unaligned
402 (define_memory_constraint "Uw"
404 In Thumb state an address that is valid in 16bit encoding, and that can be
405 used for unaligned accesses."
406 (and (match_code "mem")
407 (match_test "TARGET_THUMB
408 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
410 && GET_CODE (XEXP (op, 0)) != POST_INC")))
412 ;; We used to have constraint letters for S and R in ARM state, but
413 ;; all uses of these now appear to have been removed.
415 ;; Additionally, we used to have a Q constraint in Thumb state, but
416 ;; this wasn't really a valid memory constraint. Again, all uses of
417 ;; this now seem to have been removed.
419 (define_constraint "Ss"
421 Ss is a symbol reference."
422 (match_code "symbol_ref")