1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
26 #include "hash-table.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
42 #include "diagnostic-core.h"
49 #include "target-def.h"
51 #include "langhooks.h"
59 /* Forward definitions of types. */
60 typedef struct minipool_node Mnode
;
61 typedef struct minipool_fixup Mfix
;
63 void (*arm_lang_output_object_attributes_hook
)(void);
70 /* Forward function declarations. */
71 static bool arm_needs_doubleword_align (enum machine_mode
, const_tree
);
72 static int arm_compute_static_chain_stack_bytes (void);
73 static arm_stack_offsets
*arm_get_frame_offsets (void);
74 static void arm_add_gc_roots (void);
75 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
76 HOST_WIDE_INT
, rtx
, rtx
, int, int);
77 static unsigned bit_count (unsigned long);
78 static int arm_address_register_rtx_p (rtx
, int);
79 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
80 static int thumb2_legitimate_index_p (enum machine_mode
, rtx
, int);
81 static int thumb1_base_register_rtx_p (rtx
, enum machine_mode
, int);
82 static rtx
arm_legitimize_address (rtx
, rtx
, enum machine_mode
);
83 static reg_class_t
arm_preferred_reload_class (rtx
, reg_class_t
);
84 static rtx
thumb_legitimize_address (rtx
, rtx
, enum machine_mode
);
85 inline static int thumb1_index_register_rtx_p (rtx
, int);
86 static bool arm_legitimate_address_p (enum machine_mode
, rtx
, bool);
87 static int thumb_far_jump_used_p (void);
88 static bool thumb_force_lr_save (void);
89 static unsigned arm_size_return_regs (void);
90 static bool arm_assemble_integer (rtx
, unsigned int, int);
91 static void arm_print_operand (FILE *, rtx
, int);
92 static void arm_print_operand_address (FILE *, rtx
);
93 static bool arm_print_operand_punct_valid_p (unsigned char code
);
94 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
95 static arm_cc
get_arm_condition_code (rtx
);
96 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
97 static rtx
is_jump_table (rtx
);
98 static const char *output_multi_immediate (rtx
*, const char *, const char *,
100 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
101 static struct machine_function
*arm_init_machine_status (void);
102 static void thumb_exit (FILE *, int);
103 static rtx
is_jump_table (rtx
);
104 static HOST_WIDE_INT
get_jump_table_size (rtx
);
105 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
106 static Mnode
*add_minipool_forward_ref (Mfix
*);
107 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
108 static Mnode
*add_minipool_backward_ref (Mfix
*);
109 static void assign_minipool_offsets (Mfix
*);
110 static void arm_print_value (FILE *, rtx
);
111 static void dump_minipool (rtx
);
112 static int arm_barrier_cost (rtx
);
113 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
114 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
115 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
117 static void arm_reorg (void);
118 static void note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
119 static unsigned long arm_compute_save_reg0_reg12_mask (void);
120 static unsigned long arm_compute_save_reg_mask (void);
121 static unsigned long arm_isr_value (tree
);
122 static unsigned long arm_compute_func_type (void);
123 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
124 static tree
arm_handle_pcs_attribute (tree
*, tree
, tree
, int, bool *);
125 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
126 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
127 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
129 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
130 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
131 static int arm_comp_type_attributes (const_tree
, const_tree
);
132 static void arm_set_default_type_attributes (tree
);
133 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
134 static int arm_sched_reorder (FILE *, int, rtx
*, int *, int);
135 static int optimal_immediate_sequence (enum rtx_code code
,
136 unsigned HOST_WIDE_INT val
,
137 struct four_ints
*return_sequence
);
138 static int optimal_immediate_sequence_1 (enum rtx_code code
,
139 unsigned HOST_WIDE_INT val
,
140 struct four_ints
*return_sequence
,
142 static int arm_get_strip_length (int);
143 static bool arm_function_ok_for_sibcall (tree
, tree
);
144 static enum machine_mode
arm_promote_function_mode (const_tree
,
145 enum machine_mode
, int *,
147 static bool arm_return_in_memory (const_tree
, const_tree
);
148 static rtx
arm_function_value (const_tree
, const_tree
, bool);
149 static rtx
arm_libcall_value_1 (enum machine_mode
);
150 static rtx
arm_libcall_value (enum machine_mode
, const_rtx
);
151 static bool arm_function_value_regno_p (const unsigned int);
152 static void arm_internal_label (FILE *, const char *, unsigned long);
153 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
155 static bool arm_have_conditional_execution (void);
156 static bool arm_cannot_force_const_mem (enum machine_mode
, rtx
);
157 static bool arm_legitimate_constant_p (enum machine_mode
, rtx
);
158 static bool arm_rtx_costs_1 (rtx
, enum rtx_code
, int*, bool);
159 static bool arm_size_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *);
160 static bool arm_slowmul_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
161 static bool arm_fastmul_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
162 static bool arm_xscale_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
163 static bool arm_9e_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
164 static bool arm_rtx_costs (rtx
, int, int, int, int *, bool);
165 static int arm_address_cost (rtx
, enum machine_mode
, addr_space_t
, bool);
166 static int arm_register_move_cost (enum machine_mode
, reg_class_t
, reg_class_t
);
167 static int arm_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
168 static void arm_init_builtins (void);
169 static void arm_init_iwmmxt_builtins (void);
170 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
171 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
172 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
173 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
174 static tree
arm_builtin_decl (unsigned, bool);
175 static void emit_constant_insn (rtx cond
, rtx pattern
);
176 static rtx
emit_set_insn (rtx
, rtx
);
177 static rtx
emit_multi_reg_push (unsigned long);
178 static int arm_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
180 static rtx
arm_function_arg (cumulative_args_t
, enum machine_mode
,
182 static void arm_function_arg_advance (cumulative_args_t
, enum machine_mode
,
184 static unsigned int arm_function_arg_boundary (enum machine_mode
, const_tree
);
185 static rtx
aapcs_allocate_return_reg (enum machine_mode
, const_tree
,
187 static rtx
aapcs_libcall_value (enum machine_mode
);
188 static int aapcs_select_return_coproc (const_tree
, const_tree
);
190 #ifdef OBJECT_FORMAT_ELF
191 static void arm_elf_asm_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
192 static void arm_elf_asm_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
195 static void arm_encode_section_info (tree
, rtx
, int);
198 static void arm_file_end (void);
199 static void arm_file_start (void);
201 static void arm_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
,
203 static bool arm_pass_by_reference (cumulative_args_t
,
204 enum machine_mode
, const_tree
, bool);
205 static bool arm_promote_prototypes (const_tree
);
206 static bool arm_default_short_enums (void);
207 static bool arm_align_anon_bitfield (void);
208 static bool arm_return_in_msb (const_tree
);
209 static bool arm_must_pass_in_stack (enum machine_mode
, const_tree
);
210 static bool arm_return_in_memory (const_tree
, const_tree
);
212 static void arm_unwind_emit (FILE *, rtx
);
213 static bool arm_output_ttype (rtx
);
214 static void arm_asm_emit_except_personality (rtx
);
215 static void arm_asm_init_sections (void);
217 static rtx
arm_dwarf_register_span (rtx
);
219 static tree
arm_cxx_guard_type (void);
220 static bool arm_cxx_guard_mask_bit (void);
221 static tree
arm_get_cookie_size (tree
);
222 static bool arm_cookie_has_size (void);
223 static bool arm_cxx_cdtor_returns_this (void);
224 static bool arm_cxx_key_method_may_be_inline (void);
225 static void arm_cxx_determine_class_data_visibility (tree
);
226 static bool arm_cxx_class_data_always_comdat (void);
227 static bool arm_cxx_use_aeabi_atexit (void);
228 static void arm_init_libfuncs (void);
229 static tree
arm_build_builtin_va_list (void);
230 static void arm_expand_builtin_va_start (tree
, rtx
);
231 static tree
arm_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
232 static void arm_option_override (void);
233 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
234 static bool arm_cannot_copy_insn_p (rtx
);
235 static bool arm_tls_symbol_p (rtx x
);
236 static int arm_issue_rate (void);
237 static void arm_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
238 static bool arm_output_addr_const_extra (FILE *, rtx
);
239 static bool arm_allocate_stack_slots_for_args (void);
240 static bool arm_warn_func_return (tree
);
241 static const char *arm_invalid_parameter_type (const_tree t
);
242 static const char *arm_invalid_return_type (const_tree t
);
243 static tree
arm_promoted_type (const_tree t
);
244 static tree
arm_convert_to_type (tree type
, tree expr
);
245 static bool arm_scalar_mode_supported_p (enum machine_mode
);
246 static bool arm_frame_pointer_required (void);
247 static bool arm_can_eliminate (const int, const int);
248 static void arm_asm_trampoline_template (FILE *);
249 static void arm_trampoline_init (rtx
, tree
, rtx
);
250 static rtx
arm_trampoline_adjust_address (rtx
);
251 static rtx
arm_pic_static_addr (rtx orig
, rtx reg
);
252 static bool cortex_a9_sched_adjust_cost (rtx
, rtx
, rtx
, int *);
253 static bool xscale_sched_adjust_cost (rtx
, rtx
, rtx
, int *);
254 static bool fa726te_sched_adjust_cost (rtx
, rtx
, rtx
, int *);
255 static bool arm_array_mode_supported_p (enum machine_mode
,
256 unsigned HOST_WIDE_INT
);
257 static enum machine_mode
arm_preferred_simd_mode (enum machine_mode
);
258 static bool arm_class_likely_spilled_p (reg_class_t
);
259 static HOST_WIDE_INT
arm_vector_alignment (const_tree type
);
260 static bool arm_vector_alignment_reachable (const_tree type
, bool is_packed
);
261 static bool arm_builtin_support_vector_misalignment (enum machine_mode mode
,
265 static void arm_conditional_register_usage (void);
266 static reg_class_t
arm_preferred_rename_class (reg_class_t rclass
);
267 static unsigned int arm_autovectorize_vector_sizes (void);
268 static int arm_default_branch_cost (bool, bool);
269 static int arm_cortex_a5_branch_cost (bool, bool);
271 static bool arm_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
272 const unsigned char *sel
);
274 static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
276 int misalign ATTRIBUTE_UNUSED
);
277 static unsigned arm_add_stmt_cost (void *data
, int count
,
278 enum vect_cost_for_stmt kind
,
279 struct _stmt_vec_info
*stmt_info
,
281 enum vect_cost_model_location where
);
283 static void arm_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
284 bool op0_preserve_value
);
285 static unsigned HOST_WIDE_INT
arm_asan_shadow_offset (void);
287 /* Table of machine attributes. */
288 static const struct attribute_spec arm_attribute_table
[] =
290 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
291 affects_type_identity } */
292 /* Function calls made to this symbol must be done indirectly, because
293 it may lie outside of the 26 bit addressing range of a normal function
295 { "long_call", 0, 0, false, true, true, NULL
, false },
296 /* Whereas these functions are always known to reside within the 26 bit
298 { "short_call", 0, 0, false, true, true, NULL
, false },
299 /* Specify the procedure call conventions for a function. */
300 { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute
,
302 /* Interrupt Service Routines have special prologue and epilogue requirements. */
303 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
,
305 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
,
307 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
,
310 /* ARM/PE has three new attributes:
312 dllexport - for exporting a function/variable that will live in a dll
313 dllimport - for importing a function/variable from a dll
315 Microsoft allows multiple declspecs in one __declspec, separating
316 them with spaces. We do NOT support this. Instead, use __declspec
319 { "dllimport", 0, 0, true, false, false, NULL
, false },
320 { "dllexport", 0, 0, true, false, false, NULL
, false },
321 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
,
323 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
324 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
, false },
325 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
, false },
326 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
,
329 { NULL
, 0, 0, false, false, false, NULL
, false }
332 /* Initialize the GCC target structure. */
333 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
334 #undef TARGET_MERGE_DECL_ATTRIBUTES
335 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
338 #undef TARGET_LEGITIMIZE_ADDRESS
339 #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address
341 #undef TARGET_ATTRIBUTE_TABLE
342 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
344 #undef TARGET_ASM_FILE_START
345 #define TARGET_ASM_FILE_START arm_file_start
346 #undef TARGET_ASM_FILE_END
347 #define TARGET_ASM_FILE_END arm_file_end
349 #undef TARGET_ASM_ALIGNED_SI_OP
350 #define TARGET_ASM_ALIGNED_SI_OP NULL
351 #undef TARGET_ASM_INTEGER
352 #define TARGET_ASM_INTEGER arm_assemble_integer
354 #undef TARGET_PRINT_OPERAND
355 #define TARGET_PRINT_OPERAND arm_print_operand
356 #undef TARGET_PRINT_OPERAND_ADDRESS
357 #define TARGET_PRINT_OPERAND_ADDRESS arm_print_operand_address
358 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
359 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P arm_print_operand_punct_valid_p
361 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
362 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA arm_output_addr_const_extra
364 #undef TARGET_ASM_FUNCTION_PROLOGUE
365 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
367 #undef TARGET_ASM_FUNCTION_EPILOGUE
368 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
370 #undef TARGET_OPTION_OVERRIDE
371 #define TARGET_OPTION_OVERRIDE arm_option_override
373 #undef TARGET_COMP_TYPE_ATTRIBUTES
374 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
376 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
377 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
379 #undef TARGET_SCHED_ADJUST_COST
380 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
382 #undef TARGET_SCHED_REORDER
383 #define TARGET_SCHED_REORDER arm_sched_reorder
385 #undef TARGET_REGISTER_MOVE_COST
386 #define TARGET_REGISTER_MOVE_COST arm_register_move_cost
388 #undef TARGET_MEMORY_MOVE_COST
389 #define TARGET_MEMORY_MOVE_COST arm_memory_move_cost
391 #undef TARGET_ENCODE_SECTION_INFO
393 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
395 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
398 #undef TARGET_STRIP_NAME_ENCODING
399 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
401 #undef TARGET_ASM_INTERNAL_LABEL
402 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
404 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
405 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
407 #undef TARGET_FUNCTION_VALUE
408 #define TARGET_FUNCTION_VALUE arm_function_value
410 #undef TARGET_LIBCALL_VALUE
411 #define TARGET_LIBCALL_VALUE arm_libcall_value
413 #undef TARGET_FUNCTION_VALUE_REGNO_P
414 #define TARGET_FUNCTION_VALUE_REGNO_P arm_function_value_regno_p
416 #undef TARGET_ASM_OUTPUT_MI_THUNK
417 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
418 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
419 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
421 #undef TARGET_RTX_COSTS
422 #define TARGET_RTX_COSTS arm_rtx_costs
423 #undef TARGET_ADDRESS_COST
424 #define TARGET_ADDRESS_COST arm_address_cost
426 #undef TARGET_SHIFT_TRUNCATION_MASK
427 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
428 #undef TARGET_VECTOR_MODE_SUPPORTED_P
429 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
430 #undef TARGET_ARRAY_MODE_SUPPORTED_P
431 #define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
432 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
433 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
434 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
435 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
436 arm_autovectorize_vector_sizes
438 #undef TARGET_MACHINE_DEPENDENT_REORG
439 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
441 #undef TARGET_INIT_BUILTINS
442 #define TARGET_INIT_BUILTINS arm_init_builtins
443 #undef TARGET_EXPAND_BUILTIN
444 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
445 #undef TARGET_BUILTIN_DECL
446 #define TARGET_BUILTIN_DECL arm_builtin_decl
448 #undef TARGET_INIT_LIBFUNCS
449 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
451 #undef TARGET_PROMOTE_FUNCTION_MODE
452 #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode
453 #undef TARGET_PROMOTE_PROTOTYPES
454 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
455 #undef TARGET_PASS_BY_REFERENCE
456 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
457 #undef TARGET_ARG_PARTIAL_BYTES
458 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
459 #undef TARGET_FUNCTION_ARG
460 #define TARGET_FUNCTION_ARG arm_function_arg
461 #undef TARGET_FUNCTION_ARG_ADVANCE
462 #define TARGET_FUNCTION_ARG_ADVANCE arm_function_arg_advance
463 #undef TARGET_FUNCTION_ARG_BOUNDARY
464 #define TARGET_FUNCTION_ARG_BOUNDARY arm_function_arg_boundary
466 #undef TARGET_SETUP_INCOMING_VARARGS
467 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
469 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
470 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
472 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
473 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template
474 #undef TARGET_TRAMPOLINE_INIT
475 #define TARGET_TRAMPOLINE_INIT arm_trampoline_init
476 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
477 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
479 #undef TARGET_WARN_FUNC_RETURN
480 #define TARGET_WARN_FUNC_RETURN arm_warn_func_return
482 #undef TARGET_DEFAULT_SHORT_ENUMS
483 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
485 #undef TARGET_ALIGN_ANON_BITFIELD
486 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
488 #undef TARGET_NARROW_VOLATILE_BITFIELD
489 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
491 #undef TARGET_CXX_GUARD_TYPE
492 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
494 #undef TARGET_CXX_GUARD_MASK_BIT
495 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
497 #undef TARGET_CXX_GET_COOKIE_SIZE
498 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
500 #undef TARGET_CXX_COOKIE_HAS_SIZE
501 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
503 #undef TARGET_CXX_CDTOR_RETURNS_THIS
504 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
506 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
507 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
509 #undef TARGET_CXX_USE_AEABI_ATEXIT
510 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
512 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
513 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
514 arm_cxx_determine_class_data_visibility
516 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
517 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
519 #undef TARGET_RETURN_IN_MSB
520 #define TARGET_RETURN_IN_MSB arm_return_in_msb
522 #undef TARGET_RETURN_IN_MEMORY
523 #define TARGET_RETURN_IN_MEMORY arm_return_in_memory
525 #undef TARGET_MUST_PASS_IN_STACK
526 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
529 #undef TARGET_ASM_UNWIND_EMIT
530 #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit
532 /* EABI unwinding tables use a different format for the typeinfo tables. */
533 #undef TARGET_ASM_TTYPE
534 #define TARGET_ASM_TTYPE arm_output_ttype
536 #undef TARGET_ARM_EABI_UNWINDER
537 #define TARGET_ARM_EABI_UNWINDER true
539 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
540 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
542 #undef TARGET_ASM_INIT_SECTIONS
543 #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
544 #endif /* ARM_UNWIND_INFO */
546 #undef TARGET_DWARF_REGISTER_SPAN
547 #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
549 #undef TARGET_CANNOT_COPY_INSN_P
550 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
553 #undef TARGET_HAVE_TLS
554 #define TARGET_HAVE_TLS true
557 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
558 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
560 #undef TARGET_LEGITIMATE_CONSTANT_P
561 #define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
563 #undef TARGET_CANNOT_FORCE_CONST_MEM
564 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
566 #undef TARGET_MAX_ANCHOR_OFFSET
567 #define TARGET_MAX_ANCHOR_OFFSET 4095
569 /* The minimum is set such that the total size of the block
570 for a particular anchor is -4088 + 1 + 4095 bytes, which is
571 divisible by eight, ensuring natural spacing of anchors. */
572 #undef TARGET_MIN_ANCHOR_OFFSET
573 #define TARGET_MIN_ANCHOR_OFFSET -4088
575 #undef TARGET_SCHED_ISSUE_RATE
576 #define TARGET_SCHED_ISSUE_RATE arm_issue_rate
578 #undef TARGET_MANGLE_TYPE
579 #define TARGET_MANGLE_TYPE arm_mangle_type
581 #undef TARGET_BUILD_BUILTIN_VA_LIST
582 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
583 #undef TARGET_EXPAND_BUILTIN_VA_START
584 #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start
585 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
586 #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr
589 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
590 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
593 #undef TARGET_LEGITIMATE_ADDRESS_P
594 #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p
596 #undef TARGET_PREFERRED_RELOAD_CLASS
597 #define TARGET_PREFERRED_RELOAD_CLASS arm_preferred_reload_class
599 #undef TARGET_INVALID_PARAMETER_TYPE
600 #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
602 #undef TARGET_INVALID_RETURN_TYPE
603 #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
605 #undef TARGET_PROMOTED_TYPE
606 #define TARGET_PROMOTED_TYPE arm_promoted_type
608 #undef TARGET_CONVERT_TO_TYPE
609 #define TARGET_CONVERT_TO_TYPE arm_convert_to_type
611 #undef TARGET_SCALAR_MODE_SUPPORTED_P
612 #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p
614 #undef TARGET_FRAME_POINTER_REQUIRED
615 #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required
617 #undef TARGET_CAN_ELIMINATE
618 #define TARGET_CAN_ELIMINATE arm_can_eliminate
620 #undef TARGET_CONDITIONAL_REGISTER_USAGE
621 #define TARGET_CONDITIONAL_REGISTER_USAGE arm_conditional_register_usage
623 #undef TARGET_CLASS_LIKELY_SPILLED_P
624 #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p
626 #undef TARGET_VECTORIZE_BUILTINS
627 #define TARGET_VECTORIZE_BUILTINS
629 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
630 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
631 arm_builtin_vectorized_function
633 #undef TARGET_VECTOR_ALIGNMENT
634 #define TARGET_VECTOR_ALIGNMENT arm_vector_alignment
636 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
637 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
638 arm_vector_alignment_reachable
640 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
641 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
642 arm_builtin_support_vector_misalignment
644 #undef TARGET_PREFERRED_RENAME_CLASS
645 #define TARGET_PREFERRED_RENAME_CLASS \
646 arm_preferred_rename_class
648 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
649 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
650 arm_vectorize_vec_perm_const_ok
652 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
653 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
654 arm_builtin_vectorization_cost
655 #undef TARGET_VECTORIZE_ADD_STMT_COST
656 #define TARGET_VECTORIZE_ADD_STMT_COST arm_add_stmt_cost
658 #undef TARGET_CANONICALIZE_COMPARISON
659 #define TARGET_CANONICALIZE_COMPARISON \
660 arm_canonicalize_comparison
662 #undef TARGET_ASAN_SHADOW_OFFSET
663 #define TARGET_ASAN_SHADOW_OFFSET arm_asan_shadow_offset
665 #undef MAX_INSN_PER_IT_BLOCK
666 #define MAX_INSN_PER_IT_BLOCK (arm_restrict_it ? 1 : 4)
669 struct gcc_target targetm
= TARGET_INITIALIZER
;
671 /* Obstack for minipool constant handling. */
672 static struct obstack minipool_obstack
;
673 static char * minipool_startobj
;
675 /* The maximum number of insns skipped which
676 will be conditionalised if possible. */
677 static int max_insns_skipped
= 5;
679 extern FILE * asm_out_file
;
681 /* True if we are currently building a constant table. */
682 int making_const_table
;
684 /* The processor for which instructions should be scheduled. */
685 enum processor_type arm_tune
= arm_none
;
687 /* The current tuning set. */
688 const struct tune_params
*current_tune
;
690 /* Which floating point hardware to schedule for. */
693 /* Which floating popint hardware to use. */
694 const struct arm_fpu_desc
*arm_fpu_desc
;
696 /* Used for Thumb call_via trampolines. */
697 rtx thumb_call_via_label
[14];
698 static int thumb_call_reg_needed
;
700 /* Bit values used to identify processor capabilities. */
701 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
702 #define FL_ARCH3M (1 << 1) /* Extended multiply */
703 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
704 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
705 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
706 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
707 #define FL_THUMB (1 << 6) /* Thumb aware */
708 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
709 #define FL_STRONG (1 << 8) /* StrongARM */
710 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
711 #define FL_XSCALE (1 << 10) /* XScale */
712 /* spare (1 << 11) */
713 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
714 media instructions. */
715 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
716 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
717 Note: ARM6 & 7 derivatives only. */
718 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
719 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
720 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
722 #define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
723 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
724 #define FL_NEON (1 << 20) /* Neon instructions. */
725 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
727 #define FL_ARCH7 (1 << 22) /* Architecture 7. */
728 #define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
729 #define FL_ARCH8 (1 << 24) /* Architecture 8. */
731 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
732 #define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
734 /* Flags that only effect tuning, not available instructions. */
735 #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
738 #define FL_FOR_ARCH2 FL_NOTM
739 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
740 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
741 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
742 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
743 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
744 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
745 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
746 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
747 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
748 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
749 #define FL_FOR_ARCH6J FL_FOR_ARCH6
750 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
751 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
752 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
753 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
754 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
755 #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
756 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
757 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
758 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
759 #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
760 #define FL_FOR_ARCH8A (FL_FOR_ARCH7 | FL_ARCH6K | FL_ARCH8 | FL_THUMB_DIV \
761 | FL_ARM_DIV | FL_NOTM)
763 /* The bits in this mask specify which
764 instructions we are allowed to generate. */
765 static unsigned long insn_flags
= 0;
767 /* The bits in this mask specify which instruction scheduling options should
769 static unsigned long tune_flags
= 0;
771 /* The highest ARM architecture version supported by the
773 enum base_architecture arm_base_arch
= BASE_ARCH_0
;
775 /* The following are used in the arm.md file as equivalents to bits
776 in the above two flag variables. */
778 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
781 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
784 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
787 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
790 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
793 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
796 /* Nonzero if this chip supports the ARM 6K extensions. */
799 /* Nonzero if instructions present in ARMv6-M can be used. */
802 /* Nonzero if this chip supports the ARM 7 extensions. */
805 /* Nonzero if instructions not present in the 'M' profile can be used. */
806 int arm_arch_notm
= 0;
808 /* Nonzero if instructions present in ARMv7E-M can be used. */
811 /* Nonzero if instructions present in ARMv8 can be used. */
814 /* Nonzero if this chip can benefit from load scheduling. */
815 int arm_ld_sched
= 0;
817 /* Nonzero if this chip is a StrongARM. */
818 int arm_tune_strongarm
= 0;
820 /* Nonzero if this chip supports Intel Wireless MMX technology. */
821 int arm_arch_iwmmxt
= 0;
823 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
824 int arm_arch_iwmmxt2
= 0;
826 /* Nonzero if this chip is an XScale. */
827 int arm_arch_xscale
= 0;
829 /* Nonzero if tuning for XScale */
830 int arm_tune_xscale
= 0;
832 /* Nonzero if we want to tune for stores that access the write-buffer.
833 This typically means an ARM6 or ARM7 with MMU or MPU. */
834 int arm_tune_wbuf
= 0;
836 /* Nonzero if tuning for Cortex-A9. */
837 int arm_tune_cortex_a9
= 0;
839 /* Nonzero if generating Thumb instructions. */
842 /* Nonzero if generating Thumb-1 instructions. */
845 /* Nonzero if we should define __THUMB_INTERWORK__ in the
847 XXX This is a bit of a hack, it's intended to help work around
848 problems in GLD which doesn't understand that armv5t code is
849 interworking clean. */
850 int arm_cpp_interwork
= 0;
852 /* Nonzero if chip supports Thumb 2. */
855 /* Nonzero if chip supports integer division instruction. */
856 int arm_arch_arm_hwdiv
;
857 int arm_arch_thumb_hwdiv
;
859 /* Nonzero if we should use Neon to handle 64-bits operations rather
860 than core registers. */
861 int prefer_neon_for_64bits
= 0;
863 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
864 we must report the mode of the memory reference from
865 TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */
866 enum machine_mode output_memory_reference_mode
;
868 /* The register number to be used for the PIC offset register. */
869 unsigned arm_pic_register
= INVALID_REGNUM
;
871 /* Set to 1 after arm_reorg has started. Reset to start at the start of
872 the next function. */
873 static int after_arm_reorg
= 0;
875 enum arm_pcs arm_pcs_default
;
877 /* For an explanation of these variables, see final_prescan_insn below. */
879 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
880 enum arm_cond_code arm_current_cc
;
883 int arm_target_label
;
884 /* The number of conditionally executed insns, including the current insn. */
885 int arm_condexec_count
= 0;
886 /* A bitmask specifying the patterns for the IT block.
887 Zero means do not output an IT block before this insn. */
888 int arm_condexec_mask
= 0;
889 /* The number of bits used in arm_condexec_mask. */
890 int arm_condexec_masklen
= 0;
892 /* The condition codes of the ARM, and the inverse function. */
893 static const char * const arm_condition_codes
[] =
895 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
896 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
899 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
900 int arm_regs_in_sequence
[] =
902 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
905 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
906 #define streq(string1, string2) (strcmp (string1, string2) == 0)
908 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
909 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
910 | (1 << PIC_OFFSET_TABLE_REGNUM)))
912 /* Initialization code. */
916 const char *const name
;
917 enum processor_type core
;
919 enum base_architecture base_arch
;
920 const unsigned long flags
;
921 const struct tune_params
*const tune
;
925 #define ARM_PREFETCH_NOT_BENEFICIAL 0, -1, -1
926 #define ARM_PREFETCH_BENEFICIAL(prefetch_slots,l1_size,l1_line_size) \
931 /* arm generic vectorizer costs. */
933 struct cpu_vec_costs arm_default_vec_cost
= {
934 1, /* scalar_stmt_cost. */
935 1, /* scalar load_cost. */
936 1, /* scalar_store_cost. */
937 1, /* vec_stmt_cost. */
938 1, /* vec_to_scalar_cost. */
939 1, /* scalar_to_vec_cost. */
940 1, /* vec_align_load_cost. */
941 1, /* vec_unalign_load_cost. */
942 1, /* vec_unalign_store_cost. */
943 1, /* vec_store_cost. */
944 3, /* cond_taken_branch_cost. */
945 1, /* cond_not_taken_branch_cost. */
948 const struct tune_params arm_slowmul_tune
=
950 arm_slowmul_rtx_costs
,
952 3, /* Constant limit. */
953 5, /* Max cond insns. */
954 ARM_PREFETCH_NOT_BENEFICIAL
,
955 true, /* Prefer constant pool. */
956 arm_default_branch_cost
,
957 false, /* Prefer LDRD/STRD. */
958 {true, true}, /* Prefer non short circuit. */
959 &arm_default_vec_cost
, /* Vectorizer costs. */
960 false /* Prefer Neon for 64-bits bitops. */
963 const struct tune_params arm_fastmul_tune
=
965 arm_fastmul_rtx_costs
,
967 1, /* Constant limit. */
968 5, /* Max cond insns. */
969 ARM_PREFETCH_NOT_BENEFICIAL
,
970 true, /* Prefer constant pool. */
971 arm_default_branch_cost
,
972 false, /* Prefer LDRD/STRD. */
973 {true, true}, /* Prefer non short circuit. */
974 &arm_default_vec_cost
, /* Vectorizer costs. */
975 false /* Prefer Neon for 64-bits bitops. */
978 /* StrongARM has early execution of branches, so a sequence that is worth
979 skipping is shorter. Set max_insns_skipped to a lower value. */
981 const struct tune_params arm_strongarm_tune
=
983 arm_fastmul_rtx_costs
,
985 1, /* Constant limit. */
986 3, /* Max cond insns. */
987 ARM_PREFETCH_NOT_BENEFICIAL
,
988 true, /* Prefer constant pool. */
989 arm_default_branch_cost
,
990 false, /* Prefer LDRD/STRD. */
991 {true, true}, /* Prefer non short circuit. */
992 &arm_default_vec_cost
, /* Vectorizer costs. */
993 false /* Prefer Neon for 64-bits bitops. */
996 const struct tune_params arm_xscale_tune
=
998 arm_xscale_rtx_costs
,
999 xscale_sched_adjust_cost
,
1000 2, /* Constant limit. */
1001 3, /* Max cond insns. */
1002 ARM_PREFETCH_NOT_BENEFICIAL
,
1003 true, /* Prefer constant pool. */
1004 arm_default_branch_cost
,
1005 false, /* Prefer LDRD/STRD. */
1006 {true, true}, /* Prefer non short circuit. */
1007 &arm_default_vec_cost
, /* Vectorizer costs. */
1008 false /* Prefer Neon for 64-bits bitops. */
1011 const struct tune_params arm_9e_tune
=
1015 1, /* Constant limit. */
1016 5, /* Max cond insns. */
1017 ARM_PREFETCH_NOT_BENEFICIAL
,
1018 true, /* Prefer constant pool. */
1019 arm_default_branch_cost
,
1020 false, /* Prefer LDRD/STRD. */
1021 {true, true}, /* Prefer non short circuit. */
1022 &arm_default_vec_cost
, /* Vectorizer costs. */
1023 false /* Prefer Neon for 64-bits bitops. */
1026 const struct tune_params arm_v6t2_tune
=
1030 1, /* Constant limit. */
1031 5, /* Max cond insns. */
1032 ARM_PREFETCH_NOT_BENEFICIAL
,
1033 false, /* Prefer constant pool. */
1034 arm_default_branch_cost
,
1035 false, /* Prefer LDRD/STRD. */
1036 {true, true}, /* Prefer non short circuit. */
1037 &arm_default_vec_cost
, /* Vectorizer costs. */
1038 false /* Prefer Neon for 64-bits bitops. */
1041 /* Generic Cortex tuning. Use more specific tunings if appropriate. */
1042 const struct tune_params arm_cortex_tune
=
1046 1, /* Constant limit. */
1047 5, /* Max cond insns. */
1048 ARM_PREFETCH_NOT_BENEFICIAL
,
1049 false, /* Prefer constant pool. */
1050 arm_default_branch_cost
,
1051 false, /* Prefer LDRD/STRD. */
1052 {true, true}, /* Prefer non short circuit. */
1053 &arm_default_vec_cost
, /* Vectorizer costs. */
1054 false /* Prefer Neon for 64-bits bitops. */
1057 const struct tune_params arm_cortex_a15_tune
=
1061 1, /* Constant limit. */
1062 5, /* Max cond insns. */
1063 ARM_PREFETCH_NOT_BENEFICIAL
,
1064 false, /* Prefer constant pool. */
1065 arm_default_branch_cost
,
1066 true, /* Prefer LDRD/STRD. */
1067 {true, true}, /* Prefer non short circuit. */
1068 &arm_default_vec_cost
, /* Vectorizer costs. */
1069 false /* Prefer Neon for 64-bits bitops. */
1072 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
1073 less appealing. Set max_insns_skipped to a low value. */
1075 const struct tune_params arm_cortex_a5_tune
=
1079 1, /* Constant limit. */
1080 1, /* Max cond insns. */
1081 ARM_PREFETCH_NOT_BENEFICIAL
,
1082 false, /* Prefer constant pool. */
1083 arm_cortex_a5_branch_cost
,
1084 false, /* Prefer LDRD/STRD. */
1085 {false, false}, /* Prefer non short circuit. */
1086 &arm_default_vec_cost
, /* Vectorizer costs. */
1087 false /* Prefer Neon for 64-bits bitops. */
1090 const struct tune_params arm_cortex_a9_tune
=
1093 cortex_a9_sched_adjust_cost
,
1094 1, /* Constant limit. */
1095 5, /* Max cond insns. */
1096 ARM_PREFETCH_BENEFICIAL(4,32,32),
1097 false, /* Prefer constant pool. */
1098 arm_default_branch_cost
,
1099 false, /* Prefer LDRD/STRD. */
1100 {true, true}, /* Prefer non short circuit. */
1101 &arm_default_vec_cost
, /* Vectorizer costs. */
1102 false /* Prefer Neon for 64-bits bitops. */
1105 /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
1106 arm_v6t2_tune. It is used for cortex-m0, cortex-m1 and cortex-m0plus. */
1107 const struct tune_params arm_v6m_tune
=
1111 1, /* Constant limit. */
1112 5, /* Max cond insns. */
1113 ARM_PREFETCH_NOT_BENEFICIAL
,
1114 false, /* Prefer constant pool. */
1115 arm_default_branch_cost
,
1116 false, /* Prefer LDRD/STRD. */
1117 {false, false}, /* Prefer non short circuit. */
1118 &arm_default_vec_cost
, /* Vectorizer costs. */
1119 false /* Prefer Neon for 64-bits bitops. */
1122 const struct tune_params arm_fa726te_tune
=
1125 fa726te_sched_adjust_cost
,
1126 1, /* Constant limit. */
1127 5, /* Max cond insns. */
1128 ARM_PREFETCH_NOT_BENEFICIAL
,
1129 true, /* Prefer constant pool. */
1130 arm_default_branch_cost
,
1131 false, /* Prefer LDRD/STRD. */
1132 {true, true}, /* Prefer non short circuit. */
1133 &arm_default_vec_cost
, /* Vectorizer costs. */
1134 false /* Prefer Neon for 64-bits bitops. */
1138 /* Not all of these give usefully different compilation alternatives,
1139 but there is no simple way of generalizing them. */
1140 static const struct processors all_cores
[] =
1143 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
1144 {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH, \
1145 FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
1146 #include "arm-cores.def"
1148 {NULL
, arm_none
, NULL
, BASE_ARCH_0
, 0, NULL
}
1151 static const struct processors all_architectures
[] =
1153 /* ARM Architectures */
1154 /* We don't specify tuning costs here as it will be figured out
1157 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
1158 {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
1159 #include "arm-arches.def"
1161 {NULL
, arm_none
, NULL
, BASE_ARCH_0
, 0, NULL
}
1165 /* These are populated as commandline arguments are processed, or NULL
1166 if not specified. */
1167 static const struct processors
*arm_selected_arch
;
1168 static const struct processors
*arm_selected_cpu
;
1169 static const struct processors
*arm_selected_tune
;
1171 /* The name of the preprocessor macro to define for this architecture. */
1173 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
1175 /* Available values for -mfpu=. */
1177 static const struct arm_fpu_desc all_fpus
[] =
1179 #define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO) \
1180 { NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO },
1181 #include "arm-fpus.def"
1186 /* Supported TLS relocations. */
1194 TLS_DESCSEQ
/* GNU scheme */
1197 /* The maximum number of insns to be used when loading a constant. */
1199 arm_constant_limit (bool size_p
)
1201 return size_p
? 1 : current_tune
->constant_limit
;
1204 /* Emit an insn that's a simple single-set. Both the operands must be known
1207 emit_set_insn (rtx x
, rtx y
)
1209 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
1212 /* Return the number of bits set in VALUE. */
1214 bit_count (unsigned long value
)
1216 unsigned long count
= 0;
1221 value
&= value
- 1; /* Clear the least-significant set bit. */
1229 enum machine_mode mode
;
1231 } arm_fixed_mode_set
;
1233 /* A small helper for setting fixed-point library libfuncs. */
1236 arm_set_fixed_optab_libfunc (optab optable
, enum machine_mode mode
,
1237 const char *funcname
, const char *modename
,
1242 if (num_suffix
== 0)
1243 sprintf (buffer
, "__gnu_%s%s", funcname
, modename
);
1245 sprintf (buffer
, "__gnu_%s%s%d", funcname
, modename
, num_suffix
);
1247 set_optab_libfunc (optable
, mode
, buffer
);
1251 arm_set_fixed_conv_libfunc (convert_optab optable
, enum machine_mode to
,
1252 enum machine_mode from
, const char *funcname
,
1253 const char *toname
, const char *fromname
)
1256 const char *maybe_suffix_2
= "";
1258 /* Follow the logic for selecting a "2" suffix in fixed-bit.h. */
1259 if (ALL_FIXED_POINT_MODE_P (from
) && ALL_FIXED_POINT_MODE_P (to
)
1260 && UNSIGNED_FIXED_POINT_MODE_P (from
) == UNSIGNED_FIXED_POINT_MODE_P (to
)
1261 && ALL_FRACT_MODE_P (from
) == ALL_FRACT_MODE_P (to
))
1262 maybe_suffix_2
= "2";
1264 sprintf (buffer
, "__gnu_%s%s%s%s", funcname
, fromname
, toname
,
1267 set_conv_libfunc (optable
, to
, from
, buffer
);
1270 /* Set up library functions unique to ARM. */
1273 arm_init_libfuncs (void)
1275 /* For Linux, we have access to kernel support for atomic operations. */
1276 if (arm_abi
== ARM_ABI_AAPCS_LINUX
)
1277 init_sync_libfuncs (2 * UNITS_PER_WORD
);
1279 /* There are no special library functions unless we are using the
1284 /* The functions below are described in Section 4 of the "Run-Time
1285 ABI for the ARM architecture", Version 1.0. */
1287 /* Double-precision floating-point arithmetic. Table 2. */
1288 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
1289 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
1290 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
1291 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
1292 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
1294 /* Double-precision comparisons. Table 3. */
1295 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
1296 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
1297 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
1298 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
1299 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
1300 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
1301 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
1303 /* Single-precision floating-point arithmetic. Table 4. */
1304 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
1305 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
1306 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
1307 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
1308 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
1310 /* Single-precision comparisons. Table 5. */
1311 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
1312 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
1313 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
1314 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
1315 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
1316 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
1317 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
1319 /* Floating-point to integer conversions. Table 6. */
1320 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
1321 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
1322 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
1323 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
1324 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
1325 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
1326 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
1327 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
1329 /* Conversions between floating types. Table 7. */
1330 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
1331 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
1333 /* Integer to floating-point conversions. Table 8. */
1334 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
1335 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
1336 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
1337 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
1338 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
1339 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
1340 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
1341 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
1343 /* Long long. Table 9. */
1344 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
1345 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
1346 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
1347 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
1348 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
1349 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
1350 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
1351 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
1353 /* Integer (32/32->32) division. \S 4.3.1. */
1354 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
1355 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
1357 /* The divmod functions are designed so that they can be used for
1358 plain division, even though they return both the quotient and the
1359 remainder. The quotient is returned in the usual location (i.e.,
1360 r0 for SImode, {r0, r1} for DImode), just as would be expected
1361 for an ordinary division routine. Because the AAPCS calling
1362 conventions specify that all of { r0, r1, r2, r3 } are
1363 callee-saved registers, there is no need to tell the compiler
1364 explicitly that those registers are clobbered by these
1366 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
1367 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
1369 /* For SImode division the ABI provides div-without-mod routines,
1370 which are faster. */
1371 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
1372 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
1374 /* We don't have mod libcalls. Fortunately gcc knows how to use the
1375 divmod libcalls instead. */
1376 set_optab_libfunc (smod_optab
, DImode
, NULL
);
1377 set_optab_libfunc (umod_optab
, DImode
, NULL
);
1378 set_optab_libfunc (smod_optab
, SImode
, NULL
);
1379 set_optab_libfunc (umod_optab
, SImode
, NULL
);
1381 /* Half-precision float operations. The compiler handles all operations
1382 with NULL libfuncs by converting the SFmode. */
1383 switch (arm_fp16_format
)
1385 case ARM_FP16_FORMAT_IEEE
:
1386 case ARM_FP16_FORMAT_ALTERNATIVE
:
1389 set_conv_libfunc (trunc_optab
, HFmode
, SFmode
,
1390 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
1392 : "__gnu_f2h_alternative"));
1393 set_conv_libfunc (sext_optab
, SFmode
, HFmode
,
1394 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
1396 : "__gnu_h2f_alternative"));
1399 set_optab_libfunc (add_optab
, HFmode
, NULL
);
1400 set_optab_libfunc (sdiv_optab
, HFmode
, NULL
);
1401 set_optab_libfunc (smul_optab
, HFmode
, NULL
);
1402 set_optab_libfunc (neg_optab
, HFmode
, NULL
);
1403 set_optab_libfunc (sub_optab
, HFmode
, NULL
);
1406 set_optab_libfunc (eq_optab
, HFmode
, NULL
);
1407 set_optab_libfunc (ne_optab
, HFmode
, NULL
);
1408 set_optab_libfunc (lt_optab
, HFmode
, NULL
);
1409 set_optab_libfunc (le_optab
, HFmode
, NULL
);
1410 set_optab_libfunc (ge_optab
, HFmode
, NULL
);
1411 set_optab_libfunc (gt_optab
, HFmode
, NULL
);
1412 set_optab_libfunc (unord_optab
, HFmode
, NULL
);
1419 /* Use names prefixed with __gnu_ for fixed-point helper functions. */
1421 const arm_fixed_mode_set fixed_arith_modes
[] =
1442 const arm_fixed_mode_set fixed_conv_modes
[] =
1472 for (i
= 0; i
< ARRAY_SIZE (fixed_arith_modes
); i
++)
1474 arm_set_fixed_optab_libfunc (add_optab
, fixed_arith_modes
[i
].mode
,
1475 "add", fixed_arith_modes
[i
].name
, 3);
1476 arm_set_fixed_optab_libfunc (ssadd_optab
, fixed_arith_modes
[i
].mode
,
1477 "ssadd", fixed_arith_modes
[i
].name
, 3);
1478 arm_set_fixed_optab_libfunc (usadd_optab
, fixed_arith_modes
[i
].mode
,
1479 "usadd", fixed_arith_modes
[i
].name
, 3);
1480 arm_set_fixed_optab_libfunc (sub_optab
, fixed_arith_modes
[i
].mode
,
1481 "sub", fixed_arith_modes
[i
].name
, 3);
1482 arm_set_fixed_optab_libfunc (sssub_optab
, fixed_arith_modes
[i
].mode
,
1483 "sssub", fixed_arith_modes
[i
].name
, 3);
1484 arm_set_fixed_optab_libfunc (ussub_optab
, fixed_arith_modes
[i
].mode
,
1485 "ussub", fixed_arith_modes
[i
].name
, 3);
1486 arm_set_fixed_optab_libfunc (smul_optab
, fixed_arith_modes
[i
].mode
,
1487 "mul", fixed_arith_modes
[i
].name
, 3);
1488 arm_set_fixed_optab_libfunc (ssmul_optab
, fixed_arith_modes
[i
].mode
,
1489 "ssmul", fixed_arith_modes
[i
].name
, 3);
1490 arm_set_fixed_optab_libfunc (usmul_optab
, fixed_arith_modes
[i
].mode
,
1491 "usmul", fixed_arith_modes
[i
].name
, 3);
1492 arm_set_fixed_optab_libfunc (sdiv_optab
, fixed_arith_modes
[i
].mode
,
1493 "div", fixed_arith_modes
[i
].name
, 3);
1494 arm_set_fixed_optab_libfunc (udiv_optab
, fixed_arith_modes
[i
].mode
,
1495 "udiv", fixed_arith_modes
[i
].name
, 3);
1496 arm_set_fixed_optab_libfunc (ssdiv_optab
, fixed_arith_modes
[i
].mode
,
1497 "ssdiv", fixed_arith_modes
[i
].name
, 3);
1498 arm_set_fixed_optab_libfunc (usdiv_optab
, fixed_arith_modes
[i
].mode
,
1499 "usdiv", fixed_arith_modes
[i
].name
, 3);
1500 arm_set_fixed_optab_libfunc (neg_optab
, fixed_arith_modes
[i
].mode
,
1501 "neg", fixed_arith_modes
[i
].name
, 2);
1502 arm_set_fixed_optab_libfunc (ssneg_optab
, fixed_arith_modes
[i
].mode
,
1503 "ssneg", fixed_arith_modes
[i
].name
, 2);
1504 arm_set_fixed_optab_libfunc (usneg_optab
, fixed_arith_modes
[i
].mode
,
1505 "usneg", fixed_arith_modes
[i
].name
, 2);
1506 arm_set_fixed_optab_libfunc (ashl_optab
, fixed_arith_modes
[i
].mode
,
1507 "ashl", fixed_arith_modes
[i
].name
, 3);
1508 arm_set_fixed_optab_libfunc (ashr_optab
, fixed_arith_modes
[i
].mode
,
1509 "ashr", fixed_arith_modes
[i
].name
, 3);
1510 arm_set_fixed_optab_libfunc (lshr_optab
, fixed_arith_modes
[i
].mode
,
1511 "lshr", fixed_arith_modes
[i
].name
, 3);
1512 arm_set_fixed_optab_libfunc (ssashl_optab
, fixed_arith_modes
[i
].mode
,
1513 "ssashl", fixed_arith_modes
[i
].name
, 3);
1514 arm_set_fixed_optab_libfunc (usashl_optab
, fixed_arith_modes
[i
].mode
,
1515 "usashl", fixed_arith_modes
[i
].name
, 3);
1516 arm_set_fixed_optab_libfunc (cmp_optab
, fixed_arith_modes
[i
].mode
,
1517 "cmp", fixed_arith_modes
[i
].name
, 2);
1520 for (i
= 0; i
< ARRAY_SIZE (fixed_conv_modes
); i
++)
1521 for (j
= 0; j
< ARRAY_SIZE (fixed_conv_modes
); j
++)
1524 || (!ALL_FIXED_POINT_MODE_P (fixed_conv_modes
[i
].mode
)
1525 && !ALL_FIXED_POINT_MODE_P (fixed_conv_modes
[j
].mode
)))
1528 arm_set_fixed_conv_libfunc (fract_optab
, fixed_conv_modes
[i
].mode
,
1529 fixed_conv_modes
[j
].mode
, "fract",
1530 fixed_conv_modes
[i
].name
,
1531 fixed_conv_modes
[j
].name
);
1532 arm_set_fixed_conv_libfunc (satfract_optab
,
1533 fixed_conv_modes
[i
].mode
,
1534 fixed_conv_modes
[j
].mode
, "satfract",
1535 fixed_conv_modes
[i
].name
,
1536 fixed_conv_modes
[j
].name
);
1537 arm_set_fixed_conv_libfunc (fractuns_optab
,
1538 fixed_conv_modes
[i
].mode
,
1539 fixed_conv_modes
[j
].mode
, "fractuns",
1540 fixed_conv_modes
[i
].name
,
1541 fixed_conv_modes
[j
].name
);
1542 arm_set_fixed_conv_libfunc (satfractuns_optab
,
1543 fixed_conv_modes
[i
].mode
,
1544 fixed_conv_modes
[j
].mode
, "satfractuns",
1545 fixed_conv_modes
[i
].name
,
1546 fixed_conv_modes
[j
].name
);
1550 if (TARGET_AAPCS_BASED
)
1551 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
1554 /* On AAPCS systems, this is the "struct __va_list". */
1555 static GTY(()) tree va_list_type
;
1557 /* Return the type to use as __builtin_va_list. */
1559 arm_build_builtin_va_list (void)
1564 if (!TARGET_AAPCS_BASED
)
1565 return std_build_builtin_va_list ();
1567 /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type
1575 The C Library ABI further reinforces this definition in \S
1578 We must follow this definition exactly. The structure tag
1579 name is visible in C++ mangled names, and thus forms a part
1580 of the ABI. The field name may be used by people who
1581 #include <stdarg.h>. */
1582 /* Create the type. */
1583 va_list_type
= lang_hooks
.types
.make_type (RECORD_TYPE
);
1584 /* Give it the required name. */
1585 va_list_name
= build_decl (BUILTINS_LOCATION
,
1587 get_identifier ("__va_list"),
1589 DECL_ARTIFICIAL (va_list_name
) = 1;
1590 TYPE_NAME (va_list_type
) = va_list_name
;
1591 TYPE_STUB_DECL (va_list_type
) = va_list_name
;
1592 /* Create the __ap field. */
1593 ap_field
= build_decl (BUILTINS_LOCATION
,
1595 get_identifier ("__ap"),
1597 DECL_ARTIFICIAL (ap_field
) = 1;
1598 DECL_FIELD_CONTEXT (ap_field
) = va_list_type
;
1599 TYPE_FIELDS (va_list_type
) = ap_field
;
1600 /* Compute its layout. */
1601 layout_type (va_list_type
);
1603 return va_list_type
;
1606 /* Return an expression of type "void *" pointing to the next
1607 available argument in a variable-argument list. VALIST is the
1608 user-level va_list object, of type __builtin_va_list. */
1610 arm_extract_valist_ptr (tree valist
)
1612 if (TREE_TYPE (valist
) == error_mark_node
)
1613 return error_mark_node
;
1615 /* On an AAPCS target, the pointer is stored within "struct
1617 if (TARGET_AAPCS_BASED
)
1619 tree ap_field
= TYPE_FIELDS (TREE_TYPE (valist
));
1620 valist
= build3 (COMPONENT_REF
, TREE_TYPE (ap_field
),
1621 valist
, ap_field
, NULL_TREE
);
1627 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
1629 arm_expand_builtin_va_start (tree valist
, rtx nextarg
)
1631 valist
= arm_extract_valist_ptr (valist
);
1632 std_expand_builtin_va_start (valist
, nextarg
);
1635 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
1637 arm_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
1640 valist
= arm_extract_valist_ptr (valist
);
1641 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
1644 /* Fix up any incompatible options that the user has specified. */
1646 arm_option_override (void)
1648 if (global_options_set
.x_arm_arch_option
)
1649 arm_selected_arch
= &all_architectures
[arm_arch_option
];
1651 if (global_options_set
.x_arm_cpu_option
)
1652 arm_selected_cpu
= &all_cores
[(int) arm_cpu_option
];
1654 if (global_options_set
.x_arm_tune_option
)
1655 arm_selected_tune
= &all_cores
[(int) arm_tune_option
];
1657 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1658 SUBTARGET_OVERRIDE_OPTIONS
;
1661 if (arm_selected_arch
)
1663 if (arm_selected_cpu
)
1665 /* Check for conflict between mcpu and march. */
1666 if ((arm_selected_cpu
->flags
^ arm_selected_arch
->flags
) & ~FL_TUNE
)
1668 warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
1669 arm_selected_cpu
->name
, arm_selected_arch
->name
);
1670 /* -march wins for code generation.
1671 -mcpu wins for default tuning. */
1672 if (!arm_selected_tune
)
1673 arm_selected_tune
= arm_selected_cpu
;
1675 arm_selected_cpu
= arm_selected_arch
;
1679 arm_selected_arch
= NULL
;
1682 /* Pick a CPU based on the architecture. */
1683 arm_selected_cpu
= arm_selected_arch
;
1686 /* If the user did not specify a processor, choose one for them. */
1687 if (!arm_selected_cpu
)
1689 const struct processors
* sel
;
1690 unsigned int sought
;
1692 arm_selected_cpu
= &all_cores
[TARGET_CPU_DEFAULT
];
1693 if (!arm_selected_cpu
->name
)
1695 #ifdef SUBTARGET_CPU_DEFAULT
1696 /* Use the subtarget default CPU if none was specified by
1698 arm_selected_cpu
= &all_cores
[SUBTARGET_CPU_DEFAULT
];
1700 /* Default to ARM6. */
1701 if (!arm_selected_cpu
->name
)
1702 arm_selected_cpu
= &all_cores
[arm6
];
1705 sel
= arm_selected_cpu
;
1706 insn_flags
= sel
->flags
;
1708 /* Now check to see if the user has specified some command line
1709 switch that require certain abilities from the cpu. */
1712 if (TARGET_INTERWORK
|| TARGET_THUMB
)
1714 sought
|= (FL_THUMB
| FL_MODE32
);
1716 /* There are no ARM processors that support both APCS-26 and
1717 interworking. Therefore we force FL_MODE26 to be removed
1718 from insn_flags here (if it was set), so that the search
1719 below will always be able to find a compatible processor. */
1720 insn_flags
&= ~FL_MODE26
;
1723 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
1725 /* Try to locate a CPU type that supports all of the abilities
1726 of the default CPU, plus the extra abilities requested by
1728 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1729 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
1732 if (sel
->name
== NULL
)
1734 unsigned current_bit_count
= 0;
1735 const struct processors
* best_fit
= NULL
;
1737 /* Ideally we would like to issue an error message here
1738 saying that it was not possible to find a CPU compatible
1739 with the default CPU, but which also supports the command
1740 line options specified by the programmer, and so they
1741 ought to use the -mcpu=<name> command line option to
1742 override the default CPU type.
1744 If we cannot find a cpu that has both the
1745 characteristics of the default cpu and the given
1746 command line options we scan the array again looking
1747 for a best match. */
1748 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1749 if ((sel
->flags
& sought
) == sought
)
1753 count
= bit_count (sel
->flags
& insn_flags
);
1755 if (count
>= current_bit_count
)
1758 current_bit_count
= count
;
1762 gcc_assert (best_fit
);
1766 arm_selected_cpu
= sel
;
1770 gcc_assert (arm_selected_cpu
);
1771 /* The selected cpu may be an architecture, so lookup tuning by core ID. */
1772 if (!arm_selected_tune
)
1773 arm_selected_tune
= &all_cores
[arm_selected_cpu
->core
];
1775 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", arm_selected_cpu
->arch
);
1776 insn_flags
= arm_selected_cpu
->flags
;
1777 arm_base_arch
= arm_selected_cpu
->base_arch
;
1779 arm_tune
= arm_selected_tune
->core
;
1780 tune_flags
= arm_selected_tune
->flags
;
1781 current_tune
= arm_selected_tune
->tune
;
1783 /* Make sure that the processor choice does not conflict with any of the
1784 other command line choices. */
1785 if (TARGET_ARM
&& !(insn_flags
& FL_NOTM
))
1786 error ("target CPU does not support ARM mode");
1788 /* BPABI targets use linker tricks to allow interworking on cores
1789 without thumb support. */
1790 if (TARGET_INTERWORK
&& !((insn_flags
& FL_THUMB
) || TARGET_BPABI
))
1792 warning (0, "target CPU does not support interworking" );
1793 target_flags
&= ~MASK_INTERWORK
;
1796 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1798 warning (0, "target CPU does not support THUMB instructions");
1799 target_flags
&= ~MASK_THUMB
;
1802 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1804 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1805 target_flags
&= ~MASK_APCS_FRAME
;
1808 /* Callee super interworking implies thumb interworking. Adding
1809 this to the flags here simplifies the logic elsewhere. */
1810 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1811 target_flags
|= MASK_INTERWORK
;
1813 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1814 from here where no function is being compiled currently. */
1815 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1816 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1818 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1819 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1821 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1823 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1824 target_flags
|= MASK_APCS_FRAME
;
1827 if (TARGET_POKE_FUNCTION_NAME
)
1828 target_flags
|= MASK_APCS_FRAME
;
1830 if (TARGET_APCS_REENT
&& flag_pic
)
1831 error ("-fpic and -mapcs-reent are incompatible");
1833 if (TARGET_APCS_REENT
)
1834 warning (0, "APCS reentrant code not supported. Ignored");
1836 /* If this target is normally configured to use APCS frames, warn if they
1837 are turned off and debugging is turned on. */
1839 && write_symbols
!= NO_DEBUG
1840 && !TARGET_APCS_FRAME
1841 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1842 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1844 if (TARGET_APCS_FLOAT
)
1845 warning (0, "passing floating point arguments in fp regs not yet supported");
1847 if (TARGET_LITTLE_WORDS
)
1848 warning (OPT_Wdeprecated
, "%<mwords-little-endian%> is deprecated and "
1849 "will be removed in a future release");
1851 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1852 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1853 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1854 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1855 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1856 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1857 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1858 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1859 arm_arch_notm
= (insn_flags
& FL_NOTM
) != 0;
1860 arm_arch6m
= arm_arch6
&& !arm_arch_notm
;
1861 arm_arch7
= (insn_flags
& FL_ARCH7
) != 0;
1862 arm_arch7em
= (insn_flags
& FL_ARCH7EM
) != 0;
1863 arm_arch8
= (insn_flags
& FL_ARCH8
) != 0;
1864 arm_arch_thumb2
= (insn_flags
& FL_THUMB2
) != 0;
1865 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1867 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1868 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1869 thumb_code
= TARGET_ARM
== 0;
1870 thumb1_code
= TARGET_THUMB1
!= 0;
1871 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1872 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1873 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1874 arm_arch_iwmmxt2
= (insn_flags
& FL_IWMMXT2
) != 0;
1875 arm_arch_thumb_hwdiv
= (insn_flags
& FL_THUMB_DIV
) != 0;
1876 arm_arch_arm_hwdiv
= (insn_flags
& FL_ARM_DIV
) != 0;
1877 arm_tune_cortex_a9
= (arm_tune
== cortexa9
) != 0;
1878 if (arm_restrict_it
== 2)
1879 arm_restrict_it
= arm_arch8
&& TARGET_THUMB2
;
1882 arm_restrict_it
= 0;
1884 /* If we are not using the default (ARM mode) section anchor offset
1885 ranges, then set the correct ranges now. */
1888 /* Thumb-1 LDR instructions cannot have negative offsets.
1889 Permissible positive offset ranges are 5-bit (for byte loads),
1890 6-bit (for halfword loads), or 7-bit (for word loads).
1891 Empirical results suggest a 7-bit anchor range gives the best
1892 overall code size. */
1893 targetm
.min_anchor_offset
= 0;
1894 targetm
.max_anchor_offset
= 127;
1896 else if (TARGET_THUMB2
)
1898 /* The minimum is set such that the total size of the block
1899 for a particular anchor is 248 + 1 + 4095 bytes, which is
1900 divisible by eight, ensuring natural spacing of anchors. */
1901 targetm
.min_anchor_offset
= -248;
1902 targetm
.max_anchor_offset
= 4095;
1905 /* V5 code we generate is completely interworking capable, so we turn off
1906 TARGET_INTERWORK here to avoid many tests later on. */
1908 /* XXX However, we must pass the right pre-processor defines to CPP
1909 or GLD can get confused. This is a hack. */
1910 if (TARGET_INTERWORK
)
1911 arm_cpp_interwork
= 1;
1914 target_flags
&= ~MASK_INTERWORK
;
1916 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1917 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1919 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1920 error ("iwmmxt abi requires an iwmmxt capable cpu");
1922 if (!global_options_set
.x_arm_fpu_index
)
1924 const char *target_fpu_name
;
1927 #ifdef FPUTYPE_DEFAULT
1928 target_fpu_name
= FPUTYPE_DEFAULT
;
1930 target_fpu_name
= "vfp";
1933 ok
= opt_enum_arg_to_value (OPT_mfpu_
, target_fpu_name
, &arm_fpu_index
,
1938 arm_fpu_desc
= &all_fpus
[arm_fpu_index
];
1940 switch (arm_fpu_desc
->model
)
1942 case ARM_FP_MODEL_VFP
:
1943 arm_fpu_attr
= FPU_VFP
;
1950 if (TARGET_AAPCS_BASED
)
1952 if (TARGET_CALLER_INTERWORKING
)
1953 error ("AAPCS does not support -mcaller-super-interworking");
1955 if (TARGET_CALLEE_INTERWORKING
)
1956 error ("AAPCS does not support -mcallee-super-interworking");
1959 /* iWMMXt and NEON are incompatible. */
1960 if (TARGET_IWMMXT
&& TARGET_NEON
)
1961 error ("iWMMXt and NEON are incompatible");
1963 /* iWMMXt unsupported under Thumb mode. */
1964 if (TARGET_THUMB
&& TARGET_IWMMXT
)
1965 error ("iWMMXt unsupported under Thumb mode");
1967 /* __fp16 support currently assumes the core has ldrh. */
1968 if (!arm_arch4
&& arm_fp16_format
!= ARM_FP16_FORMAT_NONE
)
1969 sorry ("__fp16 and no ldrh");
1971 /* If soft-float is specified then don't use FPU. */
1972 if (TARGET_SOFT_FLOAT
)
1973 arm_fpu_attr
= FPU_NONE
;
1975 if (TARGET_AAPCS_BASED
)
1977 if (arm_abi
== ARM_ABI_IWMMXT
)
1978 arm_pcs_default
= ARM_PCS_AAPCS_IWMMXT
;
1979 else if (arm_float_abi
== ARM_FLOAT_ABI_HARD
1980 && TARGET_HARD_FLOAT
1982 arm_pcs_default
= ARM_PCS_AAPCS_VFP
;
1984 arm_pcs_default
= ARM_PCS_AAPCS
;
1988 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1989 sorry ("-mfloat-abi=hard and VFP");
1991 if (arm_abi
== ARM_ABI_APCS
)
1992 arm_pcs_default
= ARM_PCS_APCS
;
1994 arm_pcs_default
= ARM_PCS_ATPCS
;
1997 /* For arm2/3 there is no need to do any scheduling if we are doing
1998 software floating-point. */
1999 if (TARGET_SOFT_FLOAT
&& (tune_flags
& FL_MODE32
) == 0)
2000 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
2002 /* Use the cp15 method if it is available. */
2003 if (target_thread_pointer
== TP_AUTO
)
2005 if (arm_arch6k
&& !TARGET_THUMB1
)
2006 target_thread_pointer
= TP_CP15
;
2008 target_thread_pointer
= TP_SOFT
;
2011 if (TARGET_HARD_TP
&& TARGET_THUMB1
)
2012 error ("can not use -mtp=cp15 with 16-bit Thumb");
2014 /* Override the default structure alignment for AAPCS ABI. */
2015 if (!global_options_set
.x_arm_structure_size_boundary
)
2017 if (TARGET_AAPCS_BASED
)
2018 arm_structure_size_boundary
= 8;
2022 if (arm_structure_size_boundary
!= 8
2023 && arm_structure_size_boundary
!= 32
2024 && !(ARM_DOUBLEWORD_ALIGN
&& arm_structure_size_boundary
== 64))
2026 if (ARM_DOUBLEWORD_ALIGN
)
2028 "structure size boundary can only be set to 8, 32 or 64");
2030 warning (0, "structure size boundary can only be set to 8 or 32");
2031 arm_structure_size_boundary
2032 = (TARGET_AAPCS_BASED
? 8 : DEFAULT_STRUCTURE_SIZE_BOUNDARY
);
2036 if (!TARGET_ARM
&& TARGET_VXWORKS_RTP
&& flag_pic
)
2038 error ("RTP PIC is incompatible with Thumb");
2042 /* If stack checking is disabled, we can use r10 as the PIC register,
2043 which keeps r9 available. The EABI specifies r9 as the PIC register. */
2044 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
2046 if (TARGET_VXWORKS_RTP
)
2047 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
2048 arm_pic_register
= (TARGET_APCS_STACK
|| TARGET_AAPCS_BASED
) ? 9 : 10;
2051 if (flag_pic
&& TARGET_VXWORKS_RTP
)
2052 arm_pic_register
= 9;
2054 if (arm_pic_register_string
!= NULL
)
2056 int pic_register
= decode_reg_name (arm_pic_register_string
);
2059 warning (0, "-mpic-register= is useless without -fpic");
2061 /* Prevent the user from choosing an obviously stupid PIC register. */
2062 else if (pic_register
< 0 || call_used_regs
[pic_register
]
2063 || pic_register
== HARD_FRAME_POINTER_REGNUM
2064 || pic_register
== STACK_POINTER_REGNUM
2065 || pic_register
>= PC_REGNUM
2066 || (TARGET_VXWORKS_RTP
2067 && (unsigned int) pic_register
!= arm_pic_register
))
2068 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
2070 arm_pic_register
= pic_register
;
2073 /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
2074 if (fix_cm3_ldrd
== 2)
2076 if (arm_selected_cpu
->core
== cortexm3
)
2082 /* Enable -munaligned-access by default for
2083 - all ARMv6 architecture-based processors
2084 - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
2085 - ARMv8 architecture-base processors.
2087 Disable -munaligned-access by default for
2088 - all pre-ARMv6 architecture-based processors
2089 - ARMv6-M architecture-based processors. */
2091 if (unaligned_access
== 2)
2093 if (arm_arch6
&& (arm_arch_notm
|| arm_arch7
))
2094 unaligned_access
= 1;
2096 unaligned_access
= 0;
2098 else if (unaligned_access
== 1
2099 && !(arm_arch6
&& (arm_arch_notm
|| arm_arch7
)))
2101 warning (0, "target CPU does not support unaligned accesses");
2102 unaligned_access
= 0;
2105 if (TARGET_THUMB1
&& flag_schedule_insns
)
2107 /* Don't warn since it's on by default in -O2. */
2108 flag_schedule_insns
= 0;
2113 /* If optimizing for size, bump the number of instructions that we
2114 are prepared to conditionally execute (even on a StrongARM). */
2115 max_insns_skipped
= 6;
2118 max_insns_skipped
= current_tune
->max_insns_skipped
;
2120 /* Hot/Cold partitioning is not currently supported, since we can't
2121 handle literal pool placement in that case. */
2122 if (flag_reorder_blocks_and_partition
)
2124 inform (input_location
,
2125 "-freorder-blocks-and-partition not supported on this architecture");
2126 flag_reorder_blocks_and_partition
= 0;
2127 flag_reorder_blocks
= 1;
2131 /* Hoisting PIC address calculations more aggressively provides a small,
2132 but measurable, size reduction for PIC code. Therefore, we decrease
2133 the bar for unrestricted expression hoisting to the cost of PIC address
2134 calculation, which is 2 instructions. */
2135 maybe_set_param_value (PARAM_GCSE_UNRESTRICTED_COST
, 2,
2136 global_options
.x_param_values
,
2137 global_options_set
.x_param_values
);
2139 /* ARM EABI defaults to strict volatile bitfields. */
2140 if (TARGET_AAPCS_BASED
&& flag_strict_volatile_bitfields
< 0
2141 && abi_version_at_least(2))
2142 flag_strict_volatile_bitfields
= 1;
2144 /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed
2145 it beneficial (signified by setting num_prefetch_slots to 1 or more.) */
2146 if (flag_prefetch_loop_arrays
< 0
2149 && current_tune
->num_prefetch_slots
> 0)
2150 flag_prefetch_loop_arrays
= 1;
2152 /* Set up parameters to be used in prefetching algorithm. Do not override the
2153 defaults unless we are tuning for a core we have researched values for. */
2154 if (current_tune
->num_prefetch_slots
> 0)
2155 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
2156 current_tune
->num_prefetch_slots
,
2157 global_options
.x_param_values
,
2158 global_options_set
.x_param_values
);
2159 if (current_tune
->l1_cache_line_size
>= 0)
2160 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
2161 current_tune
->l1_cache_line_size
,
2162 global_options
.x_param_values
,
2163 global_options_set
.x_param_values
);
2164 if (current_tune
->l1_cache_size
>= 0)
2165 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
2166 current_tune
->l1_cache_size
,
2167 global_options
.x_param_values
,
2168 global_options_set
.x_param_values
);
2170 /* Use Neon to perform 64-bits operations rather than core
2172 prefer_neon_for_64bits
= current_tune
->prefer_neon_for_64bits
;
2173 if (use_neon_for_64bits
== 1)
2174 prefer_neon_for_64bits
= true;
2176 /* Use the alternative scheduling-pressure algorithm by default. */
2177 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
2178 global_options
.x_param_values
,
2179 global_options_set
.x_param_values
);
2181 /* Disable shrink-wrap when optimizing function for size, since it tends to
2182 generate additional returns. */
2183 if (optimize_function_for_size_p (cfun
) && TARGET_THUMB2
)
2184 flag_shrink_wrap
= false;
2185 /* TBD: Dwarf info for apcs frame is not handled yet. */
2186 if (TARGET_APCS_FRAME
)
2187 flag_shrink_wrap
= false;
2189 /* Register global variables with the garbage collector. */
2190 arm_add_gc_roots ();
2194 arm_add_gc_roots (void)
2196 gcc_obstack_init(&minipool_obstack
);
2197 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
2200 /* A table of known ARM exception types.
2201 For use with the interrupt function attribute. */
2205 const char *const arg
;
2206 const unsigned long return_value
;
2210 static const isr_attribute_arg isr_attribute_args
[] =
2212 { "IRQ", ARM_FT_ISR
},
2213 { "irq", ARM_FT_ISR
},
2214 { "FIQ", ARM_FT_FIQ
},
2215 { "fiq", ARM_FT_FIQ
},
2216 { "ABORT", ARM_FT_ISR
},
2217 { "abort", ARM_FT_ISR
},
2218 { "ABORT", ARM_FT_ISR
},
2219 { "abort", ARM_FT_ISR
},
2220 { "UNDEF", ARM_FT_EXCEPTION
},
2221 { "undef", ARM_FT_EXCEPTION
},
2222 { "SWI", ARM_FT_EXCEPTION
},
2223 { "swi", ARM_FT_EXCEPTION
},
2224 { NULL
, ARM_FT_NORMAL
}
2227 /* Returns the (interrupt) function type of the current
2228 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
2230 static unsigned long
2231 arm_isr_value (tree argument
)
2233 const isr_attribute_arg
* ptr
;
2237 return ARM_FT_NORMAL
| ARM_FT_STACKALIGN
;
2239 /* No argument - default to IRQ. */
2240 if (argument
== NULL_TREE
)
2243 /* Get the value of the argument. */
2244 if (TREE_VALUE (argument
) == NULL_TREE
2245 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
2246 return ARM_FT_UNKNOWN
;
2248 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
2250 /* Check it against the list of known arguments. */
2251 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
2252 if (streq (arg
, ptr
->arg
))
2253 return ptr
->return_value
;
2255 /* An unrecognized interrupt type. */
2256 return ARM_FT_UNKNOWN
;
2259 /* Computes the type of the current function. */
2261 static unsigned long
2262 arm_compute_func_type (void)
2264 unsigned long type
= ARM_FT_UNKNOWN
;
2268 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
2270 /* Decide if the current function is volatile. Such functions
2271 never return, and many memory cycles can be saved by not storing
2272 register values that will never be needed again. This optimization
2273 was added to speed up context switching in a kernel application. */
2275 && (TREE_NOTHROW (current_function_decl
)
2276 || !(flag_unwind_tables
2278 && arm_except_unwind_info (&global_options
) != UI_SJLJ
)))
2279 && TREE_THIS_VOLATILE (current_function_decl
))
2280 type
|= ARM_FT_VOLATILE
;
2282 if (cfun
->static_chain_decl
!= NULL
)
2283 type
|= ARM_FT_NESTED
;
2285 attr
= DECL_ATTRIBUTES (current_function_decl
);
2287 a
= lookup_attribute ("naked", attr
);
2289 type
|= ARM_FT_NAKED
;
2291 a
= lookup_attribute ("isr", attr
);
2293 a
= lookup_attribute ("interrupt", attr
);
2296 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
2298 type
|= arm_isr_value (TREE_VALUE (a
));
2303 /* Returns the type of the current function. */
2306 arm_current_func_type (void)
2308 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
2309 cfun
->machine
->func_type
= arm_compute_func_type ();
2311 return cfun
->machine
->func_type
;
2315 arm_allocate_stack_slots_for_args (void)
2317 /* Naked functions should not allocate stack slots for arguments. */
2318 return !IS_NAKED (arm_current_func_type ());
2322 arm_warn_func_return (tree decl
)
2324 /* Naked functions are implemented entirely in assembly, including the
2325 return sequence, so suppress warnings about this. */
2326 return lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) == NULL_TREE
;
2330 /* Output assembler code for a block containing the constant parts
2331 of a trampoline, leaving space for the variable parts.
2333 On the ARM, (if r8 is the static chain regnum, and remembering that
2334 referencing pc adds an offset of 8) the trampoline looks like:
2337 .word static chain value
2338 .word function's address
2339 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
2342 arm_asm_trampoline_template (FILE *f
)
2346 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM
, PC_REGNUM
);
2347 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", PC_REGNUM
, PC_REGNUM
);
2349 else if (TARGET_THUMB2
)
2351 /* The Thumb-2 trampoline is similar to the arm implementation.
2352 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
2353 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n",
2354 STATIC_CHAIN_REGNUM
, PC_REGNUM
);
2355 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM
, PC_REGNUM
);
2359 ASM_OUTPUT_ALIGN (f
, 2);
2360 fprintf (f
, "\t.code\t16\n");
2361 fprintf (f
, ".Ltrampoline_start:\n");
2362 asm_fprintf (f
, "\tpush\t{r0, r1}\n");
2363 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
2364 asm_fprintf (f
, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM
);
2365 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
2366 asm_fprintf (f
, "\tstr\tr0, [%r, #4]\n", SP_REGNUM
);
2367 asm_fprintf (f
, "\tpop\t{r0, %r}\n", PC_REGNUM
);
2369 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2370 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2373 /* Emit RTL insns to initialize the variable parts of a trampoline. */
2376 arm_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2378 rtx fnaddr
, mem
, a_tramp
;
2380 emit_block_move (m_tramp
, assemble_trampoline_template (),
2381 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2383 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 8 : 12);
2384 emit_move_insn (mem
, chain_value
);
2386 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 12 : 16);
2387 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2388 emit_move_insn (mem
, fnaddr
);
2390 a_tramp
= XEXP (m_tramp
, 0);
2391 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__clear_cache"),
2392 LCT_NORMAL
, VOIDmode
, 2, a_tramp
, Pmode
,
2393 plus_constant (Pmode
, a_tramp
, TRAMPOLINE_SIZE
), Pmode
);
2396 /* Thumb trampolines should be entered in thumb mode, so set
2397 the bottom bit of the address. */
2400 arm_trampoline_adjust_address (rtx addr
)
2403 addr
= expand_simple_binop (Pmode
, IOR
, addr
, const1_rtx
,
2404 NULL
, 0, OPTAB_LIB_WIDEN
);
2408 /* Return 1 if it is possible to return using a single instruction.
2409 If SIBLING is non-null, this is a test for a return before a sibling
2410 call. SIBLING is the call insn, so we can examine its register usage. */
2413 use_return_insn (int iscond
, rtx sibling
)
2416 unsigned int func_type
;
2417 unsigned long saved_int_regs
;
2418 unsigned HOST_WIDE_INT stack_adjust
;
2419 arm_stack_offsets
*offsets
;
2421 /* Never use a return instruction before reload has run. */
2422 if (!reload_completed
)
2425 func_type
= arm_current_func_type ();
2427 /* Naked, volatile and stack alignment functions need special
2429 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
| ARM_FT_STACKALIGN
))
2432 /* So do interrupt functions that use the frame pointer and Thumb
2433 interrupt functions. */
2434 if (IS_INTERRUPT (func_type
) && (frame_pointer_needed
|| TARGET_THUMB
))
2437 if (TARGET_LDRD
&& current_tune
->prefer_ldrd_strd
2438 && !optimize_function_for_size_p (cfun
))
2441 offsets
= arm_get_frame_offsets ();
2442 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
2444 /* As do variadic functions. */
2445 if (crtl
->args
.pretend_args_size
2446 || cfun
->machine
->uses_anonymous_args
2447 /* Or if the function calls __builtin_eh_return () */
2448 || crtl
->calls_eh_return
2449 /* Or if the function calls alloca */
2450 || cfun
->calls_alloca
2451 /* Or if there is a stack adjustment. However, if the stack pointer
2452 is saved on the stack, we can use a pre-incrementing stack load. */
2453 || !(stack_adjust
== 0 || (TARGET_APCS_FRAME
&& frame_pointer_needed
2454 && stack_adjust
== 4)))
2457 saved_int_regs
= offsets
->saved_regs_mask
;
2459 /* Unfortunately, the insn
2461 ldmib sp, {..., sp, ...}
2463 triggers a bug on most SA-110 based devices, such that the stack
2464 pointer won't be correctly restored if the instruction takes a
2465 page fault. We work around this problem by popping r3 along with
2466 the other registers, since that is never slower than executing
2467 another instruction.
2469 We test for !arm_arch5 here, because code for any architecture
2470 less than this could potentially be run on one of the buggy
2472 if (stack_adjust
== 4 && !arm_arch5
&& TARGET_ARM
)
2474 /* Validate that r3 is a call-clobbered register (always true in
2475 the default abi) ... */
2476 if (!call_used_regs
[3])
2479 /* ... that it isn't being used for a return value ... */
2480 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
2483 /* ... or for a tail-call argument ... */
2486 gcc_assert (CALL_P (sibling
));
2488 if (find_regno_fusage (sibling
, USE
, 3))
2492 /* ... and that there are no call-saved registers in r0-r2
2493 (always true in the default ABI). */
2494 if (saved_int_regs
& 0x7)
2498 /* Can't be done if interworking with Thumb, and any registers have been
2500 if (TARGET_INTERWORK
&& saved_int_regs
!= 0 && !IS_INTERRUPT(func_type
))
2503 /* On StrongARM, conditional returns are expensive if they aren't
2504 taken and multiple registers have been stacked. */
2505 if (iscond
&& arm_tune_strongarm
)
2507 /* Conditional return when just the LR is stored is a simple
2508 conditional-load instruction, that's not expensive. */
2509 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
2513 && arm_pic_register
!= INVALID_REGNUM
2514 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
2518 /* If there are saved registers but the LR isn't saved, then we need
2519 two instructions for the return. */
2520 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
2523 /* Can't be done if any of the VFP regs are pushed,
2524 since this also requires an insn. */
2525 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
2526 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
2527 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
2530 if (TARGET_REALLY_IWMMXT
)
2531 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
2532 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2538 /* Return TRUE if we should try to use a simple_return insn, i.e. perform
2539 shrink-wrapping if possible. This is the case if we need to emit a
2540 prologue, which we can test by looking at the offsets. */
2542 use_simple_return_p (void)
2544 arm_stack_offsets
*offsets
;
2546 offsets
= arm_get_frame_offsets ();
2547 return offsets
->outgoing_args
!= 0;
2550 /* Return TRUE if int I is a valid immediate ARM constant. */
2553 const_ok_for_arm (HOST_WIDE_INT i
)
2557 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
2558 be all zero, or all one. */
2559 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
2560 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
2561 != ((~(unsigned HOST_WIDE_INT
) 0)
2562 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
2565 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
2567 /* Fast return for 0 and small values. We must do this for zero, since
2568 the code below can't handle that one case. */
2569 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
2572 /* Get the number of trailing zeros. */
2573 lowbit
= ffs((int) i
) - 1;
2575 /* Only even shifts are allowed in ARM mode so round down to the
2576 nearest even number. */
2580 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
2585 /* Allow rotated constants in ARM mode. */
2587 && ((i
& ~0xc000003f) == 0
2588 || (i
& ~0xf000000f) == 0
2589 || (i
& ~0xfc000003) == 0))
2596 /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */
2599 if (i
== v
|| i
== (v
| (v
<< 8)))
2602 /* Allow repeated pattern 0xXY00XY00. */
2612 /* Return true if I is a valid constant for the operation CODE. */
2614 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
2616 if (const_ok_for_arm (i
))
2622 /* See if we can use movw. */
2623 if (arm_arch_thumb2
&& (i
& 0xffff0000) == 0)
2626 /* Otherwise, try mvn. */
2627 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
2630 /* See if we can use addw or subw. */
2632 && ((i
& 0xfffff000) == 0
2633 || ((-i
) & 0xfffff000) == 0))
2635 /* else fall through. */
2655 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
2657 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
2663 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
2667 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
2674 /* Return true if I is a valid di mode constant for the operation CODE. */
2676 const_ok_for_dimode_op (HOST_WIDE_INT i
, enum rtx_code code
)
2678 HOST_WIDE_INT hi_val
= (i
>> 32) & 0xFFFFFFFF;
2679 HOST_WIDE_INT lo_val
= i
& 0xFFFFFFFF;
2680 rtx hi
= GEN_INT (hi_val
);
2681 rtx lo
= GEN_INT (lo_val
);
2691 return (const_ok_for_op (hi_val
, code
) || hi_val
== 0xFFFFFFFF)
2692 && (const_ok_for_op (lo_val
, code
) || lo_val
== 0xFFFFFFFF);
2694 return arm_not_operand (hi
, SImode
) && arm_add_operand (lo
, SImode
);
2701 /* Emit a sequence of insns to handle a large constant.
2702 CODE is the code of the operation required, it can be any of SET, PLUS,
2703 IOR, AND, XOR, MINUS;
2704 MODE is the mode in which the operation is being performed;
2705 VAL is the integer to operate on;
2706 SOURCE is the other operand (a register, or a null-pointer for SET);
2707 SUBTARGETS means it is safe to create scratch registers if that will
2708 either produce a simpler sequence, or we will want to cse the values.
2709 Return value is the number of insns emitted. */
2711 /* ??? Tweak this for thumb2. */
2713 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
2714 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
2718 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
2719 cond
= COND_EXEC_TEST (PATTERN (insn
));
2723 if (subtargets
|| code
== SET
2724 || (REG_P (target
) && REG_P (source
)
2725 && REGNO (target
) != REGNO (source
)))
2727 /* After arm_reorg has been called, we can't fix up expensive
2728 constants by pushing them into memory so we must synthesize
2729 them in-line, regardless of the cost. This is only likely to
2730 be more costly on chips that have load delay slots and we are
2731 compiling without running the scheduler (so no splitting
2732 occurred before the final instruction emission).
2734 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
2736 if (!after_arm_reorg
2738 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
2740 > (arm_constant_limit (optimize_function_for_size_p (cfun
))
2745 /* Currently SET is the only monadic value for CODE, all
2746 the rest are diadic. */
2747 if (TARGET_USE_MOVT
)
2748 arm_emit_movpair (target
, GEN_INT (val
));
2750 emit_set_insn (target
, GEN_INT (val
));
2756 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
2758 if (TARGET_USE_MOVT
)
2759 arm_emit_movpair (temp
, GEN_INT (val
));
2761 emit_set_insn (temp
, GEN_INT (val
));
2763 /* For MINUS, the value is subtracted from, since we never
2764 have subtraction of a constant. */
2766 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
2768 emit_set_insn (target
,
2769 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
2775 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
2779 /* Return a sequence of integers, in RETURN_SEQUENCE that fit into
2780 ARM/THUMB2 immediates, and add up to VAL.
2781 Thr function return value gives the number of insns required. */
2783 optimal_immediate_sequence (enum rtx_code code
, unsigned HOST_WIDE_INT val
,
2784 struct four_ints
*return_sequence
)
2786 int best_consecutive_zeros
= 0;
2790 struct four_ints tmp_sequence
;
2792 /* If we aren't targeting ARM, the best place to start is always at
2793 the bottom, otherwise look more closely. */
2796 for (i
= 0; i
< 32; i
+= 2)
2798 int consecutive_zeros
= 0;
2800 if (!(val
& (3 << i
)))
2802 while ((i
< 32) && !(val
& (3 << i
)))
2804 consecutive_zeros
+= 2;
2807 if (consecutive_zeros
> best_consecutive_zeros
)
2809 best_consecutive_zeros
= consecutive_zeros
;
2810 best_start
= i
- consecutive_zeros
;
2817 /* So long as it won't require any more insns to do so, it's
2818 desirable to emit a small constant (in bits 0...9) in the last
2819 insn. This way there is more chance that it can be combined with
2820 a later addressing insn to form a pre-indexed load or store
2821 operation. Consider:
2823 *((volatile int *)0xe0000100) = 1;
2824 *((volatile int *)0xe0000110) = 2;
2826 We want this to wind up as:
2830 str rB, [rA, #0x100]
2832 str rB, [rA, #0x110]
2834 rather than having to synthesize both large constants from scratch.
2836 Therefore, we calculate how many insns would be required to emit
2837 the constant starting from `best_start', and also starting from
2838 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2839 yield a shorter sequence, we may as well use zero. */
2840 insns1
= optimal_immediate_sequence_1 (code
, val
, return_sequence
, best_start
);
2842 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < val
))
2844 insns2
= optimal_immediate_sequence_1 (code
, val
, &tmp_sequence
, 0);
2845 if (insns2
<= insns1
)
2847 *return_sequence
= tmp_sequence
;
2855 /* As for optimal_immediate_sequence, but starting at bit-position I. */
2857 optimal_immediate_sequence_1 (enum rtx_code code
, unsigned HOST_WIDE_INT val
,
2858 struct four_ints
*return_sequence
, int i
)
2860 int remainder
= val
& 0xffffffff;
2863 /* Try and find a way of doing the job in either two or three
2866 In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
2867 location. We start at position I. This may be the MSB, or
2868 optimial_immediate_sequence may have positioned it at the largest block
2869 of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
2870 wrapping around to the top of the word when we drop off the bottom.
2871 In the worst case this code should produce no more than four insns.
2873 In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
2874 constants, shifted to any arbitrary location. We should always start
2879 unsigned int b1
, b2
, b3
, b4
;
2880 unsigned HOST_WIDE_INT result
;
2883 gcc_assert (insns
< 4);
2888 /* First, find the next normal 12/8-bit shifted/rotated immediate. */
2889 if (remainder
& ((TARGET_ARM
? (3 << (i
- 2)) : (1 << (i
- 1)))))
2892 if (i
<= 12 && TARGET_THUMB2
&& code
== PLUS
)
2893 /* We can use addw/subw for the last 12 bits. */
2897 /* Use an 8-bit shifted/rotated immediate. */
2901 result
= remainder
& ((0x0ff << end
)
2902 | ((i
< end
) ? (0xff >> (32 - end
))
2909 /* Arm allows rotates by a multiple of two. Thumb-2 allows
2910 arbitrary shifts. */
2911 i
-= TARGET_ARM
? 2 : 1;
2915 /* Next, see if we can do a better job with a thumb2 replicated
2918 We do it this way around to catch the cases like 0x01F001E0 where
2919 two 8-bit immediates would work, but a replicated constant would
2922 TODO: 16-bit constants that don't clear all the bits, but still win.
2923 TODO: Arithmetic splitting for set/add/sub, rather than bitwise. */
2926 b1
= (remainder
& 0xff000000) >> 24;
2927 b2
= (remainder
& 0x00ff0000) >> 16;
2928 b3
= (remainder
& 0x0000ff00) >> 8;
2929 b4
= remainder
& 0xff;
2933 /* The 8-bit immediate already found clears b1 (and maybe b2),
2934 but must leave b3 and b4 alone. */
2936 /* First try to find a 32-bit replicated constant that clears
2937 almost everything. We can assume that we can't do it in one,
2938 or else we wouldn't be here. */
2939 unsigned int tmp
= b1
& b2
& b3
& b4
;
2940 unsigned int tmp2
= tmp
+ (tmp
<< 8) + (tmp
<< 16)
2942 unsigned int matching_bytes
= (tmp
== b1
) + (tmp
== b2
)
2943 + (tmp
== b3
) + (tmp
== b4
);
2945 && (matching_bytes
>= 3
2946 || (matching_bytes
== 2
2947 && const_ok_for_op (remainder
& ~tmp2
, code
))))
2949 /* At least 3 of the bytes match, and the fourth has at
2950 least as many bits set, or two of the bytes match
2951 and it will only require one more insn to finish. */
2959 /* Second, try to find a 16-bit replicated constant that can
2960 leave three of the bytes clear. If b2 or b4 is already
2961 zero, then we can. If the 8-bit from above would not
2962 clear b2 anyway, then we still win. */
2963 else if (b1
== b3
&& (!b2
|| !b4
2964 || (remainder
& 0x00ff0000 & ~result
)))
2966 result
= remainder
& 0xff00ff00;
2972 /* The 8-bit immediate already found clears b2 (and maybe b3)
2973 and we don't get here unless b1 is alredy clear, but it will
2974 leave b4 unchanged. */
2976 /* If we can clear b2 and b4 at once, then we win, since the
2977 8-bits couldn't possibly reach that far. */
2980 result
= remainder
& 0x00ff00ff;
2986 return_sequence
->i
[insns
++] = result
;
2987 remainder
&= ~result
;
2989 if (code
== SET
|| code
== MINUS
)
2997 /* Emit an instruction with the indicated PATTERN. If COND is
2998 non-NULL, conditionalize the execution of the instruction on COND
3002 emit_constant_insn (rtx cond
, rtx pattern
)
3005 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
3006 emit_insn (pattern
);
3009 /* As above, but extra parameter GENERATE which, if clear, suppresses
3013 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
3014 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
3019 int final_invert
= 0;
3021 int set_sign_bit_copies
= 0;
3022 int clear_sign_bit_copies
= 0;
3023 int clear_zero_bit_copies
= 0;
3024 int set_zero_bit_copies
= 0;
3025 int insns
= 0, neg_insns
, inv_insns
;
3026 unsigned HOST_WIDE_INT temp1
, temp2
;
3027 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
3028 struct four_ints
*immediates
;
3029 struct four_ints pos_immediates
, neg_immediates
, inv_immediates
;
3031 /* Find out which operations are safe for a given CODE. Also do a quick
3032 check for degenerate cases; these can occur when DImode operations
3045 if (remainder
== 0xffffffff)
3048 emit_constant_insn (cond
,
3049 gen_rtx_SET (VOIDmode
, target
,
3050 GEN_INT (ARM_SIGN_EXTEND (val
))));
3056 if (reload_completed
&& rtx_equal_p (target
, source
))
3060 emit_constant_insn (cond
,
3061 gen_rtx_SET (VOIDmode
, target
, source
));
3070 emit_constant_insn (cond
,
3071 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
3074 if (remainder
== 0xffffffff)
3076 if (reload_completed
&& rtx_equal_p (target
, source
))
3079 emit_constant_insn (cond
,
3080 gen_rtx_SET (VOIDmode
, target
, source
));
3089 if (reload_completed
&& rtx_equal_p (target
, source
))
3092 emit_constant_insn (cond
,
3093 gen_rtx_SET (VOIDmode
, target
, source
));
3097 if (remainder
== 0xffffffff)
3100 emit_constant_insn (cond
,
3101 gen_rtx_SET (VOIDmode
, target
,
3102 gen_rtx_NOT (mode
, source
)));
3109 /* We treat MINUS as (val - source), since (source - val) is always
3110 passed as (source + (-val)). */
3114 emit_constant_insn (cond
,
3115 gen_rtx_SET (VOIDmode
, target
,
3116 gen_rtx_NEG (mode
, source
)));
3119 if (const_ok_for_arm (val
))
3122 emit_constant_insn (cond
,
3123 gen_rtx_SET (VOIDmode
, target
,
3124 gen_rtx_MINUS (mode
, GEN_INT (val
),
3135 /* If we can do it in one insn get out quickly. */
3136 if (const_ok_for_op (val
, code
))
3139 emit_constant_insn (cond
,
3140 gen_rtx_SET (VOIDmode
, target
,
3142 ? gen_rtx_fmt_ee (code
, mode
, source
,
3148 /* On targets with UXTH/UBFX, we can deal with AND (2^N)-1 in a single
3150 if (code
== AND
&& (i
= exact_log2 (remainder
+ 1)) > 0
3151 && (arm_arch_thumb2
|| (i
== 16 && arm_arch6
&& mode
== SImode
)))
3155 if (mode
== SImode
&& i
== 16)
3156 /* Use UXTH in preference to UBFX, since on Thumb2 it's a
3158 emit_constant_insn (cond
,
3159 gen_zero_extendhisi2
3160 (target
, gen_lowpart (HImode
, source
)));
3162 /* Extz only supports SImode, but we can coerce the operands
3164 emit_constant_insn (cond
,
3165 gen_extzv_t2 (gen_lowpart (SImode
, target
),
3166 gen_lowpart (SImode
, source
),
3167 GEN_INT (i
), const0_rtx
));
3173 /* Calculate a few attributes that may be useful for specific
3175 /* Count number of leading zeros. */
3176 for (i
= 31; i
>= 0; i
--)
3178 if ((remainder
& (1 << i
)) == 0)
3179 clear_sign_bit_copies
++;
3184 /* Count number of leading 1's. */
3185 for (i
= 31; i
>= 0; i
--)
3187 if ((remainder
& (1 << i
)) != 0)
3188 set_sign_bit_copies
++;
3193 /* Count number of trailing zero's. */
3194 for (i
= 0; i
<= 31; i
++)
3196 if ((remainder
& (1 << i
)) == 0)
3197 clear_zero_bit_copies
++;
3202 /* Count number of trailing 1's. */
3203 for (i
= 0; i
<= 31; i
++)
3205 if ((remainder
& (1 << i
)) != 0)
3206 set_zero_bit_copies
++;
3214 /* See if we can do this by sign_extending a constant that is known
3215 to be negative. This is a good, way of doing it, since the shift
3216 may well merge into a subsequent insn. */
3217 if (set_sign_bit_copies
> 1)
3219 if (const_ok_for_arm
3220 (temp1
= ARM_SIGN_EXTEND (remainder
3221 << (set_sign_bit_copies
- 1))))
3225 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3226 emit_constant_insn (cond
,
3227 gen_rtx_SET (VOIDmode
, new_src
,
3229 emit_constant_insn (cond
,
3230 gen_ashrsi3 (target
, new_src
,
3231 GEN_INT (set_sign_bit_copies
- 1)));
3235 /* For an inverted constant, we will need to set the low bits,
3236 these will be shifted out of harm's way. */
3237 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
3238 if (const_ok_for_arm (~temp1
))
3242 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3243 emit_constant_insn (cond
,
3244 gen_rtx_SET (VOIDmode
, new_src
,
3246 emit_constant_insn (cond
,
3247 gen_ashrsi3 (target
, new_src
,
3248 GEN_INT (set_sign_bit_copies
- 1)));
3254 /* See if we can calculate the value as the difference between two
3255 valid immediates. */
3256 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
3258 int topshift
= clear_sign_bit_copies
& ~1;
3260 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
3261 & (0xff000000 >> topshift
));
3263 /* If temp1 is zero, then that means the 9 most significant
3264 bits of remainder were 1 and we've caused it to overflow.
3265 When topshift is 0 we don't need to do anything since we
3266 can borrow from 'bit 32'. */
3267 if (temp1
== 0 && topshift
!= 0)
3268 temp1
= 0x80000000 >> (topshift
- 1);
3270 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
3272 if (const_ok_for_arm (temp2
))
3276 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3277 emit_constant_insn (cond
,
3278 gen_rtx_SET (VOIDmode
, new_src
,
3280 emit_constant_insn (cond
,
3281 gen_addsi3 (target
, new_src
,
3289 /* See if we can generate this by setting the bottom (or the top)
3290 16 bits, and then shifting these into the other half of the
3291 word. We only look for the simplest cases, to do more would cost
3292 too much. Be careful, however, not to generate this when the
3293 alternative would take fewer insns. */
3294 if (val
& 0xffff0000)
3296 temp1
= remainder
& 0xffff0000;
3297 temp2
= remainder
& 0x0000ffff;
3299 /* Overlaps outside this range are best done using other methods. */
3300 for (i
= 9; i
< 24; i
++)
3302 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
3303 && !const_ok_for_arm (temp2
))
3305 rtx new_src
= (subtargets
3306 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
3308 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
3309 source
, subtargets
, generate
);
3317 gen_rtx_ASHIFT (mode
, source
,
3324 /* Don't duplicate cases already considered. */
3325 for (i
= 17; i
< 24; i
++)
3327 if (((temp1
| (temp1
>> i
)) == remainder
)
3328 && !const_ok_for_arm (temp1
))
3330 rtx new_src
= (subtargets
3331 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
3333 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
3334 source
, subtargets
, generate
);
3339 gen_rtx_SET (VOIDmode
, target
,
3342 gen_rtx_LSHIFTRT (mode
, source
,
3353 /* If we have IOR or XOR, and the constant can be loaded in a
3354 single instruction, and we can find a temporary to put it in,
3355 then this can be done in two instructions instead of 3-4. */
3357 /* TARGET can't be NULL if SUBTARGETS is 0 */
3358 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
3360 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
3364 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
3366 emit_constant_insn (cond
,
3367 gen_rtx_SET (VOIDmode
, sub
,
3369 emit_constant_insn (cond
,
3370 gen_rtx_SET (VOIDmode
, target
,
3371 gen_rtx_fmt_ee (code
, mode
,
3382 x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
3383 and the remainder 0s for e.g. 0xfff00000)
3384 x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies)
3386 This can be done in 2 instructions by using shifts with mov or mvn.
3391 mvn r0, r0, lsr #12 */
3392 if (set_sign_bit_copies
> 8
3393 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
3397 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
3398 rtx shift
= GEN_INT (set_sign_bit_copies
);
3402 gen_rtx_SET (VOIDmode
, sub
,
3404 gen_rtx_ASHIFT (mode
,
3409 gen_rtx_SET (VOIDmode
, target
,
3411 gen_rtx_LSHIFTRT (mode
, sub
,
3418 x = y | constant (which has set_zero_bit_copies number of trailing ones).
3420 x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies).
3422 For eg. r0 = r0 | 0xfff
3427 if (set_zero_bit_copies
> 8
3428 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
3432 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
3433 rtx shift
= GEN_INT (set_zero_bit_copies
);
3437 gen_rtx_SET (VOIDmode
, sub
,
3439 gen_rtx_LSHIFTRT (mode
,
3444 gen_rtx_SET (VOIDmode
, target
,
3446 gen_rtx_ASHIFT (mode
, sub
,
3452 /* This will never be reached for Thumb2 because orn is a valid
3453 instruction. This is for Thumb1 and the ARM 32 bit cases.
3455 x = y | constant (such that ~constant is a valid constant)
3457 x = ~(~y & ~constant).
3459 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
3463 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
3464 emit_constant_insn (cond
,
3465 gen_rtx_SET (VOIDmode
, sub
,
3466 gen_rtx_NOT (mode
, source
)));
3469 sub
= gen_reg_rtx (mode
);
3470 emit_constant_insn (cond
,
3471 gen_rtx_SET (VOIDmode
, sub
,
3472 gen_rtx_AND (mode
, source
,
3474 emit_constant_insn (cond
,
3475 gen_rtx_SET (VOIDmode
, target
,
3476 gen_rtx_NOT (mode
, sub
)));
3483 /* See if two shifts will do 2 or more insn's worth of work. */
3484 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
3486 HOST_WIDE_INT shift_mask
= ((0xffffffff
3487 << (32 - clear_sign_bit_copies
))
3490 if ((remainder
| shift_mask
) != 0xffffffff)
3494 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3495 insns
= arm_gen_constant (AND
, mode
, cond
,
3496 remainder
| shift_mask
,
3497 new_src
, source
, subtargets
, 1);
3502 rtx targ
= subtargets
? NULL_RTX
: target
;
3503 insns
= arm_gen_constant (AND
, mode
, cond
,
3504 remainder
| shift_mask
,
3505 targ
, source
, subtargets
, 0);
3511 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3512 rtx shift
= GEN_INT (clear_sign_bit_copies
);
3514 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
3515 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
3521 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
3523 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
3525 if ((remainder
| shift_mask
) != 0xffffffff)
3529 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3531 insns
= arm_gen_constant (AND
, mode
, cond
,
3532 remainder
| shift_mask
,
3533 new_src
, source
, subtargets
, 1);
3538 rtx targ
= subtargets
? NULL_RTX
: target
;
3540 insns
= arm_gen_constant (AND
, mode
, cond
,
3541 remainder
| shift_mask
,
3542 targ
, source
, subtargets
, 0);
3548 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3549 rtx shift
= GEN_INT (clear_zero_bit_copies
);
3551 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
3552 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
3564 /* Calculate what the instruction sequences would be if we generated it
3565 normally, negated, or inverted. */
3567 /* AND cannot be split into multiple insns, so invert and use BIC. */
3570 insns
= optimal_immediate_sequence (code
, remainder
, &pos_immediates
);
3573 neg_insns
= optimal_immediate_sequence (code
, (-remainder
) & 0xffffffff,
3578 if (can_invert
|| final_invert
)
3579 inv_insns
= optimal_immediate_sequence (code
, remainder
^ 0xffffffff,
3584 immediates
= &pos_immediates
;
3586 /* Is the negated immediate sequence more efficient? */
3587 if (neg_insns
< insns
&& neg_insns
<= inv_insns
)
3590 immediates
= &neg_immediates
;
3595 /* Is the inverted immediate sequence more efficient?
3596 We must allow for an extra NOT instruction for XOR operations, although
3597 there is some chance that the final 'mvn' will get optimized later. */
3598 if ((inv_insns
+ 1) < insns
|| (!final_invert
&& inv_insns
< insns
))
3601 immediates
= &inv_immediates
;
3609 /* Now output the chosen sequence as instructions. */
3612 for (i
= 0; i
< insns
; i
++)
3614 rtx new_src
, temp1_rtx
;
3616 temp1
= immediates
->i
[i
];
3618 if (code
== SET
|| code
== MINUS
)
3619 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
3620 else if ((final_invert
|| i
< (insns
- 1)) && subtargets
)
3621 new_src
= gen_reg_rtx (mode
);
3627 else if (can_negate
)
3630 temp1
= trunc_int_for_mode (temp1
, mode
);
3631 temp1_rtx
= GEN_INT (temp1
);
3635 else if (code
== MINUS
)
3636 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
3638 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
3640 emit_constant_insn (cond
,
3641 gen_rtx_SET (VOIDmode
, new_src
,
3647 can_negate
= can_invert
;
3651 else if (code
== MINUS
)
3659 emit_constant_insn (cond
, gen_rtx_SET (VOIDmode
, target
,
3660 gen_rtx_NOT (mode
, source
)));
3667 /* Canonicalize a comparison so that we are more likely to recognize it.
3668 This can be done for a few constant compares, where we can make the
3669 immediate value easier to load. */
3672 arm_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
3673 bool op0_preserve_value
)
3675 enum machine_mode mode
;
3676 unsigned HOST_WIDE_INT i
, maxval
;
3678 mode
= GET_MODE (*op0
);
3679 if (mode
== VOIDmode
)
3680 mode
= GET_MODE (*op1
);
3682 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
3684 /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode
3685 we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either
3686 reversed or (for constant OP1) adjusted to GE/LT. Similarly
3687 for GTU/LEU in Thumb mode. */
3692 if (*code
== GT
|| *code
== LE
3693 || (!TARGET_ARM
&& (*code
== GTU
|| *code
== LEU
)))
3695 /* Missing comparison. First try to use an available
3697 if (CONST_INT_P (*op1
))
3705 && arm_const_double_by_immediates (GEN_INT (i
+ 1)))
3707 *op1
= GEN_INT (i
+ 1);
3708 *code
= *code
== GT
? GE
: LT
;
3714 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
3715 && arm_const_double_by_immediates (GEN_INT (i
+ 1)))
3717 *op1
= GEN_INT (i
+ 1);
3718 *code
= *code
== GTU
? GEU
: LTU
;
3727 /* If that did not work, reverse the condition. */
3728 if (!op0_preserve_value
)
3733 *code
= (int)swap_condition ((enum rtx_code
)*code
);
3739 /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing
3740 with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)),
3741 to facilitate possible combining with a cmp into 'ands'. */
3743 && GET_CODE (*op0
) == ZERO_EXTEND
3744 && GET_CODE (XEXP (*op0
, 0)) == SUBREG
3745 && GET_MODE (XEXP (*op0
, 0)) == QImode
3746 && GET_MODE (SUBREG_REG (XEXP (*op0
, 0))) == SImode
3747 && subreg_lowpart_p (XEXP (*op0
, 0))
3748 && *op1
== const0_rtx
)
3749 *op0
= gen_rtx_AND (SImode
, SUBREG_REG (XEXP (*op0
, 0)),
3752 /* Comparisons smaller than DImode. Only adjust comparisons against
3753 an out-of-range constant. */
3754 if (!CONST_INT_P (*op1
)
3755 || const_ok_for_arm (INTVAL (*op1
))
3756 || const_ok_for_arm (- INTVAL (*op1
)))
3770 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
3772 *op1
= GEN_INT (i
+ 1);
3773 *code
= *code
== GT
? GE
: LT
;
3781 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
3783 *op1
= GEN_INT (i
- 1);
3784 *code
= *code
== GE
? GT
: LE
;
3791 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
3792 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
3794 *op1
= GEN_INT (i
+ 1);
3795 *code
= *code
== GTU
? GEU
: LTU
;
3803 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
3805 *op1
= GEN_INT (i
- 1);
3806 *code
= *code
== GEU
? GTU
: LEU
;
3817 /* Define how to find the value returned by a function. */
3820 arm_function_value(const_tree type
, const_tree func
,
3821 bool outgoing ATTRIBUTE_UNUSED
)
3823 enum machine_mode mode
;
3824 int unsignedp ATTRIBUTE_UNUSED
;
3825 rtx r ATTRIBUTE_UNUSED
;
3827 mode
= TYPE_MODE (type
);
3829 if (TARGET_AAPCS_BASED
)
3830 return aapcs_allocate_return_reg (mode
, type
, func
);
3832 /* Promote integer types. */
3833 if (INTEGRAL_TYPE_P (type
))
3834 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, func
, 1);
3836 /* Promotes small structs returned in a register to full-word size
3837 for big-endian AAPCS. */
3838 if (arm_return_in_msb (type
))
3840 HOST_WIDE_INT size
= int_size_in_bytes (type
);
3841 if (size
% UNITS_PER_WORD
!= 0)
3843 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
3844 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
3848 return arm_libcall_value_1 (mode
);
3851 /* libcall hashtable helpers. */
3853 struct libcall_hasher
: typed_noop_remove
<rtx_def
>
3855 typedef rtx_def value_type
;
3856 typedef rtx_def compare_type
;
3857 static inline hashval_t
hash (const value_type
*);
3858 static inline bool equal (const value_type
*, const compare_type
*);
3859 static inline void remove (value_type
*);
3863 libcall_hasher::equal (const value_type
*p1
, const compare_type
*p2
)
3865 return rtx_equal_p (p1
, p2
);
3869 libcall_hasher::hash (const value_type
*p1
)
3871 return hash_rtx (p1
, VOIDmode
, NULL
, NULL
, FALSE
);
3874 typedef hash_table
<libcall_hasher
> libcall_table_type
;
3877 add_libcall (libcall_table_type htab
, rtx libcall
)
3879 *htab
.find_slot (libcall
, INSERT
) = libcall
;
3883 arm_libcall_uses_aapcs_base (const_rtx libcall
)
3885 static bool init_done
= false;
3886 static libcall_table_type libcall_htab
;
3892 libcall_htab
.create (31);
3893 add_libcall (libcall_htab
,
3894 convert_optab_libfunc (sfloat_optab
, SFmode
, SImode
));
3895 add_libcall (libcall_htab
,
3896 convert_optab_libfunc (sfloat_optab
, DFmode
, SImode
));
3897 add_libcall (libcall_htab
,
3898 convert_optab_libfunc (sfloat_optab
, SFmode
, DImode
));
3899 add_libcall (libcall_htab
,
3900 convert_optab_libfunc (sfloat_optab
, DFmode
, DImode
));
3902 add_libcall (libcall_htab
,
3903 convert_optab_libfunc (ufloat_optab
, SFmode
, SImode
));
3904 add_libcall (libcall_htab
,
3905 convert_optab_libfunc (ufloat_optab
, DFmode
, SImode
));
3906 add_libcall (libcall_htab
,
3907 convert_optab_libfunc (ufloat_optab
, SFmode
, DImode
));
3908 add_libcall (libcall_htab
,
3909 convert_optab_libfunc (ufloat_optab
, DFmode
, DImode
));
3911 add_libcall (libcall_htab
,
3912 convert_optab_libfunc (sext_optab
, SFmode
, HFmode
));
3913 add_libcall (libcall_htab
,
3914 convert_optab_libfunc (trunc_optab
, HFmode
, SFmode
));
3915 add_libcall (libcall_htab
,
3916 convert_optab_libfunc (sfix_optab
, SImode
, DFmode
));
3917 add_libcall (libcall_htab
,
3918 convert_optab_libfunc (ufix_optab
, SImode
, DFmode
));
3919 add_libcall (libcall_htab
,
3920 convert_optab_libfunc (sfix_optab
, DImode
, DFmode
));
3921 add_libcall (libcall_htab
,
3922 convert_optab_libfunc (ufix_optab
, DImode
, DFmode
));
3923 add_libcall (libcall_htab
,
3924 convert_optab_libfunc (sfix_optab
, DImode
, SFmode
));
3925 add_libcall (libcall_htab
,
3926 convert_optab_libfunc (ufix_optab
, DImode
, SFmode
));
3928 /* Values from double-precision helper functions are returned in core
3929 registers if the selected core only supports single-precision
3930 arithmetic, even if we are using the hard-float ABI. The same is
3931 true for single-precision helpers, but we will never be using the
3932 hard-float ABI on a CPU which doesn't support single-precision
3933 operations in hardware. */
3934 add_libcall (libcall_htab
, optab_libfunc (add_optab
, DFmode
));
3935 add_libcall (libcall_htab
, optab_libfunc (sdiv_optab
, DFmode
));
3936 add_libcall (libcall_htab
, optab_libfunc (smul_optab
, DFmode
));
3937 add_libcall (libcall_htab
, optab_libfunc (neg_optab
, DFmode
));
3938 add_libcall (libcall_htab
, optab_libfunc (sub_optab
, DFmode
));
3939 add_libcall (libcall_htab
, optab_libfunc (eq_optab
, DFmode
));
3940 add_libcall (libcall_htab
, optab_libfunc (lt_optab
, DFmode
));
3941 add_libcall (libcall_htab
, optab_libfunc (le_optab
, DFmode
));
3942 add_libcall (libcall_htab
, optab_libfunc (ge_optab
, DFmode
));
3943 add_libcall (libcall_htab
, optab_libfunc (gt_optab
, DFmode
));
3944 add_libcall (libcall_htab
, optab_libfunc (unord_optab
, DFmode
));
3945 add_libcall (libcall_htab
, convert_optab_libfunc (sext_optab
, DFmode
,
3947 add_libcall (libcall_htab
, convert_optab_libfunc (trunc_optab
, SFmode
,
3951 return libcall
&& libcall_htab
.find (libcall
) != NULL
;
3955 arm_libcall_value_1 (enum machine_mode mode
)
3957 if (TARGET_AAPCS_BASED
)
3958 return aapcs_libcall_value (mode
);
3959 else if (TARGET_IWMMXT_ABI
3960 && arm_vector_mode_supported_p (mode
))
3961 return gen_rtx_REG (mode
, FIRST_IWMMXT_REGNUM
);
3963 return gen_rtx_REG (mode
, ARG_REGISTER (1));
3966 /* Define how to find the value returned by a library function
3967 assuming the value has mode MODE. */
3970 arm_libcall_value (enum machine_mode mode
, const_rtx libcall
)
3972 if (TARGET_AAPCS_BASED
&& arm_pcs_default
!= ARM_PCS_AAPCS
3973 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3975 /* The following libcalls return their result in integer registers,
3976 even though they return a floating point value. */
3977 if (arm_libcall_uses_aapcs_base (libcall
))
3978 return gen_rtx_REG (mode
, ARG_REGISTER(1));
3982 return arm_libcall_value_1 (mode
);
3985 /* Implement TARGET_FUNCTION_VALUE_REGNO_P. */
3988 arm_function_value_regno_p (const unsigned int regno
)
3990 if (regno
== ARG_REGISTER (1)
3992 && TARGET_AAPCS_BASED
3994 && TARGET_HARD_FLOAT
3995 && regno
== FIRST_VFP_REGNUM
)
3996 || (TARGET_IWMMXT_ABI
3997 && regno
== FIRST_IWMMXT_REGNUM
))
4003 /* Determine the amount of memory needed to store the possible return
4004 registers of an untyped call. */
4006 arm_apply_result_size (void)
4012 if (TARGET_HARD_FLOAT_ABI
&& TARGET_VFP
)
4014 if (TARGET_IWMMXT_ABI
)
4021 /* Decide whether TYPE should be returned in memory (true)
4022 or in a register (false). FNTYPE is the type of the function making
4025 arm_return_in_memory (const_tree type
, const_tree fntype
)
4029 size
= int_size_in_bytes (type
); /* Negative if not fixed size. */
4031 if (TARGET_AAPCS_BASED
)
4033 /* Simple, non-aggregate types (ie not including vectors and
4034 complex) are always returned in a register (or registers).
4035 We don't care about which register here, so we can short-cut
4036 some of the detail. */
4037 if (!AGGREGATE_TYPE_P (type
)
4038 && TREE_CODE (type
) != VECTOR_TYPE
4039 && TREE_CODE (type
) != COMPLEX_TYPE
)
4042 /* Any return value that is no larger than one word can be
4044 if (((unsigned HOST_WIDE_INT
) size
) <= UNITS_PER_WORD
)
4047 /* Check any available co-processors to see if they accept the
4048 type as a register candidate (VFP, for example, can return
4049 some aggregates in consecutive registers). These aren't
4050 available if the call is variadic. */
4051 if (aapcs_select_return_coproc (type
, fntype
) >= 0)
4054 /* Vector values should be returned using ARM registers, not
4055 memory (unless they're over 16 bytes, which will break since
4056 we only have four call-clobbered registers to play with). */
4057 if (TREE_CODE (type
) == VECTOR_TYPE
)
4058 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
4060 /* The rest go in memory. */
4064 if (TREE_CODE (type
) == VECTOR_TYPE
)
4065 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
4067 if (!AGGREGATE_TYPE_P (type
) &&
4068 (TREE_CODE (type
) != VECTOR_TYPE
))
4069 /* All simple types are returned in registers. */
4072 if (arm_abi
!= ARM_ABI_APCS
)
4074 /* ATPCS and later return aggregate types in memory only if they are
4075 larger than a word (or are variable size). */
4076 return (size
< 0 || size
> UNITS_PER_WORD
);
4079 /* For the arm-wince targets we choose to be compatible with Microsoft's
4080 ARM and Thumb compilers, which always return aggregates in memory. */
4082 /* All structures/unions bigger than one word are returned in memory.
4083 Also catch the case where int_size_in_bytes returns -1. In this case
4084 the aggregate is either huge or of variable size, and in either case
4085 we will want to return it via memory and not in a register. */
4086 if (size
< 0 || size
> UNITS_PER_WORD
)
4089 if (TREE_CODE (type
) == RECORD_TYPE
)
4093 /* For a struct the APCS says that we only return in a register
4094 if the type is 'integer like' and every addressable element
4095 has an offset of zero. For practical purposes this means
4096 that the structure can have at most one non bit-field element
4097 and that this element must be the first one in the structure. */
4099 /* Find the first field, ignoring non FIELD_DECL things which will
4100 have been created by C++. */
4101 for (field
= TYPE_FIELDS (type
);
4102 field
&& TREE_CODE (field
) != FIELD_DECL
;
4103 field
= DECL_CHAIN (field
))
4107 return false; /* An empty structure. Allowed by an extension to ANSI C. */
4109 /* Check that the first field is valid for returning in a register. */
4111 /* ... Floats are not allowed */
4112 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
4115 /* ... Aggregates that are not themselves valid for returning in
4116 a register are not allowed. */
4117 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
4120 /* Now check the remaining fields, if any. Only bitfields are allowed,
4121 since they are not addressable. */
4122 for (field
= DECL_CHAIN (field
);
4124 field
= DECL_CHAIN (field
))
4126 if (TREE_CODE (field
) != FIELD_DECL
)
4129 if (!DECL_BIT_FIELD_TYPE (field
))
4136 if (TREE_CODE (type
) == UNION_TYPE
)
4140 /* Unions can be returned in registers if every element is
4141 integral, or can be returned in an integer register. */
4142 for (field
= TYPE_FIELDS (type
);
4144 field
= DECL_CHAIN (field
))
4146 if (TREE_CODE (field
) != FIELD_DECL
)
4149 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
4152 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
4158 #endif /* not ARM_WINCE */
4160 /* Return all other types in memory. */
4164 const struct pcs_attribute_arg
4168 } pcs_attribute_args
[] =
4170 {"aapcs", ARM_PCS_AAPCS
},
4171 {"aapcs-vfp", ARM_PCS_AAPCS_VFP
},
4173 /* We could recognize these, but changes would be needed elsewhere
4174 * to implement them. */
4175 {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT
},
4176 {"atpcs", ARM_PCS_ATPCS
},
4177 {"apcs", ARM_PCS_APCS
},
4179 {NULL
, ARM_PCS_UNKNOWN
}
4183 arm_pcs_from_attribute (tree attr
)
4185 const struct pcs_attribute_arg
*ptr
;
4188 /* Get the value of the argument. */
4189 if (TREE_VALUE (attr
) == NULL_TREE
4190 || TREE_CODE (TREE_VALUE (attr
)) != STRING_CST
)
4191 return ARM_PCS_UNKNOWN
;
4193 arg
= TREE_STRING_POINTER (TREE_VALUE (attr
));
4195 /* Check it against the list of known arguments. */
4196 for (ptr
= pcs_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
4197 if (streq (arg
, ptr
->arg
))
4200 /* An unrecognized interrupt type. */
4201 return ARM_PCS_UNKNOWN
;
4204 /* Get the PCS variant to use for this call. TYPE is the function's type
4205 specification, DECL is the specific declartion. DECL may be null if
4206 the call could be indirect or if this is a library call. */
4208 arm_get_pcs_model (const_tree type
, const_tree decl
)
4210 bool user_convention
= false;
4211 enum arm_pcs user_pcs
= arm_pcs_default
;
4216 attr
= lookup_attribute ("pcs", TYPE_ATTRIBUTES (type
));
4219 user_pcs
= arm_pcs_from_attribute (TREE_VALUE (attr
));
4220 user_convention
= true;
4223 if (TARGET_AAPCS_BASED
)
4225 /* Detect varargs functions. These always use the base rules
4226 (no argument is ever a candidate for a co-processor
4228 bool base_rules
= stdarg_p (type
);
4230 if (user_convention
)
4232 if (user_pcs
> ARM_PCS_AAPCS_LOCAL
)
4233 sorry ("non-AAPCS derived PCS variant");
4234 else if (base_rules
&& user_pcs
!= ARM_PCS_AAPCS
)
4235 error ("variadic functions must use the base AAPCS variant");
4239 return ARM_PCS_AAPCS
;
4240 else if (user_convention
)
4242 else if (decl
&& flag_unit_at_a_time
)
4244 /* Local functions never leak outside this compilation unit,
4245 so we are free to use whatever conventions are
4247 /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */
4248 struct cgraph_local_info
*i
= cgraph_local_info (CONST_CAST_TREE(decl
));
4250 return ARM_PCS_AAPCS_LOCAL
;
4253 else if (user_convention
&& user_pcs
!= arm_pcs_default
)
4254 sorry ("PCS variant");
4256 /* For everything else we use the target's default. */
4257 return arm_pcs_default
;
4262 aapcs_vfp_cum_init (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
4263 const_tree fntype ATTRIBUTE_UNUSED
,
4264 rtx libcall ATTRIBUTE_UNUSED
,
4265 const_tree fndecl ATTRIBUTE_UNUSED
)
4267 /* Record the unallocated VFP registers. */
4268 pcum
->aapcs_vfp_regs_free
= (1 << NUM_VFP_ARG_REGS
) - 1;
4269 pcum
->aapcs_vfp_reg_alloc
= 0;
4272 /* Walk down the type tree of TYPE counting consecutive base elements.
4273 If *MODEP is VOIDmode, then set it to the first valid floating point
4274 type. If a non-floating point type is found, or if a floating point
4275 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
4276 otherwise return the count in the sub-tree. */
4278 aapcs_vfp_sub_candidate (const_tree type
, enum machine_mode
*modep
)
4280 enum machine_mode mode
;
4283 switch (TREE_CODE (type
))
4286 mode
= TYPE_MODE (type
);
4287 if (mode
!= DFmode
&& mode
!= SFmode
)
4290 if (*modep
== VOIDmode
)
4299 mode
= TYPE_MODE (TREE_TYPE (type
));
4300 if (mode
!= DFmode
&& mode
!= SFmode
)
4303 if (*modep
== VOIDmode
)
4312 /* Use V2SImode and V4SImode as representatives of all 64-bit
4313 and 128-bit vector types, whether or not those modes are
4314 supported with the present options. */
4315 size
= int_size_in_bytes (type
);
4328 if (*modep
== VOIDmode
)
4331 /* Vector modes are considered to be opaque: two vectors are
4332 equivalent for the purposes of being homogeneous aggregates
4333 if they are the same size. */
4342 tree index
= TYPE_DOMAIN (type
);
4344 /* Can't handle incomplete types. */
4345 if (!COMPLETE_TYPE_P (type
))
4348 count
= aapcs_vfp_sub_candidate (TREE_TYPE (type
), modep
);
4351 || !TYPE_MAX_VALUE (index
)
4352 || !host_integerp (TYPE_MAX_VALUE (index
), 1)
4353 || !TYPE_MIN_VALUE (index
)
4354 || !host_integerp (TYPE_MIN_VALUE (index
), 1)
4358 count
*= (1 + tree_low_cst (TYPE_MAX_VALUE (index
), 1)
4359 - tree_low_cst (TYPE_MIN_VALUE (index
), 1));
4361 /* There must be no padding. */
4362 if (!host_integerp (TYPE_SIZE (type
), 1)
4363 || (tree_low_cst (TYPE_SIZE (type
), 1)
4364 != count
* GET_MODE_BITSIZE (*modep
)))
4376 /* Can't handle incomplete types. */
4377 if (!COMPLETE_TYPE_P (type
))
4380 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
4382 if (TREE_CODE (field
) != FIELD_DECL
)
4385 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
);
4391 /* There must be no padding. */
4392 if (!host_integerp (TYPE_SIZE (type
), 1)
4393 || (tree_low_cst (TYPE_SIZE (type
), 1)
4394 != count
* GET_MODE_BITSIZE (*modep
)))
4401 case QUAL_UNION_TYPE
:
4403 /* These aren't very interesting except in a degenerate case. */
4408 /* Can't handle incomplete types. */
4409 if (!COMPLETE_TYPE_P (type
))
4412 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
4414 if (TREE_CODE (field
) != FIELD_DECL
)
4417 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
);
4420 count
= count
> sub_count
? count
: sub_count
;
4423 /* There must be no padding. */
4424 if (!host_integerp (TYPE_SIZE (type
), 1)
4425 || (tree_low_cst (TYPE_SIZE (type
), 1)
4426 != count
* GET_MODE_BITSIZE (*modep
)))
4439 /* Return true if PCS_VARIANT should use VFP registers. */
4441 use_vfp_abi (enum arm_pcs pcs_variant
, bool is_double
)
4443 if (pcs_variant
== ARM_PCS_AAPCS_VFP
)
4445 static bool seen_thumb1_vfp
= false;
4447 if (TARGET_THUMB1
&& !seen_thumb1_vfp
)
4449 sorry ("Thumb-1 hard-float VFP ABI");
4450 /* sorry() is not immediately fatal, so only display this once. */
4451 seen_thumb1_vfp
= true;
4457 if (pcs_variant
!= ARM_PCS_AAPCS_LOCAL
)
4460 return (TARGET_32BIT
&& TARGET_VFP
&& TARGET_HARD_FLOAT
&&
4461 (TARGET_VFP_DOUBLE
|| !is_double
));
4464 /* Return true if an argument whose type is TYPE, or mode is MODE, is
4465 suitable for passing or returning in VFP registers for the PCS
4466 variant selected. If it is, then *BASE_MODE is updated to contain
4467 a machine mode describing each element of the argument's type and
4468 *COUNT to hold the number of such elements. */
4470 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant
,
4471 enum machine_mode mode
, const_tree type
,
4472 enum machine_mode
*base_mode
, int *count
)
4474 enum machine_mode new_mode
= VOIDmode
;
4476 /* If we have the type information, prefer that to working things
4477 out from the mode. */
4480 int ag_count
= aapcs_vfp_sub_candidate (type
, &new_mode
);
4482 if (ag_count
> 0 && ag_count
<= 4)
4487 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4488 || GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
4489 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4494 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4497 new_mode
= (mode
== DCmode
? DFmode
: SFmode
);
4503 if (!use_vfp_abi (pcs_variant
, ARM_NUM_REGS (new_mode
) > 1))
4506 *base_mode
= new_mode
;
4511 aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant
,
4512 enum machine_mode mode
, const_tree type
)
4514 int count ATTRIBUTE_UNUSED
;
4515 enum machine_mode ag_mode ATTRIBUTE_UNUSED
;
4517 if (!use_vfp_abi (pcs_variant
, false))
4519 return aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
4524 aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4527 if (!use_vfp_abi (pcum
->pcs_variant
, false))
4530 return aapcs_vfp_is_call_or_return_candidate (pcum
->pcs_variant
, mode
, type
,
4531 &pcum
->aapcs_vfp_rmode
,
4532 &pcum
->aapcs_vfp_rcount
);
4536 aapcs_vfp_allocate (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4537 const_tree type ATTRIBUTE_UNUSED
)
4539 int shift
= GET_MODE_SIZE (pcum
->aapcs_vfp_rmode
) / GET_MODE_SIZE (SFmode
);
4540 unsigned mask
= (1 << (shift
* pcum
->aapcs_vfp_rcount
)) - 1;
4543 for (regno
= 0; regno
< NUM_VFP_ARG_REGS
; regno
+= shift
)
4544 if (((pcum
->aapcs_vfp_regs_free
>> regno
) & mask
) == mask
)
4546 pcum
->aapcs_vfp_reg_alloc
= mask
<< regno
;
4547 if (mode
== BLKmode
|| (mode
== TImode
&& !TARGET_NEON
))
4550 int rcount
= pcum
->aapcs_vfp_rcount
;
4552 enum machine_mode rmode
= pcum
->aapcs_vfp_rmode
;
4556 /* Avoid using unsupported vector modes. */
4557 if (rmode
== V2SImode
)
4559 else if (rmode
== V4SImode
)
4566 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (rcount
));
4567 for (i
= 0; i
< rcount
; i
++)
4569 rtx tmp
= gen_rtx_REG (rmode
,
4570 FIRST_VFP_REGNUM
+ regno
+ i
* rshift
);
4571 tmp
= gen_rtx_EXPR_LIST
4573 GEN_INT (i
* GET_MODE_SIZE (rmode
)));
4574 XVECEXP (par
, 0, i
) = tmp
;
4577 pcum
->aapcs_reg
= par
;
4580 pcum
->aapcs_reg
= gen_rtx_REG (mode
, FIRST_VFP_REGNUM
+ regno
);
4587 aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED
,
4588 enum machine_mode mode
,
4589 const_tree type ATTRIBUTE_UNUSED
)
4591 if (!use_vfp_abi (pcs_variant
, false))
4594 if (mode
== BLKmode
|| (mode
== TImode
&& !TARGET_NEON
))
4597 enum machine_mode ag_mode
;
4602 aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
4607 if (ag_mode
== V2SImode
)
4609 else if (ag_mode
== V4SImode
)
4615 shift
= GET_MODE_SIZE(ag_mode
) / GET_MODE_SIZE(SFmode
);
4616 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (count
));
4617 for (i
= 0; i
< count
; i
++)
4619 rtx tmp
= gen_rtx_REG (ag_mode
, FIRST_VFP_REGNUM
+ i
* shift
);
4620 tmp
= gen_rtx_EXPR_LIST (VOIDmode
, tmp
,
4621 GEN_INT (i
* GET_MODE_SIZE (ag_mode
)));
4622 XVECEXP (par
, 0, i
) = tmp
;
4628 return gen_rtx_REG (mode
, FIRST_VFP_REGNUM
);
4632 aapcs_vfp_advance (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
4633 enum machine_mode mode ATTRIBUTE_UNUSED
,
4634 const_tree type ATTRIBUTE_UNUSED
)
4636 pcum
->aapcs_vfp_regs_free
&= ~pcum
->aapcs_vfp_reg_alloc
;
4637 pcum
->aapcs_vfp_reg_alloc
= 0;
4641 #define AAPCS_CP(X) \
4643 aapcs_ ## X ## _cum_init, \
4644 aapcs_ ## X ## _is_call_candidate, \
4645 aapcs_ ## X ## _allocate, \
4646 aapcs_ ## X ## _is_return_candidate, \
4647 aapcs_ ## X ## _allocate_return_reg, \
4648 aapcs_ ## X ## _advance \
4651 /* Table of co-processors that can be used to pass arguments in
4652 registers. Idealy no arugment should be a candidate for more than
4653 one co-processor table entry, but the table is processed in order
4654 and stops after the first match. If that entry then fails to put
4655 the argument into a co-processor register, the argument will go on
4659 /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */
4660 void (*cum_init
) (CUMULATIVE_ARGS
*, const_tree
, rtx
, const_tree
);
4662 /* Return true if an argument of mode MODE (or type TYPE if MODE is
4663 BLKmode) is a candidate for this co-processor's registers; this
4664 function should ignore any position-dependent state in
4665 CUMULATIVE_ARGS and only use call-type dependent information. */
4666 bool (*is_call_candidate
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
4668 /* Return true if the argument does get a co-processor register; it
4669 should set aapcs_reg to an RTX of the register allocated as is
4670 required for a return from FUNCTION_ARG. */
4671 bool (*allocate
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
4673 /* Return true if a result of mode MODE (or type TYPE if MODE is
4674 BLKmode) is can be returned in this co-processor's registers. */
4675 bool (*is_return_candidate
) (enum arm_pcs
, enum machine_mode
, const_tree
);
4677 /* Allocate and return an RTX element to hold the return type of a
4678 call, this routine must not fail and will only be called if
4679 is_return_candidate returned true with the same parameters. */
4680 rtx (*allocate_return_reg
) (enum arm_pcs
, enum machine_mode
, const_tree
);
4682 /* Finish processing this argument and prepare to start processing
4684 void (*advance
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
4685 } aapcs_cp_arg_layout
[ARM_NUM_COPROC_SLOTS
] =
4693 aapcs_select_call_coproc (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4698 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4699 if (aapcs_cp_arg_layout
[i
].is_call_candidate (pcum
, mode
, type
))
4706 aapcs_select_return_coproc (const_tree type
, const_tree fntype
)
4708 /* We aren't passed a decl, so we can't check that a call is local.
4709 However, it isn't clear that that would be a win anyway, since it
4710 might limit some tail-calling opportunities. */
4711 enum arm_pcs pcs_variant
;
4715 const_tree fndecl
= NULL_TREE
;
4717 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
4720 fntype
= TREE_TYPE (fntype
);
4723 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4726 pcs_variant
= arm_pcs_default
;
4728 if (pcs_variant
!= ARM_PCS_AAPCS
)
4732 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4733 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
,
4742 aapcs_allocate_return_reg (enum machine_mode mode
, const_tree type
,
4745 /* We aren't passed a decl, so we can't check that a call is local.
4746 However, it isn't clear that that would be a win anyway, since it
4747 might limit some tail-calling opportunities. */
4748 enum arm_pcs pcs_variant
;
4749 int unsignedp ATTRIBUTE_UNUSED
;
4753 const_tree fndecl
= NULL_TREE
;
4755 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
4758 fntype
= TREE_TYPE (fntype
);
4761 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4764 pcs_variant
= arm_pcs_default
;
4766 /* Promote integer types. */
4767 if (type
&& INTEGRAL_TYPE_P (type
))
4768 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, fntype
, 1);
4770 if (pcs_variant
!= ARM_PCS_AAPCS
)
4774 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4775 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
, mode
,
4777 return aapcs_cp_arg_layout
[i
].allocate_return_reg (pcs_variant
,
4781 /* Promotes small structs returned in a register to full-word size
4782 for big-endian AAPCS. */
4783 if (type
&& arm_return_in_msb (type
))
4785 HOST_WIDE_INT size
= int_size_in_bytes (type
);
4786 if (size
% UNITS_PER_WORD
!= 0)
4788 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
4789 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
4793 return gen_rtx_REG (mode
, R0_REGNUM
);
4797 aapcs_libcall_value (enum machine_mode mode
)
4799 if (BYTES_BIG_ENDIAN
&& ALL_FIXED_POINT_MODE_P (mode
)
4800 && GET_MODE_SIZE (mode
) <= 4)
4803 return aapcs_allocate_return_reg (mode
, NULL_TREE
, NULL_TREE
);
4806 /* Lay out a function argument using the AAPCS rules. The rule
4807 numbers referred to here are those in the AAPCS. */
4809 aapcs_layout_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4810 const_tree type
, bool named
)
4815 /* We only need to do this once per argument. */
4816 if (pcum
->aapcs_arg_processed
)
4819 pcum
->aapcs_arg_processed
= true;
4821 /* Special case: if named is false then we are handling an incoming
4822 anonymous argument which is on the stack. */
4826 /* Is this a potential co-processor register candidate? */
4827 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
4829 int slot
= aapcs_select_call_coproc (pcum
, mode
, type
);
4830 pcum
->aapcs_cprc_slot
= slot
;
4832 /* We don't have to apply any of the rules from part B of the
4833 preparation phase, these are handled elsewhere in the
4838 /* A Co-processor register candidate goes either in its own
4839 class of registers or on the stack. */
4840 if (!pcum
->aapcs_cprc_failed
[slot
])
4842 /* C1.cp - Try to allocate the argument to co-processor
4844 if (aapcs_cp_arg_layout
[slot
].allocate (pcum
, mode
, type
))
4847 /* C2.cp - Put the argument on the stack and note that we
4848 can't assign any more candidates in this slot. We also
4849 need to note that we have allocated stack space, so that
4850 we won't later try to split a non-cprc candidate between
4851 core registers and the stack. */
4852 pcum
->aapcs_cprc_failed
[slot
] = true;
4853 pcum
->can_split
= false;
4856 /* We didn't get a register, so this argument goes on the
4858 gcc_assert (pcum
->can_split
== false);
4863 /* C3 - For double-word aligned arguments, round the NCRN up to the
4864 next even number. */
4865 ncrn
= pcum
->aapcs_ncrn
;
4866 if ((ncrn
& 1) && arm_needs_doubleword_align (mode
, type
))
4869 nregs
= ARM_NUM_REGS2(mode
, type
);
4871 /* Sigh, this test should really assert that nregs > 0, but a GCC
4872 extension allows empty structs and then gives them empty size; it
4873 then allows such a structure to be passed by value. For some of
4874 the code below we have to pretend that such an argument has
4875 non-zero size so that we 'locate' it correctly either in
4876 registers or on the stack. */
4877 gcc_assert (nregs
>= 0);
4879 nregs2
= nregs
? nregs
: 1;
4881 /* C4 - Argument fits entirely in core registers. */
4882 if (ncrn
+ nregs2
<= NUM_ARG_REGS
)
4884 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
4885 pcum
->aapcs_next_ncrn
= ncrn
+ nregs
;
4889 /* C5 - Some core registers left and there are no arguments already
4890 on the stack: split this argument between the remaining core
4891 registers and the stack. */
4892 if (ncrn
< NUM_ARG_REGS
&& pcum
->can_split
)
4894 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
4895 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
4896 pcum
->aapcs_partial
= (NUM_ARG_REGS
- ncrn
) * UNITS_PER_WORD
;
4900 /* C6 - NCRN is set to 4. */
4901 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
4903 /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
4907 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4908 for a call to a function whose data type is FNTYPE.
4909 For a library call, FNTYPE is NULL. */
4911 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
4913 tree fndecl ATTRIBUTE_UNUSED
)
4915 /* Long call handling. */
4917 pcum
->pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4919 pcum
->pcs_variant
= arm_pcs_default
;
4921 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4923 if (arm_libcall_uses_aapcs_base (libname
))
4924 pcum
->pcs_variant
= ARM_PCS_AAPCS
;
4926 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
= 0;
4927 pcum
->aapcs_reg
= NULL_RTX
;
4928 pcum
->aapcs_partial
= 0;
4929 pcum
->aapcs_arg_processed
= false;
4930 pcum
->aapcs_cprc_slot
= -1;
4931 pcum
->can_split
= true;
4933 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
4937 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4939 pcum
->aapcs_cprc_failed
[i
] = false;
4940 aapcs_cp_arg_layout
[i
].cum_init (pcum
, fntype
, libname
, fndecl
);
4948 /* On the ARM, the offset starts at 0. */
4950 pcum
->iwmmxt_nregs
= 0;
4951 pcum
->can_split
= true;
4953 /* Varargs vectors are treated the same as long long.
4954 named_count avoids having to change the way arm handles 'named' */
4955 pcum
->named_count
= 0;
4958 if (TARGET_REALLY_IWMMXT
&& fntype
)
4962 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
4964 fn_arg
= TREE_CHAIN (fn_arg
))
4965 pcum
->named_count
+= 1;
4967 if (! pcum
->named_count
)
4968 pcum
->named_count
= INT_MAX
;
4973 /* Return true if mode/type need doubleword alignment. */
4975 arm_needs_doubleword_align (enum machine_mode mode
, const_tree type
)
4977 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
4978 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
4982 /* Determine where to put an argument to a function.
4983 Value is zero to push the argument on the stack,
4984 or a hard register in which to store the argument.
4986 MODE is the argument's machine mode.
4987 TYPE is the data type of the argument (as a tree).
4988 This is null for libcalls where that information may
4990 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4991 the preceding args and about the function being called.
4992 NAMED is nonzero if this argument is a named parameter
4993 (otherwise it is an extra parameter matching an ellipsis).
4995 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
4996 other arguments are passed on the stack. If (NAMED == 0) (which happens
4997 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
4998 defined), say it is passed in the stack (function_prologue will
4999 indeed make it pass in the stack if necessary). */
5002 arm_function_arg (cumulative_args_t pcum_v
, enum machine_mode mode
,
5003 const_tree type
, bool named
)
5005 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
5008 /* Handle the special case quickly. Pick an arbitrary value for op2 of
5009 a call insn (op3 of a call_value insn). */
5010 if (mode
== VOIDmode
)
5013 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
5015 aapcs_layout_arg (pcum
, mode
, type
, named
);
5016 return pcum
->aapcs_reg
;
5019 /* Varargs vectors are treated the same as long long.
5020 named_count avoids having to change the way arm handles 'named' */
5021 if (TARGET_IWMMXT_ABI
5022 && arm_vector_mode_supported_p (mode
)
5023 && pcum
->named_count
> pcum
->nargs
+ 1)
5025 if (pcum
->iwmmxt_nregs
<= 9)
5026 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
5029 pcum
->can_split
= false;
5034 /* Put doubleword aligned quantities in even register pairs. */
5036 && ARM_DOUBLEWORD_ALIGN
5037 && arm_needs_doubleword_align (mode
, type
))
5040 /* Only allow splitting an arg between regs and memory if all preceding
5041 args were allocated to regs. For args passed by reference we only count
5042 the reference pointer. */
5043 if (pcum
->can_split
)
5046 nregs
= ARM_NUM_REGS2 (mode
, type
);
5048 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
5051 return gen_rtx_REG (mode
, pcum
->nregs
);
5055 arm_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5057 return (ARM_DOUBLEWORD_ALIGN
&& arm_needs_doubleword_align (mode
, type
)
5058 ? DOUBLEWORD_ALIGNMENT
5063 arm_arg_partial_bytes (cumulative_args_t pcum_v
, enum machine_mode mode
,
5064 tree type
, bool named
)
5066 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
5067 int nregs
= pcum
->nregs
;
5069 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
5071 aapcs_layout_arg (pcum
, mode
, type
, named
);
5072 return pcum
->aapcs_partial
;
5075 if (TARGET_IWMMXT_ABI
&& arm_vector_mode_supported_p (mode
))
5078 if (NUM_ARG_REGS
> nregs
5079 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
5081 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
5086 /* Update the data in PCUM to advance over an argument
5087 of mode MODE and data type TYPE.
5088 (TYPE is null for libcalls where that information may not be available.) */
5091 arm_function_arg_advance (cumulative_args_t pcum_v
, enum machine_mode mode
,
5092 const_tree type
, bool named
)
5094 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
5096 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
5098 aapcs_layout_arg (pcum
, mode
, type
, named
);
5100 if (pcum
->aapcs_cprc_slot
>= 0)
5102 aapcs_cp_arg_layout
[pcum
->aapcs_cprc_slot
].advance (pcum
, mode
,
5104 pcum
->aapcs_cprc_slot
= -1;
5107 /* Generic stuff. */
5108 pcum
->aapcs_arg_processed
= false;
5109 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
;
5110 pcum
->aapcs_reg
= NULL_RTX
;
5111 pcum
->aapcs_partial
= 0;
5116 if (arm_vector_mode_supported_p (mode
)
5117 && pcum
->named_count
> pcum
->nargs
5118 && TARGET_IWMMXT_ABI
)
5119 pcum
->iwmmxt_nregs
+= 1;
5121 pcum
->nregs
+= ARM_NUM_REGS2 (mode
, type
);
5125 /* Variable sized types are passed by reference. This is a GCC
5126 extension to the ARM ABI. */
5129 arm_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5130 enum machine_mode mode ATTRIBUTE_UNUSED
,
5131 const_tree type
, bool named ATTRIBUTE_UNUSED
)
5133 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
5136 /* Encode the current state of the #pragma [no_]long_calls. */
5139 OFF
, /* No #pragma [no_]long_calls is in effect. */
5140 LONG
, /* #pragma long_calls is in effect. */
5141 SHORT
/* #pragma no_long_calls is in effect. */
5144 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
5147 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
5149 arm_pragma_long_calls
= LONG
;
5153 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
5155 arm_pragma_long_calls
= SHORT
;
5159 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
5161 arm_pragma_long_calls
= OFF
;
5164 /* Handle an attribute requiring a FUNCTION_DECL;
5165 arguments as in struct attribute_spec.handler. */
5167 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
5168 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
5170 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5172 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5174 *no_add_attrs
= true;
5180 /* Handle an "interrupt" or "isr" attribute;
5181 arguments as in struct attribute_spec.handler. */
5183 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
5188 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5190 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5192 *no_add_attrs
= true;
5194 /* FIXME: the argument if any is checked for type attributes;
5195 should it be checked for decl ones? */
5199 if (TREE_CODE (*node
) == FUNCTION_TYPE
5200 || TREE_CODE (*node
) == METHOD_TYPE
)
5202 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
5204 warning (OPT_Wattributes
, "%qE attribute ignored",
5206 *no_add_attrs
= true;
5209 else if (TREE_CODE (*node
) == POINTER_TYPE
5210 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
5211 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
5212 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
5214 *node
= build_variant_type_copy (*node
);
5215 TREE_TYPE (*node
) = build_type_attribute_variant
5217 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
5218 *no_add_attrs
= true;
5222 /* Possibly pass this attribute on from the type to a decl. */
5223 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
5224 | (int) ATTR_FLAG_FUNCTION_NEXT
5225 | (int) ATTR_FLAG_ARRAY_NEXT
))
5227 *no_add_attrs
= true;
5228 return tree_cons (name
, args
, NULL_TREE
);
5232 warning (OPT_Wattributes
, "%qE attribute ignored",
5241 /* Handle a "pcs" attribute; arguments as in struct
5242 attribute_spec.handler. */
5244 arm_handle_pcs_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
5245 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
5247 if (arm_pcs_from_attribute (args
) == ARM_PCS_UNKNOWN
)
5249 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
5250 *no_add_attrs
= true;
5255 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
5256 /* Handle the "notshared" attribute. This attribute is another way of
5257 requesting hidden visibility. ARM's compiler supports
5258 "__declspec(notshared)"; we support the same thing via an
5262 arm_handle_notshared_attribute (tree
*node
,
5263 tree name ATTRIBUTE_UNUSED
,
5264 tree args ATTRIBUTE_UNUSED
,
5265 int flags ATTRIBUTE_UNUSED
,
5268 tree decl
= TYPE_NAME (*node
);
5272 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
5273 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
5274 *no_add_attrs
= false;
5280 /* Return 0 if the attributes for two types are incompatible, 1 if they
5281 are compatible, and 2 if they are nearly compatible (which causes a
5282 warning to be generated). */
5284 arm_comp_type_attributes (const_tree type1
, const_tree type2
)
5288 /* Check for mismatch of non-default calling convention. */
5289 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
5292 /* Check for mismatched call attributes. */
5293 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
5294 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
5295 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
5296 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
5298 /* Only bother to check if an attribute is defined. */
5299 if (l1
| l2
| s1
| s2
)
5301 /* If one type has an attribute, the other must have the same attribute. */
5302 if ((l1
!= l2
) || (s1
!= s2
))
5305 /* Disallow mixed attributes. */
5306 if ((l1
& s2
) || (l2
& s1
))
5310 /* Check for mismatched ISR attribute. */
5311 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
5313 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
5314 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
5316 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
5323 /* Assigns default attributes to newly defined type. This is used to
5324 set short_call/long_call attributes for function types of
5325 functions defined inside corresponding #pragma scopes. */
5327 arm_set_default_type_attributes (tree type
)
5329 /* Add __attribute__ ((long_call)) to all functions, when
5330 inside #pragma long_calls or __attribute__ ((short_call)),
5331 when inside #pragma no_long_calls. */
5332 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
5334 tree type_attr_list
, attr_name
;
5335 type_attr_list
= TYPE_ATTRIBUTES (type
);
5337 if (arm_pragma_long_calls
== LONG
)
5338 attr_name
= get_identifier ("long_call");
5339 else if (arm_pragma_long_calls
== SHORT
)
5340 attr_name
= get_identifier ("short_call");
5344 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
5345 TYPE_ATTRIBUTES (type
) = type_attr_list
;
5349 /* Return true if DECL is known to be linked into section SECTION. */
5352 arm_function_in_section_p (tree decl
, section
*section
)
5354 /* We can only be certain about functions defined in the same
5355 compilation unit. */
5356 if (!TREE_STATIC (decl
))
5359 /* Make sure that SYMBOL always binds to the definition in this
5360 compilation unit. */
5361 if (!targetm
.binds_local_p (decl
))
5364 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
5365 if (!DECL_SECTION_NAME (decl
))
5367 /* Make sure that we will not create a unique section for DECL. */
5368 if (flag_function_sections
|| DECL_ONE_ONLY (decl
))
5372 return function_section (decl
) == section
;
5375 /* Return nonzero if a 32-bit "long_call" should be generated for
5376 a call from the current function to DECL. We generate a long_call
5379 a. has an __attribute__((long call))
5380 or b. is within the scope of a #pragma long_calls
5381 or c. the -mlong-calls command line switch has been specified
5383 However we do not generate a long call if the function:
5385 d. has an __attribute__ ((short_call))
5386 or e. is inside the scope of a #pragma no_long_calls
5387 or f. is defined in the same section as the current function. */
5390 arm_is_long_call_p (tree decl
)
5395 return TARGET_LONG_CALLS
;
5397 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
5398 if (lookup_attribute ("short_call", attrs
))
5401 /* For "f", be conservative, and only cater for cases in which the
5402 whole of the current function is placed in the same section. */
5403 if (!flag_reorder_blocks_and_partition
5404 && TREE_CODE (decl
) == FUNCTION_DECL
5405 && arm_function_in_section_p (decl
, current_function_section ()))
5408 if (lookup_attribute ("long_call", attrs
))
5411 return TARGET_LONG_CALLS
;
5414 /* Return nonzero if it is ok to make a tail-call to DECL. */
5416 arm_function_ok_for_sibcall (tree decl
, tree exp
)
5418 unsigned long func_type
;
5420 if (cfun
->machine
->sibcall_blocked
)
5423 /* Never tailcall something if we are generating code for Thumb-1. */
5427 /* The PIC register is live on entry to VxWorks PLT entries, so we
5428 must make the call before restoring the PIC register. */
5429 if (TARGET_VXWORKS_RTP
&& flag_pic
&& !targetm
.binds_local_p (decl
))
5432 /* Cannot tail-call to long calls, since these are out of range of
5433 a branch instruction. */
5434 if (decl
&& arm_is_long_call_p (decl
))
5437 /* If we are interworking and the function is not declared static
5438 then we can't tail-call it unless we know that it exists in this
5439 compilation unit (since it might be a Thumb routine). */
5440 if (TARGET_INTERWORK
&& decl
&& TREE_PUBLIC (decl
)
5441 && !TREE_ASM_WRITTEN (decl
))
5444 func_type
= arm_current_func_type ();
5445 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
5446 if (IS_INTERRUPT (func_type
))
5449 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
5451 /* Check that the return value locations are the same. For
5452 example that we aren't returning a value from the sibling in
5453 a VFP register but then need to transfer it to a core
5457 a
= arm_function_value (TREE_TYPE (exp
), decl
, false);
5458 b
= arm_function_value (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
5460 if (!rtx_equal_p (a
, b
))
5464 /* Never tailcall if function may be called with a misaligned SP. */
5465 if (IS_STACKALIGN (func_type
))
5468 /* The AAPCS says that, on bare-metal, calls to unresolved weak
5469 references should become a NOP. Don't convert such calls into
5471 if (TARGET_AAPCS_BASED
5472 && arm_abi
== ARM_ABI_AAPCS
5474 && DECL_WEAK (decl
))
5477 /* Everything else is ok. */
5482 /* Addressing mode support functions. */
5484 /* Return nonzero if X is a legitimate immediate operand when compiling
5485 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
5487 legitimate_pic_operand_p (rtx x
)
5489 if (GET_CODE (x
) == SYMBOL_REF
5490 || (GET_CODE (x
) == CONST
5491 && GET_CODE (XEXP (x
, 0)) == PLUS
5492 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
5498 /* Record that the current function needs a PIC register. Initialize
5499 cfun->machine->pic_reg if we have not already done so. */
5502 require_pic_register (void)
5504 /* A lot of the logic here is made obscure by the fact that this
5505 routine gets called as part of the rtx cost estimation process.
5506 We don't want those calls to affect any assumptions about the real
5507 function; and further, we can't call entry_of_function() until we
5508 start the real expansion process. */
5509 if (!crtl
->uses_pic_offset_table
)
5511 gcc_assert (can_create_pseudo_p ());
5512 if (arm_pic_register
!= INVALID_REGNUM
)
5514 if (!cfun
->machine
->pic_reg
)
5515 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
5517 /* Play games to avoid marking the function as needing pic
5518 if we are being called as part of the cost-estimation
5520 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
5521 crtl
->uses_pic_offset_table
= 1;
5527 if (!cfun
->machine
->pic_reg
)
5528 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
5530 /* Play games to avoid marking the function as needing pic
5531 if we are being called as part of the cost-estimation
5533 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
5535 crtl
->uses_pic_offset_table
= 1;
5538 arm_load_pic_register (0UL);
5543 for (insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
5545 INSN_LOCATION (insn
) = prologue_location
;
5547 /* We can be called during expansion of PHI nodes, where
5548 we can't yet emit instructions directly in the final
5549 insn stream. Queue the insns on the entry edge, they will
5550 be committed after everything else is expanded. */
5551 insert_insn_on_edge (seq
, single_succ_edge (ENTRY_BLOCK_PTR
));
5558 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
5560 if (GET_CODE (orig
) == SYMBOL_REF
5561 || GET_CODE (orig
) == LABEL_REF
)
5567 gcc_assert (can_create_pseudo_p ());
5568 reg
= gen_reg_rtx (Pmode
);
5571 /* VxWorks does not impose a fixed gap between segments; the run-time
5572 gap can be different from the object-file gap. We therefore can't
5573 use GOTOFF unless we are absolutely sure that the symbol is in the
5574 same segment as the GOT. Unfortunately, the flexibility of linker
5575 scripts means that we can't be sure of that in general, so assume
5576 that GOTOFF is never valid on VxWorks. */
5577 if ((GET_CODE (orig
) == LABEL_REF
5578 || (GET_CODE (orig
) == SYMBOL_REF
&&
5579 SYMBOL_REF_LOCAL_P (orig
)))
5581 && !TARGET_VXWORKS_RTP
)
5582 insn
= arm_pic_static_addr (orig
, reg
);
5588 /* If this function doesn't have a pic register, create one now. */
5589 require_pic_register ();
5591 pat
= gen_calculate_pic_address (reg
, cfun
->machine
->pic_reg
, orig
);
5593 /* Make the MEM as close to a constant as possible. */
5594 mem
= SET_SRC (pat
);
5595 gcc_assert (MEM_P (mem
) && !MEM_VOLATILE_P (mem
));
5596 MEM_READONLY_P (mem
) = 1;
5597 MEM_NOTRAP_P (mem
) = 1;
5599 insn
= emit_insn (pat
);
5602 /* Put a REG_EQUAL note on this insn, so that it can be optimized
5604 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
5608 else if (GET_CODE (orig
) == CONST
)
5612 if (GET_CODE (XEXP (orig
, 0)) == PLUS
5613 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
5616 /* Handle the case where we have: const (UNSPEC_TLS). */
5617 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
5618 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
5621 /* Handle the case where we have:
5622 const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a
5624 if (GET_CODE (XEXP (orig
, 0)) == PLUS
5625 && GET_CODE (XEXP (XEXP (orig
, 0), 0)) == UNSPEC
5626 && XINT (XEXP (XEXP (orig
, 0), 0), 1) == UNSPEC_TLS
)
5628 gcc_assert (CONST_INT_P (XEXP (XEXP (orig
, 0), 1)));
5634 gcc_assert (can_create_pseudo_p ());
5635 reg
= gen_reg_rtx (Pmode
);
5638 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
5640 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
5641 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
5642 base
== reg
? 0 : reg
);
5644 if (CONST_INT_P (offset
))
5646 /* The base register doesn't really matter, we only want to
5647 test the index for the appropriate mode. */
5648 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
5650 gcc_assert (can_create_pseudo_p ());
5651 offset
= force_reg (Pmode
, offset
);
5654 if (CONST_INT_P (offset
))
5655 return plus_constant (Pmode
, base
, INTVAL (offset
));
5658 if (GET_MODE_SIZE (mode
) > 4
5659 && (GET_MODE_CLASS (mode
) == MODE_INT
5660 || TARGET_SOFT_FLOAT
))
5662 emit_insn (gen_addsi3 (reg
, base
, offset
));
5666 return gen_rtx_PLUS (Pmode
, base
, offset
);
5673 /* Find a spare register to use during the prolog of a function. */
5676 thumb_find_work_register (unsigned long pushed_regs_mask
)
5680 /* Check the argument registers first as these are call-used. The
5681 register allocation order means that sometimes r3 might be used
5682 but earlier argument registers might not, so check them all. */
5683 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
5684 if (!df_regs_ever_live_p (reg
))
5687 /* Before going on to check the call-saved registers we can try a couple
5688 more ways of deducing that r3 is available. The first is when we are
5689 pushing anonymous arguments onto the stack and we have less than 4
5690 registers worth of fixed arguments(*). In this case r3 will be part of
5691 the variable argument list and so we can be sure that it will be
5692 pushed right at the start of the function. Hence it will be available
5693 for the rest of the prologue.
5694 (*): ie crtl->args.pretend_args_size is greater than 0. */
5695 if (cfun
->machine
->uses_anonymous_args
5696 && crtl
->args
.pretend_args_size
> 0)
5697 return LAST_ARG_REGNUM
;
5699 /* The other case is when we have fixed arguments but less than 4 registers
5700 worth. In this case r3 might be used in the body of the function, but
5701 it is not being used to convey an argument into the function. In theory
5702 we could just check crtl->args.size to see how many bytes are
5703 being passed in argument registers, but it seems that it is unreliable.
5704 Sometimes it will have the value 0 when in fact arguments are being
5705 passed. (See testcase execute/20021111-1.c for an example). So we also
5706 check the args_info.nregs field as well. The problem with this field is
5707 that it makes no allowances for arguments that are passed to the
5708 function but which are not used. Hence we could miss an opportunity
5709 when a function has an unused argument in r3. But it is better to be
5710 safe than to be sorry. */
5711 if (! cfun
->machine
->uses_anonymous_args
5712 && crtl
->args
.size
>= 0
5713 && crtl
->args
.size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
5714 && (TARGET_AAPCS_BASED
5715 ? crtl
->args
.info
.aapcs_ncrn
< 4
5716 : crtl
->args
.info
.nregs
< 4))
5717 return LAST_ARG_REGNUM
;
5719 /* Otherwise look for a call-saved register that is going to be pushed. */
5720 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
5721 if (pushed_regs_mask
& (1 << reg
))
5726 /* Thumb-2 can use high regs. */
5727 for (reg
= FIRST_HI_REGNUM
; reg
< 15; reg
++)
5728 if (pushed_regs_mask
& (1 << reg
))
5731 /* Something went wrong - thumb_compute_save_reg_mask()
5732 should have arranged for a suitable register to be pushed. */
5736 static GTY(()) int pic_labelno
;
5738 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
5742 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
5744 rtx l1
, labelno
, pic_tmp
, pic_rtx
, pic_reg
;
5746 if (crtl
->uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
5749 gcc_assert (flag_pic
);
5751 pic_reg
= cfun
->machine
->pic_reg
;
5752 if (TARGET_VXWORKS_RTP
)
5754 pic_rtx
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_BASE
);
5755 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
5756 emit_insn (gen_pic_load_addr_32bit (pic_reg
, pic_rtx
));
5758 emit_insn (gen_rtx_SET (Pmode
, pic_reg
, gen_rtx_MEM (Pmode
, pic_reg
)));
5760 pic_tmp
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_INDEX
);
5761 emit_insn (gen_pic_offset_arm (pic_reg
, pic_reg
, pic_tmp
));
5765 /* We use an UNSPEC rather than a LABEL_REF because this label
5766 never appears in the code stream. */
5768 labelno
= GEN_INT (pic_labelno
++);
5769 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5770 l1
= gen_rtx_CONST (VOIDmode
, l1
);
5772 /* On the ARM the PC register contains 'dot + 8' at the time of the
5773 addition, on the Thumb it is 'dot + 4'. */
5774 pic_rtx
= plus_constant (Pmode
, l1
, TARGET_ARM
? 8 : 4);
5775 pic_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, pic_rtx
),
5777 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
5781 emit_insn (gen_pic_load_addr_unified (pic_reg
, pic_rtx
, labelno
));
5783 else /* TARGET_THUMB1 */
5785 if (arm_pic_register
!= INVALID_REGNUM
5786 && REGNO (pic_reg
) > LAST_LO_REGNUM
)
5788 /* We will have pushed the pic register, so we should always be
5789 able to find a work register. */
5790 pic_tmp
= gen_rtx_REG (SImode
,
5791 thumb_find_work_register (saved_regs
));
5792 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp
, pic_rtx
));
5793 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
5794 emit_insn (gen_pic_add_dot_plus_four (pic_reg
, pic_reg
, labelno
));
5797 emit_insn (gen_pic_load_addr_unified (pic_reg
, pic_rtx
, labelno
));
5801 /* Need to emit this whether or not we obey regdecls,
5802 since setjmp/longjmp can cause life info to screw up. */
5806 /* Generate code to load the address of a static var when flag_pic is set. */
5808 arm_pic_static_addr (rtx orig
, rtx reg
)
5810 rtx l1
, labelno
, offset_rtx
, insn
;
5812 gcc_assert (flag_pic
);
5814 /* We use an UNSPEC rather than a LABEL_REF because this label
5815 never appears in the code stream. */
5816 labelno
= GEN_INT (pic_labelno
++);
5817 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5818 l1
= gen_rtx_CONST (VOIDmode
, l1
);
5820 /* On the ARM the PC register contains 'dot + 8' at the time of the
5821 addition, on the Thumb it is 'dot + 4'. */
5822 offset_rtx
= plus_constant (Pmode
, l1
, TARGET_ARM
? 8 : 4);
5823 offset_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, orig
, offset_rtx
),
5824 UNSPEC_SYMBOL_OFFSET
);
5825 offset_rtx
= gen_rtx_CONST (Pmode
, offset_rtx
);
5827 insn
= emit_insn (gen_pic_load_addr_unified (reg
, offset_rtx
, labelno
));
5831 /* Return nonzero if X is valid as an ARM state addressing register. */
5833 arm_address_register_rtx_p (rtx x
, int strict_p
)
5843 return ARM_REGNO_OK_FOR_BASE_P (regno
);
5845 return (regno
<= LAST_ARM_REGNUM
5846 || regno
>= FIRST_PSEUDO_REGISTER
5847 || regno
== FRAME_POINTER_REGNUM
5848 || regno
== ARG_POINTER_REGNUM
);
5851 /* Return TRUE if this rtx is the difference of a symbol and a label,
5852 and will reduce to a PC-relative relocation in the object file.
5853 Expressions like this can be left alone when generating PIC, rather
5854 than forced through the GOT. */
5856 pcrel_constant_p (rtx x
)
5858 if (GET_CODE (x
) == MINUS
)
5859 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
5864 /* Return true if X will surely end up in an index register after next
5867 will_be_in_index_register (const_rtx x
)
5869 /* arm.md: calculate_pic_address will split this into a register. */
5870 return GET_CODE (x
) == UNSPEC
&& (XINT (x
, 1) == UNSPEC_PIC_SYM
);
5873 /* Return nonzero if X is a valid ARM state address operand. */
5875 arm_legitimate_address_outer_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
5879 enum rtx_code code
= GET_CODE (x
);
5881 if (arm_address_register_rtx_p (x
, strict_p
))
5884 use_ldrd
= (TARGET_LDRD
5886 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
5888 if (code
== POST_INC
|| code
== PRE_DEC
5889 || ((code
== PRE_INC
|| code
== POST_DEC
)
5890 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
5891 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
5893 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
5894 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
5895 && GET_CODE (XEXP (x
, 1)) == PLUS
5896 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5898 rtx addend
= XEXP (XEXP (x
, 1), 1);
5900 /* Don't allow ldrd post increment by register because it's hard
5901 to fixup invalid register choices. */
5903 && GET_CODE (x
) == POST_MODIFY
5907 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
5908 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
5911 /* After reload constants split into minipools will have addresses
5912 from a LABEL_REF. */
5913 else if (reload_completed
5914 && (code
== LABEL_REF
5916 && GET_CODE (XEXP (x
, 0)) == PLUS
5917 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5918 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))))
5921 else if (mode
== TImode
|| (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
)))
5924 else if (code
== PLUS
)
5926 rtx xop0
= XEXP (x
, 0);
5927 rtx xop1
= XEXP (x
, 1);
5929 return ((arm_address_register_rtx_p (xop0
, strict_p
)
5930 && ((CONST_INT_P (xop1
)
5931 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
5932 || (!strict_p
&& will_be_in_index_register (xop1
))))
5933 || (arm_address_register_rtx_p (xop1
, strict_p
)
5934 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
5938 /* Reload currently can't handle MINUS, so disable this for now */
5939 else if (GET_CODE (x
) == MINUS
)
5941 rtx xop0
= XEXP (x
, 0);
5942 rtx xop1
= XEXP (x
, 1);
5944 return (arm_address_register_rtx_p (xop0
, strict_p
)
5945 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
5949 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
5950 && code
== SYMBOL_REF
5951 && CONSTANT_POOL_ADDRESS_P (x
)
5953 && symbol_mentioned_p (get_pool_constant (x
))
5954 && ! pcrel_constant_p (get_pool_constant (x
))))
5960 /* Return nonzero if X is a valid Thumb-2 address operand. */
5962 thumb2_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
5965 enum rtx_code code
= GET_CODE (x
);
5967 if (arm_address_register_rtx_p (x
, strict_p
))
5970 use_ldrd
= (TARGET_LDRD
5972 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
5974 if (code
== POST_INC
|| code
== PRE_DEC
5975 || ((code
== PRE_INC
|| code
== POST_DEC
)
5976 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
5977 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
5979 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
5980 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
5981 && GET_CODE (XEXP (x
, 1)) == PLUS
5982 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5984 /* Thumb-2 only has autoincrement by constant. */
5985 rtx addend
= XEXP (XEXP (x
, 1), 1);
5986 HOST_WIDE_INT offset
;
5988 if (!CONST_INT_P (addend
))
5991 offset
= INTVAL(addend
);
5992 if (GET_MODE_SIZE (mode
) <= 4)
5993 return (offset
> -256 && offset
< 256);
5995 return (use_ldrd
&& offset
> -1024 && offset
< 1024
5996 && (offset
& 3) == 0);
5999 /* After reload constants split into minipools will have addresses
6000 from a LABEL_REF. */
6001 else if (reload_completed
6002 && (code
== LABEL_REF
6004 && GET_CODE (XEXP (x
, 0)) == PLUS
6005 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
6006 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))))
6009 else if (mode
== TImode
|| (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
)))
6012 else if (code
== PLUS
)
6014 rtx xop0
= XEXP (x
, 0);
6015 rtx xop1
= XEXP (x
, 1);
6017 return ((arm_address_register_rtx_p (xop0
, strict_p
)
6018 && (thumb2_legitimate_index_p (mode
, xop1
, strict_p
)
6019 || (!strict_p
&& will_be_in_index_register (xop1
))))
6020 || (arm_address_register_rtx_p (xop1
, strict_p
)
6021 && thumb2_legitimate_index_p (mode
, xop0
, strict_p
)));
6024 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
6025 && code
== SYMBOL_REF
6026 && CONSTANT_POOL_ADDRESS_P (x
)
6028 && symbol_mentioned_p (get_pool_constant (x
))
6029 && ! pcrel_constant_p (get_pool_constant (x
))))
6035 /* Return nonzero if INDEX is valid for an address index operand in
6038 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
6041 HOST_WIDE_INT range
;
6042 enum rtx_code code
= GET_CODE (index
);
6044 /* Standard coprocessor addressing modes. */
6045 if (TARGET_HARD_FLOAT
6047 && (mode
== SFmode
|| mode
== DFmode
))
6048 return (code
== CONST_INT
&& INTVAL (index
) < 1024
6049 && INTVAL (index
) > -1024
6050 && (INTVAL (index
) & 3) == 0);
6052 /* For quad modes, we restrict the constant offset to be slightly less
6053 than what the instruction format permits. We do this because for
6054 quad mode moves, we will actually decompose them into two separate
6055 double-mode reads or writes. INDEX must therefore be a valid
6056 (double-mode) offset and so should INDEX+8. */
6057 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
))
6058 return (code
== CONST_INT
6059 && INTVAL (index
) < 1016
6060 && INTVAL (index
) > -1024
6061 && (INTVAL (index
) & 3) == 0);
6063 /* We have no such constraint on double mode offsets, so we permit the
6064 full range of the instruction format. */
6065 if (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
))
6066 return (code
== CONST_INT
6067 && INTVAL (index
) < 1024
6068 && INTVAL (index
) > -1024
6069 && (INTVAL (index
) & 3) == 0);
6071 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
6072 return (code
== CONST_INT
6073 && INTVAL (index
) < 1024
6074 && INTVAL (index
) > -1024
6075 && (INTVAL (index
) & 3) == 0);
6077 if (arm_address_register_rtx_p (index
, strict_p
)
6078 && (GET_MODE_SIZE (mode
) <= 4))
6081 if (mode
== DImode
|| mode
== DFmode
)
6083 if (code
== CONST_INT
)
6085 HOST_WIDE_INT val
= INTVAL (index
);
6088 return val
> -256 && val
< 256;
6090 return val
> -4096 && val
< 4092;
6093 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
6096 if (GET_MODE_SIZE (mode
) <= 4
6100 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
6104 rtx xiop0
= XEXP (index
, 0);
6105 rtx xiop1
= XEXP (index
, 1);
6107 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
6108 && power_of_two_operand (xiop1
, SImode
))
6109 || (arm_address_register_rtx_p (xiop1
, strict_p
)
6110 && power_of_two_operand (xiop0
, SImode
)));
6112 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
6113 || code
== ASHIFT
|| code
== ROTATERT
)
6115 rtx op
= XEXP (index
, 1);
6117 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
6120 && INTVAL (op
) <= 31);
6124 /* For ARM v4 we may be doing a sign-extend operation during the
6130 || (outer
== SIGN_EXTEND
&& mode
== QImode
))
6136 range
= (mode
== HImode
|| mode
== HFmode
) ? 4095 : 4096;
6138 return (code
== CONST_INT
6139 && INTVAL (index
) < range
6140 && INTVAL (index
) > -range
);
6143 /* Return true if OP is a valid index scaling factor for Thumb-2 address
6144 index operand. i.e. 1, 2, 4 or 8. */
6146 thumb2_index_mul_operand (rtx op
)
6150 if (!CONST_INT_P (op
))
6154 return (val
== 1 || val
== 2 || val
== 4 || val
== 8);
6157 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
6159 thumb2_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
6161 enum rtx_code code
= GET_CODE (index
);
6163 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
6164 /* Standard coprocessor addressing modes. */
6165 if (TARGET_HARD_FLOAT
6167 && (mode
== SFmode
|| mode
== DFmode
))
6168 return (code
== CONST_INT
&& INTVAL (index
) < 1024
6169 /* Thumb-2 allows only > -256 index range for it's core register
6170 load/stores. Since we allow SF/DF in core registers, we have
6171 to use the intersection between -256~4096 (core) and -1024~1024
6173 && INTVAL (index
) > -256
6174 && (INTVAL (index
) & 3) == 0);
6176 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
6178 /* For DImode assume values will usually live in core regs
6179 and only allow LDRD addressing modes. */
6180 if (!TARGET_LDRD
|| mode
!= DImode
)
6181 return (code
== CONST_INT
6182 && INTVAL (index
) < 1024
6183 && INTVAL (index
) > -1024
6184 && (INTVAL (index
) & 3) == 0);
6187 /* For quad modes, we restrict the constant offset to be slightly less
6188 than what the instruction format permits. We do this because for
6189 quad mode moves, we will actually decompose them into two separate
6190 double-mode reads or writes. INDEX must therefore be a valid
6191 (double-mode) offset and so should INDEX+8. */
6192 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
))
6193 return (code
== CONST_INT
6194 && INTVAL (index
) < 1016
6195 && INTVAL (index
) > -1024
6196 && (INTVAL (index
) & 3) == 0);
6198 /* We have no such constraint on double mode offsets, so we permit the
6199 full range of the instruction format. */
6200 if (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
))
6201 return (code
== CONST_INT
6202 && INTVAL (index
) < 1024
6203 && INTVAL (index
) > -1024
6204 && (INTVAL (index
) & 3) == 0);
6206 if (arm_address_register_rtx_p (index
, strict_p
)
6207 && (GET_MODE_SIZE (mode
) <= 4))
6210 if (mode
== DImode
|| mode
== DFmode
)
6212 if (code
== CONST_INT
)
6214 HOST_WIDE_INT val
= INTVAL (index
);
6215 /* ??? Can we assume ldrd for thumb2? */
6216 /* Thumb-2 ldrd only has reg+const addressing modes. */
6217 /* ldrd supports offsets of +-1020.
6218 However the ldr fallback does not. */
6219 return val
> -256 && val
< 256 && (val
& 3) == 0;
6227 rtx xiop0
= XEXP (index
, 0);
6228 rtx xiop1
= XEXP (index
, 1);
6230 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
6231 && thumb2_index_mul_operand (xiop1
))
6232 || (arm_address_register_rtx_p (xiop1
, strict_p
)
6233 && thumb2_index_mul_operand (xiop0
)));
6235 else if (code
== ASHIFT
)
6237 rtx op
= XEXP (index
, 1);
6239 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
6242 && INTVAL (op
) <= 3);
6245 return (code
== CONST_INT
6246 && INTVAL (index
) < 4096
6247 && INTVAL (index
) > -256);
6250 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
6252 thumb1_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
6262 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
6264 return (regno
<= LAST_LO_REGNUM
6265 || regno
> LAST_VIRTUAL_REGISTER
6266 || regno
== FRAME_POINTER_REGNUM
6267 || (GET_MODE_SIZE (mode
) >= 4
6268 && (regno
== STACK_POINTER_REGNUM
6269 || regno
>= FIRST_PSEUDO_REGISTER
6270 || x
== hard_frame_pointer_rtx
6271 || x
== arg_pointer_rtx
)));
6274 /* Return nonzero if x is a legitimate index register. This is the case
6275 for any base register that can access a QImode object. */
6277 thumb1_index_register_rtx_p (rtx x
, int strict_p
)
6279 return thumb1_base_register_rtx_p (x
, QImode
, strict_p
);
6282 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
6284 The AP may be eliminated to either the SP or the FP, so we use the
6285 least common denominator, e.g. SImode, and offsets from 0 to 64.
6287 ??? Verify whether the above is the right approach.
6289 ??? Also, the FP may be eliminated to the SP, so perhaps that
6290 needs special handling also.
6292 ??? Look at how the mips16 port solves this problem. It probably uses
6293 better ways to solve some of these problems.
6295 Although it is not incorrect, we don't accept QImode and HImode
6296 addresses based on the frame pointer or arg pointer until the
6297 reload pass starts. This is so that eliminating such addresses
6298 into stack based ones won't produce impossible code. */
6300 thumb1_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
6302 /* ??? Not clear if this is right. Experiment. */
6303 if (GET_MODE_SIZE (mode
) < 4
6304 && !(reload_in_progress
|| reload_completed
)
6305 && (reg_mentioned_p (frame_pointer_rtx
, x
)
6306 || reg_mentioned_p (arg_pointer_rtx
, x
)
6307 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
6308 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
6309 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
6310 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
6313 /* Accept any base register. SP only in SImode or larger. */
6314 else if (thumb1_base_register_rtx_p (x
, mode
, strict_p
))
6317 /* This is PC relative data before arm_reorg runs. */
6318 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
6319 && GET_CODE (x
) == SYMBOL_REF
6320 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
6323 /* This is PC relative data after arm_reorg runs. */
6324 else if ((GET_MODE_SIZE (mode
) >= 4 || mode
== HFmode
)
6326 && (GET_CODE (x
) == LABEL_REF
6327 || (GET_CODE (x
) == CONST
6328 && GET_CODE (XEXP (x
, 0)) == PLUS
6329 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
6330 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))))
6333 /* Post-inc indexing only supported for SImode and larger. */
6334 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
6335 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
))
6338 else if (GET_CODE (x
) == PLUS
)
6340 /* REG+REG address can be any two index registers. */
6341 /* We disallow FRAME+REG addressing since we know that FRAME
6342 will be replaced with STACK, and SP relative addressing only
6343 permits SP+OFFSET. */
6344 if (GET_MODE_SIZE (mode
) <= 4
6345 && XEXP (x
, 0) != frame_pointer_rtx
6346 && XEXP (x
, 1) != frame_pointer_rtx
6347 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
6348 && (thumb1_index_register_rtx_p (XEXP (x
, 1), strict_p
)
6349 || (!strict_p
&& will_be_in_index_register (XEXP (x
, 1)))))
6352 /* REG+const has 5-7 bit offset for non-SP registers. */
6353 else if ((thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
6354 || XEXP (x
, 0) == arg_pointer_rtx
)
6355 && CONST_INT_P (XEXP (x
, 1))
6356 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
6359 /* REG+const has 10-bit offset for SP, but only SImode and
6360 larger is supported. */
6361 /* ??? Should probably check for DI/DFmode overflow here
6362 just like GO_IF_LEGITIMATE_OFFSET does. */
6363 else if (REG_P (XEXP (x
, 0))
6364 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
6365 && GET_MODE_SIZE (mode
) >= 4
6366 && CONST_INT_P (XEXP (x
, 1))
6367 && INTVAL (XEXP (x
, 1)) >= 0
6368 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
6369 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
6372 else if (REG_P (XEXP (x
, 0))
6373 && (REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
6374 || REGNO (XEXP (x
, 0)) == ARG_POINTER_REGNUM
6375 || (REGNO (XEXP (x
, 0)) >= FIRST_VIRTUAL_REGISTER
6376 && REGNO (XEXP (x
, 0))
6377 <= LAST_VIRTUAL_POINTER_REGISTER
))
6378 && GET_MODE_SIZE (mode
) >= 4
6379 && CONST_INT_P (XEXP (x
, 1))
6380 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
6384 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
6385 && GET_MODE_SIZE (mode
) == 4
6386 && GET_CODE (x
) == SYMBOL_REF
6387 && CONSTANT_POOL_ADDRESS_P (x
)
6389 && symbol_mentioned_p (get_pool_constant (x
))
6390 && ! pcrel_constant_p (get_pool_constant (x
))))
6396 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
6397 instruction of mode MODE. */
6399 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
6401 switch (GET_MODE_SIZE (mode
))
6404 return val
>= 0 && val
< 32;
6407 return val
>= 0 && val
< 64 && (val
& 1) == 0;
6411 && (val
+ GET_MODE_SIZE (mode
)) <= 128
6417 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
6420 return arm_legitimate_address_outer_p (mode
, x
, SET
, strict_p
);
6421 else if (TARGET_THUMB2
)
6422 return thumb2_legitimate_address_p (mode
, x
, strict_p
);
6423 else /* if (TARGET_THUMB1) */
6424 return thumb1_legitimate_address_p (mode
, x
, strict_p
);
6427 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
6429 Given an rtx X being reloaded into a reg required to be
6430 in class CLASS, return the class of reg to actually use.
6431 In general this is just CLASS, but for the Thumb core registers and
6432 immediate constants we prefer a LO_REGS class or a subset. */
6435 arm_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
6441 if (rclass
== GENERAL_REGS
6442 || rclass
== HI_REGS
6443 || rclass
== NO_REGS
6444 || rclass
== STACK_REG
)
6451 /* Build the SYMBOL_REF for __tls_get_addr. */
6453 static GTY(()) rtx tls_get_addr_libfunc
;
6456 get_tls_get_addr (void)
6458 if (!tls_get_addr_libfunc
)
6459 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
6460 return tls_get_addr_libfunc
;
6464 arm_load_tp (rtx target
)
6467 target
= gen_reg_rtx (SImode
);
6471 /* Can return in any reg. */
6472 emit_insn (gen_load_tp_hard (target
));
6476 /* Always returned in r0. Immediately copy the result into a pseudo,
6477 otherwise other uses of r0 (e.g. setting up function arguments) may
6478 clobber the value. */
6482 emit_insn (gen_load_tp_soft ());
6484 tmp
= gen_rtx_REG (SImode
, 0);
6485 emit_move_insn (target
, tmp
);
6491 load_tls_operand (rtx x
, rtx reg
)
6495 if (reg
== NULL_RTX
)
6496 reg
= gen_reg_rtx (SImode
);
6498 tmp
= gen_rtx_CONST (SImode
, x
);
6500 emit_move_insn (reg
, tmp
);
6506 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
6508 rtx insns
, label
, labelno
, sum
;
6510 gcc_assert (reloc
!= TLS_DESCSEQ
);
6513 labelno
= GEN_INT (pic_labelno
++);
6514 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
6515 label
= gen_rtx_CONST (VOIDmode
, label
);
6517 sum
= gen_rtx_UNSPEC (Pmode
,
6518 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
6519 GEN_INT (TARGET_ARM
? 8 : 4)),
6521 reg
= load_tls_operand (sum
, reg
);
6524 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
6526 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
6528 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
,
6529 LCT_PURE
, /* LCT_CONST? */
6530 Pmode
, 1, reg
, Pmode
);
6532 insns
= get_insns ();
6539 arm_tls_descseq_addr (rtx x
, rtx reg
)
6541 rtx labelno
= GEN_INT (pic_labelno
++);
6542 rtx label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
6543 rtx sum
= gen_rtx_UNSPEC (Pmode
,
6544 gen_rtvec (4, x
, GEN_INT (TLS_DESCSEQ
),
6545 gen_rtx_CONST (VOIDmode
, label
),
6546 GEN_INT (!TARGET_ARM
)),
6548 rtx reg0
= load_tls_operand (sum
, gen_rtx_REG (SImode
, 0));
6550 emit_insn (gen_tlscall (x
, labelno
));
6552 reg
= gen_reg_rtx (SImode
);
6554 gcc_assert (REGNO (reg
) != 0);
6556 emit_move_insn (reg
, reg0
);
6562 legitimize_tls_address (rtx x
, rtx reg
)
6564 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
6565 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
6569 case TLS_MODEL_GLOBAL_DYNAMIC
:
6570 if (TARGET_GNU2_TLS
)
6572 reg
= arm_tls_descseq_addr (x
, reg
);
6574 tp
= arm_load_tp (NULL_RTX
);
6576 dest
= gen_rtx_PLUS (Pmode
, tp
, reg
);
6580 /* Original scheme */
6581 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
6582 dest
= gen_reg_rtx (Pmode
);
6583 emit_libcall_block (insns
, dest
, ret
, x
);
6587 case TLS_MODEL_LOCAL_DYNAMIC
:
6588 if (TARGET_GNU2_TLS
)
6590 reg
= arm_tls_descseq_addr (x
, reg
);
6592 tp
= arm_load_tp (NULL_RTX
);
6594 dest
= gen_rtx_PLUS (Pmode
, tp
, reg
);
6598 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
6600 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
6601 share the LDM result with other LD model accesses. */
6602 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
6604 dest
= gen_reg_rtx (Pmode
);
6605 emit_libcall_block (insns
, dest
, ret
, eqv
);
6607 /* Load the addend. */
6608 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
,
6609 GEN_INT (TLS_LDO32
)),
6611 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
6612 dest
= gen_rtx_PLUS (Pmode
, dest
, addend
);
6616 case TLS_MODEL_INITIAL_EXEC
:
6617 labelno
= GEN_INT (pic_labelno
++);
6618 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
6619 label
= gen_rtx_CONST (VOIDmode
, label
);
6620 sum
= gen_rtx_UNSPEC (Pmode
,
6621 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
6622 GEN_INT (TARGET_ARM
? 8 : 4)),
6624 reg
= load_tls_operand (sum
, reg
);
6627 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
6628 else if (TARGET_THUMB2
)
6629 emit_insn (gen_tls_load_dot_plus_four (reg
, NULL
, reg
, labelno
));
6632 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
6633 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
6636 tp
= arm_load_tp (NULL_RTX
);
6638 return gen_rtx_PLUS (Pmode
, tp
, reg
);
6640 case TLS_MODEL_LOCAL_EXEC
:
6641 tp
= arm_load_tp (NULL_RTX
);
6643 reg
= gen_rtx_UNSPEC (Pmode
,
6644 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
6646 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
6648 return gen_rtx_PLUS (Pmode
, tp
, reg
);
6655 /* Try machine-dependent ways of modifying an illegitimate address
6656 to be legitimate. If we find one, return the new, valid address. */
6658 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
6662 /* TODO: legitimize_address for Thumb2. */
6665 return thumb_legitimize_address (x
, orig_x
, mode
);
6668 if (arm_tls_symbol_p (x
))
6669 return legitimize_tls_address (x
, NULL_RTX
);
6671 if (GET_CODE (x
) == PLUS
)
6673 rtx xop0
= XEXP (x
, 0);
6674 rtx xop1
= XEXP (x
, 1);
6676 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
6677 xop0
= force_reg (SImode
, xop0
);
6679 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
6680 xop1
= force_reg (SImode
, xop1
);
6682 if (ARM_BASE_REGISTER_RTX_P (xop0
)
6683 && CONST_INT_P (xop1
))
6685 HOST_WIDE_INT n
, low_n
;
6689 /* VFP addressing modes actually allow greater offsets, but for
6690 now we just stick with the lowest common denominator. */
6692 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
6704 low_n
= ((mode
) == TImode
? 0
6705 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
6709 base_reg
= gen_reg_rtx (SImode
);
6710 val
= force_operand (plus_constant (Pmode
, xop0
, n
), NULL_RTX
);
6711 emit_move_insn (base_reg
, val
);
6712 x
= plus_constant (Pmode
, base_reg
, low_n
);
6714 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
6715 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
6718 /* XXX We don't allow MINUS any more -- see comment in
6719 arm_legitimate_address_outer_p (). */
6720 else if (GET_CODE (x
) == MINUS
)
6722 rtx xop0
= XEXP (x
, 0);
6723 rtx xop1
= XEXP (x
, 1);
6725 if (CONSTANT_P (xop0
))
6726 xop0
= force_reg (SImode
, xop0
);
6728 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
6729 xop1
= force_reg (SImode
, xop1
);
6731 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
6732 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
6735 /* Make sure to take full advantage of the pre-indexed addressing mode
6736 with absolute addresses which often allows for the base register to
6737 be factorized for multiple adjacent memory references, and it might
6738 even allows for the mini pool to be avoided entirely. */
6739 else if (CONST_INT_P (x
) && optimize
> 0)
6742 HOST_WIDE_INT mask
, base
, index
;
6745 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
6746 use a 8-bit index. So let's use a 12-bit index for SImode only and
6747 hope that arm_gen_constant will enable ldrb to use more bits. */
6748 bits
= (mode
== SImode
) ? 12 : 8;
6749 mask
= (1 << bits
) - 1;
6750 base
= INTVAL (x
) & ~mask
;
6751 index
= INTVAL (x
) & mask
;
6752 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
6754 /* It'll most probably be more efficient to generate the base
6755 with more bits set and use a negative index instead. */
6759 base_reg
= force_reg (SImode
, GEN_INT (base
));
6760 x
= plus_constant (Pmode
, base_reg
, index
);
6765 /* We need to find and carefully transform any SYMBOL and LABEL
6766 references; so go back to the original address expression. */
6767 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
6769 if (new_x
!= orig_x
)
6777 /* Try machine-dependent ways of modifying an illegitimate Thumb address
6778 to be legitimate. If we find one, return the new, valid address. */
6780 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
6782 if (arm_tls_symbol_p (x
))
6783 return legitimize_tls_address (x
, NULL_RTX
);
6785 if (GET_CODE (x
) == PLUS
6786 && CONST_INT_P (XEXP (x
, 1))
6787 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
6788 || INTVAL (XEXP (x
, 1)) < 0))
6790 rtx xop0
= XEXP (x
, 0);
6791 rtx xop1
= XEXP (x
, 1);
6792 HOST_WIDE_INT offset
= INTVAL (xop1
);
6794 /* Try and fold the offset into a biasing of the base register and
6795 then offsetting that. Don't do this when optimizing for space
6796 since it can cause too many CSEs. */
6797 if (optimize_size
&& offset
>= 0
6798 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
6800 HOST_WIDE_INT delta
;
6803 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
6804 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
6805 delta
= 31 * GET_MODE_SIZE (mode
);
6807 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
6809 xop0
= force_operand (plus_constant (Pmode
, xop0
, offset
- delta
),
6811 x
= plus_constant (Pmode
, xop0
, delta
);
6813 else if (offset
< 0 && offset
> -256)
6814 /* Small negative offsets are best done with a subtract before the
6815 dereference, forcing these into a register normally takes two
6817 x
= force_operand (x
, NULL_RTX
);
6820 /* For the remaining cases, force the constant into a register. */
6821 xop1
= force_reg (SImode
, xop1
);
6822 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
6825 else if (GET_CODE (x
) == PLUS
6826 && s_register_operand (XEXP (x
, 1), SImode
)
6827 && !s_register_operand (XEXP (x
, 0), SImode
))
6829 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
6831 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
6836 /* We need to find and carefully transform any SYMBOL and LABEL
6837 references; so go back to the original address expression. */
6838 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
6840 if (new_x
!= orig_x
)
6848 arm_legitimize_reload_address (rtx
*p
,
6849 enum machine_mode mode
,
6850 int opnum
, int type
,
6851 int ind_levels ATTRIBUTE_UNUSED
)
6853 /* We must recognize output that we have already generated ourselves. */
6854 if (GET_CODE (*p
) == PLUS
6855 && GET_CODE (XEXP (*p
, 0)) == PLUS
6856 && REG_P (XEXP (XEXP (*p
, 0), 0))
6857 && CONST_INT_P (XEXP (XEXP (*p
, 0), 1))
6858 && CONST_INT_P (XEXP (*p
, 1)))
6860 push_reload (XEXP (*p
, 0), NULL_RTX
, &XEXP (*p
, 0), NULL
,
6861 MODE_BASE_REG_CLASS (mode
), GET_MODE (*p
),
6862 VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
6866 if (GET_CODE (*p
) == PLUS
6867 && REG_P (XEXP (*p
, 0))
6868 && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p
, 0)))
6869 /* If the base register is equivalent to a constant, let the generic
6870 code handle it. Otherwise we will run into problems if a future
6871 reload pass decides to rematerialize the constant. */
6872 && !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p
, 0)))
6873 && CONST_INT_P (XEXP (*p
, 1)))
6875 HOST_WIDE_INT val
= INTVAL (XEXP (*p
, 1));
6876 HOST_WIDE_INT low
, high
;
6878 /* Detect coprocessor load/stores. */
6879 bool coproc_p
= ((TARGET_HARD_FLOAT
6881 && (mode
== SFmode
|| mode
== DFmode
))
6882 || (TARGET_REALLY_IWMMXT
6883 && VALID_IWMMXT_REG_MODE (mode
))
6885 && (VALID_NEON_DREG_MODE (mode
)
6886 || VALID_NEON_QREG_MODE (mode
))));
6888 /* For some conditions, bail out when lower two bits are unaligned. */
6889 if ((val
& 0x3) != 0
6890 /* Coprocessor load/store indexes are 8-bits + '00' appended. */
6892 /* For DI, and DF under soft-float: */
6893 || ((mode
== DImode
|| mode
== DFmode
)
6894 /* Without ldrd, we use stm/ldm, which does not
6895 fair well with unaligned bits. */
6897 /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
6898 || TARGET_THUMB2
))))
6901 /* When breaking down a [reg+index] reload address into [(reg+high)+low],
6902 of which the (reg+high) gets turned into a reload add insn,
6903 we try to decompose the index into high/low values that can often
6904 also lead to better reload CSE.
6906 ldr r0, [r2, #4100] // Offset too large
6907 ldr r1, [r2, #4104] // Offset too large
6909 is best reloaded as:
6915 which post-reload CSE can simplify in most cases to eliminate the
6916 second add instruction:
6921 The idea here is that we want to split out the bits of the constant
6922 as a mask, rather than as subtracting the maximum offset that the
6923 respective type of load/store used can handle.
6925 When encountering negative offsets, we can still utilize it even if
6926 the overall offset is positive; sometimes this may lead to an immediate
6927 that can be constructed with fewer instructions.
6929 ldr r0, [r2, #0x3FFFFC]
6931 This is best reloaded as:
6932 add t1, r2, #0x400000
6935 The trick for spotting this for a load insn with N bits of offset
6936 (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
6937 negative offset that is going to make bit N and all the bits below
6938 it become zero in the remainder part.
6940 The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
6941 to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
6942 used in most cases of ARM load/store instructions. */
6944 #define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
6945 (((VAL) & ((1 << (N)) - 1)) \
6946 ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
6951 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 10);
6953 /* NEON quad-word load/stores are made of two double-word accesses,
6954 so the valid index range is reduced by 8. Treat as 9-bit range if
6956 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
) && low
>= 1016)
6957 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 9);
6959 else if (GET_MODE_SIZE (mode
) == 8)
6962 low
= (TARGET_THUMB2
6963 ? SIGN_MAG_LOW_ADDR_BITS (val
, 10)
6964 : SIGN_MAG_LOW_ADDR_BITS (val
, 8));
6966 /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
6967 to access doublewords. The supported load/store offsets are
6968 -8, -4, and 4, which we try to produce here. */
6969 low
= ((val
& 0xf) ^ 0x8) - 0x8;
6971 else if (GET_MODE_SIZE (mode
) < 8)
6973 /* NEON element load/stores do not have an offset. */
6974 if (TARGET_NEON_FP16
&& mode
== HFmode
)
6979 /* Thumb-2 has an asymmetrical index range of (-256,4096).
6980 Try the wider 12-bit range first, and re-try if the result
6982 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 12);
6984 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 8);
6988 if (mode
== HImode
|| mode
== HFmode
)
6991 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 8);
6994 /* The storehi/movhi_bytes fallbacks can use only
6995 [-4094,+4094] of the full ldrb/strb index range. */
6996 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 12);
6997 if (low
== 4095 || low
== -4095)
7002 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 12);
7008 high
= ((((val
- low
) & (unsigned HOST_WIDE_INT
) 0xffffffff)
7009 ^ (unsigned HOST_WIDE_INT
) 0x80000000)
7010 - (unsigned HOST_WIDE_INT
) 0x80000000);
7011 /* Check for overflow or zero */
7012 if (low
== 0 || high
== 0 || (high
+ low
!= val
))
7015 /* Reload the high part into a base reg; leave the low part
7017 *p
= gen_rtx_PLUS (GET_MODE (*p
),
7018 gen_rtx_PLUS (GET_MODE (*p
), XEXP (*p
, 0),
7021 push_reload (XEXP (*p
, 0), NULL_RTX
, &XEXP (*p
, 0), NULL
,
7022 MODE_BASE_REG_CLASS (mode
), GET_MODE (*p
),
7023 VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
7031 thumb_legitimize_reload_address (rtx
*x_p
,
7032 enum machine_mode mode
,
7033 int opnum
, int type
,
7034 int ind_levels ATTRIBUTE_UNUSED
)
7038 if (GET_CODE (x
) == PLUS
7039 && GET_MODE_SIZE (mode
) < 4
7040 && REG_P (XEXP (x
, 0))
7041 && XEXP (x
, 0) == stack_pointer_rtx
7042 && CONST_INT_P (XEXP (x
, 1))
7043 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
7048 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
7049 Pmode
, VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
7053 /* If both registers are hi-regs, then it's better to reload the
7054 entire expression rather than each register individually. That
7055 only requires one reload register rather than two. */
7056 if (GET_CODE (x
) == PLUS
7057 && REG_P (XEXP (x
, 0))
7058 && REG_P (XEXP (x
, 1))
7059 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
7060 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
7065 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
7066 Pmode
, VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
7073 /* Test for various thread-local symbols. */
7075 /* Return TRUE if X is a thread-local symbol. */
7078 arm_tls_symbol_p (rtx x
)
7080 if (! TARGET_HAVE_TLS
)
7083 if (GET_CODE (x
) != SYMBOL_REF
)
7086 return SYMBOL_REF_TLS_MODEL (x
) != 0;
7089 /* Helper for arm_tls_referenced_p. */
7092 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7094 if (GET_CODE (*x
) == SYMBOL_REF
)
7095 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
7097 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
7098 TLS offsets, not real symbol references. */
7099 if (GET_CODE (*x
) == UNSPEC
7100 && XINT (*x
, 1) == UNSPEC_TLS
)
7106 /* Return TRUE if X contains any TLS symbol references. */
7109 arm_tls_referenced_p (rtx x
)
7111 if (! TARGET_HAVE_TLS
)
7114 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
7117 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
7119 On the ARM, allow any integer (invalid ones are removed later by insn
7120 patterns), nice doubles and symbol_refs which refer to the function's
7123 When generating pic allow anything. */
7126 arm_legitimate_constant_p_1 (enum machine_mode mode
, rtx x
)
7128 /* At present, we have no support for Neon structure constants, so forbid
7129 them here. It might be possible to handle simple cases like 0 and -1
7131 if (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
))
7134 return flag_pic
|| !label_mentioned_p (x
);
7138 thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7140 return (CONST_INT_P (x
)
7141 || CONST_DOUBLE_P (x
)
7142 || CONSTANT_ADDRESS_P (x
)
7147 arm_legitimate_constant_p (enum machine_mode mode
, rtx x
)
7149 return (!arm_cannot_force_const_mem (mode
, x
)
7151 ? arm_legitimate_constant_p_1 (mode
, x
)
7152 : thumb_legitimate_constant_p (mode
, x
)));
7155 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7158 arm_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7162 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
7164 split_const (x
, &base
, &offset
);
7165 if (GET_CODE (base
) == SYMBOL_REF
7166 && !offset_within_block_p (base
, INTVAL (offset
)))
7169 return arm_tls_referenced_p (x
);
7172 #define REG_OR_SUBREG_REG(X) \
7174 || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))))
7176 #define REG_OR_SUBREG_RTX(X) \
7177 (REG_P (X) ? (X) : SUBREG_REG (X))
7180 thumb1_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
7182 enum machine_mode mode
= GET_MODE (x
);
7191 return (mode
== SImode
) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
7198 return COSTS_N_INSNS (1);
7201 if (CONST_INT_P (XEXP (x
, 1)))
7204 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
7211 return COSTS_N_INSNS (2) + cycles
;
7213 return COSTS_N_INSNS (1) + 16;
7216 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
7218 words
= ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x
))));
7219 return (COSTS_N_INSNS (words
)
7220 + 4 * ((MEM_P (SET_SRC (x
)))
7221 + MEM_P (SET_DEST (x
))));
7226 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
7228 if (thumb_shiftable_const (INTVAL (x
)))
7229 return COSTS_N_INSNS (2);
7230 return COSTS_N_INSNS (3);
7232 else if ((outer
== PLUS
|| outer
== COMPARE
)
7233 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
7235 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
7236 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
7237 return COSTS_N_INSNS (1);
7238 else if (outer
== AND
)
7241 /* This duplicates the tests in the andsi3 expander. */
7242 for (i
= 9; i
<= 31; i
++)
7243 if ((((HOST_WIDE_INT
) 1) << i
) - 1 == INTVAL (x
)
7244 || (((HOST_WIDE_INT
) 1) << i
) - 1 == ~INTVAL (x
))
7245 return COSTS_N_INSNS (2);
7247 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
7248 || outer
== LSHIFTRT
)
7250 return COSTS_N_INSNS (2);
7256 return COSTS_N_INSNS (3);
7274 /* XXX another guess. */
7275 /* Memory costs quite a lot for the first word, but subsequent words
7276 load at the equivalent of a single insn each. */
7277 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
7278 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
7283 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
7289 total
= mode
== DImode
? COSTS_N_INSNS (1) : 0;
7290 total
+= thumb1_rtx_costs (XEXP (x
, 0), GET_CODE (XEXP (x
, 0)), code
);
7296 return total
+ COSTS_N_INSNS (1);
7298 /* Assume a two-shift sequence. Increase the cost slightly so
7299 we prefer actual shifts over an extend operation. */
7300 return total
+ 1 + COSTS_N_INSNS (2);
7308 arm_rtx_costs_1 (rtx x
, enum rtx_code outer
, int* total
, bool speed
)
7310 enum machine_mode mode
= GET_MODE (x
);
7311 enum rtx_code subcode
;
7313 enum rtx_code code
= GET_CODE (x
);
7319 /* Memory costs quite a lot for the first word, but subsequent words
7320 load at the equivalent of a single insn each. */
7321 *total
= COSTS_N_INSNS (2 + ARM_NUM_REGS (mode
));
7328 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
7329 *total
= COSTS_N_INSNS (2);
7330 else if (TARGET_HARD_FLOAT
&& mode
== DFmode
&& !TARGET_VFP_SINGLE
)
7331 *total
= COSTS_N_INSNS (4);
7333 *total
= COSTS_N_INSNS (20);
7337 if (REG_P (XEXP (x
, 1)))
7338 *total
= COSTS_N_INSNS (1); /* Need to subtract from 32 */
7339 else if (!CONST_INT_P (XEXP (x
, 1)))
7340 *total
= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7346 *total
+= COSTS_N_INSNS (4);
7351 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
7352 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7355 *total
+= COSTS_N_INSNS (3);
7359 *total
+= COSTS_N_INSNS (1);
7360 /* Increase the cost of complex shifts because they aren't any faster,
7361 and reduce dual issue opportunities. */
7362 if (arm_tune_cortex_a9
7363 && outer
!= SET
&& !CONST_INT_P (XEXP (x
, 1)))
7371 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7372 if (CONST_INT_P (XEXP (x
, 0))
7373 && const_ok_for_arm (INTVAL (XEXP (x
, 0))))
7375 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7379 if (CONST_INT_P (XEXP (x
, 1))
7380 && const_ok_for_arm (INTVAL (XEXP (x
, 1))))
7382 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7389 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7391 if (TARGET_HARD_FLOAT
7393 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7395 *total
= COSTS_N_INSNS (1);
7396 if (CONST_DOUBLE_P (XEXP (x
, 0))
7397 && arm_const_double_rtx (XEXP (x
, 0)))
7399 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7403 if (CONST_DOUBLE_P (XEXP (x
, 1))
7404 && arm_const_double_rtx (XEXP (x
, 1)))
7406 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7412 *total
= COSTS_N_INSNS (20);
7416 *total
= COSTS_N_INSNS (1);
7417 if (CONST_INT_P (XEXP (x
, 0))
7418 && const_ok_for_arm (INTVAL (XEXP (x
, 0))))
7420 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7424 subcode
= GET_CODE (XEXP (x
, 1));
7425 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
7426 || subcode
== LSHIFTRT
7427 || subcode
== ROTATE
|| subcode
== ROTATERT
)
7429 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7430 *total
+= rtx_cost (XEXP (XEXP (x
, 1), 0), subcode
, 0, speed
);
7434 /* A shift as a part of RSB costs no more than RSB itself. */
7435 if (GET_CODE (XEXP (x
, 0)) == MULT
7436 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
7438 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), code
, 0, speed
);
7439 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7444 && power_of_two_operand (XEXP (XEXP (x
, 1), 1), SImode
))
7446 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7447 *total
+= rtx_cost (XEXP (XEXP (x
, 1), 0), subcode
, 0, speed
);
7451 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == RTX_COMPARE
7452 || GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == RTX_COMM_COMPARE
)
7454 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7455 if (REG_P (XEXP (XEXP (x
, 1), 0))
7456 && REGNO (XEXP (XEXP (x
, 1), 0)) != CC_REGNUM
)
7457 *total
+= COSTS_N_INSNS (1);
7465 if (code
== PLUS
&& arm_arch6
&& mode
== SImode
7466 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
7467 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
7469 *total
= COSTS_N_INSNS (1);
7470 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), GET_CODE (XEXP (x
, 0)),
7472 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7476 /* MLA: All arguments must be registers. We filter out
7477 multiplication by a power of two, so that we fall down into
7479 if (GET_CODE (XEXP (x
, 0)) == MULT
7480 && !power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
7482 /* The cost comes from the cost of the multiply. */
7486 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7488 if (TARGET_HARD_FLOAT
7490 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7492 *total
= COSTS_N_INSNS (1);
7493 if (CONST_DOUBLE_P (XEXP (x
, 1))
7494 && arm_const_double_rtx (XEXP (x
, 1)))
7496 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7503 *total
= COSTS_N_INSNS (20);
7507 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMPARE
7508 || GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMM_COMPARE
)
7510 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7511 if (REG_P (XEXP (XEXP (x
, 0), 0))
7512 && REGNO (XEXP (XEXP (x
, 0), 0)) != CC_REGNUM
)
7513 *total
+= COSTS_N_INSNS (1);
7519 case AND
: case XOR
: case IOR
:
7521 /* Normally the frame registers will be spilt into reg+const during
7522 reload, so it is a bad idea to combine them with other instructions,
7523 since then they might not be moved outside of loops. As a compromise
7524 we allow integration with ops that have a constant as their second
7526 if (REG_OR_SUBREG_REG (XEXP (x
, 0))
7527 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
7528 && !CONST_INT_P (XEXP (x
, 1)))
7529 *total
= COSTS_N_INSNS (1);
7533 *total
+= COSTS_N_INSNS (2);
7534 if (CONST_INT_P (XEXP (x
, 1))
7535 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
7537 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7544 *total
+= COSTS_N_INSNS (1);
7545 if (CONST_INT_P (XEXP (x
, 1))
7546 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
7548 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7551 subcode
= GET_CODE (XEXP (x
, 0));
7552 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
7553 || subcode
== LSHIFTRT
7554 || subcode
== ROTATE
|| subcode
== ROTATERT
)
7556 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7557 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, 0, speed
);
7562 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
7564 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7565 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, 0, speed
);
7569 if (subcode
== UMIN
|| subcode
== UMAX
7570 || subcode
== SMIN
|| subcode
== SMAX
)
7572 *total
= COSTS_N_INSNS (3);
7579 /* This should have been handled by the CPU specific routines. */
7583 if (arm_arch3m
&& mode
== SImode
7584 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7585 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
7586 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
7587 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
7588 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
7589 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
7591 *total
= rtx_cost (XEXP (XEXP (x
, 0), 0), LSHIFTRT
, 0, speed
);
7594 *total
= COSTS_N_INSNS (2); /* Plus the cost of the MULT */
7598 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7600 if (TARGET_HARD_FLOAT
7602 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7604 *total
= COSTS_N_INSNS (1);
7607 *total
= COSTS_N_INSNS (2);
7613 *total
= COSTS_N_INSNS (ARM_NUM_REGS(mode
));
7614 if (mode
== SImode
&& code
== NOT
)
7616 subcode
= GET_CODE (XEXP (x
, 0));
7617 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
7618 || subcode
== LSHIFTRT
7619 || subcode
== ROTATE
|| subcode
== ROTATERT
7621 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
)))
7623 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, 0, speed
);
7624 /* Register shifts cost an extra cycle. */
7625 if (!CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
7626 *total
+= COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x
, 0), 1),
7635 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
7637 *total
= COSTS_N_INSNS (4);
7641 operand
= XEXP (x
, 0);
7643 if (!((GET_RTX_CLASS (GET_CODE (operand
)) == RTX_COMPARE
7644 || GET_RTX_CLASS (GET_CODE (operand
)) == RTX_COMM_COMPARE
)
7645 && REG_P (XEXP (operand
, 0))
7646 && REGNO (XEXP (operand
, 0)) == CC_REGNUM
))
7647 *total
+= COSTS_N_INSNS (1);
7648 *total
+= (rtx_cost (XEXP (x
, 1), code
, 1, speed
)
7649 + rtx_cost (XEXP (x
, 2), code
, 2, speed
));
7653 if (mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
7655 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7661 if ((!REG_P (XEXP (x
, 0)) || REGNO (XEXP (x
, 0)) != CC_REGNUM
)
7662 && mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
7664 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7670 if ((!REG_P (XEXP (x
, 0)) || REGNO (XEXP (x
, 0)) != CC_REGNUM
)
7671 && mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
7673 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7693 /* SCC insns. In the case where the comparison has already been
7694 performed, then they cost 2 instructions. Otherwise they need
7695 an additional comparison before them. */
7696 *total
= COSTS_N_INSNS (2);
7697 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) == CC_REGNUM
)
7704 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) == CC_REGNUM
)
7710 *total
+= COSTS_N_INSNS (1);
7711 if (CONST_INT_P (XEXP (x
, 1))
7712 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
7714 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7718 subcode
= GET_CODE (XEXP (x
, 0));
7719 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
7720 || subcode
== LSHIFTRT
7721 || subcode
== ROTATE
|| subcode
== ROTATERT
)
7723 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7724 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, 0, speed
);
7729 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
7731 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7732 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, 0, speed
);
7742 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7743 if (!CONST_INT_P (XEXP (x
, 1))
7744 || !const_ok_for_arm (INTVAL (XEXP (x
, 1))))
7745 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
7749 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7751 if (TARGET_HARD_FLOAT
7753 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7755 *total
= COSTS_N_INSNS (1);
7758 *total
= COSTS_N_INSNS (20);
7761 *total
= COSTS_N_INSNS (1);
7763 *total
+= COSTS_N_INSNS (3);
7769 if (GET_MODE_CLASS (mode
) == MODE_INT
)
7771 rtx op
= XEXP (x
, 0);
7772 enum machine_mode opmode
= GET_MODE (op
);
7775 *total
+= COSTS_N_INSNS (1);
7777 if (opmode
!= SImode
)
7781 /* If !arm_arch4, we use one of the extendhisi2_mem
7782 or movhi_bytes patterns for HImode. For a QImode
7783 sign extension, we first zero-extend from memory
7784 and then perform a shift sequence. */
7785 if (!arm_arch4
&& (opmode
!= QImode
|| code
== SIGN_EXTEND
))
7786 *total
+= COSTS_N_INSNS (2);
7789 *total
+= COSTS_N_INSNS (1);
7791 /* We don't have the necessary insn, so we need to perform some
7793 else if (TARGET_ARM
&& code
== ZERO_EXTEND
&& mode
== QImode
)
7794 /* An and with constant 255. */
7795 *total
+= COSTS_N_INSNS (1);
7797 /* A shift sequence. Increase costs slightly to avoid
7798 combining two shifts into an extend operation. */
7799 *total
+= COSTS_N_INSNS (2) + 1;
7805 switch (GET_MODE (XEXP (x
, 0)))
7812 *total
= COSTS_N_INSNS (1);
7822 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7826 if (const_ok_for_arm (INTVAL (x
))
7827 || const_ok_for_arm (~INTVAL (x
)))
7828 *total
= COSTS_N_INSNS (1);
7830 *total
= COSTS_N_INSNS (arm_gen_constant (SET
, mode
, NULL_RTX
,
7831 INTVAL (x
), NULL_RTX
,
7838 *total
= COSTS_N_INSNS (3);
7842 *total
= COSTS_N_INSNS (1);
7846 *total
= COSTS_N_INSNS (1);
7847 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
7851 if (TARGET_HARD_FLOAT
&& vfp3_const_double_rtx (x
)
7852 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7853 *total
= COSTS_N_INSNS (1);
7855 *total
= COSTS_N_INSNS (4);
7859 /* The vec_extract patterns accept memory operands that require an
7860 address reload. Account for the cost of that reload to give the
7861 auto-inc-dec pass an incentive to try to replace them. */
7862 if (TARGET_NEON
&& MEM_P (SET_DEST (x
))
7863 && GET_CODE (SET_SRC (x
)) == VEC_SELECT
)
7865 *total
= rtx_cost (SET_DEST (x
), code
, 0, speed
);
7866 if (!neon_vector_mem_operand (SET_DEST (x
), 2, true))
7867 *total
+= COSTS_N_INSNS (1);
7870 /* Likewise for the vec_set patterns. */
7871 if (TARGET_NEON
&& GET_CODE (SET_SRC (x
)) == VEC_MERGE
7872 && GET_CODE (XEXP (SET_SRC (x
), 0)) == VEC_DUPLICATE
7873 && MEM_P (XEXP (XEXP (SET_SRC (x
), 0), 0)))
7875 rtx mem
= XEXP (XEXP (SET_SRC (x
), 0), 0);
7876 *total
= rtx_cost (mem
, code
, 0, speed
);
7877 if (!neon_vector_mem_operand (mem
, 2, true))
7878 *total
+= COSTS_N_INSNS (1);
7884 /* We cost this as high as our memory costs to allow this to
7885 be hoisted from loops. */
7886 if (XINT (x
, 1) == UNSPEC_PIC_UNIFIED
)
7888 *total
= COSTS_N_INSNS (2 + ARM_NUM_REGS (mode
));
7894 && TARGET_HARD_FLOAT
7896 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
))
7897 && neon_immediate_valid_for_move (x
, mode
, NULL
, NULL
))
7898 *total
= COSTS_N_INSNS (1);
7900 *total
= COSTS_N_INSNS (4);
7904 *total
= COSTS_N_INSNS (4);
7909 /* Estimates the size cost of thumb1 instructions.
7910 For now most of the code is copied from thumb1_rtx_costs. We need more
7911 fine grain tuning when we have more related test cases. */
7913 thumb1_size_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
7915 enum machine_mode mode
= GET_MODE (x
);
7924 return (mode
== SImode
) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
7931 return COSTS_N_INSNS (1);
7934 if (CONST_INT_P (XEXP (x
, 1)))
7936 /* Thumb1 mul instruction can't operate on const. We must Load it
7937 into a register first. */
7938 int const_size
= thumb1_size_rtx_costs (XEXP (x
, 1), CONST_INT
, SET
);
7939 return COSTS_N_INSNS (1) + const_size
;
7941 return COSTS_N_INSNS (1);
7944 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
7946 words
= ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x
))));
7947 return (COSTS_N_INSNS (words
)
7948 + 4 * ((MEM_P (SET_SRC (x
)))
7949 + MEM_P (SET_DEST (x
))));
7954 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
7955 return COSTS_N_INSNS (1);
7956 /* See split "TARGET_THUMB1 && satisfies_constraint_J". */
7957 if (INTVAL (x
) >= -255 && INTVAL (x
) <= -1)
7958 return COSTS_N_INSNS (2);
7959 /* See split "TARGET_THUMB1 && satisfies_constraint_K". */
7960 if (thumb_shiftable_const (INTVAL (x
)))
7961 return COSTS_N_INSNS (2);
7962 return COSTS_N_INSNS (3);
7964 else if ((outer
== PLUS
|| outer
== COMPARE
)
7965 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
7967 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
7968 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
7969 return COSTS_N_INSNS (1);
7970 else if (outer
== AND
)
7973 /* This duplicates the tests in the andsi3 expander. */
7974 for (i
= 9; i
<= 31; i
++)
7975 if ((((HOST_WIDE_INT
) 1) << i
) - 1 == INTVAL (x
)
7976 || (((HOST_WIDE_INT
) 1) << i
) - 1 == ~INTVAL (x
))
7977 return COSTS_N_INSNS (2);
7979 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
7980 || outer
== LSHIFTRT
)
7982 return COSTS_N_INSNS (2);
7988 return COSTS_N_INSNS (3);
8006 /* XXX another guess. */
8007 /* Memory costs quite a lot for the first word, but subsequent words
8008 load at the equivalent of a single insn each. */
8009 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
8010 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
8015 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
8020 /* XXX still guessing. */
8021 switch (GET_MODE (XEXP (x
, 0)))
8024 return (1 + (mode
== DImode
? 4 : 0)
8025 + (MEM_P (XEXP (x
, 0)) ? 10 : 0));
8028 return (4 + (mode
== DImode
? 4 : 0)
8029 + (MEM_P (XEXP (x
, 0)) ? 10 : 0));
8032 return (1 + (MEM_P (XEXP (x
, 0)) ? 10 : 0));
8043 /* RTX costs when optimizing for size. */
8045 arm_size_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
8048 enum machine_mode mode
= GET_MODE (x
);
8051 *total
= thumb1_size_rtx_costs (x
, code
, outer_code
);
8055 /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */
8059 /* A memory access costs 1 insn if the mode is small, or the address is
8060 a single register, otherwise it costs one insn per word. */
8061 if (REG_P (XEXP (x
, 0)))
8062 *total
= COSTS_N_INSNS (1);
8064 && GET_CODE (XEXP (x
, 0)) == PLUS
8065 && will_be_in_index_register (XEXP (XEXP (x
, 0), 1)))
8066 /* This will be split into two instructions.
8067 See arm.md:calculate_pic_address. */
8068 *total
= COSTS_N_INSNS (2);
8070 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
8077 /* Needs a libcall, so it costs about this. */
8078 *total
= COSTS_N_INSNS (2);
8082 if (mode
== SImode
&& REG_P (XEXP (x
, 1)))
8084 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, 0, false);
8092 if (mode
== DImode
&& CONST_INT_P (XEXP (x
, 1)))
8094 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
, 0, false);
8097 else if (mode
== SImode
)
8099 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, 0, false);
8100 /* Slightly disparage register shifts, but not by much. */
8101 if (!CONST_INT_P (XEXP (x
, 1)))
8102 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
, 1, false);
8106 /* Needs a libcall. */
8107 *total
= COSTS_N_INSNS (2);
8111 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
8112 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
8114 *total
= COSTS_N_INSNS (1);
8120 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
8121 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
8123 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
8124 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
8125 || subcode1
== ROTATE
|| subcode1
== ROTATERT
8126 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
8127 || subcode1
== ASHIFTRT
)
8129 /* It's just the cost of the two operands. */
8134 *total
= COSTS_N_INSNS (1);
8138 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
8142 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
8143 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
8145 *total
= COSTS_N_INSNS (1);
8149 /* A shift as a part of ADD costs nothing. */
8150 if (GET_CODE (XEXP (x
, 0)) == MULT
8151 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
8153 *total
= COSTS_N_INSNS (TARGET_THUMB2
? 2 : 1);
8154 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), code
, 0, false);
8155 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, false);
8160 case AND
: case XOR
: case IOR
:
8163 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
8165 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
8166 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
8167 || (code
== AND
&& subcode
== NOT
))
8169 /* It's just the cost of the two operands. */
8175 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
8179 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
8183 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
8184 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
8186 *total
= COSTS_N_INSNS (1);
8192 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
8201 if (cc_register (XEXP (x
, 0), VOIDmode
))
8204 *total
= COSTS_N_INSNS (1);
8208 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
8209 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
8210 *total
= COSTS_N_INSNS (1);
8212 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
8217 return arm_rtx_costs_1 (x
, outer_code
, total
, 0);
8220 if (const_ok_for_arm (INTVAL (x
)))
8221 /* A multiplication by a constant requires another instruction
8222 to load the constant to a register. */
8223 *total
= COSTS_N_INSNS ((outer_code
== SET
|| outer_code
== MULT
)
8225 else if (const_ok_for_arm (~INTVAL (x
)))
8226 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
8227 else if (const_ok_for_arm (-INTVAL (x
)))
8229 if (outer_code
== COMPARE
|| outer_code
== PLUS
8230 || outer_code
== MINUS
)
8233 *total
= COSTS_N_INSNS (1);
8236 *total
= COSTS_N_INSNS (2);
8242 *total
= COSTS_N_INSNS (2);
8246 *total
= COSTS_N_INSNS (4);
8251 && TARGET_HARD_FLOAT
8252 && outer_code
== SET
8253 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
))
8254 && neon_immediate_valid_for_move (x
, mode
, NULL
, NULL
))
8255 *total
= COSTS_N_INSNS (1);
8257 *total
= COSTS_N_INSNS (4);
8262 /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
8263 cost of these slightly. */
8264 *total
= COSTS_N_INSNS (1) + 1;
8271 if (mode
!= VOIDmode
)
8272 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
8274 *total
= COSTS_N_INSNS (4); /* How knows? */
8279 /* RTX costs when optimizing for size. */
8281 arm_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
8282 int *total
, bool speed
)
8285 return arm_size_rtx_costs (x
, (enum rtx_code
) code
,
8286 (enum rtx_code
) outer_code
, total
);
8288 return current_tune
->rtx_costs (x
, (enum rtx_code
) code
,
8289 (enum rtx_code
) outer_code
,
8293 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
8294 supported on any "slowmul" cores, so it can be ignored. */
8297 arm_slowmul_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
8298 int *total
, bool speed
)
8300 enum machine_mode mode
= GET_MODE (x
);
8304 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
8311 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
8314 *total
= COSTS_N_INSNS (20);
8318 if (CONST_INT_P (XEXP (x
, 1)))
8320 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
8321 & (unsigned HOST_WIDE_INT
) 0xffffffff);
8322 int cost
, const_ok
= const_ok_for_arm (i
);
8323 int j
, booth_unit_size
;
8325 /* Tune as appropriate. */
8326 cost
= const_ok
? 4 : 8;
8327 booth_unit_size
= 2;
8328 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
8330 i
>>= booth_unit_size
;
8334 *total
= COSTS_N_INSNS (cost
);
8335 *total
+= rtx_cost (XEXP (x
, 0), code
, 0, speed
);
8339 *total
= COSTS_N_INSNS (20);
8343 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);;
8348 /* RTX cost for cores with a fast multiply unit (M variants). */
8351 arm_fastmul_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
8352 int *total
, bool speed
)
8354 enum machine_mode mode
= GET_MODE (x
);
8358 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
8362 /* ??? should thumb2 use different costs? */
8366 /* There is no point basing this on the tuning, since it is always the
8367 fast variant if it exists at all. */
8369 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
8370 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8371 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
8373 *total
= COSTS_N_INSNS(2);
8380 *total
= COSTS_N_INSNS (5);
8384 if (CONST_INT_P (XEXP (x
, 1)))
8386 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
8387 & (unsigned HOST_WIDE_INT
) 0xffffffff);
8388 int cost
, const_ok
= const_ok_for_arm (i
);
8389 int j
, booth_unit_size
;
8391 /* Tune as appropriate. */
8392 cost
= const_ok
? 4 : 8;
8393 booth_unit_size
= 8;
8394 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
8396 i
>>= booth_unit_size
;
8400 *total
= COSTS_N_INSNS(cost
);
8406 *total
= COSTS_N_INSNS (4);
8410 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
8412 if (TARGET_HARD_FLOAT
8414 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
8416 *total
= COSTS_N_INSNS (1);
8421 /* Requires a lib call */
8422 *total
= COSTS_N_INSNS (20);
8426 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
8431 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
8432 so it can be ignored. */
8435 arm_xscale_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
8436 int *total
, bool speed
)
8438 enum machine_mode mode
= GET_MODE (x
);
8442 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
8449 if (GET_CODE (XEXP (x
, 0)) != MULT
)
8450 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
8452 /* A COMPARE of a MULT is slow on XScale; the muls instruction
8453 will stall until the multiplication is complete. */
8454 *total
= COSTS_N_INSNS (3);
8458 /* There is no point basing this on the tuning, since it is always the
8459 fast variant if it exists at all. */
8461 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
8462 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8463 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
8465 *total
= COSTS_N_INSNS (2);
8472 *total
= COSTS_N_INSNS (5);
8476 if (CONST_INT_P (XEXP (x
, 1)))
8478 /* If operand 1 is a constant we can more accurately
8479 calculate the cost of the multiply. The multiplier can
8480 retire 15 bits on the first cycle and a further 12 on the
8481 second. We do, of course, have to load the constant into
8482 a register first. */
8483 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
8484 /* There's a general overhead of one cycle. */
8486 unsigned HOST_WIDE_INT masked_const
;
8491 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
8493 masked_const
= i
& 0xffff8000;
8494 if (masked_const
!= 0)
8497 masked_const
= i
& 0xf8000000;
8498 if (masked_const
!= 0)
8501 *total
= COSTS_N_INSNS (cost
);
8507 *total
= COSTS_N_INSNS (3);
8511 /* Requires a lib call */
8512 *total
= COSTS_N_INSNS (20);
8516 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
8521 /* RTX costs for 9e (and later) cores. */
8524 arm_9e_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
8525 int *total
, bool speed
)
8527 enum machine_mode mode
= GET_MODE (x
);
8534 *total
= COSTS_N_INSNS (3);
8538 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
8546 /* There is no point basing this on the tuning, since it is always the
8547 fast variant if it exists at all. */
8549 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
8550 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8551 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
8553 *total
= COSTS_N_INSNS (2);
8560 *total
= COSTS_N_INSNS (5);
8566 *total
= COSTS_N_INSNS (2);
8570 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
8572 if (TARGET_HARD_FLOAT
8574 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
8576 *total
= COSTS_N_INSNS (1);
8581 *total
= COSTS_N_INSNS (20);
8585 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
8588 /* All address computations that can be done are free, but rtx cost returns
8589 the same for practically all of them. So we weight the different types
8590 of address here in the order (most pref first):
8591 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
8593 arm_arm_address_cost (rtx x
)
8595 enum rtx_code c
= GET_CODE (x
);
8597 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
8599 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
8604 if (CONST_INT_P (XEXP (x
, 1)))
8607 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
8617 arm_thumb_address_cost (rtx x
)
8619 enum rtx_code c
= GET_CODE (x
);
8624 && REG_P (XEXP (x
, 0))
8625 && CONST_INT_P (XEXP (x
, 1)))
8632 arm_address_cost (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
,
8633 addr_space_t as ATTRIBUTE_UNUSED
, bool speed ATTRIBUTE_UNUSED
)
8635 return TARGET_32BIT
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
8638 /* Adjust cost hook for XScale. */
8640 xscale_sched_adjust_cost (rtx insn
, rtx link
, rtx dep
, int * cost
)
8642 /* Some true dependencies can have a higher cost depending
8643 on precisely how certain input operands are used. */
8644 if (REG_NOTE_KIND(link
) == 0
8645 && recog_memoized (insn
) >= 0
8646 && recog_memoized (dep
) >= 0)
8648 int shift_opnum
= get_attr_shift (insn
);
8649 enum attr_type attr_type
= get_attr_type (dep
);
8651 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
8652 operand for INSN. If we have a shifted input operand and the
8653 instruction we depend on is another ALU instruction, then we may
8654 have to account for an additional stall. */
8655 if (shift_opnum
!= 0
8656 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
8658 rtx shifted_operand
;
8661 /* Get the shifted operand. */
8662 extract_insn (insn
);
8663 shifted_operand
= recog_data
.operand
[shift_opnum
];
8665 /* Iterate over all the operands in DEP. If we write an operand
8666 that overlaps with SHIFTED_OPERAND, then we have increase the
8667 cost of this dependency. */
8669 preprocess_constraints ();
8670 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8672 /* We can ignore strict inputs. */
8673 if (recog_data
.operand_type
[opno
] == OP_IN
)
8676 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
8688 /* Adjust cost hook for Cortex A9. */
8690 cortex_a9_sched_adjust_cost (rtx insn
, rtx link
, rtx dep
, int * cost
)
8692 switch (REG_NOTE_KIND (link
))
8699 case REG_DEP_OUTPUT
:
8700 if (recog_memoized (insn
) >= 0
8701 && recog_memoized (dep
) >= 0)
8703 if (GET_CODE (PATTERN (insn
)) == SET
)
8706 (GET_MODE (SET_DEST (PATTERN (insn
)))) == MODE_FLOAT
8708 (GET_MODE (SET_SRC (PATTERN (insn
)))) == MODE_FLOAT
)
8710 enum attr_type attr_type_insn
= get_attr_type (insn
);
8711 enum attr_type attr_type_dep
= get_attr_type (dep
);
8713 /* By default all dependencies of the form
8716 have an extra latency of 1 cycle because
8717 of the input and output dependency in this
8718 case. However this gets modeled as an true
8719 dependency and hence all these checks. */
8720 if (REG_P (SET_DEST (PATTERN (insn
)))
8721 && REG_P (SET_DEST (PATTERN (dep
)))
8722 && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn
)),
8723 SET_DEST (PATTERN (dep
))))
8725 /* FMACS is a special case where the dependent
8726 instruction can be issued 3 cycles before
8727 the normal latency in case of an output
8729 if ((attr_type_insn
== TYPE_FMACS
8730 || attr_type_insn
== TYPE_FMACD
)
8731 && (attr_type_dep
== TYPE_FMACS
8732 || attr_type_dep
== TYPE_FMACD
))
8734 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
8735 *cost
= insn_default_latency (dep
) - 3;
8737 *cost
= insn_default_latency (dep
);
8742 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
8743 *cost
= insn_default_latency (dep
) + 1;
8745 *cost
= insn_default_latency (dep
);
8761 /* Adjust cost hook for FA726TE. */
8763 fa726te_sched_adjust_cost (rtx insn
, rtx link
, rtx dep
, int * cost
)
8765 /* For FA726TE, true dependency on CPSR (i.e. set cond followed by predicated)
8766 have penalty of 3. */
8767 if (REG_NOTE_KIND (link
) == REG_DEP_TRUE
8768 && recog_memoized (insn
) >= 0
8769 && recog_memoized (dep
) >= 0
8770 && get_attr_conds (dep
) == CONDS_SET
)
8772 /* Use of carry (e.g. 64-bit arithmetic) in ALU: 3-cycle latency. */
8773 if (get_attr_conds (insn
) == CONDS_USE
8774 && get_attr_type (insn
) != TYPE_BRANCH
)
8780 if (GET_CODE (PATTERN (insn
)) == COND_EXEC
8781 || get_attr_conds (insn
) == CONDS_USE
)
8791 /* Implement TARGET_REGISTER_MOVE_COST.
8793 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
8794 it is typically more expensive than a single memory access. We set
8795 the cost to less than two memory accesses so that floating
8796 point to integer conversion does not go through memory. */
8799 arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
8800 reg_class_t from
, reg_class_t to
)
8804 if ((IS_VFP_CLASS (from
) && !IS_VFP_CLASS (to
))
8805 || (!IS_VFP_CLASS (from
) && IS_VFP_CLASS (to
)))
8807 else if ((from
== IWMMXT_REGS
&& to
!= IWMMXT_REGS
)
8808 || (from
!= IWMMXT_REGS
&& to
== IWMMXT_REGS
))
8810 else if (from
== IWMMXT_GR_REGS
|| to
== IWMMXT_GR_REGS
)
8817 if (from
== HI_REGS
|| to
== HI_REGS
)
8824 /* Implement TARGET_MEMORY_MOVE_COST. */
8827 arm_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
8828 bool in ATTRIBUTE_UNUSED
)
8834 if (GET_MODE_SIZE (mode
) < 4)
8837 return ((2 * GET_MODE_SIZE (mode
)) * (rclass
== LO_REGS
? 1 : 2));
8841 /* Vectorizer cost model implementation. */
8843 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8845 arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
8847 int misalign ATTRIBUTE_UNUSED
)
8851 switch (type_of_cost
)
8854 return current_tune
->vec_costs
->scalar_stmt_cost
;
8857 return current_tune
->vec_costs
->scalar_load_cost
;
8860 return current_tune
->vec_costs
->scalar_store_cost
;
8863 return current_tune
->vec_costs
->vec_stmt_cost
;
8866 return current_tune
->vec_costs
->vec_align_load_cost
;
8869 return current_tune
->vec_costs
->vec_store_cost
;
8872 return current_tune
->vec_costs
->vec_to_scalar_cost
;
8875 return current_tune
->vec_costs
->scalar_to_vec_cost
;
8877 case unaligned_load
:
8878 return current_tune
->vec_costs
->vec_unalign_load_cost
;
8880 case unaligned_store
:
8881 return current_tune
->vec_costs
->vec_unalign_store_cost
;
8883 case cond_branch_taken
:
8884 return current_tune
->vec_costs
->cond_taken_branch_cost
;
8886 case cond_branch_not_taken
:
8887 return current_tune
->vec_costs
->cond_not_taken_branch_cost
;
8890 case vec_promote_demote
:
8891 return current_tune
->vec_costs
->vec_stmt_cost
;
8894 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
8895 return elements
/ 2 + 1;
8902 /* Implement targetm.vectorize.add_stmt_cost. */
8905 arm_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
8906 struct _stmt_vec_info
*stmt_info
, int misalign
,
8907 enum vect_cost_model_location where
)
8909 unsigned *cost
= (unsigned *) data
;
8910 unsigned retval
= 0;
8912 if (flag_vect_cost_model
)
8914 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
8915 int stmt_cost
= arm_builtin_vectorization_cost (kind
, vectype
, misalign
);
8917 /* Statements in an inner loop relative to the loop being
8918 vectorized are weighted more heavily. The value here is
8919 arbitrary and could potentially be improved with analysis. */
8920 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
8921 count
*= 50; /* FIXME. */
8923 retval
= (unsigned) (count
* stmt_cost
);
8924 cost
[where
] += retval
;
8930 /* Return true if and only if this insn can dual-issue only as older. */
8932 cortexa7_older_only (rtx insn
)
8934 if (recog_memoized (insn
) < 0)
8937 if (get_attr_insn (insn
) == INSN_MOV
)
8940 switch (get_attr_type (insn
))
8943 case TYPE_LOAD_BYTE
:
8972 /* Return true if and only if this insn can dual-issue as younger. */
8974 cortexa7_younger (FILE *file
, int verbose
, rtx insn
)
8976 if (recog_memoized (insn
) < 0)
8979 fprintf (file
, ";; not cortexa7_younger %d\n", INSN_UID (insn
));
8983 if (get_attr_insn (insn
) == INSN_MOV
)
8986 switch (get_attr_type (insn
))
8988 case TYPE_SIMPLE_ALU_IMM
:
8989 case TYPE_SIMPLE_ALU_SHIFT
:
8999 /* Look for an instruction that can dual issue only as an older
9000 instruction, and move it in front of any instructions that can
9001 dual-issue as younger, while preserving the relative order of all
9002 other instructions in the ready list. This is a hueuristic to help
9003 dual-issue in later cycles, by postponing issue of more flexible
9004 instructions. This heuristic may affect dual issue opportunities
9005 in the current cycle. */
9007 cortexa7_sched_reorder (FILE *file
, int verbose
, rtx
*ready
, int *n_readyp
,
9011 int first_older_only
= -1, first_younger
= -1;
9015 ";; sched_reorder for cycle %d with %d insns in ready list\n",
9019 /* Traverse the ready list from the head (the instruction to issue
9020 first), and looking for the first instruction that can issue as
9021 younger and the first instruction that can dual-issue only as
9023 for (i
= *n_readyp
- 1; i
>= 0; i
--)
9025 rtx insn
= ready
[i
];
9026 if (cortexa7_older_only (insn
))
9028 first_older_only
= i
;
9030 fprintf (file
, ";; reorder older found %d\n", INSN_UID (insn
));
9033 else if (cortexa7_younger (file
, verbose
, insn
) && first_younger
== -1)
9037 /* Nothing to reorder because either no younger insn found or insn
9038 that can dual-issue only as older appears before any insn that
9039 can dual-issue as younger. */
9040 if (first_younger
== -1)
9043 fprintf (file
, ";; sched_reorder nothing to reorder as no younger\n");
9047 /* Nothing to reorder because no older-only insn in the ready list. */
9048 if (first_older_only
== -1)
9051 fprintf (file
, ";; sched_reorder nothing to reorder as no older_only\n");
9055 /* Move first_older_only insn before first_younger. */
9057 fprintf (file
, ";; cortexa7_sched_reorder insn %d before %d\n",
9058 INSN_UID(ready
[first_older_only
]),
9059 INSN_UID(ready
[first_younger
]));
9060 rtx first_older_only_insn
= ready
[first_older_only
];
9061 for (i
= first_older_only
; i
< first_younger
; i
++)
9063 ready
[i
] = ready
[i
+1];
9066 ready
[i
] = first_older_only_insn
;
9070 /* Implement TARGET_SCHED_REORDER. */
9072 arm_sched_reorder (FILE *file
, int verbose
, rtx
*ready
, int *n_readyp
,
9078 cortexa7_sched_reorder (file
, verbose
, ready
, n_readyp
, clock
);
9081 /* Do nothing for other cores. */
9085 return arm_issue_rate ();
9088 /* This function implements the target macro TARGET_SCHED_ADJUST_COST.
9089 It corrects the value of COST based on the relationship between
9090 INSN and DEP through the dependence LINK. It returns the new
9091 value. There is a per-core adjust_cost hook to adjust scheduler costs
9092 and the per-core hook can choose to completely override the generic
9093 adjust_cost function. Only put bits of code into arm_adjust_cost that
9094 are common across all cores. */
9096 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
9100 /* When generating Thumb-1 code, we want to place flag-setting operations
9101 close to a conditional branch which depends on them, so that we can
9102 omit the comparison. */
9104 && REG_NOTE_KIND (link
) == 0
9105 && recog_memoized (insn
) == CODE_FOR_cbranchsi4_insn
9106 && recog_memoized (dep
) >= 0
9107 && get_attr_conds (dep
) == CONDS_SET
)
9110 if (current_tune
->sched_adjust_cost
!= NULL
)
9112 if (!current_tune
->sched_adjust_cost (insn
, link
, dep
, &cost
))
9116 /* XXX Is this strictly true? */
9117 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
9118 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
9121 /* Call insns don't incur a stall, even if they follow a load. */
9122 if (REG_NOTE_KIND (link
) == 0
9126 if ((i_pat
= single_set (insn
)) != NULL
9127 && MEM_P (SET_SRC (i_pat
))
9128 && (d_pat
= single_set (dep
)) != NULL
9129 && MEM_P (SET_DEST (d_pat
)))
9131 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
9132 /* This is a load after a store, there is no conflict if the load reads
9133 from a cached area. Assume that loads from the stack, and from the
9134 constant pool are cached, and that others will miss. This is a
9137 if ((GET_CODE (src_mem
) == SYMBOL_REF
9138 && CONSTANT_POOL_ADDRESS_P (src_mem
))
9139 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
9140 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
9141 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
9149 arm_default_branch_cost (bool speed_p
, bool predictable_p ATTRIBUTE_UNUSED
)
9152 return (TARGET_THUMB2
&& !speed_p
) ? 1 : 4;
9154 return (optimize
> 0) ? 2 : 0;
9158 arm_cortex_a5_branch_cost (bool speed_p
, bool predictable_p
)
9160 return speed_p
? 0 : arm_default_branch_cost (speed_p
, predictable_p
);
9163 static bool fp_consts_inited
= false;
9165 static REAL_VALUE_TYPE value_fp0
;
9168 init_fp_table (void)
9172 r
= REAL_VALUE_ATOF ("0", DFmode
);
9174 fp_consts_inited
= true;
9177 /* Return TRUE if rtx X is a valid immediate FP constant. */
9179 arm_const_double_rtx (rtx x
)
9183 if (!fp_consts_inited
)
9186 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
9187 if (REAL_VALUE_MINUS_ZERO (r
))
9190 if (REAL_VALUES_EQUAL (r
, value_fp0
))
9196 /* VFPv3 has a fairly wide range of representable immediates, formed from
9197 "quarter-precision" floating-point values. These can be evaluated using this
9198 formula (with ^ for exponentiation):
9202 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
9203 16 <= n <= 31 and 0 <= r <= 7.
9205 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
9207 - A (most-significant) is the sign bit.
9208 - BCD are the exponent (encoded as r XOR 3).
9209 - EFGH are the mantissa (encoded as n - 16).
9212 /* Return an integer index for a VFPv3 immediate operand X suitable for the
9213 fconst[sd] instruction, or -1 if X isn't suitable. */
9215 vfp3_const_double_index (rtx x
)
9217 REAL_VALUE_TYPE r
, m
;
9219 unsigned HOST_WIDE_INT mantissa
, mant_hi
;
9220 unsigned HOST_WIDE_INT mask
;
9221 HOST_WIDE_INT m1
, m2
;
9222 int point_pos
= 2 * HOST_BITS_PER_WIDE_INT
- 1;
9224 if (!TARGET_VFP3
|| !CONST_DOUBLE_P (x
))
9227 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
9229 /* We can't represent these things, so detect them first. */
9230 if (REAL_VALUE_ISINF (r
) || REAL_VALUE_ISNAN (r
) || REAL_VALUE_MINUS_ZERO (r
))
9233 /* Extract sign, exponent and mantissa. */
9234 sign
= REAL_VALUE_NEGATIVE (r
) ? 1 : 0;
9235 r
= real_value_abs (&r
);
9236 exponent
= REAL_EXP (&r
);
9237 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
9238 highest (sign) bit, with a fixed binary point at bit point_pos.
9239 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
9240 bits for the mantissa, this may fail (low bits would be lost). */
9241 real_ldexp (&m
, &r
, point_pos
- exponent
);
9242 REAL_VALUE_TO_INT (&m1
, &m2
, m
);
9246 /* If there are bits set in the low part of the mantissa, we can't
9247 represent this value. */
9251 /* Now make it so that mantissa contains the most-significant bits, and move
9252 the point_pos to indicate that the least-significant bits have been
9254 point_pos
-= HOST_BITS_PER_WIDE_INT
;
9257 /* We can permit four significant bits of mantissa only, plus a high bit
9258 which is always 1. */
9259 mask
= ((unsigned HOST_WIDE_INT
)1 << (point_pos
- 5)) - 1;
9260 if ((mantissa
& mask
) != 0)
9263 /* Now we know the mantissa is in range, chop off the unneeded bits. */
9264 mantissa
>>= point_pos
- 5;
9266 /* The mantissa may be zero. Disallow that case. (It's possible to load the
9267 floating-point immediate zero with Neon using an integer-zero load, but
9268 that case is handled elsewhere.) */
9272 gcc_assert (mantissa
>= 16 && mantissa
<= 31);
9274 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
9275 normalized significands are in the range [1, 2). (Our mantissa is shifted
9276 left 4 places at this point relative to normalized IEEE754 values). GCC
9277 internally uses [0.5, 1) (see real.c), so the exponent returned from
9278 REAL_EXP must be altered. */
9279 exponent
= 5 - exponent
;
9281 if (exponent
< 0 || exponent
> 7)
9284 /* Sign, mantissa and exponent are now in the correct form to plug into the
9285 formula described in the comment above. */
9286 return (sign
<< 7) | ((exponent
^ 3) << 4) | (mantissa
- 16);
9289 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
9291 vfp3_const_double_rtx (rtx x
)
9296 return vfp3_const_double_index (x
) != -1;
9299 /* Recognize immediates which can be used in various Neon instructions. Legal
9300 immediates are described by the following table (for VMVN variants, the
9301 bitwise inverse of the constant shown is recognized. In either case, VMOV
9302 is output and the correct instruction to use for a given constant is chosen
9303 by the assembler). The constant shown is replicated across all elements of
9304 the destination vector.
9306 insn elems variant constant (binary)
9307 ---- ----- ------- -----------------
9308 vmov i32 0 00000000 00000000 00000000 abcdefgh
9309 vmov i32 1 00000000 00000000 abcdefgh 00000000
9310 vmov i32 2 00000000 abcdefgh 00000000 00000000
9311 vmov i32 3 abcdefgh 00000000 00000000 00000000
9312 vmov i16 4 00000000 abcdefgh
9313 vmov i16 5 abcdefgh 00000000
9314 vmvn i32 6 00000000 00000000 00000000 abcdefgh
9315 vmvn i32 7 00000000 00000000 abcdefgh 00000000
9316 vmvn i32 8 00000000 abcdefgh 00000000 00000000
9317 vmvn i32 9 abcdefgh 00000000 00000000 00000000
9318 vmvn i16 10 00000000 abcdefgh
9319 vmvn i16 11 abcdefgh 00000000
9320 vmov i32 12 00000000 00000000 abcdefgh 11111111
9321 vmvn i32 13 00000000 00000000 abcdefgh 11111111
9322 vmov i32 14 00000000 abcdefgh 11111111 11111111
9323 vmvn i32 15 00000000 abcdefgh 11111111 11111111
9325 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
9326 eeeeeeee ffffffff gggggggg hhhhhhhh
9327 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
9328 vmov f32 19 00000000 00000000 00000000 00000000
9330 For case 18, B = !b. Representable values are exactly those accepted by
9331 vfp3_const_double_index, but are output as floating-point numbers rather
9334 For case 19, we will change it to vmov.i32 when assembling.
9336 Variants 0-5 (inclusive) may also be used as immediates for the second
9337 operand of VORR/VBIC instructions.
9339 The INVERSE argument causes the bitwise inverse of the given operand to be
9340 recognized instead (used for recognizing legal immediates for the VAND/VORN
9341 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
9342 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
9343 output, rather than the real insns vbic/vorr).
9345 INVERSE makes no difference to the recognition of float vectors.
9347 The return value is the variant of immediate as shown in the above table, or
9348 -1 if the given value doesn't match any of the listed patterns.
9351 neon_valid_immediate (rtx op
, enum machine_mode mode
, int inverse
,
9352 rtx
*modconst
, int *elementwidth
)
9354 #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
9356 for (i = 0; i < idx; i += (STRIDE)) \
9361 immtype = (CLASS); \
9362 elsize = (ELSIZE); \
9366 unsigned int i
, elsize
= 0, idx
= 0, n_elts
;
9367 unsigned int innersize
;
9368 unsigned char bytes
[16];
9369 int immtype
= -1, matches
;
9370 unsigned int invmask
= inverse
? 0xff : 0;
9371 bool vector
= GET_CODE (op
) == CONST_VECTOR
;
9375 n_elts
= CONST_VECTOR_NUNITS (op
);
9376 innersize
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
9381 if (mode
== VOIDmode
)
9383 innersize
= GET_MODE_SIZE (mode
);
9386 /* Vectors of float constants. */
9387 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
9389 rtx el0
= CONST_VECTOR_ELT (op
, 0);
9392 if (!vfp3_const_double_rtx (el0
) && el0
!= CONST0_RTX (GET_MODE (el0
)))
9395 REAL_VALUE_FROM_CONST_DOUBLE (r0
, el0
);
9397 for (i
= 1; i
< n_elts
; i
++)
9399 rtx elt
= CONST_VECTOR_ELT (op
, i
);
9402 REAL_VALUE_FROM_CONST_DOUBLE (re
, elt
);
9404 if (!REAL_VALUES_EQUAL (r0
, re
))
9409 *modconst
= CONST_VECTOR_ELT (op
, 0);
9414 if (el0
== CONST0_RTX (GET_MODE (el0
)))
9420 /* Splat vector constant out into a byte vector. */
9421 for (i
= 0; i
< n_elts
; i
++)
9423 rtx el
= vector
? CONST_VECTOR_ELT (op
, i
) : op
;
9424 unsigned HOST_WIDE_INT elpart
;
9425 unsigned int part
, parts
;
9427 if (CONST_INT_P (el
))
9429 elpart
= INTVAL (el
);
9432 else if (CONST_DOUBLE_P (el
))
9434 elpart
= CONST_DOUBLE_LOW (el
);
9440 for (part
= 0; part
< parts
; part
++)
9443 for (byte
= 0; byte
< innersize
; byte
++)
9445 bytes
[idx
++] = (elpart
& 0xff) ^ invmask
;
9446 elpart
>>= BITS_PER_UNIT
;
9448 if (CONST_DOUBLE_P (el
))
9449 elpart
= CONST_DOUBLE_HIGH (el
);
9454 gcc_assert (idx
== GET_MODE_SIZE (mode
));
9458 CHECK (4, 32, 0, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0
9459 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
9461 CHECK (4, 32, 1, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
9462 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
9464 CHECK (4, 32, 2, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
9465 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
9467 CHECK (4, 32, 3, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
9468 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == bytes
[3]);
9470 CHECK (2, 16, 4, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0);
9472 CHECK (2, 16, 5, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]);
9474 CHECK (4, 32, 6, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff
9475 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
9477 CHECK (4, 32, 7, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
9478 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
9480 CHECK (4, 32, 8, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
9481 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
9483 CHECK (4, 32, 9, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
9484 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == bytes
[3]);
9486 CHECK (2, 16, 10, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff);
9488 CHECK (2, 16, 11, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]);
9490 CHECK (4, 32, 12, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
9491 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
9493 CHECK (4, 32, 13, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
9494 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
9496 CHECK (4, 32, 14, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
9497 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
9499 CHECK (4, 32, 15, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
9500 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
9502 CHECK (1, 8, 16, bytes
[i
] == bytes
[0]);
9504 CHECK (1, 64, 17, (bytes
[i
] == 0 || bytes
[i
] == 0xff)
9505 && bytes
[i
] == bytes
[(i
+ 8) % idx
]);
9513 *elementwidth
= elsize
;
9517 unsigned HOST_WIDE_INT imm
= 0;
9519 /* Un-invert bytes of recognized vector, if necessary. */
9521 for (i
= 0; i
< idx
; i
++)
9522 bytes
[i
] ^= invmask
;
9526 /* FIXME: Broken on 32-bit H_W_I hosts. */
9527 gcc_assert (sizeof (HOST_WIDE_INT
) == 8);
9529 for (i
= 0; i
< 8; i
++)
9530 imm
|= (unsigned HOST_WIDE_INT
) (bytes
[i
] ? 0xff : 0)
9531 << (i
* BITS_PER_UNIT
);
9533 *modconst
= GEN_INT (imm
);
9537 unsigned HOST_WIDE_INT imm
= 0;
9539 for (i
= 0; i
< elsize
/ BITS_PER_UNIT
; i
++)
9540 imm
|= (unsigned HOST_WIDE_INT
) bytes
[i
] << (i
* BITS_PER_UNIT
);
9542 *modconst
= GEN_INT (imm
);
9550 /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly,
9551 VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for
9552 float elements), and a modified constant (whatever should be output for a
9553 VMOV) in *MODCONST. */
9556 neon_immediate_valid_for_move (rtx op
, enum machine_mode mode
,
9557 rtx
*modconst
, int *elementwidth
)
9561 int retval
= neon_valid_immediate (op
, mode
, 0, &tmpconst
, &tmpwidth
);
9567 *modconst
= tmpconst
;
9570 *elementwidth
= tmpwidth
;
9575 /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
9576 the immediate is valid, write a constant suitable for using as an operand
9577 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
9578 *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */
9581 neon_immediate_valid_for_logic (rtx op
, enum machine_mode mode
, int inverse
,
9582 rtx
*modconst
, int *elementwidth
)
9586 int retval
= neon_valid_immediate (op
, mode
, inverse
, &tmpconst
, &tmpwidth
);
9588 if (retval
< 0 || retval
> 5)
9592 *modconst
= tmpconst
;
9595 *elementwidth
= tmpwidth
;
9600 /* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction. If
9601 the immediate is valid, write a constant suitable for using as an operand
9602 to VSHR/VSHL to *MODCONST and the corresponding element width to
9603 *ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
9604 because they have different limitations. */
9607 neon_immediate_valid_for_shift (rtx op
, enum machine_mode mode
,
9608 rtx
*modconst
, int *elementwidth
,
9611 unsigned int innersize
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
9612 unsigned int n_elts
= CONST_VECTOR_NUNITS (op
), i
;
9613 unsigned HOST_WIDE_INT last_elt
= 0;
9614 unsigned HOST_WIDE_INT maxshift
;
9616 /* Split vector constant out into a byte vector. */
9617 for (i
= 0; i
< n_elts
; i
++)
9619 rtx el
= CONST_VECTOR_ELT (op
, i
);
9620 unsigned HOST_WIDE_INT elpart
;
9622 if (CONST_INT_P (el
))
9623 elpart
= INTVAL (el
);
9624 else if (CONST_DOUBLE_P (el
))
9629 if (i
!= 0 && elpart
!= last_elt
)
9635 /* Shift less than element size. */
9636 maxshift
= innersize
* 8;
9640 /* Left shift immediate value can be from 0 to <size>-1. */
9641 if (last_elt
>= maxshift
)
9646 /* Right shift immediate value can be from 1 to <size>. */
9647 if (last_elt
== 0 || last_elt
> maxshift
)
9652 *elementwidth
= innersize
* 8;
9655 *modconst
= CONST_VECTOR_ELT (op
, 0);
9660 /* Return a string suitable for output of Neon immediate logic operation
9664 neon_output_logic_immediate (const char *mnem
, rtx
*op2
, enum machine_mode mode
,
9665 int inverse
, int quad
)
9667 int width
, is_valid
;
9668 static char templ
[40];
9670 is_valid
= neon_immediate_valid_for_logic (*op2
, mode
, inverse
, op2
, &width
);
9672 gcc_assert (is_valid
!= 0);
9675 sprintf (templ
, "%s.i%d\t%%q0, %%2", mnem
, width
);
9677 sprintf (templ
, "%s.i%d\t%%P0, %%2", mnem
, width
);
9682 /* Return a string suitable for output of Neon immediate shift operation
9683 (VSHR or VSHL) MNEM. */
9686 neon_output_shift_immediate (const char *mnem
, char sign
, rtx
*op2
,
9687 enum machine_mode mode
, int quad
,
9690 int width
, is_valid
;
9691 static char templ
[40];
9693 is_valid
= neon_immediate_valid_for_shift (*op2
, mode
, op2
, &width
, isleftshift
);
9694 gcc_assert (is_valid
!= 0);
9697 sprintf (templ
, "%s.%c%d\t%%q0, %%q1, %%2", mnem
, sign
, width
);
9699 sprintf (templ
, "%s.%c%d\t%%P0, %%P1, %%2", mnem
, sign
, width
);
9704 /* Output a sequence of pairwise operations to implement a reduction.
9705 NOTE: We do "too much work" here, because pairwise operations work on two
9706 registers-worth of operands in one go. Unfortunately we can't exploit those
9707 extra calculations to do the full operation in fewer steps, I don't think.
9708 Although all vector elements of the result but the first are ignored, we
9709 actually calculate the same result in each of the elements. An alternative
9710 such as initially loading a vector with zero to use as each of the second
9711 operands would use up an additional register and take an extra instruction,
9712 for no particular gain. */
9715 neon_pairwise_reduce (rtx op0
, rtx op1
, enum machine_mode mode
,
9716 rtx (*reduc
) (rtx
, rtx
, rtx
))
9718 enum machine_mode inner
= GET_MODE_INNER (mode
);
9719 unsigned int i
, parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (inner
);
9722 for (i
= parts
/ 2; i
>= 1; i
/= 2)
9724 rtx dest
= (i
== 1) ? op0
: gen_reg_rtx (mode
);
9725 emit_insn (reduc (dest
, tmpsum
, tmpsum
));
9730 /* If VALS is a vector constant that can be loaded into a register
9731 using VDUP, generate instructions to do so and return an RTX to
9732 assign to the register. Otherwise return NULL_RTX. */
9735 neon_vdup_constant (rtx vals
)
9737 enum machine_mode mode
= GET_MODE (vals
);
9738 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
9739 int n_elts
= GET_MODE_NUNITS (mode
);
9740 bool all_same
= true;
9744 if (GET_CODE (vals
) != CONST_VECTOR
|| GET_MODE_SIZE (inner_mode
) > 4)
9747 for (i
= 0; i
< n_elts
; ++i
)
9749 x
= XVECEXP (vals
, 0, i
);
9750 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
9755 /* The elements are not all the same. We could handle repeating
9756 patterns of a mode larger than INNER_MODE here (e.g. int8x8_t
9757 {0, C, 0, C, 0, C, 0, C} which can be loaded using
9761 /* We can load this constant by using VDUP and a constant in a
9762 single ARM register. This will be cheaper than a vector
9765 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, 0));
9766 return gen_rtx_VEC_DUPLICATE (mode
, x
);
9769 /* Generate code to load VALS, which is a PARALLEL containing only
9770 constants (for vec_init) or CONST_VECTOR, efficiently into a
9771 register. Returns an RTX to copy into the register, or NULL_RTX
9772 for a PARALLEL that can not be converted into a CONST_VECTOR. */
9775 neon_make_constant (rtx vals
)
9777 enum machine_mode mode
= GET_MODE (vals
);
9779 rtx const_vec
= NULL_RTX
;
9780 int n_elts
= GET_MODE_NUNITS (mode
);
9784 if (GET_CODE (vals
) == CONST_VECTOR
)
9786 else if (GET_CODE (vals
) == PARALLEL
)
9788 /* A CONST_VECTOR must contain only CONST_INTs and
9789 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
9790 Only store valid constants in a CONST_VECTOR. */
9791 for (i
= 0; i
< n_elts
; ++i
)
9793 rtx x
= XVECEXP (vals
, 0, i
);
9794 if (CONST_INT_P (x
) || CONST_DOUBLE_P (x
))
9797 if (n_const
== n_elts
)
9798 const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
9803 if (const_vec
!= NULL
9804 && neon_immediate_valid_for_move (const_vec
, mode
, NULL
, NULL
))
9805 /* Load using VMOV. On Cortex-A8 this takes one cycle. */
9807 else if ((target
= neon_vdup_constant (vals
)) != NULL_RTX
)
9808 /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON
9809 pipeline cycle; creating the constant takes one or two ARM
9812 else if (const_vec
!= NULL_RTX
)
9813 /* Load from constant pool. On Cortex-A8 this takes two cycles
9814 (for either double or quad vectors). We can not take advantage
9815 of single-cycle VLD1 because we need a PC-relative addressing
9819 /* A PARALLEL containing something not valid inside CONST_VECTOR.
9820 We can not construct an initializer. */
9824 /* Initialize vector TARGET to VALS. */
9827 neon_expand_vector_init (rtx target
, rtx vals
)
9829 enum machine_mode mode
= GET_MODE (target
);
9830 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
9831 int n_elts
= GET_MODE_NUNITS (mode
);
9832 int n_var
= 0, one_var
= -1;
9833 bool all_same
= true;
9837 for (i
= 0; i
< n_elts
; ++i
)
9839 x
= XVECEXP (vals
, 0, i
);
9840 if (!CONSTANT_P (x
))
9841 ++n_var
, one_var
= i
;
9843 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
9849 rtx constant
= neon_make_constant (vals
);
9850 if (constant
!= NULL_RTX
)
9852 emit_move_insn (target
, constant
);
9857 /* Splat a single non-constant element if we can. */
9858 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
9860 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, 0));
9861 emit_insn (gen_rtx_SET (VOIDmode
, target
,
9862 gen_rtx_VEC_DUPLICATE (mode
, x
)));
9866 /* One field is non-constant. Load constant then overwrite varying
9867 field. This is more efficient than using the stack. */
9870 rtx copy
= copy_rtx (vals
);
9871 rtx index
= GEN_INT (one_var
);
9873 /* Load constant part of vector, substitute neighboring value for
9875 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
9876 neon_expand_vector_init (target
, copy
);
9878 /* Insert variable. */
9879 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, one_var
));
9883 emit_insn (gen_neon_vset_lanev8qi (target
, x
, target
, index
));
9886 emit_insn (gen_neon_vset_lanev16qi (target
, x
, target
, index
));
9889 emit_insn (gen_neon_vset_lanev4hi (target
, x
, target
, index
));
9892 emit_insn (gen_neon_vset_lanev8hi (target
, x
, target
, index
));
9895 emit_insn (gen_neon_vset_lanev2si (target
, x
, target
, index
));
9898 emit_insn (gen_neon_vset_lanev4si (target
, x
, target
, index
));
9901 emit_insn (gen_neon_vset_lanev2sf (target
, x
, target
, index
));
9904 emit_insn (gen_neon_vset_lanev4sf (target
, x
, target
, index
));
9907 emit_insn (gen_neon_vset_lanev2di (target
, x
, target
, index
));
9915 /* Construct the vector in memory one field at a time
9916 and load the whole vector. */
9917 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
9918 for (i
= 0; i
< n_elts
; i
++)
9919 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
9920 i
* GET_MODE_SIZE (inner_mode
)),
9921 XVECEXP (vals
, 0, i
));
9922 emit_move_insn (target
, mem
);
9925 /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise
9926 ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so
9927 reported source locations are bogus. */
9930 bounds_check (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
,
9935 gcc_assert (CONST_INT_P (operand
));
9937 lane
= INTVAL (operand
);
9939 if (lane
< low
|| lane
>= high
)
9943 /* Bounds-check lanes. */
9946 neon_lane_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
)
9948 bounds_check (operand
, low
, high
, "lane out of range");
9951 /* Bounds-check constants. */
9954 neon_const_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
)
9956 bounds_check (operand
, low
, high
, "constant out of range");
9960 neon_element_bits (enum machine_mode mode
)
9963 return GET_MODE_BITSIZE (mode
);
9965 return GET_MODE_BITSIZE (GET_MODE_INNER (mode
));
9969 /* Predicates for `match_operand' and `match_operator'. */
9971 /* Return TRUE if OP is a valid coprocessor memory address pattern.
9972 WB is true if full writeback address modes are allowed and is false
9973 if limited writeback address modes (POST_INC and PRE_DEC) are
9977 arm_coproc_mem_operand (rtx op
, bool wb
)
9981 /* Reject eliminable registers. */
9982 if (! (reload_in_progress
|| reload_completed
)
9983 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
9984 || reg_mentioned_p (arg_pointer_rtx
, op
)
9985 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
9986 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
9987 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
9988 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
9991 /* Constants are converted into offsets from labels. */
9997 if (reload_completed
9998 && (GET_CODE (ind
) == LABEL_REF
9999 || (GET_CODE (ind
) == CONST
10000 && GET_CODE (XEXP (ind
, 0)) == PLUS
10001 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
10002 && CONST_INT_P (XEXP (XEXP (ind
, 0), 1)))))
10005 /* Match: (mem (reg)). */
10007 return arm_address_register_rtx_p (ind
, 0);
10009 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
10010 acceptable in any case (subject to verification by
10011 arm_address_register_rtx_p). We need WB to be true to accept
10012 PRE_INC and POST_DEC. */
10013 if (GET_CODE (ind
) == POST_INC
10014 || GET_CODE (ind
) == PRE_DEC
10016 && (GET_CODE (ind
) == PRE_INC
10017 || GET_CODE (ind
) == POST_DEC
)))
10018 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
10021 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
10022 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
10023 && GET_CODE (XEXP (ind
, 1)) == PLUS
10024 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
10025 ind
= XEXP (ind
, 1);
10030 if (GET_CODE (ind
) == PLUS
10031 && REG_P (XEXP (ind
, 0))
10032 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
10033 && CONST_INT_P (XEXP (ind
, 1))
10034 && INTVAL (XEXP (ind
, 1)) > -1024
10035 && INTVAL (XEXP (ind
, 1)) < 1024
10036 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
10042 /* Return TRUE if OP is a memory operand which we can load or store a vector
10043 to/from. TYPE is one of the following values:
10044 0 - Vector load/stor (vldr)
10045 1 - Core registers (ldm)
10046 2 - Element/structure loads (vld1)
10049 neon_vector_mem_operand (rtx op
, int type
, bool strict
)
10053 /* Reject eliminable registers. */
10054 if (! (reload_in_progress
|| reload_completed
)
10055 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
10056 || reg_mentioned_p (arg_pointer_rtx
, op
)
10057 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
10058 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
10059 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
10060 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
10063 /* Constants are converted into offsets from labels. */
10067 ind
= XEXP (op
, 0);
10069 if (reload_completed
10070 && (GET_CODE (ind
) == LABEL_REF
10071 || (GET_CODE (ind
) == CONST
10072 && GET_CODE (XEXP (ind
, 0)) == PLUS
10073 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
10074 && CONST_INT_P (XEXP (XEXP (ind
, 0), 1)))))
10077 /* Match: (mem (reg)). */
10079 return arm_address_register_rtx_p (ind
, 0);
10081 /* Allow post-increment with Neon registers. */
10082 if ((type
!= 1 && GET_CODE (ind
) == POST_INC
)
10083 || (type
== 0 && GET_CODE (ind
) == PRE_DEC
))
10084 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
10086 /* FIXME: vld1 allows register post-modify. */
10092 && GET_CODE (ind
) == PLUS
10093 && REG_P (XEXP (ind
, 0))
10094 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
10095 && CONST_INT_P (XEXP (ind
, 1))
10096 && INTVAL (XEXP (ind
, 1)) > -1024
10097 /* For quad modes, we restrict the constant offset to be slightly less
10098 than what the instruction format permits. We have no such constraint
10099 on double mode offsets. (This must match arm_legitimate_index_p.) */
10100 && (INTVAL (XEXP (ind
, 1))
10101 < (VALID_NEON_QREG_MODE (GET_MODE (op
))? 1016 : 1024))
10102 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
10108 /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
10111 neon_struct_mem_operand (rtx op
)
10115 /* Reject eliminable registers. */
10116 if (! (reload_in_progress
|| reload_completed
)
10117 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
10118 || reg_mentioned_p (arg_pointer_rtx
, op
)
10119 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
10120 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
10121 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
10122 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
10125 /* Constants are converted into offsets from labels. */
10129 ind
= XEXP (op
, 0);
10131 if (reload_completed
10132 && (GET_CODE (ind
) == LABEL_REF
10133 || (GET_CODE (ind
) == CONST
10134 && GET_CODE (XEXP (ind
, 0)) == PLUS
10135 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
10136 && CONST_INT_P (XEXP (XEXP (ind
, 0), 1)))))
10139 /* Match: (mem (reg)). */
10141 return arm_address_register_rtx_p (ind
, 0);
10143 /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
10144 if (GET_CODE (ind
) == POST_INC
10145 || GET_CODE (ind
) == PRE_DEC
)
10146 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
10151 /* Return true if X is a register that will be eliminated later on. */
10153 arm_eliminable_register (rtx x
)
10155 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
10156 || REGNO (x
) == ARG_POINTER_REGNUM
10157 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
10158 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
10161 /* Return GENERAL_REGS if a scratch register required to reload x to/from
10162 coprocessor registers. Otherwise return NO_REGS. */
10165 coproc_secondary_reload_class (enum machine_mode mode
, rtx x
, bool wb
)
10167 if (mode
== HFmode
)
10169 if (!TARGET_NEON_FP16
)
10170 return GENERAL_REGS
;
10171 if (s_register_operand (x
, mode
) || neon_vector_mem_operand (x
, 2, true))
10173 return GENERAL_REGS
;
10176 /* The neon move patterns handle all legitimate vector and struct
10179 && (MEM_P (x
) || GET_CODE (x
) == CONST_VECTOR
)
10180 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
10181 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
10182 || VALID_NEON_STRUCT_MODE (mode
)))
10185 if (arm_coproc_mem_operand (x
, wb
) || s_register_operand (x
, mode
))
10188 return GENERAL_REGS
;
10191 /* Values which must be returned in the most-significant end of the return
10195 arm_return_in_msb (const_tree valtype
)
10197 return (TARGET_AAPCS_BASED
10198 && BYTES_BIG_ENDIAN
10199 && (AGGREGATE_TYPE_P (valtype
)
10200 || TREE_CODE (valtype
) == COMPLEX_TYPE
10201 || FIXED_POINT_TYPE_P (valtype
)));
10204 /* Return TRUE if X references a SYMBOL_REF. */
10206 symbol_mentioned_p (rtx x
)
10211 if (GET_CODE (x
) == SYMBOL_REF
)
10214 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
10215 are constant offsets, not symbols. */
10216 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
10219 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10221 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
10227 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10228 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
10231 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
10238 /* Return TRUE if X references a LABEL_REF. */
10240 label_mentioned_p (rtx x
)
10245 if (GET_CODE (x
) == LABEL_REF
)
10248 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
10249 instruction, but they are constant offsets, not symbols. */
10250 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
10253 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10254 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
10260 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10261 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
10264 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
10272 tls_mentioned_p (rtx x
)
10274 switch (GET_CODE (x
))
10277 return tls_mentioned_p (XEXP (x
, 0));
10280 if (XINT (x
, 1) == UNSPEC_TLS
)
10288 /* Must not copy any rtx that uses a pc-relative address. */
10291 arm_note_pic_base (rtx
*x
, void *date ATTRIBUTE_UNUSED
)
10293 if (GET_CODE (*x
) == UNSPEC
10294 && (XINT (*x
, 1) == UNSPEC_PIC_BASE
10295 || XINT (*x
, 1) == UNSPEC_PIC_UNIFIED
))
10301 arm_cannot_copy_insn_p (rtx insn
)
10303 /* The tls call insn cannot be copied, as it is paired with a data
10305 if (recog_memoized (insn
) == CODE_FOR_tlscall
)
10308 return for_each_rtx (&PATTERN (insn
), arm_note_pic_base
, NULL
);
10312 minmax_code (rtx x
)
10314 enum rtx_code code
= GET_CODE (x
);
10327 gcc_unreachable ();
10331 /* Match pair of min/max operators that can be implemented via usat/ssat. */
10334 arm_sat_operator_match (rtx lo_bound
, rtx hi_bound
,
10335 int *mask
, bool *signed_sat
)
10337 /* The high bound must be a power of two minus one. */
10338 int log
= exact_log2 (INTVAL (hi_bound
) + 1);
10342 /* The low bound is either zero (for usat) or one less than the
10343 negation of the high bound (for ssat). */
10344 if (INTVAL (lo_bound
) == 0)
10349 *signed_sat
= false;
10354 if (INTVAL (lo_bound
) == -INTVAL (hi_bound
) - 1)
10359 *signed_sat
= true;
10367 /* Return 1 if memory locations are adjacent. */
10369 adjacent_mem_locations (rtx a
, rtx b
)
10371 /* We don't guarantee to preserve the order of these memory refs. */
10372 if (volatile_refs_p (a
) || volatile_refs_p (b
))
10375 if ((REG_P (XEXP (a
, 0))
10376 || (GET_CODE (XEXP (a
, 0)) == PLUS
10377 && CONST_INT_P (XEXP (XEXP (a
, 0), 1))))
10378 && (REG_P (XEXP (b
, 0))
10379 || (GET_CODE (XEXP (b
, 0)) == PLUS
10380 && CONST_INT_P (XEXP (XEXP (b
, 0), 1)))))
10382 HOST_WIDE_INT val0
= 0, val1
= 0;
10386 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
10388 reg0
= XEXP (XEXP (a
, 0), 0);
10389 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
10392 reg0
= XEXP (a
, 0);
10394 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
10396 reg1
= XEXP (XEXP (b
, 0), 0);
10397 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
10400 reg1
= XEXP (b
, 0);
10402 /* Don't accept any offset that will require multiple
10403 instructions to handle, since this would cause the
10404 arith_adjacentmem pattern to output an overlong sequence. */
10405 if (!const_ok_for_op (val0
, PLUS
) || !const_ok_for_op (val1
, PLUS
))
10408 /* Don't allow an eliminable register: register elimination can make
10409 the offset too large. */
10410 if (arm_eliminable_register (reg0
))
10413 val_diff
= val1
- val0
;
10417 /* If the target has load delay slots, then there's no benefit
10418 to using an ldm instruction unless the offset is zero and
10419 we are optimizing for size. */
10420 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
10421 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
10422 && (val_diff
== 4 || val_diff
== -4));
10425 return ((REGNO (reg0
) == REGNO (reg1
))
10426 && (val_diff
== 4 || val_diff
== -4));
10432 /* Return true if OP is a valid load or store multiple operation. LOAD is true
10433 for load operations, false for store operations. CONSECUTIVE is true
10434 if the register numbers in the operation must be consecutive in the register
10435 bank. RETURN_PC is true if value is to be loaded in PC.
10436 The pattern we are trying to match for load is:
10437 [(SET (R_d0) (MEM (PLUS (addr) (offset))))
10438 (SET (R_d1) (MEM (PLUS (addr) (offset + <reg_increment>))))
10441 (SET (R_dn) (MEM (PLUS (addr) (offset + n * <reg_increment>))))
10444 1. If offset is 0, first insn should be (SET (R_d0) (MEM (src_addr))).
10445 2. REGNO (R_d0) < REGNO (R_d1) < ... < REGNO (R_dn).
10446 3. If consecutive is TRUE, then for kth register being loaded,
10447 REGNO (R_dk) = REGNO (R_d0) + k.
10448 The pattern for store is similar. */
10450 ldm_stm_operation_p (rtx op
, bool load
, enum machine_mode mode
,
10451 bool consecutive
, bool return_pc
)
10453 HOST_WIDE_INT count
= XVECLEN (op
, 0);
10454 rtx reg
, mem
, addr
;
10456 unsigned first_regno
;
10457 HOST_WIDE_INT i
= 1, base
= 0, offset
= 0;
10459 bool addr_reg_in_reglist
= false;
10460 bool update
= false;
10465 /* If not in SImode, then registers must be consecutive
10466 (e.g., VLDM instructions for DFmode). */
10467 gcc_assert ((mode
== SImode
) || consecutive
);
10468 /* Setting return_pc for stores is illegal. */
10469 gcc_assert (!return_pc
|| load
);
10471 /* Set up the increments and the regs per val based on the mode. */
10472 reg_increment
= GET_MODE_SIZE (mode
);
10473 regs_per_val
= reg_increment
/ 4;
10474 offset_adj
= return_pc
? 1 : 0;
10477 || GET_CODE (XVECEXP (op
, 0, offset_adj
)) != SET
10478 || (load
&& !REG_P (SET_DEST (XVECEXP (op
, 0, offset_adj
)))))
10481 /* Check if this is a write-back. */
10482 elt
= XVECEXP (op
, 0, offset_adj
);
10483 if (GET_CODE (SET_SRC (elt
)) == PLUS
)
10489 /* The offset adjustment must be the number of registers being
10490 popped times the size of a single register. */
10491 if (!REG_P (SET_DEST (elt
))
10492 || !REG_P (XEXP (SET_SRC (elt
), 0))
10493 || (REGNO (SET_DEST (elt
)) != REGNO (XEXP (SET_SRC (elt
), 0)))
10494 || !CONST_INT_P (XEXP (SET_SRC (elt
), 1))
10495 || INTVAL (XEXP (SET_SRC (elt
), 1)) !=
10496 ((count
- 1 - offset_adj
) * reg_increment
))
10500 i
= i
+ offset_adj
;
10501 base
= base
+ offset_adj
;
10502 /* Perform a quick check so we don't blow up below. If only one reg is loaded,
10503 success depends on the type: VLDM can do just one reg,
10504 LDM must do at least two. */
10505 if ((count
<= i
) && (mode
== SImode
))
10508 elt
= XVECEXP (op
, 0, i
- 1);
10509 if (GET_CODE (elt
) != SET
)
10514 reg
= SET_DEST (elt
);
10515 mem
= SET_SRC (elt
);
10519 reg
= SET_SRC (elt
);
10520 mem
= SET_DEST (elt
);
10523 if (!REG_P (reg
) || !MEM_P (mem
))
10526 regno
= REGNO (reg
);
10527 first_regno
= regno
;
10528 addr
= XEXP (mem
, 0);
10529 if (GET_CODE (addr
) == PLUS
)
10531 if (!CONST_INT_P (XEXP (addr
, 1)))
10534 offset
= INTVAL (XEXP (addr
, 1));
10535 addr
= XEXP (addr
, 0);
10541 /* Don't allow SP to be loaded unless it is also the base register. It
10542 guarantees that SP is reset correctly when an LDM instruction
10543 is interrupted. Otherwise, we might end up with a corrupt stack. */
10544 if (load
&& (REGNO (reg
) == SP_REGNUM
) && (REGNO (addr
) != SP_REGNUM
))
10547 for (; i
< count
; i
++)
10549 elt
= XVECEXP (op
, 0, i
);
10550 if (GET_CODE (elt
) != SET
)
10555 reg
= SET_DEST (elt
);
10556 mem
= SET_SRC (elt
);
10560 reg
= SET_SRC (elt
);
10561 mem
= SET_DEST (elt
);
10565 || GET_MODE (reg
) != mode
10566 || REGNO (reg
) <= regno
10569 (unsigned int) (first_regno
+ regs_per_val
* (i
- base
))))
10570 /* Don't allow SP to be loaded unless it is also the base register. It
10571 guarantees that SP is reset correctly when an LDM instruction
10572 is interrupted. Otherwise, we might end up with a corrupt stack. */
10573 || (load
&& (REGNO (reg
) == SP_REGNUM
) && (REGNO (addr
) != SP_REGNUM
))
10575 || GET_MODE (mem
) != mode
10576 || ((GET_CODE (XEXP (mem
, 0)) != PLUS
10577 || !rtx_equal_p (XEXP (XEXP (mem
, 0), 0), addr
)
10578 || !CONST_INT_P (XEXP (XEXP (mem
, 0), 1))
10579 || (INTVAL (XEXP (XEXP (mem
, 0), 1)) !=
10580 offset
+ (i
- base
) * reg_increment
))
10581 && (!REG_P (XEXP (mem
, 0))
10582 || offset
+ (i
- base
) * reg_increment
!= 0)))
10585 regno
= REGNO (reg
);
10586 if (regno
== REGNO (addr
))
10587 addr_reg_in_reglist
= true;
10592 if (update
&& addr_reg_in_reglist
)
10595 /* For Thumb-1, address register is always modified - either by write-back
10596 or by explicit load. If the pattern does not describe an update,
10597 then the address register must be in the list of loaded registers. */
10599 return update
|| addr_reg_in_reglist
;
10605 /* Return true iff it would be profitable to turn a sequence of NOPS loads
10606 or stores (depending on IS_STORE) into a load-multiple or store-multiple
10607 instruction. ADD_OFFSET is nonzero if the base address register needs
10608 to be modified with an add instruction before we can use it. */
10611 multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED
,
10612 int nops
, HOST_WIDE_INT add_offset
)
10614 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
10615 if the offset isn't small enough. The reason 2 ldrs are faster
10616 is because these ARMs are able to do more than one cache access
10617 in a single cycle. The ARM9 and StrongARM have Harvard caches,
10618 whilst the ARM8 has a double bandwidth cache. This means that
10619 these cores can do both an instruction fetch and a data fetch in
10620 a single cycle, so the trick of calculating the address into a
10621 scratch register (one of the result regs) and then doing a load
10622 multiple actually becomes slower (and no smaller in code size).
10623 That is the transformation
10625 ldr rd1, [rbase + offset]
10626 ldr rd2, [rbase + offset + 4]
10630 add rd1, rbase, offset
10631 ldmia rd1, {rd1, rd2}
10633 produces worse code -- '3 cycles + any stalls on rd2' instead of
10634 '2 cycles + any stalls on rd2'. On ARMs with only one cache
10635 access per cycle, the first sequence could never complete in less
10636 than 6 cycles, whereas the ldm sequence would only take 5 and
10637 would make better use of sequential accesses if not hitting the
10640 We cheat here and test 'arm_ld_sched' which we currently know to
10641 only be true for the ARM8, ARM9 and StrongARM. If this ever
10642 changes, then the test below needs to be reworked. */
10643 if (nops
== 2 && arm_ld_sched
&& add_offset
!= 0)
10646 /* XScale has load-store double instructions, but they have stricter
10647 alignment requirements than load-store multiple, so we cannot
10650 For XScale ldm requires 2 + NREGS cycles to complete and blocks
10651 the pipeline until completion.
10659 An ldr instruction takes 1-3 cycles, but does not block the
10668 Best case ldr will always win. However, the more ldr instructions
10669 we issue, the less likely we are to be able to schedule them well.
10670 Using ldr instructions also increases code size.
10672 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
10673 for counts of 3 or 4 regs. */
10674 if (nops
<= 2 && arm_tune_xscale
&& !optimize_size
)
10679 /* Subroutine of load_multiple_sequence and store_multiple_sequence.
10680 Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
10681 an array ORDER which describes the sequence to use when accessing the
10682 offsets that produces an ascending order. In this sequence, each
10683 offset must be larger by exactly 4 than the previous one. ORDER[0]
10684 must have been filled in with the lowest offset by the caller.
10685 If UNSORTED_REGS is nonnull, it is an array of register numbers that
10686 we use to verify that ORDER produces an ascending order of registers.
10687 Return true if it was possible to construct such an order, false if
10691 compute_offset_order (int nops
, HOST_WIDE_INT
*unsorted_offsets
, int *order
,
10692 int *unsorted_regs
)
10695 for (i
= 1; i
< nops
; i
++)
10699 order
[i
] = order
[i
- 1];
10700 for (j
= 0; j
< nops
; j
++)
10701 if (unsorted_offsets
[j
] == unsorted_offsets
[order
[i
- 1]] + 4)
10703 /* We must find exactly one offset that is higher than the
10704 previous one by 4. */
10705 if (order
[i
] != order
[i
- 1])
10709 if (order
[i
] == order
[i
- 1])
10711 /* The register numbers must be ascending. */
10712 if (unsorted_regs
!= NULL
10713 && unsorted_regs
[order
[i
]] <= unsorted_regs
[order
[i
- 1]])
10719 /* Used to determine in a peephole whether a sequence of load
10720 instructions can be changed into a load-multiple instruction.
10721 NOPS is the number of separate load instructions we are examining. The
10722 first NOPS entries in OPERANDS are the destination registers, the
10723 next NOPS entries are memory operands. If this function is
10724 successful, *BASE is set to the common base register of the memory
10725 accesses; *LOAD_OFFSET is set to the first memory location's offset
10726 from that base register.
10727 REGS is an array filled in with the destination register numbers.
10728 SAVED_ORDER (if nonnull), is an array filled in with an order that maps
10729 insn numbers to an ascending order of stores. If CHECK_REGS is true,
10730 the sequence of registers in REGS matches the loads from ascending memory
10731 locations, and the function verifies that the register numbers are
10732 themselves ascending. If CHECK_REGS is false, the register numbers
10733 are stored in the order they are found in the operands. */
10735 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *saved_order
,
10736 int *base
, HOST_WIDE_INT
*load_offset
, bool check_regs
)
10738 int unsorted_regs
[MAX_LDM_STM_OPS
];
10739 HOST_WIDE_INT unsorted_offsets
[MAX_LDM_STM_OPS
];
10740 int order
[MAX_LDM_STM_OPS
];
10741 rtx base_reg_rtx
= NULL
;
10745 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
10746 easily extended if required. */
10747 gcc_assert (nops
>= 2 && nops
<= MAX_LDM_STM_OPS
);
10749 memset (order
, 0, MAX_LDM_STM_OPS
* sizeof (int));
10751 /* Loop over the operands and check that the memory references are
10752 suitable (i.e. immediate offsets from the same base register). At
10753 the same time, extract the target register, and the memory
10755 for (i
= 0; i
< nops
; i
++)
10760 /* Convert a subreg of a mem into the mem itself. */
10761 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
10762 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
), true);
10764 gcc_assert (MEM_P (operands
[nops
+ i
]));
10766 /* Don't reorder volatile memory references; it doesn't seem worth
10767 looking for the case where the order is ok anyway. */
10768 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
10771 offset
= const0_rtx
;
10773 if ((REG_P (reg
= XEXP (operands
[nops
+ i
], 0))
10774 || (GET_CODE (reg
) == SUBREG
10775 && REG_P (reg
= SUBREG_REG (reg
))))
10776 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
10777 && ((REG_P (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0)))
10778 || (GET_CODE (reg
) == SUBREG
10779 && REG_P (reg
= SUBREG_REG (reg
))))
10780 && (CONST_INT_P (offset
10781 = XEXP (XEXP (operands
[nops
+ i
], 0), 1)))))
10785 base_reg
= REGNO (reg
);
10786 base_reg_rtx
= reg
;
10787 if (TARGET_THUMB1
&& base_reg
> LAST_LO_REGNUM
)
10790 else if (base_reg
!= (int) REGNO (reg
))
10791 /* Not addressed from the same base register. */
10794 unsorted_regs
[i
] = (REG_P (operands
[i
])
10795 ? REGNO (operands
[i
])
10796 : REGNO (SUBREG_REG (operands
[i
])));
10798 /* If it isn't an integer register, or if it overwrites the
10799 base register but isn't the last insn in the list, then
10800 we can't do this. */
10801 if (unsorted_regs
[i
] < 0
10802 || (TARGET_THUMB1
&& unsorted_regs
[i
] > LAST_LO_REGNUM
)
10803 || unsorted_regs
[i
] > 14
10804 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
10807 /* Don't allow SP to be loaded unless it is also the base
10808 register. It guarantees that SP is reset correctly when
10809 an LDM instruction is interrupted. Otherwise, we might
10810 end up with a corrupt stack. */
10811 if (unsorted_regs
[i
] == SP_REGNUM
&& base_reg
!= SP_REGNUM
)
10814 unsorted_offsets
[i
] = INTVAL (offset
);
10815 if (i
== 0 || unsorted_offsets
[i
] < unsorted_offsets
[order
[0]])
10819 /* Not a suitable memory address. */
10823 /* All the useful information has now been extracted from the
10824 operands into unsorted_regs and unsorted_offsets; additionally,
10825 order[0] has been set to the lowest offset in the list. Sort
10826 the offsets into order, verifying that they are adjacent, and
10827 check that the register numbers are ascending. */
10828 if (!compute_offset_order (nops
, unsorted_offsets
, order
,
10829 check_regs
? unsorted_regs
: NULL
))
10833 memcpy (saved_order
, order
, sizeof order
);
10839 for (i
= 0; i
< nops
; i
++)
10840 regs
[i
] = unsorted_regs
[check_regs
? order
[i
] : i
];
10842 *load_offset
= unsorted_offsets
[order
[0]];
10846 && !peep2_reg_dead_p (nops
, base_reg_rtx
))
10849 if (unsorted_offsets
[order
[0]] == 0)
10850 ldm_case
= 1; /* ldmia */
10851 else if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
10852 ldm_case
= 2; /* ldmib */
10853 else if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
10854 ldm_case
= 3; /* ldmda */
10855 else if (TARGET_32BIT
&& unsorted_offsets
[order
[nops
- 1]] == -4)
10856 ldm_case
= 4; /* ldmdb */
10857 else if (const_ok_for_arm (unsorted_offsets
[order
[0]])
10858 || const_ok_for_arm (-unsorted_offsets
[order
[0]]))
10863 if (!multiple_operation_profitable_p (false, nops
,
10865 ? unsorted_offsets
[order
[0]] : 0))
10871 /* Used to determine in a peephole whether a sequence of store instructions can
10872 be changed into a store-multiple instruction.
10873 NOPS is the number of separate store instructions we are examining.
10874 NOPS_TOTAL is the total number of instructions recognized by the peephole
10876 The first NOPS entries in OPERANDS are the source registers, the next
10877 NOPS entries are memory operands. If this function is successful, *BASE is
10878 set to the common base register of the memory accesses; *LOAD_OFFSET is set
10879 to the first memory location's offset from that base register. REGS is an
10880 array filled in with the source register numbers, REG_RTXS (if nonnull) is
10881 likewise filled with the corresponding rtx's.
10882 SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn
10883 numbers to an ascending order of stores.
10884 If CHECK_REGS is true, the sequence of registers in *REGS matches the stores
10885 from ascending memory locations, and the function verifies that the register
10886 numbers are themselves ascending. If CHECK_REGS is false, the register
10887 numbers are stored in the order they are found in the operands. */
10889 store_multiple_sequence (rtx
*operands
, int nops
, int nops_total
,
10890 int *regs
, rtx
*reg_rtxs
, int *saved_order
, int *base
,
10891 HOST_WIDE_INT
*load_offset
, bool check_regs
)
10893 int unsorted_regs
[MAX_LDM_STM_OPS
];
10894 rtx unsorted_reg_rtxs
[MAX_LDM_STM_OPS
];
10895 HOST_WIDE_INT unsorted_offsets
[MAX_LDM_STM_OPS
];
10896 int order
[MAX_LDM_STM_OPS
];
10898 rtx base_reg_rtx
= NULL
;
10901 /* Write back of base register is currently only supported for Thumb 1. */
10902 int base_writeback
= TARGET_THUMB1
;
10904 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
10905 easily extended if required. */
10906 gcc_assert (nops
>= 2 && nops
<= MAX_LDM_STM_OPS
);
10908 memset (order
, 0, MAX_LDM_STM_OPS
* sizeof (int));
10910 /* Loop over the operands and check that the memory references are
10911 suitable (i.e. immediate offsets from the same base register). At
10912 the same time, extract the target register, and the memory
10914 for (i
= 0; i
< nops
; i
++)
10919 /* Convert a subreg of a mem into the mem itself. */
10920 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
10921 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
), true);
10923 gcc_assert (MEM_P (operands
[nops
+ i
]));
10925 /* Don't reorder volatile memory references; it doesn't seem worth
10926 looking for the case where the order is ok anyway. */
10927 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
10930 offset
= const0_rtx
;
10932 if ((REG_P (reg
= XEXP (operands
[nops
+ i
], 0))
10933 || (GET_CODE (reg
) == SUBREG
10934 && REG_P (reg
= SUBREG_REG (reg
))))
10935 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
10936 && ((REG_P (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0)))
10937 || (GET_CODE (reg
) == SUBREG
10938 && REG_P (reg
= SUBREG_REG (reg
))))
10939 && (CONST_INT_P (offset
10940 = XEXP (XEXP (operands
[nops
+ i
], 0), 1)))))
10942 unsorted_reg_rtxs
[i
] = (REG_P (operands
[i
])
10943 ? operands
[i
] : SUBREG_REG (operands
[i
]));
10944 unsorted_regs
[i
] = REGNO (unsorted_reg_rtxs
[i
]);
10948 base_reg
= REGNO (reg
);
10949 base_reg_rtx
= reg
;
10950 if (TARGET_THUMB1
&& base_reg
> LAST_LO_REGNUM
)
10953 else if (base_reg
!= (int) REGNO (reg
))
10954 /* Not addressed from the same base register. */
10957 /* If it isn't an integer register, then we can't do this. */
10958 if (unsorted_regs
[i
] < 0
10959 || (TARGET_THUMB1
&& unsorted_regs
[i
] > LAST_LO_REGNUM
)
10960 /* The effects are unpredictable if the base register is
10961 both updated and stored. */
10962 || (base_writeback
&& unsorted_regs
[i
] == base_reg
)
10963 || (TARGET_THUMB2
&& unsorted_regs
[i
] == SP_REGNUM
)
10964 || unsorted_regs
[i
] > 14)
10967 unsorted_offsets
[i
] = INTVAL (offset
);
10968 if (i
== 0 || unsorted_offsets
[i
] < unsorted_offsets
[order
[0]])
10972 /* Not a suitable memory address. */
10976 /* All the useful information has now been extracted from the
10977 operands into unsorted_regs and unsorted_offsets; additionally,
10978 order[0] has been set to the lowest offset in the list. Sort
10979 the offsets into order, verifying that they are adjacent, and
10980 check that the register numbers are ascending. */
10981 if (!compute_offset_order (nops
, unsorted_offsets
, order
,
10982 check_regs
? unsorted_regs
: NULL
))
10986 memcpy (saved_order
, order
, sizeof order
);
10992 for (i
= 0; i
< nops
; i
++)
10994 regs
[i
] = unsorted_regs
[check_regs
? order
[i
] : i
];
10996 reg_rtxs
[i
] = unsorted_reg_rtxs
[check_regs
? order
[i
] : i
];
10999 *load_offset
= unsorted_offsets
[order
[0]];
11003 && !peep2_reg_dead_p (nops_total
, base_reg_rtx
))
11006 if (unsorted_offsets
[order
[0]] == 0)
11007 stm_case
= 1; /* stmia */
11008 else if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
11009 stm_case
= 2; /* stmib */
11010 else if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
11011 stm_case
= 3; /* stmda */
11012 else if (TARGET_32BIT
&& unsorted_offsets
[order
[nops
- 1]] == -4)
11013 stm_case
= 4; /* stmdb */
11017 if (!multiple_operation_profitable_p (false, nops
, 0))
11023 /* Routines for use in generating RTL. */
11025 /* Generate a load-multiple instruction. COUNT is the number of loads in
11026 the instruction; REGS and MEMS are arrays containing the operands.
11027 BASEREG is the base register to be used in addressing the memory operands.
11028 WBACK_OFFSET is nonzero if the instruction should update the base
11032 arm_gen_load_multiple_1 (int count
, int *regs
, rtx
*mems
, rtx basereg
,
11033 HOST_WIDE_INT wback_offset
)
11038 if (!multiple_operation_profitable_p (false, count
, 0))
11044 for (i
= 0; i
< count
; i
++)
11045 emit_move_insn (gen_rtx_REG (SImode
, regs
[i
]), mems
[i
]);
11047 if (wback_offset
!= 0)
11048 emit_move_insn (basereg
, plus_constant (Pmode
, basereg
, wback_offset
));
11050 seq
= get_insns ();
11056 result
= gen_rtx_PARALLEL (VOIDmode
,
11057 rtvec_alloc (count
+ (wback_offset
!= 0 ? 1 : 0)));
11058 if (wback_offset
!= 0)
11060 XVECEXP (result
, 0, 0)
11061 = gen_rtx_SET (VOIDmode
, basereg
,
11062 plus_constant (Pmode
, basereg
, wback_offset
));
11067 for (j
= 0; i
< count
; i
++, j
++)
11068 XVECEXP (result
, 0, i
)
11069 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regs
[j
]), mems
[j
]);
11074 /* Generate a store-multiple instruction. COUNT is the number of stores in
11075 the instruction; REGS and MEMS are arrays containing the operands.
11076 BASEREG is the base register to be used in addressing the memory operands.
11077 WBACK_OFFSET is nonzero if the instruction should update the base
11081 arm_gen_store_multiple_1 (int count
, int *regs
, rtx
*mems
, rtx basereg
,
11082 HOST_WIDE_INT wback_offset
)
11087 if (GET_CODE (basereg
) == PLUS
)
11088 basereg
= XEXP (basereg
, 0);
11090 if (!multiple_operation_profitable_p (false, count
, 0))
11096 for (i
= 0; i
< count
; i
++)
11097 emit_move_insn (mems
[i
], gen_rtx_REG (SImode
, regs
[i
]));
11099 if (wback_offset
!= 0)
11100 emit_move_insn (basereg
, plus_constant (Pmode
, basereg
, wback_offset
));
11102 seq
= get_insns ();
11108 result
= gen_rtx_PARALLEL (VOIDmode
,
11109 rtvec_alloc (count
+ (wback_offset
!= 0 ? 1 : 0)));
11110 if (wback_offset
!= 0)
11112 XVECEXP (result
, 0, 0)
11113 = gen_rtx_SET (VOIDmode
, basereg
,
11114 plus_constant (Pmode
, basereg
, wback_offset
));
11119 for (j
= 0; i
< count
; i
++, j
++)
11120 XVECEXP (result
, 0, i
)
11121 = gen_rtx_SET (VOIDmode
, mems
[j
], gen_rtx_REG (SImode
, regs
[j
]));
11126 /* Generate either a load-multiple or a store-multiple instruction. This
11127 function can be used in situations where we can start with a single MEM
11128 rtx and adjust its address upwards.
11129 COUNT is the number of operations in the instruction, not counting a
11130 possible update of the base register. REGS is an array containing the
11132 BASEREG is the base register to be used in addressing the memory operands,
11133 which are constructed from BASEMEM.
11134 WRITE_BACK specifies whether the generated instruction should include an
11135 update of the base register.
11136 OFFSETP is used to pass an offset to and from this function; this offset
11137 is not used when constructing the address (instead BASEMEM should have an
11138 appropriate offset in its address), it is used only for setting
11139 MEM_OFFSET. It is updated only if WRITE_BACK is true.*/
11142 arm_gen_multiple_op (bool is_load
, int *regs
, int count
, rtx basereg
,
11143 bool write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
11145 rtx mems
[MAX_LDM_STM_OPS
];
11146 HOST_WIDE_INT offset
= *offsetp
;
11149 gcc_assert (count
<= MAX_LDM_STM_OPS
);
11151 if (GET_CODE (basereg
) == PLUS
)
11152 basereg
= XEXP (basereg
, 0);
11154 for (i
= 0; i
< count
; i
++)
11156 rtx addr
= plus_constant (Pmode
, basereg
, i
* 4);
11157 mems
[i
] = adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
11165 return arm_gen_load_multiple_1 (count
, regs
, mems
, basereg
,
11166 write_back
? 4 * count
: 0);
11168 return arm_gen_store_multiple_1 (count
, regs
, mems
, basereg
,
11169 write_back
? 4 * count
: 0);
11173 arm_gen_load_multiple (int *regs
, int count
, rtx basereg
, int write_back
,
11174 rtx basemem
, HOST_WIDE_INT
*offsetp
)
11176 return arm_gen_multiple_op (TRUE
, regs
, count
, basereg
, write_back
, basemem
,
11181 arm_gen_store_multiple (int *regs
, int count
, rtx basereg
, int write_back
,
11182 rtx basemem
, HOST_WIDE_INT
*offsetp
)
11184 return arm_gen_multiple_op (FALSE
, regs
, count
, basereg
, write_back
, basemem
,
11188 /* Called from a peephole2 expander to turn a sequence of loads into an
11189 LDM instruction. OPERANDS are the operands found by the peephole matcher;
11190 NOPS indicates how many separate loads we are trying to combine. SORT_REGS
11191 is true if we can reorder the registers because they are used commutatively
11193 Returns true iff we could generate a new instruction. */
11196 gen_ldm_seq (rtx
*operands
, int nops
, bool sort_regs
)
11198 int regs
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
11199 rtx mems
[MAX_LDM_STM_OPS
];
11200 int i
, j
, base_reg
;
11202 HOST_WIDE_INT offset
;
11203 int write_back
= FALSE
;
11207 ldm_case
= load_multiple_sequence (operands
, nops
, regs
, mem_order
,
11208 &base_reg
, &offset
, !sort_regs
);
11214 for (i
= 0; i
< nops
- 1; i
++)
11215 for (j
= i
+ 1; j
< nops
; j
++)
11216 if (regs
[i
] > regs
[j
])
11222 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
11226 gcc_assert (peep2_reg_dead_p (nops
, base_reg_rtx
));
11227 gcc_assert (ldm_case
== 1 || ldm_case
== 5);
11233 rtx newbase
= TARGET_THUMB1
? base_reg_rtx
: gen_rtx_REG (SImode
, regs
[0]);
11234 emit_insn (gen_addsi3 (newbase
, base_reg_rtx
, GEN_INT (offset
)));
11236 if (!TARGET_THUMB1
)
11238 base_reg
= regs
[0];
11239 base_reg_rtx
= newbase
;
11243 for (i
= 0; i
< nops
; i
++)
11245 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
+ i
* 4);
11246 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
11249 emit_insn (arm_gen_load_multiple_1 (nops
, regs
, mems
, base_reg_rtx
,
11250 write_back
? offset
+ i
* 4 : 0));
11254 /* Called from a peephole2 expander to turn a sequence of stores into an
11255 STM instruction. OPERANDS are the operands found by the peephole matcher;
11256 NOPS indicates how many separate stores we are trying to combine.
11257 Returns true iff we could generate a new instruction. */
11260 gen_stm_seq (rtx
*operands
, int nops
)
11263 int regs
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
11264 rtx mems
[MAX_LDM_STM_OPS
];
11267 HOST_WIDE_INT offset
;
11268 int write_back
= FALSE
;
11271 bool base_reg_dies
;
11273 stm_case
= store_multiple_sequence (operands
, nops
, nops
, regs
, NULL
,
11274 mem_order
, &base_reg
, &offset
, true);
11279 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
11281 base_reg_dies
= peep2_reg_dead_p (nops
, base_reg_rtx
);
11284 gcc_assert (base_reg_dies
);
11290 gcc_assert (base_reg_dies
);
11291 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, GEN_INT (offset
)));
11295 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
);
11297 for (i
= 0; i
< nops
; i
++)
11299 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
+ i
* 4);
11300 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
11303 emit_insn (arm_gen_store_multiple_1 (nops
, regs
, mems
, base_reg_rtx
,
11304 write_back
? offset
+ i
* 4 : 0));
11308 /* Called from a peephole2 expander to turn a sequence of stores that are
11309 preceded by constant loads into an STM instruction. OPERANDS are the
11310 operands found by the peephole matcher; NOPS indicates how many
11311 separate stores we are trying to combine; there are 2 * NOPS
11312 instructions in the peephole.
11313 Returns true iff we could generate a new instruction. */
11316 gen_const_stm_seq (rtx
*operands
, int nops
)
11318 int regs
[MAX_LDM_STM_OPS
], sorted_regs
[MAX_LDM_STM_OPS
];
11319 int reg_order
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
11320 rtx reg_rtxs
[MAX_LDM_STM_OPS
], orig_reg_rtxs
[MAX_LDM_STM_OPS
];
11321 rtx mems
[MAX_LDM_STM_OPS
];
11324 HOST_WIDE_INT offset
;
11325 int write_back
= FALSE
;
11328 bool base_reg_dies
;
11330 HARD_REG_SET allocated
;
11332 stm_case
= store_multiple_sequence (operands
, nops
, 2 * nops
, regs
, reg_rtxs
,
11333 mem_order
, &base_reg
, &offset
, false);
11338 memcpy (orig_reg_rtxs
, reg_rtxs
, sizeof orig_reg_rtxs
);
11340 /* If the same register is used more than once, try to find a free
11342 CLEAR_HARD_REG_SET (allocated
);
11343 for (i
= 0; i
< nops
; i
++)
11345 for (j
= i
+ 1; j
< nops
; j
++)
11346 if (regs
[i
] == regs
[j
])
11348 rtx t
= peep2_find_free_register (0, nops
* 2,
11349 TARGET_THUMB1
? "l" : "r",
11350 SImode
, &allocated
);
11354 regs
[i
] = REGNO (t
);
11358 /* Compute an ordering that maps the register numbers to an ascending
11361 for (i
= 0; i
< nops
; i
++)
11362 if (regs
[i
] < regs
[reg_order
[0]])
11365 for (i
= 1; i
< nops
; i
++)
11367 int this_order
= reg_order
[i
- 1];
11368 for (j
= 0; j
< nops
; j
++)
11369 if (regs
[j
] > regs
[reg_order
[i
- 1]]
11370 && (this_order
== reg_order
[i
- 1]
11371 || regs
[j
] < regs
[this_order
]))
11373 reg_order
[i
] = this_order
;
11376 /* Ensure that registers that must be live after the instruction end
11377 up with the correct value. */
11378 for (i
= 0; i
< nops
; i
++)
11380 int this_order
= reg_order
[i
];
11381 if ((this_order
!= mem_order
[i
]
11382 || orig_reg_rtxs
[this_order
] != reg_rtxs
[this_order
])
11383 && !peep2_reg_dead_p (nops
* 2, orig_reg_rtxs
[this_order
]))
11387 /* Load the constants. */
11388 for (i
= 0; i
< nops
; i
++)
11390 rtx op
= operands
[2 * nops
+ mem_order
[i
]];
11391 sorted_regs
[i
] = regs
[reg_order
[i
]];
11392 emit_move_insn (reg_rtxs
[reg_order
[i
]], op
);
11395 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
11397 base_reg_dies
= peep2_reg_dead_p (nops
* 2, base_reg_rtx
);
11400 gcc_assert (base_reg_dies
);
11406 gcc_assert (base_reg_dies
);
11407 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, GEN_INT (offset
)));
11411 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
);
11413 for (i
= 0; i
< nops
; i
++)
11415 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
+ i
* 4);
11416 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
11419 emit_insn (arm_gen_store_multiple_1 (nops
, sorted_regs
, mems
, base_reg_rtx
,
11420 write_back
? offset
+ i
* 4 : 0));
11424 /* Copy a block of memory using plain ldr/str/ldrh/strh instructions, to permit
11425 unaligned copies on processors which support unaligned semantics for those
11426 instructions. INTERLEAVE_FACTOR can be used to attempt to hide load latency
11427 (using more registers) by doing e.g. load/load/store/store for a factor of 2.
11428 An interleave factor of 1 (the minimum) will perform no interleaving.
11429 Load/store multiple are used for aligned addresses where possible. */
11432 arm_block_move_unaligned_straight (rtx dstbase
, rtx srcbase
,
11433 HOST_WIDE_INT length
,
11434 unsigned int interleave_factor
)
11436 rtx
*regs
= XALLOCAVEC (rtx
, interleave_factor
);
11437 int *regnos
= XALLOCAVEC (int, interleave_factor
);
11438 HOST_WIDE_INT block_size_bytes
= interleave_factor
* UNITS_PER_WORD
;
11439 HOST_WIDE_INT i
, j
;
11440 HOST_WIDE_INT remaining
= length
, words
;
11441 rtx halfword_tmp
= NULL
, byte_tmp
= NULL
;
11443 bool src_aligned
= MEM_ALIGN (srcbase
) >= BITS_PER_WORD
;
11444 bool dst_aligned
= MEM_ALIGN (dstbase
) >= BITS_PER_WORD
;
11445 HOST_WIDE_INT srcoffset
, dstoffset
;
11446 HOST_WIDE_INT src_autoinc
, dst_autoinc
;
11449 gcc_assert (1 <= interleave_factor
&& interleave_factor
<= 4);
11451 /* Use hard registers if we have aligned source or destination so we can use
11452 load/store multiple with contiguous registers. */
11453 if (dst_aligned
|| src_aligned
)
11454 for (i
= 0; i
< interleave_factor
; i
++)
11455 regs
[i
] = gen_rtx_REG (SImode
, i
);
11457 for (i
= 0; i
< interleave_factor
; i
++)
11458 regs
[i
] = gen_reg_rtx (SImode
);
11460 dst
= copy_addr_to_reg (XEXP (dstbase
, 0));
11461 src
= copy_addr_to_reg (XEXP (srcbase
, 0));
11463 srcoffset
= dstoffset
= 0;
11465 /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST.
11466 For copying the last bytes we want to subtract this offset again. */
11467 src_autoinc
= dst_autoinc
= 0;
11469 for (i
= 0; i
< interleave_factor
; i
++)
11472 /* Copy BLOCK_SIZE_BYTES chunks. */
11474 for (i
= 0; i
+ block_size_bytes
<= length
; i
+= block_size_bytes
)
11477 if (src_aligned
&& interleave_factor
> 1)
11479 emit_insn (arm_gen_load_multiple (regnos
, interleave_factor
, src
,
11480 TRUE
, srcbase
, &srcoffset
));
11481 src_autoinc
+= UNITS_PER_WORD
* interleave_factor
;
11485 for (j
= 0; j
< interleave_factor
; j
++)
11487 addr
= plus_constant (Pmode
, src
, (srcoffset
+ j
* UNITS_PER_WORD
11489 mem
= adjust_automodify_address (srcbase
, SImode
, addr
,
11490 srcoffset
+ j
* UNITS_PER_WORD
);
11491 emit_insn (gen_unaligned_loadsi (regs
[j
], mem
));
11493 srcoffset
+= block_size_bytes
;
11497 if (dst_aligned
&& interleave_factor
> 1)
11499 emit_insn (arm_gen_store_multiple (regnos
, interleave_factor
, dst
,
11500 TRUE
, dstbase
, &dstoffset
));
11501 dst_autoinc
+= UNITS_PER_WORD
* interleave_factor
;
11505 for (j
= 0; j
< interleave_factor
; j
++)
11507 addr
= plus_constant (Pmode
, dst
, (dstoffset
+ j
* UNITS_PER_WORD
11509 mem
= adjust_automodify_address (dstbase
, SImode
, addr
,
11510 dstoffset
+ j
* UNITS_PER_WORD
);
11511 emit_insn (gen_unaligned_storesi (mem
, regs
[j
]));
11513 dstoffset
+= block_size_bytes
;
11516 remaining
-= block_size_bytes
;
11519 /* Copy any whole words left (note these aren't interleaved with any
11520 subsequent halfword/byte load/stores in the interests of simplicity). */
11522 words
= remaining
/ UNITS_PER_WORD
;
11524 gcc_assert (words
< interleave_factor
);
11526 if (src_aligned
&& words
> 1)
11528 emit_insn (arm_gen_load_multiple (regnos
, words
, src
, TRUE
, srcbase
,
11530 src_autoinc
+= UNITS_PER_WORD
* words
;
11534 for (j
= 0; j
< words
; j
++)
11536 addr
= plus_constant (Pmode
, src
,
11537 srcoffset
+ j
* UNITS_PER_WORD
- src_autoinc
);
11538 mem
= adjust_automodify_address (srcbase
, SImode
, addr
,
11539 srcoffset
+ j
* UNITS_PER_WORD
);
11540 emit_insn (gen_unaligned_loadsi (regs
[j
], mem
));
11542 srcoffset
+= words
* UNITS_PER_WORD
;
11545 if (dst_aligned
&& words
> 1)
11547 emit_insn (arm_gen_store_multiple (regnos
, words
, dst
, TRUE
, dstbase
,
11549 dst_autoinc
+= words
* UNITS_PER_WORD
;
11553 for (j
= 0; j
< words
; j
++)
11555 addr
= plus_constant (Pmode
, dst
,
11556 dstoffset
+ j
* UNITS_PER_WORD
- dst_autoinc
);
11557 mem
= adjust_automodify_address (dstbase
, SImode
, addr
,
11558 dstoffset
+ j
* UNITS_PER_WORD
);
11559 emit_insn (gen_unaligned_storesi (mem
, regs
[j
]));
11561 dstoffset
+= words
* UNITS_PER_WORD
;
11564 remaining
-= words
* UNITS_PER_WORD
;
11566 gcc_assert (remaining
< 4);
11568 /* Copy a halfword if necessary. */
11570 if (remaining
>= 2)
11572 halfword_tmp
= gen_reg_rtx (SImode
);
11574 addr
= plus_constant (Pmode
, src
, srcoffset
- src_autoinc
);
11575 mem
= adjust_automodify_address (srcbase
, HImode
, addr
, srcoffset
);
11576 emit_insn (gen_unaligned_loadhiu (halfword_tmp
, mem
));
11578 /* Either write out immediately, or delay until we've loaded the last
11579 byte, depending on interleave factor. */
11580 if (interleave_factor
== 1)
11582 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
11583 mem
= adjust_automodify_address (dstbase
, HImode
, addr
, dstoffset
);
11584 emit_insn (gen_unaligned_storehi (mem
,
11585 gen_lowpart (HImode
, halfword_tmp
)));
11586 halfword_tmp
= NULL
;
11594 gcc_assert (remaining
< 2);
11596 /* Copy last byte. */
11598 if ((remaining
& 1) != 0)
11600 byte_tmp
= gen_reg_rtx (SImode
);
11602 addr
= plus_constant (Pmode
, src
, srcoffset
- src_autoinc
);
11603 mem
= adjust_automodify_address (srcbase
, QImode
, addr
, srcoffset
);
11604 emit_move_insn (gen_lowpart (QImode
, byte_tmp
), mem
);
11606 if (interleave_factor
== 1)
11608 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
11609 mem
= adjust_automodify_address (dstbase
, QImode
, addr
, dstoffset
);
11610 emit_move_insn (mem
, gen_lowpart (QImode
, byte_tmp
));
11619 /* Store last halfword if we haven't done so already. */
11623 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
11624 mem
= adjust_automodify_address (dstbase
, HImode
, addr
, dstoffset
);
11625 emit_insn (gen_unaligned_storehi (mem
,
11626 gen_lowpart (HImode
, halfword_tmp
)));
11630 /* Likewise for last byte. */
11634 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
11635 mem
= adjust_automodify_address (dstbase
, QImode
, addr
, dstoffset
);
11636 emit_move_insn (mem
, gen_lowpart (QImode
, byte_tmp
));
11640 gcc_assert (remaining
== 0 && srcoffset
== dstoffset
);
11643 /* From mips_adjust_block_mem:
11645 Helper function for doing a loop-based block operation on memory
11646 reference MEM. Each iteration of the loop will operate on LENGTH
11649 Create a new base register for use within the loop and point it to
11650 the start of MEM. Create a new memory reference that uses this
11651 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
11654 arm_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
, rtx
*loop_reg
,
11657 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
11659 /* Although the new mem does not refer to a known location,
11660 it does keep up to LENGTH bytes of alignment. */
11661 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
11662 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
11665 /* From mips_block_move_loop:
11667 Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
11668 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
11669 the memory regions do not overlap. */
11672 arm_block_move_unaligned_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
11673 unsigned int interleave_factor
,
11674 HOST_WIDE_INT bytes_per_iter
)
11676 rtx label
, src_reg
, dest_reg
, final_src
, test
;
11677 HOST_WIDE_INT leftover
;
11679 leftover
= length
% bytes_per_iter
;
11680 length
-= leftover
;
11682 /* Create registers and memory references for use within the loop. */
11683 arm_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
11684 arm_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
11686 /* Calculate the value that SRC_REG should have after the last iteration of
11688 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
11689 0, 0, OPTAB_WIDEN
);
11691 /* Emit the start of the loop. */
11692 label
= gen_label_rtx ();
11693 emit_label (label
);
11695 /* Emit the loop body. */
11696 arm_block_move_unaligned_straight (dest
, src
, bytes_per_iter
,
11697 interleave_factor
);
11699 /* Move on to the next block. */
11700 emit_move_insn (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
11701 emit_move_insn (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
11703 /* Emit the loop condition. */
11704 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
11705 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
11707 /* Mop up any left-over bytes. */
11709 arm_block_move_unaligned_straight (dest
, src
, leftover
, interleave_factor
);
11712 /* Emit a block move when either the source or destination is unaligned (not
11713 aligned to a four-byte boundary). This may need further tuning depending on
11714 core type, optimize_size setting, etc. */
11717 arm_movmemqi_unaligned (rtx
*operands
)
11719 HOST_WIDE_INT length
= INTVAL (operands
[2]);
11723 bool src_aligned
= MEM_ALIGN (operands
[1]) >= BITS_PER_WORD
;
11724 bool dst_aligned
= MEM_ALIGN (operands
[0]) >= BITS_PER_WORD
;
11725 /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
11726 size of code if optimizing for size. We'll use ldm/stm if src_aligned
11727 or dst_aligned though: allow more interleaving in those cases since the
11728 resulting code can be smaller. */
11729 unsigned int interleave_factor
= (src_aligned
|| dst_aligned
) ? 2 : 1;
11730 HOST_WIDE_INT bytes_per_iter
= (src_aligned
|| dst_aligned
) ? 8 : 4;
11733 arm_block_move_unaligned_loop (operands
[0], operands
[1], length
,
11734 interleave_factor
, bytes_per_iter
);
11736 arm_block_move_unaligned_straight (operands
[0], operands
[1], length
,
11737 interleave_factor
);
11741 /* Note that the loop created by arm_block_move_unaligned_loop may be
11742 subject to loop unrolling, which makes tuning this condition a little
11745 arm_block_move_unaligned_loop (operands
[0], operands
[1], length
, 4, 16);
11747 arm_block_move_unaligned_straight (operands
[0], operands
[1], length
, 4);
11754 arm_gen_movmemqi (rtx
*operands
)
11756 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
11757 HOST_WIDE_INT srcoffset
, dstoffset
;
11759 rtx src
, dst
, srcbase
, dstbase
;
11760 rtx part_bytes_reg
= NULL
;
11763 if (!CONST_INT_P (operands
[2])
11764 || !CONST_INT_P (operands
[3])
11765 || INTVAL (operands
[2]) > 64)
11768 if (unaligned_access
&& (INTVAL (operands
[3]) & 3) != 0)
11769 return arm_movmemqi_unaligned (operands
);
11771 if (INTVAL (operands
[3]) & 3)
11774 dstbase
= operands
[0];
11775 srcbase
= operands
[1];
11777 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
11778 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
11780 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
11781 out_words_to_go
= INTVAL (operands
[2]) / 4;
11782 last_bytes
= INTVAL (operands
[2]) & 3;
11783 dstoffset
= srcoffset
= 0;
11785 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
11786 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
11788 for (i
= 0; in_words_to_go
>= 2; i
+=4)
11790 if (in_words_to_go
> 4)
11791 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence
, 4, src
,
11792 TRUE
, srcbase
, &srcoffset
));
11794 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence
, in_words_to_go
,
11795 src
, FALSE
, srcbase
,
11798 if (out_words_to_go
)
11800 if (out_words_to_go
> 4)
11801 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence
, 4, dst
,
11802 TRUE
, dstbase
, &dstoffset
));
11803 else if (out_words_to_go
!= 1)
11804 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence
,
11805 out_words_to_go
, dst
,
11808 dstbase
, &dstoffset
));
11811 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
11812 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
11813 if (last_bytes
!= 0)
11815 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
11821 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
11822 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
11825 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
11826 if (out_words_to_go
)
11830 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
11831 sreg
= copy_to_reg (mem
);
11833 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
11834 emit_move_insn (mem
, sreg
);
11837 gcc_assert (!in_words_to_go
); /* Sanity check */
11840 if (in_words_to_go
)
11842 gcc_assert (in_words_to_go
> 0);
11844 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
11845 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
11848 gcc_assert (!last_bytes
|| part_bytes_reg
);
11850 if (BYTES_BIG_ENDIAN
&& last_bytes
)
11852 rtx tmp
= gen_reg_rtx (SImode
);
11854 /* The bytes we want are in the top end of the word. */
11855 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
11856 GEN_INT (8 * (4 - last_bytes
))));
11857 part_bytes_reg
= tmp
;
11861 mem
= adjust_automodify_address (dstbase
, QImode
,
11862 plus_constant (Pmode
, dst
,
11864 dstoffset
+ last_bytes
- 1);
11865 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
11869 tmp
= gen_reg_rtx (SImode
);
11870 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
11871 part_bytes_reg
= tmp
;
11878 if (last_bytes
> 1)
11880 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
11881 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
11885 rtx tmp
= gen_reg_rtx (SImode
);
11886 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
11887 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
11888 part_bytes_reg
= tmp
;
11895 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
11896 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
11903 /* Helper for gen_movmem_ldrd_strd. Increase the address of memory rtx
11906 next_consecutive_mem (rtx mem
)
11908 enum machine_mode mode
= GET_MODE (mem
);
11909 HOST_WIDE_INT offset
= GET_MODE_SIZE (mode
);
11910 rtx addr
= plus_constant (Pmode
, XEXP (mem
, 0), offset
);
11912 return adjust_automodify_address (mem
, mode
, addr
, offset
);
11915 /* Copy using LDRD/STRD instructions whenever possible.
11916 Returns true upon success. */
11918 gen_movmem_ldrd_strd (rtx
*operands
)
11920 unsigned HOST_WIDE_INT len
;
11921 HOST_WIDE_INT align
;
11922 rtx src
, dst
, base
;
11924 bool src_aligned
, dst_aligned
;
11925 bool src_volatile
, dst_volatile
;
11927 gcc_assert (CONST_INT_P (operands
[2]));
11928 gcc_assert (CONST_INT_P (operands
[3]));
11930 len
= UINTVAL (operands
[2]);
11934 /* Maximum alignment we can assume for both src and dst buffers. */
11935 align
= INTVAL (operands
[3]);
11937 if ((!unaligned_access
) && (len
>= 4) && ((align
& 3) != 0))
11940 /* Place src and dst addresses in registers
11941 and update the corresponding mem rtx. */
11943 dst_volatile
= MEM_VOLATILE_P (dst
);
11944 dst_aligned
= MEM_ALIGN (dst
) >= BITS_PER_WORD
;
11945 base
= copy_to_mode_reg (SImode
, XEXP (dst
, 0));
11946 dst
= adjust_automodify_address (dst
, VOIDmode
, base
, 0);
11949 src_volatile
= MEM_VOLATILE_P (src
);
11950 src_aligned
= MEM_ALIGN (src
) >= BITS_PER_WORD
;
11951 base
= copy_to_mode_reg (SImode
, XEXP (src
, 0));
11952 src
= adjust_automodify_address (src
, VOIDmode
, base
, 0);
11954 if (!unaligned_access
&& !(src_aligned
&& dst_aligned
))
11957 if (src_volatile
|| dst_volatile
)
11960 /* If we cannot generate any LDRD/STRD, try to generate LDM/STM. */
11961 if (!(dst_aligned
|| src_aligned
))
11962 return arm_gen_movmemqi (operands
);
11964 src
= adjust_address (src
, DImode
, 0);
11965 dst
= adjust_address (dst
, DImode
, 0);
11969 reg0
= gen_reg_rtx (DImode
);
11971 emit_move_insn (reg0
, src
);
11973 emit_insn (gen_unaligned_loaddi (reg0
, src
));
11976 emit_move_insn (dst
, reg0
);
11978 emit_insn (gen_unaligned_storedi (dst
, reg0
));
11980 src
= next_consecutive_mem (src
);
11981 dst
= next_consecutive_mem (dst
);
11984 gcc_assert (len
< 8);
11987 /* More than a word but less than a double-word to copy. Copy a word. */
11988 reg0
= gen_reg_rtx (SImode
);
11989 src
= adjust_address (src
, SImode
, 0);
11990 dst
= adjust_address (dst
, SImode
, 0);
11992 emit_move_insn (reg0
, src
);
11994 emit_insn (gen_unaligned_loadsi (reg0
, src
));
11997 emit_move_insn (dst
, reg0
);
11999 emit_insn (gen_unaligned_storesi (dst
, reg0
));
12001 src
= next_consecutive_mem (src
);
12002 dst
= next_consecutive_mem (dst
);
12009 /* Copy the remaining bytes. */
12012 dst
= adjust_address (dst
, HImode
, 0);
12013 src
= adjust_address (src
, HImode
, 0);
12014 reg0
= gen_reg_rtx (SImode
);
12015 emit_insn (gen_unaligned_loadhiu (reg0
, src
));
12016 emit_insn (gen_unaligned_storehi (dst
, gen_lowpart (HImode
, reg0
)));
12017 src
= next_consecutive_mem (src
);
12018 dst
= next_consecutive_mem (dst
);
12023 dst
= adjust_address (dst
, QImode
, 0);
12024 src
= adjust_address (src
, QImode
, 0);
12025 reg0
= gen_reg_rtx (QImode
);
12026 emit_move_insn (reg0
, src
);
12027 emit_move_insn (dst
, reg0
);
12031 /* Select a dominance comparison mode if possible for a test of the general
12032 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
12033 COND_OR == DOM_CC_X_AND_Y => (X && Y)
12034 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
12035 COND_OR == DOM_CC_X_OR_Y => (X || Y)
12036 In all cases OP will be either EQ or NE, but we don't need to know which
12037 here. If we are unable to support a dominance comparison we return
12038 CC mode. This will then fail to match for the RTL expressions that
12039 generate this call. */
12041 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
12043 enum rtx_code cond1
, cond2
;
12046 /* Currently we will probably get the wrong result if the individual
12047 comparisons are not simple. This also ensures that it is safe to
12048 reverse a comparison if necessary. */
12049 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
12051 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
12055 /* The if_then_else variant of this tests the second condition if the
12056 first passes, but is true if the first fails. Reverse the first
12057 condition to get a true "inclusive-or" expression. */
12058 if (cond_or
== DOM_CC_NX_OR_Y
)
12059 cond1
= reverse_condition (cond1
);
12061 /* If the comparisons are not equal, and one doesn't dominate the other,
12062 then we can't do this. */
12064 && !comparison_dominates_p (cond1
, cond2
)
12065 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
12070 enum rtx_code temp
= cond1
;
12078 if (cond_or
== DOM_CC_X_AND_Y
)
12083 case EQ
: return CC_DEQmode
;
12084 case LE
: return CC_DLEmode
;
12085 case LEU
: return CC_DLEUmode
;
12086 case GE
: return CC_DGEmode
;
12087 case GEU
: return CC_DGEUmode
;
12088 default: gcc_unreachable ();
12092 if (cond_or
== DOM_CC_X_AND_Y
)
12104 gcc_unreachable ();
12108 if (cond_or
== DOM_CC_X_AND_Y
)
12120 gcc_unreachable ();
12124 if (cond_or
== DOM_CC_X_AND_Y
)
12125 return CC_DLTUmode
;
12130 return CC_DLTUmode
;
12132 return CC_DLEUmode
;
12136 gcc_unreachable ();
12140 if (cond_or
== DOM_CC_X_AND_Y
)
12141 return CC_DGTUmode
;
12146 return CC_DGTUmode
;
12148 return CC_DGEUmode
;
12152 gcc_unreachable ();
12155 /* The remaining cases only occur when both comparisons are the
12158 gcc_assert (cond1
== cond2
);
12162 gcc_assert (cond1
== cond2
);
12166 gcc_assert (cond1
== cond2
);
12170 gcc_assert (cond1
== cond2
);
12171 return CC_DLEUmode
;
12174 gcc_assert (cond1
== cond2
);
12175 return CC_DGEUmode
;
12178 gcc_unreachable ();
12183 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
12185 /* All floating point compares return CCFP if it is an equality
12186 comparison, and CCFPE otherwise. */
12187 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
12210 gcc_unreachable ();
12214 /* A compare with a shifted operand. Because of canonicalization, the
12215 comparison will have to be swapped when we emit the assembler. */
12216 if (GET_MODE (y
) == SImode
12217 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
))
12218 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
12219 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
12220 || GET_CODE (x
) == ROTATERT
))
12223 /* This operation is performed swapped, but since we only rely on the Z
12224 flag we don't need an additional mode. */
12225 if (GET_MODE (y
) == SImode
12226 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
))
12227 && GET_CODE (x
) == NEG
12228 && (op
== EQ
|| op
== NE
))
12231 /* This is a special case that is used by combine to allow a
12232 comparison of a shifted byte load to be split into a zero-extend
12233 followed by a comparison of the shifted integer (only valid for
12234 equalities and unsigned inequalities). */
12235 if (GET_MODE (x
) == SImode
12236 && GET_CODE (x
) == ASHIFT
12237 && CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 24
12238 && GET_CODE (XEXP (x
, 0)) == SUBREG
12239 && MEM_P (SUBREG_REG (XEXP (x
, 0)))
12240 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
12241 && (op
== EQ
|| op
== NE
12242 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
12243 && CONST_INT_P (y
))
12246 /* A construct for a conditional compare, if the false arm contains
12247 0, then both conditions must be true, otherwise either condition
12248 must be true. Not all conditions are possible, so CCmode is
12249 returned if it can't be done. */
12250 if (GET_CODE (x
) == IF_THEN_ELSE
12251 && (XEXP (x
, 2) == const0_rtx
12252 || XEXP (x
, 2) == const1_rtx
)
12253 && COMPARISON_P (XEXP (x
, 0))
12254 && COMPARISON_P (XEXP (x
, 1)))
12255 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
12256 INTVAL (XEXP (x
, 2)));
12258 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
12259 if (GET_CODE (x
) == AND
12260 && (op
== EQ
|| op
== NE
)
12261 && COMPARISON_P (XEXP (x
, 0))
12262 && COMPARISON_P (XEXP (x
, 1)))
12263 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
12266 if (GET_CODE (x
) == IOR
12267 && (op
== EQ
|| op
== NE
)
12268 && COMPARISON_P (XEXP (x
, 0))
12269 && COMPARISON_P (XEXP (x
, 1)))
12270 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
12273 /* An operation (on Thumb) where we want to test for a single bit.
12274 This is done by shifting that bit up into the top bit of a
12275 scratch register; we can then branch on the sign bit. */
12277 && GET_MODE (x
) == SImode
12278 && (op
== EQ
|| op
== NE
)
12279 && GET_CODE (x
) == ZERO_EXTRACT
12280 && XEXP (x
, 1) == const1_rtx
)
12283 /* An operation that sets the condition codes as a side-effect, the
12284 V flag is not set correctly, so we can only use comparisons where
12285 this doesn't matter. (For LT and GE we can use "mi" and "pl"
12287 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
12288 if (GET_MODE (x
) == SImode
12290 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
12291 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
12292 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
12293 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
12294 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
12295 || GET_CODE (x
) == LSHIFTRT
12296 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
12297 || GET_CODE (x
) == ROTATERT
12298 || (TARGET_32BIT
&& GET_CODE (x
) == ZERO_EXTRACT
)))
12299 return CC_NOOVmode
;
12301 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
12304 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
12305 && GET_CODE (x
) == PLUS
12306 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
12309 if (GET_MODE (x
) == DImode
|| GET_MODE (y
) == DImode
)
12315 /* A DImode comparison against zero can be implemented by
12316 or'ing the two halves together. */
12317 if (y
== const0_rtx
)
12320 /* We can do an equality test in three Thumb instructions. */
12330 /* DImode unsigned comparisons can be implemented by cmp +
12331 cmpeq without a scratch register. Not worth doing in
12342 /* DImode signed and unsigned comparisons can be implemented
12343 by cmp + sbcs with a scratch register, but that does not
12344 set the Z flag - we must reverse GT/LE/GTU/LEU. */
12345 gcc_assert (op
!= EQ
&& op
!= NE
);
12349 gcc_unreachable ();
12353 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
12354 return GET_MODE (x
);
12359 /* X and Y are two things to compare using CODE. Emit the compare insn and
12360 return the rtx for register 0 in the proper mode. FP means this is a
12361 floating point compare: I don't think that it is needed on the arm. */
12363 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
, rtx scratch
)
12365 enum machine_mode mode
;
12367 int dimode_comparison
= GET_MODE (x
) == DImode
|| GET_MODE (y
) == DImode
;
12369 /* We might have X as a constant, Y as a register because of the predicates
12370 used for cmpdi. If so, force X to a register here. */
12371 if (dimode_comparison
&& !REG_P (x
))
12372 x
= force_reg (DImode
, x
);
12374 mode
= SELECT_CC_MODE (code
, x
, y
);
12375 cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
12377 if (dimode_comparison
12378 && mode
!= CC_CZmode
)
12382 /* To compare two non-zero values for equality, XOR them and
12383 then compare against zero. Not used for ARM mode; there
12384 CC_CZmode is cheaper. */
12385 if (mode
== CC_Zmode
&& y
!= const0_rtx
)
12387 gcc_assert (!reload_completed
);
12388 x
= expand_binop (DImode
, xor_optab
, x
, y
, NULL_RTX
, 0, OPTAB_WIDEN
);
12392 /* A scratch register is required. */
12393 if (reload_completed
)
12394 gcc_assert (scratch
!= NULL
&& GET_MODE (scratch
) == SImode
);
12396 scratch
= gen_rtx_SCRATCH (SImode
);
12398 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
12399 set
= gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
12400 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
12403 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
12408 /* Generate a sequence of insns that will generate the correct return
12409 address mask depending on the physical architecture that the program
12412 arm_gen_return_addr_mask (void)
12414 rtx reg
= gen_reg_rtx (Pmode
);
12416 emit_insn (gen_return_addr_mask (reg
));
12421 arm_reload_in_hi (rtx
*operands
)
12423 rtx ref
= operands
[1];
12425 HOST_WIDE_INT offset
= 0;
12427 if (GET_CODE (ref
) == SUBREG
)
12429 offset
= SUBREG_BYTE (ref
);
12430 ref
= SUBREG_REG (ref
);
12435 /* We have a pseudo which has been spilt onto the stack; there
12436 are two cases here: the first where there is a simple
12437 stack-slot replacement and a second where the stack-slot is
12438 out of range, or is used as a subreg. */
12439 if (reg_equiv_mem (REGNO (ref
)))
12441 ref
= reg_equiv_mem (REGNO (ref
));
12442 base
= find_replacement (&XEXP (ref
, 0));
12445 /* The slot is out of range, or was dressed up in a SUBREG. */
12446 base
= reg_equiv_address (REGNO (ref
));
12449 base
= find_replacement (&XEXP (ref
, 0));
12451 /* Handle the case where the address is too complex to be offset by 1. */
12452 if (GET_CODE (base
) == MINUS
12453 || (GET_CODE (base
) == PLUS
&& !CONST_INT_P (XEXP (base
, 1))))
12455 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
12457 emit_set_insn (base_plus
, base
);
12460 else if (GET_CODE (base
) == PLUS
)
12462 /* The addend must be CONST_INT, or we would have dealt with it above. */
12463 HOST_WIDE_INT hi
, lo
;
12465 offset
+= INTVAL (XEXP (base
, 1));
12466 base
= XEXP (base
, 0);
12468 /* Rework the address into a legal sequence of insns. */
12469 /* Valid range for lo is -4095 -> 4095 */
12472 : -((-offset
) & 0xfff));
12474 /* Corner case, if lo is the max offset then we would be out of range
12475 once we have added the additional 1 below, so bump the msb into the
12476 pre-loading insn(s). */
12480 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
12481 ^ (HOST_WIDE_INT
) 0x80000000)
12482 - (HOST_WIDE_INT
) 0x80000000);
12484 gcc_assert (hi
+ lo
== offset
);
12488 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
12490 /* Get the base address; addsi3 knows how to handle constants
12491 that require more than one insn. */
12492 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
12498 /* Operands[2] may overlap operands[0] (though it won't overlap
12499 operands[1]), that's why we asked for a DImode reg -- so we can
12500 use the bit that does not overlap. */
12501 if (REGNO (operands
[2]) == REGNO (operands
[0]))
12502 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
12504 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
12506 emit_insn (gen_zero_extendqisi2 (scratch
,
12507 gen_rtx_MEM (QImode
,
12508 plus_constant (Pmode
, base
,
12510 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
12511 gen_rtx_MEM (QImode
,
12512 plus_constant (Pmode
, base
,
12514 if (!BYTES_BIG_ENDIAN
)
12515 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
12516 gen_rtx_IOR (SImode
,
12519 gen_rtx_SUBREG (SImode
, operands
[0], 0),
12523 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
12524 gen_rtx_IOR (SImode
,
12525 gen_rtx_ASHIFT (SImode
, scratch
,
12527 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
12530 /* Handle storing a half-word to memory during reload by synthesizing as two
12531 byte stores. Take care not to clobber the input values until after we
12532 have moved them somewhere safe. This code assumes that if the DImode
12533 scratch in operands[2] overlaps either the input value or output address
12534 in some way, then that value must die in this insn (we absolutely need
12535 two scratch registers for some corner cases). */
12537 arm_reload_out_hi (rtx
*operands
)
12539 rtx ref
= operands
[0];
12540 rtx outval
= operands
[1];
12542 HOST_WIDE_INT offset
= 0;
12544 if (GET_CODE (ref
) == SUBREG
)
12546 offset
= SUBREG_BYTE (ref
);
12547 ref
= SUBREG_REG (ref
);
12552 /* We have a pseudo which has been spilt onto the stack; there
12553 are two cases here: the first where there is a simple
12554 stack-slot replacement and a second where the stack-slot is
12555 out of range, or is used as a subreg. */
12556 if (reg_equiv_mem (REGNO (ref
)))
12558 ref
= reg_equiv_mem (REGNO (ref
));
12559 base
= find_replacement (&XEXP (ref
, 0));
12562 /* The slot is out of range, or was dressed up in a SUBREG. */
12563 base
= reg_equiv_address (REGNO (ref
));
12566 base
= find_replacement (&XEXP (ref
, 0));
12568 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
12570 /* Handle the case where the address is too complex to be offset by 1. */
12571 if (GET_CODE (base
) == MINUS
12572 || (GET_CODE (base
) == PLUS
&& !CONST_INT_P (XEXP (base
, 1))))
12574 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
12576 /* Be careful not to destroy OUTVAL. */
12577 if (reg_overlap_mentioned_p (base_plus
, outval
))
12579 /* Updating base_plus might destroy outval, see if we can
12580 swap the scratch and base_plus. */
12581 if (!reg_overlap_mentioned_p (scratch
, outval
))
12584 scratch
= base_plus
;
12589 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
12591 /* Be conservative and copy OUTVAL into the scratch now,
12592 this should only be necessary if outval is a subreg
12593 of something larger than a word. */
12594 /* XXX Might this clobber base? I can't see how it can,
12595 since scratch is known to overlap with OUTVAL, and
12596 must be wider than a word. */
12597 emit_insn (gen_movhi (scratch_hi
, outval
));
12598 outval
= scratch_hi
;
12602 emit_set_insn (base_plus
, base
);
12605 else if (GET_CODE (base
) == PLUS
)
12607 /* The addend must be CONST_INT, or we would have dealt with it above. */
12608 HOST_WIDE_INT hi
, lo
;
12610 offset
+= INTVAL (XEXP (base
, 1));
12611 base
= XEXP (base
, 0);
12613 /* Rework the address into a legal sequence of insns. */
12614 /* Valid range for lo is -4095 -> 4095 */
12617 : -((-offset
) & 0xfff));
12619 /* Corner case, if lo is the max offset then we would be out of range
12620 once we have added the additional 1 below, so bump the msb into the
12621 pre-loading insn(s). */
12625 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
12626 ^ (HOST_WIDE_INT
) 0x80000000)
12627 - (HOST_WIDE_INT
) 0x80000000);
12629 gcc_assert (hi
+ lo
== offset
);
12633 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
12635 /* Be careful not to destroy OUTVAL. */
12636 if (reg_overlap_mentioned_p (base_plus
, outval
))
12638 /* Updating base_plus might destroy outval, see if we
12639 can swap the scratch and base_plus. */
12640 if (!reg_overlap_mentioned_p (scratch
, outval
))
12643 scratch
= base_plus
;
12648 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
12650 /* Be conservative and copy outval into scratch now,
12651 this should only be necessary if outval is a
12652 subreg of something larger than a word. */
12653 /* XXX Might this clobber base? I can't see how it
12654 can, since scratch is known to overlap with
12656 emit_insn (gen_movhi (scratch_hi
, outval
));
12657 outval
= scratch_hi
;
12661 /* Get the base address; addsi3 knows how to handle constants
12662 that require more than one insn. */
12663 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
12669 if (BYTES_BIG_ENDIAN
)
12671 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
12672 plus_constant (Pmode
, base
,
12674 gen_lowpart (QImode
, outval
)));
12675 emit_insn (gen_lshrsi3 (scratch
,
12676 gen_rtx_SUBREG (SImode
, outval
, 0),
12678 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (Pmode
, base
,
12680 gen_lowpart (QImode
, scratch
)));
12684 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (Pmode
, base
,
12686 gen_lowpart (QImode
, outval
)));
12687 emit_insn (gen_lshrsi3 (scratch
,
12688 gen_rtx_SUBREG (SImode
, outval
, 0),
12690 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
12691 plus_constant (Pmode
, base
,
12693 gen_lowpart (QImode
, scratch
)));
12697 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
12698 (padded to the size of a word) should be passed in a register. */
12701 arm_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
12703 if (TARGET_AAPCS_BASED
)
12704 return must_pass_in_stack_var_size (mode
, type
);
12706 return must_pass_in_stack_var_size_or_pad (mode
, type
);
12710 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
12711 Return true if an argument passed on the stack should be padded upwards,
12712 i.e. if the least-significant byte has useful data.
12713 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
12714 aggregate types are placed in the lowest memory address. */
12717 arm_pad_arg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
, const_tree type
)
12719 if (!TARGET_AAPCS_BASED
)
12720 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
12722 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
12729 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
12730 Return !BYTES_BIG_ENDIAN if the least significant byte of the
12731 register has useful data, and return the opposite if the most
12732 significant byte does. */
12735 arm_pad_reg_upward (enum machine_mode mode
,
12736 tree type
, int first ATTRIBUTE_UNUSED
)
12738 if (TARGET_AAPCS_BASED
&& BYTES_BIG_ENDIAN
)
12740 /* For AAPCS, small aggregates, small fixed-point types,
12741 and small complex types are always padded upwards. */
12744 if ((AGGREGATE_TYPE_P (type
)
12745 || TREE_CODE (type
) == COMPLEX_TYPE
12746 || FIXED_POINT_TYPE_P (type
))
12747 && int_size_in_bytes (type
) <= 4)
12752 if ((COMPLEX_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
))
12753 && GET_MODE_SIZE (mode
) <= 4)
12758 /* Otherwise, use default padding. */
12759 return !BYTES_BIG_ENDIAN
;
12762 /* Returns true iff OFFSET is valid for use in an LDRD/STRD instruction,
12763 assuming that the address in the base register is word aligned. */
12765 offset_ok_for_ldrd_strd (HOST_WIDE_INT offset
)
12767 HOST_WIDE_INT max_offset
;
12769 /* Offset must be a multiple of 4 in Thumb mode. */
12770 if (TARGET_THUMB2
&& ((offset
& 3) != 0))
12775 else if (TARGET_ARM
)
12780 return ((offset
<= max_offset
) && (offset
>= -max_offset
));
12783 /* Checks whether the operands are valid for use in an LDRD/STRD instruction.
12784 Assumes that RT, RT2, and RN are REG. This is guaranteed by the patterns.
12785 Assumes that the address in the base register RN is word aligned. Pattern
12786 guarantees that both memory accesses use the same base register,
12787 the offsets are constants within the range, and the gap between the offsets is 4.
12788 If preload complete then check that registers are legal. WBACK indicates whether
12789 address is updated. LOAD indicates whether memory access is load or store. */
12791 operands_ok_ldrd_strd (rtx rt
, rtx rt2
, rtx rn
, HOST_WIDE_INT offset
,
12792 bool wback
, bool load
)
12794 unsigned int t
, t2
, n
;
12796 if (!reload_completed
)
12799 if (!offset_ok_for_ldrd_strd (offset
))
12806 if ((TARGET_THUMB2
)
12807 && ((wback
&& (n
== t
|| n
== t2
))
12808 || (t
== SP_REGNUM
)
12809 || (t
== PC_REGNUM
)
12810 || (t2
== SP_REGNUM
)
12811 || (t2
== PC_REGNUM
)
12812 || (!load
&& (n
== PC_REGNUM
))
12813 || (load
&& (t
== t2
))
12814 /* Triggers Cortex-M3 LDRD errata. */
12815 || (!wback
&& load
&& fix_cm3_ldrd
&& (n
== t
))))
12819 && ((wback
&& (n
== t
|| n
== t2
))
12820 || (t2
== PC_REGNUM
)
12821 || (t
% 2 != 0) /* First destination register is not even. */
12823 /* PC can be used as base register (for offset addressing only),
12824 but it is depricated. */
12825 || (n
== PC_REGNUM
)))
12831 /* Helper for gen_operands_ldrd_strd. Returns true iff the memory
12832 operand ADDR is an immediate offset from the base register and is
12833 not volatile, in which case it sets BASE and OFFSET
12836 mem_ok_for_ldrd_strd (rtx addr
, rtx
*base
, rtx
*offset
)
12838 /* TODO: Handle more general memory operand patterns, such as
12839 PRE_DEC and PRE_INC. */
12841 /* Convert a subreg of mem into mem itself. */
12842 if (GET_CODE (addr
) == SUBREG
)
12843 addr
= alter_subreg (&addr
, true);
12845 gcc_assert (MEM_P (addr
));
12847 /* Don't modify volatile memory accesses. */
12848 if (MEM_VOLATILE_P (addr
))
12851 *offset
= const0_rtx
;
12853 addr
= XEXP (addr
, 0);
12859 else if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == MINUS
)
12861 *base
= XEXP (addr
, 0);
12862 *offset
= XEXP (addr
, 1);
12863 return (REG_P (*base
) && CONST_INT_P (*offset
));
12869 #define SWAP_RTX(x,y) do { rtx tmp = x; x = y; y = tmp; } while (0)
12871 /* Called from a peephole2 to replace two word-size accesses with a
12872 single LDRD/STRD instruction. Returns true iff we can generate a
12873 new instruction sequence. That is, both accesses use the same base
12874 register and the gap between constant offsets is 4. This function
12875 may reorder its operands to match ldrd/strd RTL templates.
12876 OPERANDS are the operands found by the peephole matcher;
12877 OPERANDS[0,1] are register operands, and OPERANDS[2,3] are the
12878 corresponding memory operands. LOAD indicaates whether the access
12879 is load or store. CONST_STORE indicates a store of constant
12880 integer values held in OPERANDS[4,5] and assumes that the pattern
12881 is of length 4 insn, for the purpose of checking dead registers.
12882 COMMUTE indicates that register operands may be reordered. */
12884 gen_operands_ldrd_strd (rtx
*operands
, bool load
,
12885 bool const_store
, bool commute
)
12888 HOST_WIDE_INT offsets
[2], offset
;
12889 rtx base
= NULL_RTX
;
12890 rtx cur_base
, cur_offset
, tmp
;
12892 HARD_REG_SET regset
;
12894 gcc_assert (!const_store
|| !load
);
12895 /* Check that the memory references are immediate offsets from the
12896 same base register. Extract the base register, the destination
12897 registers, and the corresponding memory offsets. */
12898 for (i
= 0; i
< nops
; i
++)
12900 if (!mem_ok_for_ldrd_strd (operands
[nops
+i
], &cur_base
, &cur_offset
))
12905 else if (REGNO (base
) != REGNO (cur_base
))
12908 offsets
[i
] = INTVAL (cur_offset
);
12909 if (GET_CODE (operands
[i
]) == SUBREG
)
12911 tmp
= SUBREG_REG (operands
[i
]);
12912 gcc_assert (GET_MODE (operands
[i
]) == GET_MODE (tmp
));
12917 /* Make sure there is no dependency between the individual loads. */
12918 if (load
&& REGNO (operands
[0]) == REGNO (base
))
12919 return false; /* RAW */
12921 if (load
&& REGNO (operands
[0]) == REGNO (operands
[1]))
12922 return false; /* WAW */
12924 /* If the same input register is used in both stores
12925 when storing different constants, try to find a free register.
12926 For example, the code
12931 can be transformed into
12934 in Thumb mode assuming that r1 is free. */
12936 && REGNO (operands
[0]) == REGNO (operands
[1])
12937 && INTVAL (operands
[4]) != INTVAL (operands
[5]))
12941 CLEAR_HARD_REG_SET (regset
);
12942 tmp
= peep2_find_free_register (0, 4, "r", SImode
, ®set
);
12943 if (tmp
== NULL_RTX
)
12946 /* Use the new register in the first load to ensure that
12947 if the original input register is not dead after peephole,
12948 then it will have the correct constant value. */
12951 else if (TARGET_ARM
)
12954 int regno
= REGNO (operands
[0]);
12955 if (!peep2_reg_dead_p (4, operands
[0]))
12957 /* When the input register is even and is not dead after the
12958 pattern, it has to hold the second constant but we cannot
12959 form a legal STRD in ARM mode with this register as the second
12961 if (regno
% 2 == 0)
12964 /* Is regno-1 free? */
12965 SET_HARD_REG_SET (regset
);
12966 CLEAR_HARD_REG_BIT(regset
, regno
- 1);
12967 tmp
= peep2_find_free_register (0, 4, "r", SImode
, ®set
);
12968 if (tmp
== NULL_RTX
)
12975 /* Find a DImode register. */
12976 CLEAR_HARD_REG_SET (regset
);
12977 tmp
= peep2_find_free_register (0, 4, "r", DImode
, ®set
);
12978 if (tmp
!= NULL_RTX
)
12980 operands
[0] = simplify_gen_subreg (SImode
, tmp
, DImode
, 0);
12981 operands
[1] = simplify_gen_subreg (SImode
, tmp
, DImode
, 4);
12985 /* Can we use the input register to form a DI register? */
12986 SET_HARD_REG_SET (regset
);
12987 CLEAR_HARD_REG_BIT(regset
,
12988 regno
% 2 == 0 ? regno
+ 1 : regno
- 1);
12989 tmp
= peep2_find_free_register (0, 4, "r", SImode
, ®set
);
12990 if (tmp
== NULL_RTX
)
12992 operands
[regno
% 2 == 1 ? 0 : 1] = tmp
;
12996 gcc_assert (operands
[0] != NULL_RTX
);
12997 gcc_assert (operands
[1] != NULL_RTX
);
12998 gcc_assert (REGNO (operands
[0]) % 2 == 0);
12999 gcc_assert (REGNO (operands
[1]) == REGNO (operands
[0]) + 1);
13003 /* Make sure the instructions are ordered with lower memory access first. */
13004 if (offsets
[0] > offsets
[1])
13006 gap
= offsets
[0] - offsets
[1];
13007 offset
= offsets
[1];
13009 /* Swap the instructions such that lower memory is accessed first. */
13010 SWAP_RTX (operands
[0], operands
[1]);
13011 SWAP_RTX (operands
[2], operands
[3]);
13013 SWAP_RTX (operands
[4], operands
[5]);
13017 gap
= offsets
[1] - offsets
[0];
13018 offset
= offsets
[0];
13021 /* Make sure accesses are to consecutive memory locations. */
13025 /* Make sure we generate legal instructions. */
13026 if (operands_ok_ldrd_strd (operands
[0], operands
[1], base
, offset
,
13030 /* In Thumb state, where registers are almost unconstrained, there
13031 is little hope to fix it. */
13035 if (load
&& commute
)
13037 /* Try reordering registers. */
13038 SWAP_RTX (operands
[0], operands
[1]);
13039 if (operands_ok_ldrd_strd (operands
[0], operands
[1], base
, offset
,
13046 /* If input registers are dead after this pattern, they can be
13047 reordered or replaced by other registers that are free in the
13048 current pattern. */
13049 if (!peep2_reg_dead_p (4, operands
[0])
13050 || !peep2_reg_dead_p (4, operands
[1]))
13053 /* Try to reorder the input registers. */
13054 /* For example, the code
13059 can be transformed into
13064 if (operands_ok_ldrd_strd (operands
[1], operands
[0], base
, offset
,
13067 SWAP_RTX (operands
[0], operands
[1]);
13071 /* Try to find a free DI register. */
13072 CLEAR_HARD_REG_SET (regset
);
13073 add_to_hard_reg_set (®set
, SImode
, REGNO (operands
[0]));
13074 add_to_hard_reg_set (®set
, SImode
, REGNO (operands
[1]));
13077 tmp
= peep2_find_free_register (0, 4, "r", DImode
, ®set
);
13078 if (tmp
== NULL_RTX
)
13081 /* DREG must be an even-numbered register in DImode.
13082 Split it into SI registers. */
13083 operands
[0] = simplify_gen_subreg (SImode
, tmp
, DImode
, 0);
13084 operands
[1] = simplify_gen_subreg (SImode
, tmp
, DImode
, 4);
13085 gcc_assert (operands
[0] != NULL_RTX
);
13086 gcc_assert (operands
[1] != NULL_RTX
);
13087 gcc_assert (REGNO (operands
[0]) % 2 == 0);
13088 gcc_assert (REGNO (operands
[0]) + 1 == REGNO (operands
[1]));
13090 return (operands_ok_ldrd_strd (operands
[0], operands
[1],
13103 /* Print a symbolic form of X to the debug file, F. */
13105 arm_print_value (FILE *f
, rtx x
)
13107 switch (GET_CODE (x
))
13110 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
13114 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
13122 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
13124 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
13125 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
13133 fprintf (f
, "\"%s\"", XSTR (x
, 0));
13137 fprintf (f
, "`%s'", XSTR (x
, 0));
13141 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
13145 arm_print_value (f
, XEXP (x
, 0));
13149 arm_print_value (f
, XEXP (x
, 0));
13151 arm_print_value (f
, XEXP (x
, 1));
13159 fprintf (f
, "????");
13164 /* Routines for manipulation of the constant pool. */
13166 /* Arm instructions cannot load a large constant directly into a
13167 register; they have to come from a pc relative load. The constant
13168 must therefore be placed in the addressable range of the pc
13169 relative load. Depending on the precise pc relative load
13170 instruction the range is somewhere between 256 bytes and 4k. This
13171 means that we often have to dump a constant inside a function, and
13172 generate code to branch around it.
13174 It is important to minimize this, since the branches will slow
13175 things down and make the code larger.
13177 Normally we can hide the table after an existing unconditional
13178 branch so that there is no interruption of the flow, but in the
13179 worst case the code looks like this:
13197 We fix this by performing a scan after scheduling, which notices
13198 which instructions need to have their operands fetched from the
13199 constant table and builds the table.
13201 The algorithm starts by building a table of all the constants that
13202 need fixing up and all the natural barriers in the function (places
13203 where a constant table can be dropped without breaking the flow).
13204 For each fixup we note how far the pc-relative replacement will be
13205 able to reach and the offset of the instruction into the function.
13207 Having built the table we then group the fixes together to form
13208 tables that are as large as possible (subject to addressing
13209 constraints) and emit each table of constants after the last
13210 barrier that is within range of all the instructions in the group.
13211 If a group does not contain a barrier, then we forcibly create one
13212 by inserting a jump instruction into the flow. Once the table has
13213 been inserted, the insns are then modified to reference the
13214 relevant entry in the pool.
13216 Possible enhancements to the algorithm (not implemented) are:
13218 1) For some processors and object formats, there may be benefit in
13219 aligning the pools to the start of cache lines; this alignment
13220 would need to be taken into account when calculating addressability
13223 /* These typedefs are located at the start of this file, so that
13224 they can be used in the prototypes there. This comment is to
13225 remind readers of that fact so that the following structures
13226 can be understood more easily.
13228 typedef struct minipool_node Mnode;
13229 typedef struct minipool_fixup Mfix; */
13231 struct minipool_node
13233 /* Doubly linked chain of entries. */
13236 /* The maximum offset into the code that this entry can be placed. While
13237 pushing fixes for forward references, all entries are sorted in order
13238 of increasing max_address. */
13239 HOST_WIDE_INT max_address
;
13240 /* Similarly for an entry inserted for a backwards ref. */
13241 HOST_WIDE_INT min_address
;
13242 /* The number of fixes referencing this entry. This can become zero
13243 if we "unpush" an entry. In this case we ignore the entry when we
13244 come to emit the code. */
13246 /* The offset from the start of the minipool. */
13247 HOST_WIDE_INT offset
;
13248 /* The value in table. */
13250 /* The mode of value. */
13251 enum machine_mode mode
;
13252 /* The size of the value. With iWMMXt enabled
13253 sizes > 4 also imply an alignment of 8-bytes. */
13257 struct minipool_fixup
13261 HOST_WIDE_INT address
;
13263 enum machine_mode mode
;
13267 HOST_WIDE_INT forwards
;
13268 HOST_WIDE_INT backwards
;
13271 /* Fixes less than a word need padding out to a word boundary. */
13272 #define MINIPOOL_FIX_SIZE(mode) \
13273 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
13275 static Mnode
* minipool_vector_head
;
13276 static Mnode
* minipool_vector_tail
;
13277 static rtx minipool_vector_label
;
13278 static int minipool_pad
;
13280 /* The linked list of all minipool fixes required for this function. */
13281 Mfix
* minipool_fix_head
;
13282 Mfix
* minipool_fix_tail
;
13283 /* The fix entry for the current minipool, once it has been placed. */
13284 Mfix
* minipool_barrier
;
13286 /* Determines if INSN is the start of a jump table. Returns the end
13287 of the TABLE or NULL_RTX. */
13289 is_jump_table (rtx insn
)
13293 if (jump_to_label_p (insn
)
13294 && ((table
= next_active_insn (JUMP_LABEL (insn
)))
13295 == next_active_insn (insn
))
13297 && JUMP_TABLE_DATA_P (table
))
13303 #ifndef JUMP_TABLES_IN_TEXT_SECTION
13304 #define JUMP_TABLES_IN_TEXT_SECTION 0
13307 static HOST_WIDE_INT
13308 get_jump_table_size (rtx insn
)
13310 /* ADDR_VECs only take room if read-only data does into the text
13312 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
13314 rtx body
= PATTERN (insn
);
13315 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
13316 HOST_WIDE_INT size
;
13317 HOST_WIDE_INT modesize
;
13319 modesize
= GET_MODE_SIZE (GET_MODE (body
));
13320 size
= modesize
* XVECLEN (body
, elt
);
13324 /* Round up size of TBB table to a halfword boundary. */
13325 size
= (size
+ 1) & ~(HOST_WIDE_INT
)1;
13328 /* No padding necessary for TBH. */
13331 /* Add two bytes for alignment on Thumb. */
13336 gcc_unreachable ();
13344 /* Return the maximum amount of padding that will be inserted before
13347 static HOST_WIDE_INT
13348 get_label_padding (rtx label
)
13350 HOST_WIDE_INT align
, min_insn_size
;
13352 align
= 1 << label_to_alignment (label
);
13353 min_insn_size
= TARGET_THUMB
? 2 : 4;
13354 return align
> min_insn_size
? align
- min_insn_size
: 0;
13357 /* Move a minipool fix MP from its current location to before MAX_MP.
13358 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
13359 constraints may need updating. */
13361 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
13362 HOST_WIDE_INT max_address
)
13364 /* The code below assumes these are different. */
13365 gcc_assert (mp
!= max_mp
);
13367 if (max_mp
== NULL
)
13369 if (max_address
< mp
->max_address
)
13370 mp
->max_address
= max_address
;
13374 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
13375 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
13377 mp
->max_address
= max_address
;
13379 /* Unlink MP from its current position. Since max_mp is non-null,
13380 mp->prev must be non-null. */
13381 mp
->prev
->next
= mp
->next
;
13382 if (mp
->next
!= NULL
)
13383 mp
->next
->prev
= mp
->prev
;
13385 minipool_vector_tail
= mp
->prev
;
13387 /* Re-insert it before MAX_MP. */
13389 mp
->prev
= max_mp
->prev
;
13392 if (mp
->prev
!= NULL
)
13393 mp
->prev
->next
= mp
;
13395 minipool_vector_head
= mp
;
13398 /* Save the new entry. */
13401 /* Scan over the preceding entries and adjust their addresses as
13403 while (mp
->prev
!= NULL
13404 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
13406 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
13413 /* Add a constant to the minipool for a forward reference. Returns the
13414 node added or NULL if the constant will not fit in this pool. */
13416 add_minipool_forward_ref (Mfix
*fix
)
13418 /* If set, max_mp is the first pool_entry that has a lower
13419 constraint than the one we are trying to add. */
13420 Mnode
* max_mp
= NULL
;
13421 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
13424 /* If the minipool starts before the end of FIX->INSN then this FIX
13425 can not be placed into the current pool. Furthermore, adding the
13426 new constant pool entry may cause the pool to start FIX_SIZE bytes
13428 if (minipool_vector_head
&&
13429 (fix
->address
+ get_attr_length (fix
->insn
)
13430 >= minipool_vector_head
->max_address
- fix
->fix_size
))
13433 /* Scan the pool to see if a constant with the same value has
13434 already been added. While we are doing this, also note the
13435 location where we must insert the constant if it doesn't already
13437 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
13439 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
13440 && fix
->mode
== mp
->mode
13441 && (!LABEL_P (fix
->value
)
13442 || (CODE_LABEL_NUMBER (fix
->value
)
13443 == CODE_LABEL_NUMBER (mp
->value
)))
13444 && rtx_equal_p (fix
->value
, mp
->value
))
13446 /* More than one fix references this entry. */
13448 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
13451 /* Note the insertion point if necessary. */
13453 && mp
->max_address
> max_address
)
13456 /* If we are inserting an 8-bytes aligned quantity and
13457 we have not already found an insertion point, then
13458 make sure that all such 8-byte aligned quantities are
13459 placed at the start of the pool. */
13460 if (ARM_DOUBLEWORD_ALIGN
13462 && fix
->fix_size
>= 8
13463 && mp
->fix_size
< 8)
13466 max_address
= mp
->max_address
;
13470 /* The value is not currently in the minipool, so we need to create
13471 a new entry for it. If MAX_MP is NULL, the entry will be put on
13472 the end of the list since the placement is less constrained than
13473 any existing entry. Otherwise, we insert the new fix before
13474 MAX_MP and, if necessary, adjust the constraints on the other
13477 mp
->fix_size
= fix
->fix_size
;
13478 mp
->mode
= fix
->mode
;
13479 mp
->value
= fix
->value
;
13481 /* Not yet required for a backwards ref. */
13482 mp
->min_address
= -65536;
13484 if (max_mp
== NULL
)
13486 mp
->max_address
= max_address
;
13488 mp
->prev
= minipool_vector_tail
;
13490 if (mp
->prev
== NULL
)
13492 minipool_vector_head
= mp
;
13493 minipool_vector_label
= gen_label_rtx ();
13496 mp
->prev
->next
= mp
;
13498 minipool_vector_tail
= mp
;
13502 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
13503 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
13505 mp
->max_address
= max_address
;
13508 mp
->prev
= max_mp
->prev
;
13510 if (mp
->prev
!= NULL
)
13511 mp
->prev
->next
= mp
;
13513 minipool_vector_head
= mp
;
13516 /* Save the new entry. */
13519 /* Scan over the preceding entries and adjust their addresses as
13521 while (mp
->prev
!= NULL
13522 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
13524 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
13532 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
13533 HOST_WIDE_INT min_address
)
13535 HOST_WIDE_INT offset
;
13537 /* The code below assumes these are different. */
13538 gcc_assert (mp
!= min_mp
);
13540 if (min_mp
== NULL
)
13542 if (min_address
> mp
->min_address
)
13543 mp
->min_address
= min_address
;
13547 /* We will adjust this below if it is too loose. */
13548 mp
->min_address
= min_address
;
13550 /* Unlink MP from its current position. Since min_mp is non-null,
13551 mp->next must be non-null. */
13552 mp
->next
->prev
= mp
->prev
;
13553 if (mp
->prev
!= NULL
)
13554 mp
->prev
->next
= mp
->next
;
13556 minipool_vector_head
= mp
->next
;
13558 /* Reinsert it after MIN_MP. */
13560 mp
->next
= min_mp
->next
;
13562 if (mp
->next
!= NULL
)
13563 mp
->next
->prev
= mp
;
13565 minipool_vector_tail
= mp
;
13571 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
13573 mp
->offset
= offset
;
13574 if (mp
->refcount
> 0)
13575 offset
+= mp
->fix_size
;
13577 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
13578 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
13584 /* Add a constant to the minipool for a backward reference. Returns the
13585 node added or NULL if the constant will not fit in this pool.
13587 Note that the code for insertion for a backwards reference can be
13588 somewhat confusing because the calculated offsets for each fix do
13589 not take into account the size of the pool (which is still under
13592 add_minipool_backward_ref (Mfix
*fix
)
13594 /* If set, min_mp is the last pool_entry that has a lower constraint
13595 than the one we are trying to add. */
13596 Mnode
*min_mp
= NULL
;
13597 /* This can be negative, since it is only a constraint. */
13598 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
13601 /* If we can't reach the current pool from this insn, or if we can't
13602 insert this entry at the end of the pool without pushing other
13603 fixes out of range, then we don't try. This ensures that we
13604 can't fail later on. */
13605 if (min_address
>= minipool_barrier
->address
13606 || (minipool_vector_tail
->min_address
+ fix
->fix_size
13607 >= minipool_barrier
->address
))
13610 /* Scan the pool to see if a constant with the same value has
13611 already been added. While we are doing this, also note the
13612 location where we must insert the constant if it doesn't already
13614 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
13616 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
13617 && fix
->mode
== mp
->mode
13618 && (!LABEL_P (fix
->value
)
13619 || (CODE_LABEL_NUMBER (fix
->value
)
13620 == CODE_LABEL_NUMBER (mp
->value
)))
13621 && rtx_equal_p (fix
->value
, mp
->value
)
13622 /* Check that there is enough slack to move this entry to the
13623 end of the table (this is conservative). */
13624 && (mp
->max_address
13625 > (minipool_barrier
->address
13626 + minipool_vector_tail
->offset
13627 + minipool_vector_tail
->fix_size
)))
13630 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
13633 if (min_mp
!= NULL
)
13634 mp
->min_address
+= fix
->fix_size
;
13637 /* Note the insertion point if necessary. */
13638 if (mp
->min_address
< min_address
)
13640 /* For now, we do not allow the insertion of 8-byte alignment
13641 requiring nodes anywhere but at the start of the pool. */
13642 if (ARM_DOUBLEWORD_ALIGN
13643 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
13648 else if (mp
->max_address
13649 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
13651 /* Inserting before this entry would push the fix beyond
13652 its maximum address (which can happen if we have
13653 re-located a forwards fix); force the new fix to come
13655 if (ARM_DOUBLEWORD_ALIGN
13656 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
13661 min_address
= mp
->min_address
+ fix
->fix_size
;
13664 /* Do not insert a non-8-byte aligned quantity before 8-byte
13665 aligned quantities. */
13666 else if (ARM_DOUBLEWORD_ALIGN
13667 && fix
->fix_size
< 8
13668 && mp
->fix_size
>= 8)
13671 min_address
= mp
->min_address
+ fix
->fix_size
;
13676 /* We need to create a new entry. */
13678 mp
->fix_size
= fix
->fix_size
;
13679 mp
->mode
= fix
->mode
;
13680 mp
->value
= fix
->value
;
13682 mp
->max_address
= minipool_barrier
->address
+ 65536;
13684 mp
->min_address
= min_address
;
13686 if (min_mp
== NULL
)
13689 mp
->next
= minipool_vector_head
;
13691 if (mp
->next
== NULL
)
13693 minipool_vector_tail
= mp
;
13694 minipool_vector_label
= gen_label_rtx ();
13697 mp
->next
->prev
= mp
;
13699 minipool_vector_head
= mp
;
13703 mp
->next
= min_mp
->next
;
13707 if (mp
->next
!= NULL
)
13708 mp
->next
->prev
= mp
;
13710 minipool_vector_tail
= mp
;
13713 /* Save the new entry. */
13721 /* Scan over the following entries and adjust their offsets. */
13722 while (mp
->next
!= NULL
)
13724 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
13725 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
13728 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
13730 mp
->next
->offset
= mp
->offset
;
13739 assign_minipool_offsets (Mfix
*barrier
)
13741 HOST_WIDE_INT offset
= 0;
13744 minipool_barrier
= barrier
;
13746 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
13748 mp
->offset
= offset
;
13750 if (mp
->refcount
> 0)
13751 offset
+= mp
->fix_size
;
13755 /* Output the literal table */
13757 dump_minipool (rtx scan
)
13763 if (ARM_DOUBLEWORD_ALIGN
)
13764 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
13765 if (mp
->refcount
> 0 && mp
->fix_size
>= 8)
13772 fprintf (dump_file
,
13773 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
13774 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
13776 scan
= emit_label_after (gen_label_rtx (), scan
);
13777 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
13778 scan
= emit_label_after (minipool_vector_label
, scan
);
13780 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
13782 if (mp
->refcount
> 0)
13786 fprintf (dump_file
,
13787 ";; Offset %u, min %ld, max %ld ",
13788 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
13789 (unsigned long) mp
->max_address
);
13790 arm_print_value (dump_file
, mp
->value
);
13791 fputc ('\n', dump_file
);
13794 switch (mp
->fix_size
)
13796 #ifdef HAVE_consttable_1
13798 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
13802 #ifdef HAVE_consttable_2
13804 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
13808 #ifdef HAVE_consttable_4
13810 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
13814 #ifdef HAVE_consttable_8
13816 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
13820 #ifdef HAVE_consttable_16
13822 scan
= emit_insn_after (gen_consttable_16 (mp
->value
), scan
);
13827 gcc_unreachable ();
13835 minipool_vector_head
= minipool_vector_tail
= NULL
;
13836 scan
= emit_insn_after (gen_consttable_end (), scan
);
13837 scan
= emit_barrier_after (scan
);
13840 /* Return the cost of forcibly inserting a barrier after INSN. */
13842 arm_barrier_cost (rtx insn
)
13844 /* Basing the location of the pool on the loop depth is preferable,
13845 but at the moment, the basic block information seems to be
13846 corrupt by this stage of the compilation. */
13847 int base_cost
= 50;
13848 rtx next
= next_nonnote_insn (insn
);
13850 if (next
!= NULL
&& LABEL_P (next
))
13853 switch (GET_CODE (insn
))
13856 /* It will always be better to place the table before the label, rather
13865 return base_cost
- 10;
13868 return base_cost
+ 10;
13872 /* Find the best place in the insn stream in the range
13873 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
13874 Create the barrier by inserting a jump and add a new fix entry for
13877 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
13879 HOST_WIDE_INT count
= 0;
13881 rtx from
= fix
->insn
;
13882 /* The instruction after which we will insert the jump. */
13883 rtx selected
= NULL
;
13885 /* The address at which the jump instruction will be placed. */
13886 HOST_WIDE_INT selected_address
;
13888 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
13889 rtx label
= gen_label_rtx ();
13891 selected_cost
= arm_barrier_cost (from
);
13892 selected_address
= fix
->address
;
13894 while (from
&& count
< max_count
)
13899 /* This code shouldn't have been called if there was a natural barrier
13901 gcc_assert (!BARRIER_P (from
));
13903 /* Count the length of this insn. This must stay in sync with the
13904 code that pushes minipool fixes. */
13905 if (LABEL_P (from
))
13906 count
+= get_label_padding (from
);
13908 count
+= get_attr_length (from
);
13910 /* If there is a jump table, add its length. */
13911 tmp
= is_jump_table (from
);
13914 count
+= get_jump_table_size (tmp
);
13916 /* Jump tables aren't in a basic block, so base the cost on
13917 the dispatch insn. If we select this location, we will
13918 still put the pool after the table. */
13919 new_cost
= arm_barrier_cost (from
);
13921 if (count
< max_count
13922 && (!selected
|| new_cost
<= selected_cost
))
13925 selected_cost
= new_cost
;
13926 selected_address
= fix
->address
+ count
;
13929 /* Continue after the dispatch table. */
13930 from
= NEXT_INSN (tmp
);
13934 new_cost
= arm_barrier_cost (from
);
13936 if (count
< max_count
13937 && (!selected
|| new_cost
<= selected_cost
))
13940 selected_cost
= new_cost
;
13941 selected_address
= fix
->address
+ count
;
13944 from
= NEXT_INSN (from
);
13947 /* Make sure that we found a place to insert the jump. */
13948 gcc_assert (selected
);
13950 /* Make sure we do not split a call and its corresponding
13951 CALL_ARG_LOCATION note. */
13952 if (CALL_P (selected
))
13954 rtx next
= NEXT_INSN (selected
);
13955 if (next
&& NOTE_P (next
)
13956 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
13960 /* Create a new JUMP_INSN that branches around a barrier. */
13961 from
= emit_jump_insn_after (gen_jump (label
), selected
);
13962 JUMP_LABEL (from
) = label
;
13963 barrier
= emit_barrier_after (from
);
13964 emit_label_after (label
, barrier
);
13966 /* Create a minipool barrier entry for the new barrier. */
13967 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
13968 new_fix
->insn
= barrier
;
13969 new_fix
->address
= selected_address
;
13970 new_fix
->next
= fix
->next
;
13971 fix
->next
= new_fix
;
13976 /* Record that there is a natural barrier in the insn stream at
13979 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
13981 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
13984 fix
->address
= address
;
13987 if (minipool_fix_head
!= NULL
)
13988 minipool_fix_tail
->next
= fix
;
13990 minipool_fix_head
= fix
;
13992 minipool_fix_tail
= fix
;
13995 /* Record INSN, which will need fixing up to load a value from the
13996 minipool. ADDRESS is the offset of the insn since the start of the
13997 function; LOC is a pointer to the part of the insn which requires
13998 fixing; VALUE is the constant that must be loaded, which is of type
14001 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
14002 enum machine_mode mode
, rtx value
)
14004 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
14007 fix
->address
= address
;
14010 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
14011 fix
->value
= value
;
14012 fix
->forwards
= get_attr_pool_range (insn
);
14013 fix
->backwards
= get_attr_neg_pool_range (insn
);
14014 fix
->minipool
= NULL
;
14016 /* If an insn doesn't have a range defined for it, then it isn't
14017 expecting to be reworked by this code. Better to stop now than
14018 to generate duff assembly code. */
14019 gcc_assert (fix
->forwards
|| fix
->backwards
);
14021 /* If an entry requires 8-byte alignment then assume all constant pools
14022 require 4 bytes of padding. Trying to do this later on a per-pool
14023 basis is awkward because existing pool entries have to be modified. */
14024 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
>= 8)
14029 fprintf (dump_file
,
14030 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
14031 GET_MODE_NAME (mode
),
14032 INSN_UID (insn
), (unsigned long) address
,
14033 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
14034 arm_print_value (dump_file
, fix
->value
);
14035 fprintf (dump_file
, "\n");
14038 /* Add it to the chain of fixes. */
14041 if (minipool_fix_head
!= NULL
)
14042 minipool_fix_tail
->next
= fix
;
14044 minipool_fix_head
= fix
;
14046 minipool_fix_tail
= fix
;
14049 /* Return the cost of synthesizing a 64-bit constant VAL inline.
14050 Returns the number of insns needed, or 99 if we don't know how to
14053 arm_const_double_inline_cost (rtx val
)
14055 rtx lowpart
, highpart
;
14056 enum machine_mode mode
;
14058 mode
= GET_MODE (val
);
14060 if (mode
== VOIDmode
)
14063 gcc_assert (GET_MODE_SIZE (mode
) == 8);
14065 lowpart
= gen_lowpart (SImode
, val
);
14066 highpart
= gen_highpart_mode (SImode
, mode
, val
);
14068 gcc_assert (CONST_INT_P (lowpart
));
14069 gcc_assert (CONST_INT_P (highpart
));
14071 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
14072 NULL_RTX
, NULL_RTX
, 0, 0)
14073 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
14074 NULL_RTX
, NULL_RTX
, 0, 0));
14077 /* Return true if it is worthwhile to split a 64-bit constant into two
14078 32-bit operations. This is the case if optimizing for size, or
14079 if we have load delay slots, or if one 32-bit part can be done with
14080 a single data operation. */
14082 arm_const_double_by_parts (rtx val
)
14084 enum machine_mode mode
= GET_MODE (val
);
14087 if (optimize_size
|| arm_ld_sched
)
14090 if (mode
== VOIDmode
)
14093 part
= gen_highpart_mode (SImode
, mode
, val
);
14095 gcc_assert (CONST_INT_P (part
));
14097 if (const_ok_for_arm (INTVAL (part
))
14098 || const_ok_for_arm (~INTVAL (part
)))
14101 part
= gen_lowpart (SImode
, val
);
14103 gcc_assert (CONST_INT_P (part
));
14105 if (const_ok_for_arm (INTVAL (part
))
14106 || const_ok_for_arm (~INTVAL (part
)))
14112 /* Return true if it is possible to inline both the high and low parts
14113 of a 64-bit constant into 32-bit data processing instructions. */
14115 arm_const_double_by_immediates (rtx val
)
14117 enum machine_mode mode
= GET_MODE (val
);
14120 if (mode
== VOIDmode
)
14123 part
= gen_highpart_mode (SImode
, mode
, val
);
14125 gcc_assert (CONST_INT_P (part
));
14127 if (!const_ok_for_arm (INTVAL (part
)))
14130 part
= gen_lowpart (SImode
, val
);
14132 gcc_assert (CONST_INT_P (part
));
14134 if (!const_ok_for_arm (INTVAL (part
)))
14140 /* Scan INSN and note any of its operands that need fixing.
14141 If DO_PUSHES is false we do not actually push any of the fixups
14144 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
14148 extract_insn (insn
);
14150 if (!constrain_operands (1))
14151 fatal_insn_not_found (insn
);
14153 if (recog_data
.n_alternatives
== 0)
14156 /* Fill in recog_op_alt with information about the constraints of
14158 preprocess_constraints ();
14160 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
14162 /* Things we need to fix can only occur in inputs. */
14163 if (recog_data
.operand_type
[opno
] != OP_IN
)
14166 /* If this alternative is a memory reference, then any mention
14167 of constants in this alternative is really to fool reload
14168 into allowing us to accept one there. We need to fix them up
14169 now so that we output the right code. */
14170 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
14172 rtx op
= recog_data
.operand
[opno
];
14174 if (CONSTANT_P (op
))
14177 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
14178 recog_data
.operand_mode
[opno
], op
);
14180 else if (MEM_P (op
)
14181 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
14182 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
14186 rtx cop
= avoid_constant_pool_reference (op
);
14188 /* Casting the address of something to a mode narrower
14189 than a word can cause avoid_constant_pool_reference()
14190 to return the pool reference itself. That's no good to
14191 us here. Lets just hope that we can use the
14192 constant pool value directly. */
14194 cop
= get_pool_constant (XEXP (op
, 0));
14196 push_minipool_fix (insn
, address
,
14197 recog_data
.operand_loc
[opno
],
14198 recog_data
.operand_mode
[opno
], cop
);
14208 /* Rewrite move insn into subtract of 0 if the condition codes will
14209 be useful in next conditional jump insn. */
14212 thumb1_reorg (void)
14218 rtx set
, dest
, src
;
14220 rtx prev
, insn
= BB_END (bb
);
14222 while (insn
!= BB_HEAD (bb
) && DEBUG_INSN_P (insn
))
14223 insn
= PREV_INSN (insn
);
14225 /* Find the last cbranchsi4_insn in basic block BB. */
14226 if (INSN_CODE (insn
) != CODE_FOR_cbranchsi4_insn
)
14229 /* Find the first non-note insn before INSN in basic block BB. */
14230 gcc_assert (insn
!= BB_HEAD (bb
));
14231 prev
= PREV_INSN (insn
);
14232 while (prev
!= BB_HEAD (bb
) && (NOTE_P (prev
) || DEBUG_INSN_P (prev
)))
14233 prev
= PREV_INSN (prev
);
14235 set
= single_set (prev
);
14239 dest
= SET_DEST (set
);
14240 src
= SET_SRC (set
);
14241 if (!low_register_operand (dest
, SImode
)
14242 || !low_register_operand (src
, SImode
))
14245 pat
= PATTERN (insn
);
14246 op0
= XEXP (XEXP (SET_SRC (pat
), 0), 0);
14247 /* Rewrite move into subtract of 0 if its operand is compared with ZERO
14248 in INSN. Don't need to check dest since cprop_hardreg pass propagates
14250 if (REGNO (op0
) == REGNO (src
))
14252 dest
= copy_rtx (dest
);
14253 src
= copy_rtx (src
);
14254 src
= gen_rtx_MINUS (SImode
, src
, const0_rtx
);
14255 PATTERN (prev
) = gen_rtx_SET (VOIDmode
, dest
, src
);
14256 INSN_CODE (prev
) = -1;
14257 /* Set test register in INSN to dest. */
14258 XEXP (XEXP (SET_SRC (pat
), 0), 0) = copy_rtx (dest
);
14259 INSN_CODE (insn
) = -1;
14264 /* Convert instructions to their cc-clobbering variant if possible, since
14265 that allows us to use smaller encodings. */
14268 thumb2_reorg (void)
14273 INIT_REG_SET (&live
);
14275 /* We are freeing block_for_insn in the toplev to keep compatibility
14276 with old MDEP_REORGS that are not CFG based. Recompute it now. */
14277 compute_bb_for_insn ();
14284 COPY_REG_SET (&live
, DF_LR_OUT (bb
));
14285 df_simulate_initialize_backwards (bb
, &live
);
14286 FOR_BB_INSNS_REVERSE (bb
, insn
)
14288 if (NONJUMP_INSN_P (insn
)
14289 && !REGNO_REG_SET_P (&live
, CC_REGNUM
)
14290 && GET_CODE (PATTERN (insn
)) == SET
)
14292 enum {SKIP
, CONV
, SWAP_CONV
} action
= SKIP
;
14293 rtx pat
= PATTERN (insn
);
14294 rtx dst
= XEXP (pat
, 0);
14295 rtx src
= XEXP (pat
, 1);
14296 rtx op0
= NULL_RTX
, op1
= NULL_RTX
;
14298 if (!OBJECT_P (src
))
14299 op0
= XEXP (src
, 0);
14301 if (BINARY_P (src
))
14302 op1
= XEXP (src
, 1);
14304 if (low_register_operand (dst
, SImode
))
14306 switch (GET_CODE (src
))
14309 /* Adding two registers and storing the result
14310 in the first source is already a 16-bit
14312 if (rtx_equal_p (dst
, op0
)
14313 && register_operand (op1
, SImode
))
14316 if (low_register_operand (op0
, SImode
))
14318 /* ADDS <Rd>,<Rn>,<Rm> */
14319 if (low_register_operand (op1
, SImode
))
14321 /* ADDS <Rdn>,#<imm8> */
14322 /* SUBS <Rdn>,#<imm8> */
14323 else if (rtx_equal_p (dst
, op0
)
14324 && CONST_INT_P (op1
)
14325 && IN_RANGE (INTVAL (op1
), -255, 255))
14327 /* ADDS <Rd>,<Rn>,#<imm3> */
14328 /* SUBS <Rd>,<Rn>,#<imm3> */
14329 else if (CONST_INT_P (op1
)
14330 && IN_RANGE (INTVAL (op1
), -7, 7))
14336 /* RSBS <Rd>,<Rn>,#0
14337 Not handled here: see NEG below. */
14338 /* SUBS <Rd>,<Rn>,#<imm3>
14340 Not handled here: see PLUS above. */
14341 /* SUBS <Rd>,<Rn>,<Rm> */
14342 if (low_register_operand (op0
, SImode
)
14343 && low_register_operand (op1
, SImode
))
14348 /* MULS <Rdm>,<Rn>,<Rdm>
14349 As an exception to the rule, this is only used
14350 when optimizing for size since MULS is slow on all
14351 known implementations. We do not even want to use
14352 MULS in cold code, if optimizing for speed, so we
14353 test the global flag here. */
14354 if (!optimize_size
)
14356 /* else fall through. */
14360 /* ANDS <Rdn>,<Rm> */
14361 if (rtx_equal_p (dst
, op0
)
14362 && low_register_operand (op1
, SImode
))
14364 else if (rtx_equal_p (dst
, op1
)
14365 && low_register_operand (op0
, SImode
))
14366 action
= SWAP_CONV
;
14372 /* ASRS <Rdn>,<Rm> */
14373 /* LSRS <Rdn>,<Rm> */
14374 /* LSLS <Rdn>,<Rm> */
14375 if (rtx_equal_p (dst
, op0
)
14376 && low_register_operand (op1
, SImode
))
14378 /* ASRS <Rd>,<Rm>,#<imm5> */
14379 /* LSRS <Rd>,<Rm>,#<imm5> */
14380 /* LSLS <Rd>,<Rm>,#<imm5> */
14381 else if (low_register_operand (op0
, SImode
)
14382 && CONST_INT_P (op1
)
14383 && IN_RANGE (INTVAL (op1
), 0, 31))
14388 /* RORS <Rdn>,<Rm> */
14389 if (rtx_equal_p (dst
, op0
)
14390 && low_register_operand (op1
, SImode
))
14396 /* MVNS <Rd>,<Rm> */
14397 /* NEGS <Rd>,<Rm> (a.k.a RSBS) */
14398 if (low_register_operand (op0
, SImode
))
14403 /* MOVS <Rd>,#<imm8> */
14404 if (CONST_INT_P (src
)
14405 && IN_RANGE (INTVAL (src
), 0, 255))
14410 /* MOVS and MOV<c> with registers have different
14411 encodings, so are not relevant here. */
14419 if (action
!= SKIP
)
14421 rtx ccreg
= gen_rtx_REG (CCmode
, CC_REGNUM
);
14422 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, ccreg
);
14425 if (action
== SWAP_CONV
)
14427 src
= copy_rtx (src
);
14428 XEXP (src
, 0) = op1
;
14429 XEXP (src
, 1) = op0
;
14430 pat
= gen_rtx_SET (VOIDmode
, dst
, src
);
14431 vec
= gen_rtvec (2, pat
, clobber
);
14433 else /* action == CONV */
14434 vec
= gen_rtvec (2, pat
, clobber
);
14436 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
14437 INSN_CODE (insn
) = -1;
14441 if (NONDEBUG_INSN_P (insn
))
14442 df_simulate_one_insn_backwards (bb
, insn
, &live
);
14446 CLEAR_REG_SET (&live
);
14449 /* Gcc puts the pool in the wrong place for ARM, since we can only
14450 load addresses a limited distance around the pc. We do some
14451 special munging to move the constant pool values to the correct
14452 point in the code. */
14457 HOST_WIDE_INT address
= 0;
14462 else if (TARGET_THUMB2
)
14465 /* Ensure all insns that must be split have been split at this point.
14466 Otherwise, the pool placement code below may compute incorrect
14467 insn lengths. Note that when optimizing, all insns have already
14468 been split at this point. */
14470 split_all_insns_noflow ();
14472 minipool_fix_head
= minipool_fix_tail
= NULL
;
14474 /* The first insn must always be a note, or the code below won't
14475 scan it properly. */
14476 insn
= get_insns ();
14477 gcc_assert (NOTE_P (insn
));
14480 /* Scan all the insns and record the operands that will need fixing. */
14481 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
14483 if (BARRIER_P (insn
))
14484 push_minipool_barrier (insn
, address
);
14485 else if (INSN_P (insn
))
14489 note_invalid_constants (insn
, address
, true);
14490 address
+= get_attr_length (insn
);
14492 /* If the insn is a vector jump, add the size of the table
14493 and skip the table. */
14494 if ((table
= is_jump_table (insn
)) != NULL
)
14496 address
+= get_jump_table_size (table
);
14500 else if (LABEL_P (insn
))
14501 /* Add the worst-case padding due to alignment. We don't add
14502 the _current_ padding because the minipool insertions
14503 themselves might change it. */
14504 address
+= get_label_padding (insn
);
14507 fix
= minipool_fix_head
;
14509 /* Now scan the fixups and perform the required changes. */
14514 Mfix
* last_added_fix
;
14515 Mfix
* last_barrier
= NULL
;
14518 /* Skip any further barriers before the next fix. */
14519 while (fix
&& BARRIER_P (fix
->insn
))
14522 /* No more fixes. */
14526 last_added_fix
= NULL
;
14528 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
14530 if (BARRIER_P (ftmp
->insn
))
14532 if (ftmp
->address
>= minipool_vector_head
->max_address
)
14535 last_barrier
= ftmp
;
14537 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
14540 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
14543 /* If we found a barrier, drop back to that; any fixes that we
14544 could have reached but come after the barrier will now go in
14545 the next mini-pool. */
14546 if (last_barrier
!= NULL
)
14548 /* Reduce the refcount for those fixes that won't go into this
14550 for (fdel
= last_barrier
->next
;
14551 fdel
&& fdel
!= ftmp
;
14554 fdel
->minipool
->refcount
--;
14555 fdel
->minipool
= NULL
;
14558 ftmp
= last_barrier
;
14562 /* ftmp is first fix that we can't fit into this pool and
14563 there no natural barriers that we could use. Insert a
14564 new barrier in the code somewhere between the previous
14565 fix and this one, and arrange to jump around it. */
14566 HOST_WIDE_INT max_address
;
14568 /* The last item on the list of fixes must be a barrier, so
14569 we can never run off the end of the list of fixes without
14570 last_barrier being set. */
14573 max_address
= minipool_vector_head
->max_address
;
14574 /* Check that there isn't another fix that is in range that
14575 we couldn't fit into this pool because the pool was
14576 already too large: we need to put the pool before such an
14577 instruction. The pool itself may come just after the
14578 fix because create_fix_barrier also allows space for a
14579 jump instruction. */
14580 if (ftmp
->address
< max_address
)
14581 max_address
= ftmp
->address
+ 1;
14583 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
14586 assign_minipool_offsets (last_barrier
);
14590 if (!BARRIER_P (ftmp
->insn
)
14591 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
14598 /* Scan over the fixes we have identified for this pool, fixing them
14599 up and adding the constants to the pool itself. */
14600 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
14601 this_fix
= this_fix
->next
)
14602 if (!BARRIER_P (this_fix
->insn
))
14605 = plus_constant (Pmode
,
14606 gen_rtx_LABEL_REF (VOIDmode
,
14607 minipool_vector_label
),
14608 this_fix
->minipool
->offset
);
14609 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
14612 dump_minipool (last_barrier
->insn
);
14616 /* From now on we must synthesize any constants that we can't handle
14617 directly. This can happen if the RTL gets split during final
14618 instruction generation. */
14619 after_arm_reorg
= 1;
14621 /* Free the minipool memory. */
14622 obstack_free (&minipool_obstack
, minipool_startobj
);
14625 /* Routines to output assembly language. */
14627 /* If the rtx is the correct value then return the string of the number.
14628 In this way we can ensure that valid double constants are generated even
14629 when cross compiling. */
14631 fp_immediate_constant (rtx x
)
14635 if (!fp_consts_inited
)
14638 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
14640 gcc_assert (REAL_VALUES_EQUAL (r
, value_fp0
));
14644 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
14645 static const char *
14646 fp_const_from_val (REAL_VALUE_TYPE
*r
)
14648 if (!fp_consts_inited
)
14651 gcc_assert (REAL_VALUES_EQUAL (*r
, value_fp0
));
14655 /* OPERANDS[0] is the entire list of insns that constitute pop,
14656 OPERANDS[1] is the base register, RETURN_PC is true iff return insn
14657 is in the list, UPDATE is true iff the list contains explicit
14658 update of base register. */
14660 arm_output_multireg_pop (rtx
*operands
, bool return_pc
, rtx cond
, bool reverse
,
14666 const char *conditional
;
14667 int num_saves
= XVECLEN (operands
[0], 0);
14668 unsigned int regno
;
14669 unsigned int regno_base
= REGNO (operands
[1]);
14672 offset
+= update
? 1 : 0;
14673 offset
+= return_pc
? 1 : 0;
14675 /* Is the base register in the list? */
14676 for (i
= offset
; i
< num_saves
; i
++)
14678 regno
= REGNO (XEXP (XVECEXP (operands
[0], 0, i
), 0));
14679 /* If SP is in the list, then the base register must be SP. */
14680 gcc_assert ((regno
!= SP_REGNUM
) || (regno_base
== SP_REGNUM
));
14681 /* If base register is in the list, there must be no explicit update. */
14682 if (regno
== regno_base
)
14683 gcc_assert (!update
);
14686 conditional
= reverse
? "%?%D0" : "%?%d0";
14687 if ((regno_base
== SP_REGNUM
) && TARGET_UNIFIED_ASM
)
14689 /* Output pop (not stmfd) because it has a shorter encoding. */
14690 gcc_assert (update
);
14691 sprintf (pattern
, "pop%s\t{", conditional
);
14695 /* Output ldmfd when the base register is SP, otherwise output ldmia.
14696 It's just a convention, their semantics are identical. */
14697 if (regno_base
== SP_REGNUM
)
14698 sprintf (pattern
, "ldm%sfd\t", conditional
);
14699 else if (TARGET_UNIFIED_ASM
)
14700 sprintf (pattern
, "ldmia%s\t", conditional
);
14702 sprintf (pattern
, "ldm%sia\t", conditional
);
14704 strcat (pattern
, reg_names
[regno_base
]);
14706 strcat (pattern
, "!, {");
14708 strcat (pattern
, ", {");
14711 /* Output the first destination register. */
14713 reg_names
[REGNO (XEXP (XVECEXP (operands
[0], 0, offset
), 0))]);
14715 /* Output the rest of the destination registers. */
14716 for (i
= offset
+ 1; i
< num_saves
; i
++)
14718 strcat (pattern
, ", ");
14720 reg_names
[REGNO (XEXP (XVECEXP (operands
[0], 0, i
), 0))]);
14723 strcat (pattern
, "}");
14725 if (IS_INTERRUPT (arm_current_func_type ()) && return_pc
)
14726 strcat (pattern
, "^");
14728 output_asm_insn (pattern
, &cond
);
14732 /* Output the assembly for a store multiple. */
14735 vfp_output_fstmd (rtx
* operands
)
14742 strcpy (pattern
, "fstmfdd%?\t%m0!, {%P1");
14743 p
= strlen (pattern
);
14745 gcc_assert (REG_P (operands
[1]));
14747 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
14748 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
14750 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
14752 strcpy (&pattern
[p
], "}");
14754 output_asm_insn (pattern
, operands
);
14759 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
14760 number of bytes pushed. */
14763 vfp_emit_fstmd (int base_reg
, int count
)
14770 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
14771 register pairs are stored by a store multiple insn. We avoid this
14772 by pushing an extra pair. */
14773 if (count
== 2 && !arm_arch6
)
14775 if (base_reg
== LAST_VFP_REGNUM
- 3)
14780 /* FSTMD may not store more than 16 doubleword registers at once. Split
14781 larger stores into multiple parts (up to a maximum of two, in
14786 /* NOTE: base_reg is an internal register number, so each D register
14788 saved
= vfp_emit_fstmd (base_reg
+ 32, count
- 16);
14789 saved
+= vfp_emit_fstmd (base_reg
, 16);
14793 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
14794 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
14796 reg
= gen_rtx_REG (DFmode
, base_reg
);
14799 XVECEXP (par
, 0, 0)
14800 = gen_rtx_SET (VOIDmode
,
14803 gen_rtx_PRE_MODIFY (Pmode
,
14806 (Pmode
, stack_pointer_rtx
,
14809 gen_rtx_UNSPEC (BLKmode
,
14810 gen_rtvec (1, reg
),
14811 UNSPEC_PUSH_MULT
));
14813 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
14814 plus_constant (Pmode
, stack_pointer_rtx
, -(count
* 8)));
14815 RTX_FRAME_RELATED_P (tmp
) = 1;
14816 XVECEXP (dwarf
, 0, 0) = tmp
;
14818 tmp
= gen_rtx_SET (VOIDmode
,
14819 gen_frame_mem (DFmode
, stack_pointer_rtx
),
14821 RTX_FRAME_RELATED_P (tmp
) = 1;
14822 XVECEXP (dwarf
, 0, 1) = tmp
;
14824 for (i
= 1; i
< count
; i
++)
14826 reg
= gen_rtx_REG (DFmode
, base_reg
);
14828 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
14830 tmp
= gen_rtx_SET (VOIDmode
,
14831 gen_frame_mem (DFmode
,
14832 plus_constant (Pmode
,
14836 RTX_FRAME_RELATED_P (tmp
) = 1;
14837 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
14840 par
= emit_insn (par
);
14841 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
14842 RTX_FRAME_RELATED_P (par
) = 1;
14847 /* Emit a call instruction with pattern PAT. ADDR is the address of
14848 the call target. */
14851 arm_emit_call_insn (rtx pat
, rtx addr
)
14855 insn
= emit_call_insn (pat
);
14857 /* The PIC register is live on entry to VxWorks PIC PLT entries.
14858 If the call might use such an entry, add a use of the PIC register
14859 to the instruction's CALL_INSN_FUNCTION_USAGE. */
14860 if (TARGET_VXWORKS_RTP
14862 && GET_CODE (addr
) == SYMBOL_REF
14863 && (SYMBOL_REF_DECL (addr
)
14864 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
14865 : !SYMBOL_REF_LOCAL_P (addr
)))
14867 require_pic_register ();
14868 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), cfun
->machine
->pic_reg
);
14872 /* Output a 'call' insn. */
14874 output_call (rtx
*operands
)
14876 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
14878 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
14879 if (REGNO (operands
[0]) == LR_REGNUM
)
14881 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
14882 output_asm_insn ("mov%?\t%0, %|lr", operands
);
14885 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
14887 if (TARGET_INTERWORK
|| arm_arch4t
)
14888 output_asm_insn ("bx%?\t%0", operands
);
14890 output_asm_insn ("mov%?\t%|pc, %0", operands
);
14895 /* Output a 'call' insn that is a reference in memory. This is
14896 disabled for ARMv5 and we prefer a blx instead because otherwise
14897 there's a significant performance overhead. */
14899 output_call_mem (rtx
*operands
)
14901 gcc_assert (!arm_arch5
);
14902 if (TARGET_INTERWORK
)
14904 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
14905 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
14906 output_asm_insn ("bx%?\t%|ip", operands
);
14908 else if (regno_use_in (LR_REGNUM
, operands
[0]))
14910 /* LR is used in the memory address. We load the address in the
14911 first instruction. It's safe to use IP as the target of the
14912 load since the call will kill it anyway. */
14913 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
14914 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
14916 output_asm_insn ("bx%?\t%|ip", operands
);
14918 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
14922 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
14923 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
14930 /* Output a move from arm registers to arm registers of a long double
14931 OPERANDS[0] is the destination.
14932 OPERANDS[1] is the source. */
14934 output_mov_long_double_arm_from_arm (rtx
*operands
)
14936 /* We have to be careful here because the two might overlap. */
14937 int dest_start
= REGNO (operands
[0]);
14938 int src_start
= REGNO (operands
[1]);
14942 if (dest_start
< src_start
)
14944 for (i
= 0; i
< 3; i
++)
14946 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
14947 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
14948 output_asm_insn ("mov%?\t%0, %1", ops
);
14953 for (i
= 2; i
>= 0; i
--)
14955 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
14956 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
14957 output_asm_insn ("mov%?\t%0, %1", ops
);
14965 arm_emit_movpair (rtx dest
, rtx src
)
14967 /* If the src is an immediate, simplify it. */
14968 if (CONST_INT_P (src
))
14970 HOST_WIDE_INT val
= INTVAL (src
);
14971 emit_set_insn (dest
, GEN_INT (val
& 0x0000ffff));
14972 if ((val
>> 16) & 0x0000ffff)
14973 emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode
, dest
, GEN_INT (16),
14975 GEN_INT ((val
>> 16) & 0x0000ffff));
14978 emit_set_insn (dest
, gen_rtx_HIGH (SImode
, src
));
14979 emit_set_insn (dest
, gen_rtx_LO_SUM (SImode
, dest
, src
));
14982 /* Output a move between double words. It must be REG<-MEM
14985 output_move_double (rtx
*operands
, bool emit
, int *count
)
14987 enum rtx_code code0
= GET_CODE (operands
[0]);
14988 enum rtx_code code1
= GET_CODE (operands
[1]);
14993 /* The only case when this might happen is when
14994 you are looking at the length of a DImode instruction
14995 that has an invalid constant in it. */
14996 if (code0
== REG
&& code1
!= MEM
)
14998 gcc_assert (!emit
);
15005 unsigned int reg0
= REGNO (operands
[0]);
15007 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
15009 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
15011 switch (GET_CODE (XEXP (operands
[1], 0)))
15018 && !(fix_cm3_ldrd
&& reg0
== REGNO(XEXP (operands
[1], 0))))
15019 output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands
);
15021 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
15026 gcc_assert (TARGET_LDRD
);
15028 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands
);
15035 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands
);
15037 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands
);
15045 output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands
);
15047 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands
);
15052 gcc_assert (TARGET_LDRD
);
15054 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands
);
15059 /* Autoicrement addressing modes should never have overlapping
15060 base and destination registers, and overlapping index registers
15061 are already prohibited, so this doesn't need to worry about
15063 otherops
[0] = operands
[0];
15064 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
15065 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
15067 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
15069 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
15071 /* Registers overlap so split out the increment. */
15074 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
15075 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops
);
15082 /* Use a single insn if we can.
15083 FIXME: IWMMXT allows offsets larger than ldrd can
15084 handle, fix these up with a pair of ldr. */
15086 || !CONST_INT_P (otherops
[2])
15087 || (INTVAL (otherops
[2]) > -256
15088 && INTVAL (otherops
[2]) < 256))
15091 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops
);
15097 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops
);
15098 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
15108 /* Use a single insn if we can.
15109 FIXME: IWMMXT allows offsets larger than ldrd can handle,
15110 fix these up with a pair of ldr. */
15112 || !CONST_INT_P (otherops
[2])
15113 || (INTVAL (otherops
[2]) > -256
15114 && INTVAL (otherops
[2]) < 256))
15117 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops
);
15123 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
15124 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops
);
15134 /* We might be able to use ldrd %0, %1 here. However the range is
15135 different to ldr/adr, and it is broken on some ARMv7-M
15136 implementations. */
15137 /* Use the second register of the pair to avoid problematic
15139 otherops
[1] = operands
[1];
15141 output_asm_insn ("adr%?\t%0, %1", otherops
);
15142 operands
[1] = otherops
[0];
15146 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands
);
15148 output_asm_insn ("ldm%(ia%)\t%1, %M0", operands
);
15155 /* ??? This needs checking for thumb2. */
15157 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
15158 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
15160 otherops
[0] = operands
[0];
15161 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
15162 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
15164 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
15166 if (CONST_INT_P (otherops
[2]) && !TARGET_LDRD
)
15168 switch ((int) INTVAL (otherops
[2]))
15172 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops
);
15178 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops
);
15184 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops
);
15188 otherops
[0] = gen_rtx_REG(SImode
, REGNO(operands
[0]) + 1);
15189 operands
[1] = otherops
[0];
15191 && (REG_P (otherops
[2])
15193 || (CONST_INT_P (otherops
[2])
15194 && INTVAL (otherops
[2]) > -256
15195 && INTVAL (otherops
[2]) < 256)))
15197 if (reg_overlap_mentioned_p (operands
[0],
15201 /* Swap base and index registers over to
15202 avoid a conflict. */
15204 otherops
[1] = otherops
[2];
15207 /* If both registers conflict, it will usually
15208 have been fixed by a splitter. */
15209 if (reg_overlap_mentioned_p (operands
[0], otherops
[2])
15210 || (fix_cm3_ldrd
&& reg0
== REGNO (otherops
[1])))
15214 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
15215 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands
);
15222 otherops
[0] = operands
[0];
15224 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops
);
15229 if (CONST_INT_P (otherops
[2]))
15233 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
15234 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
15236 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
15242 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
15248 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
15255 return "ldr%(d%)\t%0, [%1]";
15257 return "ldm%(ia%)\t%1, %M0";
15261 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
15262 /* Take care of overlapping base/data reg. */
15263 if (reg_mentioned_p (operands
[0], operands
[1]))
15267 output_asm_insn ("ldr%?\t%0, %1", otherops
);
15268 output_asm_insn ("ldr%?\t%0, %1", operands
);
15278 output_asm_insn ("ldr%?\t%0, %1", operands
);
15279 output_asm_insn ("ldr%?\t%0, %1", otherops
);
15289 /* Constraints should ensure this. */
15290 gcc_assert (code0
== MEM
&& code1
== REG
);
15291 gcc_assert ((REGNO (operands
[1]) != IP_REGNUM
)
15292 || (TARGET_ARM
&& TARGET_LDRD
));
15294 switch (GET_CODE (XEXP (operands
[0], 0)))
15300 output_asm_insn ("str%(d%)\t%1, [%m0]", operands
);
15302 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
15307 gcc_assert (TARGET_LDRD
);
15309 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands
);
15316 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands
);
15318 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands
);
15326 output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands
);
15328 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands
);
15333 gcc_assert (TARGET_LDRD
);
15335 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands
);
15340 otherops
[0] = operands
[1];
15341 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
15342 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
15344 /* IWMMXT allows offsets larger than ldrd can handle,
15345 fix these up with a pair of ldr. */
15347 && CONST_INT_P (otherops
[2])
15348 && (INTVAL(otherops
[2]) <= -256
15349 || INTVAL(otherops
[2]) >= 256))
15351 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
15355 output_asm_insn ("str%?\t%0, [%1, %2]!", otherops
);
15356 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops
);
15365 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops
);
15366 output_asm_insn ("str%?\t%0, [%1], %2", otherops
);
15372 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
15375 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops
);
15380 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops
);
15385 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
15386 if (CONST_INT_P (otherops
[2]) && !TARGET_LDRD
)
15388 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
15392 output_asm_insn ("stm%(db%)\t%m0, %M1", operands
);
15399 output_asm_insn ("stm%(da%)\t%m0, %M1", operands
);
15406 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands
);
15411 && (REG_P (otherops
[2])
15413 || (CONST_INT_P (otherops
[2])
15414 && INTVAL (otherops
[2]) > -256
15415 && INTVAL (otherops
[2]) < 256)))
15417 otherops
[0] = operands
[1];
15418 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
15420 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops
);
15426 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
15427 otherops
[1] = operands
[1];
15430 output_asm_insn ("str%?\t%1, %0", operands
);
15431 output_asm_insn ("str%?\t%H1, %0", otherops
);
15441 /* Output a move, load or store for quad-word vectors in ARM registers. Only
15442 handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
15445 output_move_quad (rtx
*operands
)
15447 if (REG_P (operands
[0]))
15449 /* Load, or reg->reg move. */
15451 if (MEM_P (operands
[1]))
15453 switch (GET_CODE (XEXP (operands
[1], 0)))
15456 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
15461 output_asm_insn ("adr%?\t%0, %1", operands
);
15462 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands
);
15466 gcc_unreachable ();
15474 gcc_assert (REG_P (operands
[1]));
15476 dest
= REGNO (operands
[0]);
15477 src
= REGNO (operands
[1]);
15479 /* This seems pretty dumb, but hopefully GCC won't try to do it
15482 for (i
= 0; i
< 4; i
++)
15484 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
15485 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
15486 output_asm_insn ("mov%?\t%0, %1", ops
);
15489 for (i
= 3; i
>= 0; i
--)
15491 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
15492 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
15493 output_asm_insn ("mov%?\t%0, %1", ops
);
15499 gcc_assert (MEM_P (operands
[0]));
15500 gcc_assert (REG_P (operands
[1]));
15501 gcc_assert (!reg_overlap_mentioned_p (operands
[1], operands
[0]));
15503 switch (GET_CODE (XEXP (operands
[0], 0)))
15506 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
15510 gcc_unreachable ();
15517 /* Output a VFP load or store instruction. */
15520 output_move_vfp (rtx
*operands
)
15522 rtx reg
, mem
, addr
, ops
[2];
15523 int load
= REG_P (operands
[0]);
15524 int dp
= GET_MODE_SIZE (GET_MODE (operands
[0])) == 8;
15525 int integer_p
= GET_MODE_CLASS (GET_MODE (operands
[0])) == MODE_INT
;
15528 enum machine_mode mode
;
15530 reg
= operands
[!load
];
15531 mem
= operands
[load
];
15533 mode
= GET_MODE (reg
);
15535 gcc_assert (REG_P (reg
));
15536 gcc_assert (IS_VFP_REGNUM (REGNO (reg
)));
15537 gcc_assert (mode
== SFmode
15541 || (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
)));
15542 gcc_assert (MEM_P (mem
));
15544 addr
= XEXP (mem
, 0);
15546 switch (GET_CODE (addr
))
15549 templ
= "f%smdb%c%%?\t%%0!, {%%%s1}%s";
15550 ops
[0] = XEXP (addr
, 0);
15555 templ
= "f%smia%c%%?\t%%0!, {%%%s1}%s";
15556 ops
[0] = XEXP (addr
, 0);
15561 templ
= "f%s%c%%?\t%%%s0, %%1%s";
15567 sprintf (buff
, templ
,
15568 load
? "ld" : "st",
15571 integer_p
? "\t%@ int" : "");
15572 output_asm_insn (buff
, ops
);
15577 /* Output a Neon double-word or quad-word load or store, or a load
15578 or store for larger structure modes.
15580 WARNING: The ordering of elements is weird in big-endian mode,
15581 because the EABI requires that vectors stored in memory appear
15582 as though they were stored by a VSTM, as required by the EABI.
15583 GCC RTL defines element ordering based on in-memory order.
15584 This can be different from the architectural ordering of elements
15585 within a NEON register. The intrinsics defined in arm_neon.h use the
15586 NEON register element ordering, not the GCC RTL element ordering.
15588 For example, the in-memory ordering of a big-endian a quadword
15589 vector with 16-bit elements when stored from register pair {d0,d1}
15590 will be (lowest address first, d0[N] is NEON register element N):
15592 [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]]
15594 When necessary, quadword registers (dN, dN+1) are moved to ARM
15595 registers from rN in the order:
15597 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
15599 So that STM/LDM can be used on vectors in ARM registers, and the
15600 same memory layout will result as if VSTM/VLDM were used.
15602 Instead of VSTM/VLDM we prefer to use VST1.64/VLD1.64 where
15603 possible, which allows use of appropriate alignment tags.
15604 Note that the choice of "64" is independent of the actual vector
15605 element size; this size simply ensures that the behavior is
15606 equivalent to VSTM/VLDM in both little-endian and big-endian mode.
15608 Due to limitations of those instructions, use of VST1.64/VLD1.64
15609 is not possible if:
15610 - the address contains PRE_DEC, or
15611 - the mode refers to more than 4 double-word registers
15613 In those cases, it would be possible to replace VSTM/VLDM by a
15614 sequence of instructions; this is not currently implemented since
15615 this is not certain to actually improve performance. */
15618 output_move_neon (rtx
*operands
)
15620 rtx reg
, mem
, addr
, ops
[2];
15621 int regno
, nregs
, load
= REG_P (operands
[0]);
15624 enum machine_mode mode
;
15626 reg
= operands
[!load
];
15627 mem
= operands
[load
];
15629 mode
= GET_MODE (reg
);
15631 gcc_assert (REG_P (reg
));
15632 regno
= REGNO (reg
);
15633 nregs
= HARD_REGNO_NREGS (regno
, mode
) / 2;
15634 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno
)
15635 || NEON_REGNO_OK_FOR_QUAD (regno
));
15636 gcc_assert (VALID_NEON_DREG_MODE (mode
)
15637 || VALID_NEON_QREG_MODE (mode
)
15638 || VALID_NEON_STRUCT_MODE (mode
));
15639 gcc_assert (MEM_P (mem
));
15641 addr
= XEXP (mem
, 0);
15643 /* Strip off const from addresses like (const (plus (...))). */
15644 if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
)
15645 addr
= XEXP (addr
, 0);
15647 switch (GET_CODE (addr
))
15650 /* We have to use vldm / vstm for too-large modes. */
15653 templ
= "v%smia%%?\t%%0!, %%h1";
15654 ops
[0] = XEXP (addr
, 0);
15658 templ
= "v%s1.64\t%%h1, %%A0";
15665 /* We have to use vldm / vstm in this case, since there is no
15666 pre-decrement form of the vld1 / vst1 instructions. */
15667 templ
= "v%smdb%%?\t%%0!, %%h1";
15668 ops
[0] = XEXP (addr
, 0);
15673 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
15674 gcc_unreachable ();
15681 for (i
= 0; i
< nregs
; i
++)
15683 /* We're only using DImode here because it's a convenient size. */
15684 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * i
);
15685 ops
[1] = adjust_address (mem
, DImode
, 8 * i
);
15686 if (reg_overlap_mentioned_p (ops
[0], mem
))
15688 gcc_assert (overlap
== -1);
15693 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
15694 output_asm_insn (buff
, ops
);
15699 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * overlap
);
15700 ops
[1] = adjust_address (mem
, SImode
, 8 * overlap
);
15701 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
15702 output_asm_insn (buff
, ops
);
15709 /* We have to use vldm / vstm for too-large modes. */
15711 templ
= "v%smia%%?\t%%m0, %%h1";
15713 templ
= "v%s1.64\t%%h1, %%A0";
15719 sprintf (buff
, templ
, load
? "ld" : "st");
15720 output_asm_insn (buff
, ops
);
15725 /* Compute and return the length of neon_mov<mode>, where <mode> is
15726 one of VSTRUCT modes: EI, OI, CI or XI. */
15728 arm_attr_length_move_neon (rtx insn
)
15730 rtx reg
, mem
, addr
;
15732 enum machine_mode mode
;
15734 extract_insn_cached (insn
);
15736 if (REG_P (recog_data
.operand
[0]) && REG_P (recog_data
.operand
[1]))
15738 mode
= GET_MODE (recog_data
.operand
[0]);
15749 gcc_unreachable ();
15753 load
= REG_P (recog_data
.operand
[0]);
15754 reg
= recog_data
.operand
[!load
];
15755 mem
= recog_data
.operand
[load
];
15757 gcc_assert (MEM_P (mem
));
15759 mode
= GET_MODE (reg
);
15760 addr
= XEXP (mem
, 0);
15762 /* Strip off const from addresses like (const (plus (...))). */
15763 if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
)
15764 addr
= XEXP (addr
, 0);
15766 if (GET_CODE (addr
) == LABEL_REF
|| GET_CODE (addr
) == PLUS
)
15768 int insns
= HARD_REGNO_NREGS (REGNO (reg
), mode
) / 2;
15775 /* Return nonzero if the offset in the address is an immediate. Otherwise,
15779 arm_address_offset_is_imm (rtx insn
)
15783 extract_insn_cached (insn
);
15785 if (REG_P (recog_data
.operand
[0]))
15788 mem
= recog_data
.operand
[0];
15790 gcc_assert (MEM_P (mem
));
15792 addr
= XEXP (mem
, 0);
15795 || (GET_CODE (addr
) == PLUS
15796 && REG_P (XEXP (addr
, 0))
15797 && CONST_INT_P (XEXP (addr
, 1))))
15803 /* Output an ADD r, s, #n where n may be too big for one instruction.
15804 If adding zero to one register, output nothing. */
15806 output_add_immediate (rtx
*operands
)
15808 HOST_WIDE_INT n
= INTVAL (operands
[2]);
15810 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
15813 output_multi_immediate (operands
,
15814 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
15817 output_multi_immediate (operands
,
15818 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
15825 /* Output a multiple immediate operation.
15826 OPERANDS is the vector of operands referred to in the output patterns.
15827 INSTR1 is the output pattern to use for the first constant.
15828 INSTR2 is the output pattern to use for subsequent constants.
15829 IMMED_OP is the index of the constant slot in OPERANDS.
15830 N is the constant value. */
15831 static const char *
15832 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
15833 int immed_op
, HOST_WIDE_INT n
)
15835 #if HOST_BITS_PER_WIDE_INT > 32
15841 /* Quick and easy output. */
15842 operands
[immed_op
] = const0_rtx
;
15843 output_asm_insn (instr1
, operands
);
15848 const char * instr
= instr1
;
15850 /* Note that n is never zero here (which would give no output). */
15851 for (i
= 0; i
< 32; i
+= 2)
15855 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
15856 output_asm_insn (instr
, operands
);
15866 /* Return the name of a shifter operation. */
15867 static const char *
15868 arm_shift_nmem(enum rtx_code code
)
15873 return ARM_LSL_NAME
;
15889 /* Return the appropriate ARM instruction for the operation code.
15890 The returned result should not be overwritten. OP is the rtx of the
15891 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
15894 arithmetic_instr (rtx op
, int shift_first_arg
)
15896 switch (GET_CODE (op
))
15902 return shift_first_arg
? "rsb" : "sub";
15917 return arm_shift_nmem(GET_CODE(op
));
15920 gcc_unreachable ();
15924 /* Ensure valid constant shifts and return the appropriate shift mnemonic
15925 for the operation code. The returned result should not be overwritten.
15926 OP is the rtx code of the shift.
15927 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
15929 static const char *
15930 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
15933 enum rtx_code code
= GET_CODE (op
);
15938 if (!CONST_INT_P (XEXP (op
, 1)))
15940 output_operand_lossage ("invalid shift operand");
15945 *amountp
= 32 - INTVAL (XEXP (op
, 1));
15953 mnem
= arm_shift_nmem(code
);
15954 if (CONST_INT_P (XEXP (op
, 1)))
15956 *amountp
= INTVAL (XEXP (op
, 1));
15958 else if (REG_P (XEXP (op
, 1)))
15965 output_operand_lossage ("invalid shift operand");
15971 /* We never have to worry about the amount being other than a
15972 power of 2, since this case can never be reloaded from a reg. */
15973 if (!CONST_INT_P (XEXP (op
, 1)))
15975 output_operand_lossage ("invalid shift operand");
15979 *amountp
= INTVAL (XEXP (op
, 1)) & 0xFFFFFFFF;
15981 /* Amount must be a power of two. */
15982 if (*amountp
& (*amountp
- 1))
15984 output_operand_lossage ("invalid shift operand");
15988 *amountp
= int_log2 (*amountp
);
15989 return ARM_LSL_NAME
;
15992 output_operand_lossage ("invalid shift operand");
15996 /* This is not 100% correct, but follows from the desire to merge
15997 multiplication by a power of 2 with the recognizer for a
15998 shift. >=32 is not a valid shift for "lsl", so we must try and
15999 output a shift that produces the correct arithmetical result.
16000 Using lsr #32 is identical except for the fact that the carry bit
16001 is not set correctly if we set the flags; but we never use the
16002 carry bit from such an operation, so we can ignore that. */
16003 if (code
== ROTATERT
)
16004 /* Rotate is just modulo 32. */
16006 else if (*amountp
!= (*amountp
& 31))
16008 if (code
== ASHIFT
)
16013 /* Shifts of 0 are no-ops. */
16020 /* Obtain the shift from the POWER of two. */
16022 static HOST_WIDE_INT
16023 int_log2 (HOST_WIDE_INT power
)
16025 HOST_WIDE_INT shift
= 0;
16027 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
16029 gcc_assert (shift
<= 31);
16036 /* Output a .ascii pseudo-op, keeping track of lengths. This is
16037 because /bin/as is horribly restrictive. The judgement about
16038 whether or not each character is 'printable' (and can be output as
16039 is) or not (and must be printed with an octal escape) must be made
16040 with reference to the *host* character set -- the situation is
16041 similar to that discussed in the comments above pp_c_char in
16042 c-pretty-print.c. */
16044 #define MAX_ASCII_LEN 51
16047 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
16050 int len_so_far
= 0;
16052 fputs ("\t.ascii\t\"", stream
);
16054 for (i
= 0; i
< len
; i
++)
16058 if (len_so_far
>= MAX_ASCII_LEN
)
16060 fputs ("\"\n\t.ascii\t\"", stream
);
16066 if (c
== '\\' || c
== '\"')
16068 putc ('\\', stream
);
16076 fprintf (stream
, "\\%03o", c
);
16081 fputs ("\"\n", stream
);
16084 /* Compute the register save mask for registers 0 through 12
16085 inclusive. This code is used by arm_compute_save_reg_mask. */
16087 static unsigned long
16088 arm_compute_save_reg0_reg12_mask (void)
16090 unsigned long func_type
= arm_current_func_type ();
16091 unsigned long save_reg_mask
= 0;
16094 if (IS_INTERRUPT (func_type
))
16096 unsigned int max_reg
;
16097 /* Interrupt functions must not corrupt any registers,
16098 even call clobbered ones. If this is a leaf function
16099 we can just examine the registers used by the RTL, but
16100 otherwise we have to assume that whatever function is
16101 called might clobber anything, and so we have to save
16102 all the call-clobbered registers as well. */
16103 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
16104 /* FIQ handlers have registers r8 - r12 banked, so
16105 we only need to check r0 - r7, Normal ISRs only
16106 bank r14 and r15, so we must check up to r12.
16107 r13 is the stack pointer which is always preserved,
16108 so we do not need to consider it here. */
16113 for (reg
= 0; reg
<= max_reg
; reg
++)
16114 if (df_regs_ever_live_p (reg
)
16115 || (! crtl
->is_leaf
&& call_used_regs
[reg
]))
16116 save_reg_mask
|= (1 << reg
);
16118 /* Also save the pic base register if necessary. */
16120 && !TARGET_SINGLE_PIC_BASE
16121 && arm_pic_register
!= INVALID_REGNUM
16122 && crtl
->uses_pic_offset_table
)
16123 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
16125 else if (IS_VOLATILE(func_type
))
16127 /* For noreturn functions we historically omitted register saves
16128 altogether. However this really messes up debugging. As a
16129 compromise save just the frame pointers. Combined with the link
16130 register saved elsewhere this should be sufficient to get
16132 if (frame_pointer_needed
)
16133 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
16134 if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM
))
16135 save_reg_mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
16136 if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM
))
16137 save_reg_mask
|= 1 << THUMB_HARD_FRAME_POINTER_REGNUM
;
16141 /* In the normal case we only need to save those registers
16142 which are call saved and which are used by this function. */
16143 for (reg
= 0; reg
<= 11; reg
++)
16144 if (df_regs_ever_live_p (reg
) && ! call_used_regs
[reg
])
16145 save_reg_mask
|= (1 << reg
);
16147 /* Handle the frame pointer as a special case. */
16148 if (frame_pointer_needed
)
16149 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
16151 /* If we aren't loading the PIC register,
16152 don't stack it even though it may be live. */
16154 && !TARGET_SINGLE_PIC_BASE
16155 && arm_pic_register
!= INVALID_REGNUM
16156 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
)
16157 || crtl
->uses_pic_offset_table
))
16158 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
16160 /* The prologue will copy SP into R0, so save it. */
16161 if (IS_STACKALIGN (func_type
))
16162 save_reg_mask
|= 1;
16165 /* Save registers so the exception handler can modify them. */
16166 if (crtl
->calls_eh_return
)
16172 reg
= EH_RETURN_DATA_REGNO (i
);
16173 if (reg
== INVALID_REGNUM
)
16175 save_reg_mask
|= 1 << reg
;
16179 return save_reg_mask
;
16182 /* Return true if r3 is live at the start of the function. */
16185 arm_r3_live_at_start_p (void)
16187 /* Just look at cfg info, which is still close enough to correct at this
16188 point. This gives false positives for broken functions that might use
16189 uninitialized data that happens to be allocated in r3, but who cares? */
16190 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR
), 3);
16193 /* Compute the number of bytes used to store the static chain register on the
16194 stack, above the stack frame. We need to know this accurately to get the
16195 alignment of the rest of the stack frame correct. */
16198 arm_compute_static_chain_stack_bytes (void)
16200 /* See the defining assertion in arm_expand_prologue. */
16201 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
16202 && IS_NESTED (arm_current_func_type ())
16203 && arm_r3_live_at_start_p ()
16204 && crtl
->args
.pretend_args_size
== 0)
16210 /* Compute a bit mask of which registers need to be
16211 saved on the stack for the current function.
16212 This is used by arm_get_frame_offsets, which may add extra registers. */
16214 static unsigned long
16215 arm_compute_save_reg_mask (void)
16217 unsigned int save_reg_mask
= 0;
16218 unsigned long func_type
= arm_current_func_type ();
16221 if (IS_NAKED (func_type
))
16222 /* This should never really happen. */
16225 /* If we are creating a stack frame, then we must save the frame pointer,
16226 IP (which will hold the old stack pointer), LR and the PC. */
16227 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
16229 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
16232 | (1 << PC_REGNUM
);
16234 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
16236 /* Decide if we need to save the link register.
16237 Interrupt routines have their own banked link register,
16238 so they never need to save it.
16239 Otherwise if we do not use the link register we do not need to save
16240 it. If we are pushing other registers onto the stack however, we
16241 can save an instruction in the epilogue by pushing the link register
16242 now and then popping it back into the PC. This incurs extra memory
16243 accesses though, so we only do it when optimizing for size, and only
16244 if we know that we will not need a fancy return sequence. */
16245 if (df_regs_ever_live_p (LR_REGNUM
)
16248 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
16249 && !crtl
->calls_eh_return
))
16250 save_reg_mask
|= 1 << LR_REGNUM
;
16252 if (cfun
->machine
->lr_save_eliminated
)
16253 save_reg_mask
&= ~ (1 << LR_REGNUM
);
16255 if (TARGET_REALLY_IWMMXT
16256 && ((bit_count (save_reg_mask
)
16257 + ARM_NUM_INTS (crtl
->args
.pretend_args_size
+
16258 arm_compute_static_chain_stack_bytes())
16261 /* The total number of registers that are going to be pushed
16262 onto the stack is odd. We need to ensure that the stack
16263 is 64-bit aligned before we start to save iWMMXt registers,
16264 and also before we start to create locals. (A local variable
16265 might be a double or long long which we will load/store using
16266 an iWMMXt instruction). Therefore we need to push another
16267 ARM register, so that the stack will be 64-bit aligned. We
16268 try to avoid using the arg registers (r0 -r3) as they might be
16269 used to pass values in a tail call. */
16270 for (reg
= 4; reg
<= 12; reg
++)
16271 if ((save_reg_mask
& (1 << reg
)) == 0)
16275 save_reg_mask
|= (1 << reg
);
16278 cfun
->machine
->sibcall_blocked
= 1;
16279 save_reg_mask
|= (1 << 3);
16283 /* We may need to push an additional register for use initializing the
16284 PIC base register. */
16285 if (TARGET_THUMB2
&& IS_NESTED (func_type
) && flag_pic
16286 && (save_reg_mask
& THUMB2_WORK_REGS
) == 0)
16288 reg
= thumb_find_work_register (1 << 4);
16289 if (!call_used_regs
[reg
])
16290 save_reg_mask
|= (1 << reg
);
16293 return save_reg_mask
;
16297 /* Compute a bit mask of which registers need to be
16298 saved on the stack for the current function. */
16299 static unsigned long
16300 thumb1_compute_save_reg_mask (void)
16302 unsigned long mask
;
16306 for (reg
= 0; reg
< 12; reg
++)
16307 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
16311 && !TARGET_SINGLE_PIC_BASE
16312 && arm_pic_register
!= INVALID_REGNUM
16313 && crtl
->uses_pic_offset_table
)
16314 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
16316 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
16317 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
16318 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
16320 /* LR will also be pushed if any lo regs are pushed. */
16321 if (mask
& 0xff || thumb_force_lr_save ())
16322 mask
|= (1 << LR_REGNUM
);
16324 /* Make sure we have a low work register if we need one.
16325 We will need one if we are going to push a high register,
16326 but we are not currently intending to push a low register. */
16327 if ((mask
& 0xff) == 0
16328 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
16330 /* Use thumb_find_work_register to choose which register
16331 we will use. If the register is live then we will
16332 have to push it. Use LAST_LO_REGNUM as our fallback
16333 choice for the register to select. */
16334 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
16335 /* Make sure the register returned by thumb_find_work_register is
16336 not part of the return value. */
16337 if (reg
* UNITS_PER_WORD
<= (unsigned) arm_size_return_regs ())
16338 reg
= LAST_LO_REGNUM
;
16340 if (! call_used_regs
[reg
])
16344 /* The 504 below is 8 bytes less than 512 because there are two possible
16345 alignment words. We can't tell here if they will be present or not so we
16346 have to play it safe and assume that they are. */
16347 if ((CALLER_INTERWORKING_SLOT_SIZE
+
16348 ROUND_UP_WORD (get_frame_size ()) +
16349 crtl
->outgoing_args_size
) >= 504)
16351 /* This is the same as the code in thumb1_expand_prologue() which
16352 determines which register to use for stack decrement. */
16353 for (reg
= LAST_ARG_REGNUM
+ 1; reg
<= LAST_LO_REGNUM
; reg
++)
16354 if (mask
& (1 << reg
))
16357 if (reg
> LAST_LO_REGNUM
)
16359 /* Make sure we have a register available for stack decrement. */
16360 mask
|= 1 << LAST_LO_REGNUM
;
16368 /* Return the number of bytes required to save VFP registers. */
16370 arm_get_vfp_saved_size (void)
16372 unsigned int regno
;
16377 /* Space for saved VFP registers. */
16378 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
16381 for (regno
= FIRST_VFP_REGNUM
;
16382 regno
< LAST_VFP_REGNUM
;
16385 if ((!df_regs_ever_live_p (regno
) || call_used_regs
[regno
])
16386 && (!df_regs_ever_live_p (regno
+ 1) || call_used_regs
[regno
+ 1]))
16390 /* Workaround ARM10 VFPr1 bug. */
16391 if (count
== 2 && !arm_arch6
)
16393 saved
+= count
* 8;
16402 if (count
== 2 && !arm_arch6
)
16404 saved
+= count
* 8;
16411 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
16412 everything bar the final return instruction. If simple_return is true,
16413 then do not output epilogue, because it has already been emitted in RTL. */
16415 output_return_instruction (rtx operand
, bool really_return
, bool reverse
,
16416 bool simple_return
)
16418 char conditional
[10];
16421 unsigned long live_regs_mask
;
16422 unsigned long func_type
;
16423 arm_stack_offsets
*offsets
;
16425 func_type
= arm_current_func_type ();
16427 if (IS_NAKED (func_type
))
16430 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
16432 /* If this function was declared non-returning, and we have
16433 found a tail call, then we have to trust that the called
16434 function won't return. */
16439 /* Otherwise, trap an attempted return by aborting. */
16441 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
16443 assemble_external_libcall (ops
[1]);
16444 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
16450 gcc_assert (!cfun
->calls_alloca
|| really_return
);
16452 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
16454 cfun
->machine
->return_used_this_function
= 1;
16456 offsets
= arm_get_frame_offsets ();
16457 live_regs_mask
= offsets
->saved_regs_mask
;
16459 if (!simple_return
&& live_regs_mask
)
16461 const char * return_reg
;
16463 /* If we do not have any special requirements for function exit
16464 (e.g. interworking) then we can load the return address
16465 directly into the PC. Otherwise we must load it into LR. */
16467 && (IS_INTERRUPT (func_type
) || !TARGET_INTERWORK
))
16468 return_reg
= reg_names
[PC_REGNUM
];
16470 return_reg
= reg_names
[LR_REGNUM
];
16472 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
16474 /* There are three possible reasons for the IP register
16475 being saved. 1) a stack frame was created, in which case
16476 IP contains the old stack pointer, or 2) an ISR routine
16477 corrupted it, or 3) it was saved to align the stack on
16478 iWMMXt. In case 1, restore IP into SP, otherwise just
16480 if (frame_pointer_needed
)
16482 live_regs_mask
&= ~ (1 << IP_REGNUM
);
16483 live_regs_mask
|= (1 << SP_REGNUM
);
16486 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
16489 /* On some ARM architectures it is faster to use LDR rather than
16490 LDM to load a single register. On other architectures, the
16491 cost is the same. In 26 bit mode, or for exception handlers,
16492 we have to use LDM to load the PC so that the CPSR is also
16494 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
16495 if (live_regs_mask
== (1U << reg
))
16498 if (reg
<= LAST_ARM_REGNUM
16499 && (reg
!= LR_REGNUM
16501 || ! IS_INTERRUPT (func_type
)))
16503 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
16504 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
16511 /* Generate the load multiple instruction to restore the
16512 registers. Note we can get here, even if
16513 frame_pointer_needed is true, but only if sp already
16514 points to the base of the saved core registers. */
16515 if (live_regs_mask
& (1 << SP_REGNUM
))
16517 unsigned HOST_WIDE_INT stack_adjust
;
16519 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
16520 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
16522 if (stack_adjust
&& arm_arch5
&& TARGET_ARM
)
16523 if (TARGET_UNIFIED_ASM
)
16524 sprintf (instr
, "ldmib%s\t%%|sp, {", conditional
);
16526 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
16529 /* If we can't use ldmib (SA110 bug),
16530 then try to pop r3 instead. */
16532 live_regs_mask
|= 1 << 3;
16534 if (TARGET_UNIFIED_ASM
)
16535 sprintf (instr
, "ldmfd%s\t%%|sp, {", conditional
);
16537 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
16541 if (TARGET_UNIFIED_ASM
)
16542 sprintf (instr
, "pop%s\t{", conditional
);
16544 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
16546 p
= instr
+ strlen (instr
);
16548 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
16549 if (live_regs_mask
& (1 << reg
))
16551 int l
= strlen (reg_names
[reg
]);
16557 memcpy (p
, ", ", 2);
16561 memcpy (p
, "%|", 2);
16562 memcpy (p
+ 2, reg_names
[reg
], l
);
16566 if (live_regs_mask
& (1 << LR_REGNUM
))
16568 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
16569 /* If returning from an interrupt, restore the CPSR. */
16570 if (IS_INTERRUPT (func_type
))
16577 output_asm_insn (instr
, & operand
);
16579 /* See if we need to generate an extra instruction to
16580 perform the actual function return. */
16582 && func_type
!= ARM_FT_INTERWORKED
16583 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
16585 /* The return has already been handled
16586 by loading the LR into the PC. */
16593 switch ((int) ARM_FUNC_TYPE (func_type
))
16597 /* ??? This is wrong for unified assembly syntax. */
16598 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
16601 case ARM_FT_INTERWORKED
:
16602 sprintf (instr
, "bx%s\t%%|lr", conditional
);
16605 case ARM_FT_EXCEPTION
:
16606 /* ??? This is wrong for unified assembly syntax. */
16607 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
16611 /* Use bx if it's available. */
16612 if (arm_arch5
|| arm_arch4t
)
16613 sprintf (instr
, "bx%s\t%%|lr", conditional
);
16615 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
16619 output_asm_insn (instr
, & operand
);
16625 /* Write the function name into the code section, directly preceding
16626 the function prologue.
16628 Code will be output similar to this:
16630 .ascii "arm_poke_function_name", 0
16633 .word 0xff000000 + (t1 - t0)
16634 arm_poke_function_name
16636 stmfd sp!, {fp, ip, lr, pc}
16639 When performing a stack backtrace, code can inspect the value
16640 of 'pc' stored at 'fp' + 0. If the trace function then looks
16641 at location pc - 12 and the top 8 bits are set, then we know
16642 that there is a function name embedded immediately preceding this
16643 location and has length ((pc[-3]) & 0xff000000).
16645 We assume that pc is declared as a pointer to an unsigned long.
16647 It is of no benefit to output the function name if we are assembling
16648 a leaf function. These function types will not contain a stack
16649 backtrace structure, therefore it is not possible to determine the
16652 arm_poke_function_name (FILE *stream
, const char *name
)
16654 unsigned long alignlength
;
16655 unsigned long length
;
16658 length
= strlen (name
) + 1;
16659 alignlength
= ROUND_UP_WORD (length
);
16661 ASM_OUTPUT_ASCII (stream
, name
, length
);
16662 ASM_OUTPUT_ALIGN (stream
, 2);
16663 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
16664 assemble_aligned_integer (UNITS_PER_WORD
, x
);
16667 /* Place some comments into the assembler stream
16668 describing the current function. */
16670 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
16672 unsigned long func_type
;
16674 /* ??? Do we want to print some of the below anyway? */
16678 /* Sanity check. */
16679 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
16681 func_type
= arm_current_func_type ();
16683 switch ((int) ARM_FUNC_TYPE (func_type
))
16686 case ARM_FT_NORMAL
:
16688 case ARM_FT_INTERWORKED
:
16689 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
16692 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
16695 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
16697 case ARM_FT_EXCEPTION
:
16698 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
16702 if (IS_NAKED (func_type
))
16703 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
16705 if (IS_VOLATILE (func_type
))
16706 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
16708 if (IS_NESTED (func_type
))
16709 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
16710 if (IS_STACKALIGN (func_type
))
16711 asm_fprintf (f
, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
16713 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
16715 crtl
->args
.pretend_args_size
, frame_size
);
16717 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
16718 frame_pointer_needed
,
16719 cfun
->machine
->uses_anonymous_args
);
16721 if (cfun
->machine
->lr_save_eliminated
)
16722 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
16724 if (crtl
->calls_eh_return
)
16725 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
16730 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
16731 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
16733 arm_stack_offsets
*offsets
;
16739 /* Emit any call-via-reg trampolines that are needed for v4t support
16740 of call_reg and call_value_reg type insns. */
16741 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
16743 rtx label
= cfun
->machine
->call_via
[regno
];
16747 switch_to_section (function_section (current_function_decl
));
16748 targetm
.asm_out
.internal_label (asm_out_file
, "L",
16749 CODE_LABEL_NUMBER (label
));
16750 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
16754 /* ??? Probably not safe to set this here, since it assumes that a
16755 function will be emitted as assembly immediately after we generate
16756 RTL for it. This does not happen for inline functions. */
16757 cfun
->machine
->return_used_this_function
= 0;
16759 else /* TARGET_32BIT */
16761 /* We need to take into account any stack-frame rounding. */
16762 offsets
= arm_get_frame_offsets ();
16764 gcc_assert (!use_return_insn (FALSE
, NULL
)
16765 || (cfun
->machine
->return_used_this_function
!= 0)
16766 || offsets
->saved_regs
== offsets
->outgoing_args
16767 || frame_pointer_needed
);
16769 /* Reset the ARM-specific per-function variables. */
16770 after_arm_reorg
= 0;
16774 /* Generate and emit a pattern that will be recognized as STRD pattern. If even
16775 number of registers are being pushed, multiple STRD patterns are created for
16776 all register pairs. If odd number of registers are pushed, emit a
16777 combination of STRDs and STR for the prologue saves. */
16779 thumb2_emit_strd_push (unsigned long saved_regs_mask
)
16783 rtx par
= NULL_RTX
;
16784 rtx insn
= NULL_RTX
;
16785 rtx dwarf
= NULL_RTX
;
16786 rtx tmp
, reg
, tmp1
;
16788 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
16789 if (saved_regs_mask
& (1 << i
))
16792 gcc_assert (num_regs
&& num_regs
<= 16);
16794 /* Pre-decrement the stack pointer, based on there being num_regs 4-byte
16795 registers to push. */
16796 tmp
= gen_rtx_SET (VOIDmode
,
16798 plus_constant (Pmode
, stack_pointer_rtx
, -4 * num_regs
));
16799 RTX_FRAME_RELATED_P (tmp
) = 1;
16800 insn
= emit_insn (tmp
);
16802 /* Create sequence for DWARF info. */
16803 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_regs
+ 1));
16805 /* RTLs cannot be shared, hence create new copy for dwarf. */
16806 tmp1
= gen_rtx_SET (VOIDmode
,
16808 plus_constant (Pmode
, stack_pointer_rtx
, -4 * num_regs
));
16809 RTX_FRAME_RELATED_P (tmp1
) = 1;
16810 XVECEXP (dwarf
, 0, 0) = tmp1
;
16812 gcc_assert (!(saved_regs_mask
& (1 << SP_REGNUM
)));
16813 gcc_assert (!(saved_regs_mask
& (1 << PC_REGNUM
)));
16815 /* Var j iterates over all the registers to gather all the registers in
16816 saved_regs_mask. Var i gives index of register R_j in stack frame.
16817 A PARALLEL RTX of register-pair is created here, so that pattern for
16818 STRD can be matched. If num_regs is odd, 1st register will be pushed
16819 using STR and remaining registers will be pushed with STRD in pairs.
16820 If num_regs is even, all registers are pushed with STRD in pairs.
16821 Hence, skip first element for odd num_regs. */
16822 for (i
= num_regs
- 1, j
= LAST_ARM_REGNUM
; i
>= (num_regs
% 2); j
--)
16823 if (saved_regs_mask
& (1 << j
))
16825 /* Create RTX for store. New RTX is created for dwarf as
16826 they are not sharable. */
16827 reg
= gen_rtx_REG (SImode
, j
);
16828 tmp
= gen_rtx_SET (SImode
,
16831 plus_constant (Pmode
, stack_pointer_rtx
, 4 * i
)),
16834 tmp1
= gen_rtx_SET (SImode
,
16837 plus_constant (Pmode
, stack_pointer_rtx
, 4 * i
)),
16839 RTX_FRAME_RELATED_P (tmp
) = 1;
16840 RTX_FRAME_RELATED_P (tmp1
) = 1;
16842 if (((i
- (num_regs
% 2)) % 2) == 1)
16843 /* When (i - (num_regs % 2)) is odd, the RTX to be emitted is yet to
16844 be created. Hence create it first. The STRD pattern we are
16846 [ (SET (MEM (PLUS (SP) (NUM))) (reg_t1))
16847 (SET (MEM (PLUS (SP) (NUM + 4))) (reg_t2)) ]
16848 where the target registers need not be consecutive. */
16849 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
16851 /* Register R_j is added in PARALLEL RTX. If (i - (num_regs % 2)) is
16852 even, the reg_j is added as 0th element and if it is odd, reg_i is
16853 added as 1st element of STRD pattern shown above. */
16854 XVECEXP (par
, 0, ((i
- (num_regs
% 2)) % 2)) = tmp
;
16855 XVECEXP (dwarf
, 0, (i
+ 1)) = tmp1
;
16857 if (((i
- (num_regs
% 2)) % 2) == 0)
16858 /* When (i - (num_regs % 2)) is even, RTXs for both the registers
16859 to be loaded are generated in above given STRD pattern, and the
16860 pattern can be emitted now. */
16866 if ((num_regs
% 2) == 1)
16868 /* If odd number of registers are pushed, generate STR pattern to store
16870 for (; (saved_regs_mask
& (1 << j
)) == 0; j
--);
16872 tmp1
= gen_frame_mem (SImode
, plus_constant (Pmode
,
16873 stack_pointer_rtx
, 4 * i
));
16874 reg
= gen_rtx_REG (SImode
, j
);
16875 tmp
= gen_rtx_SET (SImode
, tmp1
, reg
);
16876 RTX_FRAME_RELATED_P (tmp
) = 1;
16880 tmp1
= gen_rtx_SET (SImode
,
16883 plus_constant (Pmode
, stack_pointer_rtx
, 4 * i
)),
16885 RTX_FRAME_RELATED_P (tmp1
) = 1;
16886 XVECEXP (dwarf
, 0, (i
+ 1)) = tmp1
;
16889 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
16890 RTX_FRAME_RELATED_P (insn
) = 1;
16894 /* STRD in ARM mode requires consecutive registers. This function emits STRD
16895 whenever possible, otherwise it emits single-word stores. The first store
16896 also allocates stack space for all saved registers, using writeback with
16897 post-addressing mode. All other stores use offset addressing. If no STRD
16898 can be emitted, this function emits a sequence of single-word stores,
16899 and not an STM as before, because single-word stores provide more freedom
16900 scheduling and can be turned into an STM by peephole optimizations. */
16902 arm_emit_strd_push (unsigned long saved_regs_mask
)
16905 int i
, j
, dwarf_index
= 0;
16907 rtx dwarf
= NULL_RTX
;
16908 rtx insn
= NULL_RTX
;
16911 /* TODO: A more efficient code can be emitted by changing the
16912 layout, e.g., first push all pairs that can use STRD to keep the
16913 stack aligned, and then push all other registers. */
16914 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
16915 if (saved_regs_mask
& (1 << i
))
16918 gcc_assert (!(saved_regs_mask
& (1 << SP_REGNUM
)));
16919 gcc_assert (!(saved_regs_mask
& (1 << PC_REGNUM
)));
16920 gcc_assert (num_regs
> 0);
16922 /* Create sequence for DWARF info. */
16923 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_regs
+ 1));
16925 /* For dwarf info, we generate explicit stack update. */
16926 tmp
= gen_rtx_SET (VOIDmode
,
16928 plus_constant (Pmode
, stack_pointer_rtx
, -4 * num_regs
));
16929 RTX_FRAME_RELATED_P (tmp
) = 1;
16930 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
16932 /* Save registers. */
16933 offset
= - 4 * num_regs
;
16935 while (j
<= LAST_ARM_REGNUM
)
16936 if (saved_regs_mask
& (1 << j
))
16939 && (saved_regs_mask
& (1 << (j
+ 1))))
16941 /* Current register and previous register form register pair for
16942 which STRD can be generated. */
16945 /* Allocate stack space for all saved registers. */
16946 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
16947 tmp
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, tmp
);
16948 mem
= gen_frame_mem (DImode
, tmp
);
16951 else if (offset
> 0)
16952 mem
= gen_frame_mem (DImode
,
16953 plus_constant (Pmode
,
16957 mem
= gen_frame_mem (DImode
, stack_pointer_rtx
);
16959 tmp
= gen_rtx_SET (DImode
, mem
, gen_rtx_REG (DImode
, j
));
16960 RTX_FRAME_RELATED_P (tmp
) = 1;
16961 tmp
= emit_insn (tmp
);
16963 /* Record the first store insn. */
16964 if (dwarf_index
== 1)
16967 /* Generate dwarf info. */
16968 mem
= gen_frame_mem (SImode
,
16969 plus_constant (Pmode
,
16972 tmp
= gen_rtx_SET (SImode
, mem
, gen_rtx_REG (SImode
, j
));
16973 RTX_FRAME_RELATED_P (tmp
) = 1;
16974 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
16976 mem
= gen_frame_mem (SImode
,
16977 plus_constant (Pmode
,
16980 tmp
= gen_rtx_SET (SImode
, mem
, gen_rtx_REG (SImode
, j
+ 1));
16981 RTX_FRAME_RELATED_P (tmp
) = 1;
16982 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
16989 /* Emit a single word store. */
16992 /* Allocate stack space for all saved registers. */
16993 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
16994 tmp
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, tmp
);
16995 mem
= gen_frame_mem (SImode
, tmp
);
16998 else if (offset
> 0)
16999 mem
= gen_frame_mem (SImode
,
17000 plus_constant (Pmode
,
17004 mem
= gen_frame_mem (SImode
, stack_pointer_rtx
);
17006 tmp
= gen_rtx_SET (SImode
, mem
, gen_rtx_REG (SImode
, j
));
17007 RTX_FRAME_RELATED_P (tmp
) = 1;
17008 tmp
= emit_insn (tmp
);
17010 /* Record the first store insn. */
17011 if (dwarf_index
== 1)
17014 /* Generate dwarf info. */
17015 mem
= gen_frame_mem (SImode
,
17016 plus_constant(Pmode
,
17019 tmp
= gen_rtx_SET (SImode
, mem
, gen_rtx_REG (SImode
, j
));
17020 RTX_FRAME_RELATED_P (tmp
) = 1;
17021 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
17030 /* Attach dwarf info to the first insn we generate. */
17031 gcc_assert (insn
!= NULL_RTX
);
17032 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
17033 RTX_FRAME_RELATED_P (insn
) = 1;
17036 /* Generate and emit an insn that we will recognize as a push_multi.
17037 Unfortunately, since this insn does not reflect very well the actual
17038 semantics of the operation, we need to annotate the insn for the benefit
17039 of DWARF2 frame unwind information. */
17041 emit_multi_reg_push (unsigned long mask
)
17044 int num_dwarf_regs
;
17048 int dwarf_par_index
;
17051 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
17052 if (mask
& (1 << i
))
17055 gcc_assert (num_regs
&& num_regs
<= 16);
17057 /* We don't record the PC in the dwarf frame information. */
17058 num_dwarf_regs
= num_regs
;
17059 if (mask
& (1 << PC_REGNUM
))
17062 /* For the body of the insn we are going to generate an UNSPEC in
17063 parallel with several USEs. This allows the insn to be recognized
17064 by the push_multi pattern in the arm.md file.
17066 The body of the insn looks something like this:
17069 (set (mem:BLK (pre_modify:SI (reg:SI sp)
17070 (const_int:SI <num>)))
17071 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
17077 For the frame note however, we try to be more explicit and actually
17078 show each register being stored into the stack frame, plus a (single)
17079 decrement of the stack pointer. We do it this way in order to be
17080 friendly to the stack unwinding code, which only wants to see a single
17081 stack decrement per instruction. The RTL we generate for the note looks
17082 something like this:
17085 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
17086 (set (mem:SI (reg:SI sp)) (reg:SI r4))
17087 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX))
17088 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY))
17092 FIXME:: In an ideal world the PRE_MODIFY would not exist and
17093 instead we'd have a parallel expression detailing all
17094 the stores to the various memory addresses so that debug
17095 information is more up-to-date. Remember however while writing
17096 this to take care of the constraints with the push instruction.
17098 Note also that this has to be taken care of for the VFP registers.
17100 For more see PR43399. */
17102 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
17103 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
17104 dwarf_par_index
= 1;
17106 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
17108 if (mask
& (1 << i
))
17110 reg
= gen_rtx_REG (SImode
, i
);
17112 XVECEXP (par
, 0, 0)
17113 = gen_rtx_SET (VOIDmode
,
17116 gen_rtx_PRE_MODIFY (Pmode
,
17119 (Pmode
, stack_pointer_rtx
,
17122 gen_rtx_UNSPEC (BLKmode
,
17123 gen_rtvec (1, reg
),
17124 UNSPEC_PUSH_MULT
));
17126 if (i
!= PC_REGNUM
)
17128 tmp
= gen_rtx_SET (VOIDmode
,
17129 gen_frame_mem (SImode
, stack_pointer_rtx
),
17131 RTX_FRAME_RELATED_P (tmp
) = 1;
17132 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
17140 for (j
= 1, i
++; j
< num_regs
; i
++)
17142 if (mask
& (1 << i
))
17144 reg
= gen_rtx_REG (SImode
, i
);
17146 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
17148 if (i
!= PC_REGNUM
)
17151 = gen_rtx_SET (VOIDmode
,
17154 plus_constant (Pmode
, stack_pointer_rtx
,
17157 RTX_FRAME_RELATED_P (tmp
) = 1;
17158 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
17165 par
= emit_insn (par
);
17167 tmp
= gen_rtx_SET (VOIDmode
,
17169 plus_constant (Pmode
, stack_pointer_rtx
, -4 * num_regs
));
17170 RTX_FRAME_RELATED_P (tmp
) = 1;
17171 XVECEXP (dwarf
, 0, 0) = tmp
;
17173 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
17178 /* Add a REG_CFA_ADJUST_CFA REG note to INSN.
17179 SIZE is the offset to be adjusted.
17180 DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx. */
17182 arm_add_cfa_adjust_cfa_note (rtx insn
, int size
, rtx dest
, rtx src
)
17186 RTX_FRAME_RELATED_P (insn
) = 1;
17187 dwarf
= gen_rtx_SET (VOIDmode
, dest
, plus_constant (Pmode
, src
, size
));
17188 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, dwarf
);
17191 /* Generate and emit an insn pattern that we will recognize as a pop_multi.
17192 SAVED_REGS_MASK shows which registers need to be restored.
17194 Unfortunately, since this insn does not reflect very well the actual
17195 semantics of the operation, we need to annotate the insn for the benefit
17196 of DWARF2 frame unwind information. */
17198 arm_emit_multi_reg_pop (unsigned long saved_regs_mask
)
17203 rtx dwarf
= NULL_RTX
;
17209 return_in_pc
= (saved_regs_mask
& (1 << PC_REGNUM
)) ? true : false;
17210 offset_adj
= return_in_pc
? 1 : 0;
17211 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
17212 if (saved_regs_mask
& (1 << i
))
17215 gcc_assert (num_regs
&& num_regs
<= 16);
17217 /* If SP is in reglist, then we don't emit SP update insn. */
17218 emit_update
= (saved_regs_mask
& (1 << SP_REGNUM
)) ? 0 : 1;
17220 /* The parallel needs to hold num_regs SETs
17221 and one SET for the stack update. */
17222 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
+ emit_update
+ offset_adj
));
17227 XVECEXP (par
, 0, 0) = tmp
;
17232 /* Increment the stack pointer, based on there being
17233 num_regs 4-byte registers to restore. */
17234 tmp
= gen_rtx_SET (VOIDmode
,
17236 plus_constant (Pmode
,
17239 RTX_FRAME_RELATED_P (tmp
) = 1;
17240 XVECEXP (par
, 0, offset_adj
) = tmp
;
17243 /* Now restore every reg, which may include PC. */
17244 for (j
= 0, i
= 0; j
< num_regs
; i
++)
17245 if (saved_regs_mask
& (1 << i
))
17247 reg
= gen_rtx_REG (SImode
, i
);
17248 if ((num_regs
== 1) && emit_update
&& !return_in_pc
)
17250 /* Emit single load with writeback. */
17251 tmp
= gen_frame_mem (SImode
,
17252 gen_rtx_POST_INC (Pmode
,
17253 stack_pointer_rtx
));
17254 tmp
= emit_insn (gen_rtx_SET (VOIDmode
, reg
, tmp
));
17255 REG_NOTES (tmp
) = alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
17259 tmp
= gen_rtx_SET (VOIDmode
,
17263 plus_constant (Pmode
, stack_pointer_rtx
, 4 * j
)));
17264 RTX_FRAME_RELATED_P (tmp
) = 1;
17265 XVECEXP (par
, 0, j
+ emit_update
+ offset_adj
) = tmp
;
17267 /* We need to maintain a sequence for DWARF info too. As dwarf info
17268 should not have PC, skip PC. */
17269 if (i
!= PC_REGNUM
)
17270 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
17276 par
= emit_jump_insn (par
);
17278 par
= emit_insn (par
);
17280 REG_NOTES (par
) = dwarf
;
17282 arm_add_cfa_adjust_cfa_note (par
, UNITS_PER_WORD
* num_regs
,
17283 stack_pointer_rtx
, stack_pointer_rtx
);
17286 /* Generate and emit an insn pattern that we will recognize as a pop_multi
17287 of NUM_REGS consecutive VFP regs, starting at FIRST_REG.
17289 Unfortunately, since this insn does not reflect very well the actual
17290 semantics of the operation, we need to annotate the insn for the benefit
17291 of DWARF2 frame unwind information. */
17293 arm_emit_vfp_multi_reg_pop (int first_reg
, int num_regs
, rtx base_reg
)
17297 rtx dwarf
= NULL_RTX
;
17300 gcc_assert (num_regs
&& num_regs
<= 32);
17302 /* Workaround ARM10 VFPr1 bug. */
17303 if (num_regs
== 2 && !arm_arch6
)
17305 if (first_reg
== 15)
17311 /* We can emit at most 16 D-registers in a single pop_multi instruction, and
17312 there could be up to 32 D-registers to restore.
17313 If there are more than 16 D-registers, make two recursive calls,
17314 each of which emits one pop_multi instruction. */
17317 arm_emit_vfp_multi_reg_pop (first_reg
, 16, base_reg
);
17318 arm_emit_vfp_multi_reg_pop (first_reg
+ 16, num_regs
- 16, base_reg
);
17322 /* The parallel needs to hold num_regs SETs
17323 and one SET for the stack update. */
17324 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
+ 1));
17326 /* Increment the stack pointer, based on there being
17327 num_regs 8-byte registers to restore. */
17328 tmp
= gen_rtx_SET (VOIDmode
,
17330 plus_constant (Pmode
, base_reg
, 8 * num_regs
));
17331 RTX_FRAME_RELATED_P (tmp
) = 1;
17332 XVECEXP (par
, 0, 0) = tmp
;
17334 /* Now show every reg that will be restored, using a SET for each. */
17335 for (j
= 0, i
=first_reg
; j
< num_regs
; i
+= 2)
17337 reg
= gen_rtx_REG (DFmode
, i
);
17339 tmp
= gen_rtx_SET (VOIDmode
,
17343 plus_constant (Pmode
, base_reg
, 8 * j
)));
17344 RTX_FRAME_RELATED_P (tmp
) = 1;
17345 XVECEXP (par
, 0, j
+ 1) = tmp
;
17347 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
17352 par
= emit_insn (par
);
17353 REG_NOTES (par
) = dwarf
;
17355 arm_add_cfa_adjust_cfa_note (par
, 2 * UNITS_PER_WORD
* num_regs
,
17356 base_reg
, base_reg
);
17359 /* Generate and emit a pattern that will be recognized as LDRD pattern. If even
17360 number of registers are being popped, multiple LDRD patterns are created for
17361 all register pairs. If odd number of registers are popped, last register is
17362 loaded by using LDR pattern. */
17364 thumb2_emit_ldrd_pop (unsigned long saved_regs_mask
)
17368 rtx par
= NULL_RTX
;
17369 rtx dwarf
= NULL_RTX
;
17370 rtx tmp
, reg
, tmp1
;
17373 return_in_pc
= (saved_regs_mask
& (1 << PC_REGNUM
)) ? true : false;
17374 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
17375 if (saved_regs_mask
& (1 << i
))
17378 gcc_assert (num_regs
&& num_regs
<= 16);
17380 /* We cannot generate ldrd for PC. Hence, reduce the count if PC is
17381 to be popped. So, if num_regs is even, now it will become odd,
17382 and we can generate pop with PC. If num_regs is odd, it will be
17383 even now, and ldr with return can be generated for PC. */
17387 gcc_assert (!(saved_regs_mask
& (1 << SP_REGNUM
)));
17389 /* Var j iterates over all the registers to gather all the registers in
17390 saved_regs_mask. Var i gives index of saved registers in stack frame.
17391 A PARALLEL RTX of register-pair is created here, so that pattern for
17392 LDRD can be matched. As PC is always last register to be popped, and
17393 we have already decremented num_regs if PC, we don't have to worry
17394 about PC in this loop. */
17395 for (i
= 0, j
= 0; i
< (num_regs
- (num_regs
% 2)); j
++)
17396 if (saved_regs_mask
& (1 << j
))
17398 /* Create RTX for memory load. */
17399 reg
= gen_rtx_REG (SImode
, j
);
17400 tmp
= gen_rtx_SET (SImode
,
17402 gen_frame_mem (SImode
,
17403 plus_constant (Pmode
,
17404 stack_pointer_rtx
, 4 * i
)));
17405 RTX_FRAME_RELATED_P (tmp
) = 1;
17409 /* When saved-register index (i) is even, the RTX to be emitted is
17410 yet to be created. Hence create it first. The LDRD pattern we
17411 are generating is :
17412 [ (SET (reg_t0) (MEM (PLUS (SP) (NUM))))
17413 (SET (reg_t1) (MEM (PLUS (SP) (NUM + 4)))) ]
17414 where target registers need not be consecutive. */
17415 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
17419 /* ith register is added in PARALLEL RTX. If i is even, the reg_i is
17420 added as 0th element and if i is odd, reg_i is added as 1st element
17421 of LDRD pattern shown above. */
17422 XVECEXP (par
, 0, (i
% 2)) = tmp
;
17423 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
17427 /* When saved-register index (i) is odd, RTXs for both the registers
17428 to be loaded are generated in above given LDRD pattern, and the
17429 pattern can be emitted now. */
17430 par
= emit_insn (par
);
17431 REG_NOTES (par
) = dwarf
;
17432 RTX_FRAME_RELATED_P (par
) = 1;
17438 /* If the number of registers pushed is odd AND return_in_pc is false OR
17439 number of registers are even AND return_in_pc is true, last register is
17440 popped using LDR. It can be PC as well. Hence, adjust the stack first and
17441 then LDR with post increment. */
17443 /* Increment the stack pointer, based on there being
17444 num_regs 4-byte registers to restore. */
17445 tmp
= gen_rtx_SET (VOIDmode
,
17447 plus_constant (Pmode
, stack_pointer_rtx
, 4 * i
));
17448 RTX_FRAME_RELATED_P (tmp
) = 1;
17449 tmp
= emit_insn (tmp
);
17452 arm_add_cfa_adjust_cfa_note (tmp
, UNITS_PER_WORD
* i
,
17453 stack_pointer_rtx
, stack_pointer_rtx
);
17458 if (((num_regs
% 2) == 1 && !return_in_pc
)
17459 || ((num_regs
% 2) == 0 && return_in_pc
))
17461 /* Scan for the single register to be popped. Skip until the saved
17462 register is found. */
17463 for (; (saved_regs_mask
& (1 << j
)) == 0; j
++);
17465 /* Gen LDR with post increment here. */
17466 tmp1
= gen_rtx_MEM (SImode
,
17467 gen_rtx_POST_INC (SImode
,
17468 stack_pointer_rtx
));
17469 set_mem_alias_set (tmp1
, get_frame_alias_set ());
17471 reg
= gen_rtx_REG (SImode
, j
);
17472 tmp
= gen_rtx_SET (SImode
, reg
, tmp1
);
17473 RTX_FRAME_RELATED_P (tmp
) = 1;
17474 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
17478 /* If return_in_pc, j must be PC_REGNUM. */
17479 gcc_assert (j
== PC_REGNUM
);
17480 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
17481 XVECEXP (par
, 0, 0) = ret_rtx
;
17482 XVECEXP (par
, 0, 1) = tmp
;
17483 par
= emit_jump_insn (par
);
17487 par
= emit_insn (tmp
);
17488 REG_NOTES (par
) = dwarf
;
17489 arm_add_cfa_adjust_cfa_note (par
, UNITS_PER_WORD
,
17490 stack_pointer_rtx
, stack_pointer_rtx
);
17494 else if ((num_regs
% 2) == 1 && return_in_pc
)
17496 /* There are 2 registers to be popped. So, generate the pattern
17497 pop_multiple_with_stack_update_and_return to pop in PC. */
17498 arm_emit_multi_reg_pop (saved_regs_mask
& (~((1 << j
) - 1)));
17504 /* LDRD in ARM mode needs consecutive registers as operands. This function
17505 emits LDRD whenever possible, otherwise it emits single-word loads. It uses
17506 offset addressing and then generates one separate stack udpate. This provides
17507 more scheduling freedom, compared to writeback on every load. However,
17508 if the function returns using load into PC directly
17509 (i.e., if PC is in SAVED_REGS_MASK), the stack needs to be updated
17510 before the last load. TODO: Add a peephole optimization to recognize
17511 the new epilogue sequence as an LDM instruction whenever possible. TODO: Add
17512 peephole optimization to merge the load at stack-offset zero
17513 with the stack update instruction using load with writeback
17514 in post-index addressing mode. */
17516 arm_emit_ldrd_pop (unsigned long saved_regs_mask
)
17520 rtx par
= NULL_RTX
;
17521 rtx dwarf
= NULL_RTX
;
17524 /* Restore saved registers. */
17525 gcc_assert (!((saved_regs_mask
& (1 << SP_REGNUM
))));
17527 while (j
<= LAST_ARM_REGNUM
)
17528 if (saved_regs_mask
& (1 << j
))
17531 && (saved_regs_mask
& (1 << (j
+ 1)))
17532 && (j
+ 1) != PC_REGNUM
)
17534 /* Current register and next register form register pair for which
17535 LDRD can be generated. PC is always the last register popped, and
17536 we handle it separately. */
17538 mem
= gen_frame_mem (DImode
,
17539 plus_constant (Pmode
,
17543 mem
= gen_frame_mem (DImode
, stack_pointer_rtx
);
17545 tmp
= gen_rtx_SET (DImode
, gen_rtx_REG (DImode
, j
), mem
);
17546 RTX_FRAME_RELATED_P (tmp
) = 1;
17547 tmp
= emit_insn (tmp
);
17549 /* Generate dwarf info. */
17551 dwarf
= alloc_reg_note (REG_CFA_RESTORE
,
17552 gen_rtx_REG (SImode
, j
),
17554 dwarf
= alloc_reg_note (REG_CFA_RESTORE
,
17555 gen_rtx_REG (SImode
, j
+ 1),
17558 REG_NOTES (tmp
) = dwarf
;
17563 else if (j
!= PC_REGNUM
)
17565 /* Emit a single word load. */
17567 mem
= gen_frame_mem (SImode
,
17568 plus_constant (Pmode
,
17572 mem
= gen_frame_mem (SImode
, stack_pointer_rtx
);
17574 tmp
= gen_rtx_SET (SImode
, gen_rtx_REG (SImode
, j
), mem
);
17575 RTX_FRAME_RELATED_P (tmp
) = 1;
17576 tmp
= emit_insn (tmp
);
17578 /* Generate dwarf info. */
17579 REG_NOTES (tmp
) = alloc_reg_note (REG_CFA_RESTORE
,
17580 gen_rtx_REG (SImode
, j
),
17586 else /* j == PC_REGNUM */
17592 /* Update the stack. */
17595 tmp
= gen_rtx_SET (Pmode
,
17597 plus_constant (Pmode
,
17600 RTX_FRAME_RELATED_P (tmp
) = 1;
17605 if (saved_regs_mask
& (1 << PC_REGNUM
))
17607 /* Only PC is to be popped. */
17608 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
17609 XVECEXP (par
, 0, 0) = ret_rtx
;
17610 tmp
= gen_rtx_SET (SImode
,
17611 gen_rtx_REG (SImode
, PC_REGNUM
),
17612 gen_frame_mem (SImode
,
17613 gen_rtx_POST_INC (SImode
,
17614 stack_pointer_rtx
)));
17615 RTX_FRAME_RELATED_P (tmp
) = 1;
17616 XVECEXP (par
, 0, 1) = tmp
;
17617 par
= emit_jump_insn (par
);
17619 /* Generate dwarf info. */
17620 dwarf
= alloc_reg_note (REG_CFA_RESTORE
,
17621 gen_rtx_REG (SImode
, PC_REGNUM
),
17623 REG_NOTES (par
) = dwarf
;
17627 /* Calculate the size of the return value that is passed in registers. */
17629 arm_size_return_regs (void)
17631 enum machine_mode mode
;
17633 if (crtl
->return_rtx
!= 0)
17634 mode
= GET_MODE (crtl
->return_rtx
);
17636 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
17638 return GET_MODE_SIZE (mode
);
17641 /* Return true if the current function needs to save/restore LR. */
17643 thumb_force_lr_save (void)
17645 return !cfun
->machine
->lr_save_eliminated
17646 && (!leaf_function_p ()
17647 || thumb_far_jump_used_p ()
17648 || df_regs_ever_live_p (LR_REGNUM
));
17651 /* We do not know if r3 will be available because
17652 we do have an indirect tailcall happening in this
17653 particular case. */
17655 is_indirect_tailcall_p (rtx call
)
17657 rtx pat
= PATTERN (call
);
17659 /* Indirect tail call. */
17660 pat
= XVECEXP (pat
, 0, 0);
17661 if (GET_CODE (pat
) == SET
)
17662 pat
= SET_SRC (pat
);
17664 pat
= XEXP (XEXP (pat
, 0), 0);
17665 return REG_P (pat
);
17668 /* Return true if r3 is used by any of the tail call insns in the
17669 current function. */
17671 any_sibcall_could_use_r3 (void)
17676 if (!crtl
->tail_call_emit
)
17678 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
17679 if (e
->flags
& EDGE_SIBCALL
)
17681 rtx call
= BB_END (e
->src
);
17682 if (!CALL_P (call
))
17683 call
= prev_nonnote_nondebug_insn (call
);
17684 gcc_assert (CALL_P (call
) && SIBLING_CALL_P (call
));
17685 if (find_regno_fusage (call
, USE
, 3)
17686 || is_indirect_tailcall_p (call
))
17693 /* Compute the distance from register FROM to register TO.
17694 These can be the arg pointer (26), the soft frame pointer (25),
17695 the stack pointer (13) or the hard frame pointer (11).
17696 In thumb mode r7 is used as the soft frame pointer, if needed.
17697 Typical stack layout looks like this:
17699 old stack pointer -> | |
17702 | | saved arguments for
17703 | | vararg functions
17706 hard FP & arg pointer -> | | \
17714 soft frame pointer -> | | /
17719 locals base pointer -> | | /
17724 current stack pointer -> | | /
17727 For a given function some or all of these stack components
17728 may not be needed, giving rise to the possibility of
17729 eliminating some of the registers.
17731 The values returned by this function must reflect the behavior
17732 of arm_expand_prologue() and arm_compute_save_reg_mask().
17734 The sign of the number returned reflects the direction of stack
17735 growth, so the values are positive for all eliminations except
17736 from the soft frame pointer to the hard frame pointer.
17738 SFP may point just inside the local variables block to ensure correct
17742 /* Calculate stack offsets. These are used to calculate register elimination
17743 offsets and in prologue/epilogue code. Also calculates which registers
17744 should be saved. */
17746 static arm_stack_offsets
*
17747 arm_get_frame_offsets (void)
17749 struct arm_stack_offsets
*offsets
;
17750 unsigned long func_type
;
17754 HOST_WIDE_INT frame_size
;
17757 offsets
= &cfun
->machine
->stack_offsets
;
17759 /* We need to know if we are a leaf function. Unfortunately, it
17760 is possible to be called after start_sequence has been called,
17761 which causes get_insns to return the insns for the sequence,
17762 not the function, which will cause leaf_function_p to return
17763 the incorrect result.
17765 to know about leaf functions once reload has completed, and the
17766 frame size cannot be changed after that time, so we can safely
17767 use the cached value. */
17769 if (reload_completed
)
17772 /* Initially this is the size of the local variables. It will translated
17773 into an offset once we have determined the size of preceding data. */
17774 frame_size
= ROUND_UP_WORD (get_frame_size ());
17776 leaf
= leaf_function_p ();
17778 /* Space for variadic functions. */
17779 offsets
->saved_args
= crtl
->args
.pretend_args_size
;
17781 /* In Thumb mode this is incorrect, but never used. */
17782 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0) +
17783 arm_compute_static_chain_stack_bytes();
17787 unsigned int regno
;
17789 offsets
->saved_regs_mask
= arm_compute_save_reg_mask ();
17790 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
17791 saved
= core_saved
;
17793 /* We know that SP will be doubleword aligned on entry, and we must
17794 preserve that condition at any subroutine call. We also require the
17795 soft frame pointer to be doubleword aligned. */
17797 if (TARGET_REALLY_IWMMXT
)
17799 /* Check for the call-saved iWMMXt registers. */
17800 for (regno
= FIRST_IWMMXT_REGNUM
;
17801 regno
<= LAST_IWMMXT_REGNUM
;
17803 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
17807 func_type
= arm_current_func_type ();
17808 /* Space for saved VFP registers. */
17809 if (! IS_VOLATILE (func_type
)
17810 && TARGET_HARD_FLOAT
&& TARGET_VFP
)
17811 saved
+= arm_get_vfp_saved_size ();
17813 else /* TARGET_THUMB1 */
17815 offsets
->saved_regs_mask
= thumb1_compute_save_reg_mask ();
17816 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
17817 saved
= core_saved
;
17818 if (TARGET_BACKTRACE
)
17822 /* Saved registers include the stack frame. */
17823 offsets
->saved_regs
= offsets
->saved_args
+ saved
+
17824 arm_compute_static_chain_stack_bytes();
17825 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
17826 /* A leaf function does not need any stack alignment if it has nothing
17828 if (leaf
&& frame_size
== 0
17829 /* However if it calls alloca(), we have a dynamically allocated
17830 block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
17831 && ! cfun
->calls_alloca
)
17833 offsets
->outgoing_args
= offsets
->soft_frame
;
17834 offsets
->locals_base
= offsets
->soft_frame
;
17838 /* Ensure SFP has the correct alignment. */
17839 if (ARM_DOUBLEWORD_ALIGN
17840 && (offsets
->soft_frame
& 7))
17842 offsets
->soft_frame
+= 4;
17843 /* Try to align stack by pushing an extra reg. Don't bother doing this
17844 when there is a stack frame as the alignment will be rolled into
17845 the normal stack adjustment. */
17846 if (frame_size
+ crtl
->outgoing_args_size
== 0)
17850 /* If it is safe to use r3, then do so. This sometimes
17851 generates better code on Thumb-2 by avoiding the need to
17852 use 32-bit push/pop instructions. */
17853 if (! any_sibcall_could_use_r3 ()
17854 && arm_size_return_regs () <= 12
17855 && (offsets
->saved_regs_mask
& (1 << 3)) == 0
17856 && (TARGET_THUMB2
|| !current_tune
->prefer_ldrd_strd
))
17861 for (i
= 4; i
<= (TARGET_THUMB1
? LAST_LO_REGNUM
: 11); i
++)
17863 /* Avoid fixed registers; they may be changed at
17864 arbitrary times so it's unsafe to restore them
17865 during the epilogue. */
17867 && (offsets
->saved_regs_mask
& (1 << i
)) == 0)
17876 offsets
->saved_regs
+= 4;
17877 offsets
->saved_regs_mask
|= (1 << reg
);
17882 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
17883 offsets
->outgoing_args
= (offsets
->locals_base
17884 + crtl
->outgoing_args_size
);
17886 if (ARM_DOUBLEWORD_ALIGN
)
17888 /* Ensure SP remains doubleword aligned. */
17889 if (offsets
->outgoing_args
& 7)
17890 offsets
->outgoing_args
+= 4;
17891 gcc_assert (!(offsets
->outgoing_args
& 7));
17898 /* Calculate the relative offsets for the different stack pointers. Positive
17899 offsets are in the direction of stack growth. */
17902 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
17904 arm_stack_offsets
*offsets
;
17906 offsets
= arm_get_frame_offsets ();
17908 /* OK, now we have enough information to compute the distances.
17909 There must be an entry in these switch tables for each pair
17910 of registers in ELIMINABLE_REGS, even if some of the entries
17911 seem to be redundant or useless. */
17914 case ARG_POINTER_REGNUM
:
17917 case THUMB_HARD_FRAME_POINTER_REGNUM
:
17920 case FRAME_POINTER_REGNUM
:
17921 /* This is the reverse of the soft frame pointer
17922 to hard frame pointer elimination below. */
17923 return offsets
->soft_frame
- offsets
->saved_args
;
17925 case ARM_HARD_FRAME_POINTER_REGNUM
:
17926 /* This is only non-zero in the case where the static chain register
17927 is stored above the frame. */
17928 return offsets
->frame
- offsets
->saved_args
- 4;
17930 case STACK_POINTER_REGNUM
:
17931 /* If nothing has been pushed on the stack at all
17932 then this will return -4. This *is* correct! */
17933 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
17936 gcc_unreachable ();
17938 gcc_unreachable ();
17940 case FRAME_POINTER_REGNUM
:
17943 case THUMB_HARD_FRAME_POINTER_REGNUM
:
17946 case ARM_HARD_FRAME_POINTER_REGNUM
:
17947 /* The hard frame pointer points to the top entry in the
17948 stack frame. The soft frame pointer to the bottom entry
17949 in the stack frame. If there is no stack frame at all,
17950 then they are identical. */
17952 return offsets
->frame
- offsets
->soft_frame
;
17954 case STACK_POINTER_REGNUM
:
17955 return offsets
->outgoing_args
- offsets
->soft_frame
;
17958 gcc_unreachable ();
17960 gcc_unreachable ();
17963 /* You cannot eliminate from the stack pointer.
17964 In theory you could eliminate from the hard frame
17965 pointer to the stack pointer, but this will never
17966 happen, since if a stack frame is not needed the
17967 hard frame pointer will never be used. */
17968 gcc_unreachable ();
17972 /* Given FROM and TO register numbers, say whether this elimination is
17973 allowed. Frame pointer elimination is automatically handled.
17975 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
17976 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
17977 pointer, we must eliminate FRAME_POINTER_REGNUM into
17978 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
17979 ARG_POINTER_REGNUM. */
17982 arm_can_eliminate (const int from
, const int to
)
17984 return ((to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
) ? false :
17985 (to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
) ? false :
17986 (to
== ARM_HARD_FRAME_POINTER_REGNUM
&& TARGET_THUMB
) ? false :
17987 (to
== THUMB_HARD_FRAME_POINTER_REGNUM
&& TARGET_ARM
) ? false :
17991 /* Emit RTL to save coprocessor registers on function entry. Returns the
17992 number of bytes pushed. */
17995 arm_save_coproc_regs(void)
17997 int saved_size
= 0;
17999 unsigned start_reg
;
18002 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
18003 if (df_regs_ever_live_p (reg
) && ! call_used_regs
[reg
])
18005 insn
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
18006 insn
= gen_rtx_MEM (V2SImode
, insn
);
18007 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
18008 RTX_FRAME_RELATED_P (insn
) = 1;
18012 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
18014 start_reg
= FIRST_VFP_REGNUM
;
18016 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
18018 if ((!df_regs_ever_live_p (reg
) || call_used_regs
[reg
])
18019 && (!df_regs_ever_live_p (reg
+ 1) || call_used_regs
[reg
+ 1]))
18021 if (start_reg
!= reg
)
18022 saved_size
+= vfp_emit_fstmd (start_reg
,
18023 (reg
- start_reg
) / 2);
18024 start_reg
= reg
+ 2;
18027 if (start_reg
!= reg
)
18028 saved_size
+= vfp_emit_fstmd (start_reg
,
18029 (reg
- start_reg
) / 2);
18035 /* Set the Thumb frame pointer from the stack pointer. */
18038 thumb_set_frame_pointer (arm_stack_offsets
*offsets
)
18040 HOST_WIDE_INT amount
;
18043 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
18045 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
18046 stack_pointer_rtx
, GEN_INT (amount
)));
18049 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
18050 /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1
18051 expects the first two operands to be the same. */
18054 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
18056 hard_frame_pointer_rtx
));
18060 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
18061 hard_frame_pointer_rtx
,
18062 stack_pointer_rtx
));
18064 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
18065 plus_constant (Pmode
, stack_pointer_rtx
, amount
));
18066 RTX_FRAME_RELATED_P (dwarf
) = 1;
18067 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
18070 RTX_FRAME_RELATED_P (insn
) = 1;
18073 /* Generate the prologue instructions for entry into an ARM or Thumb-2
18076 arm_expand_prologue (void)
18081 unsigned long live_regs_mask
;
18082 unsigned long func_type
;
18084 int saved_pretend_args
= 0;
18085 int saved_regs
= 0;
18086 unsigned HOST_WIDE_INT args_to_push
;
18087 arm_stack_offsets
*offsets
;
18089 func_type
= arm_current_func_type ();
18091 /* Naked functions don't have prologues. */
18092 if (IS_NAKED (func_type
))
18095 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
18096 args_to_push
= crtl
->args
.pretend_args_size
;
18098 /* Compute which register we will have to save onto the stack. */
18099 offsets
= arm_get_frame_offsets ();
18100 live_regs_mask
= offsets
->saved_regs_mask
;
18102 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
18104 if (IS_STACKALIGN (func_type
))
18108 /* Handle a word-aligned stack pointer. We generate the following:
18113 <save and restore r0 in normal prologue/epilogue>
18117 The unwinder doesn't need to know about the stack realignment.
18118 Just tell it we saved SP in r0. */
18119 gcc_assert (TARGET_THUMB2
&& !arm_arch_notm
&& args_to_push
== 0);
18121 r0
= gen_rtx_REG (SImode
, 0);
18122 r1
= gen_rtx_REG (SImode
, 1);
18124 insn
= emit_insn (gen_movsi (r0
, stack_pointer_rtx
));
18125 RTX_FRAME_RELATED_P (insn
) = 1;
18126 add_reg_note (insn
, REG_CFA_REGISTER
, NULL
);
18128 emit_insn (gen_andsi3 (r1
, r0
, GEN_INT (~(HOST_WIDE_INT
)7)));
18130 /* ??? The CFA changes here, which may cause GDB to conclude that it
18131 has entered a different function. That said, the unwind info is
18132 correct, individually, before and after this instruction because
18133 we've described the save of SP, which will override the default
18134 handling of SP as restoring from the CFA. */
18135 emit_insn (gen_movsi (stack_pointer_rtx
, r1
));
18138 /* For APCS frames, if IP register is clobbered
18139 when creating frame, save that register in a special
18141 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
18143 if (IS_INTERRUPT (func_type
))
18145 /* Interrupt functions must not corrupt any registers.
18146 Creating a frame pointer however, corrupts the IP
18147 register, so we must push it first. */
18148 emit_multi_reg_push (1 << IP_REGNUM
);
18150 /* Do not set RTX_FRAME_RELATED_P on this insn.
18151 The dwarf stack unwinding code only wants to see one
18152 stack decrement per function, and this is not it. If
18153 this instruction is labeled as being part of the frame
18154 creation sequence then dwarf2out_frame_debug_expr will
18155 die when it encounters the assignment of IP to FP
18156 later on, since the use of SP here establishes SP as
18157 the CFA register and not IP.
18159 Anyway this instruction is not really part of the stack
18160 frame creation although it is part of the prologue. */
18162 else if (IS_NESTED (func_type
))
18164 /* The static chain register is the same as the IP register
18165 used as a scratch register during stack frame creation.
18166 To get around this need to find somewhere to store IP
18167 whilst the frame is being created. We try the following
18170 1. The last argument register r3.
18171 2. A slot on the stack above the frame. (This only
18172 works if the function is not a varargs function).
18173 3. Register r3 again, after pushing the argument registers
18176 Note - we only need to tell the dwarf2 backend about the SP
18177 adjustment in the second variant; the static chain register
18178 doesn't need to be unwound, as it doesn't contain a value
18179 inherited from the caller. */
18181 if (!arm_r3_live_at_start_p ())
18182 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
18183 else if (args_to_push
== 0)
18187 gcc_assert(arm_compute_static_chain_stack_bytes() == 4);
18190 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
18191 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
18194 /* Just tell the dwarf backend that we adjusted SP. */
18195 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
18196 plus_constant (Pmode
, stack_pointer_rtx
,
18198 RTX_FRAME_RELATED_P (insn
) = 1;
18199 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
18203 /* Store the args on the stack. */
18204 if (cfun
->machine
->uses_anonymous_args
)
18205 insn
= emit_multi_reg_push
18206 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
18209 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
18210 GEN_INT (- args_to_push
)));
18212 RTX_FRAME_RELATED_P (insn
) = 1;
18214 saved_pretend_args
= 1;
18215 fp_offset
= args_to_push
;
18218 /* Now reuse r3 to preserve IP. */
18219 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
18223 insn
= emit_set_insn (ip_rtx
,
18224 plus_constant (Pmode
, stack_pointer_rtx
,
18226 RTX_FRAME_RELATED_P (insn
) = 1;
18231 /* Push the argument registers, or reserve space for them. */
18232 if (cfun
->machine
->uses_anonymous_args
)
18233 insn
= emit_multi_reg_push
18234 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
18237 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
18238 GEN_INT (- args_to_push
)));
18239 RTX_FRAME_RELATED_P (insn
) = 1;
18242 /* If this is an interrupt service routine, and the link register
18243 is going to be pushed, and we're not generating extra
18244 push of IP (needed when frame is needed and frame layout if apcs),
18245 subtracting four from LR now will mean that the function return
18246 can be done with a single instruction. */
18247 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
18248 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
18249 && !(frame_pointer_needed
&& TARGET_APCS_FRAME
)
18252 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
18254 emit_set_insn (lr
, plus_constant (SImode
, lr
, -4));
18257 if (live_regs_mask
)
18259 saved_regs
+= bit_count (live_regs_mask
) * 4;
18260 if (optimize_size
&& !frame_pointer_needed
18261 && saved_regs
== offsets
->saved_regs
- offsets
->saved_args
)
18263 /* If no coprocessor registers are being pushed and we don't have
18264 to worry about a frame pointer then push extra registers to
18265 create the stack frame. This is done is a way that does not
18266 alter the frame layout, so is independent of the epilogue. */
18270 while (n
< 8 && (live_regs_mask
& (1 << n
)) == 0)
18272 frame
= offsets
->outgoing_args
- (offsets
->saved_args
+ saved_regs
);
18273 if (frame
&& n
* 4 >= frame
)
18276 live_regs_mask
|= (1 << n
) - 1;
18277 saved_regs
+= frame
;
18281 if (current_tune
->prefer_ldrd_strd
18282 && !optimize_function_for_size_p (cfun
))
18286 thumb2_emit_strd_push (live_regs_mask
);
18288 else if (TARGET_ARM
18289 && !TARGET_APCS_FRAME
18290 && !IS_INTERRUPT (func_type
))
18292 arm_emit_strd_push (live_regs_mask
);
18296 insn
= emit_multi_reg_push (live_regs_mask
);
18297 RTX_FRAME_RELATED_P (insn
) = 1;
18302 insn
= emit_multi_reg_push (live_regs_mask
);
18303 RTX_FRAME_RELATED_P (insn
) = 1;
18307 if (! IS_VOLATILE (func_type
))
18308 saved_regs
+= arm_save_coproc_regs ();
18310 if (frame_pointer_needed
&& TARGET_ARM
)
18312 /* Create the new frame pointer. */
18313 if (TARGET_APCS_FRAME
)
18315 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
18316 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
18317 RTX_FRAME_RELATED_P (insn
) = 1;
18319 if (IS_NESTED (func_type
))
18321 /* Recover the static chain register. */
18322 if (!arm_r3_live_at_start_p () || saved_pretend_args
)
18323 insn
= gen_rtx_REG (SImode
, 3);
18324 else /* if (crtl->args.pretend_args_size == 0) */
18326 insn
= plus_constant (Pmode
, hard_frame_pointer_rtx
, 4);
18327 insn
= gen_frame_mem (SImode
, insn
);
18329 emit_set_insn (ip_rtx
, insn
);
18330 /* Add a USE to stop propagate_one_insn() from barfing. */
18331 emit_insn (gen_force_register_use (ip_rtx
));
18336 insn
= GEN_INT (saved_regs
- 4);
18337 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
18338 stack_pointer_rtx
, insn
));
18339 RTX_FRAME_RELATED_P (insn
) = 1;
18343 if (flag_stack_usage_info
)
18344 current_function_static_stack_size
18345 = offsets
->outgoing_args
- offsets
->saved_args
;
18347 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
18349 /* This add can produce multiple insns for a large constant, so we
18350 need to get tricky. */
18351 rtx last
= get_last_insn ();
18353 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
18354 - offsets
->outgoing_args
);
18356 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
18360 last
= last
? NEXT_INSN (last
) : get_insns ();
18361 RTX_FRAME_RELATED_P (last
) = 1;
18363 while (last
!= insn
);
18365 /* If the frame pointer is needed, emit a special barrier that
18366 will prevent the scheduler from moving stores to the frame
18367 before the stack adjustment. */
18368 if (frame_pointer_needed
)
18369 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
18370 hard_frame_pointer_rtx
));
18374 if (frame_pointer_needed
&& TARGET_THUMB2
)
18375 thumb_set_frame_pointer (offsets
);
18377 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
18379 unsigned long mask
;
18381 mask
= live_regs_mask
;
18382 mask
&= THUMB2_WORK_REGS
;
18383 if (!IS_NESTED (func_type
))
18384 mask
|= (1 << IP_REGNUM
);
18385 arm_load_pic_register (mask
);
18388 /* If we are profiling, make sure no instructions are scheduled before
18389 the call to mcount. Similarly if the user has requested no
18390 scheduling in the prolog. Similarly if we want non-call exceptions
18391 using the EABI unwinder, to prevent faulting instructions from being
18392 swapped with a stack adjustment. */
18393 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
18394 || (arm_except_unwind_info (&global_options
) == UI_TARGET
18395 && cfun
->can_throw_non_call_exceptions
))
18396 emit_insn (gen_blockage ());
18398 /* If the link register is being kept alive, with the return address in it,
18399 then make sure that it does not get reused by the ce2 pass. */
18400 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
18401 cfun
->machine
->lr_save_eliminated
= 1;
18404 /* Print condition code to STREAM. Helper function for arm_print_operand. */
18406 arm_print_condition (FILE *stream
)
18408 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
18410 /* Branch conversion is not implemented for Thumb-2. */
18413 output_operand_lossage ("predicated Thumb instruction");
18416 if (current_insn_predicate
!= NULL
)
18418 output_operand_lossage
18419 ("predicated instruction in conditional sequence");
18423 fputs (arm_condition_codes
[arm_current_cc
], stream
);
18425 else if (current_insn_predicate
)
18427 enum arm_cond_code code
;
18431 output_operand_lossage ("predicated Thumb instruction");
18435 code
= get_arm_condition_code (current_insn_predicate
);
18436 fputs (arm_condition_codes
[code
], stream
);
18441 /* If CODE is 'd', then the X is a condition operand and the instruction
18442 should only be executed if the condition is true.
18443 if CODE is 'D', then the X is a condition operand and the instruction
18444 should only be executed if the condition is false: however, if the mode
18445 of the comparison is CCFPEmode, then always execute the instruction -- we
18446 do this because in these circumstances !GE does not necessarily imply LT;
18447 in these cases the instruction pattern will take care to make sure that
18448 an instruction containing %d will follow, thereby undoing the effects of
18449 doing this instruction unconditionally.
18450 If CODE is 'N' then X is a floating point operand that must be negated
18452 If CODE is 'B' then output a bitwise inverted value of X (a const int).
18453 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
18455 arm_print_operand (FILE *stream
, rtx x
, int code
)
18460 fputs (ASM_COMMENT_START
, stream
);
18464 fputs (user_label_prefix
, stream
);
18468 fputs (REGISTER_PREFIX
, stream
);
18472 arm_print_condition (stream
);
18476 /* Nothing in unified syntax, otherwise the current condition code. */
18477 if (!TARGET_UNIFIED_ASM
)
18478 arm_print_condition (stream
);
18482 /* The current condition code in unified syntax, otherwise nothing. */
18483 if (TARGET_UNIFIED_ASM
)
18484 arm_print_condition (stream
);
18488 /* The current condition code for a condition code setting instruction.
18489 Preceded by 's' in unified syntax, otherwise followed by 's'. */
18490 if (TARGET_UNIFIED_ASM
)
18492 fputc('s', stream
);
18493 arm_print_condition (stream
);
18497 arm_print_condition (stream
);
18498 fputc('s', stream
);
18503 /* If the instruction is conditionally executed then print
18504 the current condition code, otherwise print 's'. */
18505 gcc_assert (TARGET_THUMB2
&& TARGET_UNIFIED_ASM
);
18506 if (current_insn_predicate
)
18507 arm_print_condition (stream
);
18509 fputc('s', stream
);
18512 /* %# is a "break" sequence. It doesn't output anything, but is used to
18513 separate e.g. operand numbers from following text, if that text consists
18514 of further digits which we don't want to be part of the operand
18522 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
18523 r
= real_value_negate (&r
);
18524 fprintf (stream
, "%s", fp_const_from_val (&r
));
18528 /* An integer or symbol address without a preceding # sign. */
18530 switch (GET_CODE (x
))
18533 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
18537 output_addr_const (stream
, x
);
18541 if (GET_CODE (XEXP (x
, 0)) == PLUS
18542 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
18544 output_addr_const (stream
, x
);
18547 /* Fall through. */
18550 output_operand_lossage ("Unsupported operand for code '%c'", code
);
18554 /* An integer that we want to print in HEX. */
18556 switch (GET_CODE (x
))
18559 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
18563 output_operand_lossage ("Unsupported operand for code '%c'", code
);
18568 if (CONST_INT_P (x
))
18571 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
18572 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
18576 putc ('~', stream
);
18577 output_addr_const (stream
, x
);
18582 /* The low 16 bits of an immediate constant. */
18583 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL(x
) & 0xffff);
18587 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
18591 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
18599 shift
= shift_op (x
, &val
);
18603 fprintf (stream
, ", %s ", shift
);
18605 arm_print_operand (stream
, XEXP (x
, 1), 0);
18607 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
18612 /* An explanation of the 'Q', 'R' and 'H' register operands:
18614 In a pair of registers containing a DI or DF value the 'Q'
18615 operand returns the register number of the register containing
18616 the least significant part of the value. The 'R' operand returns
18617 the register number of the register containing the most
18618 significant part of the value.
18620 The 'H' operand returns the higher of the two register numbers.
18621 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
18622 same as the 'Q' operand, since the most significant part of the
18623 value is held in the lower number register. The reverse is true
18624 on systems where WORDS_BIG_ENDIAN is false.
18626 The purpose of these operands is to distinguish between cases
18627 where the endian-ness of the values is important (for example
18628 when they are added together), and cases where the endian-ness
18629 is irrelevant, but the order of register operations is important.
18630 For example when loading a value from memory into a register
18631 pair, the endian-ness does not matter. Provided that the value
18632 from the lower memory address is put into the lower numbered
18633 register, and the value from the higher address is put into the
18634 higher numbered register, the load will work regardless of whether
18635 the value being loaded is big-wordian or little-wordian. The
18636 order of the two register loads can matter however, if the address
18637 of the memory location is actually held in one of the registers
18638 being overwritten by the load.
18640 The 'Q' and 'R' constraints are also available for 64-bit
18643 if (CONST_INT_P (x
) || CONST_DOUBLE_P (x
))
18645 rtx part
= gen_lowpart (SImode
, x
);
18646 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, INTVAL (part
));
18650 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
18652 output_operand_lossage ("invalid operand for code '%c'", code
);
18656 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
18660 if (CONST_INT_P (x
) || CONST_DOUBLE_P (x
))
18662 enum machine_mode mode
= GET_MODE (x
);
18665 if (mode
== VOIDmode
)
18667 part
= gen_highpart_mode (SImode
, mode
, x
);
18668 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, INTVAL (part
));
18672 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
18674 output_operand_lossage ("invalid operand for code '%c'", code
);
18678 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
18682 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
18684 output_operand_lossage ("invalid operand for code '%c'", code
);
18688 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
18692 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
18694 output_operand_lossage ("invalid operand for code '%c'", code
);
18698 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 3 : 2));
18702 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
18704 output_operand_lossage ("invalid operand for code '%c'", code
);
18708 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 2 : 3));
18712 asm_fprintf (stream
, "%r",
18713 REG_P (XEXP (x
, 0))
18714 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
18718 asm_fprintf (stream
, "{%r-%r}",
18720 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
18723 /* Like 'M', but writing doubleword vector registers, for use by Neon
18727 int regno
= (REGNO (x
) - FIRST_VFP_REGNUM
) / 2;
18728 int numregs
= ARM_NUM_REGS (GET_MODE (x
)) / 2;
18730 asm_fprintf (stream
, "{d%d}", regno
);
18732 asm_fprintf (stream
, "{d%d-d%d}", regno
, regno
+ numregs
- 1);
18737 /* CONST_TRUE_RTX means always -- that's the default. */
18738 if (x
== const_true_rtx
)
18741 if (!COMPARISON_P (x
))
18743 output_operand_lossage ("invalid operand for code '%c'", code
);
18747 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
18752 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
18753 want to do that. */
18754 if (x
== const_true_rtx
)
18756 output_operand_lossage ("instruction never executed");
18759 if (!COMPARISON_P (x
))
18761 output_operand_lossage ("invalid operand for code '%c'", code
);
18765 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
18766 (get_arm_condition_code (x
))],
18776 /* Former Maverick support, removed after GCC-4.7. */
18777 output_operand_lossage ("obsolete Maverick format code '%c'", code
);
18782 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
18783 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
18784 /* Bad value for wCG register number. */
18786 output_operand_lossage ("invalid operand for code '%c'", code
);
18791 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
18794 /* Print an iWMMXt control register name. */
18796 if (!CONST_INT_P (x
)
18798 || INTVAL (x
) >= 16)
18799 /* Bad value for wC register number. */
18801 output_operand_lossage ("invalid operand for code '%c'", code
);
18807 static const char * wc_reg_names
[16] =
18809 "wCID", "wCon", "wCSSF", "wCASF",
18810 "wC4", "wC5", "wC6", "wC7",
18811 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
18812 "wC12", "wC13", "wC14", "wC15"
18815 fputs (wc_reg_names
[INTVAL (x
)], stream
);
18819 /* Print the high single-precision register of a VFP double-precision
18823 int mode
= GET_MODE (x
);
18826 if (GET_MODE_SIZE (mode
) != 8 || !REG_P (x
))
18828 output_operand_lossage ("invalid operand for code '%c'", code
);
18833 if (!VFP_REGNO_OK_FOR_DOUBLE (regno
))
18835 output_operand_lossage ("invalid operand for code '%c'", code
);
18839 fprintf (stream
, "s%d", regno
- FIRST_VFP_REGNUM
+ 1);
18843 /* Print a VFP/Neon double precision or quad precision register name. */
18847 int mode
= GET_MODE (x
);
18848 int is_quad
= (code
== 'q');
18851 if (GET_MODE_SIZE (mode
) != (is_quad
? 16 : 8))
18853 output_operand_lossage ("invalid operand for code '%c'", code
);
18858 || !IS_VFP_REGNUM (REGNO (x
)))
18860 output_operand_lossage ("invalid operand for code '%c'", code
);
18865 if ((is_quad
&& !NEON_REGNO_OK_FOR_QUAD (regno
))
18866 || (!is_quad
&& !VFP_REGNO_OK_FOR_DOUBLE (regno
)))
18868 output_operand_lossage ("invalid operand for code '%c'", code
);
18872 fprintf (stream
, "%c%d", is_quad
? 'q' : 'd',
18873 (regno
- FIRST_VFP_REGNUM
) >> (is_quad
? 2 : 1));
18877 /* These two codes print the low/high doubleword register of a Neon quad
18878 register, respectively. For pair-structure types, can also print
18879 low/high quadword registers. */
18883 int mode
= GET_MODE (x
);
18886 if ((GET_MODE_SIZE (mode
) != 16
18887 && GET_MODE_SIZE (mode
) != 32) || !REG_P (x
))
18889 output_operand_lossage ("invalid operand for code '%c'", code
);
18894 if (!NEON_REGNO_OK_FOR_QUAD (regno
))
18896 output_operand_lossage ("invalid operand for code '%c'", code
);
18900 if (GET_MODE_SIZE (mode
) == 16)
18901 fprintf (stream
, "d%d", ((regno
- FIRST_VFP_REGNUM
) >> 1)
18902 + (code
== 'f' ? 1 : 0));
18904 fprintf (stream
, "q%d", ((regno
- FIRST_VFP_REGNUM
) >> 2)
18905 + (code
== 'f' ? 1 : 0));
18909 /* Print a VFPv3 floating-point constant, represented as an integer
18913 int index
= vfp3_const_double_index (x
);
18914 gcc_assert (index
!= -1);
18915 fprintf (stream
, "%d", index
);
18919 /* Print bits representing opcode features for Neon.
18921 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
18922 and polynomials as unsigned.
18924 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
18926 Bit 2 is 1 for rounding functions, 0 otherwise. */
18928 /* Identify the type as 's', 'u', 'p' or 'f'. */
18931 HOST_WIDE_INT bits
= INTVAL (x
);
18932 fputc ("uspf"[bits
& 3], stream
);
18936 /* Likewise, but signed and unsigned integers are both 'i'. */
18939 HOST_WIDE_INT bits
= INTVAL (x
);
18940 fputc ("iipf"[bits
& 3], stream
);
18944 /* As for 'T', but emit 'u' instead of 'p'. */
18947 HOST_WIDE_INT bits
= INTVAL (x
);
18948 fputc ("usuf"[bits
& 3], stream
);
18952 /* Bit 2: rounding (vs none). */
18955 HOST_WIDE_INT bits
= INTVAL (x
);
18956 fputs ((bits
& 4) != 0 ? "r" : "", stream
);
18960 /* Memory operand for vld1/vst1 instruction. */
18964 bool postinc
= FALSE
;
18965 unsigned align
, memsize
, align_bits
;
18967 gcc_assert (MEM_P (x
));
18968 addr
= XEXP (x
, 0);
18969 if (GET_CODE (addr
) == POST_INC
)
18972 addr
= XEXP (addr
, 0);
18974 asm_fprintf (stream
, "[%r", REGNO (addr
));
18976 /* We know the alignment of this access, so we can emit a hint in the
18977 instruction (for some alignments) as an aid to the memory subsystem
18979 align
= MEM_ALIGN (x
) >> 3;
18980 memsize
= MEM_SIZE (x
);
18982 /* Only certain alignment specifiers are supported by the hardware. */
18983 if (memsize
== 32 && (align
% 32) == 0)
18985 else if ((memsize
== 16 || memsize
== 32) && (align
% 16) == 0)
18987 else if (memsize
>= 8 && (align
% 8) == 0)
18992 if (align_bits
!= 0)
18993 asm_fprintf (stream
, ":%d", align_bits
);
18995 asm_fprintf (stream
, "]");
18998 fputs("!", stream
);
19006 gcc_assert (MEM_P (x
));
19007 addr
= XEXP (x
, 0);
19008 gcc_assert (REG_P (addr
));
19009 asm_fprintf (stream
, "[%r]", REGNO (addr
));
19013 /* Translate an S register number into a D register number and element index. */
19016 int mode
= GET_MODE (x
);
19019 if (GET_MODE_SIZE (mode
) != 4 || !REG_P (x
))
19021 output_operand_lossage ("invalid operand for code '%c'", code
);
19026 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
19028 output_operand_lossage ("invalid operand for code '%c'", code
);
19032 regno
= regno
- FIRST_VFP_REGNUM
;
19033 fprintf (stream
, "d%d[%d]", regno
/ 2, regno
% 2);
19038 gcc_assert (CONST_DOUBLE_P (x
));
19039 fprintf (stream
, "#%d", vfp3_const_double_for_fract_bits (x
));
19042 /* Register specifier for vld1.16/vst1.16. Translate the S register
19043 number into a D register number and element index. */
19046 int mode
= GET_MODE (x
);
19049 if (GET_MODE_SIZE (mode
) != 2 || !REG_P (x
))
19051 output_operand_lossage ("invalid operand for code '%c'", code
);
19056 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
19058 output_operand_lossage ("invalid operand for code '%c'", code
);
19062 regno
= regno
- FIRST_VFP_REGNUM
;
19063 fprintf (stream
, "d%d[%d]", regno
/2, ((regno
% 2) ? 2 : 0));
19070 output_operand_lossage ("missing operand");
19074 switch (GET_CODE (x
))
19077 asm_fprintf (stream
, "%r", REGNO (x
));
19081 output_memory_reference_mode
= GET_MODE (x
);
19082 output_address (XEXP (x
, 0));
19089 real_to_decimal (fpstr
, CONST_DOUBLE_REAL_VALUE (x
),
19090 sizeof (fpstr
), 0, 1);
19091 fprintf (stream
, "#%s", fpstr
);
19094 fprintf (stream
, "#%s", fp_immediate_constant (x
));
19098 gcc_assert (GET_CODE (x
) != NEG
);
19099 fputc ('#', stream
);
19100 if (GET_CODE (x
) == HIGH
)
19102 fputs (":lower16:", stream
);
19106 output_addr_const (stream
, x
);
19112 /* Target hook for printing a memory address. */
19114 arm_print_operand_address (FILE *stream
, rtx x
)
19118 int is_minus
= GET_CODE (x
) == MINUS
;
19121 asm_fprintf (stream
, "[%r]", REGNO (x
));
19122 else if (GET_CODE (x
) == PLUS
|| is_minus
)
19124 rtx base
= XEXP (x
, 0);
19125 rtx index
= XEXP (x
, 1);
19126 HOST_WIDE_INT offset
= 0;
19128 || (REG_P (index
) && REGNO (index
) == SP_REGNUM
))
19130 /* Ensure that BASE is a register. */
19131 /* (one of them must be). */
19132 /* Also ensure the SP is not used as in index register. */
19137 switch (GET_CODE (index
))
19140 offset
= INTVAL (index
);
19143 asm_fprintf (stream
, "[%r, #%wd]",
19144 REGNO (base
), offset
);
19148 asm_fprintf (stream
, "[%r, %s%r]",
19149 REGNO (base
), is_minus
? "-" : "",
19159 asm_fprintf (stream
, "[%r, %s%r",
19160 REGNO (base
), is_minus
? "-" : "",
19161 REGNO (XEXP (index
, 0)));
19162 arm_print_operand (stream
, index
, 'S');
19163 fputs ("]", stream
);
19168 gcc_unreachable ();
19171 else if (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_INC
19172 || GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_DEC
)
19174 extern enum machine_mode output_memory_reference_mode
;
19176 gcc_assert (REG_P (XEXP (x
, 0)));
19178 if (GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == PRE_INC
)
19179 asm_fprintf (stream
, "[%r, #%s%d]!",
19180 REGNO (XEXP (x
, 0)),
19181 GET_CODE (x
) == PRE_DEC
? "-" : "",
19182 GET_MODE_SIZE (output_memory_reference_mode
));
19184 asm_fprintf (stream
, "[%r], #%s%d",
19185 REGNO (XEXP (x
, 0)),
19186 GET_CODE (x
) == POST_DEC
? "-" : "",
19187 GET_MODE_SIZE (output_memory_reference_mode
));
19189 else if (GET_CODE (x
) == PRE_MODIFY
)
19191 asm_fprintf (stream
, "[%r, ", REGNO (XEXP (x
, 0)));
19192 if (CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
19193 asm_fprintf (stream
, "#%wd]!",
19194 INTVAL (XEXP (XEXP (x
, 1), 1)));
19196 asm_fprintf (stream
, "%r]!",
19197 REGNO (XEXP (XEXP (x
, 1), 1)));
19199 else if (GET_CODE (x
) == POST_MODIFY
)
19201 asm_fprintf (stream
, "[%r], ", REGNO (XEXP (x
, 0)));
19202 if (CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
19203 asm_fprintf (stream
, "#%wd",
19204 INTVAL (XEXP (XEXP (x
, 1), 1)));
19206 asm_fprintf (stream
, "%r",
19207 REGNO (XEXP (XEXP (x
, 1), 1)));
19209 else output_addr_const (stream
, x
);
19214 asm_fprintf (stream
, "[%r]", REGNO (x
));
19215 else if (GET_CODE (x
) == POST_INC
)
19216 asm_fprintf (stream
, "%r!", REGNO (XEXP (x
, 0)));
19217 else if (GET_CODE (x
) == PLUS
)
19219 gcc_assert (REG_P (XEXP (x
, 0)));
19220 if (CONST_INT_P (XEXP (x
, 1)))
19221 asm_fprintf (stream
, "[%r, #%wd]",
19222 REGNO (XEXP (x
, 0)),
19223 INTVAL (XEXP (x
, 1)));
19225 asm_fprintf (stream
, "[%r, %r]",
19226 REGNO (XEXP (x
, 0)),
19227 REGNO (XEXP (x
, 1)));
19230 output_addr_const (stream
, x
);
19234 /* Target hook for indicating whether a punctuation character for
19235 TARGET_PRINT_OPERAND is valid. */
19237 arm_print_operand_punct_valid_p (unsigned char code
)
19239 return (code
== '@' || code
== '|' || code
== '.'
19240 || code
== '(' || code
== ')' || code
== '#'
19241 || (TARGET_32BIT
&& (code
== '?'))
19242 || (TARGET_THUMB2
&& (code
== '!'))
19243 || (TARGET_THUMB
&& (code
== '_')));
19246 /* Target hook for assembling integer objects. The ARM version needs to
19247 handle word-sized values specially. */
19249 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
19251 enum machine_mode mode
;
19253 if (size
== UNITS_PER_WORD
&& aligned_p
)
19255 fputs ("\t.word\t", asm_out_file
);
19256 output_addr_const (asm_out_file
, x
);
19258 /* Mark symbols as position independent. We only do this in the
19259 .text segment, not in the .data segment. */
19260 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
19261 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
19263 /* See legitimize_pic_address for an explanation of the
19264 TARGET_VXWORKS_RTP check. */
19265 if (TARGET_VXWORKS_RTP
19266 || (GET_CODE (x
) == SYMBOL_REF
&& !SYMBOL_REF_LOCAL_P (x
)))
19267 fputs ("(GOT)", asm_out_file
);
19269 fputs ("(GOTOFF)", asm_out_file
);
19271 fputc ('\n', asm_out_file
);
19275 mode
= GET_MODE (x
);
19277 if (arm_vector_mode_supported_p (mode
))
19281 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
19283 units
= CONST_VECTOR_NUNITS (x
);
19284 size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
19286 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
19287 for (i
= 0; i
< units
; i
++)
19289 rtx elt
= CONST_VECTOR_ELT (x
, i
);
19291 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
19294 for (i
= 0; i
< units
; i
++)
19296 rtx elt
= CONST_VECTOR_ELT (x
, i
);
19297 REAL_VALUE_TYPE rval
;
19299 REAL_VALUE_FROM_CONST_DOUBLE (rval
, elt
);
19302 (rval
, GET_MODE_INNER (mode
),
19303 i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
);
19309 return default_assemble_integer (x
, size
, aligned_p
);
19313 arm_elf_asm_cdtor (rtx symbol
, int priority
, bool is_ctor
)
19317 if (!TARGET_AAPCS_BASED
)
19320 default_named_section_asm_out_constructor
19321 : default_named_section_asm_out_destructor
) (symbol
, priority
);
19325 /* Put these in the .init_array section, using a special relocation. */
19326 if (priority
!= DEFAULT_INIT_PRIORITY
)
19329 sprintf (buf
, "%s.%.5u",
19330 is_ctor
? ".init_array" : ".fini_array",
19332 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
19339 switch_to_section (s
);
19340 assemble_align (POINTER_SIZE
);
19341 fputs ("\t.word\t", asm_out_file
);
19342 output_addr_const (asm_out_file
, symbol
);
19343 fputs ("(target1)\n", asm_out_file
);
19346 /* Add a function to the list of static constructors. */
19349 arm_elf_asm_constructor (rtx symbol
, int priority
)
19351 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/true);
19354 /* Add a function to the list of static destructors. */
19357 arm_elf_asm_destructor (rtx symbol
, int priority
)
19359 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/false);
19362 /* A finite state machine takes care of noticing whether or not instructions
19363 can be conditionally executed, and thus decrease execution time and code
19364 size by deleting branch instructions. The fsm is controlled by
19365 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
19367 /* The state of the fsm controlling condition codes are:
19368 0: normal, do nothing special
19369 1: make ASM_OUTPUT_OPCODE not output this instruction
19370 2: make ASM_OUTPUT_OPCODE not output this instruction
19371 3: make instructions conditional
19372 4: make instructions conditional
19374 State transitions (state->state by whom under condition):
19375 0 -> 1 final_prescan_insn if the `target' is a label
19376 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
19377 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
19378 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
19379 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
19380 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
19381 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
19382 (the target insn is arm_target_insn).
19384 If the jump clobbers the conditions then we use states 2 and 4.
19386 A similar thing can be done with conditional return insns.
19388 XXX In case the `target' is an unconditional branch, this conditionalising
19389 of the instructions always reduces code size, but not always execution
19390 time. But then, I want to reduce the code size to somewhere near what
19391 /bin/cc produces. */
19393 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
19394 instructions. When a COND_EXEC instruction is seen the subsequent
19395 instructions are scanned so that multiple conditional instructions can be
19396 combined into a single IT block. arm_condexec_count and arm_condexec_mask
19397 specify the length and true/false mask for the IT block. These will be
19398 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
19400 /* Returns the index of the ARM condition code string in
19401 `arm_condition_codes', or ARM_NV if the comparison is invalid.
19402 COMPARISON should be an rtx like `(eq (...) (...))'. */
19405 maybe_get_arm_condition_code (rtx comparison
)
19407 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
19408 enum arm_cond_code code
;
19409 enum rtx_code comp_code
= GET_CODE (comparison
);
19411 if (GET_MODE_CLASS (mode
) != MODE_CC
)
19412 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
19413 XEXP (comparison
, 1));
19417 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
19418 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
19419 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
19420 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
19421 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
19422 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
19423 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
19424 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
19425 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
19426 case CC_DLTUmode
: code
= ARM_CC
;
19429 if (comp_code
== EQ
)
19430 return ARM_INVERSE_CONDITION_CODE (code
);
19431 if (comp_code
== NE
)
19438 case NE
: return ARM_NE
;
19439 case EQ
: return ARM_EQ
;
19440 case GE
: return ARM_PL
;
19441 case LT
: return ARM_MI
;
19442 default: return ARM_NV
;
19448 case NE
: return ARM_NE
;
19449 case EQ
: return ARM_EQ
;
19450 default: return ARM_NV
;
19456 case NE
: return ARM_MI
;
19457 case EQ
: return ARM_PL
;
19458 default: return ARM_NV
;
19463 /* We can handle all cases except UNEQ and LTGT. */
19466 case GE
: return ARM_GE
;
19467 case GT
: return ARM_GT
;
19468 case LE
: return ARM_LS
;
19469 case LT
: return ARM_MI
;
19470 case NE
: return ARM_NE
;
19471 case EQ
: return ARM_EQ
;
19472 case ORDERED
: return ARM_VC
;
19473 case UNORDERED
: return ARM_VS
;
19474 case UNLT
: return ARM_LT
;
19475 case UNLE
: return ARM_LE
;
19476 case UNGT
: return ARM_HI
;
19477 case UNGE
: return ARM_PL
;
19478 /* UNEQ and LTGT do not have a representation. */
19479 case UNEQ
: /* Fall through. */
19480 case LTGT
: /* Fall through. */
19481 default: return ARM_NV
;
19487 case NE
: return ARM_NE
;
19488 case EQ
: return ARM_EQ
;
19489 case GE
: return ARM_LE
;
19490 case GT
: return ARM_LT
;
19491 case LE
: return ARM_GE
;
19492 case LT
: return ARM_GT
;
19493 case GEU
: return ARM_LS
;
19494 case GTU
: return ARM_CC
;
19495 case LEU
: return ARM_CS
;
19496 case LTU
: return ARM_HI
;
19497 default: return ARM_NV
;
19503 case LTU
: return ARM_CS
;
19504 case GEU
: return ARM_CC
;
19505 default: return ARM_NV
;
19511 case NE
: return ARM_NE
;
19512 case EQ
: return ARM_EQ
;
19513 case GEU
: return ARM_CS
;
19514 case GTU
: return ARM_HI
;
19515 case LEU
: return ARM_LS
;
19516 case LTU
: return ARM_CC
;
19517 default: return ARM_NV
;
19523 case GE
: return ARM_GE
;
19524 case LT
: return ARM_LT
;
19525 case GEU
: return ARM_CS
;
19526 case LTU
: return ARM_CC
;
19527 default: return ARM_NV
;
19533 case NE
: return ARM_NE
;
19534 case EQ
: return ARM_EQ
;
19535 case GE
: return ARM_GE
;
19536 case GT
: return ARM_GT
;
19537 case LE
: return ARM_LE
;
19538 case LT
: return ARM_LT
;
19539 case GEU
: return ARM_CS
;
19540 case GTU
: return ARM_HI
;
19541 case LEU
: return ARM_LS
;
19542 case LTU
: return ARM_CC
;
19543 default: return ARM_NV
;
19546 default: gcc_unreachable ();
19550 /* Like maybe_get_arm_condition_code, but never return ARM_NV. */
19551 static enum arm_cond_code
19552 get_arm_condition_code (rtx comparison
)
19554 enum arm_cond_code code
= maybe_get_arm_condition_code (comparison
);
19555 gcc_assert (code
!= ARM_NV
);
19559 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
19562 thumb2_final_prescan_insn (rtx insn
)
19564 rtx first_insn
= insn
;
19565 rtx body
= PATTERN (insn
);
19567 enum arm_cond_code code
;
19571 /* Remove the previous insn from the count of insns to be output. */
19572 if (arm_condexec_count
)
19573 arm_condexec_count
--;
19575 /* Nothing to do if we are already inside a conditional block. */
19576 if (arm_condexec_count
)
19579 if (GET_CODE (body
) != COND_EXEC
)
19582 /* Conditional jumps are implemented directly. */
19586 predicate
= COND_EXEC_TEST (body
);
19587 arm_current_cc
= get_arm_condition_code (predicate
);
19589 n
= get_attr_ce_count (insn
);
19590 arm_condexec_count
= 1;
19591 arm_condexec_mask
= (1 << n
) - 1;
19592 arm_condexec_masklen
= n
;
19593 /* See if subsequent instructions can be combined into the same block. */
19596 insn
= next_nonnote_insn (insn
);
19598 /* Jumping into the middle of an IT block is illegal, so a label or
19599 barrier terminates the block. */
19600 if (!NONJUMP_INSN_P (insn
) && !JUMP_P (insn
))
19603 body
= PATTERN (insn
);
19604 /* USE and CLOBBER aren't really insns, so just skip them. */
19605 if (GET_CODE (body
) == USE
19606 || GET_CODE (body
) == CLOBBER
)
19609 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
19610 if (GET_CODE (body
) != COND_EXEC
)
19612 /* Allow up to 4 conditionally executed instructions in a block. */
19613 n
= get_attr_ce_count (insn
);
19614 if (arm_condexec_masklen
+ n
> MAX_INSN_PER_IT_BLOCK
)
19617 predicate
= COND_EXEC_TEST (body
);
19618 code
= get_arm_condition_code (predicate
);
19619 mask
= (1 << n
) - 1;
19620 if (arm_current_cc
== code
)
19621 arm_condexec_mask
|= (mask
<< arm_condexec_masklen
);
19622 else if (arm_current_cc
!= ARM_INVERSE_CONDITION_CODE(code
))
19625 arm_condexec_count
++;
19626 arm_condexec_masklen
+= n
;
19628 /* A jump must be the last instruction in a conditional block. */
19632 /* Restore recog_data (getting the attributes of other insns can
19633 destroy this array, but final.c assumes that it remains intact
19634 across this call). */
19635 extract_constrain_insn_cached (first_insn
);
19639 arm_final_prescan_insn (rtx insn
)
19641 /* BODY will hold the body of INSN. */
19642 rtx body
= PATTERN (insn
);
19644 /* This will be 1 if trying to repeat the trick, and things need to be
19645 reversed if it appears to fail. */
19648 /* If we start with a return insn, we only succeed if we find another one. */
19649 int seeking_return
= 0;
19650 enum rtx_code return_code
= UNKNOWN
;
19652 /* START_INSN will hold the insn from where we start looking. This is the
19653 first insn after the following code_label if REVERSE is true. */
19654 rtx start_insn
= insn
;
19656 /* If in state 4, check if the target branch is reached, in order to
19657 change back to state 0. */
19658 if (arm_ccfsm_state
== 4)
19660 if (insn
== arm_target_insn
)
19662 arm_target_insn
= NULL
;
19663 arm_ccfsm_state
= 0;
19668 /* If in state 3, it is possible to repeat the trick, if this insn is an
19669 unconditional branch to a label, and immediately following this branch
19670 is the previous target label which is only used once, and the label this
19671 branch jumps to is not too far off. */
19672 if (arm_ccfsm_state
== 3)
19674 if (simplejump_p (insn
))
19676 start_insn
= next_nonnote_insn (start_insn
);
19677 if (BARRIER_P (start_insn
))
19679 /* XXX Isn't this always a barrier? */
19680 start_insn
= next_nonnote_insn (start_insn
);
19682 if (LABEL_P (start_insn
)
19683 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
19684 && LABEL_NUSES (start_insn
) == 1)
19689 else if (ANY_RETURN_P (body
))
19691 start_insn
= next_nonnote_insn (start_insn
);
19692 if (BARRIER_P (start_insn
))
19693 start_insn
= next_nonnote_insn (start_insn
);
19694 if (LABEL_P (start_insn
)
19695 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
19696 && LABEL_NUSES (start_insn
) == 1)
19699 seeking_return
= 1;
19700 return_code
= GET_CODE (body
);
19709 gcc_assert (!arm_ccfsm_state
|| reverse
);
19710 if (!JUMP_P (insn
))
19713 /* This jump might be paralleled with a clobber of the condition codes
19714 the jump should always come first */
19715 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
19716 body
= XVECEXP (body
, 0, 0);
19719 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
19720 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
19723 int fail
= FALSE
, succeed
= FALSE
;
19724 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
19725 int then_not_else
= TRUE
;
19726 rtx this_insn
= start_insn
, label
= 0;
19728 /* Register the insn jumped to. */
19731 if (!seeking_return
)
19732 label
= XEXP (SET_SRC (body
), 0);
19734 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
19735 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
19736 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
19738 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
19739 then_not_else
= FALSE
;
19741 else if (ANY_RETURN_P (XEXP (SET_SRC (body
), 1)))
19743 seeking_return
= 1;
19744 return_code
= GET_CODE (XEXP (SET_SRC (body
), 1));
19746 else if (ANY_RETURN_P (XEXP (SET_SRC (body
), 2)))
19748 seeking_return
= 1;
19749 return_code
= GET_CODE (XEXP (SET_SRC (body
), 2));
19750 then_not_else
= FALSE
;
19753 gcc_unreachable ();
19755 /* See how many insns this branch skips, and what kind of insns. If all
19756 insns are okay, and the label or unconditional branch to the same
19757 label is not too far away, succeed. */
19758 for (insns_skipped
= 0;
19759 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
19763 this_insn
= next_nonnote_insn (this_insn
);
19767 switch (GET_CODE (this_insn
))
19770 /* Succeed if it is the target label, otherwise fail since
19771 control falls in from somewhere else. */
19772 if (this_insn
== label
)
19774 arm_ccfsm_state
= 1;
19782 /* Succeed if the following insn is the target label.
19784 If return insns are used then the last insn in a function
19785 will be a barrier. */
19786 this_insn
= next_nonnote_insn (this_insn
);
19787 if (this_insn
&& this_insn
== label
)
19789 arm_ccfsm_state
= 1;
19797 /* The AAPCS says that conditional calls should not be
19798 used since they make interworking inefficient (the
19799 linker can't transform BL<cond> into BLX). That's
19800 only a problem if the machine has BLX. */
19807 /* Succeed if the following insn is the target label, or
19808 if the following two insns are a barrier and the
19810 this_insn
= next_nonnote_insn (this_insn
);
19811 if (this_insn
&& BARRIER_P (this_insn
))
19812 this_insn
= next_nonnote_insn (this_insn
);
19814 if (this_insn
&& this_insn
== label
19815 && insns_skipped
< max_insns_skipped
)
19817 arm_ccfsm_state
= 1;
19825 /* If this is an unconditional branch to the same label, succeed.
19826 If it is to another label, do nothing. If it is conditional,
19828 /* XXX Probably, the tests for SET and the PC are
19831 scanbody
= PATTERN (this_insn
);
19832 if (GET_CODE (scanbody
) == SET
19833 && GET_CODE (SET_DEST (scanbody
)) == PC
)
19835 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
19836 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
19838 arm_ccfsm_state
= 2;
19841 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
19844 /* Fail if a conditional return is undesirable (e.g. on a
19845 StrongARM), but still allow this if optimizing for size. */
19846 else if (GET_CODE (scanbody
) == return_code
19847 && !use_return_insn (TRUE
, NULL
)
19850 else if (GET_CODE (scanbody
) == return_code
)
19852 arm_ccfsm_state
= 2;
19855 else if (GET_CODE (scanbody
) == PARALLEL
)
19857 switch (get_attr_conds (this_insn
))
19867 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
19872 /* Instructions using or affecting the condition codes make it
19874 scanbody
= PATTERN (this_insn
);
19875 if (!(GET_CODE (scanbody
) == SET
19876 || GET_CODE (scanbody
) == PARALLEL
)
19877 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
19887 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
19888 arm_target_label
= CODE_LABEL_NUMBER (label
);
19891 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
19893 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
19895 this_insn
= next_nonnote_insn (this_insn
);
19896 gcc_assert (!this_insn
19897 || (!BARRIER_P (this_insn
)
19898 && !LABEL_P (this_insn
)));
19902 /* Oh, dear! we ran off the end.. give up. */
19903 extract_constrain_insn_cached (insn
);
19904 arm_ccfsm_state
= 0;
19905 arm_target_insn
= NULL
;
19908 arm_target_insn
= this_insn
;
19911 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
19914 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
), 0));
19916 if (reverse
|| then_not_else
)
19917 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
19920 /* Restore recog_data (getting the attributes of other insns can
19921 destroy this array, but final.c assumes that it remains intact
19922 across this call. */
19923 extract_constrain_insn_cached (insn
);
19927 /* Output IT instructions. */
19929 thumb2_asm_output_opcode (FILE * stream
)
19934 if (arm_condexec_mask
)
19936 for (n
= 0; n
< arm_condexec_masklen
; n
++)
19937 buff
[n
] = (arm_condexec_mask
& (1 << n
)) ? 't' : 'e';
19939 asm_fprintf(stream
, "i%s\t%s\n\t", buff
,
19940 arm_condition_codes
[arm_current_cc
]);
19941 arm_condexec_mask
= 0;
19945 /* Returns true if REGNO is a valid register
19946 for holding a quantity of type MODE. */
19948 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
19950 if (GET_MODE_CLASS (mode
) == MODE_CC
)
19951 return (regno
== CC_REGNUM
19952 || (TARGET_HARD_FLOAT
&& TARGET_VFP
19953 && regno
== VFPCC_REGNUM
));
19956 /* For the Thumb we only allow values bigger than SImode in
19957 registers 0 - 6, so that there is always a second low
19958 register available to hold the upper part of the value.
19959 We probably we ought to ensure that the register is the
19960 start of an even numbered register pair. */
19961 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
19963 if (TARGET_HARD_FLOAT
&& TARGET_VFP
19964 && IS_VFP_REGNUM (regno
))
19966 if (mode
== SFmode
|| mode
== SImode
)
19967 return VFP_REGNO_OK_FOR_SINGLE (regno
);
19969 if (mode
== DFmode
)
19970 return VFP_REGNO_OK_FOR_DOUBLE (regno
);
19972 /* VFP registers can hold HFmode values, but there is no point in
19973 putting them there unless we have hardware conversion insns. */
19974 if (mode
== HFmode
)
19975 return TARGET_FP16
&& VFP_REGNO_OK_FOR_SINGLE (regno
);
19978 return (VALID_NEON_DREG_MODE (mode
) && VFP_REGNO_OK_FOR_DOUBLE (regno
))
19979 || (VALID_NEON_QREG_MODE (mode
)
19980 && NEON_REGNO_OK_FOR_QUAD (regno
))
19981 || (mode
== TImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 2))
19982 || (mode
== EImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 3))
19983 || (mode
== OImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 4))
19984 || (mode
== CImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 6))
19985 || (mode
== XImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 8));
19990 if (TARGET_REALLY_IWMMXT
)
19992 if (IS_IWMMXT_GR_REGNUM (regno
))
19993 return mode
== SImode
;
19995 if (IS_IWMMXT_REGNUM (regno
))
19996 return VALID_IWMMXT_REG_MODE (mode
);
19999 /* We allow almost any value to be stored in the general registers.
20000 Restrict doubleword quantities to even register pairs so that we can
20001 use ldrd. Do not allow very large Neon structure opaque modes in
20002 general registers; they would use too many. */
20003 if (regno
<= LAST_ARM_REGNUM
)
20004 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0)
20005 && ARM_NUM_REGS (mode
) <= 4;
20007 if (regno
== FRAME_POINTER_REGNUM
20008 || regno
== ARG_POINTER_REGNUM
)
20009 /* We only allow integers in the fake hard registers. */
20010 return GET_MODE_CLASS (mode
) == MODE_INT
;
20015 /* Implement MODES_TIEABLE_P. */
20018 arm_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
20020 if (GET_MODE_CLASS (mode1
) == GET_MODE_CLASS (mode2
))
20023 /* We specifically want to allow elements of "structure" modes to
20024 be tieable to the structure. This more general condition allows
20025 other rarer situations too. */
20027 && (VALID_NEON_DREG_MODE (mode1
)
20028 || VALID_NEON_QREG_MODE (mode1
)
20029 || VALID_NEON_STRUCT_MODE (mode1
))
20030 && (VALID_NEON_DREG_MODE (mode2
)
20031 || VALID_NEON_QREG_MODE (mode2
)
20032 || VALID_NEON_STRUCT_MODE (mode2
)))
20038 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
20039 not used in arm mode. */
20042 arm_regno_class (int regno
)
20046 if (regno
== STACK_POINTER_REGNUM
)
20048 if (regno
== CC_REGNUM
)
20055 if (TARGET_THUMB2
&& regno
< 8)
20058 if ( regno
<= LAST_ARM_REGNUM
20059 || regno
== FRAME_POINTER_REGNUM
20060 || regno
== ARG_POINTER_REGNUM
)
20061 return TARGET_THUMB2
? HI_REGS
: GENERAL_REGS
;
20063 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
20064 return TARGET_THUMB2
? CC_REG
: NO_REGS
;
20066 if (IS_VFP_REGNUM (regno
))
20068 if (regno
<= D7_VFP_REGNUM
)
20069 return VFP_D0_D7_REGS
;
20070 else if (regno
<= LAST_LO_VFP_REGNUM
)
20071 return VFP_LO_REGS
;
20073 return VFP_HI_REGS
;
20076 if (IS_IWMMXT_REGNUM (regno
))
20077 return IWMMXT_REGS
;
20079 if (IS_IWMMXT_GR_REGNUM (regno
))
20080 return IWMMXT_GR_REGS
;
20085 /* Handle a special case when computing the offset
20086 of an argument from the frame pointer. */
20088 arm_debugger_arg_offset (int value
, rtx addr
)
20092 /* We are only interested if dbxout_parms() failed to compute the offset. */
20096 /* We can only cope with the case where the address is held in a register. */
20100 /* If we are using the frame pointer to point at the argument, then
20101 an offset of 0 is correct. */
20102 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
20105 /* If we are using the stack pointer to point at the
20106 argument, then an offset of 0 is correct. */
20107 /* ??? Check this is consistent with thumb2 frame layout. */
20108 if ((TARGET_THUMB
|| !frame_pointer_needed
)
20109 && REGNO (addr
) == SP_REGNUM
)
20112 /* Oh dear. The argument is pointed to by a register rather
20113 than being held in a register, or being stored at a known
20114 offset from the frame pointer. Since GDB only understands
20115 those two kinds of argument we must translate the address
20116 held in the register into an offset from the frame pointer.
20117 We do this by searching through the insns for the function
20118 looking to see where this register gets its value. If the
20119 register is initialized from the frame pointer plus an offset
20120 then we are in luck and we can continue, otherwise we give up.
20122 This code is exercised by producing debugging information
20123 for a function with arguments like this:
20125 double func (double a, double b, int c, double d) {return d;}
20127 Without this code the stab for parameter 'd' will be set to
20128 an offset of 0 from the frame pointer, rather than 8. */
20130 /* The if() statement says:
20132 If the insn is a normal instruction
20133 and if the insn is setting the value in a register
20134 and if the register being set is the register holding the address of the argument
20135 and if the address is computing by an addition
20136 that involves adding to a register
20137 which is the frame pointer
20142 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
20144 if ( NONJUMP_INSN_P (insn
)
20145 && GET_CODE (PATTERN (insn
)) == SET
20146 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
20147 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
20148 && REG_P (XEXP (XEXP (PATTERN (insn
), 1), 0))
20149 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
20150 && CONST_INT_P (XEXP (XEXP (PATTERN (insn
), 1), 1))
20153 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
20162 warning (0, "unable to compute real location of stacked parameter");
20163 value
= 8; /* XXX magic hack */
20184 T_MAX
/* Size of enum. Keep last. */
20185 } neon_builtin_type_mode
;
20187 #define TYPE_MODE_BIT(X) (1 << (X))
20189 #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \
20190 | TYPE_MODE_BIT (T_V4HF) | TYPE_MODE_BIT (T_V2SI) \
20191 | TYPE_MODE_BIT (T_V2SF) | TYPE_MODE_BIT (T_DI))
20192 #define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \
20193 | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \
20194 | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
20196 #define v8qi_UP T_V8QI
20197 #define v4hi_UP T_V4HI
20198 #define v4hf_UP T_V4HF
20199 #define v2si_UP T_V2SI
20200 #define v2sf_UP T_V2SF
20202 #define v16qi_UP T_V16QI
20203 #define v8hi_UP T_V8HI
20204 #define v4si_UP T_V4SI
20205 #define v4sf_UP T_V4SF
20206 #define v2di_UP T_V2DI
20211 #define UP(X) X##_UP
20247 NEON_LOADSTRUCTLANE
,
20249 NEON_STORESTRUCTLANE
,
20258 const neon_itype itype
;
20259 const neon_builtin_type_mode mode
;
20260 const enum insn_code code
;
20261 unsigned int fcode
;
20262 } neon_builtin_datum
;
20264 #define CF(N,X) CODE_FOR_neon_##N##X
20266 #define VAR1(T, N, A) \
20267 {#N, NEON_##T, UP (A), CF (N, A), 0}
20268 #define VAR2(T, N, A, B) \
20270 {#N, NEON_##T, UP (B), CF (N, B), 0}
20271 #define VAR3(T, N, A, B, C) \
20272 VAR2 (T, N, A, B), \
20273 {#N, NEON_##T, UP (C), CF (N, C), 0}
20274 #define VAR4(T, N, A, B, C, D) \
20275 VAR3 (T, N, A, B, C), \
20276 {#N, NEON_##T, UP (D), CF (N, D), 0}
20277 #define VAR5(T, N, A, B, C, D, E) \
20278 VAR4 (T, N, A, B, C, D), \
20279 {#N, NEON_##T, UP (E), CF (N, E), 0}
20280 #define VAR6(T, N, A, B, C, D, E, F) \
20281 VAR5 (T, N, A, B, C, D, E), \
20282 {#N, NEON_##T, UP (F), CF (N, F), 0}
20283 #define VAR7(T, N, A, B, C, D, E, F, G) \
20284 VAR6 (T, N, A, B, C, D, E, F), \
20285 {#N, NEON_##T, UP (G), CF (N, G), 0}
20286 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
20287 VAR7 (T, N, A, B, C, D, E, F, G), \
20288 {#N, NEON_##T, UP (H), CF (N, H), 0}
20289 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
20290 VAR8 (T, N, A, B, C, D, E, F, G, H), \
20291 {#N, NEON_##T, UP (I), CF (N, I), 0}
20292 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
20293 VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
20294 {#N, NEON_##T, UP (J), CF (N, J), 0}
20296 /* The NEON builtin data can be found in arm_neon_builtins.def.
20297 The mode entries in the following table correspond to the "key" type of the
20298 instruction variant, i.e. equivalent to that which would be specified after
20299 the assembler mnemonic, which usually refers to the last vector operand.
20300 (Signed/unsigned/polynomial types are not differentiated between though, and
20301 are all mapped onto the same mode for a given element size.) The modes
20302 listed per instruction should be the same as those defined for that
20303 instruction's pattern in neon.md. */
20305 static neon_builtin_datum neon_builtin_data
[] =
20307 #include "arm_neon_builtins.def"
20322 #define CF(N,X) ARM_BUILTIN_NEON_##N##X
20323 #define VAR1(T, N, A) \
20325 #define VAR2(T, N, A, B) \
20328 #define VAR3(T, N, A, B, C) \
20329 VAR2 (T, N, A, B), \
20331 #define VAR4(T, N, A, B, C, D) \
20332 VAR3 (T, N, A, B, C), \
20334 #define VAR5(T, N, A, B, C, D, E) \
20335 VAR4 (T, N, A, B, C, D), \
20337 #define VAR6(T, N, A, B, C, D, E, F) \
20338 VAR5 (T, N, A, B, C, D, E), \
20340 #define VAR7(T, N, A, B, C, D, E, F, G) \
20341 VAR6 (T, N, A, B, C, D, E, F), \
20343 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
20344 VAR7 (T, N, A, B, C, D, E, F, G), \
20346 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
20347 VAR8 (T, N, A, B, C, D, E, F, G, H), \
20349 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
20350 VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
20354 ARM_BUILTIN_GETWCGR0
,
20355 ARM_BUILTIN_GETWCGR1
,
20356 ARM_BUILTIN_GETWCGR2
,
20357 ARM_BUILTIN_GETWCGR3
,
20359 ARM_BUILTIN_SETWCGR0
,
20360 ARM_BUILTIN_SETWCGR1
,
20361 ARM_BUILTIN_SETWCGR2
,
20362 ARM_BUILTIN_SETWCGR3
,
20366 ARM_BUILTIN_WAVG2BR
,
20367 ARM_BUILTIN_WAVG2HR
,
20368 ARM_BUILTIN_WAVG2B
,
20369 ARM_BUILTIN_WAVG2H
,
20376 ARM_BUILTIN_WMACSZ
,
20378 ARM_BUILTIN_WMACUZ
,
20381 ARM_BUILTIN_WSADBZ
,
20383 ARM_BUILTIN_WSADHZ
,
20385 ARM_BUILTIN_WALIGNI
,
20386 ARM_BUILTIN_WALIGNR0
,
20387 ARM_BUILTIN_WALIGNR1
,
20388 ARM_BUILTIN_WALIGNR2
,
20389 ARM_BUILTIN_WALIGNR3
,
20392 ARM_BUILTIN_TMIAPH
,
20393 ARM_BUILTIN_TMIABB
,
20394 ARM_BUILTIN_TMIABT
,
20395 ARM_BUILTIN_TMIATB
,
20396 ARM_BUILTIN_TMIATT
,
20398 ARM_BUILTIN_TMOVMSKB
,
20399 ARM_BUILTIN_TMOVMSKH
,
20400 ARM_BUILTIN_TMOVMSKW
,
20402 ARM_BUILTIN_TBCSTB
,
20403 ARM_BUILTIN_TBCSTH
,
20404 ARM_BUILTIN_TBCSTW
,
20406 ARM_BUILTIN_WMADDS
,
20407 ARM_BUILTIN_WMADDU
,
20409 ARM_BUILTIN_WPACKHSS
,
20410 ARM_BUILTIN_WPACKWSS
,
20411 ARM_BUILTIN_WPACKDSS
,
20412 ARM_BUILTIN_WPACKHUS
,
20413 ARM_BUILTIN_WPACKWUS
,
20414 ARM_BUILTIN_WPACKDUS
,
20419 ARM_BUILTIN_WADDSSB
,
20420 ARM_BUILTIN_WADDSSH
,
20421 ARM_BUILTIN_WADDSSW
,
20422 ARM_BUILTIN_WADDUSB
,
20423 ARM_BUILTIN_WADDUSH
,
20424 ARM_BUILTIN_WADDUSW
,
20428 ARM_BUILTIN_WSUBSSB
,
20429 ARM_BUILTIN_WSUBSSH
,
20430 ARM_BUILTIN_WSUBSSW
,
20431 ARM_BUILTIN_WSUBUSB
,
20432 ARM_BUILTIN_WSUBUSH
,
20433 ARM_BUILTIN_WSUBUSW
,
20440 ARM_BUILTIN_WCMPEQB
,
20441 ARM_BUILTIN_WCMPEQH
,
20442 ARM_BUILTIN_WCMPEQW
,
20443 ARM_BUILTIN_WCMPGTUB
,
20444 ARM_BUILTIN_WCMPGTUH
,
20445 ARM_BUILTIN_WCMPGTUW
,
20446 ARM_BUILTIN_WCMPGTSB
,
20447 ARM_BUILTIN_WCMPGTSH
,
20448 ARM_BUILTIN_WCMPGTSW
,
20450 ARM_BUILTIN_TEXTRMSB
,
20451 ARM_BUILTIN_TEXTRMSH
,
20452 ARM_BUILTIN_TEXTRMSW
,
20453 ARM_BUILTIN_TEXTRMUB
,
20454 ARM_BUILTIN_TEXTRMUH
,
20455 ARM_BUILTIN_TEXTRMUW
,
20456 ARM_BUILTIN_TINSRB
,
20457 ARM_BUILTIN_TINSRH
,
20458 ARM_BUILTIN_TINSRW
,
20460 ARM_BUILTIN_WMAXSW
,
20461 ARM_BUILTIN_WMAXSH
,
20462 ARM_BUILTIN_WMAXSB
,
20463 ARM_BUILTIN_WMAXUW
,
20464 ARM_BUILTIN_WMAXUH
,
20465 ARM_BUILTIN_WMAXUB
,
20466 ARM_BUILTIN_WMINSW
,
20467 ARM_BUILTIN_WMINSH
,
20468 ARM_BUILTIN_WMINSB
,
20469 ARM_BUILTIN_WMINUW
,
20470 ARM_BUILTIN_WMINUH
,
20471 ARM_BUILTIN_WMINUB
,
20473 ARM_BUILTIN_WMULUM
,
20474 ARM_BUILTIN_WMULSM
,
20475 ARM_BUILTIN_WMULUL
,
20477 ARM_BUILTIN_PSADBH
,
20478 ARM_BUILTIN_WSHUFH
,
20492 ARM_BUILTIN_WSLLHI
,
20493 ARM_BUILTIN_WSLLWI
,
20494 ARM_BUILTIN_WSLLDI
,
20495 ARM_BUILTIN_WSRAHI
,
20496 ARM_BUILTIN_WSRAWI
,
20497 ARM_BUILTIN_WSRADI
,
20498 ARM_BUILTIN_WSRLHI
,
20499 ARM_BUILTIN_WSRLWI
,
20500 ARM_BUILTIN_WSRLDI
,
20501 ARM_BUILTIN_WRORHI
,
20502 ARM_BUILTIN_WRORWI
,
20503 ARM_BUILTIN_WRORDI
,
20505 ARM_BUILTIN_WUNPCKIHB
,
20506 ARM_BUILTIN_WUNPCKIHH
,
20507 ARM_BUILTIN_WUNPCKIHW
,
20508 ARM_BUILTIN_WUNPCKILB
,
20509 ARM_BUILTIN_WUNPCKILH
,
20510 ARM_BUILTIN_WUNPCKILW
,
20512 ARM_BUILTIN_WUNPCKEHSB
,
20513 ARM_BUILTIN_WUNPCKEHSH
,
20514 ARM_BUILTIN_WUNPCKEHSW
,
20515 ARM_BUILTIN_WUNPCKEHUB
,
20516 ARM_BUILTIN_WUNPCKEHUH
,
20517 ARM_BUILTIN_WUNPCKEHUW
,
20518 ARM_BUILTIN_WUNPCKELSB
,
20519 ARM_BUILTIN_WUNPCKELSH
,
20520 ARM_BUILTIN_WUNPCKELSW
,
20521 ARM_BUILTIN_WUNPCKELUB
,
20522 ARM_BUILTIN_WUNPCKELUH
,
20523 ARM_BUILTIN_WUNPCKELUW
,
20529 ARM_BUILTIN_WADDSUBHX
,
20530 ARM_BUILTIN_WSUBADDHX
,
20532 ARM_BUILTIN_WABSDIFFB
,
20533 ARM_BUILTIN_WABSDIFFH
,
20534 ARM_BUILTIN_WABSDIFFW
,
20536 ARM_BUILTIN_WADDCH
,
20537 ARM_BUILTIN_WADDCW
,
20540 ARM_BUILTIN_WAVG4R
,
20542 ARM_BUILTIN_WMADDSX
,
20543 ARM_BUILTIN_WMADDUX
,
20545 ARM_BUILTIN_WMADDSN
,
20546 ARM_BUILTIN_WMADDUN
,
20548 ARM_BUILTIN_WMULWSM
,
20549 ARM_BUILTIN_WMULWUM
,
20551 ARM_BUILTIN_WMULWSMR
,
20552 ARM_BUILTIN_WMULWUMR
,
20554 ARM_BUILTIN_WMULWL
,
20556 ARM_BUILTIN_WMULSMR
,
20557 ARM_BUILTIN_WMULUMR
,
20559 ARM_BUILTIN_WQMULM
,
20560 ARM_BUILTIN_WQMULMR
,
20562 ARM_BUILTIN_WQMULWM
,
20563 ARM_BUILTIN_WQMULWMR
,
20565 ARM_BUILTIN_WADDBHUSM
,
20566 ARM_BUILTIN_WADDBHUSL
,
20568 ARM_BUILTIN_WQMIABB
,
20569 ARM_BUILTIN_WQMIABT
,
20570 ARM_BUILTIN_WQMIATB
,
20571 ARM_BUILTIN_WQMIATT
,
20573 ARM_BUILTIN_WQMIABBN
,
20574 ARM_BUILTIN_WQMIABTN
,
20575 ARM_BUILTIN_WQMIATBN
,
20576 ARM_BUILTIN_WQMIATTN
,
20578 ARM_BUILTIN_WMIABB
,
20579 ARM_BUILTIN_WMIABT
,
20580 ARM_BUILTIN_WMIATB
,
20581 ARM_BUILTIN_WMIATT
,
20583 ARM_BUILTIN_WMIABBN
,
20584 ARM_BUILTIN_WMIABTN
,
20585 ARM_BUILTIN_WMIATBN
,
20586 ARM_BUILTIN_WMIATTN
,
20588 ARM_BUILTIN_WMIAWBB
,
20589 ARM_BUILTIN_WMIAWBT
,
20590 ARM_BUILTIN_WMIAWTB
,
20591 ARM_BUILTIN_WMIAWTT
,
20593 ARM_BUILTIN_WMIAWBBN
,
20594 ARM_BUILTIN_WMIAWBTN
,
20595 ARM_BUILTIN_WMIAWTBN
,
20596 ARM_BUILTIN_WMIAWTTN
,
20598 ARM_BUILTIN_WMERGE
,
20600 #include "arm_neon_builtins.def"
20605 #define ARM_BUILTIN_NEON_BASE (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data))
20619 static GTY(()) tree arm_builtin_decls
[ARM_BUILTIN_MAX
];
20622 arm_init_neon_builtins (void)
20624 unsigned int i
, fcode
;
20627 tree neon_intQI_type_node
;
20628 tree neon_intHI_type_node
;
20629 tree neon_floatHF_type_node
;
20630 tree neon_polyQI_type_node
;
20631 tree neon_polyHI_type_node
;
20632 tree neon_intSI_type_node
;
20633 tree neon_intDI_type_node
;
20634 tree neon_float_type_node
;
20636 tree intQI_pointer_node
;
20637 tree intHI_pointer_node
;
20638 tree intSI_pointer_node
;
20639 tree intDI_pointer_node
;
20640 tree float_pointer_node
;
20642 tree const_intQI_node
;
20643 tree const_intHI_node
;
20644 tree const_intSI_node
;
20645 tree const_intDI_node
;
20646 tree const_float_node
;
20648 tree const_intQI_pointer_node
;
20649 tree const_intHI_pointer_node
;
20650 tree const_intSI_pointer_node
;
20651 tree const_intDI_pointer_node
;
20652 tree const_float_pointer_node
;
20654 tree V8QI_type_node
;
20655 tree V4HI_type_node
;
20656 tree V4HF_type_node
;
20657 tree V2SI_type_node
;
20658 tree V2SF_type_node
;
20659 tree V16QI_type_node
;
20660 tree V8HI_type_node
;
20661 tree V4SI_type_node
;
20662 tree V4SF_type_node
;
20663 tree V2DI_type_node
;
20665 tree intUQI_type_node
;
20666 tree intUHI_type_node
;
20667 tree intUSI_type_node
;
20668 tree intUDI_type_node
;
20670 tree intEI_type_node
;
20671 tree intOI_type_node
;
20672 tree intCI_type_node
;
20673 tree intXI_type_node
;
20675 tree V8QI_pointer_node
;
20676 tree V4HI_pointer_node
;
20677 tree V2SI_pointer_node
;
20678 tree V2SF_pointer_node
;
20679 tree V16QI_pointer_node
;
20680 tree V8HI_pointer_node
;
20681 tree V4SI_pointer_node
;
20682 tree V4SF_pointer_node
;
20683 tree V2DI_pointer_node
;
20685 tree void_ftype_pv8qi_v8qi_v8qi
;
20686 tree void_ftype_pv4hi_v4hi_v4hi
;
20687 tree void_ftype_pv2si_v2si_v2si
;
20688 tree void_ftype_pv2sf_v2sf_v2sf
;
20689 tree void_ftype_pdi_di_di
;
20690 tree void_ftype_pv16qi_v16qi_v16qi
;
20691 tree void_ftype_pv8hi_v8hi_v8hi
;
20692 tree void_ftype_pv4si_v4si_v4si
;
20693 tree void_ftype_pv4sf_v4sf_v4sf
;
20694 tree void_ftype_pv2di_v2di_v2di
;
20696 tree reinterp_ftype_dreg
[5][5];
20697 tree reinterp_ftype_qreg
[5][5];
20698 tree dreg_types
[5], qreg_types
[5];
20700 /* Create distinguished type nodes for NEON vector element types,
20701 and pointers to values of such types, so we can detect them later. */
20702 neon_intQI_type_node
= make_signed_type (GET_MODE_PRECISION (QImode
));
20703 neon_intHI_type_node
= make_signed_type (GET_MODE_PRECISION (HImode
));
20704 neon_polyQI_type_node
= make_signed_type (GET_MODE_PRECISION (QImode
));
20705 neon_polyHI_type_node
= make_signed_type (GET_MODE_PRECISION (HImode
));
20706 neon_intSI_type_node
= make_signed_type (GET_MODE_PRECISION (SImode
));
20707 neon_intDI_type_node
= make_signed_type (GET_MODE_PRECISION (DImode
));
20708 neon_float_type_node
= make_node (REAL_TYPE
);
20709 TYPE_PRECISION (neon_float_type_node
) = FLOAT_TYPE_SIZE
;
20710 layout_type (neon_float_type_node
);
20711 neon_floatHF_type_node
= make_node (REAL_TYPE
);
20712 TYPE_PRECISION (neon_floatHF_type_node
) = GET_MODE_PRECISION (HFmode
);
20713 layout_type (neon_floatHF_type_node
);
20715 /* Define typedefs which exactly correspond to the modes we are basing vector
20716 types on. If you change these names you'll need to change
20717 the table used by arm_mangle_type too. */
20718 (*lang_hooks
.types
.register_builtin_type
) (neon_intQI_type_node
,
20719 "__builtin_neon_qi");
20720 (*lang_hooks
.types
.register_builtin_type
) (neon_intHI_type_node
,
20721 "__builtin_neon_hi");
20722 (*lang_hooks
.types
.register_builtin_type
) (neon_floatHF_type_node
,
20723 "__builtin_neon_hf");
20724 (*lang_hooks
.types
.register_builtin_type
) (neon_intSI_type_node
,
20725 "__builtin_neon_si");
20726 (*lang_hooks
.types
.register_builtin_type
) (neon_float_type_node
,
20727 "__builtin_neon_sf");
20728 (*lang_hooks
.types
.register_builtin_type
) (neon_intDI_type_node
,
20729 "__builtin_neon_di");
20730 (*lang_hooks
.types
.register_builtin_type
) (neon_polyQI_type_node
,
20731 "__builtin_neon_poly8");
20732 (*lang_hooks
.types
.register_builtin_type
) (neon_polyHI_type_node
,
20733 "__builtin_neon_poly16");
20735 intQI_pointer_node
= build_pointer_type (neon_intQI_type_node
);
20736 intHI_pointer_node
= build_pointer_type (neon_intHI_type_node
);
20737 intSI_pointer_node
= build_pointer_type (neon_intSI_type_node
);
20738 intDI_pointer_node
= build_pointer_type (neon_intDI_type_node
);
20739 float_pointer_node
= build_pointer_type (neon_float_type_node
);
20741 /* Next create constant-qualified versions of the above types. */
20742 const_intQI_node
= build_qualified_type (neon_intQI_type_node
,
20744 const_intHI_node
= build_qualified_type (neon_intHI_type_node
,
20746 const_intSI_node
= build_qualified_type (neon_intSI_type_node
,
20748 const_intDI_node
= build_qualified_type (neon_intDI_type_node
,
20750 const_float_node
= build_qualified_type (neon_float_type_node
,
20753 const_intQI_pointer_node
= build_pointer_type (const_intQI_node
);
20754 const_intHI_pointer_node
= build_pointer_type (const_intHI_node
);
20755 const_intSI_pointer_node
= build_pointer_type (const_intSI_node
);
20756 const_intDI_pointer_node
= build_pointer_type (const_intDI_node
);
20757 const_float_pointer_node
= build_pointer_type (const_float_node
);
20759 /* Now create vector types based on our NEON element types. */
20760 /* 64-bit vectors. */
20762 build_vector_type_for_mode (neon_intQI_type_node
, V8QImode
);
20764 build_vector_type_for_mode (neon_intHI_type_node
, V4HImode
);
20766 build_vector_type_for_mode (neon_floatHF_type_node
, V4HFmode
);
20768 build_vector_type_for_mode (neon_intSI_type_node
, V2SImode
);
20770 build_vector_type_for_mode (neon_float_type_node
, V2SFmode
);
20771 /* 128-bit vectors. */
20773 build_vector_type_for_mode (neon_intQI_type_node
, V16QImode
);
20775 build_vector_type_for_mode (neon_intHI_type_node
, V8HImode
);
20777 build_vector_type_for_mode (neon_intSI_type_node
, V4SImode
);
20779 build_vector_type_for_mode (neon_float_type_node
, V4SFmode
);
20781 build_vector_type_for_mode (neon_intDI_type_node
, V2DImode
);
20783 /* Unsigned integer types for various mode sizes. */
20784 intUQI_type_node
= make_unsigned_type (GET_MODE_PRECISION (QImode
));
20785 intUHI_type_node
= make_unsigned_type (GET_MODE_PRECISION (HImode
));
20786 intUSI_type_node
= make_unsigned_type (GET_MODE_PRECISION (SImode
));
20787 intUDI_type_node
= make_unsigned_type (GET_MODE_PRECISION (DImode
));
20789 (*lang_hooks
.types
.register_builtin_type
) (intUQI_type_node
,
20790 "__builtin_neon_uqi");
20791 (*lang_hooks
.types
.register_builtin_type
) (intUHI_type_node
,
20792 "__builtin_neon_uhi");
20793 (*lang_hooks
.types
.register_builtin_type
) (intUSI_type_node
,
20794 "__builtin_neon_usi");
20795 (*lang_hooks
.types
.register_builtin_type
) (intUDI_type_node
,
20796 "__builtin_neon_udi");
20798 /* Opaque integer types for structures of vectors. */
20799 intEI_type_node
= make_signed_type (GET_MODE_PRECISION (EImode
));
20800 intOI_type_node
= make_signed_type (GET_MODE_PRECISION (OImode
));
20801 intCI_type_node
= make_signed_type (GET_MODE_PRECISION (CImode
));
20802 intXI_type_node
= make_signed_type (GET_MODE_PRECISION (XImode
));
20804 (*lang_hooks
.types
.register_builtin_type
) (intTI_type_node
,
20805 "__builtin_neon_ti");
20806 (*lang_hooks
.types
.register_builtin_type
) (intEI_type_node
,
20807 "__builtin_neon_ei");
20808 (*lang_hooks
.types
.register_builtin_type
) (intOI_type_node
,
20809 "__builtin_neon_oi");
20810 (*lang_hooks
.types
.register_builtin_type
) (intCI_type_node
,
20811 "__builtin_neon_ci");
20812 (*lang_hooks
.types
.register_builtin_type
) (intXI_type_node
,
20813 "__builtin_neon_xi");
20815 /* Pointers to vector types. */
20816 V8QI_pointer_node
= build_pointer_type (V8QI_type_node
);
20817 V4HI_pointer_node
= build_pointer_type (V4HI_type_node
);
20818 V2SI_pointer_node
= build_pointer_type (V2SI_type_node
);
20819 V2SF_pointer_node
= build_pointer_type (V2SF_type_node
);
20820 V16QI_pointer_node
= build_pointer_type (V16QI_type_node
);
20821 V8HI_pointer_node
= build_pointer_type (V8HI_type_node
);
20822 V4SI_pointer_node
= build_pointer_type (V4SI_type_node
);
20823 V4SF_pointer_node
= build_pointer_type (V4SF_type_node
);
20824 V2DI_pointer_node
= build_pointer_type (V2DI_type_node
);
20826 /* Operations which return results as pairs. */
20827 void_ftype_pv8qi_v8qi_v8qi
=
20828 build_function_type_list (void_type_node
, V8QI_pointer_node
, V8QI_type_node
,
20829 V8QI_type_node
, NULL
);
20830 void_ftype_pv4hi_v4hi_v4hi
=
20831 build_function_type_list (void_type_node
, V4HI_pointer_node
, V4HI_type_node
,
20832 V4HI_type_node
, NULL
);
20833 void_ftype_pv2si_v2si_v2si
=
20834 build_function_type_list (void_type_node
, V2SI_pointer_node
, V2SI_type_node
,
20835 V2SI_type_node
, NULL
);
20836 void_ftype_pv2sf_v2sf_v2sf
=
20837 build_function_type_list (void_type_node
, V2SF_pointer_node
, V2SF_type_node
,
20838 V2SF_type_node
, NULL
);
20839 void_ftype_pdi_di_di
=
20840 build_function_type_list (void_type_node
, intDI_pointer_node
,
20841 neon_intDI_type_node
, neon_intDI_type_node
, NULL
);
20842 void_ftype_pv16qi_v16qi_v16qi
=
20843 build_function_type_list (void_type_node
, V16QI_pointer_node
,
20844 V16QI_type_node
, V16QI_type_node
, NULL
);
20845 void_ftype_pv8hi_v8hi_v8hi
=
20846 build_function_type_list (void_type_node
, V8HI_pointer_node
, V8HI_type_node
,
20847 V8HI_type_node
, NULL
);
20848 void_ftype_pv4si_v4si_v4si
=
20849 build_function_type_list (void_type_node
, V4SI_pointer_node
, V4SI_type_node
,
20850 V4SI_type_node
, NULL
);
20851 void_ftype_pv4sf_v4sf_v4sf
=
20852 build_function_type_list (void_type_node
, V4SF_pointer_node
, V4SF_type_node
,
20853 V4SF_type_node
, NULL
);
20854 void_ftype_pv2di_v2di_v2di
=
20855 build_function_type_list (void_type_node
, V2DI_pointer_node
, V2DI_type_node
,
20856 V2DI_type_node
, NULL
);
20858 dreg_types
[0] = V8QI_type_node
;
20859 dreg_types
[1] = V4HI_type_node
;
20860 dreg_types
[2] = V2SI_type_node
;
20861 dreg_types
[3] = V2SF_type_node
;
20862 dreg_types
[4] = neon_intDI_type_node
;
20864 qreg_types
[0] = V16QI_type_node
;
20865 qreg_types
[1] = V8HI_type_node
;
20866 qreg_types
[2] = V4SI_type_node
;
20867 qreg_types
[3] = V4SF_type_node
;
20868 qreg_types
[4] = V2DI_type_node
;
20870 for (i
= 0; i
< 5; i
++)
20873 for (j
= 0; j
< 5; j
++)
20875 reinterp_ftype_dreg
[i
][j
]
20876 = build_function_type_list (dreg_types
[i
], dreg_types
[j
], NULL
);
20877 reinterp_ftype_qreg
[i
][j
]
20878 = build_function_type_list (qreg_types
[i
], qreg_types
[j
], NULL
);
20882 for (i
= 0, fcode
= ARM_BUILTIN_NEON_BASE
;
20883 i
< ARRAY_SIZE (neon_builtin_data
);
20886 neon_builtin_datum
*d
= &neon_builtin_data
[i
];
20888 const char* const modenames
[] = {
20889 "v8qi", "v4hi", "v4hf", "v2si", "v2sf", "di",
20890 "v16qi", "v8hi", "v4si", "v4sf", "v2di",
20895 int is_load
= 0, is_store
= 0;
20897 gcc_assert (ARRAY_SIZE (modenames
) == T_MAX
);
20904 case NEON_LOAD1LANE
:
20905 case NEON_LOADSTRUCT
:
20906 case NEON_LOADSTRUCTLANE
:
20908 /* Fall through. */
20910 case NEON_STORE1LANE
:
20911 case NEON_STORESTRUCT
:
20912 case NEON_STORESTRUCTLANE
:
20915 /* Fall through. */
20919 case NEON_LOGICBINOP
:
20920 case NEON_SHIFTINSERT
:
20927 case NEON_SHIFTIMM
:
20928 case NEON_SHIFTACC
:
20934 case NEON_LANEMULL
:
20935 case NEON_LANEMULH
:
20937 case NEON_SCALARMUL
:
20938 case NEON_SCALARMULL
:
20939 case NEON_SCALARMULH
:
20940 case NEON_SCALARMAC
:
20946 tree return_type
= void_type_node
, args
= void_list_node
;
20948 /* Build a function type directly from the insn_data for
20949 this builtin. The build_function_type() function takes
20950 care of removing duplicates for us. */
20951 for (k
= insn_data
[d
->code
].n_generator_args
- 1; k
>= 0; k
--)
20955 if (is_load
&& k
== 1)
20957 /* Neon load patterns always have the memory
20958 operand in the operand 1 position. */
20959 gcc_assert (insn_data
[d
->code
].operand
[k
].predicate
20960 == neon_struct_operand
);
20966 eltype
= const_intQI_pointer_node
;
20971 eltype
= const_intHI_pointer_node
;
20976 eltype
= const_intSI_pointer_node
;
20981 eltype
= const_float_pointer_node
;
20986 eltype
= const_intDI_pointer_node
;
20989 default: gcc_unreachable ();
20992 else if (is_store
&& k
== 0)
20994 /* Similarly, Neon store patterns use operand 0 as
20995 the memory location to store to. */
20996 gcc_assert (insn_data
[d
->code
].operand
[k
].predicate
20997 == neon_struct_operand
);
21003 eltype
= intQI_pointer_node
;
21008 eltype
= intHI_pointer_node
;
21013 eltype
= intSI_pointer_node
;
21018 eltype
= float_pointer_node
;
21023 eltype
= intDI_pointer_node
;
21026 default: gcc_unreachable ();
21031 switch (insn_data
[d
->code
].operand
[k
].mode
)
21033 case VOIDmode
: eltype
= void_type_node
; break;
21035 case QImode
: eltype
= neon_intQI_type_node
; break;
21036 case HImode
: eltype
= neon_intHI_type_node
; break;
21037 case SImode
: eltype
= neon_intSI_type_node
; break;
21038 case SFmode
: eltype
= neon_float_type_node
; break;
21039 case DImode
: eltype
= neon_intDI_type_node
; break;
21040 case TImode
: eltype
= intTI_type_node
; break;
21041 case EImode
: eltype
= intEI_type_node
; break;
21042 case OImode
: eltype
= intOI_type_node
; break;
21043 case CImode
: eltype
= intCI_type_node
; break;
21044 case XImode
: eltype
= intXI_type_node
; break;
21045 /* 64-bit vectors. */
21046 case V8QImode
: eltype
= V8QI_type_node
; break;
21047 case V4HImode
: eltype
= V4HI_type_node
; break;
21048 case V2SImode
: eltype
= V2SI_type_node
; break;
21049 case V2SFmode
: eltype
= V2SF_type_node
; break;
21050 /* 128-bit vectors. */
21051 case V16QImode
: eltype
= V16QI_type_node
; break;
21052 case V8HImode
: eltype
= V8HI_type_node
; break;
21053 case V4SImode
: eltype
= V4SI_type_node
; break;
21054 case V4SFmode
: eltype
= V4SF_type_node
; break;
21055 case V2DImode
: eltype
= V2DI_type_node
; break;
21056 default: gcc_unreachable ();
21060 if (k
== 0 && !is_store
)
21061 return_type
= eltype
;
21063 args
= tree_cons (NULL_TREE
, eltype
, args
);
21066 ftype
= build_function_type (return_type
, args
);
21070 case NEON_RESULTPAIR
:
21072 switch (insn_data
[d
->code
].operand
[1].mode
)
21074 case V8QImode
: ftype
= void_ftype_pv8qi_v8qi_v8qi
; break;
21075 case V4HImode
: ftype
= void_ftype_pv4hi_v4hi_v4hi
; break;
21076 case V2SImode
: ftype
= void_ftype_pv2si_v2si_v2si
; break;
21077 case V2SFmode
: ftype
= void_ftype_pv2sf_v2sf_v2sf
; break;
21078 case DImode
: ftype
= void_ftype_pdi_di_di
; break;
21079 case V16QImode
: ftype
= void_ftype_pv16qi_v16qi_v16qi
; break;
21080 case V8HImode
: ftype
= void_ftype_pv8hi_v8hi_v8hi
; break;
21081 case V4SImode
: ftype
= void_ftype_pv4si_v4si_v4si
; break;
21082 case V4SFmode
: ftype
= void_ftype_pv4sf_v4sf_v4sf
; break;
21083 case V2DImode
: ftype
= void_ftype_pv2di_v2di_v2di
; break;
21084 default: gcc_unreachable ();
21089 case NEON_REINTERP
:
21091 /* We iterate over 5 doubleword types, then 5 quadword
21092 types. V4HF is not a type used in reinterpret, so we translate
21093 d->mode to the correct index in reinterp_ftype_dreg. */
21094 int rhs
= (d
->mode
- ((d
->mode
> T_V4HF
) ? 1 : 0)) % 5;
21095 switch (insn_data
[d
->code
].operand
[0].mode
)
21097 case V8QImode
: ftype
= reinterp_ftype_dreg
[0][rhs
]; break;
21098 case V4HImode
: ftype
= reinterp_ftype_dreg
[1][rhs
]; break;
21099 case V2SImode
: ftype
= reinterp_ftype_dreg
[2][rhs
]; break;
21100 case V2SFmode
: ftype
= reinterp_ftype_dreg
[3][rhs
]; break;
21101 case DImode
: ftype
= reinterp_ftype_dreg
[4][rhs
]; break;
21102 case V16QImode
: ftype
= reinterp_ftype_qreg
[0][rhs
]; break;
21103 case V8HImode
: ftype
= reinterp_ftype_qreg
[1][rhs
]; break;
21104 case V4SImode
: ftype
= reinterp_ftype_qreg
[2][rhs
]; break;
21105 case V4SFmode
: ftype
= reinterp_ftype_qreg
[3][rhs
]; break;
21106 case V2DImode
: ftype
= reinterp_ftype_qreg
[4][rhs
]; break;
21107 default: gcc_unreachable ();
21111 case NEON_FLOAT_WIDEN
:
21113 tree eltype
= NULL_TREE
;
21114 tree return_type
= NULL_TREE
;
21116 switch (insn_data
[d
->code
].operand
[1].mode
)
21119 eltype
= V4HF_type_node
;
21120 return_type
= V4SF_type_node
;
21122 default: gcc_unreachable ();
21124 ftype
= build_function_type_list (return_type
, eltype
, NULL
);
21127 case NEON_FLOAT_NARROW
:
21129 tree eltype
= NULL_TREE
;
21130 tree return_type
= NULL_TREE
;
21132 switch (insn_data
[d
->code
].operand
[1].mode
)
21135 eltype
= V4SF_type_node
;
21136 return_type
= V4HF_type_node
;
21138 default: gcc_unreachable ();
21140 ftype
= build_function_type_list (return_type
, eltype
, NULL
);
21144 gcc_unreachable ();
21147 gcc_assert (ftype
!= NULL
);
21149 sprintf (namebuf
, "__builtin_neon_%s%s", d
->name
, modenames
[d
->mode
]);
21151 decl
= add_builtin_function (namebuf
, ftype
, fcode
, BUILT_IN_MD
, NULL
,
21153 arm_builtin_decls
[fcode
] = decl
;
21157 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
21160 if ((MASK) & insn_flags) \
21163 bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \
21164 BUILT_IN_MD, NULL, NULL_TREE); \
21165 arm_builtin_decls[CODE] = bdecl; \
21170 struct builtin_description
21172 const unsigned int mask
;
21173 const enum insn_code icode
;
21174 const char * const name
;
21175 const enum arm_builtins code
;
21176 const enum rtx_code comparison
;
21177 const unsigned int flag
;
21180 static const struct builtin_description bdesc_2arg
[] =
21182 #define IWMMXT_BUILTIN(code, string, builtin) \
21183 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
21184 ARM_BUILTIN_##builtin, UNKNOWN, 0 },
21186 #define IWMMXT2_BUILTIN(code, string, builtin) \
21187 { FL_IWMMXT2, CODE_FOR_##code, "__builtin_arm_" string, \
21188 ARM_BUILTIN_##builtin, UNKNOWN, 0 },
21190 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
21191 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
21192 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
21193 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
21194 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
21195 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
21196 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
21197 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
21198 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
21199 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
21200 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
21201 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
21202 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
21203 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
21204 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
21205 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
21206 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
21207 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
21208 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
21209 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
21210 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
21211 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
21212 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
21213 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
21214 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
21215 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
21216 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
21217 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
21218 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
21219 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
21220 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
21221 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
21222 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
21223 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
21224 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
21225 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
21226 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
21227 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
21228 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
21229 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
21230 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
21231 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
21232 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
21233 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
21234 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
21235 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
21236 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
21237 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
21238 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
21239 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
21240 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
21241 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
21242 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
21243 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
21244 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
21245 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
21246 IWMMXT2_BUILTIN (iwmmxt_waddsubhx
, "waddsubhx", WADDSUBHX
)
21247 IWMMXT2_BUILTIN (iwmmxt_wsubaddhx
, "wsubaddhx", WSUBADDHX
)
21248 IWMMXT2_BUILTIN (iwmmxt_wabsdiffb
, "wabsdiffb", WABSDIFFB
)
21249 IWMMXT2_BUILTIN (iwmmxt_wabsdiffh
, "wabsdiffh", WABSDIFFH
)
21250 IWMMXT2_BUILTIN (iwmmxt_wabsdiffw
, "wabsdiffw", WABSDIFFW
)
21251 IWMMXT2_BUILTIN (iwmmxt_avg4
, "wavg4", WAVG4
)
21252 IWMMXT2_BUILTIN (iwmmxt_avg4r
, "wavg4r", WAVG4R
)
21253 IWMMXT2_BUILTIN (iwmmxt_wmulwsm
, "wmulwsm", WMULWSM
)
21254 IWMMXT2_BUILTIN (iwmmxt_wmulwum
, "wmulwum", WMULWUM
)
21255 IWMMXT2_BUILTIN (iwmmxt_wmulwsmr
, "wmulwsmr", WMULWSMR
)
21256 IWMMXT2_BUILTIN (iwmmxt_wmulwumr
, "wmulwumr", WMULWUMR
)
21257 IWMMXT2_BUILTIN (iwmmxt_wmulwl
, "wmulwl", WMULWL
)
21258 IWMMXT2_BUILTIN (iwmmxt_wmulsmr
, "wmulsmr", WMULSMR
)
21259 IWMMXT2_BUILTIN (iwmmxt_wmulumr
, "wmulumr", WMULUMR
)
21260 IWMMXT2_BUILTIN (iwmmxt_wqmulm
, "wqmulm", WQMULM
)
21261 IWMMXT2_BUILTIN (iwmmxt_wqmulmr
, "wqmulmr", WQMULMR
)
21262 IWMMXT2_BUILTIN (iwmmxt_wqmulwm
, "wqmulwm", WQMULWM
)
21263 IWMMXT2_BUILTIN (iwmmxt_wqmulwmr
, "wqmulwmr", WQMULWMR
)
21264 IWMMXT_BUILTIN (iwmmxt_walignr0
, "walignr0", WALIGNR0
)
21265 IWMMXT_BUILTIN (iwmmxt_walignr1
, "walignr1", WALIGNR1
)
21266 IWMMXT_BUILTIN (iwmmxt_walignr2
, "walignr2", WALIGNR2
)
21267 IWMMXT_BUILTIN (iwmmxt_walignr3
, "walignr3", WALIGNR3
)
21269 #define IWMMXT_BUILTIN2(code, builtin) \
21270 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
21272 #define IWMMXT2_BUILTIN2(code, builtin) \
21273 { FL_IWMMXT2, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
21275 IWMMXT2_BUILTIN2 (iwmmxt_waddbhusm
, WADDBHUSM
)
21276 IWMMXT2_BUILTIN2 (iwmmxt_waddbhusl
, WADDBHUSL
)
21277 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
21278 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
21279 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
21280 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
21281 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
21282 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
21283 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
21284 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
21287 static const struct builtin_description bdesc_1arg
[] =
21289 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
21290 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
21291 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
21292 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
21293 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
21294 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
21295 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
21296 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
21297 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
21298 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
21299 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
21300 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
21301 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
21302 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
21303 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
21304 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
21305 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
21306 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
21307 IWMMXT2_BUILTIN (iwmmxt_wabsv8qi3
, "wabsb", WABSB
)
21308 IWMMXT2_BUILTIN (iwmmxt_wabsv4hi3
, "wabsh", WABSH
)
21309 IWMMXT2_BUILTIN (iwmmxt_wabsv2si3
, "wabsw", WABSW
)
21310 IWMMXT_BUILTIN (tbcstv8qi
, "tbcstb", TBCSTB
)
21311 IWMMXT_BUILTIN (tbcstv4hi
, "tbcsth", TBCSTH
)
21312 IWMMXT_BUILTIN (tbcstv2si
, "tbcstw", TBCSTW
)
21315 /* Set up all the iWMMXt builtins. This is not called if
21316 TARGET_IWMMXT is zero. */
21319 arm_init_iwmmxt_builtins (void)
21321 const struct builtin_description
* d
;
21324 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
21325 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
21326 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
21328 tree v8qi_ftype_v8qi_v8qi_int
21329 = build_function_type_list (V8QI_type_node
,
21330 V8QI_type_node
, V8QI_type_node
,
21331 integer_type_node
, NULL_TREE
);
21332 tree v4hi_ftype_v4hi_int
21333 = build_function_type_list (V4HI_type_node
,
21334 V4HI_type_node
, integer_type_node
, NULL_TREE
);
21335 tree v2si_ftype_v2si_int
21336 = build_function_type_list (V2SI_type_node
,
21337 V2SI_type_node
, integer_type_node
, NULL_TREE
);
21338 tree v2si_ftype_di_di
21339 = build_function_type_list (V2SI_type_node
,
21340 long_long_integer_type_node
,
21341 long_long_integer_type_node
,
21343 tree di_ftype_di_int
21344 = build_function_type_list (long_long_integer_type_node
,
21345 long_long_integer_type_node
,
21346 integer_type_node
, NULL_TREE
);
21347 tree di_ftype_di_int_int
21348 = build_function_type_list (long_long_integer_type_node
,
21349 long_long_integer_type_node
,
21351 integer_type_node
, NULL_TREE
);
21352 tree int_ftype_v8qi
21353 = build_function_type_list (integer_type_node
,
21354 V8QI_type_node
, NULL_TREE
);
21355 tree int_ftype_v4hi
21356 = build_function_type_list (integer_type_node
,
21357 V4HI_type_node
, NULL_TREE
);
21358 tree int_ftype_v2si
21359 = build_function_type_list (integer_type_node
,
21360 V2SI_type_node
, NULL_TREE
);
21361 tree int_ftype_v8qi_int
21362 = build_function_type_list (integer_type_node
,
21363 V8QI_type_node
, integer_type_node
, NULL_TREE
);
21364 tree int_ftype_v4hi_int
21365 = build_function_type_list (integer_type_node
,
21366 V4HI_type_node
, integer_type_node
, NULL_TREE
);
21367 tree int_ftype_v2si_int
21368 = build_function_type_list (integer_type_node
,
21369 V2SI_type_node
, integer_type_node
, NULL_TREE
);
21370 tree v8qi_ftype_v8qi_int_int
21371 = build_function_type_list (V8QI_type_node
,
21372 V8QI_type_node
, integer_type_node
,
21373 integer_type_node
, NULL_TREE
);
21374 tree v4hi_ftype_v4hi_int_int
21375 = build_function_type_list (V4HI_type_node
,
21376 V4HI_type_node
, integer_type_node
,
21377 integer_type_node
, NULL_TREE
);
21378 tree v2si_ftype_v2si_int_int
21379 = build_function_type_list (V2SI_type_node
,
21380 V2SI_type_node
, integer_type_node
,
21381 integer_type_node
, NULL_TREE
);
21382 /* Miscellaneous. */
21383 tree v8qi_ftype_v4hi_v4hi
21384 = build_function_type_list (V8QI_type_node
,
21385 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
21386 tree v4hi_ftype_v2si_v2si
21387 = build_function_type_list (V4HI_type_node
,
21388 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
21389 tree v8qi_ftype_v4hi_v8qi
21390 = build_function_type_list (V8QI_type_node
,
21391 V4HI_type_node
, V8QI_type_node
, NULL_TREE
);
21392 tree v2si_ftype_v4hi_v4hi
21393 = build_function_type_list (V2SI_type_node
,
21394 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
21395 tree v2si_ftype_v8qi_v8qi
21396 = build_function_type_list (V2SI_type_node
,
21397 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
21398 tree v4hi_ftype_v4hi_di
21399 = build_function_type_list (V4HI_type_node
,
21400 V4HI_type_node
, long_long_integer_type_node
,
21402 tree v2si_ftype_v2si_di
21403 = build_function_type_list (V2SI_type_node
,
21404 V2SI_type_node
, long_long_integer_type_node
,
21407 = build_function_type_list (long_long_unsigned_type_node
, NULL_TREE
);
21408 tree int_ftype_void
21409 = build_function_type_list (integer_type_node
, NULL_TREE
);
21411 = build_function_type_list (long_long_integer_type_node
,
21412 V8QI_type_node
, NULL_TREE
);
21414 = build_function_type_list (long_long_integer_type_node
,
21415 V4HI_type_node
, NULL_TREE
);
21417 = build_function_type_list (long_long_integer_type_node
,
21418 V2SI_type_node
, NULL_TREE
);
21419 tree v2si_ftype_v4hi
21420 = build_function_type_list (V2SI_type_node
,
21421 V4HI_type_node
, NULL_TREE
);
21422 tree v4hi_ftype_v8qi
21423 = build_function_type_list (V4HI_type_node
,
21424 V8QI_type_node
, NULL_TREE
);
21425 tree v8qi_ftype_v8qi
21426 = build_function_type_list (V8QI_type_node
,
21427 V8QI_type_node
, NULL_TREE
);
21428 tree v4hi_ftype_v4hi
21429 = build_function_type_list (V4HI_type_node
,
21430 V4HI_type_node
, NULL_TREE
);
21431 tree v2si_ftype_v2si
21432 = build_function_type_list (V2SI_type_node
,
21433 V2SI_type_node
, NULL_TREE
);
21435 tree di_ftype_di_v4hi_v4hi
21436 = build_function_type_list (long_long_unsigned_type_node
,
21437 long_long_unsigned_type_node
,
21438 V4HI_type_node
, V4HI_type_node
,
21441 tree di_ftype_v4hi_v4hi
21442 = build_function_type_list (long_long_unsigned_type_node
,
21443 V4HI_type_node
,V4HI_type_node
,
21446 tree v2si_ftype_v2si_v4hi_v4hi
21447 = build_function_type_list (V2SI_type_node
,
21448 V2SI_type_node
, V4HI_type_node
,
21449 V4HI_type_node
, NULL_TREE
);
21451 tree v2si_ftype_v2si_v8qi_v8qi
21452 = build_function_type_list (V2SI_type_node
,
21453 V2SI_type_node
, V8QI_type_node
,
21454 V8QI_type_node
, NULL_TREE
);
21456 tree di_ftype_di_v2si_v2si
21457 = build_function_type_list (long_long_unsigned_type_node
,
21458 long_long_unsigned_type_node
,
21459 V2SI_type_node
, V2SI_type_node
,
21462 tree di_ftype_di_di_int
21463 = build_function_type_list (long_long_unsigned_type_node
,
21464 long_long_unsigned_type_node
,
21465 long_long_unsigned_type_node
,
21466 integer_type_node
, NULL_TREE
);
21468 tree void_ftype_int
21469 = build_function_type_list (void_type_node
,
21470 integer_type_node
, NULL_TREE
);
21472 tree v8qi_ftype_char
21473 = build_function_type_list (V8QI_type_node
,
21474 signed_char_type_node
, NULL_TREE
);
21476 tree v4hi_ftype_short
21477 = build_function_type_list (V4HI_type_node
,
21478 short_integer_type_node
, NULL_TREE
);
21480 tree v2si_ftype_int
21481 = build_function_type_list (V2SI_type_node
,
21482 integer_type_node
, NULL_TREE
);
21484 /* Normal vector binops. */
21485 tree v8qi_ftype_v8qi_v8qi
21486 = build_function_type_list (V8QI_type_node
,
21487 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
21488 tree v4hi_ftype_v4hi_v4hi
21489 = build_function_type_list (V4HI_type_node
,
21490 V4HI_type_node
,V4HI_type_node
, NULL_TREE
);
21491 tree v2si_ftype_v2si_v2si
21492 = build_function_type_list (V2SI_type_node
,
21493 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
21494 tree di_ftype_di_di
21495 = build_function_type_list (long_long_unsigned_type_node
,
21496 long_long_unsigned_type_node
,
21497 long_long_unsigned_type_node
,
21500 /* Add all builtins that are more or less simple operations on two
21502 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
21504 /* Use one of the operands; the target can have a different mode for
21505 mask-generating compares. */
21506 enum machine_mode mode
;
21512 mode
= insn_data
[d
->icode
].operand
[1].mode
;
21517 type
= v8qi_ftype_v8qi_v8qi
;
21520 type
= v4hi_ftype_v4hi_v4hi
;
21523 type
= v2si_ftype_v2si_v2si
;
21526 type
= di_ftype_di_di
;
21530 gcc_unreachable ();
21533 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
21536 /* Add the remaining MMX insns with somewhat more complicated types. */
21537 #define iwmmx_mbuiltin(NAME, TYPE, CODE) \
21538 def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \
21539 ARM_BUILTIN_ ## CODE)
21541 #define iwmmx2_mbuiltin(NAME, TYPE, CODE) \
21542 def_mbuiltin (FL_IWMMXT2, "__builtin_arm_" NAME, (TYPE), \
21543 ARM_BUILTIN_ ## CODE)
21545 iwmmx_mbuiltin ("wzero", di_ftype_void
, WZERO
);
21546 iwmmx_mbuiltin ("setwcgr0", void_ftype_int
, SETWCGR0
);
21547 iwmmx_mbuiltin ("setwcgr1", void_ftype_int
, SETWCGR1
);
21548 iwmmx_mbuiltin ("setwcgr2", void_ftype_int
, SETWCGR2
);
21549 iwmmx_mbuiltin ("setwcgr3", void_ftype_int
, SETWCGR3
);
21550 iwmmx_mbuiltin ("getwcgr0", int_ftype_void
, GETWCGR0
);
21551 iwmmx_mbuiltin ("getwcgr1", int_ftype_void
, GETWCGR1
);
21552 iwmmx_mbuiltin ("getwcgr2", int_ftype_void
, GETWCGR2
);
21553 iwmmx_mbuiltin ("getwcgr3", int_ftype_void
, GETWCGR3
);
21555 iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di
, WSLLH
);
21556 iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di
, WSLLW
);
21557 iwmmx_mbuiltin ("wslld", di_ftype_di_di
, WSLLD
);
21558 iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int
, WSLLHI
);
21559 iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int
, WSLLWI
);
21560 iwmmx_mbuiltin ("wslldi", di_ftype_di_int
, WSLLDI
);
21562 iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di
, WSRLH
);
21563 iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di
, WSRLW
);
21564 iwmmx_mbuiltin ("wsrld", di_ftype_di_di
, WSRLD
);
21565 iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int
, WSRLHI
);
21566 iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int
, WSRLWI
);
21567 iwmmx_mbuiltin ("wsrldi", di_ftype_di_int
, WSRLDI
);
21569 iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di
, WSRAH
);
21570 iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di
, WSRAW
);
21571 iwmmx_mbuiltin ("wsrad", di_ftype_di_di
, WSRAD
);
21572 iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int
, WSRAHI
);
21573 iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int
, WSRAWI
);
21574 iwmmx_mbuiltin ("wsradi", di_ftype_di_int
, WSRADI
);
21576 iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di
, WRORH
);
21577 iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di
, WRORW
);
21578 iwmmx_mbuiltin ("wrord", di_ftype_di_di
, WRORD
);
21579 iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int
, WRORHI
);
21580 iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int
, WRORWI
);
21581 iwmmx_mbuiltin ("wrordi", di_ftype_di_int
, WRORDI
);
21583 iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int
, WSHUFH
);
21585 iwmmx_mbuiltin ("wsadb", v2si_ftype_v2si_v8qi_v8qi
, WSADB
);
21586 iwmmx_mbuiltin ("wsadh", v2si_ftype_v2si_v4hi_v4hi
, WSADH
);
21587 iwmmx_mbuiltin ("wmadds", v2si_ftype_v4hi_v4hi
, WMADDS
);
21588 iwmmx2_mbuiltin ("wmaddsx", v2si_ftype_v4hi_v4hi
, WMADDSX
);
21589 iwmmx2_mbuiltin ("wmaddsn", v2si_ftype_v4hi_v4hi
, WMADDSN
);
21590 iwmmx_mbuiltin ("wmaddu", v2si_ftype_v4hi_v4hi
, WMADDU
);
21591 iwmmx2_mbuiltin ("wmaddux", v2si_ftype_v4hi_v4hi
, WMADDUX
);
21592 iwmmx2_mbuiltin ("wmaddun", v2si_ftype_v4hi_v4hi
, WMADDUN
);
21593 iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi
, WSADBZ
);
21594 iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi
, WSADHZ
);
21596 iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int
, TEXTRMSB
);
21597 iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int
, TEXTRMSH
);
21598 iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int
, TEXTRMSW
);
21599 iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int
, TEXTRMUB
);
21600 iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int
, TEXTRMUH
);
21601 iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int
, TEXTRMUW
);
21602 iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int
, TINSRB
);
21603 iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int
, TINSRH
);
21604 iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int
, TINSRW
);
21606 iwmmx_mbuiltin ("waccb", di_ftype_v8qi
, WACCB
);
21607 iwmmx_mbuiltin ("wacch", di_ftype_v4hi
, WACCH
);
21608 iwmmx_mbuiltin ("waccw", di_ftype_v2si
, WACCW
);
21610 iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi
, TMOVMSKB
);
21611 iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi
, TMOVMSKH
);
21612 iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si
, TMOVMSKW
);
21614 iwmmx2_mbuiltin ("waddbhusm", v8qi_ftype_v4hi_v8qi
, WADDBHUSM
);
21615 iwmmx2_mbuiltin ("waddbhusl", v8qi_ftype_v4hi_v8qi
, WADDBHUSL
);
21617 iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi
, WPACKHSS
);
21618 iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi
, WPACKHUS
);
21619 iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si
, WPACKWUS
);
21620 iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si
, WPACKWSS
);
21621 iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di
, WPACKDUS
);
21622 iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di
, WPACKDSS
);
21624 iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi
, WUNPCKEHUB
);
21625 iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi
, WUNPCKEHUH
);
21626 iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si
, WUNPCKEHUW
);
21627 iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi
, WUNPCKEHSB
);
21628 iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi
, WUNPCKEHSH
);
21629 iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si
, WUNPCKEHSW
);
21630 iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi
, WUNPCKELUB
);
21631 iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi
, WUNPCKELUH
);
21632 iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si
, WUNPCKELUW
);
21633 iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi
, WUNPCKELSB
);
21634 iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi
, WUNPCKELSH
);
21635 iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si
, WUNPCKELSW
);
21637 iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi
, WMACS
);
21638 iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi
, WMACSZ
);
21639 iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi
, WMACU
);
21640 iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi
, WMACUZ
);
21642 iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int
, WALIGNI
);
21643 iwmmx_mbuiltin ("tmia", di_ftype_di_int_int
, TMIA
);
21644 iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int
, TMIAPH
);
21645 iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int
, TMIABB
);
21646 iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int
, TMIABT
);
21647 iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int
, TMIATB
);
21648 iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int
, TMIATT
);
21650 iwmmx2_mbuiltin ("wabsb", v8qi_ftype_v8qi
, WABSB
);
21651 iwmmx2_mbuiltin ("wabsh", v4hi_ftype_v4hi
, WABSH
);
21652 iwmmx2_mbuiltin ("wabsw", v2si_ftype_v2si
, WABSW
);
21654 iwmmx2_mbuiltin ("wqmiabb", v2si_ftype_v2si_v4hi_v4hi
, WQMIABB
);
21655 iwmmx2_mbuiltin ("wqmiabt", v2si_ftype_v2si_v4hi_v4hi
, WQMIABT
);
21656 iwmmx2_mbuiltin ("wqmiatb", v2si_ftype_v2si_v4hi_v4hi
, WQMIATB
);
21657 iwmmx2_mbuiltin ("wqmiatt", v2si_ftype_v2si_v4hi_v4hi
, WQMIATT
);
21659 iwmmx2_mbuiltin ("wqmiabbn", v2si_ftype_v2si_v4hi_v4hi
, WQMIABBN
);
21660 iwmmx2_mbuiltin ("wqmiabtn", v2si_ftype_v2si_v4hi_v4hi
, WQMIABTN
);
21661 iwmmx2_mbuiltin ("wqmiatbn", v2si_ftype_v2si_v4hi_v4hi
, WQMIATBN
);
21662 iwmmx2_mbuiltin ("wqmiattn", v2si_ftype_v2si_v4hi_v4hi
, WQMIATTN
);
21664 iwmmx2_mbuiltin ("wmiabb", di_ftype_di_v4hi_v4hi
, WMIABB
);
21665 iwmmx2_mbuiltin ("wmiabt", di_ftype_di_v4hi_v4hi
, WMIABT
);
21666 iwmmx2_mbuiltin ("wmiatb", di_ftype_di_v4hi_v4hi
, WMIATB
);
21667 iwmmx2_mbuiltin ("wmiatt", di_ftype_di_v4hi_v4hi
, WMIATT
);
21669 iwmmx2_mbuiltin ("wmiabbn", di_ftype_di_v4hi_v4hi
, WMIABBN
);
21670 iwmmx2_mbuiltin ("wmiabtn", di_ftype_di_v4hi_v4hi
, WMIABTN
);
21671 iwmmx2_mbuiltin ("wmiatbn", di_ftype_di_v4hi_v4hi
, WMIATBN
);
21672 iwmmx2_mbuiltin ("wmiattn", di_ftype_di_v4hi_v4hi
, WMIATTN
);
21674 iwmmx2_mbuiltin ("wmiawbb", di_ftype_di_v2si_v2si
, WMIAWBB
);
21675 iwmmx2_mbuiltin ("wmiawbt", di_ftype_di_v2si_v2si
, WMIAWBT
);
21676 iwmmx2_mbuiltin ("wmiawtb", di_ftype_di_v2si_v2si
, WMIAWTB
);
21677 iwmmx2_mbuiltin ("wmiawtt", di_ftype_di_v2si_v2si
, WMIAWTT
);
21679 iwmmx2_mbuiltin ("wmiawbbn", di_ftype_di_v2si_v2si
, WMIAWBBN
);
21680 iwmmx2_mbuiltin ("wmiawbtn", di_ftype_di_v2si_v2si
, WMIAWBTN
);
21681 iwmmx2_mbuiltin ("wmiawtbn", di_ftype_di_v2si_v2si
, WMIAWTBN
);
21682 iwmmx2_mbuiltin ("wmiawttn", di_ftype_di_v2si_v2si
, WMIAWTTN
);
21684 iwmmx2_mbuiltin ("wmerge", di_ftype_di_di_int
, WMERGE
);
21686 iwmmx_mbuiltin ("tbcstb", v8qi_ftype_char
, TBCSTB
);
21687 iwmmx_mbuiltin ("tbcsth", v4hi_ftype_short
, TBCSTH
);
21688 iwmmx_mbuiltin ("tbcstw", v2si_ftype_int
, TBCSTW
);
21690 #undef iwmmx_mbuiltin
21691 #undef iwmmx2_mbuiltin
21695 arm_init_fp16_builtins (void)
21697 tree fp16_type
= make_node (REAL_TYPE
);
21698 TYPE_PRECISION (fp16_type
) = 16;
21699 layout_type (fp16_type
);
21700 (*lang_hooks
.types
.register_builtin_type
) (fp16_type
, "__fp16");
21704 arm_init_builtins (void)
21706 if (TARGET_REALLY_IWMMXT
)
21707 arm_init_iwmmxt_builtins ();
21710 arm_init_neon_builtins ();
21712 if (arm_fp16_format
)
21713 arm_init_fp16_builtins ();
21716 /* Return the ARM builtin for CODE. */
21719 arm_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
21721 if (code
>= ARM_BUILTIN_MAX
)
21722 return error_mark_node
;
21724 return arm_builtin_decls
[code
];
21727 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
21729 static const char *
21730 arm_invalid_parameter_type (const_tree t
)
21732 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
21733 return N_("function parameters cannot have __fp16 type");
21737 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
21739 static const char *
21740 arm_invalid_return_type (const_tree t
)
21742 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
21743 return N_("functions cannot return __fp16 type");
21747 /* Implement TARGET_PROMOTED_TYPE. */
21750 arm_promoted_type (const_tree t
)
21752 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
21753 return float_type_node
;
21757 /* Implement TARGET_CONVERT_TO_TYPE.
21758 Specifically, this hook implements the peculiarity of the ARM
21759 half-precision floating-point C semantics that requires conversions between
21760 __fp16 to or from double to do an intermediate conversion to float. */
21763 arm_convert_to_type (tree type
, tree expr
)
21765 tree fromtype
= TREE_TYPE (expr
);
21766 if (!SCALAR_FLOAT_TYPE_P (fromtype
) || !SCALAR_FLOAT_TYPE_P (type
))
21768 if ((TYPE_PRECISION (fromtype
) == 16 && TYPE_PRECISION (type
) > 32)
21769 || (TYPE_PRECISION (type
) == 16 && TYPE_PRECISION (fromtype
) > 32))
21770 return convert (type
, convert (float_type_node
, expr
));
21774 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P.
21775 This simply adds HFmode as a supported mode; even though we don't
21776 implement arithmetic on this type directly, it's supported by
21777 optabs conversions, much the way the double-word arithmetic is
21778 special-cased in the default hook. */
21781 arm_scalar_mode_supported_p (enum machine_mode mode
)
21783 if (mode
== HFmode
)
21784 return (arm_fp16_format
!= ARM_FP16_FORMAT_NONE
);
21785 else if (ALL_FIXED_POINT_MODE_P (mode
))
21788 return default_scalar_mode_supported_p (mode
);
21791 /* Errors in the source file can cause expand_expr to return const0_rtx
21792 where we expect a vector. To avoid crashing, use one of the vector
21793 clear instructions. */
21796 safe_vector_operand (rtx x
, enum machine_mode mode
)
21798 if (x
!= const0_rtx
)
21800 x
= gen_reg_rtx (mode
);
21802 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
21803 : gen_rtx_SUBREG (DImode
, x
, 0)));
21807 /* Subroutine of arm_expand_builtin to take care of binop insns. */
21810 arm_expand_binop_builtin (enum insn_code icode
,
21811 tree exp
, rtx target
)
21814 tree arg0
= CALL_EXPR_ARG (exp
, 0);
21815 tree arg1
= CALL_EXPR_ARG (exp
, 1);
21816 rtx op0
= expand_normal (arg0
);
21817 rtx op1
= expand_normal (arg1
);
21818 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
21819 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
21820 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
21822 if (VECTOR_MODE_P (mode0
))
21823 op0
= safe_vector_operand (op0
, mode0
);
21824 if (VECTOR_MODE_P (mode1
))
21825 op1
= safe_vector_operand (op1
, mode1
);
21828 || GET_MODE (target
) != tmode
21829 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
21830 target
= gen_reg_rtx (tmode
);
21832 gcc_assert ((GET_MODE (op0
) == mode0
|| GET_MODE (op0
) == VOIDmode
)
21833 && (GET_MODE (op1
) == mode1
|| GET_MODE (op1
) == VOIDmode
));
21835 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
21836 op0
= copy_to_mode_reg (mode0
, op0
);
21837 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
21838 op1
= copy_to_mode_reg (mode1
, op1
);
21840 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
21847 /* Subroutine of arm_expand_builtin to take care of unop insns. */
21850 arm_expand_unop_builtin (enum insn_code icode
,
21851 tree exp
, rtx target
, int do_load
)
21854 tree arg0
= CALL_EXPR_ARG (exp
, 0);
21855 rtx op0
= expand_normal (arg0
);
21856 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
21857 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
21860 || GET_MODE (target
) != tmode
21861 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
21862 target
= gen_reg_rtx (tmode
);
21864 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
21867 if (VECTOR_MODE_P (mode0
))
21868 op0
= safe_vector_operand (op0
, mode0
);
21870 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
21871 op0
= copy_to_mode_reg (mode0
, op0
);
21874 pat
= GEN_FCN (icode
) (target
, op0
);
21882 NEON_ARG_COPY_TO_REG
,
21888 #define NEON_MAX_BUILTIN_ARGS 5
21890 /* EXP is a pointer argument to a Neon load or store intrinsic. Derive
21891 and return an expression for the accessed memory.
21893 The intrinsic function operates on a block of registers that has
21894 mode REG_MODE. This block contains vectors of type TYPE_MODE. The
21895 function references the memory at EXP of type TYPE and in mode
21896 MEM_MODE; this mode may be BLKmode if no more suitable mode is
21900 neon_dereference_pointer (tree exp
, tree type
, enum machine_mode mem_mode
,
21901 enum machine_mode reg_mode
,
21902 neon_builtin_type_mode type_mode
)
21904 HOST_WIDE_INT reg_size
, vector_size
, nvectors
, nelems
;
21905 tree elem_type
, upper_bound
, array_type
;
21907 /* Work out the size of the register block in bytes. */
21908 reg_size
= GET_MODE_SIZE (reg_mode
);
21910 /* Work out the size of each vector in bytes. */
21911 gcc_assert (TYPE_MODE_BIT (type_mode
) & (TB_DREG
| TB_QREG
));
21912 vector_size
= (TYPE_MODE_BIT (type_mode
) & TB_QREG
? 16 : 8);
21914 /* Work out how many vectors there are. */
21915 gcc_assert (reg_size
% vector_size
== 0);
21916 nvectors
= reg_size
/ vector_size
;
21918 /* Work out the type of each element. */
21919 gcc_assert (POINTER_TYPE_P (type
));
21920 elem_type
= TREE_TYPE (type
);
21922 /* Work out how many elements are being loaded or stored.
21923 MEM_MODE == REG_MODE implies a one-to-one mapping between register
21924 and memory elements; anything else implies a lane load or store. */
21925 if (mem_mode
== reg_mode
)
21926 nelems
= vector_size
* nvectors
/ int_size_in_bytes (elem_type
);
21930 /* Create a type that describes the full access. */
21931 upper_bound
= build_int_cst (size_type_node
, nelems
- 1);
21932 array_type
= build_array_type (elem_type
, build_index_type (upper_bound
));
21934 /* Dereference EXP using that type. */
21935 return fold_build2 (MEM_REF
, array_type
, exp
,
21936 build_int_cst (build_pointer_type (array_type
), 0));
21939 /* Expand a Neon builtin. */
21941 arm_expand_neon_args (rtx target
, int icode
, int have_retval
,
21942 neon_builtin_type_mode type_mode
,
21943 tree exp
, int fcode
, ...)
21947 tree arg
[NEON_MAX_BUILTIN_ARGS
];
21948 rtx op
[NEON_MAX_BUILTIN_ARGS
];
21951 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
21952 enum machine_mode mode
[NEON_MAX_BUILTIN_ARGS
];
21953 enum machine_mode other_mode
;
21959 || GET_MODE (target
) != tmode
21960 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
)))
21961 target
= gen_reg_rtx (tmode
);
21963 va_start (ap
, fcode
);
21965 formals
= TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls
[fcode
]));
21969 builtin_arg thisarg
= (builtin_arg
) va_arg (ap
, int);
21971 if (thisarg
== NEON_ARG_STOP
)
21975 opno
= argc
+ have_retval
;
21976 mode
[argc
] = insn_data
[icode
].operand
[opno
].mode
;
21977 arg
[argc
] = CALL_EXPR_ARG (exp
, argc
);
21978 arg_type
= TREE_VALUE (formals
);
21979 if (thisarg
== NEON_ARG_MEMORY
)
21981 other_mode
= insn_data
[icode
].operand
[1 - opno
].mode
;
21982 arg
[argc
] = neon_dereference_pointer (arg
[argc
], arg_type
,
21983 mode
[argc
], other_mode
,
21987 op
[argc
] = expand_normal (arg
[argc
]);
21991 case NEON_ARG_COPY_TO_REG
:
21992 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
21993 if (!(*insn_data
[icode
].operand
[opno
].predicate
)
21994 (op
[argc
], mode
[argc
]))
21995 op
[argc
] = copy_to_mode_reg (mode
[argc
], op
[argc
]);
21998 case NEON_ARG_CONSTANT
:
21999 /* FIXME: This error message is somewhat unhelpful. */
22000 if (!(*insn_data
[icode
].operand
[opno
].predicate
)
22001 (op
[argc
], mode
[argc
]))
22002 error ("argument must be a constant");
22005 case NEON_ARG_MEMORY
:
22006 gcc_assert (MEM_P (op
[argc
]));
22007 PUT_MODE (op
[argc
], mode
[argc
]);
22008 /* ??? arm_neon.h uses the same built-in functions for signed
22009 and unsigned accesses, casting where necessary. This isn't
22011 set_mem_alias_set (op
[argc
], 0);
22012 if (!(*insn_data
[icode
].operand
[opno
].predicate
)
22013 (op
[argc
], mode
[argc
]))
22014 op
[argc
] = (replace_equiv_address
22015 (op
[argc
], force_reg (Pmode
, XEXP (op
[argc
], 0))));
22018 case NEON_ARG_STOP
:
22019 gcc_unreachable ();
22023 formals
= TREE_CHAIN (formals
);
22033 pat
= GEN_FCN (icode
) (target
, op
[0]);
22037 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
22041 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2]);
22045 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3]);
22049 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4]);
22053 gcc_unreachable ();
22059 pat
= GEN_FCN (icode
) (op
[0]);
22063 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
22067 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
22071 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
22075 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4]);
22079 gcc_unreachable ();
22090 /* Expand a Neon builtin. These are "special" because they don't have symbolic
22091 constants defined per-instruction or per instruction-variant. Instead, the
22092 required info is looked up in the table neon_builtin_data. */
22094 arm_expand_neon_builtin (int fcode
, tree exp
, rtx target
)
22096 neon_builtin_datum
*d
= &neon_builtin_data
[fcode
- ARM_BUILTIN_NEON_BASE
];
22097 neon_itype itype
= d
->itype
;
22098 enum insn_code icode
= d
->code
;
22099 neon_builtin_type_mode type_mode
= d
->mode
;
22106 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22107 NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
22111 case NEON_SCALARMUL
:
22112 case NEON_SCALARMULL
:
22113 case NEON_SCALARMULH
:
22114 case NEON_SHIFTINSERT
:
22115 case NEON_LOGICBINOP
:
22116 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22117 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
22121 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22122 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
22123 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
22127 case NEON_SHIFTIMM
:
22128 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22129 NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
, NEON_ARG_CONSTANT
,
22133 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22134 NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
22139 case NEON_FLOAT_WIDEN
:
22140 case NEON_FLOAT_NARROW
:
22141 case NEON_REINTERP
:
22142 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22143 NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
22147 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22148 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
22150 case NEON_RESULTPAIR
:
22151 return arm_expand_neon_args (target
, icode
, 0, type_mode
, exp
, fcode
,
22152 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
22156 case NEON_LANEMULL
:
22157 case NEON_LANEMULH
:
22158 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22159 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
22160 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
22163 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22164 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
22165 NEON_ARG_CONSTANT
, NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
22167 case NEON_SHIFTACC
:
22168 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22169 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
22170 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
22172 case NEON_SCALARMAC
:
22173 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22174 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
22175 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
22179 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22180 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
22184 case NEON_LOADSTRUCT
:
22185 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22186 NEON_ARG_MEMORY
, NEON_ARG_STOP
);
22188 case NEON_LOAD1LANE
:
22189 case NEON_LOADSTRUCTLANE
:
22190 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
, fcode
,
22191 NEON_ARG_MEMORY
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
22195 case NEON_STORESTRUCT
:
22196 return arm_expand_neon_args (target
, icode
, 0, type_mode
, exp
, fcode
,
22197 NEON_ARG_MEMORY
, NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
22199 case NEON_STORE1LANE
:
22200 case NEON_STORESTRUCTLANE
:
22201 return arm_expand_neon_args (target
, icode
, 0, type_mode
, exp
, fcode
,
22202 NEON_ARG_MEMORY
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
22206 gcc_unreachable ();
22209 /* Emit code to reinterpret one Neon type as another, without altering bits. */
22211 neon_reinterpret (rtx dest
, rtx src
)
22213 emit_move_insn (dest
, gen_lowpart (GET_MODE (dest
), src
));
22216 /* Emit code to place a Neon pair result in memory locations (with equal
22219 neon_emit_pair_result_insn (enum machine_mode mode
,
22220 rtx (*intfn
) (rtx
, rtx
, rtx
, rtx
), rtx destaddr
,
22223 rtx mem
= gen_rtx_MEM (mode
, destaddr
);
22224 rtx tmp1
= gen_reg_rtx (mode
);
22225 rtx tmp2
= gen_reg_rtx (mode
);
22227 emit_insn (intfn (tmp1
, op1
, op2
, tmp2
));
22229 emit_move_insn (mem
, tmp1
);
22230 mem
= adjust_address (mem
, mode
, GET_MODE_SIZE (mode
));
22231 emit_move_insn (mem
, tmp2
);
22234 /* Set up OPERANDS for a register copy from SRC to DEST, taking care
22235 not to early-clobber SRC registers in the process.
22237 We assume that the operands described by SRC and DEST represent a
22238 decomposed copy of OPERANDS[1] into OPERANDS[0]. COUNT is the
22239 number of components into which the copy has been decomposed. */
22241 neon_disambiguate_copy (rtx
*operands
, rtx
*dest
, rtx
*src
, unsigned int count
)
22245 if (!reg_overlap_mentioned_p (operands
[0], operands
[1])
22246 || REGNO (operands
[0]) < REGNO (operands
[1]))
22248 for (i
= 0; i
< count
; i
++)
22250 operands
[2 * i
] = dest
[i
];
22251 operands
[2 * i
+ 1] = src
[i
];
22256 for (i
= 0; i
< count
; i
++)
22258 operands
[2 * i
] = dest
[count
- i
- 1];
22259 operands
[2 * i
+ 1] = src
[count
- i
- 1];
22264 /* Split operands into moves from op[1] + op[2] into op[0]. */
22267 neon_split_vcombine (rtx operands
[3])
22269 unsigned int dest
= REGNO (operands
[0]);
22270 unsigned int src1
= REGNO (operands
[1]);
22271 unsigned int src2
= REGNO (operands
[2]);
22272 enum machine_mode halfmode
= GET_MODE (operands
[1]);
22273 unsigned int halfregs
= HARD_REGNO_NREGS (src1
, halfmode
);
22274 rtx destlo
, desthi
;
22276 if (src1
== dest
&& src2
== dest
+ halfregs
)
22278 /* No-op move. Can't split to nothing; emit something. */
22279 emit_note (NOTE_INSN_DELETED
);
22283 /* Preserve register attributes for variable tracking. */
22284 destlo
= gen_rtx_REG_offset (operands
[0], halfmode
, dest
, 0);
22285 desthi
= gen_rtx_REG_offset (operands
[0], halfmode
, dest
+ halfregs
,
22286 GET_MODE_SIZE (halfmode
));
22288 /* Special case of reversed high/low parts. Use VSWP. */
22289 if (src2
== dest
&& src1
== dest
+ halfregs
)
22291 rtx x
= gen_rtx_SET (VOIDmode
, destlo
, operands
[1]);
22292 rtx y
= gen_rtx_SET (VOIDmode
, desthi
, operands
[2]);
22293 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x
, y
)));
22297 if (!reg_overlap_mentioned_p (operands
[2], destlo
))
22299 /* Try to avoid unnecessary moves if part of the result
22300 is in the right place already. */
22302 emit_move_insn (destlo
, operands
[1]);
22303 if (src2
!= dest
+ halfregs
)
22304 emit_move_insn (desthi
, operands
[2]);
22308 if (src2
!= dest
+ halfregs
)
22309 emit_move_insn (desthi
, operands
[2]);
22311 emit_move_insn (destlo
, operands
[1]);
22315 /* Expand an expression EXP that calls a built-in function,
22316 with result going to TARGET if that's convenient
22317 (and in mode MODE if that's convenient).
22318 SUBTARGET may be used as the target for computing one of EXP's operands.
22319 IGNORE is nonzero if the value is to be ignored. */
22322 arm_expand_builtin (tree exp
,
22324 rtx subtarget ATTRIBUTE_UNUSED
,
22325 enum machine_mode mode ATTRIBUTE_UNUSED
,
22326 int ignore ATTRIBUTE_UNUSED
)
22328 const struct builtin_description
* d
;
22329 enum insn_code icode
;
22330 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
22338 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
22340 enum machine_mode tmode
;
22341 enum machine_mode mode0
;
22342 enum machine_mode mode1
;
22343 enum machine_mode mode2
;
22349 if (fcode
>= ARM_BUILTIN_NEON_BASE
)
22350 return arm_expand_neon_builtin (fcode
, exp
, target
);
22354 case ARM_BUILTIN_TEXTRMSB
:
22355 case ARM_BUILTIN_TEXTRMUB
:
22356 case ARM_BUILTIN_TEXTRMSH
:
22357 case ARM_BUILTIN_TEXTRMUH
:
22358 case ARM_BUILTIN_TEXTRMSW
:
22359 case ARM_BUILTIN_TEXTRMUW
:
22360 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
22361 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
22362 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
22363 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
22364 : CODE_FOR_iwmmxt_textrmw
);
22366 arg0
= CALL_EXPR_ARG (exp
, 0);
22367 arg1
= CALL_EXPR_ARG (exp
, 1);
22368 op0
= expand_normal (arg0
);
22369 op1
= expand_normal (arg1
);
22370 tmode
= insn_data
[icode
].operand
[0].mode
;
22371 mode0
= insn_data
[icode
].operand
[1].mode
;
22372 mode1
= insn_data
[icode
].operand
[2].mode
;
22374 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
22375 op0
= copy_to_mode_reg (mode0
, op0
);
22376 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
22378 /* @@@ better error message */
22379 error ("selector must be an immediate");
22380 return gen_reg_rtx (tmode
);
22383 opint
= INTVAL (op1
);
22384 if (fcode
== ARM_BUILTIN_TEXTRMSB
|| fcode
== ARM_BUILTIN_TEXTRMUB
)
22386 if (opint
> 7 || opint
< 0)
22387 error ("the range of selector should be in 0 to 7");
22389 else if (fcode
== ARM_BUILTIN_TEXTRMSH
|| fcode
== ARM_BUILTIN_TEXTRMUH
)
22391 if (opint
> 3 || opint
< 0)
22392 error ("the range of selector should be in 0 to 3");
22394 else /* ARM_BUILTIN_TEXTRMSW || ARM_BUILTIN_TEXTRMUW. */
22396 if (opint
> 1 || opint
< 0)
22397 error ("the range of selector should be in 0 to 1");
22401 || GET_MODE (target
) != tmode
22402 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
22403 target
= gen_reg_rtx (tmode
);
22404 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
22410 case ARM_BUILTIN_WALIGNI
:
22411 /* If op2 is immediate, call walighi, else call walighr. */
22412 arg0
= CALL_EXPR_ARG (exp
, 0);
22413 arg1
= CALL_EXPR_ARG (exp
, 1);
22414 arg2
= CALL_EXPR_ARG (exp
, 2);
22415 op0
= expand_normal (arg0
);
22416 op1
= expand_normal (arg1
);
22417 op2
= expand_normal (arg2
);
22418 if (CONST_INT_P (op2
))
22420 icode
= CODE_FOR_iwmmxt_waligni
;
22421 tmode
= insn_data
[icode
].operand
[0].mode
;
22422 mode0
= insn_data
[icode
].operand
[1].mode
;
22423 mode1
= insn_data
[icode
].operand
[2].mode
;
22424 mode2
= insn_data
[icode
].operand
[3].mode
;
22425 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
22426 op0
= copy_to_mode_reg (mode0
, op0
);
22427 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
22428 op1
= copy_to_mode_reg (mode1
, op1
);
22429 gcc_assert ((*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
));
22430 selector
= INTVAL (op2
);
22431 if (selector
> 7 || selector
< 0)
22432 error ("the range of selector should be in 0 to 7");
22436 icode
= CODE_FOR_iwmmxt_walignr
;
22437 tmode
= insn_data
[icode
].operand
[0].mode
;
22438 mode0
= insn_data
[icode
].operand
[1].mode
;
22439 mode1
= insn_data
[icode
].operand
[2].mode
;
22440 mode2
= insn_data
[icode
].operand
[3].mode
;
22441 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
22442 op0
= copy_to_mode_reg (mode0
, op0
);
22443 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
22444 op1
= copy_to_mode_reg (mode1
, op1
);
22445 if (!(*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
22446 op2
= copy_to_mode_reg (mode2
, op2
);
22449 || GET_MODE (target
) != tmode
22450 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
22451 target
= gen_reg_rtx (tmode
);
22452 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
22458 case ARM_BUILTIN_TINSRB
:
22459 case ARM_BUILTIN_TINSRH
:
22460 case ARM_BUILTIN_TINSRW
:
22461 case ARM_BUILTIN_WMERGE
:
22462 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
22463 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
22464 : fcode
== ARM_BUILTIN_WMERGE
? CODE_FOR_iwmmxt_wmerge
22465 : CODE_FOR_iwmmxt_tinsrw
);
22466 arg0
= CALL_EXPR_ARG (exp
, 0);
22467 arg1
= CALL_EXPR_ARG (exp
, 1);
22468 arg2
= CALL_EXPR_ARG (exp
, 2);
22469 op0
= expand_normal (arg0
);
22470 op1
= expand_normal (arg1
);
22471 op2
= expand_normal (arg2
);
22472 tmode
= insn_data
[icode
].operand
[0].mode
;
22473 mode0
= insn_data
[icode
].operand
[1].mode
;
22474 mode1
= insn_data
[icode
].operand
[2].mode
;
22475 mode2
= insn_data
[icode
].operand
[3].mode
;
22477 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
22478 op0
= copy_to_mode_reg (mode0
, op0
);
22479 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
22480 op1
= copy_to_mode_reg (mode1
, op1
);
22481 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
22483 error ("selector must be an immediate");
22486 if (icode
== CODE_FOR_iwmmxt_wmerge
)
22488 selector
= INTVAL (op2
);
22489 if (selector
> 7 || selector
< 0)
22490 error ("the range of selector should be in 0 to 7");
22492 if ((icode
== CODE_FOR_iwmmxt_tinsrb
)
22493 || (icode
== CODE_FOR_iwmmxt_tinsrh
)
22494 || (icode
== CODE_FOR_iwmmxt_tinsrw
))
22497 selector
= INTVAL (op2
);
22498 if (icode
== CODE_FOR_iwmmxt_tinsrb
&& (selector
< 0 || selector
> 7))
22499 error ("the range of selector should be in 0 to 7");
22500 else if (icode
== CODE_FOR_iwmmxt_tinsrh
&& (selector
< 0 ||selector
> 3))
22501 error ("the range of selector should be in 0 to 3");
22502 else if (icode
== CODE_FOR_iwmmxt_tinsrw
&& (selector
< 0 ||selector
> 1))
22503 error ("the range of selector should be in 0 to 1");
22505 op2
= GEN_INT (mask
);
22508 || GET_MODE (target
) != tmode
22509 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
22510 target
= gen_reg_rtx (tmode
);
22511 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
22517 case ARM_BUILTIN_SETWCGR0
:
22518 case ARM_BUILTIN_SETWCGR1
:
22519 case ARM_BUILTIN_SETWCGR2
:
22520 case ARM_BUILTIN_SETWCGR3
:
22521 icode
= (fcode
== ARM_BUILTIN_SETWCGR0
? CODE_FOR_iwmmxt_setwcgr0
22522 : fcode
== ARM_BUILTIN_SETWCGR1
? CODE_FOR_iwmmxt_setwcgr1
22523 : fcode
== ARM_BUILTIN_SETWCGR2
? CODE_FOR_iwmmxt_setwcgr2
22524 : CODE_FOR_iwmmxt_setwcgr3
);
22525 arg0
= CALL_EXPR_ARG (exp
, 0);
22526 op0
= expand_normal (arg0
);
22527 mode0
= insn_data
[icode
].operand
[0].mode
;
22528 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
22529 op0
= copy_to_mode_reg (mode0
, op0
);
22530 pat
= GEN_FCN (icode
) (op0
);
22536 case ARM_BUILTIN_GETWCGR0
:
22537 case ARM_BUILTIN_GETWCGR1
:
22538 case ARM_BUILTIN_GETWCGR2
:
22539 case ARM_BUILTIN_GETWCGR3
:
22540 icode
= (fcode
== ARM_BUILTIN_GETWCGR0
? CODE_FOR_iwmmxt_getwcgr0
22541 : fcode
== ARM_BUILTIN_GETWCGR1
? CODE_FOR_iwmmxt_getwcgr1
22542 : fcode
== ARM_BUILTIN_GETWCGR2
? CODE_FOR_iwmmxt_getwcgr2
22543 : CODE_FOR_iwmmxt_getwcgr3
);
22544 tmode
= insn_data
[icode
].operand
[0].mode
;
22546 || GET_MODE (target
) != tmode
22547 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
22548 target
= gen_reg_rtx (tmode
);
22549 pat
= GEN_FCN (icode
) (target
);
22555 case ARM_BUILTIN_WSHUFH
:
22556 icode
= CODE_FOR_iwmmxt_wshufh
;
22557 arg0
= CALL_EXPR_ARG (exp
, 0);
22558 arg1
= CALL_EXPR_ARG (exp
, 1);
22559 op0
= expand_normal (arg0
);
22560 op1
= expand_normal (arg1
);
22561 tmode
= insn_data
[icode
].operand
[0].mode
;
22562 mode1
= insn_data
[icode
].operand
[1].mode
;
22563 mode2
= insn_data
[icode
].operand
[2].mode
;
22565 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
22566 op0
= copy_to_mode_reg (mode1
, op0
);
22567 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
22569 error ("mask must be an immediate");
22572 selector
= INTVAL (op1
);
22573 if (selector
< 0 || selector
> 255)
22574 error ("the range of mask should be in 0 to 255");
22576 || GET_MODE (target
) != tmode
22577 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
22578 target
= gen_reg_rtx (tmode
);
22579 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
22585 case ARM_BUILTIN_WMADDS
:
22586 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmadds
, exp
, target
);
22587 case ARM_BUILTIN_WMADDSX
:
22588 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsx
, exp
, target
);
22589 case ARM_BUILTIN_WMADDSN
:
22590 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsn
, exp
, target
);
22591 case ARM_BUILTIN_WMADDU
:
22592 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddu
, exp
, target
);
22593 case ARM_BUILTIN_WMADDUX
:
22594 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddux
, exp
, target
);
22595 case ARM_BUILTIN_WMADDUN
:
22596 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddun
, exp
, target
);
22597 case ARM_BUILTIN_WSADBZ
:
22598 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, exp
, target
);
22599 case ARM_BUILTIN_WSADHZ
:
22600 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, exp
, target
);
22602 /* Several three-argument builtins. */
22603 case ARM_BUILTIN_WMACS
:
22604 case ARM_BUILTIN_WMACU
:
22605 case ARM_BUILTIN_TMIA
:
22606 case ARM_BUILTIN_TMIAPH
:
22607 case ARM_BUILTIN_TMIATT
:
22608 case ARM_BUILTIN_TMIATB
:
22609 case ARM_BUILTIN_TMIABT
:
22610 case ARM_BUILTIN_TMIABB
:
22611 case ARM_BUILTIN_WQMIABB
:
22612 case ARM_BUILTIN_WQMIABT
:
22613 case ARM_BUILTIN_WQMIATB
:
22614 case ARM_BUILTIN_WQMIATT
:
22615 case ARM_BUILTIN_WQMIABBN
:
22616 case ARM_BUILTIN_WQMIABTN
:
22617 case ARM_BUILTIN_WQMIATBN
:
22618 case ARM_BUILTIN_WQMIATTN
:
22619 case ARM_BUILTIN_WMIABB
:
22620 case ARM_BUILTIN_WMIABT
:
22621 case ARM_BUILTIN_WMIATB
:
22622 case ARM_BUILTIN_WMIATT
:
22623 case ARM_BUILTIN_WMIABBN
:
22624 case ARM_BUILTIN_WMIABTN
:
22625 case ARM_BUILTIN_WMIATBN
:
22626 case ARM_BUILTIN_WMIATTN
:
22627 case ARM_BUILTIN_WMIAWBB
:
22628 case ARM_BUILTIN_WMIAWBT
:
22629 case ARM_BUILTIN_WMIAWTB
:
22630 case ARM_BUILTIN_WMIAWTT
:
22631 case ARM_BUILTIN_WMIAWBBN
:
22632 case ARM_BUILTIN_WMIAWBTN
:
22633 case ARM_BUILTIN_WMIAWTBN
:
22634 case ARM_BUILTIN_WMIAWTTN
:
22635 case ARM_BUILTIN_WSADB
:
22636 case ARM_BUILTIN_WSADH
:
22637 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
22638 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
22639 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
22640 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
22641 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
22642 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
22643 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
22644 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
22645 : fcode
== ARM_BUILTIN_WQMIABB
? CODE_FOR_iwmmxt_wqmiabb
22646 : fcode
== ARM_BUILTIN_WQMIABT
? CODE_FOR_iwmmxt_wqmiabt
22647 : fcode
== ARM_BUILTIN_WQMIATB
? CODE_FOR_iwmmxt_wqmiatb
22648 : fcode
== ARM_BUILTIN_WQMIATT
? CODE_FOR_iwmmxt_wqmiatt
22649 : fcode
== ARM_BUILTIN_WQMIABBN
? CODE_FOR_iwmmxt_wqmiabbn
22650 : fcode
== ARM_BUILTIN_WQMIABTN
? CODE_FOR_iwmmxt_wqmiabtn
22651 : fcode
== ARM_BUILTIN_WQMIATBN
? CODE_FOR_iwmmxt_wqmiatbn
22652 : fcode
== ARM_BUILTIN_WQMIATTN
? CODE_FOR_iwmmxt_wqmiattn
22653 : fcode
== ARM_BUILTIN_WMIABB
? CODE_FOR_iwmmxt_wmiabb
22654 : fcode
== ARM_BUILTIN_WMIABT
? CODE_FOR_iwmmxt_wmiabt
22655 : fcode
== ARM_BUILTIN_WMIATB
? CODE_FOR_iwmmxt_wmiatb
22656 : fcode
== ARM_BUILTIN_WMIATT
? CODE_FOR_iwmmxt_wmiatt
22657 : fcode
== ARM_BUILTIN_WMIABBN
? CODE_FOR_iwmmxt_wmiabbn
22658 : fcode
== ARM_BUILTIN_WMIABTN
? CODE_FOR_iwmmxt_wmiabtn
22659 : fcode
== ARM_BUILTIN_WMIATBN
? CODE_FOR_iwmmxt_wmiatbn
22660 : fcode
== ARM_BUILTIN_WMIATTN
? CODE_FOR_iwmmxt_wmiattn
22661 : fcode
== ARM_BUILTIN_WMIAWBB
? CODE_FOR_iwmmxt_wmiawbb
22662 : fcode
== ARM_BUILTIN_WMIAWBT
? CODE_FOR_iwmmxt_wmiawbt
22663 : fcode
== ARM_BUILTIN_WMIAWTB
? CODE_FOR_iwmmxt_wmiawtb
22664 : fcode
== ARM_BUILTIN_WMIAWTT
? CODE_FOR_iwmmxt_wmiawtt
22665 : fcode
== ARM_BUILTIN_WMIAWBBN
? CODE_FOR_iwmmxt_wmiawbbn
22666 : fcode
== ARM_BUILTIN_WMIAWBTN
? CODE_FOR_iwmmxt_wmiawbtn
22667 : fcode
== ARM_BUILTIN_WMIAWTBN
? CODE_FOR_iwmmxt_wmiawtbn
22668 : fcode
== ARM_BUILTIN_WMIAWTTN
? CODE_FOR_iwmmxt_wmiawttn
22669 : fcode
== ARM_BUILTIN_WSADB
? CODE_FOR_iwmmxt_wsadb
22670 : CODE_FOR_iwmmxt_wsadh
);
22671 arg0
= CALL_EXPR_ARG (exp
, 0);
22672 arg1
= CALL_EXPR_ARG (exp
, 1);
22673 arg2
= CALL_EXPR_ARG (exp
, 2);
22674 op0
= expand_normal (arg0
);
22675 op1
= expand_normal (arg1
);
22676 op2
= expand_normal (arg2
);
22677 tmode
= insn_data
[icode
].operand
[0].mode
;
22678 mode0
= insn_data
[icode
].operand
[1].mode
;
22679 mode1
= insn_data
[icode
].operand
[2].mode
;
22680 mode2
= insn_data
[icode
].operand
[3].mode
;
22682 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
22683 op0
= copy_to_mode_reg (mode0
, op0
);
22684 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
22685 op1
= copy_to_mode_reg (mode1
, op1
);
22686 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
22687 op2
= copy_to_mode_reg (mode2
, op2
);
22689 || GET_MODE (target
) != tmode
22690 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
22691 target
= gen_reg_rtx (tmode
);
22692 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
22698 case ARM_BUILTIN_WZERO
:
22699 target
= gen_reg_rtx (DImode
);
22700 emit_insn (gen_iwmmxt_clrdi (target
));
22703 case ARM_BUILTIN_WSRLHI
:
22704 case ARM_BUILTIN_WSRLWI
:
22705 case ARM_BUILTIN_WSRLDI
:
22706 case ARM_BUILTIN_WSLLHI
:
22707 case ARM_BUILTIN_WSLLWI
:
22708 case ARM_BUILTIN_WSLLDI
:
22709 case ARM_BUILTIN_WSRAHI
:
22710 case ARM_BUILTIN_WSRAWI
:
22711 case ARM_BUILTIN_WSRADI
:
22712 case ARM_BUILTIN_WRORHI
:
22713 case ARM_BUILTIN_WRORWI
:
22714 case ARM_BUILTIN_WRORDI
:
22715 case ARM_BUILTIN_WSRLH
:
22716 case ARM_BUILTIN_WSRLW
:
22717 case ARM_BUILTIN_WSRLD
:
22718 case ARM_BUILTIN_WSLLH
:
22719 case ARM_BUILTIN_WSLLW
:
22720 case ARM_BUILTIN_WSLLD
:
22721 case ARM_BUILTIN_WSRAH
:
22722 case ARM_BUILTIN_WSRAW
:
22723 case ARM_BUILTIN_WSRAD
:
22724 case ARM_BUILTIN_WRORH
:
22725 case ARM_BUILTIN_WRORW
:
22726 case ARM_BUILTIN_WRORD
:
22727 icode
= (fcode
== ARM_BUILTIN_WSRLHI
? CODE_FOR_lshrv4hi3_iwmmxt
22728 : fcode
== ARM_BUILTIN_WSRLWI
? CODE_FOR_lshrv2si3_iwmmxt
22729 : fcode
== ARM_BUILTIN_WSRLDI
? CODE_FOR_lshrdi3_iwmmxt
22730 : fcode
== ARM_BUILTIN_WSLLHI
? CODE_FOR_ashlv4hi3_iwmmxt
22731 : fcode
== ARM_BUILTIN_WSLLWI
? CODE_FOR_ashlv2si3_iwmmxt
22732 : fcode
== ARM_BUILTIN_WSLLDI
? CODE_FOR_ashldi3_iwmmxt
22733 : fcode
== ARM_BUILTIN_WSRAHI
? CODE_FOR_ashrv4hi3_iwmmxt
22734 : fcode
== ARM_BUILTIN_WSRAWI
? CODE_FOR_ashrv2si3_iwmmxt
22735 : fcode
== ARM_BUILTIN_WSRADI
? CODE_FOR_ashrdi3_iwmmxt
22736 : fcode
== ARM_BUILTIN_WRORHI
? CODE_FOR_rorv4hi3
22737 : fcode
== ARM_BUILTIN_WRORWI
? CODE_FOR_rorv2si3
22738 : fcode
== ARM_BUILTIN_WRORDI
? CODE_FOR_rordi3
22739 : fcode
== ARM_BUILTIN_WSRLH
? CODE_FOR_lshrv4hi3_di
22740 : fcode
== ARM_BUILTIN_WSRLW
? CODE_FOR_lshrv2si3_di
22741 : fcode
== ARM_BUILTIN_WSRLD
? CODE_FOR_lshrdi3_di
22742 : fcode
== ARM_BUILTIN_WSLLH
? CODE_FOR_ashlv4hi3_di
22743 : fcode
== ARM_BUILTIN_WSLLW
? CODE_FOR_ashlv2si3_di
22744 : fcode
== ARM_BUILTIN_WSLLD
? CODE_FOR_ashldi3_di
22745 : fcode
== ARM_BUILTIN_WSRAH
? CODE_FOR_ashrv4hi3_di
22746 : fcode
== ARM_BUILTIN_WSRAW
? CODE_FOR_ashrv2si3_di
22747 : fcode
== ARM_BUILTIN_WSRAD
? CODE_FOR_ashrdi3_di
22748 : fcode
== ARM_BUILTIN_WRORH
? CODE_FOR_rorv4hi3_di
22749 : fcode
== ARM_BUILTIN_WRORW
? CODE_FOR_rorv2si3_di
22750 : fcode
== ARM_BUILTIN_WRORD
? CODE_FOR_rordi3_di
22751 : CODE_FOR_nothing
);
22752 arg1
= CALL_EXPR_ARG (exp
, 1);
22753 op1
= expand_normal (arg1
);
22754 if (GET_MODE (op1
) == VOIDmode
)
22756 imm
= INTVAL (op1
);
22757 if ((fcode
== ARM_BUILTIN_WRORHI
|| fcode
== ARM_BUILTIN_WRORWI
22758 || fcode
== ARM_BUILTIN_WRORH
|| fcode
== ARM_BUILTIN_WRORW
)
22759 && (imm
< 0 || imm
> 32))
22761 if (fcode
== ARM_BUILTIN_WRORHI
)
22762 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi16 in code.");
22763 else if (fcode
== ARM_BUILTIN_WRORWI
)
22764 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi32 in code.");
22765 else if (fcode
== ARM_BUILTIN_WRORH
)
22766 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi16 in code.");
22768 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi32 in code.");
22770 else if ((fcode
== ARM_BUILTIN_WRORDI
|| fcode
== ARM_BUILTIN_WRORD
)
22771 && (imm
< 0 || imm
> 64))
22773 if (fcode
== ARM_BUILTIN_WRORDI
)
22774 error ("the range of count should be in 0 to 64. please check the intrinsic _mm_rori_si64 in code.");
22776 error ("the range of count should be in 0 to 64. please check the intrinsic _mm_ror_si64 in code.");
22780 if (fcode
== ARM_BUILTIN_WSRLHI
)
22781 error ("the count should be no less than 0. please check the intrinsic _mm_srli_pi16 in code.");
22782 else if (fcode
== ARM_BUILTIN_WSRLWI
)
22783 error ("the count should be no less than 0. please check the intrinsic _mm_srli_pi32 in code.");
22784 else if (fcode
== ARM_BUILTIN_WSRLDI
)
22785 error ("the count should be no less than 0. please check the intrinsic _mm_srli_si64 in code.");
22786 else if (fcode
== ARM_BUILTIN_WSLLHI
)
22787 error ("the count should be no less than 0. please check the intrinsic _mm_slli_pi16 in code.");
22788 else if (fcode
== ARM_BUILTIN_WSLLWI
)
22789 error ("the count should be no less than 0. please check the intrinsic _mm_slli_pi32 in code.");
22790 else if (fcode
== ARM_BUILTIN_WSLLDI
)
22791 error ("the count should be no less than 0. please check the intrinsic _mm_slli_si64 in code.");
22792 else if (fcode
== ARM_BUILTIN_WSRAHI
)
22793 error ("the count should be no less than 0. please check the intrinsic _mm_srai_pi16 in code.");
22794 else if (fcode
== ARM_BUILTIN_WSRAWI
)
22795 error ("the count should be no less than 0. please check the intrinsic _mm_srai_pi32 in code.");
22796 else if (fcode
== ARM_BUILTIN_WSRADI
)
22797 error ("the count should be no less than 0. please check the intrinsic _mm_srai_si64 in code.");
22798 else if (fcode
== ARM_BUILTIN_WSRLH
)
22799 error ("the count should be no less than 0. please check the intrinsic _mm_srl_pi16 in code.");
22800 else if (fcode
== ARM_BUILTIN_WSRLW
)
22801 error ("the count should be no less than 0. please check the intrinsic _mm_srl_pi32 in code.");
22802 else if (fcode
== ARM_BUILTIN_WSRLD
)
22803 error ("the count should be no less than 0. please check the intrinsic _mm_srl_si64 in code.");
22804 else if (fcode
== ARM_BUILTIN_WSLLH
)
22805 error ("the count should be no less than 0. please check the intrinsic _mm_sll_pi16 in code.");
22806 else if (fcode
== ARM_BUILTIN_WSLLW
)
22807 error ("the count should be no less than 0. please check the intrinsic _mm_sll_pi32 in code.");
22808 else if (fcode
== ARM_BUILTIN_WSLLD
)
22809 error ("the count should be no less than 0. please check the intrinsic _mm_sll_si64 in code.");
22810 else if (fcode
== ARM_BUILTIN_WSRAH
)
22811 error ("the count should be no less than 0. please check the intrinsic _mm_sra_pi16 in code.");
22812 else if (fcode
== ARM_BUILTIN_WSRAW
)
22813 error ("the count should be no less than 0. please check the intrinsic _mm_sra_pi32 in code.");
22815 error ("the count should be no less than 0. please check the intrinsic _mm_sra_si64 in code.");
22818 return arm_expand_binop_builtin (icode
, exp
, target
);
22824 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
22825 if (d
->code
== (const enum arm_builtins
) fcode
)
22826 return arm_expand_binop_builtin (d
->icode
, exp
, target
);
22828 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
22829 if (d
->code
== (const enum arm_builtins
) fcode
)
22830 return arm_expand_unop_builtin (d
->icode
, exp
, target
, 0);
22832 /* @@@ Should really do something sensible here. */
22836 /* Return the number (counting from 0) of
22837 the least significant set bit in MASK. */
22840 number_of_first_bit_set (unsigned mask
)
22842 return ctz_hwi (mask
);
22845 /* Like emit_multi_reg_push, but allowing for a different set of
22846 registers to be described as saved. MASK is the set of registers
22847 to be saved; REAL_REGS is the set of registers to be described as
22848 saved. If REAL_REGS is 0, only describe the stack adjustment. */
22851 thumb1_emit_multi_reg_push (unsigned long mask
, unsigned long real_regs
)
22853 unsigned long regno
;
22854 rtx par
[10], tmp
, reg
, insn
;
22857 /* Build the parallel of the registers actually being stored. */
22858 for (i
= 0; mask
; ++i
, mask
&= mask
- 1)
22860 regno
= ctz_hwi (mask
);
22861 reg
= gen_rtx_REG (SImode
, regno
);
22864 tmp
= gen_rtx_UNSPEC (BLKmode
, gen_rtvec (1, reg
), UNSPEC_PUSH_MULT
);
22866 tmp
= gen_rtx_USE (VOIDmode
, reg
);
22871 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, -4 * i
);
22872 tmp
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, tmp
);
22873 tmp
= gen_frame_mem (BLKmode
, tmp
);
22874 tmp
= gen_rtx_SET (VOIDmode
, tmp
, par
[0]);
22877 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (i
, par
));
22878 insn
= emit_insn (tmp
);
22880 /* Always build the stack adjustment note for unwind info. */
22881 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, -4 * i
);
22882 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, tmp
);
22885 /* Build the parallel of the registers recorded as saved for unwind. */
22886 for (j
= 0; real_regs
; ++j
, real_regs
&= real_regs
- 1)
22888 regno
= ctz_hwi (real_regs
);
22889 reg
= gen_rtx_REG (SImode
, regno
);
22891 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, j
* 4);
22892 tmp
= gen_frame_mem (SImode
, tmp
);
22893 tmp
= gen_rtx_SET (VOIDmode
, tmp
, reg
);
22894 RTX_FRAME_RELATED_P (tmp
) = 1;
22902 RTX_FRAME_RELATED_P (par
[0]) = 1;
22903 tmp
= gen_rtx_SEQUENCE (VOIDmode
, gen_rtvec_v (j
+ 1, par
));
22906 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, tmp
);
22911 /* Emit code to push or pop registers to or from the stack. F is the
22912 assembly file. MASK is the registers to pop. */
22914 thumb_pop (FILE *f
, unsigned long mask
)
22917 int lo_mask
= mask
& 0xFF;
22918 int pushed_words
= 0;
22922 if (lo_mask
== 0 && (mask
& (1 << PC_REGNUM
)))
22924 /* Special case. Do not generate a POP PC statement here, do it in
22926 thumb_exit (f
, -1);
22930 fprintf (f
, "\tpop\t{");
22932 /* Look at the low registers first. */
22933 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
22937 asm_fprintf (f
, "%r", regno
);
22939 if ((lo_mask
& ~1) != 0)
22946 if (mask
& (1 << PC_REGNUM
))
22948 /* Catch popping the PC. */
22949 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
22950 || crtl
->calls_eh_return
)
22952 /* The PC is never poped directly, instead
22953 it is popped into r3 and then BX is used. */
22954 fprintf (f
, "}\n");
22956 thumb_exit (f
, -1);
22965 asm_fprintf (f
, "%r", PC_REGNUM
);
22969 fprintf (f
, "}\n");
22972 /* Generate code to return from a thumb function.
22973 If 'reg_containing_return_addr' is -1, then the return address is
22974 actually on the stack, at the stack pointer. */
22976 thumb_exit (FILE *f
, int reg_containing_return_addr
)
22978 unsigned regs_available_for_popping
;
22979 unsigned regs_to_pop
;
22981 unsigned available
;
22985 int restore_a4
= FALSE
;
22987 /* Compute the registers we need to pop. */
22991 if (reg_containing_return_addr
== -1)
22993 regs_to_pop
|= 1 << LR_REGNUM
;
22997 if (TARGET_BACKTRACE
)
22999 /* Restore the (ARM) frame pointer and stack pointer. */
23000 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
23004 /* If there is nothing to pop then just emit the BX instruction and
23006 if (pops_needed
== 0)
23008 if (crtl
->calls_eh_return
)
23009 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
23011 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
23014 /* Otherwise if we are not supporting interworking and we have not created
23015 a backtrace structure and the function was not entered in ARM mode then
23016 just pop the return address straight into the PC. */
23017 else if (!TARGET_INTERWORK
23018 && !TARGET_BACKTRACE
23019 && !is_called_in_ARM_mode (current_function_decl
)
23020 && !crtl
->calls_eh_return
)
23022 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
23026 /* Find out how many of the (return) argument registers we can corrupt. */
23027 regs_available_for_popping
= 0;
23029 /* If returning via __builtin_eh_return, the bottom three registers
23030 all contain information needed for the return. */
23031 if (crtl
->calls_eh_return
)
23035 /* If we can deduce the registers used from the function's
23036 return value. This is more reliable that examining
23037 df_regs_ever_live_p () because that will be set if the register is
23038 ever used in the function, not just if the register is used
23039 to hold a return value. */
23041 if (crtl
->return_rtx
!= 0)
23042 mode
= GET_MODE (crtl
->return_rtx
);
23044 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
23046 size
= GET_MODE_SIZE (mode
);
23050 /* In a void function we can use any argument register.
23051 In a function that returns a structure on the stack
23052 we can use the second and third argument registers. */
23053 if (mode
== VOIDmode
)
23054 regs_available_for_popping
=
23055 (1 << ARG_REGISTER (1))
23056 | (1 << ARG_REGISTER (2))
23057 | (1 << ARG_REGISTER (3));
23059 regs_available_for_popping
=
23060 (1 << ARG_REGISTER (2))
23061 | (1 << ARG_REGISTER (3));
23063 else if (size
<= 4)
23064 regs_available_for_popping
=
23065 (1 << ARG_REGISTER (2))
23066 | (1 << ARG_REGISTER (3));
23067 else if (size
<= 8)
23068 regs_available_for_popping
=
23069 (1 << ARG_REGISTER (3));
23072 /* Match registers to be popped with registers into which we pop them. */
23073 for (available
= regs_available_for_popping
,
23074 required
= regs_to_pop
;
23075 required
!= 0 && available
!= 0;
23076 available
&= ~(available
& - available
),
23077 required
&= ~(required
& - required
))
23080 /* If we have any popping registers left over, remove them. */
23082 regs_available_for_popping
&= ~available
;
23084 /* Otherwise if we need another popping register we can use
23085 the fourth argument register. */
23086 else if (pops_needed
)
23088 /* If we have not found any free argument registers and
23089 reg a4 contains the return address, we must move it. */
23090 if (regs_available_for_popping
== 0
23091 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
23093 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
23094 reg_containing_return_addr
= LR_REGNUM
;
23096 else if (size
> 12)
23098 /* Register a4 is being used to hold part of the return value,
23099 but we have dire need of a free, low register. */
23102 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
23105 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
23107 /* The fourth argument register is available. */
23108 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
23114 /* Pop as many registers as we can. */
23115 thumb_pop (f
, regs_available_for_popping
);
23117 /* Process the registers we popped. */
23118 if (reg_containing_return_addr
== -1)
23120 /* The return address was popped into the lowest numbered register. */
23121 regs_to_pop
&= ~(1 << LR_REGNUM
);
23123 reg_containing_return_addr
=
23124 number_of_first_bit_set (regs_available_for_popping
);
23126 /* Remove this register for the mask of available registers, so that
23127 the return address will not be corrupted by further pops. */
23128 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
23131 /* If we popped other registers then handle them here. */
23132 if (regs_available_for_popping
)
23136 /* Work out which register currently contains the frame pointer. */
23137 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
23139 /* Move it into the correct place. */
23140 asm_fprintf (f
, "\tmov\t%r, %r\n",
23141 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
23143 /* (Temporarily) remove it from the mask of popped registers. */
23144 regs_available_for_popping
&= ~(1 << frame_pointer
);
23145 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
23147 if (regs_available_for_popping
)
23151 /* We popped the stack pointer as well,
23152 find the register that contains it. */
23153 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
23155 /* Move it into the stack register. */
23156 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
23158 /* At this point we have popped all necessary registers, so
23159 do not worry about restoring regs_available_for_popping
23160 to its correct value:
23162 assert (pops_needed == 0)
23163 assert (regs_available_for_popping == (1 << frame_pointer))
23164 assert (regs_to_pop == (1 << STACK_POINTER)) */
23168 /* Since we have just move the popped value into the frame
23169 pointer, the popping register is available for reuse, and
23170 we know that we still have the stack pointer left to pop. */
23171 regs_available_for_popping
|= (1 << frame_pointer
);
23175 /* If we still have registers left on the stack, but we no longer have
23176 any registers into which we can pop them, then we must move the return
23177 address into the link register and make available the register that
23179 if (regs_available_for_popping
== 0 && pops_needed
> 0)
23181 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
23183 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
23184 reg_containing_return_addr
);
23186 reg_containing_return_addr
= LR_REGNUM
;
23189 /* If we have registers left on the stack then pop some more.
23190 We know that at most we will want to pop FP and SP. */
23191 if (pops_needed
> 0)
23196 thumb_pop (f
, regs_available_for_popping
);
23198 /* We have popped either FP or SP.
23199 Move whichever one it is into the correct register. */
23200 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
23201 move_to
= number_of_first_bit_set (regs_to_pop
);
23203 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
23205 regs_to_pop
&= ~(1 << move_to
);
23210 /* If we still have not popped everything then we must have only
23211 had one register available to us and we are now popping the SP. */
23212 if (pops_needed
> 0)
23216 thumb_pop (f
, regs_available_for_popping
);
23218 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
23220 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
23222 assert (regs_to_pop == (1 << STACK_POINTER))
23223 assert (pops_needed == 1)
23227 /* If necessary restore the a4 register. */
23230 if (reg_containing_return_addr
!= LR_REGNUM
)
23232 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
23233 reg_containing_return_addr
= LR_REGNUM
;
23236 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
23239 if (crtl
->calls_eh_return
)
23240 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
23242 /* Return to caller. */
23243 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
23246 /* Scan INSN just before assembler is output for it.
23247 For Thumb-1, we track the status of the condition codes; this
23248 information is used in the cbranchsi4_insn pattern. */
23250 thumb1_final_prescan_insn (rtx insn
)
23252 if (flag_print_asm_name
)
23253 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
23254 INSN_ADDRESSES (INSN_UID (insn
)));
23255 /* Don't overwrite the previous setter when we get to a cbranch. */
23256 if (INSN_CODE (insn
) != CODE_FOR_cbranchsi4_insn
)
23258 enum attr_conds conds
;
23260 if (cfun
->machine
->thumb1_cc_insn
)
23262 if (modified_in_p (cfun
->machine
->thumb1_cc_op0
, insn
)
23263 || modified_in_p (cfun
->machine
->thumb1_cc_op1
, insn
))
23266 conds
= get_attr_conds (insn
);
23267 if (conds
== CONDS_SET
)
23269 rtx set
= single_set (insn
);
23270 cfun
->machine
->thumb1_cc_insn
= insn
;
23271 cfun
->machine
->thumb1_cc_op0
= SET_DEST (set
);
23272 cfun
->machine
->thumb1_cc_op1
= const0_rtx
;
23273 cfun
->machine
->thumb1_cc_mode
= CC_NOOVmode
;
23274 if (INSN_CODE (insn
) == CODE_FOR_thumb1_subsi3_insn
)
23276 rtx src1
= XEXP (SET_SRC (set
), 1);
23277 if (src1
== const0_rtx
)
23278 cfun
->machine
->thumb1_cc_mode
= CCmode
;
23280 else if (REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
23282 /* Record the src register operand instead of dest because
23283 cprop_hardreg pass propagates src. */
23284 cfun
->machine
->thumb1_cc_op0
= SET_SRC (set
);
23287 else if (conds
!= CONDS_NOCOND
)
23288 cfun
->machine
->thumb1_cc_insn
= NULL_RTX
;
23291 /* Check if unexpected far jump is used. */
23292 if (cfun
->machine
->lr_save_eliminated
23293 && get_attr_far_jump (insn
) == FAR_JUMP_YES
)
23294 internal_error("Unexpected thumb1 far jump");
23298 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
23300 unsigned HOST_WIDE_INT mask
= 0xff;
23303 val
= val
& (unsigned HOST_WIDE_INT
)0xffffffffu
;
23304 if (val
== 0) /* XXX */
23307 for (i
= 0; i
< 25; i
++)
23308 if ((val
& (mask
<< i
)) == val
)
23314 /* Returns nonzero if the current function contains,
23315 or might contain a far jump. */
23317 thumb_far_jump_used_p (void)
23320 bool far_jump
= false;
23321 unsigned int func_size
= 0;
23323 /* This test is only important for leaf functions. */
23324 /* assert (!leaf_function_p ()); */
23326 /* If we have already decided that far jumps may be used,
23327 do not bother checking again, and always return true even if
23328 it turns out that they are not being used. Once we have made
23329 the decision that far jumps are present (and that hence the link
23330 register will be pushed onto the stack) we cannot go back on it. */
23331 if (cfun
->machine
->far_jump_used
)
23334 /* If this function is not being called from the prologue/epilogue
23335 generation code then it must be being called from the
23336 INITIAL_ELIMINATION_OFFSET macro. */
23337 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
23339 /* In this case we know that we are being asked about the elimination
23340 of the arg pointer register. If that register is not being used,
23341 then there are no arguments on the stack, and we do not have to
23342 worry that a far jump might force the prologue to push the link
23343 register, changing the stack offsets. In this case we can just
23344 return false, since the presence of far jumps in the function will
23345 not affect stack offsets.
23347 If the arg pointer is live (or if it was live, but has now been
23348 eliminated and so set to dead) then we do have to test to see if
23349 the function might contain a far jump. This test can lead to some
23350 false negatives, since before reload is completed, then length of
23351 branch instructions is not known, so gcc defaults to returning their
23352 longest length, which in turn sets the far jump attribute to true.
23354 A false negative will not result in bad code being generated, but it
23355 will result in a needless push and pop of the link register. We
23356 hope that this does not occur too often.
23358 If we need doubleword stack alignment this could affect the other
23359 elimination offsets so we can't risk getting it wrong. */
23360 if (df_regs_ever_live_p (ARG_POINTER_REGNUM
))
23361 cfun
->machine
->arg_pointer_live
= 1;
23362 else if (!cfun
->machine
->arg_pointer_live
)
23366 /* Check to see if the function contains a branch
23367 insn with the far jump attribute set. */
23368 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
23370 if (JUMP_P (insn
) && get_attr_far_jump (insn
) == FAR_JUMP_YES
)
23374 func_size
+= get_attr_length (insn
);
23377 /* Attribute far_jump will always be true for thumb1 before
23378 shorten_branch pass. So checking far_jump attribute before
23379 shorten_branch isn't much useful.
23381 Following heuristic tries to estimate more accurately if a far jump
23382 may finally be used. The heuristic is very conservative as there is
23383 no chance to roll-back the decision of not to use far jump.
23385 Thumb1 long branch offset is -2048 to 2046. The worst case is each
23386 2-byte insn is associated with a 4 byte constant pool. Using
23387 function size 2048/3 as the threshold is conservative enough. */
23390 if ((func_size
* 3) >= 2048)
23392 /* Record the fact that we have decided that
23393 the function does use far jumps. */
23394 cfun
->machine
->far_jump_used
= 1;
23402 /* Return nonzero if FUNC must be entered in ARM mode. */
23404 is_called_in_ARM_mode (tree func
)
23406 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
23408 /* Ignore the problem about functions whose address is taken. */
23409 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
23413 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
23419 /* Given the stack offsets and register mask in OFFSETS, decide how
23420 many additional registers to push instead of subtracting a constant
23421 from SP. For epilogues the principle is the same except we use pop.
23422 FOR_PROLOGUE indicates which we're generating. */
23424 thumb1_extra_regs_pushed (arm_stack_offsets
*offsets
, bool for_prologue
)
23426 HOST_WIDE_INT amount
;
23427 unsigned long live_regs_mask
= offsets
->saved_regs_mask
;
23428 /* Extract a mask of the ones we can give to the Thumb's push/pop
23430 unsigned long l_mask
= live_regs_mask
& (for_prologue
? 0x40ff : 0xff);
23431 /* Then count how many other high registers will need to be pushed. */
23432 unsigned long high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
23433 int n_free
, reg_base
, size
;
23435 if (!for_prologue
&& frame_pointer_needed
)
23436 amount
= offsets
->locals_base
- offsets
->saved_regs
;
23438 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
23440 /* If the stack frame size is 512 exactly, we can save one load
23441 instruction, which should make this a win even when optimizing
23443 if (!optimize_size
&& amount
!= 512)
23446 /* Can't do this if there are high registers to push. */
23447 if (high_regs_pushed
!= 0)
23450 /* Shouldn't do it in the prologue if no registers would normally
23451 be pushed at all. In the epilogue, also allow it if we'll have
23452 a pop insn for the PC. */
23455 || TARGET_BACKTRACE
23456 || (live_regs_mask
& 1 << LR_REGNUM
) == 0
23457 || TARGET_INTERWORK
23458 || crtl
->args
.pretend_args_size
!= 0))
23461 /* Don't do this if thumb_expand_prologue wants to emit instructions
23462 between the push and the stack frame allocation. */
23464 && ((flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
23465 || (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)))
23472 size
= arm_size_return_regs ();
23473 reg_base
= ARM_NUM_INTS (size
);
23474 live_regs_mask
>>= reg_base
;
23477 while (reg_base
+ n_free
< 8 && !(live_regs_mask
& 1)
23478 && (for_prologue
|| call_used_regs
[reg_base
+ n_free
]))
23480 live_regs_mask
>>= 1;
23486 gcc_assert (amount
/ 4 * 4 == amount
);
23488 if (amount
>= 512 && (amount
- n_free
* 4) < 512)
23489 return (amount
- 508) / 4;
23490 if (amount
<= n_free
* 4)
23495 /* The bits which aren't usefully expanded as rtl. */
23497 thumb1_unexpanded_epilogue (void)
23499 arm_stack_offsets
*offsets
;
23501 unsigned long live_regs_mask
= 0;
23502 int high_regs_pushed
= 0;
23504 int had_to_push_lr
;
23507 if (cfun
->machine
->return_used_this_function
!= 0)
23510 if (IS_NAKED (arm_current_func_type ()))
23513 offsets
= arm_get_frame_offsets ();
23514 live_regs_mask
= offsets
->saved_regs_mask
;
23515 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
23517 /* If we can deduce the registers used from the function's return value.
23518 This is more reliable that examining df_regs_ever_live_p () because that
23519 will be set if the register is ever used in the function, not just if
23520 the register is used to hold a return value. */
23521 size
= arm_size_return_regs ();
23523 extra_pop
= thumb1_extra_regs_pushed (offsets
, false);
23526 unsigned long extra_mask
= (1 << extra_pop
) - 1;
23527 live_regs_mask
|= extra_mask
<< ARM_NUM_INTS (size
);
23530 /* The prolog may have pushed some high registers to use as
23531 work registers. e.g. the testsuite file:
23532 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
23533 compiles to produce:
23534 push {r4, r5, r6, r7, lr}
23538 as part of the prolog. We have to undo that pushing here. */
23540 if (high_regs_pushed
)
23542 unsigned long mask
= live_regs_mask
& 0xff;
23545 /* The available low registers depend on the size of the value we are
23553 /* Oh dear! We have no low registers into which we can pop
23556 ("no low registers available for popping high registers");
23558 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
23559 if (live_regs_mask
& (1 << next_hi_reg
))
23562 while (high_regs_pushed
)
23564 /* Find lo register(s) into which the high register(s) can
23566 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
23568 if (mask
& (1 << regno
))
23569 high_regs_pushed
--;
23570 if (high_regs_pushed
== 0)
23574 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
23576 /* Pop the values into the low register(s). */
23577 thumb_pop (asm_out_file
, mask
);
23579 /* Move the value(s) into the high registers. */
23580 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
23582 if (mask
& (1 << regno
))
23584 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
23587 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
23588 if (live_regs_mask
& (1 << next_hi_reg
))
23593 live_regs_mask
&= ~0x0f00;
23596 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
23597 live_regs_mask
&= 0xff;
23599 if (crtl
->args
.pretend_args_size
== 0 || TARGET_BACKTRACE
)
23601 /* Pop the return address into the PC. */
23602 if (had_to_push_lr
)
23603 live_regs_mask
|= 1 << PC_REGNUM
;
23605 /* Either no argument registers were pushed or a backtrace
23606 structure was created which includes an adjusted stack
23607 pointer, so just pop everything. */
23608 if (live_regs_mask
)
23609 thumb_pop (asm_out_file
, live_regs_mask
);
23611 /* We have either just popped the return address into the
23612 PC or it is was kept in LR for the entire function.
23613 Note that thumb_pop has already called thumb_exit if the
23614 PC was in the list. */
23615 if (!had_to_push_lr
)
23616 thumb_exit (asm_out_file
, LR_REGNUM
);
23620 /* Pop everything but the return address. */
23621 if (live_regs_mask
)
23622 thumb_pop (asm_out_file
, live_regs_mask
);
23624 if (had_to_push_lr
)
23628 /* We have no free low regs, so save one. */
23629 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
23633 /* Get the return address into a temporary register. */
23634 thumb_pop (asm_out_file
, 1 << LAST_ARG_REGNUM
);
23638 /* Move the return address to lr. */
23639 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
23641 /* Restore the low register. */
23642 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
23647 regno
= LAST_ARG_REGNUM
;
23652 /* Remove the argument registers that were pushed onto the stack. */
23653 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
23654 SP_REGNUM
, SP_REGNUM
,
23655 crtl
->args
.pretend_args_size
);
23657 thumb_exit (asm_out_file
, regno
);
23663 /* Functions to save and restore machine-specific function data. */
23664 static struct machine_function
*
23665 arm_init_machine_status (void)
23667 struct machine_function
*machine
;
23668 machine
= ggc_alloc_cleared_machine_function ();
23670 #if ARM_FT_UNKNOWN != 0
23671 machine
->func_type
= ARM_FT_UNKNOWN
;
23676 /* Return an RTX indicating where the return address to the
23677 calling function can be found. */
23679 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
23684 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
23687 /* Do anything needed before RTL is emitted for each function. */
23689 arm_init_expanders (void)
23691 /* Arrange to initialize and mark the machine per-function status. */
23692 init_machine_status
= arm_init_machine_status
;
23694 /* This is to stop the combine pass optimizing away the alignment
23695 adjustment of va_arg. */
23696 /* ??? It is claimed that this should not be necessary. */
23698 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
23702 /* Like arm_compute_initial_elimination offset. Simpler because there
23703 isn't an ABI specified frame pointer for Thumb. Instead, we set it
23704 to point at the base of the local variables after static stack
23705 space for a function has been allocated. */
23708 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
23710 arm_stack_offsets
*offsets
;
23712 offsets
= arm_get_frame_offsets ();
23716 case ARG_POINTER_REGNUM
:
23719 case STACK_POINTER_REGNUM
:
23720 return offsets
->outgoing_args
- offsets
->saved_args
;
23722 case FRAME_POINTER_REGNUM
:
23723 return offsets
->soft_frame
- offsets
->saved_args
;
23725 case ARM_HARD_FRAME_POINTER_REGNUM
:
23726 return offsets
->saved_regs
- offsets
->saved_args
;
23728 case THUMB_HARD_FRAME_POINTER_REGNUM
:
23729 return offsets
->locals_base
- offsets
->saved_args
;
23732 gcc_unreachable ();
23736 case FRAME_POINTER_REGNUM
:
23739 case STACK_POINTER_REGNUM
:
23740 return offsets
->outgoing_args
- offsets
->soft_frame
;
23742 case ARM_HARD_FRAME_POINTER_REGNUM
:
23743 return offsets
->saved_regs
- offsets
->soft_frame
;
23745 case THUMB_HARD_FRAME_POINTER_REGNUM
:
23746 return offsets
->locals_base
- offsets
->soft_frame
;
23749 gcc_unreachable ();
23754 gcc_unreachable ();
23758 /* Generate the function's prologue. */
23761 thumb1_expand_prologue (void)
23765 HOST_WIDE_INT amount
;
23766 arm_stack_offsets
*offsets
;
23767 unsigned long func_type
;
23769 unsigned long live_regs_mask
;
23770 unsigned long l_mask
;
23771 unsigned high_regs_pushed
= 0;
23773 func_type
= arm_current_func_type ();
23775 /* Naked functions don't have prologues. */
23776 if (IS_NAKED (func_type
))
23779 if (IS_INTERRUPT (func_type
))
23781 error ("interrupt Service Routines cannot be coded in Thumb mode");
23785 if (is_called_in_ARM_mode (current_function_decl
))
23786 emit_insn (gen_prologue_thumb1_interwork ());
23788 offsets
= arm_get_frame_offsets ();
23789 live_regs_mask
= offsets
->saved_regs_mask
;
23791 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
23792 l_mask
= live_regs_mask
& 0x40ff;
23793 /* Then count how many other high registers will need to be pushed. */
23794 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
23796 if (crtl
->args
.pretend_args_size
)
23798 rtx x
= GEN_INT (-crtl
->args
.pretend_args_size
);
23800 if (cfun
->machine
->uses_anonymous_args
)
23802 int num_pushes
= ARM_NUM_INTS (crtl
->args
.pretend_args_size
);
23803 unsigned long mask
;
23805 mask
= 1ul << (LAST_ARG_REGNUM
+ 1);
23806 mask
-= 1ul << (LAST_ARG_REGNUM
+ 1 - num_pushes
);
23808 insn
= thumb1_emit_multi_reg_push (mask
, 0);
23812 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
23813 stack_pointer_rtx
, x
));
23815 RTX_FRAME_RELATED_P (insn
) = 1;
23818 if (TARGET_BACKTRACE
)
23820 HOST_WIDE_INT offset
= 0;
23821 unsigned work_register
;
23822 rtx work_reg
, x
, arm_hfp_rtx
;
23824 /* We have been asked to create a stack backtrace structure.
23825 The code looks like this:
23829 0 sub SP, #16 Reserve space for 4 registers.
23830 2 push {R7} Push low registers.
23831 4 add R7, SP, #20 Get the stack pointer before the push.
23832 6 str R7, [SP, #8] Store the stack pointer
23833 (before reserving the space).
23834 8 mov R7, PC Get hold of the start of this code + 12.
23835 10 str R7, [SP, #16] Store it.
23836 12 mov R7, FP Get hold of the current frame pointer.
23837 14 str R7, [SP, #4] Store it.
23838 16 mov R7, LR Get hold of the current return address.
23839 18 str R7, [SP, #12] Store it.
23840 20 add R7, SP, #16 Point at the start of the
23841 backtrace structure.
23842 22 mov FP, R7 Put this value into the frame pointer. */
23844 work_register
= thumb_find_work_register (live_regs_mask
);
23845 work_reg
= gen_rtx_REG (SImode
, work_register
);
23846 arm_hfp_rtx
= gen_rtx_REG (SImode
, ARM_HARD_FRAME_POINTER_REGNUM
);
23848 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
23849 stack_pointer_rtx
, GEN_INT (-16)));
23850 RTX_FRAME_RELATED_P (insn
) = 1;
23854 insn
= thumb1_emit_multi_reg_push (l_mask
, l_mask
);
23855 RTX_FRAME_RELATED_P (insn
) = 1;
23857 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
23860 x
= GEN_INT (offset
+ 16 + crtl
->args
.pretend_args_size
);
23861 emit_insn (gen_addsi3 (work_reg
, stack_pointer_rtx
, x
));
23863 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 4);
23864 x
= gen_frame_mem (SImode
, x
);
23865 emit_move_insn (x
, work_reg
);
23867 /* Make sure that the instruction fetching the PC is in the right place
23868 to calculate "start of backtrace creation code + 12". */
23869 /* ??? The stores using the common WORK_REG ought to be enough to
23870 prevent the scheduler from doing anything weird. Failing that
23871 we could always move all of the following into an UNSPEC_VOLATILE. */
23874 x
= gen_rtx_REG (SImode
, PC_REGNUM
);
23875 emit_move_insn (work_reg
, x
);
23877 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 12);
23878 x
= gen_frame_mem (SImode
, x
);
23879 emit_move_insn (x
, work_reg
);
23881 emit_move_insn (work_reg
, arm_hfp_rtx
);
23883 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
23884 x
= gen_frame_mem (SImode
, x
);
23885 emit_move_insn (x
, work_reg
);
23889 emit_move_insn (work_reg
, arm_hfp_rtx
);
23891 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
23892 x
= gen_frame_mem (SImode
, x
);
23893 emit_move_insn (x
, work_reg
);
23895 x
= gen_rtx_REG (SImode
, PC_REGNUM
);
23896 emit_move_insn (work_reg
, x
);
23898 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 12);
23899 x
= gen_frame_mem (SImode
, x
);
23900 emit_move_insn (x
, work_reg
);
23903 x
= gen_rtx_REG (SImode
, LR_REGNUM
);
23904 emit_move_insn (work_reg
, x
);
23906 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 8);
23907 x
= gen_frame_mem (SImode
, x
);
23908 emit_move_insn (x
, work_reg
);
23910 x
= GEN_INT (offset
+ 12);
23911 emit_insn (gen_addsi3 (work_reg
, stack_pointer_rtx
, x
));
23913 emit_move_insn (arm_hfp_rtx
, work_reg
);
23915 /* Optimization: If we are not pushing any low registers but we are going
23916 to push some high registers then delay our first push. This will just
23917 be a push of LR and we can combine it with the push of the first high
23919 else if ((l_mask
& 0xff) != 0
23920 || (high_regs_pushed
== 0 && l_mask
))
23922 unsigned long mask
= l_mask
;
23923 mask
|= (1 << thumb1_extra_regs_pushed (offsets
, true)) - 1;
23924 insn
= thumb1_emit_multi_reg_push (mask
, mask
);
23925 RTX_FRAME_RELATED_P (insn
) = 1;
23928 if (high_regs_pushed
)
23930 unsigned pushable_regs
;
23931 unsigned next_hi_reg
;
23932 unsigned arg_regs_num
= TARGET_AAPCS_BASED
? crtl
->args
.info
.aapcs_ncrn
23933 : crtl
->args
.info
.nregs
;
23934 unsigned arg_regs_mask
= (1 << arg_regs_num
) - 1;
23936 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
23937 if (live_regs_mask
& (1 << next_hi_reg
))
23940 /* Here we need to mask out registers used for passing arguments
23941 even if they can be pushed. This is to avoid using them to stash the high
23942 registers. Such kind of stash may clobber the use of arguments. */
23943 pushable_regs
= l_mask
& (~arg_regs_mask
) & 0xff;
23945 if (pushable_regs
== 0)
23946 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
23948 while (high_regs_pushed
> 0)
23950 unsigned long real_regs_mask
= 0;
23952 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
23954 if (pushable_regs
& (1 << regno
))
23956 emit_move_insn (gen_rtx_REG (SImode
, regno
),
23957 gen_rtx_REG (SImode
, next_hi_reg
));
23959 high_regs_pushed
--;
23960 real_regs_mask
|= (1 << next_hi_reg
);
23962 if (high_regs_pushed
)
23964 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
23966 if (live_regs_mask
& (1 << next_hi_reg
))
23971 pushable_regs
&= ~((1 << regno
) - 1);
23977 /* If we had to find a work register and we have not yet
23978 saved the LR then add it to the list of regs to push. */
23979 if (l_mask
== (1 << LR_REGNUM
))
23981 pushable_regs
|= l_mask
;
23982 real_regs_mask
|= l_mask
;
23986 insn
= thumb1_emit_multi_reg_push (pushable_regs
, real_regs_mask
);
23987 RTX_FRAME_RELATED_P (insn
) = 1;
23991 /* Load the pic register before setting the frame pointer,
23992 so we can use r7 as a temporary work register. */
23993 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
23994 arm_load_pic_register (live_regs_mask
);
23996 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
23997 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
23998 stack_pointer_rtx
);
24000 if (flag_stack_usage_info
)
24001 current_function_static_stack_size
24002 = offsets
->outgoing_args
- offsets
->saved_args
;
24004 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
24005 amount
-= 4 * thumb1_extra_regs_pushed (offsets
, true);
24010 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
24011 GEN_INT (- amount
)));
24012 RTX_FRAME_RELATED_P (insn
) = 1;
24018 /* The stack decrement is too big for an immediate value in a single
24019 insn. In theory we could issue multiple subtracts, but after
24020 three of them it becomes more space efficient to place the full
24021 value in the constant pool and load into a register. (Also the
24022 ARM debugger really likes to see only one stack decrement per
24023 function). So instead we look for a scratch register into which
24024 we can load the decrement, and then we subtract this from the
24025 stack pointer. Unfortunately on the thumb the only available
24026 scratch registers are the argument registers, and we cannot use
24027 these as they may hold arguments to the function. Instead we
24028 attempt to locate a call preserved register which is used by this
24029 function. If we can find one, then we know that it will have
24030 been pushed at the start of the prologue and so we can corrupt
24032 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
24033 if (live_regs_mask
& (1 << regno
))
24036 gcc_assert(regno
<= LAST_LO_REGNUM
);
24038 reg
= gen_rtx_REG (SImode
, regno
);
24040 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
24042 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
24043 stack_pointer_rtx
, reg
));
24045 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
24046 plus_constant (Pmode
, stack_pointer_rtx
,
24048 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
24049 RTX_FRAME_RELATED_P (insn
) = 1;
24053 if (frame_pointer_needed
)
24054 thumb_set_frame_pointer (offsets
);
24056 /* If we are profiling, make sure no instructions are scheduled before
24057 the call to mcount. Similarly if the user has requested no
24058 scheduling in the prolog. Similarly if we want non-call exceptions
24059 using the EABI unwinder, to prevent faulting instructions from being
24060 swapped with a stack adjustment. */
24061 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
24062 || (arm_except_unwind_info (&global_options
) == UI_TARGET
24063 && cfun
->can_throw_non_call_exceptions
))
24064 emit_insn (gen_blockage ());
24066 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
24067 if (live_regs_mask
& 0xff)
24068 cfun
->machine
->lr_save_eliminated
= 0;
24071 /* Generate pattern *pop_multiple_with_stack_update_and_return if single
24072 POP instruction can be generated. LR should be replaced by PC. All
24073 the checks required are already done by USE_RETURN_INSN (). Hence,
24074 all we really need to check here is if single register is to be
24075 returned, or multiple register return. */
24077 thumb2_expand_return (bool simple_return
)
24080 unsigned long saved_regs_mask
;
24081 arm_stack_offsets
*offsets
;
24083 offsets
= arm_get_frame_offsets ();
24084 saved_regs_mask
= offsets
->saved_regs_mask
;
24086 for (i
= 0, num_regs
= 0; i
<= LAST_ARM_REGNUM
; i
++)
24087 if (saved_regs_mask
& (1 << i
))
24090 if (!simple_return
&& saved_regs_mask
)
24094 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
24095 rtx reg
= gen_rtx_REG (SImode
, PC_REGNUM
);
24096 rtx addr
= gen_rtx_MEM (SImode
,
24097 gen_rtx_POST_INC (SImode
,
24098 stack_pointer_rtx
));
24099 set_mem_alias_set (addr
, get_frame_alias_set ());
24100 XVECEXP (par
, 0, 0) = ret_rtx
;
24101 XVECEXP (par
, 0, 1) = gen_rtx_SET (SImode
, reg
, addr
);
24102 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, 1)) = 1;
24103 emit_jump_insn (par
);
24107 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
24108 saved_regs_mask
|= (1 << PC_REGNUM
);
24109 arm_emit_multi_reg_pop (saved_regs_mask
);
24114 emit_jump_insn (simple_return_rtx
);
24119 thumb1_expand_epilogue (void)
24121 HOST_WIDE_INT amount
;
24122 arm_stack_offsets
*offsets
;
24125 /* Naked functions don't have prologues. */
24126 if (IS_NAKED (arm_current_func_type ()))
24129 offsets
= arm_get_frame_offsets ();
24130 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
24132 if (frame_pointer_needed
)
24134 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
24135 amount
= offsets
->locals_base
- offsets
->saved_regs
;
24137 amount
-= 4 * thumb1_extra_regs_pushed (offsets
, false);
24139 gcc_assert (amount
>= 0);
24142 emit_insn (gen_blockage ());
24145 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
24146 GEN_INT (amount
)));
24149 /* r3 is always free in the epilogue. */
24150 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
24152 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
24153 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
24157 /* Emit a USE (stack_pointer_rtx), so that
24158 the stack adjustment will not be deleted. */
24159 emit_insn (gen_force_register_use (stack_pointer_rtx
));
24161 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
)
24162 emit_insn (gen_blockage ());
24164 /* Emit a clobber for each insn that will be restored in the epilogue,
24165 so that flow2 will get register lifetimes correct. */
24166 for (regno
= 0; regno
< 13; regno
++)
24167 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
24168 emit_clobber (gen_rtx_REG (SImode
, regno
));
24170 if (! df_regs_ever_live_p (LR_REGNUM
))
24171 emit_use (gen_rtx_REG (SImode
, LR_REGNUM
));
24174 /* Epilogue code for APCS frame. */
24176 arm_expand_epilogue_apcs_frame (bool really_return
)
24178 unsigned long func_type
;
24179 unsigned long saved_regs_mask
;
24182 int floats_from_frame
= 0;
24183 arm_stack_offsets
*offsets
;
24185 gcc_assert (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
);
24186 func_type
= arm_current_func_type ();
24188 /* Get frame offsets for ARM. */
24189 offsets
= arm_get_frame_offsets ();
24190 saved_regs_mask
= offsets
->saved_regs_mask
;
24192 /* Find the offset of the floating-point save area in the frame. */
24193 floats_from_frame
= offsets
->saved_args
- offsets
->frame
;
24195 /* Compute how many core registers saved and how far away the floats are. */
24196 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
24197 if (saved_regs_mask
& (1 << i
))
24200 floats_from_frame
+= 4;
24203 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
24207 /* The offset is from IP_REGNUM. */
24208 int saved_size
= arm_get_vfp_saved_size ();
24209 if (saved_size
> 0)
24211 floats_from_frame
+= saved_size
;
24212 emit_insn (gen_addsi3 (gen_rtx_REG (SImode
, IP_REGNUM
),
24213 hard_frame_pointer_rtx
,
24214 GEN_INT (-floats_from_frame
)));
24217 /* Generate VFP register multi-pop. */
24218 start_reg
= FIRST_VFP_REGNUM
;
24220 for (i
= FIRST_VFP_REGNUM
; i
< LAST_VFP_REGNUM
; i
+= 2)
24221 /* Look for a case where a reg does not need restoring. */
24222 if ((!df_regs_ever_live_p (i
) || call_used_regs
[i
])
24223 && (!df_regs_ever_live_p (i
+ 1)
24224 || call_used_regs
[i
+ 1]))
24226 if (start_reg
!= i
)
24227 arm_emit_vfp_multi_reg_pop (start_reg
,
24228 (i
- start_reg
) / 2,
24229 gen_rtx_REG (SImode
,
24234 /* Restore the remaining regs that we have discovered (or possibly
24235 even all of them, if the conditional in the for loop never
24237 if (start_reg
!= i
)
24238 arm_emit_vfp_multi_reg_pop (start_reg
,
24239 (i
- start_reg
) / 2,
24240 gen_rtx_REG (SImode
, IP_REGNUM
));
24245 /* The frame pointer is guaranteed to be non-double-word aligned, as
24246 it is set to double-word-aligned old_stack_pointer - 4. */
24248 int lrm_count
= (num_regs
% 2) ? (num_regs
+ 2) : (num_regs
+ 1);
24250 for (i
= LAST_IWMMXT_REGNUM
; i
>= FIRST_IWMMXT_REGNUM
; i
--)
24251 if (df_regs_ever_live_p (i
) && !call_used_regs
[i
])
24253 rtx addr
= gen_frame_mem (V2SImode
,
24254 plus_constant (Pmode
, hard_frame_pointer_rtx
,
24256 insn
= emit_insn (gen_movsi (gen_rtx_REG (V2SImode
, i
), addr
));
24257 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
24258 gen_rtx_REG (V2SImode
, i
),
24264 /* saved_regs_mask should contain IP which contains old stack pointer
24265 at the time of activation creation. Since SP and IP are adjacent registers,
24266 we can restore the value directly into SP. */
24267 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
24268 saved_regs_mask
&= ~(1 << IP_REGNUM
);
24269 saved_regs_mask
|= (1 << SP_REGNUM
);
24271 /* There are two registers left in saved_regs_mask - LR and PC. We
24272 only need to restore LR (the return address), but to
24273 save time we can load it directly into PC, unless we need a
24274 special function exit sequence, or we are not really returning. */
24276 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
24277 && !crtl
->calls_eh_return
)
24278 /* Delete LR from the register mask, so that LR on
24279 the stack is loaded into the PC in the register mask. */
24280 saved_regs_mask
&= ~(1 << LR_REGNUM
);
24282 saved_regs_mask
&= ~(1 << PC_REGNUM
);
24284 num_regs
= bit_count (saved_regs_mask
);
24285 if ((offsets
->outgoing_args
!= (1 + num_regs
)) || cfun
->calls_alloca
)
24287 /* Unwind the stack to just below the saved registers. */
24288 emit_insn (gen_addsi3 (stack_pointer_rtx
,
24289 hard_frame_pointer_rtx
,
24290 GEN_INT (- 4 * num_regs
)));
24293 arm_emit_multi_reg_pop (saved_regs_mask
);
24295 if (IS_INTERRUPT (func_type
))
24297 /* Interrupt handlers will have pushed the
24298 IP onto the stack, so restore it now. */
24300 rtx addr
= gen_rtx_MEM (SImode
,
24301 gen_rtx_POST_INC (SImode
,
24302 stack_pointer_rtx
));
24303 set_mem_alias_set (addr
, get_frame_alias_set ());
24304 insn
= emit_insn (gen_movsi (gen_rtx_REG (SImode
, IP_REGNUM
), addr
));
24305 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
24306 gen_rtx_REG (SImode
, IP_REGNUM
),
24310 if (!really_return
|| (saved_regs_mask
& (1 << PC_REGNUM
)))
24313 if (crtl
->calls_eh_return
)
24314 emit_insn (gen_addsi3 (stack_pointer_rtx
,
24316 GEN_INT (ARM_EH_STACKADJ_REGNUM
)));
24318 if (IS_STACKALIGN (func_type
))
24319 /* Restore the original stack pointer. Before prologue, the stack was
24320 realigned and the original stack pointer saved in r0. For details,
24321 see comment in arm_expand_prologue. */
24322 emit_insn (gen_movsi (stack_pointer_rtx
, gen_rtx_REG (SImode
, 0)));
24324 emit_jump_insn (simple_return_rtx
);
24327 /* Generate RTL to represent ARM epilogue. Really_return is true if the
24328 function is not a sibcall. */
24330 arm_expand_epilogue (bool really_return
)
24332 unsigned long func_type
;
24333 unsigned long saved_regs_mask
;
24337 arm_stack_offsets
*offsets
;
24339 func_type
= arm_current_func_type ();
24341 /* Naked functions don't have epilogue. Hence, generate return pattern, and
24342 let output_return_instruction take care of instruction emition if any. */
24343 if (IS_NAKED (func_type
)
24344 || (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
))
24347 emit_jump_insn (simple_return_rtx
);
24351 /* If we are throwing an exception, then we really must be doing a
24352 return, so we can't tail-call. */
24353 gcc_assert (!crtl
->calls_eh_return
|| really_return
);
24355 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
24357 arm_expand_epilogue_apcs_frame (really_return
);
24361 /* Get frame offsets for ARM. */
24362 offsets
= arm_get_frame_offsets ();
24363 saved_regs_mask
= offsets
->saved_regs_mask
;
24364 num_regs
= bit_count (saved_regs_mask
);
24366 if (frame_pointer_needed
)
24369 /* Restore stack pointer if necessary. */
24372 /* In ARM mode, frame pointer points to first saved register.
24373 Restore stack pointer to last saved register. */
24374 amount
= offsets
->frame
- offsets
->saved_regs
;
24376 /* Force out any pending memory operations that reference stacked data
24377 before stack de-allocation occurs. */
24378 emit_insn (gen_blockage ());
24379 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
24380 hard_frame_pointer_rtx
,
24381 GEN_INT (amount
)));
24382 arm_add_cfa_adjust_cfa_note (insn
, amount
,
24384 hard_frame_pointer_rtx
);
24386 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
24388 emit_insn (gen_force_register_use (stack_pointer_rtx
));
24392 /* In Thumb-2 mode, the frame pointer points to the last saved
24394 amount
= offsets
->locals_base
- offsets
->saved_regs
;
24397 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
24398 hard_frame_pointer_rtx
,
24399 GEN_INT (amount
)));
24400 arm_add_cfa_adjust_cfa_note (insn
, amount
,
24401 hard_frame_pointer_rtx
,
24402 hard_frame_pointer_rtx
);
24405 /* Force out any pending memory operations that reference stacked data
24406 before stack de-allocation occurs. */
24407 emit_insn (gen_blockage ());
24408 insn
= emit_insn (gen_movsi (stack_pointer_rtx
,
24409 hard_frame_pointer_rtx
));
24410 arm_add_cfa_adjust_cfa_note (insn
, 0,
24412 hard_frame_pointer_rtx
);
24413 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
24415 emit_insn (gen_force_register_use (stack_pointer_rtx
));
24420 /* Pop off outgoing args and local frame to adjust stack pointer to
24421 last saved register. */
24422 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
24426 /* Force out any pending memory operations that reference stacked data
24427 before stack de-allocation occurs. */
24428 emit_insn (gen_blockage ());
24429 tmp
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
24431 GEN_INT (amount
)));
24432 arm_add_cfa_adjust_cfa_note (tmp
, amount
,
24433 stack_pointer_rtx
, stack_pointer_rtx
);
24434 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is
24436 emit_insn (gen_force_register_use (stack_pointer_rtx
));
24440 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
24442 /* Generate VFP register multi-pop. */
24443 int end_reg
= LAST_VFP_REGNUM
+ 1;
24445 /* Scan the registers in reverse order. We need to match
24446 any groupings made in the prologue and generate matching
24447 vldm operations. The need to match groups is because,
24448 unlike pop, vldm can only do consecutive regs. */
24449 for (i
= LAST_VFP_REGNUM
- 1; i
>= FIRST_VFP_REGNUM
; i
-= 2)
24450 /* Look for a case where a reg does not need restoring. */
24451 if ((!df_regs_ever_live_p (i
) || call_used_regs
[i
])
24452 && (!df_regs_ever_live_p (i
+ 1)
24453 || call_used_regs
[i
+ 1]))
24455 /* Restore the regs discovered so far (from reg+2 to
24457 if (end_reg
> i
+ 2)
24458 arm_emit_vfp_multi_reg_pop (i
+ 2,
24459 (end_reg
- (i
+ 2)) / 2,
24460 stack_pointer_rtx
);
24464 /* Restore the remaining regs that we have discovered (or possibly
24465 even all of them, if the conditional in the for loop never
24467 if (end_reg
> i
+ 2)
24468 arm_emit_vfp_multi_reg_pop (i
+ 2,
24469 (end_reg
- (i
+ 2)) / 2,
24470 stack_pointer_rtx
);
24474 for (i
= FIRST_IWMMXT_REGNUM
; i
<= LAST_IWMMXT_REGNUM
; i
++)
24475 if (df_regs_ever_live_p (i
) && !call_used_regs
[i
])
24478 rtx addr
= gen_rtx_MEM (V2SImode
,
24479 gen_rtx_POST_INC (SImode
,
24480 stack_pointer_rtx
));
24481 set_mem_alias_set (addr
, get_frame_alias_set ());
24482 insn
= emit_insn (gen_movsi (gen_rtx_REG (V2SImode
, i
), addr
));
24483 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
24484 gen_rtx_REG (V2SImode
, i
),
24486 arm_add_cfa_adjust_cfa_note (insn
, UNITS_PER_WORD
,
24487 stack_pointer_rtx
, stack_pointer_rtx
);
24490 if (saved_regs_mask
)
24493 bool return_in_pc
= false;
24495 if (ARM_FUNC_TYPE (func_type
) != ARM_FT_INTERWORKED
24496 && (TARGET_ARM
|| ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
24497 && !IS_STACKALIGN (func_type
)
24499 && crtl
->args
.pretend_args_size
== 0
24500 && saved_regs_mask
& (1 << LR_REGNUM
)
24501 && !crtl
->calls_eh_return
)
24503 saved_regs_mask
&= ~(1 << LR_REGNUM
);
24504 saved_regs_mask
|= (1 << PC_REGNUM
);
24505 return_in_pc
= true;
24508 if (num_regs
== 1 && (!IS_INTERRUPT (func_type
) || !return_in_pc
))
24510 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
24511 if (saved_regs_mask
& (1 << i
))
24513 rtx addr
= gen_rtx_MEM (SImode
,
24514 gen_rtx_POST_INC (SImode
,
24515 stack_pointer_rtx
));
24516 set_mem_alias_set (addr
, get_frame_alias_set ());
24518 if (i
== PC_REGNUM
)
24520 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
24521 XVECEXP (insn
, 0, 0) = ret_rtx
;
24522 XVECEXP (insn
, 0, 1) = gen_rtx_SET (SImode
,
24523 gen_rtx_REG (SImode
, i
),
24525 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, 1)) = 1;
24526 insn
= emit_jump_insn (insn
);
24530 insn
= emit_insn (gen_movsi (gen_rtx_REG (SImode
, i
),
24532 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
24533 gen_rtx_REG (SImode
, i
),
24535 arm_add_cfa_adjust_cfa_note (insn
, UNITS_PER_WORD
,
24537 stack_pointer_rtx
);
24543 if (current_tune
->prefer_ldrd_strd
24544 && !optimize_function_for_size_p (cfun
))
24547 thumb2_emit_ldrd_pop (saved_regs_mask
);
24548 else if (TARGET_ARM
&& !IS_INTERRUPT (func_type
))
24549 arm_emit_ldrd_pop (saved_regs_mask
);
24551 arm_emit_multi_reg_pop (saved_regs_mask
);
24554 arm_emit_multi_reg_pop (saved_regs_mask
);
24557 if (return_in_pc
== true)
24561 if (crtl
->args
.pretend_args_size
)
24564 rtx dwarf
= NULL_RTX
;
24565 rtx tmp
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
24567 GEN_INT (crtl
->args
.pretend_args_size
)));
24569 RTX_FRAME_RELATED_P (tmp
) = 1;
24571 if (cfun
->machine
->uses_anonymous_args
)
24573 /* Restore pretend args. Refer arm_expand_prologue on how to save
24574 pretend_args in stack. */
24575 int num_regs
= crtl
->args
.pretend_args_size
/ 4;
24576 saved_regs_mask
= (0xf0 >> num_regs
) & 0xf;
24577 for (j
= 0, i
= 0; j
< num_regs
; i
++)
24578 if (saved_regs_mask
& (1 << i
))
24580 rtx reg
= gen_rtx_REG (SImode
, i
);
24581 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
24584 REG_NOTES (tmp
) = dwarf
;
24586 arm_add_cfa_adjust_cfa_note (tmp
, crtl
->args
.pretend_args_size
,
24587 stack_pointer_rtx
, stack_pointer_rtx
);
24590 if (!really_return
)
24593 if (crtl
->calls_eh_return
)
24594 emit_insn (gen_addsi3 (stack_pointer_rtx
,
24596 gen_rtx_REG (SImode
, ARM_EH_STACKADJ_REGNUM
)));
24598 if (IS_STACKALIGN (func_type
))
24599 /* Restore the original stack pointer. Before prologue, the stack was
24600 realigned and the original stack pointer saved in r0. For details,
24601 see comment in arm_expand_prologue. */
24602 emit_insn (gen_movsi (stack_pointer_rtx
, gen_rtx_REG (SImode
, 0)));
24604 emit_jump_insn (simple_return_rtx
);
24607 /* Implementation of insn prologue_thumb1_interwork. This is the first
24608 "instruction" of a function called in ARM mode. Swap to thumb mode. */
24611 thumb1_output_interwork (void)
24614 FILE *f
= asm_out_file
;
24616 gcc_assert (MEM_P (DECL_RTL (current_function_decl
)));
24617 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
24619 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24621 /* Generate code sequence to switch us into Thumb mode. */
24622 /* The .code 32 directive has already been emitted by
24623 ASM_DECLARE_FUNCTION_NAME. */
24624 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
24625 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
24627 /* Generate a label, so that the debugger will notice the
24628 change in instruction sets. This label is also used by
24629 the assembler to bypass the ARM code when this function
24630 is called from a Thumb encoded function elsewhere in the
24631 same file. Hence the definition of STUB_NAME here must
24632 agree with the definition in gas/config/tc-arm.c. */
24634 #define STUB_NAME ".real_start_of"
24636 fprintf (f
, "\t.code\t16\n");
24638 if (arm_dllexport_name_p (name
))
24639 name
= arm_strip_name_encoding (name
);
24641 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
24642 fprintf (f
, "\t.thumb_func\n");
24643 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
24648 /* Handle the case of a double word load into a low register from
24649 a computed memory address. The computed address may involve a
24650 register which is overwritten by the load. */
24652 thumb_load_double_from_address (rtx
*operands
)
24660 gcc_assert (REG_P (operands
[0]));
24661 gcc_assert (MEM_P (operands
[1]));
24663 /* Get the memory address. */
24664 addr
= XEXP (operands
[1], 0);
24666 /* Work out how the memory address is computed. */
24667 switch (GET_CODE (addr
))
24670 operands
[2] = adjust_address (operands
[1], SImode
, 4);
24672 if (REGNO (operands
[0]) == REGNO (addr
))
24674 output_asm_insn ("ldr\t%H0, %2", operands
);
24675 output_asm_insn ("ldr\t%0, %1", operands
);
24679 output_asm_insn ("ldr\t%0, %1", operands
);
24680 output_asm_insn ("ldr\t%H0, %2", operands
);
24685 /* Compute <address> + 4 for the high order load. */
24686 operands
[2] = adjust_address (operands
[1], SImode
, 4);
24688 output_asm_insn ("ldr\t%0, %1", operands
);
24689 output_asm_insn ("ldr\t%H0, %2", operands
);
24693 arg1
= XEXP (addr
, 0);
24694 arg2
= XEXP (addr
, 1);
24696 if (CONSTANT_P (arg1
))
24697 base
= arg2
, offset
= arg1
;
24699 base
= arg1
, offset
= arg2
;
24701 gcc_assert (REG_P (base
));
24703 /* Catch the case of <address> = <reg> + <reg> */
24704 if (REG_P (offset
))
24706 int reg_offset
= REGNO (offset
);
24707 int reg_base
= REGNO (base
);
24708 int reg_dest
= REGNO (operands
[0]);
24710 /* Add the base and offset registers together into the
24711 higher destination register. */
24712 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
24713 reg_dest
+ 1, reg_base
, reg_offset
);
24715 /* Load the lower destination register from the address in
24716 the higher destination register. */
24717 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
24718 reg_dest
, reg_dest
+ 1);
24720 /* Load the higher destination register from its own address
24722 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
24723 reg_dest
+ 1, reg_dest
+ 1);
24727 /* Compute <address> + 4 for the high order load. */
24728 operands
[2] = adjust_address (operands
[1], SImode
, 4);
24730 /* If the computed address is held in the low order register
24731 then load the high order register first, otherwise always
24732 load the low order register first. */
24733 if (REGNO (operands
[0]) == REGNO (base
))
24735 output_asm_insn ("ldr\t%H0, %2", operands
);
24736 output_asm_insn ("ldr\t%0, %1", operands
);
24740 output_asm_insn ("ldr\t%0, %1", operands
);
24741 output_asm_insn ("ldr\t%H0, %2", operands
);
24747 /* With no registers to worry about we can just load the value
24749 operands
[2] = adjust_address (operands
[1], SImode
, 4);
24751 output_asm_insn ("ldr\t%H0, %2", operands
);
24752 output_asm_insn ("ldr\t%0, %1", operands
);
24756 gcc_unreachable ();
24763 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
24770 if (REGNO (operands
[4]) > REGNO (operands
[5]))
24773 operands
[4] = operands
[5];
24776 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
24777 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
24781 if (REGNO (operands
[4]) > REGNO (operands
[5]))
24784 operands
[4] = operands
[5];
24787 if (REGNO (operands
[5]) > REGNO (operands
[6]))
24790 operands
[5] = operands
[6];
24793 if (REGNO (operands
[4]) > REGNO (operands
[5]))
24796 operands
[4] = operands
[5];
24800 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
24801 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
24805 gcc_unreachable ();
24811 /* Output a call-via instruction for thumb state. */
24813 thumb_call_via_reg (rtx reg
)
24815 int regno
= REGNO (reg
);
24818 gcc_assert (regno
< LR_REGNUM
);
24820 /* If we are in the normal text section we can use a single instance
24821 per compilation unit. If we are doing function sections, then we need
24822 an entry per section, since we can't rely on reachability. */
24823 if (in_section
== text_section
)
24825 thumb_call_reg_needed
= 1;
24827 if (thumb_call_via_label
[regno
] == NULL
)
24828 thumb_call_via_label
[regno
] = gen_label_rtx ();
24829 labelp
= thumb_call_via_label
+ regno
;
24833 if (cfun
->machine
->call_via
[regno
] == NULL
)
24834 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
24835 labelp
= cfun
->machine
->call_via
+ regno
;
24838 output_asm_insn ("bl\t%a0", labelp
);
24842 /* Routines for generating rtl. */
24844 thumb_expand_movmemqi (rtx
*operands
)
24846 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
24847 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
24848 HOST_WIDE_INT len
= INTVAL (operands
[2]);
24849 HOST_WIDE_INT offset
= 0;
24853 emit_insn (gen_movmem12b (out
, in
, out
, in
));
24859 emit_insn (gen_movmem8b (out
, in
, out
, in
));
24865 rtx reg
= gen_reg_rtx (SImode
);
24866 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
24867 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
24874 rtx reg
= gen_reg_rtx (HImode
);
24875 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
24876 plus_constant (Pmode
, in
,
24878 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (Pmode
, out
,
24887 rtx reg
= gen_reg_rtx (QImode
);
24888 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
24889 plus_constant (Pmode
, in
,
24891 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (Pmode
, out
,
24898 thumb_reload_out_hi (rtx
*operands
)
24900 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
24903 /* Handle reading a half-word from memory during reload. */
24905 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
24907 gcc_unreachable ();
24910 /* Return the length of a function name prefix
24911 that starts with the character 'c'. */
24913 arm_get_strip_length (int c
)
24917 ARM_NAME_ENCODING_LENGTHS
24922 /* Return a pointer to a function's name with any
24923 and all prefix encodings stripped from it. */
24925 arm_strip_name_encoding (const char *name
)
24929 while ((skip
= arm_get_strip_length (* name
)))
24935 /* If there is a '*' anywhere in the name's prefix, then
24936 emit the stripped name verbatim, otherwise prepend an
24937 underscore if leading underscores are being used. */
24939 arm_asm_output_labelref (FILE *stream
, const char *name
)
24944 while ((skip
= arm_get_strip_length (* name
)))
24946 verbatim
|= (*name
== '*');
24951 fputs (name
, stream
);
24953 asm_fprintf (stream
, "%U%s", name
);
24956 /* This function is used to emit an EABI tag and its associated value.
24957 We emit the numerical value of the tag in case the assembler does not
24958 support textual tags. (Eg gas prior to 2.20). If requested we include
24959 the tag name in a comment so that anyone reading the assembler output
24960 will know which tag is being set.
24962 This function is not static because arm-c.c needs it too. */
24965 arm_emit_eabi_attribute (const char *name
, int num
, int val
)
24967 asm_fprintf (asm_out_file
, "\t.eabi_attribute %d, %d", num
, val
);
24968 if (flag_verbose_asm
|| flag_debug_asm
)
24969 asm_fprintf (asm_out_file
, "\t%s %s", ASM_COMMENT_START
, name
);
24970 asm_fprintf (asm_out_file
, "\n");
24974 arm_file_start (void)
24978 if (TARGET_UNIFIED_ASM
)
24979 asm_fprintf (asm_out_file
, "\t.syntax unified\n");
24983 const char *fpu_name
;
24984 if (arm_selected_arch
)
24985 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_selected_arch
->name
);
24986 else if (strncmp (arm_selected_cpu
->name
, "generic", 7) == 0)
24987 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_selected_cpu
->name
+ 8);
24989 asm_fprintf (asm_out_file
, "\t.cpu %s\n", arm_selected_cpu
->name
);
24991 if (TARGET_SOFT_FLOAT
)
24993 fpu_name
= "softvfp";
24997 fpu_name
= arm_fpu_desc
->name
;
24998 if (arm_fpu_desc
->model
== ARM_FP_MODEL_VFP
)
25000 if (TARGET_HARD_FLOAT
)
25001 arm_emit_eabi_attribute ("Tag_ABI_HardFP_use", 27, 3);
25002 if (TARGET_HARD_FLOAT_ABI
)
25003 arm_emit_eabi_attribute ("Tag_ABI_VFP_args", 28, 1);
25006 asm_fprintf (asm_out_file
, "\t.fpu %s\n", fpu_name
);
25008 /* Some of these attributes only apply when the corresponding features
25009 are used. However we don't have any easy way of figuring this out.
25010 Conservatively record the setting that would have been used. */
25012 if (flag_rounding_math
)
25013 arm_emit_eabi_attribute ("Tag_ABI_FP_rounding", 19, 1);
25015 if (!flag_unsafe_math_optimizations
)
25017 arm_emit_eabi_attribute ("Tag_ABI_FP_denormal", 20, 1);
25018 arm_emit_eabi_attribute ("Tag_ABI_FP_exceptions", 21, 1);
25020 if (flag_signaling_nans
)
25021 arm_emit_eabi_attribute ("Tag_ABI_FP_user_exceptions", 22, 1);
25023 arm_emit_eabi_attribute ("Tag_ABI_FP_number_model", 23,
25024 flag_finite_math_only
? 1 : 3);
25026 arm_emit_eabi_attribute ("Tag_ABI_align8_needed", 24, 1);
25027 arm_emit_eabi_attribute ("Tag_ABI_align8_preserved", 25, 1);
25028 arm_emit_eabi_attribute ("Tag_ABI_enum_size", 26,
25029 flag_short_enums
? 1 : 2);
25031 /* Tag_ABI_optimization_goals. */
25034 else if (optimize
>= 2)
25040 arm_emit_eabi_attribute ("Tag_ABI_optimization_goals", 30, val
);
25042 arm_emit_eabi_attribute ("Tag_CPU_unaligned_access", 34,
25045 if (arm_fp16_format
)
25046 arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
25047 (int) arm_fp16_format
);
25049 if (arm_lang_output_object_attributes_hook
)
25050 arm_lang_output_object_attributes_hook();
25053 default_file_start ();
25057 arm_file_end (void)
25061 if (NEED_INDICATE_EXEC_STACK
)
25062 /* Add .note.GNU-stack. */
25063 file_end_indicate_exec_stack ();
25065 if (! thumb_call_reg_needed
)
25068 switch_to_section (text_section
);
25069 asm_fprintf (asm_out_file
, "\t.code 16\n");
25070 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
25072 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
25074 rtx label
= thumb_call_via_label
[regno
];
25078 targetm
.asm_out
.internal_label (asm_out_file
, "L",
25079 CODE_LABEL_NUMBER (label
));
25080 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
25086 /* Symbols in the text segment can be accessed without indirecting via the
25087 constant pool; it may take an extra binary operation, but this is still
25088 faster than indirecting via memory. Don't do this when not optimizing,
25089 since we won't be calculating al of the offsets necessary to do this
25093 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
25095 if (optimize
> 0 && TREE_CONSTANT (decl
))
25096 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
25098 default_encode_section_info (decl
, rtl
, first
);
25100 #endif /* !ARM_PE */
25103 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
25105 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
25106 && !strcmp (prefix
, "L"))
25108 arm_ccfsm_state
= 0;
25109 arm_target_insn
= NULL
;
25111 default_internal_label (stream
, prefix
, labelno
);
25114 /* Output code to add DELTA to the first argument, and then jump
25115 to FUNCTION. Used for C++ multiple inheritance. */
25117 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
25118 HOST_WIDE_INT delta
,
25119 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
25122 static int thunk_label
= 0;
25125 int mi_delta
= delta
;
25126 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
25128 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
25131 mi_delta
= - mi_delta
;
25133 final_start_function (emit_barrier (), file
, 1);
25137 int labelno
= thunk_label
++;
25138 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
25139 /* Thunks are entered in arm mode when avaiable. */
25140 if (TARGET_THUMB1_ONLY
)
25142 /* push r3 so we can use it as a temporary. */
25143 /* TODO: Omit this save if r3 is not used. */
25144 fputs ("\tpush {r3}\n", file
);
25145 fputs ("\tldr\tr3, ", file
);
25149 fputs ("\tldr\tr12, ", file
);
25151 assemble_name (file
, label
);
25152 fputc ('\n', file
);
25155 /* If we are generating PIC, the ldr instruction below loads
25156 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
25157 the address of the add + 8, so we have:
25159 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
25162 Note that we have "+ 1" because some versions of GNU ld
25163 don't set the low bit of the result for R_ARM_REL32
25164 relocations against thumb function symbols.
25165 On ARMv6M this is +4, not +8. */
25166 ASM_GENERATE_INTERNAL_LABEL (labelpc
, "LTHUNKPC", labelno
);
25167 assemble_name (file
, labelpc
);
25168 fputs (":\n", file
);
25169 if (TARGET_THUMB1_ONLY
)
25171 /* This is 2 insns after the start of the thunk, so we know it
25172 is 4-byte aligned. */
25173 fputs ("\tadd\tr3, pc, r3\n", file
);
25174 fputs ("\tmov r12, r3\n", file
);
25177 fputs ("\tadd\tr12, pc, r12\n", file
);
25179 else if (TARGET_THUMB1_ONLY
)
25180 fputs ("\tmov r12, r3\n", file
);
25182 if (TARGET_THUMB1_ONLY
)
25184 if (mi_delta
> 255)
25186 fputs ("\tldr\tr3, ", file
);
25187 assemble_name (file
, label
);
25188 fputs ("+4\n", file
);
25189 asm_fprintf (file
, "\t%s\t%r, %r, r3\n",
25190 mi_op
, this_regno
, this_regno
);
25192 else if (mi_delta
!= 0)
25194 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
25195 mi_op
, this_regno
, this_regno
,
25201 /* TODO: Use movw/movt for large constants when available. */
25202 while (mi_delta
!= 0)
25204 if ((mi_delta
& (3 << shift
)) == 0)
25208 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
25209 mi_op
, this_regno
, this_regno
,
25210 mi_delta
& (0xff << shift
));
25211 mi_delta
&= ~(0xff << shift
);
25218 if (TARGET_THUMB1_ONLY
)
25219 fputs ("\tpop\t{r3}\n", file
);
25221 fprintf (file
, "\tbx\tr12\n");
25222 ASM_OUTPUT_ALIGN (file
, 2);
25223 assemble_name (file
, label
);
25224 fputs (":\n", file
);
25227 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
25228 rtx tem
= XEXP (DECL_RTL (function
), 0);
25229 tem
= gen_rtx_PLUS (GET_MODE (tem
), tem
, GEN_INT (-7));
25230 tem
= gen_rtx_MINUS (GET_MODE (tem
),
25232 gen_rtx_SYMBOL_REF (Pmode
,
25233 ggc_strdup (labelpc
)));
25234 assemble_integer (tem
, 4, BITS_PER_WORD
, 1);
25237 /* Output ".word .LTHUNKn". */
25238 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
25240 if (TARGET_THUMB1_ONLY
&& mi_delta
> 255)
25241 assemble_integer (GEN_INT(mi_delta
), 4, BITS_PER_WORD
, 1);
25245 fputs ("\tb\t", file
);
25246 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
25247 if (NEED_PLT_RELOC
)
25248 fputs ("(PLT)", file
);
25249 fputc ('\n', file
);
25252 final_end_function ();
25256 arm_emit_vector_const (FILE *file
, rtx x
)
25259 const char * pattern
;
25261 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
25263 switch (GET_MODE (x
))
25265 case V2SImode
: pattern
= "%08x"; break;
25266 case V4HImode
: pattern
= "%04x"; break;
25267 case V8QImode
: pattern
= "%02x"; break;
25268 default: gcc_unreachable ();
25271 fprintf (file
, "0x");
25272 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
25276 element
= CONST_VECTOR_ELT (x
, i
);
25277 fprintf (file
, pattern
, INTVAL (element
));
25283 /* Emit a fp16 constant appropriately padded to occupy a 4-byte word.
25284 HFmode constant pool entries are actually loaded with ldr. */
25286 arm_emit_fp16_const (rtx c
)
25291 REAL_VALUE_FROM_CONST_DOUBLE (r
, c
);
25292 bits
= real_to_target (NULL
, &r
, HFmode
);
25293 if (WORDS_BIG_ENDIAN
)
25294 assemble_zeros (2);
25295 assemble_integer (GEN_INT (bits
), 2, BITS_PER_WORD
, 1);
25296 if (!WORDS_BIG_ENDIAN
)
25297 assemble_zeros (2);
25301 arm_output_load_gr (rtx
*operands
)
25308 if (!MEM_P (operands
[1])
25309 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
25310 || !REG_P (reg
= XEXP (sum
, 0))
25311 || !CONST_INT_P (offset
= XEXP (sum
, 1))
25312 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
25313 return "wldrw%?\t%0, %1";
25315 /* Fix up an out-of-range load of a GR register. */
25316 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
25317 wcgr
= operands
[0];
25319 output_asm_insn ("ldr%?\t%0, %1", operands
);
25321 operands
[0] = wcgr
;
25323 output_asm_insn ("tmcr%?\t%0, %1", operands
);
25324 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
25329 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
25331 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
25332 named arg and all anonymous args onto the stack.
25333 XXX I know the prologue shouldn't be pushing registers, but it is faster
25337 arm_setup_incoming_varargs (cumulative_args_t pcum_v
,
25338 enum machine_mode mode
,
25341 int second_time ATTRIBUTE_UNUSED
)
25343 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
25346 cfun
->machine
->uses_anonymous_args
= 1;
25347 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
25349 nregs
= pcum
->aapcs_ncrn
;
25350 if ((nregs
& 1) && arm_needs_doubleword_align (mode
, type
))
25354 nregs
= pcum
->nregs
;
25356 if (nregs
< NUM_ARG_REGS
)
25357 *pretend_size
= (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
25360 /* Return nonzero if the CONSUMER instruction (a store) does not need
25361 PRODUCER's value to calculate the address. */
25364 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
25366 rtx value
= PATTERN (producer
);
25367 rtx addr
= PATTERN (consumer
);
25369 if (GET_CODE (value
) == COND_EXEC
)
25370 value
= COND_EXEC_CODE (value
);
25371 if (GET_CODE (value
) == PARALLEL
)
25372 value
= XVECEXP (value
, 0, 0);
25373 value
= XEXP (value
, 0);
25374 if (GET_CODE (addr
) == COND_EXEC
)
25375 addr
= COND_EXEC_CODE (addr
);
25376 if (GET_CODE (addr
) == PARALLEL
)
25377 addr
= XVECEXP (addr
, 0, 0);
25378 addr
= XEXP (addr
, 0);
25380 return !reg_overlap_mentioned_p (value
, addr
);
25383 /* Return nonzero if the CONSUMER instruction (a store) does need
25384 PRODUCER's value to calculate the address. */
25387 arm_early_store_addr_dep (rtx producer
, rtx consumer
)
25389 return !arm_no_early_store_addr_dep (producer
, consumer
);
25392 /* Return nonzero if the CONSUMER instruction (a load) does need
25393 PRODUCER's value to calculate the address. */
25396 arm_early_load_addr_dep (rtx producer
, rtx consumer
)
25398 rtx value
= PATTERN (producer
);
25399 rtx addr
= PATTERN (consumer
);
25401 if (GET_CODE (value
) == COND_EXEC
)
25402 value
= COND_EXEC_CODE (value
);
25403 if (GET_CODE (value
) == PARALLEL
)
25404 value
= XVECEXP (value
, 0, 0);
25405 value
= XEXP (value
, 0);
25406 if (GET_CODE (addr
) == COND_EXEC
)
25407 addr
= COND_EXEC_CODE (addr
);
25408 if (GET_CODE (addr
) == PARALLEL
)
25410 if (GET_CODE (XVECEXP (addr
, 0, 0)) == RETURN
)
25411 addr
= XVECEXP (addr
, 0, 1);
25413 addr
= XVECEXP (addr
, 0, 0);
25415 addr
= XEXP (addr
, 1);
25417 return reg_overlap_mentioned_p (value
, addr
);
25420 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
25421 have an early register shift value or amount dependency on the
25422 result of PRODUCER. */
25425 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
25427 rtx value
= PATTERN (producer
);
25428 rtx op
= PATTERN (consumer
);
25431 if (GET_CODE (value
) == COND_EXEC
)
25432 value
= COND_EXEC_CODE (value
);
25433 if (GET_CODE (value
) == PARALLEL
)
25434 value
= XVECEXP (value
, 0, 0);
25435 value
= XEXP (value
, 0);
25436 if (GET_CODE (op
) == COND_EXEC
)
25437 op
= COND_EXEC_CODE (op
);
25438 if (GET_CODE (op
) == PARALLEL
)
25439 op
= XVECEXP (op
, 0, 0);
25442 early_op
= XEXP (op
, 0);
25443 /* This is either an actual independent shift, or a shift applied to
25444 the first operand of another operation. We want the whole shift
25446 if (REG_P (early_op
))
25449 return !reg_overlap_mentioned_p (value
, early_op
);
25452 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
25453 have an early register shift value dependency on the result of
25457 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
25459 rtx value
= PATTERN (producer
);
25460 rtx op
= PATTERN (consumer
);
25463 if (GET_CODE (value
) == COND_EXEC
)
25464 value
= COND_EXEC_CODE (value
);
25465 if (GET_CODE (value
) == PARALLEL
)
25466 value
= XVECEXP (value
, 0, 0);
25467 value
= XEXP (value
, 0);
25468 if (GET_CODE (op
) == COND_EXEC
)
25469 op
= COND_EXEC_CODE (op
);
25470 if (GET_CODE (op
) == PARALLEL
)
25471 op
= XVECEXP (op
, 0, 0);
25474 early_op
= XEXP (op
, 0);
25476 /* This is either an actual independent shift, or a shift applied to
25477 the first operand of another operation. We want the value being
25478 shifted, in either case. */
25479 if (!REG_P (early_op
))
25480 early_op
= XEXP (early_op
, 0);
25482 return !reg_overlap_mentioned_p (value
, early_op
);
25485 /* Return nonzero if the CONSUMER (a mul or mac op) does not
25486 have an early register mult dependency on the result of
25490 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
25492 rtx value
= PATTERN (producer
);
25493 rtx op
= PATTERN (consumer
);
25495 if (GET_CODE (value
) == COND_EXEC
)
25496 value
= COND_EXEC_CODE (value
);
25497 if (GET_CODE (value
) == PARALLEL
)
25498 value
= XVECEXP (value
, 0, 0);
25499 value
= XEXP (value
, 0);
25500 if (GET_CODE (op
) == COND_EXEC
)
25501 op
= COND_EXEC_CODE (op
);
25502 if (GET_CODE (op
) == PARALLEL
)
25503 op
= XVECEXP (op
, 0, 0);
25506 if (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
25508 if (GET_CODE (XEXP (op
, 0)) == MULT
)
25509 return !reg_overlap_mentioned_p (value
, XEXP (op
, 0));
25511 return !reg_overlap_mentioned_p (value
, XEXP (op
, 1));
25517 /* We can't rely on the caller doing the proper promotion when
25518 using APCS or ATPCS. */
25521 arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED
)
25523 return !TARGET_AAPCS_BASED
;
25526 static enum machine_mode
25527 arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
25528 enum machine_mode mode
,
25529 int *punsignedp ATTRIBUTE_UNUSED
,
25530 const_tree fntype ATTRIBUTE_UNUSED
,
25531 int for_return ATTRIBUTE_UNUSED
)
25533 if (GET_MODE_CLASS (mode
) == MODE_INT
25534 && GET_MODE_SIZE (mode
) < 4)
25540 /* AAPCS based ABIs use short enums by default. */
25543 arm_default_short_enums (void)
25545 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
25549 /* AAPCS requires that anonymous bitfields affect structure alignment. */
25552 arm_align_anon_bitfield (void)
25554 return TARGET_AAPCS_BASED
;
25558 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
25561 arm_cxx_guard_type (void)
25563 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
25566 /* Return non-zero iff the consumer (a multiply-accumulate or a
25567 multiple-subtract instruction) has an accumulator dependency on the
25568 result of the producer and no other dependency on that result. It
25569 does not check if the producer is multiply-accumulate instruction. */
25571 arm_mac_accumulator_is_result (rtx producer
, rtx consumer
)
25576 producer
= PATTERN (producer
);
25577 consumer
= PATTERN (consumer
);
25579 if (GET_CODE (producer
) == COND_EXEC
)
25580 producer
= COND_EXEC_CODE (producer
);
25581 if (GET_CODE (consumer
) == COND_EXEC
)
25582 consumer
= COND_EXEC_CODE (consumer
);
25584 if (GET_CODE (producer
) != SET
)
25587 result
= XEXP (producer
, 0);
25589 if (GET_CODE (consumer
) != SET
)
25592 /* Check that the consumer is of the form
25593 (set (...) (plus (mult ...) (...)))
25595 (set (...) (minus (...) (mult ...))). */
25596 if (GET_CODE (XEXP (consumer
, 1)) == PLUS
)
25598 if (GET_CODE (XEXP (XEXP (consumer
, 1), 0)) != MULT
)
25601 op0
= XEXP (XEXP (XEXP (consumer
, 1), 0), 0);
25602 op1
= XEXP (XEXP (XEXP (consumer
, 1), 0), 1);
25603 acc
= XEXP (XEXP (consumer
, 1), 1);
25605 else if (GET_CODE (XEXP (consumer
, 1)) == MINUS
)
25607 if (GET_CODE (XEXP (XEXP (consumer
, 1), 1)) != MULT
)
25610 op0
= XEXP (XEXP (XEXP (consumer
, 1), 1), 0);
25611 op1
= XEXP (XEXP (XEXP (consumer
, 1), 1), 1);
25612 acc
= XEXP (XEXP (consumer
, 1), 0);
25617 return (reg_overlap_mentioned_p (result
, acc
)
25618 && !reg_overlap_mentioned_p (result
, op0
)
25619 && !reg_overlap_mentioned_p (result
, op1
));
25622 /* Return non-zero if the consumer (a multiply-accumulate instruction)
25623 has an accumulator dependency on the result of the producer (a
25624 multiplication instruction) and no other dependency on that result. */
25626 arm_mac_accumulator_is_mul_result (rtx producer
, rtx consumer
)
25628 rtx mul
= PATTERN (producer
);
25629 rtx mac
= PATTERN (consumer
);
25631 rtx mac_op0
, mac_op1
, mac_acc
;
25633 if (GET_CODE (mul
) == COND_EXEC
)
25634 mul
= COND_EXEC_CODE (mul
);
25635 if (GET_CODE (mac
) == COND_EXEC
)
25636 mac
= COND_EXEC_CODE (mac
);
25638 /* Check that mul is of the form (set (...) (mult ...))
25639 and mla is of the form (set (...) (plus (mult ...) (...))). */
25640 if ((GET_CODE (mul
) != SET
|| GET_CODE (XEXP (mul
, 1)) != MULT
)
25641 || (GET_CODE (mac
) != SET
|| GET_CODE (XEXP (mac
, 1)) != PLUS
25642 || GET_CODE (XEXP (XEXP (mac
, 1), 0)) != MULT
))
25645 mul_result
= XEXP (mul
, 0);
25646 mac_op0
= XEXP (XEXP (XEXP (mac
, 1), 0), 0);
25647 mac_op1
= XEXP (XEXP (XEXP (mac
, 1), 0), 1);
25648 mac_acc
= XEXP (XEXP (mac
, 1), 1);
25650 return (reg_overlap_mentioned_p (mul_result
, mac_acc
)
25651 && !reg_overlap_mentioned_p (mul_result
, mac_op0
)
25652 && !reg_overlap_mentioned_p (mul_result
, mac_op1
));
25656 /* The EABI says test the least significant bit of a guard variable. */
25659 arm_cxx_guard_mask_bit (void)
25661 return TARGET_AAPCS_BASED
;
25665 /* The EABI specifies that all array cookies are 8 bytes long. */
25668 arm_get_cookie_size (tree type
)
25672 if (!TARGET_AAPCS_BASED
)
25673 return default_cxx_get_cookie_size (type
);
25675 size
= build_int_cst (sizetype
, 8);
25680 /* The EABI says that array cookies should also contain the element size. */
25683 arm_cookie_has_size (void)
25685 return TARGET_AAPCS_BASED
;
25689 /* The EABI says constructors and destructors should return a pointer to
25690 the object constructed/destroyed. */
25693 arm_cxx_cdtor_returns_this (void)
25695 return TARGET_AAPCS_BASED
;
25698 /* The EABI says that an inline function may never be the key
25702 arm_cxx_key_method_may_be_inline (void)
25704 return !TARGET_AAPCS_BASED
;
25708 arm_cxx_determine_class_data_visibility (tree decl
)
25710 if (!TARGET_AAPCS_BASED
25711 || !TARGET_DLLIMPORT_DECL_ATTRIBUTES
)
25714 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
25715 is exported. However, on systems without dynamic vague linkage,
25716 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
25717 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
25718 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
25720 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
25721 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
25725 arm_cxx_class_data_always_comdat (void)
25727 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
25728 vague linkage if the class has no key function. */
25729 return !TARGET_AAPCS_BASED
;
25733 /* The EABI says __aeabi_atexit should be used to register static
25737 arm_cxx_use_aeabi_atexit (void)
25739 return TARGET_AAPCS_BASED
;
25744 arm_set_return_address (rtx source
, rtx scratch
)
25746 arm_stack_offsets
*offsets
;
25747 HOST_WIDE_INT delta
;
25749 unsigned long saved_regs
;
25751 offsets
= arm_get_frame_offsets ();
25752 saved_regs
= offsets
->saved_regs_mask
;
25754 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
25755 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
25758 if (frame_pointer_needed
)
25759 addr
= plus_constant (Pmode
, hard_frame_pointer_rtx
, -4);
25762 /* LR will be the first saved register. */
25763 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
25768 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
25769 GEN_INT (delta
& ~4095)));
25774 addr
= stack_pointer_rtx
;
25776 addr
= plus_constant (Pmode
, addr
, delta
);
25778 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
25784 thumb_set_return_address (rtx source
, rtx scratch
)
25786 arm_stack_offsets
*offsets
;
25787 HOST_WIDE_INT delta
;
25788 HOST_WIDE_INT limit
;
25791 unsigned long mask
;
25795 offsets
= arm_get_frame_offsets ();
25796 mask
= offsets
->saved_regs_mask
;
25797 if (mask
& (1 << LR_REGNUM
))
25800 /* Find the saved regs. */
25801 if (frame_pointer_needed
)
25803 delta
= offsets
->soft_frame
- offsets
->saved_args
;
25804 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
25810 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
25813 /* Allow for the stack frame. */
25814 if (TARGET_THUMB1
&& TARGET_BACKTRACE
)
25816 /* The link register is always the first saved register. */
25819 /* Construct the address. */
25820 addr
= gen_rtx_REG (SImode
, reg
);
25823 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
25824 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
25828 addr
= plus_constant (Pmode
, addr
, delta
);
25830 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
25833 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
25836 /* Implements target hook vector_mode_supported_p. */
25838 arm_vector_mode_supported_p (enum machine_mode mode
)
25840 /* Neon also supports V2SImode, etc. listed in the clause below. */
25841 if (TARGET_NEON
&& (mode
== V2SFmode
|| mode
== V4SImode
|| mode
== V8HImode
25842 || mode
== V4HFmode
|| mode
== V16QImode
|| mode
== V4SFmode
|| mode
== V2DImode
))
25845 if ((TARGET_NEON
|| TARGET_IWMMXT
)
25846 && ((mode
== V2SImode
)
25847 || (mode
== V4HImode
)
25848 || (mode
== V8QImode
)))
25851 if (TARGET_INT_SIMD
&& (mode
== V4UQQmode
|| mode
== V4QQmode
25852 || mode
== V2UHQmode
|| mode
== V2HQmode
|| mode
== V2UHAmode
25853 || mode
== V2HAmode
))
25859 /* Implements target hook array_mode_supported_p. */
25862 arm_array_mode_supported_p (enum machine_mode mode
,
25863 unsigned HOST_WIDE_INT nelems
)
25866 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
))
25867 && (nelems
>= 2 && nelems
<= 4))
25873 /* Use the option -mvectorize-with-neon-double to override the use of quardword
25874 registers when autovectorizing for Neon, at least until multiple vector
25875 widths are supported properly by the middle-end. */
25877 static enum machine_mode
25878 arm_preferred_simd_mode (enum machine_mode mode
)
25884 return TARGET_NEON_VECTORIZE_DOUBLE
? V2SFmode
: V4SFmode
;
25886 return TARGET_NEON_VECTORIZE_DOUBLE
? V2SImode
: V4SImode
;
25888 return TARGET_NEON_VECTORIZE_DOUBLE
? V4HImode
: V8HImode
;
25890 return TARGET_NEON_VECTORIZE_DOUBLE
? V8QImode
: V16QImode
;
25892 if (!TARGET_NEON_VECTORIZE_DOUBLE
)
25899 if (TARGET_REALLY_IWMMXT
)
25915 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
25917 We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
25918 using r0-r4 for function arguments, r7 for the stack frame and don't have
25919 enough left over to do doubleword arithmetic. For Thumb-2 all the
25920 potentially problematic instructions accept high registers so this is not
25921 necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
25922 that require many low registers. */
25924 arm_class_likely_spilled_p (reg_class_t rclass
)
25926 if ((TARGET_THUMB1
&& rclass
== LO_REGS
)
25927 || rclass
== CC_REG
)
25933 /* Implements target hook small_register_classes_for_mode_p. */
25935 arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED
)
25937 return TARGET_THUMB1
;
25940 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
25941 ARM insns and therefore guarantee that the shift count is modulo 256.
25942 DImode shifts (those implemented by lib1funcs.S or by optabs.c)
25943 guarantee no particular behavior for out-of-range counts. */
25945 static unsigned HOST_WIDE_INT
25946 arm_shift_truncation_mask (enum machine_mode mode
)
25948 return mode
== SImode
? 255 : 0;
25952 /* Map internal gcc register numbers to DWARF2 register numbers. */
25955 arm_dbx_register_number (unsigned int regno
)
25960 if (IS_VFP_REGNUM (regno
))
25962 /* See comment in arm_dwarf_register_span. */
25963 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
25964 return 64 + regno
- FIRST_VFP_REGNUM
;
25966 return 256 + (regno
- FIRST_VFP_REGNUM
) / 2;
25969 if (IS_IWMMXT_GR_REGNUM (regno
))
25970 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
25972 if (IS_IWMMXT_REGNUM (regno
))
25973 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
25975 gcc_unreachable ();
25978 /* Dwarf models VFPv3 registers as 32 64-bit registers.
25979 GCC models tham as 64 32-bit registers, so we need to describe this to
25980 the DWARF generation code. Other registers can use the default. */
25982 arm_dwarf_register_span (rtx rtl
)
25989 regno
= REGNO (rtl
);
25990 if (!IS_VFP_REGNUM (regno
))
25993 /* XXX FIXME: The EABI defines two VFP register ranges:
25994 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
25996 The recommended encoding for S0-S31 is a DW_OP_bit_piece of the
25997 corresponding D register. Until GDB supports this, we shall use the
25998 legacy encodings. We also use these encodings for D0-D15 for
25999 compatibility with older debuggers. */
26000 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
26003 nregs
= GET_MODE_SIZE (GET_MODE (rtl
)) / 8;
26004 p
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
26005 for (i
= 0; i
< nregs
; i
++)
26006 XVECEXP (p
, 0, i
) = gen_rtx_REG (DImode
, regno
+ i
);
26011 #if ARM_UNWIND_INFO
26012 /* Emit unwind directives for a store-multiple instruction or stack pointer
26013 push during alignment.
26014 These should only ever be generated by the function prologue code, so
26015 expect them to have a particular form. */
26018 arm_unwind_emit_sequence (FILE * asm_out_file
, rtx p
)
26021 HOST_WIDE_INT offset
;
26022 HOST_WIDE_INT nregs
;
26028 e
= XVECEXP (p
, 0, 0);
26029 if (GET_CODE (e
) != SET
)
26032 /* First insn will adjust the stack pointer. */
26033 if (GET_CODE (e
) != SET
26034 || !REG_P (XEXP (e
, 0))
26035 || REGNO (XEXP (e
, 0)) != SP_REGNUM
26036 || GET_CODE (XEXP (e
, 1)) != PLUS
)
26039 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
26040 nregs
= XVECLEN (p
, 0) - 1;
26042 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
26045 /* The function prologue may also push pc, but not annotate it as it is
26046 never restored. We turn this into a stack pointer adjustment. */
26047 if (nregs
* 4 == offset
- 4)
26049 fprintf (asm_out_file
, "\t.pad #4\n");
26053 fprintf (asm_out_file
, "\t.save {");
26055 else if (IS_VFP_REGNUM (reg
))
26058 fprintf (asm_out_file
, "\t.vsave {");
26061 /* Unknown register type. */
26064 /* If the stack increment doesn't match the size of the saved registers,
26065 something has gone horribly wrong. */
26066 if (offset
!= nregs
* reg_size
)
26071 /* The remaining insns will describe the stores. */
26072 for (i
= 1; i
<= nregs
; i
++)
26074 /* Expect (set (mem <addr>) (reg)).
26075 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
26076 e
= XVECEXP (p
, 0, i
);
26077 if (GET_CODE (e
) != SET
26078 || !MEM_P (XEXP (e
, 0))
26079 || !REG_P (XEXP (e
, 1)))
26082 reg
= REGNO (XEXP (e
, 1));
26087 fprintf (asm_out_file
, ", ");
26088 /* We can't use %r for vfp because we need to use the
26089 double precision register names. */
26090 if (IS_VFP_REGNUM (reg
))
26091 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
26093 asm_fprintf (asm_out_file
, "%r", reg
);
26095 #ifdef ENABLE_CHECKING
26096 /* Check that the addresses are consecutive. */
26097 e
= XEXP (XEXP (e
, 0), 0);
26098 if (GET_CODE (e
) == PLUS
)
26100 offset
+= reg_size
;
26101 if (!REG_P (XEXP (e
, 0))
26102 || REGNO (XEXP (e
, 0)) != SP_REGNUM
26103 || !CONST_INT_P (XEXP (e
, 1))
26104 || offset
!= INTVAL (XEXP (e
, 1)))
26109 || REGNO (e
) != SP_REGNUM
)
26113 fprintf (asm_out_file
, "}\n");
26116 /* Emit unwind directives for a SET. */
26119 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
26127 switch (GET_CODE (e0
))
26130 /* Pushing a single register. */
26131 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
26132 || !REG_P (XEXP (XEXP (e0
, 0), 0))
26133 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
26136 asm_fprintf (asm_out_file
, "\t.save ");
26137 if (IS_VFP_REGNUM (REGNO (e1
)))
26138 asm_fprintf(asm_out_file
, "{d%d}\n",
26139 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
26141 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
26145 if (REGNO (e0
) == SP_REGNUM
)
26147 /* A stack increment. */
26148 if (GET_CODE (e1
) != PLUS
26149 || !REG_P (XEXP (e1
, 0))
26150 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
26151 || !CONST_INT_P (XEXP (e1
, 1)))
26154 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
26155 -INTVAL (XEXP (e1
, 1)));
26157 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
26159 HOST_WIDE_INT offset
;
26161 if (GET_CODE (e1
) == PLUS
)
26163 if (!REG_P (XEXP (e1
, 0))
26164 || !CONST_INT_P (XEXP (e1
, 1)))
26166 reg
= REGNO (XEXP (e1
, 0));
26167 offset
= INTVAL (XEXP (e1
, 1));
26168 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
26169 HARD_FRAME_POINTER_REGNUM
, reg
,
26172 else if (REG_P (e1
))
26175 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
26176 HARD_FRAME_POINTER_REGNUM
, reg
);
26181 else if (REG_P (e1
) && REGNO (e1
) == SP_REGNUM
)
26183 /* Move from sp to reg. */
26184 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
26186 else if (GET_CODE (e1
) == PLUS
26187 && REG_P (XEXP (e1
, 0))
26188 && REGNO (XEXP (e1
, 0)) == SP_REGNUM
26189 && CONST_INT_P (XEXP (e1
, 1)))
26191 /* Set reg to offset from sp. */
26192 asm_fprintf (asm_out_file
, "\t.movsp %r, #%d\n",
26193 REGNO (e0
), (int)INTVAL(XEXP (e1
, 1)));
26205 /* Emit unwind directives for the given insn. */
26208 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
26211 bool handled_one
= false;
26213 if (arm_except_unwind_info (&global_options
) != UI_TARGET
)
26216 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
26217 && (TREE_NOTHROW (current_function_decl
)
26218 || crtl
->all_throwers_are_sibcalls
))
26221 if (NOTE_P (insn
) || !RTX_FRAME_RELATED_P (insn
))
26224 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
26226 pat
= XEXP (note
, 0);
26227 switch (REG_NOTE_KIND (note
))
26229 case REG_FRAME_RELATED_EXPR
:
26232 case REG_CFA_REGISTER
:
26235 pat
= PATTERN (insn
);
26236 if (GET_CODE (pat
) == PARALLEL
)
26237 pat
= XVECEXP (pat
, 0, 0);
26240 /* Only emitted for IS_STACKALIGN re-alignment. */
26245 src
= SET_SRC (pat
);
26246 dest
= SET_DEST (pat
);
26248 gcc_assert (src
== stack_pointer_rtx
);
26249 reg
= REGNO (dest
);
26250 asm_fprintf (asm_out_file
, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
26253 handled_one
= true;
26256 /* The INSN is generated in epilogue. It is set as RTX_FRAME_RELATED_P
26257 to get correct dwarf information for shrink-wrap. We should not
26258 emit unwind information for it because these are used either for
26259 pretend arguments or notes to adjust sp and restore registers from
26261 case REG_CFA_ADJUST_CFA
:
26262 case REG_CFA_RESTORE
:
26265 case REG_CFA_DEF_CFA
:
26266 case REG_CFA_EXPRESSION
:
26267 case REG_CFA_OFFSET
:
26268 /* ??? Only handling here what we actually emit. */
26269 gcc_unreachable ();
26277 pat
= PATTERN (insn
);
26280 switch (GET_CODE (pat
))
26283 arm_unwind_emit_set (asm_out_file
, pat
);
26287 /* Store multiple. */
26288 arm_unwind_emit_sequence (asm_out_file
, pat
);
26297 /* Output a reference from a function exception table to the type_info
26298 object X. The EABI specifies that the symbol should be relocated by
26299 an R_ARM_TARGET2 relocation. */
26302 arm_output_ttype (rtx x
)
26304 fputs ("\t.word\t", asm_out_file
);
26305 output_addr_const (asm_out_file
, x
);
26306 /* Use special relocations for symbol references. */
26307 if (!CONST_INT_P (x
))
26308 fputs ("(TARGET2)", asm_out_file
);
26309 fputc ('\n', asm_out_file
);
26314 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
26317 arm_asm_emit_except_personality (rtx personality
)
26319 fputs ("\t.personality\t", asm_out_file
);
26320 output_addr_const (asm_out_file
, personality
);
26321 fputc ('\n', asm_out_file
);
26324 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
26327 arm_asm_init_sections (void)
26329 exception_section
= get_unnamed_section (0, output_section_asm_op
,
26332 #endif /* ARM_UNWIND_INFO */
26334 /* Output unwind directives for the start/end of a function. */
26337 arm_output_fn_unwind (FILE * f
, bool prologue
)
26339 if (arm_except_unwind_info (&global_options
) != UI_TARGET
)
26343 fputs ("\t.fnstart\n", f
);
26346 /* If this function will never be unwound, then mark it as such.
26347 The came condition is used in arm_unwind_emit to suppress
26348 the frame annotations. */
26349 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
26350 && (TREE_NOTHROW (current_function_decl
)
26351 || crtl
->all_throwers_are_sibcalls
))
26352 fputs("\t.cantunwind\n", f
);
26354 fputs ("\t.fnend\n", f
);
26359 arm_emit_tls_decoration (FILE *fp
, rtx x
)
26361 enum tls_reloc reloc
;
26364 val
= XVECEXP (x
, 0, 0);
26365 reloc
= (enum tls_reloc
) INTVAL (XVECEXP (x
, 0, 1));
26367 output_addr_const (fp
, val
);
26372 fputs ("(tlsgd)", fp
);
26375 fputs ("(tlsldm)", fp
);
26378 fputs ("(tlsldo)", fp
);
26381 fputs ("(gottpoff)", fp
);
26384 fputs ("(tpoff)", fp
);
26387 fputs ("(tlsdesc)", fp
);
26390 gcc_unreachable ();
26399 fputs (" + (. - ", fp
);
26400 output_addr_const (fp
, XVECEXP (x
, 0, 2));
26401 /* For DESCSEQ the 3rd operand encodes thumbness, and is added */
26402 fputs (reloc
== TLS_DESCSEQ
? " + " : " - ", fp
);
26403 output_addr_const (fp
, XVECEXP (x
, 0, 3));
26413 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
26416 arm_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
26418 gcc_assert (size
== 4);
26419 fputs ("\t.word\t", file
);
26420 output_addr_const (file
, x
);
26421 fputs ("(tlsldo)", file
);
26424 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
26427 arm_output_addr_const_extra (FILE *fp
, rtx x
)
26429 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
26430 return arm_emit_tls_decoration (fp
, x
);
26431 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
26434 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
26436 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
26437 assemble_name_raw (fp
, label
);
26441 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOTSYM_OFF
)
26443 assemble_name (fp
, "_GLOBAL_OFFSET_TABLE_");
26447 output_addr_const (fp
, XVECEXP (x
, 0, 0));
26451 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_SYMBOL_OFFSET
)
26453 output_addr_const (fp
, XVECEXP (x
, 0, 0));
26457 output_addr_const (fp
, XVECEXP (x
, 0, 1));
26461 else if (GET_CODE (x
) == CONST_VECTOR
)
26462 return arm_emit_vector_const (fp
, x
);
26467 /* Output assembly for a shift instruction.
26468 SET_FLAGS determines how the instruction modifies the condition codes.
26469 0 - Do not set condition codes.
26470 1 - Set condition codes.
26471 2 - Use smallest instruction. */
26473 arm_output_shift(rtx
* operands
, int set_flags
)
26476 static const char flag_chars
[3] = {'?', '.', '!'};
26481 c
= flag_chars
[set_flags
];
26482 if (TARGET_UNIFIED_ASM
)
26484 shift
= shift_op(operands
[3], &val
);
26488 operands
[2] = GEN_INT(val
);
26489 sprintf (pattern
, "%s%%%c\t%%0, %%1, %%2", shift
, c
);
26492 sprintf (pattern
, "mov%%%c\t%%0, %%1", c
);
26495 sprintf (pattern
, "mov%%%c\t%%0, %%1%%S3", c
);
26496 output_asm_insn (pattern
, operands
);
26500 /* Output assembly for a WMMX immediate shift instruction. */
26502 arm_output_iwmmxt_shift_immediate (const char *insn_name
, rtx
*operands
, bool wror_or_wsra
)
26504 int shift
= INTVAL (operands
[2]);
26506 enum machine_mode opmode
= GET_MODE (operands
[0]);
26508 gcc_assert (shift
>= 0);
26510 /* If the shift value in the register versions is > 63 (for D qualifier),
26511 31 (for W qualifier) or 15 (for H qualifier). */
26512 if (((opmode
== V4HImode
) && (shift
> 15))
26513 || ((opmode
== V2SImode
) && (shift
> 31))
26514 || ((opmode
== DImode
) && (shift
> 63)))
26518 sprintf (templ
, "%s\t%%0, %%1, #%d", insn_name
, 32);
26519 output_asm_insn (templ
, operands
);
26520 if (opmode
== DImode
)
26522 sprintf (templ
, "%s\t%%0, %%0, #%d", insn_name
, 32);
26523 output_asm_insn (templ
, operands
);
26528 /* The destination register will contain all zeros. */
26529 sprintf (templ
, "wzero\t%%0");
26530 output_asm_insn (templ
, operands
);
26535 if ((opmode
== DImode
) && (shift
> 32))
26537 sprintf (templ
, "%s\t%%0, %%1, #%d", insn_name
, 32);
26538 output_asm_insn (templ
, operands
);
26539 sprintf (templ
, "%s\t%%0, %%0, #%d", insn_name
, shift
- 32);
26540 output_asm_insn (templ
, operands
);
26544 sprintf (templ
, "%s\t%%0, %%1, #%d", insn_name
, shift
);
26545 output_asm_insn (templ
, operands
);
26550 /* Output assembly for a WMMX tinsr instruction. */
26552 arm_output_iwmmxt_tinsr (rtx
*operands
)
26554 int mask
= INTVAL (operands
[3]);
26557 int units
= mode_nunits
[GET_MODE (operands
[0])];
26558 gcc_assert ((mask
& (mask
- 1)) == 0);
26559 for (i
= 0; i
< units
; ++i
)
26561 if ((mask
& 0x01) == 1)
26567 gcc_assert (i
< units
);
26569 switch (GET_MODE (operands
[0]))
26572 sprintf (templ
, "tinsrb%%?\t%%0, %%2, #%d", i
);
26575 sprintf (templ
, "tinsrh%%?\t%%0, %%2, #%d", i
);
26578 sprintf (templ
, "tinsrw%%?\t%%0, %%2, #%d", i
);
26581 gcc_unreachable ();
26584 output_asm_insn (templ
, operands
);
26589 /* Output a Thumb-1 casesi dispatch sequence. */
26591 thumb1_output_casesi (rtx
*operands
)
26593 rtx diff_vec
= PATTERN (next_active_insn (operands
[0]));
26595 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
26597 switch (GET_MODE(diff_vec
))
26600 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
26601 "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi");
26603 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
26604 "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi");
26606 return "bl\t%___gnu_thumb1_case_si";
26608 gcc_unreachable ();
26612 /* Output a Thumb-2 casesi instruction. */
26614 thumb2_output_casesi (rtx
*operands
)
26616 rtx diff_vec
= PATTERN (next_active_insn (operands
[2]));
26618 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
26620 output_asm_insn ("cmp\t%0, %1", operands
);
26621 output_asm_insn ("bhi\t%l3", operands
);
26622 switch (GET_MODE(diff_vec
))
26625 return "tbb\t[%|pc, %0]";
26627 return "tbh\t[%|pc, %0, lsl #1]";
26631 output_asm_insn ("adr\t%4, %l2", operands
);
26632 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands
);
26633 output_asm_insn ("add\t%4, %4, %5", operands
);
26638 output_asm_insn ("adr\t%4, %l2", operands
);
26639 return "ldr\t%|pc, [%4, %0, lsl #2]";
26642 gcc_unreachable ();
26646 /* Most ARM cores are single issue, but some newer ones can dual issue.
26647 The scheduler descriptions rely on this being correct. */
26649 arm_issue_rate (void)
26674 /* A table and a function to perform ARM-specific name mangling for
26675 NEON vector types in order to conform to the AAPCS (see "Procedure
26676 Call Standard for the ARM Architecture", Appendix A). To qualify
26677 for emission with the mangled names defined in that document, a
26678 vector type must not only be of the correct mode but also be
26679 composed of NEON vector element types (e.g. __builtin_neon_qi). */
26682 enum machine_mode mode
;
26683 const char *element_type_name
;
26684 const char *aapcs_name
;
26685 } arm_mangle_map_entry
;
26687 static arm_mangle_map_entry arm_mangle_map
[] = {
26688 /* 64-bit containerized types. */
26689 { V8QImode
, "__builtin_neon_qi", "15__simd64_int8_t" },
26690 { V8QImode
, "__builtin_neon_uqi", "16__simd64_uint8_t" },
26691 { V4HImode
, "__builtin_neon_hi", "16__simd64_int16_t" },
26692 { V4HImode
, "__builtin_neon_uhi", "17__simd64_uint16_t" },
26693 { V4HFmode
, "__builtin_neon_hf", "18__simd64_float16_t" },
26694 { V2SImode
, "__builtin_neon_si", "16__simd64_int32_t" },
26695 { V2SImode
, "__builtin_neon_usi", "17__simd64_uint32_t" },
26696 { V2SFmode
, "__builtin_neon_sf", "18__simd64_float32_t" },
26697 { V8QImode
, "__builtin_neon_poly8", "16__simd64_poly8_t" },
26698 { V4HImode
, "__builtin_neon_poly16", "17__simd64_poly16_t" },
26699 /* 128-bit containerized types. */
26700 { V16QImode
, "__builtin_neon_qi", "16__simd128_int8_t" },
26701 { V16QImode
, "__builtin_neon_uqi", "17__simd128_uint8_t" },
26702 { V8HImode
, "__builtin_neon_hi", "17__simd128_int16_t" },
26703 { V8HImode
, "__builtin_neon_uhi", "18__simd128_uint16_t" },
26704 { V4SImode
, "__builtin_neon_si", "17__simd128_int32_t" },
26705 { V4SImode
, "__builtin_neon_usi", "18__simd128_uint32_t" },
26706 { V4SFmode
, "__builtin_neon_sf", "19__simd128_float32_t" },
26707 { V16QImode
, "__builtin_neon_poly8", "17__simd128_poly8_t" },
26708 { V8HImode
, "__builtin_neon_poly16", "18__simd128_poly16_t" },
26709 { VOIDmode
, NULL
, NULL
}
26713 arm_mangle_type (const_tree type
)
26715 arm_mangle_map_entry
*pos
= arm_mangle_map
;
26717 /* The ARM ABI documents (10th October 2008) say that "__va_list"
26718 has to be managled as if it is in the "std" namespace. */
26719 if (TARGET_AAPCS_BASED
26720 && lang_hooks
.types_compatible_p (CONST_CAST_TREE (type
), va_list_type
))
26721 return "St9__va_list";
26723 /* Half-precision float. */
26724 if (TREE_CODE (type
) == REAL_TYPE
&& TYPE_PRECISION (type
) == 16)
26727 if (TREE_CODE (type
) != VECTOR_TYPE
)
26730 /* Check the mode of the vector type, and the name of the vector
26731 element type, against the table. */
26732 while (pos
->mode
!= VOIDmode
)
26734 tree elt_type
= TREE_TYPE (type
);
26736 if (pos
->mode
== TYPE_MODE (type
)
26737 && TREE_CODE (TYPE_NAME (elt_type
)) == TYPE_DECL
26738 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type
))),
26739 pos
->element_type_name
))
26740 return pos
->aapcs_name
;
26745 /* Use the default mangling for unrecognized (possibly user-defined)
26750 /* Order of allocation of core registers for Thumb: this allocation is
26751 written over the corresponding initial entries of the array
26752 initialized with REG_ALLOC_ORDER. We allocate all low registers
26753 first. Saving and restoring a low register is usually cheaper than
26754 using a call-clobbered high register. */
26756 static const int thumb_core_reg_alloc_order
[] =
26758 3, 2, 1, 0, 4, 5, 6, 7,
26759 14, 12, 8, 9, 10, 11
26762 /* Adjust register allocation order when compiling for Thumb. */
26765 arm_order_regs_for_local_alloc (void)
26767 const int arm_reg_alloc_order
[] = REG_ALLOC_ORDER
;
26768 memcpy(reg_alloc_order
, arm_reg_alloc_order
, sizeof (reg_alloc_order
));
26770 memcpy (reg_alloc_order
, thumb_core_reg_alloc_order
,
26771 sizeof (thumb_core_reg_alloc_order
));
26774 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
26777 arm_frame_pointer_required (void)
26779 return (cfun
->has_nonlocal_label
26780 || SUBTARGET_FRAME_POINTER_REQUIRED
26781 || (TARGET_ARM
&& TARGET_APCS_FRAME
&& ! leaf_function_p ()));
26784 /* Only thumb1 can't support conditional execution, so return true if
26785 the target is not thumb1. */
26787 arm_have_conditional_execution (void)
26789 return !TARGET_THUMB1
;
26793 arm_builtin_vectorized_function (tree fndecl
, tree type_out
, tree type_in
)
26795 enum machine_mode in_mode
, out_mode
;
26798 if (TREE_CODE (type_out
) != VECTOR_TYPE
26799 || TREE_CODE (type_in
) != VECTOR_TYPE
26800 || !(TARGET_NEON
&& TARGET_FPU_ARMV8
&& flag_unsafe_math_optimizations
))
26803 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
26804 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
26805 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
26806 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
26808 /* ARM_CHECK_BUILTIN_MODE and ARM_FIND_VRINT_VARIANT are used to find the
26809 decl of the vectorized builtin for the appropriate vector mode.
26810 NULL_TREE is returned if no such builtin is available. */
26811 #undef ARM_CHECK_BUILTIN_MODE
26812 #define ARM_CHECK_BUILTIN_MODE(C) \
26813 (out_mode == SFmode && out_n == C \
26814 && in_mode == SFmode && in_n == C)
26816 #undef ARM_FIND_VRINT_VARIANT
26817 #define ARM_FIND_VRINT_VARIANT(N) \
26818 (ARM_CHECK_BUILTIN_MODE (2) \
26819 ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v2sf, false) \
26820 : (ARM_CHECK_BUILTIN_MODE (4) \
26821 ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v4sf, false) \
26824 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
26826 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
26829 case BUILT_IN_FLOORF
:
26830 return ARM_FIND_VRINT_VARIANT (vrintm
);
26831 case BUILT_IN_CEILF
:
26832 return ARM_FIND_VRINT_VARIANT (vrintp
);
26833 case BUILT_IN_TRUNCF
:
26834 return ARM_FIND_VRINT_VARIANT (vrintz
);
26835 case BUILT_IN_ROUNDF
:
26836 return ARM_FIND_VRINT_VARIANT (vrinta
);
26843 #undef ARM_CHECK_BUILTIN_MODE
26844 #undef ARM_FIND_VRINT_VARIANT
26846 /* The AAPCS sets the maximum alignment of a vector to 64 bits. */
26847 static HOST_WIDE_INT
26848 arm_vector_alignment (const_tree type
)
26850 HOST_WIDE_INT align
= tree_low_cst (TYPE_SIZE (type
), 0);
26852 if (TARGET_AAPCS_BASED
)
26853 align
= MIN (align
, 64);
26858 static unsigned int
26859 arm_autovectorize_vector_sizes (void)
26861 return TARGET_NEON_VECTORIZE_DOUBLE
? 0 : (16 | 8);
26865 arm_vector_alignment_reachable (const_tree type
, bool is_packed
)
26867 /* Vectors which aren't in packed structures will not be less aligned than
26868 the natural alignment of their element type, so this is safe. */
26869 if (TARGET_NEON
&& !BYTES_BIG_ENDIAN
)
26872 return default_builtin_vector_alignment_reachable (type
, is_packed
);
26876 arm_builtin_support_vector_misalignment (enum machine_mode mode
,
26877 const_tree type
, int misalignment
,
26880 if (TARGET_NEON
&& !BYTES_BIG_ENDIAN
)
26882 HOST_WIDE_INT align
= TYPE_ALIGN_UNIT (type
);
26887 /* If the misalignment is unknown, we should be able to handle the access
26888 so long as it is not to a member of a packed data structure. */
26889 if (misalignment
== -1)
26892 /* Return true if the misalignment is a multiple of the natural alignment
26893 of the vector's element type. This is probably always going to be
26894 true in practice, since we've already established that this isn't a
26896 return ((misalignment
% align
) == 0);
26899 return default_builtin_support_vector_misalignment (mode
, type
, misalignment
,
26904 arm_conditional_register_usage (void)
26908 if (TARGET_THUMB1
&& optimize_size
)
26910 /* When optimizing for size on Thumb-1, it's better not
26911 to use the HI regs, because of the overhead of
26913 for (regno
= FIRST_HI_REGNUM
;
26914 regno
<= LAST_HI_REGNUM
; ++regno
)
26915 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
26918 /* The link register can be clobbered by any branch insn,
26919 but we have no way to track that at present, so mark
26920 it as unavailable. */
26922 fixed_regs
[LR_REGNUM
] = call_used_regs
[LR_REGNUM
] = 1;
26924 if (TARGET_32BIT
&& TARGET_HARD_FLOAT
&& TARGET_VFP
)
26926 /* VFPv3 registers are disabled when earlier VFP
26927 versions are selected due to the definition of
26928 LAST_VFP_REGNUM. */
26929 for (regno
= FIRST_VFP_REGNUM
;
26930 regno
<= LAST_VFP_REGNUM
; ++ regno
)
26932 fixed_regs
[regno
] = 0;
26933 call_used_regs
[regno
] = regno
< FIRST_VFP_REGNUM
+ 16
26934 || regno
>= FIRST_VFP_REGNUM
+ 32;
26938 if (TARGET_REALLY_IWMMXT
)
26940 regno
= FIRST_IWMMXT_GR_REGNUM
;
26941 /* The 2002/10/09 revision of the XScale ABI has wCG0
26942 and wCG1 as call-preserved registers. The 2002/11/21
26943 revision changed this so that all wCG registers are
26944 scratch registers. */
26945 for (regno
= FIRST_IWMMXT_GR_REGNUM
;
26946 regno
<= LAST_IWMMXT_GR_REGNUM
; ++ regno
)
26947 fixed_regs
[regno
] = 0;
26948 /* The XScale ABI has wR0 - wR9 as scratch registers,
26949 the rest as call-preserved registers. */
26950 for (regno
= FIRST_IWMMXT_REGNUM
;
26951 regno
<= LAST_IWMMXT_REGNUM
; ++ regno
)
26953 fixed_regs
[regno
] = 0;
26954 call_used_regs
[regno
] = regno
< FIRST_IWMMXT_REGNUM
+ 10;
26958 if ((unsigned) PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
26960 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
26961 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
26963 else if (TARGET_APCS_STACK
)
26965 fixed_regs
[10] = 1;
26966 call_used_regs
[10] = 1;
26968 /* -mcaller-super-interworking reserves r11 for calls to
26969 _interwork_r11_call_via_rN(). Making the register global
26970 is an easy way of ensuring that it remains valid for all
26972 if (TARGET_APCS_FRAME
|| TARGET_CALLER_INTERWORKING
26973 || TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
)
26975 fixed_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
26976 call_used_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
26977 if (TARGET_CALLER_INTERWORKING
)
26978 global_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
26980 SUBTARGET_CONDITIONAL_REGISTER_USAGE
26984 arm_preferred_rename_class (reg_class_t rclass
)
26986 /* Thumb-2 instructions using LO_REGS may be smaller than instructions
26987 using GENERIC_REGS. During register rename pass, we prefer LO_REGS,
26988 and code size can be reduced. */
26989 if (TARGET_THUMB2
&& rclass
== GENERAL_REGS
)
26995 /* Compute the atrribute "length" of insn "*push_multi".
26996 So this function MUST be kept in sync with that insn pattern. */
26998 arm_attr_length_push_multi(rtx parallel_op
, rtx first_op
)
27000 int i
, regno
, hi_reg
;
27001 int num_saves
= XVECLEN (parallel_op
, 0);
27011 regno
= REGNO (first_op
);
27012 hi_reg
= (REGNO_REG_CLASS (regno
) == HI_REGS
) && (regno
!= LR_REGNUM
);
27013 for (i
= 1; i
< num_saves
&& !hi_reg
; i
++)
27015 regno
= REGNO (XEXP (XVECEXP (parallel_op
, 0, i
), 0));
27016 hi_reg
|= (REGNO_REG_CLASS (regno
) == HI_REGS
) && (regno
!= LR_REGNUM
);
27024 /* Compute the number of instructions emitted by output_move_double. */
27026 arm_count_output_move_double_insns (rtx
*operands
)
27030 /* output_move_double may modify the operands array, so call it
27031 here on a copy of the array. */
27032 ops
[0] = operands
[0];
27033 ops
[1] = operands
[1];
27034 output_move_double (ops
, false, &count
);
27039 vfp3_const_double_for_fract_bits (rtx operand
)
27041 REAL_VALUE_TYPE r0
;
27043 if (!CONST_DOUBLE_P (operand
))
27046 REAL_VALUE_FROM_CONST_DOUBLE (r0
, operand
);
27047 if (exact_real_inverse (DFmode
, &r0
))
27049 if (exact_real_truncate (DFmode
, &r0
))
27051 HOST_WIDE_INT value
= real_to_integer (&r0
);
27052 value
= value
& 0xffffffff;
27053 if ((value
!= 0) && ( (value
& (value
- 1)) == 0))
27054 return int_log2 (value
);
27060 /* Emit a memory barrier around an atomic sequence according to MODEL. */
27063 arm_pre_atomic_barrier (enum memmodel model
)
27065 if (need_atomic_barrier_p (model
, true))
27066 emit_insn (gen_memory_barrier ());
27070 arm_post_atomic_barrier (enum memmodel model
)
27072 if (need_atomic_barrier_p (model
, false))
27073 emit_insn (gen_memory_barrier ());
27076 /* Emit the load-exclusive and store-exclusive instructions.
27077 Use acquire and release versions if necessary. */
27080 arm_emit_load_exclusive (enum machine_mode mode
, rtx rval
, rtx mem
, bool acq
)
27082 rtx (*gen
) (rtx
, rtx
);
27088 case QImode
: gen
= gen_arm_load_acquire_exclusiveqi
; break;
27089 case HImode
: gen
= gen_arm_load_acquire_exclusivehi
; break;
27090 case SImode
: gen
= gen_arm_load_acquire_exclusivesi
; break;
27091 case DImode
: gen
= gen_arm_load_acquire_exclusivedi
; break;
27093 gcc_unreachable ();
27100 case QImode
: gen
= gen_arm_load_exclusiveqi
; break;
27101 case HImode
: gen
= gen_arm_load_exclusivehi
; break;
27102 case SImode
: gen
= gen_arm_load_exclusivesi
; break;
27103 case DImode
: gen
= gen_arm_load_exclusivedi
; break;
27105 gcc_unreachable ();
27109 emit_insn (gen (rval
, mem
));
27113 arm_emit_store_exclusive (enum machine_mode mode
, rtx bval
, rtx rval
,
27116 rtx (*gen
) (rtx
, rtx
, rtx
);
27122 case QImode
: gen
= gen_arm_store_release_exclusiveqi
; break;
27123 case HImode
: gen
= gen_arm_store_release_exclusivehi
; break;
27124 case SImode
: gen
= gen_arm_store_release_exclusivesi
; break;
27125 case DImode
: gen
= gen_arm_store_release_exclusivedi
; break;
27127 gcc_unreachable ();
27134 case QImode
: gen
= gen_arm_store_exclusiveqi
; break;
27135 case HImode
: gen
= gen_arm_store_exclusivehi
; break;
27136 case SImode
: gen
= gen_arm_store_exclusivesi
; break;
27137 case DImode
: gen
= gen_arm_store_exclusivedi
; break;
27139 gcc_unreachable ();
27143 emit_insn (gen (bval
, rval
, mem
));
27146 /* Mark the previous jump instruction as unlikely. */
27149 emit_unlikely_jump (rtx insn
)
27151 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
27153 insn
= emit_jump_insn (insn
);
27154 add_reg_note (insn
, REG_BR_PROB
, very_unlikely
);
27157 /* Expand a compare and swap pattern. */
27160 arm_expand_compare_and_swap (rtx operands
[])
27162 rtx bval
, rval
, mem
, oldval
, newval
, is_weak
, mod_s
, mod_f
, x
;
27163 enum machine_mode mode
;
27164 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
27166 bval
= operands
[0];
27167 rval
= operands
[1];
27169 oldval
= operands
[3];
27170 newval
= operands
[4];
27171 is_weak
= operands
[5];
27172 mod_s
= operands
[6];
27173 mod_f
= operands
[7];
27174 mode
= GET_MODE (mem
);
27176 /* Normally the succ memory model must be stronger than fail, but in the
27177 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
27178 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
27180 if (TARGET_HAVE_LDACQ
27181 && INTVAL (mod_f
) == MEMMODEL_ACQUIRE
27182 && INTVAL (mod_s
) == MEMMODEL_RELEASE
)
27183 mod_s
= GEN_INT (MEMMODEL_ACQ_REL
);
27189 /* For narrow modes, we're going to perform the comparison in SImode,
27190 so do the zero-extension now. */
27191 rval
= gen_reg_rtx (SImode
);
27192 oldval
= convert_modes (SImode
, mode
, oldval
, true);
27196 /* Force the value into a register if needed. We waited until after
27197 the zero-extension above to do this properly. */
27198 if (!arm_add_operand (oldval
, SImode
))
27199 oldval
= force_reg (SImode
, oldval
);
27203 if (!cmpdi_operand (oldval
, mode
))
27204 oldval
= force_reg (mode
, oldval
);
27208 gcc_unreachable ();
27213 case QImode
: gen
= gen_atomic_compare_and_swapqi_1
; break;
27214 case HImode
: gen
= gen_atomic_compare_and_swaphi_1
; break;
27215 case SImode
: gen
= gen_atomic_compare_and_swapsi_1
; break;
27216 case DImode
: gen
= gen_atomic_compare_and_swapdi_1
; break;
27218 gcc_unreachable ();
27221 emit_insn (gen (rval
, mem
, oldval
, newval
, is_weak
, mod_s
, mod_f
));
27223 if (mode
== QImode
|| mode
== HImode
)
27224 emit_move_insn (operands
[1], gen_lowpart (mode
, rval
));
27226 /* In all cases, we arrange for success to be signaled by Z set.
27227 This arrangement allows for the boolean result to be used directly
27228 in a subsequent branch, post optimization. */
27229 x
= gen_rtx_REG (CCmode
, CC_REGNUM
);
27230 x
= gen_rtx_EQ (SImode
, x
, const0_rtx
);
27231 emit_insn (gen_rtx_SET (VOIDmode
, bval
, x
));
27234 /* Split a compare and swap pattern. It is IMPLEMENTATION DEFINED whether
27235 another memory store between the load-exclusive and store-exclusive can
27236 reset the monitor from Exclusive to Open state. This means we must wait
27237 until after reload to split the pattern, lest we get a register spill in
27238 the middle of the atomic sequence. */
27241 arm_split_compare_and_swap (rtx operands
[])
27243 rtx rval
, mem
, oldval
, newval
, scratch
;
27244 enum machine_mode mode
;
27245 enum memmodel mod_s
, mod_f
;
27247 rtx label1
, label2
, x
, cond
;
27249 rval
= operands
[0];
27251 oldval
= operands
[2];
27252 newval
= operands
[3];
27253 is_weak
= (operands
[4] != const0_rtx
);
27254 mod_s
= (enum memmodel
) INTVAL (operands
[5]);
27255 mod_f
= (enum memmodel
) INTVAL (operands
[6]);
27256 scratch
= operands
[7];
27257 mode
= GET_MODE (mem
);
27259 bool use_acquire
= TARGET_HAVE_LDACQ
27260 && !(mod_s
== MEMMODEL_RELAXED
27261 || mod_s
== MEMMODEL_CONSUME
27262 || mod_s
== MEMMODEL_RELEASE
);
27264 bool use_release
= TARGET_HAVE_LDACQ
27265 && !(mod_s
== MEMMODEL_RELAXED
27266 || mod_s
== MEMMODEL_CONSUME
27267 || mod_s
== MEMMODEL_ACQUIRE
);
27269 /* Checks whether a barrier is needed and emits one accordingly. */
27270 if (!(use_acquire
|| use_release
))
27271 arm_pre_atomic_barrier (mod_s
);
27276 label1
= gen_label_rtx ();
27277 emit_label (label1
);
27279 label2
= gen_label_rtx ();
27281 arm_emit_load_exclusive (mode
, rval
, mem
, use_acquire
);
27283 cond
= arm_gen_compare_reg (NE
, rval
, oldval
, scratch
);
27284 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
27285 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
27286 gen_rtx_LABEL_REF (Pmode
, label2
), pc_rtx
);
27287 emit_unlikely_jump (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
27289 arm_emit_store_exclusive (mode
, scratch
, mem
, newval
, use_release
);
27291 /* Weak or strong, we want EQ to be true for success, so that we
27292 match the flags that we got from the compare above. */
27293 cond
= gen_rtx_REG (CCmode
, CC_REGNUM
);
27294 x
= gen_rtx_COMPARE (CCmode
, scratch
, const0_rtx
);
27295 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
27299 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
27300 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
27301 gen_rtx_LABEL_REF (Pmode
, label1
), pc_rtx
);
27302 emit_unlikely_jump (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
27305 if (mod_f
!= MEMMODEL_RELAXED
)
27306 emit_label (label2
);
27308 /* Checks whether a barrier is needed and emits one accordingly. */
27309 if (!(use_acquire
|| use_release
))
27310 arm_post_atomic_barrier (mod_s
);
27312 if (mod_f
== MEMMODEL_RELAXED
)
27313 emit_label (label2
);
27317 arm_split_atomic_op (enum rtx_code code
, rtx old_out
, rtx new_out
, rtx mem
,
27318 rtx value
, rtx model_rtx
, rtx cond
)
27320 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
27321 enum machine_mode mode
= GET_MODE (mem
);
27322 enum machine_mode wmode
= (mode
== DImode
? DImode
: SImode
);
27325 bool use_acquire
= TARGET_HAVE_LDACQ
27326 && !(model
== MEMMODEL_RELAXED
27327 || model
== MEMMODEL_CONSUME
27328 || model
== MEMMODEL_RELEASE
);
27330 bool use_release
= TARGET_HAVE_LDACQ
27331 && !(model
== MEMMODEL_RELAXED
27332 || model
== MEMMODEL_CONSUME
27333 || model
== MEMMODEL_ACQUIRE
);
27335 /* Checks whether a barrier is needed and emits one accordingly. */
27336 if (!(use_acquire
|| use_release
))
27337 arm_pre_atomic_barrier (model
);
27339 label
= gen_label_rtx ();
27340 emit_label (label
);
27343 new_out
= gen_lowpart (wmode
, new_out
);
27345 old_out
= gen_lowpart (wmode
, old_out
);
27348 value
= simplify_gen_subreg (wmode
, value
, mode
, 0);
27350 arm_emit_load_exclusive (mode
, old_out
, mem
, use_acquire
);
27359 x
= gen_rtx_AND (wmode
, old_out
, value
);
27360 emit_insn (gen_rtx_SET (VOIDmode
, new_out
, x
));
27361 x
= gen_rtx_NOT (wmode
, new_out
);
27362 emit_insn (gen_rtx_SET (VOIDmode
, new_out
, x
));
27366 if (CONST_INT_P (value
))
27368 value
= GEN_INT (-INTVAL (value
));
27374 if (mode
== DImode
)
27376 /* DImode plus/minus need to clobber flags. */
27377 /* The adddi3 and subdi3 patterns are incorrectly written so that
27378 they require matching operands, even when we could easily support
27379 three operands. Thankfully, this can be fixed up post-splitting,
27380 as the individual add+adc patterns do accept three operands and
27381 post-reload cprop can make these moves go away. */
27382 emit_move_insn (new_out
, old_out
);
27384 x
= gen_adddi3 (new_out
, new_out
, value
);
27386 x
= gen_subdi3 (new_out
, new_out
, value
);
27393 x
= gen_rtx_fmt_ee (code
, wmode
, old_out
, value
);
27394 emit_insn (gen_rtx_SET (VOIDmode
, new_out
, x
));
27398 arm_emit_store_exclusive (mode
, cond
, mem
, gen_lowpart (mode
, new_out
),
27401 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
27402 emit_unlikely_jump (gen_cbranchsi4 (x
, cond
, const0_rtx
, label
));
27404 /* Checks whether a barrier is needed and emits one accordingly. */
27405 if (!(use_acquire
|| use_release
))
27406 arm_post_atomic_barrier (model
);
27409 #define MAX_VECT_LEN 16
27411 struct expand_vec_perm_d
27413 rtx target
, op0
, op1
;
27414 unsigned char perm
[MAX_VECT_LEN
];
27415 enum machine_mode vmode
;
27416 unsigned char nelt
;
27421 /* Generate a variable permutation. */
27424 arm_expand_vec_perm_1 (rtx target
, rtx op0
, rtx op1
, rtx sel
)
27426 enum machine_mode vmode
= GET_MODE (target
);
27427 bool one_vector_p
= rtx_equal_p (op0
, op1
);
27429 gcc_checking_assert (vmode
== V8QImode
|| vmode
== V16QImode
);
27430 gcc_checking_assert (GET_MODE (op0
) == vmode
);
27431 gcc_checking_assert (GET_MODE (op1
) == vmode
);
27432 gcc_checking_assert (GET_MODE (sel
) == vmode
);
27433 gcc_checking_assert (TARGET_NEON
);
27437 if (vmode
== V8QImode
)
27438 emit_insn (gen_neon_vtbl1v8qi (target
, op0
, sel
));
27440 emit_insn (gen_neon_vtbl1v16qi (target
, op0
, sel
));
27446 if (vmode
== V8QImode
)
27448 pair
= gen_reg_rtx (V16QImode
);
27449 emit_insn (gen_neon_vcombinev8qi (pair
, op0
, op1
));
27450 pair
= gen_lowpart (TImode
, pair
);
27451 emit_insn (gen_neon_vtbl2v8qi (target
, pair
, sel
));
27455 pair
= gen_reg_rtx (OImode
);
27456 emit_insn (gen_neon_vcombinev16qi (pair
, op0
, op1
));
27457 emit_insn (gen_neon_vtbl2v16qi (target
, pair
, sel
));
27463 arm_expand_vec_perm (rtx target
, rtx op0
, rtx op1
, rtx sel
)
27465 enum machine_mode vmode
= GET_MODE (target
);
27466 unsigned int i
, nelt
= GET_MODE_NUNITS (vmode
);
27467 bool one_vector_p
= rtx_equal_p (op0
, op1
);
27468 rtx rmask
[MAX_VECT_LEN
], mask
;
27470 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
27471 numbering of elements for big-endian, we must reverse the order. */
27472 gcc_checking_assert (!BYTES_BIG_ENDIAN
);
27474 /* The VTBL instruction does not use a modulo index, so we must take care
27475 of that ourselves. */
27476 mask
= GEN_INT (one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
27477 for (i
= 0; i
< nelt
; ++i
)
27479 mask
= gen_rtx_CONST_VECTOR (vmode
, gen_rtvec_v (nelt
, rmask
));
27480 sel
= expand_simple_binop (vmode
, AND
, sel
, mask
, NULL
, 0, OPTAB_LIB_WIDEN
);
27482 arm_expand_vec_perm_1 (target
, op0
, op1
, sel
);
27485 /* Generate or test for an insn that supports a constant permutation. */
27487 /* Recognize patterns for the VUZP insns. */
27490 arm_evpc_neon_vuzp (struct expand_vec_perm_d
*d
)
27492 unsigned int i
, odd
, mask
, nelt
= d
->nelt
;
27493 rtx out0
, out1
, in0
, in1
, x
;
27494 rtx (*gen
)(rtx
, rtx
, rtx
, rtx
);
27496 if (GET_MODE_UNIT_SIZE (d
->vmode
) >= 8)
27499 /* Note that these are little-endian tests. Adjust for big-endian later. */
27500 if (d
->perm
[0] == 0)
27502 else if (d
->perm
[0] == 1)
27506 mask
= (d
->one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
27508 for (i
= 0; i
< nelt
; i
++)
27510 unsigned elt
= (i
* 2 + odd
) & mask
;
27511 if (d
->perm
[i
] != elt
)
27521 case V16QImode
: gen
= gen_neon_vuzpv16qi_internal
; break;
27522 case V8QImode
: gen
= gen_neon_vuzpv8qi_internal
; break;
27523 case V8HImode
: gen
= gen_neon_vuzpv8hi_internal
; break;
27524 case V4HImode
: gen
= gen_neon_vuzpv4hi_internal
; break;
27525 case V4SImode
: gen
= gen_neon_vuzpv4si_internal
; break;
27526 case V2SImode
: gen
= gen_neon_vuzpv2si_internal
; break;
27527 case V2SFmode
: gen
= gen_neon_vuzpv2sf_internal
; break;
27528 case V4SFmode
: gen
= gen_neon_vuzpv4sf_internal
; break;
27530 gcc_unreachable ();
27535 if (BYTES_BIG_ENDIAN
)
27537 x
= in0
, in0
= in1
, in1
= x
;
27542 out1
= gen_reg_rtx (d
->vmode
);
27544 x
= out0
, out0
= out1
, out1
= x
;
27546 emit_insn (gen (out0
, in0
, in1
, out1
));
27550 /* Recognize patterns for the VZIP insns. */
27553 arm_evpc_neon_vzip (struct expand_vec_perm_d
*d
)
27555 unsigned int i
, high
, mask
, nelt
= d
->nelt
;
27556 rtx out0
, out1
, in0
, in1
, x
;
27557 rtx (*gen
)(rtx
, rtx
, rtx
, rtx
);
27559 if (GET_MODE_UNIT_SIZE (d
->vmode
) >= 8)
27562 /* Note that these are little-endian tests. Adjust for big-endian later. */
27564 if (d
->perm
[0] == high
)
27566 else if (d
->perm
[0] == 0)
27570 mask
= (d
->one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
27572 for (i
= 0; i
< nelt
/ 2; i
++)
27574 unsigned elt
= (i
+ high
) & mask
;
27575 if (d
->perm
[i
* 2] != elt
)
27577 elt
= (elt
+ nelt
) & mask
;
27578 if (d
->perm
[i
* 2 + 1] != elt
)
27588 case V16QImode
: gen
= gen_neon_vzipv16qi_internal
; break;
27589 case V8QImode
: gen
= gen_neon_vzipv8qi_internal
; break;
27590 case V8HImode
: gen
= gen_neon_vzipv8hi_internal
; break;
27591 case V4HImode
: gen
= gen_neon_vzipv4hi_internal
; break;
27592 case V4SImode
: gen
= gen_neon_vzipv4si_internal
; break;
27593 case V2SImode
: gen
= gen_neon_vzipv2si_internal
; break;
27594 case V2SFmode
: gen
= gen_neon_vzipv2sf_internal
; break;
27595 case V4SFmode
: gen
= gen_neon_vzipv4sf_internal
; break;
27597 gcc_unreachable ();
27602 if (BYTES_BIG_ENDIAN
)
27604 x
= in0
, in0
= in1
, in1
= x
;
27609 out1
= gen_reg_rtx (d
->vmode
);
27611 x
= out0
, out0
= out1
, out1
= x
;
27613 emit_insn (gen (out0
, in0
, in1
, out1
));
27617 /* Recognize patterns for the VREV insns. */
27620 arm_evpc_neon_vrev (struct expand_vec_perm_d
*d
)
27622 unsigned int i
, j
, diff
, nelt
= d
->nelt
;
27623 rtx (*gen
)(rtx
, rtx
, rtx
);
27625 if (!d
->one_vector_p
)
27634 case V16QImode
: gen
= gen_neon_vrev64v16qi
; break;
27635 case V8QImode
: gen
= gen_neon_vrev64v8qi
; break;
27643 case V16QImode
: gen
= gen_neon_vrev32v16qi
; break;
27644 case V8QImode
: gen
= gen_neon_vrev32v8qi
; break;
27645 case V8HImode
: gen
= gen_neon_vrev64v8hi
; break;
27646 case V4HImode
: gen
= gen_neon_vrev64v4hi
; break;
27654 case V16QImode
: gen
= gen_neon_vrev16v16qi
; break;
27655 case V8QImode
: gen
= gen_neon_vrev16v8qi
; break;
27656 case V8HImode
: gen
= gen_neon_vrev32v8hi
; break;
27657 case V4HImode
: gen
= gen_neon_vrev32v4hi
; break;
27658 case V4SImode
: gen
= gen_neon_vrev64v4si
; break;
27659 case V2SImode
: gen
= gen_neon_vrev64v2si
; break;
27660 case V4SFmode
: gen
= gen_neon_vrev64v4sf
; break;
27661 case V2SFmode
: gen
= gen_neon_vrev64v2sf
; break;
27670 for (i
= 0; i
< nelt
; i
+= diff
+ 1)
27671 for (j
= 0; j
<= diff
; j
+= 1)
27673 /* This is guaranteed to be true as the value of diff
27674 is 7, 3, 1 and we should have enough elements in the
27675 queue to generate this. Getting a vector mask with a
27676 value of diff other than these values implies that
27677 something is wrong by the time we get here. */
27678 gcc_assert (i
+ j
< nelt
);
27679 if (d
->perm
[i
+ j
] != i
+ diff
- j
)
27687 /* ??? The third operand is an artifact of the builtin infrastructure
27688 and is ignored by the actual instruction. */
27689 emit_insn (gen (d
->target
, d
->op0
, const0_rtx
));
27693 /* Recognize patterns for the VTRN insns. */
27696 arm_evpc_neon_vtrn (struct expand_vec_perm_d
*d
)
27698 unsigned int i
, odd
, mask
, nelt
= d
->nelt
;
27699 rtx out0
, out1
, in0
, in1
, x
;
27700 rtx (*gen
)(rtx
, rtx
, rtx
, rtx
);
27702 if (GET_MODE_UNIT_SIZE (d
->vmode
) >= 8)
27705 /* Note that these are little-endian tests. Adjust for big-endian later. */
27706 if (d
->perm
[0] == 0)
27708 else if (d
->perm
[0] == 1)
27712 mask
= (d
->one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
27714 for (i
= 0; i
< nelt
; i
+= 2)
27716 if (d
->perm
[i
] != i
+ odd
)
27718 if (d
->perm
[i
+ 1] != ((i
+ nelt
+ odd
) & mask
))
27728 case V16QImode
: gen
= gen_neon_vtrnv16qi_internal
; break;
27729 case V8QImode
: gen
= gen_neon_vtrnv8qi_internal
; break;
27730 case V8HImode
: gen
= gen_neon_vtrnv8hi_internal
; break;
27731 case V4HImode
: gen
= gen_neon_vtrnv4hi_internal
; break;
27732 case V4SImode
: gen
= gen_neon_vtrnv4si_internal
; break;
27733 case V2SImode
: gen
= gen_neon_vtrnv2si_internal
; break;
27734 case V2SFmode
: gen
= gen_neon_vtrnv2sf_internal
; break;
27735 case V4SFmode
: gen
= gen_neon_vtrnv4sf_internal
; break;
27737 gcc_unreachable ();
27742 if (BYTES_BIG_ENDIAN
)
27744 x
= in0
, in0
= in1
, in1
= x
;
27749 out1
= gen_reg_rtx (d
->vmode
);
27751 x
= out0
, out0
= out1
, out1
= x
;
27753 emit_insn (gen (out0
, in0
, in1
, out1
));
27757 /* Recognize patterns for the VEXT insns. */
27760 arm_evpc_neon_vext (struct expand_vec_perm_d
*d
)
27762 unsigned int i
, nelt
= d
->nelt
;
27763 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
27766 unsigned int location
;
27768 unsigned int next
= d
->perm
[0] + 1;
27770 /* TODO: Handle GCC's numbering of elements for big-endian. */
27771 if (BYTES_BIG_ENDIAN
)
27774 /* Check if the extracted indexes are increasing by one. */
27775 for (i
= 1; i
< nelt
; next
++, i
++)
27777 /* If we hit the most significant element of the 2nd vector in
27778 the previous iteration, no need to test further. */
27779 if (next
== 2 * nelt
)
27782 /* If we are operating on only one vector: it could be a
27783 rotation. If there are only two elements of size < 64, let
27784 arm_evpc_neon_vrev catch it. */
27785 if (d
->one_vector_p
&& (next
== nelt
))
27787 if ((nelt
== 2) && (d
->vmode
!= V2DImode
))
27793 if (d
->perm
[i
] != next
)
27797 location
= d
->perm
[0];
27801 case V16QImode
: gen
= gen_neon_vextv16qi
; break;
27802 case V8QImode
: gen
= gen_neon_vextv8qi
; break;
27803 case V4HImode
: gen
= gen_neon_vextv4hi
; break;
27804 case V8HImode
: gen
= gen_neon_vextv8hi
; break;
27805 case V2SImode
: gen
= gen_neon_vextv2si
; break;
27806 case V4SImode
: gen
= gen_neon_vextv4si
; break;
27807 case V2SFmode
: gen
= gen_neon_vextv2sf
; break;
27808 case V4SFmode
: gen
= gen_neon_vextv4sf
; break;
27809 case V2DImode
: gen
= gen_neon_vextv2di
; break;
27818 offset
= GEN_INT (location
);
27819 emit_insn (gen (d
->target
, d
->op0
, d
->op1
, offset
));
27823 /* The NEON VTBL instruction is a fully variable permuation that's even
27824 stronger than what we expose via VEC_PERM_EXPR. What it doesn't do
27825 is mask the index operand as VEC_PERM_EXPR requires. Therefore we
27826 can do slightly better by expanding this as a constant where we don't
27827 have to apply a mask. */
27830 arm_evpc_neon_vtbl (struct expand_vec_perm_d
*d
)
27832 rtx rperm
[MAX_VECT_LEN
], sel
;
27833 enum machine_mode vmode
= d
->vmode
;
27834 unsigned int i
, nelt
= d
->nelt
;
27836 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
27837 numbering of elements for big-endian, we must reverse the order. */
27838 if (BYTES_BIG_ENDIAN
)
27844 /* Generic code will try constant permutation twice. Once with the
27845 original mode and again with the elements lowered to QImode.
27846 So wait and don't do the selector expansion ourselves. */
27847 if (vmode
!= V8QImode
&& vmode
!= V16QImode
)
27850 for (i
= 0; i
< nelt
; ++i
)
27851 rperm
[i
] = GEN_INT (d
->perm
[i
]);
27852 sel
= gen_rtx_CONST_VECTOR (vmode
, gen_rtvec_v (nelt
, rperm
));
27853 sel
= force_reg (vmode
, sel
);
27855 arm_expand_vec_perm_1 (d
->target
, d
->op0
, d
->op1
, sel
);
27860 arm_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
27862 /* Check if the input mask matches vext before reordering the
27865 if (arm_evpc_neon_vext (d
))
27868 /* The pattern matching functions above are written to look for a small
27869 number to begin the sequence (0, 1, N/2). If we begin with an index
27870 from the second operand, we can swap the operands. */
27871 if (d
->perm
[0] >= d
->nelt
)
27873 unsigned i
, nelt
= d
->nelt
;
27876 for (i
= 0; i
< nelt
; ++i
)
27877 d
->perm
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
27886 if (arm_evpc_neon_vuzp (d
))
27888 if (arm_evpc_neon_vzip (d
))
27890 if (arm_evpc_neon_vrev (d
))
27892 if (arm_evpc_neon_vtrn (d
))
27894 return arm_evpc_neon_vtbl (d
);
27899 /* Expand a vec_perm_const pattern. */
27902 arm_expand_vec_perm_const (rtx target
, rtx op0
, rtx op1
, rtx sel
)
27904 struct expand_vec_perm_d d
;
27905 int i
, nelt
, which
;
27911 d
.vmode
= GET_MODE (target
);
27912 gcc_assert (VECTOR_MODE_P (d
.vmode
));
27913 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
27914 d
.testing_p
= false;
27916 for (i
= which
= 0; i
< nelt
; ++i
)
27918 rtx e
= XVECEXP (sel
, 0, i
);
27919 int ei
= INTVAL (e
) & (2 * nelt
- 1);
27920 which
|= (ei
< nelt
? 1 : 2);
27930 d
.one_vector_p
= false;
27931 if (!rtx_equal_p (op0
, op1
))
27934 /* The elements of PERM do not suggest that only the first operand
27935 is used, but both operands are identical. Allow easier matching
27936 of the permutation by folding the permutation into the single
27940 for (i
= 0; i
< nelt
; ++i
)
27941 d
.perm
[i
] &= nelt
- 1;
27943 d
.one_vector_p
= true;
27948 d
.one_vector_p
= true;
27952 return arm_expand_vec_perm_const_1 (&d
);
27955 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
27958 arm_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
27959 const unsigned char *sel
)
27961 struct expand_vec_perm_d d
;
27962 unsigned int i
, nelt
, which
;
27966 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
27967 d
.testing_p
= true;
27968 memcpy (d
.perm
, sel
, nelt
);
27970 /* Categorize the set of elements in the selector. */
27971 for (i
= which
= 0; i
< nelt
; ++i
)
27973 unsigned char e
= d
.perm
[i
];
27974 gcc_assert (e
< 2 * nelt
);
27975 which
|= (e
< nelt
? 1 : 2);
27978 /* For all elements from second vector, fold the elements to first. */
27980 for (i
= 0; i
< nelt
; ++i
)
27983 /* Check whether the mask can be applied to the vector type. */
27984 d
.one_vector_p
= (which
!= 3);
27986 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
27987 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
27988 if (!d
.one_vector_p
)
27989 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
27992 ret
= arm_expand_vec_perm_const_1 (&d
);
27999 arm_autoinc_modes_ok_p (enum machine_mode mode
, enum arm_auto_incmodes code
)
28001 /* If we are soft float and we do not have ldrd
28002 then all auto increment forms are ok. */
28003 if (TARGET_SOFT_FLOAT
&& (TARGET_LDRD
|| GET_MODE_SIZE (mode
) <= 4))
28008 /* Post increment and Pre Decrement are supported for all
28009 instruction forms except for vector forms. */
28012 if (VECTOR_MODE_P (mode
))
28014 if (code
!= ARM_PRE_DEC
)
28024 /* Without LDRD and mode size greater than
28025 word size, there is no point in auto-incrementing
28026 because ldm and stm will not have these forms. */
28027 if (!TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4)
28030 /* Vector and floating point modes do not support
28031 these auto increment forms. */
28032 if (FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
28045 /* The default expansion of general 64-bit shifts in core-regs is suboptimal,
28046 on ARM, since we know that shifts by negative amounts are no-ops.
28047 Additionally, the default expansion code is not available or suitable
28048 for post-reload insn splits (this can occur when the register allocator
28049 chooses not to do a shift in NEON).
28051 This function is used in both initial expand and post-reload splits, and
28052 handles all kinds of 64-bit shifts.
28054 Input requirements:
28055 - It is safe for the input and output to be the same register, but
28056 early-clobber rules apply for the shift amount and scratch registers.
28057 - Shift by register requires both scratch registers. In all other cases
28058 the scratch registers may be NULL.
28059 - Ashiftrt by a register also clobbers the CC register. */
28061 arm_emit_coreregs_64bit_shift (enum rtx_code code
, rtx out
, rtx in
,
28062 rtx amount
, rtx scratch1
, rtx scratch2
)
28064 rtx out_high
= gen_highpart (SImode
, out
);
28065 rtx out_low
= gen_lowpart (SImode
, out
);
28066 rtx in_high
= gen_highpart (SImode
, in
);
28067 rtx in_low
= gen_lowpart (SImode
, in
);
28070 in = the register pair containing the input value.
28071 out = the destination register pair.
28072 up = the high- or low-part of each pair.
28073 down = the opposite part to "up".
28074 In a shift, we can consider bits to shift from "up"-stream to
28075 "down"-stream, so in a left-shift "up" is the low-part and "down"
28076 is the high-part of each register pair. */
28078 rtx out_up
= code
== ASHIFT
? out_low
: out_high
;
28079 rtx out_down
= code
== ASHIFT
? out_high
: out_low
;
28080 rtx in_up
= code
== ASHIFT
? in_low
: in_high
;
28081 rtx in_down
= code
== ASHIFT
? in_high
: in_low
;
28083 gcc_assert (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
);
28085 && (REG_P (out
) || GET_CODE (out
) == SUBREG
)
28086 && GET_MODE (out
) == DImode
);
28088 && (REG_P (in
) || GET_CODE (in
) == SUBREG
)
28089 && GET_MODE (in
) == DImode
);
28091 && (((REG_P (amount
) || GET_CODE (amount
) == SUBREG
)
28092 && GET_MODE (amount
) == SImode
)
28093 || CONST_INT_P (amount
)));
28094 gcc_assert (scratch1
== NULL
28095 || (GET_CODE (scratch1
) == SCRATCH
)
28096 || (GET_MODE (scratch1
) == SImode
28097 && REG_P (scratch1
)));
28098 gcc_assert (scratch2
== NULL
28099 || (GET_CODE (scratch2
) == SCRATCH
)
28100 || (GET_MODE (scratch2
) == SImode
28101 && REG_P (scratch2
)));
28102 gcc_assert (!REG_P (out
) || !REG_P (amount
)
28103 || !HARD_REGISTER_P (out
)
28104 || (REGNO (out
) != REGNO (amount
)
28105 && REGNO (out
) + 1 != REGNO (amount
)));
28107 /* Macros to make following code more readable. */
28108 #define SUB_32(DEST,SRC) \
28109 gen_addsi3 ((DEST), (SRC), GEN_INT (-32))
28110 #define RSB_32(DEST,SRC) \
28111 gen_subsi3 ((DEST), GEN_INT (32), (SRC))
28112 #define SUB_S_32(DEST,SRC) \
28113 gen_addsi3_compare0 ((DEST), (SRC), \
28115 #define SET(DEST,SRC) \
28116 gen_rtx_SET (SImode, (DEST), (SRC))
28117 #define SHIFT(CODE,SRC,AMOUNT) \
28118 gen_rtx_fmt_ee ((CODE), SImode, (SRC), (AMOUNT))
28119 #define LSHIFT(CODE,SRC,AMOUNT) \
28120 gen_rtx_fmt_ee ((CODE) == ASHIFT ? ASHIFT : LSHIFTRT, \
28121 SImode, (SRC), (AMOUNT))
28122 #define REV_LSHIFT(CODE,SRC,AMOUNT) \
28123 gen_rtx_fmt_ee ((CODE) == ASHIFT ? LSHIFTRT : ASHIFT, \
28124 SImode, (SRC), (AMOUNT))
28126 gen_rtx_IOR (SImode, (A), (B))
28127 #define BRANCH(COND,LABEL) \
28128 gen_arm_cond_branch ((LABEL), \
28129 gen_rtx_ ## COND (CCmode, cc_reg, \
28133 /* Shifts by register and shifts by constant are handled separately. */
28134 if (CONST_INT_P (amount
))
28136 /* We have a shift-by-constant. */
28138 /* First, handle out-of-range shift amounts.
28139 In both cases we try to match the result an ARM instruction in a
28140 shift-by-register would give. This helps reduce execution
28141 differences between optimization levels, but it won't stop other
28142 parts of the compiler doing different things. This is "undefined
28143 behaviour, in any case. */
28144 if (INTVAL (amount
) <= 0)
28145 emit_insn (gen_movdi (out
, in
));
28146 else if (INTVAL (amount
) >= 64)
28148 if (code
== ASHIFTRT
)
28150 rtx const31_rtx
= GEN_INT (31);
28151 emit_insn (SET (out_down
, SHIFT (code
, in_up
, const31_rtx
)));
28152 emit_insn (SET (out_up
, SHIFT (code
, in_up
, const31_rtx
)));
28155 emit_insn (gen_movdi (out
, const0_rtx
));
28158 /* Now handle valid shifts. */
28159 else if (INTVAL (amount
) < 32)
28161 /* Shifts by a constant less than 32. */
28162 rtx reverse_amount
= GEN_INT (32 - INTVAL (amount
));
28164 emit_insn (SET (out_down
, LSHIFT (code
, in_down
, amount
)));
28165 emit_insn (SET (out_down
,
28166 ORR (REV_LSHIFT (code
, in_up
, reverse_amount
),
28168 emit_insn (SET (out_up
, SHIFT (code
, in_up
, amount
)));
28172 /* Shifts by a constant greater than 31. */
28173 rtx adj_amount
= GEN_INT (INTVAL (amount
) - 32);
28175 emit_insn (SET (out_down
, SHIFT (code
, in_up
, adj_amount
)));
28176 if (code
== ASHIFTRT
)
28177 emit_insn (gen_ashrsi3 (out_up
, in_up
,
28180 emit_insn (SET (out_up
, const0_rtx
));
28185 /* We have a shift-by-register. */
28186 rtx cc_reg
= gen_rtx_REG (CC_NOOVmode
, CC_REGNUM
);
28188 /* This alternative requires the scratch registers. */
28189 gcc_assert (scratch1
&& REG_P (scratch1
));
28190 gcc_assert (scratch2
&& REG_P (scratch2
));
28192 /* We will need the values "amount-32" and "32-amount" later.
28193 Swapping them around now allows the later code to be more general. */
28197 emit_insn (SUB_32 (scratch1
, amount
));
28198 emit_insn (RSB_32 (scratch2
, amount
));
28201 emit_insn (RSB_32 (scratch1
, amount
));
28202 /* Also set CC = amount > 32. */
28203 emit_insn (SUB_S_32 (scratch2
, amount
));
28206 emit_insn (RSB_32 (scratch1
, amount
));
28207 emit_insn (SUB_32 (scratch2
, amount
));
28210 gcc_unreachable ();
28213 /* Emit code like this:
28216 out_down = in_down << amount;
28217 out_down = (in_up << (amount - 32)) | out_down;
28218 out_down = ((unsigned)in_up >> (32 - amount)) | out_down;
28219 out_up = in_up << amount;
28222 out_down = in_down >> amount;
28223 out_down = (in_up << (32 - amount)) | out_down;
28225 out_down = ((signed)in_up >> (amount - 32)) | out_down;
28226 out_up = in_up << amount;
28229 out_down = in_down >> amount;
28230 out_down = (in_up << (32 - amount)) | out_down;
28232 out_down = ((unsigned)in_up >> (amount - 32)) | out_down;
28233 out_up = in_up << amount;
28235 The ARM and Thumb2 variants are the same but implemented slightly
28236 differently. If this were only called during expand we could just
28237 use the Thumb2 case and let combine do the right thing, but this
28238 can also be called from post-reload splitters. */
28240 emit_insn (SET (out_down
, LSHIFT (code
, in_down
, amount
)));
28242 if (!TARGET_THUMB2
)
28244 /* Emit code for ARM mode. */
28245 emit_insn (SET (out_down
,
28246 ORR (SHIFT (ASHIFT
, in_up
, scratch1
), out_down
)));
28247 if (code
== ASHIFTRT
)
28249 rtx done_label
= gen_label_rtx ();
28250 emit_jump_insn (BRANCH (LT
, done_label
));
28251 emit_insn (SET (out_down
, ORR (SHIFT (ASHIFTRT
, in_up
, scratch2
),
28253 emit_label (done_label
);
28256 emit_insn (SET (out_down
, ORR (SHIFT (LSHIFTRT
, in_up
, scratch2
),
28261 /* Emit code for Thumb2 mode.
28262 Thumb2 can't do shift and or in one insn. */
28263 emit_insn (SET (scratch1
, SHIFT (ASHIFT
, in_up
, scratch1
)));
28264 emit_insn (gen_iorsi3 (out_down
, out_down
, scratch1
));
28266 if (code
== ASHIFTRT
)
28268 rtx done_label
= gen_label_rtx ();
28269 emit_jump_insn (BRANCH (LT
, done_label
));
28270 emit_insn (SET (scratch2
, SHIFT (ASHIFTRT
, in_up
, scratch2
)));
28271 emit_insn (SET (out_down
, ORR (out_down
, scratch2
)));
28272 emit_label (done_label
);
28276 emit_insn (SET (scratch2
, SHIFT (LSHIFTRT
, in_up
, scratch2
)));
28277 emit_insn (gen_iorsi3 (out_down
, out_down
, scratch2
));
28281 emit_insn (SET (out_up
, SHIFT (code
, in_up
, amount
)));
28296 /* Returns true if a valid comparison operation and makes
28297 the operands in a form that is valid. */
28299 arm_validize_comparison (rtx
*comparison
, rtx
* op1
, rtx
* op2
)
28301 enum rtx_code code
= GET_CODE (*comparison
);
28303 enum machine_mode mode
= (GET_MODE (*op1
) == VOIDmode
)
28304 ? GET_MODE (*op2
) : GET_MODE (*op1
);
28306 gcc_assert (GET_MODE (*op1
) != VOIDmode
|| GET_MODE (*op2
) != VOIDmode
);
28308 if (code
== UNEQ
|| code
== LTGT
)
28311 code_int
= (int)code
;
28312 arm_canonicalize_comparison (&code_int
, op1
, op2
, 0);
28313 PUT_CODE (*comparison
, (enum rtx_code
)code_int
);
28318 if (!arm_add_operand (*op1
, mode
))
28319 *op1
= force_reg (mode
, *op1
);
28320 if (!arm_add_operand (*op2
, mode
))
28321 *op2
= force_reg (mode
, *op2
);
28325 if (!cmpdi_operand (*op1
, mode
))
28326 *op1
= force_reg (mode
, *op1
);
28327 if (!cmpdi_operand (*op2
, mode
))
28328 *op2
= force_reg (mode
, *op2
);
28333 if (!arm_float_compare_operand (*op1
, mode
))
28334 *op1
= force_reg (mode
, *op1
);
28335 if (!arm_float_compare_operand (*op2
, mode
))
28336 *op2
= force_reg (mode
, *op2
);
28346 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
28348 static unsigned HOST_WIDE_INT
28349 arm_asan_shadow_offset (void)
28351 return (unsigned HOST_WIDE_INT
) 1 << 29;
28354 #include "gt-arm.h"