1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
101 #include "tree-pass.h"
103 #include "valtrack.h"
107 /* Number of attempts to combine instructions in this function. */
109 static int combine_attempts
;
111 /* Number of attempts that got as far as substitution in this function. */
113 static int combine_merges
;
115 /* Number of instructions combined with added SETs in this function. */
117 static int combine_extras
;
119 /* Number of instructions combined in this function. */
121 static int combine_successes
;
123 /* Totals over entire compilation. */
125 static int total_attempts
, total_merges
, total_extras
, total_successes
;
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
138 static rtx i2mod_old_rhs
;
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
142 static rtx i2mod_new_rhs
;
144 typedef struct reg_stat_struct
{
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
201 int last_set_table_tick
;
203 /* Record the value of label_tick when the value for register n is placed in
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
213 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
214 char last_set_sign_bit_copies
;
215 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
221 char last_set_invalid
;
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
233 If an entry is zero, it means that we don't know anything special. */
235 unsigned char sign_bit_copies
;
237 unsigned HOST_WIDE_INT nonzero_bits
;
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
243 int truncation_label
;
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
250 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
254 static vec
<reg_stat_type
> reg_stat
;
256 /* Record the luid of the last insn that invalidated memory
257 (anything that writes memory, and subroutine calls, but not pushes). */
259 static int mem_last_set
;
261 /* Record the luid of the last CALL_INSN
262 so we can tell whether a potential combination crosses any calls. */
264 static int last_call_luid
;
266 /* When `subst' is called, this is the insn that is being modified
267 (by combining in a previous insn). The PATTERN of this insn
268 is still the old pattern partially modified and it should not be
269 looked at, but this may be used to examine the successors of the insn
270 to judge whether a simplification is valid. */
272 static rtx subst_insn
;
274 /* This is the lowest LUID that `subst' is currently dealing with.
275 get_last_value will not return a value if the register was set at or
276 after this LUID. If not for this mechanism, we could get confused if
277 I2 or I1 in try_combine were an insn that used the old value of a register
278 to obtain a new value. In that case, we might erroneously get the
279 new value of the register when we wanted the old one. */
281 static int subst_low_luid
;
283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
284 must consider all these registers to be always live. */
286 static HARD_REG_SET newpat_used_regs
;
288 /* This is an insn to which a LOG_LINKS entry has been added. If this
289 insn is the earlier than I2 or I3, combine should rescan starting at
292 static rtx added_links_insn
;
294 /* Basic block in which we are performing combines. */
295 static basic_block this_basic_block
;
296 static bool optimize_this_for_speed_p
;
299 /* Length of the currently allocated uid_insn_cost array. */
301 static int max_uid_known
;
303 /* The following array records the insn_rtx_cost for every insn
304 in the instruction stream. */
306 static int *uid_insn_cost
;
308 /* The following array records the LOG_LINKS for every insn in the
309 instruction stream as struct insn_link pointers. */
313 struct insn_link
*next
;
316 static struct insn_link
**uid_log_links
;
318 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
319 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
321 #define FOR_EACH_LOG_LINK(L, INSN) \
322 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
324 /* Links for LOG_LINKS are allocated from this obstack. */
326 static struct obstack insn_link_obstack
;
328 /* Allocate a link. */
330 static inline struct insn_link
*
331 alloc_insn_link (rtx insn
, struct insn_link
*next
)
334 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
335 sizeof (struct insn_link
));
341 /* Incremented for each basic block. */
343 static int label_tick
;
345 /* Reset to label_tick for each extended basic block in scanning order. */
347 static int label_tick_ebb_start
;
349 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
350 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
352 static enum machine_mode nonzero_bits_mode
;
354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
355 be safely used. It is zero while computing them and after combine has
356 completed. This former test prevents propagating values based on
357 previously set values, which can be incorrect if a variable is modified
360 static int nonzero_sign_valid
;
363 /* Record one modification to rtl structure
364 to be undone by storing old_contents into *where. */
366 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
372 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
373 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
377 num_undo says how many are currently recorded.
379 other_insn is nonzero if we have modified some other insn in the process
380 of working on subst_insn. It must be verified too. */
389 static struct undobuf undobuf
;
391 /* Number of times the pseudo being substituted for
392 was found and replaced. */
394 static int n_occurrences
;
396 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
398 unsigned HOST_WIDE_INT
,
399 unsigned HOST_WIDE_INT
*);
400 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
402 unsigned int, unsigned int *);
403 static void do_SUBST (rtx
*, rtx
);
404 static void do_SUBST_INT (int *, int);
405 static void init_reg_last (void);
406 static void setup_incoming_promotions (rtx
);
407 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
408 static int cant_combine_insn_p (rtx
);
409 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
410 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
411 static int contains_muldiv (rtx
);
412 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
413 static void undo_all (void);
414 static void undo_commit (void);
415 static rtx
*find_split_point (rtx
*, rtx
, bool);
416 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
417 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
418 static rtx
simplify_if_then_else (rtx
);
419 static rtx
simplify_set (rtx
);
420 static rtx
simplify_logical (rtx
);
421 static rtx
expand_compound_operation (rtx
);
422 static const_rtx
expand_field_assignment (const_rtx
);
423 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
424 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
425 static rtx
extract_left_shift (rtx
, int);
426 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
427 unsigned HOST_WIDE_INT
*);
428 static rtx
canon_reg_for_combine (rtx
, rtx
);
429 static rtx
force_to_mode (rtx
, enum machine_mode
,
430 unsigned HOST_WIDE_INT
, int);
431 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
432 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
433 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
434 static rtx
make_field_assignment (rtx
);
435 static rtx
apply_distributive_law (rtx
);
436 static rtx
distribute_and_simplify_rtx (rtx
, int);
437 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
438 unsigned HOST_WIDE_INT
);
439 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
440 unsigned HOST_WIDE_INT
);
441 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
442 HOST_WIDE_INT
, enum machine_mode
, int *);
443 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
444 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
446 static int recog_for_combine (rtx
*, rtx
, rtx
*);
447 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
448 static enum rtx_code
simplify_compare_const (enum rtx_code
, rtx
, rtx
*);
449 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
450 static void update_table_tick (rtx
);
451 static void record_value_for_reg (rtx
, rtx
, rtx
);
452 static void check_promoted_subreg (rtx
, rtx
);
453 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
454 static void record_dead_and_set_regs (rtx
);
455 static int get_last_value_validate (rtx
*, rtx
, int, int);
456 static rtx
get_last_value (const_rtx
);
457 static int use_crosses_set_p (const_rtx
, int);
458 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
459 static int reg_dead_at_p (rtx
, rtx
);
460 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
461 static int reg_bitfield_target_p (rtx
, rtx
);
462 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
463 static void distribute_links (struct insn_link
*);
464 static void mark_used_regs_combine (rtx
);
465 static void record_promoted_value (rtx
, rtx
);
466 static int unmentioned_reg_p_1 (rtx
*, void *);
467 static bool unmentioned_reg_p (rtx
, rtx
);
468 static int record_truncated_value (rtx
*, void *);
469 static void record_truncated_values (rtx
*, void *);
470 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
471 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
474 /* It is not safe to use ordinary gen_lowpart in combine.
475 See comments in gen_lowpart_for_combine. */
476 #undef RTL_HOOKS_GEN_LOWPART
477 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
479 /* Our implementation of gen_lowpart never emits a new pseudo. */
480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
484 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
492 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
495 /* Convenience wrapper for the canonicalize_comparison target hook.
496 Target hooks cannot use enum rtx_code. */
498 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
499 bool op0_preserve_value
)
501 int code_int
= (int)*code
;
502 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
503 *code
= (enum rtx_code
)code_int
;
506 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
507 PATTERN can not be split. Otherwise, it returns an insn sequence.
508 This is a wrapper around split_insns which ensures that the
509 reg_stat vector is made larger if the splitter creates a new
513 combine_split_insns (rtx pattern
, rtx insn
)
518 ret
= split_insns (pattern
, insn
);
519 nregs
= max_reg_num ();
520 if (nregs
> reg_stat
.length ())
521 reg_stat
.safe_grow_cleared (nregs
);
525 /* This is used by find_single_use to locate an rtx in LOC that
526 contains exactly one use of DEST, which is typically either a REG
527 or CC0. It returns a pointer to the innermost rtx expression
528 containing DEST. Appearances of DEST that are being used to
529 totally replace it are not counted. */
532 find_single_use_1 (rtx dest
, rtx
*loc
)
535 enum rtx_code code
= GET_CODE (x
);
551 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
552 of a REG that occupies all of the REG, the insn uses DEST if
553 it is mentioned in the destination or the source. Otherwise, we
554 need just check the source. */
555 if (GET_CODE (SET_DEST (x
)) != CC0
556 && GET_CODE (SET_DEST (x
)) != PC
557 && !REG_P (SET_DEST (x
))
558 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
559 && REG_P (SUBREG_REG (SET_DEST (x
)))
560 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
561 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
562 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
563 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
566 return find_single_use_1 (dest
, &SET_SRC (x
));
570 return find_single_use_1 (dest
, &XEXP (x
, 0));
576 /* If it wasn't one of the common cases above, check each expression and
577 vector of this code. Look for a unique usage of DEST. */
579 fmt
= GET_RTX_FORMAT (code
);
580 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
584 if (dest
== XEXP (x
, i
)
585 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
586 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
589 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
592 result
= this_result
;
593 else if (this_result
)
594 /* Duplicate usage. */
597 else if (fmt
[i
] == 'E')
601 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
603 if (XVECEXP (x
, i
, j
) == dest
605 && REG_P (XVECEXP (x
, i
, j
))
606 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
609 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
612 result
= this_result
;
613 else if (this_result
)
623 /* See if DEST, produced in INSN, is used only a single time in the
624 sequel. If so, return a pointer to the innermost rtx expression in which
627 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
629 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
630 care about REG_DEAD notes or LOG_LINKS.
632 Otherwise, we find the single use by finding an insn that has a
633 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
634 only referenced once in that insn, we know that it must be the first
635 and last insn referencing DEST. */
638 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
643 struct insn_link
*link
;
648 next
= NEXT_INSN (insn
);
650 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
653 result
= find_single_use_1 (dest
, &PATTERN (next
));
663 bb
= BLOCK_FOR_INSN (insn
);
664 for (next
= NEXT_INSN (insn
);
665 next
&& BLOCK_FOR_INSN (next
) == bb
;
666 next
= NEXT_INSN (next
))
667 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
669 FOR_EACH_LOG_LINK (link
, next
)
670 if (link
->insn
== insn
)
675 result
= find_single_use_1 (dest
, &PATTERN (next
));
685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
686 insn. The substitution can be undone by undo_all. If INTO is already
687 set to NEWVAL, do not record this change. Because computing NEWVAL might
688 also call SUBST, we have to compute it before we put anything into
692 do_SUBST (rtx
*into
, rtx newval
)
697 if (oldval
== newval
)
700 /* We'd like to catch as many invalid transformations here as
701 possible. Unfortunately, there are way too many mode changes
702 that are perfectly valid, so we'd waste too much effort for
703 little gain doing the checks here. Focus on catching invalid
704 transformations involving integer constants. */
705 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
706 && CONST_INT_P (newval
))
708 /* Sanity check that we're replacing oldval with a CONST_INT
709 that is a valid sign-extension for the original mode. */
710 gcc_assert (INTVAL (newval
)
711 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
713 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
714 CONST_INT is not valid, because after the replacement, the
715 original mode would be gone. Unfortunately, we can't tell
716 when do_SUBST is called to replace the operand thereof, so we
717 perform this test on oldval instead, checking whether an
718 invalid replacement took place before we got here. */
719 gcc_assert (!(GET_CODE (oldval
) == SUBREG
720 && CONST_INT_P (SUBREG_REG (oldval
))));
721 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
722 && CONST_INT_P (XEXP (oldval
, 0))));
726 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
728 buf
= XNEW (struct undo
);
730 buf
->kind
= UNDO_RTX
;
732 buf
->old_contents
.r
= oldval
;
735 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
738 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
740 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
741 for the value of a HOST_WIDE_INT value (including CONST_INT) is
745 do_SUBST_INT (int *into
, int newval
)
750 if (oldval
== newval
)
754 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
756 buf
= XNEW (struct undo
);
758 buf
->kind
= UNDO_INT
;
760 buf
->old_contents
.i
= oldval
;
763 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
766 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
768 /* Similar to SUBST, but just substitute the mode. This is used when
769 changing the mode of a pseudo-register, so that any other
770 references to the entry in the regno_reg_rtx array will change as
774 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
777 enum machine_mode oldval
= GET_MODE (*into
);
779 if (oldval
== newval
)
783 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
785 buf
= XNEW (struct undo
);
787 buf
->kind
= UNDO_MODE
;
789 buf
->old_contents
.m
= oldval
;
790 adjust_reg_mode (*into
, newval
);
792 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
795 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
801 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
804 struct insn_link
* oldval
= *into
;
806 if (oldval
== newval
)
810 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
812 buf
= XNEW (struct undo
);
814 buf
->kind
= UNDO_LINKS
;
816 buf
->old_contents
.l
= oldval
;
819 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
825 /* Subroutine of try_combine. Determine whether the replacement patterns
826 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
827 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
828 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
829 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
830 of all the instructions can be estimated and the replacements are more
831 expensive than the original sequence. */
834 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
835 rtx newi2pat
, rtx newotherpat
)
837 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
838 int new_i2_cost
, new_i3_cost
;
839 int old_cost
, new_cost
;
841 /* Lookup the original insn_rtx_costs. */
842 i2_cost
= INSN_COST (i2
);
843 i3_cost
= INSN_COST (i3
);
847 i1_cost
= INSN_COST (i1
);
850 i0_cost
= INSN_COST (i0
);
851 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
852 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
856 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
857 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
863 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
864 i1_cost
= i0_cost
= 0;
867 /* Calculate the replacement insn_rtx_costs. */
868 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
871 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
872 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
873 ? new_i2_cost
+ new_i3_cost
: 0;
877 new_cost
= new_i3_cost
;
881 if (undobuf
.other_insn
)
883 int old_other_cost
, new_other_cost
;
885 old_other_cost
= INSN_COST (undobuf
.other_insn
);
886 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
887 if (old_other_cost
> 0 && new_other_cost
> 0)
889 old_cost
+= old_other_cost
;
890 new_cost
+= new_other_cost
;
896 /* Disallow this combination if both new_cost and old_cost are greater than
897 zero, and new_cost is greater than old cost. */
898 if (old_cost
> 0 && new_cost
> old_cost
)
905 "rejecting combination of insns %d, %d, %d and %d\n",
906 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
908 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
909 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
914 "rejecting combination of insns %d, %d and %d\n",
915 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
916 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
917 i1_cost
, i2_cost
, i3_cost
, old_cost
);
922 "rejecting combination of insns %d and %d\n",
923 INSN_UID (i2
), INSN_UID (i3
));
924 fprintf (dump_file
, "original costs %d + %d = %d\n",
925 i2_cost
, i3_cost
, old_cost
);
930 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
931 new_i2_cost
, new_i3_cost
, new_cost
);
934 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
940 /* Update the uid_insn_cost array with the replacement costs. */
941 INSN_COST (i2
) = new_i2_cost
;
942 INSN_COST (i3
) = new_i3_cost
;
954 /* Delete any insns that copy a register to itself. */
957 delete_noop_moves (void)
964 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
966 next
= NEXT_INSN (insn
);
967 if (INSN_P (insn
) && noop_move_p (insn
))
970 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
972 delete_insn_and_edges (insn
);
979 /* Fill in log links field for all insns. */
982 create_log_links (void)
986 df_ref
*def_vec
, *use_vec
;
988 next_use
= XCNEWVEC (rtx
, max_reg_num ());
990 /* Pass through each block from the end, recording the uses of each
991 register and establishing log links when def is encountered.
992 Note that we do not clear next_use array in order to save time,
993 so we have to test whether the use is in the same basic block as def.
995 There are a few cases below when we do not consider the definition or
996 usage -- these are taken from original flow.c did. Don't ask me why it is
997 done this way; I don't know and if it works, I don't want to know. */
1001 FOR_BB_INSNS_REVERSE (bb
, insn
)
1003 if (!NONDEBUG_INSN_P (insn
))
1006 /* Log links are created only once. */
1007 gcc_assert (!LOG_LINKS (insn
));
1009 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
1011 df_ref def
= *def_vec
;
1012 int regno
= DF_REF_REGNO (def
);
1015 if (!next_use
[regno
])
1018 /* Do not consider if it is pre/post modification in MEM. */
1019 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1022 /* Do not make the log link for frame pointer. */
1023 if ((regno
== FRAME_POINTER_REGNUM
1024 && (! reload_completed
|| frame_pointer_needed
))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026 || (regno
== HARD_FRAME_POINTER_REGNUM
1027 && (! reload_completed
|| frame_pointer_needed
))
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1035 use_insn
= next_use
[regno
];
1036 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1040 We don't build a LOG_LINK for hard registers contained
1041 in ASM_OPERANDs. If these registers get replaced,
1042 we might wind up changing the semantics of the insn,
1043 even if reload can make what appear to be valid
1044 assignments later. */
1045 if (regno
>= FIRST_PSEUDO_REGISTER
1046 || asm_noperands (PATTERN (use_insn
)) < 0)
1048 /* Don't add duplicate links between instructions. */
1049 struct insn_link
*links
;
1050 FOR_EACH_LOG_LINK (links
, use_insn
)
1051 if (insn
== links
->insn
)
1055 LOG_LINKS (use_insn
)
1056 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1059 next_use
[regno
] = NULL_RTX
;
1062 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1064 df_ref use
= *use_vec
;
1065 int regno
= DF_REF_REGNO (use
);
1067 /* Do not consider the usage of the stack pointer
1068 by function call. */
1069 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1072 next_use
[regno
] = insn
;
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1081 true if we found a LOG_LINK that proves that A feeds B. This only works
1082 if there are no instructions between A and B which could have a link
1083 depending on A, since in that case we would not record a link for B.
1084 We also check the implicit dependency created by a cc0 setter/user
1088 insn_a_feeds_b (rtx a
, rtx b
)
1090 struct insn_link
*links
;
1091 FOR_EACH_LOG_LINK (links
, b
)
1092 if (links
->insn
== a
)
1101 /* Main entry point for combiner. F is the first insn of the function.
1102 NREGS is the first unused pseudo-reg number.
1104 Return nonzero if the combiner has turned an indirect jump
1105 instruction into a direct jump. */
1107 combine_instructions (rtx f
, unsigned int nregs
)
1113 struct insn_link
*links
, *nextlinks
;
1115 basic_block last_bb
;
1117 int new_direct_jump_p
= 0;
1119 for (first
= f
; first
&& !INSN_P (first
); )
1120 first
= NEXT_INSN (first
);
1124 combine_attempts
= 0;
1127 combine_successes
= 0;
1129 rtl_hooks
= combine_rtl_hooks
;
1131 reg_stat
.safe_grow_cleared (nregs
);
1133 init_recog_no_volatile ();
1135 /* Allocate array for insn info. */
1136 max_uid_known
= get_max_uid ();
1137 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1138 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1139 gcc_obstack_init (&insn_link_obstack
);
1141 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1143 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1144 problems when, for example, we have j <<= 1 in a loop. */
1146 nonzero_sign_valid
= 0;
1147 label_tick
= label_tick_ebb_start
= 1;
1149 /* Scan all SETs and see if we can deduce anything about what
1150 bits are known to be zero for some registers and how many copies
1151 of the sign bit are known to exist for those registers.
1153 Also set any known values so that we can use it while searching
1154 for what bits are known to be set. */
1156 setup_incoming_promotions (first
);
1157 /* Allow the entry block and the first block to fall into the same EBB.
1158 Conceptually the incoming promotions are assigned to the entry block. */
1159 last_bb
= ENTRY_BLOCK_PTR
;
1161 create_log_links ();
1162 FOR_EACH_BB (this_basic_block
)
1164 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1169 if (!single_pred_p (this_basic_block
)
1170 || single_pred (this_basic_block
) != last_bb
)
1171 label_tick_ebb_start
= label_tick
;
1172 last_bb
= this_basic_block
;
1174 FOR_BB_INSNS (this_basic_block
, insn
)
1175 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1181 subst_low_luid
= DF_INSN_LUID (insn
);
1184 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1186 record_dead_and_set_regs (insn
);
1189 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1190 if (REG_NOTE_KIND (links
) == REG_INC
)
1191 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1195 /* Record the current insn_rtx_cost of this instruction. */
1196 if (NONJUMP_INSN_P (insn
))
1197 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1198 optimize_this_for_speed_p
);
1200 fprintf (dump_file
, "insn_cost %d: %d\n",
1201 INSN_UID (insn
), INSN_COST (insn
));
1205 nonzero_sign_valid
= 1;
1207 /* Now scan all the insns in forward order. */
1208 label_tick
= label_tick_ebb_start
= 1;
1210 setup_incoming_promotions (first
);
1211 last_bb
= ENTRY_BLOCK_PTR
;
1213 FOR_EACH_BB (this_basic_block
)
1215 rtx last_combined_insn
= NULL_RTX
;
1216 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1221 if (!single_pred_p (this_basic_block
)
1222 || single_pred (this_basic_block
) != last_bb
)
1223 label_tick_ebb_start
= label_tick
;
1224 last_bb
= this_basic_block
;
1226 rtl_profile_for_bb (this_basic_block
);
1227 for (insn
= BB_HEAD (this_basic_block
);
1228 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1229 insn
= next
? next
: NEXT_INSN (insn
))
1232 if (NONDEBUG_INSN_P (insn
))
1234 while (last_combined_insn
1235 && INSN_DELETED_P (last_combined_insn
))
1236 last_combined_insn
= PREV_INSN (last_combined_insn
);
1237 if (last_combined_insn
== NULL_RTX
1238 || BARRIER_P (last_combined_insn
)
1239 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1240 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1241 last_combined_insn
= insn
;
1243 /* See if we know about function return values before this
1244 insn based upon SUBREG flags. */
1245 check_promoted_subreg (insn
, PATTERN (insn
));
1247 /* See if we can find hardregs and subreg of pseudos in
1248 narrower modes. This could help turning TRUNCATEs
1250 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1252 /* Try this insn with each insn it links back to. */
1254 FOR_EACH_LOG_LINK (links
, insn
)
1255 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1256 NULL_RTX
, &new_direct_jump_p
,
1257 last_combined_insn
)) != 0)
1260 /* Try each sequence of three linked insns ending with this one. */
1262 FOR_EACH_LOG_LINK (links
, insn
)
1264 rtx link
= links
->insn
;
1266 /* If the linked insn has been replaced by a note, then there
1267 is no point in pursuing this chain any further. */
1271 FOR_EACH_LOG_LINK (nextlinks
, link
)
1272 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1273 NULL_RTX
, &new_direct_jump_p
,
1274 last_combined_insn
)) != 0)
1279 /* Try to combine a jump insn that uses CC0
1280 with a preceding insn that sets CC0, and maybe with its
1281 logical predecessor as well.
1282 This is how we make decrement-and-branch insns.
1283 We need this special code because data flow connections
1284 via CC0 do not get entered in LOG_LINKS. */
1287 && (prev
= prev_nonnote_insn (insn
)) != 0
1288 && NONJUMP_INSN_P (prev
)
1289 && sets_cc0_p (PATTERN (prev
)))
1291 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1293 last_combined_insn
)) != 0)
1296 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1297 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1298 NULL_RTX
, &new_direct_jump_p
,
1299 last_combined_insn
)) != 0)
1303 /* Do the same for an insn that explicitly references CC0. */
1304 if (NONJUMP_INSN_P (insn
)
1305 && (prev
= prev_nonnote_insn (insn
)) != 0
1306 && NONJUMP_INSN_P (prev
)
1307 && sets_cc0_p (PATTERN (prev
))
1308 && GET_CODE (PATTERN (insn
)) == SET
1309 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1311 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1313 last_combined_insn
)) != 0)
1316 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1317 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1318 NULL_RTX
, &new_direct_jump_p
,
1319 last_combined_insn
)) != 0)
1323 /* Finally, see if any of the insns that this insn links to
1324 explicitly references CC0. If so, try this insn, that insn,
1325 and its predecessor if it sets CC0. */
1326 FOR_EACH_LOG_LINK (links
, insn
)
1327 if (NONJUMP_INSN_P (links
->insn
)
1328 && GET_CODE (PATTERN (links
->insn
)) == SET
1329 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1330 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1331 && NONJUMP_INSN_P (prev
)
1332 && sets_cc0_p (PATTERN (prev
))
1333 && (next
= try_combine (insn
, links
->insn
,
1334 prev
, NULL_RTX
, &new_direct_jump_p
,
1335 last_combined_insn
)) != 0)
1339 /* Try combining an insn with two different insns whose results it
1341 FOR_EACH_LOG_LINK (links
, insn
)
1342 for (nextlinks
= links
->next
; nextlinks
;
1343 nextlinks
= nextlinks
->next
)
1344 if ((next
= try_combine (insn
, links
->insn
,
1345 nextlinks
->insn
, NULL_RTX
,
1347 last_combined_insn
)) != 0)
1350 /* Try four-instruction combinations. */
1351 FOR_EACH_LOG_LINK (links
, insn
)
1353 struct insn_link
*next1
;
1354 rtx link
= links
->insn
;
1356 /* If the linked insn has been replaced by a note, then there
1357 is no point in pursuing this chain any further. */
1361 FOR_EACH_LOG_LINK (next1
, link
)
1363 rtx link1
= next1
->insn
;
1366 /* I0 -> I1 -> I2 -> I3. */
1367 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1368 if ((next
= try_combine (insn
, link
, link1
,
1371 last_combined_insn
)) != 0)
1373 /* I0, I1 -> I2, I2 -> I3. */
1374 for (nextlinks
= next1
->next
; nextlinks
;
1375 nextlinks
= nextlinks
->next
)
1376 if ((next
= try_combine (insn
, link
, link1
,
1379 last_combined_insn
)) != 0)
1383 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1385 rtx link1
= next1
->insn
;
1388 /* I0 -> I2; I1, I2 -> I3. */
1389 FOR_EACH_LOG_LINK (nextlinks
, link
)
1390 if ((next
= try_combine (insn
, link
, link1
,
1393 last_combined_insn
)) != 0)
1395 /* I0 -> I1; I1, I2 -> I3. */
1396 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1397 if ((next
= try_combine (insn
, link
, link1
,
1400 last_combined_insn
)) != 0)
1405 /* Try this insn with each REG_EQUAL note it links back to. */
1406 FOR_EACH_LOG_LINK (links
, insn
)
1409 rtx temp
= links
->insn
;
1410 if ((set
= single_set (temp
)) != 0
1411 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1412 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1413 /* Avoid using a register that may already been marked
1414 dead by an earlier instruction. */
1415 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1416 && (GET_MODE (note
) == VOIDmode
1417 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1418 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1420 /* Temporarily replace the set's source with the
1421 contents of the REG_EQUAL note. The insn will
1422 be deleted or recognized by try_combine. */
1423 rtx orig
= SET_SRC (set
);
1424 SET_SRC (set
) = note
;
1426 i2mod_old_rhs
= copy_rtx (orig
);
1427 i2mod_new_rhs
= copy_rtx (note
);
1428 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1430 last_combined_insn
);
1434 SET_SRC (set
) = orig
;
1439 record_dead_and_set_regs (insn
);
1447 default_rtl_profile ();
1449 new_direct_jump_p
|= purge_all_dead_edges ();
1450 delete_noop_moves ();
1453 obstack_free (&insn_link_obstack
, NULL
);
1454 free (uid_log_links
);
1455 free (uid_insn_cost
);
1456 reg_stat
.release ();
1459 struct undo
*undo
, *next
;
1460 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1468 total_attempts
+= combine_attempts
;
1469 total_merges
+= combine_merges
;
1470 total_extras
+= combine_extras
;
1471 total_successes
+= combine_successes
;
1473 nonzero_sign_valid
= 0;
1474 rtl_hooks
= general_rtl_hooks
;
1476 /* Make recognizer allow volatile MEMs again. */
1479 return new_direct_jump_p
;
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1485 init_reg_last (void)
1490 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1491 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1494 /* Set up any promoted values for incoming argument registers. */
1497 setup_incoming_promotions (rtx first
)
1500 bool strictly_local
= false;
1502 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1503 arg
= DECL_CHAIN (arg
))
1505 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1507 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1509 /* Only continue if the incoming argument is in a register. */
1513 /* Determine, if possible, whether all call sites of the current
1514 function lie within the current compilation unit. (This does
1515 take into account the exporting of a function via taking its
1516 address, and so forth.) */
1517 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1519 /* The mode and signedness of the argument before any promotions happen
1520 (equal to the mode of the pseudo holding it at that stage). */
1521 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1522 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1524 /* The mode and signedness of the argument after any source language and
1525 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1526 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1527 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1529 /* The mode and signedness of the argument as it is actually passed,
1530 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1531 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1532 TREE_TYPE (cfun
->decl
), 0);
1534 /* The mode of the register in which the argument is being passed. */
1535 mode4
= GET_MODE (reg
);
1537 /* Eliminate sign extensions in the callee when:
1538 (a) A mode promotion has occurred; */
1541 /* (b) The mode of the register is the same as the mode of
1542 the argument as it is passed; */
1545 /* (c) There's no language level extension; */
1548 /* (c.1) All callers are from the current compilation unit. If that's
1549 the case we don't have to rely on an ABI, we only have to know
1550 what we're generating right now, and we know that we will do the
1551 mode1 to mode2 promotion with the given sign. */
1552 else if (!strictly_local
)
1554 /* (c.2) The combination of the two promotions is useful. This is
1555 true when the signs match, or if the first promotion is unsigned.
1556 In the later case, (sign_extend (zero_extend x)) is the same as
1557 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1563 /* Record that the value was promoted from mode1 to mode3,
1564 so that any sign extension at the head of the current
1565 function may be eliminated. */
1566 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1567 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1568 record_value_for_reg (reg
, first
, x
);
1572 /* Called via note_stores. If X is a pseudo that is narrower than
1573 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1575 If we are setting only a portion of X and we can't figure out what
1576 portion, assume all bits will be used since we don't know what will
1579 Similarly, set how many bits of X are known to be copies of the sign bit
1580 at all locations in the function. This is the smallest number implied
1584 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1586 rtx insn
= (rtx
) data
;
1590 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1591 /* If this register is undefined at the start of the file, we can't
1592 say what its contents were. */
1593 && ! REGNO_REG_SET_P
1594 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1595 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1597 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1599 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1601 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1602 rsp
->sign_bit_copies
= 1;
1606 /* If this register is being initialized using itself, and the
1607 register is uninitialized in this basic block, and there are
1608 no LOG_LINKS which set the register, then part of the
1609 register is uninitialized. In that case we can't assume
1610 anything about the number of nonzero bits.
1612 ??? We could do better if we checked this in
1613 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1614 could avoid making assumptions about the insn which initially
1615 sets the register, while still using the information in other
1616 insns. We would have to be careful to check every insn
1617 involved in the combination. */
1620 && reg_referenced_p (x
, PATTERN (insn
))
1621 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1624 struct insn_link
*link
;
1626 FOR_EACH_LOG_LINK (link
, insn
)
1627 if (dead_or_set_p (link
->insn
, x
))
1631 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1632 rsp
->sign_bit_copies
= 1;
1637 /* If this is a complex assignment, see if we can convert it into a
1638 simple assignment. */
1639 set
= expand_field_assignment (set
);
1641 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642 set what we know about X. */
1644 if (SET_DEST (set
) == x
1645 || (paradoxical_subreg_p (SET_DEST (set
))
1646 && SUBREG_REG (SET_DEST (set
)) == x
))
1648 rtx src
= SET_SRC (set
);
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651 /* If X is narrower than a word and SRC is a non-negative
1652 constant that would appear negative in the mode of X,
1653 sign-extend it for use in reg_stat[].nonzero_bits because some
1654 machines (maybe most) will actually do the sign-extension
1655 and this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard
1658 instead of this kludge. */
1660 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1661 && CONST_INT_P (src
)
1663 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1664 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1667 /* Don't call nonzero_bits if it cannot change anything. */
1668 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1669 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1670 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1671 if (rsp
->sign_bit_copies
== 0
1672 || rsp
->sign_bit_copies
> num
)
1673 rsp
->sign_bit_copies
= num
;
1677 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1678 rsp
->sign_bit_copies
= 1;
1683 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1684 optionally insns that were previously combined into I3 or that will be
1685 combined into the merger of INSN and I3. The order is PRED, PRED2,
1686 INSN, SUCC, SUCC2, I3.
1688 Return 0 if the combination is not allowed for any reason.
1690 If the combination is allowed, *PDEST will be set to the single
1691 destination of INSN and *PSRC to the single source, and this function
1695 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1696 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1697 rtx
*pdest
, rtx
*psrc
)
1706 bool all_adjacent
= true;
1707 int (*is_volatile_p
) (const_rtx
);
1713 if (next_active_insn (succ2
) != i3
)
1714 all_adjacent
= false;
1715 if (next_active_insn (succ
) != succ2
)
1716 all_adjacent
= false;
1718 else if (next_active_insn (succ
) != i3
)
1719 all_adjacent
= false;
1720 if (next_active_insn (insn
) != succ
)
1721 all_adjacent
= false;
1723 else if (next_active_insn (insn
) != i3
)
1724 all_adjacent
= false;
1726 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727 or a PARALLEL consisting of such a SET and CLOBBERs.
1729 If INSN has CLOBBER parallel parts, ignore them for our processing.
1730 By definition, these happen during the execution of the insn. When it
1731 is merged with another insn, all bets are off. If they are, in fact,
1732 needed and aren't also supplied in I3, they may be added by
1733 recog_for_combine. Otherwise, it won't match.
1735 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1738 Get the source and destination of INSN. If more than one, can't
1741 if (GET_CODE (PATTERN (insn
)) == SET
)
1742 set
= PATTERN (insn
);
1743 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1744 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1746 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1748 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1750 switch (GET_CODE (elt
))
1752 /* This is important to combine floating point insns
1753 for the SH4 port. */
1755 /* Combining an isolated USE doesn't make sense.
1756 We depend here on combinable_i3pat to reject them. */
1757 /* The code below this loop only verifies that the inputs of
1758 the SET in INSN do not change. We call reg_set_between_p
1759 to verify that the REG in the USE does not change between
1761 If the USE in INSN was for a pseudo register, the matching
1762 insn pattern will likely match any register; combining this
1763 with any other USE would only be safe if we knew that the
1764 used registers have identical values, or if there was
1765 something to tell them apart, e.g. different modes. For
1766 now, we forgo such complicated tests and simply disallow
1767 combining of USES of pseudo registers with any other USE. */
1768 if (REG_P (XEXP (elt
, 0))
1769 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1771 rtx i3pat
= PATTERN (i3
);
1772 int i
= XVECLEN (i3pat
, 0) - 1;
1773 unsigned int regno
= REGNO (XEXP (elt
, 0));
1777 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1779 if (GET_CODE (i3elt
) == USE
1780 && REG_P (XEXP (i3elt
, 0))
1781 && (REGNO (XEXP (i3elt
, 0)) == regno
1782 ? reg_set_between_p (XEXP (elt
, 0),
1783 PREV_INSN (insn
), i3
)
1784 : regno
>= FIRST_PSEUDO_REGISTER
))
1791 /* We can ignore CLOBBERs. */
1796 /* Ignore SETs whose result isn't used but not those that
1797 have side-effects. */
1798 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1799 && insn_nothrow_p (insn
)
1800 && !side_effects_p (elt
))
1803 /* If we have already found a SET, this is a second one and
1804 so we cannot combine with this insn. */
1812 /* Anything else means we can't combine. */
1818 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819 so don't do anything with it. */
1820 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1829 /* The simplification in expand_field_assignment may call back to
1830 get_last_value, so set safe guard here. */
1831 subst_low_luid
= DF_INSN_LUID (insn
);
1833 set
= expand_field_assignment (set
);
1834 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1836 /* Don't eliminate a store in the stack pointer. */
1837 if (dest
== stack_pointer_rtx
1838 /* Don't combine with an insn that sets a register to itself if it has
1839 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1840 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1841 /* Can't merge an ASM_OPERANDS. */
1842 || GET_CODE (src
) == ASM_OPERANDS
1843 /* Can't merge a function call. */
1844 || GET_CODE (src
) == CALL
1845 /* Don't eliminate a function call argument. */
1847 && (find_reg_fusage (i3
, USE
, dest
)
1849 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1850 && global_regs
[REGNO (dest
)])))
1851 /* Don't substitute into an incremented register. */
1852 || FIND_REG_INC_NOTE (i3
, dest
)
1853 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1854 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1855 /* Don't substitute into a non-local goto, this confuses CFG. */
1856 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1857 /* Make sure that DEST is not used after SUCC but before I3. */
1860 && (reg_used_between_p (dest
, succ2
, i3
)
1861 || reg_used_between_p (dest
, succ
, succ2
)))
1862 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1863 /* Make sure that the value that is to be substituted for the register
1864 does not use any registers whose values alter in between. However,
1865 If the insns are adjacent, a use can't cross a set even though we
1866 think it might (this can happen for a sequence of insns each setting
1867 the same destination; last_set of that register might point to
1868 a NOTE). If INSN has a REG_EQUIV note, the register is always
1869 equivalent to the memory so the substitution is valid even if there
1870 are intervening stores. Also, don't move a volatile asm or
1871 UNSPEC_VOLATILE across any other insns. */
1874 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1875 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1876 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1877 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1878 /* Don't combine across a CALL_INSN, because that would possibly
1879 change whether the life span of some REGs crosses calls or not,
1880 and it is a pain to update that information.
1881 Exception: if source is a constant, moving it later can't hurt.
1882 Accept that as a special case. */
1883 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1886 /* DEST must either be a REG or CC0. */
1889 /* If register alignment is being enforced for multi-word items in all
1890 cases except for parameters, it is possible to have a register copy
1891 insn referencing a hard register that is not allowed to contain the
1892 mode being copied and which would not be valid as an operand of most
1893 insns. Eliminate this problem by not combining with such an insn.
1895 Also, on some machines we don't want to extend the life of a hard
1899 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1900 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1901 /* Don't extend the life of a hard register unless it is
1902 user variable (if we have few registers) or it can't
1903 fit into the desired register (meaning something special
1905 Also avoid substituting a return register into I3, because
1906 reload can't handle a conflict with constraints of other
1908 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1909 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1912 else if (GET_CODE (dest
) != CC0
)
1916 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1917 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1918 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1920 /* Don't substitute for a register intended as a clobberable
1922 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1923 if (rtx_equal_p (reg
, dest
))
1926 /* If the clobber represents an earlyclobber operand, we must not
1927 substitute an expression containing the clobbered register.
1928 As we do not analyze the constraint strings here, we have to
1929 make the conservative assumption. However, if the register is
1930 a fixed hard reg, the clobber cannot represent any operand;
1931 we leave it up to the machine description to either accept or
1932 reject use-and-clobber patterns. */
1934 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1935 || !fixed_regs
[REGNO (reg
)])
1936 if (reg_overlap_mentioned_p (reg
, src
))
1940 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941 or not), reject, unless nothing volatile comes between it and I3 */
1943 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1945 /* Make sure neither succ nor succ2 contains a volatile reference. */
1946 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1948 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1950 /* We'll check insns between INSN and I3 below. */
1953 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954 to be an explicit register variable, and was chosen for a reason. */
1956 if (GET_CODE (src
) == ASM_OPERANDS
1957 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1960 /* If INSN contains volatile references (specifically volatile MEMs),
1961 we cannot combine across any other volatile references.
1962 Even if INSN doesn't contain volatile references, any intervening
1963 volatile insn might affect machine state. */
1965 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
1969 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1970 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
1973 /* If INSN contains an autoincrement or autodecrement, make sure that
1974 register is not used between there and I3, and not already used in
1975 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1976 Also insist that I3 not be a jump; if it were one
1977 and the incremented register were spilled, we would lose. */
1980 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1981 if (REG_NOTE_KIND (link
) == REG_INC
1983 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1984 || (pred
!= NULL_RTX
1985 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1986 || (pred2
!= NULL_RTX
1987 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1988 || (succ
!= NULL_RTX
1989 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1990 || (succ2
!= NULL_RTX
1991 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1992 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1997 /* Don't combine an insn that follows a CC0-setting insn.
1998 An insn that uses CC0 must not be separated from the one that sets it.
1999 We do, however, allow I2 to follow a CC0-setting insn if that insn
2000 is passed as I1; in that case it will be deleted also.
2001 We also allow combining in this case if all the insns are adjacent
2002 because that would leave the two CC0 insns adjacent as well.
2003 It would be more logical to test whether CC0 occurs inside I1 or I2,
2004 but that would be much slower, and this ought to be equivalent. */
2006 p
= prev_nonnote_insn (insn
);
2007 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2012 /* If we get here, we have passed all the tests and the combination is
2021 /* LOC is the location within I3 that contains its pattern or the component
2022 of a PARALLEL of the pattern. We validate that it is valid for combining.
2024 One problem is if I3 modifies its output, as opposed to replacing it
2025 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026 doing so would produce an insn that is not equivalent to the original insns.
2030 (set (reg:DI 101) (reg:DI 100))
2031 (set (subreg:SI (reg:DI 101) 0) <foo>)
2033 This is NOT equivalent to:
2035 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036 (set (reg:DI 101) (reg:DI 100))])
2038 Not only does this modify 100 (in which case it might still be valid
2039 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2041 We can also run into a problem if I2 sets a register that I1
2042 uses and I1 gets directly substituted into I3 (not via I2). In that
2043 case, we would be getting the wrong value of I2DEST into I3, so we
2044 must reject the combination. This case occurs when I2 and I1 both
2045 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047 of a SET must prevent combination from occurring. The same situation
2048 can occur for I0, in which case I0_NOT_IN_SRC is set.
2050 Before doing the above check, we first try to expand a field assignment
2051 into a set of logical operations.
2053 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054 we place a register that is both set and used within I3. If more than one
2055 such register is detected, we fail.
2057 Return 1 if the combination is valid, zero otherwise. */
2060 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2061 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2065 if (GET_CODE (x
) == SET
)
2068 rtx dest
= SET_DEST (set
);
2069 rtx src
= SET_SRC (set
);
2070 rtx inner_dest
= dest
;
2073 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2074 || GET_CODE (inner_dest
) == SUBREG
2075 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2076 inner_dest
= XEXP (inner_dest
, 0);
2078 /* Check for the case where I3 modifies its output, as discussed
2079 above. We don't want to prevent pseudos from being combined
2080 into the address of a MEM, so only prevent the combination if
2081 i1 or i2 set the same MEM. */
2082 if ((inner_dest
!= dest
&&
2083 (!MEM_P (inner_dest
)
2084 || rtx_equal_p (i2dest
, inner_dest
)
2085 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2086 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2087 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2088 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2089 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2091 /* This is the same test done in can_combine_p except we can't test
2092 all_adjacent; we don't have to, since this instruction will stay
2093 in place, thus we are not considering increasing the lifetime of
2096 Also, if this insn sets a function argument, combining it with
2097 something that might need a spill could clobber a previous
2098 function argument; the all_adjacent test in can_combine_p also
2099 checks this; here, we do a more specific test for this case. */
2101 || (REG_P (inner_dest
)
2102 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2103 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2104 GET_MODE (inner_dest
))))
2105 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2106 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2109 /* If DEST is used in I3, it is being killed in this insn, so
2110 record that for later. We have to consider paradoxical
2111 subregs here, since they kill the whole register, but we
2112 ignore partial subregs, STRICT_LOW_PART, etc.
2113 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114 STACK_POINTER_REGNUM, since these are always considered to be
2115 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2117 if (GET_CODE (subdest
) == SUBREG
2118 && (GET_MODE_SIZE (GET_MODE (subdest
))
2119 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2120 subdest
= SUBREG_REG (subdest
);
2123 && reg_referenced_p (subdest
, PATTERN (i3
))
2124 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2130 || ! fixed_regs
[REGNO (subdest
)])
2132 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2134 if (*pi3dest_killed
)
2137 *pi3dest_killed
= subdest
;
2141 else if (GET_CODE (x
) == PARALLEL
)
2145 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2146 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2147 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155 and division. We don't count multiplications by powers of two here. */
2158 contains_muldiv (rtx x
)
2160 switch (GET_CODE (x
))
2162 case MOD
: case DIV
: case UMOD
: case UDIV
:
2166 return ! (CONST_INT_P (XEXP (x
, 1))
2167 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2170 return contains_muldiv (XEXP (x
, 0))
2171 || contains_muldiv (XEXP (x
, 1));
2174 return contains_muldiv (XEXP (x
, 0));
2180 /* Determine whether INSN can be used in a combination. Return nonzero if
2181 not. This is used in try_combine to detect early some cases where we
2182 can't perform combinations. */
2185 cant_combine_insn_p (rtx insn
)
2190 /* If this isn't really an insn, we can't do anything.
2191 This can occur when flow deletes an insn that it has merged into an
2192 auto-increment address. */
2193 if (! INSN_P (insn
))
2196 /* Never combine loads and stores involving hard regs that are likely
2197 to be spilled. The register allocator can usually handle such
2198 reg-reg moves by tying. If we allow the combiner to make
2199 substitutions of likely-spilled regs, reload might die.
2200 As an exception, we allow combinations involving fixed regs; these are
2201 not available to the register allocator so there's no risk involved. */
2203 set
= single_set (insn
);
2206 src
= SET_SRC (set
);
2207 dest
= SET_DEST (set
);
2208 if (GET_CODE (src
) == SUBREG
)
2209 src
= SUBREG_REG (src
);
2210 if (GET_CODE (dest
) == SUBREG
)
2211 dest
= SUBREG_REG (dest
);
2212 if (REG_P (src
) && REG_P (dest
)
2213 && ((HARD_REGISTER_P (src
)
2214 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2215 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2216 || (HARD_REGISTER_P (dest
)
2217 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2218 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2224 struct likely_spilled_retval_info
2226 unsigned regno
, nregs
;
2230 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2231 hard registers that are known to be written to / clobbered in full. */
2233 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2235 struct likely_spilled_retval_info
*const info
=
2236 (struct likely_spilled_retval_info
*) data
;
2237 unsigned regno
, nregs
;
2240 if (!REG_P (XEXP (set
, 0)))
2243 if (regno
>= info
->regno
+ info
->nregs
)
2245 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2246 if (regno
+ nregs
<= info
->regno
)
2248 new_mask
= (2U << (nregs
- 1)) - 1;
2249 if (regno
< info
->regno
)
2250 new_mask
>>= info
->regno
- regno
;
2252 new_mask
<<= regno
- info
->regno
;
2253 info
->mask
&= ~new_mask
;
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257 it is likely spilled. This can happen when more than one insn is needed
2258 to copy the return value, e.g. when we consider to combine into the
2259 second copy insn for a complex value. */
2262 likely_spilled_retval_p (rtx insn
)
2264 rtx use
= BB_END (this_basic_block
);
2266 unsigned regno
, nregs
;
2267 /* We assume here that no machine mode needs more than
2268 32 hard registers when the value overlaps with a register
2269 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2271 struct likely_spilled_retval_info info
;
2273 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2275 reg
= XEXP (PATTERN (use
), 0);
2276 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2278 regno
= REGNO (reg
);
2279 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2282 mask
= (2U << (nregs
- 1)) - 1;
2284 /* Disregard parts of the return value that are set later. */
2288 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2290 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2293 /* Check if any of the (probably) live return value registers is
2298 if ((mask
& 1 << nregs
)
2299 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2305 /* Adjust INSN after we made a change to its destination.
2307 Changing the destination can invalidate notes that say something about
2308 the results of the insn and a LOG_LINK pointing to the insn. */
2311 adjust_for_new_dest (rtx insn
)
2313 /* For notes, be conservative and simply remove them. */
2314 remove_reg_equal_equiv_notes (insn
);
2316 /* The new insn will have a destination that was previously the destination
2317 of an insn just above it. Call distribute_links to make a LOG_LINK from
2318 the next use of that destination. */
2319 distribute_links (alloc_insn_link (insn
, NULL
));
2321 df_insn_rescan (insn
);
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325 ADDED_SETS is nonzero if the original set is still required. */
2327 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2335 /* Allow hard registers if the new mode is legal, and occupies no more
2336 registers than the old mode. */
2337 if (regno
< FIRST_PSEUDO_REGISTER
)
2338 return (HARD_REGNO_MODE_OK (regno
, mode
)
2339 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2340 >= hard_regno_nregs
[regno
][mode
]));
2342 /* Or a pseudo that is only used once. */
2343 return (REG_N_SETS (regno
) == 1 && !added_sets
2344 && !REG_USERVAR_P (x
));
2348 /* Check whether X, the destination of a set, refers to part of
2349 the register specified by REG. */
2352 reg_subword_p (rtx x
, rtx reg
)
2354 /* Check that reg is an integer mode register. */
2355 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2358 if (GET_CODE (x
) == STRICT_LOW_PART
2359 || GET_CODE (x
) == ZERO_EXTRACT
)
2362 return GET_CODE (x
) == SUBREG
2363 && SUBREG_REG (x
) == reg
2364 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368 Note that the INSN should be deleted *after* removing dead edges, so
2369 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370 but not for a (set (pc) (label_ref FOO)). */
2373 update_cfg_for_uncondjump (rtx insn
)
2375 basic_block bb
= BLOCK_FOR_INSN (insn
);
2376 gcc_assert (BB_END (bb
) == insn
);
2378 purge_dead_edges (bb
);
2381 if (EDGE_COUNT (bb
->succs
) == 1)
2385 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2387 /* Remove barriers from the footer if there are any. */
2388 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2389 if (BARRIER_P (insn
))
2391 if (PREV_INSN (insn
))
2392 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2394 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2395 if (NEXT_INSN (insn
))
2396 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2398 else if (LABEL_P (insn
))
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404 Here I0, I1 and I2 appear earlier than I3.
2405 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2408 If we are combining more than two insns and the resulting insn is not
2409 recognized, try splitting it into two insns. If that happens, I2 and I3
2410 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411 Otherwise, I0, I1 and I2 are pseudo-deleted.
2413 Return 0 if the combination does not work. Then nothing is changed.
2414 If we did the combination, return the insn at which combine should
2417 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418 new direct jump instruction.
2420 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421 been I3 passed to an earlier try_combine within the same basic
2425 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2426 rtx last_combined_insn
)
2428 /* New patterns for I3 and I2, respectively. */
2429 rtx newpat
, newi2pat
= 0;
2430 rtvec newpat_vec_with_clobbers
= 0;
2431 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2432 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2434 int added_sets_0
, added_sets_1
, added_sets_2
;
2435 /* Total number of SETs to put into I3. */
2437 /* Nonzero if I2's or I1's body now appears in I3. */
2438 int i2_is_used
= 0, i1_is_used
= 0;
2439 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2440 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2441 /* Contains I3 if the destination of I3 is used in its source, which means
2442 that the old life of I3 is being killed. If that usage is placed into
2443 I2 and not in I3, a REG_DEAD note must be made. */
2444 rtx i3dest_killed
= 0;
2445 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2446 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2447 /* Copy of SET_SRC of I1 and I0, if needed. */
2448 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2449 /* Set if I2DEST was reused as a scratch register. */
2450 bool i2scratch
= false;
2451 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2452 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2453 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2454 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2455 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2456 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2457 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2458 /* Notes that must be added to REG_NOTES in I3 and I2. */
2459 rtx new_i3_notes
, new_i2_notes
;
2460 /* Notes that we substituted I3 into I2 instead of the normal case. */
2461 int i3_subst_into_i2
= 0;
2462 /* Notes that I1, I2 or I3 is a MULT operation. */
2465 int changed_i3_dest
= 0;
2469 struct insn_link
*link
;
2471 rtx new_other_notes
;
2474 /* Only try four-insn combinations when there's high likelihood of
2475 success. Look for simple insns, such as loads of constants or
2476 binary operations involving a constant. */
2483 if (!flag_expensive_optimizations
)
2486 for (i
= 0; i
< 4; i
++)
2488 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2489 rtx set
= single_set (insn
);
2493 src
= SET_SRC (set
);
2494 if (CONSTANT_P (src
))
2499 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2501 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2502 || GET_CODE (src
) == LSHIFTRT
)
2505 if (ngood
< 2 && nshift
< 2)
2509 /* Exit early if one of the insns involved can't be used for
2511 if (cant_combine_insn_p (i3
)
2512 || cant_combine_insn_p (i2
)
2513 || (i1
&& cant_combine_insn_p (i1
))
2514 || (i0
&& cant_combine_insn_p (i0
))
2515 || likely_spilled_retval_p (i3
))
2519 undobuf
.other_insn
= 0;
2521 /* Reset the hard register usage information. */
2522 CLEAR_HARD_REG_SET (newpat_used_regs
);
2524 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2527 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2528 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2530 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2531 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2533 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2534 INSN_UID (i2
), INSN_UID (i3
));
2537 /* If multiple insns feed into one of I2 or I3, they can be in any
2538 order. To simplify the code below, reorder them in sequence. */
2539 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2540 temp
= i2
, i2
= i0
, i0
= temp
;
2541 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2542 temp
= i1
, i1
= i0
, i0
= temp
;
2543 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2544 temp
= i1
, i1
= i2
, i2
= temp
;
2546 added_links_insn
= 0;
2548 /* First check for one important special case that the code below will
2549 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2550 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2551 we may be able to replace that destination with the destination of I3.
2552 This occurs in the common code where we compute both a quotient and
2553 remainder into a structure, in which case we want to do the computation
2554 directly into the structure to avoid register-register copies.
2556 Note that this case handles both multiple sets in I2 and also cases
2557 where I2 has a number of CLOBBERs inside the PARALLEL.
2559 We make very conservative checks below and only try to handle the
2560 most common cases of this. For example, we only handle the case
2561 where I2 and I3 are adjacent to avoid making difficult register
2564 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2565 && REG_P (SET_SRC (PATTERN (i3
)))
2566 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2567 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2568 && GET_CODE (PATTERN (i2
)) == PARALLEL
2569 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2570 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571 below would need to check what is inside (and reg_overlap_mentioned_p
2572 doesn't support those codes anyway). Don't allow those destinations;
2573 the resulting insn isn't likely to be recognized anyway. */
2574 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2575 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2576 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2577 SET_DEST (PATTERN (i3
)))
2578 && next_active_insn (i2
) == i3
)
2580 rtx p2
= PATTERN (i2
);
2582 /* Make sure that the destination of I3,
2583 which we are going to substitute into one output of I2,
2584 is not used within another output of I2. We must avoid making this:
2585 (parallel [(set (mem (reg 69)) ...)
2586 (set (reg 69) ...)])
2587 which is not well-defined as to order of actions.
2588 (Besides, reload can't handle output reloads for this.)
2590 The problem can also happen if the dest of I3 is a memory ref,
2591 if another dest in I2 is an indirect memory ref. */
2592 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2593 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2594 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2595 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2596 SET_DEST (XVECEXP (p2
, 0, i
))))
2599 if (i
== XVECLEN (p2
, 0))
2600 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2601 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2602 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2607 subst_low_luid
= DF_INSN_LUID (i2
);
2609 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2610 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2611 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2612 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2614 /* Replace the dest in I2 with our dest and make the resulting
2615 insn the new pattern for I3. Then skip to where we validate
2616 the pattern. Everything was set up above. */
2617 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2619 i3_subst_into_i2
= 1;
2620 goto validate_replacement
;
2624 /* If I2 is setting a pseudo to a constant and I3 is setting some
2625 sub-part of it to another constant, merge them by making a new
2628 && (temp
= single_set (i2
)) != 0
2629 && CONST_SCALAR_INT_P (SET_SRC (temp
))
2630 && GET_CODE (PATTERN (i3
)) == SET
2631 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2632 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2634 rtx dest
= SET_DEST (PATTERN (i3
));
2638 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2640 if (CONST_INT_P (XEXP (dest
, 1))
2641 && CONST_INT_P (XEXP (dest
, 2)))
2643 width
= INTVAL (XEXP (dest
, 1));
2644 offset
= INTVAL (XEXP (dest
, 2));
2645 dest
= XEXP (dest
, 0);
2646 if (BITS_BIG_ENDIAN
)
2647 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2652 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2653 dest
= XEXP (dest
, 0);
2654 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2660 /* If this is the low part, we're done. */
2661 if (subreg_lowpart_p (dest
))
2663 /* Handle the case where inner is twice the size of outer. */
2664 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2665 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2666 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2667 /* Otherwise give up for now. */
2674 rtx inner
= SET_SRC (PATTERN (i3
));
2675 rtx outer
= SET_SRC (temp
);
2678 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp
))),
2679 std::make_pair (inner
, GET_MODE (dest
)),
2684 subst_low_luid
= DF_INSN_LUID (i2
);
2685 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2686 i2dest
= SET_DEST (temp
);
2687 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2689 /* Replace the source in I2 with the new constant and make the
2690 resulting insn the new pattern for I3. Then skip to where we
2691 validate the pattern. Everything was set up above. */
2692 SUBST (SET_SRC (temp
),
2693 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp
))));
2695 newpat
= PATTERN (i2
);
2697 /* The dest of I3 has been replaced with the dest of I2. */
2698 changed_i3_dest
= 1;
2699 goto validate_replacement
;
2704 /* If we have no I1 and I2 looks like:
2705 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2707 make up a dummy I1 that is
2710 (set (reg:CC X) (compare:CC Y (const_int 0)))
2712 (We can ignore any trailing CLOBBERs.)
2714 This undoes a previous combination and allows us to match a branch-and-
2717 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2718 && XVECLEN (PATTERN (i2
), 0) >= 2
2719 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2720 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2722 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2723 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2724 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2725 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2726 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2727 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2729 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2730 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2735 /* We make I1 with the same INSN_UID as I2. This gives it
2736 the same DF_INSN_LUID for value tracking. Our fake I1 will
2737 never appear in the insn stream so giving it the same INSN_UID
2738 as I2 will not cause a problem. */
2740 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2741 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2742 INSN_LOCATION (i2
), -1, NULL_RTX
);
2744 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2745 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2746 SET_DEST (PATTERN (i1
)));
2747 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2752 /* Verify that I2 and I1 are valid for combining. */
2753 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2754 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2756 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2763 /* Record whether I2DEST is used in I2SRC and similarly for the other
2764 cases. Knowing this will help in register status updating below. */
2765 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2766 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2767 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2768 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2769 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2770 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2771 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2772 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2773 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2775 /* For the earlier insns, determine which of the subsequent ones they
2777 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2778 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2779 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2780 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2781 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2783 /* Ensure that I3's pattern can be the destination of combines. */
2784 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2785 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2786 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2787 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2794 /* See if any of the insns is a MULT operation. Unless one is, we will
2795 reject a combination that is, since it must be slower. Be conservative
2797 if (GET_CODE (i2src
) == MULT
2798 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2799 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2800 || (GET_CODE (PATTERN (i3
)) == SET
2801 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2805 We used to do this EXCEPT in one case: I3 has a post-inc in an
2806 output operand. However, that exception can give rise to insns like
2808 which is a famous insn on the PDP-11 where the value of r3 used as the
2809 source was model-dependent. Avoid this sort of thing. */
2812 if (!(GET_CODE (PATTERN (i3
)) == SET
2813 && REG_P (SET_SRC (PATTERN (i3
)))
2814 && MEM_P (SET_DEST (PATTERN (i3
)))
2815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2817 /* It's not the exception. */
2822 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2823 if (REG_NOTE_KIND (link
) == REG_INC
2824 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2826 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2834 /* See if the SETs in I1 or I2 need to be kept around in the merged
2835 instruction: whenever the value set there is still needed past I3.
2836 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2838 For the SET in I1, we have two cases: if I1 and I2 independently feed
2839 into I3, the set in I1 needs to be kept around unless I1DEST dies
2840 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2841 in I1 needs to be kept around unless I1DEST dies or is set in either
2842 I2 or I3. The same considerations apply to I0. */
2844 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2847 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2848 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2853 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2854 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2855 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2856 && dead_or_set_p (i2
, i0dest
)));
2860 /* We are about to copy insns for the case where they need to be kept
2861 around. Check that they can be copied in the merged instruction. */
2863 if (targetm
.cannot_copy_insn_p
2864 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2865 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2866 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2872 /* If the set in I2 needs to be kept around, we must make a copy of
2873 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2874 PATTERN (I2), we are only substituting for the original I1DEST, not into
2875 an already-substituted copy. This also prevents making self-referential
2876 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2881 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2882 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2884 i2pat
= copy_rtx (PATTERN (i2
));
2889 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2890 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2892 i1pat
= copy_rtx (PATTERN (i1
));
2897 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2898 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2900 i0pat
= copy_rtx (PATTERN (i0
));
2905 /* Substitute in the latest insn for the regs set by the earlier ones. */
2907 maxreg
= max_reg_num ();
2912 /* Many machines that don't use CC0 have insns that can both perform an
2913 arithmetic operation and set the condition code. These operations will
2914 be represented as a PARALLEL with the first element of the vector
2915 being a COMPARE of an arithmetic operation with the constant zero.
2916 The second element of the vector will set some pseudo to the result
2917 of the same arithmetic operation. If we simplify the COMPARE, we won't
2918 match such a pattern and so will generate an extra insn. Here we test
2919 for this case, where both the comparison and the operation result are
2920 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2921 I2SRC. Later we will make the PARALLEL that contains I2. */
2923 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2924 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2925 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2926 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2929 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
2930 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2931 enum machine_mode compare_mode
, orig_compare_mode
;
2932 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2934 newpat
= PATTERN (i3
);
2935 newpat_dest
= SET_DEST (newpat
);
2936 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2938 if (undobuf
.other_insn
== 0
2939 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2942 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2943 compare_code
= simplify_compare_const (compare_code
,
2945 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2948 /* Do the rest only if op1 is const0_rtx, which may be the
2949 result of simplification. */
2950 if (op1
== const0_rtx
)
2952 /* If a single use of the CC is found, prepare to modify it
2953 when SELECT_CC_MODE returns a new CC-class mode, or when
2954 the above simplify_compare_const() returned a new comparison
2955 operator. undobuf.other_insn is assigned the CC use insn
2956 when modifying it. */
2959 #ifdef SELECT_CC_MODE
2960 enum machine_mode new_mode
2961 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2962 if (new_mode
!= orig_compare_mode
2963 && can_change_dest_mode (SET_DEST (newpat
),
2964 added_sets_2
, new_mode
))
2966 unsigned int regno
= REGNO (newpat_dest
);
2967 compare_mode
= new_mode
;
2968 if (regno
< FIRST_PSEUDO_REGISTER
)
2969 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
2972 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2973 newpat_dest
= regno_reg_rtx
[regno
];
2977 /* Cases for modifying the CC-using comparison. */
2978 if (compare_code
!= orig_compare_code
2979 /* ??? Do we need to verify the zero rtx? */
2980 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
2982 /* Replace cc_use_loc with entire new RTX. */
2984 gen_rtx_fmt_ee (compare_code
, compare_mode
,
2985 newpat_dest
, const0_rtx
));
2986 undobuf
.other_insn
= cc_use_insn
;
2988 else if (compare_mode
!= orig_compare_mode
)
2990 /* Just replace the CC reg with a new mode. */
2991 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
2992 undobuf
.other_insn
= cc_use_insn
;
2996 /* Now we modify the current newpat:
2997 First, SET_DEST(newpat) is updated if the CC mode has been
2998 altered. For targets without SELECT_CC_MODE, this should be
3000 if (compare_mode
!= orig_compare_mode
)
3001 SUBST (SET_DEST (newpat
), newpat_dest
);
3002 /* This is always done to propagate i2src into newpat. */
3003 SUBST (SET_SRC (newpat
),
3004 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3005 /* Create new version of i2pat if needed; the below PARALLEL
3006 creation needs this to work correctly. */
3007 if (! rtx_equal_p (i2src
, op0
))
3008 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3014 if (i2_is_used
== 0)
3016 /* It is possible that the source of I2 or I1 may be performing
3017 an unneeded operation, such as a ZERO_EXTEND of something
3018 that is known to have the high part zero. Handle that case
3019 by letting subst look at the inner insns.
3021 Another way to do this would be to have a function that tries
3022 to simplify a single insn instead of merging two or more
3023 insns. We don't do this because of the potential of infinite
3024 loops and because of the potential extra memory required.
3025 However, doing it the way we are is a bit of a kludge and
3026 doesn't catch all cases.
3028 But only do this if -fexpensive-optimizations since it slows
3029 things down and doesn't usually win.
3031 This is not done in the COMPARE case above because the
3032 unmodified I2PAT is used in the PARALLEL and so a pattern
3033 with a modified I2SRC would not match. */
3035 if (flag_expensive_optimizations
)
3037 /* Pass pc_rtx so no substitutions are done, just
3041 subst_low_luid
= DF_INSN_LUID (i1
);
3042 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3045 subst_low_luid
= DF_INSN_LUID (i2
);
3046 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3049 n_occurrences
= 0; /* `subst' counts here */
3050 subst_low_luid
= DF_INSN_LUID (i2
);
3052 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3053 copy of I2SRC each time we substitute it, in order to avoid creating
3054 self-referential RTL when we will be substituting I1SRC for I1DEST
3055 later. Likewise if I0 feeds into I2, either directly or indirectly
3056 through I1, and I0DEST is in I0SRC. */
3057 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3058 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3059 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3060 && i0dest_in_i0src
));
3063 /* Record whether I2's body now appears within I3's body. */
3064 i2_is_used
= n_occurrences
;
3067 /* If we already got a failure, don't try to do more. Otherwise, try to
3068 substitute I1 if we have it. */
3070 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3072 /* Check that an autoincrement side-effect on I1 has not been lost.
3073 This happens if I1DEST is mentioned in I2 and dies there, and
3074 has disappeared from the new pattern. */
3075 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3077 && dead_or_set_p (i2
, i1dest
)
3078 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3079 /* Before we can do this substitution, we must redo the test done
3080 above (see detailed comments there) that ensures I1DEST isn't
3081 mentioned in any SETs in NEWPAT that are field assignments. */
3082 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3090 subst_low_luid
= DF_INSN_LUID (i1
);
3092 /* If the following substitution will modify I1SRC, make a copy of it
3093 for the case where it is substituted for I1DEST in I2PAT later. */
3094 if (added_sets_2
&& i1_feeds_i2_n
)
3095 i1src_copy
= copy_rtx (i1src
);
3097 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3098 copy of I1SRC each time we substitute it, in order to avoid creating
3099 self-referential RTL when we will be substituting I0SRC for I0DEST
3101 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3102 i0_feeds_i1_n
&& i0dest_in_i0src
);
3105 /* Record whether I1's body now appears within I3's body. */
3106 i1_is_used
= n_occurrences
;
3109 /* Likewise for I0 if we have it. */
3111 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3113 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3114 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3115 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3116 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3117 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3124 /* If the following substitution will modify I0SRC, make a copy of it
3125 for the case where it is substituted for I0DEST in I1PAT later. */
3126 if (added_sets_1
&& i0_feeds_i1_n
)
3127 i0src_copy
= copy_rtx (i0src
);
3128 /* And a copy for I0DEST in I2PAT substitution. */
3129 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3130 || (i0_feeds_i2_n
)))
3131 i0src_copy2
= copy_rtx (i0src
);
3134 subst_low_luid
= DF_INSN_LUID (i0
);
3135 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3139 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3140 to count all the ways that I2SRC and I1SRC can be used. */
3141 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3142 && i2_is_used
+ added_sets_2
> 1)
3143 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3144 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3146 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3147 && (n_occurrences
+ added_sets_0
3148 + (added_sets_1
&& i0_feeds_i1_n
)
3149 + (added_sets_2
&& i0_feeds_i2_n
)
3151 /* Fail if we tried to make a new register. */
3152 || max_reg_num () != maxreg
3153 /* Fail if we couldn't do something and have a CLOBBER. */
3154 || GET_CODE (newpat
) == CLOBBER
3155 /* Fail if this new pattern is a MULT and we didn't have one before
3156 at the outer level. */
3157 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3164 /* If the actions of the earlier insns must be kept
3165 in addition to substituting them into the latest one,
3166 we must make a new PARALLEL for the latest insn
3167 to hold additional the SETs. */
3169 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3171 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3174 if (GET_CODE (newpat
) == PARALLEL
)
3176 rtvec old
= XVEC (newpat
, 0);
3177 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3178 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3179 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3180 sizeof (old
->elem
[0]) * old
->num_elem
);
3185 total_sets
= 1 + extra_sets
;
3186 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3187 XVECEXP (newpat
, 0, 0) = old
;
3191 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3197 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3199 XVECEXP (newpat
, 0, --total_sets
) = t
;
3205 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3206 i0_feeds_i1_n
&& i0dest_in_i0src
);
3207 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3208 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3210 XVECEXP (newpat
, 0, --total_sets
) = t
;
3214 validate_replacement
:
3216 /* Note which hard regs this insn has as inputs. */
3217 mark_used_regs_combine (newpat
);
3219 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3220 consider splitting this pattern, we might need these clobbers. */
3221 if (i1
&& GET_CODE (newpat
) == PARALLEL
3222 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3224 int len
= XVECLEN (newpat
, 0);
3226 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3227 for (i
= 0; i
< len
; i
++)
3228 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3231 /* Is the result of combination a valid instruction? */
3232 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3234 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3235 the second SET's destination is a register that is unused and isn't
3236 marked as an instruction that might trap in an EH region. In that case,
3237 we just need the first SET. This can occur when simplifying a divmod
3238 insn. We *must* test for this case here because the code below that
3239 splits two independent SETs doesn't handle this case correctly when it
3240 updates the register status.
3242 It's pointless doing this if we originally had two sets, one from
3243 i3, and one from i2. Combining then splitting the parallel results
3244 in the original i2 again plus an invalid insn (which we delete).
3245 The net effect is only to move instructions around, which makes
3246 debug info less accurate.
3248 Also check the case where the first SET's destination is unused.
3249 That would not cause incorrect code, but does cause an unneeded
3252 if (insn_code_number
< 0
3253 && !(added_sets_2
&& i1
== 0)
3254 && GET_CODE (newpat
) == PARALLEL
3255 && XVECLEN (newpat
, 0) == 2
3256 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3257 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3258 && asm_noperands (newpat
) < 0)
3260 rtx set0
= XVECEXP (newpat
, 0, 0);
3261 rtx set1
= XVECEXP (newpat
, 0, 1);
3263 if (((REG_P (SET_DEST (set1
))
3264 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3265 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3266 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3267 && insn_nothrow_p (i3
)
3268 && !side_effects_p (SET_SRC (set1
)))
3271 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3274 else if (((REG_P (SET_DEST (set0
))
3275 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3276 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3277 && find_reg_note (i3
, REG_UNUSED
,
3278 SUBREG_REG (SET_DEST (set0
)))))
3279 && insn_nothrow_p (i3
)
3280 && !side_effects_p (SET_SRC (set0
)))
3283 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3285 if (insn_code_number
>= 0)
3286 changed_i3_dest
= 1;
3290 /* If we were combining three insns and the result is a simple SET
3291 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3292 insns. There are two ways to do this. It can be split using a
3293 machine-specific method (like when you have an addition of a large
3294 constant) or by combine in the function find_split_point. */
3296 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3297 && asm_noperands (newpat
) < 0)
3299 rtx parallel
, m_split
, *split
;
3301 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3302 use I2DEST as a scratch register will help. In the latter case,
3303 convert I2DEST to the mode of the source of NEWPAT if we can. */
3305 m_split
= combine_split_insns (newpat
, i3
);
3307 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3308 inputs of NEWPAT. */
3310 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3311 possible to try that as a scratch reg. This would require adding
3312 more code to make it work though. */
3314 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3316 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3318 /* First try to split using the original register as a
3319 scratch register. */
3320 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3321 gen_rtvec (2, newpat
,
3322 gen_rtx_CLOBBER (VOIDmode
,
3324 m_split
= combine_split_insns (parallel
, i3
);
3326 /* If that didn't work, try changing the mode of I2DEST if
3329 && new_mode
!= GET_MODE (i2dest
)
3330 && new_mode
!= VOIDmode
3331 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3333 enum machine_mode old_mode
= GET_MODE (i2dest
);
3336 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3337 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3340 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3341 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3344 parallel
= (gen_rtx_PARALLEL
3346 gen_rtvec (2, newpat
,
3347 gen_rtx_CLOBBER (VOIDmode
,
3349 m_split
= combine_split_insns (parallel
, i3
);
3352 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3356 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3357 buf
= undobuf
.undos
;
3358 undobuf
.undos
= buf
->next
;
3359 buf
->next
= undobuf
.frees
;
3360 undobuf
.frees
= buf
;
3364 i2scratch
= m_split
!= 0;
3367 /* If recog_for_combine has discarded clobbers, try to use them
3368 again for the split. */
3369 if (m_split
== 0 && newpat_vec_with_clobbers
)
3371 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3372 m_split
= combine_split_insns (parallel
, i3
);
3375 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3377 m_split
= PATTERN (m_split
);
3378 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3379 if (insn_code_number
>= 0)
3382 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3383 && (next_nonnote_nondebug_insn (i2
) == i3
3384 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3387 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3388 newi2pat
= PATTERN (m_split
);
3390 i3set
= single_set (NEXT_INSN (m_split
));
3391 i2set
= single_set (m_split
);
3393 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3395 /* If I2 or I3 has multiple SETs, we won't know how to track
3396 register status, so don't use these insns. If I2's destination
3397 is used between I2 and I3, we also can't use these insns. */
3399 if (i2_code_number
>= 0 && i2set
&& i3set
3400 && (next_nonnote_nondebug_insn (i2
) == i3
3401 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3402 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3404 if (insn_code_number
>= 0)
3407 /* It is possible that both insns now set the destination of I3.
3408 If so, we must show an extra use of it. */
3410 if (insn_code_number
>= 0)
3412 rtx new_i3_dest
= SET_DEST (i3set
);
3413 rtx new_i2_dest
= SET_DEST (i2set
);
3415 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3416 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3417 || GET_CODE (new_i3_dest
) == SUBREG
)
3418 new_i3_dest
= XEXP (new_i3_dest
, 0);
3420 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3421 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3422 || GET_CODE (new_i2_dest
) == SUBREG
)
3423 new_i2_dest
= XEXP (new_i2_dest
, 0);
3425 if (REG_P (new_i3_dest
)
3426 && REG_P (new_i2_dest
)
3427 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3428 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3432 /* If we can split it and use I2DEST, go ahead and see if that
3433 helps things be recognized. Verify that none of the registers
3434 are set between I2 and I3. */
3435 if (insn_code_number
< 0
3436 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3440 /* We need I2DEST in the proper mode. If it is a hard register
3441 or the only use of a pseudo, we can change its mode.
3442 Make sure we don't change a hard register to have a mode that
3443 isn't valid for it, or change the number of registers. */
3444 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3445 || GET_MODE (*split
) == VOIDmode
3446 || can_change_dest_mode (i2dest
, added_sets_2
,
3448 && (next_nonnote_nondebug_insn (i2
) == i3
3449 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3450 /* We can't overwrite I2DEST if its value is still used by
3452 && ! reg_referenced_p (i2dest
, newpat
))
3454 rtx newdest
= i2dest
;
3455 enum rtx_code split_code
= GET_CODE (*split
);
3456 enum machine_mode split_mode
= GET_MODE (*split
);
3457 bool subst_done
= false;
3458 newi2pat
= NULL_RTX
;
3462 /* *SPLIT may be part of I2SRC, so make sure we have the
3463 original expression around for later debug processing.
3464 We should not need I2SRC any more in other cases. */
3465 if (MAY_HAVE_DEBUG_INSNS
)
3466 i2src
= copy_rtx (i2src
);
3470 /* Get NEWDEST as a register in the proper mode. We have already
3471 validated that we can do this. */
3472 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3474 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3475 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3478 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3479 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3483 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3484 an ASHIFT. This can occur if it was inside a PLUS and hence
3485 appeared to be a memory address. This is a kludge. */
3486 if (split_code
== MULT
3487 && CONST_INT_P (XEXP (*split
, 1))
3488 && INTVAL (XEXP (*split
, 1)) > 0
3489 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3491 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3492 XEXP (*split
, 0), GEN_INT (i
)));
3493 /* Update split_code because we may not have a multiply
3495 split_code
= GET_CODE (*split
);
3498 #ifdef INSN_SCHEDULING
3499 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3500 be written as a ZERO_EXTEND. */
3501 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3503 #ifdef LOAD_EXTEND_OP
3504 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3505 what it really is. */
3506 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3508 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3509 SUBREG_REG (*split
)));
3512 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3513 SUBREG_REG (*split
)));
3517 /* Attempt to split binary operators using arithmetic identities. */
3518 if (BINARY_P (SET_SRC (newpat
))
3519 && split_mode
== GET_MODE (SET_SRC (newpat
))
3520 && ! side_effects_p (SET_SRC (newpat
)))
3522 rtx setsrc
= SET_SRC (newpat
);
3523 enum machine_mode mode
= GET_MODE (setsrc
);
3524 enum rtx_code code
= GET_CODE (setsrc
);
3525 rtx src_op0
= XEXP (setsrc
, 0);
3526 rtx src_op1
= XEXP (setsrc
, 1);
3528 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3529 if (rtx_equal_p (src_op0
, src_op1
))
3531 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3532 SUBST (XEXP (setsrc
, 0), newdest
);
3533 SUBST (XEXP (setsrc
, 1), newdest
);
3536 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3537 else if ((code
== PLUS
|| code
== MULT
)
3538 && GET_CODE (src_op0
) == code
3539 && GET_CODE (XEXP (src_op0
, 0)) == code
3540 && (INTEGRAL_MODE_P (mode
)
3541 || (FLOAT_MODE_P (mode
)
3542 && flag_unsafe_math_optimizations
)))
3544 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3545 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3546 rtx r
= XEXP (src_op0
, 1);
3549 /* Split both "((X op Y) op X) op Y" and
3550 "((X op Y) op Y) op X" as "T op T" where T is
3552 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3553 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3555 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3557 SUBST (XEXP (setsrc
, 0), newdest
);
3558 SUBST (XEXP (setsrc
, 1), newdest
);
3561 /* Split "((X op X) op Y) op Y)" as "T op T" where
3563 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3565 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3566 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3567 SUBST (XEXP (setsrc
, 0), newdest
);
3568 SUBST (XEXP (setsrc
, 1), newdest
);
3576 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3577 SUBST (*split
, newdest
);
3580 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3582 /* recog_for_combine might have added CLOBBERs to newi2pat.
3583 Make sure NEWPAT does not depend on the clobbered regs. */
3584 if (GET_CODE (newi2pat
) == PARALLEL
)
3585 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3586 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3588 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3589 if (reg_overlap_mentioned_p (reg
, newpat
))
3596 /* If the split point was a MULT and we didn't have one before,
3597 don't use one now. */
3598 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3599 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3603 /* Check for a case where we loaded from memory in a narrow mode and
3604 then sign extended it, but we need both registers. In that case,
3605 we have a PARALLEL with both loads from the same memory location.
3606 We can split this into a load from memory followed by a register-register
3607 copy. This saves at least one insn, more if register allocation can
3610 We cannot do this if the destination of the first assignment is a
3611 condition code register or cc0. We eliminate this case by making sure
3612 the SET_DEST and SET_SRC have the same mode.
3614 We cannot do this if the destination of the second assignment is
3615 a register that we have already assumed is zero-extended. Similarly
3616 for a SUBREG of such a register. */
3618 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3619 && GET_CODE (newpat
) == PARALLEL
3620 && XVECLEN (newpat
, 0) == 2
3621 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3622 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3623 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3624 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3625 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3626 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3627 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3628 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3630 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3631 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3632 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3634 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3635 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3636 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3637 && (reg_stat
[REGNO (temp
)].nonzero_bits
3638 != GET_MODE_MASK (word_mode
))))
3639 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3640 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3642 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3643 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3644 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3645 && (reg_stat
[REGNO (temp
)].nonzero_bits
3646 != GET_MODE_MASK (word_mode
)))))
3647 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3648 SET_SRC (XVECEXP (newpat
, 0, 1)))
3649 && ! find_reg_note (i3
, REG_UNUSED
,
3650 SET_DEST (XVECEXP (newpat
, 0, 0))))
3654 newi2pat
= XVECEXP (newpat
, 0, 0);
3655 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3656 newpat
= XVECEXP (newpat
, 0, 1);
3657 SUBST (SET_SRC (newpat
),
3658 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3659 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3661 if (i2_code_number
>= 0)
3662 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3664 if (insn_code_number
>= 0)
3668 /* Similarly, check for a case where we have a PARALLEL of two independent
3669 SETs but we started with three insns. In this case, we can do the sets
3670 as two separate insns. This case occurs when some SET allows two
3671 other insns to combine, but the destination of that SET is still live. */
3673 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3674 && GET_CODE (newpat
) == PARALLEL
3675 && XVECLEN (newpat
, 0) == 2
3676 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3677 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3678 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3679 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3680 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3681 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3682 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3683 XVECEXP (newpat
, 0, 0))
3684 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3685 XVECEXP (newpat
, 0, 1))
3686 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3687 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3689 rtx set0
= XVECEXP (newpat
, 0, 0);
3690 rtx set1
= XVECEXP (newpat
, 0, 1);
3692 /* Normally, it doesn't matter which of the two is done first,
3693 but the one that references cc0 can't be the second, and
3694 one which uses any regs/memory set in between i2 and i3 can't
3695 be first. The PARALLEL might also have been pre-existing in i3,
3696 so we need to make sure that we won't wrongly hoist a SET to i2
3697 that would conflict with a death note present in there. */
3698 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3699 && !(REG_P (SET_DEST (set1
))
3700 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3701 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3702 && find_reg_note (i2
, REG_DEAD
,
3703 SUBREG_REG (SET_DEST (set1
))))
3705 && !reg_referenced_p (cc0_rtx
, set0
)
3712 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3713 && !(REG_P (SET_DEST (set0
))
3714 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3715 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3716 && find_reg_note (i2
, REG_DEAD
,
3717 SUBREG_REG (SET_DEST (set0
))))
3719 && !reg_referenced_p (cc0_rtx
, set1
)
3732 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3734 if (i2_code_number
>= 0)
3736 /* recog_for_combine might have added CLOBBERs to newi2pat.
3737 Make sure NEWPAT does not depend on the clobbered regs. */
3738 if (GET_CODE (newi2pat
) == PARALLEL
)
3740 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3741 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3743 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3744 if (reg_overlap_mentioned_p (reg
, newpat
))
3752 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3756 /* If it still isn't recognized, fail and change things back the way they
3758 if ((insn_code_number
< 0
3759 /* Is the result a reasonable ASM_OPERANDS? */
3760 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3766 /* If we had to change another insn, make sure it is valid also. */
3767 if (undobuf
.other_insn
)
3769 CLEAR_HARD_REG_SET (newpat_used_regs
);
3771 other_pat
= PATTERN (undobuf
.other_insn
);
3772 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3775 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3783 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3784 they are adjacent to each other or not. */
3786 rtx p
= prev_nonnote_insn (i3
);
3787 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3788 && sets_cc0_p (newi2pat
))
3796 /* Only allow this combination if insn_rtx_costs reports that the
3797 replacement instructions are cheaper than the originals. */
3798 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3804 if (MAY_HAVE_DEBUG_INSNS
)
3808 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3809 if (undo
->kind
== UNDO_MODE
)
3811 rtx reg
= *undo
->where
.r
;
3812 enum machine_mode new_mode
= GET_MODE (reg
);
3813 enum machine_mode old_mode
= undo
->old_contents
.m
;
3815 /* Temporarily revert mode back. */
3816 adjust_reg_mode (reg
, old_mode
);
3818 if (reg
== i2dest
&& i2scratch
)
3820 /* If we used i2dest as a scratch register with a
3821 different mode, substitute it for the original
3822 i2src while its original mode is temporarily
3823 restored, and then clear i2scratch so that we don't
3824 do it again later. */
3825 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3828 /* Put back the new mode. */
3829 adjust_reg_mode (reg
, new_mode
);
3833 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3839 last
= last_combined_insn
;
3844 last
= undobuf
.other_insn
;
3846 if (DF_INSN_LUID (last
)
3847 < DF_INSN_LUID (last_combined_insn
))
3848 last
= last_combined_insn
;
3851 /* We're dealing with a reg that changed mode but not
3852 meaning, so we want to turn it into a subreg for
3853 the new mode. However, because of REG sharing and
3854 because its mode had already changed, we have to do
3855 it in two steps. First, replace any debug uses of
3856 reg, with its original mode temporarily restored,
3857 with this copy we have created; then, replace the
3858 copy with the SUBREG of the original shared reg,
3859 once again changed to the new mode. */
3860 propagate_for_debug (first
, last
, reg
, tempreg
,
3862 adjust_reg_mode (reg
, new_mode
);
3863 propagate_for_debug (first
, last
, tempreg
,
3864 lowpart_subreg (old_mode
, reg
, new_mode
),
3870 /* If we will be able to accept this, we have made a
3871 change to the destination of I3. This requires us to
3872 do a few adjustments. */
3874 if (changed_i3_dest
)
3876 PATTERN (i3
) = newpat
;
3877 adjust_for_new_dest (i3
);
3880 /* We now know that we can do this combination. Merge the insns and
3881 update the status of registers and LOG_LINKS. */
3883 if (undobuf
.other_insn
)
3887 PATTERN (undobuf
.other_insn
) = other_pat
;
3889 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3890 are still valid. Then add any non-duplicate notes added by
3891 recog_for_combine. */
3892 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3894 next
= XEXP (note
, 1);
3896 if (REG_NOTE_KIND (note
) == REG_UNUSED
3897 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3898 remove_note (undobuf
.other_insn
, note
);
3901 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3902 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3909 struct insn_link
*link
;
3912 /* I3 now uses what used to be its destination and which is now
3913 I2's destination. This requires us to do a few adjustments. */
3914 PATTERN (i3
) = newpat
;
3915 adjust_for_new_dest (i3
);
3917 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3920 However, some later insn might be using I2's dest and have
3921 a LOG_LINK pointing at I3. We must remove this link.
3922 The simplest way to remove the link is to point it at I1,
3923 which we know will be a NOTE. */
3925 /* newi2pat is usually a SET here; however, recog_for_combine might
3926 have added some clobbers. */
3927 if (GET_CODE (newi2pat
) == PARALLEL
)
3928 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3930 ni2dest
= SET_DEST (newi2pat
);
3932 for (insn
= NEXT_INSN (i3
);
3933 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3934 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3935 insn
= NEXT_INSN (insn
))
3937 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3939 FOR_EACH_LOG_LINK (link
, insn
)
3940 if (link
->insn
== i3
)
3949 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3950 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
3953 /* Compute which registers we expect to eliminate. newi2pat may be setting
3954 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3955 same as i3dest, in which case newi2pat may be setting i1dest. */
3956 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3957 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3960 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3961 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3964 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3965 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3969 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3971 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3972 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3974 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3976 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3978 /* Ensure that we do not have something that should not be shared but
3979 occurs multiple times in the new insns. Check this by first
3980 resetting all the `used' flags and then copying anything is shared. */
3982 reset_used_flags (i3notes
);
3983 reset_used_flags (i2notes
);
3984 reset_used_flags (i1notes
);
3985 reset_used_flags (i0notes
);
3986 reset_used_flags (newpat
);
3987 reset_used_flags (newi2pat
);
3988 if (undobuf
.other_insn
)
3989 reset_used_flags (PATTERN (undobuf
.other_insn
));
3991 i3notes
= copy_rtx_if_shared (i3notes
);
3992 i2notes
= copy_rtx_if_shared (i2notes
);
3993 i1notes
= copy_rtx_if_shared (i1notes
);
3994 i0notes
= copy_rtx_if_shared (i0notes
);
3995 newpat
= copy_rtx_if_shared (newpat
);
3996 newi2pat
= copy_rtx_if_shared (newi2pat
);
3997 if (undobuf
.other_insn
)
3998 reset_used_flags (PATTERN (undobuf
.other_insn
));
4000 INSN_CODE (i3
) = insn_code_number
;
4001 PATTERN (i3
) = newpat
;
4003 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4005 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4007 reset_used_flags (call_usage
);
4008 call_usage
= copy_rtx (call_usage
);
4012 /* I2SRC must still be meaningful at this point. Some splitting
4013 operations can invalidate I2SRC, but those operations do not
4016 replace_rtx (call_usage
, i2dest
, i2src
);
4020 replace_rtx (call_usage
, i1dest
, i1src
);
4022 replace_rtx (call_usage
, i0dest
, i0src
);
4024 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4027 if (undobuf
.other_insn
)
4028 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4030 /* We had one special case above where I2 had more than one set and
4031 we replaced a destination of one of those sets with the destination
4032 of I3. In that case, we have to update LOG_LINKS of insns later
4033 in this basic block. Note that this (expensive) case is rare.
4035 Also, in this case, we must pretend that all REG_NOTEs for I2
4036 actually came from I3, so that REG_UNUSED notes from I2 will be
4037 properly handled. */
4039 if (i3_subst_into_i2
)
4041 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4042 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4043 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4044 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4045 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4046 && ! find_reg_note (i2
, REG_UNUSED
,
4047 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4048 for (temp
= NEXT_INSN (i2
);
4049 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4050 || BB_HEAD (this_basic_block
) != temp
);
4051 temp
= NEXT_INSN (temp
))
4052 if (temp
!= i3
&& INSN_P (temp
))
4053 FOR_EACH_LOG_LINK (link
, temp
)
4054 if (link
->insn
== i2
)
4060 while (XEXP (link
, 1))
4061 link
= XEXP (link
, 1);
4062 XEXP (link
, 1) = i2notes
;
4069 LOG_LINKS (i3
) = NULL
;
4071 LOG_LINKS (i2
) = NULL
;
4076 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4077 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4079 INSN_CODE (i2
) = i2_code_number
;
4080 PATTERN (i2
) = newi2pat
;
4084 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4085 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4087 SET_INSN_DELETED (i2
);
4092 LOG_LINKS (i1
) = NULL
;
4094 if (MAY_HAVE_DEBUG_INSNS
)
4095 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4097 SET_INSN_DELETED (i1
);
4102 LOG_LINKS (i0
) = NULL
;
4104 if (MAY_HAVE_DEBUG_INSNS
)
4105 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4107 SET_INSN_DELETED (i0
);
4110 /* Get death notes for everything that is now used in either I3 or
4111 I2 and used to die in a previous insn. If we built two new
4112 patterns, move from I1 to I2 then I2 to I3 so that we get the
4113 proper movement on registers that I2 modifies. */
4116 from_luid
= DF_INSN_LUID (i0
);
4118 from_luid
= DF_INSN_LUID (i1
);
4120 from_luid
= DF_INSN_LUID (i2
);
4122 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4123 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4125 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4127 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4128 elim_i2
, elim_i1
, elim_i0
);
4130 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4131 elim_i2
, elim_i1
, elim_i0
);
4133 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4134 elim_i2
, elim_i1
, elim_i0
);
4136 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4137 elim_i2
, elim_i1
, elim_i0
);
4139 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4140 elim_i2
, elim_i1
, elim_i0
);
4142 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4143 know these are REG_UNUSED and want them to go to the desired insn,
4144 so we always pass it as i3. */
4146 if (newi2pat
&& new_i2_notes
)
4147 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4151 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4154 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4155 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4156 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4157 in that case, it might delete I2. Similarly for I2 and I1.
4158 Show an additional death due to the REG_DEAD note we make here. If
4159 we discard it in distribute_notes, we will decrement it again. */
4163 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4164 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4165 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, elim_i2
,
4168 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4169 elim_i2
, elim_i1
, elim_i0
);
4172 if (i2dest_in_i2src
)
4174 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4175 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4176 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4177 NULL_RTX
, NULL_RTX
);
4179 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4180 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4183 if (i1dest_in_i1src
)
4185 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4186 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4187 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4188 NULL_RTX
, NULL_RTX
);
4190 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4191 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4194 if (i0dest_in_i0src
)
4196 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4197 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4198 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4199 NULL_RTX
, NULL_RTX
);
4201 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4202 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4205 distribute_links (i3links
);
4206 distribute_links (i2links
);
4207 distribute_links (i1links
);
4208 distribute_links (i0links
);
4212 struct insn_link
*link
;
4213 rtx i2_insn
= 0, i2_val
= 0, set
;
4215 /* The insn that used to set this register doesn't exist, and
4216 this life of the register may not exist either. See if one of
4217 I3's links points to an insn that sets I2DEST. If it does,
4218 that is now the last known value for I2DEST. If we don't update
4219 this and I2 set the register to a value that depended on its old
4220 contents, we will get confused. If this insn is used, thing
4221 will be set correctly in combine_instructions. */
4222 FOR_EACH_LOG_LINK (link
, i3
)
4223 if ((set
= single_set (link
->insn
)) != 0
4224 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4225 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4227 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4229 /* If the reg formerly set in I2 died only once and that was in I3,
4230 zero its use count so it won't make `reload' do any work. */
4232 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4233 && ! i2dest_in_i2src
)
4234 INC_REG_N_SETS (REGNO (i2dest
), -1);
4237 if (i1
&& REG_P (i1dest
))
4239 struct insn_link
*link
;
4240 rtx i1_insn
= 0, i1_val
= 0, set
;
4242 FOR_EACH_LOG_LINK (link
, i3
)
4243 if ((set
= single_set (link
->insn
)) != 0
4244 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4245 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4247 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4249 if (! added_sets_1
&& ! i1dest_in_i1src
)
4250 INC_REG_N_SETS (REGNO (i1dest
), -1);
4253 if (i0
&& REG_P (i0dest
))
4255 struct insn_link
*link
;
4256 rtx i0_insn
= 0, i0_val
= 0, set
;
4258 FOR_EACH_LOG_LINK (link
, i3
)
4259 if ((set
= single_set (link
->insn
)) != 0
4260 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4261 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4263 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4265 if (! added_sets_0
&& ! i0dest_in_i0src
)
4266 INC_REG_N_SETS (REGNO (i0dest
), -1);
4269 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4270 been made to this insn. The order is important, because newi2pat
4271 can affect nonzero_bits of newpat. */
4273 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4274 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4277 if (undobuf
.other_insn
!= NULL_RTX
)
4281 fprintf (dump_file
, "modifying other_insn ");
4282 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4284 df_insn_rescan (undobuf
.other_insn
);
4287 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4291 fprintf (dump_file
, "modifying insn i0 ");
4292 dump_insn_slim (dump_file
, i0
);
4294 df_insn_rescan (i0
);
4297 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4301 fprintf (dump_file
, "modifying insn i1 ");
4302 dump_insn_slim (dump_file
, i1
);
4304 df_insn_rescan (i1
);
4307 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4311 fprintf (dump_file
, "modifying insn i2 ");
4312 dump_insn_slim (dump_file
, i2
);
4314 df_insn_rescan (i2
);
4317 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4321 fprintf (dump_file
, "modifying insn i3 ");
4322 dump_insn_slim (dump_file
, i3
);
4324 df_insn_rescan (i3
);
4327 /* Set new_direct_jump_p if a new return or simple jump instruction
4328 has been created. Adjust the CFG accordingly. */
4329 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4331 *new_direct_jump_p
= 1;
4332 mark_jump_label (PATTERN (i3
), i3
, 0);
4333 update_cfg_for_uncondjump (i3
);
4336 if (undobuf
.other_insn
!= NULL_RTX
4337 && (returnjump_p (undobuf
.other_insn
)
4338 || any_uncondjump_p (undobuf
.other_insn
)))
4340 *new_direct_jump_p
= 1;
4341 update_cfg_for_uncondjump (undobuf
.other_insn
);
4344 /* A noop might also need cleaning up of CFG, if it comes from the
4345 simplification of a jump. */
4347 && GET_CODE (newpat
) == SET
4348 && SET_SRC (newpat
) == pc_rtx
4349 && SET_DEST (newpat
) == pc_rtx
)
4351 *new_direct_jump_p
= 1;
4352 update_cfg_for_uncondjump (i3
);
4355 if (undobuf
.other_insn
!= NULL_RTX
4356 && JUMP_P (undobuf
.other_insn
)
4357 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4358 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4359 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4361 *new_direct_jump_p
= 1;
4362 update_cfg_for_uncondjump (undobuf
.other_insn
);
4365 combine_successes
++;
4368 if (added_links_insn
4369 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4370 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4371 return added_links_insn
;
4373 return newi2pat
? i2
: i3
;
4376 /* Undo all the modifications recorded in undobuf. */
4381 struct undo
*undo
, *next
;
4383 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4389 *undo
->where
.r
= undo
->old_contents
.r
;
4392 *undo
->where
.i
= undo
->old_contents
.i
;
4395 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4398 *undo
->where
.l
= undo
->old_contents
.l
;
4404 undo
->next
= undobuf
.frees
;
4405 undobuf
.frees
= undo
;
4411 /* We've committed to accepting the changes we made. Move all
4412 of the undos to the free list. */
4417 struct undo
*undo
, *next
;
4419 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4422 undo
->next
= undobuf
.frees
;
4423 undobuf
.frees
= undo
;
4428 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4429 where we have an arithmetic expression and return that point. LOC will
4432 try_combine will call this function to see if an insn can be split into
4436 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4439 enum rtx_code code
= GET_CODE (x
);
4441 unsigned HOST_WIDE_INT len
= 0;
4442 HOST_WIDE_INT pos
= 0;
4444 rtx inner
= NULL_RTX
;
4446 /* First special-case some codes. */
4450 #ifdef INSN_SCHEDULING
4451 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4453 if (MEM_P (SUBREG_REG (x
)))
4456 return find_split_point (&SUBREG_REG (x
), insn
, false);
4460 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4461 using LO_SUM and HIGH. */
4462 if (GET_CODE (XEXP (x
, 0)) == CONST
4463 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4465 enum machine_mode address_mode
= get_address_mode (x
);
4468 gen_rtx_LO_SUM (address_mode
,
4469 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4471 return &XEXP (XEXP (x
, 0), 0);
4475 /* If we have a PLUS whose second operand is a constant and the
4476 address is not valid, perhaps will can split it up using
4477 the machine-specific way to split large constants. We use
4478 the first pseudo-reg (one of the virtual regs) as a placeholder;
4479 it will not remain in the result. */
4480 if (GET_CODE (XEXP (x
, 0)) == PLUS
4481 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4482 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4483 MEM_ADDR_SPACE (x
)))
4485 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4486 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4490 /* This should have produced two insns, each of which sets our
4491 placeholder. If the source of the second is a valid address,
4492 we can make put both sources together and make a split point
4496 && NEXT_INSN (seq
) != NULL_RTX
4497 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4498 && NONJUMP_INSN_P (seq
)
4499 && GET_CODE (PATTERN (seq
)) == SET
4500 && SET_DEST (PATTERN (seq
)) == reg
4501 && ! reg_mentioned_p (reg
,
4502 SET_SRC (PATTERN (seq
)))
4503 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4504 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4505 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4506 && memory_address_addr_space_p
4507 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4508 MEM_ADDR_SPACE (x
)))
4510 rtx src1
= SET_SRC (PATTERN (seq
));
4511 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4513 /* Replace the placeholder in SRC2 with SRC1. If we can
4514 find where in SRC2 it was placed, that can become our
4515 split point and we can replace this address with SRC2.
4516 Just try two obvious places. */
4518 src2
= replace_rtx (src2
, reg
, src1
);
4520 if (XEXP (src2
, 0) == src1
)
4521 split
= &XEXP (src2
, 0);
4522 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4523 && XEXP (XEXP (src2
, 0), 0) == src1
)
4524 split
= &XEXP (XEXP (src2
, 0), 0);
4528 SUBST (XEXP (x
, 0), src2
);
4533 /* If that didn't work, perhaps the first operand is complex and
4534 needs to be computed separately, so make a split point there.
4535 This will occur on machines that just support REG + CONST
4536 and have a constant moved through some previous computation. */
4538 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4539 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4540 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4541 return &XEXP (XEXP (x
, 0), 0);
4544 /* If we have a PLUS whose first operand is complex, try computing it
4545 separately by making a split there. */
4546 if (GET_CODE (XEXP (x
, 0)) == PLUS
4547 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4549 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4550 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4551 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4552 return &XEXP (XEXP (x
, 0), 0);
4557 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4558 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4559 we need to put the operand into a register. So split at that
4562 if (SET_DEST (x
) == cc0_rtx
4563 && GET_CODE (SET_SRC (x
)) != COMPARE
4564 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4565 && !OBJECT_P (SET_SRC (x
))
4566 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4567 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4568 return &SET_SRC (x
);
4571 /* See if we can split SET_SRC as it stands. */
4572 split
= find_split_point (&SET_SRC (x
), insn
, true);
4573 if (split
&& split
!= &SET_SRC (x
))
4576 /* See if we can split SET_DEST as it stands. */
4577 split
= find_split_point (&SET_DEST (x
), insn
, false);
4578 if (split
&& split
!= &SET_DEST (x
))
4581 /* See if this is a bitfield assignment with everything constant. If
4582 so, this is an IOR of an AND, so split it into that. */
4583 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4584 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4585 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4586 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4587 && CONST_INT_P (SET_SRC (x
))
4588 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4589 + INTVAL (XEXP (SET_DEST (x
), 2)))
4590 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4591 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4593 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4594 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4595 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4596 rtx dest
= XEXP (SET_DEST (x
), 0);
4597 enum machine_mode mode
= GET_MODE (dest
);
4598 unsigned HOST_WIDE_INT mask
4599 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4602 if (BITS_BIG_ENDIAN
)
4603 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4605 or_mask
= gen_int_mode (src
<< pos
, mode
);
4608 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4611 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4613 simplify_gen_binary (IOR
, mode
,
4614 simplify_gen_binary (AND
, mode
,
4619 SUBST (SET_DEST (x
), dest
);
4621 split
= find_split_point (&SET_SRC (x
), insn
, true);
4622 if (split
&& split
!= &SET_SRC (x
))
4626 /* Otherwise, see if this is an operation that we can split into two.
4627 If so, try to split that. */
4628 code
= GET_CODE (SET_SRC (x
));
4633 /* If we are AND'ing with a large constant that is only a single
4634 bit and the result is only being used in a context where we
4635 need to know if it is zero or nonzero, replace it with a bit
4636 extraction. This will avoid the large constant, which might
4637 have taken more than one insn to make. If the constant were
4638 not a valid argument to the AND but took only one insn to make,
4639 this is no worse, but if it took more than one insn, it will
4642 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4643 && REG_P (XEXP (SET_SRC (x
), 0))
4644 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4645 && REG_P (SET_DEST (x
))
4646 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4647 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4648 && XEXP (*split
, 0) == SET_DEST (x
)
4649 && XEXP (*split
, 1) == const0_rtx
)
4651 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4652 XEXP (SET_SRC (x
), 0),
4653 pos
, NULL_RTX
, 1, 1, 0, 0);
4654 if (extraction
!= 0)
4656 SUBST (SET_SRC (x
), extraction
);
4657 return find_split_point (loc
, insn
, false);
4663 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4664 is known to be on, this can be converted into a NEG of a shift. */
4665 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4666 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4667 && 1 <= (pos
= exact_log2
4668 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4669 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4671 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4675 gen_rtx_LSHIFTRT (mode
,
4676 XEXP (SET_SRC (x
), 0),
4679 split
= find_split_point (&SET_SRC (x
), insn
, true);
4680 if (split
&& split
!= &SET_SRC (x
))
4686 inner
= XEXP (SET_SRC (x
), 0);
4688 /* We can't optimize if either mode is a partial integer
4689 mode as we don't know how many bits are significant
4691 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4692 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4696 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4702 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4703 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4705 inner
= XEXP (SET_SRC (x
), 0);
4706 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4707 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4709 if (BITS_BIG_ENDIAN
)
4710 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4711 unsignedp
= (code
== ZERO_EXTRACT
);
4720 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4722 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4724 /* For unsigned, we have a choice of a shift followed by an
4725 AND or two shifts. Use two shifts for field sizes where the
4726 constant might be too large. We assume here that we can
4727 always at least get 8-bit constants in an AND insn, which is
4728 true for every current RISC. */
4730 if (unsignedp
&& len
<= 8)
4732 unsigned HOST_WIDE_INT mask
4733 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4737 (mode
, gen_lowpart (mode
, inner
),
4739 gen_int_mode (mask
, mode
)));
4741 split
= find_split_point (&SET_SRC (x
), insn
, true);
4742 if (split
&& split
!= &SET_SRC (x
))
4749 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4750 gen_rtx_ASHIFT (mode
,
4751 gen_lowpart (mode
, inner
),
4752 GEN_INT (GET_MODE_PRECISION (mode
)
4754 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4756 split
= find_split_point (&SET_SRC (x
), insn
, true);
4757 if (split
&& split
!= &SET_SRC (x
))
4762 /* See if this is a simple operation with a constant as the second
4763 operand. It might be that this constant is out of range and hence
4764 could be used as a split point. */
4765 if (BINARY_P (SET_SRC (x
))
4766 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4767 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4768 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4769 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4770 return &XEXP (SET_SRC (x
), 1);
4772 /* Finally, see if this is a simple operation with its first operand
4773 not in a register. The operation might require this operand in a
4774 register, so return it as a split point. We can always do this
4775 because if the first operand were another operation, we would have
4776 already found it as a split point. */
4777 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4778 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4779 return &XEXP (SET_SRC (x
), 0);
4785 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4786 it is better to write this as (not (ior A B)) so we can split it.
4787 Similarly for IOR. */
4788 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4791 gen_rtx_NOT (GET_MODE (x
),
4792 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4794 XEXP (XEXP (x
, 0), 0),
4795 XEXP (XEXP (x
, 1), 0))));
4796 return find_split_point (loc
, insn
, set_src
);
4799 /* Many RISC machines have a large set of logical insns. If the
4800 second operand is a NOT, put it first so we will try to split the
4801 other operand first. */
4802 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4804 rtx tem
= XEXP (x
, 0);
4805 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4806 SUBST (XEXP (x
, 1), tem
);
4812 /* Canonicalization can produce (minus A (mult B C)), where C is a
4813 constant. It may be better to try splitting (plus (mult B -C) A)
4814 instead if this isn't a multiply by a power of two. */
4815 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4816 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4817 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4819 enum machine_mode mode
= GET_MODE (x
);
4820 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4821 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4822 SUBST (*loc
, gen_rtx_PLUS (mode
,
4824 XEXP (XEXP (x
, 1), 0),
4825 gen_int_mode (other_int
,
4828 return find_split_point (loc
, insn
, set_src
);
4831 /* Split at a multiply-accumulate instruction. However if this is
4832 the SET_SRC, we likely do not have such an instruction and it's
4833 worthless to try this split. */
4834 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4841 /* Otherwise, select our actions depending on our rtx class. */
4842 switch (GET_RTX_CLASS (code
))
4844 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4846 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4849 /* ... fall through ... */
4851 case RTX_COMM_ARITH
:
4853 case RTX_COMM_COMPARE
:
4854 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4857 /* ... fall through ... */
4859 /* Some machines have (and (shift ...) ...) insns. If X is not
4860 an AND, but XEXP (X, 0) is, use it as our split point. */
4861 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4862 return &XEXP (x
, 0);
4864 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4870 /* Otherwise, we don't have a split point. */
4875 /* Throughout X, replace FROM with TO, and return the result.
4876 The result is TO if X is FROM;
4877 otherwise the result is X, but its contents may have been modified.
4878 If they were modified, a record was made in undobuf so that
4879 undo_all will (among other things) return X to its original state.
4881 If the number of changes necessary is too much to record to undo,
4882 the excess changes are not made, so the result is invalid.
4883 The changes already made can still be undone.
4884 undobuf.num_undo is incremented for such changes, so by testing that
4885 the caller can tell whether the result is valid.
4887 `n_occurrences' is incremented each time FROM is replaced.
4889 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4891 IN_COND is nonzero if we are at the top level of a condition.
4893 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4894 by copying if `n_occurrences' is nonzero. */
4897 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4899 enum rtx_code code
= GET_CODE (x
);
4900 enum machine_mode op0_mode
= VOIDmode
;
4905 /* Two expressions are equal if they are identical copies of a shared
4906 RTX or if they are both registers with the same register number
4909 #define COMBINE_RTX_EQUAL_P(X,Y) \
4911 || (REG_P (X) && REG_P (Y) \
4912 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4914 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4917 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4920 /* If X and FROM are the same register but different modes, they
4921 will not have been seen as equal above. However, the log links code
4922 will make a LOG_LINKS entry for that case. If we do nothing, we
4923 will try to rerecognize our original insn and, when it succeeds,
4924 we will delete the feeding insn, which is incorrect.
4926 So force this insn not to match in this (rare) case. */
4927 if (! in_dest
&& code
== REG
&& REG_P (from
)
4928 && reg_overlap_mentioned_p (x
, from
))
4929 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4931 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4932 of which may contain things that can be combined. */
4933 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4936 /* It is possible to have a subexpression appear twice in the insn.
4937 Suppose that FROM is a register that appears within TO.
4938 Then, after that subexpression has been scanned once by `subst',
4939 the second time it is scanned, TO may be found. If we were
4940 to scan TO here, we would find FROM within it and create a
4941 self-referent rtl structure which is completely wrong. */
4942 if (COMBINE_RTX_EQUAL_P (x
, to
))
4945 /* Parallel asm_operands need special attention because all of the
4946 inputs are shared across the arms. Furthermore, unsharing the
4947 rtl results in recognition failures. Failure to handle this case
4948 specially can result in circular rtl.
4950 Solve this by doing a normal pass across the first entry of the
4951 parallel, and only processing the SET_DESTs of the subsequent
4954 if (code
== PARALLEL
4955 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4956 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4958 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
4960 /* If this substitution failed, this whole thing fails. */
4961 if (GET_CODE (new_rtx
) == CLOBBER
4962 && XEXP (new_rtx
, 0) == const0_rtx
)
4965 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4967 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4969 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4972 && GET_CODE (dest
) != CC0
4973 && GET_CODE (dest
) != PC
)
4975 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
4977 /* If this substitution failed, this whole thing fails. */
4978 if (GET_CODE (new_rtx
) == CLOBBER
4979 && XEXP (new_rtx
, 0) == const0_rtx
)
4982 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4988 len
= GET_RTX_LENGTH (code
);
4989 fmt
= GET_RTX_FORMAT (code
);
4991 /* We don't need to process a SET_DEST that is a register, CC0,
4992 or PC, so set up to skip this common case. All other cases
4993 where we want to suppress replacing something inside a
4994 SET_SRC are handled via the IN_DEST operand. */
4996 && (REG_P (SET_DEST (x
))
4997 || GET_CODE (SET_DEST (x
)) == CC0
4998 || GET_CODE (SET_DEST (x
)) == PC
))
5001 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5004 op0_mode
= GET_MODE (XEXP (x
, 0));
5006 for (i
= 0; i
< len
; i
++)
5011 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5013 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5015 new_rtx
= (unique_copy
&& n_occurrences
5016 ? copy_rtx (to
) : to
);
5021 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5024 /* If this substitution failed, this whole thing
5026 if (GET_CODE (new_rtx
) == CLOBBER
5027 && XEXP (new_rtx
, 0) == const0_rtx
)
5031 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5034 else if (fmt
[i
] == 'e')
5036 /* If this is a register being set, ignore it. */
5037 new_rtx
= XEXP (x
, i
);
5040 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5042 || code
== STRICT_LOW_PART
))
5045 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5047 /* In general, don't install a subreg involving two
5048 modes not tieable. It can worsen register
5049 allocation, and can even make invalid reload
5050 insns, since the reg inside may need to be copied
5051 from in the outside mode, and that may be invalid
5052 if it is an fp reg copied in integer mode.
5054 We allow two exceptions to this: It is valid if
5055 it is inside another SUBREG and the mode of that
5056 SUBREG and the mode of the inside of TO is
5057 tieable and it is valid if X is a SET that copies
5060 if (GET_CODE (to
) == SUBREG
5061 && ! MODES_TIEABLE_P (GET_MODE (to
),
5062 GET_MODE (SUBREG_REG (to
)))
5063 && ! (code
== SUBREG
5064 && MODES_TIEABLE_P (GET_MODE (x
),
5065 GET_MODE (SUBREG_REG (to
))))
5067 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5070 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5072 #ifdef CANNOT_CHANGE_MODE_CLASS
5075 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5076 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5079 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5082 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5086 /* If we are in a SET_DEST, suppress most cases unless we
5087 have gone inside a MEM, in which case we want to
5088 simplify the address. We assume here that things that
5089 are actually part of the destination have their inner
5090 parts in the first expression. This is true for SUBREG,
5091 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5092 things aside from REG and MEM that should appear in a
5094 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5096 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5097 || code
== ZERO_EXTRACT
))
5100 code
== IF_THEN_ELSE
&& i
== 0,
5103 /* If we found that we will have to reject this combination,
5104 indicate that by returning the CLOBBER ourselves, rather than
5105 an expression containing it. This will speed things up as
5106 well as prevent accidents where two CLOBBERs are considered
5107 to be equal, thus producing an incorrect simplification. */
5109 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5112 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5114 enum machine_mode mode
= GET_MODE (x
);
5116 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5117 GET_MODE (SUBREG_REG (x
)),
5120 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5122 else if (CONST_SCALAR_INT_P (new_rtx
)
5123 && GET_CODE (x
) == ZERO_EXTEND
)
5125 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5126 new_rtx
, GET_MODE (XEXP (x
, 0)));
5130 SUBST (XEXP (x
, i
), new_rtx
);
5135 /* Check if we are loading something from the constant pool via float
5136 extension; in this case we would undo compress_float_constant
5137 optimization and degenerate constant load to an immediate value. */
5138 if (GET_CODE (x
) == FLOAT_EXTEND
5139 && MEM_P (XEXP (x
, 0))
5140 && MEM_READONLY_P (XEXP (x
, 0)))
5142 rtx tmp
= avoid_constant_pool_reference (x
);
5147 /* Try to simplify X. If the simplification changed the code, it is likely
5148 that further simplification will help, so loop, but limit the number
5149 of repetitions that will be performed. */
5151 for (i
= 0; i
< 4; i
++)
5153 /* If X is sufficiently simple, don't bother trying to do anything
5155 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5156 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5158 if (GET_CODE (x
) == code
)
5161 code
= GET_CODE (x
);
5163 /* We no longer know the original mode of operand 0 since we
5164 have changed the form of X) */
5165 op0_mode
= VOIDmode
;
5171 /* Simplify X, a piece of RTL. We just operate on the expression at the
5172 outer level; call `subst' to simplify recursively. Return the new
5175 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5176 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5180 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5183 enum rtx_code code
= GET_CODE (x
);
5184 enum machine_mode mode
= GET_MODE (x
);
5188 /* If this is a commutative operation, put a constant last and a complex
5189 expression first. We don't need to do this for comparisons here. */
5190 if (COMMUTATIVE_ARITH_P (x
)
5191 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5194 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5195 SUBST (XEXP (x
, 1), temp
);
5198 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5199 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5200 things. Check for cases where both arms are testing the same
5203 Don't do anything if all operands are very simple. */
5206 && ((!OBJECT_P (XEXP (x
, 0))
5207 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5208 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5209 || (!OBJECT_P (XEXP (x
, 1))
5210 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5211 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5213 && (!OBJECT_P (XEXP (x
, 0))
5214 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5215 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5217 rtx cond
, true_rtx
, false_rtx
;
5219 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5221 /* If everything is a comparison, what we have is highly unlikely
5222 to be simpler, so don't use it. */
5223 && ! (COMPARISON_P (x
)
5224 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5226 rtx cop1
= const0_rtx
;
5227 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5229 if (cond_code
== NE
&& COMPARISON_P (cond
))
5232 /* Simplify the alternative arms; this may collapse the true and
5233 false arms to store-flag values. Be careful to use copy_rtx
5234 here since true_rtx or false_rtx might share RTL with x as a
5235 result of the if_then_else_cond call above. */
5236 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5237 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5239 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5240 is unlikely to be simpler. */
5241 if (general_operand (true_rtx
, VOIDmode
)
5242 && general_operand (false_rtx
, VOIDmode
))
5244 enum rtx_code reversed
;
5246 /* Restarting if we generate a store-flag expression will cause
5247 us to loop. Just drop through in this case. */
5249 /* If the result values are STORE_FLAG_VALUE and zero, we can
5250 just make the comparison operation. */
5251 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5252 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5254 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5255 && ((reversed
= reversed_comparison_code_parts
5256 (cond_code
, cond
, cop1
, NULL
))
5258 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5261 /* Likewise, we can make the negate of a comparison operation
5262 if the result values are - STORE_FLAG_VALUE and zero. */
5263 else if (CONST_INT_P (true_rtx
)
5264 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5265 && false_rtx
== const0_rtx
)
5266 x
= simplify_gen_unary (NEG
, mode
,
5267 simplify_gen_relational (cond_code
,
5271 else if (CONST_INT_P (false_rtx
)
5272 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5273 && true_rtx
== const0_rtx
5274 && ((reversed
= reversed_comparison_code_parts
5275 (cond_code
, cond
, cop1
, NULL
))
5277 x
= simplify_gen_unary (NEG
, mode
,
5278 simplify_gen_relational (reversed
,
5283 return gen_rtx_IF_THEN_ELSE (mode
,
5284 simplify_gen_relational (cond_code
,
5289 true_rtx
, false_rtx
);
5291 code
= GET_CODE (x
);
5292 op0_mode
= VOIDmode
;
5297 /* Try to fold this expression in case we have constants that weren't
5300 switch (GET_RTX_CLASS (code
))
5303 if (op0_mode
== VOIDmode
)
5304 op0_mode
= GET_MODE (XEXP (x
, 0));
5305 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5308 case RTX_COMM_COMPARE
:
5310 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5311 if (cmp_mode
== VOIDmode
)
5313 cmp_mode
= GET_MODE (XEXP (x
, 1));
5314 if (cmp_mode
== VOIDmode
)
5315 cmp_mode
= op0_mode
;
5317 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5318 XEXP (x
, 0), XEXP (x
, 1));
5321 case RTX_COMM_ARITH
:
5323 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5325 case RTX_BITFIELD_OPS
:
5327 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5328 XEXP (x
, 1), XEXP (x
, 2));
5337 code
= GET_CODE (temp
);
5338 op0_mode
= VOIDmode
;
5339 mode
= GET_MODE (temp
);
5342 /* First see if we can apply the inverse distributive law. */
5343 if (code
== PLUS
|| code
== MINUS
5344 || code
== AND
|| code
== IOR
|| code
== XOR
)
5346 x
= apply_distributive_law (x
);
5347 code
= GET_CODE (x
);
5348 op0_mode
= VOIDmode
;
5351 /* If CODE is an associative operation not otherwise handled, see if we
5352 can associate some operands. This can win if they are constants or
5353 if they are logically related (i.e. (a & b) & a). */
5354 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5355 || code
== AND
|| code
== IOR
|| code
== XOR
5356 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5357 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5358 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5360 if (GET_CODE (XEXP (x
, 0)) == code
)
5362 rtx other
= XEXP (XEXP (x
, 0), 0);
5363 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5364 rtx inner_op1
= XEXP (x
, 1);
5367 /* Make sure we pass the constant operand if any as the second
5368 one if this is a commutative operation. */
5369 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5371 rtx tem
= inner_op0
;
5372 inner_op0
= inner_op1
;
5375 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5376 : code
== DIV
? MULT
5378 mode
, inner_op0
, inner_op1
);
5380 /* For commutative operations, try the other pair if that one
5382 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5384 other
= XEXP (XEXP (x
, 0), 1);
5385 inner
= simplify_binary_operation (code
, mode
,
5386 XEXP (XEXP (x
, 0), 0),
5391 return simplify_gen_binary (code
, mode
, other
, inner
);
5395 /* A little bit of algebraic simplification here. */
5399 /* Ensure that our address has any ASHIFTs converted to MULT in case
5400 address-recognizing predicates are called later. */
5401 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5402 SUBST (XEXP (x
, 0), temp
);
5406 if (op0_mode
== VOIDmode
)
5407 op0_mode
= GET_MODE (SUBREG_REG (x
));
5409 /* See if this can be moved to simplify_subreg. */
5410 if (CONSTANT_P (SUBREG_REG (x
))
5411 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5412 /* Don't call gen_lowpart if the inner mode
5413 is VOIDmode and we cannot simplify it, as SUBREG without
5414 inner mode is invalid. */
5415 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5416 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5417 return gen_lowpart (mode
, SUBREG_REG (x
));
5419 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5423 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5428 /* If op is known to have all lower bits zero, the result is zero. */
5430 && SCALAR_INT_MODE_P (mode
)
5431 && SCALAR_INT_MODE_P (op0_mode
)
5432 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5433 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5434 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5435 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5436 & GET_MODE_MASK (mode
)) == 0)
5437 return CONST0_RTX (mode
);
5440 /* Don't change the mode of the MEM if that would change the meaning
5442 if (MEM_P (SUBREG_REG (x
))
5443 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5444 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5445 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5446 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5448 /* Note that we cannot do any narrowing for non-constants since
5449 we might have been counting on using the fact that some bits were
5450 zero. We now do this in the SET. */
5455 temp
= expand_compound_operation (XEXP (x
, 0));
5457 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5458 replaced by (lshiftrt X C). This will convert
5459 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5461 if (GET_CODE (temp
) == ASHIFTRT
5462 && CONST_INT_P (XEXP (temp
, 1))
5463 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5464 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5465 INTVAL (XEXP (temp
, 1)));
5467 /* If X has only a single bit that might be nonzero, say, bit I, convert
5468 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5469 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5470 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5471 or a SUBREG of one since we'd be making the expression more
5472 complex if it was just a register. */
5475 && ! (GET_CODE (temp
) == SUBREG
5476 && REG_P (SUBREG_REG (temp
)))
5477 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5479 rtx temp1
= simplify_shift_const
5480 (NULL_RTX
, ASHIFTRT
, mode
,
5481 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5482 GET_MODE_PRECISION (mode
) - 1 - i
),
5483 GET_MODE_PRECISION (mode
) - 1 - i
);
5485 /* If all we did was surround TEMP with the two shifts, we
5486 haven't improved anything, so don't use it. Otherwise,
5487 we are better off with TEMP1. */
5488 if (GET_CODE (temp1
) != ASHIFTRT
5489 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5490 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5496 /* We can't handle truncation to a partial integer mode here
5497 because we don't know the real bitsize of the partial
5499 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5502 if (HWI_COMPUTABLE_MODE_P (mode
))
5504 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5505 GET_MODE_MASK (mode
), 0));
5507 /* We can truncate a constant value and return it. */
5508 if (CONST_INT_P (XEXP (x
, 0)))
5509 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5511 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5512 whose value is a comparison can be replaced with a subreg if
5513 STORE_FLAG_VALUE permits. */
5514 if (HWI_COMPUTABLE_MODE_P (mode
)
5515 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5516 && (temp
= get_last_value (XEXP (x
, 0)))
5517 && COMPARISON_P (temp
))
5518 return gen_lowpart (mode
, XEXP (x
, 0));
5522 /* (const (const X)) can become (const X). Do it this way rather than
5523 returning the inner CONST since CONST can be shared with a
5525 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5526 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5531 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5532 can add in an offset. find_split_point will split this address up
5533 again if it doesn't match. */
5534 if (GET_CODE (XEXP (x
, 0)) == HIGH
5535 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5541 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5542 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5543 bit-field and can be replaced by either a sign_extend or a
5544 sign_extract. The `and' may be a zero_extend and the two
5545 <c>, -<c> constants may be reversed. */
5546 if (GET_CODE (XEXP (x
, 0)) == XOR
5547 && CONST_INT_P (XEXP (x
, 1))
5548 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5549 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5550 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5551 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5552 && HWI_COMPUTABLE_MODE_P (mode
)
5553 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5554 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5555 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5556 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5557 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5558 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5559 == (unsigned int) i
+ 1))))
5560 return simplify_shift_const
5561 (NULL_RTX
, ASHIFTRT
, mode
,
5562 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5563 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5564 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5565 GET_MODE_PRECISION (mode
) - (i
+ 1));
5567 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5568 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5569 the bitsize of the mode - 1. This allows simplification of
5570 "a = (b & 8) == 0;" */
5571 if (XEXP (x
, 1) == constm1_rtx
5572 && !REG_P (XEXP (x
, 0))
5573 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5574 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5575 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5576 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5577 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5578 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5579 GET_MODE_PRECISION (mode
) - 1),
5580 GET_MODE_PRECISION (mode
) - 1);
5582 /* If we are adding two things that have no bits in common, convert
5583 the addition into an IOR. This will often be further simplified,
5584 for example in cases like ((a & 1) + (a & 2)), which can
5587 if (HWI_COMPUTABLE_MODE_P (mode
)
5588 && (nonzero_bits (XEXP (x
, 0), mode
)
5589 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5591 /* Try to simplify the expression further. */
5592 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5593 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5595 /* If we could, great. If not, do not go ahead with the IOR
5596 replacement, since PLUS appears in many special purpose
5597 address arithmetic instructions. */
5598 if (GET_CODE (temp
) != CLOBBER
5599 && (GET_CODE (temp
) != IOR
5600 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5601 || XEXP (temp
, 1) != XEXP (x
, 1))
5602 && (XEXP (temp
, 0) != XEXP (x
, 1)
5603 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5609 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5610 (and <foo> (const_int pow2-1)) */
5611 if (GET_CODE (XEXP (x
, 1)) == AND
5612 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5613 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5614 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5615 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5616 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5620 /* If we have (mult (plus A B) C), apply the distributive law and then
5621 the inverse distributive law to see if things simplify. This
5622 occurs mostly in addresses, often when unrolling loops. */
5624 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5626 rtx result
= distribute_and_simplify_rtx (x
, 0);
5631 /* Try simplify a*(b/c) as (a*b)/c. */
5632 if (FLOAT_MODE_P (mode
) && flag_associative_math
5633 && GET_CODE (XEXP (x
, 0)) == DIV
)
5635 rtx tem
= simplify_binary_operation (MULT
, mode
,
5636 XEXP (XEXP (x
, 0), 0),
5639 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5644 /* If this is a divide by a power of two, treat it as a shift if
5645 its first operand is a shift. */
5646 if (CONST_INT_P (XEXP (x
, 1))
5647 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5648 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5649 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5650 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5651 || GET_CODE (XEXP (x
, 0)) == ROTATE
5652 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5653 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5657 case GT
: case GTU
: case GE
: case GEU
:
5658 case LT
: case LTU
: case LE
: case LEU
:
5659 case UNEQ
: case LTGT
:
5660 case UNGT
: case UNGE
:
5661 case UNLT
: case UNLE
:
5662 case UNORDERED
: case ORDERED
:
5663 /* If the first operand is a condition code, we can't do anything
5665 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5666 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5667 && ! CC0_P (XEXP (x
, 0))))
5669 rtx op0
= XEXP (x
, 0);
5670 rtx op1
= XEXP (x
, 1);
5671 enum rtx_code new_code
;
5673 if (GET_CODE (op0
) == COMPARE
)
5674 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5676 /* Simplify our comparison, if possible. */
5677 new_code
= simplify_comparison (code
, &op0
, &op1
);
5679 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5680 if only the low-order bit is possibly nonzero in X (such as when
5681 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5682 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5683 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5686 Remove any ZERO_EXTRACT we made when thinking this was a
5687 comparison. It may now be simpler to use, e.g., an AND. If a
5688 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5689 the call to make_compound_operation in the SET case.
5691 Don't apply these optimizations if the caller would
5692 prefer a comparison rather than a value.
5693 E.g., for the condition in an IF_THEN_ELSE most targets need
5694 an explicit comparison. */
5699 else if (STORE_FLAG_VALUE
== 1
5700 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5701 && op1
== const0_rtx
5702 && mode
== GET_MODE (op0
)
5703 && nonzero_bits (op0
, mode
) == 1)
5704 return gen_lowpart (mode
,
5705 expand_compound_operation (op0
));
5707 else if (STORE_FLAG_VALUE
== 1
5708 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5709 && op1
== const0_rtx
5710 && mode
== GET_MODE (op0
)
5711 && (num_sign_bit_copies (op0
, mode
)
5712 == GET_MODE_PRECISION (mode
)))
5714 op0
= expand_compound_operation (op0
);
5715 return simplify_gen_unary (NEG
, mode
,
5716 gen_lowpart (mode
, op0
),
5720 else if (STORE_FLAG_VALUE
== 1
5721 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5722 && op1
== const0_rtx
5723 && mode
== GET_MODE (op0
)
5724 && nonzero_bits (op0
, mode
) == 1)
5726 op0
= expand_compound_operation (op0
);
5727 return simplify_gen_binary (XOR
, mode
,
5728 gen_lowpart (mode
, op0
),
5732 else if (STORE_FLAG_VALUE
== 1
5733 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5734 && op1
== const0_rtx
5735 && mode
== GET_MODE (op0
)
5736 && (num_sign_bit_copies (op0
, mode
)
5737 == GET_MODE_PRECISION (mode
)))
5739 op0
= expand_compound_operation (op0
);
5740 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5743 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5748 else if (STORE_FLAG_VALUE
== -1
5749 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5750 && op1
== const0_rtx
5751 && (num_sign_bit_copies (op0
, mode
)
5752 == GET_MODE_PRECISION (mode
)))
5753 return gen_lowpart (mode
,
5754 expand_compound_operation (op0
));
5756 else if (STORE_FLAG_VALUE
== -1
5757 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5758 && op1
== const0_rtx
5759 && mode
== GET_MODE (op0
)
5760 && nonzero_bits (op0
, mode
) == 1)
5762 op0
= expand_compound_operation (op0
);
5763 return simplify_gen_unary (NEG
, mode
,
5764 gen_lowpart (mode
, op0
),
5768 else if (STORE_FLAG_VALUE
== -1
5769 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5770 && op1
== const0_rtx
5771 && mode
== GET_MODE (op0
)
5772 && (num_sign_bit_copies (op0
, mode
)
5773 == GET_MODE_PRECISION (mode
)))
5775 op0
= expand_compound_operation (op0
);
5776 return simplify_gen_unary (NOT
, mode
,
5777 gen_lowpart (mode
, op0
),
5781 /* If X is 0/1, (eq X 0) is X-1. */
5782 else if (STORE_FLAG_VALUE
== -1
5783 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5784 && op1
== const0_rtx
5785 && mode
== GET_MODE (op0
)
5786 && nonzero_bits (op0
, mode
) == 1)
5788 op0
= expand_compound_operation (op0
);
5789 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5792 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5793 one bit that might be nonzero, we can convert (ne x 0) to
5794 (ashift x c) where C puts the bit in the sign bit. Remove any
5795 AND with STORE_FLAG_VALUE when we are done, since we are only
5796 going to test the sign bit. */
5797 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5798 && HWI_COMPUTABLE_MODE_P (mode
)
5799 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5800 && op1
== const0_rtx
5801 && mode
== GET_MODE (op0
)
5802 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5804 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5805 expand_compound_operation (op0
),
5806 GET_MODE_PRECISION (mode
) - 1 - i
);
5807 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5813 /* If the code changed, return a whole new comparison.
5814 We also need to avoid using SUBST in cases where
5815 simplify_comparison has widened a comparison with a CONST_INT,
5816 since in that case the wider CONST_INT may fail the sanity
5817 checks in do_SUBST. */
5818 if (new_code
!= code
5819 || (CONST_INT_P (op1
)
5820 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5821 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5822 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5824 /* Otherwise, keep this operation, but maybe change its operands.
5825 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5826 SUBST (XEXP (x
, 0), op0
);
5827 SUBST (XEXP (x
, 1), op1
);
5832 return simplify_if_then_else (x
);
5838 /* If we are processing SET_DEST, we are done. */
5842 return expand_compound_operation (x
);
5845 return simplify_set (x
);
5849 return simplify_logical (x
);
5856 /* If this is a shift by a constant amount, simplify it. */
5857 if (CONST_INT_P (XEXP (x
, 1)))
5858 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5859 INTVAL (XEXP (x
, 1)));
5861 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5863 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5864 ((unsigned HOST_WIDE_INT
) 1
5865 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5877 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5880 simplify_if_then_else (rtx x
)
5882 enum machine_mode mode
= GET_MODE (x
);
5883 rtx cond
= XEXP (x
, 0);
5884 rtx true_rtx
= XEXP (x
, 1);
5885 rtx false_rtx
= XEXP (x
, 2);
5886 enum rtx_code true_code
= GET_CODE (cond
);
5887 int comparison_p
= COMPARISON_P (cond
);
5890 enum rtx_code false_code
;
5893 /* Simplify storing of the truth value. */
5894 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5895 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5896 XEXP (cond
, 0), XEXP (cond
, 1));
5898 /* Also when the truth value has to be reversed. */
5900 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5901 && (reversed
= reversed_comparison (cond
, mode
)))
5904 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5905 in it is being compared against certain values. Get the true and false
5906 comparisons and see if that says anything about the value of each arm. */
5909 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5911 && REG_P (XEXP (cond
, 0)))
5914 rtx from
= XEXP (cond
, 0);
5915 rtx true_val
= XEXP (cond
, 1);
5916 rtx false_val
= true_val
;
5919 /* If FALSE_CODE is EQ, swap the codes and arms. */
5921 if (false_code
== EQ
)
5923 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5924 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5927 /* If we are comparing against zero and the expression being tested has
5928 only a single bit that might be nonzero, that is its value when it is
5929 not equal to zero. Similarly if it is known to be -1 or 0. */
5931 if (true_code
== EQ
&& true_val
== const0_rtx
5932 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5935 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5937 else if (true_code
== EQ
&& true_val
== const0_rtx
5938 && (num_sign_bit_copies (from
, GET_MODE (from
))
5939 == GET_MODE_PRECISION (GET_MODE (from
))))
5942 false_val
= constm1_rtx
;
5945 /* Now simplify an arm if we know the value of the register in the
5946 branch and it is used in the arm. Be careful due to the potential
5947 of locally-shared RTL. */
5949 if (reg_mentioned_p (from
, true_rtx
))
5950 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5952 pc_rtx
, pc_rtx
, 0, 0, 0);
5953 if (reg_mentioned_p (from
, false_rtx
))
5954 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5956 pc_rtx
, pc_rtx
, 0, 0, 0);
5958 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5959 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5961 true_rtx
= XEXP (x
, 1);
5962 false_rtx
= XEXP (x
, 2);
5963 true_code
= GET_CODE (cond
);
5966 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5967 reversed, do so to avoid needing two sets of patterns for
5968 subtract-and-branch insns. Similarly if we have a constant in the true
5969 arm, the false arm is the same as the first operand of the comparison, or
5970 the false arm is more complicated than the true arm. */
5973 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5974 && (true_rtx
== pc_rtx
5975 || (CONSTANT_P (true_rtx
)
5976 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5977 || true_rtx
== const0_rtx
5978 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5979 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5980 && !OBJECT_P (false_rtx
))
5981 || reg_mentioned_p (true_rtx
, false_rtx
)
5982 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5984 true_code
= reversed_comparison_code (cond
, NULL
);
5985 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5986 SUBST (XEXP (x
, 1), false_rtx
);
5987 SUBST (XEXP (x
, 2), true_rtx
);
5989 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5992 /* It is possible that the conditional has been simplified out. */
5993 true_code
= GET_CODE (cond
);
5994 comparison_p
= COMPARISON_P (cond
);
5997 /* If the two arms are identical, we don't need the comparison. */
5999 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6002 /* Convert a == b ? b : a to "a". */
6003 if (true_code
== EQ
&& ! side_effects_p (cond
)
6004 && !HONOR_NANS (mode
)
6005 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6006 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6008 else if (true_code
== NE
&& ! side_effects_p (cond
)
6009 && !HONOR_NANS (mode
)
6010 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6011 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6014 /* Look for cases where we have (abs x) or (neg (abs X)). */
6016 if (GET_MODE_CLASS (mode
) == MODE_INT
6018 && XEXP (cond
, 1) == const0_rtx
6019 && GET_CODE (false_rtx
) == NEG
6020 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6021 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6022 && ! side_effects_p (true_rtx
))
6027 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6031 simplify_gen_unary (NEG
, mode
,
6032 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6038 /* Look for MIN or MAX. */
6040 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6042 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6043 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6044 && ! side_effects_p (cond
))
6049 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6052 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6055 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6058 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6063 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6064 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6065 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6066 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6067 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6068 neither 1 or -1, but it isn't worth checking for. */
6070 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6072 && GET_MODE_CLASS (mode
) == MODE_INT
6073 && ! side_effects_p (x
))
6075 rtx t
= make_compound_operation (true_rtx
, SET
);
6076 rtx f
= make_compound_operation (false_rtx
, SET
);
6077 rtx cond_op0
= XEXP (cond
, 0);
6078 rtx cond_op1
= XEXP (cond
, 1);
6079 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6080 enum machine_mode m
= mode
;
6081 rtx z
= 0, c1
= NULL_RTX
;
6083 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6084 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6085 || GET_CODE (t
) == ASHIFT
6086 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6087 && rtx_equal_p (XEXP (t
, 0), f
))
6088 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6090 /* If an identity-zero op is commutative, check whether there
6091 would be a match if we swapped the operands. */
6092 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6093 || GET_CODE (t
) == XOR
)
6094 && rtx_equal_p (XEXP (t
, 1), f
))
6095 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6096 else if (GET_CODE (t
) == SIGN_EXTEND
6097 && (GET_CODE (XEXP (t
, 0)) == PLUS
6098 || GET_CODE (XEXP (t
, 0)) == MINUS
6099 || GET_CODE (XEXP (t
, 0)) == IOR
6100 || GET_CODE (XEXP (t
, 0)) == XOR
6101 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6102 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6103 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6104 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6105 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6106 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6107 && (num_sign_bit_copies (f
, GET_MODE (f
))
6109 (GET_MODE_PRECISION (mode
)
6110 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6112 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6113 extend_op
= SIGN_EXTEND
;
6114 m
= GET_MODE (XEXP (t
, 0));
6116 else if (GET_CODE (t
) == SIGN_EXTEND
6117 && (GET_CODE (XEXP (t
, 0)) == PLUS
6118 || GET_CODE (XEXP (t
, 0)) == IOR
6119 || GET_CODE (XEXP (t
, 0)) == XOR
)
6120 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6121 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6122 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6123 && (num_sign_bit_copies (f
, GET_MODE (f
))
6125 (GET_MODE_PRECISION (mode
)
6126 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6128 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6129 extend_op
= SIGN_EXTEND
;
6130 m
= GET_MODE (XEXP (t
, 0));
6132 else if (GET_CODE (t
) == ZERO_EXTEND
6133 && (GET_CODE (XEXP (t
, 0)) == PLUS
6134 || GET_CODE (XEXP (t
, 0)) == MINUS
6135 || GET_CODE (XEXP (t
, 0)) == IOR
6136 || GET_CODE (XEXP (t
, 0)) == XOR
6137 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6138 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6139 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6140 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6141 && HWI_COMPUTABLE_MODE_P (mode
)
6142 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6143 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6144 && ((nonzero_bits (f
, GET_MODE (f
))
6145 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6148 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6149 extend_op
= ZERO_EXTEND
;
6150 m
= GET_MODE (XEXP (t
, 0));
6152 else if (GET_CODE (t
) == ZERO_EXTEND
6153 && (GET_CODE (XEXP (t
, 0)) == PLUS
6154 || GET_CODE (XEXP (t
, 0)) == IOR
6155 || GET_CODE (XEXP (t
, 0)) == XOR
)
6156 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6157 && HWI_COMPUTABLE_MODE_P (mode
)
6158 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6159 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6160 && ((nonzero_bits (f
, GET_MODE (f
))
6161 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6164 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6165 extend_op
= ZERO_EXTEND
;
6166 m
= GET_MODE (XEXP (t
, 0));
6171 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6172 cond_op0
, cond_op1
),
6173 pc_rtx
, pc_rtx
, 0, 0, 0);
6174 temp
= simplify_gen_binary (MULT
, m
, temp
,
6175 simplify_gen_binary (MULT
, m
, c1
,
6177 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6178 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6180 if (extend_op
!= UNKNOWN
)
6181 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6187 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6188 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6189 negation of a single bit, we can convert this operation to a shift. We
6190 can actually do this more generally, but it doesn't seem worth it. */
6192 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6193 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6194 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6195 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6196 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6197 == GET_MODE_PRECISION (mode
))
6198 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6200 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6201 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6203 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6204 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6205 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6206 && GET_MODE (XEXP (cond
, 0)) == mode
6207 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6208 == nonzero_bits (XEXP (cond
, 0), mode
)
6209 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6210 return XEXP (cond
, 0);
6215 /* Simplify X, a SET expression. Return the new expression. */
6218 simplify_set (rtx x
)
6220 rtx src
= SET_SRC (x
);
6221 rtx dest
= SET_DEST (x
);
6222 enum machine_mode mode
6223 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6227 /* (set (pc) (return)) gets written as (return). */
6228 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6231 /* Now that we know for sure which bits of SRC we are using, see if we can
6232 simplify the expression for the object knowing that we only need the
6235 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6237 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6238 SUBST (SET_SRC (x
), src
);
6241 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6242 the comparison result and try to simplify it unless we already have used
6243 undobuf.other_insn. */
6244 if ((GET_MODE_CLASS (mode
) == MODE_CC
6245 || GET_CODE (src
) == COMPARE
6247 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6248 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6249 && COMPARISON_P (*cc_use
)
6250 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6252 enum rtx_code old_code
= GET_CODE (*cc_use
);
6253 enum rtx_code new_code
;
6255 int other_changed
= 0;
6256 rtx inner_compare
= NULL_RTX
;
6257 enum machine_mode compare_mode
= GET_MODE (dest
);
6259 if (GET_CODE (src
) == COMPARE
)
6261 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6262 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6264 inner_compare
= op0
;
6265 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6269 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6271 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6274 new_code
= old_code
;
6275 else if (!CONSTANT_P (tmp
))
6277 new_code
= GET_CODE (tmp
);
6278 op0
= XEXP (tmp
, 0);
6279 op1
= XEXP (tmp
, 1);
6283 rtx pat
= PATTERN (other_insn
);
6284 undobuf
.other_insn
= other_insn
;
6285 SUBST (*cc_use
, tmp
);
6287 /* Attempt to simplify CC user. */
6288 if (GET_CODE (pat
) == SET
)
6290 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6291 if (new_rtx
!= NULL_RTX
)
6292 SUBST (SET_SRC (pat
), new_rtx
);
6295 /* Convert X into a no-op move. */
6296 SUBST (SET_DEST (x
), pc_rtx
);
6297 SUBST (SET_SRC (x
), pc_rtx
);
6301 /* Simplify our comparison, if possible. */
6302 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6304 #ifdef SELECT_CC_MODE
6305 /* If this machine has CC modes other than CCmode, check to see if we
6306 need to use a different CC mode here. */
6307 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6308 compare_mode
= GET_MODE (op0
);
6309 else if (inner_compare
6310 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6311 && new_code
== old_code
6312 && op0
== XEXP (inner_compare
, 0)
6313 && op1
== XEXP (inner_compare
, 1))
6314 compare_mode
= GET_MODE (inner_compare
);
6316 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6319 /* If the mode changed, we have to change SET_DEST, the mode in the
6320 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6321 a hard register, just build new versions with the proper mode. If it
6322 is a pseudo, we lose unless it is only time we set the pseudo, in
6323 which case we can safely change its mode. */
6324 if (compare_mode
!= GET_MODE (dest
))
6326 if (can_change_dest_mode (dest
, 0, compare_mode
))
6328 unsigned int regno
= REGNO (dest
);
6331 if (regno
< FIRST_PSEUDO_REGISTER
)
6332 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6335 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6336 new_dest
= regno_reg_rtx
[regno
];
6339 SUBST (SET_DEST (x
), new_dest
);
6340 SUBST (XEXP (*cc_use
, 0), new_dest
);
6347 #endif /* SELECT_CC_MODE */
6349 /* If the code changed, we have to build a new comparison in
6350 undobuf.other_insn. */
6351 if (new_code
!= old_code
)
6353 int other_changed_previously
= other_changed
;
6354 unsigned HOST_WIDE_INT mask
;
6355 rtx old_cc_use
= *cc_use
;
6357 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6361 /* If the only change we made was to change an EQ into an NE or
6362 vice versa, OP0 has only one bit that might be nonzero, and OP1
6363 is zero, check if changing the user of the condition code will
6364 produce a valid insn. If it won't, we can keep the original code
6365 in that insn by surrounding our operation with an XOR. */
6367 if (((old_code
== NE
&& new_code
== EQ
)
6368 || (old_code
== EQ
&& new_code
== NE
))
6369 && ! other_changed_previously
&& op1
== const0_rtx
6370 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6371 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6373 rtx pat
= PATTERN (other_insn
), note
= 0;
6375 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6376 && ! check_asm_operands (pat
)))
6378 *cc_use
= old_cc_use
;
6381 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6389 undobuf
.other_insn
= other_insn
;
6391 /* Otherwise, if we didn't previously have a COMPARE in the
6392 correct mode, we need one. */
6393 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6395 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6398 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6400 SUBST (SET_SRC (x
), op0
);
6403 /* Otherwise, update the COMPARE if needed. */
6404 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6406 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6412 /* Get SET_SRC in a form where we have placed back any
6413 compound expressions. Then do the checks below. */
6414 src
= make_compound_operation (src
, SET
);
6415 SUBST (SET_SRC (x
), src
);
6418 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6419 and X being a REG or (subreg (reg)), we may be able to convert this to
6420 (set (subreg:m2 x) (op)).
6422 We can always do this if M1 is narrower than M2 because that means that
6423 we only care about the low bits of the result.
6425 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6426 perform a narrower operation than requested since the high-order bits will
6427 be undefined. On machine where it is defined, this transformation is safe
6428 as long as M1 and M2 have the same number of words. */
6430 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6431 && !OBJECT_P (SUBREG_REG (src
))
6432 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6434 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6435 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6436 #ifndef WORD_REGISTER_OPERATIONS
6437 && (GET_MODE_SIZE (GET_MODE (src
))
6438 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6440 #ifdef CANNOT_CHANGE_MODE_CLASS
6441 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6442 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6443 GET_MODE (SUBREG_REG (src
)),
6447 || (GET_CODE (dest
) == SUBREG
6448 && REG_P (SUBREG_REG (dest
)))))
6450 SUBST (SET_DEST (x
),
6451 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6453 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6455 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6459 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6462 && GET_CODE (src
) == SUBREG
6463 && subreg_lowpart_p (src
)
6464 && (GET_MODE_PRECISION (GET_MODE (src
))
6465 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6467 rtx inner
= SUBREG_REG (src
);
6468 enum machine_mode inner_mode
= GET_MODE (inner
);
6470 /* Here we make sure that we don't have a sign bit on. */
6471 if (val_signbit_known_clear_p (GET_MODE (src
),
6472 nonzero_bits (inner
, inner_mode
)))
6474 SUBST (SET_SRC (x
), inner
);
6480 #ifdef LOAD_EXTEND_OP
6481 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6482 would require a paradoxical subreg. Replace the subreg with a
6483 zero_extend to avoid the reload that would otherwise be required. */
6485 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6486 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6487 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6488 && SUBREG_BYTE (src
) == 0
6489 && paradoxical_subreg_p (src
)
6490 && MEM_P (SUBREG_REG (src
)))
6493 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6494 GET_MODE (src
), SUBREG_REG (src
)));
6500 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6501 are comparing an item known to be 0 or -1 against 0, use a logical
6502 operation instead. Check for one of the arms being an IOR of the other
6503 arm with some value. We compute three terms to be IOR'ed together. In
6504 practice, at most two will be nonzero. Then we do the IOR's. */
6506 if (GET_CODE (dest
) != PC
6507 && GET_CODE (src
) == IF_THEN_ELSE
6508 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6509 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6510 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6511 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6512 #ifdef HAVE_conditional_move
6513 && ! can_conditionally_move_p (GET_MODE (src
))
6515 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6516 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6517 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6518 && ! side_effects_p (src
))
6520 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6521 ? XEXP (src
, 1) : XEXP (src
, 2));
6522 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6523 ? XEXP (src
, 2) : XEXP (src
, 1));
6524 rtx term1
= const0_rtx
, term2
, term3
;
6526 if (GET_CODE (true_rtx
) == IOR
6527 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6528 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6529 else if (GET_CODE (true_rtx
) == IOR
6530 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6531 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6532 else if (GET_CODE (false_rtx
) == IOR
6533 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6534 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6535 else if (GET_CODE (false_rtx
) == IOR
6536 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6537 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6539 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6540 XEXP (XEXP (src
, 0), 0), true_rtx
);
6541 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6542 simplify_gen_unary (NOT
, GET_MODE (src
),
6543 XEXP (XEXP (src
, 0), 0),
6548 simplify_gen_binary (IOR
, GET_MODE (src
),
6549 simplify_gen_binary (IOR
, GET_MODE (src
),
6556 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6557 whole thing fail. */
6558 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6560 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6563 /* Convert this into a field assignment operation, if possible. */
6564 return make_field_assignment (x
);
6567 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6571 simplify_logical (rtx x
)
6573 enum machine_mode mode
= GET_MODE (x
);
6574 rtx op0
= XEXP (x
, 0);
6575 rtx op1
= XEXP (x
, 1);
6577 switch (GET_CODE (x
))
6580 /* We can call simplify_and_const_int only if we don't lose
6581 any (sign) bits when converting INTVAL (op1) to
6582 "unsigned HOST_WIDE_INT". */
6583 if (CONST_INT_P (op1
)
6584 && (HWI_COMPUTABLE_MODE_P (mode
)
6585 || INTVAL (op1
) > 0))
6587 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6588 if (GET_CODE (x
) != AND
)
6595 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6596 apply the distributive law and then the inverse distributive
6597 law to see if things simplify. */
6598 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6600 rtx result
= distribute_and_simplify_rtx (x
, 0);
6604 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6606 rtx result
= distribute_and_simplify_rtx (x
, 1);
6613 /* If we have (ior (and A B) C), apply the distributive law and then
6614 the inverse distributive law to see if things simplify. */
6616 if (GET_CODE (op0
) == AND
)
6618 rtx result
= distribute_and_simplify_rtx (x
, 0);
6623 if (GET_CODE (op1
) == AND
)
6625 rtx result
= distribute_and_simplify_rtx (x
, 1);
6638 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6639 operations" because they can be replaced with two more basic operations.
6640 ZERO_EXTEND is also considered "compound" because it can be replaced with
6641 an AND operation, which is simpler, though only one operation.
6643 The function expand_compound_operation is called with an rtx expression
6644 and will convert it to the appropriate shifts and AND operations,
6645 simplifying at each stage.
6647 The function make_compound_operation is called to convert an expression
6648 consisting of shifts and ANDs into the equivalent compound expression.
6649 It is the inverse of this function, loosely speaking. */
6652 expand_compound_operation (rtx x
)
6654 unsigned HOST_WIDE_INT pos
= 0, len
;
6656 unsigned int modewidth
;
6659 switch (GET_CODE (x
))
6664 /* We can't necessarily use a const_int for a multiword mode;
6665 it depends on implicitly extending the value.
6666 Since we don't know the right way to extend it,
6667 we can't tell whether the implicit way is right.
6669 Even for a mode that is no wider than a const_int,
6670 we can't win, because we need to sign extend one of its bits through
6671 the rest of it, and we don't know which bit. */
6672 if (CONST_INT_P (XEXP (x
, 0)))
6675 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6676 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6677 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6678 reloaded. If not for that, MEM's would very rarely be safe.
6680 Reject MODEs bigger than a word, because we might not be able
6681 to reference a two-register group starting with an arbitrary register
6682 (and currently gen_lowpart might crash for a SUBREG). */
6684 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6687 /* Reject MODEs that aren't scalar integers because turning vector
6688 or complex modes into shifts causes problems. */
6690 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6693 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6694 /* If the inner object has VOIDmode (the only way this can happen
6695 is if it is an ASM_OPERANDS), we can't do anything since we don't
6696 know how much masking to do. */
6705 /* ... fall through ... */
6708 /* If the operand is a CLOBBER, just return it. */
6709 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6712 if (!CONST_INT_P (XEXP (x
, 1))
6713 || !CONST_INT_P (XEXP (x
, 2))
6714 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6717 /* Reject MODEs that aren't scalar integers because turning vector
6718 or complex modes into shifts causes problems. */
6720 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6723 len
= INTVAL (XEXP (x
, 1));
6724 pos
= INTVAL (XEXP (x
, 2));
6726 /* This should stay within the object being extracted, fail otherwise. */
6727 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6730 if (BITS_BIG_ENDIAN
)
6731 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6738 /* Convert sign extension to zero extension, if we know that the high
6739 bit is not set, as this is easier to optimize. It will be converted
6740 back to cheaper alternative in make_extraction. */
6741 if (GET_CODE (x
) == SIGN_EXTEND
6742 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6743 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6744 & ~(((unsigned HOST_WIDE_INT
)
6745 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6749 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6750 rtx temp2
= expand_compound_operation (temp
);
6752 /* Make sure this is a profitable operation. */
6753 if (set_src_cost (x
, optimize_this_for_speed_p
)
6754 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6756 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6757 > set_src_cost (temp
, optimize_this_for_speed_p
))
6763 /* We can optimize some special cases of ZERO_EXTEND. */
6764 if (GET_CODE (x
) == ZERO_EXTEND
)
6766 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6767 know that the last value didn't have any inappropriate bits
6769 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6770 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6771 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6772 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6773 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6774 return XEXP (XEXP (x
, 0), 0);
6776 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6777 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6778 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6779 && subreg_lowpart_p (XEXP (x
, 0))
6780 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6781 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6782 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6783 return SUBREG_REG (XEXP (x
, 0));
6785 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6786 is a comparison and STORE_FLAG_VALUE permits. This is like
6787 the first case, but it works even when GET_MODE (x) is larger
6788 than HOST_WIDE_INT. */
6789 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6790 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6791 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6792 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6793 <= HOST_BITS_PER_WIDE_INT
)
6794 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6795 return XEXP (XEXP (x
, 0), 0);
6797 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6798 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6799 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6800 && subreg_lowpart_p (XEXP (x
, 0))
6801 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6802 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6803 <= HOST_BITS_PER_WIDE_INT
)
6804 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6805 return SUBREG_REG (XEXP (x
, 0));
6809 /* If we reach here, we want to return a pair of shifts. The inner
6810 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6811 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6812 logical depending on the value of UNSIGNEDP.
6814 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6815 converted into an AND of a shift.
6817 We must check for the case where the left shift would have a negative
6818 count. This can happen in a case like (x >> 31) & 255 on machines
6819 that can't shift by a constant. On those machines, we would first
6820 combine the shift with the AND to produce a variable-position
6821 extraction. Then the constant of 31 would be substituted in
6822 to produce such a position. */
6824 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6825 if (modewidth
>= pos
+ len
)
6827 enum machine_mode mode
= GET_MODE (x
);
6828 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6829 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6831 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6832 tem
, modewidth
- pos
- len
);
6833 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6834 mode
, tem
, modewidth
- len
);
6836 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6837 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6838 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6841 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6843 /* Any other cases we can't handle. */
6846 /* If we couldn't do this for some reason, return the original
6848 if (GET_CODE (tem
) == CLOBBER
)
6854 /* X is a SET which contains an assignment of one object into
6855 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6856 or certain SUBREGS). If possible, convert it into a series of
6859 We half-heartedly support variable positions, but do not at all
6860 support variable lengths. */
6863 expand_field_assignment (const_rtx x
)
6866 rtx pos
; /* Always counts from low bit. */
6868 rtx mask
, cleared
, masked
;
6869 enum machine_mode compute_mode
;
6871 /* Loop until we find something we can't simplify. */
6874 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6875 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6877 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6878 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6879 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6881 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6882 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6884 inner
= XEXP (SET_DEST (x
), 0);
6885 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6886 pos
= XEXP (SET_DEST (x
), 2);
6888 /* A constant position should stay within the width of INNER. */
6889 if (CONST_INT_P (pos
)
6890 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6893 if (BITS_BIG_ENDIAN
)
6895 if (CONST_INT_P (pos
))
6896 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6898 else if (GET_CODE (pos
) == MINUS
6899 && CONST_INT_P (XEXP (pos
, 1))
6900 && (INTVAL (XEXP (pos
, 1))
6901 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6902 /* If position is ADJUST - X, new position is X. */
6903 pos
= XEXP (pos
, 0);
6906 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
6907 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6908 gen_int_mode (prec
- len
,
6915 /* A SUBREG between two modes that occupy the same numbers of words
6916 can be done by moving the SUBREG to the source. */
6917 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6918 /* We need SUBREGs to compute nonzero_bits properly. */
6919 && nonzero_sign_valid
6920 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6921 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6922 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6923 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6925 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6927 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6934 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6935 inner
= SUBREG_REG (inner
);
6937 compute_mode
= GET_MODE (inner
);
6939 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6940 if (! SCALAR_INT_MODE_P (compute_mode
))
6942 enum machine_mode imode
;
6944 /* Don't do anything for vector or complex integral types. */
6945 if (! FLOAT_MODE_P (compute_mode
))
6948 /* Try to find an integral mode to pun with. */
6949 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6950 if (imode
== BLKmode
)
6953 compute_mode
= imode
;
6954 inner
= gen_lowpart (imode
, inner
);
6957 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6958 if (len
>= HOST_BITS_PER_WIDE_INT
)
6961 /* Now compute the equivalent expression. Make a copy of INNER
6962 for the SET_DEST in case it is a MEM into which we will substitute;
6963 we don't want shared RTL in that case. */
6964 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6966 cleared
= simplify_gen_binary (AND
, compute_mode
,
6967 simplify_gen_unary (NOT
, compute_mode
,
6968 simplify_gen_binary (ASHIFT
,
6973 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6974 simplify_gen_binary (
6976 gen_lowpart (compute_mode
, SET_SRC (x
)),
6980 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6981 simplify_gen_binary (IOR
, compute_mode
,
6988 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6989 it is an RTX that represents the (variable) starting position; otherwise,
6990 POS is the (constant) starting bit position. Both are counted from the LSB.
6992 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6994 IN_DEST is nonzero if this is a reference in the destination of a SET.
6995 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6996 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6999 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7000 ZERO_EXTRACT should be built even for bits starting at bit 0.
7002 MODE is the desired mode of the result (if IN_DEST == 0).
7004 The result is an RTX for the extraction or NULL_RTX if the target
7008 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7009 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7010 int in_dest
, int in_compare
)
7012 /* This mode describes the size of the storage area
7013 to fetch the overall value from. Within that, we
7014 ignore the POS lowest bits, etc. */
7015 enum machine_mode is_mode
= GET_MODE (inner
);
7016 enum machine_mode inner_mode
;
7017 enum machine_mode wanted_inner_mode
;
7018 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7019 enum machine_mode pos_mode
= word_mode
;
7020 enum machine_mode extraction_mode
= word_mode
;
7021 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7023 rtx orig_pos_rtx
= pos_rtx
;
7024 HOST_WIDE_INT orig_pos
;
7026 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7027 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7029 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7031 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7032 consider just the QI as the memory to extract from.
7033 The subreg adds or removes high bits; its mode is
7034 irrelevant to the meaning of this extraction,
7035 since POS and LEN count from the lsb. */
7036 if (MEM_P (SUBREG_REG (inner
)))
7037 is_mode
= GET_MODE (SUBREG_REG (inner
));
7038 inner
= SUBREG_REG (inner
);
7040 else if (GET_CODE (inner
) == ASHIFT
7041 && CONST_INT_P (XEXP (inner
, 1))
7042 && pos_rtx
== 0 && pos
== 0
7043 && len
> UINTVAL (XEXP (inner
, 1)))
7045 /* We're extracting the least significant bits of an rtx
7046 (ashift X (const_int C)), where LEN > C. Extract the
7047 least significant (LEN - C) bits of X, giving an rtx
7048 whose mode is MODE, then shift it left C times. */
7049 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7050 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7051 unsignedp
, in_dest
, in_compare
);
7053 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7055 else if (GET_CODE (inner
) == TRUNCATE
)
7056 inner
= XEXP (inner
, 0);
7058 inner_mode
= GET_MODE (inner
);
7060 /* See if this can be done without an extraction. We never can if the
7061 width of the field is not the same as that of some integer mode. For
7062 registers, we can only avoid the extraction if the position is at the
7063 low-order bit and this is either not in the destination or we have the
7064 appropriate STRICT_LOW_PART operation available.
7066 For MEM, we can avoid an extract if the field starts on an appropriate
7067 boundary and we can change the mode of the memory reference. */
7069 if (tmode
!= BLKmode
7070 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7072 && (inner_mode
== tmode
7074 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7075 || reg_truncated_to_mode (tmode
, inner
))
7078 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7079 || (MEM_P (inner
) && pos_rtx
== 0
7081 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7082 : BITS_PER_UNIT
)) == 0
7083 /* We can't do this if we are widening INNER_MODE (it
7084 may not be aligned, for one thing). */
7085 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7086 && (inner_mode
== tmode
7087 || (! mode_dependent_address_p (XEXP (inner
, 0),
7088 MEM_ADDR_SPACE (inner
))
7089 && ! MEM_VOLATILE_P (inner
))))))
7091 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7092 field. If the original and current mode are the same, we need not
7093 adjust the offset. Otherwise, we do if bytes big endian.
7095 If INNER is not a MEM, get a piece consisting of just the field
7096 of interest (in this case POS % BITS_PER_WORD must be 0). */
7100 HOST_WIDE_INT offset
;
7102 /* POS counts from lsb, but make OFFSET count in memory order. */
7103 if (BYTES_BIG_ENDIAN
)
7104 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7106 offset
= pos
/ BITS_PER_UNIT
;
7108 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7110 else if (REG_P (inner
))
7112 if (tmode
!= inner_mode
)
7114 /* We can't call gen_lowpart in a DEST since we
7115 always want a SUBREG (see below) and it would sometimes
7116 return a new hard register. */
7119 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7121 if (WORDS_BIG_ENDIAN
7122 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7123 final_word
= ((GET_MODE_SIZE (inner_mode
)
7124 - GET_MODE_SIZE (tmode
))
7125 / UNITS_PER_WORD
) - final_word
;
7127 final_word
*= UNITS_PER_WORD
;
7128 if (BYTES_BIG_ENDIAN
&&
7129 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7130 final_word
+= (GET_MODE_SIZE (inner_mode
)
7131 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7133 /* Avoid creating invalid subregs, for example when
7134 simplifying (x>>32)&255. */
7135 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7138 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7141 new_rtx
= gen_lowpart (tmode
, inner
);
7147 new_rtx
= force_to_mode (inner
, tmode
,
7148 len
>= HOST_BITS_PER_WIDE_INT
7149 ? ~(unsigned HOST_WIDE_INT
) 0
7150 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7153 /* If this extraction is going into the destination of a SET,
7154 make a STRICT_LOW_PART unless we made a MEM. */
7157 return (MEM_P (new_rtx
) ? new_rtx
7158 : (GET_CODE (new_rtx
) != SUBREG
7159 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7160 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7165 if (CONST_SCALAR_INT_P (new_rtx
))
7166 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7167 mode
, new_rtx
, tmode
);
7169 /* If we know that no extraneous bits are set, and that the high
7170 bit is not set, convert the extraction to the cheaper of
7171 sign and zero extension, that are equivalent in these cases. */
7172 if (flag_expensive_optimizations
7173 && (HWI_COMPUTABLE_MODE_P (tmode
)
7174 && ((nonzero_bits (new_rtx
, tmode
)
7175 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7178 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7179 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7181 /* Prefer ZERO_EXTENSION, since it gives more information to
7183 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7184 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7189 /* Otherwise, sign- or zero-extend unless we already are in the
7192 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7196 /* Unless this is a COMPARE or we have a funny memory reference,
7197 don't do anything with zero-extending field extracts starting at
7198 the low-order bit since they are simple AND operations. */
7199 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7200 && ! in_compare
&& unsignedp
)
7203 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7204 if the position is not a constant and the length is not 1. In all
7205 other cases, we would only be going outside our object in cases when
7206 an original shift would have been undefined. */
7208 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7209 || (pos_rtx
!= 0 && len
!= 1)))
7212 enum extraction_pattern pattern
= (in_dest
? EP_insv
7213 : unsignedp
? EP_extzv
: EP_extv
);
7215 /* If INNER is not from memory, we want it to have the mode of a register
7216 extraction pattern's structure operand, or word_mode if there is no
7217 such pattern. The same applies to extraction_mode and pos_mode
7218 and their respective operands.
7220 For memory, assume that the desired extraction_mode and pos_mode
7221 are the same as for a register operation, since at present we don't
7222 have named patterns for aligned memory structures. */
7223 struct extraction_insn insn
;
7224 if (get_best_reg_extraction_insn (&insn
, pattern
,
7225 GET_MODE_BITSIZE (inner_mode
), mode
))
7227 wanted_inner_reg_mode
= insn
.struct_mode
;
7228 pos_mode
= insn
.pos_mode
;
7229 extraction_mode
= insn
.field_mode
;
7232 /* Never narrow an object, since that might not be safe. */
7234 if (mode
!= VOIDmode
7235 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7236 extraction_mode
= mode
;
7239 wanted_inner_mode
= wanted_inner_reg_mode
;
7242 /* Be careful not to go beyond the extracted object and maintain the
7243 natural alignment of the memory. */
7244 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7245 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7246 > GET_MODE_BITSIZE (wanted_inner_mode
))
7248 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7249 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7255 if (BITS_BIG_ENDIAN
)
7257 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7258 BITS_BIG_ENDIAN style. If position is constant, compute new
7259 position. Otherwise, build subtraction.
7260 Note that POS is relative to the mode of the original argument.
7261 If it's a MEM we need to recompute POS relative to that.
7262 However, if we're extracting from (or inserting into) a register,
7263 we want to recompute POS relative to wanted_inner_mode. */
7264 int width
= (MEM_P (inner
)
7265 ? GET_MODE_BITSIZE (is_mode
)
7266 : GET_MODE_BITSIZE (wanted_inner_mode
));
7269 pos
= width
- len
- pos
;
7272 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7273 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7275 /* POS may be less than 0 now, but we check for that below.
7276 Note that it can only be less than 0 if !MEM_P (inner). */
7279 /* If INNER has a wider mode, and this is a constant extraction, try to
7280 make it smaller and adjust the byte to point to the byte containing
7282 if (wanted_inner_mode
!= VOIDmode
7283 && inner_mode
!= wanted_inner_mode
7285 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7287 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7288 && ! MEM_VOLATILE_P (inner
))
7292 /* The computations below will be correct if the machine is big
7293 endian in both bits and bytes or little endian in bits and bytes.
7294 If it is mixed, we must adjust. */
7296 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7297 adjust OFFSET to compensate. */
7298 if (BYTES_BIG_ENDIAN
7299 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7300 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7302 /* We can now move to the desired byte. */
7303 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7304 * GET_MODE_SIZE (wanted_inner_mode
);
7305 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7307 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7308 && is_mode
!= wanted_inner_mode
)
7309 offset
= (GET_MODE_SIZE (is_mode
)
7310 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7312 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7315 /* If INNER is not memory, get it into the proper mode. If we are changing
7316 its mode, POS must be a constant and smaller than the size of the new
7318 else if (!MEM_P (inner
))
7320 /* On the LHS, don't create paradoxical subregs implicitely truncating
7321 the register unless TRULY_NOOP_TRUNCATION. */
7323 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7327 if (GET_MODE (inner
) != wanted_inner_mode
7329 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7335 inner
= force_to_mode (inner
, wanted_inner_mode
,
7337 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7338 ? ~(unsigned HOST_WIDE_INT
) 0
7339 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7344 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7345 have to zero extend. Otherwise, we can just use a SUBREG. */
7347 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7349 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7350 GET_MODE (pos_rtx
));
7352 /* If we know that no extraneous bits are set, and that the high
7353 bit is not set, convert extraction to cheaper one - either
7354 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7356 if (flag_expensive_optimizations
7357 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7358 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7359 & ~(((unsigned HOST_WIDE_INT
)
7360 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7364 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7365 GET_MODE (pos_rtx
));
7367 /* Prefer ZERO_EXTENSION, since it gives more information to
7369 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7370 < set_src_cost (temp
, optimize_this_for_speed_p
))
7376 /* Make POS_RTX unless we already have it and it is correct. If we don't
7377 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7379 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7380 pos_rtx
= orig_pos_rtx
;
7382 else if (pos_rtx
== 0)
7383 pos_rtx
= GEN_INT (pos
);
7385 /* Make the required operation. See if we can use existing rtx. */
7386 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7387 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7389 new_rtx
= gen_lowpart (mode
, new_rtx
);
7394 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7395 with any other operations in X. Return X without that shift if so. */
7398 extract_left_shift (rtx x
, int count
)
7400 enum rtx_code code
= GET_CODE (x
);
7401 enum machine_mode mode
= GET_MODE (x
);
7407 /* This is the shift itself. If it is wide enough, we will return
7408 either the value being shifted if the shift count is equal to
7409 COUNT or a shift for the difference. */
7410 if (CONST_INT_P (XEXP (x
, 1))
7411 && INTVAL (XEXP (x
, 1)) >= count
)
7412 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7413 INTVAL (XEXP (x
, 1)) - count
);
7417 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7418 return simplify_gen_unary (code
, mode
, tem
, mode
);
7422 case PLUS
: case IOR
: case XOR
: case AND
:
7423 /* If we can safely shift this constant and we find the inner shift,
7424 make a new operation. */
7425 if (CONST_INT_P (XEXP (x
, 1))
7426 && (UINTVAL (XEXP (x
, 1))
7427 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7428 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7430 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7431 return simplify_gen_binary (code
, mode
, tem
,
7432 gen_int_mode (val
, mode
));
7443 /* Look at the expression rooted at X. Look for expressions
7444 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7445 Form these expressions.
7447 Return the new rtx, usually just X.
7449 Also, for machines like the VAX that don't have logical shift insns,
7450 try to convert logical to arithmetic shift operations in cases where
7451 they are equivalent. This undoes the canonicalizations to logical
7452 shifts done elsewhere.
7454 We try, as much as possible, to re-use rtl expressions to save memory.
7456 IN_CODE says what kind of expression we are processing. Normally, it is
7457 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7458 being kludges), it is MEM. When processing the arguments of a comparison
7459 or a COMPARE against zero, it is COMPARE. */
7462 make_compound_operation (rtx x
, enum rtx_code in_code
)
7464 enum rtx_code code
= GET_CODE (x
);
7465 enum machine_mode mode
= GET_MODE (x
);
7466 int mode_width
= GET_MODE_PRECISION (mode
);
7468 enum rtx_code next_code
;
7474 /* Select the code to be used in recursive calls. Once we are inside an
7475 address, we stay there. If we have a comparison, set to COMPARE,
7476 but once inside, go back to our default of SET. */
7478 next_code
= (code
== MEM
? MEM
7479 : ((code
== PLUS
|| code
== MINUS
)
7480 && SCALAR_INT_MODE_P (mode
)) ? MEM
7481 : ((code
== COMPARE
|| COMPARISON_P (x
))
7482 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7483 : in_code
== COMPARE
? SET
: in_code
);
7485 /* Process depending on the code of this operation. If NEW is set
7486 nonzero, it will be returned. */
7491 /* Convert shifts by constants into multiplications if inside
7493 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7494 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7495 && INTVAL (XEXP (x
, 1)) >= 0
7496 && SCALAR_INT_MODE_P (mode
))
7498 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7499 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7501 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7502 if (GET_CODE (new_rtx
) == NEG
)
7504 new_rtx
= XEXP (new_rtx
, 0);
7507 multval
= trunc_int_for_mode (multval
, mode
);
7508 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7515 lhs
= make_compound_operation (lhs
, next_code
);
7516 rhs
= make_compound_operation (rhs
, next_code
);
7517 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7518 && SCALAR_INT_MODE_P (mode
))
7520 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7522 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7524 else if (GET_CODE (lhs
) == MULT
7525 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7527 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7528 simplify_gen_unary (NEG
, mode
,
7531 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7535 SUBST (XEXP (x
, 0), lhs
);
7536 SUBST (XEXP (x
, 1), rhs
);
7539 x
= gen_lowpart (mode
, new_rtx
);
7545 lhs
= make_compound_operation (lhs
, next_code
);
7546 rhs
= make_compound_operation (rhs
, next_code
);
7547 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7548 && SCALAR_INT_MODE_P (mode
))
7550 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7552 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7554 else if (GET_CODE (rhs
) == MULT
7555 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7557 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7558 simplify_gen_unary (NEG
, mode
,
7561 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7565 SUBST (XEXP (x
, 0), lhs
);
7566 SUBST (XEXP (x
, 1), rhs
);
7569 return gen_lowpart (mode
, new_rtx
);
7572 /* If the second operand is not a constant, we can't do anything
7574 if (!CONST_INT_P (XEXP (x
, 1)))
7577 /* If the constant is a power of two minus one and the first operand
7578 is a logical right shift, make an extraction. */
7579 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7580 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7582 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7583 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7584 0, in_code
== COMPARE
);
7587 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7588 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7589 && subreg_lowpart_p (XEXP (x
, 0))
7590 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7591 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7593 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7595 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7596 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7597 0, in_code
== COMPARE
);
7599 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7600 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7601 || GET_CODE (XEXP (x
, 0)) == IOR
)
7602 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7603 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7604 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7606 /* Apply the distributive law, and then try to make extractions. */
7607 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7608 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7610 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7612 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7615 /* If we are have (and (rotate X C) M) and C is larger than the number
7616 of bits in M, this is an extraction. */
7618 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7619 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7620 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7621 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7623 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7624 new_rtx
= make_extraction (mode
, new_rtx
,
7625 (GET_MODE_PRECISION (mode
)
7626 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7627 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7630 /* On machines without logical shifts, if the operand of the AND is
7631 a logical shift and our mask turns off all the propagated sign
7632 bits, we can replace the logical shift with an arithmetic shift. */
7633 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7634 && !have_insn_for (LSHIFTRT
, mode
)
7635 && have_insn_for (ASHIFTRT
, mode
)
7636 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7637 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7638 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7639 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7641 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7643 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7644 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7646 gen_rtx_ASHIFTRT (mode
,
7647 make_compound_operation
7648 (XEXP (XEXP (x
, 0), 0), next_code
),
7649 XEXP (XEXP (x
, 0), 1)));
7652 /* If the constant is one less than a power of two, this might be
7653 representable by an extraction even if no shift is present.
7654 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7655 we are in a COMPARE. */
7656 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7657 new_rtx
= make_extraction (mode
,
7658 make_compound_operation (XEXP (x
, 0),
7660 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7662 /* If we are in a comparison and this is an AND with a power of two,
7663 convert this into the appropriate bit extract. */
7664 else if (in_code
== COMPARE
7665 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7666 new_rtx
= make_extraction (mode
,
7667 make_compound_operation (XEXP (x
, 0),
7669 i
, NULL_RTX
, 1, 1, 0, 1);
7674 /* If the sign bit is known to be zero, replace this with an
7675 arithmetic shift. */
7676 if (have_insn_for (ASHIFTRT
, mode
)
7677 && ! have_insn_for (LSHIFTRT
, mode
)
7678 && mode_width
<= HOST_BITS_PER_WIDE_INT
7679 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7681 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7682 make_compound_operation (XEXP (x
, 0),
7688 /* ... fall through ... */
7694 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7695 this is a SIGN_EXTRACT. */
7696 if (CONST_INT_P (rhs
)
7697 && GET_CODE (lhs
) == ASHIFT
7698 && CONST_INT_P (XEXP (lhs
, 1))
7699 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7700 && INTVAL (XEXP (lhs
, 1)) >= 0
7701 && INTVAL (rhs
) < mode_width
)
7703 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7704 new_rtx
= make_extraction (mode
, new_rtx
,
7705 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7706 NULL_RTX
, mode_width
- INTVAL (rhs
),
7707 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7711 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7712 If so, try to merge the shifts into a SIGN_EXTEND. We could
7713 also do this for some cases of SIGN_EXTRACT, but it doesn't
7714 seem worth the effort; the case checked for occurs on Alpha. */
7717 && ! (GET_CODE (lhs
) == SUBREG
7718 && (OBJECT_P (SUBREG_REG (lhs
))))
7719 && CONST_INT_P (rhs
)
7720 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7721 && INTVAL (rhs
) < mode_width
7722 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7723 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7724 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7725 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7730 /* Call ourselves recursively on the inner expression. If we are
7731 narrowing the object and it has a different RTL code from
7732 what it originally did, do this SUBREG as a force_to_mode. */
7734 rtx inner
= SUBREG_REG (x
), simplified
;
7735 enum rtx_code subreg_code
= in_code
;
7737 /* If in_code is COMPARE, it isn't always safe to pass it through
7738 to the recursive make_compound_operation call. */
7739 if (subreg_code
== COMPARE
7740 && (!subreg_lowpart_p (x
)
7741 || GET_CODE (inner
) == SUBREG
7742 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7743 is (const_int 0), rather than
7744 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7745 || (GET_CODE (inner
) == AND
7746 && CONST_INT_P (XEXP (inner
, 1))
7747 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7748 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7749 >= GET_MODE_BITSIZE (mode
))))
7752 tem
= make_compound_operation (inner
, subreg_code
);
7755 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7759 if (GET_CODE (tem
) != GET_CODE (inner
)
7760 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7761 && subreg_lowpart_p (x
))
7764 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7766 /* If we have something other than a SUBREG, we might have
7767 done an expansion, so rerun ourselves. */
7768 if (GET_CODE (newer
) != SUBREG
)
7769 newer
= make_compound_operation (newer
, in_code
);
7771 /* force_to_mode can expand compounds. If it just re-expanded the
7772 compound, use gen_lowpart to convert to the desired mode. */
7773 if (rtx_equal_p (newer
, x
)
7774 /* Likewise if it re-expanded the compound only partially.
7775 This happens for SUBREG of ZERO_EXTRACT if they extract
7776 the same number of bits. */
7777 || (GET_CODE (newer
) == SUBREG
7778 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7779 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7780 && GET_CODE (inner
) == AND
7781 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7782 return gen_lowpart (GET_MODE (x
), tem
);
7798 x
= gen_lowpart (mode
, new_rtx
);
7799 code
= GET_CODE (x
);
7802 /* Now recursively process each operand of this operation. We need to
7803 handle ZERO_EXTEND specially so that we don't lose track of the
7805 if (GET_CODE (x
) == ZERO_EXTEND
)
7807 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7808 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7809 new_rtx
, GET_MODE (XEXP (x
, 0)));
7812 SUBST (XEXP (x
, 0), new_rtx
);
7816 fmt
= GET_RTX_FORMAT (code
);
7817 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7820 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7821 SUBST (XEXP (x
, i
), new_rtx
);
7823 else if (fmt
[i
] == 'E')
7824 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7826 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7827 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7831 /* If this is a commutative operation, the changes to the operands
7832 may have made it noncanonical. */
7833 if (COMMUTATIVE_ARITH_P (x
)
7834 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7837 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7838 SUBST (XEXP (x
, 1), tem
);
7844 /* Given M see if it is a value that would select a field of bits
7845 within an item, but not the entire word. Return -1 if not.
7846 Otherwise, return the starting position of the field, where 0 is the
7849 *PLEN is set to the length of the field. */
7852 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7854 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7855 int pos
= m
? ctz_hwi (m
) : -1;
7859 /* Now shift off the low-order zero bits and see if we have a
7860 power of two minus 1. */
7861 len
= exact_log2 ((m
>> pos
) + 1);
7870 /* If X refers to a register that equals REG in value, replace these
7871 references with REG. */
7873 canon_reg_for_combine (rtx x
, rtx reg
)
7880 enum rtx_code code
= GET_CODE (x
);
7881 switch (GET_RTX_CLASS (code
))
7884 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7885 if (op0
!= XEXP (x
, 0))
7886 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7891 case RTX_COMM_ARITH
:
7892 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7893 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7894 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7895 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7899 case RTX_COMM_COMPARE
:
7900 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7901 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7902 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7903 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7904 GET_MODE (op0
), op0
, op1
);
7908 case RTX_BITFIELD_OPS
:
7909 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7910 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7911 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7912 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7913 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7914 GET_MODE (op0
), op0
, op1
, op2
);
7919 if (rtx_equal_p (get_last_value (reg
), x
)
7920 || rtx_equal_p (reg
, get_last_value (x
)))
7929 fmt
= GET_RTX_FORMAT (code
);
7931 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7934 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7935 if (op
!= XEXP (x
, i
))
7945 else if (fmt
[i
] == 'E')
7948 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7950 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7951 if (op
!= XVECEXP (x
, i
, j
))
7958 XVECEXP (x
, i
, j
) = op
;
7969 /* Return X converted to MODE. If the value is already truncated to
7970 MODE we can just return a subreg even though in the general case we
7971 would need an explicit truncation. */
7974 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7976 if (!CONST_INT_P (x
)
7977 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7978 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
7979 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7981 /* Bit-cast X into an integer mode. */
7982 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7983 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7984 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7988 return gen_lowpart (mode
, x
);
7991 /* See if X can be simplified knowing that we will only refer to it in
7992 MODE and will only refer to those bits that are nonzero in MASK.
7993 If other bits are being computed or if masking operations are done
7994 that select a superset of the bits in MASK, they can sometimes be
7997 Return a possibly simplified expression, but always convert X to
7998 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8000 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8001 are all off in X. This is used when X will be complemented, by either
8002 NOT, NEG, or XOR. */
8005 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8008 enum rtx_code code
= GET_CODE (x
);
8009 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8010 enum machine_mode op_mode
;
8011 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8014 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8015 code below will do the wrong thing since the mode of such an
8016 expression is VOIDmode.
8018 Also do nothing if X is a CLOBBER; this can happen if X was
8019 the return value from a call to gen_lowpart. */
8020 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8023 /* We want to perform the operation is its present mode unless we know
8024 that the operation is valid in MODE, in which case we do the operation
8026 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8027 && have_insn_for (code
, mode
))
8028 ? mode
: GET_MODE (x
));
8030 /* It is not valid to do a right-shift in a narrower mode
8031 than the one it came in with. */
8032 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8033 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8034 op_mode
= GET_MODE (x
);
8036 /* Truncate MASK to fit OP_MODE. */
8038 mask
&= GET_MODE_MASK (op_mode
);
8040 /* When we have an arithmetic operation, or a shift whose count we
8041 do not know, we need to assume that all bits up to the highest-order
8042 bit in MASK will be needed. This is how we form such a mask. */
8043 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8044 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8046 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8049 /* Determine what bits of X are guaranteed to be (non)zero. */
8050 nonzero
= nonzero_bits (x
, mode
);
8052 /* If none of the bits in X are needed, return a zero. */
8053 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8056 /* If X is a CONST_INT, return a new one. Do this here since the
8057 test below will fail. */
8058 if (CONST_INT_P (x
))
8060 if (SCALAR_INT_MODE_P (mode
))
8061 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8064 x
= GEN_INT (INTVAL (x
) & mask
);
8065 return gen_lowpart_common (mode
, x
);
8069 /* If X is narrower than MODE and we want all the bits in X's mode, just
8070 get X in the proper mode. */
8071 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8072 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8073 return gen_lowpart (mode
, x
);
8075 /* We can ignore the effect of a SUBREG if it narrows the mode or
8076 if the constant masks to zero all the bits the mode doesn't have. */
8077 if (GET_CODE (x
) == SUBREG
8078 && subreg_lowpart_p (x
)
8079 && ((GET_MODE_SIZE (GET_MODE (x
))
8080 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8082 & GET_MODE_MASK (GET_MODE (x
))
8083 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8084 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8086 /* The arithmetic simplifications here only work for scalar integer modes. */
8087 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8088 return gen_lowpart_or_truncate (mode
, x
);
8093 /* If X is a (clobber (const_int)), return it since we know we are
8094 generating something that won't match. */
8101 x
= expand_compound_operation (x
);
8102 if (GET_CODE (x
) != code
)
8103 return force_to_mode (x
, mode
, mask
, next_select
);
8107 /* Similarly for a truncate. */
8108 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8111 /* If this is an AND with a constant, convert it into an AND
8112 whose constant is the AND of that constant with MASK. If it
8113 remains an AND of MASK, delete it since it is redundant. */
8115 if (CONST_INT_P (XEXP (x
, 1)))
8117 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8118 mask
& INTVAL (XEXP (x
, 1)));
8120 /* If X is still an AND, see if it is an AND with a mask that
8121 is just some low-order bits. If so, and it is MASK, we don't
8124 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8125 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8129 /* If it remains an AND, try making another AND with the bits
8130 in the mode mask that aren't in MASK turned on. If the
8131 constant in the AND is wide enough, this might make a
8132 cheaper constant. */
8134 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8135 && GET_MODE_MASK (GET_MODE (x
)) != mask
8136 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8138 unsigned HOST_WIDE_INT cval
8139 = UINTVAL (XEXP (x
, 1))
8140 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8143 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8144 gen_int_mode (cval
, GET_MODE (x
)));
8145 if (set_src_cost (y
, optimize_this_for_speed_p
)
8146 < set_src_cost (x
, optimize_this_for_speed_p
))
8156 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8157 low-order bits (as in an alignment operation) and FOO is already
8158 aligned to that boundary, mask C1 to that boundary as well.
8159 This may eliminate that PLUS and, later, the AND. */
8162 unsigned int width
= GET_MODE_PRECISION (mode
);
8163 unsigned HOST_WIDE_INT smask
= mask
;
8165 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8166 number, sign extend it. */
8168 if (width
< HOST_BITS_PER_WIDE_INT
8169 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8170 smask
|= HOST_WIDE_INT_M1U
<< width
;
8172 if (CONST_INT_P (XEXP (x
, 1))
8173 && exact_log2 (- smask
) >= 0
8174 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8175 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8176 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8177 (INTVAL (XEXP (x
, 1)) & smask
)),
8178 mode
, smask
, next_select
);
8181 /* ... fall through ... */
8184 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8185 most significant bit in MASK since carries from those bits will
8186 affect the bits we are interested in. */
8191 /* If X is (minus C Y) where C's least set bit is larger than any bit
8192 in the mask, then we may replace with (neg Y). */
8193 if (CONST_INT_P (XEXP (x
, 0))
8194 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8195 & -INTVAL (XEXP (x
, 0))))
8198 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8200 return force_to_mode (x
, mode
, mask
, next_select
);
8203 /* Similarly, if C contains every bit in the fuller_mask, then we may
8204 replace with (not Y). */
8205 if (CONST_INT_P (XEXP (x
, 0))
8206 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8208 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8209 XEXP (x
, 1), GET_MODE (x
));
8210 return force_to_mode (x
, mode
, mask
, next_select
);
8218 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8219 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8220 operation which may be a bitfield extraction. Ensure that the
8221 constant we form is not wider than the mode of X. */
8223 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8224 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8225 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8226 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8227 && CONST_INT_P (XEXP (x
, 1))
8228 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8229 + floor_log2 (INTVAL (XEXP (x
, 1))))
8230 < GET_MODE_PRECISION (GET_MODE (x
)))
8231 && (UINTVAL (XEXP (x
, 1))
8232 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8234 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8235 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8237 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8238 XEXP (XEXP (x
, 0), 0), temp
);
8239 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8240 XEXP (XEXP (x
, 0), 1));
8241 return force_to_mode (x
, mode
, mask
, next_select
);
8245 /* For most binary operations, just propagate into the operation and
8246 change the mode if we have an operation of that mode. */
8248 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8249 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8251 /* If we ended up truncating both operands, truncate the result of the
8252 operation instead. */
8253 if (GET_CODE (op0
) == TRUNCATE
8254 && GET_CODE (op1
) == TRUNCATE
)
8256 op0
= XEXP (op0
, 0);
8257 op1
= XEXP (op1
, 0);
8260 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8261 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8263 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8264 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8268 /* For left shifts, do the same, but just for the first operand.
8269 However, we cannot do anything with shifts where we cannot
8270 guarantee that the counts are smaller than the size of the mode
8271 because such a count will have a different meaning in a
8274 if (! (CONST_INT_P (XEXP (x
, 1))
8275 && INTVAL (XEXP (x
, 1)) >= 0
8276 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8277 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8278 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8279 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8282 /* If the shift count is a constant and we can do arithmetic in
8283 the mode of the shift, refine which bits we need. Otherwise, use the
8284 conservative form of the mask. */
8285 if (CONST_INT_P (XEXP (x
, 1))
8286 && INTVAL (XEXP (x
, 1)) >= 0
8287 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8288 && HWI_COMPUTABLE_MODE_P (op_mode
))
8289 mask
>>= INTVAL (XEXP (x
, 1));
8293 op0
= gen_lowpart_or_truncate (op_mode
,
8294 force_to_mode (XEXP (x
, 0), op_mode
,
8295 mask
, next_select
));
8297 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8298 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8302 /* Here we can only do something if the shift count is a constant,
8303 this shift constant is valid for the host, and we can do arithmetic
8306 if (CONST_INT_P (XEXP (x
, 1))
8307 && INTVAL (XEXP (x
, 1)) >= 0
8308 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8309 && HWI_COMPUTABLE_MODE_P (op_mode
))
8311 rtx inner
= XEXP (x
, 0);
8312 unsigned HOST_WIDE_INT inner_mask
;
8314 /* Select the mask of the bits we need for the shift operand. */
8315 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8317 /* We can only change the mode of the shift if we can do arithmetic
8318 in the mode of the shift and INNER_MASK is no wider than the
8319 width of X's mode. */
8320 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8321 op_mode
= GET_MODE (x
);
8323 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8325 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8326 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8329 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8330 shift and AND produces only copies of the sign bit (C2 is one less
8331 than a power of two), we can do this with just a shift. */
8333 if (GET_CODE (x
) == LSHIFTRT
8334 && CONST_INT_P (XEXP (x
, 1))
8335 /* The shift puts one of the sign bit copies in the least significant
8337 && ((INTVAL (XEXP (x
, 1))
8338 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8339 >= GET_MODE_PRECISION (GET_MODE (x
)))
8340 && exact_log2 (mask
+ 1) >= 0
8341 /* Number of bits left after the shift must be more than the mask
8343 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8344 <= GET_MODE_PRECISION (GET_MODE (x
)))
8345 /* Must be more sign bit copies than the mask needs. */
8346 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8347 >= exact_log2 (mask
+ 1)))
8348 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8349 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8350 - exact_log2 (mask
+ 1)));
8355 /* If we are just looking for the sign bit, we don't need this shift at
8356 all, even if it has a variable count. */
8357 if (val_signbit_p (GET_MODE (x
), mask
))
8358 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8360 /* If this is a shift by a constant, get a mask that contains those bits
8361 that are not copies of the sign bit. We then have two cases: If
8362 MASK only includes those bits, this can be a logical shift, which may
8363 allow simplifications. If MASK is a single-bit field not within
8364 those bits, we are requesting a copy of the sign bit and hence can
8365 shift the sign bit to the appropriate location. */
8367 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8368 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8372 /* If the considered data is wider than HOST_WIDE_INT, we can't
8373 represent a mask for all its bits in a single scalar.
8374 But we only care about the lower bits, so calculate these. */
8376 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8378 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8380 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8381 is the number of bits a full-width mask would have set.
8382 We need only shift if these are fewer than nonzero can
8383 hold. If not, we must keep all bits set in nonzero. */
8385 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8386 < HOST_BITS_PER_WIDE_INT
)
8387 nonzero
>>= INTVAL (XEXP (x
, 1))
8388 + HOST_BITS_PER_WIDE_INT
8389 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8393 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8394 nonzero
>>= INTVAL (XEXP (x
, 1));
8397 if ((mask
& ~nonzero
) == 0)
8399 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8400 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8401 if (GET_CODE (x
) != ASHIFTRT
)
8402 return force_to_mode (x
, mode
, mask
, next_select
);
8405 else if ((i
= exact_log2 (mask
)) >= 0)
8407 x
= simplify_shift_const
8408 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8409 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8411 if (GET_CODE (x
) != ASHIFTRT
)
8412 return force_to_mode (x
, mode
, mask
, next_select
);
8416 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8417 even if the shift count isn't a constant. */
8419 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8420 XEXP (x
, 0), XEXP (x
, 1));
8424 /* If this is a zero- or sign-extension operation that just affects bits
8425 we don't care about, remove it. Be sure the call above returned
8426 something that is still a shift. */
8428 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8429 && CONST_INT_P (XEXP (x
, 1))
8430 && INTVAL (XEXP (x
, 1)) >= 0
8431 && (INTVAL (XEXP (x
, 1))
8432 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8433 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8434 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8435 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8442 /* If the shift count is constant and we can do computations
8443 in the mode of X, compute where the bits we care about are.
8444 Otherwise, we can't do anything. Don't change the mode of
8445 the shift or propagate MODE into the shift, though. */
8446 if (CONST_INT_P (XEXP (x
, 1))
8447 && INTVAL (XEXP (x
, 1)) >= 0)
8449 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8451 gen_int_mode (mask
, GET_MODE (x
)),
8453 if (temp
&& CONST_INT_P (temp
))
8455 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8456 INTVAL (temp
), next_select
));
8461 /* If we just want the low-order bit, the NEG isn't needed since it
8462 won't change the low-order bit. */
8464 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8466 /* We need any bits less significant than the most significant bit in
8467 MASK since carries from those bits will affect the bits we are
8473 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8474 same as the XOR case above. Ensure that the constant we form is not
8475 wider than the mode of X. */
8477 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8478 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8479 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8480 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8481 < GET_MODE_PRECISION (GET_MODE (x
)))
8482 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8484 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8486 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8487 XEXP (XEXP (x
, 0), 0), temp
);
8488 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8489 temp
, XEXP (XEXP (x
, 0), 1));
8491 return force_to_mode (x
, mode
, mask
, next_select
);
8494 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8495 use the full mask inside the NOT. */
8499 op0
= gen_lowpart_or_truncate (op_mode
,
8500 force_to_mode (XEXP (x
, 0), mode
, mask
,
8502 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8503 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8507 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8508 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8509 which is equal to STORE_FLAG_VALUE. */
8510 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8511 && XEXP (x
, 1) == const0_rtx
8512 && GET_MODE (XEXP (x
, 0)) == mode
8513 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8514 && (nonzero_bits (XEXP (x
, 0), mode
)
8515 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8516 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8521 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8522 written in a narrower mode. We play it safe and do not do so. */
8525 gen_lowpart_or_truncate (GET_MODE (x
),
8526 force_to_mode (XEXP (x
, 1), mode
,
8527 mask
, next_select
)));
8529 gen_lowpart_or_truncate (GET_MODE (x
),
8530 force_to_mode (XEXP (x
, 2), mode
,
8531 mask
, next_select
)));
8538 /* Ensure we return a value of the proper mode. */
8539 return gen_lowpart_or_truncate (mode
, x
);
8542 /* Return nonzero if X is an expression that has one of two values depending on
8543 whether some other value is zero or nonzero. In that case, we return the
8544 value that is being tested, *PTRUE is set to the value if the rtx being
8545 returned has a nonzero value, and *PFALSE is set to the other alternative.
8547 If we return zero, we set *PTRUE and *PFALSE to X. */
8550 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8552 enum machine_mode mode
= GET_MODE (x
);
8553 enum rtx_code code
= GET_CODE (x
);
8554 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8555 unsigned HOST_WIDE_INT nz
;
8557 /* If we are comparing a value against zero, we are done. */
8558 if ((code
== NE
|| code
== EQ
)
8559 && XEXP (x
, 1) == const0_rtx
)
8561 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8562 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8566 /* If this is a unary operation whose operand has one of two values, apply
8567 our opcode to compute those values. */
8568 else if (UNARY_P (x
)
8569 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8571 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8572 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8573 GET_MODE (XEXP (x
, 0)));
8577 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8578 make can't possibly match and would suppress other optimizations. */
8579 else if (code
== COMPARE
)
8582 /* If this is a binary operation, see if either side has only one of two
8583 values. If either one does or if both do and they are conditional on
8584 the same value, compute the new true and false values. */
8585 else if (BINARY_P (x
))
8587 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8588 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8590 if ((cond0
!= 0 || cond1
!= 0)
8591 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8593 /* If if_then_else_cond returned zero, then true/false are the
8594 same rtl. We must copy one of them to prevent invalid rtl
8597 true0
= copy_rtx (true0
);
8598 else if (cond1
== 0)
8599 true1
= copy_rtx (true1
);
8601 if (COMPARISON_P (x
))
8603 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8605 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8610 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8611 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8614 return cond0
? cond0
: cond1
;
8617 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8618 operands is zero when the other is nonzero, and vice-versa,
8619 and STORE_FLAG_VALUE is 1 or -1. */
8621 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8622 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8624 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8626 rtx op0
= XEXP (XEXP (x
, 0), 1);
8627 rtx op1
= XEXP (XEXP (x
, 1), 1);
8629 cond0
= XEXP (XEXP (x
, 0), 0);
8630 cond1
= XEXP (XEXP (x
, 1), 0);
8632 if (COMPARISON_P (cond0
)
8633 && COMPARISON_P (cond1
)
8634 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8635 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8636 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8637 || ((swap_condition (GET_CODE (cond0
))
8638 == reversed_comparison_code (cond1
, NULL
))
8639 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8640 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8641 && ! side_effects_p (x
))
8643 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8644 *pfalse
= simplify_gen_binary (MULT
, mode
,
8646 ? simplify_gen_unary (NEG
, mode
,
8654 /* Similarly for MULT, AND and UMIN, except that for these the result
8656 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8657 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8658 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8660 cond0
= XEXP (XEXP (x
, 0), 0);
8661 cond1
= XEXP (XEXP (x
, 1), 0);
8663 if (COMPARISON_P (cond0
)
8664 && COMPARISON_P (cond1
)
8665 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8666 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8667 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8668 || ((swap_condition (GET_CODE (cond0
))
8669 == reversed_comparison_code (cond1
, NULL
))
8670 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8671 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8672 && ! side_effects_p (x
))
8674 *ptrue
= *pfalse
= const0_rtx
;
8680 else if (code
== IF_THEN_ELSE
)
8682 /* If we have IF_THEN_ELSE already, extract the condition and
8683 canonicalize it if it is NE or EQ. */
8684 cond0
= XEXP (x
, 0);
8685 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8686 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8687 return XEXP (cond0
, 0);
8688 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8690 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8691 return XEXP (cond0
, 0);
8697 /* If X is a SUBREG, we can narrow both the true and false values
8698 if the inner expression, if there is a condition. */
8699 else if (code
== SUBREG
8700 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8703 true0
= simplify_gen_subreg (mode
, true0
,
8704 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8705 false0
= simplify_gen_subreg (mode
, false0
,
8706 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8707 if (true0
&& false0
)
8715 /* If X is a constant, this isn't special and will cause confusions
8716 if we treat it as such. Likewise if it is equivalent to a constant. */
8717 else if (CONSTANT_P (x
)
8718 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8721 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8722 will be least confusing to the rest of the compiler. */
8723 else if (mode
== BImode
)
8725 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8729 /* If X is known to be either 0 or -1, those are the true and
8730 false values when testing X. */
8731 else if (x
== constm1_rtx
|| x
== const0_rtx
8732 || (mode
!= VOIDmode
8733 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8735 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8739 /* Likewise for 0 or a single bit. */
8740 else if (HWI_COMPUTABLE_MODE_P (mode
)
8741 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8743 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8747 /* Otherwise fail; show no condition with true and false values the same. */
8748 *ptrue
= *pfalse
= x
;
8752 /* Return the value of expression X given the fact that condition COND
8753 is known to be true when applied to REG as its first operand and VAL
8754 as its second. X is known to not be shared and so can be modified in
8757 We only handle the simplest cases, and specifically those cases that
8758 arise with IF_THEN_ELSE expressions. */
8761 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8763 enum rtx_code code
= GET_CODE (x
);
8768 if (side_effects_p (x
))
8771 /* If either operand of the condition is a floating point value,
8772 then we have to avoid collapsing an EQ comparison. */
8774 && rtx_equal_p (x
, reg
)
8775 && ! FLOAT_MODE_P (GET_MODE (x
))
8776 && ! FLOAT_MODE_P (GET_MODE (val
)))
8779 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8782 /* If X is (abs REG) and we know something about REG's relationship
8783 with zero, we may be able to simplify this. */
8785 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8788 case GE
: case GT
: case EQ
:
8791 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8793 GET_MODE (XEXP (x
, 0)));
8798 /* The only other cases we handle are MIN, MAX, and comparisons if the
8799 operands are the same as REG and VAL. */
8801 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8803 if (rtx_equal_p (XEXP (x
, 0), val
))
8804 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8806 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8808 if (COMPARISON_P (x
))
8810 if (comparison_dominates_p (cond
, code
))
8811 return const_true_rtx
;
8813 code
= reversed_comparison_code (x
, NULL
);
8815 && comparison_dominates_p (cond
, code
))
8820 else if (code
== SMAX
|| code
== SMIN
8821 || code
== UMIN
|| code
== UMAX
)
8823 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8825 /* Do not reverse the condition when it is NE or EQ.
8826 This is because we cannot conclude anything about
8827 the value of 'SMAX (x, y)' when x is not equal to y,
8828 but we can when x equals y. */
8829 if ((code
== SMAX
|| code
== UMAX
)
8830 && ! (cond
== EQ
|| cond
== NE
))
8831 cond
= reverse_condition (cond
);
8836 return unsignedp
? x
: XEXP (x
, 1);
8838 return unsignedp
? x
: XEXP (x
, 0);
8840 return unsignedp
? XEXP (x
, 1) : x
;
8842 return unsignedp
? XEXP (x
, 0) : x
;
8849 else if (code
== SUBREG
)
8851 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8852 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8854 if (SUBREG_REG (x
) != r
)
8856 /* We must simplify subreg here, before we lose track of the
8857 original inner_mode. */
8858 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8859 inner_mode
, SUBREG_BYTE (x
));
8863 SUBST (SUBREG_REG (x
), r
);
8868 /* We don't have to handle SIGN_EXTEND here, because even in the
8869 case of replacing something with a modeless CONST_INT, a
8870 CONST_INT is already (supposed to be) a valid sign extension for
8871 its narrower mode, which implies it's already properly
8872 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8873 story is different. */
8874 else if (code
== ZERO_EXTEND
)
8876 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8877 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8879 if (XEXP (x
, 0) != r
)
8881 /* We must simplify the zero_extend here, before we lose
8882 track of the original inner_mode. */
8883 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8888 SUBST (XEXP (x
, 0), r
);
8894 fmt
= GET_RTX_FORMAT (code
);
8895 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8898 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8899 else if (fmt
[i
] == 'E')
8900 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8901 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8908 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8909 assignment as a field assignment. */
8912 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8914 if (x
== y
|| rtx_equal_p (x
, y
))
8917 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8920 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8921 Note that all SUBREGs of MEM are paradoxical; otherwise they
8922 would have been rewritten. */
8923 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8924 && MEM_P (SUBREG_REG (y
))
8925 && rtx_equal_p (SUBREG_REG (y
),
8926 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8929 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8930 && MEM_P (SUBREG_REG (x
))
8931 && rtx_equal_p (SUBREG_REG (x
),
8932 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8935 /* We used to see if get_last_value of X and Y were the same but that's
8936 not correct. In one direction, we'll cause the assignment to have
8937 the wrong destination and in the case, we'll import a register into this
8938 insn that might have already have been dead. So fail if none of the
8939 above cases are true. */
8943 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8944 Return that assignment if so.
8946 We only handle the most common cases. */
8949 make_field_assignment (rtx x
)
8951 rtx dest
= SET_DEST (x
);
8952 rtx src
= SET_SRC (x
);
8957 unsigned HOST_WIDE_INT len
;
8959 enum machine_mode mode
;
8961 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8962 a clear of a one-bit field. We will have changed it to
8963 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8966 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8967 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8968 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8969 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8971 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8974 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8978 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8979 && subreg_lowpart_p (XEXP (src
, 0))
8980 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8981 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8982 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8983 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8984 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8985 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8987 assign
= make_extraction (VOIDmode
, dest
, 0,
8988 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8991 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8995 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8997 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8998 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8999 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9001 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9004 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9008 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9009 SRC is an AND with all bits of that field set, then we can discard
9011 if (GET_CODE (dest
) == ZERO_EXTRACT
9012 && CONST_INT_P (XEXP (dest
, 1))
9013 && GET_CODE (src
) == AND
9014 && CONST_INT_P (XEXP (src
, 1)))
9016 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9017 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9018 unsigned HOST_WIDE_INT ze_mask
;
9020 if (width
>= HOST_BITS_PER_WIDE_INT
)
9023 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9025 /* Complete overlap. We can remove the source AND. */
9026 if ((and_mask
& ze_mask
) == ze_mask
)
9027 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9029 /* Partial overlap. We can reduce the source AND. */
9030 if ((and_mask
& ze_mask
) != and_mask
)
9032 mode
= GET_MODE (src
);
9033 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9034 gen_int_mode (and_mask
& ze_mask
, mode
));
9035 return gen_rtx_SET (VOIDmode
, dest
, src
);
9039 /* The other case we handle is assignments into a constant-position
9040 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9041 a mask that has all one bits except for a group of zero bits and
9042 OTHER is known to have zeros where C1 has ones, this is such an
9043 assignment. Compute the position and length from C1. Shift OTHER
9044 to the appropriate position, force it to the required mode, and
9045 make the extraction. Check for the AND in both operands. */
9047 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9050 rhs
= expand_compound_operation (XEXP (src
, 0));
9051 lhs
= expand_compound_operation (XEXP (src
, 1));
9053 if (GET_CODE (rhs
) == AND
9054 && CONST_INT_P (XEXP (rhs
, 1))
9055 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9056 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9057 else if (GET_CODE (lhs
) == AND
9058 && CONST_INT_P (XEXP (lhs
, 1))
9059 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9060 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9064 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9065 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9066 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9067 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9070 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9074 /* The mode to use for the source is the mode of the assignment, or of
9075 what is inside a possible STRICT_LOW_PART. */
9076 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9077 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9079 /* Shift OTHER right POS places and make it the source, restricting it
9080 to the proper length and mode. */
9082 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9086 src
= force_to_mode (src
, mode
,
9087 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9088 ? ~(unsigned HOST_WIDE_INT
) 0
9089 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9092 /* If SRC is masked by an AND that does not make a difference in
9093 the value being stored, strip it. */
9094 if (GET_CODE (assign
) == ZERO_EXTRACT
9095 && CONST_INT_P (XEXP (assign
, 1))
9096 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9097 && GET_CODE (src
) == AND
9098 && CONST_INT_P (XEXP (src
, 1))
9099 && UINTVAL (XEXP (src
, 1))
9100 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9101 src
= XEXP (src
, 0);
9103 return gen_rtx_SET (VOIDmode
, assign
, src
);
9106 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9110 apply_distributive_law (rtx x
)
9112 enum rtx_code code
= GET_CODE (x
);
9113 enum rtx_code inner_code
;
9114 rtx lhs
, rhs
, other
;
9117 /* Distributivity is not true for floating point as it can change the
9118 value. So we don't do it unless -funsafe-math-optimizations. */
9119 if (FLOAT_MODE_P (GET_MODE (x
))
9120 && ! flag_unsafe_math_optimizations
)
9123 /* The outer operation can only be one of the following: */
9124 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9125 && code
!= PLUS
&& code
!= MINUS
)
9131 /* If either operand is a primitive we can't do anything, so get out
9133 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9136 lhs
= expand_compound_operation (lhs
);
9137 rhs
= expand_compound_operation (rhs
);
9138 inner_code
= GET_CODE (lhs
);
9139 if (inner_code
!= GET_CODE (rhs
))
9142 /* See if the inner and outer operations distribute. */
9149 /* These all distribute except over PLUS. */
9150 if (code
== PLUS
|| code
== MINUS
)
9155 if (code
!= PLUS
&& code
!= MINUS
)
9160 /* This is also a multiply, so it distributes over everything. */
9163 /* This used to handle SUBREG, but this turned out to be counter-
9164 productive, since (subreg (op ...)) usually is not handled by
9165 insn patterns, and this "optimization" therefore transformed
9166 recognizable patterns into unrecognizable ones. Therefore the
9167 SUBREG case was removed from here.
9169 It is possible that distributing SUBREG over arithmetic operations
9170 leads to an intermediate result than can then be optimized further,
9171 e.g. by moving the outer SUBREG to the other side of a SET as done
9172 in simplify_set. This seems to have been the original intent of
9173 handling SUBREGs here.
9175 However, with current GCC this does not appear to actually happen,
9176 at least on major platforms. If some case is found where removing
9177 the SUBREG case here prevents follow-on optimizations, distributing
9178 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9184 /* Set LHS and RHS to the inner operands (A and B in the example
9185 above) and set OTHER to the common operand (C in the example).
9186 There is only one way to do this unless the inner operation is
9188 if (COMMUTATIVE_ARITH_P (lhs
)
9189 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9190 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9191 else if (COMMUTATIVE_ARITH_P (lhs
)
9192 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9193 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9194 else if (COMMUTATIVE_ARITH_P (lhs
)
9195 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9196 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9197 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9198 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9202 /* Form the new inner operation, seeing if it simplifies first. */
9203 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9205 /* There is one exception to the general way of distributing:
9206 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9207 if (code
== XOR
&& inner_code
== IOR
)
9210 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9213 /* We may be able to continuing distributing the result, so call
9214 ourselves recursively on the inner operation before forming the
9215 outer operation, which we return. */
9216 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9217 apply_distributive_law (tem
), other
);
9220 /* See if X is of the form (* (+ A B) C), and if so convert to
9221 (+ (* A C) (* B C)) and try to simplify.
9223 Most of the time, this results in no change. However, if some of
9224 the operands are the same or inverses of each other, simplifications
9227 For example, (and (ior A B) (not B)) can occur as the result of
9228 expanding a bit field assignment. When we apply the distributive
9229 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9230 which then simplifies to (and (A (not B))).
9232 Note that no checks happen on the validity of applying the inverse
9233 distributive law. This is pointless since we can do it in the
9234 few places where this routine is called.
9236 N is the index of the term that is decomposed (the arithmetic operation,
9237 i.e. (+ A B) in the first example above). !N is the index of the term that
9238 is distributed, i.e. of C in the first example above. */
9240 distribute_and_simplify_rtx (rtx x
, int n
)
9242 enum machine_mode mode
;
9243 enum rtx_code outer_code
, inner_code
;
9244 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9246 /* Distributivity is not true for floating point as it can change the
9247 value. So we don't do it unless -funsafe-math-optimizations. */
9248 if (FLOAT_MODE_P (GET_MODE (x
))
9249 && ! flag_unsafe_math_optimizations
)
9252 decomposed
= XEXP (x
, n
);
9253 if (!ARITHMETIC_P (decomposed
))
9256 mode
= GET_MODE (x
);
9257 outer_code
= GET_CODE (x
);
9258 distributed
= XEXP (x
, !n
);
9260 inner_code
= GET_CODE (decomposed
);
9261 inner_op0
= XEXP (decomposed
, 0);
9262 inner_op1
= XEXP (decomposed
, 1);
9264 /* Special case (and (xor B C) (not A)), which is equivalent to
9265 (xor (ior A B) (ior A C)) */
9266 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9268 distributed
= XEXP (distributed
, 0);
9274 /* Distribute the second term. */
9275 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9276 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9280 /* Distribute the first term. */
9281 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9282 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9285 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9287 if (GET_CODE (tmp
) != outer_code
9288 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9289 < set_src_cost (x
, optimize_this_for_speed_p
)))
9295 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9296 in MODE. Return an equivalent form, if different from (and VAROP
9297 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9300 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9301 unsigned HOST_WIDE_INT constop
)
9303 unsigned HOST_WIDE_INT nonzero
;
9304 unsigned HOST_WIDE_INT orig_constop
;
9309 orig_constop
= constop
;
9310 if (GET_CODE (varop
) == CLOBBER
)
9313 /* Simplify VAROP knowing that we will be only looking at some of the
9316 Note by passing in CONSTOP, we guarantee that the bits not set in
9317 CONSTOP are not significant and will never be examined. We must
9318 ensure that is the case by explicitly masking out those bits
9319 before returning. */
9320 varop
= force_to_mode (varop
, mode
, constop
, 0);
9322 /* If VAROP is a CLOBBER, we will fail so return it. */
9323 if (GET_CODE (varop
) == CLOBBER
)
9326 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9327 to VAROP and return the new constant. */
9328 if (CONST_INT_P (varop
))
9329 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9331 /* See what bits may be nonzero in VAROP. Unlike the general case of
9332 a call to nonzero_bits, here we don't care about bits outside
9335 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9337 /* Turn off all bits in the constant that are known to already be zero.
9338 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9339 which is tested below. */
9343 /* If we don't have any bits left, return zero. */
9347 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9348 a power of two, we can replace this with an ASHIFT. */
9349 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9350 && (i
= exact_log2 (constop
)) >= 0)
9351 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9353 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9354 or XOR, then try to apply the distributive law. This may eliminate
9355 operations if either branch can be simplified because of the AND.
9356 It may also make some cases more complex, but those cases probably
9357 won't match a pattern either with or without this. */
9359 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9363 apply_distributive_law
9364 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9365 simplify_and_const_int (NULL_RTX
,
9369 simplify_and_const_int (NULL_RTX
,
9374 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9375 the AND and see if one of the operands simplifies to zero. If so, we
9376 may eliminate it. */
9378 if (GET_CODE (varop
) == PLUS
9379 && exact_log2 (constop
+ 1) >= 0)
9383 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9384 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9385 if (o0
== const0_rtx
)
9387 if (o1
== const0_rtx
)
9391 /* Make a SUBREG if necessary. If we can't make it, fail. */
9392 varop
= gen_lowpart (mode
, varop
);
9393 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9396 /* If we are only masking insignificant bits, return VAROP. */
9397 if (constop
== nonzero
)
9400 if (varop
== orig_varop
&& constop
== orig_constop
)
9403 /* Otherwise, return an AND. */
9404 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9408 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9411 Return an equivalent form, if different from X. Otherwise, return X. If
9412 X is zero, we are to always construct the equivalent form. */
9415 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9416 unsigned HOST_WIDE_INT constop
)
9418 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9423 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9424 gen_int_mode (constop
, mode
));
9425 if (GET_MODE (x
) != mode
)
9426 x
= gen_lowpart (mode
, x
);
9430 /* Given a REG, X, compute which bits in X can be nonzero.
9431 We don't care about bits outside of those defined in MODE.
9433 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9434 a shift, AND, or zero_extract, we can do better. */
9437 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9438 const_rtx known_x ATTRIBUTE_UNUSED
,
9439 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9440 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9441 unsigned HOST_WIDE_INT
*nonzero
)
9446 /* If X is a register whose nonzero bits value is current, use it.
9447 Otherwise, if X is a register whose value we can find, use that
9448 value. Otherwise, use the previously-computed global nonzero bits
9449 for this register. */
9451 rsp
= ®_stat
[REGNO (x
)];
9452 if (rsp
->last_set_value
!= 0
9453 && (rsp
->last_set_mode
== mode
9454 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9455 && GET_MODE_CLASS (mode
) == MODE_INT
))
9456 && ((rsp
->last_set_label
>= label_tick_ebb_start
9457 && rsp
->last_set_label
< label_tick
)
9458 || (rsp
->last_set_label
== label_tick
9459 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9460 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9461 && REG_N_SETS (REGNO (x
)) == 1
9463 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9465 *nonzero
&= rsp
->last_set_nonzero_bits
;
9469 tem
= get_last_value (x
);
9473 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9474 /* If X is narrower than MODE and TEM is a non-negative
9475 constant that would appear negative in the mode of X,
9476 sign-extend it for use in reg_nonzero_bits because some
9477 machines (maybe most) will actually do the sign-extension
9478 and this is the conservative approach.
9480 ??? For 2.5, try to tighten up the MD files in this regard
9481 instead of this kludge. */
9483 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9484 && CONST_INT_P (tem
)
9486 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9487 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9491 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9493 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9495 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9496 /* We don't know anything about the upper bits. */
9497 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9504 /* Return the number of bits at the high-order end of X that are known to
9505 be equal to the sign bit. X will be used in mode MODE; if MODE is
9506 VOIDmode, X will be used in its own mode. The returned value will always
9507 be between 1 and the number of bits in MODE. */
9510 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9511 const_rtx known_x ATTRIBUTE_UNUSED
,
9512 enum machine_mode known_mode
9514 unsigned int known_ret ATTRIBUTE_UNUSED
,
9515 unsigned int *result
)
9520 rsp
= ®_stat
[REGNO (x
)];
9521 if (rsp
->last_set_value
!= 0
9522 && rsp
->last_set_mode
== mode
9523 && ((rsp
->last_set_label
>= label_tick_ebb_start
9524 && rsp
->last_set_label
< label_tick
)
9525 || (rsp
->last_set_label
== label_tick
9526 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9527 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9528 && REG_N_SETS (REGNO (x
)) == 1
9530 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9532 *result
= rsp
->last_set_sign_bit_copies
;
9536 tem
= get_last_value (x
);
9540 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9541 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9542 *result
= rsp
->sign_bit_copies
;
9547 /* Return the number of "extended" bits there are in X, when interpreted
9548 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9549 unsigned quantities, this is the number of high-order zero bits.
9550 For signed quantities, this is the number of copies of the sign bit
9551 minus 1. In both case, this function returns the number of "spare"
9552 bits. For example, if two quantities for which this function returns
9553 at least 1 are added, the addition is known not to overflow.
9555 This function will always return 0 unless called during combine, which
9556 implies that it must be called from a define_split. */
9559 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9561 if (nonzero_sign_valid
== 0)
9565 ? (HWI_COMPUTABLE_MODE_P (mode
)
9566 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9567 - floor_log2 (nonzero_bits (x
, mode
)))
9569 : num_sign_bit_copies (x
, mode
) - 1);
9572 /* This function is called from `simplify_shift_const' to merge two
9573 outer operations. Specifically, we have already found that we need
9574 to perform operation *POP0 with constant *PCONST0 at the outermost
9575 position. We would now like to also perform OP1 with constant CONST1
9576 (with *POP0 being done last).
9578 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9579 the resulting operation. *PCOMP_P is set to 1 if we would need to
9580 complement the innermost operand, otherwise it is unchanged.
9582 MODE is the mode in which the operation will be done. No bits outside
9583 the width of this mode matter. It is assumed that the width of this mode
9584 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9586 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9587 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9588 result is simply *PCONST0.
9590 If the resulting operation cannot be expressed as one operation, we
9591 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9594 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9596 enum rtx_code op0
= *pop0
;
9597 HOST_WIDE_INT const0
= *pconst0
;
9599 const0
&= GET_MODE_MASK (mode
);
9600 const1
&= GET_MODE_MASK (mode
);
9602 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9606 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9609 if (op1
== UNKNOWN
|| op0
== SET
)
9612 else if (op0
== UNKNOWN
)
9613 op0
= op1
, const0
= const1
;
9615 else if (op0
== op1
)
9639 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9640 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9643 /* If the two constants aren't the same, we can't do anything. The
9644 remaining six cases can all be done. */
9645 else if (const0
!= const1
)
9653 /* (a & b) | b == b */
9655 else /* op1 == XOR */
9656 /* (a ^ b) | b == a | b */
9662 /* (a & b) ^ b == (~a) & b */
9663 op0
= AND
, *pcomp_p
= 1;
9664 else /* op1 == IOR */
9665 /* (a | b) ^ b == a & ~b */
9666 op0
= AND
, const0
= ~const0
;
9671 /* (a | b) & b == b */
9673 else /* op1 == XOR */
9674 /* (a ^ b) & b) == (~a) & b */
9681 /* Check for NO-OP cases. */
9682 const0
&= GET_MODE_MASK (mode
);
9684 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9686 else if (const0
== 0 && op0
== AND
)
9688 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9694 /* ??? Slightly redundant with the above mask, but not entirely.
9695 Moving this above means we'd have to sign-extend the mode mask
9696 for the final test. */
9697 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9698 *pconst0
= trunc_int_for_mode (const0
, mode
);
9703 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9704 the shift in. The original shift operation CODE is performed on OP in
9705 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9706 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9707 result of the shift is subject to operation OUTER_CODE with operand
9710 static enum machine_mode
9711 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9712 enum machine_mode orig_mode
, enum machine_mode mode
,
9713 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9715 if (orig_mode
== mode
)
9717 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9719 /* In general we can't perform in wider mode for right shift and rotate. */
9723 /* We can still widen if the bits brought in from the left are identical
9724 to the sign bit of ORIG_MODE. */
9725 if (num_sign_bit_copies (op
, mode
)
9726 > (unsigned) (GET_MODE_PRECISION (mode
)
9727 - GET_MODE_PRECISION (orig_mode
)))
9732 /* Similarly here but with zero bits. */
9733 if (HWI_COMPUTABLE_MODE_P (mode
)
9734 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9737 /* We can also widen if the bits brought in will be masked off. This
9738 operation is performed in ORIG_MODE. */
9739 if (outer_code
== AND
)
9741 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9744 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9760 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9761 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9762 if we cannot simplify it. Otherwise, return a simplified value.
9764 The shift is normally computed in the widest mode we find in VAROP, as
9765 long as it isn't a different number of words than RESULT_MODE. Exceptions
9766 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9769 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9770 rtx varop
, int orig_count
)
9772 enum rtx_code orig_code
= code
;
9773 rtx orig_varop
= varop
;
9775 enum machine_mode mode
= result_mode
;
9776 enum machine_mode shift_mode
, tmode
;
9777 unsigned int mode_words
9778 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9779 /* We form (outer_op (code varop count) (outer_const)). */
9780 enum rtx_code outer_op
= UNKNOWN
;
9781 HOST_WIDE_INT outer_const
= 0;
9782 int complement_p
= 0;
9785 /* Make sure and truncate the "natural" shift on the way in. We don't
9786 want to do this inside the loop as it makes it more difficult to
9788 if (SHIFT_COUNT_TRUNCATED
)
9789 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9791 /* If we were given an invalid count, don't do anything except exactly
9792 what was requested. */
9794 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9799 /* Unless one of the branches of the `if' in this loop does a `continue',
9800 we will `break' the loop after the `if'. */
9804 /* If we have an operand of (clobber (const_int 0)), fail. */
9805 if (GET_CODE (varop
) == CLOBBER
)
9808 /* Convert ROTATERT to ROTATE. */
9809 if (code
== ROTATERT
)
9811 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9813 if (VECTOR_MODE_P (result_mode
))
9814 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9816 count
= bitsize
- count
;
9819 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9820 mode
, outer_op
, outer_const
);
9822 /* Handle cases where the count is greater than the size of the mode
9823 minus 1. For ASHIFT, use the size minus one as the count (this can
9824 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9825 take the count modulo the size. For other shifts, the result is
9828 Since these shifts are being produced by the compiler by combining
9829 multiple operations, each of which are defined, we know what the
9830 result is supposed to be. */
9832 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9834 if (code
== ASHIFTRT
)
9835 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9836 else if (code
== ROTATE
|| code
== ROTATERT
)
9837 count
%= GET_MODE_PRECISION (shift_mode
);
9840 /* We can't simply return zero because there may be an
9848 /* If we discovered we had to complement VAROP, leave. Making a NOT
9849 here would cause an infinite loop. */
9853 /* An arithmetic right shift of a quantity known to be -1 or 0
9855 if (code
== ASHIFTRT
9856 && (num_sign_bit_copies (varop
, shift_mode
)
9857 == GET_MODE_PRECISION (shift_mode
)))
9863 /* If we are doing an arithmetic right shift and discarding all but
9864 the sign bit copies, this is equivalent to doing a shift by the
9865 bitsize minus one. Convert it into that shift because it will often
9866 allow other simplifications. */
9868 if (code
== ASHIFTRT
9869 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9870 >= GET_MODE_PRECISION (shift_mode
)))
9871 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9873 /* We simplify the tests below and elsewhere by converting
9874 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9875 `make_compound_operation' will convert it to an ASHIFTRT for
9876 those machines (such as VAX) that don't have an LSHIFTRT. */
9877 if (code
== ASHIFTRT
9878 && val_signbit_known_clear_p (shift_mode
,
9879 nonzero_bits (varop
, shift_mode
)))
9882 if (((code
== LSHIFTRT
9883 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9884 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9886 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9887 && !((nonzero_bits (varop
, shift_mode
) << count
)
9888 & GET_MODE_MASK (shift_mode
))))
9889 && !side_effects_p (varop
))
9892 switch (GET_CODE (varop
))
9898 new_rtx
= expand_compound_operation (varop
);
9899 if (new_rtx
!= varop
)
9907 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9908 minus the width of a smaller mode, we can do this with a
9909 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9910 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9911 && ! mode_dependent_address_p (XEXP (varop
, 0),
9912 MEM_ADDR_SPACE (varop
))
9913 && ! MEM_VOLATILE_P (varop
)
9914 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9915 MODE_INT
, 1)) != BLKmode
)
9917 new_rtx
= adjust_address_nv (varop
, tmode
,
9918 BYTES_BIG_ENDIAN
? 0
9919 : count
/ BITS_PER_UNIT
);
9921 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9922 : ZERO_EXTEND
, mode
, new_rtx
);
9929 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9930 the same number of words as what we've seen so far. Then store
9931 the widest mode in MODE. */
9932 if (subreg_lowpart_p (varop
)
9933 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9934 > GET_MODE_SIZE (GET_MODE (varop
)))
9935 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9936 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9938 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9939 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9941 varop
= SUBREG_REG (varop
);
9942 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9943 mode
= GET_MODE (varop
);
9949 /* Some machines use MULT instead of ASHIFT because MULT
9950 is cheaper. But it is still better on those machines to
9951 merge two shifts into one. */
9952 if (CONST_INT_P (XEXP (varop
, 1))
9953 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9956 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9958 GEN_INT (exact_log2 (
9959 UINTVAL (XEXP (varop
, 1)))));
9965 /* Similar, for when divides are cheaper. */
9966 if (CONST_INT_P (XEXP (varop
, 1))
9967 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9970 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9972 GEN_INT (exact_log2 (
9973 UINTVAL (XEXP (varop
, 1)))));
9979 /* If we are extracting just the sign bit of an arithmetic
9980 right shift, that shift is not needed. However, the sign
9981 bit of a wider mode may be different from what would be
9982 interpreted as the sign bit in a narrower mode, so, if
9983 the result is narrower, don't discard the shift. */
9984 if (code
== LSHIFTRT
9985 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9986 && (GET_MODE_BITSIZE (result_mode
)
9987 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9989 varop
= XEXP (varop
, 0);
9993 /* ... fall through ... */
9998 /* Here we have two nested shifts. The result is usually the
9999 AND of a new shift with a mask. We compute the result below. */
10000 if (CONST_INT_P (XEXP (varop
, 1))
10001 && INTVAL (XEXP (varop
, 1)) >= 0
10002 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10003 && HWI_COMPUTABLE_MODE_P (result_mode
)
10004 && HWI_COMPUTABLE_MODE_P (mode
)
10005 && !VECTOR_MODE_P (result_mode
))
10007 enum rtx_code first_code
= GET_CODE (varop
);
10008 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10009 unsigned HOST_WIDE_INT mask
;
10012 /* We have one common special case. We can't do any merging if
10013 the inner code is an ASHIFTRT of a smaller mode. However, if
10014 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10015 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10016 we can convert it to
10017 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10018 This simplifies certain SIGN_EXTEND operations. */
10019 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10020 && count
== (GET_MODE_PRECISION (result_mode
)
10021 - GET_MODE_PRECISION (GET_MODE (varop
))))
10023 /* C3 has the low-order C1 bits zero. */
10025 mask
= GET_MODE_MASK (mode
)
10026 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10028 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10029 XEXP (varop
, 0), mask
);
10030 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10032 count
= first_count
;
10037 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10038 than C1 high-order bits equal to the sign bit, we can convert
10039 this to either an ASHIFT or an ASHIFTRT depending on the
10042 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10044 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10045 && GET_MODE (varop
) == shift_mode
10046 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10049 varop
= XEXP (varop
, 0);
10050 count
-= first_count
;
10060 /* There are some cases we can't do. If CODE is ASHIFTRT,
10061 we can only do this if FIRST_CODE is also ASHIFTRT.
10063 We can't do the case when CODE is ROTATE and FIRST_CODE is
10066 If the mode of this shift is not the mode of the outer shift,
10067 we can't do this if either shift is a right shift or ROTATE.
10069 Finally, we can't do any of these if the mode is too wide
10070 unless the codes are the same.
10072 Handle the case where the shift codes are the same
10075 if (code
== first_code
)
10077 if (GET_MODE (varop
) != result_mode
10078 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10079 || code
== ROTATE
))
10082 count
+= first_count
;
10083 varop
= XEXP (varop
, 0);
10087 if (code
== ASHIFTRT
10088 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10089 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10090 || (GET_MODE (varop
) != result_mode
10091 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10092 || first_code
== ROTATE
10093 || code
== ROTATE
)))
10096 /* To compute the mask to apply after the shift, shift the
10097 nonzero bits of the inner shift the same way the
10098 outer shift will. */
10100 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10104 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10107 /* Give up if we can't compute an outer operation to use. */
10109 || !CONST_INT_P (mask_rtx
)
10110 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10112 result_mode
, &complement_p
))
10115 /* If the shifts are in the same direction, we add the
10116 counts. Otherwise, we subtract them. */
10117 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10118 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10119 count
+= first_count
;
10121 count
-= first_count
;
10123 /* If COUNT is positive, the new shift is usually CODE,
10124 except for the two exceptions below, in which case it is
10125 FIRST_CODE. If the count is negative, FIRST_CODE should
10128 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10129 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10131 else if (count
< 0)
10132 code
= first_code
, count
= -count
;
10134 varop
= XEXP (varop
, 0);
10138 /* If we have (A << B << C) for any shift, we can convert this to
10139 (A << C << B). This wins if A is a constant. Only try this if
10140 B is not a constant. */
10142 else if (GET_CODE (varop
) == code
10143 && CONST_INT_P (XEXP (varop
, 0))
10144 && !CONST_INT_P (XEXP (varop
, 1)))
10146 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10149 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10156 if (VECTOR_MODE_P (mode
))
10159 /* Make this fit the case below. */
10160 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10166 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10167 with C the size of VAROP - 1 and the shift is logical if
10168 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10169 we have an (le X 0) operation. If we have an arithmetic shift
10170 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10171 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10173 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10174 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10175 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10176 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10177 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10178 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10181 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10184 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10185 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10190 /* If we have (shift (logical)), move the logical to the outside
10191 to allow it to possibly combine with another logical and the
10192 shift to combine with another shift. This also canonicalizes to
10193 what a ZERO_EXTRACT looks like. Also, some machines have
10194 (and (shift)) insns. */
10196 if (CONST_INT_P (XEXP (varop
, 1))
10197 /* We can't do this if we have (ashiftrt (xor)) and the
10198 constant has its sign bit set in shift_mode. */
10199 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10200 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10202 && (new_rtx
= simplify_const_binary_operation
10203 (code
, result_mode
,
10204 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10205 GEN_INT (count
))) != 0
10206 && CONST_INT_P (new_rtx
)
10207 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10208 INTVAL (new_rtx
), result_mode
, &complement_p
))
10210 varop
= XEXP (varop
, 0);
10214 /* If we can't do that, try to simplify the shift in each arm of the
10215 logical expression, make a new logical expression, and apply
10216 the inverse distributive law. This also can't be done
10217 for some (ashiftrt (xor)). */
10218 if (CONST_INT_P (XEXP (varop
, 1))
10219 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10220 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10223 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10224 XEXP (varop
, 0), count
);
10225 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10226 XEXP (varop
, 1), count
);
10228 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10230 varop
= apply_distributive_law (varop
);
10238 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10239 says that the sign bit can be tested, FOO has mode MODE, C is
10240 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10241 that may be nonzero. */
10242 if (code
== LSHIFTRT
10243 && XEXP (varop
, 1) == const0_rtx
10244 && GET_MODE (XEXP (varop
, 0)) == result_mode
10245 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10246 && HWI_COMPUTABLE_MODE_P (result_mode
)
10247 && STORE_FLAG_VALUE
== -1
10248 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10249 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10252 varop
= XEXP (varop
, 0);
10259 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10260 than the number of bits in the mode is equivalent to A. */
10261 if (code
== LSHIFTRT
10262 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10263 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10265 varop
= XEXP (varop
, 0);
10270 /* NEG commutes with ASHIFT since it is multiplication. Move the
10271 NEG outside to allow shifts to combine. */
10273 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10276 varop
= XEXP (varop
, 0);
10282 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10283 is one less than the number of bits in the mode is
10284 equivalent to (xor A 1). */
10285 if (code
== LSHIFTRT
10286 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10287 && XEXP (varop
, 1) == constm1_rtx
10288 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10289 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10293 varop
= XEXP (varop
, 0);
10297 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10298 that might be nonzero in BAR are those being shifted out and those
10299 bits are known zero in FOO, we can replace the PLUS with FOO.
10300 Similarly in the other operand order. This code occurs when
10301 we are computing the size of a variable-size array. */
10303 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10304 && count
< HOST_BITS_PER_WIDE_INT
10305 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10306 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10307 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10309 varop
= XEXP (varop
, 0);
10312 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10313 && count
< HOST_BITS_PER_WIDE_INT
10314 && HWI_COMPUTABLE_MODE_P (result_mode
)
10315 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10317 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10318 & nonzero_bits (XEXP (varop
, 1),
10321 varop
= XEXP (varop
, 1);
10325 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10327 && CONST_INT_P (XEXP (varop
, 1))
10328 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10330 GEN_INT (count
))) != 0
10331 && CONST_INT_P (new_rtx
)
10332 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10333 INTVAL (new_rtx
), result_mode
, &complement_p
))
10335 varop
= XEXP (varop
, 0);
10339 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10340 signbit', and attempt to change the PLUS to an XOR and move it to
10341 the outer operation as is done above in the AND/IOR/XOR case
10342 leg for shift(logical). See details in logical handling above
10343 for reasoning in doing so. */
10344 if (code
== LSHIFTRT
10345 && CONST_INT_P (XEXP (varop
, 1))
10346 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10347 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10349 GEN_INT (count
))) != 0
10350 && CONST_INT_P (new_rtx
)
10351 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10352 INTVAL (new_rtx
), result_mode
, &complement_p
))
10354 varop
= XEXP (varop
, 0);
10361 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10362 with C the size of VAROP - 1 and the shift is logical if
10363 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10364 we have a (gt X 0) operation. If the shift is arithmetic with
10365 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10366 we have a (neg (gt X 0)) operation. */
10368 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10369 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10370 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10371 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10372 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10373 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10374 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10377 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10380 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10381 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10388 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10389 if the truncate does not affect the value. */
10390 if (code
== LSHIFTRT
10391 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10392 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10393 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10394 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10395 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10397 rtx varop_inner
= XEXP (varop
, 0);
10400 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10401 XEXP (varop_inner
, 0),
10403 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10404 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10417 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10418 outer_op
, outer_const
);
10420 /* We have now finished analyzing the shift. The result should be
10421 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10422 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10423 to the result of the shift. OUTER_CONST is the relevant constant,
10424 but we must turn off all bits turned off in the shift. */
10426 if (outer_op
== UNKNOWN
10427 && orig_code
== code
&& orig_count
== count
10428 && varop
== orig_varop
10429 && shift_mode
== GET_MODE (varop
))
10432 /* Make a SUBREG if necessary. If we can't make it, fail. */
10433 varop
= gen_lowpart (shift_mode
, varop
);
10434 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10437 /* If we have an outer operation and we just made a shift, it is
10438 possible that we could have simplified the shift were it not
10439 for the outer operation. So try to do the simplification
10442 if (outer_op
!= UNKNOWN
)
10443 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10448 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10450 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10451 turn off all the bits that the shift would have turned off. */
10452 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10453 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10454 GET_MODE_MASK (result_mode
) >> orig_count
);
10456 /* Do the remainder of the processing in RESULT_MODE. */
10457 x
= gen_lowpart_or_truncate (result_mode
, x
);
10459 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10462 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10464 if (outer_op
!= UNKNOWN
)
10466 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10467 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10468 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10470 if (outer_op
== AND
)
10471 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10472 else if (outer_op
== SET
)
10474 /* This means that we have determined that the result is
10475 equivalent to a constant. This should be rare. */
10476 if (!side_effects_p (x
))
10477 x
= GEN_INT (outer_const
);
10479 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10480 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10482 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10483 GEN_INT (outer_const
));
10489 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10490 The result of the shift is RESULT_MODE. If we cannot simplify it,
10491 return X or, if it is NULL, synthesize the expression with
10492 simplify_gen_binary. Otherwise, return a simplified value.
10494 The shift is normally computed in the widest mode we find in VAROP, as
10495 long as it isn't a different number of words than RESULT_MODE. Exceptions
10496 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10499 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10500 rtx varop
, int count
)
10502 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10507 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10508 if (GET_MODE (x
) != result_mode
)
10509 x
= gen_lowpart (result_mode
, x
);
10514 /* Like recog, but we receive the address of a pointer to a new pattern.
10515 We try to match the rtx that the pointer points to.
10516 If that fails, we may try to modify or replace the pattern,
10517 storing the replacement into the same pointer object.
10519 Modifications include deletion or addition of CLOBBERs.
10521 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10522 the CLOBBERs are placed.
10524 The value is the final insn code from the pattern ultimately matched,
10528 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10530 rtx pat
= *pnewpat
;
10531 rtx pat_without_clobbers
;
10532 int insn_code_number
;
10533 int num_clobbers_to_add
= 0;
10535 rtx notes
= NULL_RTX
;
10536 rtx old_notes
, old_pat
;
10539 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10540 we use to indicate that something didn't match. If we find such a
10541 thing, force rejection. */
10542 if (GET_CODE (pat
) == PARALLEL
)
10543 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10544 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10545 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10548 old_pat
= PATTERN (insn
);
10549 old_notes
= REG_NOTES (insn
);
10550 PATTERN (insn
) = pat
;
10551 REG_NOTES (insn
) = NULL_RTX
;
10553 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10554 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10556 if (insn_code_number
< 0)
10557 fputs ("Failed to match this instruction:\n", dump_file
);
10559 fputs ("Successfully matched this instruction:\n", dump_file
);
10560 print_rtl_single (dump_file
, pat
);
10563 /* If it isn't, there is the possibility that we previously had an insn
10564 that clobbered some register as a side effect, but the combined
10565 insn doesn't need to do that. So try once more without the clobbers
10566 unless this represents an ASM insn. */
10568 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10569 && GET_CODE (pat
) == PARALLEL
)
10573 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10574 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10577 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10581 SUBST_INT (XVECLEN (pat
, 0), pos
);
10584 pat
= XVECEXP (pat
, 0, 0);
10586 PATTERN (insn
) = pat
;
10587 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10588 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10590 if (insn_code_number
< 0)
10591 fputs ("Failed to match this instruction:\n", dump_file
);
10593 fputs ("Successfully matched this instruction:\n", dump_file
);
10594 print_rtl_single (dump_file
, pat
);
10598 pat_without_clobbers
= pat
;
10600 PATTERN (insn
) = old_pat
;
10601 REG_NOTES (insn
) = old_notes
;
10603 /* Recognize all noop sets, these will be killed by followup pass. */
10604 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10605 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10607 /* If we had any clobbers to add, make a new pattern than contains
10608 them. Then check to make sure that all of them are dead. */
10609 if (num_clobbers_to_add
)
10611 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10612 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10613 ? (XVECLEN (pat
, 0)
10614 + num_clobbers_to_add
)
10615 : num_clobbers_to_add
+ 1));
10617 if (GET_CODE (pat
) == PARALLEL
)
10618 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10619 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10621 XVECEXP (newpat
, 0, 0) = pat
;
10623 add_clobbers (newpat
, insn_code_number
);
10625 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10626 i
< XVECLEN (newpat
, 0); i
++)
10628 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10629 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10631 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10633 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10634 notes
= alloc_reg_note (REG_UNUSED
,
10635 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10641 if (insn_code_number
>= 0
10642 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10644 old_pat
= PATTERN (insn
);
10645 old_notes
= REG_NOTES (insn
);
10646 old_icode
= INSN_CODE (insn
);
10647 PATTERN (insn
) = pat
;
10648 REG_NOTES (insn
) = notes
;
10650 /* Allow targets to reject combined insn. */
10651 if (!targetm
.legitimate_combined_insn (insn
))
10653 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10654 fputs ("Instruction not appropriate for target.",
10657 /* Callers expect recog_for_combine to strip
10658 clobbers from the pattern on failure. */
10659 pat
= pat_without_clobbers
;
10662 insn_code_number
= -1;
10665 PATTERN (insn
) = old_pat
;
10666 REG_NOTES (insn
) = old_notes
;
10667 INSN_CODE (insn
) = old_icode
;
10673 return insn_code_number
;
10676 /* Like gen_lowpart_general but for use by combine. In combine it
10677 is not possible to create any new pseudoregs. However, it is
10678 safe to create invalid memory addresses, because combine will
10679 try to recognize them and all they will do is make the combine
10682 If for some reason this cannot do its job, an rtx
10683 (clobber (const_int 0)) is returned.
10684 An insn containing that will not be recognized. */
10687 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10689 enum machine_mode imode
= GET_MODE (x
);
10690 unsigned int osize
= GET_MODE_SIZE (omode
);
10691 unsigned int isize
= GET_MODE_SIZE (imode
);
10694 if (omode
== imode
)
10697 /* We can only support MODE being wider than a word if X is a
10698 constant integer or has a mode the same size. */
10699 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10700 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10703 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10704 won't know what to do. So we will strip off the SUBREG here and
10705 process normally. */
10706 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10708 x
= SUBREG_REG (x
);
10710 /* For use in case we fall down into the address adjustments
10711 further below, we need to adjust the known mode and size of
10712 x; imode and isize, since we just adjusted x. */
10713 imode
= GET_MODE (x
);
10715 if (imode
== omode
)
10718 isize
= GET_MODE_SIZE (imode
);
10721 result
= gen_lowpart_common (omode
, x
);
10730 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10732 if (MEM_VOLATILE_P (x
)
10733 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10736 /* If we want to refer to something bigger than the original memref,
10737 generate a paradoxical subreg instead. That will force a reload
10738 of the original memref X. */
10740 return gen_rtx_SUBREG (omode
, x
, 0);
10742 if (WORDS_BIG_ENDIAN
)
10743 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10745 /* Adjust the address so that the address-after-the-data is
10747 if (BYTES_BIG_ENDIAN
)
10748 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10750 return adjust_address_nv (x
, omode
, offset
);
10753 /* If X is a comparison operator, rewrite it in a new mode. This
10754 probably won't match, but may allow further simplifications. */
10755 else if (COMPARISON_P (x
))
10756 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10758 /* If we couldn't simplify X any other way, just enclose it in a
10759 SUBREG. Normally, this SUBREG won't match, but some patterns may
10760 include an explicit SUBREG or we may simplify it further in combine. */
10766 offset
= subreg_lowpart_offset (omode
, imode
);
10767 if (imode
== VOIDmode
)
10769 imode
= int_mode_for_mode (omode
);
10770 x
= gen_lowpart_common (imode
, x
);
10774 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10780 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10783 /* Try to simplify a comparison between OP0 and a constant OP1,
10784 where CODE is the comparison code that will be tested, into a
10785 (CODE OP0 const0_rtx) form.
10787 The result is a possibly different comparison code to use.
10788 *POP1 may be updated. */
10790 static enum rtx_code
10791 simplify_compare_const (enum rtx_code code
, rtx op0
, rtx
*pop1
)
10793 enum machine_mode mode
= GET_MODE (op0
);
10794 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10795 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10797 /* Get the constant we are comparing against and turn off all bits
10798 not on in our mode. */
10799 if (mode
!= VOIDmode
)
10800 const_op
= trunc_int_for_mode (const_op
, mode
);
10802 /* If we are comparing against a constant power of two and the value
10803 being compared can only have that single bit nonzero (e.g., it was
10804 `and'ed with that bit), we can replace this with a comparison
10807 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10808 || code
== LT
|| code
== LTU
)
10809 && mode_width
<= HOST_BITS_PER_WIDE_INT
10810 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10811 && (nonzero_bits (op0
, mode
)
10812 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10814 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10818 /* Similarly, if we are comparing a value known to be either -1 or
10819 0 with -1, change it to the opposite comparison against zero. */
10821 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10822 || code
== GEU
|| code
== LTU
)
10823 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10825 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10829 /* Do some canonicalizations based on the comparison code. We prefer
10830 comparisons against zero and then prefer equality comparisons.
10831 If we can reduce the size of a constant, we will do that too. */
10835 /* < C is equivalent to <= (C - 1) */
10840 /* ... fall through to LE case below. */
10846 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10853 /* If we are doing a <= 0 comparison on a value known to have
10854 a zero sign bit, we can replace this with == 0. */
10855 else if (const_op
== 0
10856 && mode_width
<= HOST_BITS_PER_WIDE_INT
10857 && (nonzero_bits (op0
, mode
)
10858 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10864 /* >= C is equivalent to > (C - 1). */
10869 /* ... fall through to GT below. */
10875 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10882 /* If we are doing a > 0 comparison on a value known to have
10883 a zero sign bit, we can replace this with != 0. */
10884 else if (const_op
== 0
10885 && mode_width
<= HOST_BITS_PER_WIDE_INT
10886 && (nonzero_bits (op0
, mode
)
10887 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10893 /* < C is equivalent to <= (C - 1). */
10898 /* ... fall through ... */
10900 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10901 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10902 && (unsigned HOST_WIDE_INT
) const_op
10903 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10913 /* unsigned <= 0 is equivalent to == 0 */
10916 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10917 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10918 && (unsigned HOST_WIDE_INT
) const_op
10919 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10927 /* >= C is equivalent to > (C - 1). */
10932 /* ... fall through ... */
10935 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10936 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10937 && (unsigned HOST_WIDE_INT
) const_op
10938 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10948 /* unsigned > 0 is equivalent to != 0 */
10951 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10952 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10953 && (unsigned HOST_WIDE_INT
) const_op
10954 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10965 *pop1
= GEN_INT (const_op
);
10969 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10970 comparison code that will be tested.
10972 The result is a possibly different comparison code to use. *POP0 and
10973 *POP1 may be updated.
10975 It is possible that we might detect that a comparison is either always
10976 true or always false. However, we do not perform general constant
10977 folding in combine, so this knowledge isn't useful. Such tautologies
10978 should have been detected earlier. Hence we ignore all such cases. */
10980 static enum rtx_code
10981 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10987 enum machine_mode mode
, tmode
;
10989 /* Try a few ways of applying the same transformation to both operands. */
10992 #ifndef WORD_REGISTER_OPERATIONS
10993 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10994 so check specially. */
10995 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10996 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10997 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10998 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10999 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11000 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11001 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11002 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11003 && CONST_INT_P (XEXP (op0
, 1))
11004 && XEXP (op0
, 1) == XEXP (op1
, 1)
11005 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11006 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11007 && (INTVAL (XEXP (op0
, 1))
11008 == (GET_MODE_PRECISION (GET_MODE (op0
))
11009 - (GET_MODE_PRECISION
11010 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11012 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11013 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11017 /* If both operands are the same constant shift, see if we can ignore the
11018 shift. We can if the shift is a rotate or if the bits shifted out of
11019 this shift are known to be zero for both inputs and if the type of
11020 comparison is compatible with the shift. */
11021 if (GET_CODE (op0
) == GET_CODE (op1
)
11022 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11023 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11024 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11025 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11026 || (GET_CODE (op0
) == ASHIFTRT
11027 && (code
!= GTU
&& code
!= LTU
11028 && code
!= GEU
&& code
!= LEU
)))
11029 && CONST_INT_P (XEXP (op0
, 1))
11030 && INTVAL (XEXP (op0
, 1)) >= 0
11031 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11032 && XEXP (op0
, 1) == XEXP (op1
, 1))
11034 enum machine_mode mode
= GET_MODE (op0
);
11035 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11036 int shift_count
= INTVAL (XEXP (op0
, 1));
11038 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11039 mask
&= (mask
>> shift_count
) << shift_count
;
11040 else if (GET_CODE (op0
) == ASHIFT
)
11041 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11043 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11044 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11045 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11050 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11051 SUBREGs are of the same mode, and, in both cases, the AND would
11052 be redundant if the comparison was done in the narrower mode,
11053 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11054 and the operand's possibly nonzero bits are 0xffffff01; in that case
11055 if we only care about QImode, we don't need the AND). This case
11056 occurs if the output mode of an scc insn is not SImode and
11057 STORE_FLAG_VALUE == 1 (e.g., the 386).
11059 Similarly, check for a case where the AND's are ZERO_EXTEND
11060 operations from some narrower mode even though a SUBREG is not
11063 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11064 && CONST_INT_P (XEXP (op0
, 1))
11065 && CONST_INT_P (XEXP (op1
, 1)))
11067 rtx inner_op0
= XEXP (op0
, 0);
11068 rtx inner_op1
= XEXP (op1
, 0);
11069 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11070 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11073 if (paradoxical_subreg_p (inner_op0
)
11074 && GET_CODE (inner_op1
) == SUBREG
11075 && (GET_MODE (SUBREG_REG (inner_op0
))
11076 == GET_MODE (SUBREG_REG (inner_op1
)))
11077 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11078 <= HOST_BITS_PER_WIDE_INT
)
11079 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11080 GET_MODE (SUBREG_REG (inner_op0
)))))
11081 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11082 GET_MODE (SUBREG_REG (inner_op1
))))))
11084 op0
= SUBREG_REG (inner_op0
);
11085 op1
= SUBREG_REG (inner_op1
);
11087 /* The resulting comparison is always unsigned since we masked
11088 off the original sign bit. */
11089 code
= unsigned_condition (code
);
11095 for (tmode
= GET_CLASS_NARROWEST_MODE
11096 (GET_MODE_CLASS (GET_MODE (op0
)));
11097 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11098 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11100 op0
= gen_lowpart (tmode
, inner_op0
);
11101 op1
= gen_lowpart (tmode
, inner_op1
);
11102 code
= unsigned_condition (code
);
11111 /* If both operands are NOT, we can strip off the outer operation
11112 and adjust the comparison code for swapped operands; similarly for
11113 NEG, except that this must be an equality comparison. */
11114 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11115 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11116 && (code
== EQ
|| code
== NE
)))
11117 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11123 /* If the first operand is a constant, swap the operands and adjust the
11124 comparison code appropriately, but don't do this if the second operand
11125 is already a constant integer. */
11126 if (swap_commutative_operands_p (op0
, op1
))
11128 tem
= op0
, op0
= op1
, op1
= tem
;
11129 code
= swap_condition (code
);
11132 /* We now enter a loop during which we will try to simplify the comparison.
11133 For the most part, we only are concerned with comparisons with zero,
11134 but some things may really be comparisons with zero but not start
11135 out looking that way. */
11137 while (CONST_INT_P (op1
))
11139 enum machine_mode mode
= GET_MODE (op0
);
11140 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11141 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11142 int equality_comparison_p
;
11143 int sign_bit_comparison_p
;
11144 int unsigned_comparison_p
;
11145 HOST_WIDE_INT const_op
;
11147 /* We only want to handle integral modes. This catches VOIDmode,
11148 CCmode, and the floating-point modes. An exception is that we
11149 can handle VOIDmode if OP0 is a COMPARE or a comparison
11152 if (GET_MODE_CLASS (mode
) != MODE_INT
11153 && ! (mode
== VOIDmode
11154 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11157 /* Try to simplify the compare to constant, possibly changing the
11158 comparison op, and/or changing op1 to zero. */
11159 code
= simplify_compare_const (code
, op0
, &op1
);
11160 const_op
= INTVAL (op1
);
11162 /* Compute some predicates to simplify code below. */
11164 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11165 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11166 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11169 /* If this is a sign bit comparison and we can do arithmetic in
11170 MODE, say that we will only be needing the sign bit of OP0. */
11171 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11172 op0
= force_to_mode (op0
, mode
,
11173 (unsigned HOST_WIDE_INT
) 1
11174 << (GET_MODE_PRECISION (mode
) - 1),
11177 /* Now try cases based on the opcode of OP0. If none of the cases
11178 does a "continue", we exit this loop immediately after the
11181 switch (GET_CODE (op0
))
11184 /* If we are extracting a single bit from a variable position in
11185 a constant that has only a single bit set and are comparing it
11186 with zero, we can convert this into an equality comparison
11187 between the position and the location of the single bit. */
11188 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11189 have already reduced the shift count modulo the word size. */
11190 if (!SHIFT_COUNT_TRUNCATED
11191 && CONST_INT_P (XEXP (op0
, 0))
11192 && XEXP (op0
, 1) == const1_rtx
11193 && equality_comparison_p
&& const_op
== 0
11194 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11196 if (BITS_BIG_ENDIAN
)
11197 i
= BITS_PER_WORD
- 1 - i
;
11199 op0
= XEXP (op0
, 2);
11203 /* Result is nonzero iff shift count is equal to I. */
11204 code
= reverse_condition (code
);
11208 /* ... fall through ... */
11211 tem
= expand_compound_operation (op0
);
11220 /* If testing for equality, we can take the NOT of the constant. */
11221 if (equality_comparison_p
11222 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11224 op0
= XEXP (op0
, 0);
11229 /* If just looking at the sign bit, reverse the sense of the
11231 if (sign_bit_comparison_p
)
11233 op0
= XEXP (op0
, 0);
11234 code
= (code
== GE
? LT
: GE
);
11240 /* If testing for equality, we can take the NEG of the constant. */
11241 if (equality_comparison_p
11242 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11244 op0
= XEXP (op0
, 0);
11249 /* The remaining cases only apply to comparisons with zero. */
11253 /* When X is ABS or is known positive,
11254 (neg X) is < 0 if and only if X != 0. */
11256 if (sign_bit_comparison_p
11257 && (GET_CODE (XEXP (op0
, 0)) == ABS
11258 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11259 && (nonzero_bits (XEXP (op0
, 0), mode
)
11260 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11263 op0
= XEXP (op0
, 0);
11264 code
= (code
== LT
? NE
: EQ
);
11268 /* If we have NEG of something whose two high-order bits are the
11269 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11270 if (num_sign_bit_copies (op0
, mode
) >= 2)
11272 op0
= XEXP (op0
, 0);
11273 code
= swap_condition (code
);
11279 /* If we are testing equality and our count is a constant, we
11280 can perform the inverse operation on our RHS. */
11281 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11282 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11283 op1
, XEXP (op0
, 1))) != 0)
11285 op0
= XEXP (op0
, 0);
11290 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11291 a particular bit. Convert it to an AND of a constant of that
11292 bit. This will be converted into a ZERO_EXTRACT. */
11293 if (const_op
== 0 && sign_bit_comparison_p
11294 && CONST_INT_P (XEXP (op0
, 1))
11295 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11297 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11298 ((unsigned HOST_WIDE_INT
) 1
11300 - INTVAL (XEXP (op0
, 1)))));
11301 code
= (code
== LT
? NE
: EQ
);
11305 /* Fall through. */
11308 /* ABS is ignorable inside an equality comparison with zero. */
11309 if (const_op
== 0 && equality_comparison_p
)
11311 op0
= XEXP (op0
, 0);
11317 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11318 (compare FOO CONST) if CONST fits in FOO's mode and we
11319 are either testing inequality or have an unsigned
11320 comparison with ZERO_EXTEND or a signed comparison with
11321 SIGN_EXTEND. But don't do it if we don't have a compare
11322 insn of the given mode, since we'd have to revert it
11323 later on, and then we wouldn't know whether to sign- or
11325 mode
= GET_MODE (XEXP (op0
, 0));
11326 if (GET_MODE_CLASS (mode
) == MODE_INT
11327 && ! unsigned_comparison_p
11328 && HWI_COMPUTABLE_MODE_P (mode
)
11329 && trunc_int_for_mode (const_op
, mode
) == const_op
11330 && have_insn_for (COMPARE
, mode
))
11332 op0
= XEXP (op0
, 0);
11338 /* Check for the case where we are comparing A - C1 with C2, that is
11340 (subreg:MODE (plus (A) (-C1))) op (C2)
11342 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11343 comparison in the wider mode. One of the following two conditions
11344 must be true in order for this to be valid:
11346 1. The mode extension results in the same bit pattern being added
11347 on both sides and the comparison is equality or unsigned. As
11348 C2 has been truncated to fit in MODE, the pattern can only be
11351 2. The mode extension results in the sign bit being copied on
11354 The difficulty here is that we have predicates for A but not for
11355 (A - C1) so we need to check that C1 is within proper bounds so
11356 as to perturbate A as little as possible. */
11358 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11359 && subreg_lowpart_p (op0
)
11360 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11361 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11362 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11364 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11365 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11366 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11369 && (unsigned HOST_WIDE_INT
) c1
11370 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11371 && (equality_comparison_p
|| unsigned_comparison_p
)
11372 /* (A - C1) zero-extends if it is positive and sign-extends
11373 if it is negative, C2 both zero- and sign-extends. */
11374 && ((0 == (nonzero_bits (a
, inner_mode
)
11375 & ~GET_MODE_MASK (mode
))
11377 /* (A - C1) sign-extends if it is positive and 1-extends
11378 if it is negative, C2 both sign- and 1-extends. */
11379 || (num_sign_bit_copies (a
, inner_mode
)
11380 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11383 || ((unsigned HOST_WIDE_INT
) c1
11384 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11385 /* (A - C1) always sign-extends, like C2. */
11386 && num_sign_bit_copies (a
, inner_mode
)
11387 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11388 - (mode_width
- 1))))
11390 op0
= SUBREG_REG (op0
);
11395 /* If the inner mode is narrower and we are extracting the low part,
11396 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11397 if (subreg_lowpart_p (op0
)
11398 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11399 /* Fall through */ ;
11403 /* ... fall through ... */
11406 mode
= GET_MODE (XEXP (op0
, 0));
11407 if (GET_MODE_CLASS (mode
) == MODE_INT
11408 && (unsigned_comparison_p
|| equality_comparison_p
)
11409 && HWI_COMPUTABLE_MODE_P (mode
)
11410 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11412 && have_insn_for (COMPARE
, mode
))
11414 op0
= XEXP (op0
, 0);
11420 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11421 this for equality comparisons due to pathological cases involving
11423 if (equality_comparison_p
11424 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11425 op1
, XEXP (op0
, 1))))
11427 op0
= XEXP (op0
, 0);
11432 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11433 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11434 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11436 op0
= XEXP (XEXP (op0
, 0), 0);
11437 code
= (code
== LT
? EQ
: NE
);
11443 /* We used to optimize signed comparisons against zero, but that
11444 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11445 arrive here as equality comparisons, or (GEU, LTU) are
11446 optimized away. No need to special-case them. */
11448 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11449 (eq B (minus A C)), whichever simplifies. We can only do
11450 this for equality comparisons due to pathological cases involving
11452 if (equality_comparison_p
11453 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11454 XEXP (op0
, 1), op1
)))
11456 op0
= XEXP (op0
, 0);
11461 if (equality_comparison_p
11462 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11463 XEXP (op0
, 0), op1
)))
11465 op0
= XEXP (op0
, 1);
11470 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11471 of bits in X minus 1, is one iff X > 0. */
11472 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11473 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11474 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11475 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11477 op0
= XEXP (op0
, 1);
11478 code
= (code
== GE
? LE
: GT
);
11484 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11485 if C is zero or B is a constant. */
11486 if (equality_comparison_p
11487 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11488 XEXP (op0
, 1), op1
)))
11490 op0
= XEXP (op0
, 0);
11497 case UNEQ
: case LTGT
:
11498 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11499 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11500 case UNORDERED
: case ORDERED
:
11501 /* We can't do anything if OP0 is a condition code value, rather
11502 than an actual data value. */
11504 || CC0_P (XEXP (op0
, 0))
11505 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11508 /* Get the two operands being compared. */
11509 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11510 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11512 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11514 /* Check for the cases where we simply want the result of the
11515 earlier test or the opposite of that result. */
11516 if (code
== NE
|| code
== EQ
11517 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11518 && (code
== LT
|| code
== GE
)))
11520 enum rtx_code new_code
;
11521 if (code
== LT
|| code
== NE
)
11522 new_code
= GET_CODE (op0
);
11524 new_code
= reversed_comparison_code (op0
, NULL
);
11526 if (new_code
!= UNKNOWN
)
11537 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11539 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11540 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11541 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11543 op0
= XEXP (op0
, 1);
11544 code
= (code
== GE
? GT
: LE
);
11550 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11551 will be converted to a ZERO_EXTRACT later. */
11552 if (const_op
== 0 && equality_comparison_p
11553 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11554 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11556 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11557 XEXP (XEXP (op0
, 0), 1));
11558 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11562 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11563 zero and X is a comparison and C1 and C2 describe only bits set
11564 in STORE_FLAG_VALUE, we can compare with X. */
11565 if (const_op
== 0 && equality_comparison_p
11566 && mode_width
<= HOST_BITS_PER_WIDE_INT
11567 && CONST_INT_P (XEXP (op0
, 1))
11568 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11569 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11570 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11571 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11573 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11574 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11575 if ((~STORE_FLAG_VALUE
& mask
) == 0
11576 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11577 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11578 && COMPARISON_P (tem
))))
11580 op0
= XEXP (XEXP (op0
, 0), 0);
11585 /* If we are doing an equality comparison of an AND of a bit equal
11586 to the sign bit, replace this with a LT or GE comparison of
11587 the underlying value. */
11588 if (equality_comparison_p
11590 && CONST_INT_P (XEXP (op0
, 1))
11591 && mode_width
<= HOST_BITS_PER_WIDE_INT
11592 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11593 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11595 op0
= XEXP (op0
, 0);
11596 code
= (code
== EQ
? GE
: LT
);
11600 /* If this AND operation is really a ZERO_EXTEND from a narrower
11601 mode, the constant fits within that mode, and this is either an
11602 equality or unsigned comparison, try to do this comparison in
11607 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11608 -> (ne:DI (reg:SI 4) (const_int 0))
11610 unless TRULY_NOOP_TRUNCATION allows it or the register is
11611 known to hold a value of the required mode the
11612 transformation is invalid. */
11613 if ((equality_comparison_p
|| unsigned_comparison_p
)
11614 && CONST_INT_P (XEXP (op0
, 1))
11615 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11616 & GET_MODE_MASK (mode
))
11618 && const_op
>> i
== 0
11619 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11620 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11621 || (REG_P (XEXP (op0
, 0))
11622 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11624 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11628 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11629 fits in both M1 and M2 and the SUBREG is either paradoxical
11630 or represents the low part, permute the SUBREG and the AND
11632 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11634 unsigned HOST_WIDE_INT c1
;
11635 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11636 /* Require an integral mode, to avoid creating something like
11638 if (SCALAR_INT_MODE_P (tmode
)
11639 /* It is unsafe to commute the AND into the SUBREG if the
11640 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11641 not defined. As originally written the upper bits
11642 have a defined value due to the AND operation.
11643 However, if we commute the AND inside the SUBREG then
11644 they no longer have defined values and the meaning of
11645 the code has been changed. */
11647 #ifdef WORD_REGISTER_OPERATIONS
11648 || (mode_width
> GET_MODE_PRECISION (tmode
)
11649 && mode_width
<= BITS_PER_WORD
)
11651 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11652 && subreg_lowpart_p (XEXP (op0
, 0))))
11653 && CONST_INT_P (XEXP (op0
, 1))
11654 && mode_width
<= HOST_BITS_PER_WIDE_INT
11655 && HWI_COMPUTABLE_MODE_P (tmode
)
11656 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11657 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11659 && c1
!= GET_MODE_MASK (tmode
))
11661 op0
= simplify_gen_binary (AND
, tmode
,
11662 SUBREG_REG (XEXP (op0
, 0)),
11663 gen_int_mode (c1
, tmode
));
11664 op0
= gen_lowpart (mode
, op0
);
11669 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11670 if (const_op
== 0 && equality_comparison_p
11671 && XEXP (op0
, 1) == const1_rtx
11672 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11674 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11675 XEXP (XEXP (op0
, 0), 0), 1);
11676 code
= (code
== NE
? EQ
: NE
);
11680 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11681 (eq (and (lshiftrt X) 1) 0).
11682 Also handle the case where (not X) is expressed using xor. */
11683 if (const_op
== 0 && equality_comparison_p
11684 && XEXP (op0
, 1) == const1_rtx
11685 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11687 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11688 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11690 if (GET_CODE (shift_op
) == NOT
11691 || (GET_CODE (shift_op
) == XOR
11692 && CONST_INT_P (XEXP (shift_op
, 1))
11693 && CONST_INT_P (shift_count
)
11694 && HWI_COMPUTABLE_MODE_P (mode
)
11695 && (UINTVAL (XEXP (shift_op
, 1))
11696 == (unsigned HOST_WIDE_INT
) 1
11697 << INTVAL (shift_count
))))
11700 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11701 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11702 code
= (code
== NE
? EQ
: NE
);
11709 /* If we have (compare (ashift FOO N) (const_int C)) and
11710 the high order N bits of FOO (N+1 if an inequality comparison)
11711 are known to be zero, we can do this by comparing FOO with C
11712 shifted right N bits so long as the low-order N bits of C are
11714 if (CONST_INT_P (XEXP (op0
, 1))
11715 && INTVAL (XEXP (op0
, 1)) >= 0
11716 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11717 < HOST_BITS_PER_WIDE_INT
)
11718 && (((unsigned HOST_WIDE_INT
) const_op
11719 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11721 && mode_width
<= HOST_BITS_PER_WIDE_INT
11722 && (nonzero_bits (XEXP (op0
, 0), mode
)
11723 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11724 + ! equality_comparison_p
))) == 0)
11726 /* We must perform a logical shift, not an arithmetic one,
11727 as we want the top N bits of C to be zero. */
11728 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11730 temp
>>= INTVAL (XEXP (op0
, 1));
11731 op1
= gen_int_mode (temp
, mode
);
11732 op0
= XEXP (op0
, 0);
11736 /* If we are doing a sign bit comparison, it means we are testing
11737 a particular bit. Convert it to the appropriate AND. */
11738 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11739 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11741 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11742 ((unsigned HOST_WIDE_INT
) 1
11744 - INTVAL (XEXP (op0
, 1)))));
11745 code
= (code
== LT
? NE
: EQ
);
11749 /* If this an equality comparison with zero and we are shifting
11750 the low bit to the sign bit, we can convert this to an AND of the
11752 if (const_op
== 0 && equality_comparison_p
11753 && CONST_INT_P (XEXP (op0
, 1))
11754 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11756 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11762 /* If this is an equality comparison with zero, we can do this
11763 as a logical shift, which might be much simpler. */
11764 if (equality_comparison_p
&& const_op
== 0
11765 && CONST_INT_P (XEXP (op0
, 1)))
11767 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11769 INTVAL (XEXP (op0
, 1)));
11773 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11774 do the comparison in a narrower mode. */
11775 if (! unsigned_comparison_p
11776 && CONST_INT_P (XEXP (op0
, 1))
11777 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11778 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11779 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11780 MODE_INT
, 1)) != BLKmode
11781 && (((unsigned HOST_WIDE_INT
) const_op
11782 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11783 <= GET_MODE_MASK (tmode
)))
11785 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11789 /* Likewise if OP0 is a PLUS of a sign extension with a
11790 constant, which is usually represented with the PLUS
11791 between the shifts. */
11792 if (! unsigned_comparison_p
11793 && CONST_INT_P (XEXP (op0
, 1))
11794 && GET_CODE (XEXP (op0
, 0)) == PLUS
11795 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11796 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11797 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11798 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11799 MODE_INT
, 1)) != BLKmode
11800 && (((unsigned HOST_WIDE_INT
) const_op
11801 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11802 <= GET_MODE_MASK (tmode
)))
11804 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11805 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11806 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11807 add_const
, XEXP (op0
, 1));
11809 op0
= simplify_gen_binary (PLUS
, tmode
,
11810 gen_lowpart (tmode
, inner
),
11815 /* ... fall through ... */
11817 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11818 the low order N bits of FOO are known to be zero, we can do this
11819 by comparing FOO with C shifted left N bits so long as no
11820 overflow occurs. Even if the low order N bits of FOO aren't known
11821 to be zero, if the comparison is >= or < we can use the same
11822 optimization and for > or <= by setting all the low
11823 order N bits in the comparison constant. */
11824 if (CONST_INT_P (XEXP (op0
, 1))
11825 && INTVAL (XEXP (op0
, 1)) > 0
11826 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11827 && mode_width
<= HOST_BITS_PER_WIDE_INT
11828 && (((unsigned HOST_WIDE_INT
) const_op
11829 + (GET_CODE (op0
) != LSHIFTRT
11830 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11833 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11835 unsigned HOST_WIDE_INT low_bits
11836 = (nonzero_bits (XEXP (op0
, 0), mode
)
11837 & (((unsigned HOST_WIDE_INT
) 1
11838 << INTVAL (XEXP (op0
, 1))) - 1));
11839 if (low_bits
== 0 || !equality_comparison_p
)
11841 /* If the shift was logical, then we must make the condition
11843 if (GET_CODE (op0
) == LSHIFTRT
)
11844 code
= unsigned_condition (code
);
11846 const_op
<<= INTVAL (XEXP (op0
, 1));
11848 && (code
== GT
|| code
== GTU
11849 || code
== LE
|| code
== LEU
))
11851 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11852 op1
= GEN_INT (const_op
);
11853 op0
= XEXP (op0
, 0);
11858 /* If we are using this shift to extract just the sign bit, we
11859 can replace this with an LT or GE comparison. */
11861 && (equality_comparison_p
|| sign_bit_comparison_p
)
11862 && CONST_INT_P (XEXP (op0
, 1))
11863 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11865 op0
= XEXP (op0
, 0);
11866 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11878 /* Now make any compound operations involved in this comparison. Then,
11879 check for an outmost SUBREG on OP0 that is not doing anything or is
11880 paradoxical. The latter transformation must only be performed when
11881 it is known that the "extra" bits will be the same in op0 and op1 or
11882 that they don't matter. There are three cases to consider:
11884 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11885 care bits and we can assume they have any convenient value. So
11886 making the transformation is safe.
11888 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11889 In this case the upper bits of op0 are undefined. We should not make
11890 the simplification in that case as we do not know the contents of
11893 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11894 UNKNOWN. In that case we know those bits are zeros or ones. We must
11895 also be sure that they are the same as the upper bits of op1.
11897 We can never remove a SUBREG for a non-equality comparison because
11898 the sign bit is in a different place in the underlying object. */
11900 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11901 op1
= make_compound_operation (op1
, SET
);
11903 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11904 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11905 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11906 && (code
== NE
|| code
== EQ
))
11908 if (paradoxical_subreg_p (op0
))
11910 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11912 if (REG_P (SUBREG_REG (op0
)))
11914 op0
= SUBREG_REG (op0
);
11915 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11918 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11919 <= HOST_BITS_PER_WIDE_INT
)
11920 && (nonzero_bits (SUBREG_REG (op0
),
11921 GET_MODE (SUBREG_REG (op0
)))
11922 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11924 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11926 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11927 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11928 op0
= SUBREG_REG (op0
), op1
= tem
;
11932 /* We now do the opposite procedure: Some machines don't have compare
11933 insns in all modes. If OP0's mode is an integer mode smaller than a
11934 word and we can't do a compare in that mode, see if there is a larger
11935 mode for which we can do the compare. There are a number of cases in
11936 which we can use the wider mode. */
11938 mode
= GET_MODE (op0
);
11939 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11940 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11941 && ! have_insn_for (COMPARE
, mode
))
11942 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11943 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
11944 tmode
= GET_MODE_WIDER_MODE (tmode
))
11945 if (have_insn_for (COMPARE
, tmode
))
11949 /* If this is a test for negative, we can make an explicit
11950 test of the sign bit. Test this first so we can use
11951 a paradoxical subreg to extend OP0. */
11953 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11954 && HWI_COMPUTABLE_MODE_P (mode
))
11956 unsigned HOST_WIDE_INT sign
11957 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
11958 op0
= simplify_gen_binary (AND
, tmode
,
11959 gen_lowpart (tmode
, op0
),
11960 gen_int_mode (sign
, mode
));
11961 code
= (code
== LT
) ? NE
: EQ
;
11965 /* If the only nonzero bits in OP0 and OP1 are those in the
11966 narrower mode and this is an equality or unsigned comparison,
11967 we can use the wider mode. Similarly for sign-extended
11968 values, in which case it is true for all comparisons. */
11969 zero_extended
= ((code
== EQ
|| code
== NE
11970 || code
== GEU
|| code
== GTU
11971 || code
== LEU
|| code
== LTU
)
11972 && (nonzero_bits (op0
, tmode
)
11973 & ~GET_MODE_MASK (mode
)) == 0
11974 && ((CONST_INT_P (op1
)
11975 || (nonzero_bits (op1
, tmode
)
11976 & ~GET_MODE_MASK (mode
)) == 0)));
11979 || ((num_sign_bit_copies (op0
, tmode
)
11980 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11981 - GET_MODE_PRECISION (mode
)))
11982 && (num_sign_bit_copies (op1
, tmode
)
11983 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11984 - GET_MODE_PRECISION (mode
)))))
11986 /* If OP0 is an AND and we don't have an AND in MODE either,
11987 make a new AND in the proper mode. */
11988 if (GET_CODE (op0
) == AND
11989 && !have_insn_for (AND
, mode
))
11990 op0
= simplify_gen_binary (AND
, tmode
,
11991 gen_lowpart (tmode
,
11993 gen_lowpart (tmode
,
11999 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12000 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12004 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12005 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12012 /* We may have changed the comparison operands. Re-canonicalize. */
12013 if (swap_commutative_operands_p (op0
, op1
))
12015 tem
= op0
, op0
= op1
, op1
= tem
;
12016 code
= swap_condition (code
);
12019 /* If this machine only supports a subset of valid comparisons, see if we
12020 can convert an unsupported one into a supported one. */
12021 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12029 /* Utility function for record_value_for_reg. Count number of
12034 enum rtx_code code
= GET_CODE (x
);
12038 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12039 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12041 rtx x0
= XEXP (x
, 0);
12042 rtx x1
= XEXP (x
, 1);
12045 return 1 + 2 * count_rtxs (x0
);
12047 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12048 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12049 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12050 return 2 + 2 * count_rtxs (x0
)
12051 + count_rtxs (x
== XEXP (x1
, 0)
12052 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12054 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12055 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12056 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12057 return 2 + 2 * count_rtxs (x1
)
12058 + count_rtxs (x
== XEXP (x0
, 0)
12059 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12062 fmt
= GET_RTX_FORMAT (code
);
12063 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12065 ret
+= count_rtxs (XEXP (x
, i
));
12066 else if (fmt
[i
] == 'E')
12067 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12068 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12073 /* Utility function for following routine. Called when X is part of a value
12074 being stored into last_set_value. Sets last_set_table_tick
12075 for each register mentioned. Similar to mention_regs in cse.c */
12078 update_table_tick (rtx x
)
12080 enum rtx_code code
= GET_CODE (x
);
12081 const char *fmt
= GET_RTX_FORMAT (code
);
12086 unsigned int regno
= REGNO (x
);
12087 unsigned int endregno
= END_REGNO (x
);
12090 for (r
= regno
; r
< endregno
; r
++)
12092 reg_stat_type
*rsp
= ®_stat
[r
];
12093 rsp
->last_set_table_tick
= label_tick
;
12099 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12102 /* Check for identical subexpressions. If x contains
12103 identical subexpression we only have to traverse one of
12105 if (i
== 0 && ARITHMETIC_P (x
))
12107 /* Note that at this point x1 has already been
12109 rtx x0
= XEXP (x
, 0);
12110 rtx x1
= XEXP (x
, 1);
12112 /* If x0 and x1 are identical then there is no need to
12117 /* If x0 is identical to a subexpression of x1 then while
12118 processing x1, x0 has already been processed. Thus we
12119 are done with x. */
12120 if (ARITHMETIC_P (x1
)
12121 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12124 /* If x1 is identical to a subexpression of x0 then we
12125 still have to process the rest of x0. */
12126 if (ARITHMETIC_P (x0
)
12127 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12129 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12134 update_table_tick (XEXP (x
, i
));
12136 else if (fmt
[i
] == 'E')
12137 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12138 update_table_tick (XVECEXP (x
, i
, j
));
12141 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12142 are saying that the register is clobbered and we no longer know its
12143 value. If INSN is zero, don't update reg_stat[].last_set; this is
12144 only permitted with VALUE also zero and is used to invalidate the
12148 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12150 unsigned int regno
= REGNO (reg
);
12151 unsigned int endregno
= END_REGNO (reg
);
12153 reg_stat_type
*rsp
;
12155 /* If VALUE contains REG and we have a previous value for REG, substitute
12156 the previous value. */
12157 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12161 /* Set things up so get_last_value is allowed to see anything set up to
12163 subst_low_luid
= DF_INSN_LUID (insn
);
12164 tem
= get_last_value (reg
);
12166 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12167 it isn't going to be useful and will take a lot of time to process,
12168 so just use the CLOBBER. */
12172 if (ARITHMETIC_P (tem
)
12173 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12174 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12175 tem
= XEXP (tem
, 0);
12176 else if (count_occurrences (value
, reg
, 1) >= 2)
12178 /* If there are two or more occurrences of REG in VALUE,
12179 prevent the value from growing too much. */
12180 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12181 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12184 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12188 /* For each register modified, show we don't know its value, that
12189 we don't know about its bitwise content, that its value has been
12190 updated, and that we don't know the location of the death of the
12192 for (i
= regno
; i
< endregno
; i
++)
12194 rsp
= ®_stat
[i
];
12197 rsp
->last_set
= insn
;
12199 rsp
->last_set_value
= 0;
12200 rsp
->last_set_mode
= VOIDmode
;
12201 rsp
->last_set_nonzero_bits
= 0;
12202 rsp
->last_set_sign_bit_copies
= 0;
12203 rsp
->last_death
= 0;
12204 rsp
->truncated_to_mode
= VOIDmode
;
12207 /* Mark registers that are being referenced in this value. */
12209 update_table_tick (value
);
12211 /* Now update the status of each register being set.
12212 If someone is using this register in this block, set this register
12213 to invalid since we will get confused between the two lives in this
12214 basic block. This makes using this register always invalid. In cse, we
12215 scan the table to invalidate all entries using this register, but this
12216 is too much work for us. */
12218 for (i
= regno
; i
< endregno
; i
++)
12220 rsp
= ®_stat
[i
];
12221 rsp
->last_set_label
= label_tick
;
12223 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12224 rsp
->last_set_invalid
= 1;
12226 rsp
->last_set_invalid
= 0;
12229 /* The value being assigned might refer to X (like in "x++;"). In that
12230 case, we must replace it with (clobber (const_int 0)) to prevent
12232 rsp
= ®_stat
[regno
];
12233 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12235 value
= copy_rtx (value
);
12236 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12240 /* For the main register being modified, update the value, the mode, the
12241 nonzero bits, and the number of sign bit copies. */
12243 rsp
->last_set_value
= value
;
12247 enum machine_mode mode
= GET_MODE (reg
);
12248 subst_low_luid
= DF_INSN_LUID (insn
);
12249 rsp
->last_set_mode
= mode
;
12250 if (GET_MODE_CLASS (mode
) == MODE_INT
12251 && HWI_COMPUTABLE_MODE_P (mode
))
12252 mode
= nonzero_bits_mode
;
12253 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12254 rsp
->last_set_sign_bit_copies
12255 = num_sign_bit_copies (value
, GET_MODE (reg
));
12259 /* Called via note_stores from record_dead_and_set_regs to handle one
12260 SET or CLOBBER in an insn. DATA is the instruction in which the
12261 set is occurring. */
12264 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12266 rtx record_dead_insn
= (rtx
) data
;
12268 if (GET_CODE (dest
) == SUBREG
)
12269 dest
= SUBREG_REG (dest
);
12271 if (!record_dead_insn
)
12274 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12280 /* If we are setting the whole register, we know its value. Otherwise
12281 show that we don't know the value. We can handle SUBREG in
12283 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12284 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12285 else if (GET_CODE (setter
) == SET
12286 && GET_CODE (SET_DEST (setter
)) == SUBREG
12287 && SUBREG_REG (SET_DEST (setter
)) == dest
12288 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12289 && subreg_lowpart_p (SET_DEST (setter
)))
12290 record_value_for_reg (dest
, record_dead_insn
,
12291 gen_lowpart (GET_MODE (dest
),
12292 SET_SRC (setter
)));
12294 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12296 else if (MEM_P (dest
)
12297 /* Ignore pushes, they clobber nothing. */
12298 && ! push_operand (dest
, GET_MODE (dest
)))
12299 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12302 /* Update the records of when each REG was most recently set or killed
12303 for the things done by INSN. This is the last thing done in processing
12304 INSN in the combiner loop.
12306 We update reg_stat[], in particular fields last_set, last_set_value,
12307 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12308 last_death, and also the similar information mem_last_set (which insn
12309 most recently modified memory) and last_call_luid (which insn was the
12310 most recent subroutine call). */
12313 record_dead_and_set_regs (rtx insn
)
12318 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12320 if (REG_NOTE_KIND (link
) == REG_DEAD
12321 && REG_P (XEXP (link
, 0)))
12323 unsigned int regno
= REGNO (XEXP (link
, 0));
12324 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12326 for (i
= regno
; i
< endregno
; i
++)
12328 reg_stat_type
*rsp
;
12330 rsp
= ®_stat
[i
];
12331 rsp
->last_death
= insn
;
12334 else if (REG_NOTE_KIND (link
) == REG_INC
)
12335 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12340 hard_reg_set_iterator hrsi
;
12341 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12343 reg_stat_type
*rsp
;
12345 rsp
= ®_stat
[i
];
12346 rsp
->last_set_invalid
= 1;
12347 rsp
->last_set
= insn
;
12348 rsp
->last_set_value
= 0;
12349 rsp
->last_set_mode
= VOIDmode
;
12350 rsp
->last_set_nonzero_bits
= 0;
12351 rsp
->last_set_sign_bit_copies
= 0;
12352 rsp
->last_death
= 0;
12353 rsp
->truncated_to_mode
= VOIDmode
;
12356 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12358 /* We can't combine into a call pattern. Remember, though, that
12359 the return value register is set at this LUID. We could
12360 still replace a register with the return value from the
12361 wrong subroutine call! */
12362 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12365 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12368 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12369 register present in the SUBREG, so for each such SUBREG go back and
12370 adjust nonzero and sign bit information of the registers that are
12371 known to have some zero/sign bits set.
12373 This is needed because when combine blows the SUBREGs away, the
12374 information on zero/sign bits is lost and further combines can be
12375 missed because of that. */
12378 record_promoted_value (rtx insn
, rtx subreg
)
12380 struct insn_link
*links
;
12382 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12383 enum machine_mode mode
= GET_MODE (subreg
);
12385 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12388 for (links
= LOG_LINKS (insn
); links
;)
12390 reg_stat_type
*rsp
;
12392 insn
= links
->insn
;
12393 set
= single_set (insn
);
12395 if (! set
|| !REG_P (SET_DEST (set
))
12396 || REGNO (SET_DEST (set
)) != regno
12397 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12399 links
= links
->next
;
12403 rsp
= ®_stat
[regno
];
12404 if (rsp
->last_set
== insn
)
12406 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12407 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12410 if (REG_P (SET_SRC (set
)))
12412 regno
= REGNO (SET_SRC (set
));
12413 links
= LOG_LINKS (insn
);
12420 /* Check if X, a register, is known to contain a value already
12421 truncated to MODE. In this case we can use a subreg to refer to
12422 the truncated value even though in the generic case we would need
12423 an explicit truncation. */
12426 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12428 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12429 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12432 || rsp
->truncation_label
< label_tick_ebb_start
)
12434 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12436 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12441 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12442 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12443 might be able to turn a truncate into a subreg using this information.
12444 Return -1 if traversing *P is complete or 0 otherwise. */
12447 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12450 enum machine_mode truncated_mode
;
12451 reg_stat_type
*rsp
;
12453 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12455 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12456 truncated_mode
= GET_MODE (x
);
12458 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12461 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12464 x
= SUBREG_REG (x
);
12466 /* ??? For hard-regs we now record everything. We might be able to
12467 optimize this using last_set_mode. */
12468 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12469 truncated_mode
= GET_MODE (x
);
12473 rsp
= ®_stat
[REGNO (x
)];
12474 if (rsp
->truncated_to_mode
== 0
12475 || rsp
->truncation_label
< label_tick_ebb_start
12476 || (GET_MODE_SIZE (truncated_mode
)
12477 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12479 rsp
->truncated_to_mode
= truncated_mode
;
12480 rsp
->truncation_label
= label_tick
;
12486 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12487 the modes they are used in. This can help truning TRUNCATEs into
12491 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12493 for_each_rtx (x
, record_truncated_value
, NULL
);
12496 /* Scan X for promoted SUBREGs. For each one found,
12497 note what it implies to the registers used in it. */
12500 check_promoted_subreg (rtx insn
, rtx x
)
12502 if (GET_CODE (x
) == SUBREG
12503 && SUBREG_PROMOTED_VAR_P (x
)
12504 && REG_P (SUBREG_REG (x
)))
12505 record_promoted_value (insn
, x
);
12508 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12511 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12515 check_promoted_subreg (insn
, XEXP (x
, i
));
12519 if (XVEC (x
, i
) != 0)
12520 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12521 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12527 /* Verify that all the registers and memory references mentioned in *LOC are
12528 still valid. *LOC was part of a value set in INSN when label_tick was
12529 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12530 the invalid references with (clobber (const_int 0)) and return 1. This
12531 replacement is useful because we often can get useful information about
12532 the form of a value (e.g., if it was produced by a shift that always
12533 produces -1 or 0) even though we don't know exactly what registers it
12534 was produced from. */
12537 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12540 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12541 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12546 unsigned int regno
= REGNO (x
);
12547 unsigned int endregno
= END_REGNO (x
);
12550 for (j
= regno
; j
< endregno
; j
++)
12552 reg_stat_type
*rsp
= ®_stat
[j
];
12553 if (rsp
->last_set_invalid
12554 /* If this is a pseudo-register that was only set once and not
12555 live at the beginning of the function, it is always valid. */
12556 || (! (regno
>= FIRST_PSEUDO_REGISTER
12557 && REG_N_SETS (regno
) == 1
12558 && (!REGNO_REG_SET_P
12559 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12560 && rsp
->last_set_label
> tick
))
12563 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12570 /* If this is a memory reference, make sure that there were no stores after
12571 it that might have clobbered the value. We don't have alias info, so we
12572 assume any store invalidates it. Moreover, we only have local UIDs, so
12573 we also assume that there were stores in the intervening basic blocks. */
12574 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12575 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12578 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12582 for (i
= 0; i
< len
; i
++)
12586 /* Check for identical subexpressions. If x contains
12587 identical subexpression we only have to traverse one of
12589 if (i
== 1 && ARITHMETIC_P (x
))
12591 /* Note that at this point x0 has already been checked
12592 and found valid. */
12593 rtx x0
= XEXP (x
, 0);
12594 rtx x1
= XEXP (x
, 1);
12596 /* If x0 and x1 are identical then x is also valid. */
12600 /* If x1 is identical to a subexpression of x0 then
12601 while checking x0, x1 has already been checked. Thus
12602 it is valid and so as x. */
12603 if (ARITHMETIC_P (x0
)
12604 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12607 /* If x0 is identical to a subexpression of x1 then x is
12608 valid iff the rest of x1 is valid. */
12609 if (ARITHMETIC_P (x1
)
12610 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12612 get_last_value_validate (&XEXP (x1
,
12613 x0
== XEXP (x1
, 0) ? 1 : 0),
12614 insn
, tick
, replace
);
12617 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12621 else if (fmt
[i
] == 'E')
12622 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12623 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12624 insn
, tick
, replace
) == 0)
12628 /* If we haven't found a reason for it to be invalid, it is valid. */
12632 /* Get the last value assigned to X, if known. Some registers
12633 in the value may be replaced with (clobber (const_int 0)) if their value
12634 is known longer known reliably. */
12637 get_last_value (const_rtx x
)
12639 unsigned int regno
;
12641 reg_stat_type
*rsp
;
12643 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12644 then convert it to the desired mode. If this is a paradoxical SUBREG,
12645 we cannot predict what values the "extra" bits might have. */
12646 if (GET_CODE (x
) == SUBREG
12647 && subreg_lowpart_p (x
)
12648 && !paradoxical_subreg_p (x
)
12649 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12650 return gen_lowpart (GET_MODE (x
), value
);
12656 rsp
= ®_stat
[regno
];
12657 value
= rsp
->last_set_value
;
12659 /* If we don't have a value, or if it isn't for this basic block and
12660 it's either a hard register, set more than once, or it's a live
12661 at the beginning of the function, return 0.
12663 Because if it's not live at the beginning of the function then the reg
12664 is always set before being used (is never used without being set).
12665 And, if it's set only once, and it's always set before use, then all
12666 uses must have the same last value, even if it's not from this basic
12670 || (rsp
->last_set_label
< label_tick_ebb_start
12671 && (regno
< FIRST_PSEUDO_REGISTER
12672 || REG_N_SETS (regno
) != 1
12674 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12677 /* If the value was set in a later insn than the ones we are processing,
12678 we can't use it even if the register was only set once. */
12679 if (rsp
->last_set_label
== label_tick
12680 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12683 /* If the value has all its registers valid, return it. */
12684 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12687 /* Otherwise, make a copy and replace any invalid register with
12688 (clobber (const_int 0)). If that fails for some reason, return 0. */
12690 value
= copy_rtx (value
);
12691 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12697 /* Return nonzero if expression X refers to a REG or to memory
12698 that is set in an instruction more recent than FROM_LUID. */
12701 use_crosses_set_p (const_rtx x
, int from_luid
)
12705 enum rtx_code code
= GET_CODE (x
);
12709 unsigned int regno
= REGNO (x
);
12710 unsigned endreg
= END_REGNO (x
);
12712 #ifdef PUSH_ROUNDING
12713 /* Don't allow uses of the stack pointer to be moved,
12714 because we don't know whether the move crosses a push insn. */
12715 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12718 for (; regno
< endreg
; regno
++)
12720 reg_stat_type
*rsp
= ®_stat
[regno
];
12722 && rsp
->last_set_label
== label_tick
12723 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12729 if (code
== MEM
&& mem_last_set
> from_luid
)
12732 fmt
= GET_RTX_FORMAT (code
);
12734 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12739 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12740 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12743 else if (fmt
[i
] == 'e'
12744 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12750 /* Define three variables used for communication between the following
12753 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12754 static int reg_dead_flag
;
12756 /* Function called via note_stores from reg_dead_at_p.
12758 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12759 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12762 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12764 unsigned int regno
, endregno
;
12769 regno
= REGNO (dest
);
12770 endregno
= END_REGNO (dest
);
12771 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12772 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12775 /* Return nonzero if REG is known to be dead at INSN.
12777 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12778 referencing REG, it is dead. If we hit a SET referencing REG, it is
12779 live. Otherwise, see if it is live or dead at the start of the basic
12780 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12781 must be assumed to be always live. */
12784 reg_dead_at_p (rtx reg
, rtx insn
)
12789 /* Set variables for reg_dead_at_p_1. */
12790 reg_dead_regno
= REGNO (reg
);
12791 reg_dead_endregno
= END_REGNO (reg
);
12795 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12796 we allow the machine description to decide whether use-and-clobber
12797 patterns are OK. */
12798 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12800 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12801 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12805 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12806 beginning of basic block. */
12807 block
= BLOCK_FOR_INSN (insn
);
12812 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12814 return reg_dead_flag
== 1 ? 1 : 0;
12816 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12820 if (insn
== BB_HEAD (block
))
12823 insn
= PREV_INSN (insn
);
12826 /* Look at live-in sets for the basic block that we were in. */
12827 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12828 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12834 /* Note hard registers in X that are used. */
12837 mark_used_regs_combine (rtx x
)
12839 RTX_CODE code
= GET_CODE (x
);
12840 unsigned int regno
;
12851 case ADDR_DIFF_VEC
:
12854 /* CC0 must die in the insn after it is set, so we don't need to take
12855 special note of it here. */
12861 /* If we are clobbering a MEM, mark any hard registers inside the
12862 address as used. */
12863 if (MEM_P (XEXP (x
, 0)))
12864 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12869 /* A hard reg in a wide mode may really be multiple registers.
12870 If so, mark all of them just like the first. */
12871 if (regno
< FIRST_PSEUDO_REGISTER
)
12873 /* None of this applies to the stack, frame or arg pointers. */
12874 if (regno
== STACK_POINTER_REGNUM
12875 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12876 || regno
== HARD_FRAME_POINTER_REGNUM
12878 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12879 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12881 || regno
== FRAME_POINTER_REGNUM
)
12884 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12890 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12892 rtx testreg
= SET_DEST (x
);
12894 while (GET_CODE (testreg
) == SUBREG
12895 || GET_CODE (testreg
) == ZERO_EXTRACT
12896 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12897 testreg
= XEXP (testreg
, 0);
12899 if (MEM_P (testreg
))
12900 mark_used_regs_combine (XEXP (testreg
, 0));
12902 mark_used_regs_combine (SET_SRC (x
));
12910 /* Recursively scan the operands of this expression. */
12913 const char *fmt
= GET_RTX_FORMAT (code
);
12915 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12918 mark_used_regs_combine (XEXP (x
, i
));
12919 else if (fmt
[i
] == 'E')
12923 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12924 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12930 /* Remove register number REGNO from the dead registers list of INSN.
12932 Return the note used to record the death, if there was one. */
12935 remove_death (unsigned int regno
, rtx insn
)
12937 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12940 remove_note (insn
, note
);
12945 /* For each register (hardware or pseudo) used within expression X, if its
12946 death is in an instruction with luid between FROM_LUID (inclusive) and
12947 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12948 list headed by PNOTES.
12950 That said, don't move registers killed by maybe_kill_insn.
12952 This is done when X is being merged by combination into TO_INSN. These
12953 notes will then be distributed as needed. */
12956 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12961 enum rtx_code code
= GET_CODE (x
);
12965 unsigned int regno
= REGNO (x
);
12966 rtx where_dead
= reg_stat
[regno
].last_death
;
12968 /* Don't move the register if it gets killed in between from and to. */
12969 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12970 && ! reg_referenced_p (x
, maybe_kill_insn
))
12974 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12975 && DF_INSN_LUID (where_dead
) >= from_luid
12976 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12978 rtx note
= remove_death (regno
, where_dead
);
12980 /* It is possible for the call above to return 0. This can occur
12981 when last_death points to I2 or I1 that we combined with.
12982 In that case make a new note.
12984 We must also check for the case where X is a hard register
12985 and NOTE is a death note for a range of hard registers
12986 including X. In that case, we must put REG_DEAD notes for
12987 the remaining registers in place of NOTE. */
12989 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12990 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12991 > GET_MODE_SIZE (GET_MODE (x
))))
12993 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12994 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12995 unsigned int ourend
= END_HARD_REGNO (x
);
12998 for (i
= deadregno
; i
< deadend
; i
++)
12999 if (i
< regno
|| i
>= ourend
)
13000 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13003 /* If we didn't find any note, or if we found a REG_DEAD note that
13004 covers only part of the given reg, and we have a multi-reg hard
13005 register, then to be safe we must check for REG_DEAD notes
13006 for each register other than the first. They could have
13007 their own REG_DEAD notes lying around. */
13008 else if ((note
== 0
13010 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13011 < GET_MODE_SIZE (GET_MODE (x
)))))
13012 && regno
< FIRST_PSEUDO_REGISTER
13013 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13015 unsigned int ourend
= END_HARD_REGNO (x
);
13016 unsigned int i
, offset
;
13020 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13024 for (i
= regno
+ offset
; i
< ourend
; i
++)
13025 move_deaths (regno_reg_rtx
[i
],
13026 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13029 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13031 XEXP (note
, 1) = *pnotes
;
13035 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13041 else if (GET_CODE (x
) == SET
)
13043 rtx dest
= SET_DEST (x
);
13045 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13047 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13048 that accesses one word of a multi-word item, some
13049 piece of everything register in the expression is used by
13050 this insn, so remove any old death. */
13051 /* ??? So why do we test for equality of the sizes? */
13053 if (GET_CODE (dest
) == ZERO_EXTRACT
13054 || GET_CODE (dest
) == STRICT_LOW_PART
13055 || (GET_CODE (dest
) == SUBREG
13056 && (((GET_MODE_SIZE (GET_MODE (dest
))
13057 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13058 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13059 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13061 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13065 /* If this is some other SUBREG, we know it replaces the entire
13066 value, so use that as the destination. */
13067 if (GET_CODE (dest
) == SUBREG
)
13068 dest
= SUBREG_REG (dest
);
13070 /* If this is a MEM, adjust deaths of anything used in the address.
13071 For a REG (the only other possibility), the entire value is
13072 being replaced so the old value is not used in this insn. */
13075 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13080 else if (GET_CODE (x
) == CLOBBER
)
13083 len
= GET_RTX_LENGTH (code
);
13084 fmt
= GET_RTX_FORMAT (code
);
13086 for (i
= 0; i
< len
; i
++)
13091 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13092 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13095 else if (fmt
[i
] == 'e')
13096 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13100 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13101 pattern of an insn. X must be a REG. */
13104 reg_bitfield_target_p (rtx x
, rtx body
)
13108 if (GET_CODE (body
) == SET
)
13110 rtx dest
= SET_DEST (body
);
13112 unsigned int regno
, tregno
, endregno
, endtregno
;
13114 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13115 target
= XEXP (dest
, 0);
13116 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13117 target
= SUBREG_REG (XEXP (dest
, 0));
13121 if (GET_CODE (target
) == SUBREG
)
13122 target
= SUBREG_REG (target
);
13124 if (!REG_P (target
))
13127 tregno
= REGNO (target
), regno
= REGNO (x
);
13128 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13129 return target
== x
;
13131 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13132 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13134 return endregno
> tregno
&& regno
< endtregno
;
13137 else if (GET_CODE (body
) == PARALLEL
)
13138 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13139 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13145 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13146 as appropriate. I3 and I2 are the insns resulting from the combination
13147 insns including FROM (I2 may be zero).
13149 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13150 not need REG_DEAD notes because they are being substituted for. This
13151 saves searching in the most common cases.
13153 Each note in the list is either ignored or placed on some insns, depending
13154 on the type of note. */
13157 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13158 rtx elim_i1
, rtx elim_i0
)
13160 rtx note
, next_note
;
13163 for (note
= notes
; note
; note
= next_note
)
13165 rtx place
= 0, place2
= 0;
13167 next_note
= XEXP (note
, 1);
13168 switch (REG_NOTE_KIND (note
))
13172 /* Doesn't matter much where we put this, as long as it's somewhere.
13173 It is preferable to keep these notes on branches, which is most
13174 likely to be i3. */
13178 case REG_NON_LOCAL_GOTO
:
13183 gcc_assert (i2
&& JUMP_P (i2
));
13188 case REG_EH_REGION
:
13189 /* These notes must remain with the call or trapping instruction. */
13192 else if (i2
&& CALL_P (i2
))
13196 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13197 if (may_trap_p (i3
))
13199 else if (i2
&& may_trap_p (i2
))
13201 /* ??? Otherwise assume we've combined things such that we
13202 can now prove that the instructions can't trap. Drop the
13203 note in this case. */
13207 case REG_ARGS_SIZE
:
13208 /* ??? How to distribute between i3-i1. Assume i3 contains the
13209 entire adjustment. Assert i3 contains at least some adjust. */
13210 if (!noop_move_p (i3
))
13212 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13213 /* fixup_args_size_notes looks at REG_NORETURN note,
13214 so ensure the note is placed there first. */
13218 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13219 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13223 XEXP (n
, 1) = REG_NOTES (i3
);
13224 REG_NOTES (i3
) = n
;
13228 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13229 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13230 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13231 gcc_assert (old_size
!= args_size
13233 && !ACCUMULATE_OUTGOING_ARGS
13234 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13241 /* These notes must remain with the call. It should not be
13242 possible for both I2 and I3 to be a call. */
13247 gcc_assert (i2
&& CALL_P (i2
));
13253 /* Any clobbers for i3 may still exist, and so we must process
13254 REG_UNUSED notes from that insn.
13256 Any clobbers from i2 or i1 can only exist if they were added by
13257 recog_for_combine. In that case, recog_for_combine created the
13258 necessary REG_UNUSED notes. Trying to keep any original
13259 REG_UNUSED notes from these insns can cause incorrect output
13260 if it is for the same register as the original i3 dest.
13261 In that case, we will notice that the register is set in i3,
13262 and then add a REG_UNUSED note for the destination of i3, which
13263 is wrong. However, it is possible to have REG_UNUSED notes from
13264 i2 or i1 for register which were both used and clobbered, so
13265 we keep notes from i2 or i1 if they will turn into REG_DEAD
13268 /* If this register is set or clobbered in I3, put the note there
13269 unless there is one already. */
13270 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13272 if (from_insn
!= i3
)
13275 if (! (REG_P (XEXP (note
, 0))
13276 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13277 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13280 /* Otherwise, if this register is used by I3, then this register
13281 now dies here, so we must put a REG_DEAD note here unless there
13283 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13284 && ! (REG_P (XEXP (note
, 0))
13285 ? find_regno_note (i3
, REG_DEAD
,
13286 REGNO (XEXP (note
, 0)))
13287 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13289 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13297 /* These notes say something about results of an insn. We can
13298 only support them if they used to be on I3 in which case they
13299 remain on I3. Otherwise they are ignored.
13301 If the note refers to an expression that is not a constant, we
13302 must also ignore the note since we cannot tell whether the
13303 equivalence is still true. It might be possible to do
13304 slightly better than this (we only have a problem if I2DEST
13305 or I1DEST is present in the expression), but it doesn't
13306 seem worth the trouble. */
13308 if (from_insn
== i3
13309 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13314 /* These notes say something about how a register is used. They must
13315 be present on any use of the register in I2 or I3. */
13316 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13319 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13328 case REG_LABEL_TARGET
:
13329 case REG_LABEL_OPERAND
:
13330 /* This can show up in several ways -- either directly in the
13331 pattern, or hidden off in the constant pool with (or without?)
13332 a REG_EQUAL note. */
13333 /* ??? Ignore the without-reg_equal-note problem for now. */
13334 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13335 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13336 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13337 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13341 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13342 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13343 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13344 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13352 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13353 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13355 if (place
&& JUMP_P (place
)
13356 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13357 && (JUMP_LABEL (place
) == NULL
13358 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13360 rtx label
= JUMP_LABEL (place
);
13363 JUMP_LABEL (place
) = XEXP (note
, 0);
13364 else if (LABEL_P (label
))
13365 LABEL_NUSES (label
)--;
13368 if (place2
&& JUMP_P (place2
)
13369 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13370 && (JUMP_LABEL (place2
) == NULL
13371 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13373 rtx label
= JUMP_LABEL (place2
);
13376 JUMP_LABEL (place2
) = XEXP (note
, 0);
13377 else if (LABEL_P (label
))
13378 LABEL_NUSES (label
)--;
13384 /* This note says something about the value of a register prior
13385 to the execution of an insn. It is too much trouble to see
13386 if the note is still correct in all situations. It is better
13387 to simply delete it. */
13391 /* If we replaced the right hand side of FROM_INSN with a
13392 REG_EQUAL note, the original use of the dying register
13393 will not have been combined into I3 and I2. In such cases,
13394 FROM_INSN is guaranteed to be the first of the combined
13395 instructions, so we simply need to search back before
13396 FROM_INSN for the previous use or set of this register,
13397 then alter the notes there appropriately.
13399 If the register is used as an input in I3, it dies there.
13400 Similarly for I2, if it is nonzero and adjacent to I3.
13402 If the register is not used as an input in either I3 or I2
13403 and it is not one of the registers we were supposed to eliminate,
13404 there are two possibilities. We might have a non-adjacent I2
13405 or we might have somehow eliminated an additional register
13406 from a computation. For example, we might have had A & B where
13407 we discover that B will always be zero. In this case we will
13408 eliminate the reference to A.
13410 In both cases, we must search to see if we can find a previous
13411 use of A and put the death note there. */
13414 && from_insn
== i2mod
13415 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13420 && CALL_P (from_insn
)
13421 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13423 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13425 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13426 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13428 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13430 && reg_overlap_mentioned_p (XEXP (note
, 0),
13432 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13433 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13440 basic_block bb
= this_basic_block
;
13442 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13444 if (!NONDEBUG_INSN_P (tem
))
13446 if (tem
== BB_HEAD (bb
))
13451 /* If the register is being set at TEM, see if that is all
13452 TEM is doing. If so, delete TEM. Otherwise, make this
13453 into a REG_UNUSED note instead. Don't delete sets to
13454 global register vars. */
13455 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13456 || !global_regs
[REGNO (XEXP (note
, 0))])
13457 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13459 rtx set
= single_set (tem
);
13460 rtx inner_dest
= 0;
13462 rtx cc0_setter
= NULL_RTX
;
13466 for (inner_dest
= SET_DEST (set
);
13467 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13468 || GET_CODE (inner_dest
) == SUBREG
13469 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13470 inner_dest
= XEXP (inner_dest
, 0))
13473 /* Verify that it was the set, and not a clobber that
13474 modified the register.
13476 CC0 targets must be careful to maintain setter/user
13477 pairs. If we cannot delete the setter due to side
13478 effects, mark the user with an UNUSED note instead
13481 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13482 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13484 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13485 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13486 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13490 /* Move the notes and links of TEM elsewhere.
13491 This might delete other dead insns recursively.
13492 First set the pattern to something that won't use
13494 rtx old_notes
= REG_NOTES (tem
);
13496 PATTERN (tem
) = pc_rtx
;
13497 REG_NOTES (tem
) = NULL
;
13499 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13500 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13501 distribute_links (LOG_LINKS (tem
));
13503 SET_INSN_DELETED (tem
);
13508 /* Delete the setter too. */
13511 PATTERN (cc0_setter
) = pc_rtx
;
13512 old_notes
= REG_NOTES (cc0_setter
);
13513 REG_NOTES (cc0_setter
) = NULL
;
13515 distribute_notes (old_notes
, cc0_setter
,
13516 cc0_setter
, NULL_RTX
,
13517 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13518 distribute_links (LOG_LINKS (cc0_setter
));
13520 SET_INSN_DELETED (cc0_setter
);
13521 if (cc0_setter
== i2
)
13528 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13530 /* If there isn't already a REG_UNUSED note, put one
13531 here. Do not place a REG_DEAD note, even if
13532 the register is also used here; that would not
13533 match the algorithm used in lifetime analysis
13534 and can cause the consistency check in the
13535 scheduler to fail. */
13536 if (! find_regno_note (tem
, REG_UNUSED
,
13537 REGNO (XEXP (note
, 0))))
13542 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13544 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13548 /* If we are doing a 3->2 combination, and we have a
13549 register which formerly died in i3 and was not used
13550 by i2, which now no longer dies in i3 and is used in
13551 i2 but does not die in i2, and place is between i2
13552 and i3, then we may need to move a link from place to
13554 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13556 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13557 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13559 struct insn_link
*links
= LOG_LINKS (place
);
13560 LOG_LINKS (place
) = NULL
;
13561 distribute_links (links
);
13566 if (tem
== BB_HEAD (bb
))
13572 /* If the register is set or already dead at PLACE, we needn't do
13573 anything with this note if it is still a REG_DEAD note.
13574 We check here if it is set at all, not if is it totally replaced,
13575 which is what `dead_or_set_p' checks, so also check for it being
13578 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13580 unsigned int regno
= REGNO (XEXP (note
, 0));
13581 reg_stat_type
*rsp
= ®_stat
[regno
];
13583 if (dead_or_set_p (place
, XEXP (note
, 0))
13584 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13586 /* Unless the register previously died in PLACE, clear
13587 last_death. [I no longer understand why this is
13589 if (rsp
->last_death
!= place
)
13590 rsp
->last_death
= 0;
13594 rsp
->last_death
= place
;
13596 /* If this is a death note for a hard reg that is occupying
13597 multiple registers, ensure that we are still using all
13598 parts of the object. If we find a piece of the object
13599 that is unused, we must arrange for an appropriate REG_DEAD
13600 note to be added for it. However, we can't just emit a USE
13601 and tag the note to it, since the register might actually
13602 be dead; so we recourse, and the recursive call then finds
13603 the previous insn that used this register. */
13605 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13606 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13608 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13609 bool all_used
= true;
13612 for (i
= regno
; i
< endregno
; i
++)
13613 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13614 && ! find_regno_fusage (place
, USE
, i
))
13615 || dead_or_set_regno_p (place
, i
))
13623 /* Put only REG_DEAD notes for pieces that are
13624 not already dead or set. */
13626 for (i
= regno
; i
< endregno
;
13627 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13629 rtx piece
= regno_reg_rtx
[i
];
13630 basic_block bb
= this_basic_block
;
13632 if (! dead_or_set_p (place
, piece
)
13633 && ! reg_bitfield_target_p (piece
,
13636 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13639 distribute_notes (new_note
, place
, place
,
13640 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13643 else if (! refers_to_regno_p (i
, i
+ 1,
13644 PATTERN (place
), 0)
13645 && ! find_regno_fusage (place
, USE
, i
))
13646 for (tem
= PREV_INSN (place
); ;
13647 tem
= PREV_INSN (tem
))
13649 if (!NONDEBUG_INSN_P (tem
))
13651 if (tem
== BB_HEAD (bb
))
13655 if (dead_or_set_p (tem
, piece
)
13656 || reg_bitfield_target_p (piece
,
13659 add_reg_note (tem
, REG_UNUSED
, piece
);
13672 /* Any other notes should not be present at this point in the
13674 gcc_unreachable ();
13679 XEXP (note
, 1) = REG_NOTES (place
);
13680 REG_NOTES (place
) = note
;
13684 add_shallow_copy_of_reg_note (place2
, note
);
13688 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13689 I3, I2, and I1 to new locations. This is also called to add a link
13690 pointing at I3 when I3's destination is changed. */
13693 distribute_links (struct insn_link
*links
)
13695 struct insn_link
*link
, *next_link
;
13697 for (link
= links
; link
; link
= next_link
)
13703 next_link
= link
->next
;
13705 /* If the insn that this link points to is a NOTE or isn't a single
13706 set, ignore it. In the latter case, it isn't clear what we
13707 can do other than ignore the link, since we can't tell which
13708 register it was for. Such links wouldn't be used by combine
13711 It is not possible for the destination of the target of the link to
13712 have been changed by combine. The only potential of this is if we
13713 replace I3, I2, and I1 by I3 and I2. But in that case the
13714 destination of I2 also remains unchanged. */
13716 if (NOTE_P (link
->insn
)
13717 || (set
= single_set (link
->insn
)) == 0)
13720 reg
= SET_DEST (set
);
13721 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13722 || GET_CODE (reg
) == STRICT_LOW_PART
)
13723 reg
= XEXP (reg
, 0);
13725 /* A LOG_LINK is defined as being placed on the first insn that uses
13726 a register and points to the insn that sets the register. Start
13727 searching at the next insn after the target of the link and stop
13728 when we reach a set of the register or the end of the basic block.
13730 Note that this correctly handles the link that used to point from
13731 I3 to I2. Also note that not much searching is typically done here
13732 since most links don't point very far away. */
13734 for (insn
= NEXT_INSN (link
->insn
);
13735 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13736 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13737 insn
= NEXT_INSN (insn
))
13738 if (DEBUG_INSN_P (insn
))
13740 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13742 if (reg_referenced_p (reg
, PATTERN (insn
)))
13746 else if (CALL_P (insn
)
13747 && find_reg_fusage (insn
, USE
, reg
))
13752 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13755 /* If we found a place to put the link, place it there unless there
13756 is already a link to the same insn as LINK at that point. */
13760 struct insn_link
*link2
;
13762 FOR_EACH_LOG_LINK (link2
, place
)
13763 if (link2
->insn
== link
->insn
)
13768 link
->next
= LOG_LINKS (place
);
13769 LOG_LINKS (place
) = link
;
13771 /* Set added_links_insn to the earliest insn we added a
13773 if (added_links_insn
== 0
13774 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13775 added_links_insn
= place
;
13781 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13782 Check whether the expression pointer to by LOC is a register or
13783 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13784 Otherwise return zero. */
13787 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13792 && (REG_P (x
) || MEM_P (x
))
13793 && ! reg_mentioned_p (x
, (rtx
) expr
))
13798 /* Check for any register or memory mentioned in EQUIV that is not
13799 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13800 of EXPR where some registers may have been replaced by constants. */
13803 unmentioned_reg_p (rtx equiv
, rtx expr
)
13805 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13808 DEBUG_FUNCTION
void
13809 dump_combine_stats (FILE *file
)
13813 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13814 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13818 dump_combine_total_stats (FILE *file
)
13822 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13823 total_attempts
, total_merges
, total_extras
, total_successes
);
13827 gate_handle_combine (void)
13829 return (optimize
> 0);
13832 /* Try combining insns through substitution. */
13833 static unsigned int
13834 rest_of_handle_combine (void)
13836 int rebuild_jump_labels_after_combine
;
13838 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13839 df_note_add_problem ();
13842 regstat_init_n_sets_and_refs ();
13844 rebuild_jump_labels_after_combine
13845 = combine_instructions (get_insns (), max_reg_num ());
13847 /* Combining insns may have turned an indirect jump into a
13848 direct jump. Rebuild the JUMP_LABEL fields of jumping
13850 if (rebuild_jump_labels_after_combine
)
13852 timevar_push (TV_JUMP
);
13853 rebuild_jump_labels (get_insns ());
13855 timevar_pop (TV_JUMP
);
13858 regstat_free_n_sets_and_refs ();
13864 const pass_data pass_data_combine
=
13866 RTL_PASS
, /* type */
13867 "combine", /* name */
13868 OPTGROUP_NONE
, /* optinfo_flags */
13869 true, /* has_gate */
13870 true, /* has_execute */
13871 TV_COMBINE
, /* tv_id */
13872 PROP_cfglayout
, /* properties_required */
13873 0, /* properties_provided */
13874 0, /* properties_destroyed */
13875 0, /* todo_flags_start */
13876 ( TODO_df_finish
| TODO_verify_rtl_sharing
), /* todo_flags_finish */
13879 class pass_combine
: public rtl_opt_pass
13882 pass_combine (gcc::context
*ctxt
)
13883 : rtl_opt_pass (pass_data_combine
, ctxt
)
13886 /* opt_pass methods: */
13887 bool gate () { return gate_handle_combine (); }
13888 unsigned int execute () { return rest_of_handle_combine (); }
13890 }; // class pass_combine
13892 } // anon namespace
13895 make_pass_combine (gcc::context
*ctxt
)
13897 return new pass_combine (ctxt
);