1 /* Definitions of x86 tunable features.
2 Copyright (C
) 2013-2018 Free Software Foundation
, Inc.
4 This file is part of GCC.
6 GCC is free software
; you can redistribute it and
/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation
; either version
3, or (at your option
)
11 GCC is distributed in the hope that it will be useful
,
12 but WITHOUT ANY WARRANTY
; without even the implied warranty of
13 MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License and
17 a copy of the GCC Runtime Library Exception along with this program
;
18 see the files COPYING3 and COPYING.RUNTIME respectively. If not
, see
19 <http
://www.gnu.org
/licenses
/>.
*/
21 /* Tuning for a given CPU XXXX consists of
:
22 - adding new CPU into
:
23 - adding PROCESSOR_XXX to
processor_type (in i386.h
)
24 - possibly adding XXX into CPU attribute in i386.md
25 - adding XXX to
processor_alias_table (in i386.c
)
26 - introducing ix86_XXX_cost in i386.c
27 - Stringop generation table can be build based on test_stringop
28 - script (once rest of tuning is complete
)
29 - designing a scheduler model in
31 - Updating ix86_issue_rate and ix86_adjust_cost in i386.md
32 - possibly updating ia32_multipass_dfa_lookahead
, ix86_sched_reorder
33 and ix86_sched_init_global if those tricks are needed.
34 - Tunning the flags bellow. Those are split into sections and each
35 section is very roughly ordered by importance.
*/
37 /*****************************************************************************/
38 /* Scheduling flags.
*/
39 /*****************************************************************************/
41 /* X86_TUNE_SCHEDULE
: Enable scheduling.
*/
42 DEF_TUNE (X86_TUNE_SCHEDULE
, "schedule",
43 m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
44 | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
45 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC
)
47 /* X86_TUNE_PARTIAL_REG_DEPENDENCY
: Enable more register renaming
48 on modern chips. Preffer stores affecting whole integer register
49 over partial stores. For example preffer MOVZBL or MOVQ to load
8bit
51 DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY
, "partial_reg_dependency",
52 m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2
53 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
54 | m_KNL | m_KNM | m_AMD_MULTIPLE | m_TREMONT
57 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY
: This knob promotes all store
58 destinations to be
128bit to allow register renaming on
128bit SSE units
,
59 but usually results in one extra microop on
64bit SSE units.
60 Experimental results shows that disabling this option on P4 brings over
20%
61 SPECfp regression
, while enabling it on K8 brings roughly
2.4% regression
62 that can be partly masked by careful scheduling of moves.
*/
63 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY
, "sse_partial_reg_dependency",
64 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
65 | m_BDVER | m_ZNVER1 | m_GENERIC
)
67 /* X86_TUNE_SSE_SPLIT_REGS
: Set for machines where the type and dependencies
68 are resolved on SSE register parts instead of whole registers
, so we may
69 maintain just lower part of scalar values in proper format leaving the
70 upper part undefined.
*/
71 DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS
, "sse_split_regs", m_ATHLON_K8
)
73 /* X86_TUNE_PARTIAL_FLAG_REG_STALL
: this flag disables use of of flags
74 set by instructions affecting just some
flags (in particular shifts
).
75 This is because Core2 resolves dependencies on whole flags register
76 and such sequences introduce false dependency on previous instruction
79 The flags does not affect generation of
INC and
DEC that is controlled
80 by X86_TUNE_USE_INCDEC.
*/
82 DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL
, "partial_flag_reg_stall",
85 /* X86_TUNE_MOVX
: Enable to zero extend integer registers to avoid
86 partial dependencies.
*/
87 DEF_TUNE (X86_TUNE_MOVX
, "movx",
88 m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
89 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
90 | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE
91 | m_CORE_AVX2 | m_TREMONT | m_GENERIC
)
93 /* X86_TUNE_MEMORY_MISMATCH_STALL
: Avoid partial stores that are followed by
95 DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL
, "memory_mismatch_stall",
96 m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
97 | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
98 | m_TREMONT | m_GENERIC
)
100 /* X86_TUNE_FUSE_CMP_AND_BRANCH_32
: Fuse compare with a subsequent
101 conditional jump instruction for
32 bit TARGET.
*/
102 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32
, "fuse_cmp_and_branch_32",
103 m_CORE_ALL | m_BDVER | m_ZNVER1 | m_GENERIC
)
105 /* X86_TUNE_FUSE_CMP_AND_BRANCH_64
: Fuse compare with a subsequent
106 conditional jump instruction for TARGET_64BIT.
*/
107 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64
, "fuse_cmp_and_branch_64",
108 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER | m_ZNVER1 | m_GENERIC
)
110 /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS
: Fuse compare with a
111 subsequent conditional jump instruction when the condition jump
112 check sign
flag (SF
) or overflow
flag (OF).
*/
113 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS
, "fuse_cmp_and_branch_soflags",
114 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER | m_ZNVER1 | m_GENERIC
)
116 /* X86_TUNE_FUSE_ALU_AND_BRANCH
: Fuse alu with a subsequent conditional
117 jump instruction when the alu instruction produces the CCFLAG consumed by
118 the conditional jump instruction.
*/
119 DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH
, "fuse_alu_and_branch",
120 m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC
)
123 /*****************************************************************************/
124 /* Function prologue
, epilogue and function calling sequences.
*/
125 /*****************************************************************************/
127 /* X86_TUNE_ACCUMULATE_OUTGOING_ARGS
: Allocate stack space for outgoing
128 arguments in prologue
/epilogue instead of separately for each call
129 by push
/pop instructions.
130 This increase code size by about
5% in
32bit mode
, less so in
64bit mode
131 because parameters are passed in registers. It is considerable
132 win for targets without stack engine that prevents multple push operations
133 to happen in parallel.
*/
135 DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS
, "accumulate_outgoing_args",
136 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
137 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ATHLON_K8
)
139 /* X86_TUNE_PROLOGUE_USING_MOVE
: Do not use push
/pop in prologues that are
140 considered on critical path.
*/
141 DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE
, "prologue_using_move",
142 m_PPRO | m_ATHLON_K8
)
144 /* X86_TUNE_PROLOGUE_USING_MOVE
: Do not use push
/pop in epilogues that are
145 considered on critical path.
*/
146 DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE
, "epilogue_using_move",
147 m_PPRO | m_ATHLON_K8
)
149 /* X86_TUNE_USE_LEAVE
: Use
"leave" instruction in epilogues where it fits.
*/
150 DEF_TUNE (X86_TUNE_USE_LEAVE
, "use_leave",
151 m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC
)
153 /* X86_TUNE_PUSH_MEMORY
: Enable generation of
"push mem" instructions.
154 Some chips
, like
486 and Pentium works faster with separate load
155 and push instructions.
*/
156 DEF_TUNE (X86_TUNE_PUSH_MEMORY
, "push_memory",
157 m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
160 /* X86_TUNE_SINGLE_PUSH
: Enable if single push insn is preferred
161 over esp subtraction.
*/
162 DEF_TUNE (X86_TUNE_SINGLE_PUSH
, "single_push", m_386 | m_486 | m_PENT
163 | m_LAKEMONT | m_K6_GEODE
)
165 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
166 over esp subtraction.
*/
167 DEF_TUNE (X86_TUNE_DOUBLE_PUSH
, "double_push", m_PENT | m_LAKEMONT
170 /* X86_TUNE_SINGLE_POP
: Enable if single pop insn is preferred
171 over esp addition.
*/
172 DEF_TUNE (X86_TUNE_SINGLE_POP
, "single_pop", m_386 | m_486 | m_PENT
173 | m_LAKEMONT | m_PPRO
)
175 /* X86_TUNE_DOUBLE_POP
: Enable if double pop insn is preferred
176 over esp addition.
*/
177 DEF_TUNE (X86_TUNE_DOUBLE_POP
, "double_pop", m_PENT | m_LAKEMONT
)
179 /*****************************************************************************/
180 /* Branch predictor tuning
*/
181 /*****************************************************************************/
183 /* X86_TUNE_PAD_SHORT_FUNCTION
: Make every function to be at least
4
184 instructions long.
*/
185 DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION
, "pad_short_function", m_BONNELL
)
187 /* X86_TUNE_PAD_RETURNS
: Place NOP before every RET that is a destination
188 of conditional jump or directly preceded by other jump instruction.
189 This is important for
AND K8
-AMDFAM10 because the branch prediction
190 architecture expect at most one jump per
2 byte window. Failing to
191 pad returns leads to misaligned return stack.
*/
192 DEF_TUNE (X86_TUNE_PAD_RETURNS
, "pad_returns",
193 m_ATHLON_K8 | m_AMDFAM10
)
195 /* X86_TUNE_FOUR_JUMP_LIMIT
: Some CPU cores are not able to predict more
196 than
4 branch instructions in the
16 byte window.
*/
197 DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT
, "four_jump_limit",
198 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
199 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL | m_ATHLON_K8
202 /*****************************************************************************/
203 /* Integer instruction selection tuning
*/
204 /*****************************************************************************/
206 /* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL
: Enable software prefetching
207 at
-O3. For the moment
, the prefetching seems badly tuned for Intel
209 DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL
, "software_prefetching_beneficial",
210 m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
)
212 /* X86_TUNE_LCP_STALL
: Avoid an expensive length
-changing prefix stall
213 on
16-bit immediate moves into memory on Core2 and Corei7.
*/
214 DEF_TUNE (X86_TUNE_LCP_STALL
, "lcp_stall", m_CORE_ALL | m_GENERIC
)
216 /* X86_TUNE_READ_MODIFY
: Enable use of read
-modify instructions such
217 as
"add mem, reg".
*/
218 DEF_TUNE (X86_TUNE_READ_MODIFY
, "read_modify", ~
(m_PENT | m_LAKEMONT | m_PPRO
))
220 /* X86_TUNE_USE_INCDEC
: Enable use of inc
/dec instructions.
222 Core2 and nehalem has stall of
7 cycles for partial flag register stalls.
223 Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop
224 is output only when the values needs to be really merged
, which is not
225 done by GCC generated code.
*/
226 DEF_TUNE (X86_TUNE_USE_INCDEC
, "use_incdec",
227 ~
(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
228 | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT
229 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC
))
231 /* X86_TUNE_INTEGER_DFMODE_MOVES
: Enable if integer moves are preferred
233 DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES
, "integer_dfmode_moves",
234 ~
(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
235 | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
236 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC
))
238 /* X86_TUNE_OPT_AGU
: Optimize for Address Generation Unit. This flag
239 will impact LEA instruction selection.
*/
240 DEF_TUNE (X86_TUNE_OPT_AGU
, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
241 | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL
)
243 /* X86_TUNE_AVOID_LEA_FOR_ADDR
: Avoid lea for address computation.
*/
244 DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR
, "avoid_lea_for_addr",
245 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
248 /* X86_TUNE_SLOW_IMUL_IMM32_MEM
: Imul of
32-bit constant and memory is
249 vector path on AMD machines.
250 FIXME
: Do we need to enable this for core?
*/
251 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM
, "slow_imul_imm32_mem",
254 /* X86_TUNE_SLOW_IMUL_IMM8
: Imul of
8-bit constant is vector path on AMD
256 FIXME
: Do we need to enable this for core?
*/
257 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8
, "slow_imul_imm8",
260 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE
: Try to avoid memory operands for
261 a conditional move.
*/
262 DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE
, "avoid_mem_opnd_for_cmove",
263 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
264 | m_KNM | m_TREMONT | m_INTEL
)
266 /* X86_TUNE_SINGLE_STRINGOP
: Enable use of single string operations
, such
267 as MOVS and
STOS (without a REP prefix
) to move
/set sequences of bytes.
*/
268 DEF_TUNE (X86_TUNE_SINGLE_STRINGOP
, "single_stringop", m_386 | m_P4_NOCONA
)
270 /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
: Enable generation of
271 compact prologues and epilogues by issuing a misaligned moves. This
272 requires target to handle misaligned moves and partial memory stalls
274 FIXME
: This may actualy be a win on more targets than listed here.
*/
275 DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
,
276 "misaligned_move_string_pro_epilogues",
277 m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC
)
279 /* X86_TUNE_USE_SAHF
: Controls use of SAHF.
*/
280 DEF_TUNE (X86_TUNE_USE_SAHF
, "use_sahf",
281 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
282 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
283 | m_BTVER | m_ZNVER1 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
286 /* X86_TUNE_USE_CLTD
: Controls use of CLTD and CTQO instructions.
*/
287 DEF_TUNE (X86_TUNE_USE_CLTD
, "use_cltd",
288 ~
(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
289 | m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
))
291 /* X86_TUNE_USE_BT
: Enable use of
BT (bit test
) instructions.
*/
292 DEF_TUNE (X86_TUNE_USE_BT
, "use_bt",
293 m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
294 | m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GOLDMONT_PLUS
295 | m_TREMONT | m_GENERIC
)
297 /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI
: Avoid false dependency
298 for bit
-manipulation instructions.
*/
299 DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI
, "avoid_false_dep_for_bmi",
300 m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC
)
302 /* X86_TUNE_ADJUST_UNROLL
: This enables adjusting the unroll factor based
303 on hardware capabilities. Bdver3 hardware has a loop buffer which makes
304 unrolling small loop less important. For
, such architectures we adjust
305 the unroll factor so that the unrolled loop fits the loop buffer.
*/
306 DEF_TUNE (X86_TUNE_ADJUST_UNROLL
, "adjust_unroll_factor", m_BDVER3 | m_BDVER4
)
308 /* X86_TUNE_ONE_IF_CONV_INSNS
: Restrict a number of cmov insns in
309 if
-converted sequence to one.
*/
310 DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN
, "one_if_conv_insn",
311 m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
312 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC
)
314 /*****************************************************************************/
315 /* 387 instruction selection tuning
*/
316 /*****************************************************************************/
318 /* X86_TUNE_USE_HIMODE_FIOP
: Enables use of x87 instructions with
16bit
320 FIXME
: Why this is disabled for modern chips?
*/
321 DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP
, "use_himode_fiop",
322 m_386 | m_486 | m_K6_GEODE
)
324 /* X86_TUNE_USE_SIMODE_FIOP
: Enables use of x87 instructions with
32bit
326 DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP
, "use_simode_fiop",
327 ~
(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
328 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
329 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC
))
331 /* X86_TUNE_USE_FFREEP
: Use freep instruction instead of fstp.
*/
332 DEF_TUNE (X86_TUNE_USE_FFREEP
, "use_ffreep", m_AMD_MULTIPLE
)
334 /* X86_TUNE_EXT_80387_CONSTANTS
: Use fancy
80387 constants
, such as PI.
*/
335 DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS
, "ext_80387_constants",
336 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
337 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT
338 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC
)
340 /*****************************************************************************/
341 /* SSE instruction selection tuning
*/
342 /*****************************************************************************/
344 /* X86_TUNE_GENERAL_REGS_SSE_SPILL
: Try to spill general regs to SSE
345 regs instead of memory.
*/
346 DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL
, "general_regs_sse_spill",
349 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL
: Use movups for misaligned loads instead
350 of a sequence loading registers by parts.
*/
351 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL
, "sse_unaligned_load_optimal",
352 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
353 | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS
354 | m_TREMONT | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER1 | m_GENERIC
)
356 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL
: Use movups for misaligned stores instead
357 of a sequence loading registers by parts.
*/
358 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL
, "sse_unaligned_store_optimal",
359 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
360 | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS
361 | m_TREMONT | m_BDVER | m_ZNVER1 | m_GENERIC
)
363 /* Use packed single precision instructions where posisble. I.e. movups instead
365 DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL
, "sse_packed_single_insn_optimal",
368 /* X86_TUNE_SSE_TYPELESS_STORES
: Always movaps
/movups for
128bit stores.
*/
369 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES
, "sse_typeless_stores",
370 m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC
)
372 /* X86_TUNE_SSE_LOAD0_BY_PXOR
: Always use pxor to load0 as opposed to
373 xorps
/xorpd and other variants.
*/
374 DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR
, "sse_load0_by_pxor",
375 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER1
378 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC
: Enable moves in from integer
379 to SSE registers. If disabled
, the moves will be done by storing
380 the value to memory and reloading.
*/
381 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC
, "inter_unit_moves_to_vec",
382 ~
(m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC
))
384 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC
: Enable moves in from SSE
385 to integer registers. If disabled
, the moves will be done by storing
386 the value to memory and reloading.
*/
387 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC
, "inter_unit_moves_from_vec",
390 /* X86_TUNE_INTER_UNIT_CONVERSIONS
: Enable float
<->integer conversions
391 to use both SSE and integer registers at a same time.
*/
392 DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS
, "inter_unit_conversions",
393 ~
(m_AMDFAM10 | m_BDVER
))
395 /* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS
: Try to split memory operand for
396 fp converts to destination register.
*/
397 DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS
, "split_mem_opnd_for_fp_converts",
398 m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS
399 | m_TREMONT | m_INTEL
)
401 /* X86_TUNE_USE_VECTOR_FP_CONVERTS
: Prefer vector packed SSE conversion
402 from FP to FP. This form of instructions avoids partial write to the
404 DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS
, "use_vector_fp_converts",
407 /* X86_TUNE_USE_VECTOR_CONVERTS
: Prefer vector packed SSE conversion
408 from integer to FP.
*/
409 DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS
, "use_vector_converts", m_AMDFAM10
)
411 /* X86_TUNE_SLOW_SHUFB
: Indicates tunings with slow pshufb instruction.
*/
412 DEF_TUNE (X86_TUNE_SLOW_PSHUFB
, "slow_pshufb",
413 m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
414 | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL
)
416 /* X86_TUNE_AVOID_4BYTE_PREFIXES
: Avoid instructions requiring
4+ bytes of prefixes.
*/
417 DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES
, "avoid_4byte_prefixes",
418 m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL
)
420 /* X86_TUNE_USE_GATHER
: Use gather instructions.
*/
421 DEF_TUNE (X86_TUNE_USE_GATHER
, "use_gather",
422 ~
(m_ZNVER1 | m_GENERIC
))
424 /* X86_TUNE_AVOID_128FMA_CHAINS
: Avoid creating loops with tight
128bit or
425 smaller FMA chain.
*/
426 DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS
, "avoid_fma_chains", m_ZNVER1
)
428 /*****************************************************************************/
429 /* AVX instruction selection
tuning (some of SSE flags affects AVX
, too
) */
430 /*****************************************************************************/
432 /* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL
: if false
, unaligned loads are
434 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL
, "256_unaligned_load_optimal",
435 ~
(m_NEHALEM | m_SANDYBRIDGE | m_GENERIC
))
437 /* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL
: if false
, unaligned stores are
439 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL
, "256_unaligned_store_optimal",
440 ~
(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_ZNVER1 | m_GENERIC
))
442 /* X86_TUNE_AVX128_OPTIMAL
: Enable
128-bit AVX instruction generation for
443 the auto
-vectorizer.
*/
444 DEF_TUNE (X86_TUNE_AVX128_OPTIMAL
, "avx128_optimal", m_BDVER | m_BTVER2
447 /* X86_TUNE_AVX256_OPTIMAL
: Use
256-bit AVX instructions instead of
512-bit AVX
448 instructions in the auto
-vectorizer.
*/
449 DEF_TUNE (X86_TUNE_AVX256_OPTIMAL
, "avx256_optimal", m_CORE_AVX512
)
451 /*****************************************************************************/
452 /* Historical relics
: tuning flags that helps a specific old CPU designs
*/
453 /*****************************************************************************/
455 /* X86_TUNE_DOUBLE_WITH_ADD
: Use add instead of sal to double value in
456 an integer register.
*/
457 DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD
, "double_with_add", ~m_386
)
459 /* X86_TUNE_ALWAYS_FANCY_MATH_387
: controls use of fancy
387 operations
,
460 such as fsqrt
, fprem
, fsin
, fcos
, fsincos etc.
461 Should be enabled for all targets that always has coprocesor.
*/
462 DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387
, "always_fancy_math_387",
463 ~
(m_386 | m_486 | m_LAKEMONT
))
465 /* X86_TUNE_UNROLL_STRLEN
: Produce (quite lame
) unrolled sequence for
466 inline strlen. This affects only
-minline
-all
-stringops mode. By
467 default we always dispatch to a library since our internal strlen
469 DEF_TUNE (X86_TUNE_UNROLL_STRLEN
, "unroll_strlen", ~m_386
)
471 /* X86_TUNE_SHIFT1
: Enables use of short encoding of
"sal reg" instead of
472 longer
"sal $1, reg".
*/
473 DEF_TUNE (X86_TUNE_SHIFT1
, "shift1", ~m_486
)
475 /* X86_TUNE_ZERO_EXTEND_WITH_AND
: Use
AND instruction instead
477 DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND
, "zero_extend_with_and",
480 /* X86_TUNE_PROMOTE_HIMODE_IMUL
: Modern CPUs have same latency for HImode
481 and SImode multiply
, but
386 and
486 do HImode multiply faster.
*/
482 DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL
, "promote_himode_imul",
485 /* X86_TUNE_FAST_PREFIX
: Enable demoting some
32bit or
64bit arithmetic
486 into
16bit
/8bit when resulting sequence is shorter. For example
487 for
"and $-65536, reg" to
16bit store of
0.
*/
488 DEF_TUNE (X86_TUNE_FAST_PREFIX
, "fast_prefix",
489 ~
(m_386 | m_486 | m_PENT | m_LAKEMONT
))
491 /* X86_TUNE_READ_MODIFY_WRITE
: Enable use of read modify write instructions
492 such as
"add $1, mem".
*/
493 DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE
, "read_modify_write",
494 ~
(m_PENT | m_LAKEMONT
))
496 /* X86_TUNE_MOVE_M1_VIA_OR
: On pentiums
, it is faster to load
-1 via
OR
498 DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR
, "move_m1_via_or", m_PENT | m_LAKEMONT
)
500 /* X86_TUNE_NOT_UNPAIRABLE
: NOT is not pairable on Pentium
, while XOR is
,
501 but one byte longer.
*/
502 DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE
, "not_unpairable", m_PENT | m_LAKEMONT
)
504 /* X86_TUNE_PARTIAL_REG_STALL
: Pentium pro
, unlike later chips
, handled
505 use of partial registers by renaming. This improved performance of
16bit
506 code where upper halves of registers are not used. It also leads to
507 an penalty whenever a
16bit store is followed by
32bit use. This flag
508 disables production of such sequences in common cases.
509 See also X86_TUNE_HIMODE_MATH.
511 In current implementation the partial register stalls are not eliminated
512 very well
- they can be introduced via subregs synthesized by combine
513 and can happen in caller
/callee saving sequences.
*/
514 DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL
, "partial_reg_stall", m_PPRO
)
516 /* X86_TUNE_PROMOTE_QIMODE
: When it is cheap
, turn
8bit arithmetic to
517 corresponding
32bit arithmetic.
*/
518 DEF_TUNE (X86_TUNE_PROMOTE_QIMODE
, "promote_qimode",
521 /* X86_TUNE_PROMOTE_HI_REGS
: Same
, but for
16bit artihmetic. Again we avoid
522 partial register stalls on PentiumPro targets.
*/
523 DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS
, "promote_hi_regs", m_PPRO
)
525 /* X86_TUNE_HIMODE_MATH
: Enable use of
16bit arithmetic.
526 On PPro this flag is meant to avoid partial register stalls.
*/
527 DEF_TUNE (X86_TUNE_HIMODE_MATH
, "himode_math", ~m_PPRO
)
529 /* X86_TUNE_SPLIT_LONG_MOVES
: Avoid instructions moving immediates
530 directly to memory.
*/
531 DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES
, "split_long_moves", m_PPRO
)
533 /* X86_TUNE_USE_XCHGB
: Use xchgb
%rh
,%rl instead of rolw
/rorw $
8,rx.
*/
534 DEF_TUNE (X86_TUNE_USE_XCHGB
, "use_xchgb", m_PENT4
)
536 /* X86_TUNE_USE_MOV0
: Use
"mov $0, reg" instead of
"xor reg, reg" to clear
538 DEF_TUNE (X86_TUNE_USE_MOV0
, "use_mov0", m_K6
)
540 /* X86_TUNE_NOT_VECTORMODE
: On AMD K6
, NOT is vector decoded with memory
541 operand that cannot be represented using a modRM byte. The XOR
542 replacement is long decoded
, so this split helps here as well.
*/
543 DEF_TUNE (X86_TUNE_NOT_VECTORMODE
, "not_vectormode", m_K6
)
545 /* X86_TUNE_AVOID_VECTOR_DECODE
: Enable splitters that avoid vector decoded
546 forms of instructions on K8 targets.
*/
547 DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE
, "avoid_vector_decode",
550 /*****************************************************************************/
551 /* This never worked well before.
*/
552 /*****************************************************************************/
554 /* X86_TUNE_BRANCH_PREDICTION_HINTS
: Branch hints were put in P4 based
555 on simulation result. But after P4 was made
, no performance benefit
556 was observed with branch hints. It also increases the code size.
557 As a result
, icc never generates branch hints.
*/
558 DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS
, "branch_prediction_hints", 0U)
560 /* X86_TUNE_QIMODE_MATH
: Enable use of
8bit arithmetic.
*/
561 DEF_TUNE (X86_TUNE_QIMODE_MATH
, "qimode_math", ~
0U)
563 /* X86_TUNE_PROMOTE_QI_REGS
: This enables generic code that promotes all
8bit
564 arithmetic to
32bit via PROMOTE_MODE macro. This code generation scheme
565 is usually used for RISC targets.
*/
566 DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS
, "promote_qi_regs", 0U)
568 /* X86_TUNE_EMIT_VZEROUPPER
: This enables vzeroupper instruction insertion
569 before a transfer of control flow out of the function.
*/
570 DEF_TUNE (X86_TUNE_EMIT_VZEROUPPER
, "emit_vzeroupper", ~m_KNL
)