1 /* Subroutines for insn-output.cc for SPARC.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #define IN_TARGET_CODE 1
27 #include "coretypes.h"
36 #include "stringpool.h"
43 #include "diagnostic-core.h"
45 #include "fold-const.h"
46 #include "stor-layout.h"
50 #include "insn-attr.h"
55 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "tree-pass.h"
62 #include "tree-vector-builder.h"
65 /* This file should be included last. */
66 #include "target-def.h"
70 struct processor_costs
{
74 /* Integer signed load */
77 /* Integer zeroed load */
83 /* fmov, fneg, fabs */
87 const int float_plusminus
;
93 const int float_cmove
;
99 const int float_div_sf
;
102 const int float_div_df
;
105 const int float_sqrt_sf
;
108 const int float_sqrt_df
;
116 /* integer multiply cost for each bit set past the most
117 significant 3, so the formula for multiply cost becomes:
120 highest_bit = highest_clear_bit(rs1);
122 highest_bit = highest_set_bit(rs1);
125 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
127 A value of zero indicates that the multiply costs is fixed,
129 const int int_mul_bit_factor
;
140 /* penalty for shifts, due to scheduling rules etc. */
141 const int shift_penalty
;
143 /* cost of a (predictable) branch. */
144 const int branch_cost
;
148 struct processor_costs cypress_costs
= {
149 COSTS_N_INSNS (2), /* int load */
150 COSTS_N_INSNS (2), /* int signed load */
151 COSTS_N_INSNS (2), /* int zeroed load */
152 COSTS_N_INSNS (2), /* float load */
153 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
154 COSTS_N_INSNS (5), /* fadd, fsub */
155 COSTS_N_INSNS (1), /* fcmp */
156 COSTS_N_INSNS (1), /* fmov, fmovr */
157 COSTS_N_INSNS (7), /* fmul */
158 COSTS_N_INSNS (37), /* fdivs */
159 COSTS_N_INSNS (37), /* fdivd */
160 COSTS_N_INSNS (63), /* fsqrts */
161 COSTS_N_INSNS (63), /* fsqrtd */
162 COSTS_N_INSNS (1), /* imul */
163 COSTS_N_INSNS (1), /* imulX */
164 0, /* imul bit factor */
165 COSTS_N_INSNS (1), /* idiv */
166 COSTS_N_INSNS (1), /* idivX */
167 COSTS_N_INSNS (1), /* movcc/movr */
168 0, /* shift penalty */
173 struct processor_costs supersparc_costs
= {
174 COSTS_N_INSNS (1), /* int load */
175 COSTS_N_INSNS (1), /* int signed load */
176 COSTS_N_INSNS (1), /* int zeroed load */
177 COSTS_N_INSNS (0), /* float load */
178 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
179 COSTS_N_INSNS (3), /* fadd, fsub */
180 COSTS_N_INSNS (3), /* fcmp */
181 COSTS_N_INSNS (1), /* fmov, fmovr */
182 COSTS_N_INSNS (3), /* fmul */
183 COSTS_N_INSNS (6), /* fdivs */
184 COSTS_N_INSNS (9), /* fdivd */
185 COSTS_N_INSNS (12), /* fsqrts */
186 COSTS_N_INSNS (12), /* fsqrtd */
187 COSTS_N_INSNS (4), /* imul */
188 COSTS_N_INSNS (4), /* imulX */
189 0, /* imul bit factor */
190 COSTS_N_INSNS (4), /* idiv */
191 COSTS_N_INSNS (4), /* idivX */
192 COSTS_N_INSNS (1), /* movcc/movr */
193 1, /* shift penalty */
198 struct processor_costs hypersparc_costs
= {
199 COSTS_N_INSNS (1), /* int load */
200 COSTS_N_INSNS (1), /* int signed load */
201 COSTS_N_INSNS (1), /* int zeroed load */
202 COSTS_N_INSNS (1), /* float load */
203 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
204 COSTS_N_INSNS (1), /* fadd, fsub */
205 COSTS_N_INSNS (1), /* fcmp */
206 COSTS_N_INSNS (1), /* fmov, fmovr */
207 COSTS_N_INSNS (1), /* fmul */
208 COSTS_N_INSNS (8), /* fdivs */
209 COSTS_N_INSNS (12), /* fdivd */
210 COSTS_N_INSNS (17), /* fsqrts */
211 COSTS_N_INSNS (17), /* fsqrtd */
212 COSTS_N_INSNS (17), /* imul */
213 COSTS_N_INSNS (17), /* imulX */
214 0, /* imul bit factor */
215 COSTS_N_INSNS (17), /* idiv */
216 COSTS_N_INSNS (17), /* idivX */
217 COSTS_N_INSNS (1), /* movcc/movr */
218 0, /* shift penalty */
223 struct processor_costs leon_costs
= {
224 COSTS_N_INSNS (1), /* int load */
225 COSTS_N_INSNS (1), /* int signed load */
226 COSTS_N_INSNS (1), /* int zeroed load */
227 COSTS_N_INSNS (1), /* float load */
228 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
229 COSTS_N_INSNS (1), /* fadd, fsub */
230 COSTS_N_INSNS (1), /* fcmp */
231 COSTS_N_INSNS (1), /* fmov, fmovr */
232 COSTS_N_INSNS (1), /* fmul */
233 COSTS_N_INSNS (15), /* fdivs */
234 COSTS_N_INSNS (15), /* fdivd */
235 COSTS_N_INSNS (23), /* fsqrts */
236 COSTS_N_INSNS (23), /* fsqrtd */
237 COSTS_N_INSNS (5), /* imul */
238 COSTS_N_INSNS (5), /* imulX */
239 0, /* imul bit factor */
240 COSTS_N_INSNS (5), /* idiv */
241 COSTS_N_INSNS (5), /* idivX */
242 COSTS_N_INSNS (1), /* movcc/movr */
243 0, /* shift penalty */
248 struct processor_costs leon3_costs
= {
249 COSTS_N_INSNS (1), /* int load */
250 COSTS_N_INSNS (1), /* int signed load */
251 COSTS_N_INSNS (1), /* int zeroed load */
252 COSTS_N_INSNS (1), /* float load */
253 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
254 COSTS_N_INSNS (1), /* fadd, fsub */
255 COSTS_N_INSNS (1), /* fcmp */
256 COSTS_N_INSNS (1), /* fmov, fmovr */
257 COSTS_N_INSNS (1), /* fmul */
258 COSTS_N_INSNS (14), /* fdivs */
259 COSTS_N_INSNS (15), /* fdivd */
260 COSTS_N_INSNS (22), /* fsqrts */
261 COSTS_N_INSNS (23), /* fsqrtd */
262 COSTS_N_INSNS (5), /* imul */
263 COSTS_N_INSNS (5), /* imulX */
264 0, /* imul bit factor */
265 COSTS_N_INSNS (35), /* idiv */
266 COSTS_N_INSNS (35), /* idivX */
267 COSTS_N_INSNS (1), /* movcc/movr */
268 0, /* shift penalty */
273 struct processor_costs leon5_costs
= {
274 COSTS_N_INSNS (1), /* int load */
275 COSTS_N_INSNS (1), /* int signed load */
276 COSTS_N_INSNS (1), /* int zeroed load */
277 COSTS_N_INSNS (1), /* float load */
278 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
279 COSTS_N_INSNS (1), /* fadd, fsub */
280 COSTS_N_INSNS (1), /* fcmp */
281 COSTS_N_INSNS (1), /* fmov, fmovr */
282 COSTS_N_INSNS (1), /* fmul */
283 COSTS_N_INSNS (17), /* fdivs */
284 COSTS_N_INSNS (18), /* fdivd */
285 COSTS_N_INSNS (25), /* fsqrts */
286 COSTS_N_INSNS (26), /* fsqrtd */
287 COSTS_N_INSNS (4), /* imul */
288 COSTS_N_INSNS (4), /* imulX */
289 0, /* imul bit factor */
290 COSTS_N_INSNS (35), /* idiv */
291 COSTS_N_INSNS (35), /* idivX */
292 COSTS_N_INSNS (1), /* movcc/movr */
293 0, /* shift penalty */
298 struct processor_costs sparclet_costs
= {
299 COSTS_N_INSNS (3), /* int load */
300 COSTS_N_INSNS (3), /* int signed load */
301 COSTS_N_INSNS (1), /* int zeroed load */
302 COSTS_N_INSNS (1), /* float load */
303 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
304 COSTS_N_INSNS (1), /* fadd, fsub */
305 COSTS_N_INSNS (1), /* fcmp */
306 COSTS_N_INSNS (1), /* fmov, fmovr */
307 COSTS_N_INSNS (1), /* fmul */
308 COSTS_N_INSNS (1), /* fdivs */
309 COSTS_N_INSNS (1), /* fdivd */
310 COSTS_N_INSNS (1), /* fsqrts */
311 COSTS_N_INSNS (1), /* fsqrtd */
312 COSTS_N_INSNS (5), /* imul */
313 COSTS_N_INSNS (5), /* imulX */
314 0, /* imul bit factor */
315 COSTS_N_INSNS (5), /* idiv */
316 COSTS_N_INSNS (5), /* idivX */
317 COSTS_N_INSNS (1), /* movcc/movr */
318 0, /* shift penalty */
323 struct processor_costs ultrasparc_costs
= {
324 COSTS_N_INSNS (2), /* int load */
325 COSTS_N_INSNS (3), /* int signed load */
326 COSTS_N_INSNS (2), /* int zeroed load */
327 COSTS_N_INSNS (2), /* float load */
328 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
329 COSTS_N_INSNS (4), /* fadd, fsub */
330 COSTS_N_INSNS (1), /* fcmp */
331 COSTS_N_INSNS (2), /* fmov, fmovr */
332 COSTS_N_INSNS (4), /* fmul */
333 COSTS_N_INSNS (13), /* fdivs */
334 COSTS_N_INSNS (23), /* fdivd */
335 COSTS_N_INSNS (13), /* fsqrts */
336 COSTS_N_INSNS (23), /* fsqrtd */
337 COSTS_N_INSNS (4), /* imul */
338 COSTS_N_INSNS (4), /* imulX */
339 2, /* imul bit factor */
340 COSTS_N_INSNS (37), /* idiv */
341 COSTS_N_INSNS (68), /* idivX */
342 COSTS_N_INSNS (2), /* movcc/movr */
343 2, /* shift penalty */
348 struct processor_costs ultrasparc3_costs
= {
349 COSTS_N_INSNS (2), /* int load */
350 COSTS_N_INSNS (3), /* int signed load */
351 COSTS_N_INSNS (3), /* int zeroed load */
352 COSTS_N_INSNS (2), /* float load */
353 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
354 COSTS_N_INSNS (4), /* fadd, fsub */
355 COSTS_N_INSNS (5), /* fcmp */
356 COSTS_N_INSNS (3), /* fmov, fmovr */
357 COSTS_N_INSNS (4), /* fmul */
358 COSTS_N_INSNS (17), /* fdivs */
359 COSTS_N_INSNS (20), /* fdivd */
360 COSTS_N_INSNS (20), /* fsqrts */
361 COSTS_N_INSNS (29), /* fsqrtd */
362 COSTS_N_INSNS (6), /* imul */
363 COSTS_N_INSNS (6), /* imulX */
364 0, /* imul bit factor */
365 COSTS_N_INSNS (40), /* idiv */
366 COSTS_N_INSNS (71), /* idivX */
367 COSTS_N_INSNS (2), /* movcc/movr */
368 0, /* shift penalty */
373 struct processor_costs niagara_costs
= {
374 COSTS_N_INSNS (3), /* int load */
375 COSTS_N_INSNS (3), /* int signed load */
376 COSTS_N_INSNS (3), /* int zeroed load */
377 COSTS_N_INSNS (9), /* float load */
378 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
379 COSTS_N_INSNS (8), /* fadd, fsub */
380 COSTS_N_INSNS (26), /* fcmp */
381 COSTS_N_INSNS (8), /* fmov, fmovr */
382 COSTS_N_INSNS (29), /* fmul */
383 COSTS_N_INSNS (54), /* fdivs */
384 COSTS_N_INSNS (83), /* fdivd */
385 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
386 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
387 COSTS_N_INSNS (11), /* imul */
388 COSTS_N_INSNS (11), /* imulX */
389 0, /* imul bit factor */
390 COSTS_N_INSNS (72), /* idiv */
391 COSTS_N_INSNS (72), /* idivX */
392 COSTS_N_INSNS (1), /* movcc/movr */
393 0, /* shift penalty */
398 struct processor_costs niagara2_costs
= {
399 COSTS_N_INSNS (3), /* int load */
400 COSTS_N_INSNS (3), /* int signed load */
401 COSTS_N_INSNS (3), /* int zeroed load */
402 COSTS_N_INSNS (3), /* float load */
403 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
404 COSTS_N_INSNS (6), /* fadd, fsub */
405 COSTS_N_INSNS (6), /* fcmp */
406 COSTS_N_INSNS (6), /* fmov, fmovr */
407 COSTS_N_INSNS (6), /* fmul */
408 COSTS_N_INSNS (19), /* fdivs */
409 COSTS_N_INSNS (33), /* fdivd */
410 COSTS_N_INSNS (19), /* fsqrts */
411 COSTS_N_INSNS (33), /* fsqrtd */
412 COSTS_N_INSNS (5), /* imul */
413 COSTS_N_INSNS (5), /* imulX */
414 0, /* imul bit factor */
415 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
416 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
417 COSTS_N_INSNS (1), /* movcc/movr */
418 0, /* shift penalty */
423 struct processor_costs niagara3_costs
= {
424 COSTS_N_INSNS (3), /* int load */
425 COSTS_N_INSNS (3), /* int signed load */
426 COSTS_N_INSNS (3), /* int zeroed load */
427 COSTS_N_INSNS (3), /* float load */
428 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
429 COSTS_N_INSNS (9), /* fadd, fsub */
430 COSTS_N_INSNS (9), /* fcmp */
431 COSTS_N_INSNS (9), /* fmov, fmovr */
432 COSTS_N_INSNS (9), /* fmul */
433 COSTS_N_INSNS (23), /* fdivs */
434 COSTS_N_INSNS (37), /* fdivd */
435 COSTS_N_INSNS (23), /* fsqrts */
436 COSTS_N_INSNS (37), /* fsqrtd */
437 COSTS_N_INSNS (9), /* imul */
438 COSTS_N_INSNS (9), /* imulX */
439 0, /* imul bit factor */
440 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
441 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
442 COSTS_N_INSNS (1), /* movcc/movr */
443 0, /* shift penalty */
448 struct processor_costs niagara4_costs
= {
449 COSTS_N_INSNS (5), /* int load */
450 COSTS_N_INSNS (5), /* int signed load */
451 COSTS_N_INSNS (5), /* int zeroed load */
452 COSTS_N_INSNS (5), /* float load */
453 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
454 COSTS_N_INSNS (11), /* fadd, fsub */
455 COSTS_N_INSNS (11), /* fcmp */
456 COSTS_N_INSNS (11), /* fmov, fmovr */
457 COSTS_N_INSNS (11), /* fmul */
458 COSTS_N_INSNS (24), /* fdivs */
459 COSTS_N_INSNS (37), /* fdivd */
460 COSTS_N_INSNS (24), /* fsqrts */
461 COSTS_N_INSNS (37), /* fsqrtd */
462 COSTS_N_INSNS (12), /* imul */
463 COSTS_N_INSNS (12), /* imulX */
464 0, /* imul bit factor */
465 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
466 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
467 COSTS_N_INSNS (1), /* movcc/movr */
468 0, /* shift penalty */
473 struct processor_costs niagara7_costs
= {
474 COSTS_N_INSNS (5), /* int load */
475 COSTS_N_INSNS (5), /* int signed load */
476 COSTS_N_INSNS (5), /* int zeroed load */
477 COSTS_N_INSNS (5), /* float load */
478 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
479 COSTS_N_INSNS (11), /* fadd, fsub */
480 COSTS_N_INSNS (11), /* fcmp */
481 COSTS_N_INSNS (11), /* fmov, fmovr */
482 COSTS_N_INSNS (11), /* fmul */
483 COSTS_N_INSNS (24), /* fdivs */
484 COSTS_N_INSNS (37), /* fdivd */
485 COSTS_N_INSNS (24), /* fsqrts */
486 COSTS_N_INSNS (37), /* fsqrtd */
487 COSTS_N_INSNS (12), /* imul */
488 COSTS_N_INSNS (12), /* imulX */
489 0, /* imul bit factor */
490 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
491 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
492 COSTS_N_INSNS (1), /* movcc/movr */
493 0, /* shift penalty */
498 struct processor_costs m8_costs
= {
499 COSTS_N_INSNS (3), /* int load */
500 COSTS_N_INSNS (3), /* int signed load */
501 COSTS_N_INSNS (3), /* int zeroed load */
502 COSTS_N_INSNS (3), /* float load */
503 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
504 COSTS_N_INSNS (9), /* fadd, fsub */
505 COSTS_N_INSNS (9), /* fcmp */
506 COSTS_N_INSNS (9), /* fmov, fmovr */
507 COSTS_N_INSNS (9), /* fmul */
508 COSTS_N_INSNS (26), /* fdivs */
509 COSTS_N_INSNS (30), /* fdivd */
510 COSTS_N_INSNS (33), /* fsqrts */
511 COSTS_N_INSNS (41), /* fsqrtd */
512 COSTS_N_INSNS (12), /* imul */
513 COSTS_N_INSNS (10), /* imulX */
514 0, /* imul bit factor */
515 COSTS_N_INSNS (57), /* udiv/sdiv */
516 COSTS_N_INSNS (30), /* udivx/sdivx */
517 COSTS_N_INSNS (1), /* movcc/movr */
518 0, /* shift penalty */
522 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
524 #ifdef HAVE_AS_RELAX_OPTION
525 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
526 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
527 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
528 somebody does not branch between the sethi and jmp. */
529 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
531 #define LEAF_SIBCALL_SLOT_RESERVED_P \
532 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
535 /* Vector, indexed by hard register number, which contains 1
536 for a register that is allowable in a candidate for leaf
537 function treatment. */
538 char sparc_leaf_regs
[] =
539 { 1, 1, 1, 1, 1, 1, 1, 1,
540 0, 0, 0, 0, 0, 0, 1, 0,
541 0, 0, 0, 0, 0, 0, 0, 0,
542 1, 1, 1, 1, 1, 1, 0, 1,
543 1, 1, 1, 1, 1, 1, 1, 1,
544 1, 1, 1, 1, 1, 1, 1, 1,
545 1, 1, 1, 1, 1, 1, 1, 1,
546 1, 1, 1, 1, 1, 1, 1, 1,
547 1, 1, 1, 1, 1, 1, 1, 1,
548 1, 1, 1, 1, 1, 1, 1, 1,
549 1, 1, 1, 1, 1, 1, 1, 1,
550 1, 1, 1, 1, 1, 1, 1, 1,
551 1, 1, 1, 1, 1, 1, 1};
553 struct GTY(()) machine_function
555 /* Size of the frame of the function. */
556 HOST_WIDE_INT frame_size
;
558 /* Size of the frame of the function minus the register window save area
559 and the outgoing argument area. */
560 HOST_WIDE_INT apparent_frame_size
;
562 /* Register we pretend the frame pointer is allocated to. Normally, this
563 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
564 record "offset" separately as it may be too big for (reg + disp). */
566 HOST_WIDE_INT frame_base_offset
;
568 /* Number of global or FP registers to be saved (as 4-byte quantities). */
569 int n_global_fp_regs
;
571 /* True if the current function is leaf and uses only leaf regs,
572 so that the SPARC leaf function optimization can be applied.
573 Private version of crtl->uses_only_leaf_regs, see
574 sparc_expand_prologue for the rationale. */
577 /* True if the prologue saves local or in registers. */
578 bool save_local_in_regs_p
;
580 /* True if the data calculated by sparc_expand_prologue are valid. */
581 bool prologue_data_valid_p
;
584 #define sparc_frame_size cfun->machine->frame_size
585 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
586 #define sparc_frame_base_reg cfun->machine->frame_base_reg
587 #define sparc_frame_base_offset cfun->machine->frame_base_offset
588 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
589 #define sparc_leaf_function_p cfun->machine->leaf_function_p
590 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
591 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
593 /* 1 if the next opcode is to be specially indented. */
594 int sparc_indent_opcode
= 0;
596 static void sparc_option_override (void);
597 static void sparc_init_modes (void);
598 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
599 const_tree
, bool, bool, int *, int *);
601 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
602 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
603 static int leon5_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
605 static void sparc_emit_set_const32 (rtx
, rtx
);
606 static void sparc_emit_set_const64 (rtx
, rtx
);
607 static void sparc_output_addr_vec (rtx
);
608 static void sparc_output_addr_diff_vec (rtx
);
609 static void sparc_output_deferred_case_vectors (void);
610 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool,
611 code_helper
= ERROR_MARK
);
612 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
613 static rtx
sparc_builtin_saveregs (void);
614 static int epilogue_renumber (rtx
*, int);
615 static bool sparc_assemble_integer (rtx
, unsigned int, int);
616 static int set_extends (rtx_insn
*);
617 static void sparc_asm_function_prologue (FILE *);
618 static void sparc_asm_function_epilogue (FILE *);
619 #ifdef TARGET_SOLARIS
620 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
621 tree
) ATTRIBUTE_UNUSED
;
623 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
624 static int sparc_issue_rate (void);
625 static void sparc_sched_init (FILE *, int, int);
626 static int sparc_use_sched_lookahead (void);
628 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
629 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
630 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
631 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
632 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
634 static bool sparc_function_ok_for_sibcall (tree
, tree
);
635 static void sparc_init_libfuncs (void);
636 static void sparc_init_builtins (void);
637 static void sparc_fpu_init_builtins (void);
638 static void sparc_vis_init_builtins (void);
639 static tree
sparc_builtin_decl (unsigned, bool);
640 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
641 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
642 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
643 HOST_WIDE_INT
, tree
);
644 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
645 HOST_WIDE_INT
, const_tree
);
646 static struct machine_function
* sparc_init_machine_status (void);
647 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
648 static rtx
sparc_tls_get_addr (void);
649 static rtx
sparc_tls_got (void);
650 static int sparc_register_move_cost (machine_mode
,
651 reg_class_t
, reg_class_t
);
652 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
653 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
654 int *, const_tree
, int);
655 static bool sparc_strict_argument_naming (cumulative_args_t
);
656 static void sparc_va_start (tree
, rtx
);
657 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
658 static bool sparc_vector_mode_supported_p (machine_mode
);
659 static bool sparc_tls_referenced_p (rtx
);
660 static rtx
sparc_legitimize_tls_address (rtx
);
661 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
662 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
663 static rtx
sparc_delegitimize_address (rtx
);
664 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
665 static bool sparc_pass_by_reference (cumulative_args_t
,
666 const function_arg_info
&);
667 static void sparc_function_arg_advance (cumulative_args_t
,
668 const function_arg_info
&);
669 static rtx
sparc_function_arg (cumulative_args_t
, const function_arg_info
&);
670 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
671 const function_arg_info
&);
672 static pad_direction
sparc_function_arg_padding (machine_mode
, const_tree
);
673 static unsigned int sparc_function_arg_boundary (machine_mode
,
675 static int sparc_arg_partial_bytes (cumulative_args_t
,
676 const function_arg_info
&);
677 static bool sparc_return_in_memory (const_tree
, const_tree
);
678 static rtx
sparc_struct_value_rtx (tree
, int);
679 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
680 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
681 static bool sparc_function_value_regno_p (const unsigned int);
682 static unsigned HOST_WIDE_INT
sparc_asan_shadow_offset (void);
683 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
684 static void sparc_file_end (void);
685 static bool sparc_frame_pointer_required (void);
686 static bool sparc_can_eliminate (const int, const int);
687 static void sparc_conditional_register_usage (void);
688 static bool sparc_use_pseudo_pic_reg (void);
689 static void sparc_init_pic_reg (void);
690 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
691 static const char *sparc_mangle_type (const_tree
);
693 static void sparc_trampoline_init (rtx
, tree
, rtx
);
694 static machine_mode
sparc_preferred_simd_mode (scalar_mode
);
695 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
696 static bool sparc_lra_p (void);
697 static bool sparc_print_operand_punct_valid_p (unsigned char);
698 static void sparc_print_operand (FILE *, rtx
, int);
699 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
700 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
702 secondary_reload_info
*);
703 static bool sparc_secondary_memory_needed (machine_mode
, reg_class_t
,
705 static machine_mode
sparc_secondary_memory_needed_mode (machine_mode
);
706 static scalar_int_mode
sparc_cstore_mode (enum insn_code icode
);
707 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
708 static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
709 static unsigned int sparc_min_arithmetic_precision (void);
710 static unsigned int sparc_hard_regno_nregs (unsigned int, machine_mode
);
711 static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode
);
712 static bool sparc_modes_tieable_p (machine_mode
, machine_mode
);
713 static bool sparc_can_change_mode_class (machine_mode
, machine_mode
,
715 static HOST_WIDE_INT
sparc_constant_alignment (const_tree
, HOST_WIDE_INT
);
716 static bool sparc_vectorize_vec_perm_const (machine_mode
, machine_mode
,
718 const vec_perm_indices
&);
719 static bool sparc_can_follow_jump (const rtx_insn
*, const rtx_insn
*);
720 static HARD_REG_SET
sparc_zero_call_used_regs (HARD_REG_SET
);
722 #ifdef SUBTARGET_ATTRIBUTE_TABLE
723 /* Table of valid machine attributes. */
724 static const struct attribute_spec sparc_attribute_table
[] =
726 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
727 do_diagnostic, handler, exclude } */
728 SUBTARGET_ATTRIBUTE_TABLE
,
729 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
733 char sparc_hard_reg_printed
[8];
735 /* Initialize the GCC target structure. */
737 /* The default is to use .half rather than .short for aligned HI objects. */
738 #undef TARGET_ASM_ALIGNED_HI_OP
739 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
741 #undef TARGET_ASM_UNALIGNED_HI_OP
742 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
743 #undef TARGET_ASM_UNALIGNED_SI_OP
744 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
745 #undef TARGET_ASM_UNALIGNED_DI_OP
746 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
748 /* The target hook has to handle DI-mode values. */
749 #undef TARGET_ASM_INTEGER
750 #define TARGET_ASM_INTEGER sparc_assemble_integer
752 #undef TARGET_ASM_FUNCTION_PROLOGUE
753 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
754 #undef TARGET_ASM_FUNCTION_EPILOGUE
755 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
757 #undef TARGET_SCHED_ADJUST_COST
758 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
759 #undef TARGET_SCHED_ISSUE_RATE
760 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
761 #undef TARGET_SCHED_INIT
762 #define TARGET_SCHED_INIT sparc_sched_init
763 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
764 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
766 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
767 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
769 #undef TARGET_INIT_LIBFUNCS
770 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
772 #undef TARGET_LEGITIMIZE_ADDRESS
773 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
774 #undef TARGET_DELEGITIMIZE_ADDRESS
775 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
776 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
777 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
779 #undef TARGET_INIT_BUILTINS
780 #define TARGET_INIT_BUILTINS sparc_init_builtins
781 #undef TARGET_BUILTIN_DECL
782 #define TARGET_BUILTIN_DECL sparc_builtin_decl
783 #undef TARGET_EXPAND_BUILTIN
784 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
785 #undef TARGET_FOLD_BUILTIN
786 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
789 #undef TARGET_HAVE_TLS
790 #define TARGET_HAVE_TLS true
793 #undef TARGET_CANNOT_FORCE_CONST_MEM
794 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
796 #undef TARGET_ASM_OUTPUT_MI_THUNK
797 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
798 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
799 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
801 #undef TARGET_RTX_COSTS
802 #define TARGET_RTX_COSTS sparc_rtx_costs
803 #undef TARGET_ADDRESS_COST
804 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
805 #undef TARGET_REGISTER_MOVE_COST
806 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
808 #undef TARGET_PROMOTE_FUNCTION_MODE
809 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
810 #undef TARGET_STRICT_ARGUMENT_NAMING
811 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
813 #undef TARGET_MUST_PASS_IN_STACK
814 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
815 #undef TARGET_PASS_BY_REFERENCE
816 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
817 #undef TARGET_ARG_PARTIAL_BYTES
818 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
819 #undef TARGET_FUNCTION_ARG_ADVANCE
820 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
821 #undef TARGET_FUNCTION_ARG
822 #define TARGET_FUNCTION_ARG sparc_function_arg
823 #undef TARGET_FUNCTION_INCOMING_ARG
824 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
825 #undef TARGET_FUNCTION_ARG_PADDING
826 #define TARGET_FUNCTION_ARG_PADDING sparc_function_arg_padding
827 #undef TARGET_FUNCTION_ARG_BOUNDARY
828 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
830 #undef TARGET_RETURN_IN_MEMORY
831 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
832 #undef TARGET_STRUCT_VALUE_RTX
833 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
834 #undef TARGET_FUNCTION_VALUE
835 #define TARGET_FUNCTION_VALUE sparc_function_value
836 #undef TARGET_LIBCALL_VALUE
837 #define TARGET_LIBCALL_VALUE sparc_libcall_value
838 #undef TARGET_FUNCTION_VALUE_REGNO_P
839 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
841 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
842 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
844 #undef TARGET_ASAN_SHADOW_OFFSET
845 #define TARGET_ASAN_SHADOW_OFFSET sparc_asan_shadow_offset
847 #undef TARGET_EXPAND_BUILTIN_VA_START
848 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
849 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
850 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
852 #undef TARGET_VECTOR_MODE_SUPPORTED_P
853 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
855 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
856 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
858 #ifdef SUBTARGET_INSERT_ATTRIBUTES
859 #undef TARGET_INSERT_ATTRIBUTES
860 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
863 #ifdef SUBTARGET_ATTRIBUTE_TABLE
864 #undef TARGET_ATTRIBUTE_TABLE
865 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
868 #undef TARGET_OPTION_OVERRIDE
869 #define TARGET_OPTION_OVERRIDE sparc_option_override
871 #ifdef TARGET_THREAD_SSP_OFFSET
872 #undef TARGET_STACK_PROTECT_GUARD
873 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
876 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
877 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
878 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
881 #undef TARGET_ASM_FILE_END
882 #define TARGET_ASM_FILE_END sparc_file_end
884 #undef TARGET_FRAME_POINTER_REQUIRED
885 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
887 #undef TARGET_CAN_ELIMINATE
888 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
890 #undef TARGET_PREFERRED_RELOAD_CLASS
891 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
893 #undef TARGET_SECONDARY_RELOAD
894 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
895 #undef TARGET_SECONDARY_MEMORY_NEEDED
896 #define TARGET_SECONDARY_MEMORY_NEEDED sparc_secondary_memory_needed
897 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
898 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE sparc_secondary_memory_needed_mode
900 #undef TARGET_CONDITIONAL_REGISTER_USAGE
901 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
903 #undef TARGET_INIT_PIC_REG
904 #define TARGET_INIT_PIC_REG sparc_init_pic_reg
906 #undef TARGET_USE_PSEUDO_PIC_REG
907 #define TARGET_USE_PSEUDO_PIC_REG sparc_use_pseudo_pic_reg
909 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
910 #undef TARGET_MANGLE_TYPE
911 #define TARGET_MANGLE_TYPE sparc_mangle_type
915 #define TARGET_LRA_P sparc_lra_p
917 #undef TARGET_LEGITIMATE_ADDRESS_P
918 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
920 #undef TARGET_LEGITIMATE_CONSTANT_P
921 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
923 #undef TARGET_TRAMPOLINE_INIT
924 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
926 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
927 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
928 #undef TARGET_PRINT_OPERAND
929 #define TARGET_PRINT_OPERAND sparc_print_operand
930 #undef TARGET_PRINT_OPERAND_ADDRESS
931 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
933 /* The value stored by LDSTUB. */
934 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
935 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
937 #undef TARGET_CSTORE_MODE
938 #define TARGET_CSTORE_MODE sparc_cstore_mode
940 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
941 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
943 #undef TARGET_FIXED_CONDITION_CODE_REGS
944 #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs
946 #undef TARGET_MIN_ARITHMETIC_PRECISION
947 #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision
949 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
950 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
952 #undef TARGET_HARD_REGNO_NREGS
953 #define TARGET_HARD_REGNO_NREGS sparc_hard_regno_nregs
954 #undef TARGET_HARD_REGNO_MODE_OK
955 #define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok
957 #undef TARGET_MODES_TIEABLE_P
958 #define TARGET_MODES_TIEABLE_P sparc_modes_tieable_p
960 #undef TARGET_CAN_CHANGE_MODE_CLASS
961 #define TARGET_CAN_CHANGE_MODE_CLASS sparc_can_change_mode_class
963 #undef TARGET_CONSTANT_ALIGNMENT
964 #define TARGET_CONSTANT_ALIGNMENT sparc_constant_alignment
966 #undef TARGET_VECTORIZE_VEC_PERM_CONST
967 #define TARGET_VECTORIZE_VEC_PERM_CONST sparc_vectorize_vec_perm_const
969 #undef TARGET_CAN_FOLLOW_JUMP
970 #define TARGET_CAN_FOLLOW_JUMP sparc_can_follow_jump
972 #undef TARGET_ZERO_CALL_USED_REGS
973 #define TARGET_ZERO_CALL_USED_REGS sparc_zero_call_used_regs
975 struct gcc_target targetm
= TARGET_INITIALIZER
;
977 /* Return the memory reference contained in X if any, zero otherwise. */
982 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
991 /* True if any of INSN's source register(s) is REG. */
994 insn_uses_reg_p (rtx_insn
*insn
, unsigned int reg
)
997 return ((REG_P (recog_data
.operand
[1])
998 && REGNO (recog_data
.operand
[1]) == reg
)
999 || (recog_data
.n_operands
== 3
1000 && REG_P (recog_data
.operand
[2])
1001 && REGNO (recog_data
.operand
[2]) == reg
));
1004 /* True if INSN is a floating-point division or square-root. */
1007 div_sqrt_insn_p (rtx_insn
*insn
)
1009 if (GET_CODE (PATTERN (insn
)) != SET
)
1012 switch (get_attr_type (insn
))
1024 /* True if INSN is a floating-point instruction. */
1027 fpop_insn_p (rtx_insn
*insn
)
1029 if (GET_CODE (PATTERN (insn
)) != SET
)
1032 switch (get_attr_type (insn
))
1049 /* True if INSN is an atomic instruction. */
1052 atomic_insn_for_leon3_p (rtx_insn
*insn
)
1054 switch (INSN_CODE (insn
))
1056 case CODE_FOR_swapsi
:
1057 case CODE_FOR_ldstub
:
1058 case CODE_FOR_atomic_compare_and_swap_leon3_1
:
1065 /* True if INSN is a store instruction. */
1068 store_insn_p (rtx_insn
*insn
)
1070 if (GET_CODE (PATTERN (insn
)) != SET
)
1073 switch (get_attr_type (insn
))
1083 /* True if INSN is a load instruction. */
1086 load_insn_p (rtx_insn
*insn
)
1088 if (GET_CODE (PATTERN (insn
)) != SET
)
1091 switch (get_attr_type (insn
))
1102 /* We use a machine specific pass to enable workarounds for errata.
1104 We need to have the (essentially) final form of the insn stream in order
1105 to properly detect the various hazards. Therefore, this machine specific
1106 pass runs as late as possible. */
1108 /* True if INSN is a md pattern or asm statement. */
1109 #define USEFUL_INSN_P(INSN) \
1110 (NONDEBUG_INSN_P (INSN) \
1111 && GET_CODE (PATTERN (INSN)) != USE \
1112 && GET_CODE (PATTERN (INSN)) != CLOBBER)
1115 next_active_non_empty_insn (rtx_insn
*insn
)
1117 insn
= next_active_insn (insn
);
1120 && (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
1121 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
1122 || (USEFUL_INSN_P (insn
)
1123 && (asm_noperands (PATTERN (insn
)) >= 0)
1124 && !strcmp (decode_asm_operands (PATTERN (insn
),
1127 insn
= next_active_insn (insn
);
1133 sparc_do_work_around_errata (void)
1135 rtx_insn
*insn
, *next
;
1136 bool find_first_useful
= true;
1138 /* Force all instructions to be split into their final form. */
1139 split_all_insns_noflow ();
1141 /* Now look for specific patterns in the insn stream. */
1142 for (insn
= get_insns (); insn
; insn
= next
)
1144 bool insert_nop
= false;
1149 /* Look into the instruction in a delay slot. */
1150 if (NONJUMP_INSN_P (insn
)
1151 && (seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
))))
1153 jump
= seq
->insn (0);
1154 insn
= seq
->insn (1);
1156 else if (JUMP_P (insn
))
1161 /* Do not begin function with atomic instruction. */
1163 && find_first_useful
1164 && USEFUL_INSN_P (insn
))
1166 find_first_useful
= false;
1167 if (atomic_insn_for_leon3_p (insn
))
1168 emit_insn_before (gen_nop (), insn
);
1171 /* Place a NOP at the branch target of an integer branch if it is a
1172 floating-point operation or a floating-point branch. */
1173 if (sparc_fix_gr712rc
1175 && jump_to_label_p (jump
)
1176 && get_attr_branch_type (jump
) == BRANCH_TYPE_ICC
)
1178 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1180 && (fpop_insn_p (target
)
1182 && get_attr_branch_type (target
) == BRANCH_TYPE_FCC
)))
1183 emit_insn_before (gen_nop (), target
);
1186 /* Insert a NOP between load instruction and atomic instruction. Insert
1187 a NOP at branch target if there is a load in delay slot and an atomic
1188 instruction at branch target. */
1190 && NONJUMP_INSN_P (insn
)
1191 && load_insn_p (insn
))
1193 if (jump
&& jump_to_label_p (jump
))
1195 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1196 if (target
&& atomic_insn_for_leon3_p (target
))
1197 emit_insn_before (gen_nop (), target
);
1200 next
= next_active_non_empty_insn (insn
);
1204 if (atomic_insn_for_leon3_p (next
))
1208 /* Look for a sequence that starts with a fdiv or fsqrt instruction and
1209 ends with another fdiv or fsqrt instruction with no dependencies on
1210 the former, along with an appropriate pattern in between. */
1211 if (sparc_fix_lost_divsqrt
1212 && NONJUMP_INSN_P (insn
)
1213 && div_sqrt_insn_p (insn
))
1219 const unsigned int dest_reg
= REGNO (SET_DEST (single_set (insn
)));
1221 next
= next_active_insn (insn
);
1225 for (after
= next
, i
= 0; i
< 4; i
++)
1227 /* Count floating-point operations. */
1228 if (i
!= 3 && fpop_insn_p (after
))
1230 /* If the insn uses the destination register of
1231 the div/sqrt, then it cannot be problematic. */
1232 if (insn_uses_reg_p (after
, dest_reg
))
1237 /* Count floating-point loads. */
1239 && (set
= single_set (after
)) != NULL_RTX
1240 && REG_P (SET_DEST (set
))
1241 && REGNO (SET_DEST (set
)) > 31)
1243 /* If the insn uses the destination register of
1244 the div/sqrt, then it cannot be problematic. */
1245 if (REGNO (SET_DEST (set
)) == dest_reg
)
1250 /* Check if this is a problematic sequence. */
1253 && div_sqrt_insn_p (after
))
1255 /* If this is the short version of the problematic
1256 sequence we add two NOPs in a row to also prevent
1257 the long version. */
1259 emit_insn_before (gen_nop (), next
);
1264 /* No need to scan past a second div/sqrt. */
1265 if (div_sqrt_insn_p (after
))
1268 /* Insert NOP before branch. */
1270 && (!NONJUMP_INSN_P (after
)
1271 || GET_CODE (PATTERN (after
)) == SEQUENCE
))
1277 after
= next_active_insn (after
);
1283 /* Look for either of these two sequences:
1286 1. store of word size or less (e.g. st / stb / sth / stf)
1287 2. any single instruction that is not a load or store
1288 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
1291 1. store of double word size (e.g. std / stdf)
1292 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
1294 && NONJUMP_INSN_P (insn
)
1295 && (set
= single_set (insn
)) != NULL_RTX
1296 && store_insn_p (insn
))
1298 /* Sequence B begins with a double-word store. */
1299 bool seq_b
= GET_MODE_SIZE (GET_MODE (SET_DEST (set
))) == 8;
1303 next
= next_active_non_empty_insn (insn
);
1307 for (after
= next
, i
= 0; i
< 2; i
++)
1309 /* If the insn is a branch, then it cannot be problematic. */
1310 if (!NONJUMP_INSN_P (after
)
1311 || GET_CODE (PATTERN (after
)) == SEQUENCE
)
1314 /* Sequence B is only two instructions long. */
1317 /* Add NOP if followed by a store. */
1318 if (store_insn_p (after
))
1321 /* Otherwise it is ok. */
1325 /* If the second instruction is a load or a store,
1326 then the sequence cannot be problematic. */
1329 if ((set
= single_set (after
)) != NULL_RTX
1330 && (MEM_P (SET_DEST (set
)) || mem_ref (SET_SRC (set
))))
1333 after
= next_active_non_empty_insn (after
);
1338 /* Add NOP if third instruction is a store. */
1340 && store_insn_p (after
))
1345 /* Look for a single-word load into an odd-numbered FP register. */
1346 else if (sparc_fix_at697f
1347 && NONJUMP_INSN_P (insn
)
1348 && (set
= single_set (insn
)) != NULL_RTX
1349 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1350 && mem_ref (SET_SRC (set
))
1351 && REG_P (SET_DEST (set
))
1352 && REGNO (SET_DEST (set
)) > 31
1353 && REGNO (SET_DEST (set
)) % 2 != 0)
1355 /* The wrong dependency is on the enclosing double register. */
1356 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
1357 unsigned int src1
, src2
, dest
;
1360 next
= next_active_insn (insn
);
1363 /* If the insn is a branch, then it cannot be problematic. */
1364 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1367 extract_insn (next
);
1368 code
= INSN_CODE (next
);
1372 case CODE_FOR_adddf3
:
1373 case CODE_FOR_subdf3
:
1374 case CODE_FOR_muldf3
:
1375 case CODE_FOR_divdf3
:
1376 dest
= REGNO (recog_data
.operand
[0]);
1377 src1
= REGNO (recog_data
.operand
[1]);
1378 src2
= REGNO (recog_data
.operand
[2]);
1383 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
1384 if ((src1
== x
|| src2
== x
)
1385 && (dest
== src1
|| dest
== src2
))
1392 FPOPd %fx, %fx, %fx */
1395 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
1400 case CODE_FOR_sqrtdf2
:
1401 dest
= REGNO (recog_data
.operand
[0]);
1402 src1
= REGNO (recog_data
.operand
[1]);
1406 if (src1
== x
&& dest
== src1
)
1415 /* Look for a single-word load into an integer register. */
1416 else if (sparc_fix_ut699
1417 && NONJUMP_INSN_P (insn
)
1418 && (set
= single_set (insn
)) != NULL_RTX
1419 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
1420 && (mem_ref (SET_SRC (set
)) != NULL_RTX
1421 || INSN_CODE (insn
) == CODE_FOR_movsi_pic_gotdata_op
)
1422 && REG_P (SET_DEST (set
))
1423 && REGNO (SET_DEST (set
)) < 32)
1425 /* There is no problem if the second memory access has a data
1426 dependency on the first single-cycle load. */
1427 rtx x
= SET_DEST (set
);
1429 next
= next_active_insn (insn
);
1432 /* If the insn is a branch, then it cannot be problematic. */
1433 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1436 /* Look for a second memory access to/from an integer register. */
1437 if ((set
= single_set (next
)) != NULL_RTX
)
1439 rtx src
= SET_SRC (set
);
1440 rtx dest
= SET_DEST (set
);
1443 /* LDD is affected. */
1444 if ((mem
= mem_ref (src
)) != NULL_RTX
1446 && REGNO (dest
) < 32
1447 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1450 /* STD is *not* affected. */
1451 else if (MEM_P (dest
)
1452 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1453 && (src
== CONST0_RTX (GET_MODE (dest
))
1456 && REGNO (src
) != REGNO (x
)))
1457 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1460 /* GOT accesses uses LD. */
1461 else if (INSN_CODE (next
) == CODE_FOR_movsi_pic_gotdata_op
1462 && !reg_mentioned_p (x
, XEXP (XEXP (src
, 0), 1)))
1467 /* Look for a single-word load/operation into an FP register. */
1468 else if (sparc_fix_ut699
1469 && NONJUMP_INSN_P (insn
)
1470 && (set
= single_set (insn
)) != NULL_RTX
1471 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1472 && REG_P (SET_DEST (set
))
1473 && REGNO (SET_DEST (set
)) > 31)
1475 /* Number of instructions in the problematic window. */
1476 const int n_insns
= 4;
1477 /* The problematic combination is with the sibling FP register. */
1478 const unsigned int x
= REGNO (SET_DEST (set
));
1479 const unsigned int y
= x
^ 1;
1483 next
= next_active_insn (insn
);
1486 /* If the insn is a branch, then it cannot be problematic. */
1487 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1490 /* Look for a second load/operation into the sibling FP register. */
1491 if (!((set
= single_set (next
)) != NULL_RTX
1492 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1493 && REG_P (SET_DEST (set
))
1494 && REGNO (SET_DEST (set
)) == y
))
1497 /* Look for a (possible) store from the FP register in the next N
1498 instructions, but bail out if it is again modified or if there
1499 is a store from the sibling FP register before this store. */
1500 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1504 after
= next_active_insn (after
);
1508 /* This is a branch with an empty delay slot. */
1509 if (!NONJUMP_INSN_P (after
))
1516 /* This is a branch with a filled delay slot. */
1517 else if (rtx_sequence
*seq
=
1518 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1523 after
= seq
->insn (1);
1525 /* This is a regular instruction. */
1529 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1531 const rtx src
= SET_SRC (set
);
1532 const rtx dest
= SET_DEST (set
);
1533 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1535 /* If the FP register is again modified before the store,
1536 then the store isn't affected. */
1538 && (REGNO (dest
) == x
1539 || (REGNO (dest
) == y
&& size
== 8)))
1542 if (MEM_P (dest
) && REG_P (src
))
1544 /* If there is a store from the sibling FP register
1545 before the store, then the store is not affected. */
1546 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1549 /* Otherwise, the store is affected. */
1550 if (REGNO (src
) == x
&& size
== 4)
1558 /* If we have a branch in the first M instructions, then we
1559 cannot see the (M+2)th instruction so we play safe. */
1560 if (branch_p
&& i
<= (n_insns
- 2))
1569 next
= NEXT_INSN (insn
);
1572 emit_insn_before (gen_nop (), next
);
1580 const pass_data pass_data_work_around_errata
=
1582 RTL_PASS
, /* type */
1583 "errata", /* name */
1584 OPTGROUP_NONE
, /* optinfo_flags */
1585 TV_MACH_DEP
, /* tv_id */
1586 0, /* properties_required */
1587 0, /* properties_provided */
1588 0, /* properties_destroyed */
1589 0, /* todo_flags_start */
1590 0, /* todo_flags_finish */
1593 class pass_work_around_errata
: public rtl_opt_pass
1596 pass_work_around_errata(gcc::context
*ctxt
)
1597 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1600 /* opt_pass methods: */
1601 virtual bool gate (function
*)
1603 return sparc_fix_at697f
1604 || sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
1605 || sparc_fix_b2bst
|| sparc_fix_lost_divsqrt
;
1608 virtual unsigned int execute (function
*)
1610 return sparc_do_work_around_errata ();
1613 }; // class pass_work_around_errata
1618 make_pass_work_around_errata (gcc::context
*ctxt
)
1620 return new pass_work_around_errata (ctxt
);
1623 /* Helpers for TARGET_DEBUG_OPTIONS. */
1625 dump_target_flag_bits (const int flags
)
1627 if (flags
& MASK_64BIT
)
1628 fprintf (stderr
, "64BIT ");
1629 if (flags
& MASK_APP_REGS
)
1630 fprintf (stderr
, "APP_REGS ");
1631 if (flags
& MASK_FASTER_STRUCTS
)
1632 fprintf (stderr
, "FASTER_STRUCTS ");
1633 if (flags
& MASK_FLAT
)
1634 fprintf (stderr
, "FLAT ");
1635 if (flags
& MASK_FMAF
)
1636 fprintf (stderr
, "FMAF ");
1637 if (flags
& MASK_FSMULD
)
1638 fprintf (stderr
, "FSMULD ");
1639 if (flags
& MASK_FPU
)
1640 fprintf (stderr
, "FPU ");
1641 if (flags
& MASK_HARD_QUAD
)
1642 fprintf (stderr
, "HARD_QUAD ");
1643 if (flags
& MASK_POPC
)
1644 fprintf (stderr
, "POPC ");
1645 if (flags
& MASK_PTR64
)
1646 fprintf (stderr
, "PTR64 ");
1647 if (flags
& MASK_STACK_BIAS
)
1648 fprintf (stderr
, "STACK_BIAS ");
1649 if (flags
& MASK_UNALIGNED_DOUBLES
)
1650 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1651 if (flags
& MASK_V8PLUS
)
1652 fprintf (stderr
, "V8PLUS ");
1653 if (flags
& MASK_VIS
)
1654 fprintf (stderr
, "VIS ");
1655 if (flags
& MASK_VIS2
)
1656 fprintf (stderr
, "VIS2 ");
1657 if (flags
& MASK_VIS3
)
1658 fprintf (stderr
, "VIS3 ");
1659 if (flags
& MASK_VIS4
)
1660 fprintf (stderr
, "VIS4 ");
1661 if (flags
& MASK_VIS4B
)
1662 fprintf (stderr
, "VIS4B ");
1663 if (flags
& MASK_CBCOND
)
1664 fprintf (stderr
, "CBCOND ");
1665 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1666 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1667 if (flags
& MASK_LEON
)
1668 fprintf (stderr
, "LEON ");
1669 if (flags
& MASK_LEON3
)
1670 fprintf (stderr
, "LEON3 ");
1671 if (flags
& MASK_SPARCLET
)
1672 fprintf (stderr
, "SPARCLET ");
1673 if (flags
& MASK_SPARCLITE
)
1674 fprintf (stderr
, "SPARCLITE ");
1675 if (flags
& MASK_V8
)
1676 fprintf (stderr
, "V8 ");
1677 if (flags
& MASK_V9
)
1678 fprintf (stderr
, "V9 ");
1682 dump_target_flags (const char *prefix
, const int flags
)
1684 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1685 dump_target_flag_bits (flags
);
1686 fprintf(stderr
, "]\n");
1689 /* Validate and override various options, and do some machine dependent
1693 sparc_option_override (void)
1695 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1696 static struct cpu_default
{
1698 const enum sparc_processor_type processor
;
1699 } const cpu_default
[] = {
1700 /* There must be one entry here for each TARGET_CPU value. */
1701 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1702 { TARGET_CPU_v8
, PROCESSOR_V8
},
1703 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1704 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1705 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1706 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1707 { TARGET_CPU_leon5
, PROCESSOR_LEON5
},
1708 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1709 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1710 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1711 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1712 { TARGET_CPU_v9
, PROCESSOR_V9
},
1713 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1714 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1715 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1716 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1717 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1718 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1719 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1720 { TARGET_CPU_m8
, PROCESSOR_M8
},
1721 { -1, PROCESSOR_V7
}
1723 const struct cpu_default
*def
;
1724 /* Table of values for -m{cpu,tune}=. This must match the order of
1725 the enum processor_type in sparc-opts.h. */
1726 static struct cpu_table
{
1727 const char *const name
;
1730 } const cpu_table
[] = {
1731 { "v7", MASK_ISA
, 0 },
1732 { "cypress", MASK_ISA
, 0 },
1733 { "v8", MASK_ISA
, MASK_V8
},
1734 /* TI TMS390Z55 supersparc */
1735 { "supersparc", MASK_ISA
, MASK_V8
},
1736 { "hypersparc", MASK_ISA
, MASK_V8
},
1737 { "leon", MASK_ISA
|MASK_FSMULD
, MASK_V8
|MASK_LEON
},
1738 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
},
1739 { "leon5", MASK_ISA
, MASK_V8
|MASK_LEON3
},
1740 { "leon3v7", MASK_ISA
, MASK_LEON3
},
1741 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1742 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1743 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1744 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1745 { "f934", MASK_ISA
, MASK_SPARCLITE
},
1746 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1747 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1748 /* TEMIC sparclet */
1749 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1750 { "v9", MASK_ISA
, MASK_V9
},
1751 /* UltraSPARC I, II, IIi */
1752 { "ultrasparc", MASK_ISA
,
1753 /* Although insns using %y are deprecated, it is a clear win. */
1754 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1755 /* UltraSPARC III */
1756 /* ??? Check if %y issue still holds true. */
1757 { "ultrasparc3", MASK_ISA
,
1758 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1760 { "niagara", MASK_ISA
,
1761 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1763 { "niagara2", MASK_ISA
,
1764 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1766 { "niagara3", MASK_ISA
,
1767 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
},
1769 { "niagara4", MASK_ISA
,
1770 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1772 { "niagara7", MASK_ISA
,
1773 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
},
1776 MASK_V9
|MASK_POPC
|MASK_VIS4B
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
}
1778 const struct cpu_table
*cpu
;
1781 if (sparc_debug_string
!= NULL
)
1786 p
= ASTRDUP (sparc_debug_string
);
1787 while ((q
= strtok (p
, ",")) != NULL
)
1801 if (! strcmp (q
, "all"))
1802 mask
= MASK_DEBUG_ALL
;
1803 else if (! strcmp (q
, "options"))
1804 mask
= MASK_DEBUG_OPTIONS
;
1806 error ("unknown %<-mdebug-%s%> switch", q
);
1809 sparc_debug
&= ~mask
;
1811 sparc_debug
|= mask
;
1815 /* Enable the FsMULd instruction by default if not explicitly specified by
1816 the user. It may be later disabled by the CPU (explicitly or not). */
1817 if (TARGET_FPU
&& !(target_flags_explicit
& MASK_FSMULD
))
1818 target_flags
|= MASK_FSMULD
;
1820 if (TARGET_DEBUG_OPTIONS
)
1822 dump_target_flags("Initial target_flags", target_flags
);
1823 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1826 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1827 SUBTARGET_OVERRIDE_OPTIONS
;
1830 #ifndef SPARC_BI_ARCH
1831 /* Check for unsupported architecture size. */
1832 if (!TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1833 error ("%s is not supported by this configuration",
1834 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1837 /* We force all 64bit archs to use 128 bit long double */
1838 if (TARGET_ARCH64
&& !TARGET_LONG_DOUBLE_128
)
1840 error ("%<-mlong-double-64%> not allowed with %<-m64%>");
1841 target_flags
|= MASK_LONG_DOUBLE_128
;
1844 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1845 for (i
= 8; i
< 16; i
++)
1846 if (!call_used_regs
[i
])
1848 error ("%<-fcall-saved-REG%> is not supported for out registers");
1849 call_used_regs
[i
] = 1;
1852 /* Set the default CPU if no -mcpu option was specified. */
1853 if (!OPTION_SET_P (sparc_cpu_and_features
))
1855 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1856 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1858 gcc_assert (def
->cpu
!= -1);
1859 sparc_cpu_and_features
= def
->processor
;
1862 /* Set the default CPU if no -mtune option was specified. */
1863 if (!OPTION_SET_P (sparc_cpu
))
1864 sparc_cpu
= sparc_cpu_and_features
;
1866 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1868 if (TARGET_DEBUG_OPTIONS
)
1870 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1871 dump_target_flags ("cpu->disable", cpu
->disable
);
1872 dump_target_flags ("cpu->enable", cpu
->enable
);
1875 target_flags
&= ~cpu
->disable
;
1876 target_flags
|= (cpu
->enable
1877 #ifndef HAVE_AS_FMAF_HPC_VIS3
1878 & ~(MASK_FMAF
| MASK_VIS3
)
1880 #ifndef HAVE_AS_SPARC4
1883 #ifndef HAVE_AS_SPARC5_VIS4
1884 & ~(MASK_VIS4
| MASK_SUBXC
)
1886 #ifndef HAVE_AS_SPARC6
1889 #ifndef HAVE_AS_LEON
1890 & ~(MASK_LEON
| MASK_LEON3
)
1892 & ~(target_flags_explicit
& MASK_FEATURES
)
1895 /* FsMULd is a V8 instruction. */
1896 if (!TARGET_V8
&& !TARGET_V9
)
1897 target_flags
&= ~MASK_FSMULD
;
1899 /* -mvis2 implies -mvis. */
1901 target_flags
|= MASK_VIS
;
1903 /* -mvis3 implies -mvis2 and -mvis. */
1905 target_flags
|= MASK_VIS2
| MASK_VIS
;
1907 /* -mvis4 implies -mvis3, -mvis2 and -mvis. */
1909 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1911 /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
1913 target_flags
|= MASK_VIS4
| MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1915 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
1918 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1919 | MASK_VIS4B
| MASK_FMAF
| MASK_FSMULD
);
1921 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1922 are available; -m64 also implies v9. */
1923 if (TARGET_VIS
|| TARGET_ARCH64
)
1925 target_flags
|= MASK_V9
;
1926 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1929 /* -mvis also implies -mv8plus on 32-bit. */
1930 if (TARGET_VIS
&& !TARGET_ARCH64
)
1931 target_flags
|= MASK_V8PLUS
;
1933 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
1934 if (TARGET_V9
&& TARGET_ARCH32
)
1935 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1937 /* V8PLUS requires V9 and makes no sense in 64-bit mode. */
1938 if (!TARGET_V9
|| TARGET_ARCH64
)
1939 target_flags
&= ~MASK_V8PLUS
;
1941 /* Don't use stack biasing in 32-bit mode. */
1943 target_flags
&= ~MASK_STACK_BIAS
;
1945 /* Use LRA instead of reload, unless otherwise instructed. */
1946 if (!(target_flags_explicit
& MASK_LRA
))
1947 target_flags
|= MASK_LRA
;
1949 /* Enable applicable errata workarounds for LEON3FT. */
1950 if (sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
)
1952 sparc_fix_b2bst
= 1;
1953 sparc_fix_lost_divsqrt
= 1;
1956 /* Disable FsMULd for the UT699 since it doesn't work correctly. */
1957 if (sparc_fix_ut699
)
1958 target_flags
&= ~MASK_FSMULD
;
1960 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1961 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1962 target_flags
|= MASK_LONG_DOUBLE_128
;
1965 if (TARGET_DEBUG_OPTIONS
)
1966 dump_target_flags ("Final target_flags", target_flags
);
1968 /* Set the code model if no -mcmodel option was specified. */
1969 if (OPTION_SET_P (sparc_code_model
))
1972 error ("%<-mcmodel=%> is not supported in 32-bit mode");
1977 sparc_code_model
= CM_32
;
1979 sparc_code_model
= SPARC_DEFAULT_CMODEL
;
1982 /* Set the memory model if no -mmemory-model option was specified. */
1983 if (!OPTION_SET_P (sparc_memory_model
))
1985 /* Choose the memory model for the operating system. */
1986 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1987 if (os_default
!= SMM_DEFAULT
)
1988 sparc_memory_model
= os_default
;
1989 /* Choose the most relaxed model for the processor. */
1991 sparc_memory_model
= SMM_RMO
;
1992 else if (TARGET_LEON3
)
1993 sparc_memory_model
= SMM_TSO
;
1994 else if (TARGET_LEON
)
1995 sparc_memory_model
= SMM_SC
;
1997 sparc_memory_model
= SMM_PSO
;
1999 sparc_memory_model
= SMM_SC
;
2002 /* Supply a default value for align_functions. */
2003 if (flag_align_functions
&& !str_align_functions
)
2005 if (sparc_cpu
== PROCESSOR_ULTRASPARC
2006 || sparc_cpu
== PROCESSOR_ULTRASPARC3
2007 || sparc_cpu
== PROCESSOR_NIAGARA
2008 || sparc_cpu
== PROCESSOR_NIAGARA2
2009 || sparc_cpu
== PROCESSOR_NIAGARA3
2010 || sparc_cpu
== PROCESSOR_NIAGARA4
)
2011 str_align_functions
= "32";
2012 else if (sparc_cpu
== PROCESSOR_NIAGARA7
2013 || sparc_cpu
== PROCESSOR_M8
)
2014 str_align_functions
= "64";
2017 /* Validate PCC_STRUCT_RETURN. */
2018 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
2019 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
2021 /* Only use .uaxword when compiling for a 64-bit target. */
2023 targetm
.asm_out
.unaligned_op
.di
= NULL
;
2025 /* Set the processor costs. */
2029 case PROCESSOR_CYPRESS
:
2030 sparc_costs
= &cypress_costs
;
2033 case PROCESSOR_SPARCLITE
:
2034 case PROCESSOR_SUPERSPARC
:
2035 sparc_costs
= &supersparc_costs
;
2037 case PROCESSOR_F930
:
2038 case PROCESSOR_F934
:
2039 case PROCESSOR_HYPERSPARC
:
2040 case PROCESSOR_SPARCLITE86X
:
2041 sparc_costs
= &hypersparc_costs
;
2043 case PROCESSOR_LEON
:
2044 sparc_costs
= &leon_costs
;
2046 case PROCESSOR_LEON3
:
2047 case PROCESSOR_LEON3V7
:
2048 sparc_costs
= &leon3_costs
;
2050 case PROCESSOR_LEON5
:
2051 sparc_costs
= &leon5_costs
;
2053 case PROCESSOR_SPARCLET
:
2054 case PROCESSOR_TSC701
:
2055 sparc_costs
= &sparclet_costs
;
2058 case PROCESSOR_ULTRASPARC
:
2059 sparc_costs
= &ultrasparc_costs
;
2061 case PROCESSOR_ULTRASPARC3
:
2062 sparc_costs
= &ultrasparc3_costs
;
2064 case PROCESSOR_NIAGARA
:
2065 sparc_costs
= &niagara_costs
;
2067 case PROCESSOR_NIAGARA2
:
2068 sparc_costs
= &niagara2_costs
;
2070 case PROCESSOR_NIAGARA3
:
2071 sparc_costs
= &niagara3_costs
;
2073 case PROCESSOR_NIAGARA4
:
2074 sparc_costs
= &niagara4_costs
;
2076 case PROCESSOR_NIAGARA7
:
2077 sparc_costs
= &niagara7_costs
;
2080 sparc_costs
= &m8_costs
;
2082 case PROCESSOR_NATIVE
:
2086 /* param_simultaneous_prefetches is the number of prefetches that
2087 can run at the same time. More important, it is the threshold
2088 defining when additional prefetches will be dropped by the
2091 The UltraSPARC-III features a documented prefetch queue with a
2092 size of 8. Additional prefetches issued in the cpu are
2095 Niagara processors are different. In these processors prefetches
2096 are handled much like regular loads. The L1 miss buffer is 32
2097 entries, but prefetches start getting affected when 30 entries
2098 become occupied. That occupation could be a mix of regular loads
2099 and prefetches though. And that buffer is shared by all threads.
2100 Once the threshold is reached, if the core is running a single
2101 thread the prefetch will retry. If more than one thread is
2102 running, the prefetch will be dropped.
2104 All this makes it very difficult to determine how many
2105 simultaneous prefetches can be issued simultaneously, even in a
2106 single-threaded program. Experimental results show that setting
2107 this parameter to 32 works well when the number of threads is not
2109 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
2110 param_simultaneous_prefetches
,
2111 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2112 || sparc_cpu
== PROCESSOR_NIAGARA
2113 || sparc_cpu
== PROCESSOR_NIAGARA2
2114 || sparc_cpu
== PROCESSOR_NIAGARA3
2115 || sparc_cpu
== PROCESSOR_NIAGARA4
)
2117 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
2118 ? 8 : ((sparc_cpu
== PROCESSOR_NIAGARA7
2119 || sparc_cpu
== PROCESSOR_M8
)
2122 /* param_l1_cache_line_size is the size of the L1 cache line, in
2125 The Oracle SPARC Architecture (previously the UltraSPARC
2126 Architecture) specification states that when a PREFETCH[A]
2127 instruction is executed an implementation-specific amount of data
2128 is prefetched, and that it is at least 64 bytes long (aligned to
2131 However, this is not correct. The M7 (and implementations prior
2132 to that) does not guarantee a 64B prefetch into a cache if the
2133 line size is smaller. A single cache line is all that is ever
2134 prefetched. So for the M7, where the L1D$ has 32B lines and the
2135 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
2136 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
2137 is a read_n prefetch, which is the only type which allocates to
2139 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
2140 param_l1_cache_line_size
,
2141 (sparc_cpu
== PROCESSOR_M8
? 64 : 32));
2143 /* param_l1_cache_size is the size of the L1D$ (most SPARC chips use
2144 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
2145 Niagara processors feature a L1D$ of 16KB. */
2146 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
2147 param_l1_cache_size
,
2148 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2149 || sparc_cpu
== PROCESSOR_ULTRASPARC3
2150 || sparc_cpu
== PROCESSOR_NIAGARA
2151 || sparc_cpu
== PROCESSOR_NIAGARA2
2152 || sparc_cpu
== PROCESSOR_NIAGARA3
2153 || sparc_cpu
== PROCESSOR_NIAGARA4
2154 || sparc_cpu
== PROCESSOR_NIAGARA7
2155 || sparc_cpu
== PROCESSOR_M8
)
2158 /* param_l2_cache_size is the size fo the L2 in kilobytes. Note
2159 that 512 is the default in params.def. */
2160 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
2161 param_l2_cache_size
,
2162 ((sparc_cpu
== PROCESSOR_NIAGARA4
2163 || sparc_cpu
== PROCESSOR_M8
)
2164 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
2168 /* Disable save slot sharing for call-clobbered registers by default.
2169 The IRA sharing algorithm works on single registers only and this
2170 pessimizes for double floating-point registers. */
2171 if (!OPTION_SET_P (flag_ira_share_save_slots
))
2172 flag_ira_share_save_slots
= 0;
2174 /* Only enable REE by default in 64-bit mode where it helps to eliminate
2175 redundant 32-to-64-bit extensions. */
2176 if (!OPTION_SET_P (flag_ree
) && TARGET_ARCH32
)
2179 /* Do various machine dependent initializations. */
2180 sparc_init_modes ();
2182 /* Set up function hooks. */
2183 init_machine_status
= sparc_init_machine_status
;
2186 /* Miscellaneous utilities. */
2188 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
2189 or branch on register contents instructions. */
2192 v9_regcmp_p (enum rtx_code code
)
2194 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
2195 || code
== LE
|| code
== GT
);
2198 /* Nonzero if OP is a floating point constant which can
2199 be loaded into an integer register using a single
2200 sethi instruction. */
2205 if (GET_CODE (op
) == CONST_DOUBLE
)
2209 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2210 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
2216 /* Nonzero if OP is a floating point constant which can
2217 be loaded into an integer register using a single
2223 if (GET_CODE (op
) == CONST_DOUBLE
)
2227 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2228 return SPARC_SIMM13_P (i
);
2234 /* Nonzero if OP is a floating point constant which can
2235 be loaded into an integer register using a high/losum
2236 instruction sequence. */
2239 fp_high_losum_p (rtx op
)
2241 /* The constraints calling this should only be in
2242 SFmode move insns, so any constant which cannot
2243 be moved using a single insn will do. */
2244 if (GET_CODE (op
) == CONST_DOUBLE
)
2248 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2249 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
2255 /* Return true if the address of LABEL can be loaded by means of the
2256 mov{si,di}_pic_label_ref patterns in PIC mode. */
2259 can_use_mov_pic_label_ref (rtx label
)
2261 /* VxWorks does not impose a fixed gap between segments; the run-time
2262 gap can be different from the object-file gap. We therefore can't
2263 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
2264 are absolutely sure that X is in the same segment as the GOT.
2265 Unfortunately, the flexibility of linker scripts means that we
2266 can't be sure of that in general, so assume that GOT-relative
2267 accesses are never valid on VxWorks. */
2268 if (TARGET_VXWORKS_RTP
)
2271 /* Similarly, if the label is non-local, it might end up being placed
2272 in a different section than the current one; now mov_pic_label_ref
2273 requires the label and the code to be in the same section. */
2274 if (LABEL_REF_NONLOCAL_P (label
))
2277 /* Finally, if we are reordering basic blocks and partition into hot
2278 and cold sections, this might happen for any label. */
2279 if (flag_reorder_blocks_and_partition
)
2285 /* Expand a move instruction. Return true if all work is done. */
2288 sparc_expand_move (machine_mode mode
, rtx
*operands
)
2290 /* Handle sets of MEM first. */
2291 if (GET_CODE (operands
[0]) == MEM
)
2293 /* 0 is a register (or a pair of registers) on SPARC. */
2294 if (register_or_zero_operand (operands
[1], mode
))
2297 if (!reload_in_progress
)
2299 operands
[0] = validize_mem (operands
[0]);
2300 operands
[1] = force_reg (mode
, operands
[1]);
2304 /* Fix up TLS cases. */
2306 && CONSTANT_P (operands
[1])
2307 && sparc_tls_referenced_p (operands
[1]))
2309 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
2313 /* Fix up PIC cases. */
2314 if (flag_pic
&& CONSTANT_P (operands
[1]))
2316 if (pic_address_needs_scratch (operands
[1]))
2317 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
2319 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
2320 if ((GET_CODE (operands
[1]) == LABEL_REF
2321 && can_use_mov_pic_label_ref (operands
[1]))
2322 || (GET_CODE (operands
[1]) == CONST
2323 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2324 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
2325 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == CONST_INT
2326 && can_use_mov_pic_label_ref (XEXP (XEXP (operands
[1], 0), 0))))
2330 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
2336 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
2341 if (symbolic_operand (operands
[1], mode
))
2344 = sparc_legitimize_pic_address (operands
[1],
2346 ? operands
[0] : NULL_RTX
);
2351 /* If we are trying to toss an integer constant into FP registers,
2352 or loading a FP or vector constant, force it into memory. */
2353 if (CONSTANT_P (operands
[1])
2354 && REG_P (operands
[0])
2355 && (SPARC_FP_REG_P (REGNO (operands
[0]))
2356 || SCALAR_FLOAT_MODE_P (mode
)
2357 || VECTOR_MODE_P (mode
)))
2359 /* emit_group_store will send such bogosity to us when it is
2360 not storing directly into memory. So fix this up to avoid
2361 crashes in output_constant_pool. */
2362 if (operands
[1] == const0_rtx
)
2363 operands
[1] = CONST0_RTX (mode
);
2365 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
2366 always other regs. */
2367 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
2368 && (const_zero_operand (operands
[1], mode
)
2369 || const_all_ones_operand (operands
[1], mode
)))
2372 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
2373 /* We are able to build any SF constant in integer registers
2374 with at most 2 instructions. */
2376 /* And any DF constant in integer registers if needed. */
2377 || (mode
== DFmode
&& !can_create_pseudo_p ())))
2380 operands
[1] = force_const_mem (mode
, operands
[1]);
2381 if (!reload_in_progress
)
2382 operands
[1] = validize_mem (operands
[1]);
2386 /* Accept non-constants and valid constants unmodified. */
2387 if (!CONSTANT_P (operands
[1])
2388 || GET_CODE (operands
[1]) == HIGH
2389 || input_operand (operands
[1], mode
))
2395 /* All QImode constants require only one insn, so proceed. */
2400 sparc_emit_set_const32 (operands
[0], operands
[1]);
2404 /* input_operand should have filtered out 32-bit mode. */
2405 sparc_emit_set_const64 (operands
[0], operands
[1]);
2411 /* TImode isn't available in 32-bit mode. */
2412 split_double (operands
[1], &high
, &low
);
2413 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
2415 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
2427 /* Load OP1, a 32-bit constant, into OP0, a register.
2428 We know it can't be done in one insn when we get
2429 here, the move expander guarantees this. */
2432 sparc_emit_set_const32 (rtx op0
, rtx op1
)
2434 machine_mode mode
= GET_MODE (op0
);
2437 if (can_create_pseudo_p ())
2438 temp
= gen_reg_rtx (mode
);
2440 if (GET_CODE (op1
) == CONST_INT
)
2442 gcc_assert (!small_int_operand (op1
, mode
)
2443 && !const_high_operand (op1
, mode
));
2445 /* Emit them as real moves instead of a HIGH/LO_SUM,
2446 this way CSE can see everything and reuse intermediate
2447 values if it wants. */
2448 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
2449 & ~(HOST_WIDE_INT
) 0x3ff)));
2451 emit_insn (gen_rtx_SET (op0
,
2452 gen_rtx_IOR (mode
, temp
,
2453 GEN_INT (INTVAL (op1
) & 0x3ff))));
2457 /* A symbol, emit in the traditional way. */
2458 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
2459 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
2463 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
2464 If TEMP is nonzero, we are forbidden to use any other scratch
2465 registers. Otherwise, we are allowed to generate them as needed.
2467 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
2468 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
2471 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
2473 rtx cst
, temp1
, temp2
, temp3
, temp4
, temp5
;
2476 /* Deal with too large offsets. */
2477 if (GET_CODE (op1
) == CONST
2478 && GET_CODE (XEXP (op1
, 0)) == PLUS
2479 && CONST_INT_P (cst
= XEXP (XEXP (op1
, 0), 1))
2480 && trunc_int_for_mode (INTVAL (cst
), SImode
) != INTVAL (cst
))
2483 temp1
= gen_reg_rtx (DImode
);
2484 temp2
= gen_reg_rtx (DImode
);
2485 sparc_emit_set_const64 (temp2
, cst
);
2486 sparc_emit_set_symbolic_const64 (temp1
, XEXP (XEXP (op1
, 0), 0),
2488 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp1
, temp2
)));
2492 if (temp
&& GET_MODE (temp
) == TImode
)
2495 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2498 /* SPARC-V9 code model support. */
2499 switch (sparc_code_model
)
2502 /* The range spanned by all instructions in the object is less
2503 than 2^31 bytes (2GB) and the distance from any instruction
2504 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2505 than 2^31 bytes (2GB).
2507 The executable must be in the low 4TB of the virtual address
2510 sethi %hi(symbol), %temp1
2511 or %temp1, %lo(symbol), %reg */
2513 temp1
= temp
; /* op0 is allowed. */
2515 temp1
= gen_reg_rtx (DImode
);
2517 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2518 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2522 /* The range spanned by all instructions in the object is less
2523 than 2^31 bytes (2GB) and the distance from any instruction
2524 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2525 than 2^31 bytes (2GB).
2527 The executable must be in the low 16TB of the virtual address
2530 sethi %h44(symbol), %temp1
2531 or %temp1, %m44(symbol), %temp2
2532 sllx %temp2, 12, %temp3
2533 or %temp3, %l44(symbol), %reg */
2538 temp3
= temp
; /* op0 is allowed. */
2542 temp1
= gen_reg_rtx (DImode
);
2543 temp2
= gen_reg_rtx (DImode
);
2544 temp3
= gen_reg_rtx (DImode
);
2547 emit_insn (gen_seth44 (temp1
, op1
));
2548 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2549 emit_insn (gen_rtx_SET (temp3
,
2550 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2551 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2555 /* The range spanned by all instructions in the object is less
2556 than 2^31 bytes (2GB) and the distance from any instruction
2557 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2558 than 2^31 bytes (2GB).
2560 The executable can be placed anywhere in the virtual address
2563 sethi %hh(symbol), %temp1
2564 sethi %lm(symbol), %temp2
2565 or %temp1, %hm(symbol), %temp3
2566 sllx %temp3, 32, %temp4
2567 or %temp4, %temp2, %temp5
2568 or %temp5, %lo(symbol), %reg */
2571 /* It is possible that one of the registers we got for operands[2]
2572 might coincide with that of operands[0] (which is why we made
2573 it TImode). Pick the other one to use as our scratch. */
2574 if (rtx_equal_p (temp
, op0
))
2576 gcc_assert (ti_temp
);
2577 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2580 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2587 temp1
= gen_reg_rtx (DImode
);
2588 temp2
= gen_reg_rtx (DImode
);
2589 temp3
= gen_reg_rtx (DImode
);
2590 temp4
= gen_reg_rtx (DImode
);
2591 temp5
= gen_reg_rtx (DImode
);
2594 emit_insn (gen_sethh (temp1
, op1
));
2595 emit_insn (gen_setlm (temp2
, op1
));
2596 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2597 emit_insn (gen_rtx_SET (temp4
,
2598 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2599 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2600 emit_insn (gen_setlo (op0
, temp5
, op1
));
2604 /* Old old old backwards compatibility kruft here.
2605 Essentially it is MEDLOW with a fixed 64-bit
2606 virtual base added to all data segment addresses.
2607 Text-segment stuff is computed like MEDANY, we can't
2608 reuse the code above because the relocation knobs
2611 Data segment: sethi %hi(symbol), %temp1
2612 add %temp1, EMBMEDANY_BASE_REG, %temp2
2613 or %temp2, %lo(symbol), %reg */
2614 if (data_segment_operand (op1
, GET_MODE (op1
)))
2618 temp1
= temp
; /* op0 is allowed. */
2623 temp1
= gen_reg_rtx (DImode
);
2624 temp2
= gen_reg_rtx (DImode
);
2627 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2628 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2629 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2632 /* Text segment: sethi %uhi(symbol), %temp1
2633 sethi %hi(symbol), %temp2
2634 or %temp1, %ulo(symbol), %temp3
2635 sllx %temp3, 32, %temp4
2636 or %temp4, %temp2, %temp5
2637 or %temp5, %lo(symbol), %reg */
2642 /* It is possible that one of the registers we got for operands[2]
2643 might coincide with that of operands[0] (which is why we made
2644 it TImode). Pick the other one to use as our scratch. */
2645 if (rtx_equal_p (temp
, op0
))
2647 gcc_assert (ti_temp
);
2648 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2651 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2658 temp1
= gen_reg_rtx (DImode
);
2659 temp2
= gen_reg_rtx (DImode
);
2660 temp3
= gen_reg_rtx (DImode
);
2661 temp4
= gen_reg_rtx (DImode
);
2662 temp5
= gen_reg_rtx (DImode
);
2665 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2666 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2667 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2668 emit_insn (gen_rtx_SET (temp4
,
2669 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2670 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2671 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2680 /* These avoid problems when cross compiling. If we do not
2681 go through all this hair then the optimizer will see
2682 invalid REG_EQUAL notes or in some cases none at all. */
2683 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2684 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2685 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2686 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2688 /* The optimizer is not to assume anything about exactly
2689 which bits are set for a HIGH, they are unspecified.
2690 Unfortunately this leads to many missed optimizations
2691 during CSE. We mask out the non-HIGH bits, and matches
2692 a plain movdi, to alleviate this problem. */
2694 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2696 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2700 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2702 return gen_rtx_SET (dest
, GEN_INT (val
));
2706 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2708 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2712 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2714 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2717 /* Worker routines for 64-bit constant formation on arch64.
2718 One of the key things to be doing in these emissions is
2719 to create as many temp REGs as possible. This makes it
2720 possible for half-built constants to be used later when
2721 such values are similar to something required later on.
2722 Without doing this, the optimizer cannot see such
2725 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2726 unsigned HOST_WIDE_INT
, int);
2729 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2730 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2732 unsigned HOST_WIDE_INT high_bits
;
2735 high_bits
= (~low_bits
) & 0xffffffff;
2737 high_bits
= low_bits
;
2739 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2742 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2746 /* If we are XOR'ing with -1, then we should emit a one's complement
2747 instead. This way the combiner will notice logical operations
2748 such as ANDN later on and substitute. */
2749 if ((low_bits
& 0x3ff) == 0x3ff)
2751 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2755 emit_insn (gen_rtx_SET (op0
,
2756 gen_safe_XOR64 (temp
,
2757 (-(HOST_WIDE_INT
)0x400
2758 | (low_bits
& 0x3ff)))));
2763 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2764 unsigned HOST_WIDE_INT
, int);
2767 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2768 unsigned HOST_WIDE_INT high_bits
,
2769 unsigned HOST_WIDE_INT low_immediate
,
2774 if ((high_bits
& 0xfffffc00) != 0)
2776 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2777 if ((high_bits
& ~0xfffffc00) != 0)
2778 emit_insn (gen_rtx_SET (op0
,
2779 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2785 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2789 /* Now shift it up into place. */
2790 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2791 GEN_INT (shift_count
))));
2793 /* If there is a low immediate part piece, finish up by
2794 putting that in as well. */
2795 if (low_immediate
!= 0)
2796 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2799 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2800 unsigned HOST_WIDE_INT
);
2802 /* Full 64-bit constant decomposition. Even though this is the
2803 'worst' case, we still optimize a few things away. */
2805 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2806 unsigned HOST_WIDE_INT high_bits
,
2807 unsigned HOST_WIDE_INT low_bits
)
2811 if (can_create_pseudo_p ())
2812 sub_temp
= gen_reg_rtx (DImode
);
2814 if ((high_bits
& 0xfffffc00) != 0)
2816 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2817 if ((high_bits
& ~0xfffffc00) != 0)
2818 emit_insn (gen_rtx_SET (sub_temp
,
2819 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2825 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2829 if (can_create_pseudo_p ())
2831 rtx temp2
= gen_reg_rtx (DImode
);
2832 rtx temp3
= gen_reg_rtx (DImode
);
2833 rtx temp4
= gen_reg_rtx (DImode
);
2835 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2838 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2839 if ((low_bits
& ~0xfffffc00) != 0)
2841 emit_insn (gen_rtx_SET (temp3
,
2842 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2843 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2847 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2852 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2853 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2854 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2857 /* We are in the middle of reload, so this is really
2858 painful. However we do still make an attempt to
2859 avoid emitting truly stupid code. */
2860 if (low1
!= const0_rtx
)
2862 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2863 GEN_INT (to_shift
))));
2864 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2872 if (low2
!= const0_rtx
)
2874 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2875 GEN_INT (to_shift
))));
2876 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2884 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2885 GEN_INT (to_shift
))));
2886 if (low3
!= const0_rtx
)
2887 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2892 /* Analyze a 64-bit constant for certain properties. */
2893 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2894 unsigned HOST_WIDE_INT
,
2895 int *, int *, int *);
2898 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2899 unsigned HOST_WIDE_INT low_bits
,
2900 int *hbsp
, int *lbsp
, int *abbasp
)
2902 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2905 lowest_bit_set
= highest_bit_set
= -1;
2909 if ((lowest_bit_set
== -1)
2910 && ((low_bits
>> i
) & 1))
2912 if ((highest_bit_set
== -1)
2913 && ((high_bits
>> (32 - i
- 1)) & 1))
2914 highest_bit_set
= (64 - i
- 1);
2917 && ((highest_bit_set
== -1)
2918 || (lowest_bit_set
== -1)));
2924 if ((lowest_bit_set
== -1)
2925 && ((high_bits
>> i
) & 1))
2926 lowest_bit_set
= i
+ 32;
2927 if ((highest_bit_set
== -1)
2928 && ((low_bits
>> (32 - i
- 1)) & 1))
2929 highest_bit_set
= 32 - i
- 1;
2932 && ((highest_bit_set
== -1)
2933 || (lowest_bit_set
== -1)));
2935 /* If there are no bits set this should have gone out
2936 as one instruction! */
2937 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2938 all_bits_between_are_set
= 1;
2939 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2943 if ((low_bits
& (1 << i
)) != 0)
2948 if ((high_bits
& (1 << (i
- 32))) != 0)
2951 all_bits_between_are_set
= 0;
2954 *hbsp
= highest_bit_set
;
2955 *lbsp
= lowest_bit_set
;
2956 *abbasp
= all_bits_between_are_set
;
2959 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2962 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2963 unsigned HOST_WIDE_INT low_bits
)
2965 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2968 || high_bits
== 0xffffffff)
2971 analyze_64bit_constant (high_bits
, low_bits
,
2972 &highest_bit_set
, &lowest_bit_set
,
2973 &all_bits_between_are_set
);
2975 if ((highest_bit_set
== 63
2976 || lowest_bit_set
== 0)
2977 && all_bits_between_are_set
!= 0)
2980 if ((highest_bit_set
- lowest_bit_set
) < 21)
2986 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2987 unsigned HOST_WIDE_INT
,
2990 static unsigned HOST_WIDE_INT
2991 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2992 unsigned HOST_WIDE_INT low_bits
,
2993 int lowest_bit_set
, int shift
)
2995 HOST_WIDE_INT hi
, lo
;
2997 if (lowest_bit_set
< 32)
2999 lo
= (low_bits
>> lowest_bit_set
) << shift
;
3000 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
3005 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
3007 gcc_assert (! (hi
& lo
));
3011 /* Here we are sure to be arch64 and this is an integer constant
3012 being loaded into a register. Emit the most efficient
3013 insn sequence possible. Detection of all the 1-insn cases
3014 has been done already. */
3016 sparc_emit_set_const64 (rtx op0
, rtx op1
)
3018 unsigned HOST_WIDE_INT high_bits
, low_bits
;
3019 int lowest_bit_set
, highest_bit_set
;
3020 int all_bits_between_are_set
;
3023 /* Sanity check that we know what we are working with. */
3024 gcc_assert (TARGET_ARCH64
3025 && (GET_CODE (op0
) == SUBREG
3026 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
3028 if (! can_create_pseudo_p ())
3031 if (GET_CODE (op1
) != CONST_INT
)
3033 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
3038 temp
= gen_reg_rtx (DImode
);
3040 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
3041 low_bits
= (INTVAL (op1
) & 0xffffffff);
3043 /* low_bits bits 0 --> 31
3044 high_bits bits 32 --> 63 */
3046 analyze_64bit_constant (high_bits
, low_bits
,
3047 &highest_bit_set
, &lowest_bit_set
,
3048 &all_bits_between_are_set
);
3050 /* First try for a 2-insn sequence. */
3052 /* These situations are preferred because the optimizer can
3053 * do more things with them:
3055 * sllx %reg, shift, %reg
3057 * srlx %reg, shift, %reg
3058 * 3) mov some_small_const, %reg
3059 * sllx %reg, shift, %reg
3061 if (((highest_bit_set
== 63
3062 || lowest_bit_set
== 0)
3063 && all_bits_between_are_set
!= 0)
3064 || ((highest_bit_set
- lowest_bit_set
) < 12))
3066 HOST_WIDE_INT the_const
= -1;
3067 int shift
= lowest_bit_set
;
3069 if ((highest_bit_set
!= 63
3070 && lowest_bit_set
!= 0)
3071 || all_bits_between_are_set
== 0)
3074 create_simple_focus_bits (high_bits
, low_bits
,
3077 else if (lowest_bit_set
== 0)
3078 shift
= -(63 - highest_bit_set
);
3080 gcc_assert (SPARC_SIMM13_P (the_const
));
3081 gcc_assert (shift
!= 0);
3083 emit_insn (gen_safe_SET64 (temp
, the_const
));
3085 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
3088 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
3089 GEN_INT (-shift
))));
3093 /* Now a range of 22 or less bits set somewhere.
3094 * 1) sethi %hi(focus_bits), %reg
3095 * sllx %reg, shift, %reg
3096 * 2) sethi %hi(focus_bits), %reg
3097 * srlx %reg, shift, %reg
3099 if ((highest_bit_set
- lowest_bit_set
) < 21)
3101 unsigned HOST_WIDE_INT focus_bits
=
3102 create_simple_focus_bits (high_bits
, low_bits
,
3103 lowest_bit_set
, 10);
3105 gcc_assert (SPARC_SETHI_P (focus_bits
));
3106 gcc_assert (lowest_bit_set
!= 10);
3108 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
3110 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
3111 if (lowest_bit_set
< 10)
3112 emit_insn (gen_rtx_SET (op0
,
3113 gen_rtx_LSHIFTRT (DImode
, temp
,
3114 GEN_INT (10 - lowest_bit_set
))));
3115 else if (lowest_bit_set
> 10)
3116 emit_insn (gen_rtx_SET (op0
,
3117 gen_rtx_ASHIFT (DImode
, temp
,
3118 GEN_INT (lowest_bit_set
- 10))));
3122 /* 1) sethi %hi(low_bits), %reg
3123 * or %reg, %lo(low_bits), %reg
3124 * 2) sethi %hi(~low_bits), %reg
3125 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
3128 || high_bits
== 0xffffffff)
3130 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
3131 (high_bits
== 0xffffffff));
3135 /* Now, try 3-insn sequences. */
3137 /* 1) sethi %hi(high_bits), %reg
3138 * or %reg, %lo(high_bits), %reg
3139 * sllx %reg, 32, %reg
3143 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
3147 /* We may be able to do something quick
3148 when the constant is negated, so try that. */
3149 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
3150 (~low_bits
) & 0xfffffc00))
3152 /* NOTE: The trailing bits get XOR'd so we need the
3153 non-negated bits, not the negated ones. */
3154 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
3156 if ((((~high_bits
) & 0xffffffff) == 0
3157 && ((~low_bits
) & 0x80000000) == 0)
3158 || (((~high_bits
) & 0xffffffff) == 0xffffffff
3159 && ((~low_bits
) & 0x80000000) != 0))
3161 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
3163 if ((SPARC_SETHI_P (fast_int
)
3164 && (~high_bits
& 0xffffffff) == 0)
3165 || SPARC_SIMM13_P (fast_int
))
3166 emit_insn (gen_safe_SET64 (temp
, fast_int
));
3168 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
3173 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
3174 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
3175 sparc_emit_set_const64 (temp
, negated_const
);
3178 /* If we are XOR'ing with -1, then we should emit a one's complement
3179 instead. This way the combiner will notice logical operations
3180 such as ANDN later on and substitute. */
3181 if (trailing_bits
== 0x3ff)
3183 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
3187 emit_insn (gen_rtx_SET (op0
,
3188 gen_safe_XOR64 (temp
,
3189 (-0x400 | trailing_bits
))));
3194 /* 1) sethi %hi(xxx), %reg
3195 * or %reg, %lo(xxx), %reg
3196 * sllx %reg, yyy, %reg
3198 * ??? This is just a generalized version of the low_bits==0
3199 * thing above, FIXME...
3201 if ((highest_bit_set
- lowest_bit_set
) < 32)
3203 unsigned HOST_WIDE_INT focus_bits
=
3204 create_simple_focus_bits (high_bits
, low_bits
,
3207 /* We can't get here in this state. */
3208 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
3210 /* So what we know is that the set bits straddle the
3211 middle of the 64-bit word. */
3212 sparc_emit_set_const64_quick2 (op0
, temp
,
3218 /* 1) sethi %hi(high_bits), %reg
3219 * or %reg, %lo(high_bits), %reg
3220 * sllx %reg, 32, %reg
3221 * or %reg, low_bits, %reg
3223 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
3225 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
3229 /* The easiest way when all else fails, is full decomposition. */
3230 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
3233 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */
3236 sparc_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
3238 *p1
= SPARC_ICC_REG
;
3239 *p2
= SPARC_FCC_REG
;
3243 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
3246 sparc_min_arithmetic_precision (void)
3251 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
3252 return the mode to be used for the comparison. For floating-point,
3253 CCFP[E]mode is used. CCNZmode should be used when the first operand
3254 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
3255 processing is needed. */
3258 select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
3260 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3286 else if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
3287 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
3290 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3297 /* This is for the cmp<mode>_sne pattern. */
3298 if (GET_CODE (x
) == NOT
&& y
== constm1_rtx
)
3300 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3306 /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */
3307 if (!TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3309 if (GET_CODE (y
) == UNSPEC
3310 && (XINT (y
, 1) == UNSPEC_ADDV
3311 || XINT (y
, 1) == UNSPEC_SUBV
3312 || XINT (y
, 1) == UNSPEC_NEGV
))
3318 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3325 /* Emit the compare insn and return the CC reg for a CODE comparison
3326 with operands X and Y. */
3329 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
3334 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
3337 mode
= SELECT_CC_MODE (code
, x
, y
);
3339 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
3340 fcc regs (cse can't tell they're really call clobbered regs and will
3341 remove a duplicate comparison even if there is an intervening function
3342 call - it will then try to reload the cc reg via an int reg which is why
3343 we need the movcc patterns). It is possible to provide the movcc
3344 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
3345 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
3346 to tell cse that CCFPE mode registers (even pseudos) are call
3349 /* ??? This is an experiment. Rather than making changes to cse which may
3350 or may not be easy/clean, we do our own cse. This is possible because
3351 we will generate hard registers. Cse knows they're call clobbered (it
3352 doesn't know the same thing about pseudos). If we guess wrong, no big
3353 deal, but if we win, great! */
3355 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3356 #if 1 /* experiment */
3359 /* We cycle through the registers to ensure they're all exercised. */
3360 static int next_fcc_reg
= 0;
3361 /* Previous x,y for each fcc reg. */
3362 static rtx prev_args
[4][2];
3364 /* Scan prev_args for x,y. */
3365 for (reg
= 0; reg
< 4; reg
++)
3366 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
3371 prev_args
[reg
][0] = x
;
3372 prev_args
[reg
][1] = y
;
3373 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
3375 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
3378 cc_reg
= gen_reg_rtx (mode
);
3379 #endif /* ! experiment */
3380 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3381 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
3383 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
3385 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
3386 will only result in an unrecognizable insn so no point in asserting. */
3387 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
3393 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
3396 gen_compare_reg (rtx cmp
)
3398 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
3401 /* This function is used for v9 only.
3402 DEST is the target of the Scc insn.
3403 CODE is the code for an Scc's comparison.
3404 X and Y are the values we compare.
3406 This function is needed to turn
3409 (gt (reg:CCX 100 %icc)
3413 (gt:DI (reg:CCX 100 %icc)
3416 IE: The instruction recognizer needs to see the mode of the comparison to
3417 find the right instruction. We could use "gt:DI" right in the
3418 define_expand, but leaving it out allows us to handle DI, SI, etc. */
3421 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
3424 && (GET_MODE (x
) == DImode
3425 || GET_MODE (dest
) == DImode
))
3428 /* Try to use the movrCC insns. */
3430 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
3432 && v9_regcmp_p (compare_code
))
3437 /* Special case for op0 != 0. This can be done with one instruction if
3440 if (compare_code
== NE
3441 && GET_MODE (dest
) == DImode
3442 && rtx_equal_p (op0
, dest
))
3444 emit_insn (gen_rtx_SET (dest
,
3445 gen_rtx_IF_THEN_ELSE (DImode
,
3446 gen_rtx_fmt_ee (compare_code
, DImode
,
3453 if (reg_overlap_mentioned_p (dest
, op0
))
3455 /* Handle the case where dest == x.
3456 We "early clobber" the result. */
3457 op0
= gen_reg_rtx (GET_MODE (x
));
3458 emit_move_insn (op0
, x
);
3461 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3462 if (GET_MODE (op0
) != DImode
)
3464 temp
= gen_reg_rtx (DImode
);
3465 convert_move (temp
, op0
, 0);
3469 emit_insn (gen_rtx_SET (dest
,
3470 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3471 gen_rtx_fmt_ee (compare_code
, DImode
,
3479 x
= gen_compare_reg_1 (compare_code
, x
, y
);
3482 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3483 emit_insn (gen_rtx_SET (dest
,
3484 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3485 gen_rtx_fmt_ee (compare_code
,
3486 GET_MODE (x
), x
, y
),
3487 const1_rtx
, dest
)));
3493 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
3494 without jumps using the addx/subx instructions. */
3497 emit_scc_insn (rtx operands
[])
3503 /* The quad-word fp compare library routines all return nonzero to indicate
3504 true, which is different from the equivalent libgcc routines, so we must
3505 handle them specially here. */
3506 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
3508 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
3509 GET_CODE (operands
[1]));
3510 operands
[2] = XEXP (operands
[1], 0);
3511 operands
[3] = XEXP (operands
[1], 1);
3514 code
= GET_CODE (operands
[1]);
3517 mode
= GET_MODE (x
);
3519 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
3520 more applications). The exception to this is "reg != 0" which can
3521 be done in one instruction on v9 (so we do it). */
3522 if ((code
== EQ
|| code
== NE
) && (mode
== SImode
|| mode
== DImode
))
3524 if (y
!= const0_rtx
)
3525 x
= force_reg (mode
, gen_rtx_XOR (mode
, x
, y
));
3527 rtx pat
= gen_rtx_SET (operands
[0],
3528 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3531 /* If we can use addx/subx or addxc, add a clobber for CC. */
3532 if (mode
== SImode
|| (code
== NE
&& TARGET_VIS3
))
3535 = gen_rtx_CLOBBER (VOIDmode
,
3536 gen_rtx_REG (mode
== SImode
? CCmode
: CCXmode
,
3538 pat
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, pat
, clobber
));
3545 /* We can do LTU in DImode using the addxc instruction with VIS3. */
3548 && !((code
== LTU
|| code
== GTU
) && TARGET_VIS3
)
3549 && gen_v9_scc (operands
[0], code
, x
, y
))
3552 /* We can do LTU and GEU using the addx/subx instructions too. And
3553 for GTU/LEU, if both operands are registers swap them and fall
3554 back to the easy case. */
3555 if (code
== GTU
|| code
== LEU
)
3557 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3558 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3563 code
= swap_condition (code
);
3567 if (code
== LTU
|| code
== GEU
)
3569 emit_insn (gen_rtx_SET (operands
[0],
3570 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3571 gen_compare_reg_1 (code
, x
, y
),
3576 /* All the posibilities to use addx/subx based sequences has been
3577 exhausted, try for a 3 instruction sequence using v9 conditional
3579 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3582 /* Nope, do branches. */
3586 /* Emit a conditional jump insn for the v9 architecture using comparison code
3587 CODE and jump target LABEL.
3588 This function exists to take advantage of the v9 brxx insns. */
3591 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3593 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3594 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3595 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3597 gen_rtx_LABEL_REF (VOIDmode
, label
),
3601 /* Emit a conditional jump insn for the UA2011 architecture using
3602 comparison code CODE and jump target LABEL. This function exists
3603 to take advantage of the UA2011 Compare and Branch insns. */
3606 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3610 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3611 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3613 gen_rtx_LABEL_REF (VOIDmode
, label
),
3616 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3620 emit_conditional_branch_insn (rtx operands
[])
3622 /* The quad-word fp compare library routines all return nonzero to indicate
3623 true, which is different from the equivalent libgcc routines, so we must
3624 handle them specially here. */
3625 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3627 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3628 GET_CODE (operands
[0]));
3629 operands
[1] = XEXP (operands
[0], 0);
3630 operands
[2] = XEXP (operands
[0], 1);
3633 /* If we can tell early on that the comparison is against a constant
3634 that won't fit in the 5-bit signed immediate field of a cbcond,
3635 use one of the other v9 conditional branch sequences. */
3637 && GET_CODE (operands
[1]) == REG
3638 && (GET_MODE (operands
[1]) == SImode
3639 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3640 && (GET_CODE (operands
[2]) != CONST_INT
3641 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3643 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3647 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3648 && GET_CODE (operands
[1]) == REG
3649 && GET_MODE (operands
[1]) == DImode
)
3651 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3655 operands
[1] = gen_compare_reg (operands
[0]);
3656 operands
[2] = const0_rtx
;
3657 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3658 operands
[1], operands
[2]);
3659 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3664 /* Generate a DFmode part of a hard TFmode register.
3665 REG is the TFmode hard register, LOW is 1 for the
3666 low 64bit of the register and 0 otherwise.
3669 gen_df_reg (rtx reg
, int low
)
3671 int regno
= REGNO (reg
);
3673 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3674 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3675 return gen_rtx_REG (DFmode
, regno
);
3678 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3679 Unlike normal calls, TFmode operands are passed by reference. It is
3680 assumed that no more than 3 operands are required. */
3683 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3685 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3688 /* We only expect to be called for conversions, unary, and binary ops. */
3689 gcc_assert (nargs
== 2 || nargs
== 3);
3691 for (i
= 0; i
< nargs
; ++i
)
3693 rtx this_arg
= operands
[i
];
3696 /* TFmode arguments and return values are passed by reference. */
3697 if (GET_MODE (this_arg
) == TFmode
)
3699 int force_stack_temp
;
3701 force_stack_temp
= 0;
3702 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3703 force_stack_temp
= 1;
3705 if (GET_CODE (this_arg
) == MEM
3706 && ! force_stack_temp
)
3708 tree expr
= MEM_EXPR (this_arg
);
3710 mark_addressable (expr
);
3711 this_arg
= XEXP (this_arg
, 0);
3713 else if (CONSTANT_P (this_arg
)
3714 && ! force_stack_temp
)
3716 this_slot
= force_const_mem (TFmode
, this_arg
);
3717 this_arg
= XEXP (this_slot
, 0);
3721 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3723 /* Operand 0 is the return value. We'll copy it out later. */
3725 emit_move_insn (this_slot
, this_arg
);
3727 ret_slot
= this_slot
;
3729 this_arg
= XEXP (this_slot
, 0);
3736 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3738 if (GET_MODE (operands
[0]) == TFmode
)
3741 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3742 arg
[0], GET_MODE (arg
[0]),
3743 arg
[1], GET_MODE (arg
[1]));
3745 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3746 arg
[0], GET_MODE (arg
[0]),
3747 arg
[1], GET_MODE (arg
[1]),
3748 arg
[2], GET_MODE (arg
[2]));
3751 emit_move_insn (operands
[0], ret_slot
);
3757 gcc_assert (nargs
== 2);
3759 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3760 GET_MODE (operands
[0]),
3761 arg
[1], GET_MODE (arg
[1]));
3763 if (ret
!= operands
[0])
3764 emit_move_insn (operands
[0], ret
);
3768 /* Expand soft-float TFmode calls to sparc abi routines. */
3771 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3793 emit_soft_tfmode_libcall (func
, 3, operands
);
3797 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3801 gcc_assert (code
== SQRT
);
3804 emit_soft_tfmode_libcall (func
, 2, operands
);
3808 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3815 switch (GET_MODE (operands
[1]))
3828 case FLOAT_TRUNCATE
:
3829 switch (GET_MODE (operands
[0]))
3843 switch (GET_MODE (operands
[1]))
3848 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3858 case UNSIGNED_FLOAT
:
3859 switch (GET_MODE (operands
[1]))
3864 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3875 switch (GET_MODE (operands
[0]))
3889 switch (GET_MODE (operands
[0]))
3906 emit_soft_tfmode_libcall (func
, 2, operands
);
3909 /* Expand a hard-float tfmode operation. All arguments must be in
3913 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3917 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3919 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3920 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3924 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3925 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3926 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3927 operands
[1], operands
[2]);
3930 if (register_operand (operands
[0], VOIDmode
))
3933 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3935 emit_insn (gen_rtx_SET (dest
, op
));
3937 if (dest
!= operands
[0])
3938 emit_move_insn (operands
[0], dest
);
3942 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3944 if (TARGET_HARD_QUAD
)
3945 emit_hard_tfmode_operation (code
, operands
);
3947 emit_soft_tfmode_binop (code
, operands
);
3951 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3953 if (TARGET_HARD_QUAD
)
3954 emit_hard_tfmode_operation (code
, operands
);
3956 emit_soft_tfmode_unop (code
, operands
);
3960 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3962 if (TARGET_HARD_QUAD
)
3963 emit_hard_tfmode_operation (code
, operands
);
3965 emit_soft_tfmode_cvt (code
, operands
);
3968 /* Return nonzero if a branch/jump/call instruction will be emitting
3969 nop into its delay slot. */
3972 empty_delay_slot (rtx_insn
*insn
)
3976 /* If no previous instruction (should not happen), return true. */
3977 if (PREV_INSN (insn
) == NULL
)
3980 seq
= NEXT_INSN (PREV_INSN (insn
));
3981 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3987 /* Return nonzero if we should emit a nop after a cbcond instruction.
3988 The cbcond instruction does not have a delay slot, however there is
3989 a severe performance penalty if a control transfer appears right
3990 after a cbcond. Therefore we emit a nop when we detect this
3994 emit_cbcond_nop (rtx_insn
*insn
)
3996 rtx next
= next_active_insn (insn
);
4001 if (NONJUMP_INSN_P (next
)
4002 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
4003 next
= XVECEXP (PATTERN (next
), 0, 0);
4004 else if (CALL_P (next
)
4005 && GET_CODE (PATTERN (next
)) == PARALLEL
)
4007 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
4009 if (GET_CODE (delay
) == RETURN
)
4011 /* It's a sibling call. Do not emit the nop if we're going
4012 to emit something other than the jump itself as the first
4013 instruction of the sibcall sequence. */
4014 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4019 if (NONJUMP_INSN_P (next
))
4025 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
4026 instruction. RETURN_P is true if the v9 variant 'return' is to be
4027 considered in the test too.
4029 TRIAL must be a SET whose destination is a REG appropriate for the
4030 'restore' instruction or, if RETURN_P is true, for the 'return'
4034 eligible_for_restore_insn (rtx trial
, bool return_p
)
4036 rtx pat
= PATTERN (trial
);
4037 rtx src
= SET_SRC (pat
);
4038 bool src_is_freg
= false;
4041 /* Since we now can do moves between float and integer registers when
4042 VIS3 is enabled, we have to catch this case. We can allow such
4043 moves when doing a 'return' however. */
4045 if (GET_CODE (src_reg
) == SUBREG
)
4046 src_reg
= SUBREG_REG (src_reg
);
4047 if (GET_CODE (src_reg
) == REG
4048 && SPARC_FP_REG_P (REGNO (src_reg
)))
4051 /* The 'restore src,%g0,dest' pattern for word mode and below. */
4052 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4053 && arith_operand (src
, GET_MODE (src
))
4057 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4059 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
4062 /* The 'restore src,%g0,dest' pattern for double-word mode. */
4063 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4064 && arith_double_operand (src
, GET_MODE (src
))
4066 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4068 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
4069 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
4072 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
4073 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
4076 /* If we have the 'return' instruction, anything that does not use
4077 local or output registers and can go into a delay slot wins. */
4078 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
4081 /* The 'restore src1,src2,dest' pattern for SImode. */
4082 else if (GET_CODE (src
) == PLUS
4083 && register_operand (XEXP (src
, 0), SImode
)
4084 && arith_operand (XEXP (src
, 1), SImode
))
4087 /* The 'restore src1,src2,dest' pattern for DImode. */
4088 else if (GET_CODE (src
) == PLUS
4089 && register_operand (XEXP (src
, 0), DImode
)
4090 && arith_double_operand (XEXP (src
, 1), DImode
))
4093 /* The 'restore src1,%lo(src2),dest' pattern. */
4094 else if (GET_CODE (src
) == LO_SUM
4095 && ! TARGET_CM_MEDMID
4096 && ((register_operand (XEXP (src
, 0), SImode
)
4097 && immediate_operand (XEXP (src
, 1), SImode
))
4099 && register_operand (XEXP (src
, 0), DImode
)
4100 && immediate_operand (XEXP (src
, 1), DImode
))))
4103 /* The 'restore src,src,dest' pattern. */
4104 else if (GET_CODE (src
) == ASHIFT
4105 && (register_operand (XEXP (src
, 0), SImode
)
4106 || register_operand (XEXP (src
, 0), DImode
))
4107 && XEXP (src
, 1) == const1_rtx
)
4113 /* Return nonzero if TRIAL can go into the function return's delay slot. */
4116 eligible_for_return_delay (rtx_insn
*trial
)
4121 /* If the function uses __builtin_eh_return, the eh_return machinery
4122 occupies the delay slot. */
4123 if (crtl
->calls_eh_return
)
4126 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4129 /* In the case of a leaf or flat function, anything can go into the slot. */
4130 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4133 if (!NONJUMP_INSN_P (trial
))
4136 pat
= PATTERN (trial
);
4137 if (GET_CODE (pat
) == PARALLEL
)
4143 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
4145 rtx expr
= XVECEXP (pat
, 0, i
);
4146 if (GET_CODE (expr
) != SET
)
4148 if (GET_CODE (SET_DEST (expr
)) != REG
)
4150 regno
= REGNO (SET_DEST (expr
));
4151 if (regno
>= 8 && regno
< 24)
4154 return !epilogue_renumber (&pat
, 1);
4157 if (GET_CODE (pat
) != SET
)
4160 if (GET_CODE (SET_DEST (pat
)) != REG
)
4163 regno
= REGNO (SET_DEST (pat
));
4165 /* Otherwise, only operations which can be done in tandem with
4166 a `restore' or `return' insn can go into the delay slot. */
4167 if (regno
>= 8 && regno
< 24)
4170 /* If this instruction sets up floating point register and we have a return
4171 instruction, it can probably go in. But restore will not work
4173 if (! SPARC_INT_REG_P (regno
))
4174 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
4176 return eligible_for_restore_insn (trial
, true);
4179 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
4182 eligible_for_sibcall_delay (rtx_insn
*trial
)
4186 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4189 if (!NONJUMP_INSN_P (trial
))
4192 pat
= PATTERN (trial
);
4194 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4196 /* If the tail call is done using the call instruction,
4197 we have to restore %o7 in the delay slot. */
4198 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
4201 /* %g1 is used to build the function address */
4202 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
4208 if (GET_CODE (pat
) != SET
)
4211 /* Otherwise, only operations which can be done in tandem with
4212 a `restore' insn can go into the delay slot. */
4213 if (GET_CODE (SET_DEST (pat
)) != REG
4214 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
4215 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
4218 /* If it mentions %o7, it can't go in, because sibcall will clobber it
4220 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
4223 return eligible_for_restore_insn (trial
, false);
4226 /* Determine if it's legal to put X into the constant pool. This
4227 is not possible if X contains the address of a symbol that is
4228 not constant (TLS) or not known at final link time (PIC). */
4231 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
4233 switch (GET_CODE (x
))
4236 case CONST_WIDE_INT
:
4239 /* Accept all non-symbolic constants. */
4243 /* Labels are OK iff we are non-PIC. */
4244 return flag_pic
!= 0;
4247 /* 'Naked' TLS symbol references are never OK,
4248 non-TLS symbols are OK iff we are non-PIC. */
4249 if (SYMBOL_REF_TLS_MODEL (x
))
4252 return flag_pic
!= 0;
4255 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
4258 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
4259 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
4267 /* Global Offset Table support. */
4268 static GTY(()) rtx got_symbol_rtx
= NULL_RTX
;
4269 static GTY(()) rtx got_register_rtx
= NULL_RTX
;
4270 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
4272 static GTY(()) bool got_helper_needed
= false;
4274 /* Return the SYMBOL_REF for the Global Offset Table. */
4279 if (!got_symbol_rtx
)
4280 got_symbol_rtx
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
4282 return got_symbol_rtx
;
4285 /* Output the load_pcrel_sym pattern. */
4288 output_load_pcrel_sym (rtx
*operands
)
4290 if (flag_delayed_branch
)
4292 output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands
);
4293 output_asm_insn ("call\t%a2", operands
);
4294 output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands
);
4298 output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands
);
4299 output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands
);
4300 output_asm_insn ("call\t%a2", operands
);
4301 output_asm_insn (" nop", NULL
);
4304 if (operands
[2] == got_helper_rtx
)
4305 got_helper_needed
= true;
4310 #ifdef HAVE_GAS_HIDDEN
4311 # define USE_HIDDEN_LINKONCE 1
4313 # define USE_HIDDEN_LINKONCE 0
4316 /* Emit code to load the GOT register. */
4319 load_got_register (void)
4323 if (TARGET_VXWORKS_RTP
)
4325 if (!got_register_rtx
)
4326 got_register_rtx
= pic_offset_table_rtx
;
4328 insn
= gen_vxworks_load_got ();
4332 if (!got_register_rtx
)
4333 got_register_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4335 /* The GOT symbol is subject to a PC-relative relocation so we need a
4336 helper function to add the PC value and thus get the final value. */
4337 if (!got_helper_rtx
)
4341 /* Skip the leading '%' as that cannot be used in a symbol name. */
4342 if (USE_HIDDEN_LINKONCE
)
4343 sprintf (name
, "__sparc_get_pc_thunk.%s",
4344 reg_names
[REGNO (got_register_rtx
)] + 1);
4346 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC",
4347 REGNO (got_register_rtx
));
4349 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4352 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4353 const int orig_flag_pic
= flag_pic
;
4355 insn
= gen_load_pcrel_sym (Pmode
,
4359 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
));
4360 flag_pic
= orig_flag_pic
;
4366 /* Ensure that we are not using patterns that are not OK with PIC. */
4376 op
= recog_data
.operand
[i
];
4377 gcc_assert (GET_CODE (op
) != SYMBOL_REF
4378 && (GET_CODE (op
) != CONST
4379 || (GET_CODE (XEXP (op
, 0)) == MINUS
4380 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
4381 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
4389 /* Return true if X is an address which needs a temporary register when
4390 reloaded while generating PIC code. */
4393 pic_address_needs_scratch (rtx x
)
4395 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
4396 if (GET_CODE (x
) == CONST
4397 && GET_CODE (XEXP (x
, 0)) == PLUS
4398 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
4399 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4400 && !SMALL_INT (XEXP (XEXP (x
, 0), 1)))
4406 /* Determine if a given RTX is a valid constant. We already know this
4407 satisfies CONSTANT_P. */
4410 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
4412 switch (GET_CODE (x
))
4416 if (sparc_tls_referenced_p (x
))
4421 /* Floating point constants are generally not ok.
4422 The only exception is 0.0 and all-ones in VIS. */
4424 && SCALAR_FLOAT_MODE_P (mode
)
4425 && (const_zero_operand (x
, mode
)
4426 || const_all_ones_operand (x
, mode
)))
4432 /* Vector constants are generally not ok.
4433 The only exception is 0 or -1 in VIS. */
4435 && (const_zero_operand (x
, mode
)
4436 || const_all_ones_operand (x
, mode
)))
4448 /* Determine if a given RTX is a valid constant address. */
4451 constant_address_p (rtx x
)
4453 switch (GET_CODE (x
))
4461 if (flag_pic
&& pic_address_needs_scratch (x
))
4463 return sparc_legitimate_constant_p (Pmode
, x
);
4466 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
4473 /* Nonzero if the constant value X is a legitimate general operand
4474 when generating PIC code. It is given that flag_pic is on and
4475 that X satisfies CONSTANT_P. */
4478 legitimate_pic_operand_p (rtx x
)
4480 if (pic_address_needs_scratch (x
))
4482 if (sparc_tls_referenced_p (x
))
4487 /* Return true if X is a representation of the PIC register. */
4490 sparc_pic_register_p (rtx x
)
4492 if (!REG_P (x
) || !pic_offset_table_rtx
)
4495 if (x
== pic_offset_table_rtx
)
4498 if (!HARD_REGISTER_P (pic_offset_table_rtx
)
4499 && (HARD_REGISTER_P (x
) || lra_in_progress
|| reload_in_progress
)
4500 && ORIGINAL_REGNO (x
) == REGNO (pic_offset_table_rtx
))
4506 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
4508 && INTVAL (X) >= -0x1000 \
4509 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
4511 #define RTX_OK_FOR_OLO10_P(X, MODE) \
4513 && INTVAL (X) >= -0x1000 \
4514 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
4516 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
4518 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
4519 ordinarily. This changes a bit when generating PIC. */
4522 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
,
4525 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
4527 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
4529 else if (GET_CODE (addr
) == PLUS
)
4531 rs1
= XEXP (addr
, 0);
4532 rs2
= XEXP (addr
, 1);
4534 /* Canonicalize. REG comes first, if there are no regs,
4535 LO_SUM comes first. */
4537 && GET_CODE (rs1
) != SUBREG
4539 || GET_CODE (rs2
) == SUBREG
4540 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
4542 rs1
= XEXP (addr
, 1);
4543 rs2
= XEXP (addr
, 0);
4547 && sparc_pic_register_p (rs1
)
4549 && GET_CODE (rs2
) != SUBREG
4550 && GET_CODE (rs2
) != LO_SUM
4551 && GET_CODE (rs2
) != MEM
4552 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
4553 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
4554 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
4556 || GET_CODE (rs1
) == SUBREG
)
4557 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
4562 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
4563 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
4565 /* We prohibit REG + REG for TFmode when there are no quad move insns
4566 and we consequently need to split. We do this because REG+REG
4567 is not an offsettable address. If we get the situation in reload
4568 where source and destination of a movtf pattern are both MEMs with
4569 REG+REG address, then only one of them gets converted to an
4570 offsettable address. */
4572 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4575 /* Likewise for TImode, but in all cases. */
4579 /* We prohibit REG + REG on ARCH32 if not optimizing for
4580 DFmode/DImode because then mem_min_alignment is likely to be zero
4581 after reload and the forced split would lack a matching splitter
4583 if (TARGET_ARCH32
&& !optimize
4584 && (mode
== DFmode
|| mode
== DImode
))
4587 else if (USE_AS_OFFSETABLE_LO10
4588 && GET_CODE (rs1
) == LO_SUM
4590 && ! TARGET_CM_MEDMID
4591 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4594 imm1
= XEXP (rs1
, 1);
4595 rs1
= XEXP (rs1
, 0);
4596 if (!CONSTANT_P (imm1
)
4597 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4601 else if (GET_CODE (addr
) == LO_SUM
)
4603 rs1
= XEXP (addr
, 0);
4604 imm1
= XEXP (addr
, 1);
4606 if (!CONSTANT_P (imm1
)
4607 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4610 /* We can't allow TFmode in 32-bit mode, because an offset greater
4611 than the alignment (8) may cause the LO_SUM to overflow. */
4612 if (mode
== TFmode
&& TARGET_ARCH32
)
4615 /* During reload, accept the HIGH+LO_SUM construct generated by
4616 sparc_legitimize_reload_address. */
4617 if (reload_in_progress
4618 && GET_CODE (rs1
) == HIGH
4619 && XEXP (rs1
, 0) == imm1
)
4622 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4627 if (GET_CODE (rs1
) == SUBREG
)
4628 rs1
= SUBREG_REG (rs1
);
4634 if (GET_CODE (rs2
) == SUBREG
)
4635 rs2
= SUBREG_REG (rs2
);
4642 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4643 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4648 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4649 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4650 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4652 && (! SPARC_INT_REG_P (REGNO (rs2
))
4653 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4654 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4660 /* Return the SYMBOL_REF for the tls_get_addr function. */
4662 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4665 sparc_tls_get_addr (void)
4667 if (!sparc_tls_symbol
)
4668 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4670 return sparc_tls_symbol
;
4673 /* Return the Global Offset Table to be used in TLS mode. */
4676 sparc_tls_got (void)
4678 /* In PIC mode, this is just the PIC offset table. */
4681 crtl
->uses_pic_offset_table
= 1;
4682 return pic_offset_table_rtx
;
4685 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4686 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4687 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4689 load_got_register ();
4690 return got_register_rtx
;
4693 /* In all other cases, we load a new pseudo with the GOT symbol. */
4694 return copy_to_reg (sparc_got ());
4697 /* Return true if X contains a thread-local symbol. */
4700 sparc_tls_referenced_p (rtx x
)
4702 if (!TARGET_HAVE_TLS
)
4705 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4706 x
= XEXP (XEXP (x
, 0), 0);
4708 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4711 /* That's all we handle in sparc_legitimize_tls_address for now. */
4715 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4716 this (thread-local) address. */
4719 sparc_legitimize_tls_address (rtx addr
)
4721 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4724 gcc_assert (can_create_pseudo_p ());
4726 if (GET_CODE (addr
) == SYMBOL_REF
)
4727 /* Although the various sethi/or sequences generate SImode values, many of
4728 them can be transformed by the linker when relaxing and, if relaxing to
4729 local-exec, will become a sethi/xor pair, which is signed and therefore
4730 a full DImode value in 64-bit mode. Thus we must use Pmode, lest these
4731 values be spilled onto the stack in 64-bit mode. */
4732 switch (SYMBOL_REF_TLS_MODEL (addr
))
4734 case TLS_MODEL_GLOBAL_DYNAMIC
:
4736 temp1
= gen_reg_rtx (Pmode
);
4737 temp2
= gen_reg_rtx (Pmode
);
4738 ret
= gen_reg_rtx (Pmode
);
4739 o0
= gen_rtx_REG (Pmode
, 8);
4740 got
= sparc_tls_got ();
4741 emit_insn (gen_tgd_hi22 (Pmode
, temp1
, addr
));
4742 emit_insn (gen_tgd_lo10 (Pmode
, temp2
, temp1
, addr
));
4743 emit_insn (gen_tgd_add (Pmode
, o0
, got
, temp2
, addr
));
4744 insn
= emit_call_insn (gen_tgd_call (Pmode
, o0
, sparc_tls_get_addr (),
4746 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4747 RTL_CONST_CALL_P (insn
) = 1;
4748 insn
= get_insns ();
4750 emit_libcall_block (insn
, ret
, o0
, addr
);
4753 case TLS_MODEL_LOCAL_DYNAMIC
:
4755 temp1
= gen_reg_rtx (Pmode
);
4756 temp2
= gen_reg_rtx (Pmode
);
4757 temp3
= gen_reg_rtx (Pmode
);
4758 ret
= gen_reg_rtx (Pmode
);
4759 o0
= gen_rtx_REG (Pmode
, 8);
4760 got
= sparc_tls_got ();
4761 emit_insn (gen_tldm_hi22 (Pmode
, temp1
));
4762 emit_insn (gen_tldm_lo10 (Pmode
, temp2
, temp1
));
4763 emit_insn (gen_tldm_add (Pmode
, o0
, got
, temp2
));
4764 insn
= emit_call_insn (gen_tldm_call (Pmode
, o0
, sparc_tls_get_addr (),
4766 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4767 RTL_CONST_CALL_P (insn
) = 1;
4768 insn
= get_insns ();
4770 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
4771 share the LD_BASE result with other LD model accesses. */
4772 emit_libcall_block (insn
, temp3
, o0
,
4773 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4774 UNSPEC_TLSLD_BASE
));
4775 temp1
= gen_reg_rtx (Pmode
);
4776 temp2
= gen_reg_rtx (Pmode
);
4777 emit_insn (gen_tldo_hix22 (Pmode
, temp1
, addr
));
4778 emit_insn (gen_tldo_lox10 (Pmode
, temp2
, temp1
, addr
));
4779 emit_insn (gen_tldo_add (Pmode
, ret
, temp3
, temp2
, addr
));
4782 case TLS_MODEL_INITIAL_EXEC
:
4783 temp1
= gen_reg_rtx (Pmode
);
4784 temp2
= gen_reg_rtx (Pmode
);
4785 temp3
= gen_reg_rtx (Pmode
);
4786 got
= sparc_tls_got ();
4787 emit_insn (gen_tie_hi22 (Pmode
, temp1
, addr
));
4788 emit_insn (gen_tie_lo10 (Pmode
, temp2
, temp1
, addr
));
4790 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4792 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4795 ret
= gen_reg_rtx (Pmode
);
4796 emit_insn (gen_tie_add (Pmode
, ret
, gen_rtx_REG (Pmode
, 7),
4800 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4803 case TLS_MODEL_LOCAL_EXEC
:
4804 temp1
= gen_reg_rtx (Pmode
);
4805 temp2
= gen_reg_rtx (Pmode
);
4806 emit_insn (gen_tle_hix22 (Pmode
, temp1
, addr
));
4807 emit_insn (gen_tle_lox10 (Pmode
, temp2
, temp1
, addr
));
4808 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4815 else if (GET_CODE (addr
) == CONST
)
4819 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4821 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4822 offset
= XEXP (XEXP (addr
, 0), 1);
4824 base
= force_operand (base
, NULL_RTX
);
4825 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4826 offset
= force_reg (Pmode
, offset
);
4827 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4831 gcc_unreachable (); /* for now ... */
4836 /* Legitimize PIC addresses. If the address is already position-independent,
4837 we return ORIG. Newly generated position-independent addresses go into a
4838 reg. This is REG if nonzero, otherwise we allocate register(s) as
4842 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4844 if (GET_CODE (orig
) == SYMBOL_REF
4845 /* See the comment in sparc_expand_move. */
4846 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4848 bool gotdata_op
= false;
4849 rtx pic_ref
, address
;
4854 gcc_assert (can_create_pseudo_p ());
4855 reg
= gen_reg_rtx (Pmode
);
4860 /* If not during reload, allocate another temp reg here for loading
4861 in the address, so that these instructions can be optimized
4863 rtx temp_reg
= can_create_pseudo_p () ? gen_reg_rtx (Pmode
) : reg
;
4865 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4866 won't get confused into thinking that these two instructions
4867 are loading in the true address of the symbol. If in the
4868 future a PIC rtx exists, that should be used instead. */
4871 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4872 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4876 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4877 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4886 crtl
->uses_pic_offset_table
= 1;
4890 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4891 pic_offset_table_rtx
,
4894 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4895 pic_offset_table_rtx
,
4901 = gen_const_mem (Pmode
,
4902 gen_rtx_PLUS (Pmode
,
4903 pic_offset_table_rtx
, address
));
4904 insn
= emit_move_insn (reg
, pic_ref
);
4907 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4909 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4912 else if (GET_CODE (orig
) == CONST
)
4916 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4917 && sparc_pic_register_p (XEXP (XEXP (orig
, 0), 0)))
4922 gcc_assert (can_create_pseudo_p ());
4923 reg
= gen_reg_rtx (Pmode
);
4926 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4927 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4928 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4929 base
== reg
? NULL_RTX
: reg
);
4931 if (GET_CODE (offset
) == CONST_INT
)
4933 if (SMALL_INT (offset
))
4934 return plus_constant (Pmode
, base
, INTVAL (offset
));
4935 else if (can_create_pseudo_p ())
4936 offset
= force_reg (Pmode
, offset
);
4938 /* If we reach here, then something is seriously wrong. */
4941 return gen_rtx_PLUS (Pmode
, base
, offset
);
4943 else if (GET_CODE (orig
) == LABEL_REF
)
4944 /* ??? We ought to be checking that the register is live instead, in case
4945 it is eliminated. */
4946 crtl
->uses_pic_offset_table
= 1;
4951 /* Try machine-dependent ways of modifying an illegitimate address X
4952 to be legitimate. If we find one, return the new, valid address.
4954 OLDX is the address as it was before break_out_memory_refs was called.
4955 In some cases it is useful to look at this to decide what needs to be done.
4957 MODE is the mode of the operand pointed to by X.
4959 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4962 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4967 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4968 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4969 force_operand (XEXP (x
, 0), NULL_RTX
));
4970 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4971 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4972 force_operand (XEXP (x
, 1), NULL_RTX
));
4973 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4974 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4976 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4977 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4978 force_operand (XEXP (x
, 1), NULL_RTX
));
4980 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4983 if (sparc_tls_referenced_p (x
))
4984 x
= sparc_legitimize_tls_address (x
);
4986 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4987 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4988 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4989 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4990 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4991 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4992 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4993 else if (GET_CODE (x
) == SYMBOL_REF
4994 || GET_CODE (x
) == CONST
4995 || GET_CODE (x
) == LABEL_REF
)
4996 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
5001 /* Delegitimize an address that was legitimized by the above function. */
5004 sparc_delegitimize_address (rtx x
)
5006 x
= delegitimize_mem_from_attrs (x
);
5008 if (GET_CODE (x
) == LO_SUM
)
5011 if (GET_CODE (x
) == UNSPEC
)
5012 switch (XINT (x
, 1))
5014 case UNSPEC_MOVE_PIC
:
5016 x
= XVECEXP (x
, 0, 0);
5017 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
5019 case UNSPEC_MOVE_GOTDATA
:
5020 x
= XVECEXP (x
, 0, 2);
5021 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
5027 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
5028 if (GET_CODE (x
) == MINUS
5029 && (XEXP (x
, 0) == got_register_rtx
5030 || sparc_pic_register_p (XEXP (x
, 0))))
5032 rtx y
= XEXP (x
, 1);
5034 if (GET_CODE (y
) == LO_SUM
)
5037 if (GET_CODE (y
) == UNSPEC
&& XINT (y
, 1) == UNSPEC_MOVE_PIC_LABEL
)
5039 x
= XVECEXP (y
, 0, 0);
5040 gcc_assert (GET_CODE (x
) == LABEL_REF
5041 || (GET_CODE (x
) == CONST
5042 && GET_CODE (XEXP (x
, 0)) == PLUS
5043 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5044 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
));
5051 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
5052 replace the input X, or the original X if no replacement is called for.
5053 The output parameter *WIN is 1 if the calling macro should goto WIN,
5056 For SPARC, we wish to handle addresses by splitting them into
5057 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
5058 This cuts the number of extra insns by one.
5060 Do nothing when generating PIC code and the address is a symbolic
5061 operand or requires a scratch register. */
5064 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
5065 int opnum
, int type
,
5066 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
5068 /* Decompose SImode constants into HIGH+LO_SUM. */
5070 && (mode
!= TFmode
|| TARGET_ARCH64
)
5071 && GET_MODE (x
) == SImode
5072 && GET_CODE (x
) != LO_SUM
5073 && GET_CODE (x
) != HIGH
5074 && sparc_code_model
<= CM_MEDLOW
5076 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
5078 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
5079 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
5080 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
5081 opnum
, (enum reload_type
)type
);
5086 /* We have to recognize what we have already generated above. */
5087 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
5089 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
5090 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
5091 opnum
, (enum reload_type
)type
);
5100 /* Return true if ADDR (a legitimate address expression)
5101 has an effect that depends on the machine mode it is used for.
5107 is not equivalent to
5109 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
5111 because [%l7+a+1] is interpreted as the address of (a+1). */
5115 sparc_mode_dependent_address_p (const_rtx addr
,
5116 addr_space_t as ATTRIBUTE_UNUSED
)
5118 if (GET_CODE (addr
) == PLUS
5119 && sparc_pic_register_p (XEXP (addr
, 0))
5120 && symbolic_operand (XEXP (addr
, 1), VOIDmode
))
5126 /* Emit a call instruction with the pattern given by PAT. ADDR is the
5127 address of the call target. */
5130 sparc_emit_call_insn (rtx pat
, rtx addr
)
5134 insn
= emit_call_insn (pat
);
5136 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
5137 if (TARGET_VXWORKS_RTP
5139 && GET_CODE (addr
) == SYMBOL_REF
5140 && (SYMBOL_REF_DECL (addr
)
5141 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
5142 : !SYMBOL_REF_LOCAL_P (addr
)))
5144 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
5145 crtl
->uses_pic_offset_table
= 1;
5149 /* Return 1 if RTX is a MEM which is known to be aligned to at
5150 least a DESIRED byte boundary. */
5153 mem_min_alignment (rtx mem
, int desired
)
5155 rtx addr
, base
, offset
;
5157 /* If it's not a MEM we can't accept it. */
5158 if (GET_CODE (mem
) != MEM
)
5162 if (!TARGET_UNALIGNED_DOUBLES
5163 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
5166 /* ??? The rest of the function predates MEM_ALIGN so
5167 there is probably a bit of redundancy. */
5168 addr
= XEXP (mem
, 0);
5169 base
= offset
= NULL_RTX
;
5170 if (GET_CODE (addr
) == PLUS
)
5172 if (GET_CODE (XEXP (addr
, 0)) == REG
)
5174 base
= XEXP (addr
, 0);
5176 /* What we are saying here is that if the base
5177 REG is aligned properly, the compiler will make
5178 sure any REG based index upon it will be so
5180 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5181 offset
= XEXP (addr
, 1);
5183 offset
= const0_rtx
;
5186 else if (GET_CODE (addr
) == REG
)
5189 offset
= const0_rtx
;
5192 if (base
!= NULL_RTX
)
5194 int regno
= REGNO (base
);
5196 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
5198 /* Check if the compiler has recorded some information
5199 about the alignment of the base REG. If reload has
5200 completed, we already matched with proper alignments.
5201 If not running global_alloc, reload might give us
5202 unaligned pointer to local stack though. */
5204 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
5205 || (optimize
&& reload_completed
))
5206 && (INTVAL (offset
) & (desired
- 1)) == 0)
5211 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
5215 else if (! TARGET_UNALIGNED_DOUBLES
5216 || CONSTANT_P (addr
)
5217 || GET_CODE (addr
) == LO_SUM
)
5219 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
5220 is true, in which case we can only assume that an access is aligned if
5221 it is to a constant address, or the address involves a LO_SUM. */
5225 /* An obviously unaligned address. */
5230 /* Vectors to keep interesting information about registers where it can easily
5231 be got. We used to use the actual mode value as the bit number, but there
5232 are more than 32 modes now. Instead we use two tables: one indexed by
5233 hard register number, and one indexed by mode. */
5235 /* The purpose of sparc_mode_class is to shrink the range of modes so that
5236 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
5237 mapped into one sparc_mode_class mode. */
5239 enum sparc_mode_class
{
5240 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
5241 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
5245 /* Modes for single-word and smaller quantities. */
5247 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
5249 /* Modes for double-word and smaller quantities. */
5250 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5252 /* Modes for quad-word and smaller quantities. */
5253 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
5255 /* Modes for 8-word and smaller quantities. */
5256 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
5258 /* Modes for single-float quantities. */
5259 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
5261 /* Modes for double-float and smaller quantities. */
5262 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5264 /* Modes for quad-float and smaller quantities. */
5265 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
5267 /* Modes for quad-float pairs and smaller quantities. */
5268 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
5270 /* Modes for double-float only quantities. */
5271 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
5273 /* Modes for quad-float and double-float only quantities. */
5274 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
5276 /* Modes for quad-float pairs and double-float only quantities. */
5277 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
5279 /* Modes for condition codes. */
5280 #define CC_MODES (1 << (int) CC_MODE)
5281 #define CCFP_MODES (1 << (int) CCFP_MODE)
5283 /* Value is 1 if register/mode pair is acceptable on sparc.
5285 The funny mixture of D and T modes is because integer operations
5286 do not specially operate on tetra quantities, so non-quad-aligned
5287 registers can hold quadword quantities (except %o4 and %i4 because
5288 they cross fixed registers).
5290 ??? Note that, despite the settings, non-double-aligned parameter
5291 registers can hold double-word quantities in 32-bit mode. */
5293 /* This points to either the 32-bit or the 64-bit version. */
5294 static const int *hard_regno_mode_classes
;
5296 static const int hard_32bit_mode_classes
[] = {
5297 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5298 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5299 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5300 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5302 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5303 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5304 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5305 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5307 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5308 and none can hold SFmode/SImode values. */
5309 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5310 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5311 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5312 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5315 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5317 /* %icc, %sfp, %gsr */
5318 CC_MODES
, 0, D_MODES
5321 static const int hard_64bit_mode_classes
[] = {
5322 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5323 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5324 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5325 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5327 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5328 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5329 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5330 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5332 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5333 and none can hold SFmode/SImode values. */
5334 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5335 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5336 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5337 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5340 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5342 /* %icc, %sfp, %gsr */
5343 CC_MODES
, 0, D_MODES
5346 static int sparc_mode_class
[NUM_MACHINE_MODES
];
5348 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
5351 sparc_init_modes (void)
5355 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5357 machine_mode m
= (machine_mode
) i
;
5358 unsigned int size
= GET_MODE_SIZE (m
);
5360 switch (GET_MODE_CLASS (m
))
5363 case MODE_PARTIAL_INT
:
5364 case MODE_COMPLEX_INT
:
5366 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
5368 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
5370 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
5371 else if (size
== 16)
5372 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
5373 else if (size
== 32)
5374 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
5376 sparc_mode_class
[i
] = 0;
5378 case MODE_VECTOR_INT
:
5380 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5382 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5384 sparc_mode_class
[i
] = 0;
5387 case MODE_COMPLEX_FLOAT
:
5389 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5391 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5392 else if (size
== 16)
5393 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
5394 else if (size
== 32)
5395 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
5397 sparc_mode_class
[i
] = 0;
5400 if (m
== CCFPmode
|| m
== CCFPEmode
)
5401 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
5403 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
5406 sparc_mode_class
[i
] = 0;
5412 hard_regno_mode_classes
= hard_64bit_mode_classes
;
5414 hard_regno_mode_classes
= hard_32bit_mode_classes
;
5416 /* Initialize the array used by REGNO_REG_CLASS. */
5417 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5419 if (i
< 16 && TARGET_V8PLUS
)
5420 sparc_regno_reg_class
[i
] = I64_REGS
;
5421 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
5422 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
5424 sparc_regno_reg_class
[i
] = FP_REGS
;
5426 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
5428 sparc_regno_reg_class
[i
] = FPCC_REGS
;
5430 sparc_regno_reg_class
[i
] = NO_REGS
;
5434 /* Return whether REGNO, a global or FP register, must be saved/restored. */
5437 save_global_or_fp_reg_p (unsigned int regno
,
5438 int leaf_function ATTRIBUTE_UNUSED
)
5440 return !call_used_or_fixed_reg_p (regno
) && df_regs_ever_live_p (regno
);
5443 /* Return whether the return address register (%i7) is needed. */
5446 return_addr_reg_needed_p (int leaf_function
)
5448 /* If it is live, for example because of __builtin_return_address (0). */
5449 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
5452 /* Otherwise, it is needed as save register if %o7 is clobbered. */
5454 /* Loading the GOT register clobbers %o7. */
5455 || crtl
->uses_pic_offset_table
5456 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
5462 /* Return whether REGNO, a local or in register, must be saved/restored. */
5465 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
5467 /* General case: call-saved registers live at some point. */
5468 if (!call_used_or_fixed_reg_p (regno
) && df_regs_ever_live_p (regno
))
5471 /* Frame pointer register (%fp) if needed. */
5472 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
5475 /* Return address register (%i7) if needed. */
5476 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
5479 /* GOT register (%l7) if needed. */
5480 if (got_register_rtx
&& regno
== REGNO (got_register_rtx
))
5483 /* If the function accesses prior frames, the frame pointer and the return
5484 address of the previous frame must be saved on the stack. */
5485 if (crtl
->accesses_prior_frames
5486 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5492 /* Compute the frame size required by the function. This function is called
5493 during the reload pass and also by sparc_expand_prologue. */
5495 static HOST_WIDE_INT
5496 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5498 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5499 int args_size
, n_global_fp_regs
= 0;
5500 bool save_local_in_regs_p
= false;
5503 /* If the function allocates dynamic stack space, the dynamic offset is
5504 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5505 if (leaf_function
&& !cfun
->calls_alloca
)
5508 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5510 /* Calculate space needed for global registers. */
5513 for (i
= 0; i
< 8; i
++)
5514 if (save_global_or_fp_reg_p (i
, 0))
5515 n_global_fp_regs
+= 2;
5519 for (i
= 0; i
< 8; i
+= 2)
5520 if (save_global_or_fp_reg_p (i
, 0)
5521 || save_global_or_fp_reg_p (i
+ 1, 0))
5522 n_global_fp_regs
+= 2;
5525 /* In the flat window model, find out which local and in registers need to
5526 be saved. We don't reserve space in the current frame for them as they
5527 will be spilled into the register window save area of the caller's frame.
5528 However, as soon as we use this register window save area, we must create
5529 that of the current frame to make it the live one. */
5531 for (i
= 16; i
< 32; i
++)
5532 if (save_local_or_in_reg_p (i
, leaf_function
))
5534 save_local_in_regs_p
= true;
5538 /* Calculate space needed for FP registers. */
5539 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5540 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5541 n_global_fp_regs
+= 2;
5544 && n_global_fp_regs
== 0
5546 && !save_local_in_regs_p
)
5547 frame_size
= apparent_frame_size
= 0;
5550 /* Start from the apparent frame size. */
5551 apparent_frame_size
= ROUND_UP (size
, 8) + n_global_fp_regs
* 4;
5553 /* We need to add the size of the outgoing argument area. */
5554 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5556 /* And that of the register window save area. */
5557 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5559 /* Finally, bump to the appropriate alignment. */
5560 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5563 /* Set up values for use in prologue and epilogue. */
5564 sparc_frame_size
= frame_size
;
5565 sparc_apparent_frame_size
= apparent_frame_size
;
5566 sparc_n_global_fp_regs
= n_global_fp_regs
;
5567 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5572 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5575 sparc_initial_elimination_offset (int to
)
5579 if (to
== STACK_POINTER_REGNUM
)
5580 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5584 offset
+= SPARC_STACK_BIAS
;
5588 /* Output any necessary .register pseudo-ops. */
5591 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5598 /* Check if %g[2367] were used without
5599 .register being printed for them already. */
5600 for (i
= 2; i
< 8; i
++)
5602 if (df_regs_ever_live_p (i
)
5603 && ! sparc_hard_reg_printed
[i
])
5605 sparc_hard_reg_printed
[i
] = 1;
5606 /* %g7 is used as TLS base register, use #ignore
5607 for it instead of #scratch. */
5608 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5609 i
== 7 ? "ignore" : "scratch");
5615 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5617 #if PROBE_INTERVAL > 4096
5618 #error Cannot use indexed addressing mode for stack probing
5621 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5622 inclusive. These are offsets from the current stack pointer.
5624 Note that we don't use the REG+REG addressing mode for the probes because
5625 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5626 so the advantages of having a single code win here. */
5629 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5631 rtx g1
= gen_rtx_REG (Pmode
, 1);
5633 /* See if we have a constant small number of probes to generate. If so,
5634 that's the easy case. */
5635 if (size
<= PROBE_INTERVAL
)
5637 emit_move_insn (g1
, GEN_INT (first
));
5638 emit_insn (gen_rtx_SET (g1
,
5639 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5640 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5643 /* The run-time loop is made up of 9 insns in the generic case while the
5644 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5645 else if (size
<= 4 * PROBE_INTERVAL
)
5649 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5650 emit_insn (gen_rtx_SET (g1
,
5651 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5652 emit_stack_probe (g1
);
5654 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5655 it exceeds SIZE. If only two probes are needed, this will not
5656 generate any code. Then probe at FIRST + SIZE. */
5657 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5659 emit_insn (gen_rtx_SET (g1
,
5660 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5661 emit_stack_probe (g1
);
5664 emit_stack_probe (plus_constant (Pmode
, g1
,
5665 (i
- PROBE_INTERVAL
) - size
));
5668 /* Otherwise, do the same as above, but in a loop. Note that we must be
5669 extra careful with variables wrapping around because we might be at
5670 the very top (or the very bottom) of the address space and we have
5671 to be able to handle this case properly; in particular, we use an
5672 equality test for the loop condition. */
5675 HOST_WIDE_INT rounded_size
;
5676 rtx g4
= gen_rtx_REG (Pmode
, 4);
5678 emit_move_insn (g1
, GEN_INT (first
));
5681 /* Step 1: round SIZE to the previous multiple of the interval. */
5683 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5684 emit_move_insn (g4
, GEN_INT (rounded_size
));
5687 /* Step 2: compute initial and final value of the loop counter. */
5689 /* TEST_ADDR = SP + FIRST. */
5690 emit_insn (gen_rtx_SET (g1
,
5691 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5693 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5694 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5699 while (TEST_ADDR != LAST_ADDR)
5701 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5705 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5706 until it is equal to ROUNDED_SIZE. */
5708 emit_insn (gen_probe_stack_range (Pmode
, g1
, g1
, g4
));
5711 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5712 that SIZE is equal to ROUNDED_SIZE. */
5714 if (size
!= rounded_size
)
5715 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5718 /* Make sure nothing is scheduled before we are done. */
5719 emit_insn (gen_blockage ());
5722 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5723 absolute addresses. */
5726 output_probe_stack_range (rtx reg1
, rtx reg2
)
5728 static int labelno
= 0;
5732 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5735 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5737 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5739 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5740 output_asm_insn ("add\t%0, %1, %0", xops
);
5742 /* Test if TEST_ADDR == LAST_ADDR. */
5744 output_asm_insn ("cmp\t%0, %1", xops
);
5746 /* Probe at TEST_ADDR and branch. */
5748 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5750 fputs ("\tbne\t", asm_out_file
);
5751 assemble_name_raw (asm_out_file
, loop_lab
);
5752 fputc ('\n', asm_out_file
);
5753 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5754 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5759 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5760 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5761 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5762 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5763 the action to be performed if it returns false. Return the new offset. */
5765 typedef bool (*sorr_pred_t
) (unsigned int, int);
5766 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5769 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5770 int offset
, int leaf_function
, sorr_pred_t save_p
,
5771 sorr_act_t action_true
, sorr_act_t action_false
)
5777 if (TARGET_ARCH64
&& high
<= 32)
5781 for (i
= low
; i
< high
; i
++)
5783 if (save_p (i
, leaf_function
))
5785 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5787 if (action_true
== SORR_SAVE
)
5789 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5790 RTX_FRAME_RELATED_P (insn
) = 1;
5792 else /* action_true == SORR_RESTORE */
5794 /* The frame pointer must be restored last since its old
5795 value may be used as base address for the frame. This
5796 is problematic in 64-bit mode only because of the lack
5797 of double-word load instruction. */
5798 if (i
== HARD_FRAME_POINTER_REGNUM
)
5801 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5805 else if (action_false
== SORR_ADVANCE
)
5811 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5812 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5817 for (i
= low
; i
< high
; i
+= 2)
5819 bool reg0
= save_p (i
, leaf_function
);
5820 bool reg1
= save_p (i
+ 1, leaf_function
);
5826 mode
= SPARC_INT_REG_P (i
) ? E_DImode
: E_DFmode
;
5831 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5836 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5842 if (action_false
== SORR_ADVANCE
)
5847 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5848 if (action_true
== SORR_SAVE
)
5850 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5851 RTX_FRAME_RELATED_P (insn
) = 1;
5855 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5857 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5858 RTX_FRAME_RELATED_P (set1
) = 1;
5860 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5862 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5863 RTX_FRAME_RELATED_P (set2
) = 1;
5864 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5865 gen_rtx_PARALLEL (VOIDmode
,
5866 gen_rtvec (2, set1
, set2
)));
5869 else /* action_true == SORR_RESTORE */
5870 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5872 /* Bump and round down to double word
5873 in case we already bumped by 4. */
5874 offset
= ROUND_DOWN (offset
+ 8, 8);
5881 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5884 emit_adjust_base_to_offset (rtx base
, int offset
)
5886 /* ??? This might be optimized a little as %g1 might already have a
5887 value close enough that a single add insn will do. */
5888 /* ??? Although, all of this is probably only a temporary fix because
5889 if %g1 can hold a function result, then sparc_expand_epilogue will
5890 lose (the result will be clobbered). */
5891 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5892 emit_move_insn (new_base
, GEN_INT (offset
));
5893 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5897 /* Emit code to save/restore call-saved global and FP registers. */
5900 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5902 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5904 base
= emit_adjust_base_to_offset (base
, offset
);
5909 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5910 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5911 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5912 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5915 /* Emit code to save/restore call-saved local and in registers. */
5918 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5920 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5922 base
= emit_adjust_base_to_offset (base
, offset
);
5926 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5927 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5930 /* Emit a window_save insn. */
5933 emit_window_save (rtx increment
)
5935 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5936 RTX_FRAME_RELATED_P (insn
) = 1;
5938 /* The incoming return address (%o7) is saved in %i7. */
5939 add_reg_note (insn
, REG_CFA_REGISTER
,
5940 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5942 INCOMING_RETURN_ADDR_REGNUM
)));
5944 /* The window save event. */
5945 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5947 /* The CFA is %fp, the hard frame pointer. */
5948 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5949 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5950 INCOMING_FRAME_SP_OFFSET
));
5955 /* Generate an increment for the stack pointer. */
5958 gen_stack_pointer_inc (rtx increment
)
5960 return gen_rtx_SET (stack_pointer_rtx
,
5961 gen_rtx_PLUS (Pmode
,
5966 /* Expand the function prologue. The prologue is responsible for reserving
5967 storage for the frame, saving the call-saved registers and loading the
5968 GOT register if needed. */
5971 sparc_expand_prologue (void)
5976 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5977 on the final value of the flag means deferring the prologue/epilogue
5978 expansion until just before the second scheduling pass, which is too
5979 late to emit multiple epilogues or return insns.
5981 Of course we are making the assumption that the value of the flag
5982 will not change between now and its final value. Of the three parts
5983 of the formula, only the last one can reasonably vary. Let's take a
5984 closer look, after assuming that the first two ones are set to true
5985 (otherwise the last value is effectively silenced).
5987 If only_leaf_regs_used returns false, the global predicate will also
5988 be false so the actual frame size calculated below will be positive.
5989 As a consequence, the save_register_window insn will be emitted in
5990 the instruction stream; now this insn explicitly references %fp
5991 which is not a leaf register so only_leaf_regs_used will always
5992 return false subsequently.
5994 If only_leaf_regs_used returns true, we hope that the subsequent
5995 optimization passes won't cause non-leaf registers to pop up. For
5996 example, the regrename pass has special provisions to not rename to
5997 non-leaf registers in a leaf function. */
5998 sparc_leaf_function_p
5999 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
6001 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
6003 if (flag_stack_usage_info
)
6004 current_function_static_stack_size
= size
;
6006 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
6007 || flag_stack_clash_protection
)
6009 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
6011 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
6012 sparc_emit_probe_stack_range (get_stack_check_protect (),
6013 size
- get_stack_check_protect ());
6016 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
6021 else if (sparc_leaf_function_p
)
6023 rtx size_int_rtx
= GEN_INT (-size
);
6026 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
6027 else if (size
<= 8192)
6029 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
6030 RTX_FRAME_RELATED_P (insn
) = 1;
6032 /* %sp is still the CFA register. */
6033 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6037 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
6038 emit_move_insn (size_rtx
, size_int_rtx
);
6039 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
6040 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
6041 gen_stack_pointer_inc (size_int_rtx
));
6044 RTX_FRAME_RELATED_P (insn
) = 1;
6046 /* Ensure no memory access is done before the frame is established. */
6047 emit_insn (gen_frame_blockage ());
6051 rtx size_int_rtx
= GEN_INT (-size
);
6054 emit_window_save (size_int_rtx
);
6055 else if (size
<= 8192)
6057 emit_window_save (GEN_INT (-4096));
6059 /* %sp is not the CFA register anymore. */
6060 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6063 emit_insn (gen_frame_blockage ());
6067 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
6068 emit_move_insn (size_rtx
, size_int_rtx
);
6069 emit_window_save (size_rtx
);
6073 if (sparc_leaf_function_p
)
6075 sparc_frame_base_reg
= stack_pointer_rtx
;
6076 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6080 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6081 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6084 if (sparc_n_global_fp_regs
> 0)
6085 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6086 sparc_frame_base_offset
6087 - sparc_apparent_frame_size
,
6090 /* Advertise that the data calculated just above are now valid. */
6091 sparc_prologue_data_valid_p
= true;
6094 /* Expand the function prologue. The prologue is responsible for reserving
6095 storage for the frame, saving the call-saved registers and loading the
6096 GOT register if needed. */
6099 sparc_flat_expand_prologue (void)
6104 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
6106 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
6108 if (flag_stack_usage_info
)
6109 current_function_static_stack_size
= size
;
6111 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
6112 || flag_stack_clash_protection
)
6114 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
6116 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
6117 sparc_emit_probe_stack_range (get_stack_check_protect (),
6118 size
- get_stack_check_protect ());
6121 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
6124 if (sparc_save_local_in_regs_p
)
6125 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
6132 rtx size_int_rtx
, size_rtx
;
6134 size_rtx
= size_int_rtx
= GEN_INT (-size
);
6136 /* We establish the frame (i.e. decrement the stack pointer) first, even
6137 if we use a frame pointer, because we cannot clobber any call-saved
6138 registers, including the frame pointer, if we haven't created a new
6139 register save area, for the sake of compatibility with the ABI. */
6141 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
6142 else if (size
<= 8192 && !frame_pointer_needed
)
6144 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
6145 RTX_FRAME_RELATED_P (insn
) = 1;
6146 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6150 size_rtx
= gen_rtx_REG (Pmode
, 1);
6151 emit_move_insn (size_rtx
, size_int_rtx
);
6152 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
6153 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6154 gen_stack_pointer_inc (size_int_rtx
));
6156 RTX_FRAME_RELATED_P (insn
) = 1;
6158 /* Ensure no memory access is done before the frame is established. */
6159 emit_insn (gen_frame_blockage ());
6161 if (frame_pointer_needed
)
6163 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
6164 gen_rtx_MINUS (Pmode
,
6167 RTX_FRAME_RELATED_P (insn
) = 1;
6169 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6170 gen_rtx_SET (hard_frame_pointer_rtx
,
6171 plus_constant (Pmode
, stack_pointer_rtx
,
6175 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6177 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
6178 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
6180 insn
= emit_move_insn (i7
, o7
);
6181 RTX_FRAME_RELATED_P (insn
) = 1;
6183 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
6185 /* Prevent this instruction from ever being considered dead,
6186 even if this function has no epilogue. */
6191 if (frame_pointer_needed
)
6193 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6194 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6198 sparc_frame_base_reg
= stack_pointer_rtx
;
6199 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6202 if (sparc_n_global_fp_regs
> 0)
6203 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6204 sparc_frame_base_offset
6205 - sparc_apparent_frame_size
,
6208 /* Advertise that the data calculated just above are now valid. */
6209 sparc_prologue_data_valid_p
= true;
6212 /* This function generates the assembly code for function entry, which boils
6213 down to emitting the necessary .register directives. */
6216 sparc_asm_function_prologue (FILE *file
)
6218 /* Check that the assumption we made in sparc_expand_prologue is valid. */
6220 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
6222 sparc_output_scratch_registers (file
);
6225 /* Expand the function epilogue, either normal or part of a sibcall.
6226 We emit all the instructions except the return or the call. */
6229 sparc_expand_epilogue (bool for_eh
)
6231 HOST_WIDE_INT size
= sparc_frame_size
;
6233 if (cfun
->calls_alloca
)
6234 emit_insn (gen_frame_blockage ());
6236 if (sparc_n_global_fp_regs
> 0)
6237 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6238 sparc_frame_base_offset
6239 - sparc_apparent_frame_size
,
6242 if (size
== 0 || for_eh
)
6244 else if (sparc_leaf_function_p
)
6246 /* Ensure no memory access is done after the frame is destroyed. */
6247 emit_insn (gen_frame_blockage ());
6250 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6251 else if (size
<= 8192)
6253 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6254 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6258 rtx reg
= gen_rtx_REG (Pmode
, 1);
6259 emit_move_insn (reg
, GEN_INT (size
));
6260 emit_insn (gen_stack_pointer_inc (reg
));
6265 /* Expand the function epilogue, either normal or part of a sibcall.
6266 We emit all the instructions except the return or the call. */
6269 sparc_flat_expand_epilogue (bool for_eh
)
6271 HOST_WIDE_INT size
= sparc_frame_size
;
6273 if (sparc_n_global_fp_regs
> 0)
6274 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6275 sparc_frame_base_offset
6276 - sparc_apparent_frame_size
,
6279 /* If we have a frame pointer, we'll need both to restore it before the
6280 frame is destroyed and use its current value in destroying the frame.
6281 Since we don't have an atomic way to do that in the flat window model,
6282 we save the current value into a temporary register (%g1). */
6283 if (frame_pointer_needed
&& !for_eh
)
6284 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
6286 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6287 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
6288 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
6290 if (sparc_save_local_in_regs_p
)
6291 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
6292 sparc_frame_base_offset
,
6295 if (size
== 0 || for_eh
)
6297 else if (frame_pointer_needed
)
6299 /* Ensure no memory access is done after the frame is destroyed. */
6300 emit_insn (gen_frame_blockage ());
6302 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
6307 emit_insn (gen_frame_blockage ());
6310 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6311 else if (size
<= 8192)
6313 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6314 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6318 rtx reg
= gen_rtx_REG (Pmode
, 1);
6319 emit_move_insn (reg
, GEN_INT (size
));
6320 emit_insn (gen_stack_pointer_inc (reg
));
6325 /* Return true if it is appropriate to emit `return' instructions in the
6326 body of a function. */
6329 sparc_can_use_return_insn_p (void)
6331 return sparc_prologue_data_valid_p
6332 && sparc_n_global_fp_regs
== 0
6334 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
6335 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
6338 /* This function generates the assembly code for function exit. */
6341 sparc_asm_function_epilogue (FILE *file
)
6343 /* If the last two instructions of a function are "call foo; dslot;"
6344 the return address might point to the first instruction in the next
6345 function and we have to output a dummy nop for the sake of sane
6346 backtraces in such cases. This is pointless for sibling calls since
6347 the return address is explicitly adjusted. */
6349 rtx_insn
*insn
= get_last_insn ();
6351 rtx last_real_insn
= prev_real_insn (insn
);
6353 && NONJUMP_INSN_P (last_real_insn
)
6354 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
6355 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
6358 && CALL_P (last_real_insn
)
6359 && !SIBLING_CALL_P (last_real_insn
))
6360 fputs("\tnop\n", file
);
6362 sparc_output_deferred_case_vectors ();
6365 /* Output a 'restore' instruction. */
6368 output_restore (rtx pat
)
6374 fputs ("\t restore\n", asm_out_file
);
6378 gcc_assert (GET_CODE (pat
) == SET
);
6380 operands
[0] = SET_DEST (pat
);
6381 pat
= SET_SRC (pat
);
6383 switch (GET_CODE (pat
))
6386 operands
[1] = XEXP (pat
, 0);
6387 operands
[2] = XEXP (pat
, 1);
6388 output_asm_insn (" restore %r1, %2, %Y0", operands
);
6391 operands
[1] = XEXP (pat
, 0);
6392 operands
[2] = XEXP (pat
, 1);
6393 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
6396 operands
[1] = XEXP (pat
, 0);
6397 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
6398 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
6402 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
6407 /* Output a return. */
6410 output_return (rtx_insn
*insn
)
6412 if (crtl
->calls_eh_return
)
6414 /* If the function uses __builtin_eh_return, the eh_return
6415 machinery occupies the delay slot. */
6416 gcc_assert (!final_sequence
);
6418 if (flag_delayed_branch
)
6420 if (!TARGET_FLAT
&& TARGET_V9
)
6421 fputs ("\treturn\t%i7+8\n", asm_out_file
);
6425 fputs ("\trestore\n", asm_out_file
);
6427 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
6430 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
6435 fputs ("\trestore\n", asm_out_file
);
6437 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
6438 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
6441 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
6443 /* This is a leaf or flat function so we don't have to bother restoring
6444 the register window, which frees us from dealing with the convoluted
6445 semantics of restore/return. We simply output the jump to the
6446 return address and the insn in the delay slot (if any). */
6448 return "jmp\t%%o7+%)%#";
6452 /* This is a regular function so we have to restore the register window.
6453 We may have a pending insn for the delay slot, which will be either
6454 combined with the 'restore' instruction or put in the delay slot of
6455 the 'return' instruction. */
6462 delay
= NEXT_INSN (insn
);
6465 pat
= PATTERN (delay
);
6467 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
6469 epilogue_renumber (&pat
, 0);
6470 return "return\t%%i7+%)%#";
6474 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6476 /* We're going to output the insn in the delay slot manually.
6477 Make sure to output its source location first. */
6478 PATTERN (delay
) = gen_blockage ();
6479 INSN_CODE (delay
) = -1;
6480 final_scan_insn (delay
, asm_out_file
, optimize
, 0, NULL
);
6481 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6483 output_restore (pat
);
6488 /* The delay slot is empty. */
6490 return "return\t%%i7+%)\n\t nop";
6491 else if (flag_delayed_branch
)
6492 return "jmp\t%%i7+%)\n\t restore";
6494 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6501 /* Output a sibling call. */
6504 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6508 gcc_assert (flag_delayed_branch
);
6510 operands
[0] = call_operand
;
6512 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6514 /* This is a leaf or flat function so we don't have to bother restoring
6515 the register window. We simply output the jump to the function and
6516 the insn in the delay slot (if any). */
6518 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6521 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6524 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6525 it into branch if possible. */
6526 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6531 /* This is a regular function so we have to restore the register window.
6532 We may have a pending insn for the delay slot, which will be combined
6533 with the 'restore' instruction. */
6535 output_asm_insn ("call\t%a0, 0", operands
);
6542 delay
= NEXT_INSN (insn
);
6545 pat
= PATTERN (delay
);
6547 /* We're going to output the insn in the delay slot manually.
6548 Make sure to output its source location first. */
6549 PATTERN (delay
) = gen_blockage ();
6550 INSN_CODE (delay
) = -1;
6551 final_scan_insn (delay
, asm_out_file
, optimize
, 0, NULL
);
6552 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6554 output_restore (pat
);
6557 output_restore (NULL_RTX
);
6563 /* Functions for handling argument passing.
6565 For 32-bit, the first 6 args are normally in registers and the rest are
6566 pushed. Any arg that starts within the first 6 words is at least
6567 partially passed in a register unless its data type forbids.
6569 For 64-bit, the argument registers are laid out as an array of 16 elements
6570 and arguments are added sequentially. The first 6 int args and up to the
6571 first 16 fp args (depending on size) are passed in regs.
6573 Slot Stack Integral Float Float in structure Double Long Double
6574 ---- ----- -------- ----- ------------------ ------ -----------
6575 15 [SP+248] %f31 %f30,%f31 %d30
6576 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6577 13 [SP+232] %f27 %f26,%f27 %d26
6578 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6579 11 [SP+216] %f23 %f22,%f23 %d22
6580 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6581 9 [SP+200] %f19 %f18,%f19 %d18
6582 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6583 7 [SP+184] %f15 %f14,%f15 %d14
6584 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6585 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6586 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6587 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6588 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6589 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6590 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6592 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6594 Integral arguments are always passed as 64-bit quantities appropriately
6597 Passing of floating point values is handled as follows.
6598 If a prototype is in scope:
6599 If the value is in a named argument (i.e. not a stdarg function or a
6600 value not part of the `...') then the value is passed in the appropriate
6602 If the value is part of the `...' and is passed in one of the first 6
6603 slots then the value is passed in the appropriate int reg.
6604 If the value is part of the `...' and is not passed in one of the first 6
6605 slots then the value is passed in memory.
6606 If a prototype is not in scope:
6607 If the value is one of the first 6 arguments the value is passed in the
6608 appropriate integer reg and the appropriate fp reg.
6609 If the value is not one of the first 6 arguments the value is passed in
6610 the appropriate fp reg and in memory.
6613 Summary of the calling conventions implemented by GCC on the SPARC:
6616 size argument return value
6618 small integer <4 int. reg. int. reg.
6619 word 4 int. reg. int. reg.
6620 double word 8 int. reg. int. reg.
6622 _Complex small integer <8 int. reg. int. reg.
6623 _Complex word 8 int. reg. int. reg.
6624 _Complex double word 16 memory int. reg.
6626 vector integer <=8 int. reg. FP reg.
6627 vector integer >8 memory memory
6629 float 4 int. reg. FP reg.
6630 double 8 int. reg. FP reg.
6631 long double 16 memory memory
6633 _Complex float 8 memory FP reg.
6634 _Complex double 16 memory FP reg.
6635 _Complex long double 32 memory FP reg.
6637 vector float any memory memory
6639 aggregate any memory memory
6644 size argument return value
6646 small integer <8 int. reg. int. reg.
6647 word 8 int. reg. int. reg.
6648 double word 16 int. reg. int. reg.
6650 _Complex small integer <16 int. reg. int. reg.
6651 _Complex word 16 int. reg. int. reg.
6652 _Complex double word 32 memory int. reg.
6654 vector integer <=16 FP reg. FP reg.
6655 vector integer 16<s<=32 memory FP reg.
6656 vector integer >32 memory memory
6658 float 4 FP reg. FP reg.
6659 double 8 FP reg. FP reg.
6660 long double 16 FP reg. FP reg.
6662 _Complex float 8 FP reg. FP reg.
6663 _Complex double 16 FP reg. FP reg.
6664 _Complex long double 32 memory FP reg.
6666 vector float <=16 FP reg. FP reg.
6667 vector float 16<s<=32 memory FP reg.
6668 vector float >32 memory memory
6670 aggregate <=16 reg. reg.
6671 aggregate 16<s<=32 memory reg.
6672 aggregate >32 memory memory
6676 Note #1: complex floating-point types follow the extended SPARC ABIs as
6677 implemented by the Sun compiler.
6679 Note #2: integer vector types follow the scalar floating-point types
6680 conventions to match what is implemented by the Sun VIS SDK.
6682 Note #3: floating-point vector types follow the aggregate types
6686 /* Maximum number of int regs for args. */
6687 #define SPARC_INT_ARG_MAX 6
6688 /* Maximum number of fp regs for args. */
6689 #define SPARC_FP_ARG_MAX 16
6690 /* Number of words (partially) occupied for a given size in units. */
6691 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6693 /* Handle the INIT_CUMULATIVE_ARGS macro.
6694 Initialize a variable CUM of type CUMULATIVE_ARGS
6695 for a call to a function whose data type is FNTYPE.
6696 For a library call, FNTYPE is 0. */
6699 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6702 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6703 cum
->libcall_p
= !fntype
;
6706 /* Handle promotion of pointer and integer arguments. */
6709 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6710 int *punsignedp
, const_tree
, int)
6712 if (type
&& POINTER_TYPE_P (type
))
6714 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6718 /* Integral arguments are passed as full words, as per the ABI. */
6719 if (GET_MODE_CLASS (mode
) == MODE_INT
6720 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6726 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6729 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6731 return TARGET_ARCH64
? true : false;
6734 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6735 Specify whether to pass the argument by reference. */
6738 sparc_pass_by_reference (cumulative_args_t
, const function_arg_info
&arg
)
6740 tree type
= arg
.type
;
6741 machine_mode mode
= arg
.mode
;
6743 /* Original SPARC 32-bit ABI says that structures and unions,
6744 and quad-precision floats are passed by reference.
6745 All other base types are passed in registers.
6747 Extended ABI (as implemented by the Sun compiler) says that all
6748 complex floats are passed by reference. Pass complex integers
6749 in registers up to 8 bytes. More generally, enforce the 2-word
6750 cap for passing arguments in registers.
6752 Vector ABI (as implemented by the Sun VIS SDK) says that integer
6753 vectors are passed like floats of the same size, that is in
6754 registers up to 8 bytes. Pass all vector floats by reference
6755 like structure and unions. */
6756 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6758 /* Catch CDImode, TFmode, DCmode and TCmode. */
6759 || GET_MODE_SIZE (mode
) > 8
6761 && VECTOR_TYPE_P (type
)
6762 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6764 /* Original SPARC 64-bit ABI says that structures and unions
6765 smaller than 16 bytes are passed in registers, as well as
6766 all other base types.
6768 Extended ABI (as implemented by the Sun compiler) says that
6769 complex floats are passed in registers up to 16 bytes. Pass
6770 all complex integers in registers up to 16 bytes. More generally,
6771 enforce the 2-word cap for passing arguments in registers.
6773 Vector ABI (as implemented by the Sun VIS SDK) says that integer
6774 vectors are passed like floats of the same size, that is in
6775 registers (up to 16 bytes). Pass all vector floats like structure
6778 && (AGGREGATE_TYPE_P (type
) || VECTOR_TYPE_P (type
))
6779 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6780 /* Catch CTImode and TCmode. */
6781 || GET_MODE_SIZE (mode
) > 16);
6784 /* Traverse the record TYPE recursively and call FUNC on its fields.
6785 NAMED is true if this is for a named parameter. DATA is passed
6786 to FUNC for each field. OFFSET is the starting position and
6787 PACKED is true if we are inside a packed record. */
6789 template <typename T
, void Func (const_tree
, int, bool, T
*)>
6791 traverse_record_type (const_tree type
, bool named
, T
*data
,
6792 int offset
= 0, bool packed
= false)
6794 /* The ABI obviously doesn't specify how packed structures are passed.
6795 These are passed in integer regs if possible, otherwise memory. */
6797 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6798 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6804 /* Walk the real fields, but skip those with no size or a zero size.
6805 ??? Fields with variable offset are handled as having zero offset. */
6806 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6807 if (TREE_CODE (field
) == FIELD_DECL
)
6809 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6812 int bitpos
= offset
;
6813 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6814 bitpos
+= int_bit_position (field
);
6816 tree field_type
= TREE_TYPE (field
);
6817 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6818 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6823 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6824 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6830 /* Handle recursive register classifying for structure layout. */
6834 bool fp_regs
; /* true if field eligible to FP registers. */
6835 bool fp_regs_in_first_word
; /* true if such field in first word. */
6838 /* A subroutine of function_arg_slotno. Classify the field. */
6841 classify_registers (const_tree
, int bitpos
, bool fp
, classify_data_t
*data
)
6845 data
->fp_regs
= true;
6846 if (bitpos
< BITS_PER_WORD
)
6847 data
->fp_regs_in_first_word
= true;
6851 /* Compute the slot number to pass an argument in.
6852 Return the slot number or -1 if passing on the stack.
6854 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6855 the preceding args and about the function being called.
6856 MODE is the argument's machine mode.
6857 TYPE is the data type of the argument (as a tree).
6858 This is null for libcalls where that information may
6860 NAMED is nonzero if this argument is a named parameter
6861 (otherwise it is an extra parameter matching an ellipsis).
6862 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6863 *PREGNO records the register number to use if scalar type.
6864 *PPADDING records the amount of padding needed in words. */
6867 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6868 const_tree type
, bool named
, bool incoming
,
6869 int *pregno
, int *ppadding
)
6872 = incoming
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
6873 int slotno
= cum
->words
, regno
;
6874 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6876 /* Silence warnings in the callers. */
6880 if (type
&& TREE_ADDRESSABLE (type
))
6883 /* In 64-bit mode, objects requiring 16-byte alignment get it. */
6885 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6886 && (slotno
& 1) != 0)
6894 /* Vector types deserve special treatment because they are polymorphic wrt
6895 their mode, depending upon whether VIS instructions are enabled. */
6896 if (type
&& VECTOR_TYPE_P (type
))
6898 if (SCALAR_FLOAT_TYPE_P (TREE_TYPE (type
)))
6900 /* The SPARC port defines no floating-point vector modes. */
6901 gcc_assert (mode
== BLKmode
);
6905 /* Integer vector types should either have a vector
6906 mode or an integral mode, because we are guaranteed
6907 by pass_by_reference that their size is not greater
6908 than 16 bytes and TImode is 16-byte wide. */
6909 gcc_assert (mode
!= BLKmode
);
6911 /* Integer vectors are handled like floats as per
6913 mclass
= MODE_FLOAT
;
6920 case MODE_COMPLEX_FLOAT
:
6921 case MODE_VECTOR_INT
:
6922 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6924 /* If all arg slots are filled, then must pass on stack. */
6925 if (slotno
>= SPARC_FP_ARG_MAX
)
6928 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6929 /* Arguments filling only one single FP register are
6930 right-justified in the outer double FP register. */
6931 if (GET_MODE_SIZE (mode
) <= 4)
6938 case MODE_COMPLEX_INT
:
6939 /* If all arg slots are filled, then must pass on stack. */
6940 if (slotno
>= SPARC_INT_ARG_MAX
)
6943 regno
= regbase
+ slotno
;
6947 /* MODE is VOIDmode when generating the actual call. */
6948 if (mode
== VOIDmode
)
6951 if (TARGET_64BIT
&& TARGET_FPU
&& named
6953 && (TREE_CODE (type
) == RECORD_TYPE
|| VECTOR_TYPE_P (type
)))
6955 /* If all arg slots are filled, then must pass on stack. */
6956 if (slotno
>= SPARC_FP_ARG_MAX
)
6959 if (TREE_CODE (type
) == RECORD_TYPE
)
6961 classify_data_t data
= { false, false };
6962 traverse_record_type
<classify_data_t
, classify_registers
>
6963 (type
, named
, &data
);
6967 /* If all FP slots are filled except for the last one and
6968 there is no FP field in the first word, then must pass
6970 if (slotno
>= SPARC_FP_ARG_MAX
- 1
6971 && !data
.fp_regs_in_first_word
)
6976 /* If all int slots are filled, then must pass on stack. */
6977 if (slotno
>= SPARC_INT_ARG_MAX
)
6981 /* PREGNO isn't set since both int and FP regs can be used. */
6985 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6989 /* If all arg slots are filled, then must pass on stack. */
6990 if (slotno
>= SPARC_INT_ARG_MAX
)
6993 regno
= regbase
+ slotno
;
7005 /* Handle recursive register counting/assigning for structure layout. */
7009 int slotno
; /* slot number of the argument. */
7010 int regbase
; /* regno of the base register. */
7011 int intoffset
; /* offset of the first pending integer field. */
7012 int nregs
; /* number of words passed in registers. */
7013 bool stack
; /* true if part of the argument is on the stack. */
7014 rtx ret
; /* return expression being built. */
7017 /* A subroutine of function_arg_record_value. Compute the number of integer
7018 registers to be assigned between PARMS->intoffset and BITPOS. Return
7019 true if at least one integer register is assigned or false otherwise. */
7022 compute_int_layout (int bitpos
, assign_data_t
*data
, int *pnregs
)
7024 if (data
->intoffset
< 0)
7027 const int intoffset
= data
->intoffset
;
7028 data
->intoffset
= -1;
7030 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
7031 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
7032 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
7033 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
7035 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
7037 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
7039 /* We need to pass this field (partly) on the stack. */
7050 /* A subroutine of function_arg_record_value. Compute the number and the mode
7051 of the FP registers to be assigned for FIELD. Return true if at least one
7052 FP register is assigned or false otherwise. */
7055 compute_fp_layout (const_tree field
, int bitpos
, assign_data_t
*data
,
7056 int *pnregs
, machine_mode
*pmode
)
7058 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
7059 machine_mode mode
= DECL_MODE (field
);
7062 /* Slots are counted as words while regs are counted as having the size of
7063 the (inner) mode. */
7064 if (VECTOR_TYPE_P (TREE_TYPE (field
)) && mode
== BLKmode
)
7066 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
7067 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
7069 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
7071 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
7077 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
7079 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
7081 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
7082 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
7084 /* We need to pass this field (partly) on the stack. */
7096 /* A subroutine of function_arg_record_value. Count the number of registers
7097 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
7100 count_registers (const_tree field
, int bitpos
, bool fp
, assign_data_t
*data
)
7107 if (compute_int_layout (bitpos
, data
, &nregs
))
7108 data
->nregs
+= nregs
;
7110 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7111 data
->nregs
+= nregs
;
7115 if (data
->intoffset
< 0)
7116 data
->intoffset
= bitpos
;
7120 /* A subroutine of function_arg_record_value. Assign the bits of the
7121 structure between PARMS->intoffset and BITPOS to integer registers. */
7124 assign_int_registers (int bitpos
, assign_data_t
*data
)
7126 int intoffset
= data
->intoffset
;
7130 if (!compute_int_layout (bitpos
, data
, &nregs
))
7133 /* If this is the trailing part of a word, only load that much into
7134 the register. Otherwise load the whole register. Note that in
7135 the latter case we may pick up unwanted bits. It's not a problem
7136 at the moment but may wish to revisit. */
7137 if (intoffset
% BITS_PER_WORD
!= 0)
7138 mode
= smallest_int_mode_for_size (BITS_PER_WORD
7139 - intoffset
% BITS_PER_WORD
);
7143 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
7144 unsigned int regno
= data
->regbase
+ this_slotno
;
7145 intoffset
/= BITS_PER_UNIT
;
7149 rtx reg
= gen_rtx_REG (mode
, regno
);
7150 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7151 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
7155 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
7157 while (--nregs
> 0);
7160 /* A subroutine of function_arg_record_value. Assign FIELD at position
7161 BITPOS to FP registers. */
7164 assign_fp_registers (const_tree field
, int bitpos
, assign_data_t
*data
)
7169 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7172 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
7173 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
7174 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
7176 int pos
= bitpos
/ BITS_PER_UNIT
;
7180 rtx reg
= gen_rtx_REG (mode
, regno
);
7181 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7182 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
7184 regno
+= GET_MODE_SIZE (mode
) / 4;
7185 pos
+= GET_MODE_SIZE (mode
);
7187 while (--nregs
> 0);
7190 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
7191 the structure between PARMS->intoffset and BITPOS to registers. */
7194 assign_registers (const_tree field
, int bitpos
, bool fp
, assign_data_t
*data
)
7198 assign_int_registers (bitpos
, data
);
7200 assign_fp_registers (field
, bitpos
, data
);
7204 if (data
->intoffset
< 0)
7205 data
->intoffset
= bitpos
;
7209 /* Used by function_arg and function_value to implement the complex
7210 conventions of the 64-bit ABI for passing and returning structures.
7211 Return an expression valid as a return value for the FUNCTION_ARG
7212 and TARGET_FUNCTION_VALUE.
7214 TYPE is the data type of the argument (as a tree).
7215 This is null for libcalls where that information may
7217 MODE is the argument's machine mode.
7218 SLOTNO is the index number of the argument's slot in the parameter array.
7219 NAMED is true if this argument is a named parameter
7220 (otherwise it is an extra parameter matching an ellipsis).
7221 REGBASE is the regno of the base register for the parameter array. */
7224 function_arg_record_value (const_tree type
, machine_mode mode
,
7225 int slotno
, bool named
, int regbase
)
7227 const int size
= int_size_in_bytes (type
);
7231 data
.slotno
= slotno
;
7232 data
.regbase
= regbase
;
7234 /* Count how many registers we need. */
7238 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
7240 /* Take into account pending integer fields. */
7241 if (compute_int_layout (size
* BITS_PER_UNIT
, &data
, &nregs
))
7242 data
.nregs
+= nregs
;
7244 /* Allocate the vector and handle some annoying special cases. */
7249 /* ??? Empty structure has no value? Duh? */
7252 /* Though there's nothing really to store, return a word register
7253 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
7254 leads to breakage due to the fact that there are zero bytes to
7256 return gen_rtx_REG (mode
, regbase
);
7259 /* ??? C++ has structures with no fields, and yet a size. Give up
7260 for now and pass everything back in integer registers. */
7261 nregs
= CEIL_NWORDS (size
);
7262 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
7263 nregs
= SPARC_INT_ARG_MAX
- slotno
;
7266 gcc_assert (nregs
> 0);
7268 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
7270 /* If at least one field must be passed on the stack, generate
7271 (parallel [(expr_list (nil) ...) ...]) so that all fields will
7272 also be passed on the stack. We can't do much better because the
7273 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
7274 of structures for which the fields passed exclusively in registers
7275 are not at the beginning of the structure. */
7277 XVECEXP (data
.ret
, 0, 0)
7278 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7280 /* Assign the registers. */
7283 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
7285 /* Assign pending integer fields. */
7286 assign_int_registers (size
* BITS_PER_UNIT
, &data
);
7288 gcc_assert (data
.nregs
== nregs
);
7293 /* Used by function_arg and function_value to implement the conventions
7294 of the 64-bit ABI for passing and returning unions.
7295 Return an expression valid as a return value for the FUNCTION_ARG
7296 and TARGET_FUNCTION_VALUE.
7298 SIZE is the size in bytes of the union.
7299 MODE is the argument's machine mode.
7300 SLOTNO is the index number of the argument's slot in the parameter array.
7301 REGNO is the hard register the union will be passed in. */
7304 function_arg_union_value (int size
, machine_mode mode
, int slotno
, int regno
)
7306 unsigned int nwords
;
7308 /* See comment in function_arg_record_value for empty structures. */
7310 return gen_rtx_REG (mode
, regno
);
7312 if (slotno
== SPARC_INT_ARG_MAX
- 1)
7315 nwords
= CEIL_NWORDS (size
);
7317 rtx regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
7319 /* Unions are passed left-justified. */
7320 for (unsigned int i
= 0; i
< nwords
; i
++)
7321 XVECEXP (regs
, 0, i
)
7322 = gen_rtx_EXPR_LIST (VOIDmode
,
7323 gen_rtx_REG (word_mode
, regno
+ i
),
7324 GEN_INT (UNITS_PER_WORD
* i
));
7329 /* Used by function_arg and function_value to implement the conventions
7330 of the 64-bit ABI for passing and returning BLKmode vectors.
7331 Return an expression valid as a return value for the FUNCTION_ARG
7332 and TARGET_FUNCTION_VALUE.
7334 SIZE is the size in bytes of the vector.
7335 SLOTNO is the index number of the argument's slot in the parameter array.
7336 NAMED is true if this argument is a named parameter
7337 (otherwise it is an extra parameter matching an ellipsis).
7338 REGNO is the hard register the vector will be passed in. */
7341 function_arg_vector_value (int size
, int slotno
, bool named
, int regno
)
7343 const int mult
= (named
? 2 : 1);
7344 unsigned int nwords
;
7346 if (slotno
== (named
? SPARC_FP_ARG_MAX
: SPARC_INT_ARG_MAX
) - 1)
7349 nwords
= CEIL_NWORDS (size
);
7351 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nwords
));
7353 if (size
< UNITS_PER_WORD
)
7354 XVECEXP (regs
, 0, 0)
7355 = gen_rtx_EXPR_LIST (VOIDmode
,
7356 gen_rtx_REG (SImode
, regno
),
7359 for (unsigned int i
= 0; i
< nwords
; i
++)
7360 XVECEXP (regs
, 0, i
)
7361 = gen_rtx_EXPR_LIST (VOIDmode
,
7362 gen_rtx_REG (word_mode
, regno
+ i
* mult
),
7363 GEN_INT (i
* UNITS_PER_WORD
));
7368 /* Determine where to put an argument to a function.
7369 Value is zero to push the argument on the stack,
7370 or a hard register in which to store the argument.
7372 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7373 the preceding args and about the function being called.
7374 ARG is a description of the argument.
7375 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
7376 TARGET_FUNCTION_INCOMING_ARG. */
7379 sparc_function_arg_1 (cumulative_args_t cum_v
, const function_arg_info
&arg
,
7382 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7384 = incoming
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
7385 int slotno
, regno
, padding
;
7386 tree type
= arg
.type
;
7387 machine_mode mode
= arg
.mode
;
7388 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7389 bool named
= arg
.named
;
7392 = function_arg_slotno (cum
, mode
, type
, named
, incoming
, ®no
, &padding
);
7396 /* Integer vectors are handled like floats as per the Sun VIS SDK. */
7397 if (type
&& VECTOR_INTEGER_TYPE_P (type
))
7398 mclass
= MODE_FLOAT
;
7401 return gen_rtx_REG (mode
, regno
);
7403 /* Structures up to 16 bytes in size are passed in arg slots on the stack
7404 and are promoted to registers if possible. */
7405 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
7407 const int size
= int_size_in_bytes (type
);
7408 gcc_assert (size
<= 16);
7410 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
7413 /* Unions up to 16 bytes in size are passed in integer registers. */
7414 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
7416 const int size
= int_size_in_bytes (type
);
7417 gcc_assert (size
<= 16);
7419 return function_arg_union_value (size
, mode
, slotno
, regno
);
7422 /* Floating-point vectors up to 16 bytes are passed in registers. */
7423 else if (type
&& VECTOR_TYPE_P (type
) && mode
== BLKmode
)
7425 const int size
= int_size_in_bytes (type
);
7426 gcc_assert (size
<= 16);
7428 return function_arg_vector_value (size
, slotno
, named
, regno
);
7431 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
7432 but also have the slot allocated for them.
7433 If no prototype is in scope fp values in register slots get passed
7434 in two places, either fp regs and int regs or fp regs and memory. */
7435 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7436 && SPARC_FP_REG_P (regno
))
7438 rtx reg
= gen_rtx_REG (mode
, regno
);
7439 if (cum
->prototype_p
|| cum
->libcall_p
)
7445 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
7449 /* On incoming, we don't need to know that the value
7450 is passed in %f0 and %i0, and it confuses other parts
7451 causing needless spillage even on the simplest cases. */
7455 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
7456 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
7458 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7459 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
7461 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7465 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7466 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7467 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7472 /* All other aggregate types are passed in an integer register in a mode
7473 corresponding to the size of the type. */
7474 else if (type
&& AGGREGATE_TYPE_P (type
))
7476 const int size
= int_size_in_bytes (type
);
7477 gcc_assert (size
<= 16);
7479 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7482 return gen_rtx_REG (mode
, regno
);
7485 /* Handle the TARGET_FUNCTION_ARG target hook. */
7488 sparc_function_arg (cumulative_args_t cum
, const function_arg_info
&arg
)
7490 return sparc_function_arg_1 (cum
, arg
, false);
7493 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7496 sparc_function_incoming_arg (cumulative_args_t cum
,
7497 const function_arg_info
&arg
)
7499 return sparc_function_arg_1 (cum
, arg
, true);
7502 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7505 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
7507 return ((TARGET_ARCH64
7508 && (GET_MODE_ALIGNMENT (mode
) == 128
7509 || (type
&& TYPE_ALIGN (type
) == 128)))
7514 /* For an arg passed partly in registers and partly in memory,
7515 this is the number of bytes of registers used.
7516 For args passed entirely in registers or entirely in memory, zero.
7518 Any arg that starts in the first 6 regs but won't entirely fit in them
7519 needs partial registers on v8. On v9, structures with integer
7520 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7521 values that begin in the last fp reg [where "last fp reg" varies with the
7522 mode] will be split between that reg and memory. */
7525 sparc_arg_partial_bytes (cumulative_args_t cum
, const function_arg_info
&arg
)
7527 int slotno
, regno
, padding
;
7529 /* We pass false for incoming here, it doesn't matter. */
7530 slotno
= function_arg_slotno (get_cumulative_args (cum
), arg
.mode
, arg
.type
,
7531 arg
.named
, false, ®no
, &padding
);
7538 /* We are guaranteed by pass_by_reference that the size of the
7539 argument is not greater than 8 bytes, so we only need to return
7540 one word if the argument is partially passed in registers. */
7541 const int size
= GET_MODE_SIZE (arg
.mode
);
7543 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_INT_ARG_MAX
- 1)
7544 return UNITS_PER_WORD
;
7548 /* We are guaranteed by pass_by_reference that the size of the
7549 argument is not greater than 16 bytes, so we only need to return
7550 one word if the argument is partially passed in registers. */
7551 if (arg
.aggregate_type_p ())
7553 const int size
= int_size_in_bytes (arg
.type
);
7555 if (size
> UNITS_PER_WORD
7556 && (slotno
== SPARC_INT_ARG_MAX
- 1
7557 || slotno
== SPARC_FP_ARG_MAX
- 1))
7558 return UNITS_PER_WORD
;
7560 else if (GET_MODE_CLASS (arg
.mode
) == MODE_COMPLEX_INT
7561 || ((GET_MODE_CLASS (arg
.mode
) == MODE_COMPLEX_FLOAT
7562 || (arg
.type
&& VECTOR_TYPE_P (arg
.type
)))
7563 && !(TARGET_FPU
&& arg
.named
)))
7565 const int size
= (arg
.type
&& VECTOR_FLOAT_TYPE_P (arg
.type
))
7566 ? int_size_in_bytes (arg
.type
)
7567 : GET_MODE_SIZE (arg
.mode
);
7569 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_INT_ARG_MAX
- 1)
7570 return UNITS_PER_WORD
;
7572 else if (GET_MODE_CLASS (arg
.mode
) == MODE_COMPLEX_FLOAT
7573 || (arg
.type
&& VECTOR_TYPE_P (arg
.type
)))
7575 const int size
= (arg
.type
&& VECTOR_FLOAT_TYPE_P (arg
.type
))
7576 ? int_size_in_bytes (arg
.type
)
7577 : GET_MODE_SIZE (arg
.mode
);
7579 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_FP_ARG_MAX
- 1)
7580 return UNITS_PER_WORD
;
7587 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7588 Update the data in CUM to advance over argument ARG. */
7591 sparc_function_arg_advance (cumulative_args_t cum_v
,
7592 const function_arg_info
&arg
)
7594 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7595 tree type
= arg
.type
;
7596 machine_mode mode
= arg
.mode
;
7599 /* We pass false for incoming here, it doesn't matter. */
7600 function_arg_slotno (cum
, mode
, type
, arg
.named
, false, ®no
, &padding
);
7602 /* If argument requires leading padding, add it. */
7603 cum
->words
+= padding
;
7606 cum
->words
+= CEIL_NWORDS (GET_MODE_SIZE (mode
));
7609 /* For types that can have BLKmode, get the size from the type. */
7610 if (type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7612 const int size
= int_size_in_bytes (type
);
7614 /* See comment in function_arg_record_value for empty structures. */
7618 cum
->words
+= CEIL_NWORDS (size
);
7621 cum
->words
+= CEIL_NWORDS (GET_MODE_SIZE (mode
));
7625 /* Implement TARGET_FUNCTION_ARG_PADDING. For the 64-bit ABI structs
7626 are always stored left shifted in their argument slot. */
7628 static pad_direction
7629 sparc_function_arg_padding (machine_mode mode
, const_tree type
)
7631 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7634 /* Fall back to the default. */
7635 return default_function_arg_padding (mode
, type
);
7638 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7639 Specify whether to return the return value in memory. */
7642 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7645 /* Original SPARC 32-bit ABI says that structures and unions, and
7646 quad-precision floats are returned in memory. But note that the
7647 first part is implemented through -fpcc-struct-return being the
7648 default, so here we only implement -freg-struct-return instead.
7649 All other base types are returned in registers.
7651 Extended ABI (as implemented by the Sun compiler) says that
7652 all complex floats are returned in registers (8 FP registers
7653 at most for '_Complex long double'). Return all complex integers
7654 in registers (4 at most for '_Complex long long').
7656 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7657 integers are returned like floats of the same size, that is in
7658 registers up to 8 bytes and in memory otherwise. Return all
7659 vector floats in memory like structure and unions; note that
7660 they always have BLKmode like the latter. */
7661 return (TYPE_MODE (type
) == BLKmode
7662 || TYPE_MODE (type
) == TFmode
7663 || (TREE_CODE (type
) == VECTOR_TYPE
7664 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7666 /* Original SPARC 64-bit ABI says that structures and unions
7667 smaller than 32 bytes are returned in registers, as well as
7668 all other base types.
7670 Extended ABI (as implemented by the Sun compiler) says that all
7671 complex floats are returned in registers (8 FP registers at most
7672 for '_Complex long double'). Return all complex integers in
7673 registers (4 at most for '_Complex TItype').
7675 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7676 integers are returned like floats of the same size, that is in
7677 registers. Return all vector floats like structure and unions;
7678 note that they always have BLKmode like the latter. */
7679 return (TYPE_MODE (type
) == BLKmode
7680 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7683 /* Handle the TARGET_STRUCT_VALUE target hook.
7684 Return where to find the structure return value address. */
7687 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7696 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7697 STRUCT_VALUE_OFFSET
));
7699 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7700 STRUCT_VALUE_OFFSET
));
7702 /* Only follow the SPARC ABI for fixed-size structure returns.
7703 Variable size structure returns are handled per the normal
7704 procedures in GCC. This is enabled by -mstd-struct-return */
7706 && sparc_std_struct_return
7707 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7708 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7710 /* We must check and adjust the return address, as it is optional
7711 as to whether the return object is really provided. */
7712 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7713 rtx scratch
= gen_reg_rtx (SImode
);
7714 rtx_code_label
*endlab
= gen_label_rtx ();
7716 /* Calculate the return object size. */
7717 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7718 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7719 /* Construct a temporary return value. */
7721 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7723 /* Implement SPARC 32-bit psABI callee return struct checking:
7725 Fetch the instruction where we will return to and see if
7726 it's an unimp instruction (the most significant 10 bits
7728 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7729 plus_constant (Pmode
,
7731 /* Assume the size is valid and pre-adjust. */
7732 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7733 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7735 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7736 /* Write the address of the memory pointed to by temp_val into
7737 the memory pointed to by mem. */
7738 emit_move_insn (mem
, XEXP (temp_val
, 0));
7739 emit_label (endlab
);
7746 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7747 For v9, function return values are subject to the same rules as arguments,
7748 except that up to 32 bytes may be returned in registers. */
7751 sparc_function_value_1 (const_tree type
, machine_mode mode
, bool outgoing
)
7753 /* Beware that the two values are swapped here wrt function_arg. */
7755 = outgoing
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
7756 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7759 /* Integer vectors are handled like floats as per the Sun VIS SDK.
7760 Note that integer vectors larger than 16 bytes have BLKmode so
7761 they need to be handled like floating-point vectors below. */
7762 if (type
&& VECTOR_INTEGER_TYPE_P (type
) && mode
!= BLKmode
)
7763 mclass
= MODE_FLOAT
;
7765 if (TARGET_ARCH64
&& type
)
7767 /* Structures up to 32 bytes in size are returned in registers. */
7768 if (TREE_CODE (type
) == RECORD_TYPE
)
7770 const int size
= int_size_in_bytes (type
);
7771 gcc_assert (size
<= 32);
7773 return function_arg_record_value (type
, mode
, 0, true, regbase
);
7776 /* Unions up to 32 bytes in size are returned in integer registers. */
7777 else if (TREE_CODE (type
) == UNION_TYPE
)
7779 const int size
= int_size_in_bytes (type
);
7780 gcc_assert (size
<= 32);
7782 return function_arg_union_value (size
, mode
, 0, regbase
);
7785 /* Vectors up to 32 bytes are returned in FP registers. */
7786 else if (VECTOR_TYPE_P (type
) && mode
== BLKmode
)
7788 const int size
= int_size_in_bytes (type
);
7789 gcc_assert (size
<= 32);
7791 return function_arg_vector_value (size
, 0, true, SPARC_FP_ARG_FIRST
);
7794 /* Objects that require it are returned in FP registers. */
7795 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7798 /* All other aggregate types are returned in an integer register in a
7799 mode corresponding to the size of the type. */
7800 else if (AGGREGATE_TYPE_P (type
))
7802 /* All other aggregate types are passed in an integer register
7803 in a mode corresponding to the size of the type. */
7804 const int size
= int_size_in_bytes (type
);
7805 gcc_assert (size
<= 32);
7807 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7809 /* ??? We probably should have made the same ABI change in
7810 3.4.0 as the one we made for unions. The latter was
7811 required by the SCD though, while the former is not
7812 specified, so we favored compatibility and efficiency.
7814 Now we're stuck for aggregates larger than 16 bytes,
7815 because OImode vanished in the meantime. Let's not
7816 try to be unduly clever, and simply follow the ABI
7817 for unions in that case. */
7818 if (mode
== BLKmode
)
7819 return function_arg_union_value (size
, mode
, 0, regbase
);
7824 /* We should only have pointer and integer types at this point. This
7825 must match sparc_promote_function_mode. */
7826 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7830 /* We should only have pointer and integer types at this point, except with
7831 -freg-struct-return. This must match sparc_promote_function_mode. */
7832 else if (TARGET_ARCH32
7833 && !(type
&& AGGREGATE_TYPE_P (type
))
7834 && mclass
== MODE_INT
7835 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7838 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7839 regno
= SPARC_FP_ARG_FIRST
;
7843 return gen_rtx_REG (mode
, regno
);
7846 /* Handle TARGET_FUNCTION_VALUE.
7847 On the SPARC, the value is found in the first "output" register, but the
7848 called function leaves it in the first "input" register. */
7851 sparc_function_value (const_tree valtype
,
7852 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7855 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7858 /* Handle TARGET_LIBCALL_VALUE. */
7861 sparc_libcall_value (machine_mode mode
,
7862 const_rtx fun ATTRIBUTE_UNUSED
)
7864 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7867 /* Handle FUNCTION_VALUE_REGNO_P.
7868 On the SPARC, the first "output" reg is used for integer values, and the
7869 first floating point register is used for floating point values. */
7872 sparc_function_value_regno_p (const unsigned int regno
)
7874 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7877 /* Do what is necessary for `va_start'. We look at the current function
7878 to determine if stdarg or varargs is used and return the address of
7879 the first unnamed parameter. */
7882 sparc_builtin_saveregs (void)
7884 int first_reg
= crtl
->args
.info
.words
;
7888 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7889 emit_move_insn (gen_rtx_MEM (word_mode
,
7890 gen_rtx_PLUS (Pmode
,
7892 GEN_INT (FIRST_PARM_OFFSET (0)
7895 gen_rtx_REG (word_mode
,
7896 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7898 address
= gen_rtx_PLUS (Pmode
,
7900 GEN_INT (FIRST_PARM_OFFSET (0)
7901 + UNITS_PER_WORD
* first_reg
));
7906 /* Implement `va_start' for stdarg. */
7909 sparc_va_start (tree valist
, rtx nextarg
)
7911 nextarg
= expand_builtin_saveregs ();
7912 std_expand_builtin_va_start (valist
, nextarg
);
7915 /* Implement `va_arg' for stdarg. */
7918 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7921 HOST_WIDE_INT size
, rsize
, align
;
7924 tree ptrtype
= build_pointer_type (type
);
7926 if (pass_va_arg_by_reference (type
))
7929 size
= rsize
= UNITS_PER_WORD
;
7935 size
= int_size_in_bytes (type
);
7936 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7941 /* For SPARC64, objects requiring 16-byte alignment get it. */
7942 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7943 align
= 2 * UNITS_PER_WORD
;
7945 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7946 are left-justified in their slots. */
7947 if (AGGREGATE_TYPE_P (type
))
7950 size
= rsize
= UNITS_PER_WORD
;
7960 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7961 incr
= fold_convert (sizetype
, incr
);
7962 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7964 incr
= fold_convert (ptr_type_node
, incr
);
7967 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7970 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7971 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7975 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7976 addr
= build_va_arg_indirect_ref (addr
);
7979 /* If the address isn't aligned properly for the type, we need a temporary.
7980 FIXME: This is inefficient, usually we can do this in registers. */
7981 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7983 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7984 tree dest_addr
= build_fold_addr_expr (tmp
);
7985 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7986 3, dest_addr
, addr
, size_int (rsize
));
7987 TREE_ADDRESSABLE (tmp
) = 1;
7988 gimplify_and_add (copy
, pre_p
);
7993 addr
= fold_convert (ptrtype
, addr
);
7995 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7996 gimplify_assign (valist
, incr
, post_p
);
7998 return build_va_arg_indirect_ref (addr
);
8001 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
8002 Specify whether the vector mode is supported by the hardware. */
8005 sparc_vector_mode_supported_p (machine_mode mode
)
8007 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
8010 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
8013 sparc_preferred_simd_mode (scalar_mode mode
)
8031 \f/* Implement TARGET_CAN_FOLLOW_JUMP. */
8034 sparc_can_follow_jump (const rtx_insn
*follower
, const rtx_insn
*followee
)
8036 /* Do not fold unconditional jumps that have been created for crossing
8037 partition boundaries. */
8038 if (CROSSING_JUMP_P (followee
) && !CROSSING_JUMP_P (follower
))
8044 /* Return the string to output an unconditional branch to LABEL, which is
8045 the operand number of the label.
8047 DEST is the destination insn (i.e. the label), INSN is the source. */
8050 output_ubranch (rtx dest
, rtx_insn
*insn
)
8052 static char string
[64];
8053 bool v9_form
= false;
8057 /* Even if we are trying to use cbcond for this, evaluate
8058 whether we can use V9 branches as our backup plan. */
8060 if (!CROSSING_JUMP_P (insn
) && INSN_ADDRESSES_SET_P ())
8061 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8062 - INSN_ADDRESSES (INSN_UID (insn
)));
8064 /* Leave some instructions for "slop". */
8065 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
8070 bool emit_nop
= emit_cbcond_nop (insn
);
8074 if (delta
< -500 || delta
> 500)
8080 rval
= "ba,a,pt\t%%xcc, %l0";
8087 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
8089 rval
= "cwbe\t%%g0, %%g0, %l0";
8095 strcpy (string
, "ba%*,pt\t%%xcc, ");
8097 strcpy (string
, "b%*\t");
8099 p
= strchr (string
, '\0');
8110 /* Return the string to output a conditional branch to LABEL, which is
8111 the operand number of the label. OP is the conditional expression.
8112 XEXP (OP, 0) is assumed to be a condition code register (integer or
8113 floating point) and its mode specifies what kind of comparison we made.
8115 DEST is the destination insn (i.e. the label), INSN is the source.
8117 REVERSED is nonzero if we should reverse the sense of the comparison.
8119 ANNUL is nonzero if we should generate an annulling branch. */
8122 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
8125 static char string
[64];
8126 enum rtx_code code
= GET_CODE (op
);
8127 rtx cc_reg
= XEXP (op
, 0);
8128 machine_mode mode
= GET_MODE (cc_reg
);
8129 const char *labelno
, *branch
;
8130 int spaces
= 8, far
;
8133 /* v9 branches are limited to +-1MB. If it is too far away,
8146 fbne,a,pn %fcc2, .LC29
8154 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
8157 /* Reversal of FP compares takes care -- an ordered compare
8158 becomes an unordered compare and vice versa. */
8159 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8160 code
= reverse_condition_maybe_unordered (code
);
8162 code
= reverse_condition (code
);
8165 /* Start by writing the branch condition. */
8166 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8216 /* ??? !v9: FP branches cannot be preceded by another floating point
8217 insn. Because there is currently no concept of pre-delay slots,
8218 we can fix this only by always emitting a nop before a floating
8223 strcpy (string
, "nop\n\t");
8224 strcat (string
, branch
);
8231 if (mode
== CCVmode
|| mode
== CCXVmode
)
8237 if (mode
== CCVmode
|| mode
== CCXVmode
)
8243 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8255 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8275 strcpy (string
, branch
);
8277 spaces
-= strlen (branch
);
8278 p
= strchr (string
, '\0');
8280 /* Now add the annulling, the label, and a possible noop. */
8293 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
8295 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8296 - INSN_ADDRESSES (INSN_UID (insn
)));
8297 /* Leave some instructions for "slop". */
8298 if (delta
< -260000 || delta
>= 260000)
8308 labelno
= "%%icc, ";
8316 labelno
= "%%xcc, ";
8322 static char v9_fcc_labelno
[] = "%%fccX, ";
8323 /* Set the char indicating the number of the fcc reg to use. */
8324 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
8325 labelno
= v9_fcc_labelno
;
8328 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
8337 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8340 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8341 >= profile_probability::even ()) ^ far
)
8354 strcpy (p
, labelno
);
8355 p
= strchr (p
, '\0');
8358 strcpy (p
, ".+12\n\t nop\n\tb\t");
8359 /* Skip the next insn if requested or
8360 if we know that it will be a nop. */
8361 if (annul
|| ! final_sequence
)
8375 /* Emit a library call comparison between floating point X and Y.
8376 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
8377 Return the new operator to be used in the comparison sequence.
8379 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
8380 values as arguments instead of the TFmode registers themselves,
8381 that's why we cannot call emit_float_lib_cmp. */
8384 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
8387 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
8389 enum rtx_code new_comparison
;
8394 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
8398 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
8402 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
8406 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
8410 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
8414 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
8425 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
8436 tree expr
= MEM_EXPR (x
);
8438 mark_addressable (expr
);
8443 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8444 emit_move_insn (slot0
, x
);
8449 tree expr
= MEM_EXPR (y
);
8451 mark_addressable (expr
);
8456 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8457 emit_move_insn (slot1
, y
);
8460 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8461 emit_library_call (libfunc
, LCT_NORMAL
,
8463 XEXP (slot0
, 0), Pmode
,
8464 XEXP (slot1
, 0), Pmode
);
8469 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8470 emit_library_call (libfunc
, LCT_NORMAL
,
8472 x
, TFmode
, y
, TFmode
);
8477 /* Immediately move the result of the libcall into a pseudo
8478 register so reload doesn't clobber the value if it needs
8479 the return register for a spill reg. */
8480 result
= gen_reg_rtx (mode
);
8481 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8486 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8489 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8490 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8493 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8494 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8496 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8498 tem
= gen_reg_rtx (mode
);
8500 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8502 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8503 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8506 tem
= gen_reg_rtx (mode
);
8508 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8510 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8511 tem2
= gen_reg_rtx (mode
);
8513 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8515 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8516 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8517 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8523 /* Generate an unsigned DImode to FP conversion. This is the same code
8524 optabs would emit if we didn't have TFmode patterns. */
8527 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8529 rtx i0
, i1
, f0
, in
, out
;
8532 in
= force_reg (DImode
, operands
[1]);
8533 rtx_code_label
*neglab
= gen_label_rtx ();
8534 rtx_code_label
*donelab
= gen_label_rtx ();
8535 i0
= gen_reg_rtx (DImode
);
8536 i1
= gen_reg_rtx (DImode
);
8537 f0
= gen_reg_rtx (mode
);
8539 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8541 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8542 emit_jump_insn (gen_jump (donelab
));
8545 emit_label (neglab
);
8547 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8548 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8549 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8550 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8551 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8553 emit_label (donelab
);
8556 /* Generate an FP to unsigned DImode conversion. This is the same code
8557 optabs would emit if we didn't have TFmode patterns. */
8560 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8562 rtx i0
, i1
, f0
, in
, out
, limit
;
8565 in
= force_reg (mode
, operands
[1]);
8566 rtx_code_label
*neglab
= gen_label_rtx ();
8567 rtx_code_label
*donelab
= gen_label_rtx ();
8568 i0
= gen_reg_rtx (DImode
);
8569 i1
= gen_reg_rtx (DImode
);
8570 limit
= gen_reg_rtx (mode
);
8571 f0
= gen_reg_rtx (mode
);
8573 emit_move_insn (limit
,
8574 const_double_from_real_value (
8575 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8576 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8578 emit_insn (gen_rtx_SET (out
,
8579 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8580 emit_jump_insn (gen_jump (donelab
));
8583 emit_label (neglab
);
8585 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8586 emit_insn (gen_rtx_SET (i0
,
8587 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8588 emit_insn (gen_movdi (i1
, const1_rtx
));
8589 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8590 emit_insn (gen_xordi3 (out
, i0
, i1
));
8592 emit_label (donelab
);
8595 /* Return the string to output a compare and branch instruction to DEST.
8596 DEST is the destination insn (i.e. the label), INSN is the source,
8597 and OP is the conditional expression. */
8600 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8602 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8603 enum rtx_code code
= GET_CODE (op
);
8604 const char *cond_str
, *tmpl
;
8605 int far
, emit_nop
, len
;
8606 static char string
[64];
8609 /* Compare and Branch is limited to +-2KB. If it is too far away,
8621 len
= get_attr_length (insn
);
8624 emit_nop
= len
== 2;
8627 code
= reverse_condition (code
);
8629 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8679 int veryfar
= 1, delta
;
8681 if (INSN_ADDRESSES_SET_P ())
8683 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8684 - INSN_ADDRESSES (INSN_UID (insn
)));
8685 /* Leave some instructions for "slop". */
8686 if (delta
>= -260000 && delta
< 260000)
8691 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8693 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8698 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8700 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8703 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8708 /* Return the string to output a conditional branch to LABEL, testing
8709 register REG. LABEL is the operand number of the label; REG is the
8710 operand number of the reg. OP is the conditional expression. The mode
8711 of REG says what kind of comparison we made.
8713 DEST is the destination insn (i.e. the label), INSN is the source.
8715 REVERSED is nonzero if we should reverse the sense of the comparison.
8717 ANNUL is nonzero if we should generate an annulling branch. */
8720 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8721 int annul
, rtx_insn
*insn
)
8723 static char string
[64];
8724 enum rtx_code code
= GET_CODE (op
);
8725 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8730 /* branch on register are limited to +-128KB. If it is too far away,
8743 brgez,a,pn %o1, .LC29
8749 ba,pt %xcc, .LC29 */
8751 far
= get_attr_length (insn
) >= 3;
8753 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8755 code
= reverse_condition (code
);
8757 /* Only 64-bit versions of these instructions exist. */
8758 gcc_assert (mode
== DImode
);
8760 /* Start by writing the branch condition. */
8765 strcpy (string
, "brnz");
8769 strcpy (string
, "brz");
8773 strcpy (string
, "brgez");
8777 strcpy (string
, "brlz");
8781 strcpy (string
, "brlez");
8785 strcpy (string
, "brgz");
8792 p
= strchr (string
, '\0');
8794 /* Now add the annulling, reg, label, and nop. */
8801 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8804 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8805 >= profile_probability::even ()) ^ far
)
8810 *p
= p
< string
+ 8 ? '\t' : ' ';
8818 int veryfar
= 1, delta
;
8820 if (INSN_ADDRESSES_SET_P ())
8822 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8823 - INSN_ADDRESSES (INSN_UID (insn
)));
8824 /* Leave some instructions for "slop". */
8825 if (delta
>= -260000 && delta
< 260000)
8829 strcpy (p
, ".+12\n\t nop\n\t");
8830 /* Skip the next insn if requested or
8831 if we know that it will be a nop. */
8832 if (annul
|| ! final_sequence
)
8842 strcpy (p
, "ba,pt\t%%xcc, ");
8856 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8857 Such instructions cannot be used in the delay slot of return insn on v9.
8858 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8862 epilogue_renumber (rtx
*where
, int test
)
8871 code
= GET_CODE (*where
);
8876 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8878 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8880 if (ORIGINAL_REGNO (*where
))
8882 rtx n
= gen_raw_REG (GET_MODE (*where
),
8883 OUTGOING_REGNO (REGNO (*where
)));
8884 ORIGINAL_REGNO (n
) = ORIGINAL_REGNO (*where
);
8888 *where
= gen_rtx_REG (GET_MODE (*where
),
8889 OUTGOING_REGNO (REGNO (*where
)));
8896 case CONST_WIDE_INT
:
8900 /* Do not replace the frame pointer with the stack pointer because
8901 it can cause the delayed instruction to load below the stack.
8902 This occurs when instructions like:
8904 (set (reg/i:SI 24 %i0)
8905 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8906 (const_int -20 [0xffffffec])) 0))
8908 are in the return delayed slot. */
8910 if (GET_CODE (XEXP (*where
, 0)) == REG
8911 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8912 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8913 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8918 if (SPARC_STACK_BIAS
8919 && GET_CODE (XEXP (*where
, 0)) == REG
8920 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8928 fmt
= GET_RTX_FORMAT (code
);
8930 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8935 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8936 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8939 else if (fmt
[i
] == 'e'
8940 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8946 /* Leaf functions and non-leaf functions have different needs. */
8948 static const int reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8950 static const int reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8952 static const int *const reg_alloc_orders
[] =
8954 reg_leaf_alloc_order
,
8955 reg_nonleaf_alloc_order
8959 sparc_order_regs_for_local_alloc (void)
8961 static int last_order_nonleaf
= 1;
8963 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8965 last_order_nonleaf
= !last_order_nonleaf
;
8966 memcpy ((char *) reg_alloc_order
,
8967 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8968 FIRST_PSEUDO_REGISTER
* sizeof (int));
8973 sparc_leaf_reg_remap (int regno
)
8975 gcc_checking_assert (regno
>= 0);
8977 /* Do not remap in flat mode. */
8981 /* Do not remap global, stack pointer or floating-point registers. */
8982 if (regno
< 8 || regno
== STACK_POINTER_REGNUM
|| regno
> SPARC_LAST_INT_REG
)
8985 /* Neither out nor local nor frame pointer registers must appear. */
8986 if ((regno
>= 8 && regno
<= 23) || regno
== HARD_FRAME_POINTER_REGNUM
)
8989 /* Remap in to out registers. */
8993 /* Return 1 if REG and MEM are legitimate enough to allow the various
8994 MEM<-->REG splits to be run. */
8997 sparc_split_reg_mem_legitimate (rtx reg
, rtx mem
)
8999 /* Punt if we are here by mistake. */
9000 gcc_assert (reload_completed
);
9002 /* We must have an offsettable memory reference. */
9003 if (!offsettable_memref_p (mem
))
9006 /* If we have legitimate args for ldd/std, we do not want
9007 the split to happen. */
9008 if ((REGNO (reg
) % 2) == 0 && mem_min_alignment (mem
, 8))
9015 /* Split a REG <-- MEM move into a pair of moves in MODE. */
9018 sparc_split_reg_mem (rtx dest
, rtx src
, machine_mode mode
)
9020 rtx high_part
= gen_highpart (mode
, dest
);
9021 rtx low_part
= gen_lowpart (mode
, dest
);
9022 rtx word0
= adjust_address (src
, mode
, 0);
9023 rtx word1
= adjust_address (src
, mode
, 4);
9025 if (reg_overlap_mentioned_p (high_part
, word1
))
9027 emit_move_insn_1 (low_part
, word1
);
9028 emit_move_insn_1 (high_part
, word0
);
9032 emit_move_insn_1 (high_part
, word0
);
9033 emit_move_insn_1 (low_part
, word1
);
9037 /* Split a MEM <-- REG move into a pair of moves in MODE. */
9040 sparc_split_mem_reg (rtx dest
, rtx src
, machine_mode mode
)
9042 rtx word0
= adjust_address (dest
, mode
, 0);
9043 rtx word1
= adjust_address (dest
, mode
, 4);
9044 rtx high_part
= gen_highpart (mode
, src
);
9045 rtx low_part
= gen_lowpart (mode
, src
);
9047 emit_move_insn_1 (word0
, high_part
);
9048 emit_move_insn_1 (word1
, low_part
);
9051 /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */
9054 sparc_split_reg_reg_legitimate (rtx reg1
, rtx reg2
)
9056 /* Punt if we are here by mistake. */
9057 gcc_assert (reload_completed
);
9059 if (GET_CODE (reg1
) == SUBREG
)
9060 reg1
= SUBREG_REG (reg1
);
9061 if (GET_CODE (reg1
) != REG
)
9063 const int regno1
= REGNO (reg1
);
9065 if (GET_CODE (reg2
) == SUBREG
)
9066 reg2
= SUBREG_REG (reg2
);
9067 if (GET_CODE (reg2
) != REG
)
9069 const int regno2
= REGNO (reg2
);
9071 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
9076 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
9077 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
9084 /* Split a REG <--> REG move into a pair of moves in MODE. */
9087 sparc_split_reg_reg (rtx dest
, rtx src
, machine_mode mode
)
9089 rtx dest1
= gen_highpart (mode
, dest
);
9090 rtx dest2
= gen_lowpart (mode
, dest
);
9091 rtx src1
= gen_highpart (mode
, src
);
9092 rtx src2
= gen_lowpart (mode
, src
);
9094 /* Now emit using the real source and destination we found, swapping
9095 the order if we detect overlap. */
9096 if (reg_overlap_mentioned_p (dest1
, src2
))
9098 emit_move_insn_1 (dest2
, src2
);
9099 emit_move_insn_1 (dest1
, src1
);
9103 emit_move_insn_1 (dest1
, src1
);
9104 emit_move_insn_1 (dest2
, src2
);
9108 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
9109 This makes them candidates for using ldd and std insns.
9111 Note reg1 and reg2 *must* be hard registers. */
9114 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
9116 /* We might have been passed a SUBREG. */
9117 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
9120 if (REGNO (reg1
) % 2 != 0)
9123 /* Integer ldd is deprecated in SPARC V9 */
9124 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
9127 return (REGNO (reg1
) == REGNO (reg2
) - 1);
9130 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
9133 This can only happen when addr1 and addr2, the addresses in mem1
9134 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
9135 addr1 must also be aligned on a 64-bit boundary.
9137 Also iff dependent_reg_rtx is not null it should not be used to
9138 compute the address for mem1, i.e. we cannot optimize a sequence
9150 But, note that the transformation from:
9155 is perfectly fine. Thus, the peephole2 patterns always pass us
9156 the destination register of the first load, never the second one.
9158 For stores we don't have a similar problem, so dependent_reg_rtx is
9162 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
9166 HOST_WIDE_INT offset1
;
9168 /* The mems cannot be volatile. */
9169 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
9172 /* MEM1 should be aligned on a 64-bit boundary. */
9173 if (MEM_ALIGN (mem1
) < 64)
9176 addr1
= XEXP (mem1
, 0);
9177 addr2
= XEXP (mem2
, 0);
9179 /* Extract a register number and offset (if used) from the first addr. */
9180 if (GET_CODE (addr1
) == PLUS
)
9182 /* If not a REG, return zero. */
9183 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
9187 reg1
= REGNO (XEXP (addr1
, 0));
9188 /* The offset must be constant! */
9189 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
9191 offset1
= INTVAL (XEXP (addr1
, 1));
9194 else if (GET_CODE (addr1
) != REG
)
9198 reg1
= REGNO (addr1
);
9199 /* This was a simple (mem (reg)) expression. Offset is 0. */
9203 /* Make sure the second address is a (mem (plus (reg) (const_int). */
9204 if (GET_CODE (addr2
) != PLUS
)
9207 if (GET_CODE (XEXP (addr2
, 0)) != REG
9208 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
9211 if (reg1
!= REGNO (XEXP (addr2
, 0)))
9214 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
9217 /* The first offset must be evenly divisible by 8 to ensure the
9218 address is 64-bit aligned. */
9219 if (offset1
% 8 != 0)
9222 /* The offset for the second addr must be 4 more than the first addr. */
9223 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
9226 /* All the tests passed. addr1 and addr2 are valid for ldd and std
9231 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
9234 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
9236 rtx x
= widen_memory_access (mem1
, mode
, 0);
9237 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
9241 /* Return 1 if reg is a pseudo, or is the first register in
9242 a hard register pair. This makes it suitable for use in
9243 ldd and std insns. */
9246 register_ok_for_ldd (rtx reg
)
9248 /* We might have been passed a SUBREG. */
9252 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
9253 return (REGNO (reg
) % 2 == 0);
9258 /* Return 1 if OP, a MEM, has an address which is known to be
9259 aligned to an 8-byte boundary. */
9262 memory_ok_for_ldd (rtx op
)
9264 if (!mem_min_alignment (op
, 8))
9267 /* We need to perform the job of a memory constraint. */
9268 if ((reload_in_progress
|| reload_completed
)
9269 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
9272 if (lra_in_progress
&& !memory_address_p (Pmode
, XEXP (op
, 0)))
9278 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
9281 sparc_print_operand_punct_valid_p (unsigned char code
)
9294 /* Implement TARGET_PRINT_OPERAND.
9295 Print operand X (an rtx) in assembler syntax to file FILE.
9296 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
9297 For `%' followed by punctuation, CODE is the punctuation and X is null. */
9300 sparc_print_operand (FILE *file
, rtx x
, int code
)
9307 /* Output an insn in a delay slot. */
9309 sparc_indent_opcode
= 1;
9311 fputs ("\n\t nop", file
);
9314 /* Output an annul flag if there's nothing for the delay slot and we
9315 are optimizing. This is always used with '(' below.
9316 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
9317 this is a dbx bug. So, we only do this when optimizing.
9318 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
9319 Always emit a nop in case the next instruction is a branch. */
9320 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9324 /* Output a 'nop' if there's nothing for the delay slot and we are
9325 not optimizing. This is always used with '*' above. */
9326 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9327 fputs ("\n\t nop", file
);
9328 else if (final_sequence
)
9329 sparc_indent_opcode
= 1;
9332 /* Output the right displacement from the saved PC on function return.
9333 The caller may have placed an "unimp" insn immediately after the call
9334 so we have to account for it. This insn is used in the 32-bit ABI
9335 when calling a function that returns a non zero-sized structure. The
9336 64-bit ABI doesn't have it. Be careful to have this test be the same
9337 as that for the call. The exception is when sparc_std_struct_return
9338 is enabled, the psABI is followed exactly and the adjustment is made
9339 by the code in sparc_struct_value_rtx. The call emitted is the same
9340 when sparc_std_struct_return is enabled. */
9342 && cfun
->returns_struct
9343 && !sparc_std_struct_return
9344 && DECL_SIZE (DECL_RESULT (current_function_decl
))
9345 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
9347 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
9353 /* Output the Embedded Medium/Anywhere code model base register. */
9354 fputs (EMBMEDANY_BASE_REG
, file
);
9357 /* Print some local dynamic TLS name. */
9358 if (const char *name
= get_some_local_dynamic_name ())
9359 assemble_name (file
, name
);
9361 output_operand_lossage ("'%%&' used without any "
9362 "local dynamic TLS references");
9366 /* Adjust the operand to take into account a RESTORE operation. */
9367 if (GET_CODE (x
) == CONST_INT
)
9369 else if (GET_CODE (x
) != REG
)
9370 output_operand_lossage ("invalid %%Y operand");
9371 else if (REGNO (x
) < 8)
9372 fputs (reg_names
[REGNO (x
)], file
);
9373 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
9374 fputs (reg_names
[REGNO (x
)-16], file
);
9376 output_operand_lossage ("invalid %%Y operand");
9379 /* Print out the low order register name of a register pair. */
9380 if (WORDS_BIG_ENDIAN
)
9381 fputs (reg_names
[REGNO (x
)+1], file
);
9383 fputs (reg_names
[REGNO (x
)], file
);
9386 /* Print out the high order register name of a register pair. */
9387 if (WORDS_BIG_ENDIAN
)
9388 fputs (reg_names
[REGNO (x
)], file
);
9390 fputs (reg_names
[REGNO (x
)+1], file
);
9393 /* Print out the second register name of a register pair or quad.
9394 I.e., R (%o0) => %o1. */
9395 fputs (reg_names
[REGNO (x
)+1], file
);
9398 /* Print out the third register name of a register quad.
9399 I.e., S (%o0) => %o2. */
9400 fputs (reg_names
[REGNO (x
)+2], file
);
9403 /* Print out the fourth register name of a register quad.
9404 I.e., T (%o0) => %o3. */
9405 fputs (reg_names
[REGNO (x
)+3], file
);
9408 /* Print a condition code register. */
9409 if (REGNO (x
) == SPARC_ICC_REG
)
9411 switch (GET_MODE (x
))
9431 /* %fccN register */
9432 fputs (reg_names
[REGNO (x
)], file
);
9435 /* Print the operand's address only. */
9436 output_address (GET_MODE (x
), XEXP (x
, 0));
9439 /* In this case we need a register. Use %g0 if the
9440 operand is const0_rtx. */
9442 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
9444 fputs ("%g0", file
);
9451 switch (GET_CODE (x
))
9463 output_operand_lossage ("invalid %%A operand");
9471 switch (GET_CODE (x
))
9483 output_operand_lossage ("invalid %%B operand");
9490 /* This is used by the conditional move instructions. */
9493 machine_mode mode
= GET_MODE (XEXP (x
, 0));
9494 switch (GET_CODE (x
))
9497 if (mode
== CCVmode
|| mode
== CCXVmode
)
9503 if (mode
== CCVmode
|| mode
== CCXVmode
)
9509 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9521 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9563 output_operand_lossage ("invalid %%C operand");
9571 /* This are used by the movr instruction pattern. */
9574 switch (GET_CODE (x
))
9595 output_operand_lossage ("invalid %%D operand");
9605 /* Print a sign-extended character. */
9606 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
9607 fprintf (file
, "%d", i
);
9612 /* Operand must be a MEM; write its address. */
9613 if (GET_CODE (x
) != MEM
)
9614 output_operand_lossage ("invalid %%f operand");
9615 output_address (GET_MODE (x
), XEXP (x
, 0));
9620 /* Print a sign-extended 32-bit value. */
9622 if (GET_CODE(x
) == CONST_INT
)
9626 output_operand_lossage ("invalid %%s operand");
9629 i
= trunc_int_for_mode (i
, SImode
);
9630 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
9635 /* Do nothing special. */
9639 /* Undocumented flag. */
9640 output_operand_lossage ("invalid operand output code");
9643 if (GET_CODE (x
) == REG
)
9644 fputs (reg_names
[REGNO (x
)], file
);
9645 else if (GET_CODE (x
) == MEM
)
9648 /* Poor Sun assembler doesn't understand absolute addressing. */
9649 if (CONSTANT_P (XEXP (x
, 0)))
9650 fputs ("%g0+", file
);
9651 output_address (GET_MODE (x
), XEXP (x
, 0));
9654 else if (GET_CODE (x
) == HIGH
)
9656 fputs ("%hi(", file
);
9657 output_addr_const (file
, XEXP (x
, 0));
9660 else if (GET_CODE (x
) == LO_SUM
)
9662 sparc_print_operand (file
, XEXP (x
, 0), 0);
9663 if (TARGET_CM_MEDMID
)
9664 fputs ("+%l44(", file
);
9666 fputs ("+%lo(", file
);
9667 output_addr_const (file
, XEXP (x
, 1));
9670 else if (GET_CODE (x
) == CONST_DOUBLE
)
9671 output_operand_lossage ("floating-point constant not a valid immediate operand");
9673 output_addr_const (file
, x
);
9676 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9679 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9681 rtx base
, index
= 0;
9686 fputs (reg_names
[REGNO (addr
)], file
);
9687 else if (GET_CODE (addr
) == PLUS
)
9689 if (CONST_INT_P (XEXP (addr
, 0)))
9690 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9691 else if (CONST_INT_P (XEXP (addr
, 1)))
9692 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9694 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9695 if (GET_CODE (base
) == LO_SUM
)
9697 gcc_assert (USE_AS_OFFSETABLE_LO10
9699 && ! TARGET_CM_MEDMID
);
9700 output_operand (XEXP (base
, 0), 0);
9701 fputs ("+%lo(", file
);
9702 output_address (VOIDmode
, XEXP (base
, 1));
9703 fprintf (file
, ")+%d", offset
);
9707 fputs (reg_names
[REGNO (base
)], file
);
9709 fprintf (file
, "%+d", offset
);
9710 else if (REG_P (index
))
9711 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9712 else if (GET_CODE (index
) == SYMBOL_REF
9713 || GET_CODE (index
) == LABEL_REF
9714 || GET_CODE (index
) == CONST
)
9715 fputc ('+', file
), output_addr_const (file
, index
);
9716 else gcc_unreachable ();
9719 else if (GET_CODE (addr
) == MINUS
9720 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9722 output_addr_const (file
, XEXP (addr
, 0));
9724 output_addr_const (file
, XEXP (addr
, 1));
9725 fputs ("-.)", file
);
9727 else if (GET_CODE (addr
) == LO_SUM
)
9729 output_operand (XEXP (addr
, 0), 0);
9730 if (TARGET_CM_MEDMID
)
9731 fputs ("+%l44(", file
);
9733 fputs ("+%lo(", file
);
9734 output_address (VOIDmode
, XEXP (addr
, 1));
9738 && GET_CODE (addr
) == CONST
9739 && GET_CODE (XEXP (addr
, 0)) == MINUS
9740 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9741 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9742 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9744 addr
= XEXP (addr
, 0);
9745 output_addr_const (file
, XEXP (addr
, 0));
9746 /* Group the args of the second CONST in parenthesis. */
9748 /* Skip past the second CONST--it does nothing for us. */
9749 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9750 /* Close the parenthesis. */
9755 output_addr_const (file
, addr
);
9759 /* Target hook for assembling integer objects. The sparc version has
9760 special handling for aligned DI-mode objects. */
9763 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9765 /* ??? We only output .xword's for symbols and only then in environments
9766 where the assembler can handle them. */
9767 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9771 assemble_integer_with_op ("\t.xword\t", x
);
9776 assemble_aligned_integer (4, const0_rtx
);
9777 assemble_aligned_integer (4, x
);
9781 return default_assemble_integer (x
, size
, aligned_p
);
9784 /* Return the value of a code used in the .proc pseudo-op that says
9785 what kind of result this function returns. For non-C types, we pick
9786 the closest C type. */
9788 #ifndef SHORT_TYPE_SIZE
9789 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9792 #ifndef INT_TYPE_SIZE
9793 #define INT_TYPE_SIZE BITS_PER_WORD
9796 #ifndef LONG_TYPE_SIZE
9797 #define LONG_TYPE_SIZE BITS_PER_WORD
9800 #ifndef LONG_LONG_TYPE_SIZE
9801 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9804 #ifndef FLOAT_TYPE_SIZE
9805 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9808 #ifndef DOUBLE_TYPE_SIZE
9809 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9812 #ifndef LONG_DOUBLE_TYPE_SIZE
9813 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9817 sparc_type_code (tree type
)
9819 unsigned long qualifiers
= 0;
9822 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9823 setting more, since some assemblers will give an error for this. Also,
9824 we must be careful to avoid shifts of 32 bits or more to avoid getting
9825 unpredictable results. */
9827 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9829 switch (TREE_CODE (type
))
9835 qualifiers
|= (3 << shift
);
9840 qualifiers
|= (2 << shift
);
9844 case REFERENCE_TYPE
:
9846 qualifiers
|= (1 << shift
);
9850 return (qualifiers
| 8);
9853 case QUAL_UNION_TYPE
:
9854 return (qualifiers
| 9);
9857 return (qualifiers
| 10);
9860 return (qualifiers
| 16);
9863 /* If this is a range type, consider it to be the underlying
9865 if (TREE_TYPE (type
) != 0)
9868 /* Carefully distinguish all the standard types of C,
9869 without messing up if the language is not C. We do this by
9870 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9871 look at both the names and the above fields, but that's redundant.
9872 Any type whose size is between two C types will be considered
9873 to be the wider of the two types. Also, we do not have a
9874 special code to use for "long long", so anything wider than
9875 long is treated the same. Note that we can't distinguish
9876 between "int" and "long" in this code if they are the same
9877 size, but that's fine, since neither can the assembler. */
9879 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9880 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9882 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9883 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9885 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9886 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9889 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9892 /* If this is a range type, consider it to be the underlying
9894 if (TREE_TYPE (type
) != 0)
9897 /* Carefully distinguish all the standard types of C,
9898 without messing up if the language is not C. */
9900 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9901 return (qualifiers
| 6);
9904 return (qualifiers
| 7);
9906 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9907 /* ??? We need to distinguish between double and float complex types,
9908 but I don't know how yet because I can't reach this code from
9909 existing front-ends. */
9910 return (qualifiers
| 7); /* Who knows? */
9913 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9919 gcc_unreachable (); /* Not a type! */
9926 /* Nested function support. */
9928 /* Emit RTL insns to initialize the variable parts of a trampoline.
9929 FNADDR is an RTX for the address of the function's pure code.
9930 CXT is an RTX for the static chain value for the function.
9932 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9933 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9934 (to store insns). This is a bit excessive. Perhaps a different
9935 mechanism would be better here.
9937 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9940 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9942 /* SPARC 32-bit trampoline:
9945 sethi %hi(static), %g2
9947 or %g2, %lo(static), %g2
9949 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9950 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9954 (adjust_address (m_tramp
, SImode
, 0),
9955 expand_binop (SImode
, ior_optab
,
9956 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9957 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9958 NULL_RTX
, 1, OPTAB_DIRECT
));
9961 (adjust_address (m_tramp
, SImode
, 4),
9962 expand_binop (SImode
, ior_optab
,
9963 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9964 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9965 NULL_RTX
, 1, OPTAB_DIRECT
));
9968 (adjust_address (m_tramp
, SImode
, 8),
9969 expand_binop (SImode
, ior_optab
,
9970 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9971 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9972 NULL_RTX
, 1, OPTAB_DIRECT
));
9975 (adjust_address (m_tramp
, SImode
, 12),
9976 expand_binop (SImode
, ior_optab
,
9977 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9978 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9979 NULL_RTX
, 1, OPTAB_DIRECT
));
9982 (gen_flush (SImode
, validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9984 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9985 aligned on a 16 byte boundary so one flush clears it all. */
9986 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9987 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9988 && sparc_cpu
!= PROCESSOR_NIAGARA
9989 && sparc_cpu
!= PROCESSOR_NIAGARA2
9990 && sparc_cpu
!= PROCESSOR_NIAGARA3
9991 && sparc_cpu
!= PROCESSOR_NIAGARA4
9992 && sparc_cpu
!= PROCESSOR_NIAGARA7
9993 && sparc_cpu
!= PROCESSOR_M8
)
9995 (gen_flush (SImode
, validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9997 /* Call __enable_execute_stack after writing onto the stack to make sure
9998 the stack address is accessible. */
9999 #ifdef HAVE_ENABLE_EXECUTE_STACK
10000 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
10001 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
10006 /* The 64-bit version is simpler because it makes more sense to load the
10007 values as "immediate" data out of the trampoline. It's also easier since
10008 we can read the PC without clobbering a register. */
10011 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
10013 /* SPARC 64-bit trampoline:
10022 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
10023 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
10024 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
10025 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
10026 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
10027 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
10028 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
10029 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
10030 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
10031 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
10033 (gen_flush (DImode
, validize_mem (adjust_address (m_tramp
, DImode
, 0))));
10035 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
10036 aligned on a 16 byte boundary so one flush clears it all. */
10037 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
10038 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
10039 && sparc_cpu
!= PROCESSOR_NIAGARA
10040 && sparc_cpu
!= PROCESSOR_NIAGARA2
10041 && sparc_cpu
!= PROCESSOR_NIAGARA3
10042 && sparc_cpu
!= PROCESSOR_NIAGARA4
10043 && sparc_cpu
!= PROCESSOR_NIAGARA7
10044 && sparc_cpu
!= PROCESSOR_M8
)
10046 (gen_flush (DImode
, validize_mem (adjust_address (m_tramp
, DImode
, 8))));
10048 /* Call __enable_execute_stack after writing onto the stack to make sure
10049 the stack address is accessible. */
10050 #ifdef HAVE_ENABLE_EXECUTE_STACK
10051 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
10052 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
10056 /* Worker for TARGET_TRAMPOLINE_INIT. */
10059 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
10061 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
10062 cxt
= force_reg (Pmode
, cxt
);
10064 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
10066 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
10069 /* Adjust the cost of a scheduling dependency. Return the new cost of
10070 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
10073 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
10076 enum attr_type insn_type
;
10078 if (recog_memoized (insn
) < 0)
10081 insn_type
= get_attr_type (insn
);
10085 /* Data dependency; DEP_INSN writes a register that INSN reads some
10088 /* if a load, then the dependence must be on the memory address;
10089 add an extra "cycle". Note that the cost could be two cycles
10090 if the reg was written late in an instruction group; we ca not tell
10092 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
10095 /* Get the delay only if the address of the store is the dependence. */
10096 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
10098 rtx pat
= PATTERN(insn
);
10099 rtx dep_pat
= PATTERN (dep_insn
);
10101 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10102 return cost
; /* This should not happen! */
10104 /* The dependency between the two instructions was on the data that
10105 is being stored. Assume that this implies that the address of the
10106 store is not dependent. */
10107 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10110 return cost
+ 3; /* An approximation. */
10113 /* A shift instruction cannot receive its data from an instruction
10114 in the same cycle; add a one cycle penalty. */
10115 if (insn_type
== TYPE_SHIFT
)
10116 return cost
+ 3; /* Split before cascade into shift. */
10120 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
10121 INSN writes some cycles later. */
10123 /* These are only significant for the fpu unit; writing a fp reg before
10124 the fpu has finished with it stalls the processor. */
10126 /* Reusing an integer register causes no problems. */
10127 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10135 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
10138 enum attr_type insn_type
, dep_type
;
10139 rtx pat
= PATTERN(insn
);
10140 rtx dep_pat
= PATTERN (dep_insn
);
10142 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
10145 insn_type
= get_attr_type (insn
);
10146 dep_type
= get_attr_type (dep_insn
);
10151 /* Data dependency; DEP_INSN writes a register that INSN reads some
10158 /* Get the delay iff the address of the store is the dependence. */
10159 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10162 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10169 /* If a load, then the dependence must be on the memory address. If
10170 the addresses aren't equal, then it might be a false dependency */
10171 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
10173 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
10174 || GET_CODE (SET_DEST (dep_pat
)) != MEM
10175 || GET_CODE (SET_SRC (pat
)) != MEM
10176 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
10177 XEXP (SET_SRC (pat
), 0)))
10185 /* Compare to branch latency is 0. There is no benefit from
10186 separating compare and branch. */
10187 if (dep_type
== TYPE_COMPARE
)
10189 /* Floating point compare to branch latency is less than
10190 compare to conditional move. */
10191 if (dep_type
== TYPE_FPCMP
)
10200 /* Anti-dependencies only penalize the fpu unit. */
10201 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10213 leon5_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
10216 enum attr_type insn_type
, dep_type
;
10217 rtx pat
= PATTERN (insn
);
10218 rtx dep_pat
= PATTERN (dep_insn
);
10220 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
10223 insn_type
= get_attr_type (insn
);
10224 dep_type
= get_attr_type (dep_insn
);
10229 /* Data dependency; DEP_INSN writes a register that INSN reads some
10235 /* Try to schedule three instructions between the store and
10236 the ALU instruction that generated the data. */
10237 if (dep_type
== TYPE_IALU
|| dep_type
== TYPE_SHIFT
)
10239 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10242 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10251 /* Penalize anti-dependencies for FPU instructions. */
10252 if (fpop_insn_p (insn
) || insn_type
== TYPE_FPLOAD
)
10263 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
10268 case PROCESSOR_LEON5
:
10269 cost
= leon5_adjust_cost (insn
, dep_type
, dep
, cost
);
10271 case PROCESSOR_SUPERSPARC
:
10272 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10274 case PROCESSOR_HYPERSPARC
:
10275 case PROCESSOR_SPARCLITE86X
:
10276 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10285 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
10286 int sched_verbose ATTRIBUTE_UNUSED
,
10287 int max_ready ATTRIBUTE_UNUSED
)
10291 sparc_use_sched_lookahead (void)
10295 case PROCESSOR_ULTRASPARC
:
10296 case PROCESSOR_ULTRASPARC3
:
10298 case PROCESSOR_SUPERSPARC
:
10299 case PROCESSOR_HYPERSPARC
:
10300 case PROCESSOR_SPARCLITE86X
:
10302 case PROCESSOR_NIAGARA4
:
10303 case PROCESSOR_NIAGARA7
:
10306 case PROCESSOR_NIAGARA
:
10307 case PROCESSOR_NIAGARA2
:
10308 case PROCESSOR_NIAGARA3
:
10315 sparc_issue_rate (void)
10319 case PROCESSOR_ULTRASPARC
:
10320 case PROCESSOR_ULTRASPARC3
:
10323 case PROCESSOR_SUPERSPARC
:
10325 case PROCESSOR_HYPERSPARC
:
10326 case PROCESSOR_SPARCLITE86X
:
10328 /* Assume V9 processors are capable of at least dual-issue. */
10329 case PROCESSOR_NIAGARA4
:
10330 case PROCESSOR_NIAGARA7
:
10332 case PROCESSOR_NIAGARA
:
10333 case PROCESSOR_NIAGARA2
:
10334 case PROCESSOR_NIAGARA3
:
10341 sparc_branch_cost (bool speed_p
, bool predictable_p
)
10346 /* For pre-V9 processors we use a single value (usually 3) to take into
10347 account the potential annulling of the delay slot (which ends up being
10348 a bubble in the pipeline slot) plus a cycle to take into consideration
10349 the instruction cache effects.
10351 On V9 and later processors, which have branch prediction facilities,
10352 we take into account whether the branch is (easily) predictable. */
10353 const int cost
= sparc_costs
->branch_cost
;
10358 case PROCESSOR_ULTRASPARC
:
10359 case PROCESSOR_ULTRASPARC3
:
10360 case PROCESSOR_NIAGARA
:
10361 case PROCESSOR_NIAGARA2
:
10362 case PROCESSOR_NIAGARA3
:
10363 case PROCESSOR_NIAGARA4
:
10364 case PROCESSOR_NIAGARA7
:
10366 return cost
+ (predictable_p
? 0 : 2);
10374 set_extends (rtx_insn
*insn
)
10376 rtx pat
= PATTERN (insn
);
10378 switch (GET_CODE (SET_SRC (pat
)))
10380 /* Load and some shift instructions zero extend. */
10383 /* sethi clears the high bits */
10385 /* LO_SUM is used with sethi. sethi cleared the high
10386 bits and the values used with lo_sum are positive */
10388 /* Store flag stores 0 or 1 */
10398 rtx op0
= XEXP (SET_SRC (pat
), 0);
10399 rtx op1
= XEXP (SET_SRC (pat
), 1);
10400 if (GET_CODE (op1
) == CONST_INT
)
10401 return INTVAL (op1
) >= 0;
10402 if (GET_CODE (op0
) != REG
)
10404 if (sparc_check_64 (op0
, insn
) == 1)
10406 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10411 rtx op0
= XEXP (SET_SRC (pat
), 0);
10412 rtx op1
= XEXP (SET_SRC (pat
), 1);
10413 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
10415 if (GET_CODE (op1
) == CONST_INT
)
10416 return INTVAL (op1
) >= 0;
10417 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10420 return GET_MODE (SET_SRC (pat
)) == SImode
;
10421 /* Positive integers leave the high bits zero. */
10423 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
10426 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
10428 return sparc_check_64 (SET_SRC (pat
), insn
);
10434 /* We _ought_ to have only one kind per function, but... */
10435 static GTY(()) rtx sparc_addr_diff_list
;
10436 static GTY(()) rtx sparc_addr_list
;
10439 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
10441 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
10443 sparc_addr_diff_list
10444 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
10446 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
10450 sparc_output_addr_vec (rtx vec
)
10452 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10453 int idx
, vlen
= XVECLEN (body
, 0);
10455 #ifdef ASM_OUTPUT_ADDR_VEC_START
10456 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10459 #ifdef ASM_OUTPUT_CASE_LABEL
10460 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10463 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10466 for (idx
= 0; idx
< vlen
; idx
++)
10468 ASM_OUTPUT_ADDR_VEC_ELT
10469 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10472 #ifdef ASM_OUTPUT_ADDR_VEC_END
10473 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10478 sparc_output_addr_diff_vec (rtx vec
)
10480 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10481 rtx base
= XEXP (XEXP (body
, 0), 0);
10482 int idx
, vlen
= XVECLEN (body
, 1);
10484 #ifdef ASM_OUTPUT_ADDR_VEC_START
10485 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10488 #ifdef ASM_OUTPUT_CASE_LABEL
10489 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10492 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10495 for (idx
= 0; idx
< vlen
; idx
++)
10497 ASM_OUTPUT_ADDR_DIFF_ELT
10500 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10501 CODE_LABEL_NUMBER (base
));
10504 #ifdef ASM_OUTPUT_ADDR_VEC_END
10505 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10510 sparc_output_deferred_case_vectors (void)
10515 if (sparc_addr_list
== NULL_RTX
10516 && sparc_addr_diff_list
== NULL_RTX
)
10519 /* Align to cache line in the function's code section. */
10520 switch_to_section (current_function_section ());
10522 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10524 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10526 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
10527 sparc_output_addr_vec (XEXP (t
, 0));
10528 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
10529 sparc_output_addr_diff_vec (XEXP (t
, 0));
10531 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
10534 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
10535 unknown. Return 1 if the high bits are zero, -1 if the register is
10538 sparc_check_64 (rtx x
, rtx_insn
*insn
)
10540 /* If a register is set only once it is safe to ignore insns this
10541 code does not know how to handle. The loop will either recognize
10542 the single set and return the correct value or fail to recognize
10543 it and return 0. */
10547 gcc_assert (GET_CODE (x
) == REG
);
10549 if (GET_MODE (x
) == DImode
)
10550 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
10552 if (flag_expensive_optimizations
10553 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
10559 insn
= get_last_insn_anywhere ();
10564 while ((insn
= PREV_INSN (insn
)))
10566 switch (GET_CODE (insn
))
10579 rtx pat
= PATTERN (insn
);
10580 if (GET_CODE (pat
) != SET
)
10582 if (rtx_equal_p (x
, SET_DEST (pat
)))
10583 return set_extends (insn
);
10584 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
10585 return set_extends (insn
);
10586 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
10594 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
10595 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
10598 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
10600 static char asm_code
[60];
10602 /* The scratch register is only required when the destination
10603 register is not a 64-bit global or out register. */
10604 if (which_alternative
!= 2)
10605 operands
[3] = operands
[0];
10607 /* We can only shift by constants <= 63. */
10608 if (GET_CODE (operands
[2]) == CONST_INT
)
10609 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
10611 if (GET_CODE (operands
[1]) == CONST_INT
)
10613 output_asm_insn ("mov\t%1, %3", operands
);
10617 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10618 if (sparc_check_64 (operands
[1], insn
) <= 0)
10619 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
10620 output_asm_insn ("or\t%L1, %3, %3", operands
);
10623 strcpy (asm_code
, opcode
);
10625 if (which_alternative
!= 2)
10626 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
10629 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
10632 /* Output rtl to increment the profiler label LABELNO
10633 for profiling a function entry. */
10636 sparc_profile_hook (int labelno
)
10641 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
10642 if (NO_PROFILE_COUNTERS
)
10644 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
);
10648 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10649 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
10650 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, lab
, Pmode
);
10654 #ifdef TARGET_SOLARIS
10655 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
10658 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
10659 tree decl ATTRIBUTE_UNUSED
)
10661 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
10663 solaris_elf_asm_comdat_section (name
, flags
, decl
);
10667 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
10669 if (!(flags
& SECTION_DEBUG
))
10670 fputs (",#alloc", asm_out_file
);
10671 #if HAVE_GAS_SECTION_EXCLUDE
10672 if (flags
& SECTION_EXCLUDE
)
10673 fputs (",#exclude", asm_out_file
);
10675 if (flags
& SECTION_WRITE
)
10676 fputs (",#write", asm_out_file
);
10677 if (flags
& SECTION_TLS
)
10678 fputs (",#tls", asm_out_file
);
10679 if (flags
& SECTION_CODE
)
10680 fputs (",#execinstr", asm_out_file
);
10682 if (flags
& SECTION_NOTYPE
)
10684 else if (flags
& SECTION_BSS
)
10685 fputs (",#nobits", asm_out_file
);
10687 fputs (",#progbits", asm_out_file
);
10689 fputc ('\n', asm_out_file
);
10691 #endif /* TARGET_SOLARIS */
10693 /* We do not allow indirect calls to be optimized into sibling calls.
10695 We cannot use sibling calls when delayed branches are disabled
10696 because they will likely require the call delay slot to be filled.
10698 Also, on SPARC 32-bit we cannot emit a sibling call when the
10699 current function returns a structure. This is because the "unimp
10700 after call" convention would cause the callee to return to the
10701 wrong place. The generic code already disallows cases where the
10702 function being called returns a structure.
10704 It may seem strange how this last case could occur. Usually there
10705 is code after the call which jumps to epilogue code which dumps the
10706 return value into the struct return area. That ought to invalidate
10707 the sibling call right? Well, in the C++ case we can end up passing
10708 the pointer to the struct return area to a constructor (which returns
10709 void) and then nothing else happens. Such a sibling call would look
10710 valid without the added check here.
10712 VxWorks PIC PLT entries require the global pointer to be initialized
10713 on entry. We therefore can't emit sibling calls to them. */
10715 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
10718 && flag_delayed_branch
10719 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
10720 && !(TARGET_VXWORKS_RTP
10722 && !targetm
.binds_local_p (decl
)));
10725 /* libfunc renaming. */
10728 sparc_init_libfuncs (void)
10732 /* Use the subroutines that Sun's library provides for integer
10733 multiply and divide. The `*' prevents an underscore from
10734 being prepended by the compiler. .umul is a little faster
10736 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
10737 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
10738 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
10739 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
10740 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
10742 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
10743 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
10744 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
10745 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
10746 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
10747 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10749 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10750 is because with soft-float, the SFmode and DFmode sqrt
10751 instructions will be absent, and the compiler will notice and
10752 try to use the TFmode sqrt instruction for calls to the
10753 builtin function sqrt, but this fails. */
10755 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10757 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10758 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10759 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10760 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10761 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10762 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10764 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10765 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10766 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10767 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10769 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10770 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10771 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10772 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10774 if (DITF_CONVERSION_LIBFUNCS
)
10776 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10777 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10778 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10779 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10782 if (SUN_CONVERSION_LIBFUNCS
)
10784 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10785 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10786 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10787 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10792 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10793 do not exist in the library. Make sure the compiler does not
10794 emit calls to them by accident. (It should always use the
10795 hardware instructions.) */
10796 set_optab_libfunc (smul_optab
, SImode
, 0);
10797 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10798 set_optab_libfunc (udiv_optab
, SImode
, 0);
10799 set_optab_libfunc (smod_optab
, SImode
, 0);
10800 set_optab_libfunc (umod_optab
, SImode
, 0);
10802 if (SUN_INTEGER_MULTIPLY_64
)
10804 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10805 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10806 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10807 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10808 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10811 if (SUN_CONVERSION_LIBFUNCS
)
10813 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10814 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10815 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10816 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10821 /* SPARC builtins. */
10822 enum sparc_builtins
10824 /* FPU builtins. */
10825 SPARC_BUILTIN_LDFSR
,
10826 SPARC_BUILTIN_STFSR
,
10828 /* VIS 1.0 builtins. */
10829 SPARC_BUILTIN_FPACK16
,
10830 SPARC_BUILTIN_FPACK32
,
10831 SPARC_BUILTIN_FPACKFIX
,
10832 SPARC_BUILTIN_FEXPAND
,
10833 SPARC_BUILTIN_FPMERGE
,
10834 SPARC_BUILTIN_FMUL8X16
,
10835 SPARC_BUILTIN_FMUL8X16AU
,
10836 SPARC_BUILTIN_FMUL8X16AL
,
10837 SPARC_BUILTIN_FMUL8SUX16
,
10838 SPARC_BUILTIN_FMUL8ULX16
,
10839 SPARC_BUILTIN_FMULD8SUX16
,
10840 SPARC_BUILTIN_FMULD8ULX16
,
10841 SPARC_BUILTIN_FALIGNDATAV4HI
,
10842 SPARC_BUILTIN_FALIGNDATAV8QI
,
10843 SPARC_BUILTIN_FALIGNDATAV2SI
,
10844 SPARC_BUILTIN_FALIGNDATADI
,
10845 SPARC_BUILTIN_WRGSR
,
10846 SPARC_BUILTIN_RDGSR
,
10847 SPARC_BUILTIN_ALIGNADDR
,
10848 SPARC_BUILTIN_ALIGNADDRL
,
10849 SPARC_BUILTIN_PDIST
,
10850 SPARC_BUILTIN_EDGE8
,
10851 SPARC_BUILTIN_EDGE8L
,
10852 SPARC_BUILTIN_EDGE16
,
10853 SPARC_BUILTIN_EDGE16L
,
10854 SPARC_BUILTIN_EDGE32
,
10855 SPARC_BUILTIN_EDGE32L
,
10856 SPARC_BUILTIN_FCMPLE16
,
10857 SPARC_BUILTIN_FCMPLE32
,
10858 SPARC_BUILTIN_FCMPNE16
,
10859 SPARC_BUILTIN_FCMPNE32
,
10860 SPARC_BUILTIN_FCMPGT16
,
10861 SPARC_BUILTIN_FCMPGT32
,
10862 SPARC_BUILTIN_FCMPEQ16
,
10863 SPARC_BUILTIN_FCMPEQ32
,
10864 SPARC_BUILTIN_FPADD16
,
10865 SPARC_BUILTIN_FPADD16S
,
10866 SPARC_BUILTIN_FPADD32
,
10867 SPARC_BUILTIN_FPADD32S
,
10868 SPARC_BUILTIN_FPSUB16
,
10869 SPARC_BUILTIN_FPSUB16S
,
10870 SPARC_BUILTIN_FPSUB32
,
10871 SPARC_BUILTIN_FPSUB32S
,
10872 SPARC_BUILTIN_ARRAY8
,
10873 SPARC_BUILTIN_ARRAY16
,
10874 SPARC_BUILTIN_ARRAY32
,
10876 /* VIS 2.0 builtins. */
10877 SPARC_BUILTIN_EDGE8N
,
10878 SPARC_BUILTIN_EDGE8LN
,
10879 SPARC_BUILTIN_EDGE16N
,
10880 SPARC_BUILTIN_EDGE16LN
,
10881 SPARC_BUILTIN_EDGE32N
,
10882 SPARC_BUILTIN_EDGE32LN
,
10883 SPARC_BUILTIN_BMASK
,
10884 SPARC_BUILTIN_BSHUFFLEV4HI
,
10885 SPARC_BUILTIN_BSHUFFLEV8QI
,
10886 SPARC_BUILTIN_BSHUFFLEV2SI
,
10887 SPARC_BUILTIN_BSHUFFLEDI
,
10889 /* VIS 3.0 builtins. */
10890 SPARC_BUILTIN_CMASK8
,
10891 SPARC_BUILTIN_CMASK16
,
10892 SPARC_BUILTIN_CMASK32
,
10893 SPARC_BUILTIN_FCHKSM16
,
10894 SPARC_BUILTIN_FSLL16
,
10895 SPARC_BUILTIN_FSLAS16
,
10896 SPARC_BUILTIN_FSRL16
,
10897 SPARC_BUILTIN_FSRA16
,
10898 SPARC_BUILTIN_FSLL32
,
10899 SPARC_BUILTIN_FSLAS32
,
10900 SPARC_BUILTIN_FSRL32
,
10901 SPARC_BUILTIN_FSRA32
,
10902 SPARC_BUILTIN_PDISTN
,
10903 SPARC_BUILTIN_FMEAN16
,
10904 SPARC_BUILTIN_FPADD64
,
10905 SPARC_BUILTIN_FPSUB64
,
10906 SPARC_BUILTIN_FPADDS16
,
10907 SPARC_BUILTIN_FPADDS16S
,
10908 SPARC_BUILTIN_FPSUBS16
,
10909 SPARC_BUILTIN_FPSUBS16S
,
10910 SPARC_BUILTIN_FPADDS32
,
10911 SPARC_BUILTIN_FPADDS32S
,
10912 SPARC_BUILTIN_FPSUBS32
,
10913 SPARC_BUILTIN_FPSUBS32S
,
10914 SPARC_BUILTIN_FUCMPLE8
,
10915 SPARC_BUILTIN_FUCMPNE8
,
10916 SPARC_BUILTIN_FUCMPGT8
,
10917 SPARC_BUILTIN_FUCMPEQ8
,
10918 SPARC_BUILTIN_FHADDS
,
10919 SPARC_BUILTIN_FHADDD
,
10920 SPARC_BUILTIN_FHSUBS
,
10921 SPARC_BUILTIN_FHSUBD
,
10922 SPARC_BUILTIN_FNHADDS
,
10923 SPARC_BUILTIN_FNHADDD
,
10924 SPARC_BUILTIN_UMULXHI
,
10925 SPARC_BUILTIN_XMULX
,
10926 SPARC_BUILTIN_XMULXHI
,
10928 /* VIS 4.0 builtins. */
10929 SPARC_BUILTIN_FPADD8
,
10930 SPARC_BUILTIN_FPADDS8
,
10931 SPARC_BUILTIN_FPADDUS8
,
10932 SPARC_BUILTIN_FPADDUS16
,
10933 SPARC_BUILTIN_FPCMPLE8
,
10934 SPARC_BUILTIN_FPCMPGT8
,
10935 SPARC_BUILTIN_FPCMPULE16
,
10936 SPARC_BUILTIN_FPCMPUGT16
,
10937 SPARC_BUILTIN_FPCMPULE32
,
10938 SPARC_BUILTIN_FPCMPUGT32
,
10939 SPARC_BUILTIN_FPMAX8
,
10940 SPARC_BUILTIN_FPMAX16
,
10941 SPARC_BUILTIN_FPMAX32
,
10942 SPARC_BUILTIN_FPMAXU8
,
10943 SPARC_BUILTIN_FPMAXU16
,
10944 SPARC_BUILTIN_FPMAXU32
,
10945 SPARC_BUILTIN_FPMIN8
,
10946 SPARC_BUILTIN_FPMIN16
,
10947 SPARC_BUILTIN_FPMIN32
,
10948 SPARC_BUILTIN_FPMINU8
,
10949 SPARC_BUILTIN_FPMINU16
,
10950 SPARC_BUILTIN_FPMINU32
,
10951 SPARC_BUILTIN_FPSUB8
,
10952 SPARC_BUILTIN_FPSUBS8
,
10953 SPARC_BUILTIN_FPSUBUS8
,
10954 SPARC_BUILTIN_FPSUBUS16
,
10956 /* VIS 4.0B builtins. */
10958 /* Note that all the DICTUNPACK* entries should be kept
10960 SPARC_BUILTIN_FIRST_DICTUNPACK
,
10961 SPARC_BUILTIN_DICTUNPACK8
= SPARC_BUILTIN_FIRST_DICTUNPACK
,
10962 SPARC_BUILTIN_DICTUNPACK16
,
10963 SPARC_BUILTIN_DICTUNPACK32
,
10964 SPARC_BUILTIN_LAST_DICTUNPACK
= SPARC_BUILTIN_DICTUNPACK32
,
10966 /* Note that all the FPCMP*SHL entries should be kept
10968 SPARC_BUILTIN_FIRST_FPCMPSHL
,
10969 SPARC_BUILTIN_FPCMPLE8SHL
= SPARC_BUILTIN_FIRST_FPCMPSHL
,
10970 SPARC_BUILTIN_FPCMPGT8SHL
,
10971 SPARC_BUILTIN_FPCMPEQ8SHL
,
10972 SPARC_BUILTIN_FPCMPNE8SHL
,
10973 SPARC_BUILTIN_FPCMPLE16SHL
,
10974 SPARC_BUILTIN_FPCMPGT16SHL
,
10975 SPARC_BUILTIN_FPCMPEQ16SHL
,
10976 SPARC_BUILTIN_FPCMPNE16SHL
,
10977 SPARC_BUILTIN_FPCMPLE32SHL
,
10978 SPARC_BUILTIN_FPCMPGT32SHL
,
10979 SPARC_BUILTIN_FPCMPEQ32SHL
,
10980 SPARC_BUILTIN_FPCMPNE32SHL
,
10981 SPARC_BUILTIN_FPCMPULE8SHL
,
10982 SPARC_BUILTIN_FPCMPUGT8SHL
,
10983 SPARC_BUILTIN_FPCMPULE16SHL
,
10984 SPARC_BUILTIN_FPCMPUGT16SHL
,
10985 SPARC_BUILTIN_FPCMPULE32SHL
,
10986 SPARC_BUILTIN_FPCMPUGT32SHL
,
10987 SPARC_BUILTIN_FPCMPDE8SHL
,
10988 SPARC_BUILTIN_FPCMPDE16SHL
,
10989 SPARC_BUILTIN_FPCMPDE32SHL
,
10990 SPARC_BUILTIN_FPCMPUR8SHL
,
10991 SPARC_BUILTIN_FPCMPUR16SHL
,
10992 SPARC_BUILTIN_FPCMPUR32SHL
,
10993 SPARC_BUILTIN_LAST_FPCMPSHL
= SPARC_BUILTIN_FPCMPUR32SHL
,
10998 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10999 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
11001 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
11002 The instruction should require a constant operand of some sort. The
11003 function prints an error if OPVAL is not valid. */
11006 check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
11008 if (GET_CODE (opval
) != CONST_INT
)
11010 error ("%qs expects a constant argument", insn_data
[icode
].name
);
11014 if (!(*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
11016 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
11022 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
11023 function decl or NULL_TREE if the builtin was not added. */
11026 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
11030 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11034 sparc_builtins
[code
] = t
;
11035 sparc_builtins_icode
[code
] = icode
;
11041 /* Likewise, but also marks the function as "const". */
11044 def_builtin_const (const char *name
, enum insn_code icode
,
11045 enum sparc_builtins code
, tree type
)
11047 tree t
= def_builtin (name
, icode
, code
, type
);
11050 TREE_READONLY (t
) = 1;
11055 /* Implement the TARGET_INIT_BUILTINS target hook.
11056 Create builtin functions for special SPARC instructions. */
11059 sparc_init_builtins (void)
11062 sparc_fpu_init_builtins ();
11065 sparc_vis_init_builtins ();
11068 /* Create builtin functions for FPU instructions. */
11071 sparc_fpu_init_builtins (void)
11074 = build_function_type_list (void_type_node
,
11075 build_pointer_type (unsigned_type_node
), 0);
11076 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
11077 SPARC_BUILTIN_LDFSR
, ftype
);
11078 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
11079 SPARC_BUILTIN_STFSR
, ftype
);
11082 /* Create builtin functions for VIS instructions. */
11085 sparc_vis_init_builtins (void)
11087 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
11088 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
11089 tree v4hi
= build_vector_type (intHI_type_node
, 4);
11090 tree v2hi
= build_vector_type (intHI_type_node
, 2);
11091 tree v2si
= build_vector_type (intSI_type_node
, 2);
11092 tree v1si
= build_vector_type (intSI_type_node
, 1);
11094 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
11095 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
11096 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
11097 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
11098 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
11099 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
11100 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
11101 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
11102 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
11103 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
11104 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
11105 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
11106 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
11107 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
11108 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
11110 intDI_type_node
, 0);
11111 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
11113 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
11115 tree v8qi_ftype_df_si
= build_function_type_list (v8qi
, double_type_node
,
11116 intSI_type_node
, 0);
11117 tree v4hi_ftype_df_si
= build_function_type_list (v4hi
, double_type_node
,
11118 intSI_type_node
, 0);
11119 tree v2si_ftype_df_si
= build_function_type_list (v2si
, double_type_node
,
11120 intDI_type_node
, 0);
11121 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
11123 intDI_type_node
, 0);
11124 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
11126 intSI_type_node
, 0);
11127 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
11129 intSI_type_node
, 0);
11130 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
11132 intDI_type_node
, 0);
11133 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
11136 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
11139 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
11141 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
11143 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
11145 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
11147 tree void_ftype_di
= build_function_type_list (void_type_node
,
11148 intDI_type_node
, 0);
11149 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
11150 void_type_node
, 0);
11151 tree void_ftype_si
= build_function_type_list (void_type_node
,
11152 intSI_type_node
, 0);
11153 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
11155 float_type_node
, 0);
11156 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
11158 double_type_node
, 0);
11160 /* Packing and expanding vectors. */
11161 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
11162 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
11163 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
11164 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
11165 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
11166 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
11167 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
11168 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
11169 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
11170 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
11172 /* Multiplications. */
11173 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
11174 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
11175 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
11176 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
11177 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
11178 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
11179 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
11180 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
11181 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
11182 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
11183 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
11184 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
11185 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
11186 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
11188 /* Data aligning. */
11189 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
11190 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
11191 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
11192 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
11193 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
11194 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
11195 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
11196 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
11198 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
11199 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
11200 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
11201 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
11205 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
11206 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
11207 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
11208 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
11212 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
11213 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
11214 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
11215 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
11218 /* Pixel distance. */
11219 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
11220 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
11222 /* Edge handling. */
11225 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
11226 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
11227 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
11228 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
11229 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
11230 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
11231 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
11232 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
11233 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
11234 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
11235 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
11236 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
11240 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
11241 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
11242 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
11243 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
11244 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
11245 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
11246 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
11247 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
11248 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
11249 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
11250 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
11251 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
11254 /* Pixel compare. */
11257 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
11258 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
11259 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
11260 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
11261 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
11262 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
11263 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
11264 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
11265 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
11266 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
11267 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
11268 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
11269 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
11270 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
11271 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
11272 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
11276 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
11277 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
11278 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
11279 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
11280 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
11281 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
11282 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
11283 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
11284 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
11285 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
11286 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
11287 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
11288 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
11289 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
11290 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
11291 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
11294 /* Addition and subtraction. */
11295 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
11296 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
11297 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
11298 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
11299 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
11300 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
11301 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
11302 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
11303 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
11304 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
11305 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
11306 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
11307 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
11308 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
11309 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
11310 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
11312 /* Three-dimensional array addressing. */
11315 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
11316 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
11317 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
11318 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
11319 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
11320 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
11324 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
11325 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
11326 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
11327 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
11328 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
11329 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
11334 /* Edge handling. */
11337 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
11338 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
11339 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
11340 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
11341 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
11342 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
11343 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
11344 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
11345 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
11346 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
11347 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
11348 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
11352 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
11353 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
11354 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
11355 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
11356 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
11357 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
11358 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
11359 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
11360 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
11361 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
11362 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
11363 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
11366 /* Byte mask and shuffle. */
11368 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
11369 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
11371 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
11372 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
11373 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
11374 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
11375 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
11376 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
11377 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
11378 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
11379 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
11380 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
11387 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
11388 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
11389 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
11390 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
11391 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
11392 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
11396 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
11397 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
11398 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
11399 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
11400 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
11401 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
11404 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
11405 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
11407 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
11408 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
11409 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
11410 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
11411 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
11412 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
11413 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
11414 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
11415 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
11416 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
11417 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
11418 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
11419 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
11420 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
11421 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
11422 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
11425 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
11426 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
11428 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
11429 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
11431 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
11432 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
11433 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
11434 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
11435 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
11436 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
11438 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
11439 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
11440 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
11441 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
11442 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
11443 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
11444 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
11445 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
11446 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
11447 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
11448 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
11449 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
11450 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
11451 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
11452 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
11453 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
11457 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
11458 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
11459 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
11460 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
11461 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
11462 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
11463 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
11464 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
11468 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
11469 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
11470 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
11471 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
11472 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
11473 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
11474 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
11475 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
11478 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
11479 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
11480 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
11481 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
11482 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
11483 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
11484 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
11485 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
11486 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
11487 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
11488 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
11489 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
11491 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
11492 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
11493 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
11494 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
11495 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
11496 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
11501 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
11502 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
11503 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
11504 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
11505 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
11506 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
11507 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
11508 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
11513 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
11514 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
11515 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
11516 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
11517 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
11518 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
11519 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
11520 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
11521 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
11522 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11523 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
11524 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11528 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
11529 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
11530 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
11531 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
11532 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
11533 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
11534 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
11535 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
11536 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
11537 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11538 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
11539 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11542 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
11543 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
11544 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
11545 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
11546 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
11547 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
11548 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
11549 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
11550 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
11551 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
11552 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
11553 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
11554 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
11555 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
11556 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
11557 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
11558 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
11559 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
11560 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
11561 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
11562 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
11563 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
11564 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
11565 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
11566 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
11567 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
11568 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
11569 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
11570 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
11571 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
11572 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
11573 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
11578 def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8
,
11579 SPARC_BUILTIN_DICTUNPACK8
, v8qi_ftype_df_si
);
11580 def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16
,
11581 SPARC_BUILTIN_DICTUNPACK16
, v4hi_ftype_df_si
);
11582 def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32
,
11583 SPARC_BUILTIN_DICTUNPACK32
, v2si_ftype_df_si
);
11587 tree di_ftype_v8qi_v8qi_si
= build_function_type_list (intDI_type_node
,
11589 intSI_type_node
, 0);
11590 tree di_ftype_v4hi_v4hi_si
= build_function_type_list (intDI_type_node
,
11592 intSI_type_node
, 0);
11593 tree di_ftype_v2si_v2si_si
= build_function_type_list (intDI_type_node
,
11595 intSI_type_node
, 0);
11597 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl
,
11598 SPARC_BUILTIN_FPCMPLE8SHL
, di_ftype_v8qi_v8qi_si
);
11599 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl
,
11600 SPARC_BUILTIN_FPCMPGT8SHL
, di_ftype_v8qi_v8qi_si
);
11601 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl
,
11602 SPARC_BUILTIN_FPCMPEQ8SHL
, di_ftype_v8qi_v8qi_si
);
11603 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl
,
11604 SPARC_BUILTIN_FPCMPNE8SHL
, di_ftype_v8qi_v8qi_si
);
11606 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl
,
11607 SPARC_BUILTIN_FPCMPLE16SHL
, di_ftype_v4hi_v4hi_si
);
11608 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl
,
11609 SPARC_BUILTIN_FPCMPGT16SHL
, di_ftype_v4hi_v4hi_si
);
11610 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl
,
11611 SPARC_BUILTIN_FPCMPEQ16SHL
, di_ftype_v4hi_v4hi_si
);
11612 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl
,
11613 SPARC_BUILTIN_FPCMPNE16SHL
, di_ftype_v4hi_v4hi_si
);
11615 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl
,
11616 SPARC_BUILTIN_FPCMPLE32SHL
, di_ftype_v2si_v2si_si
);
11617 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl
,
11618 SPARC_BUILTIN_FPCMPGT32SHL
, di_ftype_v2si_v2si_si
);
11619 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl
,
11620 SPARC_BUILTIN_FPCMPEQ32SHL
, di_ftype_v2si_v2si_si
);
11621 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl
,
11622 SPARC_BUILTIN_FPCMPNE32SHL
, di_ftype_v2si_v2si_si
);
11625 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl
,
11626 SPARC_BUILTIN_FPCMPULE8SHL
, di_ftype_v8qi_v8qi_si
);
11627 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl
,
11628 SPARC_BUILTIN_FPCMPUGT8SHL
, di_ftype_v8qi_v8qi_si
);
11630 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl
,
11631 SPARC_BUILTIN_FPCMPULE16SHL
, di_ftype_v4hi_v4hi_si
);
11632 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl
,
11633 SPARC_BUILTIN_FPCMPUGT16SHL
, di_ftype_v4hi_v4hi_si
);
11635 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl
,
11636 SPARC_BUILTIN_FPCMPULE32SHL
, di_ftype_v2si_v2si_si
);
11637 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl
,
11638 SPARC_BUILTIN_FPCMPUGT32SHL
, di_ftype_v2si_v2si_si
);
11640 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl
,
11641 SPARC_BUILTIN_FPCMPDE8SHL
, di_ftype_v8qi_v8qi_si
);
11642 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl
,
11643 SPARC_BUILTIN_FPCMPDE16SHL
, di_ftype_v4hi_v4hi_si
);
11644 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl
,
11645 SPARC_BUILTIN_FPCMPDE32SHL
, di_ftype_v2si_v2si_si
);
11647 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl
,
11648 SPARC_BUILTIN_FPCMPUR8SHL
, di_ftype_v8qi_v8qi_si
);
11649 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl
,
11650 SPARC_BUILTIN_FPCMPUR16SHL
, di_ftype_v4hi_v4hi_si
);
11651 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl
,
11652 SPARC_BUILTIN_FPCMPUR32SHL
, di_ftype_v2si_v2si_si
);
11657 tree si_ftype_v8qi_v8qi_si
= build_function_type_list (intSI_type_node
,
11659 intSI_type_node
, 0);
11660 tree si_ftype_v4hi_v4hi_si
= build_function_type_list (intSI_type_node
,
11662 intSI_type_node
, 0);
11663 tree si_ftype_v2si_v2si_si
= build_function_type_list (intSI_type_node
,
11665 intSI_type_node
, 0);
11667 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl
,
11668 SPARC_BUILTIN_FPCMPLE8SHL
, si_ftype_v8qi_v8qi_si
);
11669 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl
,
11670 SPARC_BUILTIN_FPCMPGT8SHL
, si_ftype_v8qi_v8qi_si
);
11671 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl
,
11672 SPARC_BUILTIN_FPCMPEQ8SHL
, si_ftype_v8qi_v8qi_si
);
11673 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl
,
11674 SPARC_BUILTIN_FPCMPNE8SHL
, si_ftype_v8qi_v8qi_si
);
11676 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl
,
11677 SPARC_BUILTIN_FPCMPLE16SHL
, si_ftype_v4hi_v4hi_si
);
11678 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl
,
11679 SPARC_BUILTIN_FPCMPGT16SHL
, si_ftype_v4hi_v4hi_si
);
11680 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl
,
11681 SPARC_BUILTIN_FPCMPEQ16SHL
, si_ftype_v4hi_v4hi_si
);
11682 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl
,
11683 SPARC_BUILTIN_FPCMPNE16SHL
, si_ftype_v4hi_v4hi_si
);
11685 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl
,
11686 SPARC_BUILTIN_FPCMPLE32SHL
, si_ftype_v2si_v2si_si
);
11687 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl
,
11688 SPARC_BUILTIN_FPCMPGT32SHL
, si_ftype_v2si_v2si_si
);
11689 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl
,
11690 SPARC_BUILTIN_FPCMPEQ32SHL
, si_ftype_v2si_v2si_si
);
11691 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl
,
11692 SPARC_BUILTIN_FPCMPNE32SHL
, si_ftype_v2si_v2si_si
);
11695 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl
,
11696 SPARC_BUILTIN_FPCMPULE8SHL
, si_ftype_v8qi_v8qi_si
);
11697 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl
,
11698 SPARC_BUILTIN_FPCMPUGT8SHL
, si_ftype_v8qi_v8qi_si
);
11700 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl
,
11701 SPARC_BUILTIN_FPCMPULE16SHL
, si_ftype_v4hi_v4hi_si
);
11702 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl
,
11703 SPARC_BUILTIN_FPCMPUGT16SHL
, si_ftype_v4hi_v4hi_si
);
11705 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl
,
11706 SPARC_BUILTIN_FPCMPULE32SHL
, si_ftype_v2si_v2si_si
);
11707 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl
,
11708 SPARC_BUILTIN_FPCMPUGT32SHL
, si_ftype_v2si_v2si_si
);
11710 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl
,
11711 SPARC_BUILTIN_FPCMPDE8SHL
, si_ftype_v8qi_v8qi_si
);
11712 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl
,
11713 SPARC_BUILTIN_FPCMPDE16SHL
, si_ftype_v4hi_v4hi_si
);
11714 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl
,
11715 SPARC_BUILTIN_FPCMPDE32SHL
, si_ftype_v2si_v2si_si
);
11717 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl
,
11718 SPARC_BUILTIN_FPCMPUR8SHL
, si_ftype_v8qi_v8qi_si
);
11719 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl
,
11720 SPARC_BUILTIN_FPCMPUR16SHL
, si_ftype_v4hi_v4hi_si
);
11721 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl
,
11722 SPARC_BUILTIN_FPCMPUR32SHL
, si_ftype_v2si_v2si_si
);
11727 /* Implement TARGET_BUILTIN_DECL hook. */
11730 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11732 if (code
>= SPARC_BUILTIN_MAX
)
11733 return error_mark_node
;
11735 return sparc_builtins
[code
];
11738 /* Implemented TARGET_EXPAND_BUILTIN hook. */
11741 sparc_expand_builtin (tree exp
, rtx target
,
11742 rtx subtarget ATTRIBUTE_UNUSED
,
11743 machine_mode tmode ATTRIBUTE_UNUSED
,
11744 int ignore ATTRIBUTE_UNUSED
)
11746 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11747 enum sparc_builtins code
11748 = (enum sparc_builtins
) DECL_MD_FUNCTION_CODE (fndecl
);
11749 enum insn_code icode
= sparc_builtins_icode
[code
];
11750 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11751 call_expr_arg_iterator iter
;
11758 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11760 || GET_MODE (target
) != tmode
11761 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11762 op
[0] = gen_reg_rtx (tmode
);
11769 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11771 const struct insn_operand_data
*insn_op
;
11774 if (arg
== error_mark_node
)
11778 idx
= arg_count
- !nonvoid
;
11779 insn_op
= &insn_data
[icode
].operand
[idx
];
11780 op
[arg_count
] = expand_normal (arg
);
11782 /* Some of the builtins require constant arguments. We check
11784 if ((code
>= SPARC_BUILTIN_FIRST_FPCMPSHL
11785 && code
<= SPARC_BUILTIN_LAST_FPCMPSHL
11787 || (code
>= SPARC_BUILTIN_FIRST_DICTUNPACK
11788 && code
<= SPARC_BUILTIN_LAST_DICTUNPACK
11789 && arg_count
== 2))
11791 if (!check_constant_argument (icode
, idx
, op
[arg_count
]))
11795 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
11797 if (!address_operand (op
[arg_count
], SImode
))
11799 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
11800 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
11802 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
11805 else if (insn_op
->mode
== V1DImode
11806 && GET_MODE (op
[arg_count
]) == DImode
)
11807 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
11809 else if (insn_op
->mode
== V1SImode
11810 && GET_MODE (op
[arg_count
]) == SImode
)
11811 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
11813 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
11815 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
11821 pat
= GEN_FCN (icode
) (op
[0]);
11825 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11827 pat
= GEN_FCN (icode
) (op
[1]);
11830 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11833 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11836 gcc_unreachable ();
11844 return (nonvoid
? op
[0] : const0_rtx
);
11847 /* Return the upper 16 bits of the 8x16 multiplication. */
11850 sparc_vis_mul8x16 (int e8
, int e16
)
11852 return (e8
* e16
+ 128) / 256;
11855 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
11856 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
11859 sparc_handle_vis_mul8x16 (vec
<tree
> *n_elts
, enum sparc_builtins fncode
,
11860 tree inner_type
, tree cst0
, tree cst1
)
11862 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
11867 case SPARC_BUILTIN_FMUL8X16
:
11868 for (i
= 0; i
< num
; ++i
)
11871 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11872 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
11873 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11877 case SPARC_BUILTIN_FMUL8X16AU
:
11878 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
11880 for (i
= 0; i
< num
; ++i
)
11883 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11885 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11889 case SPARC_BUILTIN_FMUL8X16AL
:
11890 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
11892 for (i
= 0; i
< num
; ++i
)
11895 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11897 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11902 gcc_unreachable ();
11906 /* Implement TARGET_FOLD_BUILTIN hook.
11908 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
11909 result of the function call is ignored. NULL_TREE is returned if the
11910 function could not be folded. */
11913 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
11914 tree
*args
, bool ignore
)
11916 enum sparc_builtins code
11917 = (enum sparc_builtins
) DECL_MD_FUNCTION_CODE (fndecl
);
11918 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
11919 tree arg0
, arg1
, arg2
;
11924 case SPARC_BUILTIN_LDFSR
:
11925 case SPARC_BUILTIN_STFSR
:
11926 case SPARC_BUILTIN_ALIGNADDR
:
11927 case SPARC_BUILTIN_WRGSR
:
11928 case SPARC_BUILTIN_BMASK
:
11929 case SPARC_BUILTIN_CMASK8
:
11930 case SPARC_BUILTIN_CMASK16
:
11931 case SPARC_BUILTIN_CMASK32
:
11935 return build_zero_cst (rtype
);
11940 case SPARC_BUILTIN_FEXPAND
:
11944 if (TREE_CODE (arg0
) == VECTOR_CST
)
11946 tree inner_type
= TREE_TYPE (rtype
);
11949 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11950 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11952 unsigned HOST_WIDE_INT val
11953 = TREE_INT_CST_LOW (VECTOR_CST_ELT (arg0
, i
));
11954 n_elts
.quick_push (build_int_cst (inner_type
, val
<< 4));
11956 return n_elts
.build ();
11960 case SPARC_BUILTIN_FMUL8X16
:
11961 case SPARC_BUILTIN_FMUL8X16AU
:
11962 case SPARC_BUILTIN_FMUL8X16AL
:
11968 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11970 tree inner_type
= TREE_TYPE (rtype
);
11971 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11972 sparc_handle_vis_mul8x16 (&n_elts
, code
, inner_type
, arg0
, arg1
);
11973 return n_elts
.build ();
11977 case SPARC_BUILTIN_FPMERGE
:
11983 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11985 tree_vector_builder
n_elts (rtype
, 2 * VECTOR_CST_NELTS (arg0
), 1);
11987 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11989 n_elts
.quick_push (VECTOR_CST_ELT (arg0
, i
));
11990 n_elts
.quick_push (VECTOR_CST_ELT (arg1
, i
));
11993 return n_elts
.build ();
11997 case SPARC_BUILTIN_PDIST
:
11998 case SPARC_BUILTIN_PDISTN
:
12003 if (code
== SPARC_BUILTIN_PDIST
)
12009 arg2
= integer_zero_node
;
12011 if (TREE_CODE (arg0
) == VECTOR_CST
12012 && TREE_CODE (arg1
) == VECTOR_CST
12013 && TREE_CODE (arg2
) == INTEGER_CST
)
12015 bool overflow
= false;
12016 widest_int result
= wi::to_widest (arg2
);
12020 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
12022 tree e0
= VECTOR_CST_ELT (arg0
, i
);
12023 tree e1
= VECTOR_CST_ELT (arg1
, i
);
12025 wi::overflow_type neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
12027 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
12028 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
12029 if (wi::neg_p (tmp
))
12030 tmp
= wi::neg (tmp
, &neg2_ovf
);
12032 neg2_ovf
= wi::OVF_NONE
;
12033 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
12034 overflow
|= ((neg1_ovf
!= wi::OVF_NONE
)
12035 | (neg2_ovf
!= wi::OVF_NONE
)
12036 | (add1_ovf
!= wi::OVF_NONE
)
12037 | (add2_ovf
!= wi::OVF_NONE
));
12040 gcc_assert (!overflow
);
12042 return wide_int_to_tree (rtype
, result
);
12052 /* ??? This duplicates information provided to the compiler by the
12053 ??? scheduler description. Some day, teach genautomata to output
12054 ??? the latencies and then CSE will just use that. */
12057 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
12058 int opno ATTRIBUTE_UNUSED
,
12059 int *total
, bool speed ATTRIBUTE_UNUSED
)
12061 int code
= GET_CODE (x
);
12062 bool float_mode_p
= FLOAT_MODE_P (mode
);
12073 case CONST_WIDE_INT
:
12075 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
12077 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
12096 /* If outer-code was a sign or zero extension, a cost
12097 of COSTS_N_INSNS (1) was already added in. This is
12098 why we are subtracting it back out. */
12099 if (outer_code
== ZERO_EXTEND
)
12101 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
12103 else if (outer_code
== SIGN_EXTEND
)
12105 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
12107 else if (float_mode_p
)
12109 *total
= sparc_costs
->float_load
;
12113 *total
= sparc_costs
->int_load
;
12121 *total
= sparc_costs
->float_plusminus
;
12123 *total
= COSTS_N_INSNS (1);
12130 gcc_assert (float_mode_p
);
12131 *total
= sparc_costs
->float_mul
;
12134 if (GET_CODE (sub
) == NEG
)
12135 sub
= XEXP (sub
, 0);
12136 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
12139 if (GET_CODE (sub
) == NEG
)
12140 sub
= XEXP (sub
, 0);
12141 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
12147 *total
= sparc_costs
->float_mul
;
12148 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
12149 *total
= COSTS_N_INSNS (25);
12155 if (sparc_costs
->int_mul_bit_factor
)
12159 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
12161 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
12162 for (nbits
= 0; value
!= 0; value
&= value
- 1)
12170 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
12171 bit_cost
= COSTS_N_INSNS (bit_cost
);
12174 if (mode
== DImode
|| !TARGET_HARD_MUL
)
12175 *total
= sparc_costs
->int_mulX
+ bit_cost
;
12177 *total
= sparc_costs
->int_mul
+ bit_cost
;
12184 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
12193 if (mode
== DFmode
)
12194 *total
= sparc_costs
->float_div_df
;
12196 *total
= sparc_costs
->float_div_sf
;
12200 if (mode
== DImode
)
12201 *total
= sparc_costs
->int_divX
;
12203 *total
= sparc_costs
->int_div
;
12208 if (! float_mode_p
)
12210 *total
= COSTS_N_INSNS (1);
12217 case UNSIGNED_FLOAT
:
12221 case FLOAT_TRUNCATE
:
12222 *total
= sparc_costs
->float_move
;
12226 if (mode
== DFmode
)
12227 *total
= sparc_costs
->float_sqrt_df
;
12229 *total
= sparc_costs
->float_sqrt_sf
;
12234 *total
= sparc_costs
->float_cmp
;
12236 *total
= COSTS_N_INSNS (1);
12241 *total
= sparc_costs
->float_cmove
;
12243 *total
= sparc_costs
->int_cmove
;
12247 /* Handle the NAND vector patterns. */
12248 if (sparc_vector_mode_supported_p (mode
)
12249 && GET_CODE (XEXP (x
, 0)) == NOT
12250 && GET_CODE (XEXP (x
, 1)) == NOT
)
12252 *total
= COSTS_N_INSNS (1);
12263 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
12266 general_or_i64_p (reg_class_t rclass
)
12268 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
12271 /* Implement TARGET_REGISTER_MOVE_COST. */
12274 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
12275 reg_class_t from
, reg_class_t to
)
12277 bool need_memory
= false;
12279 /* This helps postreload CSE to eliminate redundant comparisons. */
12280 if (from
== NO_REGS
|| to
== NO_REGS
)
12283 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
12284 need_memory
= true;
12285 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
12286 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
12290 int size
= GET_MODE_SIZE (mode
);
12291 if (size
== 8 || size
== 4)
12293 if (! TARGET_ARCH32
|| size
== 4)
12299 need_memory
= true;
12304 if (sparc_cpu
== PROCESSOR_ULTRASPARC
12305 || sparc_cpu
== PROCESSOR_ULTRASPARC3
12306 || sparc_cpu
== PROCESSOR_NIAGARA
12307 || sparc_cpu
== PROCESSOR_NIAGARA2
12308 || sparc_cpu
== PROCESSOR_NIAGARA3
12309 || sparc_cpu
== PROCESSOR_NIAGARA4
12310 || sparc_cpu
== PROCESSOR_NIAGARA7
12311 || sparc_cpu
== PROCESSOR_M8
)
12320 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
12321 This is achieved by means of a manual dynamic stack space allocation in
12322 the current frame. We make the assumption that SEQ doesn't contain any
12323 function calls, with the possible exception of calls to the GOT helper. */
12326 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
12328 /* We must preserve the lowest 16 words for the register save area. */
12329 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
12330 /* We really need only 2 words of fresh stack space. */
12331 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
12334 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
12335 SPARC_STACK_BIAS
+ offset
));
12337 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
12338 emit_insn (gen_rtx_SET (slot
, reg
));
12340 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
12344 emit_insn (gen_rtx_SET (reg2
,
12345 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
12346 emit_insn (gen_rtx_SET (reg
, slot
));
12347 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
12350 /* Output the assembler code for a thunk function. THUNK_DECL is the
12351 declaration for the thunk function itself, FUNCTION is the decl for
12352 the target function. DELTA is an immediate constant offset to be
12353 added to THIS. If VCALL_OFFSET is nonzero, the word at address
12354 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
12357 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
12358 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12361 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
12362 rtx this_rtx
, funexp
;
12364 unsigned int int_arg_first
;
12366 reload_completed
= 1;
12367 epilogue_completed
= 1;
12369 emit_note (NOTE_INSN_PROLOGUE_END
);
12373 sparc_leaf_function_p
= 1;
12375 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12377 else if (flag_delayed_branch
)
12379 /* We will emit a regular sibcall below, so we need to instruct
12380 output_sibcall that we are in a leaf function. */
12381 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
12383 /* This will cause final.cc to invoke leaf_renumber_regs so we
12384 must behave as if we were in a not-yet-leafified function. */
12385 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
12389 /* We will emit the sibcall manually below, so we will need to
12390 manually spill non-leaf registers. */
12391 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
12393 /* We really are in a leaf function. */
12394 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12397 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
12398 returns a structure, the structure return pointer is there instead. */
12400 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12401 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
12403 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
12405 /* Add DELTA. When possible use a plain add, otherwise load it into
12406 a register first. */
12409 rtx delta_rtx
= GEN_INT (delta
);
12411 if (! SPARC_SIMM13_P (delta
))
12413 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12414 emit_move_insn (scratch
, delta_rtx
);
12415 delta_rtx
= scratch
;
12418 /* THIS_RTX += DELTA. */
12419 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
12422 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
12425 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
12426 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12428 gcc_assert (vcall_offset
< 0);
12430 /* SCRATCH = *THIS_RTX. */
12431 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
12433 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
12434 may not have any available scratch register at this point. */
12435 if (SPARC_SIMM13_P (vcall_offset
))
12437 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
12438 else if (! fixed_regs
[5]
12439 /* The below sequence is made up of at least 2 insns,
12440 while the default method may need only one. */
12441 && vcall_offset
< -8192)
12443 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
12444 emit_move_insn (scratch2
, vcall_offset_rtx
);
12445 vcall_offset_rtx
= scratch2
;
12449 rtx increment
= GEN_INT (-4096);
12451 /* VCALL_OFFSET is a negative number whose typical range can be
12452 estimated as -32768..0 in 32-bit mode. In almost all cases
12453 it is therefore cheaper to emit multiple add insns than
12454 spilling and loading the constant into a register (at least
12456 while (! SPARC_SIMM13_P (vcall_offset
))
12458 emit_insn (gen_add2_insn (scratch
, increment
));
12459 vcall_offset
+= 4096;
12461 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
12464 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
12465 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
12466 gen_rtx_PLUS (Pmode
,
12468 vcall_offset_rtx
)));
12470 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
12471 emit_insn (gen_add2_insn (this_rtx
, scratch
));
12474 /* Generate a tail call to the target function. */
12475 if (! TREE_USED (function
))
12477 assemble_external (function
);
12478 TREE_USED (function
) = 1;
12480 funexp
= XEXP (DECL_RTL (function
), 0);
12482 if (flag_delayed_branch
)
12484 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
12485 insn
= emit_call_insn (gen_sibcall (funexp
));
12486 SIBLING_CALL_P (insn
) = 1;
12490 /* The hoops we have to jump through in order to generate a sibcall
12491 without using delay slots... */
12492 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
12496 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
12498 load_got_register (); /* clobbers %o7 */
12499 if (!TARGET_VXWORKS_RTP
)
12500 pic_offset_table_rtx
= got_register_rtx
;
12501 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
12502 seq
= get_insns ();
12504 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
12506 else if (TARGET_ARCH32
)
12508 emit_insn (gen_rtx_SET (scratch
,
12509 gen_rtx_HIGH (SImode
, funexp
)));
12510 emit_insn (gen_rtx_SET (scratch
,
12511 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
12513 else /* TARGET_ARCH64 */
12515 switch (sparc_code_model
)
12519 /* The destination can serve as a temporary. */
12520 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
12525 /* The destination cannot serve as a temporary. */
12526 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
12528 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
12529 seq
= get_insns ();
12531 emit_and_preserve (seq
, spill_reg
, 0);
12535 gcc_unreachable ();
12539 emit_jump_insn (gen_indirect_jump (scratch
));
12544 /* Run just enough of rest_of_compilation to get the insns emitted.
12545 There's not really enough bulk here to make other passes such as
12546 instruction scheduling worth while. */
12547 insn
= get_insns ();
12548 shorten_branches (insn
);
12549 assemble_start_function (thunk_fndecl
, fnname
);
12550 final_start_function (insn
, file
, 1);
12551 final (insn
, file
, 1);
12552 final_end_function ();
12553 assemble_end_function (thunk_fndecl
, fnname
);
12555 reload_completed
= 0;
12556 epilogue_completed
= 0;
12559 /* Return true if sparc_output_mi_thunk would be able to output the
12560 assembler code for the thunk function specified by the arguments
12561 it is passed, and false otherwise. */
12563 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
12564 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
12565 HOST_WIDE_INT vcall_offset
,
12566 const_tree function ATTRIBUTE_UNUSED
)
12568 /* Bound the loop used in the default method above. */
12569 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
12572 /* How to allocate a 'struct machine_function'. */
12574 static struct machine_function
*
12575 sparc_init_machine_status (void)
12577 return ggc_cleared_alloc
<machine_function
> ();
12580 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
12582 static unsigned HOST_WIDE_INT
12583 sparc_asan_shadow_offset (void)
12585 return TARGET_ARCH64
? (HOST_WIDE_INT_1
<< 43) : (HOST_WIDE_INT_1
<< 29);
12588 /* This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL.
12589 We need to emit DTP-relative relocations. */
12592 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
12597 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
12600 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
12603 gcc_unreachable ();
12605 output_addr_const (file
, x
);
12609 /* Do whatever processing is required at the end of a file. */
12612 sparc_file_end (void)
12614 /* If we need to emit the special GOT helper function, do so now. */
12615 if (got_helper_needed
)
12617 const char *name
= XSTR (got_helper_rtx
, 0);
12618 #ifdef DWARF2_UNWIND_INFO
12622 if (USE_HIDDEN_LINKONCE
)
12624 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
12625 get_identifier (name
),
12626 build_function_type_list (void_type_node
,
12628 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
12629 NULL_TREE
, void_type_node
);
12630 TREE_PUBLIC (decl
) = 1;
12631 TREE_STATIC (decl
) = 1;
12632 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
12633 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
12634 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
12635 resolve_unique_section (decl
, 0, flag_function_sections
);
12636 allocate_struct_function (decl
, true);
12637 cfun
->is_thunk
= 1;
12638 current_function_decl
= decl
;
12639 init_varasm_status ();
12640 assemble_start_function (decl
, name
);
12644 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
12645 switch_to_section (text_section
);
12647 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
12648 ASM_OUTPUT_LABEL (asm_out_file
, name
);
12651 #ifdef DWARF2_UNWIND_INFO
12652 do_cfi
= dwarf2out_do_cfi_asm ();
12654 output_asm_insn (".cfi_startproc", NULL
);
12656 if (flag_delayed_branch
)
12658 output_asm_insn ("jmp\t%%o7+8", NULL
);
12659 output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx
);
12663 output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx
);
12664 output_asm_insn ("jmp\t%%o7+8", NULL
);
12665 output_asm_insn (" nop", NULL
);
12667 #ifdef DWARF2_UNWIND_INFO
12669 output_asm_insn (".cfi_endproc", NULL
);
12673 if (NEED_INDICATE_EXEC_STACK
)
12674 file_end_indicate_exec_stack ();
12676 #ifdef TARGET_SOLARIS
12677 solaris_file_end ();
12681 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12682 /* Implement TARGET_MANGLE_TYPE. */
12684 static const char *
12685 sparc_mangle_type (const_tree type
)
12688 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
12689 && TARGET_LONG_DOUBLE_128
)
12692 /* For all other types, use normal C++ mangling. */
12697 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
12698 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
12699 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
12702 sparc_emit_membar_for_model (enum memmodel model
,
12703 int load_store
, int before_after
)
12705 /* Bits for the MEMBAR mmask field. */
12706 const int LoadLoad
= 1;
12707 const int StoreLoad
= 2;
12708 const int LoadStore
= 4;
12709 const int StoreStore
= 8;
12711 int mm
= 0, implied
= 0;
12713 switch (sparc_memory_model
)
12716 /* Sequential Consistency. All memory transactions are immediately
12717 visible in sequential execution order. No barriers needed. */
12718 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
12722 /* Total Store Ordering: all memory transactions with store semantics
12723 are followed by an implied StoreStore. */
12724 implied
|= StoreStore
;
12726 /* If we're not looking for a raw barrer (before+after), then atomic
12727 operations get the benefit of being both load and store. */
12728 if (load_store
== 3 && before_after
== 1)
12729 implied
|= StoreLoad
;
12733 /* Partial Store Ordering: all memory transactions with load semantics
12734 are followed by an implied LoadLoad | LoadStore. */
12735 implied
|= LoadLoad
| LoadStore
;
12737 /* If we're not looking for a raw barrer (before+after), then atomic
12738 operations get the benefit of being both load and store. */
12739 if (load_store
== 3 && before_after
== 2)
12740 implied
|= StoreLoad
| StoreStore
;
12744 /* Relaxed Memory Ordering: no implicit bits. */
12748 gcc_unreachable ();
12751 if (before_after
& 1)
12753 if (is_mm_release (model
) || is_mm_acq_rel (model
)
12754 || is_mm_seq_cst (model
))
12756 if (load_store
& 1)
12757 mm
|= LoadLoad
| StoreLoad
;
12758 if (load_store
& 2)
12759 mm
|= LoadStore
| StoreStore
;
12762 if (before_after
& 2)
12764 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
12765 || is_mm_seq_cst (model
))
12767 if (load_store
& 1)
12768 mm
|= LoadLoad
| LoadStore
;
12769 if (load_store
& 2)
12770 mm
|= StoreLoad
| StoreStore
;
12774 /* Remove the bits implied by the system memory model. */
12777 /* For raw barriers (before+after), always emit a barrier.
12778 This will become a compile-time barrier if needed. */
12779 if (mm
|| before_after
== 3)
12780 emit_insn (gen_membar (GEN_INT (mm
)));
12783 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
12784 compare and swap on the word containing the byte or half-word. */
12787 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
12788 rtx oldval
, rtx newval
)
12790 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
12791 rtx addr
= gen_reg_rtx (Pmode
);
12792 rtx off
= gen_reg_rtx (SImode
);
12793 rtx oldv
= gen_reg_rtx (SImode
);
12794 rtx newv
= gen_reg_rtx (SImode
);
12795 rtx oldvalue
= gen_reg_rtx (SImode
);
12796 rtx newvalue
= gen_reg_rtx (SImode
);
12797 rtx res
= gen_reg_rtx (SImode
);
12798 rtx resv
= gen_reg_rtx (SImode
);
12799 rtx memsi
, val
, mask
, cc
;
12801 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
12803 if (Pmode
!= SImode
)
12804 addr1
= gen_lowpart (SImode
, addr1
);
12805 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
12807 memsi
= gen_rtx_MEM (SImode
, addr
);
12808 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
12809 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
12811 val
= copy_to_reg (memsi
);
12813 emit_insn (gen_rtx_SET (off
,
12814 gen_rtx_XOR (SImode
, off
,
12815 GEN_INT (GET_MODE (mem
) == QImode
12818 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
12820 if (GET_MODE (mem
) == QImode
)
12821 mask
= force_reg (SImode
, GEN_INT (0xff));
12823 mask
= force_reg (SImode
, GEN_INT (0xffff));
12825 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
12827 emit_insn (gen_rtx_SET (val
,
12828 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12831 oldval
= gen_lowpart (SImode
, oldval
);
12832 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
12834 newval
= gen_lowpart_common (SImode
, newval
);
12835 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
12837 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
12839 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
12841 rtx_code_label
*end_label
= gen_label_rtx ();
12842 rtx_code_label
*loop_label
= gen_label_rtx ();
12843 emit_label (loop_label
);
12845 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
12847 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
12849 emit_move_insn (bool_result
, const1_rtx
);
12851 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
12853 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
12855 emit_insn (gen_rtx_SET (resv
,
12856 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12859 emit_move_insn (bool_result
, const0_rtx
);
12861 cc
= gen_compare_reg_1 (NE
, resv
, val
);
12862 emit_insn (gen_rtx_SET (val
, resv
));
12864 /* Use cbranchcc4 to separate the compare and branch! */
12865 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
12866 cc
, const0_rtx
, loop_label
));
12868 emit_label (end_label
);
12870 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
12872 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
12874 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
12877 /* Expand code to perform a compare-and-swap. */
12880 sparc_expand_compare_and_swap (rtx operands
[])
12882 rtx bval
, retval
, mem
, oldval
, newval
;
12884 enum memmodel model
;
12886 bval
= operands
[0];
12887 retval
= operands
[1];
12889 oldval
= operands
[3];
12890 newval
= operands
[4];
12891 model
= (enum memmodel
) INTVAL (operands
[6]);
12892 mode
= GET_MODE (mem
);
12894 sparc_emit_membar_for_model (model
, 3, 1);
12896 if (reg_overlap_mentioned_p (retval
, oldval
))
12897 oldval
= copy_to_reg (oldval
);
12899 if (mode
== QImode
|| mode
== HImode
)
12900 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
12903 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
12906 if (mode
== SImode
)
12907 gen
= gen_atomic_compare_and_swapsi_1
;
12909 gen
= gen_atomic_compare_and_swapdi_1
;
12910 emit_insn (gen (retval
, mem
, oldval
, newval
));
12912 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
12914 convert_move (bval
, x
, 1);
12917 sparc_emit_membar_for_model (model
, 3, 2);
12921 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
12925 sel
= gen_lowpart (DImode
, sel
);
12929 /* inp = xxxxxxxAxxxxxxxB */
12930 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12931 NULL_RTX
, 1, OPTAB_DIRECT
);
12932 /* t_1 = ....xxxxxxxAxxx. */
12933 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12934 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
12935 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12936 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
12937 /* sel = .......B */
12938 /* t_1 = ...A.... */
12939 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12940 /* sel = ...A...B */
12941 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
12942 /* sel = AAAABBBB * 4 */
12943 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
12944 /* sel = { A*4, A*4+1, A*4+2, ... } */
12948 /* inp = xxxAxxxBxxxCxxxD */
12949 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12950 NULL_RTX
, 1, OPTAB_DIRECT
);
12951 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12952 NULL_RTX
, 1, OPTAB_DIRECT
);
12953 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
12954 NULL_RTX
, 1, OPTAB_DIRECT
);
12955 /* t_1 = ..xxxAxxxBxxxCxx */
12956 /* t_2 = ....xxxAxxxBxxxC */
12957 /* t_3 = ......xxxAxxxBxx */
12958 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12960 NULL_RTX
, 1, OPTAB_DIRECT
);
12961 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12963 NULL_RTX
, 1, OPTAB_DIRECT
);
12964 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
12965 GEN_INT (0x070000),
12966 NULL_RTX
, 1, OPTAB_DIRECT
);
12967 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
12968 GEN_INT (0x07000000),
12969 NULL_RTX
, 1, OPTAB_DIRECT
);
12970 /* sel = .......D */
12971 /* t_1 = .....C.. */
12972 /* t_2 = ...B.... */
12973 /* t_3 = .A...... */
12974 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12975 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
12976 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
12977 /* sel = .A.B.C.D */
12978 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
12979 /* sel = AABBCCDD * 2 */
12980 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
12981 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
12985 /* input = xAxBxCxDxExFxGxH */
12986 sel
= expand_simple_binop (DImode
, AND
, sel
,
12987 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
12989 NULL_RTX
, 1, OPTAB_DIRECT
);
12990 /* sel = .A.B.C.D.E.F.G.H */
12991 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
12992 NULL_RTX
, 1, OPTAB_DIRECT
);
12993 /* t_1 = ..A.B.C.D.E.F.G. */
12994 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12995 NULL_RTX
, 1, OPTAB_DIRECT
);
12996 /* sel = .AABBCCDDEEFFGGH */
12997 sel
= expand_simple_binop (DImode
, AND
, sel
,
12998 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
13000 NULL_RTX
, 1, OPTAB_DIRECT
);
13001 /* sel = ..AB..CD..EF..GH */
13002 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
13003 NULL_RTX
, 1, OPTAB_DIRECT
);
13004 /* t_1 = ....AB..CD..EF.. */
13005 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
13006 NULL_RTX
, 1, OPTAB_DIRECT
);
13007 /* sel = ..ABABCDCDEFEFGH */
13008 sel
= expand_simple_binop (DImode
, AND
, sel
,
13009 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
13010 NULL_RTX
, 1, OPTAB_DIRECT
);
13011 /* sel = ....ABCD....EFGH */
13012 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
13013 NULL_RTX
, 1, OPTAB_DIRECT
);
13014 /* t_1 = ........ABCD.... */
13015 sel
= gen_lowpart (SImode
, sel
);
13016 t_1
= gen_lowpart (SImode
, t_1
);
13020 gcc_unreachable ();
13023 /* Always perform the final addition/merge within the bmask insn. */
13024 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, t_1
));
13027 /* Implement TARGET_VEC_PERM_CONST. */
13030 sparc_vectorize_vec_perm_const (machine_mode vmode
, machine_mode op_mode
,
13031 rtx target
, rtx op0
, rtx op1
,
13032 const vec_perm_indices
&sel
)
13034 if (vmode
!= op_mode
)
13040 /* All 8-byte permutes are supported. */
13042 return GET_MODE_SIZE (vmode
) == 8;
13044 /* Force target-independent code to convert constant permutations on other
13045 modes down to V8QI. Rely on this to avoid the complexity of the byte
13046 order of the permutation. */
13047 if (vmode
!= V8QImode
)
13050 rtx nop0
= force_reg (vmode
, op0
);
13054 op1
= force_reg (vmode
, op1
);
13056 unsigned int i
, mask
;
13057 for (i
= mask
= 0; i
< 8; ++i
)
13058 mask
|= (sel
[i
] & 0xf) << (28 - i
*4);
13059 rtx mask_rtx
= force_reg (SImode
, gen_int_mode (mask
, SImode
));
13061 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), mask_rtx
, const0_rtx
));
13062 emit_insn (gen_bshufflev8qi_vis (target
, op0
, op1
));
13066 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
13069 sparc_frame_pointer_required (void)
13071 /* If the stack pointer is dynamically modified in the function, it cannot
13072 serve as the frame pointer. */
13073 if (cfun
->calls_alloca
)
13076 /* If the function receives nonlocal gotos, it needs to save the frame
13077 pointer in the nonlocal_goto_save_area object. */
13078 if (cfun
->has_nonlocal_label
)
13081 /* In flat mode, that's it. */
13085 /* Otherwise, the frame pointer is required if the function isn't leaf, but
13086 we cannot use sparc_leaf_function_p since it hasn't been computed yet. */
13087 return !(optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ());
13090 /* The way this is structured, we can't eliminate SFP in favor of SP
13091 if the frame pointer is required: we want to use the SFP->HFP elimination
13092 in that case. But the test in update_eliminables doesn't know we are
13093 assuming below that we only do the former elimination. */
13096 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
13098 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
13101 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
13102 they won't be allocated. */
13105 sparc_conditional_register_usage (void)
13107 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
13108 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13109 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
13110 /* then honor it. */
13111 if (TARGET_ARCH32
&& fixed_regs
[5])
13113 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
13118 for (regno
= SPARC_FIRST_V9_FP_REG
;
13119 regno
<= SPARC_LAST_V9_FP_REG
;
13121 fixed_regs
[regno
] = 1;
13122 /* %fcc0 is used by v8 and v9. */
13123 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
13124 regno
<= SPARC_LAST_V9_FCC_REG
;
13126 fixed_regs
[regno
] = 1;
13131 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
13132 fixed_regs
[regno
] = 1;
13134 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
13135 /* then honor it. Likewise with g3 and g4. */
13136 if (fixed_regs
[2] == 2)
13137 fixed_regs
[2] = ! TARGET_APP_REGS
;
13138 if (fixed_regs
[3] == 2)
13139 fixed_regs
[3] = ! TARGET_APP_REGS
;
13140 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
13141 fixed_regs
[4] = ! TARGET_APP_REGS
;
13142 else if (TARGET_CM_EMBMEDANY
)
13144 else if (fixed_regs
[4] == 2)
13147 /* Disable leaf function optimization in flat mode. */
13149 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
13152 global_regs
[SPARC_GSR_REG
] = 1;
13155 /* Implement TARGET_USE_PSEUDO_PIC_REG. */
13158 sparc_use_pseudo_pic_reg (void)
13160 return !TARGET_VXWORKS_RTP
&& flag_pic
;
13163 /* Implement TARGET_INIT_PIC_REG. */
13166 sparc_init_pic_reg (void)
13171 /* In PIC mode, we need to always initialize the PIC register if optimization
13172 is enabled, because we are called from IRA and LRA may later force things
13173 to the constant pool for optimization purposes. */
13174 if (!flag_pic
|| (!crtl
->uses_pic_offset_table
&& !optimize
))
13178 load_got_register ();
13179 if (!TARGET_VXWORKS_RTP
)
13180 emit_move_insn (pic_offset_table_rtx
, got_register_rtx
);
13181 seq
= get_insns ();
13184 entry_edge
= single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
13185 insert_insn_on_edge (seq
, entry_edge
);
13186 commit_one_edge_insertion (entry_edge
);
13189 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
13191 - We can't load constants into FP registers.
13192 - We can't load FP constants into integer registers when soft-float,
13193 because there is no soft-float pattern with a r/F constraint.
13194 - We can't load FP constants into integer registers for TFmode unless
13195 it is 0.0L, because there is no movtf pattern with a r/F constraint.
13196 - Try and reload integer constants (symbolic or otherwise) back into
13197 registers directly, rather than having them dumped to memory. */
13200 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
13202 machine_mode mode
= GET_MODE (x
);
13203 if (CONSTANT_P (x
))
13205 if (FP_REG_CLASS_P (rclass
)
13206 || rclass
== GENERAL_OR_FP_REGS
13207 || rclass
== GENERAL_OR_EXTRA_FP_REGS
13208 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
13209 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
13212 if (GET_MODE_CLASS (mode
) == MODE_INT
)
13213 return GENERAL_REGS
;
13215 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
13217 if (! FP_REG_CLASS_P (rclass
)
13218 || !(const_zero_operand (x
, mode
)
13219 || const_all_ones_operand (x
, mode
)))
13226 && (rclass
== EXTRA_FP_REGS
13227 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
13229 int regno
= true_regnum (x
);
13231 if (SPARC_INT_REG_P (regno
))
13232 return (rclass
== EXTRA_FP_REGS
13233 ? FP_REGS
: GENERAL_OR_FP_REGS
);
13239 /* Return true if we use LRA instead of reload pass. */
13247 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
13248 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
13251 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
13255 gcc_assert (! TARGET_ARCH64
);
13257 if (sparc_check_64 (operands
[1], insn
) <= 0)
13258 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
13259 if (which_alternative
== 1)
13260 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
13261 if (GET_CODE (operands
[2]) == CONST_INT
)
13263 if (which_alternative
== 1)
13265 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13266 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
13267 output_asm_insn (mulstr
, operands
);
13268 return "srlx\t%L0, 32, %H0";
13272 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13273 output_asm_insn ("or\t%L1, %3, %3", operands
);
13274 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
13275 output_asm_insn (mulstr
, operands
);
13276 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13277 return "mov\t%3, %L0";
13280 else if (rtx_equal_p (operands
[1], operands
[2]))
13282 if (which_alternative
== 1)
13284 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13285 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
13286 output_asm_insn (mulstr
, operands
);
13287 return "srlx\t%L0, 32, %H0";
13291 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13292 output_asm_insn ("or\t%L1, %3, %3", operands
);
13293 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
13294 output_asm_insn (mulstr
, operands
);
13295 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13296 return "mov\t%3, %L0";
13299 if (sparc_check_64 (operands
[2], insn
) <= 0)
13300 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
13301 if (which_alternative
== 1)
13303 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13304 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
13305 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
13306 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
13307 output_asm_insn (mulstr
, operands
);
13308 return "srlx\t%L0, 32, %H0";
13312 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13313 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
13314 output_asm_insn ("or\t%L1, %3, %3", operands
);
13315 output_asm_insn ("or\t%L2, %4, %4", operands
);
13316 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
13317 output_asm_insn (mulstr
, operands
);
13318 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13319 return "mov\t%3, %L0";
13323 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13324 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
13325 and INNER_MODE are the modes describing TARGET. */
13328 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
13329 machine_mode inner_mode
)
13331 rtx t1
, final_insn
, sel
;
13334 t1
= gen_reg_rtx (mode
);
13336 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
13337 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
13342 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
13343 bmask
= 0x45674567;
13346 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
13347 bmask
= 0x67676767;
13350 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
13351 bmask
= 0x77777777;
13354 gcc_unreachable ();
13357 sel
= force_reg (SImode
, GEN_INT (bmask
));
13358 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, const0_rtx
));
13359 emit_insn (final_insn
);
13362 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13363 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
13366 vector_init_fpmerge (rtx target
, rtx elt
)
13368 rtx t1
, t2
, t2_low
, t3
, t3_low
;
13370 t1
= gen_reg_rtx (V4QImode
);
13371 elt
= convert_modes (SImode
, QImode
, elt
, true);
13372 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13374 t2
= gen_reg_rtx (V8QImode
);
13375 t2_low
= gen_lowpart (V4QImode
, t2
);
13376 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
13378 t3
= gen_reg_rtx (V8QImode
);
13379 t3_low
= gen_lowpart (V4QImode
, t3
);
13380 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
13382 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
13385 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13386 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
13389 vector_init_faligndata (rtx target
, rtx elt
)
13391 rtx t1
= gen_reg_rtx (V4HImode
);
13394 elt
= convert_modes (SImode
, HImode
, elt
, true);
13395 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13397 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
13398 force_reg (SImode
, GEN_INT (6)),
13401 for (i
= 0; i
< 4; i
++)
13402 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
13405 /* Emit code to initialize TARGET to values for individual fields VALS. */
13408 sparc_expand_vector_init (rtx target
, rtx vals
)
13410 const machine_mode mode
= GET_MODE (target
);
13411 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
13412 const int n_elts
= GET_MODE_NUNITS (mode
);
13414 bool all_same
= true;
13417 for (i
= 0; i
< n_elts
; i
++)
13419 rtx x
= XVECEXP (vals
, 0, i
);
13420 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
13423 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
13429 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
13433 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
13435 if (GET_MODE_SIZE (inner_mode
) == 4)
13437 emit_move_insn (gen_lowpart (SImode
, target
),
13438 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
13441 else if (GET_MODE_SIZE (inner_mode
) == 8)
13443 emit_move_insn (gen_lowpart (DImode
, target
),
13444 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
13448 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
13449 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
13451 emit_move_insn (gen_highpart (word_mode
, target
),
13452 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
13453 emit_move_insn (gen_lowpart (word_mode
, target
),
13454 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
13458 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
13462 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
13465 if (mode
== V8QImode
)
13467 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
13470 if (mode
== V4HImode
)
13472 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
13477 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
13478 for (i
= 0; i
< n_elts
; i
++)
13479 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
13480 i
* GET_MODE_SIZE (inner_mode
)),
13481 XVECEXP (vals
, 0, i
));
13482 emit_move_insn (target
, mem
);
13485 /* Implement TARGET_SECONDARY_RELOAD. */
13488 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
13489 machine_mode mode
, secondary_reload_info
*sri
)
13491 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13493 sri
->icode
= CODE_FOR_nothing
;
13494 sri
->extra_cost
= 0;
13496 /* We need a temporary when loading/storing a HImode/QImode value
13497 between memory and the FPU registers. This can happen when combine puts
13498 a paradoxical subreg in a float/fix conversion insn. */
13499 if (FP_REG_CLASS_P (rclass
)
13500 && (mode
== HImode
|| mode
== QImode
)
13501 && (GET_CODE (x
) == MEM
13502 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
13503 && true_regnum (x
) == -1)))
13504 return GENERAL_REGS
;
13506 /* On 32-bit we need a temporary when loading/storing a DFmode value
13507 between unaligned memory and the upper FPU registers. */
13509 && rclass
== EXTRA_FP_REGS
13511 && GET_CODE (x
) == MEM
13512 && ! mem_min_alignment (x
, 8))
13515 if (((TARGET_CM_MEDANY
13516 && symbolic_operand (x
, mode
))
13517 || (TARGET_CM_EMBMEDANY
13518 && text_segment_operand (x
, mode
)))
13522 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
13524 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
13528 if (TARGET_VIS3
&& TARGET_ARCH32
)
13530 int regno
= true_regnum (x
);
13532 /* When using VIS3 fp<-->int register moves, on 32-bit we have
13533 to move 8-byte values in 4-byte pieces. This only works via
13534 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
13535 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
13536 an FP_REGS intermediate move. */
13537 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
13538 || ((general_or_i64_p (rclass
)
13539 || rclass
== GENERAL_OR_FP_REGS
)
13540 && SPARC_FP_REG_P (regno
)))
13542 sri
->extra_cost
= 2;
13550 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
13552 On SPARC when not VIS3 it is not possible to directly move data
13553 between GENERAL_REGS and FP_REGS. */
13556 sparc_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
13557 reg_class_t class2
)
13559 return ((FP_REG_CLASS_P (class1
) != FP_REG_CLASS_P (class2
))
13561 || GET_MODE_SIZE (mode
) > 8
13562 || GET_MODE_SIZE (mode
) < 4));
13565 /* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
13567 get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
13568 because the movsi and movsf patterns don't handle r/f moves.
13569 For v8 we copy the default definition. */
13571 static machine_mode
13572 sparc_secondary_memory_needed_mode (machine_mode mode
)
13576 if (GET_MODE_BITSIZE (mode
) < 32)
13577 return mode_for_size (32, GET_MODE_CLASS (mode
), 0).require ();
13582 if (GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
13583 return mode_for_size (BITS_PER_WORD
,
13584 GET_MODE_CLASS (mode
), 0).require ();
13589 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
13590 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
13593 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
13595 enum rtx_code rc
= GET_CODE (operands
[1]);
13596 machine_mode cmp_mode
;
13597 rtx cc_reg
, dst
, cmp
;
13600 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
13603 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
13604 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
13606 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
13607 rc
= GET_CODE (cmp
);
13610 if (! rtx_equal_p (operands
[2], dst
)
13611 && ! rtx_equal_p (operands
[3], dst
))
13613 if (reg_overlap_mentioned_p (dst
, cmp
))
13614 dst
= gen_reg_rtx (mode
);
13616 emit_move_insn (dst
, operands
[3]);
13618 else if (operands
[2] == dst
)
13620 operands
[2] = operands
[3];
13622 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
13623 rc
= reverse_condition_maybe_unordered (rc
);
13625 rc
= reverse_condition (rc
);
13628 if (XEXP (cmp
, 1) == const0_rtx
13629 && GET_CODE (XEXP (cmp
, 0)) == REG
13630 && cmp_mode
== DImode
13631 && v9_regcmp_p (rc
))
13632 cc_reg
= XEXP (cmp
, 0);
13634 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
13636 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
13638 emit_insn (gen_rtx_SET (dst
,
13639 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
13641 if (dst
!= operands
[0])
13642 emit_move_insn (operands
[0], dst
);
13647 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
13648 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
13649 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
13650 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
13651 code to be used for the condition mask. */
13654 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
13656 enum rtx_code code
= signed_condition (GET_CODE (operands
[3]));
13657 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
13659 mask
= gen_reg_rtx (Pmode
);
13660 cop0
= operands
[4];
13661 cop1
= operands
[5];
13662 if (code
== LT
|| code
== GE
)
13664 code
= swap_condition (code
);
13665 std::swap (cop0
, cop1
);
13668 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
13670 fcmp
= gen_rtx_UNSPEC (Pmode
,
13671 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
13674 cmask
= gen_rtx_UNSPEC (DImode
,
13675 gen_rtvec (2, mask
, gsr
),
13678 bshuf
= gen_rtx_UNSPEC (mode
,
13679 gen_rtvec (3, operands
[1], operands
[2], gsr
),
13682 emit_insn (gen_rtx_SET (mask
, fcmp
));
13683 emit_insn (gen_rtx_SET (gsr
, cmask
));
13685 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
13688 /* On the SPARC, any mode which naturally allocates into the single float
13689 registers should return 4 here. */
13692 sparc_regmode_natural_size (machine_mode mode
)
13694 const enum mode_class cl
= GET_MODE_CLASS (mode
);
13696 if ((cl
== MODE_FLOAT
|| cl
== MODE_VECTOR_INT
) && GET_MODE_SIZE (mode
) <= 4)
13699 return UNITS_PER_WORD
;
13702 /* Implement TARGET_HARD_REGNO_NREGS.
13704 On SPARC, ordinary registers hold 32 bits worth; this means both
13705 integer and floating point registers. On v9, integer regs hold 64
13706 bits worth; floating point regs hold 32 bits worth (this includes the
13707 new fp regs as even the odd ones are included in the hard register
13710 static unsigned int
13711 sparc_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
13713 if (regno
== SPARC_GSR_REG
)
13717 if (SPARC_INT_REG_P (regno
) || regno
== FRAME_POINTER_REGNUM
)
13718 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13719 return CEIL (GET_MODE_SIZE (mode
), 4);
13721 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13724 /* Implement TARGET_HARD_REGNO_MODE_OK.
13726 ??? Because of the funny way we pass parameters we should allow certain
13727 ??? types of float/complex values to be in integer registers during
13728 ??? RTL generation. This only matters on arch32. */
13731 sparc_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
13733 return (hard_regno_mode_classes
[regno
] & sparc_mode_class
[mode
]) != 0;
13736 /* Implement TARGET_MODES_TIEABLE_P.
13738 For V9 we have to deal with the fact that only the lower 32 floating
13739 point registers are 32-bit addressable. */
13742 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13744 enum mode_class mclass1
, mclass2
;
13745 unsigned short size1
, size2
;
13747 if (mode1
== mode2
)
13750 mclass1
= GET_MODE_CLASS (mode1
);
13751 mclass2
= GET_MODE_CLASS (mode2
);
13752 if (mclass1
!= mclass2
)
13758 /* Classes are the same and we are V9 so we have to deal with upper
13759 vs. lower floating point registers. If one of the modes is a
13760 4-byte mode, and the other is not, we have to mark them as not
13761 tieable because only the lower 32 floating point register are
13762 addressable 32-bits at a time.
13764 We can't just test explicitly for SFmode, otherwise we won't
13765 cover the vector mode cases properly. */
13767 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
13770 size1
= GET_MODE_SIZE (mode1
);
13771 size2
= GET_MODE_SIZE (mode2
);
13772 if ((size1
> 4 && size2
== 4)
13773 || (size2
> 4 && size1
== 4))
13779 /* Implement TARGET_CSTORE_MODE. */
13781 static scalar_int_mode
13782 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
13784 return (TARGET_ARCH64
? DImode
: SImode
);
13787 /* Return the compound expression made of T1 and T2. */
13790 compound_expr (tree t1
, tree t2
)
13792 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
13795 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
13798 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
13803 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
13804 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
13806 /* We generate the equivalent of feholdexcept (&fenv_var):
13808 unsigned int fenv_var;
13809 __builtin_store_fsr (&fenv_var);
13811 unsigned int tmp1_var;
13812 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
13814 __builtin_load_fsr (&tmp1_var); */
13816 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
13817 TREE_ADDRESSABLE (fenv_var
) = 1;
13818 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
13819 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
13821 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
13822 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
13824 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
13825 TREE_ADDRESSABLE (tmp1_var
) = 1;
13826 tree masked_fenv_var
13827 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
13828 build_int_cst (unsigned_type_node
,
13829 ~(accrued_exception_mask
| trap_enable_mask
)));
13831 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
13832 NULL_TREE
, NULL_TREE
);
13834 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
13835 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
13836 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13838 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
13840 /* We reload the value of tmp1_var to clear the exceptions:
13842 __builtin_load_fsr (&tmp1_var); */
13844 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13846 /* We generate the equivalent of feupdateenv (&fenv_var):
13848 unsigned int tmp2_var;
13849 __builtin_store_fsr (&tmp2_var);
13851 __builtin_load_fsr (&fenv_var);
13853 if (SPARC_LOW_FE_EXCEPT_VALUES)
13855 __atomic_feraiseexcept ((int) tmp2_var); */
13857 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
13858 TREE_ADDRESSABLE (tmp2_var
) = 1;
13859 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
13861 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
13862 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
13864 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
13866 tree atomic_feraiseexcept
13867 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
13869 = build_call_expr (atomic_feraiseexcept
, 1,
13870 fold_convert (integer_type_node
, tmp2_var
));
13872 if (SPARC_LOW_FE_EXCEPT_VALUES
)
13874 tree shifted_tmp2_var
13875 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
13876 build_int_cst (unsigned_type_node
, 5));
13878 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
13879 update_call
= compound_expr (update_shift
, update_call
);
13883 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
13886 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. Borrowed from the PA port.
13888 SImode loads to floating-point registers are not zero-extended.
13889 The definition for LOAD_EXTEND_OP specifies that integer loads
13890 narrower than BITS_PER_WORD will be zero-extended. As a result,
13891 we inhibit changes from SImode unless they are to a mode that is
13894 Likewise for SFmode, since word-mode paradoxical subregs are
13895 problematic on big-endian architectures. */
13898 sparc_can_change_mode_class (machine_mode from
, machine_mode to
,
13899 reg_class_t rclass
)
13902 && GET_MODE_SIZE (from
) == 4
13903 && GET_MODE_SIZE (to
) != 4)
13904 return !reg_classes_intersect_p (rclass
, FP_REGS
);
13908 /* Implement TARGET_CONSTANT_ALIGNMENT. */
13910 static HOST_WIDE_INT
13911 sparc_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
13913 if (TREE_CODE (exp
) == STRING_CST
)
13914 return MAX (align
, FASTEST_ALIGNMENT
);
13918 /* Implement TARGET_ZERO_CALL_USED_REGS.
13920 Generate a sequence of instructions that zero registers specified by
13921 NEED_ZEROED_HARDREGS. Return the ZEROED_HARDREGS that are actually
13924 static HARD_REG_SET
13925 sparc_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs
)
13927 for (unsigned int regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
13928 if (TEST_HARD_REG_BIT (need_zeroed_hardregs
, regno
))
13930 /* Do not touch the CC registers or the FP registers if no VIS. */
13931 if (regno
>= SPARC_FCC_REG
13932 || (regno
>= SPARC_FIRST_FP_REG
&& !TARGET_VIS
))
13933 CLEAR_HARD_REG_BIT (need_zeroed_hardregs
, regno
);
13935 /* Do not access the odd upper FP registers individually. */
13936 else if (regno
>= SPARC_FIRST_V9_FP_REG
&& (regno
& 1))
13939 /* Use the most natural mode for the registers, which is not given by
13940 regno_reg_rtx/reg_raw_mode for the FP registers on the SPARC. */
13946 if (regno
< SPARC_FIRST_FP_REG
)
13948 reg
= regno_reg_rtx
[regno
];
13949 mode
= GET_MODE (reg
);
13953 mode
= regno
< SPARC_FIRST_V9_FP_REG
? SFmode
: DFmode
;
13954 reg
= gen_raw_REG (mode
, regno
);
13957 emit_move_insn (reg
, CONST0_RTX (mode
));
13961 return need_zeroed_hardregs
;
13964 #include "gt-sparc.h"