| blob | 053879500b73eef103f819e04961007f18718d69 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 We check (with modified_between_p) to avoid combining in such a way
37 as to move a computation to a place where its value would be different.
39 Combination is done by mathematically substituting the previous
40 insn(s) values for the regs they set into the expressions in
41 the later insns that refer to these regs. If the result is a valid insn
42 for our target machine, according to the machine description,
43 we install it, delete the earlier insns, and update the data flow
44 information (LOG_LINKS and REG_NOTES) for what we did.
46 There are a few exceptions where the dataflow information isn't
47 completely updated (however this is only a local issue since it is
48 regenerated before the next pass that uses it):
50 - reg_live_length is not updated
51 - reg_n_refs is not adjusted in the rare case when a register is
52 no longer required in a computation
53 - there are extremely rare cases (see distribute_notes) when a
54 REG_DEAD note is lost
55 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 removed because there is no way to know which register it was
57 linking
59 To simplify substitution, we combine only when the earlier insn(s)
60 consist of only a single assignment. To simplify updating afterward,
61 we never combine when a subroutine call appears in the middle. */
83 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
95 /* Number of attempts to combine instructions in this function. */
99 /* Number of attempts that got as far as substitution in this function. */
103 /* Number of instructions combined with added SETs in this function. */
107 /* Number of instructions combined in this function. */
111 /* Totals over entire compilation. */
115 /* combine_instructions may try to replace the right hand side of the
116 second instruction with the value of an associated REG_EQUAL note
117 before throwing it at try_combine. That is problematic when there
118 is a REG_DEAD note for a register used in the old right hand side
119 and can cause distribute_notes to do wrong things. This is the
120 second instruction if it has been so modified, null otherwise. */
124 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
128 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
131 \f
133 /* Record last point of death of (hard or pseudo) register n. */
136 /* Record last point of modification of (hard or pseudo) register n. */
139 /* The next group of fields allows the recording of the last value assigned
140 to (hard or pseudo) register n. We use this information to see if an
141 operation being processed is redundant given a prior operation performed
142 on the register. For example, an `and' with a constant is redundant if
143 all the zero bits are already known to be turned off.
145 We use an approach similar to that used by cse, but change it in the
146 following ways:
148 (1) We do not want to reinitialize at each label.
149 (2) It is useful, but not critical, to know the actual value assigned
150 to a register. Often just its form is helpful.
152 Therefore, we maintain the following fields:
154 last_set_value the last value assigned
155 last_set_label records the value of label_tick when the
156 register was assigned
157 last_set_table_tick records the value of label_tick when a
158 value using the register is assigned
159 last_set_invalid set to nonzero when it is not valid
160 to use the value of this register in some
161 register's value
163 To understand the usage of these tables, it is important to understand
164 the distinction between the value in last_set_value being valid and
165 the register being validly contained in some other expression in the
166 table.
168 (The next two parameters are out of date).
170 reg_stat[i].last_set_value is valid if it is nonzero, and either
171 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
173 Register I may validly appear in any expression returned for the value
174 of another register if reg_n_sets[i] is 1. It may also appear in the
175 value for register J if reg_stat[j].last_set_invalid is zero, or
176 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
178 If an expression is found in the table containing a register which may
179 not validly appear in an expression, the register is replaced by
180 something that won't match, (clobber (const_int 0)). */
182 /* Record last value assigned to (hard or pseudo) register n. */
184 rtx last_set_value;
186 /* Record the value of label_tick when an expression involving register n
187 is placed in last_set_value. */
191 /* Record the value of label_tick when the value for register n is placed in
192 last_set_value. */
196 /* These fields are maintained in parallel with last_set_value and are
197 used to store the mode in which the register was last set, the bits
198 that were known to be zero when it was last set, and the number of
199 sign bits copies it was known to have when it was last set. */
205 /* Set nonzero if references to register n in expressions should not be
206 used. last_set_invalid is set nonzero when this register is being
207 assigned to and last_set_table_tick == label_tick. */
211 /* Some registers that are set more than once and used in more than one
212 basic block are nevertheless always set in similar ways. For example,
213 a QImode register may be loaded from memory in two places on a machine
214 where byte loads zero extend.
216 We record in the following fields if a register has some leading bits
217 that are always equal to the sign bit, and what we know about the
218 nonzero bits of a register, specifically which bits are known to be
219 zero.
221 If an entry is zero, it means that we don't know anything special. */
227 /* Record the value of the label_tick when the last truncation
228 happened. The field truncated_to_mode is only valid if
229 truncation_label == label_tick. */
233 /* Record the last truncation seen for this register. If truncation
234 is not a nop to this mode we might be able to save an explicit
235 truncation if we know that value already contains a truncated
236 value. */
239 };
244 /* One plus the highest pseudo for which we track REG_N_SETS.
245 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
246 but during combine_split_insns new pseudos can be created. As we don't have
247 updated DF information in that case, it is hard to initialize the array
248 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
249 so instead of growing the arrays, just assume all newly created pseudos
250 during combine might be set multiple times. */
254 /* Record the luid of the last insn that invalidated memory
255 (anything that writes memory, and subroutine calls, but not pushes). */
259 /* Record the luid of the last CALL_INSN
260 so we can tell whether a potential combination crosses any calls. */
264 /* When `subst' is called, this is the insn that is being modified
265 (by combining in a previous insn). The PATTERN of this insn
266 is still the old pattern partially modified and it should not be
267 looked at, but this may be used to examine the successors of the insn
268 to judge whether a simplification is valid. */
272 /* This is the lowest LUID that `subst' is currently dealing with.
273 get_last_value will not return a value if the register was set at or
274 after this LUID. If not for this mechanism, we could get confused if
275 I2 or I1 in try_combine were an insn that used the old value of a register
276 to obtain a new value. In that case, we might erroneously get the
277 new value of the register when we wanted the old one. */
281 /* This contains any hard registers that are used in newpat; reg_dead_at_p
282 must consider all these registers to be always live. */
286 /* This is an insn to which a LOG_LINKS entry has been added. If this
287 insn is the earlier than I2 or I3, combine should rescan starting at
288 that location. */
292 /* And similarly, for notes. */
296 /* Basic block in which we are performing combines. */
300 \f
301 /* Length of the currently allocated uid_insn_cost array. */
305 /* The following array records the insn_cost for every insn
306 in the instruction stream. */
310 /* The following array records the LOG_LINKS for every insn in the
311 instruction stream as struct insn_link pointers. */
317 };
323 {
327 }
329 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
330 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
332 #define FOR_EACH_LOG_LINK(L, INSN) \
333 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
335 /* Links for LOG_LINKS are allocated from this obstack. */
339 /* Allocate a link. */
343 {
351 }
353 /* Incremented for each basic block. */
357 /* Reset to label_tick for each extended basic block in scanning order. */
361 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
362 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
366 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
367 be safely used. It is zero while computing them and after combine has
368 completed. This former test prevents propagating values based on
369 previously set values, which can be incorrect if a variable is modified
370 in a loop. */
374 \f
375 /* Record one modification to rtl structure
376 to be undone by storing old_contents into *where. */
380 struct undo
381 {
386 };
388 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
389 num_undo says how many are currently recorded.
391 other_insn is nonzero if we have modified some other insn in the process
392 of working on subst_insn. It must be verified too. */
394 struct undobuf
395 {
399 };
403 /* Number of times the pseudo being substituted for
404 was found and replaced. */
409 scalar_int_mode,
412 scalar_int_mode,
484 \f
486 /* It is not safe to use ordinary gen_lowpart in combine.
487 See comments in gen_lowpart_for_combine. */
488 #undef RTL_HOOKS_GEN_LOWPART
489 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
491 /* Our implementation of gen_lowpart never emits a new pseudo. */
492 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
493 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
495 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
496 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
498 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
499 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
501 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
502 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
506 \f
507 /* Convenience wrapper for the canonicalize_comparison target hook.
508 Target hooks cannot use enum rtx_code. */
512 {
516 }
518 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
519 PATTERN cannot be split. Otherwise, it returns an insn sequence.
520 This is a wrapper around split_insns which ensures that the
521 reg_stat vector is made larger if the splitter creates a new
522 register. */
526 {
535 }
537 /* This is used by find_single_use to locate an rtx in LOC that
538 contains exactly one use of DEST, which is typically a REG.
539 It returns a pointer to the innermost rtx expression
540 containing DEST. Appearances of DEST that are being used to
541 totally replace it are not counted. */
545 {
554 {
558 CASE_CONST_ANY:
563 /* If the destination is anything other than PC, a REG or a SUBREG
564 of a REG that occupies all of the REG, the insn uses DEST if
565 it is mentioned in the destination or the source. Otherwise, we
566 need just check the source. */
582 }
584 /* If it wasn't one of the common cases above, check each expression and
585 vector of this code. Look for a unique usage of DEST. */
589 {
591 {
596 else
602 /* Duplicate usage. */
604 }
606 {
610 {
616 else
623 }
624 }
625 }
628 }
631 /* See if DEST, produced in INSN, is used only a single time in the
632 sequel. If so, return a pointer to the innermost rtx expression in which
633 it is used.
635 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
637 Otherwise, we find the single use by finding an insn that has a
638 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
639 only referenced once in that insn, we know that it must be the first
640 and last insn referencing DEST. */
644 {
645 basic_block bb;
658 {
664 {
669 }
670 }
673 }
674 \f
675 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
676 insn. The substitution can be undone by undo_all. If INTO is already
677 set to NEWVAL, do not record this change. Because computing NEWVAL might
678 also call SUBST, we have to compute it before we put anything into
679 the undo table. */
681 static void
683 {
690 /* We'd like to catch as many invalid transformations here as
691 possible. Unfortunately, there are way too many mode changes
692 that are perfectly valid, so we'd waste too much effort for
693 little gain doing the checks here. Focus on catching invalid
694 transformations involving integer constants. */
697 {
698 /* Sanity check that we're replacing oldval with a CONST_INT
699 that is a valid sign-extension for the original mode. */
703 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
704 CONST_INT is not valid, because after the replacement, the
705 original mode would be gone. Unfortunately, we can't tell
706 when do_SUBST is called to replace the operand thereof, so we
707 perform this test on oldval instead, checking whether an
708 invalid replacement took place before we got here. */
713 }
717 else
726 }
728 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
730 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
731 for the value of a HOST_WIDE_INT value (including CONST_INT) is
732 not safe. */
734 static void
736 {
745 else
754 }
756 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
758 /* Similar to SUBST, but just substitute the mode. This is used when
759 changing the mode of a pseudo-register, so that any other
760 references to the entry in the regno_reg_rtx array will change as
761 well. */
763 static void
765 {
775 else
784 }
786 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
788 static void
790 {
799 else
808 }
810 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
811 \f
812 /* Subroutine of try_combine. Determine whether the replacement patterns
813 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
814 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
815 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
816 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
817 of all the instructions can be estimated and the replacements are more
818 expensive than the original sequence. */
820 static bool
823 {
828 /* Lookup the original insn_costs. */
833 {
836 {
840 }
841 else
842 {
846 }
847 }
848 else
849 {
852 }
854 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
855 correct that. */
860 /* Calculate the replacement insn_costs. */
869 {
879 }
880 else
881 {
884 }
887 {
896 optimize_this_for_speed_p);
900 {
903 }
904 else
906 }
908 /* Disallow this combination if both new_cost and old_cost are greater than
909 zero, and new_cost is greater than old cost. */
913 {
932 else
934 }
939 /* Update the uid_insn_cost array with the replacement costs. */
943 {
947 }
950 }
953 /* Delete any insns that copy a register to itself.
954 Return true if the CFG was changed. */
956 static bool
958 {
960 basic_block bb;
965 {
967 {
970 {
975 }
976 }
977 }
980 }
982 \f
983 /* Return false if we do not want to (or cannot) combine DEF. */
984 static bool
986 {
987 /* Do not consider if it is pre/post modification in MEM. */
993 /* Do not combine frame pointer adjustments. */
996 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 }
1006 /* Return false if we do not want to (or cannot) combine USE. */
1007 static bool
1009 {
1010 /* Do not consider the usage of the stack pointer by function call. */
1015 }
1017 /* Fill in log links field for all insns. */
1019 static void
1021 {
1022 basic_block bb;
1029 /* Pass through each block from the end, recording the uses of each
1030 register and establishing log links when def is encountered.
1031 Note that we do not clear next_use array in order to save time,
1032 so we have to test whether the use is in the same basic block as def.
1034 There are a few cases below when we do not consider the definition or
1035 usage -- these are taken from original flow.c did. Don't ask me why it is
1036 done this way; I don't know and if it works, I don't want to know. */
1039 {
1041 {
1045 /* Log links are created only once. */
1049 {
1065 /* flow.c claimed:
1067 We don't build a LOG_LINK for hard registers contained
1068 in ASM_OPERANDs. If these registers get replaced,
1069 we might wind up changing the semantics of the insn,
1070 even if reload can make what appear to be valid
1071 assignments later. */
1076 /* Don't add duplicate links between instructions. */
1085 }
1090 }
1091 }
1094 }
1096 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1097 true if we found a LOG_LINK that proves that A feeds B. This only works
1098 if there are no instructions between A and B which could have a link
1099 depending on A, since in that case we would not record a link for B. */
1101 static bool
1103 {
1109 }
1110 \f
1111 /* Main entry point for combiner. F is the first insn of the function.
1112 NREGS is the first unused pseudo-reg number.
1114 Return nonzero if the CFG was changed (e.g. if the combiner has
1115 turned an indirect jump instruction into a direct jump). */
1116 static int
1118 {
1122 basic_block last_bb;
1142 /* Allocate array for insn info. */
1150 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1151 problems when, for example, we have j <<= 1 in a loop. */
1156 /* Scan all SETs and see if we can deduce anything about what
1157 bits are known to be zero for some registers and how many copies
1158 of the sign bit are known to exist for those registers.
1160 Also set any known values so that we can use it while searching
1161 for what bits are known to be set. */
1164 /* Allow the entry block and the first block to fall into the same EBB.
1165 Conceptually the incoming promotions are assigned to the entry block. */
1170 {
1175 label_tick++;
1183 {
1184 rtx links;
1196 insn);
1198 /* Record the current insn_cost of this instruction. */
1201 {
1204 }
1205 }
1206 }
1210 /* Now scan all the insns in forward order. */
1218 {
1221 /* Ignore instruction combination in basic blocks that are going to
1222 be removed as unreachable anyway. See PR82386. */
1230 label_tick++;
1240 {
1254 /* See if we know about function return values before this
1255 insn based upon SUBREG flags. */
1258 /* See if we can find hardregs and subreg of pseudos in
1259 narrower modes. This could help turning TRUNCATEs
1260 into SUBREGs. */
1263 /* Try this insn with each insn it links back to. */
1269 {
1272 }
1274 /* Try each sequence of three linked insns ending with this one. */
1278 {
1281 /* If the linked insn has been replaced by a note, then there
1282 is no point in pursuing this chain any further. */
1290 {
1293 }
1294 }
1296 /* Try combining an insn with two different insns whose results it
1297 uses. */
1307 {
1310 }
1312 /* Try four-instruction combinations. */
1315 {
1319 /* If the linked insn has been replaced by a note, then there
1320 is no point in pursuing this chain any further. */
1325 {
1329 /* I0 -> I1 -> I2 -> I3. */
1335 {
1338 }
1339 /* I0, I1 -> I2, I2 -> I3. */
1346 {
1349 }
1350 }
1353 {
1357 /* I0 -> I2; I1, I2 -> I3. */
1363 {
1366 }
1367 /* I0 -> I1; I1, I2 -> I3. */
1373 {
1376 }
1377 }
1378 }
1380 /* Try this insn with each REG_EQUAL note it links back to. */
1382 {
1389 /* Avoid using a register that may already been marked
1390 dead by an earlier instruction. */
1398 {
1399 /* Temporarily replace the set's source with the
1400 contents of the REG_EQUAL note. The insn will
1401 be deleted or recognized by try_combine. */
1412 last_combined_insn);
1415 {
1418 }
1421 }
1422 }
1427 retry:
1428 ;
1429 }
1430 }
1437 /* Clean up. */
1443 {
1446 {
1449 }
1451 }
1461 /* Make recognizer allow volatile MEMs again. */
1465 }
1467 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1469 static void
1471 {
1477 }
1478 \f
1479 /* Set up any promoted values for incoming argument registers. */
1481 static void
1483 {
1484 tree arg;
1489 {
1494 /* Only continue if the incoming argument is in a register. */
1498 /* Determine, if possible, whether all call sites of the current
1499 function lie within the current compilation unit. (This does
1500 take into account the exporting of a function via taking its
1501 address, and so forth.) */
1502 strictly_local
1505 /* The mode and signedness of the argument before any promotions happen
1506 (equal to the mode of the pseudo holding it at that stage). */
1510 /* The mode and signedness of the argument after any source language and
1511 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1515 /* The mode and signedness of the argument as it is actually passed,
1516 see assign_parm_setup_reg in function.cc. */
1520 /* The mode of the register in which the argument is being passed. */
1523 /* Eliminate sign extensions in the callee when:
1524 (a) A mode promotion has occurred; */
1527 /* (b) The mode of the register is the same as the mode of
1528 the argument as it is passed; */
1531 /* (c) There's no language level extension; */
1533 ;
1534 /* (c.1) All callers are from the current compilation unit. If that's
1535 the case we don't have to rely on an ABI, we only have to know
1536 what we're generating right now, and we know that we will do the
1537 mode1 to mode2 promotion with the given sign. */
1540 /* (c.2) The combination of the two promotions is useful. This is
1541 true when the signs match, or if the first promotion is unsigned.
1542 In the later case, (sign_extend (zero_extend x)) is the same as
1543 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1549 /* Record that the value was promoted from mode1 to mode3,
1550 so that any sign extension at the head of the current
1551 function may be eliminated. */
1555 }
1556 }
1558 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1559 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1560 because some machines (maybe most) will actually do the sign-extension and
1561 this is the conservative approach.
1563 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1564 kludge. */
1566 static rtx
1568 {
1569 scalar_int_mode int_mode;
1578 }
1580 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1581 and SET. */
1583 static void
1585 rtx x)
1586 {
1596 {
1600 }
1602 /* Don't call nonzero_bits if it cannot change anything. */
1604 {
1613 }
1615 /* Don't call num_sign_bit_copies if it cannot change anything. */
1617 {
1620 {
1624 }
1627 }
1628 }
1630 /* Called via note_stores. If X is a pseudo that is narrower than
1631 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1633 If we are setting only a portion of X and we can't figure out what
1634 portion, assume all bits will be used since we don't know what will
1635 be happening.
1637 Similarly, set how many bits of X are known to be copies of the sign bit
1638 at all locations in the function. This is the smallest number implied
1639 by any set of X. */
1641 static void
1643 {
1645 scalar_int_mode mode;
1649 /* If this register is undefined at the start of the file, we can't
1650 say what its contents were. */
1651 && ! REGNO_REG_SET_P
1655 {
1659 {
1663 }
1665 /* If this register is being initialized using itself, and the
1666 register is uninitialized in this basic block, and there are
1667 no LOG_LINKS which set the register, then part of the
1668 register is uninitialized. In that case we can't assume
1669 anything about the number of nonzero bits.
1671 ??? We could do better if we checked this in
1672 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1673 could avoid making assumptions about the insn which initially
1674 sets the register, while still using the information in other
1675 insns. We would have to be careful to check every insn
1676 involved in the combination. */
1682 {
1689 {
1693 }
1694 }
1696 /* If this is a complex assignment, see if we can convert it into a
1697 simple assignment. */
1700 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1701 set what we know about X. */
1707 else
1708 {
1711 }
1712 }
1713 }
1714 \f
1715 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1716 optionally insns that were previously combined into I3 or that will be
1717 combined into the merger of INSN and I3. The order is PRED, PRED2,
1718 INSN, SUCC, SUCC2, I3.
1720 Return 0 if the combination is not allowed for any reason.
1722 If the combination is allowed, *PDEST will be set to the single
1723 destination of INSN and *PSRC to the single source, and this function
1724 will return 1. */
1726 static int
1730 {
1735 rtx link;
1740 {
1742 {
1747 }
1752 }
1756 /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1757 or a PARALLEL consisting of such a SET and CLOBBERs.
1759 If INSN has CLOBBER parallel parts, ignore them for our processing.
1760 By definition, these happen during the execution of the insn. When it
1761 is merged with another insn, all bets are off. If they are, in fact,
1762 needed and aren't also supplied in I3, they may be added by
1763 recog_for_combine. Otherwise, it won't match.
1765 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1766 note.
1768 Get the source and destination of INSN. If more than one, can't
1769 combine. */
1775 {
1777 {
1781 {
1782 /* This is important to combine floating point insns
1783 for the SH4 port. */
1785 /* Combining an isolated USE doesn't make sense.
1786 We depend here on combinable_i3pat to reject them. */
1787 /* The code below this loop only verifies that the inputs of
1788 the SET in INSN do not change. We call reg_set_between_p
1789 to verify that the REG in the USE does not change between
1790 I3 and INSN.
1791 If the USE in INSN was for a pseudo register, the matching
1792 insn pattern will likely match any register; combining this
1793 with any other USE would only be safe if we knew that the
1794 used registers have identical values, or if there was
1795 something to tell them apart, e.g. different modes. For
1796 now, we forgo such complicated tests and simply disallow
1797 combining of USES of pseudo registers with any other USE. */
1800 {
1805 do
1806 {
1816 }
1818 }
1821 /* We can ignore CLOBBERs. */
1826 /* Ignore SETs whose result isn't used but not those that
1827 have side-effects. */
1833 /* If we have already found a SET, this is a second one and
1834 so we cannot combine with this insn. */
1842 /* Anything else means we can't combine. */
1844 }
1845 }
1848 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1849 so don't do anything with it. */
1852 }
1853 else
1859 /* The simplification in expand_field_assignment may call back to
1860 get_last_value, so set safe guard here. */
1866 /* Do not eliminate user-specified register if it is in an
1867 asm input because we may break the register asm usage defined
1868 in GCC manual if allow to do so.
1869 Be aware that this may cover more cases than we expect but this
1870 should be harmless. */
1875 /* Don't eliminate a store in the stack pointer. */
1877 /* Don't combine with an insn that sets a register to itself if it has
1878 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1880 /* Can't merge an ASM_OPERANDS. */
1882 /* Can't merge a function call. */
1884 /* Don't eliminate a function call argument. */
1890 /* Don't substitute into an incremented register. */
1894 /* Don't substitute into a non-local goto, this confuses CFG. */
1896 /* Make sure that DEST is not used after INSN but before SUCC, or
1897 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1898 || (!all_adjacent
1899 && ((succ2
1904 || (succ
1905 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1906 that case SUCC is not in the insn stream, so use SUCC2
1907 instead for this test. */
1909 succ2
1912 /* Make sure that the value that is to be substituted for the register
1913 does not use any registers whose values alter in between. However,
1914 If the insns are adjacent, a use can't cross a set even though we
1915 think it might (this can happen for a sequence of insns each setting
1916 the same destination; last_set of that register might point to
1917 a NOTE). If INSN has a REG_EQUIV note, the register is always
1918 equivalent to the memory so the substitution is valid even if there
1919 are intervening stores. Also, don't move a volatile asm or
1920 UNSPEC_VOLATILE across any other insns. */
1921 || (! all_adjacent
1927 /* Don't combine across a CALL_INSN, because that would possibly
1928 change whether the life span of some REGs crosses calls or not,
1929 and it is a pain to update that information.
1930 Exception: if source is a constant, moving it later can't hurt.
1931 Accept that as a special case. */
1935 /* DEST must be a REG. */
1937 {
1938 /* If register alignment is being enforced for multi-word items in all
1939 cases except for parameters, it is possible to have a register copy
1940 insn referencing a hard register that is not allowed to contain the
1941 mode being copied and which would not be valid as an operand of most
1942 insns. Eliminate this problem by not combining with such an insn.
1944 Also, on some machines we don't want to extend the life of a hard
1945 register. */
1950 /* Don't extend the life of a hard register unless it is
1951 user variable (if we have few registers) or it can't
1952 fit into the desired register (meaning something special
1953 is going on).
1954 Also avoid substituting a return register into I3, because
1955 reload can't handle a conflict with constraints of other
1956 inputs. */
1961 }
1962 else
1969 {
1972 /* If the clobber represents an earlyclobber operand, we must not
1973 substitute an expression containing the clobbered register.
1974 As we do not analyze the constraint strings here, we have to
1975 make the conservative assumption. However, if the register is
1976 a fixed hard reg, the clobber cannot represent any operand;
1977 we leave it up to the machine description to either accept or
1978 reject use-and-clobber patterns. */
1984 }
1986 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1987 or not), reject, unless nothing volatile comes between it and I3 */
1990 {
1991 /* Make sure neither succ nor succ2 contains a volatile reference. */
1996 /* We'll check insns between INSN and I3 below. */
1997 }
1999 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2000 to be an explicit register variable, and was chosen for a reason. */
2006 /* If INSN contains volatile references (specifically volatile MEMs),
2007 we cannot combine across any other volatile references.
2008 Even if INSN doesn't contain volatile references, any intervening
2009 volatile insn might affect machine state. */
2012 ? volatile_refs_p
2019 /* If INSN contains an autoincrement or autodecrement, make sure that
2020 register is not used between there and I3, and not already used in
2021 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2022 Also insist that I3 not be a jump if using LRA; if it were one
2023 and the incremented register were spilled, we would lose.
2024 Reload handles this correctly. */
2042 /* If we get here, we have passed all the tests and the combination is
2043 to be allowed. */
2049 }
2050 \f
2051 /* LOC is the location within I3 that contains its pattern or the component
2052 of a PARALLEL of the pattern. We validate that it is valid for combining.
2054 One problem is if I3 modifies its output, as opposed to replacing it
2055 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2056 doing so would produce an insn that is not equivalent to the original insns.
2058 Consider:
2060 (set (reg:DI 101) (reg:DI 100))
2061 (set (subreg:SI (reg:DI 101) 0) <foo>)
2063 This is NOT equivalent to:
2065 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2066 (set (reg:DI 101) (reg:DI 100))])
2068 Not only does this modify 100 (in which case it might still be valid
2069 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2071 We can also run into a problem if I2 sets a register that I1
2072 uses and I1 gets directly substituted into I3 (not via I2). In that
2073 case, we would be getting the wrong value of I2DEST into I3, so we
2074 must reject the combination. This case occurs when I2 and I1 both
2075 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2076 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2077 of a SET must prevent combination from occurring. The same situation
2078 can occur for I0, in which case I0_NOT_IN_SRC is set.
2080 Before doing the above check, we first try to expand a field assignment
2081 into a set of logical operations.
2083 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2084 we place a register that is both set and used within I3. If more than one
2085 such register is detected, we fail.
2087 Return 1 if the combination is valid, zero otherwise. */
2089 static int
2092 {
2096 {
2101 rtx subdest;
2108 /* Check for the case where I3 modifies its output, as discussed
2109 above. We don't want to prevent pseudos from being combined
2110 into the address of a MEM, so only prevent the combination if
2111 i1 or i2 set the same MEM. */
2121 /* This is the same test done in can_combine_p except we can't test
2122 all_adjacent; we don't have to, since this instruction will stay
2123 in place, thus we are not considering increasing the lifetime of
2124 INNER_DEST.
2126 Also, if this insn sets a function argument, combining it with
2127 something that might need a spill could clobber a previous
2128 function argument; the all_adjacent test in can_combine_p also
2129 checks this; here, we do a more specific test for this case. */
2139 /* If DEST is used in I3, it is being killed in this insn, so
2140 record that for later. We have to consider paradoxical
2141 subregs here, since they kill the whole register, but we
2142 ignore partial subregs, STRICT_LOW_PART, etc.
2143 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2144 STACK_POINTER_REGNUM, since these are always considered to be
2145 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2153 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2159 {
2164 }
2165 }
2168 {
2175 }
2178 }
2179 \f
2180 /* Return 1 if X is an arithmetic expression that contains a multiplication
2181 and division. We don't count multiplications by powers of two here. */
2183 static int
2185 {
2187 {
2203 }
2204 }
2205 \f
2206 /* Determine whether INSN can be used in a combination. Return nonzero if
2207 not. This is used in try_combine to detect early some cases where we
2208 can't perform combinations. */
2210 static int
2212 {
2213 rtx set;
2216 /* If this isn't really an insn, we can't do anything.
2217 This can occur when flow deletes an insn that it has merged into an
2218 auto-increment address. */
2222 /* Never combine loads and stores involving hard regs that are likely
2223 to be spilled. The register allocator can usually handle such
2224 reg-reg moves by tying. If we allow the combiner to make
2225 substitutions of likely-spilled regs, reload might die.
2226 As an exception, we allow combinations involving fixed regs; these are
2227 not available to the register allocator so there's no risk involved. */
2241 #ifdef LEAF_REGISTERS
2243 #else
2244 )
2245 #endif
2252 }
2254 struct likely_spilled_retval_info
2255 {
2258 };
2260 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2261 hard registers that are known to be written to / clobbered in full. */
2262 static void
2264 {
2281 else
2284 }
2286 /* Return nonzero iff part of the return value is live during INSN, and
2287 it is likely spilled. This can happen when more than one insn is needed
2288 to copy the return value, e.g. when we consider to combine into the
2289 second copy insn for a complex value. */
2291 static int
2293 {
2295 rtx reg;
2298 /* We assume here that no machine mode needs more than
2299 32 hard registers when the value overlaps with a register
2300 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2315 /* Disregard parts of the return value that are set later. */
2324 /* Check if any of the (probably) live return value registers is
2325 likely spilled. */
2326 nregs --;
2327 do
2328 {
2334 }
2336 /* Adjust INSN after we made a change to its destination.
2338 Changing the destination can invalidate notes that say something about
2339 the results of the insn and a LOG_LINK pointing to the insn. */
2341 static void
2343 {
2344 /* For notes, be conservative and simply remove them. */
2347 /* The new insn will have a destination that was previously the destination
2348 of an insn just above it. Call distribute_links to make a LOG_LINK from
2349 the next use of that destination. */
2365 }
2367 /* Return TRUE if combine can reuse reg X in mode MODE.
2368 ADDED_SETS is nonzero if the original set is still required. */
2369 static bool
2371 {
2377 /* Don't change between modes with different underlying register sizes,
2378 since this could lead to invalid subregs. */
2384 /* Allow hard registers if the new mode is legal, and occupies no more
2385 registers than the old mode. */
2390 /* Or a pseudo that is only used once. */
2393 && !added_sets
2395 }
2398 /* Check whether X, the destination of a set, refers to part of
2399 the register specified by REG. */
2401 static bool
2403 {
2404 /* Check that reg is an integer mode register. */
2416 }
2418 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2419 by an arbitrary number of CLOBBERs. */
2420 static bool
2422 {
2437 {
2444 }
2446 }
2448 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2449 CLOBBERs), can be split into individual SETs in that order, without
2450 changing semantics. */
2451 static bool
2453 {
2461 {
2470 }
2473 }
2475 /* Return whether X is just a single_set, with the source
2476 a general_operand. */
2477 static bool
2479 {
2485 }
2487 /* Callback function to count autoincs. */
2489 static int
2491 {
2495 }
2497 /* Try to combine the insns I0, I1 and I2 into I3.
2498 Here I0, I1 and I2 appear earlier than I3.
2499 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2500 I3.
2502 If we are combining more than two insns and the resulting insn is not
2503 recognized, try splitting it into two insns. If that happens, I2 and I3
2504 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2505 Otherwise, I0, I1 and I2 are pseudo-deleted.
2507 Return 0 if the combination does not work. Then nothing is changed.
2508 If we did the combination, return the insn at which combine should
2509 resume scanning.
2511 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2512 new direct jump instruction.
2514 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2515 been I3 passed to an earlier try_combine within the same basic
2516 block. */
2521 {
2522 /* New patterns for I3 and I2, respectively. */
2526 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2527 dead. */
2529 /* Total number of SETs to put into I3. */
2531 /* Nonzero if I2's or I1's body now appears in I3. */
2533 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2535 /* Contains I3 if the destination of I3 is used in its source, which means
2536 that the old life of I3 is being killed. If that usage is placed into
2537 I2 and not in I3, a REG_DEAD note must be made. */
2539 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2541 /* Copy of SET_SRC of I1 and I0, if needed. */
2543 /* Set if I2DEST was reused as a scratch register. */
2545 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2547 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2552 /* Notes that must be added to REG_NOTES in I3 and I2. */
2554 /* Notes that we substituted I3 into I2 instead of the normal case. */
2556 /* Notes that I1, I2 or I3 is a MULT operation. */
2566 rtx temp_expr;
2569 rtx new_other_notes;
2574 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2575 never be). */
2579 /* Only try four-insn combinations when there's high likelihood of
2580 success. Look for simple insns, such as loads of constants or
2581 binary operations involving a constant. */
2583 {
2593 {
2596 rtx src;
2601 {
2604 }
2606 ngood++;
2609 nshift++;
2610 }
2612 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2613 are likely manipulating its value. Ideally we'll be able to combine
2614 all four insns into a bitfield insertion of some kind.
2616 Note the source in I0 might be inside a sign/zero extension and the
2617 memory modes in I0 and I3 might be different. So extract the address
2618 from the destination of I3 and search for it in the source of I0.
2620 In the event that there's a match but the source/dest do not actually
2621 refer to the same memory, the worst that happens is we try some
2622 combinations that we wouldn't have otherwise. */
2624 /* Ensure the source of SET0 is a MEM, possibly buried inside
2625 an extension. */
2631 /* Ensure the destination of SET3 is a MEM. */
2633 /* Would it be better to extract the base address for the MEM
2634 in SET3 and look for that? I don't have cases where it matters
2635 but I could envision such cases. */
2641 }
2643 /* Exit early if one of the insns involved can't be used for
2644 combinations. */
2655 combine_attempts++;
2658 /* Reset the hard register usage information. */
2662 {
2669 else
2679 }
2681 /* If multiple insns feed into one of I2 or I3, they can be in any
2682 order. To simplify the code below, reorder them in sequence. */
2693 /* First check for one important special case that the code below will
2694 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2695 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2696 we may be able to replace that destination with the destination of I3.
2697 This occurs in the common code where we compute both a quotient and
2698 remainder into a structure, in which case we want to do the computation
2699 directly into the structure to avoid register-register copies.
2701 Note that this case handles both multiple sets in I2 and also cases
2702 where I2 has a number of CLOBBERs inside the PARALLEL.
2704 We make very conservative checks below and only try to handle the
2705 most common cases of this. For example, we only handle the case
2706 where I2 and I3 are adjacent to avoid making difficult register
2707 usage tests. */
2715 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2716 below would need to check what is inside (and reg_overlap_mentioned_p
2717 doesn't support those codes anyway). Don't allow those destinations;
2718 the resulting insn isn't likely to be recognized anyway. */
2724 {
2727 /* Make sure that the destination of I3,
2728 which we are going to substitute into one output of I2,
2729 is not used within another output of I2. We must avoid making this:
2730 (parallel [(set (mem (reg 69)) ...)
2731 (set (reg 69) ...)])
2732 which is not well-defined as to order of actions.
2733 (Besides, reload can't handle output reloads for this.)
2735 The problem can also happen if the dest of I3 is a memory ref,
2736 if another dest in I2 is an indirect memory ref.
2738 Neither can this PARALLEL be an asm. We do not allow combining
2739 that usually (see can_combine_p), so do not here either. */
2742 {
2751 }
2757 {
2758 combine_merges++;
2768 /* Replace the dest in I2 with our dest and make the resulting
2769 insn the new pattern for I3. Then skip to where we validate
2770 the pattern. Everything was set up above. */
2775 }
2776 }
2778 /* If I2 is setting a pseudo to a constant and I3 is setting some
2779 sub-part of it to another constant, merge them by making a new
2780 constant. */
2788 {
2795 {
2800 {
2806 }
2807 }
2808 else
2809 {
2813 {
2816 }
2817 }
2820 {
2821 /* If this is the low part, we're done. */
2823 ;
2824 /* Handle the case where inner is twice the size of outer. */
2828 /* Otherwise give up for now. */
2829 else
2831 }
2834 {
2842 combine_merges++;
2849 /* Replace the source in I2 with the new constant and make the
2850 resulting insn the new pattern for I3. Then skip to where we
2851 validate the pattern. Everything was set up above. */
2857 /* The dest of I3 has been replaced with the dest of I2. */
2860 }
2861 }
2863 /* If we have no I1 and I2 looks like:
2864 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2865 (set Y OP)])
2866 make up a dummy I1 that is
2867 (set Y OP)
2868 and change I2 to be
2869 (set (reg:CC X) (compare:CC Y (const_int 0)))
2871 (We can ignore any trailing CLOBBERs.)
2873 This undoes a previous combination and allows us to match a branch-and-
2874 decrement insn. */
2886 {
2887 /* We make I1 with the same INSN_UID as I2. This gives it
2888 the same DF_INSN_LUID for value tracking. Our fake I1 will
2889 never appear in the insn stream so giving it the same INSN_UID
2890 as I2 will not cause a problem. */
2903 }
2905 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2906 make those two SETs separate I1 and I2 insns, and make an I0 that is
2907 the original I1. */
2915 {
2916 /* If there is no I1, there is no I0 either. */
2919 /* We make I1 with the same INSN_UID as I2. This gives it
2920 the same DF_INSN_LUID for value tracking. Our fake I1 will
2921 never appear in the insn stream so giving it the same INSN_UID
2922 as I2 will not cause a problem. */
2930 }
2932 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2934 {
2939 }
2941 {
2946 }
2948 {
2953 }
2955 /* With non-call exceptions we can end up trying to combine multiple
2956 insns with possible EH side effects. Make sure we can combine
2957 that to a single insn which means there must be at most one insn
2958 in the combination with an EH side effect. */
2960 {
2965 {
2971 {
2977 }
2978 }
2979 }
2981 /* Record whether i2 and i3 are trivial moves. */
2985 /* Record whether I2DEST is used in I2SRC and similarly for the other
2986 cases. Knowing this will help in register status updating below. */
2997 /* For the earlier insns, determine which of the subsequent ones they
2998 feed. */
3005 /* Ensure that I3's pattern can be the destination of combines. */
3011 {
3014 }
3016 /* See if any of the insns is a MULT operation. Unless one is, we will
3017 reject a combination that is, since it must be slower. Be conservative
3018 here. */
3026 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3027 We used to do this EXCEPT in one case: I3 has a post-inc in an
3028 output operand. However, that exception can give rise to insns like
3029 mov r3,(r3)+
3030 which is a famous insn on the PDP-11 where the value of r3 used as the
3031 source was model-dependent. Avoid this sort of thing. */
3033 #if 0
3039 /* It's not the exception. */
3040 #endif
3042 {
3043 rtx link;
3049 {
3052 }
3053 }
3055 /* See if the SETs in I1 or I2 need to be kept around in the merged
3056 instruction: whenever the value set there is still needed past I3.
3057 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3059 For the SET in I1, we have two cases: if I1 and I2 independently feed
3060 into I3, the set in I1 needs to be kept around unless I1DEST dies
3061 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3062 in I1 needs to be kept around unless I1DEST dies or is set in either
3063 I2 or I3. The same considerations apply to I0. */
3070 else
3078 else
3081 /* We are about to copy insns for the case where they need to be kept
3082 around. Check that they can be copied in the merged instruction. */
3088 {
3091 }
3093 /* We cannot safely duplicate volatile references in any case. */
3098 {
3101 }
3103 /* Count how many auto_inc expressions there were in the original insns;
3104 we need to have the same number in the resulting patterns. */
3113 /* If the set in I2 needs to be kept around, we must make a copy of
3114 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3115 PATTERN (I2), we are only substituting for the original I1DEST, not into
3116 an already-substituted copy. This also prevents making self-referential
3117 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3118 I2DEST. */
3121 {
3124 else
3126 }
3129 {
3132 else
3134 }
3137 {
3140 else
3142 }
3144 combine_merges++;
3146 /* Substitute in the latest insn for the regs set by the earlier ones. */
3152 /* Many machines have insns that can both perform an
3153 arithmetic operation and set the condition code. These operations will
3154 be represented as a PARALLEL with the first element of the vector
3155 being a COMPARE of an arithmetic operation with the constant zero.
3156 The second element of the vector will set some pseudo to the result
3157 of the same arithmetic operation. If we simplify the COMPARE, we won't
3158 match such a pattern and so will generate an extra insn. Here we test
3159 for this case, where both the comparison and the operation result are
3160 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3161 I2SRC. Later we will make the PARALLEL that contains I2. */
3167 {
3168 rtx newpat_dest;
3174 scalar_int_mode mode;
3183 {
3189 }
3191 /* Do the rest only if op1 is const0_rtx, which may be the
3192 result of simplification. */
3194 {
3195 /* If a single use of the CC is found, prepare to modify it
3196 when SELECT_CC_MODE returns a new CC-class mode, or when
3197 the above simplify_compare_const() returned a new comparison
3198 operator. undobuf.other_insn is assigned the CC use insn
3199 when modifying it. */
3201 {
3202 #ifdef SELECT_CC_MODE
3203 machine_mode new_mode
3208 {
3213 else
3214 {
3217 }
3218 }
3219 #endif
3220 /* Cases for modifying the CC-using comparison. */
3222 /* ??? Do we need to verify the zero rtx? */
3224 {
3225 /* Replace cc_use_loc with entire new RTX. */
3230 }
3232 {
3233 /* Just replace the CC reg with a new mode. */
3236 }
3237 }
3239 /* Now we modify the current newpat:
3240 First, SET_DEST(newpat) is updated if the CC mode has been
3241 altered. For targets without SELECT_CC_MODE, this should be
3242 optimized away. */
3245 /* This is always done to propagate i2src into newpat. */
3248 /* Create new version of i2pat if needed; the below PARALLEL
3249 creation needs this to work correctly. */
3253 }
3254 }
3257 {
3258 /* It is possible that the source of I2 or I1 may be performing
3259 an unneeded operation, such as a ZERO_EXTEND of something
3260 that is known to have the high part zero. Handle that case
3261 by letting subst look at the inner insns.
3263 Another way to do this would be to have a function that tries
3264 to simplify a single insn instead of merging two or more
3265 insns. We don't do this because of the potential of infinite
3266 loops and because of the potential extra memory required.
3267 However, doing it the way we are is a bit of a kludge and
3268 doesn't catch all cases.
3270 But only do this if -fexpensive-optimizations since it slows
3271 things down and doesn't usually win.
3273 This is not done in the COMPARE case above because the
3274 unmodified I2PAT is used in the PARALLEL and so a pattern
3275 with a modified I2SRC would not match. */
3278 {
3279 /* Pass pc_rtx so no substitutions are done, just
3280 simplifications. */
3282 {
3285 }
3289 }
3294 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3295 copy of I2SRC each time we substitute it, in order to avoid creating
3296 self-referential RTL when we will be substituting I1SRC for I1DEST
3297 later. Likewise if I0 feeds into I2, either directly or indirectly
3298 through I1, and I0DEST is in I0SRC. */
3305 /* Record whether I2's body now appears within I3's body. */
3307 }
3309 /* If we already got a failure, don't try to do more. Otherwise, try to
3310 substitute I1 if we have it. */
3313 {
3314 /* Before we can do this substitution, we must redo the test done
3315 above (see detailed comments there) that ensures I1DEST isn't
3316 mentioned in any SETs in NEWPAT that are field assignments. */
3319 {
3322 }
3327 /* If the following substitution will modify I1SRC, make a copy of it
3328 for the case where it is substituted for I1DEST in I2PAT later. */
3332 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3333 copy of I1SRC each time we substitute it, in order to avoid creating
3334 self-referential RTL when we will be substituting I0SRC for I0DEST
3335 later. */
3340 /* Record whether I1's body now appears within I3's body. */
3342 }
3344 /* Likewise for I0 if we have it. */
3347 {
3350 {
3353 }
3355 /* If the following substitution will modify I0SRC, make a copy of it
3356 for the case where it is substituted for I0DEST in I1PAT later. */
3359 /* And a copy for I0DEST in I2PAT substitution. */
3368 }
3371 {
3376 {
3381 }
3382 }
3384 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3385 to count all the ways that I2SRC and I1SRC can be used. */
3396 /* Fail if we tried to make a new register. */
3398 /* Fail if we couldn't do something and have a CLOBBER. */
3400 /* Fail if this new pattern is a MULT and we didn't have one before
3401 at the outer level. */
3404 {
3407 }
3409 /* If the actions of the earlier insns must be kept
3410 in addition to substituting them into the latest one,
3411 we must make a new PARALLEL for the latest insn
3412 to hold additional the SETs. */
3415 {
3417 combine_extras++;
3420 {
3426 }
3427 else
3428 {
3433 }
3439 {
3445 }
3447 {
3456 }
3457 }
3459 validate_replacement:
3461 /* Note which hard regs this insn has as inputs. */
3464 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3465 consider splitting this pattern, we might need these clobbers. */
3468 {
3474 }
3476 /* We have recognized nothing yet. */
3479 /* See if this is a PARALLEL of two SETs where one SET's destination is
3480 a register that is unused and this isn't marked as an instruction that
3481 might trap in an EH region. In that case, we just need the other SET.
3482 We prefer this over the PARALLEL.
3484 This can occur when simplifying a divmod insn. We *must* test for this
3485 case here because the code below that splits two independent SETs doesn't
3486 handle this case correctly when it updates the register status.
3488 It's pointless doing this if we originally had two sets, one from
3489 i3, and one from i2. Combining then splitting the parallel results
3490 in the original i2 again plus an invalid insn (which we delete).
3491 The net effect is only to move instructions around, which makes
3492 debug info less accurate.
3494 If the remaining SET came from I2 its destination should not be used
3495 between I2 and I3. See PR82024. */
3500 {
3511 {
3514 }
3523 {
3528 {
3534 }
3535 }
3539 }
3541 /* Is the result of combination a valid instruction? */
3545 /* If we were combining three insns and the result is a simple SET
3546 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3547 insns. There are two ways to do this. It can be split using a
3548 machine-specific method (like when you have an addition of a large
3549 constant) or by combine in the function find_split_point. */
3553 {
3557 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3558 use I2DEST as a scratch register will help. In the latter case,
3559 convert I2DEST to the mode of the source of NEWPAT if we can. */
3563 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3564 inputs of NEWPAT. */
3566 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3567 possible to try that as a scratch reg. This would require adding
3568 more code to make it work though. */
3571 {
3574 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3575 (temporarily, until we are committed to this instruction
3576 combination) does not work: for example, any call to nonzero_bits
3577 on the register (from a splitter in the MD file, for example)
3578 will get the old information, which is invalid.
3580 Since nowadays we can create registers during combine just fine,
3581 we should just create a new one here, not reuse i2dest. */
3583 /* First try to split using the original register as a
3584 scratch register. */
3588 i2dest)));
3591 /* If that didn't work, try changing the mode of I2DEST if
3592 we can. */
3597 {
3599 rtx ni2dest;
3603 else
3604 {
3607 }
3609 parallel = (gen_rtx_PARALLEL
3613 ni2dest))));
3618 {
3626 }
3627 }
3630 }
3632 /* If recog_for_combine has discarded clobbers, try to use them
3633 again for the split. */
3635 {
3638 }
3641 {
3646 }
3650 {
3660 /* If I2 or I3 has multiple SETs, we won't know how to track
3661 register status, so don't use these insns. If I2's destination
3662 is used between I2 and I3, we also can't use these insns. */
3672 /* It is possible that both insns now set the destination of I3.
3673 If so, we must show an extra use of it. */
3676 {
3695 }
3696 }
3698 /* If we can split it and use I2DEST, go ahead and see if that
3699 helps things be recognized. Verify that none of the registers
3700 are set between I2 and I3. */
3703 /* We need I2DEST in the proper mode. If it is a hard register
3704 or the only use of a pseudo, we can change its mode.
3705 Make sure we don't change a hard register to have a mode that
3706 isn't valid for it, or change the number of registers. */
3713 /* We can't overwrite I2DEST if its value is still used by
3714 NEWPAT. */
3716 /* We should not split a possibly trapping part when we
3717 care about non-call EH and have REG_EH_REGION notes
3718 to distribute. */
3720 && has_non_call_exception
3722 {
3731 /* *SPLIT may be part of I2SRC, so make sure we have the
3732 original expression around for later debug processing.
3733 We should not need I2SRC any more in other cases. */
3736 else
3739 /* Get NEWDEST as a register in the proper mode. We have already
3740 validated that we can do this. */
3742 {
3745 else
3746 {
3749 }
3750 }
3752 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3753 an ASHIFT. This can occur if it was inside a PLUS and hence
3754 appeared to be a memory address. This is a kludge. */
3759 {
3763 /* Update split_code because we may not have a multiply
3764 anymore. */
3766 }
3768 /* Similarly for (plus (mult FOO (const_int pow2))). */
3774 {
3779 i_rtx));
3780 /* Update split_code because we may not have a multiply
3781 anymore. */
3783 }
3785 #ifdef INSN_SCHEDULING
3786 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3787 be written as a ZERO_EXTEND. */
3789 {
3790 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3791 what it really is. */
3796 else
3799 }
3800 #endif
3802 /* Attempt to split binary operators using arithmetic identities. */
3806 {
3813 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3815 {
3820 }
3821 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3828 {
3834 /* Split both "((X op Y) op X) op Y" and
3835 "((X op Y) op Y) op X" as "T op T" where T is
3836 "X op Y". */
3839 {
3844 }
3845 /* Split "((X op X) op Y) op Y)" as "T op T" where
3846 T is "X op Y". */
3848 {
3854 }
3855 }
3856 }
3859 {
3862 }
3866 /* recog_for_combine might have added CLOBBERs to newi2pat.
3867 Make sure NEWPAT does not depend on the clobbered regs. */
3871 {
3874 {
3877 }
3878 }
3880 /* If the split point was a MULT and we didn't have one before,
3881 don't use one now. */
3884 }
3885 }
3887 /* Check for a case where we loaded from memory in a narrow mode and
3888 then sign extended it, but we need both registers. In that case,
3889 we have a PARALLEL with both loads from the same memory location.
3890 We can split this into a load from memory followed by a register-register
3891 copy. This saves at least one insn, more if register allocation can
3892 eliminate the copy.
3894 We cannot do this if the destination of the first assignment is a
3895 condition code register. We eliminate this case by making sure
3896 the SET_DEST and SET_SRC have the same mode.
3898 We cannot do this if the destination of the second assignment is
3899 a register that we have already assumed is zero-extended. Similarly
3900 for a SUBREG of such a register. */
3919 BITS_PER_WORD)
3921 HOST_BITS_PER_INT)
3929 BITS_PER_WORD)
3931 HOST_BITS_PER_INT)
3938 {
3939 rtx ni2dest;
3953 }
3955 /* Similarly, check for a case where we have a PARALLEL of two independent
3956 SETs but we started with three insns. In this case, we can do the sets
3957 as two separate insns. This case occurs when some SET allows two
3958 other insns to combine, but the destination of that SET is still live.
3960 Also do this if we started with two insns and (at least) one of the
3961 resulting sets is a noop; this noop will be deleted later.
3963 Also do this if we started with two insns neither of which was a simple
3964 move. */
3971 && (i1
3985 {
3989 /* Normally, it doesn't matter which of the two is done first, but
3990 one which uses any regs/memory set in between i2 and i3 can't
3991 be first. The PARALLEL might also have been pre-existing in i3,
3992 so we need to make sure that we won't wrongly hoist a SET to i2
3993 that would conflict with a death note present in there, or would
3994 have its dest modified between i2 and i3. */
4002 /* If I3 is a jump, ensure that set0 is a jump so that
4003 we do not create invalid RTL. */
4005 )
4006 {
4009 }
4017 /* If I3 is a jump, ensure that set1 is a jump so that
4018 we do not create invalid RTL. */
4020 )
4021 {
4024 }
4025 else
4026 {
4029 }
4034 {
4035 /* recog_for_combine might have added CLOBBERs to newi2pat.
4036 Make sure NEWPAT does not depend on the clobbered regs. */
4038 {
4041 {
4044 {
4047 }
4048 }
4049 }
4053 /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4054 Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4055 mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4057 {
4060 {
4064 {
4067 }
4068 }
4069 }
4073 }
4074 }
4076 /* If it still isn't recognized, fail and change things back the way they
4077 were. */
4079 /* Is the result a reasonable ASM_OPERANDS? */
4081 {
4084 }
4086 /* If we had to change another insn, make sure it is valid also. */
4088 {
4096 {
4099 }
4100 }
4102 /* Only allow this combination if insn_cost reports that the
4103 replacement instructions are cheaper than the originals. */
4105 {
4108 }
4111 {
4116 {
4121 /* Temporarily revert mode back. */
4125 {
4126 /* If we used i2dest as a scratch register with a
4127 different mode, substitute it for the original
4128 i2src while its original mode is temporarily
4129 restored, and then clear i2scratch so that we don't
4130 do it again later. */
4132 this_basic_block);
4134 /* Put back the new mode. */
4136 }
4137 else
4138 {
4143 {
4146 }
4147 else
4148 {
4155 }
4157 /* We're dealing with a reg that changed mode but not
4158 meaning, so we want to turn it into a subreg for
4159 the new mode. However, because of REG sharing and
4160 because its mode had already changed, we have to do
4161 it in two steps. First, replace any debug uses of
4162 reg, with its original mode temporarily restored,
4163 with this copy we have created; then, replace the
4164 copy with the SUBREG of the original shared reg,
4165 once again changed to the new mode. */
4167 this_basic_block);
4171 this_basic_block);
4172 }
4173 }
4174 }
4176 /* If we will be able to accept this, we have made a
4177 change to the destination of I3. This requires us to
4178 do a few adjustments. */
4181 {
4184 }
4186 /* We now know that we can do this combination. Merge the insns and
4187 update the status of registers and LOG_LINKS. */
4190 {
4195 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4196 ensure that they are still valid. Then add any non-duplicate
4197 notes added by recog_for_combine. */
4199 {
4208 /* Simply drop equal note since it may be no longer valid
4209 for other_insn. It may be possible to record that CC
4210 register is changed and only discard those notes, but
4211 in practice it's unnecessary complication and doesn't
4212 give any meaningful improvement.
4214 See PR78559. */
4218 }
4222 NULL_RTX);
4223 }
4226 {
4227 /* I3 now uses what used to be its destination and which is now
4228 I2's destination. This requires us to do a few adjustments. */
4231 }
4234 {
4235 /* We might need a LOG_LINK from I3 to I2. But then we used to
4236 have one, so we still will.
4238 However, some later insn might be using I2's dest and have
4239 a LOG_LINK pointing at I3. We should change it to point at
4240 I2 instead. */
4242 /* newi2pat is usually a SET here; however, recog_for_combine might
4243 have added some clobbers. */
4251 {
4256 !done
4257 && insn
4261 {
4267 {
4271 }
4272 }
4273 }
4274 }
4276 {
4281 /* Compute which registers we expect to eliminate. newi2pat may be setting
4282 either i3dest or i2dest, so we must check it. */
4285 || !i2dest_killed
4287 /* For i1, we need to compute both local elimination and global
4288 elimination information with respect to newi2pat because i1dest
4289 may be the same as i3dest, in which case newi2pat may be setting
4290 i1dest. Global information is used when distributing REG_DEAD
4291 note for i2 and i3, in which case it does matter if newi2pat sets
4292 i1dest or not.
4294 Local information is used when distributing REG_DEAD note for i1,
4295 in which case it doesn't matter if newi2pat sets i1dest or not.
4296 See PR62151, if we have four insns combination:
4297 i0: r0 <- i0src
4298 i1: r1 <- i1src (using r0)
4299 REG_DEAD (r0)
4300 i2: r0 <- i2src (using r1)
4301 i3: r3 <- i3src (using r0)
4302 ix: using r0
4303 From i1's point of view, r0 is eliminated, no matter if it is set
4304 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4305 should be discarded.
4307 Note local information only affects cases in forms like "I1->I2->I3",
4308 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4309 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4310 i0dest anyway. */
4312 || !i1dest_killed
4317 /* Same case as i1. */
4324 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4325 clear them. */
4333 /* Ensure that we do not have something that should not be shared but
4334 occurs multiple times in the new insns. Check this by first
4335 resetting all the `used' flags and then copying anything is shared. */
4359 {
4362 {
4364 {
4365 /* I2SRC must still be meaningful at this point. Some
4366 splitting operations can invalidate I2SRC, but those
4367 operations do not apply to calls. */
4371 }
4378 }
4379 }
4384 /* We had one special case above where I2 had more than one set and
4385 we replaced a destination of one of those sets with the destination
4386 of I3. In that case, we have to update LOG_LINKS of insns later
4387 in this basic block. Note that this (expensive) case is rare.
4389 Also, in this case, we must pretend that all REG_NOTEs for I2
4390 actually came from I3, so that REG_UNUSED notes from I2 will be
4391 properly handled. */
4394 {
4403 temp_insn
4413 {
4418 }
4419 else
4422 }
4430 {
4433 this_basic_block);
4436 }
4437 else
4438 {
4441 this_basic_block);
4443 }
4446 {
4451 this_basic_block);
4453 }
4456 {
4461 this_basic_block);
4463 }
4465 /* Get death notes for everything that is now used in either I3 or
4466 I2 and used to die in a previous insn. If we built two new
4467 patterns, move from I1 to I2 then I2 to I3 so that we get the
4468 proper movement on registers that I2 modifies. */
4474 else
4480 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4497 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4498 know these are REG_UNUSED and want them to go to the desired insn,
4499 so we always pass it as i3. */
4503 NULL_RTX);
4507 NULL_RTX);
4509 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4510 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4511 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4512 in that case, it might delete I2. Similarly for I2 and I1.
4513 Show an additional death due to the REG_DEAD note we make here. If
4514 we discard it in distribute_notes, we will decrement it again. */
4517 {
4522 else
4525 }
4528 {
4533 else
4536 }
4539 {
4544 else
4547 }
4550 {
4555 else
4558 }
4566 {
4571 /* The insn that used to set this register doesn't exist, and
4572 this life of the register may not exist either. See if one of
4573 I3's links points to an insn that sets I2DEST. If it does,
4574 that is now the last known value for I2DEST. If we don't update
4575 this and I2 set the register to a value that depended on its old
4576 contents, we will get confused. If this insn is used, thing
4577 will be set correctly in combine_instructions. */
4585 /* If the reg formerly set in I2 died only once and that was in I3,
4586 zero its use count so it won't make `reload' do any work. */
4589 && ! i2dest_in_i2src
4592 }
4595 {
4608 && ! i1dest_in_i1src
4611 }
4614 {
4627 && ! i0dest_in_i0src
4630 }
4632 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4633 been made to this insn. The order is important, because newi2pat
4634 can affect nonzero_bits of newpat. */
4638 }
4641 {
4643 {
4646 }
4648 }
4651 {
4653 {
4656 }
4658 }
4661 {
4663 {
4666 }
4668 }
4671 {
4673 {
4676 }
4678 }
4681 {
4683 {
4686 }
4688 }
4690 /* Set new_direct_jump_p if a new return or simple jump instruction
4691 has been created. Adjust the CFG accordingly. */
4693 {
4697 }
4702 {
4705 }
4709 {
4715 }
4720 {
4726 }
4728 /* A noop might also need cleaning up of CFG, if it comes from the
4729 simplification of a jump. */
4734 {
4737 }
4744 {
4747 }
4749 combine_successes++;
4759 }
4760 \f
4761 /* Get a marker for undoing to the current state. */
4765 {
4767 }
4769 /* Undo the modifications up to the marker. */
4771 static void
4773 {
4777 {
4782 {
4798 }
4802 }
4805 }
4807 /* Undo all the modifications recorded in undobuf. */
4809 static void
4811 {
4813 }
4815 /* We've committed to accepting the changes we made. Move all
4816 of the undos to the free list. */
4818 static void
4820 {
4824 {
4828 }
4830 }
4831 \f
4832 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4833 where we have an arithmetic expression and return that point. LOC will
4834 be inside INSN.
4836 try_combine will call this function to see if an insn can be split into
4837 two insns. */
4841 {
4851 /* First special-case some codes. */
4853 {
4855 #ifdef INSN_SCHEDULING
4856 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4857 point. */
4860 #endif
4864 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4865 using LO_SUM and HIGH. */
4868 {
4876 }
4878 /* If we have a PLUS whose second operand is a constant and the
4879 address is not valid, perhaps we can split it up using
4880 the machine-specific way to split large constants. We use
4881 the first pseudo-reg (one of the virtual regs) as a placeholder;
4882 it will not remain in the result. */
4887 {
4890 subst_insn);
4892 /* This should have produced two insns, each of which sets our
4893 placeholder. If the source of the second is a valid address,
4894 we can put both sources together and make a split point
4895 in the middle. */
4908 && memory_address_addr_space_p
4911 {
4915 /* Replace the placeholder in SRC2 with SRC1. If we can
4916 find where in SRC2 it was placed, that can become our
4917 split point and we can replace this address with SRC2.
4918 Just try two obvious places. */
4929 {
4932 }
4933 }
4935 /* If that didn't work and we have a nested plus, like:
4936 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4937 is valid address, try to split (REG1 * CONST1). */
4944 {
4949 {
4952 }
4954 }
4961 {
4966 {
4969 }
4971 }
4973 /* If that didn't work, perhaps the first operand is complex and
4974 needs to be computed separately, so make a split point there.
4975 This will occur on machines that just support REG + CONST
4976 and have a constant moved through some previous computation. */
4981 }
4983 /* If we have a PLUS whose first operand is complex, try computing it
4984 separately by making a split there. */
4995 /* See if we can split SET_SRC as it stands. */
5000 /* See if we can split SET_DEST as it stands. */
5005 /* See if this is a bitfield assignment with everything constant. If
5006 so, this is an IOR of an AND, so split it into that. */
5018 {
5024 rtx or_mask;
5033 else
5034 {
5040 or_mask));
5041 }
5048 }
5050 /* Otherwise, see if this is an operation that we can split into two.
5051 If so, try to split that. */
5055 {
5057 /* If we are AND'ing with a large constant that is only a single
5058 bit and the result is only being used in a context where we
5059 need to know if it is zero or nonzero, replace it with a bit
5060 extraction. This will avoid the large constant, which might
5061 have taken more than one insn to make. If the constant were
5062 not a valid argument to the AND but took only one insn to make,
5063 this is no worse, but if it took more than one insn, it will
5064 be better. */
5074 {
5079 {
5082 }
5083 }
5087 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5088 is known to be on, this can be converted into a NEG of a shift. */
5094 {
5101 pos_rtx)));
5106 }
5112 /* We can't optimize if either mode is a partial integer
5113 mode as we don't know how many bits are significant
5114 in those modes. */
5130 {
5138 }
5143 }
5149 {
5150 /* For unsigned, we have a choice of a shift followed by an
5151 AND or two shifts. Use two shifts for field sizes where the
5152 constant might be too large. We assume here that we can
5153 always at least get 8-bit constants in an AND insn, which is
5154 true for every current RISC. */
5157 {
5158 unsigned HOST_WIDE_INT mask
5163 gen_rtx_LSHIFTRT
5170 }
5171 else
5172 {
5176 gen_rtx_fmt_ee
5186 }
5187 }
5189 /* See if this is a simple operation with a constant as the second
5190 operand. It might be that this constant is out of range and hence
5191 could be used as a split point. */
5199 /* Finally, see if this is a simple operation with its first operand
5200 not in a register. The operation might require this operand in a
5201 register, so return it as a split point. We can always do this
5202 because if the first operand were another operation, we would have
5203 already found it as a split point. */
5212 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5213 it is better to write this as (not (ior A B)) so we can split it.
5214 Similarly for IOR. */
5216 {
5224 }
5226 /* Many RISC machines have a large set of logical insns. If the
5227 second operand is a NOT, put it first so we will try to split the
5228 other operand first. */
5230 {
5234 }
5239 /* Canonicalization can produce (minus A (mult B C)), where C is a
5240 constant. It may be better to try splitting (plus (mult B -C) A)
5241 instead if this isn't a multiply by a power of two. */
5245 {
5253 mode)),
5256 }
5258 /* Split at a multiply-accumulate instruction. However if this is
5259 the SET_SRC, we likely do not have such an instruction and it's
5260 worthless to try this split. */
5269 }
5271 /* Otherwise, select our actions depending on our rtx class. */
5273 {
5279 /* fall through */
5287 /* fall through */
5289 /* Some machines have (and (shift ...) ...) insns. If X is not
5290 an AND, but XEXP (X, 0) is, use it as our split point. */
5300 /* Otherwise, we don't have a split point. */
5302 }
5303 }
5304 \f
5305 /* Throughout X, replace FROM with TO, and return the result.
5306 The result is TO if X is FROM;
5307 otherwise the result is X, but its contents may have been modified.
5308 If they were modified, a record was made in undobuf so that
5309 undo_all will (among other things) return X to its original state.
5311 If the number of changes necessary is too much to record to undo,
5312 the excess changes are not made, so the result is invalid.
5313 The changes already made can still be undone.
5314 undobuf.num_undo is incremented for such changes, so by testing that
5315 the caller can tell whether the result is valid.
5317 `n_occurrences' is incremented each time FROM is replaced.
5319 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5321 IN_COND is nonzero if we are at the top level of a condition.
5323 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5324 by copying if `n_occurrences' is nonzero. */
5326 static rtx
5328 {
5333 rtx new_rtx;
5335 /* Two expressions are equal if they are identical copies of a shared
5336 RTX or if they are both registers with the same register number
5337 and mode. */
5339 #define COMBINE_RTX_EQUAL_P(X,Y) \
5340 ((X) == (Y) \
5341 || (REG_P (X) && REG_P (Y) \
5342 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5344 /* Do not substitute into clobbers of regs -- this will never result in
5345 valid RTL. */
5350 {
5351 n_occurrences++;
5353 }
5355 /* If X and FROM are the same register but different modes, they
5356 will not have been seen as equal above. However, the log links code
5357 will make a LOG_LINKS entry for that case. If we do nothing, we
5358 will try to rerecognize our original insn and, when it succeeds,
5359 we will delete the feeding insn, which is incorrect.
5361 So force this insn not to match in this (rare) case. */
5366 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5367 of which may contain things that can be combined. */
5371 /* It is possible to have a subexpression appear twice in the insn.
5372 Suppose that FROM is a register that appears within TO.
5373 Then, after that subexpression has been scanned once by `subst',
5374 the second time it is scanned, TO may be found. If we were
5375 to scan TO here, we would find FROM within it and create a
5376 self-referent rtl structure which is completely wrong. */
5380 /* Parallel asm_operands need special attention because all of the
5381 inputs are shared across the arms. Furthermore, unsharing the
5382 rtl results in recognition failures. Failure to handle this case
5383 specially can result in circular rtl.
5385 Solve this by doing a normal pass across the first entry of the
5386 parallel, and only processing the SET_DESTs of the subsequent
5387 entries. Ug. */
5392 {
5395 /* If this substitution failed, this whole thing fails. */
5403 {
5407 {
5410 /* If this substitution failed, this whole thing fails. */
5416 }
5417 }
5418 }
5419 else
5420 {
5424 /* We don't need to process a SET_DEST that is a register or PC, so
5425 set up to skip this common case. All other cases where we want
5426 to suppress replacing something inside a SET_SRC are handled via
5427 the IN_DEST operand. */
5433 /* Trying to simplify the operands of a widening MULT is not likely
5434 to create RTL matching a machine insn. */
5446 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5447 constant. */
5452 {
5454 {
5457 {
5459 {
5462 n_occurrences++;
5463 }
5464 else
5465 {
5467 unique_copy);
5469 /* If this substitution failed, this whole thing
5470 fails. */
5474 }
5477 }
5478 }
5480 {
5481 /* If this is a register being set, ignore it. */
5488 ;
5491 {
5492 /* In general, don't install a subreg involving two
5493 modes not tieable. It can worsen register
5494 allocation, and can even make invalid reload
5495 insns, since the reg inside may need to be copied
5496 from in the outside mode, and that may be invalid
5497 if it is an fp reg copied in integer mode.
5499 We allow an exception to this: It is valid if
5500 it is inside another SUBREG and the mode of that
5501 SUBREG and the mode of the inside of TO is
5502 tieable. */
5521 n_occurrences++;
5522 }
5523 else
5524 /* If we are in a SET_DEST, suppress most cases unless we
5525 have gone inside a MEM, in which case we want to
5526 simplify the address. We assume here that things that
5527 are actually part of the destination have their inner
5528 parts in the first expression. This is true for SUBREG,
5529 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5530 things aside from REG and MEM that should appear in a
5531 SET_DEST. */
5533 (((in_dest
5539 unique_copy);
5541 /* If we found that we will have to reject this combination,
5542 indicate that by returning the CLOBBER ourselves, rather than
5543 an expression containing it. This will speed things up as
5544 well as prevent accidents where two CLOBBERs are considered
5545 to be equal, thus producing an incorrect simplification. */
5551 {
5559 }
5565 {
5567 new_rtx,
5571 }
5572 /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5573 etc. arguments, otherwise we can ICE before trying to recog
5574 it. See PR104446. */
5578 else
5580 }
5581 }
5582 }
5584 /* Check if we are loading something from the constant pool via float
5585 extension; in this case we would undo compress_float_constant
5586 optimization and degenerate constant load to an immediate value. */
5590 {
5594 }
5596 /* Try to simplify X. If the simplification changed the code, it is likely
5597 that further simplification will help, so loop, but limit the number
5598 of repetitions that will be performed. */
5601 {
5602 /* If X is sufficiently simple, don't bother trying to do anything
5603 with it. */
5612 /* We no longer know the original mode of operand 0 since we
5613 have changed the form of X) */
5615 }
5618 }
5619 \f
5620 /* If X is a commutative operation whose operands are not in the canonical
5621 order, use substitutions to swap them. */
5623 static void
5625 {
5628 {
5632 }
5633 }
5635 /* Simplify X, a piece of RTL. We just operate on the expression at the
5636 outer level; call `subst' to simplify recursively. Return the new
5637 expression.
5639 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5640 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5641 of a condition. */
5643 static rtx
5646 {
5649 scalar_int_mode int_mode;
5650 rtx temp;
5653 /* If this is a commutative operation, put a constant last and a complex
5654 expression first. We don't need to do this for comparisons here. */
5657 /* Try to fold this expression in case we have constants that weren't
5658 present before. */
5661 {
5669 {
5672 {
5676 }
5679 }
5692 }
5695 {
5700 }
5702 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5703 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5704 things. Check for cases where both arms are testing the same
5705 condition.
5707 Don't do anything if all operands are very simple. */
5720 {
5725 /* If everything is a comparison, what we have is highly unlikely
5726 to be simpler, so don't use it. */
5729 /* Similarly, if we end up with one of the expressions the same
5730 as the original, it is certainly not simpler. */
5733 {
5740 /* Simplify the alternative arms; this may collapse the true and
5741 false arms to store-flag values. Be careful to use copy_rtx
5742 here since true_rtx or false_rtx might share RTL with x as a
5743 result of the if_then_else_cond call above. */
5747 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5748 is unlikely to be simpler. */
5751 {
5754 /* Restarting if we generate a store-flag expression will cause
5755 us to loop. Just drop through in this case. */
5757 /* If the result values are STORE_FLAG_VALUE and zero, we can
5758 just make the comparison operation. */
5769 /* Likewise, we can make the negate of a comparison operation
5770 if the result values are - STORE_FLAG_VALUE and zero. */
5778 mode);
5789 mode);
5793 }
5794 }
5795 }
5797 /* First see if we can apply the inverse distributive law. */
5800 {
5804 }
5806 /* If CODE is an associative operation not otherwise handled, see if we
5807 can associate some operands. This can win if they are constants or
5808 if they are logically related (i.e. (a & b) & a). */
5814 {
5816 {
5820 rtx inner;
5822 /* Make sure we pass the constant operand if any as the second
5823 one if this is a commutative operation. */
5831 /* For commutative operations, try the other pair if that one
5832 didn't simplify. */
5834 {
5839 }
5843 }
5844 }
5846 /* A little bit of algebraic simplification here. */
5848 {
5850 /* Ensure that our address has any ASHIFTs converted to MULT in case
5851 address-recognizing predicates are called later. */
5860 /* See if this can be moved to simplify_subreg. */
5863 /* Don't call gen_lowpart if the inner mode
5864 is VOIDmode and we cannot simplify it, as SUBREG without
5865 inner mode is invalid. */
5872 {
5873 rtx temp;
5879 /* If op is known to have all lower bits zero, the result is zero. */
5893 }
5895 /* Don't change the mode of the MEM if that would change the meaning
5896 of the address. */
5903 /* Note that we cannot do any narrowing for non-constants since
5904 we might have been counting on using the fact that some bits were
5905 zero. We now do this in the SET. */
5912 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5913 replaced by (lshiftrt X C). This will convert
5914 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5922 /* If X has only a single bit that might be nonzero, say, bit I, convert
5923 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5924 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5925 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5926 or a SUBREG of one since we'd be making the expression more
5927 complex if it was just a register. */
5934 {
5935 rtx temp1 = simplify_shift_const
5941 /* If all we did was surround TEMP with the two shifts, we
5942 haven't improved anything, so don't use it. Otherwise,
5943 we are better off with TEMP1. */
5948 }
5952 /* We can't handle truncation to a partial integer mode here
5953 because we don't know the real bitsize of the partial
5954 integer mode. */
5963 /* We can truncate a constant value and return it. */
5964 {
5965 poly_int64 c;
5968 }
5970 /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
5971 whose value is a comparison can be replaced with a subreg if
5972 STORE_FLAG_VALUE permits. */
5982 /* (const (const X)) can become (const X). Do it this way rather than
5983 returning the inner CONST since CONST can be shared with a
5984 REG_EQUAL note. */
5990 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5991 can add in an offset. find_split_point will split this address up
5992 again if it doesn't match. */
5999 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6000 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6001 bit-field and can be replaced by either a sign_extend or a
6002 sign_extract. The `and' may be a zero_extend and the two
6003 <c>, -<c> constants may be reversed. */
6020 return simplify_shift_const
6027 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6028 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6029 the bitsize of the mode - 1. This allows simplification of
6030 "a = (b & 8) == 0;" */
6037 return simplify_shift_const
6041 const1_rtx),
6045 /* If we are adding two things that have no bits in common, convert
6046 the addition into an IOR. This will often be further simplified,
6047 for example in cases like ((a & 1) + (a & 2)), which can
6048 become a & 3. */
6053 {
6054 /* Try to simplify the expression further. */
6058 /* If we could, great. If not, do not go ahead with the IOR
6059 replacement, since PLUS appears in many special purpose
6060 address arithmetic instructions. */
6068 }
6070 /* Canonicalize x + x into x << 1. */
6079 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6080 (and <foo> (const_int pow2-1)) */
6091 /* If we have (mult (plus A B) C), apply the distributive law and then
6092 the inverse distributive law to see if things simplify. This
6093 occurs mostly in addresses, often when unrolling loops. */
6096 {
6100 }
6102 /* Try simplify a*(b/c) as (a*b)/c. */
6105 {
6111 }
6115 /* If this is a divide by a power of two, treat it as a shift if
6116 its first operand is a shift. */
6136 /* If the first operand is a condition code, we can't do anything
6137 with it. */
6140 {
6148 /* Simplify our comparison, if possible. */
6151 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6152 if only the low-order bit is possibly nonzero in X (such as when
6153 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6154 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6155 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6156 (plus X 1).
6158 Remove any ZERO_EXTRACT we made when thinking this was a
6159 comparison. It may now be simpler to use, e.g., an AND. If a
6160 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6161 the call to make_compound_operation in the SET case.
6163 Don't apply these optimizations if the caller would
6164 prefer a comparison rather than a value.
6165 E.g., for the condition in an IF_THEN_ELSE most targets need
6166 an explicit comparison. */
6169 ;
6187 {
6191 int_mode);
6192 }
6200 {
6204 const1_rtx);
6205 }
6214 {
6217 }
6219 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6220 those above. */
6222 ;
6239 {
6243 int_mode);
6244 }
6253 {
6257 int_mode);
6258 }
6260 /* If X is 0/1, (eq X 0) is X-1. */
6267 {
6270 }
6272 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6273 one bit that might be nonzero, we can convert (ne x 0) to
6274 (ashift x c) where C puts the bit in the sign bit. Remove any
6275 AND with STORE_FLAG_VALUE when we are done, since we are only
6276 going to test the sign bit. */
6284 {
6290 else
6292 }
6294 /* If the code changed, return a whole new comparison.
6295 We also need to avoid using SUBST in cases where
6296 simplify_comparison has widened a comparison with a CONST_INT,
6297 since in that case the wider CONST_INT may fail the sanity
6298 checks in do_SUBST. */
6305 /* Otherwise, keep this operation, but maybe change its operands.
6306 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6309 }
6319 /* If we are processing SET_DEST, we are done. */
6337 /* If this is a shift by a constant amount, simplify it. */
6345 (HOST_WIDE_INT_1U
6352 {
6356 /* If we select a low-part subreg, return that. */
6358 {
6362 }
6363 }
6367 }
6370 }
6371 \f
6372 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6374 static rtx
6376 {
6383 rtx temp;
6386 rtx reversed;
6389 /* Simplify storing of the truth value. */
6394 /* Also when the truth value has to be reversed. */
6400 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6401 in it is being compared against certain values. Get the true and false
6402 comparisons and see if that says anything about the value of each arm. */
6408 {
6409 HOST_WIDE_INT nzb;
6415 /* If FALSE_CODE is EQ, swap the codes and arms. */
6418 {
6421 }
6423 scalar_int_mode from_mode;
6425 {
6426 /* If we are comparing against zero and the expression being
6427 tested has only a single bit that might be nonzero, that is
6428 its value when it is not equal to zero. Similarly if it is
6429 known to be -1 or 0. */
6433 {
6436 }
6441 {
6444 }
6445 }
6447 /* Now simplify an arm if we know the value of the register in the
6448 branch and it is used in the arm. Be careful due to the potential
6449 of locally-shared RTL. */
6466 }
6468 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6469 reversed, do so to avoid needing two sets of patterns for
6470 subtract-and-branch insns. Similarly if we have a constant in the true
6471 arm, the false arm is the same as the first operand of the comparison, or
6472 the false arm is more complicated than the true arm. */
6485 {
6493 /* It is possible that the conditional has been simplified out. */
6496 }
6498 /* If the two arms are identical, we don't need the comparison. */
6503 /* Convert a == b ? b : a to "a". */
6515 /* Look for cases where we have (abs x) or (neg (abs X)). */
6518 && comparison_p
6525 {
6531 return
6534 mode);
6537 }
6539 /* Look for MIN or MAX. */
6542 || (flag_unsafe_math_optimizations
6545 && comparison_p
6550 {
6565 }
6567 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6568 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6569 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6570 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6571 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6572 neither 1 or -1, but it isn't worth checking for. */
6575 && comparison_p
6578 {
6594 /* If an identity-zero op is commutative, check whether there
6595 would be a match if we swapped the operands. */
6616 {
6620 }
6633 {
6637 }
6654 {
6658 }
6671 {
6675 }
6678 {
6688 const_true_rtx));
6696 }
6697 }
6699 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6700 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6701 negation of a single bit, we can convert this operation to a shift. We
6702 can actually do this more generally, but it doesn't seem worth it. */
6714 return
6718 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6719 non-zero bit in A is C1. */
6727 {
6733 }
6736 }
6737 \f
6738 /* Simplify X, a SET expression. Return the new expression. */
6740 static rtx
6742 {
6745 machine_mode mode
6749 scalar_int_mode int_mode;
6751 /* (set (pc) (return)) gets written as (return). */
6755 /* Now that we know for sure which bits of SRC we are using, see if we can
6756 simplify the expression for the object knowing that we only need the
6757 low-order bits. */
6760 {
6763 }
6765 /* If the source is a COMPARE, look for the use of the comparison result
6766 and try to simplify it unless we already have used undobuf.other_insn. */
6772 {
6781 {
6784 {
6787 }
6788 }
6789 else
6797 {
6801 }
6802 else
6803 {
6808 /* Attempt to simplify CC user. */
6810 {
6814 }
6816 /* Convert X into a no-op move. */
6820 }
6822 /* Simplify our comparison, if possible. */
6825 #ifdef SELECT_CC_MODE
6826 /* If this machine has CC modes other than CCmode, check to see if we
6827 need to use a different CC mode here. */
6836 else
6839 /* If the mode changed, we have to change SET_DEST, the mode in the
6840 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6841 a hard register, just build new versions with the proper mode. If it
6842 is a pseudo, we lose unless it is only time we set the pseudo, in
6843 which case we can safely change its mode. */
6845 {
6847 {
6849 rtx new_dest;
6853 else
6854 {
6857 }
6864 }
6865 }
6868 /* If the code changed, we have to build a new comparison in
6869 undobuf.other_insn. */
6871 {
6880 /* If the only change we made was to change an EQ into an NE or
6881 vice versa, OP0 has only one bit that might be nonzero, and OP1
6882 is zero, check if changing the user of the condition code will
6883 produce a valid insn. If it won't, we can keep the original code
6884 in that insn by surrounding our operation with an XOR. */
6891 {
6896 {
6903 }
6904 }
6905 }
6910 /* Don't generate a compare of a CC with 0, just use that CC. */
6912 {
6915 }
6916 /* Otherwise, if we didn't previously have the same COMPARE we
6917 want, create it from scratch. */
6920 {
6923 }
6924 }
6925 else
6926 {
6927 /* Get SET_SRC in a form where we have placed back any
6928 compound expressions. Then do the checks below. */
6931 }
6933 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6934 and X being a REG or (subreg (reg)), we may be able to convert this to
6935 (set (subreg:m2 x) (op)).
6937 We can always do this if M1 is narrower than M2 because that means that
6938 we only care about the low bits of the result.
6940 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6941 perform a narrower operation than requested since the high-order bits will
6942 be undefined. On machine where it is defined, this transformation is safe
6943 as long as M1 and M2 have the same number of words. */
6947 && (known_equal_after_align_up
6950 UNITS_PER_WORD))
6959 {
6962 dest));
6966 }
6968 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6969 would require a paradoxical subreg. Replace the subreg with a
6970 zero_extend to avoid the reload that would otherwise be required.
6971 Don't do this unless we have a scalar integer mode, otherwise the
6972 transformation is incorrect. */
6979 {
6984 }
6986 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6987 are comparing an item known to be 0 or -1 against 0, use a logical
6988 operation instead. Check for one of the arms being an IOR of the other
6989 arm with some value. We compute three terms to be IOR'ed together. In
6990 practice, at most two will be nonzero. Then we do the IOR's. */
6998 && (!HAVE_conditional_move
7003 {
7028 int_mode),
7029 false_rtx);
7035 term3));
7038 }
7040 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7041 whole thing fail. */
7046 else
7047 /* Convert this into a field assignment operation, if possible. */
7049 }
7050 \f
7051 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7052 result. */
7054 static rtx
7056 {
7059 scalar_int_mode mode;
7062 {
7064 /* We can call simplify_and_const_int only if we don't lose
7065 any (sign) bits when converting INTVAL (op1) to
7066 "unsigned HOST_WIDE_INT". */
7071 {
7078 }
7080 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7081 apply the distributive law and then the inverse distributive
7082 law to see if things simplify. */
7084 {
7088 }
7090 {
7094 }
7098 /* If we have (ior (and A B) C), apply the distributive law and then
7099 the inverse distributive law to see if things simplify. */
7102 {
7106 }
7109 {
7113 }
7118 }
7121 }
7122 \f
7123 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7124 operations" because they can be replaced with two more basic operations.
7125 ZERO_EXTEND is also considered "compound" because it can be replaced with
7126 an AND operation, which is simpler, though only one operation.
7128 The function expand_compound_operation is called with an rtx expression
7129 and will convert it to the appropriate shifts and AND operations,
7130 simplifying at each stage.
7132 The function make_compound_operation is called to convert an expression
7133 consisting of shifts and ANDs into the equivalent compound expression.
7134 It is the inverse of this function, loosely speaking. */
7136 static rtx
7138 {
7142 rtx tem;
7143 scalar_int_mode inner_mode;
7146 {
7149 /* FALLTHRU */
7151 /* We can't necessarily use a const_int for a multiword mode;
7152 it depends on implicitly extending the value.
7153 Since we don't know the right way to extend it,
7154 we can't tell whether the implicit way is right.
7156 Even for a mode that is no wider than a const_int,
7157 we can't win, because we need to sign extend one of its bits through
7158 the rest of it, and we don't know which bit. */
7162 /* Reject modes that aren't scalar integers because turning vector
7163 or complex modes into shifts causes problems. */
7167 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7168 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7169 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7170 reloaded. If not for that, MEM's would very rarely be safe.
7172 Reject modes bigger than a word, because we might not be able
7173 to reference a two-register group starting with an arbitrary register
7174 (and currently gen_lowpart might crash for a SUBREG). */
7180 /* If the inner object has VOIDmode (the only way this can happen
7181 is if it is an ASM_OPERANDS), we can't do anything since we don't
7182 know how much masking to do. */
7191 /* fall through */
7194 /* If the operand is a CLOBBER, just return it. */
7202 /* Reject modes that aren't scalar integers because turning vector
7203 or complex modes into shifts causes problems. */
7210 /* This should stay within the object being extracted, fail otherwise. */
7221 }
7223 /* We've rejected non-scalar operations by now. */
7226 /* Convert sign extension to zero extension, if we know that the high
7227 bit is not set, as this is easier to optimize. It will be converted
7228 back to cheaper alternative in make_extraction. */
7234 {
7238 /* Make sure this is a profitable operation. */
7245 else
7247 }
7249 /* We can optimize some special cases of ZERO_EXTEND. */
7251 {
7252 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7253 know that the last value didn't have any inappropriate bits
7254 set. */
7262 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7271 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7272 is a comparison and STORE_FLAG_VALUE permits. This is like
7273 the first case, but it works even when MODE is larger
7274 than HOST_WIDE_INT. */
7282 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7291 }
7293 /* If we reach here, we want to return a pair of shifts. The inner
7294 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7295 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7296 logical depending on the value of UNSIGNEDP.
7298 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7299 converted into an AND of a shift.
7301 We must check for the case where the left shift would have a negative
7302 count. This can happen in a case like (x >> 31) & 255 on machines
7303 that can't shift by a constant. On those machines, we would first
7304 combine the shift with the AND to produce a variable-position
7305 extraction. Then the constant of 31 would be substituted in
7306 to produce such a position. */
7310 {
7318 }
7320 {
7328 }
7329 else
7330 /* Any other cases we can't handle. */
7333 /* If we couldn't do this for some reason, return the original
7334 expression. */
7339 }
7340 \f
7341 /* X is a SET which contains an assignment of one object into
7342 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7343 or certain SUBREGS). If possible, convert it into a series of
7344 logical operations.
7346 We half-heartedly support variable positions, but do not at all
7347 support variable lengths. */
7349 static const_rtx
7351 {
7352 rtx inner;
7356 scalar_int_mode compute_mode;
7358 /* Loop until we find something we can't simplify. */
7360 {
7363 {
7369 MAX_MODE_INT);
7370 }
7373 {
7381 /* A constant position should stay within the width of INNER. */
7386 {
7392 /* If position is ADJUST - X, new position is X. */
7394 else
7398 pos);
7399 }
7400 }
7402 /* If the destination is a subreg that overwrites the whole of the inner
7403 register, we can move the subreg to the source. */
7405 /* We need SUBREGs to compute nonzero_bits properly. */
7406 && nonzero_sign_valid
7408 {
7410 gen_lowpart
7414 }
7415 else
7421 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7423 {
7424 /* Don't do anything for vector or complex integral types. */
7428 /* Try to find an integral mode to pun with. */
7434 }
7436 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7440 /* Don't try to compute in too wide unsupported modes. */
7444 /* Now compute the equivalent expression. Make a copy of INNER
7445 for the SET_DEST in case it is a MEM into which we will substitute;
7446 we don't want shared RTL in that case. */
7448 compute_mode);
7452 compute_mode,
7454 compute_mode),
7455 inner);
7460 mask),
7461 pos);
7466 }
7469 }
7470 \f
7471 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7472 it is an RTX that represents the (variable) starting position; otherwise,
7473 POS is the (constant) starting bit position. Both are counted from the LSB.
7475 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7477 IN_DEST is nonzero if this is a reference in the destination of a SET.
7478 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7479 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7480 be used.
7482 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7483 ZERO_EXTRACT should be built even for bits starting at bit 0.
7485 MODE is the desired mode of the result (if IN_DEST == 0).
7487 The result is an RTX for the extraction or NULL_RTX if the target
7488 can't handle it. */
7490 static rtx
7494 {
7495 /* This mode describes the size of the storage area
7496 to fetch the overall value from. Within that, we
7497 ignore the POS lowest bits, etc. */
7499 machine_mode inner_mode;
7500 scalar_int_mode wanted_inner_mode;
7506 HOST_WIDE_INT orig_pos;
7514 /* If trying or potentionally trying to extract
7515 bits outside of is_mode, don't look through
7516 non-paradoxical SUBREGs. See PR82192. */
7519 {
7520 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7521 consider just the QI as the memory to extract from.
7522 The subreg adds or removes high bits; its mode is
7523 irrelevant to the meaning of this extraction,
7524 since POS and LEN count from the lsb. */
7528 }
7533 {
7534 /* We're extracting the least significant bits of an rtx
7535 (ashift X (const_int C)), where LEN > C. Extract the
7536 least significant (LEN - C) bits of X, giving an rtx
7537 whose mode is MODE, then shift it left C times. */
7543 }
7547 {
7548 /* We're extracting the least significant bits of an rtx
7549 (mult X (const_int 2^C)), where LEN > C. Extract the
7550 least significant (LEN - C) bits of X, giving an rtx
7551 whose mode is MODE, then multiply it by 2^C. */
7554 {
7560 }
7561 }
7563 /* If trying or potentionally trying to extract
7564 bits outside of is_mode, don't look through
7565 TRUNCATE. See PR82192. */
7572 /* See if this can be done without an extraction. We never can if the
7573 width of the field is not the same as that of some integer mode. For
7574 registers, we can only avoid the extraction if the position is at the
7575 low-order bit and this is either not in the destination or we have the
7576 appropriate STRICT_LOW_PART operation available.
7578 For MEM, we can avoid an extract if the field starts on an appropriate
7579 boundary and we can change the mode of the memory reference. */
7581 scalar_int_mode tmode;
7590 && (! in_dest
7594 && (pos
7597 /* We can't do this if we are widening INNER_MODE (it
7598 may not be aligned, for one thing). */
7605 {
7606 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7607 field. If the original and current mode are the same, we need not
7608 adjust the offset. Otherwise, we do if bytes big endian.
7610 If INNER is not a MEM, get a piece consisting of just the field
7611 of interest (in this case POS % BITS_PER_WORD must be 0). */
7614 {
7615 poly_int64 offset;
7617 /* POS counts from lsb, but make OFFSET count in memory order. */
7621 else
7625 }
7627 {
7629 {
7630 /* We can't call gen_lowpart in a DEST since we
7631 always want a SUBREG (see below) and it would sometimes
7632 return a new hard register. */
7634 {
7635 poly_uint64 offset
7638 /* Avoid creating invalid subregs, for example when
7639 simplifying (x>>32)&255. */
7644 }
7645 else
7647 }
7648 else
7650 }
7651 else
7653 len >= HOST_BITS_PER_WIDE_INT
7654 ? HOST_WIDE_INT_M1U
7657 /* If this extraction is going into the destination of a SET,
7658 make a STRICT_LOW_PART unless we made a MEM. */
7673 /* If we know that no extraneous bits are set, and that the high
7674 bit is not set, convert the extraction to the cheaper of
7675 sign and zero extension, that are equivalent in these cases. */
7681 {
7685 /* Prefer ZERO_EXTENSION, since it gives more information to
7686 backends. */
7691 }
7693 /* Otherwise, sign- or zero-extend unless we already are in the
7694 proper mode. */
7698 }
7700 /* Unless this is a COMPARE or we have a funny memory reference,
7701 don't do anything with zero-extending field extracts starting at
7702 the low-order bit since they are simple AND operations. */
7707 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7708 if the position is not a constant and the length is not 1. In all
7709 other cases, we would only be going outside our object in cases when
7710 an original shift would have been undefined. */
7719 /* If INNER is not from memory, we want it to have the mode of a register
7720 extraction pattern's structure operand, or word_mode if there is no
7721 such pattern. The same applies to extraction_mode and pos_mode
7722 and their respective operands.
7724 For memory, assume that the desired extraction_mode and pos_mode
7725 are the same as for a register operation, since at present we don't
7726 have named patterns for aligned memory structures. */
7731 {
7735 }
7737 /* Never narrow an object, since that might not be safe. */
7743 /* Punt if len is too large for extraction_mode. */
7749 else
7750 {
7751 /* Be careful not to go beyond the extracted object and maintain the
7752 natural alignment of the memory. */
7757 }
7762 {
7763 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7764 BITS_BIG_ENDIAN style. If position is constant, compute new
7765 position. Otherwise, build subtraction.
7766 Note that POS is relative to the mode of the original argument.
7767 If it's a MEM we need to recompute POS relative to that.
7768 However, if we're extracting from (or inserting into) a register,
7769 we want to recompute POS relative to wanted_inner_mode. */
7778 else
7779 pos_rtx
7782 pos_rtx);
7783 /* POS may be less than 0 now, but we check for that below.
7784 Note that it can only be less than 0 if !MEM_P (inner). */
7785 }
7787 /* If INNER has a wider mode, and this is a constant extraction, try to
7788 make it smaller and adjust the byte to point to the byte containing
7789 the value. */
7792 && ! pos_rtx
7797 {
7800 /* The computations below will be correct if the machine is big
7801 endian in both bits and bytes or little endian in bits and bytes.
7802 If it is mixed, we must adjust. */
7804 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7805 adjust OFFSET to compensate. */
7810 /* We can now move to the desired byte. */
7821 }
7823 /* If INNER is not memory, get it into the proper mode. If we are changing
7824 its mode, POS must be a constant and smaller than the size of the new
7825 mode. */
7827 {
7828 /* On the LHS, don't create paradoxical subregs implicitely truncating
7829 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7832 wanted_inner_mode))
7844 pos_rtx
7846 ? HOST_WIDE_INT_M1U
7850 }
7852 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7853 have to zero extend. Otherwise, we can just use a SUBREG.
7855 We dealt with constant rtxes earlier, so pos_rtx cannot
7856 have VOIDmode at this point. */
7860 {
7864 /* If we know that no extraneous bits are set, and that the high
7865 bit is not set, convert extraction to cheaper one - either
7866 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7867 cases. */
7875 {
7879 /* Prefer ZERO_EXTENSION, since it gives more information to
7880 backends. */
7884 }
7886 }
7888 /* Make POS_RTX unless we already have it and it is correct. If we don't
7889 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7890 be a CONST_INT. */
7897 /* Make the required operation. See if we can use existing rtx. */
7904 }
7905 \f
7906 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7907 can be commuted with any other operations in X. Return X without
7908 that shift if so. */
7910 static rtx
7912 {
7914 rtx tem;
7917 {
7919 /* This is the shift itself. If it is wide enough, we will return
7920 either the value being shifted if the shift count is equal to
7921 COUNT or a shift for the difference. */
7935 /* If we can safely shift this constant and we find the inner shift,
7936 make a new operation. */
7941 {
7945 }
7950 }
7953 }
7954 \f
7955 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7956 level of the expression and MODE is its mode. IN_CODE is as for
7957 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7958 that should be used when recursing on operands of *X_PTR.
7960 There are two possible actions:
7962 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7963 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7965 - Return a new rtx, which the caller returns directly. */
7967 static rtx
7971 {
7979 rtx tem;
7980 scalar_int_mode inner_mode;
7984 {
7987 }
7989 /* Process depending on the code of this operation. If NEW is set
7990 nonzero, it will be returned. */
7993 {
7995 /* Convert shifts by constants into multiplications if inside
7996 an address. */
8000 {
8006 {
8009 }
8012 }
8021 {
8025 }
8028 {
8032 mode));
8034 }
8035 else
8036 {
8039 }
8049 {
8053 }
8056 {
8060 mode));
8062 }
8063 else
8064 {
8068 }
8071 /* If the second operand is not a constant, we can't do anything
8072 with it. */
8076 /* If the constant is a power of two minus one and the first operand
8077 is a logical right shift, make an extraction. */
8080 {
8084 }
8086 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8093 {
8100 /* If we narrowed the mode when dropping the subreg, then we lose. */
8104 /* If that didn't give anything, see if the AND simplifies on
8105 its own. */
8107 {
8111 }
8112 }
8113 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8119 {
8120 /* Apply the distributive law, and then try to make extractions. */
8127 }
8129 /* If we are have (and (rotate X C) M) and C is larger than the number
8130 of bits in M, this is an extraction. */
8136 {
8142 }
8144 /* On machines without logical shifts, if the operand of the AND is
8145 a logical shift and our mask turns off all the propagated sign
8146 bits, we can replace the logical shift with an arithmetic shift. */
8154 {
8164 next_code),
8166 }
8168 /* If the constant is one less than a power of two, this might be
8169 representable by an extraction even if no shift is present.
8170 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8171 we are in a COMPARE. */
8175 next_code),
8178 /* If we are in a comparison and this is an AND with a power of two,
8179 convert this into the appropriate bit extract. */
8185 next_code),
8188 /* If the one operand is a paradoxical subreg of a register or memory and
8189 the constant (limited to the smaller mode) has only zero bits where
8190 the sub expression has known zero bits, this can be expressed as
8191 a zero_extend. */
8193 {
8194 rtx sub;
8202 {
8206 /* original AND constant with all the known zero bits set */
8209 {
8213 }
8214 }
8215 }
8220 /* If the sign bit is known to be zero, replace this with an
8221 arithmetic shift. */
8226 {
8229 next_code),
8232 }
8234 /* fall through */
8240 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8241 this is a SIGN_EXTRACT. */
8248 {
8255 }
8257 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8258 If so, try to merge the shifts into a SIGN_EXTEND. We could
8259 also do this for some cases of SIGN_EXTRACT, but it doesn't
8260 seem worth the effort; the case checked for occurs on Alpha. */
8271 next_code),
8278 /* Call ourselves recursively on the inner expression. If we are
8279 narrowing the object and it has a different RTL code from
8280 what it originally did, do this SUBREG as a force_to_mode. */
8281 {
8285 /* If the SUBREG is masking of a logical right shift,
8286 make an extraction. */
8293 {
8302 }
8304 /* If in_code is COMPARE, it isn't always safe to pass it through
8305 to the recursive make_compound_operation call. */
8309 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8310 is (const_int 0), rather than
8311 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8312 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8313 for non-equality comparisons against 0 is not equivalent
8314 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8324 simplified
8332 {
8333 rtx newer
8336 /* If we have something other than a SUBREG, we might have
8337 done an expansion, so rerun ourselves. */
8341 /* force_to_mode can expand compounds. If it just re-expanded
8342 the compound, use gen_lowpart to convert to the desired
8343 mode. */
8345 /* Likewise if it re-expanded the compound only partially.
8346 This happens for SUBREG of ZERO_EXTRACT if they extract
8347 the same number of bits. */
8356 }
8360 }
8365 }
8371 }
8373 /* Look at the expression rooted at X. Look for expressions
8374 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8375 Form these expressions.
8377 Return the new rtx, usually just X.
8379 Also, for machines like the VAX that don't have logical shift insns,
8380 try to convert logical to arithmetic shift operations in cases where
8381 they are equivalent. This undoes the canonicalizations to logical
8382 shifts done elsewhere.
8384 We try, as much as possible, to re-use rtl expressions to save memory.
8386 IN_CODE says what kind of expression we are processing. Normally, it is
8387 SET. In a memory address it is MEM. When processing the arguments of
8388 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8389 precisely it is an equality comparison against zero. */
8391 rtx
8393 {
8400 /* Select the code to be used in recursive calls. Once we are inside an
8401 address, we stay there. If we have a comparison, set to COMPARE,
8402 but once inside, go back to our default of SET. */
8409 scalar_int_mode mode;
8411 {
8417 }
8419 /* Now recursively process each operand of this operation. We need to
8420 handle ZERO_EXTEND specially so that we don't lose track of the
8421 inner mode. */
8423 {
8431 }
8436 {
8439 }
8442 {
8445 }
8449 }
8450 \f
8451 /* Given M see if it is a value that would select a field of bits
8452 within an item, but not the entire word. Return -1 if not.
8453 Otherwise, return the starting position of the field, where 0 is the
8454 low-order bit.
8456 *PLEN is set to the length of the field. */
8458 static int
8460 {
8461 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8466 /* Now shift off the low-order zero bits and see if we have a
8467 power of two minus 1. */
8475 }
8476 \f
8477 /* If X refers to a register that equals REG in value, replace these
8478 references with REG. */
8479 static rtx
8481 {
8489 {
8522 /* FALLTHRU */
8526 {
8530 else
8532 }
8534 /* fall through */
8541 {
8544 {
8546 {
8549 }
8551 }
8552 }
8554 {
8557 {
8560 {
8562 {
8565 }
8567 }
8568 }
8569 }
8572 }
8575 }
8577 /* Return X converted to MODE. If the value is already truncated to
8578 MODE we can just return a subreg even though in the general case we
8579 would need an explicit truncation. */
8581 static rtx
8583 {
8588 {
8589 /* Bit-cast X into an integer mode. */
8594 }
8597 }
8599 /* See if X can be simplified knowing that we will only refer to it in
8600 MODE and will only refer to those bits that are nonzero in MASK.
8601 If other bits are being computed or if masking operations are done
8602 that select a superset of the bits in MASK, they can sometimes be
8603 ignored.
8605 Return a possibly simplified expression, but always convert X to
8606 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8608 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8609 are all off in X. This is used when X will be complemented, by either
8610 NOT, NEG, or XOR. */
8612 static rtx
8615 {
8618 machine_mode op_mode;
8621 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8622 code below will do the wrong thing since the mode of such an
8623 expression is VOIDmode.
8625 Also do nothing if X is a CLOBBER; this can happen if X was
8626 the return value from a call to gen_lowpart. */
8630 /* We want to perform the operation in its present mode unless we know
8631 that the operation is valid in MODE, in which case we do the operation
8632 in MODE. */
8637 /* It is not valid to do a right-shift in a narrower mode
8638 than the one it came in with. */
8643 /* Truncate MASK to fit OP_MODE. */
8647 /* Determine what bits of X are guaranteed to be (non)zero. */
8650 /* If none of the bits in X are needed, return a zero. */
8654 /* If X is a CONST_INT, return a new one. Do this here since the
8655 test below will fail. */
8657 {
8660 else
8661 {
8664 }
8665 }
8667 /* If X is narrower than MODE and we want all the bits in X's mode, just
8668 get X in the proper mode. */
8673 /* We can ignore the effect of a SUBREG if it narrows the mode or
8674 if the constant masks to zero all the bits the mode doesn't have. */
8678 || (mask
8686 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8687 integer too. */
8693 }
8695 /* Subroutine of force_to_mode that handles cases in which both X and
8696 the result are scalar integers. MODE is the mode of the result,
8697 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8698 is preferred for simplified versions of X. The other arguments
8699 are as for force_to_mode. */
8701 static rtx
8705 {
8710 poly_int64 const_op0;
8712 /* When we have an arithmetic operation, or a shift whose count we
8713 do not know, we need to assume that all bits up to the highest-order
8714 bit in MASK will be needed. This is how we form such a mask. */
8717 else
8722 {
8724 /* If X is a (clobber (const_int)), return it since we know we are
8725 generating something that won't match. */
8738 /* Similarly for a truncate. */
8742 /* If this is an AND with a constant, convert it into an AND
8743 whose constant is the AND of that constant with MASK. If it
8744 remains an AND of MASK, delete it since it is redundant. */
8747 {
8752 /* If X is still an AND, see if it is an AND with a mask that
8753 is just some low-order bits. If so, and it is MASK, we don't
8754 need it. */
8760 /* If it remains an AND, try making another AND with the bits
8761 in the mode mask that aren't in MASK turned on. If the
8762 constant in the AND is wide enough, this might make a
8763 cheaper constant. */
8768 {
8769 unsigned HOST_WIDE_INT cval
8771 rtx y;
8778 }
8781 }
8786 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8787 low-order bits (as in an alignment operation) and FOO is already
8788 aligned to that boundary, mask C1 to that boundary as well.
8789 This may eliminate that PLUS and, later, the AND. */
8791 {
8795 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8796 number, sign extend it. */
8809 }
8811 /* fall through */
8814 /* Substituting into the operands of a widening MULT is not likely to
8815 create RTL matching a machine insn. */
8825 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8826 most significant bit in MASK since carries from those bits will
8827 affect the bits we are interested in. */
8832 /* If X is (minus C Y) where C's least set bit is larger than any bit
8833 in the mask, then we may replace with (neg Y). */
8836 {
8839 }
8841 /* Similarly, if C contains every bit in the fuller_mask, then we may
8842 replace with (not Y). */
8845 {
8848 }
8855 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8856 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8857 operation which may be a bitfield extraction. Ensure that the
8858 constant we form is not wider than the mode of X. */
8870 {
8873 xmode);
8879 }
8881 binop:
8882 /* For most binary operations, just propagate into the operation and
8883 change the mode if we have an operation of that mode. */
8888 /* If we ended up truncating both operands, truncate the result of the
8889 operation instead. */
8892 {
8895 }
8901 {
8904 }
8908 /* For left shifts, do the same, but just for the first operand.
8909 However, we cannot do anything with shifts where we cannot
8910 guarantee that the counts are smaller than the size of the mode
8911 because such a count will have a different meaning in a
8912 wider mode. */
8922 /* If the shift count is a constant and we can do arithmetic in
8923 the mode of the shift, refine which bits we need. Otherwise, use the
8924 conservative form of the mask. */
8930 else
8938 {
8941 }
8945 /* Here we can only do something if the shift count is a constant,
8946 this shift constant is valid for the host, and we can do arithmetic
8947 in OP_MODE. */
8953 {
8957 /* Select the mask of the bits we need for the shift operand. */
8960 /* We can only change the mode of the shift if we can do arithmetic
8961 in the mode of the shift and INNER_MASK is no wider than the
8962 width of X's mode. */
8969 {
8972 }
8973 }
8975 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8976 shift and AND produces only copies of the sign bit (C2 is one less
8977 than a power of two), we can do this with just a shift. */
8981 /* The shift puts one of the sign bit copies in the least significant
8982 bit. */
8987 /* Number of bits left after the shift must be more than the mask
8988 needs. */
8991 /* Must be more sign bit copies than the mask needs. */
8994 {
8998 }
9002 /* If we are just looking for the sign bit, we don't need this shift at
9003 all, even if it has a variable count. */
9007 /* If this is a shift by a constant, get a mask that contains those bits
9008 that are not copies of the sign bit. We then have two cases: If
9009 MASK only includes those bits, this can be a logical shift, which may
9010 allow simplifications. If MASK is a single-bit field not within
9011 those bits, we are requesting a copy of the sign bit and hence can
9012 shift the sign bit to the appropriate location. */
9016 {
9020 /* If the considered data is wider than HOST_WIDE_INT, we can't
9021 represent a mask for all its bits in a single scalar.
9022 But we only care about the lower bits, so calculate these. */
9025 {
9028 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9029 is the number of bits a full-width mask would have set.
9030 We need only shift if these are fewer than nonzero can
9031 hold. If not, we must keep all bits set in nonzero. */
9036 + HOST_BITS_PER_WIDE_INT
9038 }
9039 else
9040 {
9043 }
9046 {
9051 }
9054 {
9055 x = simplify_shift_const
9061 }
9062 }
9064 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9065 even if the shift count isn't a constant. */
9069 shiftrt:
9071 /* If this is a zero- or sign-extension operation that just affects bits
9072 we don't care about, remove it. Be sure the call above returned
9073 something that is still a shift. */
9083 next_select);
9089 /* If the shift count is constant and we can do computations
9090 in the mode of X, compute where the bits we care about are.
9091 Otherwise, we can't do anything. Don't change the mode of
9092 the shift or propagate MODE into the shift, though. */
9095 {
9104 }
9108 /* If we just want the low-order bit, the NEG isn't needed since it
9109 won't change the low-order bit. */
9113 /* We need any bits less significant than the most significant bit in
9114 MASK since carries from those bits will affect the bits we are
9115 interested in. */
9120 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9121 same as the XOR case above. Ensure that the constant we form is not
9122 wider than the mode of X. */
9130 {
9137 }
9139 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9140 use the full mask inside the NOT. */
9143 unop:
9146 next_select));
9148 {
9151 }
9155 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9156 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9157 which is equal to STORE_FLAG_VALUE. */
9169 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9170 written in a narrower mode. We play it safe and do not do so. */
9186 }
9188 /* Ensure we return a value of the proper mode. */
9190 }
9191 \f
9192 /* Return nonzero if X is an expression that has one of two values depending on
9193 whether some other value is zero or nonzero. In that case, we return the
9194 value that is being tested, *PTRUE is set to the value if the rtx being
9195 returned has a nonzero value, and *PFALSE is set to the other alternative.
9197 If we return zero, we set *PTRUE and *PFALSE to X. */
9199 static rtx
9201 {
9206 scalar_int_mode int_mode;
9208 /* If we are comparing a value against zero, we are done. */
9211 {
9215 }
9217 /* If this is a unary operation whose operand has one of two values, apply
9218 our opcode to compute those values. */
9221 {
9226 }
9228 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9229 make can't possibly match and would suppress other optimizations. */
9231 ;
9233 /* If this is a binary operation, see if either side has only one of two
9234 values. If either one does or if both do and they are conditional on
9235 the same value, compute the new true and false values. */
9237 {
9245 {
9246 /* Try to enable a simplification by undoing work done by
9247 if_then_else_cond if it converted a REG into something more
9248 complex. */
9250 {
9253 }
9254 else
9255 {
9258 }
9259 }
9263 {
9264 /* If if_then_else_cond returned zero, then true/false are the
9265 same rtl. We must copy one of them to prevent invalid rtl
9266 sharing. */
9273 {
9278 }
9279 else
9280 {
9283 }
9286 }
9288 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9289 operands is zero when the other is nonzero, and vice-versa,
9290 and STORE_FLAG_VALUE is 1 or -1. */
9296 {
9314 {
9321 const_true_rtx);
9323 }
9324 }
9326 /* Similarly for MULT, AND and UMIN, except that for these the result
9327 is always zero. */
9331 {
9345 {
9348 }
9349 }
9350 }
9353 {
9354 /* If we have IF_THEN_ELSE already, extract the condition and
9355 canonicalize it if it is NE or EQ. */
9361 {
9364 }
9365 else
9367 }
9369 /* If X is a SUBREG, we can narrow both the true and false values
9370 if the inner expression, if there is a condition. */
9374 {
9380 {
9384 }
9385 }
9387 /* If X is a constant, this isn't special and will cause confusions
9388 if we treat it as such. Likewise if it is equivalent to a constant. */
9391 ;
9393 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9394 will be least confusing to the rest of the compiler. */
9396 {
9399 }
9401 /* If X is known to be either 0 or -1, those are the true and
9402 false values when testing X. */
9407 {
9410 }
9412 /* Likewise for 0 or a single bit. */
9415 {
9418 }
9420 /* Otherwise fail; show no condition with true and false values the same. */
9423 }
9424 \f
9425 /* Return the value of expression X given the fact that condition COND
9426 is known to be true when applied to REG as its first operand and VAL
9427 as its second. X is known to not be shared and so can be modified in
9428 place.
9430 We only handle the simplest cases, and specifically those cases that
9431 arise with IF_THEN_ELSE expressions. */
9433 static rtx
9435 {
9443 /* If either operand of the condition is a floating point value,
9444 then we have to avoid collapsing an EQ comparison. */
9454 /* If X is (abs REG) and we know something about REG's relationship
9455 with zero, we may be able to simplify this. */
9459 {
9468 }
9470 /* The only other cases we handle are MIN, MAX, and comparisons if the
9471 operands are the same as REG and VAL. */
9474 {
9476 {
9479 }
9482 {
9484 {
9492 else
9494 }
9497 {
9500 /* Do not reverse the condition when it is NE or EQ.
9501 This is because we cannot conclude anything about
9502 the value of 'SMAX (x, y)' when x is not equal to y,
9503 but we can when x equals y. */
9509 {
9520 }
9521 }
9522 }
9523 }
9525 {
9530 {
9531 /* We must simplify subreg here, before we lose track of the
9532 original inner_mode. */
9537 else
9539 }
9542 }
9543 /* We don't have to handle SIGN_EXTEND here, because even in the
9544 case of replacing something with a modeless CONST_INT, a
9545 CONST_INT is already (supposed to be) a valid sign extension for
9546 its narrower mode, which implies it's already properly
9547 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9548 story is different. */
9550 {
9555 {
9556 /* We must simplify the zero_extend here, before we lose
9557 track of the original inner_mode. */
9562 else
9564 }
9567 }
9571 {
9578 }
9581 }
9582 \f
9583 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9584 assignment as a field assignment. */
9586 static int
9588 {
9590 {
9598 }
9606 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9607 Note that all SUBREGs of MEM are paradoxical; otherwise they
9608 would have been rewritten. */
9621 /* We used to see if get_last_value of X and Y were the same but that's
9622 not correct. In one direction, we'll cause the assignment to have
9623 the wrong destination and in the case, we'll import a register into this
9624 insn that might have already have been dead. So fail if none of the
9625 above cases are true. */
9627 }
9628 \f
9629 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9630 Return that assignment if so.
9632 We only handle the most common cases. */
9634 static rtx
9636 {
9639 rtx assign;
9641 HOST_WIDE_INT c1;
9642 HOST_WIDE_INT pos;
9644 rtx other;
9646 /* All the rules in this function are specific to scalar integers. */
9647 scalar_int_mode mode;
9651 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9652 a clear of a one-bit field. We will have changed it to
9653 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9654 for a SUBREG. */
9660 {
9666 }
9675 {
9682 }
9684 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9685 one-bit field. */
9689 {
9695 }
9697 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9698 SRC is an AND with all bits of that field set, then we can discard
9699 the AND. */
9704 {
9711 else
9714 /* Complete overlap. We can remove the source AND. */
9718 /* Partial overlap. We can reduce the source AND. */
9720 {
9724 }
9725 }
9727 /* The other case we handle is assignments into a constant-position
9728 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9729 a mask that has all one bits except for a group of zero bits and
9730 OTHER is known to have zeros where C1 has ones, this is such an
9731 assignment. Compute the position and length from C1. Shift OTHER
9732 to the appropriate position, force it to the required mode, and
9733 make the extraction. Check for the AND in both operands. */
9735 /* One or more SUBREGs might obscure the constant-position field
9736 assignment. The first one we are likely to encounter is an outer
9737 narrowing SUBREG, which we can just strip for the purposes of
9738 identifying the constant-field assignment. */
9755 /* The second SUBREG that might get in the way is a paradoxical
9756 SUBREG around the first operand of the AND. We want to
9757 pretend the operand is as wide as the destination here. We
9758 do this by adjusting the MEM to wider mode for the sole
9759 purpose of the call to rtx_equal_for_field_assignment_p. Also
9760 note this trick only works for MEMs. */
9772 /* The second SUBREG that might get in the way is a paradoxical
9773 SUBREG around the first operand of the AND. We want to
9774 pretend the operand is as wide as the destination here. We
9775 do this by adjusting the MEM to wider mode for the sole
9776 purpose of the call to rtx_equal_for_field_assignment_p. Also
9777 note this trick only works for MEMs. */
9785 else
9799 /* The mode to use for the source is the mode of the assignment, or of
9800 what is inside a possible STRICT_LOW_PART. */
9804 /* Shift OTHER right POS places and make it the source, restricting it
9805 to the proper length and mode. */
9809 dest);
9811 len >= HOST_BITS_PER_WIDE_INT
9812 ? HOST_WIDE_INT_M1U
9816 /* If SRC is masked by an AND that does not make a difference in
9817 the value being stored, strip it. */
9828 }
9829 \f
9830 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9831 if so. */
9833 static rtx
9835 {
9839 rtx tem;
9841 /* Distributivity is not true for floating point as it can change the
9842 value. So we don't do it unless -funsafe-math-optimizations. */
9847 /* The outer operation can only be one of the following: */
9855 /* If either operand is a primitive we can't do anything, so get out
9856 fast. */
9866 /* See if the inner and outer operations distribute. */
9868 {
9873 /* These all distribute except over PLUS. */
9884 /* This is also a multiply, so it distributes over everything. */
9887 /* This used to handle SUBREG, but this turned out to be counter-
9888 productive, since (subreg (op ...)) usually is not handled by
9889 insn patterns, and this "optimization" therefore transformed
9890 recognizable patterns into unrecognizable ones. Therefore the
9891 SUBREG case was removed from here.
9893 It is possible that distributing SUBREG over arithmetic operations
9894 leads to an intermediate result than can then be optimized further,
9895 e.g. by moving the outer SUBREG to the other side of a SET as done
9896 in simplify_set. This seems to have been the original intent of
9897 handling SUBREGs here.
9899 However, with current GCC this does not appear to actually happen,
9900 at least on major platforms. If some case is found where removing
9901 the SUBREG case here prevents follow-on optimizations, distributing
9902 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9906 }
9908 /* Set LHS and RHS to the inner operands (A and B in the example
9909 above) and set OTHER to the common operand (C in the example).
9910 There is only one way to do this unless the inner operation is
9911 commutative. */
9923 else
9926 /* Form the new inner operation, seeing if it simplifies first. */
9929 /* There is one exception to the general way of distributing:
9930 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9932 {
9935 }
9937 /* We may be able to continuing distributing the result, so call
9938 ourselves recursively on the inner operation before forming the
9939 outer operation, which we return. */
9942 }
9944 /* See if X is of the form (* (+ A B) C), and if so convert to
9945 (+ (* A C) (* B C)) and try to simplify.
9947 Most of the time, this results in no change. However, if some of
9948 the operands are the same or inverses of each other, simplifications
9949 will result.
9951 For example, (and (ior A B) (not B)) can occur as the result of
9952 expanding a bit field assignment. When we apply the distributive
9953 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9954 which then simplifies to (and (A (not B))).
9956 Note that no checks happen on the validity of applying the inverse
9957 distributive law. This is pointless since we can do it in the
9958 few places where this routine is called.
9960 N is the index of the term that is decomposed (the arithmetic operation,
9961 i.e. (+ A B) in the first example above). !N is the index of the term that
9962 is distributed, i.e. of C in the first example above. */
9963 static rtx
9965 {
9966 machine_mode mode;
9970 /* Distributivity is not true for floating point as it can change the
9971 value. So we don't do it unless -funsafe-math-optimizations. */
9988 /* Special case (and (xor B C) (not A)), which is equivalent to
9989 (xor (ior A B) (ior A C)) */
9991 {
9994 }
9997 {
9998 /* Distribute the second term. */
10001 }
10002 else
10003 {
10004 /* Distribute the first term. */
10007 }
10017 }
10018 \f
10019 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10020 in MODE. Return an equivalent form, if different from (and VAROP
10021 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10023 static rtx
10026 {
10029 rtx orig_varop;
10037 /* Simplify VAROP knowing that we will be only looking at some of the
10038 bits in it.
10040 Note by passing in CONSTOP, we guarantee that the bits not set in
10041 CONSTOP are not significant and will never be examined. We must
10042 ensure that is the case by explicitly masking out those bits
10043 before returning. */
10046 /* If VAROP is a CLOBBER, we will fail so return it. */
10050 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10051 to VAROP and return the new constant. */
10055 /* See what bits may be nonzero in VAROP. Unlike the general case of
10056 a call to nonzero_bits, here we don't care about bits outside
10057 MODE. */
10061 /* Turn off all bits in the constant that are known to already be zero.
10062 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10063 which is tested below. */
10067 /* If we don't have any bits left, return zero. */
10071 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10072 a power of two, we can replace this with an ASHIFT. */
10077 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10078 or XOR, then try to apply the distributive law. This may eliminate
10079 operations if either branch can be simplified because of the AND.
10080 It may also make some cases more complex, but those cases probably
10081 won't match a pattern either with or without this. */
10084 {
10086 return
10087 gen_lowpart
10089 apply_distributive_law
10093 constop),
10096 constop))));
10097 }
10099 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10100 the AND and see if one of the operands simplifies to zero. If so, we
10101 may eliminate it. */
10105 {
10114 }
10116 /* Make a SUBREG if necessary. If we can't make it, fail. */
10121 /* If we are only masking insignificant bits, return VAROP. */
10128 /* Otherwise, return an AND. */
10130 }
10133 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10134 in MODE.
10136 Return an equivalent form, if different from X. Otherwise, return X. If
10137 X is zero, we are to always construct the equivalent form. */
10139 static rtx
10142 {
10153 }
10154 \f
10155 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10156 We don't care about bits outside of those defined in MODE.
10157 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10159 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10160 a shift, AND, or zero_extract, we can do better. */
10162 static rtx
10164 scalar_int_mode mode,
10166 {
10167 rtx tem;
10170 /* If X is a register whose nonzero bits value is current, use it.
10171 Otherwise, if X is a register whose value we can find, use that
10172 value. Otherwise, use the previously-computed global nonzero bits
10173 for this register. */
10188 && !REGNO_REG_SET_P
10191 {
10192 /* Note that, even if the precision of last_set_mode is lower than that
10193 of mode, record_value_for_reg invoked nonzero_bits on the register
10194 with nonzero_bits_mode (because last_set_mode is necessarily integral
10195 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10196 are all valid, hence in mode too since nonzero_bits_mode is defined
10197 to the largest HWI_COMPUTABLE_MODE_P mode. */
10200 }
10204 {
10209 }
10212 {
10216 /* We don't know anything about the upper bits. */
10220 }
10223 }
10225 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10226 end of X that are known to be equal to the sign bit. X will be used
10227 in mode MODE; the returned value will always be between 1 and the
10228 number of bits in MODE. */
10230 static rtx
10232 scalar_int_mode mode,
10234 {
10235 rtx tem;
10248 && !REGNO_REG_SET_P
10251 {
10254 }
10265 }
10266 \f
10267 /* Return the number of "extended" bits there are in X, when interpreted
10268 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10269 unsigned quantities, this is the number of high-order zero bits.
10270 For signed quantities, this is the number of copies of the sign bit
10271 minus 1. In both case, this function returns the number of "spare"
10272 bits. For example, if two quantities for which this function returns
10273 at least 1 are added, the addition is known not to overflow.
10275 This function will always return 0 unless called during combine, which
10276 implies that it must be called from a define_split. */
10278 unsigned int
10280 {
10284 scalar_int_mode int_mode;
10292 }
10294 /* This function is called from `simplify_shift_const' to merge two
10295 outer operations. Specifically, we have already found that we need
10296 to perform operation *POP0 with constant *PCONST0 at the outermost
10297 position. We would now like to also perform OP1 with constant CONST1
10298 (with *POP0 being done last).
10300 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10301 the resulting operation. *PCOMP_P is set to 1 if we would need to
10302 complement the innermost operand, otherwise it is unchanged.
10304 MODE is the mode in which the operation will be done. No bits outside
10305 the width of this mode matter. It is assumed that the width of this mode
10306 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10308 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10309 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10310 result is simply *PCONST0.
10312 If the resulting operation cannot be expressed as one operation, we
10313 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10315 static int
10316 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10317 {
10324 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10328 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10329 if OP0 is SET. */
10338 {
10340 {
10358 }
10359 }
10361 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10365 /* If the two constants aren't the same, we can't do anything. The
10366 remaining six cases can all be done. */
10370 else
10372 {
10375 /* (a & b) | b == b */
10378 /* (a ^ b) | b == a | b */
10379 {;}
10384 /* (a & b) ^ b == (~a) & b */
10387 /* (a | b) ^ b == a & ~b */
10393 /* (a | b) & b == b */
10396 /* (a ^ b) & b) == (~a) & b */
10401 }
10403 /* Check for NO-OP cases. */
10416 /* ??? Slightly redundant with the above mask, but not entirely.
10417 Moving this above means we'd have to sign-extend the mode mask
10418 for the final test. */
10423 }
10424 \f
10425 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10426 the shift in. The original shift operation CODE is performed on OP in
10427 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10428 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10429 result of the shift is subject to operation OUTER_CODE with operand
10430 OUTER_CONST. */
10432 static scalar_int_mode
10436 {
10439 /* In general we can't perform in wider mode for right shift and rotate. */
10441 {
10443 /* We can still widen if the bits brought in from the left are identical
10444 to the sign bit of ORIG_MODE. */
10452 /* Similarly here but with zero bits. */
10457 /* We can also widen if the bits brought in will be masked off. This
10458 operation is performed in ORIG_MODE. */
10460 {
10466 }
10467 /* fall through */
10477 }
10478 }
10480 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10481 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10482 if we cannot simplify it. Otherwise, return a simplified value.
10484 The shift is normally computed in the widest mode we find in VAROP, as
10485 long as it isn't a different number of words than RESULT_MODE. Exceptions
10486 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10488 static rtx
10491 {
10496 machine_mode shift_mode;
10498 /* We form (outer_op (code varop count) (outer_const)). */
10504 /* Make sure and truncate the "natural" shift on the way in. We don't
10505 want to do this inside the loop as it makes it more difficult to
10506 combine shifts. */
10510 /* If we were given an invalid count, don't do anything except exactly
10511 what was requested. */
10518 /* Unless one of the branches of the `if' in this loop does a `continue',
10519 we will `break' the loop after the `if'. */
10522 {
10523 /* If we have an operand of (clobber (const_int 0)), fail. */
10527 /* Convert ROTATERT to ROTATE. */
10529 {
10533 }
10537 {
10538 /* We only change the modes of scalar shifts. */
10544 }
10546 scalar_int_mode shift_unit_mode
10549 /* Handle cases where the count is greater than the size of the mode
10550 minus 1. For ASHIFT, use the size minus one as the count (this can
10551 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10552 take the count modulo the size. For other shifts, the result is
10553 zero.
10555 Since these shifts are being produced by the compiler by combining
10556 multiple operations, each of which are defined, we know what the
10557 result is supposed to be. */
10560 {
10565 else
10566 {
10567 /* We can't simply return zero because there may be an
10568 outer op. */
10572 }
10573 }
10575 /* If we discovered we had to complement VAROP, leave. Making a NOT
10576 here would cause an infinite loop. */
10581 {
10582 /* An arithmetic right shift of a quantity known to be -1 or 0
10583 is a no-op. */
10587 {
10590 }
10592 /* If we are doing an arithmetic right shift and discarding all but
10593 the sign bit copies, this is equivalent to doing a shift by the
10594 bitsize minus one. Convert it into that shift because it will
10595 often allow other simplifications. */
10602 /* We simplify the tests below and elsewhere by converting
10603 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10604 `make_compound_operation' will convert it to an ASHIFTRT for
10605 those machines (such as VAX) that don't have an LSHIFTRT. */
10610 shift_unit_mode)))
10622 }
10625 {
10632 {
10635 }
10639 /* The following rules apply only to scalars. */
10644 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10645 minus the width of a smaller mode, we can do this with a
10646 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10653 {
10662 }
10666 /* The following rules apply only to scalars. */
10672 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10673 the same number of words as what we've seen so far. Then store
10674 the widest mode in MODE. */
10681 {
10686 }
10690 /* Some machines use MULT instead of ASHIFT because MULT
10691 is cheaper. But it is still better on those machines to
10692 merge two shifts into one. */
10695 {
10700 }
10704 /* Similar, for when divides are cheaper. */
10707 {
10712 }
10716 /* If we are extracting just the sign bit of an arithmetic
10717 right shift, that shift is not needed. However, the sign
10718 bit of a wider mode may be different from what would be
10719 interpreted as the sign bit in a narrower mode, so, if
10720 the result is narrower, don't discard the shift. */
10725 {
10728 }
10730 /* fall through */
10735 /* The following rules apply only to scalars. */
10742 /* Here we have two nested shifts. The result is usually the
10743 AND of a new shift with a mask. We compute the result below. */
10749 {
10753 rtx mask_rtx;
10755 /* We have one common special case. We can't do any merging if
10756 the inner code is an ASHIFTRT of a smaller mode. However, if
10757 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10758 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10759 we can convert it to
10760 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10761 This simplifies certain SIGN_EXTEND operations. */
10765 {
10766 /* C3 has the low-order C1 bits zero. */
10778 }
10780 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10781 than C1 high-order bits equal to the sign bit, we can convert
10782 this to either an ASHIFT or an ASHIFTRT depending on the
10783 two counts.
10785 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10791 {
10795 {
10798 }
10801 }
10803 /* There are some cases we can't do. If CODE is ASHIFTRT,
10804 we can only do this if FIRST_CODE is also ASHIFTRT.
10806 We can't do the case when CODE is ROTATE and FIRST_CODE is
10807 ASHIFTRT.
10809 If the mode of this shift is not the mode of the outer shift,
10810 we can't do this if either shift is a right shift or ROTATE.
10812 Finally, we can't do any of these if the mode is too wide
10813 unless the codes are the same.
10815 Handle the case where the shift codes are the same
10816 first. */
10819 {
10828 }
10839 /* To compute the mask to apply after the shift, shift the
10840 nonzero bits of the inner shift the same way the
10841 outer shift will. */
10844 int_result_mode);
10846 mask_rtx
10850 /* Give up if we can't compute an outer operation to use. */
10858 /* If the shifts are in the same direction, we add the
10859 counts. Otherwise, we subtract them. */
10863 else
10866 /* If COUNT is positive, the new shift is usually CODE,
10867 except for the two exceptions below, in which case it is
10868 FIRST_CODE. If the count is negative, FIRST_CODE should
10869 always be used */
10879 }
10881 /* If we have (A << B << C) for any shift, we can convert this to
10882 (A << C << B). This wins if A is a constant. Only try this if
10883 B is not a constant. */
10888 {
10889 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10890 sure the result will be masked. See PR70222. */
10898 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10899 up outer sign extension (often left and right shift) is
10900 hardly more efficient than the original. See PR70429.
10901 Similarly punt for rotates with different modes.
10902 See PR97386. */
10910 count_rtx);
10914 }
10918 /* The following rules apply only to scalars. */
10922 /* Make this fit the case below. */
10929 /* The following rules apply only to scalars. */
10935 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10936 with C the size of VAROP - 1 and the shift is logical if
10937 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10938 we have an (le X 0) operation. If we have an arithmetic shift
10939 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10940 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10948 {
10951 const0_rtx);
10957 }
10959 /* If we have (shift (logical)), move the logical to the outside
10960 to allow it to possibly combine with another logical and the
10961 shift to combine with another shift. This also canonicalizes to
10962 what a ZERO_EXTRACT looks like. Also, some machines have
10963 (and (shift)) insns. */
10966 /* We can't do this if we have (ashiftrt (xor)) and the
10967 constant has its sign bit set in shift_unit_mode with
10968 shift_unit_mode wider than result_mode. */
10981 {
10984 }
10986 /* If we can't do that, try to simplify the shift in each arm of the
10987 logical expression, make a new logical expression, and apply
10988 the inverse distributive law. This also can't be done for
10989 (ashiftrt (xor)) where we've widened the shift and the constant
10990 changes the sign bit. */
10996 {
11008 }
11012 /* The following rules apply only to scalars. */
11017 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11018 says that the sign bit can be tested, FOO has mode MODE, C is
11019 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11020 that may be nonzero. */
11030 {
11034 }
11038 /* The following rules apply only to scalars. */
11043 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11044 than the number of bits in the mode is equivalent to A. */
11048 {
11052 }
11054 /* NEG commutes with ASHIFT since it is multiplication. Move the
11055 NEG outside to allow shifts to combine. */
11059 {
11062 }
11066 /* The following rules apply only to scalars. */
11071 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11072 is one less than the number of bits in the mode is
11073 equivalent to (xor A 1). */
11080 {
11084 }
11086 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11087 that might be nonzero in BAR are those being shifted out and those
11088 bits are known zero in FOO, we can replace the PLUS with FOO.
11089 Similarly in the other operand order. This code occurs when
11090 we are computing the size of a variable-size array. */
11097 {
11100 }
11108 {
11111 }
11113 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11124 {
11127 }
11129 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11130 signbit', and attempt to change the PLUS to an XOR and move it to
11131 the outer operation as is done above in the AND/IOR/XOR case
11132 leg for shift(logical). See details in logical handling above
11133 for reasoning in doing so. */
11145 {
11148 }
11153 /* The following rules apply only to scalars. */
11158 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11159 with C the size of VAROP - 1 and the shift is logical if
11160 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11161 we have a (gt X 0) operation. If the shift is arithmetic with
11162 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11163 we have a (neg (gt X 0)) operation. */
11172 {
11175 const0_rtx);
11181 }
11185 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11186 if the truncate does not affect the value. */
11193 {
11197 new_count);
11200 new_count_rtx);
11204 }
11209 }
11212 }
11216 {
11217 /* We only change the modes of scalar shifts. */
11222 }
11224 /* We have now finished analyzing the shift. The result should be
11225 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11226 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11227 to the result of the shift. OUTER_CONST is the relevant constant,
11228 but we must turn off all bits turned off in the shift. */
11236 /* Make a SUBREG if necessary. If we can't make it, fail. */
11241 /* If we have an outer operation and we just made a shift, it is
11242 possible that we could have simplified the shift were it not
11243 for the outer operation. So try to do the simplification
11244 recursively. */
11248 else
11255 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11256 turn off all the bits that the shift would have turned off. */
11258 /* We only change the modes of scalar shifts. */
11262 /* Do the remainder of the processing in RESULT_MODE. */
11265 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11266 operation. */
11271 {
11281 {
11282 /* This means that we have determined that the result is
11283 equivalent to a constant. This should be rare. */
11286 }
11289 else
11292 }
11295 }
11297 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11298 The result of the shift is RESULT_MODE. If we cannot simplify it,
11299 return X or, if it is NULL, synthesize the expression with
11300 simplify_gen_binary. Otherwise, return a simplified value.
11302 The shift is normally computed in the widest mode we find in VAROP, as
11303 long as it isn't a different number of words than RESULT_MODE. Exceptions
11304 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11306 static rtx
11309 {
11320 }
11322 \f
11323 /* A subroutine of recog_for_combine. See there for arguments and
11324 return value. */
11326 static int
11328 {
11330 rtx pat_without_clobbers;
11338 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11339 we use to indicate that something didn't match. If we find such a
11340 thing, force rejection. */
11354 {
11357 else
11360 }
11362 /* If it isn't, there is the possibility that we previously had an insn
11363 that clobbered some register as a side effect, but the combined
11364 insn doesn't need to do that. So try once more without the clobbers
11365 unless this represents an ASM insn. */
11369 {
11374 {
11377 pos++;
11378 }
11388 {
11391 else
11394 }
11395 }
11402 /* Recognize all noop sets, these will be killed by followup pass. */
11406 /* If we had any clobbers to add, make a new pattern than contains
11407 them. Then check to make sure that all of them are dead. */
11409 {
11419 else
11426 {
11431 {
11435 }
11436 }
11438 }
11442 {
11450 /* Allow targets to reject combined insn. */
11452 {
11455 dump_file);
11457 /* Callers expect recog_for_combine to strip
11458 clobbers from the pattern on failure. */
11463 }
11468 }
11474 }
11476 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11477 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11478 Return whether anything was so changed. */
11480 static bool
11482 {
11488 {
11500 {
11510 else
11514 {
11520 }
11521 }
11527 {
11532 {
11538 }
11539 }
11544 {
11548 }
11549 else
11555 {
11558 }
11562 }
11569 scalar_int_mode mode;
11575 {
11589 else
11597 }
11600 }
11602 /* Like recog, but we receive the address of a pointer to a new pattern.
11603 We try to match the rtx that the pointer points to.
11604 If that fails, we may try to modify or replace the pattern,
11605 storing the replacement into the same pointer object.
11607 Modifications include deletion or addition of CLOBBERs. If the
11608 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11609 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11610 (and undo if that fails).
11612 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11613 the CLOBBERs are placed.
11615 The value is the final insn code from the pattern ultimately matched,
11616 or -1. */
11618 static int
11620 {
11630 {
11631 /* For an unrecognized single set of a constant, try placing it in
11632 the constant pool, if this function already uses one. */
11637 {
11643 {
11646 }
11647 }
11648 else
11650 }
11652 {
11655 {
11659 }
11660 }
11663 {
11668 }
11671 }
11672 \f
11673 /* Like gen_lowpart_general but for use by combine. In combine it
11674 is not possible to create any new pseudoregs. However, it is
11675 safe to create invalid memory addresses, because combine will
11676 try to recognize them and all they will do is make the combine
11677 attempt fail.
11679 If for some reason this cannot do its job, an rtx
11680 (clobber (const_int 0)) is returned.
11681 An insn containing that will not be recognized. */
11683 static rtx
11685 {
11687 rtx result;
11692 /* We can only support MODE being wider than a word if X is a
11693 constant integer or has a mode the same size. */
11699 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11700 won't know what to do. So we will strip off the SUBREG here and
11701 process normally. */
11703 {
11706 /* For use in case we fall down into the address adjustments
11707 further below, we need to adjust the known mode and size of
11708 x; imode and isize, since we just adjusted x. */
11713 }
11721 {
11722 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11723 address. */
11728 /* If we want to refer to something bigger than the original memref,
11729 generate a paradoxical subreg instead. That will force a reload
11730 of the original memref X. */
11736 }
11738 /* If X is a comparison operator, rewrite it in a new mode. This
11739 probably won't match, but may allow further simplifications. */
11745 /* If we couldn't simplify X any other way, just enclose it in a
11746 SUBREG. Normally, this SUBREG won't match, but some patterns may
11747 include an explicit SUBREG or we may simplify it further in combine. */
11748 else
11749 {
11750 rtx res;
11753 {
11758 }
11762 }
11764 fail:
11766 }
11767 \f
11768 /* Try to simplify a comparison between OP0 and a constant OP1,
11769 where CODE is the comparison code that will be tested, into a
11770 (CODE OP0 const0_rtx) form.
11772 The result is a possibly different comparison code to use.
11773 *POP1 may be updated. */
11775 static enum rtx_code
11778 {
11779 scalar_int_mode int_mode;
11782 /* Get the constant we are comparing against and turn off all bits
11783 not on in our mode. */
11787 /* If we are comparing against a constant power of two and the value
11788 being compared can only have that single bit nonzero (e.g., it was
11789 `and'ed with that bit), we can replace this with a comparison
11790 with zero. */
11799 {
11802 }
11804 /* Similarly, if we are comparing a value known to be either -1 or
11805 0 with -1, change it to the opposite comparison against zero. */
11811 {
11814 }
11816 /* Do some canonicalizations based on the comparison code. We prefer
11817 comparisons against zero and then prefer equality comparisons.
11818 If we can reduce the size of a constant, we will do that too. */
11820 {
11822 /* < C is equivalent to <= (C - 1) */
11824 {
11827 /* ... fall through to LE case below. */
11829 }
11830 else
11834 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11836 {
11839 }
11841 /* If we are doing a <= 0 comparison on a value known to have
11842 a zero sign bit, we can replace this with == 0. */
11853 /* >= C is equivalent to > (C - 1). */
11855 {
11858 /* ... fall through to GT below. */
11860 }
11861 else
11865 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11867 {
11870 }
11872 /* If we are doing a > 0 comparison on a value known to have
11873 a zero sign bit, we can replace this with != 0. */
11884 /* < C is equivalent to <= (C - 1). */
11886 {
11889 /* ... fall through ... */
11891 }
11892 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11897 {
11901 }
11902 else
11906 /* unsigned <= 0 is equivalent to == 0 */
11909 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11913 == ((HOST_WIDE_INT_1U
11915 {
11918 }
11922 /* >= C is equivalent to > (C - 1). */
11924 {
11927 /* ... fall through ... */
11929 }
11931 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11936 {
11940 }
11941 else
11945 /* unsigned > 0 is equivalent to != 0 */
11948 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11952 == (HOST_WIDE_INT_1U
11954 {
11957 }
11962 }
11966 }
11967 \f
11968 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11969 comparison code that will be tested.
11971 The result is a possibly different comparison code to use. *POP0 and
11972 *POP1 may be updated.
11974 It is possible that we might detect that a comparison is either always
11975 true or always false. However, we do not perform general constant
11976 folding in combine, so this knowledge isn't useful. Such tautologies
11977 should have been detected earlier. Hence we ignore all such cases. */
11979 static enum rtx_code
11981 {
11987 opt_scalar_int_mode tmode_iter;
11989 /* Try a few ways of applying the same transformation to both operands. */
11991 {
11992 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11993 so check specially. */
12012 {
12015 }
12017 /* If both operands are the same constant shift, see if we can ignore the
12018 shift. We can if the shift is a rotate or if the bits shifted out of
12019 this shift are known to be zero for both inputs and if the type of
12020 comparison is compatible with the shift. */
12033 {
12046 else
12048 }
12050 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12051 SUBREGs are of the same mode, and, in both cases, the AND would
12052 be redundant if the comparison was done in the narrower mode,
12053 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12054 and the operand's possibly nonzero bits are 0xffffff01; in that case
12055 if we only care about QImode, we don't need the AND). This case
12056 occurs if the output mode of an scc insn is not SImode and
12057 STORE_FLAG_VALUE == 1 (e.g., the 386).
12059 Similarly, check for a case where the AND's are ZERO_EXTEND
12060 operations from some narrower mode even though a SUBREG is not
12061 present. */
12066 {
12082 {
12086 /* The resulting comparison is always unsigned since we masked
12087 off the original sign bit. */
12091 }
12097 {
12103 }
12107 }
12109 /* If both operands are NOT, we can strip off the outer operation
12110 and adjust the comparison code for swapped operands; similarly for
12111 NEG, except that this must be an equality comparison. */
12117 else
12119 }
12121 /* If the first operand is a constant, swap the operands and adjust the
12122 comparison code appropriately, but don't do this if the second operand
12123 is already a constant integer. */
12125 {
12128 }
12130 /* We now enter a loop during which we will try to simplify the comparison.
12131 For the most part, we only are concerned with comparisons with zero,
12132 but some things may really be comparisons with zero but not start
12133 out looking that way. */
12136 {
12138 scalar_int_mode int_mode;
12142 HOST_WIDE_INT const_op;
12144 /* We only want to handle integral modes. This catches VOIDmode,
12145 CCmode, and the floating-point modes. An exception is that we
12146 can handle VOIDmode if OP0 is a COMPARE or a comparison
12147 operation. */
12154 /* Try to simplify the compare to constant, possibly changing the
12155 comparison op, and/or changing op1 to zero. */
12159 /* Compute some predicates to simplify code below. */
12166 /* If this is a sign bit comparison and we can do arithmetic in
12167 MODE, say that we will only be needing the sign bit of OP0. */
12172 HOST_WIDE_INT_1U
12177 {
12178 /* We can't do anything if OP0 is a condition code value, rather
12179 than an actual data value. */
12184 /* Get the two operands being compared. */
12187 else
12190 /* Check for the cases where we simply want the result of the
12191 earlier test or the opposite of that result. */
12195 {
12199 else
12203 {
12208 }
12209 }
12211 }
12217 /* Now try cases based on the opcode of OP0. If none of the cases
12218 does a "continue", we exit this loop immediately after the
12219 switch. */
12224 {
12226 /* If we are extracting a single bit from a variable position in
12227 a constant that has only a single bit set and are comparing it
12228 with zero, we can convert this into an equality comparison
12229 between the position and the location of the single bit. */
12230 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12231 have already reduced the shift count modulo the word size. */
12237 {
12245 /* Result is nonzero iff shift count is equal to I. */
12248 }
12250 /* fall through */
12255 {
12258 }
12262 /* If testing for equality, we can take the NOT of the constant. */
12265 {
12269 }
12271 /* If just looking at the sign bit, reverse the sense of the
12272 comparison. */
12274 {
12278 }
12282 /* If testing for equality, we can take the NEG of the constant. */
12285 {
12289 }
12291 /* The remaining cases only apply to comparisons with zero. */
12295 /* When X is ABS or is known positive,
12296 (neg X) is < 0 if and only if X != 0. */
12304 {
12308 }
12310 /* If we have NEG of something whose two high-order bits are the
12311 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12313 {
12317 }
12321 /* If we are testing equality and our count is a constant, we
12322 can perform the inverse operation on our RHS. */
12326 {
12330 }
12332 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12333 a particular bit. Convert it to an AND of a constant of that
12334 bit. This will be converted into a ZERO_EXTRACT. */
12339 {
12341 (HOST_WIDE_INT_1U
12346 }
12348 /* Fall through. */
12351 /* ABS is ignorable inside an equality comparison with zero. */
12353 {
12356 }
12360 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12361 (compare FOO CONST) if CONST fits in FOO's mode and we
12362 are either testing inequality or have an unsigned
12363 comparison with ZERO_EXTEND or a signed comparison with
12364 SIGN_EXTEND. But don't do it if we don't have a compare
12365 insn of the given mode, since we'd have to revert it
12366 later on, and then we wouldn't know whether to sign- or
12367 zero-extend. */
12369 && ! unsigned_comparison_p
12373 {
12376 }
12380 /* Check for the case where we are comparing A - C1 with C2, that is
12382 (subreg:MODE (plus (A) (-C1))) op (C2)
12384 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12385 comparison in the wider mode. One of the following two conditions
12386 must be true in order for this to be valid:
12388 1. The mode extension results in the same bit pattern being added
12389 on both sides and the comparison is equality or unsigned. As
12390 C2 has been truncated to fit in MODE, the pattern can only be
12391 all 0s or all 1s.
12393 2. The mode extension results in the sign bit being copied on
12394 each side.
12396 The difficulty here is that we have predicates for A but not for
12397 (A - C1) so we need to check that C1 is within proper bounds so
12398 as to perturbate A as little as possible. */
12407 {
12415 /* (A - C1) zero-extends if it is positive and sign-extends
12416 if it is negative, C2 both zero- and sign-extends. */
12420 /* (A - C1) sign-extends if it is positive and 1-extends
12421 if it is negative, C2 both sign- and 1-extends. */
12428 /* (A - C1) always sign-extends, like C2. */
12432 {
12435 }
12436 }
12438 /* If the inner mode is narrower and we are extracting the low part,
12439 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12441 ;
12450 {
12451 /* Remove outer subregs that don't do anything. */
12456 {
12460 }
12462 }
12463 else
12466 /* FALLTHROUGH */
12475 {
12478 }
12482 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12483 this for equality comparisons due to pathological cases involving
12484 overflows. */
12488 {
12492 }
12494 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12497 {
12501 }
12505 /* We used to optimize signed comparisons against zero, but that
12506 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12507 arrive here as equality comparisons, or (GEU, LTU) are
12508 optimized away. No need to special-case them. */
12510 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12511 (eq B (minus A C)), whichever simplifies. We can only do
12512 this for equality comparisons due to pathological cases involving
12513 overflows. */
12517 {
12521 }
12526 {
12530 }
12532 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12533 of bits in X minus 1, is one iff X > 0. */
12538 {
12542 }
12546 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12547 if C is zero or B is a constant. */
12551 {
12555 }
12560 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12561 iff X <= 0. */
12565 {
12569 }
12573 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12574 will be converted to a ZERO_EXTRACT later. */
12578 {
12583 }
12585 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12586 zero and X is a comparison and C1 and C2 describe only bits set
12587 in STORE_FLAG_VALUE, we can compare with X. */
12595 {
12602 {
12605 }
12606 }
12608 /* If we are doing an equality comparison of an AND of a bit equal
12609 to the sign bit, replace this with a LT or GE comparison of
12610 the underlying value. */
12617 {
12621 }
12623 /* If this AND operation is really a ZERO_EXTEND from a narrower
12624 mode, the constant fits within that mode, and this is either an
12625 equality or unsigned comparison, try to do this comparison in
12626 the narrower mode.
12628 Note that in:
12630 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12631 -> (ne:DI (reg:SI 4) (const_int 0))
12633 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12634 known to hold a value of the required mode the
12635 transformation is invalid. */
12643 {
12646 }
12648 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12649 fits in both M1 and M2 and the SUBREG is either paradoxical
12650 or represents the low part, permute the SUBREG and the AND
12651 and try again. */
12654 {
12656 /* Require an integral mode, to avoid creating something like
12657 (AND:SF ...). */
12660 /* It is unsafe to commute the AND into the SUBREG if the
12661 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12662 not defined. As originally written the upper bits
12663 have a defined value due to the AND operation.
12664 However, if we commute the AND inside the SUBREG then
12665 they no longer have defined values and the meaning of
12666 the code has been changed.
12667 Also C1 should not change value in the smaller mode,
12668 see PR67028 (a positive C1 can become negative in the
12669 smaller mode, so that the AND does no longer mask the
12670 upper bits). */
12671 && ((WORD_REGISTER_OPERATIONS
12683 {
12689 }
12690 }
12692 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12696 {
12701 }
12703 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12704 (eq (and (lshiftrt X) 1) 0).
12705 Also handle the case where (not X) is expressed using xor. */
12709 {
12719 == HOST_WIDE_INT_1U
12721 {
12722 op0
12727 }
12728 }
12732 /* If we have (compare (ashift FOO N) (const_int C)) and
12733 the high order N bits of FOO (N+1 if an inequality comparison)
12734 are known to be zero, we can do this by comparing FOO with C
12735 shifted right N bits so long as the low-order N bits of C are
12736 zero. */
12748 {
12749 /* We must perform a logical shift, not an arithmetic one,
12750 as we want the top N bits of C to be zero. */
12757 }
12759 /* If we are doing a sign bit comparison, it means we are testing
12760 a particular bit. Convert it to the appropriate AND. */
12763 {
12765 (HOST_WIDE_INT_1U
12770 }
12772 /* If this an equality comparison with zero and we are shifting
12773 the low bit to the sign bit, we can convert this to an AND of the
12774 low-order bit. */
12778 {
12781 }
12785 /* If this is an equality comparison with zero, we can do this
12786 as a logical shift, which might be much simpler. */
12789 {
12794 }
12796 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12797 do the comparison in a narrower mode. */
12807 {
12810 }
12812 /* Likewise if OP0 is a PLUS of a sign extension with a
12813 constant, which is usually represented with the PLUS
12814 between the shifts. */
12826 {
12834 new_const);
12836 }
12838 /* FALLTHROUGH */
12840 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12841 the low order N bits of FOO are known to be zero, we can do this
12842 by comparing FOO with C shifted left N bits so long as no
12843 overflow occurs. Even if the low order N bits of FOO aren't known
12844 to be zero, if the comparison is >= or < we can use the same
12845 optimization and for > or <= by setting all the low
12846 order N bits in the comparison constant. */
12857 {
12858 unsigned HOST_WIDE_INT low_bits
12860 & ((HOST_WIDE_INT_1U
12863 {
12864 /* If the shift was logical, then we must make the condition
12865 unsigned. */
12874 const_op
12879 }
12880 }
12882 /* If we are using this shift to extract just the sign bit, we
12883 can replace this with an LT or GE comparison. */
12888 {
12892 }
12897 }
12900 }
12902 /* Now make any compound operations involved in this comparison. Then,
12903 check for an outmost SUBREG on OP0 that is not doing anything or is
12904 paradoxical. The latter transformation must only be performed when
12905 it is known that the "extra" bits will be the same in op0 and op1 or
12906 that they don't matter. There are three cases to consider:
12908 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12909 care bits and we can assume they have any convenient value. So
12910 making the transformation is safe.
12912 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12913 In this case the upper bits of op0 are undefined. We should not make
12914 the simplification in that case as we do not know the contents of
12915 those bits.
12917 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12918 In that case we know those bits are zeros or ones. We must also be
12919 sure that they are the same as the upper bits of op1.
12921 We can never remove a SUBREG for a non-equality comparison because
12922 the sign bit is in a different place in the underlying object. */
12935 {
12937 {
12938 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12939 implemented. */
12941 {
12944 }
12945 }
12949 {
12954 }
12955 }
12957 /* We now do the opposite procedure: Some machines don't have compare
12958 insns in all modes. If OP0's mode is an integer mode smaller than a
12959 word and we can't do a compare in that mode, see if there is a larger
12960 mode for which we can do the compare. There are a number of cases in
12961 which we can use the wider mode. */
12967 {
12972 {
12975 /* If this is a test for negative, we can make an explicit
12976 test of the sign bit. Test this first so we can use
12977 a paradoxical subreg to extend OP0. */
12981 {
12982 unsigned HOST_WIDE_INT sign
12989 }
12991 /* If the only nonzero bits in OP0 and OP1 are those in the
12992 narrower mode and this is an equality or unsigned comparison,
12993 we can use the wider mode. Similarly for sign-extended
12994 values, in which case it is true for all comparisons. */
13011 {
13012 /* If OP0 is an AND and we don't have an AND in MODE either,
13013 make a new AND in the proper mode. */
13021 else
13022 {
13024 {
13029 }
13030 else
13031 {
13036 }
13038 }
13039 }
13040 }
13041 }
13043 /* We may have changed the comparison operands. Re-canonicalize. */
13045 {
13048 }
13050 /* If this machine only supports a subset of valid comparisons, see if we
13051 can convert an unsupported one into a supported one. */
13058 }
13059 \f
13060 /* Utility function for record_value_for_reg. Count number of
13061 rtxs in X. */
13062 static int
13064 {
13071 {
13091 }
13102 }
13103 \f
13104 /* Utility function for following routine. Called when X is part of a value
13105 being stored into last_set_value. Sets last_set_table_tick
13106 for each register mentioned. Similar to mention_regs in cse.cc */
13108 static void
13110 {
13116 {
13122 {
13125 }
13128 }
13132 {
13133 /* Check for identical subexpressions. If x contains
13134 identical subexpression we only have to traverse one of
13135 them. */
13137 {
13138 /* Note that at this point x1 has already been
13139 processed. */
13143 /* If x0 and x1 are identical then there is no need to
13144 process x0. */
13148 /* If x0 is identical to a subexpression of x1 then while
13149 processing x1, x0 has already been processed. Thus we
13150 are done with x. */
13155 /* If x1 is identical to a subexpression of x0 then we
13156 still have to process the rest of x0. */
13159 {
13162 }
13163 }
13166 }
13170 }
13172 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13173 are saying that the register is clobbered and we no longer know its
13174 value. If INSN is zero, don't update reg_stat[].last_set; this is
13175 only permitted with VALUE also zero and is used to invalidate the
13176 register. */
13178 static void
13180 {
13186 /* If VALUE contains REG and we have a previous value for REG, substitute
13187 the previous value. */
13189 {
13190 rtx tem;
13192 /* Set things up so get_last_value is allowed to see anything set up to
13193 our insn. */
13197 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13198 it isn't going to be useful and will take a lot of time to process,
13199 so just use the CLOBBER. */
13202 {
13208 {
13209 /* If there are two or more occurrences of REG in VALUE,
13210 prevent the value from growing too much. */
13213 }
13216 }
13217 }
13219 /* For each register modified, show we don't know its value, that
13220 we don't know about its bitwise content, that its value has been
13221 updated, and that we don't know the location of the death of the
13222 register. */
13224 {
13236 }
13238 /* Mark registers that are being referenced in this value. */
13242 /* Now update the status of each register being set.
13243 If someone is using this register in this block, set this register
13244 to invalid since we will get confused between the two lives in this
13245 basic block. This makes using this register always invalid. In cse, we
13246 scan the table to invalidate all entries using this register, but this
13247 is too much work for us. */
13250 {
13256 else
13258 }
13260 /* The value being assigned might refer to X (like in "x++;"). In that
13261 case, we must replace it with (clobber (const_int 0)) to prevent
13262 infinite loops. */
13265 {
13269 }
13271 /* For the main register being modified, update the value, the mode, the
13272 nonzero bits, and the number of sign bit copies. */
13277 {
13285 rsp->last_set_sign_bit_copies
13287 }
13288 }
13290 /* Called via note_stores from record_dead_and_set_regs to handle one
13291 SET or CLOBBER in an insn. DATA is the instruction in which the
13292 set is occurring. */
13294 static void
13296 {
13303 {
13307 }
13310 {
13311 /* If we are setting the whole register, we know its value. Otherwise
13312 show that we don't know the value. We can handle a SUBREG if it's
13313 the low part, but we must be careful with paradoxical SUBREGs on
13314 RISC architectures because we cannot strip e.g. an extension around
13315 a load and record the naked load since the RTL middle-end considers
13316 that the upper bits are defined according to LOAD_EXTEND_OP. */
13323 BITS_PER_WORD)
13326 WORD_REGISTER_OPERATIONS
13332 else
13334 }
13336 /* Ignore pushes, they clobber nothing. */
13339 }
13341 /* Update the records of when each REG was most recently set or killed
13342 for the things done by INSN. This is the last thing done in processing
13343 INSN in the combiner loop.
13345 We update reg_stat[], in particular fields last_set, last_set_value,
13346 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13347 last_death, and also the similar information mem_last_set (which insn
13348 most recently modified memory) and last_call_luid (which insn was the
13349 most recent subroutine call). */
13351 static void
13353 {
13354 rtx link;
13358 {
13361 {
13366 {
13371 }
13372 }
13375 }
13378 {
13379 HARD_REG_SET callee_clobbers
13381 hard_reg_set_iterator hrsi;
13383 {
13386 /* ??? We could try to preserve some information from the last
13387 set of register I if the call doesn't actually clobber
13388 (reg:last_set_mode I), which might be true for ABIs with
13389 partial clobbers. However, it would be difficult to
13390 update last_set_nonzero_bits and last_sign_bit_copies
13391 to account for the part of I that actually was clobbered.
13392 It wouldn't help much anyway, since we rarely see this
13393 situation before RA. */
13403 }
13407 /* We can't combine into a call pattern. Remember, though, that
13408 the return value register is set at this LUID. We could
13409 still replace a register with the return value from the
13410 wrong subroutine call! */
13412 }
13413 else
13415 }
13417 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13418 register present in the SUBREG, so for each such SUBREG go back and
13419 adjust nonzero and sign bit information of the registers that are
13420 known to have some zero/sign bits set.
13422 This is needed because when combine blows the SUBREGs away, the
13423 information on zero/sign bits is lost and further combines can be
13424 missed because of that. */
13426 static void
13428 {
13430 rtx set;
13438 {
13447 {
13450 }
13454 {
13457 }
13460 {
13463 }
13464 else
13466 }
13467 }
13469 /* Check if X, a register, is known to contain a value already
13470 truncated to MODE. In this case we can use a subreg to refer to
13471 the truncated value even though in the generic case we would need
13472 an explicit truncation. */
13474 static bool
13476 {
13488 }
13490 /* If X is a hard reg or a subreg record the mode that the register is
13491 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13492 able to turn a truncate into a subreg using this information. Return true
13493 if traversing X is complete. */
13495 static bool
13497 {
13498 machine_mode truncated_mode;
13502 {
13514 }
13515 /* ??? For hard-regs we now record everything. We might be able to
13516 optimize this using last_set_mode. */
13519 else
13526 {
13529 }
13532 }
13534 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13535 the modes they are used in. This can help truning TRUNCATEs into
13536 SUBREGs. */
13538 static void
13540 {
13545 }
13547 /* Scan X for promoted SUBREGs. For each one found,
13548 note what it implies to the registers used in it. */
13550 static void
13552 {
13557 else
13558 {
13564 {
13574 }
13575 }
13576 }
13577 \f
13578 /* Verify that all the registers and memory references mentioned in *LOC are
13579 still valid. *LOC was part of a value set in INSN when label_tick was
13580 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13581 the invalid references with (clobber (const_int 0)) and return 1. This
13582 replacement is useful because we often can get useful information about
13583 the form of a value (e.g., if it was produced by a shift that always
13584 produces -1 or 0) even though we don't know exactly what registers it
13585 was produced from. */
13587 static int
13589 {
13596 {
13602 {
13605 /* If this is a pseudo-register that was only set once and not
13606 live at the beginning of the function, it is always valid. */
13610 && (!REGNO_REG_SET_P
13612 regno)))
13614 {
13618 }
13619 }
13622 }
13623 /* If this is a memory reference, make sure that there were no stores after
13624 it that might have clobbered the value. We don't have alias info, so we
13625 assume any store invalidates it. Moreover, we only have local UIDs, so
13626 we also assume that there were stores in the intervening basic blocks. */
13629 {
13633 }
13636 {
13638 {
13639 /* Check for identical subexpressions. If x contains
13640 identical subexpression we only have to traverse one of
13641 them. */
13643 {
13644 /* Note that at this point x0 has already been checked
13645 and found valid. */
13649 /* If x0 and x1 are identical then x is also valid. */
13653 /* If x1 is identical to a subexpression of x0 then
13654 while checking x0, x1 has already been checked. Thus
13655 it is valid and so as x. */
13660 /* If x0 is identical to a subexpression of x1 then x is
13661 valid iff the rest of x1 is valid. */
13664 return
13668 }
13673 }
13679 }
13681 /* If we haven't found a reason for it to be invalid, it is valid. */
13683 }
13685 /* Get the last value assigned to X, if known. Some registers
13686 in the value may be replaced with (clobber (const_int 0)) if their value
13687 is known longer known reliably. */
13689 static rtx
13691 {
13693 rtx value;
13696 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13697 then convert it to the desired mode. If this is a paradoxical SUBREG,
13698 we cannot predict what values the "extra" bits might have. */
13712 /* If we don't have a value, or if it isn't for this basic block and
13713 it's either a hard register, set more than once, or it's a live
13714 at the beginning of the function, return 0.
13716 Because if it's not live at the beginning of the function then the reg
13717 is always set before being used (is never used without being set).
13718 And, if it's set only once, and it's always set before use, then all
13719 uses must have the same last value, even if it's not from this basic
13720 block. */
13727 || REGNO_REG_SET_P
13731 /* If the value was set in a later insn than the ones we are processing,
13732 we can't use it even if the register was only set once. */
13737 /* If fewer bits were set than what we are asked for now, we cannot use
13738 the value. */
13743 /* If the value has all its registers valid, return it. */
13747 /* Otherwise, make a copy and replace any invalid register with
13748 (clobber (const_int 0)). If that fails for some reason, return 0. */
13755 }
13756 \f
13757 /* Define three variables used for communication between the following
13758 routines. */
13762 rtx reg_dead_reg;
13764 /* Function called via note_stores from reg_dead_at_p.
13766 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13767 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13769 static void
13771 {
13781 }
13783 /* Return nonzero if REG is known to be dead at INSN.
13785 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13786 referencing REG, it is dead. If we hit a SET referencing REG, it is
13787 live. Otherwise, see if it is live or dead at the start of the basic
13788 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13789 must be assumed to be always live. */
13791 static int
13793 {
13794 basic_block block;
13797 /* Set variables for reg_dead_at_p_1. */
13804 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13805 we allow the machine description to decide whether use-and-clobber
13806 patterns are OK. */
13808 {
13812 }
13814 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13815 beginning of basic block. */
13818 {
13820 {
13830 }
13836 }
13838 /* Look at live-in sets for the basic block that we were in. */
13844 }
13845 \f
13846 /* Note hard registers in X that are used. */
13848 static void
13850 {
13856 {
13860 CASE_CONST_ANY:
13868 /* If we are clobbering a MEM, mark any hard registers inside the
13869 address as used. */
13876 /* A hard reg in a wide mode may really be multiple registers.
13877 If so, mark all of them just like the first. */
13879 {
13880 /* None of this applies to the stack, frame or arg pointers. */
13882 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13890 }
13894 {
13895 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13896 the address. */
13908 }
13913 }
13915 /* Recursively scan the operands of this expression. */
13917 {
13921 {
13925 {
13930 }
13931 }
13932 }
13933 }
13934 \f
13935 /* Remove register number REGNO from the dead registers list of INSN.
13937 Return the note used to record the death, if there was one. */
13939 rtx
13941 {
13948 }
13950 /* For each register (hardware or pseudo) used within expression X, if its
13951 death is in an instruction with luid between FROM_LUID (inclusive) and
13952 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13953 list headed by PNOTES.
13955 That said, don't move registers killed by maybe_kill_insn.
13957 This is done when X is being merged by combination into TO_INSN. These
13958 notes will then be distributed as needed. */
13960 static void
13963 {
13969 {
13973 /* If we do not know where the register died, it may still die between
13974 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13976 {
13981 {
13983 {
13987 }
13990 }
13991 }
13993 /* Don't move the register if it gets killed in between from and to. */
14002 {
14005 /* It is possible for the call above to return 0. This can occur
14006 when last_death points to I2 or I1 that we combined with.
14007 In that case make a new note.
14009 We must also check for the case where X is a hard register
14010 and NOTE is a death note for a range of hard registers
14011 including X. In that case, we must put REG_DEAD notes for
14012 the remaining registers in place of NOTE. */
14016 {
14025 }
14027 /* If we didn't find any note, or if we found a REG_DEAD note that
14028 covers only part of the given reg, and we have a multi-reg hard
14029 register, then to be safe we must check for REG_DEAD notes
14030 for each register other than the first. They could have
14031 their own REG_DEAD notes lying around. */
14038 {
14045 else
14051 }
14054 {
14057 }
14058 else
14060 }
14063 }
14066 {
14071 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14072 that accesses one word of a multi-word item, some
14073 piece of everything register in the expression is used by
14074 this insn, so remove any old death. */
14075 /* ??? So why do we test for equality of the sizes? */
14081 {
14084 }
14086 /* If this is some other SUBREG, we know it replaces the entire
14087 value, so use that as the destination. */
14091 /* If this is a MEM, adjust deaths of anything used in the address.
14092 For a REG (the only other possibility), the entire value is
14093 being replaced so the old value is not used in this insn. */
14099 }
14108 {
14110 {
14115 }
14118 }
14119 }
14120 \f
14121 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14122 pattern of an insn. X must be a REG. */
14124 static int
14126 {
14130 {
14132 rtx target;
14139 else
14156 }
14164 }
14165 \f
14166 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14167 as appropriate. I3 and I2 are the insns resulting from the combination
14168 insns including FROM (I2 may be zero).
14170 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14171 not need REG_DEAD notes because they are being substituted for. This
14172 saves searching in the most common cases.
14174 Each note in the list is either ignored or placed on some insns, depending
14175 on the type of note. */
14177 static void
14180 {
14182 rtx tem_note;
14186 {
14191 {
14194 /* Doesn't matter much where we put this, as long as it's somewhere.
14195 It is preferable to keep these notes on branches, which is most
14196 likely to be i3. */
14203 else
14204 {
14207 }
14211 {
14212 /* The landing pad handling needs to be kept in sync with the
14213 prerequisite checking in try_combine. */
14215 /* A REG_EH_REGION note transfering control can only ever come
14216 from i3. */
14219 /* We are making sure there is a single effective REG_EH_REGION
14220 note and it's valid to put it on i3. */
14223 /* Throw away stray notes on insns that can never throw or
14224 make a nonlocal goto. */
14225 ;
14226 else
14227 {
14230 else
14231 {
14233 /* If i3 can still trap preserve the note, otherwise we've
14234 combined things such that we can now prove that the
14235 instructions can't trap. Drop the note in this case. */
14238 }
14239 }
14241 }
14244 /* ??? How to distribute between i3-i1. Assume i3 contains the
14245 entire adjustment. Assert i3 contains at least some adjust. */
14247 {
14249 /* fixup_args_size_notes looks at REG_NORETURN note,
14250 so ensure the note is placed there first. */
14252 {
14256 {
14262 }
14263 }
14265 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14266 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14269 && !ACCUMULATE_OUTGOING_ARGS
14271 }
14280 /* These notes must remain with the call. It should not be
14281 possible for both I2 and I3 to be a call. */
14284 else
14285 {
14288 }
14292 /* Any clobbers for i3 may still exist, and so we must process
14293 REG_UNUSED notes from that insn.
14295 Any clobbers from i2 or i1 can only exist if they were added by
14296 recog_for_combine. In that case, recog_for_combine created the
14297 necessary REG_UNUSED notes. Trying to keep any original
14298 REG_UNUSED notes from these insns can cause incorrect output
14299 if it is for the same register as the original i3 dest.
14300 In that case, we will notice that the register is set in i3,
14301 and then add a REG_UNUSED note for the destination of i3, which
14302 is wrong. However, it is possible to have REG_UNUSED notes from
14303 i2 or i1 for register which were both used and clobbered, so
14304 we keep notes from i2 or i1 if they will turn into REG_DEAD
14305 notes. */
14307 /* If this register is set or clobbered between FROM_INSN and I3,
14308 we should not create a note for it. */
14312 /* If this register is set or clobbered in I3, put the note there
14313 unless there is one already. */
14315 {
14323 }
14324 /* Otherwise, if this register is used by I3, then this register
14325 now dies here, so we must put a REG_DEAD note here unless there
14326 is one already. */
14332 {
14335 }
14337 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14338 but we can't tell which at this point. We must reset any
14339 expectations we had about the value that was previously
14340 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14341 and, if appropriate, restore its previous value, but we
14342 don't have enough information for that at this point. */
14343 else
14344 {
14347 /* Otherwise, if this register is now referenced in i2
14348 then the register used to be modified in one of the
14349 original insns. If it was i3 (say, in an unused
14350 parallel), it's now completely gone, so the note can
14351 be discarded. But if it was modified in i2, i1 or i0
14352 and we still reference it in i2, then we're
14353 referencing the previous value, and since the
14354 register was modified and REG_UNUSED, we know that
14355 the previous value is now dead. So, if we only
14356 reference the register in i2, we change the note to
14357 REG_DEAD, to reflect the previous value. However, if
14358 we're also setting or clobbering the register as
14359 scratch, we know (because the register was not
14360 referenced in i3) that it's unused, just as it was
14361 unused before, and we place the note in i2. */
14364 {
14373 }
14374 }
14381 /* These notes say something about results of an insn. We can
14382 only support them if they used to be on I3 in which case they
14383 remain on I3. Otherwise they are ignored.
14385 If the note refers to an expression that is not a constant, we
14386 must also ignore the note since we cannot tell whether the
14387 equivalence is still true. It might be possible to do
14388 slightly better than this (we only have a problem if I2DEST
14389 or I1DEST is present in the expression), but it doesn't
14390 seem worth the trouble. */
14398 /* These notes say something about how a register is used. They must
14399 be present on any use of the register in I2 or I3. */
14404 {
14407 else
14409 }
14414 /* This can show up in several ways -- either directly in the
14415 pattern, or hidden off in the constant pool with (or without?)
14416 a REG_EQUAL note. */
14417 /* ??? Ignore the without-reg_equal-note problem for now. */
14429 {
14432 else
14434 }
14436 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14437 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14438 there. */
14443 {
14450 }
14456 {
14464 }
14468 /* This note says something about the value of a register prior
14469 to the execution of an insn. It is too much trouble to see
14470 if the note is still correct in all situations. It is better
14471 to simply delete it. */
14475 /* If we replaced the right hand side of FROM_INSN with a
14476 REG_EQUAL note, the original use of the dying register
14477 will not have been combined into I3 and I2. In such cases,
14478 FROM_INSN is guaranteed to be the first of the combined
14479 instructions, so we simply need to search back before
14480 FROM_INSN for the previous use or set of this register,
14481 then alter the notes there appropriately.
14483 If the register is used as an input in I3, it dies there.
14484 Similarly for I2, if it is nonzero and adjacent to I3.
14486 If the register is not used as an input in either I3 or I2
14487 and it is not one of the registers we were supposed to eliminate,
14488 there are two possibilities. We might have a non-adjacent I2
14489 or we might have somehow eliminated an additional register
14490 from a computation. For example, we might have had A & B where
14491 we discover that B will always be zero. In this case we will
14492 eliminate the reference to A.
14494 In both cases, we must search to see if we can find a previous
14495 use of A and put the death note there. */
14501 else
14502 {
14508 {
14509 /* If the new I2 sets the same register that is marked
14510 dead in the note, we do not in general know where to
14511 put the note. One important case we _can_ handle is
14512 when the note comes from I3. */
14515 else
14517 }
14524 && !(i2mod
14526 i2mod_old_rhs)))
14531 }
14534 {
14538 {
14540 {
14544 }
14546 /* If the register is being set at TEM_INSN, see if that is all
14547 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14548 into a REG_UNUSED note instead. Don't delete sets to
14549 global register vars. */
14553 {
14563 ;
14565 /* Verify that it was the set, and not a clobber that
14566 modified the register.
14568 If we cannot delete the setter due to side
14569 effects, mark the user with an UNUSED note instead
14570 of deleting it. */
14574 {
14575 /* Move the notes and links of TEM_INSN elsewhere.
14576 This might delete other dead insns recursively.
14577 First set the pattern to something that won't use
14578 any register. */
14596 }
14597 else
14598 {
14601 /* If there isn't already a REG_UNUSED note, put one
14602 here. Do not place a REG_DEAD note, even if
14603 the register is also used here; that would not
14604 match the algorithm used in lifetime analysis
14605 and can cause the consistency check in the
14606 scheduler to fail. */
14611 }
14612 }
14616 {
14619 /* If we are doing a 3->2 combination, and we have a
14620 register which formerly died in i3 and was not used
14621 by i2, which now no longer dies in i3 and is used in
14622 i2 but does not die in i2, and place is between i2
14623 and i3, then we may need to move a link from place to
14624 i2. */
14626 && from_insn
14629 {
14633 }
14635 }
14639 }
14641 }
14643 /* If the register is set or already dead at PLACE, we needn't do
14644 anything with this note if it is still a REG_DEAD note.
14645 We check here if it is set at all, not if is it totally replaced,
14646 which is what `dead_or_set_p' checks, so also check for it being
14647 set partially. */
14650 {
14656 {
14657 /* Unless the register previously died in PLACE, clear
14658 last_death. [I no longer understand why this is
14659 being done.] */
14663 }
14664 else
14667 /* If this is a death note for a hard reg that is occupying
14668 multiple registers, ensure that we are still using all
14669 parts of the object. If we find a piece of the object
14670 that is unused, we must arrange for an appropriate REG_DEAD
14671 note to be added for it. However, we can't just emit a USE
14672 and tag the note to it, since the register might actually
14673 be dead; so we recourse, and the recursive call then finds
14674 the previous insn that used this register. */
14677 {
14686 {
14689 }
14692 {
14693 /* Put only REG_DEAD notes for pieces that are
14694 not already dead or set. */
14698 {
14705 {
14707 NULL_RTX);
14711 NULL_RTX);
14712 }
14717 {
14719 {
14723 }
14727 {
14730 }
14731 }
14732 }
14735 }
14736 }
14737 }
14741 /* Any other notes should not be present at this point in the
14742 compilation. */
14744 }
14747 {
14751 /* Set added_notes_insn to the earliest insn we added a note to. */
14755 }
14758 {
14761 /* Set added_notes_insn to the earliest insn we added a note to. */
14765 }
14766 }
14767 }
14768 \f
14769 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14770 I3, I2, and I1 to new locations. This is also called to add a link
14771 pointing at I3 when I3's destination is changed. */
14773 static void
14775 {
14779 {
14786 /* If the insn that this link points to is a NOTE, ignore it. */
14795 {
14798 {
14814 }
14817 }
14818 else
14831 /* A LOG_LINK is defined as being placed on the first insn that uses
14832 a register and points to the insn that sets the register. Start
14833 searching at the next insn after the target of the link and stop
14834 when we reach a set of the register or the end of the basic block.
14836 Note that this correctly handles the link that used to point from
14837 I3 to I2. Also note that not much searching is typically done here
14838 since most links don't point very far away. */
14847 {
14851 }
14854 {
14857 }
14861 /* If we found a place to put the link, place it there unless there
14862 is already a link to the same insn as LINK at that point. */
14865 {
14873 {
14877 /* Set added_links_insn to the earliest insn we added a
14878 link to. */
14882 }
14883 }
14884 }
14885 }
14886 \f
14887 /* Check for any register or memory mentioned in EQUIV that is not
14888 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14889 of EXPR where some registers may have been replaced by constants. */
14891 static bool
14893 {
14896 {
14901 }
14903 }
14904 \f
14905 DEBUG_FUNCTION void
14907 {
14908 fprintf
14910 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14912 }
14914 void
14916 {
14917 fprintf
14919 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14921 }
14922 \f
14923 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
14924 the reg-to-reg copy can usefully combine with later instructions, but we
14925 do not want to combine the hard reg into later instructions, for that
14926 restricts register allocation. */
14927 static void
14929 {
14930 basic_block bb;
14933 {
14937 {
14960 }
14961 }
14962 }
14964 /* Try combining insns through substitution. */
14965 static unsigned int
14967 {
14977 int rebuild_jump_labels_after_combine
14980 /* Combining insns may have turned an indirect jump into a
14981 direct jump. Rebuild the JUMP_LABEL fields of jumping
14982 instructions. */
14984 {
14991 }
14995 }
15000 {
15010 };
15013 {
15017 {}
15019 /* opt_pass methods: */
15022 {
15024 }
15030 rtl_opt_pass *
15032 {
15034 }