1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "sched-int.h"
48 #include "target-def.h"
51 #include "langhooks.h"
53 /* This is used for communication between ASM_OUTPUT_LABEL and
54 ASM_OUTPUT_LABELREF. */
55 int ia64_asm_output_label
= 0;
57 /* Define the information needed to generate branch and scc insns. This is
58 stored from the compare operation. */
59 struct rtx_def
* ia64_compare_op0
;
60 struct rtx_def
* ia64_compare_op1
;
62 /* Register names for ia64_expand_prologue. */
63 static const char * const ia64_reg_numbers
[96] =
64 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
65 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
66 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
67 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
68 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
69 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
70 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
71 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
72 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
73 "r104","r105","r106","r107","r108","r109","r110","r111",
74 "r112","r113","r114","r115","r116","r117","r118","r119",
75 "r120","r121","r122","r123","r124","r125","r126","r127"};
77 /* ??? These strings could be shared with REGISTER_NAMES. */
78 static const char * const ia64_input_reg_names
[8] =
79 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
81 /* ??? These strings could be shared with REGISTER_NAMES. */
82 static const char * const ia64_local_reg_names
[80] =
83 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
84 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
85 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
86 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
87 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
88 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
89 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
90 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
91 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
92 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
94 /* ??? These strings could be shared with REGISTER_NAMES. */
95 static const char * const ia64_output_reg_names
[8] =
96 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
98 /* String used with the -mfixed-range= option. */
99 const char *ia64_fixed_range_string
;
101 /* Determines whether we use adds, addl, or movl to generate our
102 TLS immediate offsets. */
103 int ia64_tls_size
= 22;
105 /* String used with the -mtls-size= option. */
106 const char *ia64_tls_size_string
;
108 /* Which cpu are we scheduling for. */
109 enum processor_type ia64_tune
;
111 /* String used with the -tune= option. */
112 const char *ia64_tune_string
;
114 /* Determines whether we run our final scheduling pass or not. We always
115 avoid the normal second scheduling pass. */
116 static int ia64_flag_schedule_insns2
;
118 /* Variables which are this size or smaller are put in the sdata/sbss
121 unsigned int ia64_section_threshold
;
123 /* The following variable is used by the DFA insn scheduler. The value is
124 TRUE if we do insn bundling instead of insn scheduling. */
127 /* Structure to be filled in by ia64_compute_frame_size with register
128 save masks and offsets for the current function. */
130 struct ia64_frame_info
132 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
133 the caller's scratch area. */
134 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
135 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
136 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
137 HARD_REG_SET mask
; /* mask of saved registers. */
138 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
139 registers or long-term scratches. */
140 int n_spilled
; /* number of spilled registers. */
141 int reg_fp
; /* register for fp. */
142 int reg_save_b0
; /* save register for b0. */
143 int reg_save_pr
; /* save register for prs. */
144 int reg_save_ar_pfs
; /* save register for ar.pfs. */
145 int reg_save_ar_unat
; /* save register for ar.unat. */
146 int reg_save_ar_lc
; /* save register for ar.lc. */
147 int reg_save_gp
; /* save register for gp. */
148 int n_input_regs
; /* number of input registers used. */
149 int n_local_regs
; /* number of local registers used. */
150 int n_output_regs
; /* number of output registers used. */
151 int n_rotate_regs
; /* number of rotating registers used. */
153 char need_regstk
; /* true if a .regstk directive needed. */
154 char initialized
; /* true if the data is finalized. */
157 /* Current frame information calculated by ia64_compute_frame_size. */
158 static struct ia64_frame_info current_frame_info
;
160 static int ia64_use_dfa_pipeline_interface
PARAMS ((void));
161 static int ia64_first_cycle_multipass_dfa_lookahead
PARAMS ((void));
162 static void ia64_dependencies_evaluation_hook
PARAMS ((rtx
, rtx
));
163 static void ia64_init_dfa_pre_cycle_insn
PARAMS ((void));
164 static rtx ia64_dfa_pre_cycle_insn
PARAMS ((void));
165 static int ia64_first_cycle_multipass_dfa_lookahead_guard
PARAMS ((rtx
));
166 static int ia64_dfa_new_cycle
PARAMS ((FILE *, int, rtx
, int, int, int *));
167 static rtx gen_tls_get_addr
PARAMS ((void));
168 static rtx gen_thread_pointer
PARAMS ((void));
169 static rtx ia64_expand_tls_address
PARAMS ((enum tls_model
, rtx
, rtx
));
170 static int find_gr_spill
PARAMS ((int));
171 static int next_scratch_gr_reg
PARAMS ((void));
172 static void mark_reg_gr_used_mask
PARAMS ((rtx
, void *));
173 static void ia64_compute_frame_size
PARAMS ((HOST_WIDE_INT
));
174 static void setup_spill_pointers
PARAMS ((int, rtx
, HOST_WIDE_INT
));
175 static void finish_spill_pointers
PARAMS ((void));
176 static rtx spill_restore_mem
PARAMS ((rtx
, HOST_WIDE_INT
));
177 static void do_spill
PARAMS ((rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
));
178 static void do_restore
PARAMS ((rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
));
179 static rtx gen_movdi_x
PARAMS ((rtx
, rtx
, rtx
));
180 static rtx gen_fr_spill_x
PARAMS ((rtx
, rtx
, rtx
));
181 static rtx gen_fr_restore_x
PARAMS ((rtx
, rtx
, rtx
));
183 static enum machine_mode hfa_element_mode
PARAMS ((tree
, int));
184 static bool ia64_function_ok_for_sibcall
PARAMS ((tree
, tree
));
185 static bool ia64_rtx_costs
PARAMS ((rtx
, int, int, int *));
186 static void fix_range
PARAMS ((const char *));
187 static struct machine_function
* ia64_init_machine_status
PARAMS ((void));
188 static void emit_insn_group_barriers
PARAMS ((FILE *));
189 static void emit_all_insn_group_barriers
PARAMS ((FILE *));
190 static void final_emit_insn_group_barriers
PARAMS ((FILE *));
191 static void emit_predicate_relation_info
PARAMS ((void));
192 static void ia64_reorg
PARAMS ((void));
193 static bool ia64_in_small_data_p
PARAMS ((tree
));
194 static void process_epilogue
PARAMS ((void));
195 static int process_set
PARAMS ((FILE *, rtx
));
197 static rtx ia64_expand_fetch_and_op
PARAMS ((optab
, enum machine_mode
,
199 static rtx ia64_expand_op_and_fetch
PARAMS ((optab
, enum machine_mode
,
201 static rtx ia64_expand_compare_and_swap
PARAMS ((enum machine_mode
,
204 static rtx ia64_expand_lock_test_and_set
PARAMS ((enum machine_mode
,
206 static rtx ia64_expand_lock_release
PARAMS ((enum machine_mode
, tree
, rtx
));
207 static bool ia64_assemble_integer
PARAMS ((rtx
, unsigned int, int));
208 static void ia64_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
209 static void ia64_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
210 static void ia64_output_function_end_prologue
PARAMS ((FILE *));
212 static int ia64_issue_rate
PARAMS ((void));
213 static int ia64_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
214 static void ia64_sched_init
PARAMS ((FILE *, int, int));
215 static void ia64_sched_finish
PARAMS ((FILE *, int));
216 static int ia64_dfa_sched_reorder
PARAMS ((FILE *, int, rtx
*, int *,
218 static int ia64_sched_reorder
PARAMS ((FILE *, int, rtx
*, int *, int));
219 static int ia64_sched_reorder2
PARAMS ((FILE *, int, rtx
*, int *, int));
220 static int ia64_variable_issue
PARAMS ((FILE *, int, rtx
, int));
222 static struct bundle_state
*get_free_bundle_state
PARAMS ((void));
223 static void free_bundle_state
PARAMS ((struct bundle_state
*));
224 static void initiate_bundle_states
PARAMS ((void));
225 static void finish_bundle_states
PARAMS ((void));
226 static unsigned bundle_state_hash
PARAMS ((const void *));
227 static int bundle_state_eq_p
PARAMS ((const void *, const void *));
228 static int insert_bundle_state
PARAMS ((struct bundle_state
*));
229 static void initiate_bundle_state_table
PARAMS ((void));
230 static void finish_bundle_state_table
PARAMS ((void));
231 static int try_issue_nops
PARAMS ((struct bundle_state
*, int));
232 static int try_issue_insn
PARAMS ((struct bundle_state
*, rtx
));
233 static void issue_nops_and_insn
PARAMS ((struct bundle_state
*, int,
235 static int get_max_pos
PARAMS ((state_t
));
236 static int get_template
PARAMS ((state_t
, int));
238 static rtx get_next_important_insn
PARAMS ((rtx
, rtx
));
239 static void bundling
PARAMS ((FILE *, int, rtx
, rtx
));
241 static void ia64_output_mi_thunk
PARAMS ((FILE *, tree
, HOST_WIDE_INT
,
242 HOST_WIDE_INT
, tree
));
244 static void ia64_select_rtx_section
PARAMS ((enum machine_mode
, rtx
,
245 unsigned HOST_WIDE_INT
));
246 static void ia64_rwreloc_select_section
PARAMS ((tree
, int,
247 unsigned HOST_WIDE_INT
))
249 static void ia64_rwreloc_unique_section
PARAMS ((tree
, int))
251 static void ia64_rwreloc_select_rtx_section
PARAMS ((enum machine_mode
, rtx
,
252 unsigned HOST_WIDE_INT
))
254 static unsigned int ia64_rwreloc_section_type_flags
255 PARAMS ((tree
, const char *, int))
258 static void ia64_hpux_add_extern_decl
PARAMS ((const char *name
))
261 /* Table of valid machine attributes. */
262 static const struct attribute_spec ia64_attribute_table
[] =
264 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
265 { "syscall_linkage", 0, 0, false, true, true, NULL
},
266 { NULL
, 0, 0, false, false, false, NULL
}
269 /* Initialize the GCC target structure. */
270 #undef TARGET_ATTRIBUTE_TABLE
271 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
273 #undef TARGET_INIT_BUILTINS
274 #define TARGET_INIT_BUILTINS ia64_init_builtins
276 #undef TARGET_EXPAND_BUILTIN
277 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
279 #undef TARGET_ASM_BYTE_OP
280 #define TARGET_ASM_BYTE_OP "\tdata1\t"
281 #undef TARGET_ASM_ALIGNED_HI_OP
282 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
283 #undef TARGET_ASM_ALIGNED_SI_OP
284 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
285 #undef TARGET_ASM_ALIGNED_DI_OP
286 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
287 #undef TARGET_ASM_UNALIGNED_HI_OP
288 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
289 #undef TARGET_ASM_UNALIGNED_SI_OP
290 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
291 #undef TARGET_ASM_UNALIGNED_DI_OP
292 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
293 #undef TARGET_ASM_INTEGER
294 #define TARGET_ASM_INTEGER ia64_assemble_integer
296 #undef TARGET_ASM_FUNCTION_PROLOGUE
297 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
298 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
299 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
300 #undef TARGET_ASM_FUNCTION_EPILOGUE
301 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
303 #undef TARGET_IN_SMALL_DATA_P
304 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
306 #undef TARGET_SCHED_ADJUST_COST
307 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
308 #undef TARGET_SCHED_ISSUE_RATE
309 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
310 #undef TARGET_SCHED_VARIABLE_ISSUE
311 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
312 #undef TARGET_SCHED_INIT
313 #define TARGET_SCHED_INIT ia64_sched_init
314 #undef TARGET_SCHED_FINISH
315 #define TARGET_SCHED_FINISH ia64_sched_finish
316 #undef TARGET_SCHED_REORDER
317 #define TARGET_SCHED_REORDER ia64_sched_reorder
318 #undef TARGET_SCHED_REORDER2
319 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
321 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
322 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
324 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
325 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
327 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
328 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
330 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
331 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
332 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
333 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
335 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
336 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
337 ia64_first_cycle_multipass_dfa_lookahead_guard
339 #undef TARGET_SCHED_DFA_NEW_CYCLE
340 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
343 #undef TARGET_HAVE_TLS
344 #define TARGET_HAVE_TLS true
347 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
348 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
350 #undef TARGET_ASM_OUTPUT_MI_THUNK
351 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
352 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
353 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
355 #undef TARGET_RTX_COSTS
356 #define TARGET_RTX_COSTS ia64_rtx_costs
357 #undef TARGET_ADDRESS_COST
358 #define TARGET_ADDRESS_COST hook_int_rtx_0
360 #undef TARGET_MACHINE_DEPENDENT_REORG
361 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
363 struct gcc_target targetm
= TARGET_INITIALIZER
;
365 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
368 call_operand (op
, mode
)
370 enum machine_mode mode
;
372 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
375 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
376 || (GET_CODE (op
) == SUBREG
&& GET_CODE (XEXP (op
, 0)) == REG
));
379 /* Return 1 if OP refers to a symbol in the sdata section. */
382 sdata_symbolic_operand (op
, mode
)
384 enum machine_mode mode ATTRIBUTE_UNUSED
;
386 switch (GET_CODE (op
))
389 if (GET_CODE (XEXP (op
, 0)) != PLUS
390 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
)
392 op
= XEXP (XEXP (op
, 0), 0);
396 if (CONSTANT_POOL_ADDRESS_P (op
))
397 return GET_MODE_SIZE (get_pool_mode (op
)) <= ia64_section_threshold
;
399 return SYMBOL_REF_LOCAL_P (op
) && SYMBOL_REF_SMALL_P (op
);
408 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
411 got_symbolic_operand (op
, mode
)
413 enum machine_mode mode ATTRIBUTE_UNUSED
;
415 switch (GET_CODE (op
))
419 if (GET_CODE (op
) != PLUS
)
421 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
424 if (GET_CODE (op
) != CONST_INT
)
429 /* Ok if we're not using GOT entries at all. */
430 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
433 /* "Ok" while emitting rtl, since otherwise we won't be provided
434 with the entire offset during emission, which makes it very
435 hard to split the offset into high and low parts. */
436 if (rtx_equal_function_value_matters
)
439 /* Force the low 14 bits of the constant to zero so that we do not
440 use up so many GOT entries. */
441 return (INTVAL (op
) & 0x3fff) == 0;
453 /* Return 1 if OP refers to a symbol. */
456 symbolic_operand (op
, mode
)
458 enum machine_mode mode ATTRIBUTE_UNUSED
;
460 switch (GET_CODE (op
))
473 /* Return tls_model if OP refers to a TLS symbol. */
476 tls_symbolic_operand (op
, mode
)
478 enum machine_mode mode ATTRIBUTE_UNUSED
;
480 if (GET_CODE (op
) != SYMBOL_REF
)
482 return SYMBOL_REF_TLS_MODEL (op
);
486 /* Return 1 if OP refers to a function. */
489 function_operand (op
, mode
)
491 enum machine_mode mode ATTRIBUTE_UNUSED
;
493 if (GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (op
))
499 /* Return 1 if OP is setjmp or a similar function. */
501 /* ??? This is an unsatisfying solution. Should rethink. */
504 setjmp_operand (op
, mode
)
506 enum machine_mode mode ATTRIBUTE_UNUSED
;
511 if (GET_CODE (op
) != SYMBOL_REF
)
516 /* The following code is borrowed from special_function_p in calls.c. */
518 /* Disregard prefix _, __ or __x. */
521 if (name
[1] == '_' && name
[2] == 'x')
523 else if (name
[1] == '_')
533 && (! strcmp (name
, "setjmp")
534 || ! strcmp (name
, "setjmp_syscall")))
536 && ! strcmp (name
, "sigsetjmp"))
538 && ! strcmp (name
, "savectx")));
540 else if ((name
[0] == 'q' && name
[1] == 's'
541 && ! strcmp (name
, "qsetjmp"))
542 || (name
[0] == 'v' && name
[1] == 'f'
543 && ! strcmp (name
, "vfork")))
549 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
552 move_operand (op
, mode
)
554 enum machine_mode mode
;
556 return general_operand (op
, mode
) && !tls_symbolic_operand (op
, mode
);
559 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
562 gr_register_operand (op
, mode
)
564 enum machine_mode mode
;
566 if (! register_operand (op
, mode
))
568 if (GET_CODE (op
) == SUBREG
)
569 op
= SUBREG_REG (op
);
570 if (GET_CODE (op
) == REG
)
572 unsigned int regno
= REGNO (op
);
573 if (regno
< FIRST_PSEUDO_REGISTER
)
574 return GENERAL_REGNO_P (regno
);
579 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
582 fr_register_operand (op
, mode
)
584 enum machine_mode mode
;
586 if (! register_operand (op
, mode
))
588 if (GET_CODE (op
) == SUBREG
)
589 op
= SUBREG_REG (op
);
590 if (GET_CODE (op
) == REG
)
592 unsigned int regno
= REGNO (op
);
593 if (regno
< FIRST_PSEUDO_REGISTER
)
594 return FR_REGNO_P (regno
);
599 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
602 grfr_register_operand (op
, mode
)
604 enum machine_mode mode
;
606 if (! register_operand (op
, mode
))
608 if (GET_CODE (op
) == SUBREG
)
609 op
= SUBREG_REG (op
);
610 if (GET_CODE (op
) == REG
)
612 unsigned int regno
= REGNO (op
);
613 if (regno
< FIRST_PSEUDO_REGISTER
)
614 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
619 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
622 gr_nonimmediate_operand (op
, mode
)
624 enum machine_mode mode
;
626 if (! nonimmediate_operand (op
, mode
))
628 if (GET_CODE (op
) == SUBREG
)
629 op
= SUBREG_REG (op
);
630 if (GET_CODE (op
) == REG
)
632 unsigned int regno
= REGNO (op
);
633 if (regno
< FIRST_PSEUDO_REGISTER
)
634 return GENERAL_REGNO_P (regno
);
639 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
642 fr_nonimmediate_operand (op
, mode
)
644 enum machine_mode mode
;
646 if (! nonimmediate_operand (op
, mode
))
648 if (GET_CODE (op
) == SUBREG
)
649 op
= SUBREG_REG (op
);
650 if (GET_CODE (op
) == REG
)
652 unsigned int regno
= REGNO (op
);
653 if (regno
< FIRST_PSEUDO_REGISTER
)
654 return FR_REGNO_P (regno
);
659 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
662 grfr_nonimmediate_operand (op
, mode
)
664 enum machine_mode mode
;
666 if (! nonimmediate_operand (op
, mode
))
668 if (GET_CODE (op
) == SUBREG
)
669 op
= SUBREG_REG (op
);
670 if (GET_CODE (op
) == REG
)
672 unsigned int regno
= REGNO (op
);
673 if (regno
< FIRST_PSEUDO_REGISTER
)
674 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
679 /* Return 1 if OP is a GR register operand, or zero. */
682 gr_reg_or_0_operand (op
, mode
)
684 enum machine_mode mode
;
686 return (op
== const0_rtx
|| gr_register_operand (op
, mode
));
689 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
692 gr_reg_or_5bit_operand (op
, mode
)
694 enum machine_mode mode
;
696 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0 && INTVAL (op
) < 32)
697 || GET_CODE (op
) == CONSTANT_P_RTX
698 || gr_register_operand (op
, mode
));
701 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
704 gr_reg_or_6bit_operand (op
, mode
)
706 enum machine_mode mode
;
708 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
709 || GET_CODE (op
) == CONSTANT_P_RTX
710 || gr_register_operand (op
, mode
));
713 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
716 gr_reg_or_8bit_operand (op
, mode
)
718 enum machine_mode mode
;
720 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
721 || GET_CODE (op
) == CONSTANT_P_RTX
722 || gr_register_operand (op
, mode
));
725 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
728 grfr_reg_or_8bit_operand (op
, mode
)
730 enum machine_mode mode
;
732 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
733 || GET_CODE (op
) == CONSTANT_P_RTX
734 || grfr_register_operand (op
, mode
));
737 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
741 gr_reg_or_8bit_adjusted_operand (op
, mode
)
743 enum machine_mode mode
;
745 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
746 || GET_CODE (op
) == CONSTANT_P_RTX
747 || gr_register_operand (op
, mode
));
750 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
751 immediate and an 8 bit adjusted immediate operand. This is necessary
752 because when we emit a compare, we don't know what the condition will be,
753 so we need the union of the immediates accepted by GT and LT. */
756 gr_reg_or_8bit_and_adjusted_operand (op
, mode
)
758 enum machine_mode mode
;
760 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
))
761 && CONST_OK_FOR_L (INTVAL (op
)))
762 || GET_CODE (op
) == CONSTANT_P_RTX
763 || gr_register_operand (op
, mode
));
766 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
769 gr_reg_or_14bit_operand (op
, mode
)
771 enum machine_mode mode
;
773 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
774 || GET_CODE (op
) == CONSTANT_P_RTX
775 || gr_register_operand (op
, mode
));
778 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
781 gr_reg_or_22bit_operand (op
, mode
)
783 enum machine_mode mode
;
785 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_J (INTVAL (op
)))
786 || GET_CODE (op
) == CONSTANT_P_RTX
787 || gr_register_operand (op
, mode
));
790 /* Return 1 if OP is a 6 bit immediate operand. */
793 shift_count_operand (op
, mode
)
795 enum machine_mode mode ATTRIBUTE_UNUSED
;
797 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
798 || GET_CODE (op
) == CONSTANT_P_RTX
);
801 /* Return 1 if OP is a 5 bit immediate operand. */
804 shift_32bit_count_operand (op
, mode
)
806 enum machine_mode mode ATTRIBUTE_UNUSED
;
808 return ((GET_CODE (op
) == CONST_INT
809 && (INTVAL (op
) >= 0 && INTVAL (op
) < 32))
810 || GET_CODE (op
) == CONSTANT_P_RTX
);
813 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
816 shladd_operand (op
, mode
)
818 enum machine_mode mode ATTRIBUTE_UNUSED
;
820 return (GET_CODE (op
) == CONST_INT
821 && (INTVAL (op
) == 2 || INTVAL (op
) == 4
822 || INTVAL (op
) == 8 || INTVAL (op
) == 16));
825 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
828 fetchadd_operand (op
, mode
)
830 enum machine_mode mode ATTRIBUTE_UNUSED
;
832 return (GET_CODE (op
) == CONST_INT
833 && (INTVAL (op
) == -16 || INTVAL (op
) == -8 ||
834 INTVAL (op
) == -4 || INTVAL (op
) == -1 ||
835 INTVAL (op
) == 1 || INTVAL (op
) == 4 ||
836 INTVAL (op
) == 8 || INTVAL (op
) == 16));
839 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
842 fr_reg_or_fp01_operand (op
, mode
)
844 enum machine_mode mode
;
846 return ((GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (op
))
847 || fr_register_operand (op
, mode
));
850 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
851 POST_MODIFY with a REG as displacement. */
854 destination_operand (op
, mode
)
856 enum machine_mode mode
;
858 if (! nonimmediate_operand (op
, mode
))
860 if (GET_CODE (op
) == MEM
861 && GET_CODE (XEXP (op
, 0)) == POST_MODIFY
862 && GET_CODE (XEXP (XEXP (XEXP (op
, 0), 1), 1)) == REG
)
867 /* Like memory_operand, but don't allow post-increments. */
870 not_postinc_memory_operand (op
, mode
)
872 enum machine_mode mode
;
874 return (memory_operand (op
, mode
)
875 && GET_RTX_CLASS (GET_CODE (XEXP (op
, 0))) != 'a');
878 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
879 signed immediate operand. */
882 normal_comparison_operator (op
, mode
)
884 enum machine_mode mode
;
886 enum rtx_code code
= GET_CODE (op
);
887 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
888 && (code
== EQ
|| code
== NE
889 || code
== GT
|| code
== LE
|| code
== GTU
|| code
== LEU
));
892 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
893 signed immediate operand. */
896 adjusted_comparison_operator (op
, mode
)
898 enum machine_mode mode
;
900 enum rtx_code code
= GET_CODE (op
);
901 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
902 && (code
== LT
|| code
== GE
|| code
== LTU
|| code
== GEU
));
905 /* Return 1 if this is a signed inequality operator. */
908 signed_inequality_operator (op
, mode
)
910 enum machine_mode mode
;
912 enum rtx_code code
= GET_CODE (op
);
913 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
914 && (code
== GE
|| code
== GT
915 || code
== LE
|| code
== LT
));
918 /* Return 1 if this operator is valid for predication. */
921 predicate_operator (op
, mode
)
923 enum machine_mode mode
;
925 enum rtx_code code
= GET_CODE (op
);
926 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
927 && (code
== EQ
|| code
== NE
));
930 /* Return 1 if this operator can be used in a conditional operation. */
933 condop_operator (op
, mode
)
935 enum machine_mode mode
;
937 enum rtx_code code
= GET_CODE (op
);
938 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
939 && (code
== PLUS
|| code
== MINUS
|| code
== AND
940 || code
== IOR
|| code
== XOR
));
943 /* Return 1 if this is the ar.lc register. */
946 ar_lc_reg_operand (op
, mode
)
948 enum machine_mode mode
;
950 return (GET_MODE (op
) == DImode
951 && (mode
== DImode
|| mode
== VOIDmode
)
952 && GET_CODE (op
) == REG
953 && REGNO (op
) == AR_LC_REGNUM
);
956 /* Return 1 if this is the ar.ccv register. */
959 ar_ccv_reg_operand (op
, mode
)
961 enum machine_mode mode
;
963 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
964 && GET_CODE (op
) == REG
965 && REGNO (op
) == AR_CCV_REGNUM
);
968 /* Return 1 if this is the ar.pfs register. */
971 ar_pfs_reg_operand (op
, mode
)
973 enum machine_mode mode
;
975 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
976 && GET_CODE (op
) == REG
977 && REGNO (op
) == AR_PFS_REGNUM
);
980 /* Like general_operand, but don't allow (mem (addressof)). */
983 general_tfmode_operand (op
, mode
)
985 enum machine_mode mode
;
987 if (! general_operand (op
, mode
))
989 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
997 destination_tfmode_operand (op
, mode
)
999 enum machine_mode mode
;
1001 if (! destination_operand (op
, mode
))
1003 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
1011 tfreg_or_fp01_operand (op
, mode
)
1013 enum machine_mode mode
;
1015 if (GET_CODE (op
) == SUBREG
)
1017 return fr_reg_or_fp01_operand (op
, mode
);
1020 /* Return 1 if OP is valid as a base register in a reg + offset address. */
1023 basereg_operand (op
, mode
)
1025 enum machine_mode mode
;
1027 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
1028 checks from pa.c basereg_operand as well? Seems to be OK without them
1031 return (register_operand (op
, mode
) &&
1032 REG_POINTER ((GET_CODE (op
) == SUBREG
) ? SUBREG_REG (op
) : op
));
1035 /* Return 1 if the operands of a move are ok. */
1038 ia64_move_ok (dst
, src
)
1041 /* If we're under init_recog_no_volatile, we'll not be able to use
1042 memory_operand. So check the code directly and don't worry about
1043 the validity of the underlying address, which should have been
1044 checked elsewhere anyway. */
1045 if (GET_CODE (dst
) != MEM
)
1047 if (GET_CODE (src
) == MEM
)
1049 if (register_operand (src
, VOIDmode
))
1052 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1053 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
1054 return src
== const0_rtx
;
1056 return GET_CODE (src
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (src
);
1059 /* Return 0 if we are doing C++ code. This optimization fails with
1060 C++ because of GNAT c++/6685. */
1063 addp4_optimize_ok (op1
, op2
)
1067 if (!strcmp (lang_hooks
.name
, "GNU C++"))
1070 return (basereg_operand (op1
, GET_MODE(op1
)) !=
1071 basereg_operand (op2
, GET_MODE(op2
)));
1074 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1075 Return the length of the field, or <= 0 on failure. */
1078 ia64_depz_field_mask (rop
, rshift
)
1081 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
1082 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
1084 /* Get rid of the zero bits we're shifting in. */
1087 /* We must now have a solid block of 1's at bit 0. */
1088 return exact_log2 (op
+ 1);
1091 /* Expand a symbolic constant load. */
1094 ia64_expand_load_address (dest
, src
)
1097 if (tls_symbolic_operand (src
, VOIDmode
))
1099 if (GET_CODE (dest
) != REG
)
1102 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1103 having to pointer-extend the value afterward. Other forms of address
1104 computation below are also more natural to compute as 64-bit quantities.
1105 If we've been given an SImode destination register, change it. */
1106 if (GET_MODE (dest
) != Pmode
)
1107 dest
= gen_rtx_REG (Pmode
, REGNO (dest
));
1109 if (TARGET_AUTO_PIC
)
1111 emit_insn (gen_load_gprel64 (dest
, src
));
1114 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1116 emit_insn (gen_load_fptr (dest
, src
));
1119 else if (sdata_symbolic_operand (src
, VOIDmode
))
1121 emit_insn (gen_load_gprel (dest
, src
));
1125 if (GET_CODE (src
) == CONST
1126 && GET_CODE (XEXP (src
, 0)) == PLUS
1127 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
1128 && (INTVAL (XEXP (XEXP (src
, 0), 1)) & 0x1fff) != 0)
1130 rtx sym
= XEXP (XEXP (src
, 0), 0);
1131 HOST_WIDE_INT ofs
, hi
, lo
;
1133 /* Split the offset into a sign extended 14-bit low part
1134 and a complementary high part. */
1135 ofs
= INTVAL (XEXP (XEXP (src
, 0), 1));
1136 lo
= ((ofs
& 0x3fff) ^ 0x2000) - 0x2000;
1139 ia64_expand_load_address (dest
, plus_constant (sym
, hi
));
1140 emit_insn (gen_adddi3 (dest
, dest
, GEN_INT (lo
)));
1146 tmp
= gen_rtx_HIGH (Pmode
, src
);
1147 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1148 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1150 tmp
= gen_rtx_LO_SUM (GET_MODE (dest
), dest
, src
);
1151 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1155 static GTY(()) rtx gen_tls_tga
;
1160 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1164 static GTY(()) rtx thread_pointer_rtx
;
1166 gen_thread_pointer ()
1168 if (!thread_pointer_rtx
)
1170 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1171 RTX_UNCHANGING_P (thread_pointer_rtx
) = 1;
1173 return thread_pointer_rtx
;
1177 ia64_expand_tls_address (tls_kind
, op0
, op1
)
1178 enum tls_model tls_kind
;
1181 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1185 case TLS_MODEL_GLOBAL_DYNAMIC
:
1188 tga_op1
= gen_reg_rtx (Pmode
);
1189 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1190 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1191 RTX_UNCHANGING_P (tga_op1
) = 1;
1193 tga_op2
= gen_reg_rtx (Pmode
);
1194 emit_insn (gen_load_ltoff_dtprel (tga_op2
, op1
));
1195 tga_op2
= gen_rtx_MEM (Pmode
, tga_op2
);
1196 RTX_UNCHANGING_P (tga_op2
) = 1;
1198 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1199 LCT_CONST
, Pmode
, 2, tga_op1
,
1200 Pmode
, tga_op2
, Pmode
);
1202 insns
= get_insns ();
1205 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1208 case TLS_MODEL_LOCAL_DYNAMIC
:
1209 /* ??? This isn't the completely proper way to do local-dynamic
1210 If the call to __tls_get_addr is used only by a single symbol,
1211 then we should (somehow) move the dtprel to the second arg
1212 to avoid the extra add. */
1215 tga_op1
= gen_reg_rtx (Pmode
);
1216 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1217 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1218 RTX_UNCHANGING_P (tga_op1
) = 1;
1220 tga_op2
= const0_rtx
;
1222 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1223 LCT_CONST
, Pmode
, 2, tga_op1
,
1224 Pmode
, tga_op2
, Pmode
);
1226 insns
= get_insns ();
1229 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1231 tmp
= gen_reg_rtx (Pmode
);
1232 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1234 if (register_operand (op0
, Pmode
))
1237 tga_ret
= gen_reg_rtx (Pmode
);
1240 emit_insn (gen_load_dtprel (tga_ret
, op1
));
1241 emit_insn (gen_adddi3 (tga_ret
, tmp
, tga_ret
));
1244 emit_insn (gen_add_dtprel (tga_ret
, tmp
, op1
));
1246 return (tga_ret
== op0
? NULL_RTX
: tga_ret
);
1248 case TLS_MODEL_INITIAL_EXEC
:
1249 tmp
= gen_reg_rtx (Pmode
);
1250 emit_insn (gen_load_ltoff_tprel (tmp
, op1
));
1251 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1252 RTX_UNCHANGING_P (tmp
) = 1;
1253 tmp
= force_reg (Pmode
, tmp
);
1255 if (register_operand (op0
, Pmode
))
1258 op1
= gen_reg_rtx (Pmode
);
1259 emit_insn (gen_adddi3 (op1
, tmp
, gen_thread_pointer ()));
1261 return (op1
== op0
? NULL_RTX
: op1
);
1263 case TLS_MODEL_LOCAL_EXEC
:
1264 if (register_operand (op0
, Pmode
))
1267 tmp
= gen_reg_rtx (Pmode
);
1270 emit_insn (gen_load_tprel (tmp
, op1
));
1271 emit_insn (gen_adddi3 (tmp
, gen_thread_pointer (), tmp
));
1274 emit_insn (gen_add_tprel (tmp
, gen_thread_pointer (), op1
));
1276 return (tmp
== op0
? NULL_RTX
: tmp
);
1284 ia64_expand_move (op0
, op1
)
1287 enum machine_mode mode
= GET_MODE (op0
);
1289 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1290 op1
= force_reg (mode
, op1
);
1292 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1294 enum tls_model tls_kind
;
1295 if ((tls_kind
= tls_symbolic_operand (op1
, VOIDmode
)))
1296 return ia64_expand_tls_address (tls_kind
, op0
, op1
);
1298 if (!TARGET_NO_PIC
&& reload_completed
)
1300 ia64_expand_load_address (op0
, op1
);
1308 /* Split a move from OP1 to OP0 conditional on COND. */
1311 ia64_emit_cond_move (op0
, op1
, cond
)
1314 rtx insn
, first
= get_last_insn ();
1316 emit_move_insn (op0
, op1
);
1318 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1320 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1324 /* Split a post-reload TImode reference into two DImode components. */
1327 ia64_split_timode (out
, in
, scratch
)
1331 switch (GET_CODE (in
))
1334 out
[0] = gen_rtx_REG (DImode
, REGNO (in
));
1335 out
[1] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1340 rtx base
= XEXP (in
, 0);
1342 switch (GET_CODE (base
))
1345 out
[0] = adjust_address (in
, DImode
, 0);
1348 base
= XEXP (base
, 0);
1349 out
[0] = adjust_address (in
, DImode
, 0);
1352 /* Since we're changing the mode, we need to change to POST_MODIFY
1353 as well to preserve the size of the increment. Either that or
1354 do the update in two steps, but we've already got this scratch
1355 register handy so let's use it. */
1357 base
= XEXP (base
, 0);
1359 = change_address (in
, DImode
,
1361 (Pmode
, base
, plus_constant (base
, 16)));
1364 base
= XEXP (base
, 0);
1366 = change_address (in
, DImode
,
1368 (Pmode
, base
, plus_constant (base
, -16)));
1374 if (scratch
== NULL_RTX
)
1376 out
[1] = change_address (in
, DImode
, scratch
);
1377 return gen_adddi3 (scratch
, base
, GEN_INT (8));
1382 split_double (in
, &out
[0], &out
[1]);
1390 /* ??? Fixing GR->FR TFmode moves during reload is hard. You need to go
1391 through memory plus an extra GR scratch register. Except that you can
1392 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1393 SECONDARY_RELOAD_CLASS, but not both.
1395 We got into problems in the first place by allowing a construct like
1396 (subreg:TF (reg:TI)), which we got from a union containing a long double.
1397 This solution attempts to prevent this situation from occurring. When
1398 we see something like the above, we spill the inner register to memory. */
1401 spill_tfmode_operand (in
, force
)
1405 if (GET_CODE (in
) == SUBREG
1406 && GET_MODE (SUBREG_REG (in
)) == TImode
1407 && GET_CODE (SUBREG_REG (in
)) == REG
)
1409 rtx mem
= gen_mem_addressof (SUBREG_REG (in
), NULL_TREE
, /*rescan=*/true);
1410 return gen_rtx_MEM (TFmode
, copy_to_reg (XEXP (mem
, 0)));
1412 else if (force
&& GET_CODE (in
) == REG
)
1414 rtx mem
= gen_mem_addressof (in
, NULL_TREE
, /*rescan=*/true);
1415 return gen_rtx_MEM (TFmode
, copy_to_reg (XEXP (mem
, 0)));
1417 else if (GET_CODE (in
) == MEM
1418 && GET_CODE (XEXP (in
, 0)) == ADDRESSOF
)
1419 return change_address (in
, TFmode
, copy_to_reg (XEXP (in
, 0)));
1424 /* Emit comparison instruction if necessary, returning the expression
1425 that holds the compare result in the proper mode. */
1428 ia64_expand_compare (code
, mode
)
1430 enum machine_mode mode
;
1432 rtx op0
= ia64_compare_op0
, op1
= ia64_compare_op1
;
1435 /* If we have a BImode input, then we already have a compare result, and
1436 do not need to emit another comparison. */
1437 if (GET_MODE (op0
) == BImode
)
1439 if ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
)
1446 cmp
= gen_reg_rtx (BImode
);
1447 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1448 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
)));
1452 return gen_rtx_fmt_ee (code
, mode
, cmp
, const0_rtx
);
1455 /* Emit the appropriate sequence for a call. */
1458 ia64_expand_call (retval
, addr
, nextarg
, sibcall_p
)
1461 rtx nextarg ATTRIBUTE_UNUSED
;
1466 addr
= XEXP (addr
, 0);
1467 b0
= gen_rtx_REG (DImode
, R_BR (0));
1469 /* ??? Should do this for functions known to bind local too. */
1470 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
1473 insn
= gen_sibcall_nogp (addr
);
1475 insn
= gen_call_nogp (addr
, b0
);
1477 insn
= gen_call_value_nogp (retval
, addr
, b0
);
1478 insn
= emit_call_insn (insn
);
1483 insn
= gen_sibcall_gp (addr
);
1485 insn
= gen_call_gp (addr
, b0
);
1487 insn
= gen_call_value_gp (retval
, addr
, b0
);
1488 insn
= emit_call_insn (insn
);
1490 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
1495 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
1496 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
1497 gen_rtx_REG (DImode
, AR_PFS_REGNUM
));
1506 if (current_frame_info
.reg_save_gp
)
1507 tmp
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_gp
);
1510 HOST_WIDE_INT offset
;
1512 offset
= (current_frame_info
.spill_cfa_off
1513 + current_frame_info
.spill_size
);
1514 if (frame_pointer_needed
)
1516 tmp
= hard_frame_pointer_rtx
;
1521 tmp
= stack_pointer_rtx
;
1522 offset
= current_frame_info
.total_size
- offset
;
1525 if (CONST_OK_FOR_I (offset
))
1526 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1527 tmp
, GEN_INT (offset
)));
1530 emit_move_insn (pic_offset_table_rtx
, GEN_INT (offset
));
1531 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1532 pic_offset_table_rtx
, tmp
));
1535 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
1538 emit_move_insn (pic_offset_table_rtx
, tmp
);
1542 ia64_split_call (retval
, addr
, retaddr
, scratch_r
, scratch_b
,
1543 noreturn_p
, sibcall_p
)
1544 rtx retval
, addr
, retaddr
, scratch_r
, scratch_b
;
1545 int noreturn_p
, sibcall_p
;
1548 bool is_desc
= false;
1550 /* If we find we're calling through a register, then we're actually
1551 calling through a descriptor, so load up the values. */
1557 /* ??? We are currently constrained to *not* use peep2, because
1558 we can legitimiately change the global lifetime of the GP
1559 (in the form of killing where previously live). This is
1560 because a call through a descriptor doesn't use the previous
1561 value of the GP, while a direct call does, and we do not
1562 commit to either form until the split here.
1564 That said, this means that we lack precise life info for
1565 whether ADDR is dead after this call. This is not terribly
1566 important, since we can fix things up essentially for free
1567 with the POST_DEC below, but it's nice to not use it when we
1568 can immediately tell it's not necessary. */
1569 addr_dead_p
= ((noreturn_p
|| sibcall_p
1570 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
1572 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
1574 /* Load the code address into scratch_b. */
1575 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
1576 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1577 emit_move_insn (scratch_r
, tmp
);
1578 emit_move_insn (scratch_b
, scratch_r
);
1580 /* Load the GP address. If ADDR is not dead here, then we must
1581 revert the change made above via the POST_INCREMENT. */
1583 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
1586 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1587 emit_move_insn (pic_offset_table_rtx
, tmp
);
1594 insn
= gen_sibcall_nogp (addr
);
1596 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
1598 insn
= gen_call_nogp (addr
, retaddr
);
1599 emit_call_insn (insn
);
1601 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
1605 /* Begin the assembly file. */
1608 emit_safe_across_calls (f
)
1611 unsigned int rs
, re
;
1618 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
1622 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
1626 fputs ("\t.pred.safe_across_calls ", f
);
1632 fprintf (f
, "p%u", rs
);
1634 fprintf (f
, "p%u-p%u", rs
, re
- 1);
1641 /* Helper function for ia64_compute_frame_size: find an appropriate general
1642 register to spill some special register to. SPECIAL_SPILL_MASK contains
1643 bits in GR0 to GR31 that have already been allocated by this routine.
1644 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1647 find_gr_spill (try_locals
)
1652 /* If this is a leaf function, first try an otherwise unused
1653 call-clobbered register. */
1654 if (current_function_is_leaf
)
1656 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1657 if (! regs_ever_live
[regno
]
1658 && call_used_regs
[regno
]
1659 && ! fixed_regs
[regno
]
1660 && ! global_regs
[regno
]
1661 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1663 current_frame_info
.gr_used_mask
|= 1 << regno
;
1670 regno
= current_frame_info
.n_local_regs
;
1671 /* If there is a frame pointer, then we can't use loc79, because
1672 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1673 reg_name switching code in ia64_expand_prologue. */
1674 if (regno
< (80 - frame_pointer_needed
))
1676 current_frame_info
.n_local_regs
= regno
+ 1;
1677 return LOC_REG (0) + regno
;
1681 /* Failed to find a general register to spill to. Must use stack. */
1685 /* In order to make for nice schedules, we try to allocate every temporary
1686 to a different register. We must of course stay away from call-saved,
1687 fixed, and global registers. We must also stay away from registers
1688 allocated in current_frame_info.gr_used_mask, since those include regs
1689 used all through the prologue.
1691 Any register allocated here must be used immediately. The idea is to
1692 aid scheduling, not to solve data flow problems. */
1694 static int last_scratch_gr_reg
;
1697 next_scratch_gr_reg ()
1701 for (i
= 0; i
< 32; ++i
)
1703 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
1704 if (call_used_regs
[regno
]
1705 && ! fixed_regs
[regno
]
1706 && ! global_regs
[regno
]
1707 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1709 last_scratch_gr_reg
= regno
;
1714 /* There must be _something_ available. */
1718 /* Helper function for ia64_compute_frame_size, called through
1719 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
1722 mark_reg_gr_used_mask (reg
, data
)
1724 void *data ATTRIBUTE_UNUSED
;
1726 unsigned int regno
= REGNO (reg
);
1729 unsigned int i
, n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
1730 for (i
= 0; i
< n
; ++i
)
1731 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
1735 /* Returns the number of bytes offset between the frame pointer and the stack
1736 pointer for the current function. SIZE is the number of bytes of space
1737 needed for local variables. */
1740 ia64_compute_frame_size (size
)
1743 HOST_WIDE_INT total_size
;
1744 HOST_WIDE_INT spill_size
= 0;
1745 HOST_WIDE_INT extra_spill_size
= 0;
1746 HOST_WIDE_INT pretend_args_size
;
1749 int spilled_gr_p
= 0;
1750 int spilled_fr_p
= 0;
1754 if (current_frame_info
.initialized
)
1757 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
1758 CLEAR_HARD_REG_SET (mask
);
1760 /* Don't allocate scratches to the return register. */
1761 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
1763 /* Don't allocate scratches to the EH scratch registers. */
1764 if (cfun
->machine
->ia64_eh_epilogue_sp
)
1765 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
1766 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
1767 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
1769 /* Find the size of the register stack frame. We have only 80 local
1770 registers, because we reserve 8 for the inputs and 8 for the
1773 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
1774 since we'll be adjusting that down later. */
1775 regno
= LOC_REG (78) + ! frame_pointer_needed
;
1776 for (; regno
>= LOC_REG (0); regno
--)
1777 if (regs_ever_live
[regno
])
1779 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
1781 /* For functions marked with the syscall_linkage attribute, we must mark
1782 all eight input registers as in use, so that locals aren't visible to
1785 if (cfun
->machine
->n_varargs
> 0
1786 || lookup_attribute ("syscall_linkage",
1787 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
1788 current_frame_info
.n_input_regs
= 8;
1791 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
1792 if (regs_ever_live
[regno
])
1794 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
1797 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
1798 if (regs_ever_live
[regno
])
1800 i
= regno
- OUT_REG (0) + 1;
1802 /* When -p profiling, we need one output register for the mcount argument.
1803 Likewise for -a profiling for the bb_init_func argument. For -ax
1804 profiling, we need two output registers for the two bb_init_trace_func
1806 if (current_function_profile
)
1808 current_frame_info
.n_output_regs
= i
;
1810 /* ??? No rotating register support yet. */
1811 current_frame_info
.n_rotate_regs
= 0;
1813 /* Discover which registers need spilling, and how much room that
1814 will take. Begin with floating point and general registers,
1815 which will always wind up on the stack. */
1817 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
1818 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1820 SET_HARD_REG_BIT (mask
, regno
);
1826 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1827 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1829 SET_HARD_REG_BIT (mask
, regno
);
1835 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
1836 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1838 SET_HARD_REG_BIT (mask
, regno
);
1843 /* Now come all special registers that might get saved in other
1844 general registers. */
1846 if (frame_pointer_needed
)
1848 current_frame_info
.reg_fp
= find_gr_spill (1);
1849 /* If we did not get a register, then we take LOC79. This is guaranteed
1850 to be free, even if regs_ever_live is already set, because this is
1851 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
1852 as we don't count loc79 above. */
1853 if (current_frame_info
.reg_fp
== 0)
1855 current_frame_info
.reg_fp
= LOC_REG (79);
1856 current_frame_info
.n_local_regs
++;
1860 if (! current_function_is_leaf
)
1862 /* Emit a save of BR0 if we call other functions. Do this even
1863 if this function doesn't return, as EH depends on this to be
1864 able to unwind the stack. */
1865 SET_HARD_REG_BIT (mask
, BR_REG (0));
1867 current_frame_info
.reg_save_b0
= find_gr_spill (1);
1868 if (current_frame_info
.reg_save_b0
== 0)
1874 /* Similarly for ar.pfs. */
1875 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
1876 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
1877 if (current_frame_info
.reg_save_ar_pfs
== 0)
1879 extra_spill_size
+= 8;
1883 /* Similarly for gp. Note that if we're calling setjmp, the stacked
1884 registers are clobbered, so we fall back to the stack. */
1885 current_frame_info
.reg_save_gp
1886 = (current_function_calls_setjmp
? 0 : find_gr_spill (1));
1887 if (current_frame_info
.reg_save_gp
== 0)
1889 SET_HARD_REG_BIT (mask
, GR_REG (1));
1896 if (regs_ever_live
[BR_REG (0)] && ! call_used_regs
[BR_REG (0)])
1898 SET_HARD_REG_BIT (mask
, BR_REG (0));
1903 if (regs_ever_live
[AR_PFS_REGNUM
])
1905 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
1906 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
1907 if (current_frame_info
.reg_save_ar_pfs
== 0)
1909 extra_spill_size
+= 8;
1915 /* Unwind descriptor hackery: things are most efficient if we allocate
1916 consecutive GR save registers for RP, PFS, FP in that order. However,
1917 it is absolutely critical that FP get the only hard register that's
1918 guaranteed to be free, so we allocated it first. If all three did
1919 happen to be allocated hard regs, and are consecutive, rearrange them
1920 into the preferred order now. */
1921 if (current_frame_info
.reg_fp
!= 0
1922 && current_frame_info
.reg_save_b0
== current_frame_info
.reg_fp
+ 1
1923 && current_frame_info
.reg_save_ar_pfs
== current_frame_info
.reg_fp
+ 2)
1925 current_frame_info
.reg_save_b0
= current_frame_info
.reg_fp
;
1926 current_frame_info
.reg_save_ar_pfs
= current_frame_info
.reg_fp
+ 1;
1927 current_frame_info
.reg_fp
= current_frame_info
.reg_fp
+ 2;
1930 /* See if we need to store the predicate register block. */
1931 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
1932 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1934 if (regno
<= PR_REG (63))
1936 SET_HARD_REG_BIT (mask
, PR_REG (0));
1937 current_frame_info
.reg_save_pr
= find_gr_spill (1);
1938 if (current_frame_info
.reg_save_pr
== 0)
1940 extra_spill_size
+= 8;
1944 /* ??? Mark them all as used so that register renaming and such
1945 are free to use them. */
1946 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
1947 regs_ever_live
[regno
] = 1;
1950 /* If we're forced to use st8.spill, we're forced to save and restore
1951 ar.unat as well. The check for existing liveness allows inline asm
1952 to touch ar.unat. */
1953 if (spilled_gr_p
|| cfun
->machine
->n_varargs
1954 || regs_ever_live
[AR_UNAT_REGNUM
])
1956 regs_ever_live
[AR_UNAT_REGNUM
] = 1;
1957 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
1958 current_frame_info
.reg_save_ar_unat
= find_gr_spill (spill_size
== 0);
1959 if (current_frame_info
.reg_save_ar_unat
== 0)
1961 extra_spill_size
+= 8;
1966 if (regs_ever_live
[AR_LC_REGNUM
])
1968 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
1969 current_frame_info
.reg_save_ar_lc
= find_gr_spill (spill_size
== 0);
1970 if (current_frame_info
.reg_save_ar_lc
== 0)
1972 extra_spill_size
+= 8;
1977 /* If we have an odd number of words of pretend arguments written to
1978 the stack, then the FR save area will be unaligned. We round the
1979 size of this area up to keep things 16 byte aligned. */
1981 pretend_args_size
= IA64_STACK_ALIGN (current_function_pretend_args_size
);
1983 pretend_args_size
= current_function_pretend_args_size
;
1985 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
1986 + current_function_outgoing_args_size
);
1987 total_size
= IA64_STACK_ALIGN (total_size
);
1989 /* We always use the 16-byte scratch area provided by the caller, but
1990 if we are a leaf function, there's no one to which we need to provide
1992 if (current_function_is_leaf
)
1993 total_size
= MAX (0, total_size
- 16);
1995 current_frame_info
.total_size
= total_size
;
1996 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
1997 current_frame_info
.spill_size
= spill_size
;
1998 current_frame_info
.extra_spill_size
= extra_spill_size
;
1999 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2000 current_frame_info
.n_spilled
= n_spilled
;
2001 current_frame_info
.initialized
= reload_completed
;
2004 /* Compute the initial difference between the specified pair of registers. */
2007 ia64_initial_elimination_offset (from
, to
)
2010 HOST_WIDE_INT offset
;
2012 ia64_compute_frame_size (get_frame_size ());
2015 case FRAME_POINTER_REGNUM
:
2016 if (to
== HARD_FRAME_POINTER_REGNUM
)
2018 if (current_function_is_leaf
)
2019 offset
= -current_frame_info
.total_size
;
2021 offset
= -(current_frame_info
.total_size
2022 - current_function_outgoing_args_size
- 16);
2024 else if (to
== STACK_POINTER_REGNUM
)
2026 if (current_function_is_leaf
)
2029 offset
= 16 + current_function_outgoing_args_size
;
2035 case ARG_POINTER_REGNUM
:
2036 /* Arguments start above the 16 byte save area, unless stdarg
2037 in which case we store through the 16 byte save area. */
2038 if (to
== HARD_FRAME_POINTER_REGNUM
)
2039 offset
= 16 - current_function_pretend_args_size
;
2040 else if (to
== STACK_POINTER_REGNUM
)
2041 offset
= (current_frame_info
.total_size
2042 + 16 - current_function_pretend_args_size
);
2047 case RETURN_ADDRESS_POINTER_REGNUM
:
2058 /* If there are more than a trivial number of register spills, we use
2059 two interleaved iterators so that we can get two memory references
2062 In order to simplify things in the prologue and epilogue expanders,
2063 we use helper functions to fix up the memory references after the
2064 fact with the appropriate offsets to a POST_MODIFY memory mode.
2065 The following data structure tracks the state of the two iterators
2066 while insns are being emitted. */
2068 struct spill_fill_data
2070 rtx init_after
; /* point at which to emit initializations */
2071 rtx init_reg
[2]; /* initial base register */
2072 rtx iter_reg
[2]; /* the iterator registers */
2073 rtx
*prev_addr
[2]; /* address of last memory use */
2074 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2075 HOST_WIDE_INT prev_off
[2]; /* last offset */
2076 int n_iter
; /* number of iterators in use */
2077 int next_iter
; /* next iterator to use */
2078 unsigned int save_gr_used_mask
;
2081 static struct spill_fill_data spill_fill_data
;
2084 setup_spill_pointers (n_spills
, init_reg
, cfa_off
)
2087 HOST_WIDE_INT cfa_off
;
2091 spill_fill_data
.init_after
= get_last_insn ();
2092 spill_fill_data
.init_reg
[0] = init_reg
;
2093 spill_fill_data
.init_reg
[1] = init_reg
;
2094 spill_fill_data
.prev_addr
[0] = NULL
;
2095 spill_fill_data
.prev_addr
[1] = NULL
;
2096 spill_fill_data
.prev_insn
[0] = NULL
;
2097 spill_fill_data
.prev_insn
[1] = NULL
;
2098 spill_fill_data
.prev_off
[0] = cfa_off
;
2099 spill_fill_data
.prev_off
[1] = cfa_off
;
2100 spill_fill_data
.next_iter
= 0;
2101 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
2103 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
2104 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
2106 int regno
= next_scratch_gr_reg ();
2107 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
2108 current_frame_info
.gr_used_mask
|= 1 << regno
;
2113 finish_spill_pointers ()
2115 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
2119 spill_restore_mem (reg
, cfa_off
)
2121 HOST_WIDE_INT cfa_off
;
2123 int iter
= spill_fill_data
.next_iter
;
2124 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
2125 rtx disp_rtx
= GEN_INT (disp
);
2128 if (spill_fill_data
.prev_addr
[iter
])
2130 if (CONST_OK_FOR_N (disp
))
2132 *spill_fill_data
.prev_addr
[iter
]
2133 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
2134 gen_rtx_PLUS (DImode
,
2135 spill_fill_data
.iter_reg
[iter
],
2137 REG_NOTES (spill_fill_data
.prev_insn
[iter
])
2138 = gen_rtx_EXPR_LIST (REG_INC
, spill_fill_data
.iter_reg
[iter
],
2139 REG_NOTES (spill_fill_data
.prev_insn
[iter
]));
2143 /* ??? Could use register post_modify for loads. */
2144 if (! CONST_OK_FOR_I (disp
))
2146 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2147 emit_move_insn (tmp
, disp_rtx
);
2150 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2151 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
2154 /* Micro-optimization: if we've created a frame pointer, it's at
2155 CFA 0, which may allow the real iterator to be initialized lower,
2156 slightly increasing parallelism. Also, if there are few saves
2157 it may eliminate the iterator entirely. */
2159 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
2160 && frame_pointer_needed
)
2162 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
2163 set_mem_alias_set (mem
, get_varargs_alias_set ());
2171 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
2172 spill_fill_data
.init_reg
[iter
]);
2177 if (! CONST_OK_FOR_I (disp
))
2179 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2180 emit_move_insn (tmp
, disp_rtx
);
2184 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2185 spill_fill_data
.init_reg
[iter
],
2192 /* Careful for being the first insn in a sequence. */
2193 if (spill_fill_data
.init_after
)
2194 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
2197 rtx first
= get_insns ();
2199 insn
= emit_insn_before (seq
, first
);
2201 insn
= emit_insn (seq
);
2203 spill_fill_data
.init_after
= insn
;
2205 /* If DISP is 0, we may or may not have a further adjustment
2206 afterward. If we do, then the load/store insn may be modified
2207 to be a post-modify. If we don't, then this copy may be
2208 eliminated by copyprop_hardreg_forward, which makes this
2209 insn garbage, which runs afoul of the sanity check in
2210 propagate_one_insn. So mark this insn as legal to delete. */
2212 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
2216 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
2218 /* ??? Not all of the spills are for varargs, but some of them are.
2219 The rest of the spills belong in an alias set of their own. But
2220 it doesn't actually hurt to include them here. */
2221 set_mem_alias_set (mem
, get_varargs_alias_set ());
2223 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
2224 spill_fill_data
.prev_off
[iter
] = cfa_off
;
2226 if (++iter
>= spill_fill_data
.n_iter
)
2228 spill_fill_data
.next_iter
= iter
;
2234 do_spill (move_fn
, reg
, cfa_off
, frame_reg
)
2235 rtx (*move_fn
) PARAMS ((rtx
, rtx
, rtx
));
2237 HOST_WIDE_INT cfa_off
;
2239 int iter
= spill_fill_data
.next_iter
;
2242 mem
= spill_restore_mem (reg
, cfa_off
);
2243 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
2244 spill_fill_data
.prev_insn
[iter
] = insn
;
2251 RTX_FRAME_RELATED_P (insn
) = 1;
2253 /* Don't even pretend that the unwind code can intuit its way
2254 through a pair of interleaved post_modify iterators. Just
2255 provide the correct answer. */
2257 if (frame_pointer_needed
)
2259 base
= hard_frame_pointer_rtx
;
2264 base
= stack_pointer_rtx
;
2265 off
= current_frame_info
.total_size
- cfa_off
;
2269 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2270 gen_rtx_SET (VOIDmode
,
2271 gen_rtx_MEM (GET_MODE (reg
),
2272 plus_constant (base
, off
)),
2279 do_restore (move_fn
, reg
, cfa_off
)
2280 rtx (*move_fn
) PARAMS ((rtx
, rtx
, rtx
));
2282 HOST_WIDE_INT cfa_off
;
2284 int iter
= spill_fill_data
.next_iter
;
2287 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
2288 GEN_INT (cfa_off
)));
2289 spill_fill_data
.prev_insn
[iter
] = insn
;
2292 /* Wrapper functions that discards the CONST_INT spill offset. These
2293 exist so that we can give gr_spill/gr_fill the offset they need and
2294 use a consistent function interface. */
2297 gen_movdi_x (dest
, src
, offset
)
2299 rtx offset ATTRIBUTE_UNUSED
;
2301 return gen_movdi (dest
, src
);
2305 gen_fr_spill_x (dest
, src
, offset
)
2307 rtx offset ATTRIBUTE_UNUSED
;
2309 return gen_fr_spill (dest
, src
);
2313 gen_fr_restore_x (dest
, src
, offset
)
2315 rtx offset ATTRIBUTE_UNUSED
;
2317 return gen_fr_restore (dest
, src
);
2320 /* Called after register allocation to add any instructions needed for the
2321 prologue. Using a prologue insn is favored compared to putting all of the
2322 instructions in output_function_prologue(), since it allows the scheduler
2323 to intermix instructions with the saves of the caller saved registers. In
2324 some cases, it might be necessary to emit a barrier instruction as the last
2325 insn to prevent such scheduling.
2327 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2328 so that the debug info generation code can handle them properly.
2330 The register save area is layed out like so:
2332 [ varargs spill area ]
2333 [ fr register spill area ]
2334 [ br register spill area ]
2335 [ ar register spill area ]
2336 [ pr register spill area ]
2337 [ gr register spill area ] */
2339 /* ??? Get inefficient code when the frame size is larger than can fit in an
2340 adds instruction. */
2343 ia64_expand_prologue ()
2345 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
2346 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
2349 ia64_compute_frame_size (get_frame_size ());
2350 last_scratch_gr_reg
= 15;
2352 /* If there is no epilogue, then we don't need some prologue insns.
2353 We need to avoid emitting the dead prologue insns, because flow
2354 will complain about them. */
2359 for (e
= EXIT_BLOCK_PTR
->pred
; e
; e
= e
->pred_next
)
2360 if ((e
->flags
& EDGE_FAKE
) == 0
2361 && (e
->flags
& EDGE_FALLTHRU
) != 0)
2363 epilogue_p
= (e
!= NULL
);
2368 /* Set the local, input, and output register names. We need to do this
2369 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2370 half. If we use in/loc/out register names, then we get assembler errors
2371 in crtn.S because there is no alloc insn or regstk directive in there. */
2372 if (! TARGET_REG_NAMES
)
2374 int inputs
= current_frame_info
.n_input_regs
;
2375 int locals
= current_frame_info
.n_local_regs
;
2376 int outputs
= current_frame_info
.n_output_regs
;
2378 for (i
= 0; i
< inputs
; i
++)
2379 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
2380 for (i
= 0; i
< locals
; i
++)
2381 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
2382 for (i
= 0; i
< outputs
; i
++)
2383 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
2386 /* Set the frame pointer register name. The regnum is logically loc79,
2387 but of course we'll not have allocated that many locals. Rather than
2388 worrying about renumbering the existing rtxs, we adjust the name. */
2389 /* ??? This code means that we can never use one local register when
2390 there is a frame pointer. loc79 gets wasted in this case, as it is
2391 renamed to a register that will never be used. See also the try_locals
2392 code in find_gr_spill. */
2393 if (current_frame_info
.reg_fp
)
2395 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
2396 reg_names
[HARD_FRAME_POINTER_REGNUM
]
2397 = reg_names
[current_frame_info
.reg_fp
];
2398 reg_names
[current_frame_info
.reg_fp
] = tmp
;
2401 /* Fix up the return address placeholder. */
2402 /* ??? We can fail if __builtin_return_address is used, and we didn't
2403 allocate a register in which to save b0. I can't think of a way to
2404 eliminate RETURN_ADDRESS_POINTER_REGNUM to a local register and
2405 then be sure that I got the right one. Further, reload doesn't seem
2406 to care if an eliminable register isn't used, and "eliminates" it
2408 if (regs_ever_live
[RETURN_ADDRESS_POINTER_REGNUM
]
2409 && current_frame_info
.reg_save_b0
!= 0)
2410 XINT (return_address_pointer_rtx
, 0) = current_frame_info
.reg_save_b0
;
2412 /* We don't need an alloc instruction if we've used no outputs or locals. */
2413 if (current_frame_info
.n_local_regs
== 0
2414 && current_frame_info
.n_output_regs
== 0
2415 && current_frame_info
.n_input_regs
<= current_function_args_info
.int_regs
2416 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2418 /* If there is no alloc, but there are input registers used, then we
2419 need a .regstk directive. */
2420 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
2421 ar_pfs_save_reg
= NULL_RTX
;
2425 current_frame_info
.need_regstk
= 0;
2427 if (current_frame_info
.reg_save_ar_pfs
)
2428 regno
= current_frame_info
.reg_save_ar_pfs
;
2430 regno
= next_scratch_gr_reg ();
2431 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
2433 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
2434 GEN_INT (current_frame_info
.n_input_regs
),
2435 GEN_INT (current_frame_info
.n_local_regs
),
2436 GEN_INT (current_frame_info
.n_output_regs
),
2437 GEN_INT (current_frame_info
.n_rotate_regs
)));
2438 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_pfs
!= 0);
2441 /* Set up frame pointer, stack pointer, and spill iterators. */
2443 n_varargs
= cfun
->machine
->n_varargs
;
2444 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
2445 stack_pointer_rtx
, 0);
2447 if (frame_pointer_needed
)
2449 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2450 RTX_FRAME_RELATED_P (insn
) = 1;
2453 if (current_frame_info
.total_size
!= 0)
2455 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
2458 if (CONST_OK_FOR_I (- current_frame_info
.total_size
))
2459 offset
= frame_size_rtx
;
2462 regno
= next_scratch_gr_reg ();
2463 offset
= gen_rtx_REG (DImode
, regno
);
2464 emit_move_insn (offset
, frame_size_rtx
);
2467 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
2468 stack_pointer_rtx
, offset
));
2470 if (! frame_pointer_needed
)
2472 RTX_FRAME_RELATED_P (insn
) = 1;
2473 if (GET_CODE (offset
) != CONST_INT
)
2476 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2477 gen_rtx_SET (VOIDmode
,
2479 gen_rtx_PLUS (DImode
,
2486 /* ??? At this point we must generate a magic insn that appears to
2487 modify the stack pointer, the frame pointer, and all spill
2488 iterators. This would allow the most scheduling freedom. For
2489 now, just hard stop. */
2490 emit_insn (gen_blockage ());
2493 /* Must copy out ar.unat before doing any integer spills. */
2494 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2496 if (current_frame_info
.reg_save_ar_unat
)
2498 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2501 alt_regno
= next_scratch_gr_reg ();
2502 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2503 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2506 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2507 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
2508 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_unat
!= 0);
2510 /* Even if we're not going to generate an epilogue, we still
2511 need to save the register so that EH works. */
2512 if (! epilogue_p
&& current_frame_info
.reg_save_ar_unat
)
2513 emit_insn (gen_prologue_use (ar_unat_save_reg
));
2516 ar_unat_save_reg
= NULL_RTX
;
2518 /* Spill all varargs registers. Do this before spilling any GR registers,
2519 since we want the UNAT bits for the GR registers to override the UNAT
2520 bits from varargs, which we don't care about. */
2523 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
2525 reg
= gen_rtx_REG (DImode
, regno
);
2526 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
2529 /* Locate the bottom of the register save area. */
2530 cfa_off
= (current_frame_info
.spill_cfa_off
2531 + current_frame_info
.spill_size
2532 + current_frame_info
.extra_spill_size
);
2534 /* Save the predicate register block either in a register or in memory. */
2535 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2537 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2538 if (current_frame_info
.reg_save_pr
!= 0)
2540 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2541 insn
= emit_move_insn (alt_reg
, reg
);
2543 /* ??? Denote pr spill/fill by a DImode move that modifies all
2544 64 hard registers. */
2545 RTX_FRAME_RELATED_P (insn
) = 1;
2547 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2548 gen_rtx_SET (VOIDmode
, alt_reg
, reg
),
2551 /* Even if we're not going to generate an epilogue, we still
2552 need to save the register so that EH works. */
2554 emit_insn (gen_prologue_use (alt_reg
));
2558 alt_regno
= next_scratch_gr_reg ();
2559 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2560 insn
= emit_move_insn (alt_reg
, reg
);
2561 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2566 /* Handle AR regs in numerical order. All of them get special handling. */
2567 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
2568 && current_frame_info
.reg_save_ar_unat
== 0)
2570 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2571 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
2575 /* The alloc insn already copied ar.pfs into a general register. The
2576 only thing we have to do now is copy that register to a stack slot
2577 if we'd not allocated a local register for the job. */
2578 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
2579 && current_frame_info
.reg_save_ar_pfs
== 0)
2581 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2582 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
2586 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2588 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2589 if (current_frame_info
.reg_save_ar_lc
!= 0)
2591 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2592 insn
= emit_move_insn (alt_reg
, reg
);
2593 RTX_FRAME_RELATED_P (insn
) = 1;
2595 /* Even if we're not going to generate an epilogue, we still
2596 need to save the register so that EH works. */
2598 emit_insn (gen_prologue_use (alt_reg
));
2602 alt_regno
= next_scratch_gr_reg ();
2603 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2604 emit_move_insn (alt_reg
, reg
);
2605 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2610 if (current_frame_info
.reg_save_gp
)
2612 insn
= emit_move_insn (gen_rtx_REG (DImode
,
2613 current_frame_info
.reg_save_gp
),
2614 pic_offset_table_rtx
);
2615 /* We don't know for sure yet if this is actually needed, since
2616 we've not split the PIC call patterns. If all of the calls
2617 are indirect, and not followed by any uses of the gp, then
2618 this save is dead. Allow it to go away. */
2620 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, REG_NOTES (insn
));
2623 /* We should now be at the base of the gr/br/fr spill area. */
2624 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2625 + current_frame_info
.spill_size
))
2628 /* Spill all general registers. */
2629 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
2630 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2632 reg
= gen_rtx_REG (DImode
, regno
);
2633 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
2637 /* Handle BR0 specially -- it may be getting stored permanently in
2638 some GR register. */
2639 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2641 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2642 if (current_frame_info
.reg_save_b0
!= 0)
2644 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2645 insn
= emit_move_insn (alt_reg
, reg
);
2646 RTX_FRAME_RELATED_P (insn
) = 1;
2648 /* Even if we're not going to generate an epilogue, we still
2649 need to save the register so that EH works. */
2651 emit_insn (gen_prologue_use (alt_reg
));
2655 alt_regno
= next_scratch_gr_reg ();
2656 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2657 emit_move_insn (alt_reg
, reg
);
2658 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2663 /* Spill the rest of the BR registers. */
2664 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2665 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2667 alt_regno
= next_scratch_gr_reg ();
2668 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2669 reg
= gen_rtx_REG (DImode
, regno
);
2670 emit_move_insn (alt_reg
, reg
);
2671 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2675 /* Align the frame and spill all FR registers. */
2676 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2677 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2681 reg
= gen_rtx_REG (TFmode
, regno
);
2682 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
2686 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2689 finish_spill_pointers ();
2692 /* Called after register allocation to add any instructions needed for the
2693 epilogue. Using an epilogue insn is favored compared to putting all of the
2694 instructions in output_function_prologue(), since it allows the scheduler
2695 to intermix instructions with the saves of the caller saved registers. In
2696 some cases, it might be necessary to emit a barrier instruction as the last
2697 insn to prevent such scheduling. */
2700 ia64_expand_epilogue (sibcall_p
)
2703 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
2704 int regno
, alt_regno
, cfa_off
;
2706 ia64_compute_frame_size (get_frame_size ());
2708 /* If there is a frame pointer, then we use it instead of the stack
2709 pointer, so that the stack pointer does not need to be valid when
2710 the epilogue starts. See EXIT_IGNORE_STACK. */
2711 if (frame_pointer_needed
)
2712 setup_spill_pointers (current_frame_info
.n_spilled
,
2713 hard_frame_pointer_rtx
, 0);
2715 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
2716 current_frame_info
.total_size
);
2718 if (current_frame_info
.total_size
!= 0)
2720 /* ??? At this point we must generate a magic insn that appears to
2721 modify the spill iterators and the frame pointer. This would
2722 allow the most scheduling freedom. For now, just hard stop. */
2723 emit_insn (gen_blockage ());
2726 /* Locate the bottom of the register save area. */
2727 cfa_off
= (current_frame_info
.spill_cfa_off
2728 + current_frame_info
.spill_size
2729 + current_frame_info
.extra_spill_size
);
2731 /* Restore the predicate registers. */
2732 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2734 if (current_frame_info
.reg_save_pr
!= 0)
2735 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2738 alt_regno
= next_scratch_gr_reg ();
2739 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2740 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2743 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2744 emit_move_insn (reg
, alt_reg
);
2747 /* Restore the application registers. */
2749 /* Load the saved unat from the stack, but do not restore it until
2750 after the GRs have been restored. */
2751 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2753 if (current_frame_info
.reg_save_ar_unat
!= 0)
2755 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2758 alt_regno
= next_scratch_gr_reg ();
2759 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2760 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2761 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
2766 ar_unat_save_reg
= NULL_RTX
;
2768 if (current_frame_info
.reg_save_ar_pfs
!= 0)
2770 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_pfs
);
2771 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2772 emit_move_insn (reg
, alt_reg
);
2774 else if (! current_function_is_leaf
)
2776 alt_regno
= next_scratch_gr_reg ();
2777 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2778 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2780 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2781 emit_move_insn (reg
, alt_reg
);
2784 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2786 if (current_frame_info
.reg_save_ar_lc
!= 0)
2787 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2790 alt_regno
= next_scratch_gr_reg ();
2791 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2792 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2795 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2796 emit_move_insn (reg
, alt_reg
);
2799 /* We should now be at the base of the gr/br/fr spill area. */
2800 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2801 + current_frame_info
.spill_size
))
2804 /* The GP may be stored on the stack in the prologue, but it's
2805 never restored in the epilogue. Skip the stack slot. */
2806 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
2809 /* Restore all general registers. */
2810 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
2811 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2813 reg
= gen_rtx_REG (DImode
, regno
);
2814 do_restore (gen_gr_restore
, reg
, cfa_off
);
2818 /* Restore the branch registers. Handle B0 specially, as it may
2819 have gotten stored in some GR register. */
2820 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2822 if (current_frame_info
.reg_save_b0
!= 0)
2823 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2826 alt_regno
= next_scratch_gr_reg ();
2827 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2828 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2831 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2832 emit_move_insn (reg
, alt_reg
);
2835 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2836 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2838 alt_regno
= next_scratch_gr_reg ();
2839 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2840 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2842 reg
= gen_rtx_REG (DImode
, regno
);
2843 emit_move_insn (reg
, alt_reg
);
2846 /* Restore floating point registers. */
2847 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2848 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2852 reg
= gen_rtx_REG (TFmode
, regno
);
2853 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
2857 /* Restore ar.unat for real. */
2858 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2860 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2861 emit_move_insn (reg
, ar_unat_save_reg
);
2864 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2867 finish_spill_pointers ();
2869 if (current_frame_info
.total_size
|| cfun
->machine
->ia64_eh_epilogue_sp
)
2871 /* ??? At this point we must generate a magic insn that appears to
2872 modify the spill iterators, the stack pointer, and the frame
2873 pointer. This would allow the most scheduling freedom. For now,
2875 emit_insn (gen_blockage ());
2878 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2879 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
2880 else if (frame_pointer_needed
)
2882 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
2883 RTX_FRAME_RELATED_P (insn
) = 1;
2885 else if (current_frame_info
.total_size
)
2887 rtx offset
, frame_size_rtx
;
2889 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
2890 if (CONST_OK_FOR_I (current_frame_info
.total_size
))
2891 offset
= frame_size_rtx
;
2894 regno
= next_scratch_gr_reg ();
2895 offset
= gen_rtx_REG (DImode
, regno
);
2896 emit_move_insn (offset
, frame_size_rtx
);
2899 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2902 RTX_FRAME_RELATED_P (insn
) = 1;
2903 if (GET_CODE (offset
) != CONST_INT
)
2906 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2907 gen_rtx_SET (VOIDmode
,
2909 gen_rtx_PLUS (DImode
,
2916 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2917 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
2920 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
2923 int fp
= GR_REG (2);
2924 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
2925 first available call clobbered register. If there was a frame_pointer
2926 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
2927 so we have to make sure we're using the string "r2" when emitting
2928 the register name for the assembler. */
2929 if (current_frame_info
.reg_fp
&& current_frame_info
.reg_fp
== GR_REG (2))
2930 fp
= HARD_FRAME_POINTER_REGNUM
;
2932 /* We must emit an alloc to force the input registers to become output
2933 registers. Otherwise, if the callee tries to pass its parameters
2934 through to another call without an intervening alloc, then these
2936 /* ??? We don't need to preserve all input registers. We only need to
2937 preserve those input registers used as arguments to the sibling call.
2938 It is unclear how to compute that number here. */
2939 if (current_frame_info
.n_input_regs
!= 0)
2940 emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
2941 GEN_INT (0), GEN_INT (0),
2942 GEN_INT (current_frame_info
.n_input_regs
),
2947 /* Return 1 if br.ret can do all the work required to return from a
2951 ia64_direct_return ()
2953 if (reload_completed
&& ! frame_pointer_needed
)
2955 ia64_compute_frame_size (get_frame_size ());
2957 return (current_frame_info
.total_size
== 0
2958 && current_frame_info
.n_spilled
== 0
2959 && current_frame_info
.reg_save_b0
== 0
2960 && current_frame_info
.reg_save_pr
== 0
2961 && current_frame_info
.reg_save_ar_pfs
== 0
2962 && current_frame_info
.reg_save_ar_unat
== 0
2963 && current_frame_info
.reg_save_ar_lc
== 0);
2969 ia64_hard_regno_rename_ok (from
, to
)
2973 /* Don't clobber any of the registers we reserved for the prologue. */
2974 if (to
== current_frame_info
.reg_fp
2975 || to
== current_frame_info
.reg_save_b0
2976 || to
== current_frame_info
.reg_save_pr
2977 || to
== current_frame_info
.reg_save_ar_pfs
2978 || to
== current_frame_info
.reg_save_ar_unat
2979 || to
== current_frame_info
.reg_save_ar_lc
)
2982 if (from
== current_frame_info
.reg_fp
2983 || from
== current_frame_info
.reg_save_b0
2984 || from
== current_frame_info
.reg_save_pr
2985 || from
== current_frame_info
.reg_save_ar_pfs
2986 || from
== current_frame_info
.reg_save_ar_unat
2987 || from
== current_frame_info
.reg_save_ar_lc
)
2990 /* Don't use output registers outside the register frame. */
2991 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
2994 /* Retain even/oddness on predicate register pairs. */
2995 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
2996 return (from
& 1) == (to
& 1);
3001 /* Target hook for assembling integer objects. Handle word-sized
3002 aligned objects and detect the cases when @fptr is needed. */
3005 ia64_assemble_integer (x
, size
, aligned_p
)
3010 if (size
== (TARGET_ILP32
? 4 : 8)
3012 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
3013 && GET_CODE (x
) == SYMBOL_REF
3014 && SYMBOL_REF_FUNCTION_P (x
))
3017 fputs ("\tdata4\t@fptr(", asm_out_file
);
3019 fputs ("\tdata8\t@fptr(", asm_out_file
);
3020 output_addr_const (asm_out_file
, x
);
3021 fputs (")\n", asm_out_file
);
3024 return default_assemble_integer (x
, size
, aligned_p
);
3027 /* Emit the function prologue. */
3030 ia64_output_function_prologue (file
, size
)
3032 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
3034 int mask
, grsave
, grsave_prev
;
3036 if (current_frame_info
.need_regstk
)
3037 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
3038 current_frame_info
.n_input_regs
,
3039 current_frame_info
.n_local_regs
,
3040 current_frame_info
.n_output_regs
,
3041 current_frame_info
.n_rotate_regs
);
3043 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3046 /* Emit the .prologue directive. */
3049 grsave
= grsave_prev
= 0;
3050 if (current_frame_info
.reg_save_b0
!= 0)
3053 grsave
= grsave_prev
= current_frame_info
.reg_save_b0
;
3055 if (current_frame_info
.reg_save_ar_pfs
!= 0
3056 && (grsave_prev
== 0
3057 || current_frame_info
.reg_save_ar_pfs
== grsave_prev
+ 1))
3060 if (grsave_prev
== 0)
3061 grsave
= current_frame_info
.reg_save_ar_pfs
;
3062 grsave_prev
= current_frame_info
.reg_save_ar_pfs
;
3064 if (current_frame_info
.reg_fp
!= 0
3065 && (grsave_prev
== 0
3066 || current_frame_info
.reg_fp
== grsave_prev
+ 1))
3069 if (grsave_prev
== 0)
3070 grsave
= HARD_FRAME_POINTER_REGNUM
;
3071 grsave_prev
= current_frame_info
.reg_fp
;
3073 if (current_frame_info
.reg_save_pr
!= 0
3074 && (grsave_prev
== 0
3075 || current_frame_info
.reg_save_pr
== grsave_prev
+ 1))
3078 if (grsave_prev
== 0)
3079 grsave
= current_frame_info
.reg_save_pr
;
3083 fprintf (file
, "\t.prologue %d, %d\n", mask
,
3084 ia64_dbx_register_number (grsave
));
3086 fputs ("\t.prologue\n", file
);
3088 /* Emit a .spill directive, if necessary, to relocate the base of
3089 the register spill area. */
3090 if (current_frame_info
.spill_cfa_off
!= -16)
3091 fprintf (file
, "\t.spill %ld\n",
3092 (long) (current_frame_info
.spill_cfa_off
3093 + current_frame_info
.spill_size
));
3096 /* Emit the .body directive at the scheduled end of the prologue. */
3099 ia64_output_function_end_prologue (file
)
3102 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3105 fputs ("\t.body\n", file
);
3108 /* Emit the function epilogue. */
3111 ia64_output_function_epilogue (file
, size
)
3112 FILE *file ATTRIBUTE_UNUSED
;
3113 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
3117 /* Reset from the function's potential modifications. */
3118 XINT (return_address_pointer_rtx
, 0) = RETURN_ADDRESS_POINTER_REGNUM
;
3120 if (current_frame_info
.reg_fp
)
3122 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3123 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3124 = reg_names
[current_frame_info
.reg_fp
];
3125 reg_names
[current_frame_info
.reg_fp
] = tmp
;
3127 if (! TARGET_REG_NAMES
)
3129 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
3130 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
3131 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
3132 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
3133 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
3134 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
3137 current_frame_info
.initialized
= 0;
3141 ia64_dbx_register_number (regno
)
3144 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3145 from its home at loc79 to something inside the register frame. We
3146 must perform the same renumbering here for the debug info. */
3147 if (current_frame_info
.reg_fp
)
3149 if (regno
== HARD_FRAME_POINTER_REGNUM
)
3150 regno
= current_frame_info
.reg_fp
;
3151 else if (regno
== current_frame_info
.reg_fp
)
3152 regno
= HARD_FRAME_POINTER_REGNUM
;
3155 if (IN_REGNO_P (regno
))
3156 return 32 + regno
- IN_REG (0);
3157 else if (LOC_REGNO_P (regno
))
3158 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
3159 else if (OUT_REGNO_P (regno
))
3160 return (32 + current_frame_info
.n_input_regs
3161 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
3167 ia64_initialize_trampoline (addr
, fnaddr
, static_chain
)
3168 rtx addr
, fnaddr
, static_chain
;
3170 rtx addr_reg
, eight
= GEN_INT (8);
3172 /* Load up our iterator. */
3173 addr_reg
= gen_reg_rtx (Pmode
);
3174 emit_move_insn (addr_reg
, addr
);
3176 /* The first two words are the fake descriptor:
3177 __ia64_trampoline, ADDR+16. */
3178 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3179 gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline"));
3180 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3182 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3183 copy_to_reg (plus_constant (addr
, 16)));
3184 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3186 /* The third word is the target descriptor. */
3187 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), fnaddr
);
3188 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3190 /* The fourth word is the static chain. */
3191 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), static_chain
);
3194 /* Do any needed setup for a variadic function. CUM has not been updated
3195 for the last named argument which has type TYPE and mode MODE.
3197 We generate the actual spill instructions during prologue generation. */
3200 ia64_setup_incoming_varargs (cum
, int_mode
, type
, pretend_size
, second_time
)
3201 CUMULATIVE_ARGS cum
;
3205 int second_time ATTRIBUTE_UNUSED
;
3207 /* Skip the current argument. */
3208 ia64_function_arg_advance (&cum
, int_mode
, type
, 1);
3210 if (cum
.words
< MAX_ARGUMENT_SLOTS
)
3212 int n
= MAX_ARGUMENT_SLOTS
- cum
.words
;
3213 *pretend_size
= n
* UNITS_PER_WORD
;
3214 cfun
->machine
->n_varargs
= n
;
3218 /* Check whether TYPE is a homogeneous floating point aggregate. If
3219 it is, return the mode of the floating point type that appears
3220 in all leafs. If it is not, return VOIDmode.
3222 An aggregate is a homogeneous floating point aggregate is if all
3223 fields/elements in it have the same floating point type (e.g,
3224 SFmode). 128-bit quad-precision floats are excluded. */
3226 static enum machine_mode
3227 hfa_element_mode (type
, nested
)
3231 enum machine_mode element_mode
= VOIDmode
;
3232 enum machine_mode mode
;
3233 enum tree_code code
= TREE_CODE (type
);
3234 int know_element_mode
= 0;
3239 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
3240 case BOOLEAN_TYPE
: case CHAR_TYPE
: case POINTER_TYPE
:
3241 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
3242 case FILE_TYPE
: case SET_TYPE
: case LANG_TYPE
:
3246 /* Fortran complex types are supposed to be HFAs, so we need to handle
3247 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3250 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
3251 && (TYPE_MODE (type
) != TCmode
|| INTEL_EXTENDED_IEEE_FORMAT
))
3252 return mode_for_size (GET_MODE_UNIT_SIZE (TYPE_MODE (type
))
3253 * BITS_PER_UNIT
, MODE_FLOAT
, 0);
3258 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3259 mode if this is contained within an aggregate. */
3260 if (nested
&& (TYPE_MODE (type
) != TFmode
|| INTEL_EXTENDED_IEEE_FORMAT
))
3261 return TYPE_MODE (type
);
3266 return hfa_element_mode (TREE_TYPE (type
), 1);
3270 case QUAL_UNION_TYPE
:
3271 for (t
= TYPE_FIELDS (type
); t
; t
= TREE_CHAIN (t
))
3273 if (TREE_CODE (t
) != FIELD_DECL
)
3276 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
3277 if (know_element_mode
)
3279 if (mode
!= element_mode
)
3282 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3286 know_element_mode
= 1;
3287 element_mode
= mode
;
3290 return element_mode
;
3293 /* If we reach here, we probably have some front-end specific type
3294 that the backend doesn't know about. This can happen via the
3295 aggregate_value_p call in init_function_start. All we can do is
3296 ignore unknown tree types. */
3303 /* Return rtx for register where argument is passed, or zero if it is passed
3306 /* ??? 128-bit quad-precision floats are always passed in general
3310 ia64_function_arg (cum
, mode
, type
, named
, incoming
)
3311 CUMULATIVE_ARGS
*cum
;
3312 enum machine_mode mode
;
3317 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
3318 int words
= (((mode
== BLKmode
? int_size_in_bytes (type
)
3319 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
3322 enum machine_mode hfa_mode
= VOIDmode
;
3324 /* Integer and float arguments larger than 8 bytes start at the next even
3325 boundary. Aggregates larger than 8 bytes start at the next even boundary
3326 if the aggregate has 16 byte alignment. Net effect is that types with
3327 alignment greater than 8 start at the next even boundary. */
3328 /* ??? The ABI does not specify how to handle aggregates with alignment from
3329 9 to 15 bytes, or greater than 16. We handle them all as if they had
3330 16 byte alignment. Such aggregates can occur only if gcc extensions are
3332 if ((type
? (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3334 && (cum
->words
& 1))
3337 /* If all argument slots are used, then it must go on the stack. */
3338 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3341 /* Check for and handle homogeneous FP aggregates. */
3343 hfa_mode
= hfa_element_mode (type
, 0);
3345 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3346 and unprototyped hfas are passed specially. */
3347 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3351 int fp_regs
= cum
->fp_regs
;
3352 int int_regs
= cum
->words
+ offset
;
3353 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3357 /* If prototyped, pass it in FR regs then GR regs.
3358 If not prototyped, pass it in both FR and GR regs.
3360 If this is an SFmode aggregate, then it is possible to run out of
3361 FR regs while GR regs are still left. In that case, we pass the
3362 remaining part in the GR regs. */
3364 /* Fill the FP regs. We do this always. We stop if we reach the end
3365 of the argument, the last FP register, or the last argument slot. */
3367 byte_size
= ((mode
== BLKmode
)
3368 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3369 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3371 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3372 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
3374 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3375 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
3379 args_byte_size
+= hfa_size
;
3383 /* If no prototype, then the whole thing must go in GR regs. */
3384 if (! cum
->prototype
)
3386 /* If this is an SFmode aggregate, then we might have some left over
3387 that needs to go in GR regs. */
3388 else if (byte_size
!= offset
)
3389 int_regs
+= offset
/ UNITS_PER_WORD
;
3391 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3393 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
3395 enum machine_mode gr_mode
= DImode
;
3397 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3398 then this goes in a GR reg left adjusted/little endian, right
3399 adjusted/big endian. */
3400 /* ??? Currently this is handled wrong, because 4-byte hunks are
3401 always right adjusted/little endian. */
3404 /* If we have an even 4 byte hunk because the aggregate is a
3405 multiple of 4 bytes in size, then this goes in a GR reg right
3406 adjusted/little endian. */
3407 else if (byte_size
- offset
== 4)
3409 /* Complex floats need to have float mode. */
3410 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3413 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3414 gen_rtx_REG (gr_mode
, (basereg
3417 offset
+= GET_MODE_SIZE (gr_mode
);
3418 int_regs
+= GET_MODE_SIZE (gr_mode
) <= UNITS_PER_WORD
3419 ? 1 : GET_MODE_SIZE (gr_mode
) / UNITS_PER_WORD
;
3422 /* If we ended up using just one location, just return that one loc. */
3424 return XEXP (loc
[0], 0);
3426 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3429 /* Integral and aggregates go in general registers. If we have run out of
3430 FR registers, then FP values must also go in general registers. This can
3431 happen when we have a SFmode HFA. */
3432 else if (((mode
== TFmode
) && ! INTEL_EXTENDED_IEEE_FORMAT
)
3433 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3435 int byte_size
= ((mode
== BLKmode
)
3436 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3437 if (BYTES_BIG_ENDIAN
3438 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
3439 && byte_size
< UNITS_PER_WORD
3442 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3443 gen_rtx_REG (DImode
,
3444 (basereg
+ cum
->words
3447 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
3450 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3454 /* If there is a prototype, then FP values go in a FR register when
3455 named, and in a GR register when unnamed. */
3456 else if (cum
->prototype
)
3459 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3461 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
3463 /* If there is no prototype, then FP values go in both FR and GR
3467 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3468 gen_rtx_REG (mode
, (FR_ARG_FIRST
3471 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3473 (basereg
+ cum
->words
3477 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
3481 /* Return number of words, at the beginning of the argument, that must be
3482 put in registers. 0 is the argument is entirely in registers or entirely
3486 ia64_function_arg_partial_nregs (cum
, mode
, type
, named
)
3487 CUMULATIVE_ARGS
*cum
;
3488 enum machine_mode mode
;
3490 int named ATTRIBUTE_UNUSED
;
3492 int words
= (((mode
== BLKmode
? int_size_in_bytes (type
)
3493 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
3497 /* Arguments with alignment larger than 8 bytes start at the next even
3499 if ((type
? (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3501 && (cum
->words
& 1))
3504 /* If all argument slots are used, then it must go on the stack. */
3505 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3508 /* It doesn't matter whether the argument goes in FR or GR regs. If
3509 it fits within the 8 argument slots, then it goes entirely in
3510 registers. If it extends past the last argument slot, then the rest
3511 goes on the stack. */
3513 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
3516 return MAX_ARGUMENT_SLOTS
- cum
->words
- offset
;
3519 /* Update CUM to point after this argument. This is patterned after
3520 ia64_function_arg. */
3523 ia64_function_arg_advance (cum
, mode
, type
, named
)
3524 CUMULATIVE_ARGS
*cum
;
3525 enum machine_mode mode
;
3529 int words
= (((mode
== BLKmode
? int_size_in_bytes (type
)
3530 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
3533 enum machine_mode hfa_mode
= VOIDmode
;
3535 /* If all arg slots are already full, then there is nothing to do. */
3536 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
3539 /* Arguments with alignment larger than 8 bytes start at the next even
3541 if ((type
? (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3543 && (cum
->words
& 1))
3546 cum
->words
+= words
+ offset
;
3548 /* Check for and handle homogeneous FP aggregates. */
3550 hfa_mode
= hfa_element_mode (type
, 0);
3552 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3553 and unprototyped hfas are passed specially. */
3554 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3556 int fp_regs
= cum
->fp_regs
;
3557 /* This is the original value of cum->words + offset. */
3558 int int_regs
= cum
->words
- words
;
3559 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3563 /* If prototyped, pass it in FR regs then GR regs.
3564 If not prototyped, pass it in both FR and GR regs.
3566 If this is an SFmode aggregate, then it is possible to run out of
3567 FR regs while GR regs are still left. In that case, we pass the
3568 remaining part in the GR regs. */
3570 /* Fill the FP regs. We do this always. We stop if we reach the end
3571 of the argument, the last FP register, or the last argument slot. */
3573 byte_size
= ((mode
== BLKmode
)
3574 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3575 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3577 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3578 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
3581 args_byte_size
+= hfa_size
;
3585 cum
->fp_regs
= fp_regs
;
3588 /* Integral and aggregates go in general registers. If we have run out of
3589 FR registers, then FP values must also go in general registers. This can
3590 happen when we have a SFmode HFA. */
3591 else if (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
)
3592 cum
->int_regs
= cum
->words
;
3594 /* If there is a prototype, then FP values go in a FR register when
3595 named, and in a GR register when unnamed. */
3596 else if (cum
->prototype
)
3599 cum
->int_regs
= cum
->words
;
3601 /* ??? Complex types should not reach here. */
3602 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3604 /* If there is no prototype, then FP values go in both FR and GR
3608 /* ??? Complex types should not reach here. */
3609 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3610 cum
->int_regs
= cum
->words
;
3614 /* Variable sized types are passed by reference. */
3615 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3618 ia64_function_arg_pass_by_reference (cum
, mode
, type
, named
)
3619 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
3620 enum machine_mode mode ATTRIBUTE_UNUSED
;
3622 int named ATTRIBUTE_UNUSED
;
3624 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
3627 /* True if it is OK to do sibling call optimization for the specified
3628 call expression EXP. DECL will be the called function, or NULL if
3629 this is an indirect call. */
3631 ia64_function_ok_for_sibcall (decl
, exp
)
3633 tree exp ATTRIBUTE_UNUSED
;
3635 /* Direct calls are always ok. */
3639 /* If TARGET_CONST_GP is in effect, then our caller expects us to
3640 return with our current GP. This means that we'll always have
3641 a GP reload after an indirect call. */
3642 return !ia64_epilogue_uses (R_GR (1));
3646 /* Implement va_arg. */
3649 ia64_va_arg (valist
, type
)
3654 /* Variable sized types are passed by reference. */
3655 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
3657 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
3658 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
3661 /* Arguments with alignment larger than 8 bytes start at the next even
3663 if (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3665 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
3666 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
3667 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
3668 build_int_2 (-2 * UNITS_PER_WORD
, -1));
3669 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
3670 TREE_SIDE_EFFECTS (t
) = 1;
3671 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3674 return std_expand_builtin_va_arg (valist
, type
);
3677 /* Return 1 if function return value returned in memory. Return 0 if it is
3681 ia64_return_in_memory (valtype
)
3684 enum machine_mode mode
;
3685 enum machine_mode hfa_mode
;
3686 HOST_WIDE_INT byte_size
;
3688 mode
= TYPE_MODE (valtype
);
3689 byte_size
= GET_MODE_SIZE (mode
);
3690 if (mode
== BLKmode
)
3692 byte_size
= int_size_in_bytes (valtype
);
3697 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
3699 hfa_mode
= hfa_element_mode (valtype
, 0);
3700 if (hfa_mode
!= VOIDmode
)
3702 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3704 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
3709 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
3715 /* Return rtx for register that holds the function return value. */
3718 ia64_function_value (valtype
, func
)
3720 tree func ATTRIBUTE_UNUSED
;
3722 enum machine_mode mode
;
3723 enum machine_mode hfa_mode
;
3725 mode
= TYPE_MODE (valtype
);
3726 hfa_mode
= hfa_element_mode (valtype
, 0);
3728 if (hfa_mode
!= VOIDmode
)
3736 hfa_size
= GET_MODE_SIZE (hfa_mode
);
3737 byte_size
= ((mode
== BLKmode
)
3738 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
3740 for (i
= 0; offset
< byte_size
; i
++)
3742 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3743 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
3749 return XEXP (loc
[0], 0);
3751 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3753 else if (FLOAT_TYPE_P (valtype
) &&
3754 ((mode
!= TFmode
) || INTEL_EXTENDED_IEEE_FORMAT
))
3755 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
3758 if (BYTES_BIG_ENDIAN
3759 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
3767 bytesize
= int_size_in_bytes (valtype
);
3768 for (i
= 0; offset
< bytesize
; i
++)
3770 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3771 gen_rtx_REG (DImode
,
3774 offset
+= UNITS_PER_WORD
;
3776 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3779 return gen_rtx_REG (mode
, GR_RET_FIRST
);
3783 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3784 We need to emit DTP-relative relocations. */
3787 ia64_output_dwarf_dtprel (file
, size
, x
)
3794 fputs ("\tdata8.ua\t@dtprel(", file
);
3795 output_addr_const (file
, x
);
3799 /* Print a memory address as an operand to reference that memory location. */
3801 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
3802 also call this from ia64_print_operand for memory addresses. */
3805 ia64_print_operand_address (stream
, address
)
3806 FILE * stream ATTRIBUTE_UNUSED
;
3807 rtx address ATTRIBUTE_UNUSED
;
3811 /* Print an operand to an assembler instruction.
3812 C Swap and print a comparison operator.
3813 D Print an FP comparison operator.
3814 E Print 32 - constant, for SImode shifts as extract.
3815 e Print 64 - constant, for DImode rotates.
3816 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
3817 a floating point register emitted normally.
3818 I Invert a predicate register by adding 1.
3819 J Select the proper predicate register for a condition.
3820 j Select the inverse predicate register for a condition.
3821 O Append .acq for volatile load.
3822 P Postincrement of a MEM.
3823 Q Append .rel for volatile store.
3824 S Shift amount for shladd instruction.
3825 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
3826 for Intel assembler.
3827 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
3828 for Intel assembler.
3829 r Print register name, or constant 0 as r0. HP compatibility for
3832 ia64_print_operand (file
, x
, code
)
3842 /* Handled below. */
3847 enum rtx_code c
= swap_condition (GET_CODE (x
));
3848 fputs (GET_RTX_NAME (c
), file
);
3853 switch (GET_CODE (x
))
3865 str
= GET_RTX_NAME (GET_CODE (x
));
3872 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
3876 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
3880 if (x
== CONST0_RTX (GET_MODE (x
)))
3881 str
= reg_names
[FR_REG (0)];
3882 else if (x
== CONST1_RTX (GET_MODE (x
)))
3883 str
= reg_names
[FR_REG (1)];
3884 else if (GET_CODE (x
) == REG
)
3885 str
= reg_names
[REGNO (x
)];
3892 fputs (reg_names
[REGNO (x
) + 1], file
);
3898 unsigned int regno
= REGNO (XEXP (x
, 0));
3899 if (GET_CODE (x
) == EQ
)
3903 fputs (reg_names
[regno
], file
);
3908 if (MEM_VOLATILE_P (x
))
3909 fputs(".acq", file
);
3914 HOST_WIDE_INT value
;
3916 switch (GET_CODE (XEXP (x
, 0)))
3922 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
3923 if (GET_CODE (x
) == CONST_INT
)
3925 else if (GET_CODE (x
) == REG
)
3927 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
3935 value
= GET_MODE_SIZE (GET_MODE (x
));
3939 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
3945 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, value
);
3950 if (MEM_VOLATILE_P (x
))
3951 fputs(".rel", file
);
3955 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
3959 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
3961 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
3967 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
3969 const char *prefix
= "0x";
3970 if (INTVAL (x
) & 0x80000000)
3972 fprintf (file
, "0xffffffff");
3975 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
3981 /* If this operand is the constant zero, write it as register zero.
3982 Any register, zero, or CONST_INT value is OK here. */
3983 if (GET_CODE (x
) == REG
)
3984 fputs (reg_names
[REGNO (x
)], file
);
3985 else if (x
== CONST0_RTX (GET_MODE (x
)))
3987 else if (GET_CODE (x
) == CONST_INT
)
3988 output_addr_const (file
, x
);
3990 output_operand_lossage ("invalid %%r value");
3997 /* For conditional branches, returns or calls, substitute
3998 sptk, dptk, dpnt, or spnt for %s. */
3999 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
4002 int pred_val
= INTVAL (XEXP (x
, 0));
4004 /* Guess top and bottom 10% statically predicted. */
4005 if (pred_val
< REG_BR_PROB_BASE
/ 50)
4007 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
4009 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98)
4014 else if (GET_CODE (current_output_insn
) == CALL_INSN
)
4019 fputs (which
, file
);
4024 x
= current_insn_predicate
;
4027 unsigned int regno
= REGNO (XEXP (x
, 0));
4028 if (GET_CODE (x
) == EQ
)
4030 fprintf (file
, "(%s) ", reg_names
[regno
]);
4035 output_operand_lossage ("ia64_print_operand: unknown code");
4039 switch (GET_CODE (x
))
4041 /* This happens for the spill/restore instructions. */
4046 /* ... fall through ... */
4049 fputs (reg_names
[REGNO (x
)], file
);
4054 rtx addr
= XEXP (x
, 0);
4055 if (GET_RTX_CLASS (GET_CODE (addr
)) == 'a')
4056 addr
= XEXP (addr
, 0);
4057 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
4062 output_addr_const (file
, x
);
4069 /* Compute a (partial) cost for rtx X. Return true if the complete
4070 cost has been computed, and false if subexpressions should be
4071 scanned. In either case, *TOTAL contains the cost result. */
4072 /* ??? This is incomplete. */
4075 ia64_rtx_costs (x
, code
, outer_code
, total
)
4077 int code
, outer_code
;
4086 *total
= CONST_OK_FOR_J (INTVAL (x
)) ? 0 : COSTS_N_INSNS (1);
4089 if (CONST_OK_FOR_I (INTVAL (x
)))
4091 else if (CONST_OK_FOR_J (INTVAL (x
)))
4094 *total
= COSTS_N_INSNS (1);
4097 if (CONST_OK_FOR_K (INTVAL (x
)) || CONST_OK_FOR_L (INTVAL (x
)))
4100 *total
= COSTS_N_INSNS (1);
4105 *total
= COSTS_N_INSNS (1);
4111 *total
= COSTS_N_INSNS (3);
4115 /* For multiplies wider than HImode, we have to go to the FPU,
4116 which normally involves copies. Plus there's the latency
4117 of the multiply itself, and the latency of the instructions to
4118 transfer integer regs to FP regs. */
4119 /* ??? Check for FP mode. */
4120 if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
4121 *total
= COSTS_N_INSNS (10);
4123 *total
= COSTS_N_INSNS (2);
4131 *total
= COSTS_N_INSNS (1);
4138 /* We make divide expensive, so that divide-by-constant will be
4139 optimized to a multiply. */
4140 *total
= COSTS_N_INSNS (60);
4148 /* Calculate the cost of moving data from a register in class FROM to
4149 one in class TO, using MODE. */
4152 ia64_register_move_cost (mode
, from
, to
)
4153 enum machine_mode mode
;
4154 enum reg_class from
, to
;
4156 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4157 if (to
== ADDL_REGS
)
4159 if (from
== ADDL_REGS
)
4162 /* All costs are symmetric, so reduce cases by putting the
4163 lower number class as the destination. */
4166 enum reg_class tmp
= to
;
4167 to
= from
, from
= tmp
;
4170 /* Moving from FR<->GR in TFmode must be more expensive than 2,
4171 so that we get secondary memory reloads. Between FR_REGS,
4172 we have to make this at least as expensive as MEMORY_MOVE_COST
4173 to avoid spectacularly poor register class preferencing. */
4176 if (to
!= GR_REGS
|| from
!= GR_REGS
)
4177 return MEMORY_MOVE_COST (mode
, to
, 0);
4185 /* Moving between PR registers takes two insns. */
4186 if (from
== PR_REGS
)
4188 /* Moving between PR and anything but GR is impossible. */
4189 if (from
!= GR_REGS
)
4190 return MEMORY_MOVE_COST (mode
, to
, 0);
4194 /* Moving between BR and anything but GR is impossible. */
4195 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
4196 return MEMORY_MOVE_COST (mode
, to
, 0);
4201 /* Moving between AR and anything but GR is impossible. */
4202 if (from
!= GR_REGS
)
4203 return MEMORY_MOVE_COST (mode
, to
, 0);
4208 case GR_AND_FR_REGS
:
4209 case GR_AND_BR_REGS
:
4220 /* This function returns the register class required for a secondary
4221 register when copying between one of the registers in CLASS, and X,
4222 using MODE. A return value of NO_REGS means that no secondary register
4226 ia64_secondary_reload_class (class, mode
, x
)
4227 enum reg_class
class;
4228 enum machine_mode mode ATTRIBUTE_UNUSED
;
4233 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
4234 regno
= true_regnum (x
);
4241 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4242 interaction. We end up with two pseudos with overlapping lifetimes
4243 both of which are equiv to the same constant, and both which need
4244 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4245 changes depending on the path length, which means the qty_first_reg
4246 check in make_regs_eqv can give different answers at different times.
4247 At some point I'll probably need a reload_indi pattern to handle
4250 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4251 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4252 non-general registers for good measure. */
4253 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
4256 /* This is needed if a pseudo used as a call_operand gets spilled to a
4258 if (GET_CODE (x
) == MEM
)
4263 /* Need to go through general regsters to get to other class regs. */
4264 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
4267 /* This can happen when a paradoxical subreg is an operand to the
4269 /* ??? This shouldn't be necessary after instruction scheduling is
4270 enabled, because paradoxical subregs are not accepted by
4271 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4272 stop the paradoxical subreg stupidity in the *_operand functions
4274 if (GET_CODE (x
) == MEM
4275 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
4276 || GET_MODE (x
) == QImode
))
4279 /* This can happen because of the ior/and/etc patterns that accept FP
4280 registers as operands. If the third operand is a constant, then it
4281 needs to be reloaded into a FP register. */
4282 if (GET_CODE (x
) == CONST_INT
)
4285 /* This can happen because of register elimination in a muldi3 insn.
4286 E.g. `26107 * (unsigned long)&u'. */
4287 if (GET_CODE (x
) == PLUS
)
4292 /* ??? This happens if we cse/gcse a BImode value across a call,
4293 and the function has a nonlocal goto. This is because global
4294 does not allocate call crossing pseudos to hard registers when
4295 current_function_has_nonlocal_goto is true. This is relatively
4296 common for C++ programs that use exceptions. To reproduce,
4297 return NO_REGS and compile libstdc++. */
4298 if (GET_CODE (x
) == MEM
)
4301 /* This can happen when we take a BImode subreg of a DImode value,
4302 and that DImode value winds up in some non-GR register. */
4303 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
4308 /* Since we have no offsettable memory addresses, we need a temporary
4309 to hold the address of the second word. */
4322 /* Emit text to declare externally defined variables and functions, because
4323 the Intel assembler does not support undefined externals. */
4326 ia64_asm_output_external (file
, decl
, name
)
4331 int save_referenced
;
4333 /* GNU as does not need anything here, but the HP linker does need
4334 something for external functions. */
4338 || TREE_CODE (decl
) != FUNCTION_DECL
4339 || strstr(name
, "__builtin_") == name
))
4342 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4343 the linker when we do this, so we need to be careful not to do this for
4344 builtin functions which have no library equivalent. Unfortunately, we
4345 can't tell here whether or not a function will actually be called by
4346 expand_expr, so we pull in library functions even if we may not need
4348 if (! strcmp (name
, "__builtin_next_arg")
4349 || ! strcmp (name
, "alloca")
4350 || ! strcmp (name
, "__builtin_constant_p")
4351 || ! strcmp (name
, "__builtin_args_info"))
4355 ia64_hpux_add_extern_decl (name
);
4358 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4360 save_referenced
= TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
));
4361 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4362 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
4363 (*targetm
.asm_out
.globalize_label
) (file
, name
);
4364 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)) = save_referenced
;
4368 /* Parse the -mfixed-range= option string. */
4371 fix_range (const_str
)
4372 const char *const_str
;
4375 char *str
, *dash
, *comma
;
4377 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4378 REG2 are either register names or register numbers. The effect
4379 of this option is to mark the registers in the range from REG1 to
4380 REG2 as ``fixed'' so they won't be used by the compiler. This is
4381 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4383 i
= strlen (const_str
);
4384 str
= (char *) alloca (i
+ 1);
4385 memcpy (str
, const_str
, i
+ 1);
4389 dash
= strchr (str
, '-');
4392 warning ("value of -mfixed-range must have form REG1-REG2");
4397 comma
= strchr (dash
+ 1, ',');
4401 first
= decode_reg_name (str
);
4404 warning ("unknown register name: %s", str
);
4408 last
= decode_reg_name (dash
+ 1);
4411 warning ("unknown register name: %s", dash
+ 1);
4419 warning ("%s-%s is an empty range", str
, dash
+ 1);
4423 for (i
= first
; i
<= last
; ++i
)
4424 fixed_regs
[i
] = call_used_regs
[i
] = 1;
4434 static struct machine_function
*
4435 ia64_init_machine_status ()
4437 return ggc_alloc_cleared (sizeof (struct machine_function
));
4440 /* Handle TARGET_OPTIONS switches. */
4443 ia64_override_options ()
4447 const char *const name
; /* processor name or nickname. */
4448 const enum processor_type processor
;
4450 const processor_alias_table
[] =
4452 {"itanium", PROCESSOR_ITANIUM
},
4453 {"itanium1", PROCESSOR_ITANIUM
},
4454 {"merced", PROCESSOR_ITANIUM
},
4455 {"itanium2", PROCESSOR_ITANIUM2
},
4456 {"mckinley", PROCESSOR_ITANIUM2
},
4459 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
4462 if (TARGET_AUTO_PIC
)
4463 target_flags
|= MASK_CONST_GP
;
4465 if (TARGET_INLINE_FLOAT_DIV_LAT
&& TARGET_INLINE_FLOAT_DIV_THR
)
4467 warning ("cannot optimize floating point division for both latency and throughput");
4468 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4471 if (TARGET_INLINE_INT_DIV_LAT
&& TARGET_INLINE_INT_DIV_THR
)
4473 warning ("cannot optimize integer division for both latency and throughput");
4474 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4477 if (ia64_fixed_range_string
)
4478 fix_range (ia64_fixed_range_string
);
4480 if (ia64_tls_size_string
)
4483 unsigned long tmp
= strtoul (ia64_tls_size_string
, &end
, 10);
4484 if (*end
|| (tmp
!= 14 && tmp
!= 22 && tmp
!= 64))
4485 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string
);
4487 ia64_tls_size
= tmp
;
4490 if (!ia64_tune_string
)
4491 ia64_tune_string
= "itanium2";
4493 for (i
= 0; i
< pta_size
; i
++)
4494 if (! strcmp (ia64_tune_string
, processor_alias_table
[i
].name
))
4496 ia64_tune
= processor_alias_table
[i
].processor
;
4501 error ("bad value (%s) for -tune= switch", ia64_tune_string
);
4503 ia64_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
4504 flag_schedule_insns_after_reload
= 0;
4506 ia64_section_threshold
= g_switch_set
? g_switch_value
: IA64_DEFAULT_GVALUE
;
4508 init_machine_status
= ia64_init_machine_status
;
4510 /* Tell the compiler which flavor of TFmode we're using. */
4511 if (INTEL_EXTENDED_IEEE_FORMAT
)
4512 real_format_for_mode
[TFmode
- QFmode
] = &ieee_extended_intel_128_format
;
4515 static enum attr_itanium_class ia64_safe_itanium_class
PARAMS((rtx
));
4516 static enum attr_type ia64_safe_type
PARAMS((rtx
));
4518 static enum attr_itanium_class
4519 ia64_safe_itanium_class (insn
)
4522 if (recog_memoized (insn
) >= 0)
4523 return get_attr_itanium_class (insn
);
4525 return ITANIUM_CLASS_UNKNOWN
;
4528 static enum attr_type
4529 ia64_safe_type (insn
)
4532 if (recog_memoized (insn
) >= 0)
4533 return get_attr_type (insn
);
4535 return TYPE_UNKNOWN
;
4538 /* The following collection of routines emit instruction group stop bits as
4539 necessary to avoid dependencies. */
4541 /* Need to track some additional registers as far as serialization is
4542 concerned so we can properly handle br.call and br.ret. We could
4543 make these registers visible to gcc, but since these registers are
4544 never explicitly used in gcc generated code, it seems wasteful to
4545 do so (plus it would make the call and return patterns needlessly
4547 #define REG_GP (GR_REG (1))
4548 #define REG_RP (BR_REG (0))
4549 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4550 /* This is used for volatile asms which may require a stop bit immediately
4551 before and after them. */
4552 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4553 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4554 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4556 /* For each register, we keep track of how it has been written in the
4557 current instruction group.
4559 If a register is written unconditionally (no qualifying predicate),
4560 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4562 If a register is written if its qualifying predicate P is true, we
4563 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4564 may be written again by the complement of P (P^1) and when this happens,
4565 WRITE_COUNT gets set to 2.
4567 The result of this is that whenever an insn attempts to write a register
4568 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4570 If a predicate register is written by a floating-point insn, we set
4571 WRITTEN_BY_FP to true.
4573 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4574 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4576 struct reg_write_state
4578 unsigned int write_count
: 2;
4579 unsigned int first_pred
: 16;
4580 unsigned int written_by_fp
: 1;
4581 unsigned int written_by_and
: 1;
4582 unsigned int written_by_or
: 1;
4585 /* Cumulative info for the current instruction group. */
4586 struct reg_write_state rws_sum
[NUM_REGS
];
4587 /* Info for the current instruction. This gets copied to rws_sum after a
4588 stop bit is emitted. */
4589 struct reg_write_state rws_insn
[NUM_REGS
];
4591 /* Indicates whether this is the first instruction after a stop bit,
4592 in which case we don't need another stop bit. Without this, we hit
4593 the abort in ia64_variable_issue when scheduling an alloc. */
4594 static int first_instruction
;
4596 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4597 RTL for one instruction. */
4600 unsigned int is_write
: 1; /* Is register being written? */
4601 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
4602 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
4603 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
4604 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
4605 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
4608 static void rws_update
PARAMS ((struct reg_write_state
*, int,
4609 struct reg_flags
, int));
4610 static int rws_access_regno
PARAMS ((int, struct reg_flags
, int));
4611 static int rws_access_reg
PARAMS ((rtx
, struct reg_flags
, int));
4612 static void update_set_flags
PARAMS ((rtx
, struct reg_flags
*, int *, rtx
*));
4613 static int set_src_needs_barrier
PARAMS ((rtx
, struct reg_flags
, int, rtx
));
4614 static int rtx_needs_barrier
PARAMS ((rtx
, struct reg_flags
, int));
4615 static void init_insn_group_barriers
PARAMS ((void));
4616 static int group_barrier_needed_p
PARAMS ((rtx
));
4617 static int safe_group_barrier_needed_p
PARAMS ((rtx
));
4619 /* Update *RWS for REGNO, which is being written by the current instruction,
4620 with predicate PRED, and associated register flags in FLAGS. */
4623 rws_update (rws
, regno
, flags
, pred
)
4624 struct reg_write_state
*rws
;
4626 struct reg_flags flags
;
4630 rws
[regno
].write_count
++;
4632 rws
[regno
].write_count
= 2;
4633 rws
[regno
].written_by_fp
|= flags
.is_fp
;
4634 /* ??? Not tracking and/or across differing predicates. */
4635 rws
[regno
].written_by_and
= flags
.is_and
;
4636 rws
[regno
].written_by_or
= flags
.is_or
;
4637 rws
[regno
].first_pred
= pred
;
4640 /* Handle an access to register REGNO of type FLAGS using predicate register
4641 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4642 a dependency with an earlier instruction in the same group. */
4645 rws_access_regno (regno
, flags
, pred
)
4647 struct reg_flags flags
;
4650 int need_barrier
= 0;
4652 if (regno
>= NUM_REGS
)
4655 if (! PR_REGNO_P (regno
))
4656 flags
.is_and
= flags
.is_or
= 0;
4662 /* One insn writes same reg multiple times? */
4663 if (rws_insn
[regno
].write_count
> 0)
4666 /* Update info for current instruction. */
4667 rws_update (rws_insn
, regno
, flags
, pred
);
4668 write_count
= rws_sum
[regno
].write_count
;
4670 switch (write_count
)
4673 /* The register has not been written yet. */
4674 rws_update (rws_sum
, regno
, flags
, pred
);
4678 /* The register has been written via a predicate. If this is
4679 not a complementary predicate, then we need a barrier. */
4680 /* ??? This assumes that P and P+1 are always complementary
4681 predicates for P even. */
4682 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4684 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4686 else if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
4688 rws_update (rws_sum
, regno
, flags
, pred
);
4692 /* The register has been unconditionally written already. We
4694 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4696 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4700 rws_sum
[regno
].written_by_and
= flags
.is_and
;
4701 rws_sum
[regno
].written_by_or
= flags
.is_or
;
4710 if (flags
.is_branch
)
4712 /* Branches have several RAW exceptions that allow to avoid
4715 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
4716 /* RAW dependencies on branch regs are permissible as long
4717 as the writer is a non-branch instruction. Since we
4718 never generate code that uses a branch register written
4719 by a branch instruction, handling this case is
4723 if (REGNO_REG_CLASS (regno
) == PR_REGS
4724 && ! rws_sum
[regno
].written_by_fp
)
4725 /* The predicates of a branch are available within the
4726 same insn group as long as the predicate was written by
4727 something other than a floating-point instruction. */
4731 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4733 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4736 switch (rws_sum
[regno
].write_count
)
4739 /* The register has not been written yet. */
4743 /* The register has been written via a predicate. If this is
4744 not a complementary predicate, then we need a barrier. */
4745 /* ??? This assumes that P and P+1 are always complementary
4746 predicates for P even. */
4747 if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
4752 /* The register has been unconditionally written already. We
4762 return need_barrier
;
4766 rws_access_reg (reg
, flags
, pred
)
4768 struct reg_flags flags
;
4771 int regno
= REGNO (reg
);
4772 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
4775 return rws_access_regno (regno
, flags
, pred
);
4778 int need_barrier
= 0;
4780 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
4781 return need_barrier
;
4785 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
4786 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
4789 update_set_flags (x
, pflags
, ppred
, pcond
)
4791 struct reg_flags
*pflags
;
4795 rtx src
= SET_SRC (x
);
4799 switch (GET_CODE (src
))
4805 if (SET_DEST (x
) == pc_rtx
)
4806 /* X is a conditional branch. */
4810 int is_complemented
= 0;
4812 /* X is a conditional move. */
4813 rtx cond
= XEXP (src
, 0);
4814 if (GET_CODE (cond
) == EQ
)
4815 is_complemented
= 1;
4816 cond
= XEXP (cond
, 0);
4817 if (GET_CODE (cond
) != REG
4818 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
4821 if (XEXP (src
, 1) == SET_DEST (x
)
4822 || XEXP (src
, 2) == SET_DEST (x
))
4824 /* X is a conditional move that conditionally writes the
4827 /* We need another complement in this case. */
4828 if (XEXP (src
, 1) == SET_DEST (x
))
4829 is_complemented
= ! is_complemented
;
4831 *ppred
= REGNO (cond
);
4832 if (is_complemented
)
4836 /* ??? If this is a conditional write to the dest, then this
4837 instruction does not actually read one source. This probably
4838 doesn't matter, because that source is also the dest. */
4839 /* ??? Multiple writes to predicate registers are allowed
4840 if they are all AND type compares, or if they are all OR
4841 type compares. We do not generate such instructions
4844 /* ... fall through ... */
4847 if (GET_RTX_CLASS (GET_CODE (src
)) == '<'
4848 && GET_MODE_CLASS (GET_MODE (XEXP (src
, 0))) == MODE_FLOAT
)
4849 /* Set pflags->is_fp to 1 so that we know we're dealing
4850 with a floating point comparison when processing the
4851 destination of the SET. */
4854 /* Discover if this is a parallel comparison. We only handle
4855 and.orcm and or.andcm at present, since we must retain a
4856 strict inverse on the predicate pair. */
4857 else if (GET_CODE (src
) == AND
)
4859 else if (GET_CODE (src
) == IOR
)
4866 /* Subroutine of rtx_needs_barrier; this function determines whether the
4867 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
4868 are as in rtx_needs_barrier. COND is an rtx that holds the condition
4872 set_src_needs_barrier (x
, flags
, pred
, cond
)
4874 struct reg_flags flags
;
4878 int need_barrier
= 0;
4880 rtx src
= SET_SRC (x
);
4882 if (GET_CODE (src
) == CALL
)
4883 /* We don't need to worry about the result registers that
4884 get written by subroutine call. */
4885 return rtx_needs_barrier (src
, flags
, pred
);
4886 else if (SET_DEST (x
) == pc_rtx
)
4888 /* X is a conditional branch. */
4889 /* ??? This seems redundant, as the caller sets this bit for
4891 flags
.is_branch
= 1;
4892 return rtx_needs_barrier (src
, flags
, pred
);
4895 need_barrier
= rtx_needs_barrier (src
, flags
, pred
);
4897 /* This instruction unconditionally uses a predicate register. */
4899 need_barrier
|= rws_access_reg (cond
, flags
, 0);
4902 if (GET_CODE (dst
) == ZERO_EXTRACT
)
4904 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
4905 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
4906 dst
= XEXP (dst
, 0);
4908 return need_barrier
;
4911 /* Handle an access to rtx X of type FLAGS using predicate register PRED.
4912 Return 1 is this access creates a dependency with an earlier instruction
4913 in the same group. */
4916 rtx_needs_barrier (x
, flags
, pred
)
4918 struct reg_flags flags
;
4922 int is_complemented
= 0;
4923 int need_barrier
= 0;
4924 const char *format_ptr
;
4925 struct reg_flags new_flags
;
4933 switch (GET_CODE (x
))
4936 update_set_flags (x
, &new_flags
, &pred
, &cond
);
4937 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
, cond
);
4938 if (GET_CODE (SET_SRC (x
)) != CALL
)
4940 new_flags
.is_write
= 1;
4941 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
4946 new_flags
.is_write
= 0;
4947 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
4949 /* Avoid multiple register writes, in case this is a pattern with
4950 multiple CALL rtx. This avoids an abort in rws_access_reg. */
4951 if (! flags
.is_sibcall
&& ! rws_insn
[REG_AR_CFM
].write_count
)
4953 new_flags
.is_write
= 1;
4954 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
4955 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
4956 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
4961 /* X is a predicated instruction. */
4963 cond
= COND_EXEC_TEST (x
);
4966 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
4968 if (GET_CODE (cond
) == EQ
)
4969 is_complemented
= 1;
4970 cond
= XEXP (cond
, 0);
4971 if (GET_CODE (cond
) != REG
4972 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
4974 pred
= REGNO (cond
);
4975 if (is_complemented
)
4978 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
4979 return need_barrier
;
4983 /* Clobber & use are for earlier compiler-phases only. */
4988 /* We always emit stop bits for traditional asms. We emit stop bits
4989 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
4990 if (GET_CODE (x
) != ASM_OPERANDS
4991 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
4993 /* Avoid writing the register multiple times if we have multiple
4994 asm outputs. This avoids an abort in rws_access_reg. */
4995 if (! rws_insn
[REG_VOLATILE
].write_count
)
4997 new_flags
.is_write
= 1;
4998 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
5003 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5004 We can not just fall through here since then we would be confused
5005 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5006 traditional asms unlike their normal usage. */
5008 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
5009 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
5014 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5016 rtx pat
= XVECEXP (x
, 0, i
);
5017 if (GET_CODE (pat
) == SET
)
5019 update_set_flags (pat
, &new_flags
, &pred
, &cond
);
5020 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
, cond
);
5022 else if (GET_CODE (pat
) == USE
5023 || GET_CODE (pat
) == CALL
5024 || GET_CODE (pat
) == ASM_OPERANDS
)
5025 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5026 else if (GET_CODE (pat
) != CLOBBER
&& GET_CODE (pat
) != RETURN
)
5029 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5031 rtx pat
= XVECEXP (x
, 0, i
);
5032 if (GET_CODE (pat
) == SET
)
5034 if (GET_CODE (SET_SRC (pat
)) != CALL
)
5036 new_flags
.is_write
= 1;
5037 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
5041 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
5042 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5050 if (REGNO (x
) == AR_UNAT_REGNUM
)
5052 for (i
= 0; i
< 64; ++i
)
5053 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
5056 need_barrier
= rws_access_reg (x
, flags
, pred
);
5060 /* Find the regs used in memory address computation. */
5061 new_flags
.is_write
= 0;
5062 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5065 case CONST_INT
: case CONST_DOUBLE
:
5066 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
5069 /* Operators with side-effects. */
5070 case POST_INC
: case POST_DEC
:
5071 if (GET_CODE (XEXP (x
, 0)) != REG
)
5074 new_flags
.is_write
= 0;
5075 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5076 new_flags
.is_write
= 1;
5077 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5081 if (GET_CODE (XEXP (x
, 0)) != REG
)
5084 new_flags
.is_write
= 0;
5085 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5086 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5087 new_flags
.is_write
= 1;
5088 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5091 /* Handle common unary and binary ops for efficiency. */
5092 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
5093 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
5094 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
5095 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5096 case NE
: case EQ
: case GE
: case GT
: case LE
:
5097 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
5098 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5099 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5102 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
5103 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
5104 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
5105 case SQRT
: case FFS
: case POPCOUNT
:
5106 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5110 switch (XINT (x
, 1))
5112 case UNSPEC_LTOFF_DTPMOD
:
5113 case UNSPEC_LTOFF_DTPREL
:
5115 case UNSPEC_LTOFF_TPREL
:
5117 case UNSPEC_PRED_REL_MUTEX
:
5118 case UNSPEC_PIC_CALL
:
5120 case UNSPEC_FETCHADD_ACQ
:
5121 case UNSPEC_BSP_VALUE
:
5122 case UNSPEC_FLUSHRS
:
5123 case UNSPEC_BUNDLE_SELECTOR
:
5126 case UNSPEC_GR_SPILL
:
5127 case UNSPEC_GR_RESTORE
:
5129 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
5130 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
5132 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5133 new_flags
.is_write
= (XINT (x
, 1) == 1);
5134 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
5139 case UNSPEC_FR_SPILL
:
5140 case UNSPEC_FR_RESTORE
:
5141 case UNSPEC_GETF_EXP
:
5143 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5146 case UNSPEC_FR_RECIP_APPROX
:
5147 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5148 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5151 case UNSPEC_CMPXCHG_ACQ
:
5152 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5153 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
5161 case UNSPEC_VOLATILE
:
5162 switch (XINT (x
, 1))
5165 /* Alloc must always be the first instruction of a group.
5166 We force this by always returning true. */
5167 /* ??? We might get better scheduling if we explicitly check for
5168 input/local/output register dependencies, and modify the
5169 scheduler so that alloc is always reordered to the start of
5170 the current group. We could then eliminate all of the
5171 first_instruction code. */
5172 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5174 new_flags
.is_write
= 1;
5175 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5178 case UNSPECV_SET_BSP
:
5182 case UNSPECV_BLOCKAGE
:
5183 case UNSPECV_INSN_GROUP_BARRIER
:
5185 case UNSPECV_PSAC_ALL
:
5186 case UNSPECV_PSAC_NORMAL
:
5195 new_flags
.is_write
= 0;
5196 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
5197 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5199 new_flags
.is_write
= 1;
5200 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5201 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5205 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
5206 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5207 switch (format_ptr
[i
])
5209 case '0': /* unused field */
5210 case 'i': /* integer */
5211 case 'n': /* note */
5212 case 'w': /* wide integer */
5213 case 's': /* pointer to string */
5214 case 'S': /* optional pointer to string */
5218 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
5223 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
5224 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
5233 return need_barrier
;
5236 /* Clear out the state for group_barrier_needed_p at the start of a
5237 sequence of insns. */
5240 init_insn_group_barriers ()
5242 memset (rws_sum
, 0, sizeof (rws_sum
));
5243 first_instruction
= 1;
5246 /* Given the current state, recorded by previous calls to this function,
5247 determine whether a group barrier (a stop bit) is necessary before INSN.
5248 Return nonzero if so. */
5251 group_barrier_needed_p (insn
)
5255 int need_barrier
= 0;
5256 struct reg_flags flags
;
5258 memset (&flags
, 0, sizeof (flags
));
5259 switch (GET_CODE (insn
))
5265 /* A barrier doesn't imply an instruction group boundary. */
5269 memset (rws_insn
, 0, sizeof (rws_insn
));
5273 flags
.is_branch
= 1;
5274 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
5275 memset (rws_insn
, 0, sizeof (rws_insn
));
5277 /* Don't bundle a call following another call. */
5278 if ((pat
= prev_active_insn (insn
))
5279 && GET_CODE (pat
) == CALL_INSN
)
5285 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
5289 flags
.is_branch
= 1;
5291 /* Don't bundle a jump following a call. */
5292 if ((pat
= prev_active_insn (insn
))
5293 && GET_CODE (pat
) == CALL_INSN
)
5301 if (GET_CODE (PATTERN (insn
)) == USE
5302 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5303 /* Don't care about USE and CLOBBER "insns"---those are used to
5304 indicate to the optimizer that it shouldn't get rid of
5305 certain operations. */
5308 pat
= PATTERN (insn
);
5310 /* Ug. Hack hacks hacked elsewhere. */
5311 switch (recog_memoized (insn
))
5313 /* We play dependency tricks with the epilogue in order
5314 to get proper schedules. Undo this for dv analysis. */
5315 case CODE_FOR_epilogue_deallocate_stack
:
5316 case CODE_FOR_prologue_allocate_stack
:
5317 pat
= XVECEXP (pat
, 0, 0);
5320 /* The pattern we use for br.cloop confuses the code above.
5321 The second element of the vector is representative. */
5322 case CODE_FOR_doloop_end_internal
:
5323 pat
= XVECEXP (pat
, 0, 1);
5326 /* Doesn't generate code. */
5327 case CODE_FOR_pred_rel_mutex
:
5328 case CODE_FOR_prologue_use
:
5335 memset (rws_insn
, 0, sizeof (rws_insn
));
5336 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
5338 /* Check to see if the previous instruction was a volatile
5341 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
5348 if (first_instruction
&& INSN_P (insn
)
5349 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
5350 && GET_CODE (PATTERN (insn
)) != USE
5351 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5354 first_instruction
= 0;
5357 return need_barrier
;
5360 /* Like group_barrier_needed_p, but do not clobber the current state. */
5363 safe_group_barrier_needed_p (insn
)
5366 struct reg_write_state rws_saved
[NUM_REGS
];
5367 int saved_first_instruction
;
5370 memcpy (rws_saved
, rws_sum
, NUM_REGS
* sizeof *rws_saved
);
5371 saved_first_instruction
= first_instruction
;
5373 t
= group_barrier_needed_p (insn
);
5375 memcpy (rws_sum
, rws_saved
, NUM_REGS
* sizeof *rws_saved
);
5376 first_instruction
= saved_first_instruction
;
5381 /* Scan the current function and insert stop bits as necessary to
5382 eliminate dependencies. This function assumes that a final
5383 instruction scheduling pass has been run which has already
5384 inserted most of the necessary stop bits. This function only
5385 inserts new ones at basic block boundaries, since these are
5386 invisible to the scheduler. */
5389 emit_insn_group_barriers (dump
)
5394 int insns_since_last_label
= 0;
5396 init_insn_group_barriers ();
5398 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5400 if (GET_CODE (insn
) == CODE_LABEL
)
5402 if (insns_since_last_label
)
5404 insns_since_last_label
= 0;
5406 else if (GET_CODE (insn
) == NOTE
5407 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
5409 if (insns_since_last_label
)
5411 insns_since_last_label
= 0;
5413 else if (GET_CODE (insn
) == INSN
5414 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
5415 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
5417 init_insn_group_barriers ();
5420 else if (INSN_P (insn
))
5422 insns_since_last_label
= 1;
5424 if (group_barrier_needed_p (insn
))
5429 fprintf (dump
, "Emitting stop before label %d\n",
5430 INSN_UID (last_label
));
5431 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
5434 init_insn_group_barriers ();
5442 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5443 This function has to emit all necessary group barriers. */
5446 emit_all_insn_group_barriers (dump
)
5447 FILE *dump ATTRIBUTE_UNUSED
;
5451 init_insn_group_barriers ();
5453 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5455 if (GET_CODE (insn
) == BARRIER
)
5457 rtx last
= prev_active_insn (insn
);
5461 if (GET_CODE (last
) == JUMP_INSN
5462 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
5463 last
= prev_active_insn (last
);
5464 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
5465 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
5467 init_insn_group_barriers ();
5469 else if (INSN_P (insn
))
5471 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
5472 init_insn_group_barriers ();
5473 else if (group_barrier_needed_p (insn
))
5475 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5476 init_insn_group_barriers ();
5477 group_barrier_needed_p (insn
);
5484 static int errata_find_address_regs
PARAMS ((rtx
*, void *));
5485 static void errata_emit_nops
PARAMS ((rtx
));
5486 static void fixup_errata
PARAMS ((void));
5488 /* This structure is used to track some details about the previous insns
5489 groups so we can determine if it may be necessary to insert NOPs to
5490 workaround hardware errata. */
5493 HARD_REG_SET p_reg_set
;
5494 HARD_REG_SET gr_reg_conditionally_set
;
5497 /* Index into the last_group array. */
5498 static int group_idx
;
5500 /* Called through for_each_rtx; determines if a hard register that was
5501 conditionally set in the previous group is used as an address register.
5502 It ensures that for_each_rtx returns 1 in that case. */
5504 errata_find_address_regs (xp
, data
)
5506 void *data ATTRIBUTE_UNUSED
;
5509 if (GET_CODE (x
) != MEM
)
5512 if (GET_CODE (x
) == POST_MODIFY
)
5514 if (GET_CODE (x
) == REG
)
5516 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5517 if (TEST_HARD_REG_BIT (prev_group
->gr_reg_conditionally_set
,
5525 /* Called for each insn; this function keeps track of the state in
5526 last_group and emits additional NOPs if necessary to work around
5527 an Itanium A/B step erratum. */
5529 errata_emit_nops (insn
)
5532 struct group
*this_group
= last_group
+ group_idx
;
5533 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5534 rtx pat
= PATTERN (insn
);
5535 rtx cond
= GET_CODE (pat
) == COND_EXEC
? COND_EXEC_TEST (pat
) : 0;
5536 rtx real_pat
= cond
? COND_EXEC_CODE (pat
) : pat
;
5537 enum attr_type type
;
5540 if (GET_CODE (real_pat
) == USE
5541 || GET_CODE (real_pat
) == CLOBBER
5542 || GET_CODE (real_pat
) == ASM_INPUT
5543 || GET_CODE (real_pat
) == ADDR_VEC
5544 || GET_CODE (real_pat
) == ADDR_DIFF_VEC
5545 || asm_noperands (PATTERN (insn
)) >= 0)
5548 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5551 if (GET_CODE (set
) == PARALLEL
)
5554 set
= XVECEXP (real_pat
, 0, 0);
5555 for (i
= 1; i
< XVECLEN (real_pat
, 0); i
++)
5556 if (GET_CODE (XVECEXP (real_pat
, 0, i
)) != USE
5557 && GET_CODE (XVECEXP (real_pat
, 0, i
)) != CLOBBER
)
5564 if (set
&& GET_CODE (set
) != SET
)
5567 type
= get_attr_type (insn
);
5570 && set
&& REG_P (SET_DEST (set
)) && PR_REGNO_P (REGNO (SET_DEST (set
))))
5571 SET_HARD_REG_BIT (this_group
->p_reg_set
, REGNO (SET_DEST (set
)));
5573 if ((type
== TYPE_M
|| type
== TYPE_A
) && cond
&& set
5574 && REG_P (SET_DEST (set
))
5575 && GET_CODE (SET_SRC (set
)) != PLUS
5576 && GET_CODE (SET_SRC (set
)) != MINUS
5577 && (GET_CODE (SET_SRC (set
)) != ASHIFT
5578 || !shladd_operand (XEXP (SET_SRC (set
), 1), VOIDmode
))
5579 && (GET_CODE (SET_SRC (set
)) != MEM
5580 || GET_CODE (XEXP (SET_SRC (set
), 0)) != POST_MODIFY
)
5581 && GENERAL_REGNO_P (REGNO (SET_DEST (set
))))
5583 if (GET_RTX_CLASS (GET_CODE (cond
)) != '<'
5584 || ! REG_P (XEXP (cond
, 0)))
5587 if (TEST_HARD_REG_BIT (prev_group
->p_reg_set
, REGNO (XEXP (cond
, 0))))
5588 SET_HARD_REG_BIT (this_group
->gr_reg_conditionally_set
, REGNO (SET_DEST (set
)));
5590 if (for_each_rtx (&real_pat
, errata_find_address_regs
, NULL
))
5592 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5593 emit_insn_before (gen_nop (), insn
);
5594 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5596 memset (last_group
, 0, sizeof last_group
);
5600 /* Emit extra nops if they are required to work around hardware errata. */
5607 if (! TARGET_B_STEP
)
5611 memset (last_group
, 0, sizeof last_group
);
5613 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5618 if (ia64_safe_type (insn
) == TYPE_S
)
5621 memset (last_group
+ group_idx
, 0, sizeof last_group
[group_idx
]);
5624 errata_emit_nops (insn
);
5629 /* Instruction scheduling support. */
5631 #define NR_BUNDLES 10
5633 /* A list of names of all available bundles. */
5635 static const char *bundle_name
[NR_BUNDLES
] =
5641 #if NR_BUNDLES == 10
5651 /* Nonzero if we should insert stop bits into the schedule. */
5653 int ia64_final_schedule
= 0;
5655 /* Codes of the corresponding quieryied units: */
5657 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
5658 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
5660 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
5661 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
5663 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
5665 /* The following variable value is an insn group barrier. */
5667 static rtx dfa_stop_insn
;
5669 /* The following variable value is the last issued insn. */
5671 static rtx last_scheduled_insn
;
5673 /* The following variable value is size of the DFA state. */
5675 static size_t dfa_state_size
;
5677 /* The following variable value is pointer to a DFA state used as
5678 temporary variable. */
5680 static state_t temp_dfa_state
= NULL
;
5682 /* The following variable value is DFA state after issuing the last
5685 static state_t prev_cycle_state
= NULL
;
5687 /* The following array element values are TRUE if the corresponding
5688 insn requires to add stop bits before it. */
5690 static char *stops_p
;
5692 /* The following variable is used to set up the mentioned above array. */
5694 static int stop_before_p
= 0;
5696 /* The following variable value is length of the arrays `clocks' and
5699 static int clocks_length
;
5701 /* The following array element values are cycles on which the
5702 corresponding insn will be issued. The array is used only for
5707 /* The following array element values are numbers of cycles should be
5708 added to improve insn scheduling for MM_insns for Itanium1. */
5710 static int *add_cycles
;
5712 static rtx ia64_single_set
PARAMS ((rtx
));
5713 static void ia64_emit_insn_before
PARAMS ((rtx
, rtx
));
5715 /* Map a bundle number to its pseudo-op. */
5721 return bundle_name
[b
];
5725 /* Return the maximum number of instructions a cpu can issue. */
5733 /* Helper function - like single_set, but look inside COND_EXEC. */
5736 ia64_single_set (insn
)
5739 rtx x
= PATTERN (insn
), ret
;
5740 if (GET_CODE (x
) == COND_EXEC
)
5741 x
= COND_EXEC_CODE (x
);
5742 if (GET_CODE (x
) == SET
)
5745 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5746 Although they are not classical single set, the second set is there just
5747 to protect it from moving past FP-relative stack accesses. */
5748 switch (recog_memoized (insn
))
5750 case CODE_FOR_prologue_allocate_stack
:
5751 case CODE_FOR_epilogue_deallocate_stack
:
5752 ret
= XVECEXP (x
, 0, 0);
5756 ret
= single_set_2 (insn
, x
);
5763 /* Adjust the cost of a scheduling dependency. Return the new cost of
5764 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5767 ia64_adjust_cost (insn
, link
, dep_insn
, cost
)
5768 rtx insn
, link
, dep_insn
;
5771 enum attr_itanium_class dep_class
;
5772 enum attr_itanium_class insn_class
;
5774 if (REG_NOTE_KIND (link
) != REG_DEP_OUTPUT
)
5777 insn_class
= ia64_safe_itanium_class (insn
);
5778 dep_class
= ia64_safe_itanium_class (dep_insn
);
5779 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
5780 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
5786 /* Like emit_insn_before, but skip cycle_display notes.
5787 ??? When cycle display notes are implemented, update this. */
5790 ia64_emit_insn_before (insn
, before
)
5793 emit_insn_before (insn
, before
);
5796 /* The following function marks insns who produce addresses for load
5797 and store insns. Such insns will be placed into M slots because it
5798 decrease latency time for Itanium1 (see function
5799 `ia64_produce_address_p' and the DFA descriptions). */
5802 ia64_dependencies_evaluation_hook (head
, tail
)
5805 rtx insn
, link
, next
, next_tail
;
5807 next_tail
= NEXT_INSN (tail
);
5808 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
5811 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
5813 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
5815 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
5817 next
= XEXP (link
, 0);
5818 if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_ST
5819 || ia64_safe_itanium_class (next
) == ITANIUM_CLASS_STF
)
5820 && ia64_st_address_bypass_p (insn
, next
))
5822 else if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_LD
5823 || ia64_safe_itanium_class (next
)
5824 == ITANIUM_CLASS_FLD
)
5825 && ia64_ld_address_bypass_p (insn
, next
))
5828 insn
->call
= link
!= 0;
5832 /* We're beginning a new block. Initialize data structures as necessary. */
5835 ia64_sched_init (dump
, sched_verbose
, max_ready
)
5836 FILE *dump ATTRIBUTE_UNUSED
;
5837 int sched_verbose ATTRIBUTE_UNUSED
;
5838 int max_ready ATTRIBUTE_UNUSED
;
5840 #ifdef ENABLE_CHECKING
5843 if (reload_completed
)
5844 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
5845 insn
!= current_sched_info
->next_tail
;
5846 insn
= NEXT_INSN (insn
))
5847 if (SCHED_GROUP_P (insn
))
5850 last_scheduled_insn
= NULL_RTX
;
5851 init_insn_group_barriers ();
5854 /* We are about to being issuing insns for this clock cycle.
5855 Override the default sort algorithm to better slot instructions. */
5858 ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
5859 clock_var
, reorder_type
)
5864 int clock_var ATTRIBUTE_UNUSED
;
5868 int n_ready
= *pn_ready
;
5869 rtx
*e_ready
= ready
+ n_ready
;
5873 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
5875 if (reorder_type
== 0)
5877 /* First, move all USEs, CLOBBERs and other crud out of the way. */
5879 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
5880 if (insnp
< e_ready
)
5883 enum attr_type t
= ia64_safe_type (insn
);
5884 if (t
== TYPE_UNKNOWN
)
5886 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
5887 || asm_noperands (PATTERN (insn
)) >= 0)
5889 rtx lowest
= ready
[n_asms
];
5890 ready
[n_asms
] = insn
;
5896 rtx highest
= ready
[n_ready
- 1];
5897 ready
[n_ready
- 1] = insn
;
5904 if (n_asms
< n_ready
)
5906 /* Some normal insns to process. Skip the asms. */
5910 else if (n_ready
> 0)
5914 if (ia64_final_schedule
)
5917 int nr_need_stop
= 0;
5919 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
5920 if (safe_group_barrier_needed_p (*insnp
))
5923 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
5925 if (reorder_type
== 0)
5928 /* Move down everything that needs a stop bit, preserving
5930 while (insnp
-- > ready
+ deleted
)
5931 while (insnp
>= ready
+ deleted
)
5934 if (! safe_group_barrier_needed_p (insn
))
5936 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
5947 /* We are about to being issuing insns for this clock cycle. Override
5948 the default sort algorithm to better slot instructions. */
5951 ia64_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
, clock_var
)
5958 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
5959 pn_ready
, clock_var
, 0);
5962 /* Like ia64_sched_reorder, but called after issuing each insn.
5963 Override the default sort algorithm to better slot instructions. */
5966 ia64_sched_reorder2 (dump
, sched_verbose
, ready
, pn_ready
, clock_var
)
5967 FILE *dump ATTRIBUTE_UNUSED
;
5968 int sched_verbose ATTRIBUTE_UNUSED
;
5973 if (ia64_tune
== PROCESSOR_ITANIUM
&& reload_completed
&& last_scheduled_insn
)
5974 clocks
[INSN_UID (last_scheduled_insn
)] = clock_var
;
5975 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
5979 /* We are about to issue INSN. Return the number of insns left on the
5980 ready queue that can be issued this cycle. */
5983 ia64_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
)
5984 FILE *dump ATTRIBUTE_UNUSED
;
5985 int sched_verbose ATTRIBUTE_UNUSED
;
5986 rtx insn ATTRIBUTE_UNUSED
;
5987 int can_issue_more ATTRIBUTE_UNUSED
;
5989 last_scheduled_insn
= insn
;
5990 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
5991 if (reload_completed
)
5993 if (group_barrier_needed_p (insn
))
5995 if (GET_CODE (insn
) == CALL_INSN
)
5996 init_insn_group_barriers ();
5997 stops_p
[INSN_UID (insn
)] = stop_before_p
;
6003 /* We are choosing insn from the ready queue. Return nonzero if INSN
6007 ia64_first_cycle_multipass_dfa_lookahead_guard (insn
)
6010 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6012 return (!reload_completed
6013 || !safe_group_barrier_needed_p (insn
));
6016 /* The following variable value is pseudo-insn used by the DFA insn
6017 scheduler to change the DFA state when the simulated clock is
6020 static rtx dfa_pre_cycle_insn
;
6022 /* We are about to being issuing INSN. Return nonzero if we can not
6023 issue it on given cycle CLOCK and return zero if we should not sort
6024 the ready queue on the next clock start. */
6027 ia64_dfa_new_cycle (dump
, verbose
, insn
, last_clock
, clock
, sort_p
)
6031 int last_clock
, clock
;
6034 int setup_clocks_p
= FALSE
;
6036 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6038 if ((reload_completed
&& safe_group_barrier_needed_p (insn
))
6039 || (last_scheduled_insn
6040 && (GET_CODE (last_scheduled_insn
) == CALL_INSN
6041 || GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6042 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)))
6044 init_insn_group_barriers ();
6045 if (verbose
&& dump
)
6046 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
6047 last_clock
== clock
? " + cycle advance" : "");
6049 if (last_clock
== clock
)
6051 state_transition (curr_state
, dfa_stop_insn
);
6052 if (TARGET_EARLY_STOP_BITS
)
6053 *sort_p
= (last_scheduled_insn
== NULL_RTX
6054 || GET_CODE (last_scheduled_insn
) != CALL_INSN
);
6059 else if (reload_completed
)
6060 setup_clocks_p
= TRUE
;
6061 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
6062 state_transition (curr_state
, dfa_stop_insn
);
6063 state_transition (curr_state
, dfa_pre_cycle_insn
);
6064 state_transition (curr_state
, NULL
);
6066 else if (reload_completed
)
6067 setup_clocks_p
= TRUE
;
6068 if (setup_clocks_p
&& ia64_tune
== PROCESSOR_ITANIUM
)
6070 enum attr_itanium_class c
= ia64_safe_itanium_class (insn
);
6072 if (c
!= ITANIUM_CLASS_MMMUL
&& c
!= ITANIUM_CLASS_MMSHF
)
6077 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
6078 if (REG_NOTE_KIND (link
) == 0)
6080 enum attr_itanium_class dep_class
;
6081 rtx dep_insn
= XEXP (link
, 0);
6083 dep_class
= ia64_safe_itanium_class (dep_insn
);
6084 if ((dep_class
== ITANIUM_CLASS_MMMUL
6085 || dep_class
== ITANIUM_CLASS_MMSHF
)
6086 && last_clock
- clocks
[INSN_UID (dep_insn
)] < 4
6088 || last_clock
- clocks
[INSN_UID (dep_insn
)] < d
))
6089 d
= last_clock
- clocks
[INSN_UID (dep_insn
)];
6092 add_cycles
[INSN_UID (insn
)] = 3 - d
;
6100 /* The following page contains abstract data `bundle states' which are
6101 used for bundling insns (inserting nops and template generation). */
6103 /* The following describes state of insn bundling. */
6107 /* Unique bundle state number to identify them in the debugging
6110 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
6111 /* number nops before and after the insn */
6112 short before_nops_num
, after_nops_num
;
6113 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
6115 int cost
; /* cost of the state in cycles */
6116 int accumulated_insns_num
; /* number of all previous insns including
6117 nops. L is considered as 2 insns */
6118 int branch_deviation
; /* deviation of previous branches from 3rd slots */
6119 struct bundle_state
*next
; /* next state with the same insn_num */
6120 struct bundle_state
*originator
; /* originator (previous insn state) */
6121 /* All bundle states are in the following chain. */
6122 struct bundle_state
*allocated_states_chain
;
6123 /* The DFA State after issuing the insn and the nops. */
6127 /* The following is map insn number to the corresponding bundle state. */
6129 static struct bundle_state
**index_to_bundle_states
;
6131 /* The unique number of next bundle state. */
6133 static int bundle_states_num
;
6135 /* All allocated bundle states are in the following chain. */
6137 static struct bundle_state
*allocated_bundle_states_chain
;
6139 /* All allocated but not used bundle states are in the following
6142 static struct bundle_state
*free_bundle_state_chain
;
6145 /* The following function returns a free bundle state. */
6147 static struct bundle_state
*
6148 get_free_bundle_state ()
6150 struct bundle_state
*result
;
6152 if (free_bundle_state_chain
!= NULL
)
6154 result
= free_bundle_state_chain
;
6155 free_bundle_state_chain
= result
->next
;
6159 result
= xmalloc (sizeof (struct bundle_state
));
6160 result
->dfa_state
= xmalloc (dfa_state_size
);
6161 result
->allocated_states_chain
= allocated_bundle_states_chain
;
6162 allocated_bundle_states_chain
= result
;
6164 result
->unique_num
= bundle_states_num
++;
6169 /* The following function frees given bundle state. */
6172 free_bundle_state (state
)
6173 struct bundle_state
*state
;
6175 state
->next
= free_bundle_state_chain
;
6176 free_bundle_state_chain
= state
;
6179 /* Start work with abstract data `bundle states'. */
6182 initiate_bundle_states ()
6184 bundle_states_num
= 0;
6185 free_bundle_state_chain
= NULL
;
6186 allocated_bundle_states_chain
= NULL
;
6189 /* Finish work with abstract data `bundle states'. */
6192 finish_bundle_states ()
6194 struct bundle_state
*curr_state
, *next_state
;
6196 for (curr_state
= allocated_bundle_states_chain
;
6198 curr_state
= next_state
)
6200 next_state
= curr_state
->allocated_states_chain
;
6201 free (curr_state
->dfa_state
);
6206 /* Hash table of the bundle states. The key is dfa_state and insn_num
6207 of the bundle states. */
6209 static htab_t bundle_state_table
;
6211 /* The function returns hash of BUNDLE_STATE. */
6214 bundle_state_hash (bundle_state
)
6215 const void *bundle_state
;
6217 const struct bundle_state
*state
= (struct bundle_state
*) bundle_state
;
6220 for (result
= i
= 0; i
< dfa_state_size
; i
++)
6221 result
+= (((unsigned char *) state
->dfa_state
) [i
]
6222 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
6223 return result
+ state
->insn_num
;
6226 /* The function returns nonzero if the bundle state keys are equal. */
6229 bundle_state_eq_p (bundle_state_1
, bundle_state_2
)
6230 const void *bundle_state_1
;
6231 const void *bundle_state_2
;
6233 const struct bundle_state
* state1
= (struct bundle_state
*) bundle_state_1
;
6234 const struct bundle_state
* state2
= (struct bundle_state
*) bundle_state_2
;
6236 return (state1
->insn_num
== state2
->insn_num
6237 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
6238 dfa_state_size
) == 0);
6241 /* The function inserts the BUNDLE_STATE into the hash table. The
6242 function returns nonzero if the bundle has been inserted into the
6243 table. The table contains the best bundle state with given key. */
6246 insert_bundle_state (bundle_state
)
6247 struct bundle_state
*bundle_state
;
6251 entry_ptr
= htab_find_slot (bundle_state_table
, bundle_state
, 1);
6252 if (*entry_ptr
== NULL
)
6254 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
6255 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
6256 *entry_ptr
= (void *) bundle_state
;
6259 else if (bundle_state
->cost
< ((struct bundle_state
*) *entry_ptr
)->cost
6260 || (bundle_state
->cost
== ((struct bundle_state
*) *entry_ptr
)->cost
6261 && (((struct bundle_state
*)*entry_ptr
)->accumulated_insns_num
6262 > bundle_state
->accumulated_insns_num
6263 || (((struct bundle_state
*)
6264 *entry_ptr
)->accumulated_insns_num
6265 == bundle_state
->accumulated_insns_num
6266 && ((struct bundle_state
*)
6267 *entry_ptr
)->branch_deviation
6268 > bundle_state
->branch_deviation
))))
6271 struct bundle_state temp
;
6273 temp
= *(struct bundle_state
*) *entry_ptr
;
6274 *(struct bundle_state
*) *entry_ptr
= *bundle_state
;
6275 ((struct bundle_state
*) *entry_ptr
)->next
= temp
.next
;
6276 *bundle_state
= temp
;
6281 /* Start work with the hash table. */
6284 initiate_bundle_state_table ()
6286 bundle_state_table
= htab_create (50, bundle_state_hash
, bundle_state_eq_p
,
6290 /* Finish work with the hash table. */
6293 finish_bundle_state_table ()
6295 htab_delete (bundle_state_table
);
6300 /* The following variable is a insn `nop' used to check bundle states
6301 with different number of inserted nops. */
6303 static rtx ia64_nop
;
6305 /* The following function tries to issue NOPS_NUM nops for the current
6306 state without advancing processor cycle. If it failed, the
6307 function returns FALSE and frees the current state. */
6310 try_issue_nops (curr_state
, nops_num
)
6311 struct bundle_state
*curr_state
;
6316 for (i
= 0; i
< nops_num
; i
++)
6317 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
6319 free_bundle_state (curr_state
);
6325 /* The following function tries to issue INSN for the current
6326 state without advancing processor cycle. If it failed, the
6327 function returns FALSE and frees the current state. */
6330 try_issue_insn (curr_state
, insn
)
6331 struct bundle_state
*curr_state
;
6334 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
6336 free_bundle_state (curr_state
);
6342 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6343 starting with ORIGINATOR without advancing processor cycle. If
6344 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6345 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6346 If it was successful, the function creates new bundle state and
6347 insert into the hash table and into `index_to_bundle_states'. */
6350 issue_nops_and_insn (originator
, before_nops_num
, insn
, try_bundle_end_p
,
6352 struct bundle_state
*originator
;
6353 int before_nops_num
;
6355 int try_bundle_end_p
, only_bundle_end_p
;
6357 struct bundle_state
*curr_state
;
6359 curr_state
= get_free_bundle_state ();
6360 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
6361 curr_state
->insn
= insn
;
6362 curr_state
->insn_num
= originator
->insn_num
+ 1;
6363 curr_state
->cost
= originator
->cost
;
6364 curr_state
->originator
= originator
;
6365 curr_state
->before_nops_num
= before_nops_num
;
6366 curr_state
->after_nops_num
= 0;
6367 curr_state
->accumulated_insns_num
6368 = originator
->accumulated_insns_num
+ before_nops_num
;
6369 curr_state
->branch_deviation
= originator
->branch_deviation
;
6370 if (insn
== NULL_RTX
)
6372 else if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
6374 if (GET_MODE (insn
) == TImode
)
6376 if (!try_issue_nops (curr_state
, before_nops_num
))
6378 if (!try_issue_insn (curr_state
, insn
))
6380 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
6381 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
6382 && curr_state
->accumulated_insns_num
% 3 != 0)
6384 free_bundle_state (curr_state
);
6388 else if (GET_MODE (insn
) != TImode
)
6390 if (!try_issue_nops (curr_state
, before_nops_num
))
6392 if (!try_issue_insn (curr_state
, insn
))
6394 curr_state
->accumulated_insns_num
++;
6395 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6396 || asm_noperands (PATTERN (insn
)) >= 0)
6398 if (ia64_safe_type (insn
) == TYPE_L
)
6399 curr_state
->accumulated_insns_num
++;
6403 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
6404 state_transition (curr_state
->dfa_state
, NULL
);
6406 if (!try_issue_nops (curr_state
, before_nops_num
))
6408 if (!try_issue_insn (curr_state
, insn
))
6410 curr_state
->accumulated_insns_num
++;
6411 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6412 || asm_noperands (PATTERN (insn
)) >= 0)
6414 /* Finish bundle containing asm insn. */
6415 curr_state
->after_nops_num
6416 = 3 - curr_state
->accumulated_insns_num
% 3;
6417 curr_state
->accumulated_insns_num
6418 += 3 - curr_state
->accumulated_insns_num
% 3;
6420 else if (ia64_safe_type (insn
) == TYPE_L
)
6421 curr_state
->accumulated_insns_num
++;
6423 if (ia64_safe_type (insn
) == TYPE_B
)
6424 curr_state
->branch_deviation
6425 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
6426 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
6428 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
6431 struct bundle_state
*curr_state1
;
6432 struct bundle_state
*allocated_states_chain
;
6434 curr_state1
= get_free_bundle_state ();
6435 dfa_state
= curr_state1
->dfa_state
;
6436 allocated_states_chain
= curr_state1
->allocated_states_chain
;
6437 *curr_state1
= *curr_state
;
6438 curr_state1
->dfa_state
= dfa_state
;
6439 curr_state1
->allocated_states_chain
= allocated_states_chain
;
6440 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
6442 curr_state
= curr_state1
;
6444 if (!try_issue_nops (curr_state
,
6445 3 - curr_state
->accumulated_insns_num
% 3))
6447 curr_state
->after_nops_num
6448 = 3 - curr_state
->accumulated_insns_num
% 3;
6449 curr_state
->accumulated_insns_num
6450 += 3 - curr_state
->accumulated_insns_num
% 3;
6452 if (!insert_bundle_state (curr_state
))
6453 free_bundle_state (curr_state
);
6457 /* The following function returns position in the two window bundle
6464 if (cpu_unit_reservation_p (state
, pos_6
))
6466 else if (cpu_unit_reservation_p (state
, pos_5
))
6468 else if (cpu_unit_reservation_p (state
, pos_4
))
6470 else if (cpu_unit_reservation_p (state
, pos_3
))
6472 else if (cpu_unit_reservation_p (state
, pos_2
))
6474 else if (cpu_unit_reservation_p (state
, pos_1
))
6480 /* The function returns code of a possible template for given position
6481 and state. The function should be called only with 2 values of
6482 position equal to 3 or 6. */
6485 get_template (state
, pos
)
6492 if (cpu_unit_reservation_p (state
, _0mii_
))
6494 else if (cpu_unit_reservation_p (state
, _0mmi_
))
6496 else if (cpu_unit_reservation_p (state
, _0mfi_
))
6498 else if (cpu_unit_reservation_p (state
, _0mmf_
))
6500 else if (cpu_unit_reservation_p (state
, _0bbb_
))
6502 else if (cpu_unit_reservation_p (state
, _0mbb_
))
6504 else if (cpu_unit_reservation_p (state
, _0mib_
))
6506 else if (cpu_unit_reservation_p (state
, _0mmb_
))
6508 else if (cpu_unit_reservation_p (state
, _0mfb_
))
6510 else if (cpu_unit_reservation_p (state
, _0mlx_
))
6515 if (cpu_unit_reservation_p (state
, _1mii_
))
6517 else if (cpu_unit_reservation_p (state
, _1mmi_
))
6519 else if (cpu_unit_reservation_p (state
, _1mfi_
))
6521 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
6523 else if (cpu_unit_reservation_p (state
, _1bbb_
))
6525 else if (cpu_unit_reservation_p (state
, _1mbb_
))
6527 else if (cpu_unit_reservation_p (state
, _1mib_
))
6529 else if (cpu_unit_reservation_p (state
, _1mmb_
))
6531 else if (cpu_unit_reservation_p (state
, _1mfb_
))
6533 else if (cpu_unit_reservation_p (state
, _1mlx_
))
6542 /* The following function returns an insn important for insn bundling
6543 followed by INSN and before TAIL. */
6546 get_next_important_insn (insn
, tail
)
6549 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
6551 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6552 && GET_CODE (PATTERN (insn
)) != USE
6553 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6558 /* The following function does insn bundling. Bundling algorithm is
6559 based on dynamic programming. It tries to insert different number of
6560 nop insns before/after the real insns. At the end of EBB, it chooses the
6561 best alternative and then, moving back in EBB, inserts templates for
6562 the best alternative. The algorithm is directed by information
6563 (changes of simulated processor cycle) created by the 2nd insn
6567 bundling (dump
, verbose
, prev_head_insn
, tail
)
6570 rtx prev_head_insn
, tail
;
6572 struct bundle_state
*curr_state
, *next_state
, *best_state
;
6573 rtx insn
, next_insn
;
6575 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
6576 int pos
= 0, max_pos
, template0
, template1
;
6579 enum attr_type type
;
6582 for (insn
= NEXT_INSN (prev_head_insn
);
6583 insn
&& insn
!= tail
;
6584 insn
= NEXT_INSN (insn
))
6590 dfa_clean_insn_cache ();
6591 initiate_bundle_state_table ();
6592 index_to_bundle_states
= xmalloc ((insn_num
+ 2)
6593 * sizeof (struct bundle_state
*));
6594 /* First (forward) pass -- generates states. */
6595 curr_state
= get_free_bundle_state ();
6596 curr_state
->insn
= NULL
;
6597 curr_state
->before_nops_num
= 0;
6598 curr_state
->after_nops_num
= 0;
6599 curr_state
->insn_num
= 0;
6600 curr_state
->cost
= 0;
6601 curr_state
->accumulated_insns_num
= 0;
6602 curr_state
->branch_deviation
= 0;
6603 curr_state
->next
= NULL
;
6604 curr_state
->originator
= NULL
;
6605 state_reset (curr_state
->dfa_state
);
6606 index_to_bundle_states
[0] = curr_state
;
6608 for (insn
= NEXT_INSN (prev_head_insn
);
6610 insn
= NEXT_INSN (insn
))
6612 && (ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6613 || GET_CODE (PATTERN (insn
)) == USE
6614 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6615 && GET_MODE (insn
) == TImode
)
6617 PUT_MODE (insn
, VOIDmode
);
6618 for (next_insn
= NEXT_INSN (insn
);
6620 next_insn
= NEXT_INSN (next_insn
))
6621 if (INSN_P (next_insn
)
6622 && ia64_safe_itanium_class (next_insn
) != ITANIUM_CLASS_IGNORE
6623 && GET_CODE (PATTERN (next_insn
)) != USE
6624 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
6626 PUT_MODE (next_insn
, TImode
);
6630 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6635 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6636 || GET_CODE (PATTERN (insn
)) == USE
6637 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6639 type
= ia64_safe_type (insn
);
6640 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6642 index_to_bundle_states
[insn_num
] = NULL
;
6643 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
6645 curr_state
= next_state
)
6647 pos
= curr_state
->accumulated_insns_num
% 3;
6648 next_state
= curr_state
->next
;
6649 /* Finish the current bundle in order to start a subsequent
6650 asm insn in a new bundle. */
6652 = (next_insn
!= NULL_RTX
6653 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
6654 && ia64_safe_type (next_insn
) == TYPE_UNKNOWN
);
6656 = (only_bundle_end_p
|| next_insn
== NULL_RTX
6657 || (GET_MODE (next_insn
) == TImode
6658 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
6659 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
6661 /* We need to insert 2 Nops for cases like M_MII. */
6662 || (type
== TYPE_M
&& ia64_tune
== PROCESSOR_ITANIUM
6663 && !bundle_end_p
&& pos
== 1))
6664 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
6666 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
6668 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
6671 if (index_to_bundle_states
[insn_num
] == NULL
)
6673 for (curr_state
= index_to_bundle_states
[insn_num
];
6675 curr_state
= curr_state
->next
)
6676 if (verbose
>= 2 && dump
)
6680 unsigned short one_automaton_state
;
6681 unsigned short oneb_automaton_state
;
6682 unsigned short two_automaton_state
;
6683 unsigned short twob_automaton_state
;
6688 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6689 curr_state
->unique_num
,
6690 (curr_state
->originator
== NULL
6691 ? -1 : curr_state
->originator
->unique_num
),
6693 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6694 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6695 (ia64_tune
== PROCESSOR_ITANIUM
6696 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6697 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6701 if (index_to_bundle_states
[insn_num
] == NULL
)
6703 /* Finding state with a minimal cost: */
6705 for (curr_state
= index_to_bundle_states
[insn_num
];
6707 curr_state
= curr_state
->next
)
6708 if (curr_state
->accumulated_insns_num
% 3 == 0
6709 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
6710 || (best_state
->cost
== curr_state
->cost
6711 && (curr_state
->accumulated_insns_num
6712 < best_state
->accumulated_insns_num
6713 || (curr_state
->accumulated_insns_num
6714 == best_state
->accumulated_insns_num
6715 && curr_state
->branch_deviation
6716 < best_state
->branch_deviation
)))))
6717 best_state
= curr_state
;
6718 /* Second (backward) pass: adding nops and templates: */
6719 insn_num
= best_state
->before_nops_num
;
6720 template0
= template1
= -1;
6721 for (curr_state
= best_state
;
6722 curr_state
->originator
!= NULL
;
6723 curr_state
= curr_state
->originator
)
6725 insn
= curr_state
->insn
;
6726 asm_p
= (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6727 || asm_noperands (PATTERN (insn
)) >= 0);
6729 if (verbose
>= 2 && dump
)
6733 unsigned short one_automaton_state
;
6734 unsigned short oneb_automaton_state
;
6735 unsigned short two_automaton_state
;
6736 unsigned short twob_automaton_state
;
6741 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6742 curr_state
->unique_num
,
6743 (curr_state
->originator
== NULL
6744 ? -1 : curr_state
->originator
->unique_num
),
6746 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6747 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6748 (ia64_tune
== PROCESSOR_ITANIUM
6749 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6750 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6753 max_pos
= get_max_pos (curr_state
->dfa_state
);
6754 if (max_pos
== 6 || (max_pos
== 3 && template0
< 0))
6758 template0
= get_template (curr_state
->dfa_state
, 3);
6761 template1
= get_template (curr_state
->dfa_state
, 3);
6762 template0
= get_template (curr_state
->dfa_state
, 6);
6765 if (max_pos
> 3 && template1
< 0)
6769 template1
= get_template (curr_state
->dfa_state
, 3);
6773 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
6776 emit_insn_after (nop
, insn
);
6784 b
= gen_bundle_selector (GEN_INT (template0
));
6785 ia64_emit_insn_before (b
, nop
);
6786 template0
= template1
;
6790 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
6791 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6792 && asm_noperands (PATTERN (insn
)) < 0)
6794 if (ia64_safe_type (insn
) == TYPE_L
)
6799 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
6800 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6801 && asm_noperands (PATTERN (insn
)) < 0)
6805 b
= gen_bundle_selector (GEN_INT (template0
));
6806 ia64_emit_insn_before (b
, insn
);
6807 b
= PREV_INSN (insn
);
6809 template0
= template1
;
6812 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
6815 ia64_emit_insn_before (nop
, insn
);
6816 nop
= PREV_INSN (insn
);
6825 b
= gen_bundle_selector (GEN_INT (template0
));
6826 ia64_emit_insn_before (b
, insn
);
6827 b
= PREV_INSN (insn
);
6829 template0
= template1
;
6834 if (ia64_tune
== PROCESSOR_ITANIUM
)
6835 /* Insert additional cycles for MM-insns: */
6836 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6841 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6842 || GET_CODE (PATTERN (insn
)) == USE
6843 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6845 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6846 if (INSN_UID (insn
) < clocks_length
&& add_cycles
[INSN_UID (insn
)])
6852 last
= prev_active_insn (insn
);
6853 pred_stop_p
= recog_memoized (last
) == CODE_FOR_insn_group_barrier
;
6855 last
= prev_active_insn (last
);
6857 for (;; last
= prev_active_insn (last
))
6858 if (recog_memoized (last
) == CODE_FOR_bundle_selector
)
6860 template0
= XINT (XVECEXP (PATTERN (last
), 0, 0), 0);
6863 = gen_bundle_selector (GEN_INT (2)); /* -> MFI */
6866 else if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6868 if ((pred_stop_p
&& n
== 0) || n
> 2
6869 || (template0
== 9 && n
!= 0))
6871 for (j
= 3 - n
; j
> 0; j
--)
6872 ia64_emit_insn_before (gen_nop (), insn
);
6873 add_cycles
[INSN_UID (insn
)]--;
6874 if (!pred_stop_p
|| add_cycles
[INSN_UID (insn
)])
6875 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6878 add_cycles
[INSN_UID (insn
)]--;
6879 for (i
= add_cycles
[INSN_UID (insn
)]; i
> 0; i
--)
6881 /* Insert .MII bundle. */
6882 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)),
6884 ia64_emit_insn_before (gen_nop (), insn
);
6885 ia64_emit_insn_before (gen_nop (), insn
);
6888 ia64_emit_insn_before
6889 (gen_insn_group_barrier (GEN_INT (3)), insn
);
6892 ia64_emit_insn_before (gen_nop (), insn
);
6893 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6896 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0
)),
6898 for (j
= n
; j
> 0; j
--)
6899 ia64_emit_insn_before (gen_nop (), insn
);
6901 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6905 free (index_to_bundle_states
);
6906 finish_bundle_state_table ();
6908 dfa_clean_insn_cache ();
6911 /* The following function is called at the end of scheduling BB or
6912 EBB. After reload, it inserts stop bits and does insn bundling. */
6915 ia64_sched_finish (dump
, sched_verbose
)
6920 fprintf (dump
, "// Finishing schedule.\n");
6921 if (!reload_completed
)
6923 if (reload_completed
)
6925 final_emit_insn_group_barriers (dump
);
6926 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
6927 current_sched_info
->next_tail
);
6928 if (sched_verbose
&& dump
)
6929 fprintf (dump
, "// finishing %d-%d\n",
6930 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
6931 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
6937 /* The following function inserts stop bits in scheduled BB or EBB. */
6940 final_emit_insn_group_barriers (dump
)
6941 FILE *dump ATTRIBUTE_UNUSED
;
6944 int need_barrier_p
= 0;
6945 rtx prev_insn
= NULL_RTX
;
6947 init_insn_group_barriers ();
6949 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
6950 insn
!= current_sched_info
->next_tail
;
6951 insn
= NEXT_INSN (insn
))
6953 if (GET_CODE (insn
) == BARRIER
)
6955 rtx last
= prev_active_insn (insn
);
6959 if (GET_CODE (last
) == JUMP_INSN
6960 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
6961 last
= prev_active_insn (last
);
6962 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6963 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
6965 init_insn_group_barriers ();
6967 prev_insn
= NULL_RTX
;
6969 else if (INSN_P (insn
))
6971 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
6973 init_insn_group_barriers ();
6975 prev_insn
= NULL_RTX
;
6977 else if (need_barrier_p
|| group_barrier_needed_p (insn
))
6979 if (TARGET_EARLY_STOP_BITS
)
6984 last
!= current_sched_info
->prev_head
;
6985 last
= PREV_INSN (last
))
6986 if (INSN_P (last
) && GET_MODE (last
) == TImode
6987 && stops_p
[INSN_UID (last
)])
6989 if (last
== current_sched_info
->prev_head
)
6991 last
= prev_active_insn (last
);
6993 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6994 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
6996 init_insn_group_barriers ();
6997 for (last
= NEXT_INSN (last
);
6999 last
= NEXT_INSN (last
))
7001 group_barrier_needed_p (last
);
7005 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7007 init_insn_group_barriers ();
7009 group_barrier_needed_p (insn
);
7010 prev_insn
= NULL_RTX
;
7012 else if (recog_memoized (insn
) >= 0)
7014 need_barrier_p
= (GET_CODE (insn
) == CALL_INSN
7015 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
7016 || asm_noperands (PATTERN (insn
)) >= 0);
7023 /* If the following function returns TRUE, we will use the the DFA
7027 ia64_use_dfa_pipeline_interface ()
7032 /* If the following function returns TRUE, we will use the the DFA
7036 ia64_first_cycle_multipass_dfa_lookahead ()
7038 return (reload_completed
? 6 : 4);
7041 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7044 ia64_init_dfa_pre_cycle_insn ()
7046 if (temp_dfa_state
== NULL
)
7048 dfa_state_size
= state_size ();
7049 temp_dfa_state
= xmalloc (dfa_state_size
);
7050 prev_cycle_state
= xmalloc (dfa_state_size
);
7052 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
7053 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
7054 recog_memoized (dfa_pre_cycle_insn
);
7055 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7056 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
7057 recog_memoized (dfa_stop_insn
);
7060 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7061 used by the DFA insn scheduler. */
7064 ia64_dfa_pre_cycle_insn ()
7066 return dfa_pre_cycle_insn
;
7069 /* The following function returns TRUE if PRODUCER (of type ilog or
7070 ld) produces address for CONSUMER (of type st or stf). */
7073 ia64_st_address_bypass_p (producer
, consumer
)
7079 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7081 dest
= ia64_single_set (producer
);
7082 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7083 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7085 if (GET_CODE (reg
) == SUBREG
)
7086 reg
= SUBREG_REG (reg
);
7087 dest
= ia64_single_set (consumer
);
7088 if (dest
== NULL_RTX
|| (mem
= SET_DEST (dest
)) == NULL_RTX
7089 || GET_CODE (mem
) != MEM
)
7091 return reg_mentioned_p (reg
, mem
);
7094 /* The following function returns TRUE if PRODUCER (of type ilog or
7095 ld) produces address for CONSUMER (of type ld or fld). */
7098 ia64_ld_address_bypass_p (producer
, consumer
)
7102 rtx dest
, src
, reg
, mem
;
7104 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7106 dest
= ia64_single_set (producer
);
7107 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7108 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7110 if (GET_CODE (reg
) == SUBREG
)
7111 reg
= SUBREG_REG (reg
);
7112 src
= ia64_single_set (consumer
);
7113 if (src
== NULL_RTX
|| (mem
= SET_SRC (src
)) == NULL_RTX
)
7115 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
7116 mem
= XVECEXP (mem
, 0, 0);
7117 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
7118 mem
= XEXP (mem
, 0);
7120 /* Note that LO_SUM is used for GOT loads. */
7121 if (GET_CODE (mem
) != LO_SUM
&& GET_CODE (mem
) != MEM
)
7124 return reg_mentioned_p (reg
, mem
);
7127 /* The following function returns TRUE if INSN produces address for a
7128 load/store insn. We will place such insns into M slot because it
7129 decreases its latency time. */
7132 ia64_produce_address_p (insn
)
7139 /* Emit pseudo-ops for the assembler to describe predicate relations.
7140 At present this assumes that we only consider predicate pairs to
7141 be mutex, and that the assembler can deduce proper values from
7142 straight-line code. */
7145 emit_predicate_relation_info ()
7149 FOR_EACH_BB_REVERSE (bb
)
7152 rtx head
= bb
->head
;
7154 /* We only need such notes at code labels. */
7155 if (GET_CODE (head
) != CODE_LABEL
)
7157 if (GET_CODE (NEXT_INSN (head
)) == NOTE
7158 && NOTE_LINE_NUMBER (NEXT_INSN (head
)) == NOTE_INSN_BASIC_BLOCK
)
7159 head
= NEXT_INSN (head
);
7161 for (r
= PR_REG (0); r
< PR_REG (64); r
+= 2)
7162 if (REGNO_REG_SET_P (bb
->global_live_at_start
, r
))
7164 rtx p
= gen_rtx_REG (BImode
, r
);
7165 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
7166 if (head
== bb
->end
)
7172 /* Look for conditional calls that do not return, and protect predicate
7173 relations around them. Otherwise the assembler will assume the call
7174 returns, and complain about uses of call-clobbered predicates after
7176 FOR_EACH_BB_REVERSE (bb
)
7178 rtx insn
= bb
->head
;
7182 if (GET_CODE (insn
) == CALL_INSN
7183 && GET_CODE (PATTERN (insn
)) == COND_EXEC
7184 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
7186 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
7187 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
7188 if (bb
->head
== insn
)
7190 if (bb
->end
== insn
)
7194 if (insn
== bb
->end
)
7196 insn
= NEXT_INSN (insn
);
7201 /* Perform machine dependent operations on the rtl chain INSNS. */
7206 /* We are freeing block_for_insn in the toplev to keep compatibility
7207 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7208 compute_bb_for_insn ();
7210 /* If optimizing, we'll have split before scheduling. */
7212 split_all_insns (0);
7214 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7215 non-optimizing bootstrap. */
7216 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
7218 if (ia64_flag_schedule_insns2
)
7220 timevar_push (TV_SCHED2
);
7221 ia64_final_schedule
= 1;
7223 initiate_bundle_states ();
7224 ia64_nop
= make_insn_raw (gen_nop ());
7225 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
7226 recog_memoized (ia64_nop
);
7227 clocks_length
= get_max_uid () + 1;
7228 stops_p
= (char *) xmalloc (clocks_length
);
7229 memset (stops_p
, 0, clocks_length
);
7230 if (ia64_tune
== PROCESSOR_ITANIUM
)
7232 clocks
= (int *) xmalloc (clocks_length
* sizeof (int));
7233 memset (clocks
, 0, clocks_length
* sizeof (int));
7234 add_cycles
= (int *) xmalloc (clocks_length
* sizeof (int));
7235 memset (add_cycles
, 0, clocks_length
* sizeof (int));
7237 if (ia64_tune
== PROCESSOR_ITANIUM2
)
7239 pos_1
= get_cpu_unit_code ("2_1");
7240 pos_2
= get_cpu_unit_code ("2_2");
7241 pos_3
= get_cpu_unit_code ("2_3");
7242 pos_4
= get_cpu_unit_code ("2_4");
7243 pos_5
= get_cpu_unit_code ("2_5");
7244 pos_6
= get_cpu_unit_code ("2_6");
7245 _0mii_
= get_cpu_unit_code ("2b_0mii.");
7246 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
7247 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
7248 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
7249 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
7250 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
7251 _0mib_
= get_cpu_unit_code ("2b_0mib.");
7252 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
7253 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
7254 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
7255 _1mii_
= get_cpu_unit_code ("2b_1mii.");
7256 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
7257 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
7258 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
7259 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
7260 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
7261 _1mib_
= get_cpu_unit_code ("2b_1mib.");
7262 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
7263 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
7264 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
7268 pos_1
= get_cpu_unit_code ("1_1");
7269 pos_2
= get_cpu_unit_code ("1_2");
7270 pos_3
= get_cpu_unit_code ("1_3");
7271 pos_4
= get_cpu_unit_code ("1_4");
7272 pos_5
= get_cpu_unit_code ("1_5");
7273 pos_6
= get_cpu_unit_code ("1_6");
7274 _0mii_
= get_cpu_unit_code ("1b_0mii.");
7275 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
7276 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
7277 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
7278 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
7279 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
7280 _0mib_
= get_cpu_unit_code ("1b_0mib.");
7281 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
7282 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
7283 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
7284 _1mii_
= get_cpu_unit_code ("1b_1mii.");
7285 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
7286 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
7287 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
7288 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
7289 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
7290 _1mib_
= get_cpu_unit_code ("1b_1mib.");
7291 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
7292 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
7293 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
7295 schedule_ebbs (rtl_dump_file
);
7296 finish_bundle_states ();
7297 if (ia64_tune
== PROCESSOR_ITANIUM
)
7303 emit_insn_group_barriers (rtl_dump_file
);
7305 ia64_final_schedule
= 0;
7306 timevar_pop (TV_SCHED2
);
7309 emit_all_insn_group_barriers (rtl_dump_file
);
7311 /* A call must not be the last instruction in a function, so that the
7312 return address is still within the function, so that unwinding works
7313 properly. Note that IA-64 differs from dwarf2 on this point. */
7314 if (flag_unwind_tables
|| (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7319 insn
= get_last_insn ();
7320 if (! INSN_P (insn
))
7321 insn
= prev_active_insn (insn
);
7322 if (GET_CODE (insn
) == INSN
7323 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
7324 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
7327 insn
= prev_active_insn (insn
);
7329 if (GET_CODE (insn
) == CALL_INSN
)
7332 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7333 emit_insn (gen_break_f ());
7334 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7339 emit_predicate_relation_info ();
7342 /* Return true if REGNO is used by the epilogue. */
7345 ia64_epilogue_uses (regno
)
7351 /* When a function makes a call through a function descriptor, we
7352 will write a (potentially) new value to "gp". After returning
7353 from such a call, we need to make sure the function restores the
7354 original gp-value, even if the function itself does not use the
7356 return (TARGET_CONST_GP
&& !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
));
7358 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7359 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7360 /* For functions defined with the syscall_linkage attribute, all
7361 input registers are marked as live at all function exits. This
7362 prevents the register allocator from using the input registers,
7363 which in turn makes it possible to restart a system call after
7364 an interrupt without having to save/restore the input registers.
7365 This also prevents kernel data from leaking to application code. */
7366 return lookup_attribute ("syscall_linkage",
7367 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
7370 /* Conditional return patterns can't represent the use of `b0' as
7371 the return address, so we force the value live this way. */
7375 /* Likewise for ar.pfs, which is used by br.ret. */
7383 /* Return true if REGNO is used by the frame unwinder. */
7386 ia64_eh_uses (regno
)
7389 if (! reload_completed
)
7392 if (current_frame_info
.reg_save_b0
7393 && regno
== current_frame_info
.reg_save_b0
)
7395 if (current_frame_info
.reg_save_pr
7396 && regno
== current_frame_info
.reg_save_pr
)
7398 if (current_frame_info
.reg_save_ar_pfs
7399 && regno
== current_frame_info
.reg_save_ar_pfs
)
7401 if (current_frame_info
.reg_save_ar_unat
7402 && regno
== current_frame_info
.reg_save_ar_unat
)
7404 if (current_frame_info
.reg_save_ar_lc
7405 && regno
== current_frame_info
.reg_save_ar_lc
)
7411 /* Return true if this goes in small data/bss. */
7413 /* ??? We could also support own long data here. Generating movl/add/ld8
7414 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7415 code faster because there is one less load. This also includes incomplete
7416 types which can't go in sdata/sbss. */
7419 ia64_in_small_data_p (exp
)
7422 if (TARGET_NO_SDATA
)
7425 /* We want to merge strings, so we never consider them small data. */
7426 if (TREE_CODE (exp
) == STRING_CST
)
7429 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
7431 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
7432 if (strcmp (section
, ".sdata") == 0
7433 || strcmp (section
, ".sbss") == 0)
7438 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
7440 /* If this is an incomplete type with size 0, then we can't put it
7441 in sdata because it might be too big when completed. */
7442 if (size
> 0 && size
<= ia64_section_threshold
)
7449 /* Output assembly directives for prologue regions. */
7451 /* The current basic block number. */
7453 static bool last_block
;
7455 /* True if we need a copy_state command at the start of the next block. */
7457 static bool need_copy_state
;
7459 /* The function emits unwind directives for the start of an epilogue. */
7464 /* If this isn't the last block of the function, then we need to label the
7465 current state, and copy it back in at the start of the next block. */
7469 fprintf (asm_out_file
, "\t.label_state 1\n");
7470 need_copy_state
= true;
7473 fprintf (asm_out_file
, "\t.restore sp\n");
7476 /* This function processes a SET pattern looking for specific patterns
7477 which result in emitting an assembly directive required for unwinding. */
7480 process_set (asm_out_file
, pat
)
7484 rtx src
= SET_SRC (pat
);
7485 rtx dest
= SET_DEST (pat
);
7486 int src_regno
, dest_regno
;
7488 /* Look for the ALLOC insn. */
7489 if (GET_CODE (src
) == UNSPEC_VOLATILE
7490 && XINT (src
, 1) == UNSPECV_ALLOC
7491 && GET_CODE (dest
) == REG
)
7493 dest_regno
= REGNO (dest
);
7495 /* If this isn't the final destination for ar.pfs, the alloc
7496 shouldn't have been marked frame related. */
7497 if (dest_regno
!= current_frame_info
.reg_save_ar_pfs
)
7500 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
7501 ia64_dbx_register_number (dest_regno
));
7505 /* Look for SP = .... */
7506 if (GET_CODE (dest
) == REG
&& REGNO (dest
) == STACK_POINTER_REGNUM
)
7508 if (GET_CODE (src
) == PLUS
)
7510 rtx op0
= XEXP (src
, 0);
7511 rtx op1
= XEXP (src
, 1);
7512 if (op0
== dest
&& GET_CODE (op1
) == CONST_INT
)
7514 if (INTVAL (op1
) < 0)
7516 fputs ("\t.fframe ", asm_out_file
);
7517 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
,
7519 fputc ('\n', asm_out_file
);
7522 process_epilogue ();
7527 else if (GET_CODE (src
) == REG
7528 && REGNO (src
) == HARD_FRAME_POINTER_REGNUM
)
7529 process_epilogue ();
7536 /* Register move we need to look at. */
7537 if (GET_CODE (dest
) == REG
&& GET_CODE (src
) == REG
)
7539 src_regno
= REGNO (src
);
7540 dest_regno
= REGNO (dest
);
7545 /* Saving return address pointer. */
7546 if (dest_regno
!= current_frame_info
.reg_save_b0
)
7548 fprintf (asm_out_file
, "\t.save rp, r%d\n",
7549 ia64_dbx_register_number (dest_regno
));
7553 if (dest_regno
!= current_frame_info
.reg_save_pr
)
7555 fprintf (asm_out_file
, "\t.save pr, r%d\n",
7556 ia64_dbx_register_number (dest_regno
));
7559 case AR_UNAT_REGNUM
:
7560 if (dest_regno
!= current_frame_info
.reg_save_ar_unat
)
7562 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
7563 ia64_dbx_register_number (dest_regno
));
7567 if (dest_regno
!= current_frame_info
.reg_save_ar_lc
)
7569 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
7570 ia64_dbx_register_number (dest_regno
));
7573 case STACK_POINTER_REGNUM
:
7574 if (dest_regno
!= HARD_FRAME_POINTER_REGNUM
7575 || ! frame_pointer_needed
)
7577 fprintf (asm_out_file
, "\t.vframe r%d\n",
7578 ia64_dbx_register_number (dest_regno
));
7582 /* Everything else should indicate being stored to memory. */
7587 /* Memory store we need to look at. */
7588 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
7594 if (GET_CODE (XEXP (dest
, 0)) == REG
)
7596 base
= XEXP (dest
, 0);
7599 else if (GET_CODE (XEXP (dest
, 0)) == PLUS
7600 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
)
7602 base
= XEXP (XEXP (dest
, 0), 0);
7603 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
7608 if (base
== hard_frame_pointer_rtx
)
7610 saveop
= ".savepsp";
7613 else if (base
== stack_pointer_rtx
)
7618 src_regno
= REGNO (src
);
7622 if (current_frame_info
.reg_save_b0
!= 0)
7624 fprintf (asm_out_file
, "\t%s rp, %ld\n", saveop
, off
);
7628 if (current_frame_info
.reg_save_pr
!= 0)
7630 fprintf (asm_out_file
, "\t%s pr, %ld\n", saveop
, off
);
7634 if (current_frame_info
.reg_save_ar_lc
!= 0)
7636 fprintf (asm_out_file
, "\t%s ar.lc, %ld\n", saveop
, off
);
7640 if (current_frame_info
.reg_save_ar_pfs
!= 0)
7642 fprintf (asm_out_file
, "\t%s ar.pfs, %ld\n", saveop
, off
);
7645 case AR_UNAT_REGNUM
:
7646 if (current_frame_info
.reg_save_ar_unat
!= 0)
7648 fprintf (asm_out_file
, "\t%s ar.unat, %ld\n", saveop
, off
);
7655 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
7656 1 << (src_regno
- GR_REG (4)));
7664 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
7665 1 << (src_regno
- BR_REG (1)));
7672 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
7673 1 << (src_regno
- FR_REG (2)));
7676 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7677 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7678 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7679 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7680 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
7681 1 << (src_regno
- FR_REG (12)));
7693 /* This function looks at a single insn and emits any directives
7694 required to unwind this insn. */
7696 process_for_unwind_directive (asm_out_file
, insn
)
7700 if (flag_unwind_tables
7701 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7705 if (GET_CODE (insn
) == NOTE
7706 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
7708 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
7710 /* Restore unwind state from immediately before the epilogue. */
7711 if (need_copy_state
)
7713 fprintf (asm_out_file
, "\t.body\n");
7714 fprintf (asm_out_file
, "\t.copy_state 1\n");
7715 need_copy_state
= false;
7719 if (GET_CODE (insn
) == NOTE
|| ! RTX_FRAME_RELATED_P (insn
))
7722 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
7724 pat
= XEXP (pat
, 0);
7726 pat
= PATTERN (insn
);
7728 switch (GET_CODE (pat
))
7731 process_set (asm_out_file
, pat
);
7737 int limit
= XVECLEN (pat
, 0);
7738 for (par_index
= 0; par_index
< limit
; par_index
++)
7740 rtx x
= XVECEXP (pat
, 0, par_index
);
7741 if (GET_CODE (x
) == SET
)
7742 process_set (asm_out_file
, x
);
7755 ia64_init_builtins ()
7757 tree psi_type_node
= build_pointer_type (integer_type_node
);
7758 tree pdi_type_node
= build_pointer_type (long_integer_type_node
);
7760 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
7761 tree si_ftype_psi_si_si
7762 = build_function_type_list (integer_type_node
,
7763 psi_type_node
, integer_type_node
,
7764 integer_type_node
, NULL_TREE
);
7766 /* __sync_val_compare_and_swap_di */
7767 tree di_ftype_pdi_di_di
7768 = build_function_type_list (long_integer_type_node
,
7769 pdi_type_node
, long_integer_type_node
,
7770 long_integer_type_node
, NULL_TREE
);
7771 /* __sync_bool_compare_and_swap_di */
7772 tree si_ftype_pdi_di_di
7773 = build_function_type_list (integer_type_node
,
7774 pdi_type_node
, long_integer_type_node
,
7775 long_integer_type_node
, NULL_TREE
);
7776 /* __sync_synchronize */
7777 tree void_ftype_void
7778 = build_function_type (void_type_node
, void_list_node
);
7780 /* __sync_lock_test_and_set_si */
7781 tree si_ftype_psi_si
7782 = build_function_type_list (integer_type_node
,
7783 psi_type_node
, integer_type_node
, NULL_TREE
);
7785 /* __sync_lock_test_and_set_di */
7786 tree di_ftype_pdi_di
7787 = build_function_type_list (long_integer_type_node
,
7788 pdi_type_node
, long_integer_type_node
,
7791 /* __sync_lock_release_si */
7793 = build_function_type_list (void_type_node
, psi_type_node
, NULL_TREE
);
7795 /* __sync_lock_release_di */
7797 = build_function_type_list (void_type_node
, pdi_type_node
, NULL_TREE
);
7799 #define def_builtin(name, type, code) \
7800 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
7802 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si
,
7803 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
);
7804 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di
,
7805 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
);
7806 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si
,
7807 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
);
7808 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di
,
7809 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
);
7811 def_builtin ("__sync_synchronize", void_ftype_void
,
7812 IA64_BUILTIN_SYNCHRONIZE
);
7814 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si
,
7815 IA64_BUILTIN_LOCK_TEST_AND_SET_SI
);
7816 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di
,
7817 IA64_BUILTIN_LOCK_TEST_AND_SET_DI
);
7818 def_builtin ("__sync_lock_release_si", void_ftype_psi
,
7819 IA64_BUILTIN_LOCK_RELEASE_SI
);
7820 def_builtin ("__sync_lock_release_di", void_ftype_pdi
,
7821 IA64_BUILTIN_LOCK_RELEASE_DI
);
7823 def_builtin ("__builtin_ia64_bsp",
7824 build_function_type (ptr_type_node
, void_list_node
),
7827 def_builtin ("__builtin_ia64_flushrs",
7828 build_function_type (void_type_node
, void_list_node
),
7829 IA64_BUILTIN_FLUSHRS
);
7831 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si
,
7832 IA64_BUILTIN_FETCH_AND_ADD_SI
);
7833 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si
,
7834 IA64_BUILTIN_FETCH_AND_SUB_SI
);
7835 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si
,
7836 IA64_BUILTIN_FETCH_AND_OR_SI
);
7837 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si
,
7838 IA64_BUILTIN_FETCH_AND_AND_SI
);
7839 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si
,
7840 IA64_BUILTIN_FETCH_AND_XOR_SI
);
7841 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si
,
7842 IA64_BUILTIN_FETCH_AND_NAND_SI
);
7844 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si
,
7845 IA64_BUILTIN_ADD_AND_FETCH_SI
);
7846 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si
,
7847 IA64_BUILTIN_SUB_AND_FETCH_SI
);
7848 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si
,
7849 IA64_BUILTIN_OR_AND_FETCH_SI
);
7850 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si
,
7851 IA64_BUILTIN_AND_AND_FETCH_SI
);
7852 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si
,
7853 IA64_BUILTIN_XOR_AND_FETCH_SI
);
7854 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si
,
7855 IA64_BUILTIN_NAND_AND_FETCH_SI
);
7857 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di
,
7858 IA64_BUILTIN_FETCH_AND_ADD_DI
);
7859 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di
,
7860 IA64_BUILTIN_FETCH_AND_SUB_DI
);
7861 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di
,
7862 IA64_BUILTIN_FETCH_AND_OR_DI
);
7863 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di
,
7864 IA64_BUILTIN_FETCH_AND_AND_DI
);
7865 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di
,
7866 IA64_BUILTIN_FETCH_AND_XOR_DI
);
7867 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di
,
7868 IA64_BUILTIN_FETCH_AND_NAND_DI
);
7870 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di
,
7871 IA64_BUILTIN_ADD_AND_FETCH_DI
);
7872 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di
,
7873 IA64_BUILTIN_SUB_AND_FETCH_DI
);
7874 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di
,
7875 IA64_BUILTIN_OR_AND_FETCH_DI
);
7876 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di
,
7877 IA64_BUILTIN_AND_AND_FETCH_DI
);
7878 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di
,
7879 IA64_BUILTIN_XOR_AND_FETCH_DI
);
7880 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di
,
7881 IA64_BUILTIN_NAND_AND_FETCH_DI
);
7886 /* Expand fetch_and_op intrinsics. The basic code sequence is:
7894 cmpxchgsz.acq tmp = [ptr], tmp
7895 } while (tmp != ret)
7899 ia64_expand_fetch_and_op (binoptab
, mode
, arglist
, target
)
7901 enum machine_mode mode
;
7905 rtx ret
, label
, tmp
, ccv
, insn
, mem
, value
;
7908 arg0
= TREE_VALUE (arglist
);
7909 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7910 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
7911 #ifdef POINTERS_EXTEND_UNSIGNED
7912 if (GET_MODE(mem
) != Pmode
)
7913 mem
= convert_memory_address (Pmode
, mem
);
7915 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
7917 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
7918 MEM_VOLATILE_P (mem
) = 1;
7920 if (target
&& register_operand (target
, mode
))
7923 ret
= gen_reg_rtx (mode
);
7925 emit_insn (gen_mf ());
7927 /* Special case for fetchadd instructions. */
7928 if (binoptab
== add_optab
&& fetchadd_operand (value
, VOIDmode
))
7931 insn
= gen_fetchadd_acq_si (ret
, mem
, value
);
7933 insn
= gen_fetchadd_acq_di (ret
, mem
, value
);
7938 tmp
= gen_reg_rtx (mode
);
7939 ccv
= gen_rtx_REG (mode
, AR_CCV_REGNUM
);
7940 emit_move_insn (tmp
, mem
);
7942 label
= gen_label_rtx ();
7944 emit_move_insn (ret
, tmp
);
7945 emit_move_insn (ccv
, tmp
);
7947 /* Perform the specific operation. Special case NAND by noticing
7948 one_cmpl_optab instead. */
7949 if (binoptab
== one_cmpl_optab
)
7951 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
7952 binoptab
= and_optab
;
7954 tmp
= expand_binop (mode
, binoptab
, tmp
, value
, tmp
, 1, OPTAB_WIDEN
);
7957 insn
= gen_cmpxchg_acq_si (tmp
, mem
, tmp
, ccv
);
7959 insn
= gen_cmpxchg_acq_di (tmp
, mem
, tmp
, ccv
);
7962 emit_cmp_and_jump_insns (tmp
, ret
, NE
, 0, mode
, 1, label
);
7967 /* Expand op_and_fetch intrinsics. The basic code sequence is:
7974 ret = tmp <op> value;
7975 cmpxchgsz.acq tmp = [ptr], ret
7976 } while (tmp != old)
7980 ia64_expand_op_and_fetch (binoptab
, mode
, arglist
, target
)
7982 enum machine_mode mode
;
7986 rtx old
, label
, tmp
, ret
, ccv
, insn
, mem
, value
;
7989 arg0
= TREE_VALUE (arglist
);
7990 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7991 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
7992 #ifdef POINTERS_EXTEND_UNSIGNED
7993 if (GET_MODE(mem
) != Pmode
)
7994 mem
= convert_memory_address (Pmode
, mem
);
7997 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
7999 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8000 MEM_VOLATILE_P (mem
) = 1;
8002 if (target
&& ! register_operand (target
, mode
))
8005 emit_insn (gen_mf ());
8006 tmp
= gen_reg_rtx (mode
);
8007 old
= gen_reg_rtx (mode
);
8008 ccv
= gen_rtx_REG (mode
, AR_CCV_REGNUM
);
8010 emit_move_insn (tmp
, mem
);
8012 label
= gen_label_rtx ();
8014 emit_move_insn (old
, tmp
);
8015 emit_move_insn (ccv
, tmp
);
8017 /* Perform the specific operation. Special case NAND by noticing
8018 one_cmpl_optab instead. */
8019 if (binoptab
== one_cmpl_optab
)
8021 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8022 binoptab
= and_optab
;
8024 ret
= expand_binop (mode
, binoptab
, tmp
, value
, target
, 1, OPTAB_WIDEN
);
8027 insn
= gen_cmpxchg_acq_si (tmp
, mem
, ret
, ccv
);
8029 insn
= gen_cmpxchg_acq_di (tmp
, mem
, ret
, ccv
);
8032 emit_cmp_and_jump_insns (tmp
, old
, NE
, 0, mode
, 1, label
);
8037 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8041 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8044 For bool_ it's the same except return ret == oldval.
8048 ia64_expand_compare_and_swap (rmode
, mode
, boolp
, arglist
, target
)
8049 enum machine_mode rmode
;
8050 enum machine_mode mode
;
8055 tree arg0
, arg1
, arg2
;
8056 rtx mem
, old
, new, ccv
, tmp
, insn
;
8058 arg0
= TREE_VALUE (arglist
);
8059 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8060 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8061 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8062 old
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8063 new = expand_expr (arg2
, NULL_RTX
, mode
, 0);
8065 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8066 MEM_VOLATILE_P (mem
) = 1;
8068 if (! register_operand (old
, mode
))
8069 old
= copy_to_mode_reg (mode
, old
);
8070 if (! register_operand (new, mode
))
8071 new = copy_to_mode_reg (mode
, new);
8073 if (! boolp
&& target
&& register_operand (target
, mode
))
8076 tmp
= gen_reg_rtx (mode
);
8078 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8080 emit_move_insn (ccv
, old
);
8083 rtx ccvtmp
= gen_reg_rtx (DImode
);
8084 emit_insn (gen_zero_extendsidi2 (ccvtmp
, old
));
8085 emit_move_insn (ccv
, ccvtmp
);
8087 emit_insn (gen_mf ());
8089 insn
= gen_cmpxchg_acq_si (tmp
, mem
, new, ccv
);
8091 insn
= gen_cmpxchg_acq_di (tmp
, mem
, new, ccv
);
8097 target
= gen_reg_rtx (rmode
);
8098 return emit_store_flag_force (target
, EQ
, tmp
, old
, mode
, 1, 1);
8104 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8107 ia64_expand_lock_test_and_set (mode
, arglist
, target
)
8108 enum machine_mode mode
;
8113 rtx mem
, new, ret
, insn
;
8115 arg0
= TREE_VALUE (arglist
);
8116 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8117 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8118 new = expand_expr (arg1
, NULL_RTX
, mode
, 0);
8120 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8121 MEM_VOLATILE_P (mem
) = 1;
8122 if (! register_operand (new, mode
))
8123 new = copy_to_mode_reg (mode
, new);
8125 if (target
&& register_operand (target
, mode
))
8128 ret
= gen_reg_rtx (mode
);
8131 insn
= gen_xchgsi (ret
, mem
, new);
8133 insn
= gen_xchgdi (ret
, mem
, new);
8139 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8142 ia64_expand_lock_release (mode
, arglist
, target
)
8143 enum machine_mode mode
;
8145 rtx target ATTRIBUTE_UNUSED
;
8150 arg0
= TREE_VALUE (arglist
);
8151 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8153 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8154 MEM_VOLATILE_P (mem
) = 1;
8156 emit_move_insn (mem
, const0_rtx
);
8162 ia64_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
8165 rtx subtarget ATTRIBUTE_UNUSED
;
8166 enum machine_mode mode ATTRIBUTE_UNUSED
;
8167 int ignore ATTRIBUTE_UNUSED
;
8169 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8170 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8171 tree arglist
= TREE_OPERAND (exp
, 1);
8172 enum machine_mode rmode
= VOIDmode
;
8176 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8177 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8182 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8183 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8184 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8185 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8186 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8187 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8188 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8189 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8190 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8191 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8192 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8193 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8194 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8195 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8199 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8204 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8209 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8210 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8211 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8212 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8213 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8214 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8215 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8216 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8217 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8218 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8219 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8220 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8221 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8222 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8232 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8233 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8234 return ia64_expand_compare_and_swap (rmode
, mode
, 1, arglist
,
8237 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8238 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8239 return ia64_expand_compare_and_swap (rmode
, mode
, 0, arglist
,
8242 case IA64_BUILTIN_SYNCHRONIZE
:
8243 emit_insn (gen_mf ());
8246 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8247 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8248 return ia64_expand_lock_test_and_set (mode
, arglist
, target
);
8250 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8251 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8252 return ia64_expand_lock_release (mode
, arglist
, target
);
8254 case IA64_BUILTIN_BSP
:
8255 if (! target
|| ! register_operand (target
, DImode
))
8256 target
= gen_reg_rtx (DImode
);
8257 emit_insn (gen_bsp_value (target
));
8260 case IA64_BUILTIN_FLUSHRS
:
8261 emit_insn (gen_flushrs ());
8264 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8265 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8266 return ia64_expand_fetch_and_op (add_optab
, mode
, arglist
, target
);
8268 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8269 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8270 return ia64_expand_fetch_and_op (sub_optab
, mode
, arglist
, target
);
8272 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8273 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8274 return ia64_expand_fetch_and_op (ior_optab
, mode
, arglist
, target
);
8276 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8277 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8278 return ia64_expand_fetch_and_op (and_optab
, mode
, arglist
, target
);
8280 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8281 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8282 return ia64_expand_fetch_and_op (xor_optab
, mode
, arglist
, target
);
8284 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8285 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8286 return ia64_expand_fetch_and_op (one_cmpl_optab
, mode
, arglist
, target
);
8288 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8289 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8290 return ia64_expand_op_and_fetch (add_optab
, mode
, arglist
, target
);
8292 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8293 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8294 return ia64_expand_op_and_fetch (sub_optab
, mode
, arglist
, target
);
8296 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8297 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8298 return ia64_expand_op_and_fetch (ior_optab
, mode
, arglist
, target
);
8300 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8301 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8302 return ia64_expand_op_and_fetch (and_optab
, mode
, arglist
, target
);
8304 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8305 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8306 return ia64_expand_op_and_fetch (xor_optab
, mode
, arglist
, target
);
8308 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8309 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8310 return ia64_expand_op_and_fetch (one_cmpl_optab
, mode
, arglist
, target
);
8319 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8320 most significant bits of the stack slot. */
8323 ia64_hpux_function_arg_padding (mode
, type
)
8324 enum machine_mode mode
;
8327 /* Exception to normal case for structures/unions/etc. */
8329 if (type
&& AGGREGATE_TYPE_P (type
)
8330 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
8333 /* This is the standard FUNCTION_ARG_PADDING with !BYTES_BIG_ENDIAN
8334 hardwired to be true. */
8336 return((mode
== BLKmode
8337 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
8338 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
8339 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
8340 ? downward
: upward
);
8343 /* Linked list of all external functions that are to be emitted by GCC.
8344 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8345 order to avoid putting out names that are never really used. */
8347 struct extern_func_list
8349 struct extern_func_list
*next
; /* next external */
8350 char *name
; /* name of the external */
8351 } *extern_func_head
= 0;
8354 ia64_hpux_add_extern_decl (name
)
8357 struct extern_func_list
*p
;
8359 p
= (struct extern_func_list
*) xmalloc (sizeof (struct extern_func_list
));
8360 p
->name
= xmalloc (strlen (name
) + 1);
8361 strcpy(p
->name
, name
);
8362 p
->next
= extern_func_head
;
8363 extern_func_head
= p
;
8366 /* Print out the list of used global functions. */
8369 ia64_hpux_asm_file_end (file
)
8372 while (extern_func_head
)
8374 const char *real_name
;
8377 real_name
= (* targetm
.strip_name_encoding
) (extern_func_head
->name
);
8378 decl
= maybe_get_identifier (real_name
);
8381 || (! TREE_ASM_WRITTEN (decl
) && TREE_SYMBOL_REFERENCED (decl
)))
8384 TREE_ASM_WRITTEN (decl
) = 1;
8385 (*targetm
.asm_out
.globalize_label
) (file
, extern_func_head
->name
);
8386 fprintf (file
, "%s", TYPE_ASM_OP
);
8387 assemble_name (file
, extern_func_head
->name
);
8389 fprintf (file
, TYPE_OPERAND_FMT
, "function");
8392 extern_func_head
= extern_func_head
->next
;
8397 /* Switch to the section to which we should output X. The only thing
8398 special we do here is to honor small data. */
8401 ia64_select_rtx_section (mode
, x
, align
)
8402 enum machine_mode mode
;
8404 unsigned HOST_WIDE_INT align
;
8406 if (GET_MODE_SIZE (mode
) > 0
8407 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
)
8410 default_elf_select_rtx_section (mode
, x
, align
);
8413 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8414 Pretend flag_pic is always set. */
8417 ia64_rwreloc_select_section (exp
, reloc
, align
)
8420 unsigned HOST_WIDE_INT align
;
8422 default_elf_select_section_1 (exp
, reloc
, align
, true);
8426 ia64_rwreloc_unique_section (decl
, reloc
)
8430 default_unique_section_1 (decl
, reloc
, true);
8434 ia64_rwreloc_select_rtx_section (mode
, x
, align
)
8435 enum machine_mode mode
;
8437 unsigned HOST_WIDE_INT align
;
8439 int save_pic
= flag_pic
;
8441 ia64_select_rtx_section (mode
, x
, align
);
8442 flag_pic
= save_pic
;
8446 ia64_rwreloc_section_type_flags (decl
, name
, reloc
)
8451 return default_section_type_flags_1 (decl
, name
, reloc
, true);
8455 /* Output the assembler code for a thunk function. THUNK_DECL is the
8456 declaration for the thunk function itself, FUNCTION is the decl for
8457 the target function. DELTA is an immediate constant offset to be
8458 added to THIS. If VCALL_OFFSET is nonzero, the word at
8459 *(*this + vcall_offset) should be added to THIS. */
8462 ia64_output_mi_thunk (file
, thunk
, delta
, vcall_offset
, function
)
8464 tree thunk ATTRIBUTE_UNUSED
;
8465 HOST_WIDE_INT delta
;
8466 HOST_WIDE_INT vcall_offset
;
8469 rtx
this, insn
, funexp
;
8471 reload_completed
= 1;
8474 /* Set things up as ia64_expand_prologue might. */
8475 last_scratch_gr_reg
= 15;
8477 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
8478 current_frame_info
.spill_cfa_off
= -16;
8479 current_frame_info
.n_input_regs
= 1;
8480 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
8482 if (!TARGET_REG_NAMES
)
8483 reg_names
[IN_REG (0)] = ia64_reg_numbers
[0];
8485 /* Mark the end of the (empty) prologue. */
8486 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
8488 this = gen_rtx_REG (Pmode
, IN_REG (0));
8490 /* Apply the constant offset, if required. */
8493 rtx delta_rtx
= GEN_INT (delta
);
8495 if (!CONST_OK_FOR_I (delta
))
8497 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8498 emit_move_insn (tmp
, delta_rtx
);
8501 emit_insn (gen_adddi3 (this, this, delta_rtx
));
8504 /* Apply the offset from the vtable, if required. */
8507 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8508 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8510 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8512 if (!CONST_OK_FOR_J (vcall_offset
))
8514 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
8515 emit_move_insn (tmp2
, vcall_offset_rtx
);
8516 vcall_offset_rtx
= tmp2
;
8518 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
8520 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
8522 emit_insn (gen_adddi3 (this, this, tmp
));
8525 /* Generate a tail call to the target function. */
8526 if (! TREE_USED (function
))
8528 assemble_external (function
);
8529 TREE_USED (function
) = 1;
8531 funexp
= XEXP (DECL_RTL (function
), 0);
8532 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8533 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
8534 insn
= get_last_insn ();
8535 SIBLING_CALL_P (insn
) = 1;
8537 /* Code generation for calls relies on splitting. */
8538 reload_completed
= 1;
8539 try_split (PATTERN (insn
), insn
, 0);
8543 /* Run just enough of rest_of_compilation to get the insns emitted.
8544 There's not really enough bulk here to make other passes such as
8545 instruction scheduling worth while. Note that use_thunk calls
8546 assemble_start_function and assemble_end_function. */
8548 emit_all_insn_group_barriers (NULL
);
8549 insn
= get_insns ();
8550 shorten_branches (insn
);
8551 final_start_function (insn
, file
, 1);
8552 final (insn
, file
, 1, 0);
8553 final_end_function ();
8555 reload_completed
= 0;
8559 #include "gt-ia64.h"