1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 typedef struct reg_stat_struct
{
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 DEF_VEC_O(reg_stat_type
);
256 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
258 static VEC(reg_stat_type
,heap
) *reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx
*uid_log_links
;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick
;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start
;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode
;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid
;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
351 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
352 union { rtx
*r
; int *i
; } where
;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf
;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences
;
375 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
377 unsigned HOST_WIDE_INT
,
378 unsigned HOST_WIDE_INT
*);
379 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx
*, rtx
);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx
);
386 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
387 static int cant_combine_insn_p (rtx
);
388 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
389 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
390 static int contains_muldiv (rtx
);
391 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx
*find_split_point (rtx
*, rtx
, bool);
395 static rtx
subst (rtx
, rtx
, rtx
, int, int);
396 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
397 static rtx
simplify_if_then_else (rtx
);
398 static rtx
simplify_set (rtx
);
399 static rtx
simplify_logical (rtx
);
400 static rtx
expand_compound_operation (rtx
);
401 static const_rtx
expand_field_assignment (const_rtx
);
402 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
403 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
404 static rtx
extract_left_shift (rtx
, int);
405 static rtx
make_compound_operation (rtx
, enum rtx_code
);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
407 unsigned HOST_WIDE_INT
*);
408 static rtx
canon_reg_for_combine (rtx
, rtx
);
409 static rtx
force_to_mode (rtx
, enum machine_mode
,
410 unsigned HOST_WIDE_INT
, int);
411 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
412 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
413 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
414 static rtx
make_field_assignment (rtx
);
415 static rtx
apply_distributive_law (rtx
);
416 static rtx
distribute_and_simplify_rtx (rtx
, int);
417 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
418 unsigned HOST_WIDE_INT
);
419 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
420 unsigned HOST_WIDE_INT
);
421 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
422 HOST_WIDE_INT
, enum machine_mode
, int *);
423 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
424 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
426 static int recog_for_combine (rtx
*, rtx
, rtx
*);
427 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
428 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
429 static void update_table_tick (rtx
);
430 static void record_value_for_reg (rtx
, rtx
, rtx
);
431 static void check_promoted_subreg (rtx
, rtx
);
432 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
433 static void record_dead_and_set_regs (rtx
);
434 static int get_last_value_validate (rtx
*, rtx
, int, int);
435 static rtx
get_last_value (const_rtx
);
436 static int use_crosses_set_p (const_rtx
, int);
437 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
438 static int reg_dead_at_p (rtx
, rtx
);
439 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
440 static int reg_bitfield_target_p (rtx
, rtx
);
441 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
442 static void distribute_links (rtx
);
443 static void mark_used_regs_combine (rtx
);
444 static void record_promoted_value (rtx
, rtx
);
445 static int unmentioned_reg_p_1 (rtx
*, void *);
446 static bool unmentioned_reg_p (rtx
, rtx
);
447 static int record_truncated_value (rtx
*, void *);
448 static void record_truncated_values (rtx
*, void *);
449 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
450 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern
, rtx insn
)
486 ret
= split_insns (pattern
, insn
);
487 nregs
= max_reg_num ();
488 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
489 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest
, rtx
*loc
)
503 enum rtx_code code
= GET_CODE (x
);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x
)) != CC0
526 && GET_CODE (SET_DEST (x
)) != PC
527 && !REG_P (SET_DEST (x
))
528 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x
)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
531 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
533 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
536 return find_single_use_1 (dest
, &SET_SRC (x
));
540 return find_single_use_1 (dest
, &XEXP (x
, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt
= GET_RTX_FORMAT (code
);
550 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
554 if (dest
== XEXP (x
, i
)
555 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
556 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
559 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
562 result
= this_result
;
563 else if (this_result
)
564 /* Duplicate usage. */
567 else if (fmt
[i
] == 'E')
571 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
573 if (XVECEXP (x
, i
, j
) == dest
575 && REG_P (XVECEXP (x
, i
, j
))
576 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
579 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
582 result
= this_result
;
583 else if (this_result
)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
618 next
= NEXT_INSN (insn
);
620 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
623 result
= find_single_use_1 (dest
, &PATTERN (next
));
633 bb
= BLOCK_FOR_INSN (insn
);
634 for (next
= NEXT_INSN (insn
);
635 next
&& BLOCK_FOR_INSN (next
) == bb
;
636 next
= NEXT_INSN (next
))
637 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
639 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
640 if (XEXP (link
, 0) == insn
)
645 result
= find_single_use_1 (dest
, &PATTERN (next
));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx
*into
, rtx newval
)
667 if (oldval
== newval
)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
676 && CONST_INT_P (newval
))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval
)
681 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval
) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval
))));
691 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval
, 0))));
696 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
698 buf
= XNEW (struct undo
);
700 buf
->kind
= UNDO_RTX
;
702 buf
->old_contents
.r
= oldval
;
705 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into
, int newval
)
720 if (oldval
== newval
)
724 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
726 buf
= XNEW (struct undo
);
728 buf
->kind
= UNDO_INT
;
730 buf
->old_contents
.i
= oldval
;
733 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
747 enum machine_mode oldval
= GET_MODE (*into
);
749 if (oldval
== newval
)
753 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
755 buf
= XNEW (struct undo
);
757 buf
->kind
= UNDO_MODE
;
759 buf
->old_contents
.m
= oldval
;
760 adjust_reg_mode (*into
, newval
);
762 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
778 rtx newi2pat
, rtx newotherpat
)
780 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
781 int new_i2_cost
, new_i3_cost
;
782 int old_cost
, new_cost
;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost
= INSN_COST (i2
);
786 i3_cost
= INSN_COST (i3
);
790 i1_cost
= INSN_COST (i1
);
793 i0_cost
= INSN_COST (i0
);
794 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
795 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
799 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
800 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
806 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
807 i1_cost
= i0_cost
= 0;
810 /* Calculate the replacement insn_rtx_costs. */
811 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
814 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
815 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
816 ? new_i2_cost
+ new_i3_cost
: 0;
820 new_cost
= new_i3_cost
;
824 if (undobuf
.other_insn
)
826 int old_other_cost
, new_other_cost
;
828 old_other_cost
= INSN_COST (undobuf
.other_insn
);
829 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
830 if (old_other_cost
> 0 && new_other_cost
> 0)
832 old_cost
+= old_other_cost
;
833 new_cost
+= new_other_cost
;
839 /* Disallow this recombination if both new_cost and old_cost are
840 greater than zero, and new_cost is greater than old cost. */
842 && new_cost
> old_cost
)
849 "rejecting combination of insns %d, %d, %d and %d\n",
850 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
852 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
853 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
858 "rejecting combination of insns %d, %d and %d\n",
859 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
860 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
861 i1_cost
, i2_cost
, i3_cost
, old_cost
);
866 "rejecting combination of insns %d and %d\n",
867 INSN_UID (i2
), INSN_UID (i3
));
868 fprintf (dump_file
, "original costs %d + %d = %d\n",
869 i2_cost
, i3_cost
, old_cost
);
874 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
875 new_i2_cost
, new_i3_cost
, new_cost
);
878 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
884 /* Update the uid_insn_cost array with the replacement costs. */
885 INSN_COST (i2
) = new_i2_cost
;
886 INSN_COST (i3
) = new_i3_cost
;
894 /* Delete any insns that copy a register to itself. */
897 delete_noop_moves (void)
904 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
906 next
= NEXT_INSN (insn
);
907 if (INSN_P (insn
) && noop_move_p (insn
))
910 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
912 delete_insn_and_edges (insn
);
919 /* Fill in log links field for all insns. */
922 create_log_links (void)
926 df_ref
*def_vec
, *use_vec
;
928 next_use
= XCNEWVEC (rtx
, max_reg_num ());
930 /* Pass through each block from the end, recording the uses of each
931 register and establishing log links when def is encountered.
932 Note that we do not clear next_use array in order to save time,
933 so we have to test whether the use is in the same basic block as def.
935 There are a few cases below when we do not consider the definition or
936 usage -- these are taken from original flow.c did. Don't ask me why it is
937 done this way; I don't know and if it works, I don't want to know. */
941 FOR_BB_INSNS_REVERSE (bb
, insn
)
943 if (!NONDEBUG_INSN_P (insn
))
946 /* Log links are created only once. */
947 gcc_assert (!LOG_LINKS (insn
));
949 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
951 df_ref def
= *def_vec
;
952 int regno
= DF_REF_REGNO (def
);
955 if (!next_use
[regno
])
958 /* Do not consider if it is pre/post modification in MEM. */
959 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
962 /* Do not make the log link for frame pointer. */
963 if ((regno
== FRAME_POINTER_REGNUM
964 && (! reload_completed
|| frame_pointer_needed
))
965 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
966 || (regno
== HARD_FRAME_POINTER_REGNUM
967 && (! reload_completed
|| frame_pointer_needed
))
969 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
970 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
975 use_insn
= next_use
[regno
];
976 if (BLOCK_FOR_INSN (use_insn
) == bb
)
980 We don't build a LOG_LINK for hard registers contained
981 in ASM_OPERANDs. If these registers get replaced,
982 we might wind up changing the semantics of the insn,
983 even if reload can make what appear to be valid
984 assignments later. */
985 if (regno
>= FIRST_PSEUDO_REGISTER
986 || asm_noperands (PATTERN (use_insn
)) < 0)
988 /* Don't add duplicate links between instructions. */
990 for (links
= LOG_LINKS (use_insn
); links
;
991 links
= XEXP (links
, 1))
992 if (insn
== XEXP (links
, 0))
996 LOG_LINKS (use_insn
) =
997 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
1000 next_use
[regno
] = NULL_RTX
;
1003 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1005 df_ref use
= *use_vec
;
1006 int regno
= DF_REF_REGNO (use
);
1008 /* Do not consider the usage of the stack pointer
1009 by function call. */
1010 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1013 next_use
[regno
] = insn
;
1021 /* Clear LOG_LINKS fields of insns. */
1024 clear_log_links (void)
1028 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1030 free_INSN_LIST_list (&LOG_LINKS (insn
));
1033 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1034 true if we found a LOG_LINK that proves that A feeds B. This only works
1035 if there are no instructions between A and B which could have a link
1036 depending on A, since in that case we would not record a link for B. */
1039 insn_a_feeds_b (rtx a
, rtx b
)
1042 for (links
= LOG_LINKS (b
); links
; links
= XEXP (links
, 1))
1043 if (XEXP (links
, 0) == a
)
1048 /* Main entry point for combiner. F is the first insn of the function.
1049 NREGS is the first unused pseudo-reg number.
1051 Return nonzero if the combiner has turned an indirect jump
1052 instruction into a direct jump. */
1054 combine_instructions (rtx f
, unsigned int nregs
)
1060 rtx links
, nextlinks
;
1062 basic_block last_bb
;
1064 int new_direct_jump_p
= 0;
1066 for (first
= f
; first
&& !INSN_P (first
); )
1067 first
= NEXT_INSN (first
);
1071 combine_attempts
= 0;
1074 combine_successes
= 0;
1076 rtl_hooks
= combine_rtl_hooks
;
1078 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1080 init_recog_no_volatile ();
1082 /* Allocate array for insn info. */
1083 max_uid_known
= get_max_uid ();
1084 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1085 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1087 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1089 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1090 problems when, for example, we have j <<= 1 in a loop. */
1092 nonzero_sign_valid
= 0;
1093 label_tick
= label_tick_ebb_start
= 1;
1095 /* Scan all SETs and see if we can deduce anything about what
1096 bits are known to be zero for some registers and how many copies
1097 of the sign bit are known to exist for those registers.
1099 Also set any known values so that we can use it while searching
1100 for what bits are known to be set. */
1102 setup_incoming_promotions (first
);
1103 /* Allow the entry block and the first block to fall into the same EBB.
1104 Conceptually the incoming promotions are assigned to the entry block. */
1105 last_bb
= ENTRY_BLOCK_PTR
;
1107 create_log_links ();
1108 FOR_EACH_BB (this_basic_block
)
1110 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1115 if (!single_pred_p (this_basic_block
)
1116 || single_pred (this_basic_block
) != last_bb
)
1117 label_tick_ebb_start
= label_tick
;
1118 last_bb
= this_basic_block
;
1120 FOR_BB_INSNS (this_basic_block
, insn
)
1121 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1123 subst_low_luid
= DF_INSN_LUID (insn
);
1126 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1128 record_dead_and_set_regs (insn
);
1131 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1132 if (REG_NOTE_KIND (links
) == REG_INC
)
1133 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1137 /* Record the current insn_rtx_cost of this instruction. */
1138 if (NONJUMP_INSN_P (insn
))
1139 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1140 optimize_this_for_speed_p
);
1142 fprintf(dump_file
, "insn_cost %d: %d\n",
1143 INSN_UID (insn
), INSN_COST (insn
));
1147 nonzero_sign_valid
= 1;
1149 /* Now scan all the insns in forward order. */
1150 label_tick
= label_tick_ebb_start
= 1;
1152 setup_incoming_promotions (first
);
1153 last_bb
= ENTRY_BLOCK_PTR
;
1155 FOR_EACH_BB (this_basic_block
)
1157 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1162 if (!single_pred_p (this_basic_block
)
1163 || single_pred (this_basic_block
) != last_bb
)
1164 label_tick_ebb_start
= label_tick
;
1165 last_bb
= this_basic_block
;
1167 rtl_profile_for_bb (this_basic_block
);
1168 for (insn
= BB_HEAD (this_basic_block
);
1169 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1170 insn
= next
? next
: NEXT_INSN (insn
))
1173 if (NONDEBUG_INSN_P (insn
))
1175 /* See if we know about function return values before this
1176 insn based upon SUBREG flags. */
1177 check_promoted_subreg (insn
, PATTERN (insn
));
1179 /* See if we can find hardregs and subreg of pseudos in
1180 narrower modes. This could help turning TRUNCATEs
1182 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1184 /* Try this insn with each insn it links back to. */
1186 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1187 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
,
1188 NULL_RTX
, &new_direct_jump_p
)) != 0)
1191 /* Try each sequence of three linked insns ending with this one. */
1193 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1195 rtx link
= XEXP (links
, 0);
1197 /* If the linked insn has been replaced by a note, then there
1198 is no point in pursuing this chain any further. */
1202 for (nextlinks
= LOG_LINKS (link
);
1204 nextlinks
= XEXP (nextlinks
, 1))
1205 if ((next
= try_combine (insn
, link
, XEXP (nextlinks
, 0),
1207 &new_direct_jump_p
)) != 0)
1212 /* Try to combine a jump insn that uses CC0
1213 with a preceding insn that sets CC0, and maybe with its
1214 logical predecessor as well.
1215 This is how we make decrement-and-branch insns.
1216 We need this special code because data flow connections
1217 via CC0 do not get entered in LOG_LINKS. */
1220 && (prev
= prev_nonnote_insn (insn
)) != 0
1221 && NONJUMP_INSN_P (prev
)
1222 && sets_cc0_p (PATTERN (prev
)))
1224 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1225 &new_direct_jump_p
)) != 0)
1228 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1229 nextlinks
= XEXP (nextlinks
, 1))
1230 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1232 &new_direct_jump_p
)) != 0)
1236 /* Do the same for an insn that explicitly references CC0. */
1237 if (NONJUMP_INSN_P (insn
)
1238 && (prev
= prev_nonnote_insn (insn
)) != 0
1239 && NONJUMP_INSN_P (prev
)
1240 && sets_cc0_p (PATTERN (prev
))
1241 && GET_CODE (PATTERN (insn
)) == SET
1242 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1244 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1245 &new_direct_jump_p
)) != 0)
1248 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1249 nextlinks
= XEXP (nextlinks
, 1))
1250 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1252 &new_direct_jump_p
)) != 0)
1256 /* Finally, see if any of the insns that this insn links to
1257 explicitly references CC0. If so, try this insn, that insn,
1258 and its predecessor if it sets CC0. */
1259 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1260 if (NONJUMP_INSN_P (XEXP (links
, 0))
1261 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1262 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1263 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1264 && NONJUMP_INSN_P (prev
)
1265 && sets_cc0_p (PATTERN (prev
))
1266 && (next
= try_combine (insn
, XEXP (links
, 0),
1268 &new_direct_jump_p
)) != 0)
1272 /* Try combining an insn with two different insns whose results it
1274 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1275 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1276 nextlinks
= XEXP (nextlinks
, 1))
1277 if ((next
= try_combine (insn
, XEXP (links
, 0),
1278 XEXP (nextlinks
, 0), NULL_RTX
,
1279 &new_direct_jump_p
)) != 0)
1282 /* Try four-instruction combinations. */
1283 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1286 rtx link
= XEXP (links
, 0);
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 for (next1
= LOG_LINKS (link
); next1
; next1
= XEXP (next1
, 1))
1295 rtx link1
= XEXP (next1
, 0);
1298 /* I0 -> I1 -> I2 -> I3. */
1299 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1300 nextlinks
= XEXP (nextlinks
, 1))
1301 if ((next
= try_combine (insn
, link
, link1
,
1302 XEXP (nextlinks
, 0),
1303 &new_direct_jump_p
)) != 0)
1305 /* I0, I1 -> I2, I2 -> I3. */
1306 for (nextlinks
= XEXP (next1
, 1); nextlinks
;
1307 nextlinks
= XEXP (nextlinks
, 1))
1308 if ((next
= try_combine (insn
, link
, link1
,
1309 XEXP (nextlinks
, 0),
1310 &new_direct_jump_p
)) != 0)
1314 for (next1
= XEXP (links
, 1); next1
; next1
= XEXP (next1
, 1))
1316 rtx link1
= XEXP (next1
, 0);
1319 /* I0 -> I2; I1, I2 -> I3. */
1320 for (nextlinks
= LOG_LINKS (link
); nextlinks
;
1321 nextlinks
= XEXP (nextlinks
, 1))
1322 if ((next
= try_combine (insn
, link
, link1
,
1323 XEXP (nextlinks
, 0),
1324 &new_direct_jump_p
)) != 0)
1326 /* I0 -> I1; I1, I2 -> I3. */
1327 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1328 nextlinks
= XEXP (nextlinks
, 1))
1329 if ((next
= try_combine (insn
, link
, link1
,
1330 XEXP (nextlinks
, 0),
1331 &new_direct_jump_p
)) != 0)
1336 /* Try this insn with each REG_EQUAL note it links back to. */
1337 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1340 rtx temp
= XEXP (links
, 0);
1341 if ((set
= single_set (temp
)) != 0
1342 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1343 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1344 /* Avoid using a register that may already been marked
1345 dead by an earlier instruction. */
1346 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1347 && (GET_MODE (note
) == VOIDmode
1348 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1349 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1351 /* Temporarily replace the set's source with the
1352 contents of the REG_EQUAL note. The insn will
1353 be deleted or recognized by try_combine. */
1354 rtx orig
= SET_SRC (set
);
1355 SET_SRC (set
) = note
;
1357 i2mod_old_rhs
= copy_rtx (orig
);
1358 i2mod_new_rhs
= copy_rtx (note
);
1359 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1360 &new_direct_jump_p
);
1364 SET_SRC (set
) = orig
;
1369 record_dead_and_set_regs (insn
);
1377 default_rtl_profile ();
1380 new_direct_jump_p
|= purge_all_dead_edges ();
1381 delete_noop_moves ();
1384 free (uid_log_links
);
1385 free (uid_insn_cost
);
1386 VEC_free (reg_stat_type
, heap
, reg_stat
);
1389 struct undo
*undo
, *next
;
1390 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1398 total_attempts
+= combine_attempts
;
1399 total_merges
+= combine_merges
;
1400 total_extras
+= combine_extras
;
1401 total_successes
+= combine_successes
;
1403 nonzero_sign_valid
= 0;
1404 rtl_hooks
= general_rtl_hooks
;
1406 /* Make recognizer allow volatile MEMs again. */
1409 return new_direct_jump_p
;
1412 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1415 init_reg_last (void)
1420 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1421 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1424 /* Set up any promoted values for incoming argument registers. */
1427 setup_incoming_promotions (rtx first
)
1430 bool strictly_local
= false;
1432 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1433 arg
= DECL_CHAIN (arg
))
1435 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1437 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1439 /* Only continue if the incoming argument is in a register. */
1443 /* Determine, if possible, whether all call sites of the current
1444 function lie within the current compilation unit. (This does
1445 take into account the exporting of a function via taking its
1446 address, and so forth.) */
1447 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1449 /* The mode and signedness of the argument before any promotions happen
1450 (equal to the mode of the pseudo holding it at that stage). */
1451 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1452 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1454 /* The mode and signedness of the argument after any source language and
1455 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1456 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1457 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1459 /* The mode and signedness of the argument as it is actually passed,
1460 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1461 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1462 TREE_TYPE (cfun
->decl
), 0);
1464 /* The mode of the register in which the argument is being passed. */
1465 mode4
= GET_MODE (reg
);
1467 /* Eliminate sign extensions in the callee when:
1468 (a) A mode promotion has occurred; */
1471 /* (b) The mode of the register is the same as the mode of
1472 the argument as it is passed; */
1475 /* (c) There's no language level extension; */
1478 /* (c.1) All callers are from the current compilation unit. If that's
1479 the case we don't have to rely on an ABI, we only have to know
1480 what we're generating right now, and we know that we will do the
1481 mode1 to mode2 promotion with the given sign. */
1482 else if (!strictly_local
)
1484 /* (c.2) The combination of the two promotions is useful. This is
1485 true when the signs match, or if the first promotion is unsigned.
1486 In the later case, (sign_extend (zero_extend x)) is the same as
1487 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1493 /* Record that the value was promoted from mode1 to mode3,
1494 so that any sign extension at the head of the current
1495 function may be eliminated. */
1496 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1497 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1498 record_value_for_reg (reg
, first
, x
);
1502 /* Called via note_stores. If X is a pseudo that is narrower than
1503 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1505 If we are setting only a portion of X and we can't figure out what
1506 portion, assume all bits will be used since we don't know what will
1509 Similarly, set how many bits of X are known to be copies of the sign bit
1510 at all locations in the function. This is the smallest number implied
1514 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1516 rtx insn
= (rtx
) data
;
1520 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1521 /* If this register is undefined at the start of the file, we can't
1522 say what its contents were. */
1523 && ! REGNO_REG_SET_P
1524 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1525 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1527 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1529 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1531 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1532 rsp
->sign_bit_copies
= 1;
1536 /* If this register is being initialized using itself, and the
1537 register is uninitialized in this basic block, and there are
1538 no LOG_LINKS which set the register, then part of the
1539 register is uninitialized. In that case we can't assume
1540 anything about the number of nonzero bits.
1542 ??? We could do better if we checked this in
1543 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1544 could avoid making assumptions about the insn which initially
1545 sets the register, while still using the information in other
1546 insns. We would have to be careful to check every insn
1547 involved in the combination. */
1550 && reg_referenced_p (x
, PATTERN (insn
))
1551 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1556 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1558 if (dead_or_set_p (XEXP (link
, 0), x
))
1563 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1564 rsp
->sign_bit_copies
= 1;
1569 /* If this is a complex assignment, see if we can convert it into a
1570 simple assignment. */
1571 set
= expand_field_assignment (set
);
1573 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1574 set what we know about X. */
1576 if (SET_DEST (set
) == x
1577 || (GET_CODE (SET_DEST (set
)) == SUBREG
1578 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1579 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1580 && SUBREG_REG (SET_DEST (set
)) == x
))
1582 rtx src
= SET_SRC (set
);
1584 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1585 /* If X is narrower than a word and SRC is a non-negative
1586 constant that would appear negative in the mode of X,
1587 sign-extend it for use in reg_stat[].nonzero_bits because some
1588 machines (maybe most) will actually do the sign-extension
1589 and this is the conservative approach.
1591 ??? For 2.5, try to tighten up the MD files in this regard
1592 instead of this kludge. */
1594 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1595 && CONST_INT_P (src
)
1597 && 0 != (UINTVAL (src
)
1598 & ((unsigned HOST_WIDE_INT
) 1
1599 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1600 src
= GEN_INT (UINTVAL (src
)
1601 | ((unsigned HOST_WIDE_INT
) (-1)
1602 << GET_MODE_BITSIZE (GET_MODE (x
))));
1605 /* Don't call nonzero_bits if it cannot change anything. */
1606 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1607 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1608 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1609 if (rsp
->sign_bit_copies
== 0
1610 || rsp
->sign_bit_copies
> num
)
1611 rsp
->sign_bit_copies
= num
;
1615 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1616 rsp
->sign_bit_copies
= 1;
1621 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1622 optionally insns that were previously combined into I3 or that will be
1623 combined into the merger of INSN and I3. The order is PRED, PRED2,
1624 INSN, SUCC, SUCC2, I3.
1626 Return 0 if the combination is not allowed for any reason.
1628 If the combination is allowed, *PDEST will be set to the single
1629 destination of INSN and *PSRC to the single source, and this function
1633 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1634 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1635 rtx
*pdest
, rtx
*psrc
)
1644 bool all_adjacent
= true;
1650 if (next_active_insn (succ2
) != i3
)
1651 all_adjacent
= false;
1652 if (next_active_insn (succ
) != succ2
)
1653 all_adjacent
= false;
1655 else if (next_active_insn (succ
) != i3
)
1656 all_adjacent
= false;
1657 if (next_active_insn (insn
) != succ
)
1658 all_adjacent
= false;
1660 else if (next_active_insn (insn
) != i3
)
1661 all_adjacent
= false;
1663 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1664 or a PARALLEL consisting of such a SET and CLOBBERs.
1666 If INSN has CLOBBER parallel parts, ignore them for our processing.
1667 By definition, these happen during the execution of the insn. When it
1668 is merged with another insn, all bets are off. If they are, in fact,
1669 needed and aren't also supplied in I3, they may be added by
1670 recog_for_combine. Otherwise, it won't match.
1672 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1675 Get the source and destination of INSN. If more than one, can't
1678 if (GET_CODE (PATTERN (insn
)) == SET
)
1679 set
= PATTERN (insn
);
1680 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1681 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1683 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1685 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1687 switch (GET_CODE (elt
))
1689 /* This is important to combine floating point insns
1690 for the SH4 port. */
1692 /* Combining an isolated USE doesn't make sense.
1693 We depend here on combinable_i3pat to reject them. */
1694 /* The code below this loop only verifies that the inputs of
1695 the SET in INSN do not change. We call reg_set_between_p
1696 to verify that the REG in the USE does not change between
1698 If the USE in INSN was for a pseudo register, the matching
1699 insn pattern will likely match any register; combining this
1700 with any other USE would only be safe if we knew that the
1701 used registers have identical values, or if there was
1702 something to tell them apart, e.g. different modes. For
1703 now, we forgo such complicated tests and simply disallow
1704 combining of USES of pseudo registers with any other USE. */
1705 if (REG_P (XEXP (elt
, 0))
1706 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1708 rtx i3pat
= PATTERN (i3
);
1709 int i
= XVECLEN (i3pat
, 0) - 1;
1710 unsigned int regno
= REGNO (XEXP (elt
, 0));
1714 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1716 if (GET_CODE (i3elt
) == USE
1717 && REG_P (XEXP (i3elt
, 0))
1718 && (REGNO (XEXP (i3elt
, 0)) == regno
1719 ? reg_set_between_p (XEXP (elt
, 0),
1720 PREV_INSN (insn
), i3
)
1721 : regno
>= FIRST_PSEUDO_REGISTER
))
1728 /* We can ignore CLOBBERs. */
1733 /* Ignore SETs whose result isn't used but not those that
1734 have side-effects. */
1735 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1736 && insn_nothrow_p (insn
)
1737 && !side_effects_p (elt
))
1740 /* If we have already found a SET, this is a second one and
1741 so we cannot combine with this insn. */
1749 /* Anything else means we can't combine. */
1755 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1756 so don't do anything with it. */
1757 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1766 set
= expand_field_assignment (set
);
1767 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1769 /* Don't eliminate a store in the stack pointer. */
1770 if (dest
== stack_pointer_rtx
1771 /* Don't combine with an insn that sets a register to itself if it has
1772 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1773 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1774 /* Can't merge an ASM_OPERANDS. */
1775 || GET_CODE (src
) == ASM_OPERANDS
1776 /* Can't merge a function call. */
1777 || GET_CODE (src
) == CALL
1778 /* Don't eliminate a function call argument. */
1780 && (find_reg_fusage (i3
, USE
, dest
)
1782 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1783 && global_regs
[REGNO (dest
)])))
1784 /* Don't substitute into an incremented register. */
1785 || FIND_REG_INC_NOTE (i3
, dest
)
1786 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1787 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1788 /* Don't substitute into a non-local goto, this confuses CFG. */
1789 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1790 /* Make sure that DEST is not used after SUCC but before I3. */
1793 && (reg_used_between_p (dest
, succ2
, i3
)
1794 || reg_used_between_p (dest
, succ
, succ2
)))
1795 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1796 /* Make sure that the value that is to be substituted for the register
1797 does not use any registers whose values alter in between. However,
1798 If the insns are adjacent, a use can't cross a set even though we
1799 think it might (this can happen for a sequence of insns each setting
1800 the same destination; last_set of that register might point to
1801 a NOTE). If INSN has a REG_EQUIV note, the register is always
1802 equivalent to the memory so the substitution is valid even if there
1803 are intervening stores. Also, don't move a volatile asm or
1804 UNSPEC_VOLATILE across any other insns. */
1807 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1808 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1809 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1810 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1811 /* Don't combine across a CALL_INSN, because that would possibly
1812 change whether the life span of some REGs crosses calls or not,
1813 and it is a pain to update that information.
1814 Exception: if source is a constant, moving it later can't hurt.
1815 Accept that as a special case. */
1816 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1819 /* DEST must either be a REG or CC0. */
1822 /* If register alignment is being enforced for multi-word items in all
1823 cases except for parameters, it is possible to have a register copy
1824 insn referencing a hard register that is not allowed to contain the
1825 mode being copied and which would not be valid as an operand of most
1826 insns. Eliminate this problem by not combining with such an insn.
1828 Also, on some machines we don't want to extend the life of a hard
1832 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1833 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1834 /* Don't extend the life of a hard register unless it is
1835 user variable (if we have few registers) or it can't
1836 fit into the desired register (meaning something special
1838 Also avoid substituting a return register into I3, because
1839 reload can't handle a conflict with constraints of other
1841 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1842 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1845 else if (GET_CODE (dest
) != CC0
)
1849 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1850 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1851 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1853 /* Don't substitute for a register intended as a clobberable
1855 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1856 if (rtx_equal_p (reg
, dest
))
1859 /* If the clobber represents an earlyclobber operand, we must not
1860 substitute an expression containing the clobbered register.
1861 As we do not analyze the constraint strings here, we have to
1862 make the conservative assumption. However, if the register is
1863 a fixed hard reg, the clobber cannot represent any operand;
1864 we leave it up to the machine description to either accept or
1865 reject use-and-clobber patterns. */
1867 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1868 || !fixed_regs
[REGNO (reg
)])
1869 if (reg_overlap_mentioned_p (reg
, src
))
1873 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1874 or not), reject, unless nothing volatile comes between it and I3 */
1876 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1878 /* Make sure neither succ nor succ2 contains a volatile reference. */
1879 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1881 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1883 /* We'll check insns between INSN and I3 below. */
1886 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1887 to be an explicit register variable, and was chosen for a reason. */
1889 if (GET_CODE (src
) == ASM_OPERANDS
1890 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1893 /* If there are any volatile insns between INSN and I3, reject, because
1894 they might affect machine state. */
1896 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1897 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& volatile_insn_p (PATTERN (p
)))
1900 /* If INSN contains an autoincrement or autodecrement, make sure that
1901 register is not used between there and I3, and not already used in
1902 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1903 Also insist that I3 not be a jump; if it were one
1904 and the incremented register were spilled, we would lose. */
1907 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1908 if (REG_NOTE_KIND (link
) == REG_INC
1910 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1911 || (pred
!= NULL_RTX
1912 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1913 || (pred2
!= NULL_RTX
1914 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1915 || (succ
!= NULL_RTX
1916 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1917 || (succ2
!= NULL_RTX
1918 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1919 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1924 /* Don't combine an insn that follows a CC0-setting insn.
1925 An insn that uses CC0 must not be separated from the one that sets it.
1926 We do, however, allow I2 to follow a CC0-setting insn if that insn
1927 is passed as I1; in that case it will be deleted also.
1928 We also allow combining in this case if all the insns are adjacent
1929 because that would leave the two CC0 insns adjacent as well.
1930 It would be more logical to test whether CC0 occurs inside I1 or I2,
1931 but that would be much slower, and this ought to be equivalent. */
1933 p
= prev_nonnote_insn (insn
);
1934 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1939 /* If we get here, we have passed all the tests and the combination is
1948 /* LOC is the location within I3 that contains its pattern or the component
1949 of a PARALLEL of the pattern. We validate that it is valid for combining.
1951 One problem is if I3 modifies its output, as opposed to replacing it
1952 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1953 doing so would produce an insn that is not equivalent to the original insns.
1957 (set (reg:DI 101) (reg:DI 100))
1958 (set (subreg:SI (reg:DI 101) 0) <foo>)
1960 This is NOT equivalent to:
1962 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1963 (set (reg:DI 101) (reg:DI 100))])
1965 Not only does this modify 100 (in which case it might still be valid
1966 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1968 We can also run into a problem if I2 sets a register that I1
1969 uses and I1 gets directly substituted into I3 (not via I2). In that
1970 case, we would be getting the wrong value of I2DEST into I3, so we
1971 must reject the combination. This case occurs when I2 and I1 both
1972 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1973 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1974 of a SET must prevent combination from occurring. The same situation
1975 can occur for I0, in which case I0_NOT_IN_SRC is set.
1977 Before doing the above check, we first try to expand a field assignment
1978 into a set of logical operations.
1980 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1981 we place a register that is both set and used within I3. If more than one
1982 such register is detected, we fail.
1984 Return 1 if the combination is valid, zero otherwise. */
1987 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
1988 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
1992 if (GET_CODE (x
) == SET
)
1995 rtx dest
= SET_DEST (set
);
1996 rtx src
= SET_SRC (set
);
1997 rtx inner_dest
= dest
;
2000 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2001 || GET_CODE (inner_dest
) == SUBREG
2002 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2003 inner_dest
= XEXP (inner_dest
, 0);
2005 /* Check for the case where I3 modifies its output, as discussed
2006 above. We don't want to prevent pseudos from being combined
2007 into the address of a MEM, so only prevent the combination if
2008 i1 or i2 set the same MEM. */
2009 if ((inner_dest
!= dest
&&
2010 (!MEM_P (inner_dest
)
2011 || rtx_equal_p (i2dest
, inner_dest
)
2012 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2013 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2014 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2015 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2016 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2018 /* This is the same test done in can_combine_p except we can't test
2019 all_adjacent; we don't have to, since this instruction will stay
2020 in place, thus we are not considering increasing the lifetime of
2023 Also, if this insn sets a function argument, combining it with
2024 something that might need a spill could clobber a previous
2025 function argument; the all_adjacent test in can_combine_p also
2026 checks this; here, we do a more specific test for this case. */
2028 || (REG_P (inner_dest
)
2029 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2030 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2031 GET_MODE (inner_dest
))))
2032 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2033 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2036 /* If DEST is used in I3, it is being killed in this insn, so
2037 record that for later. We have to consider paradoxical
2038 subregs here, since they kill the whole register, but we
2039 ignore partial subregs, STRICT_LOW_PART, etc.
2040 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2041 STACK_POINTER_REGNUM, since these are always considered to be
2042 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2044 if (GET_CODE (subdest
) == SUBREG
2045 && (GET_MODE_SIZE (GET_MODE (subdest
))
2046 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2047 subdest
= SUBREG_REG (subdest
);
2050 && reg_referenced_p (subdest
, PATTERN (i3
))
2051 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2052 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2053 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2055 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2056 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2057 || ! fixed_regs
[REGNO (subdest
)])
2059 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2061 if (*pi3dest_killed
)
2064 *pi3dest_killed
= subdest
;
2068 else if (GET_CODE (x
) == PARALLEL
)
2072 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2073 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2074 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2081 /* Return 1 if X is an arithmetic expression that contains a multiplication
2082 and division. We don't count multiplications by powers of two here. */
2085 contains_muldiv (rtx x
)
2087 switch (GET_CODE (x
))
2089 case MOD
: case DIV
: case UMOD
: case UDIV
:
2093 return ! (CONST_INT_P (XEXP (x
, 1))
2094 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2097 return contains_muldiv (XEXP (x
, 0))
2098 || contains_muldiv (XEXP (x
, 1));
2101 return contains_muldiv (XEXP (x
, 0));
2107 /* Determine whether INSN can be used in a combination. Return nonzero if
2108 not. This is used in try_combine to detect early some cases where we
2109 can't perform combinations. */
2112 cant_combine_insn_p (rtx insn
)
2117 /* If this isn't really an insn, we can't do anything.
2118 This can occur when flow deletes an insn that it has merged into an
2119 auto-increment address. */
2120 if (! INSN_P (insn
))
2123 /* Never combine loads and stores involving hard regs that are likely
2124 to be spilled. The register allocator can usually handle such
2125 reg-reg moves by tying. If we allow the combiner to make
2126 substitutions of likely-spilled regs, reload might die.
2127 As an exception, we allow combinations involving fixed regs; these are
2128 not available to the register allocator so there's no risk involved. */
2130 set
= single_set (insn
);
2133 src
= SET_SRC (set
);
2134 dest
= SET_DEST (set
);
2135 if (GET_CODE (src
) == SUBREG
)
2136 src
= SUBREG_REG (src
);
2137 if (GET_CODE (dest
) == SUBREG
)
2138 dest
= SUBREG_REG (dest
);
2139 if (REG_P (src
) && REG_P (dest
)
2140 && ((HARD_REGISTER_P (src
)
2141 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2142 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2143 || (HARD_REGISTER_P (dest
)
2144 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2145 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2151 struct likely_spilled_retval_info
2153 unsigned regno
, nregs
;
2157 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2158 hard registers that are known to be written to / clobbered in full. */
2160 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2162 struct likely_spilled_retval_info
*const info
=
2163 (struct likely_spilled_retval_info
*) data
;
2164 unsigned regno
, nregs
;
2167 if (!REG_P (XEXP (set
, 0)))
2170 if (regno
>= info
->regno
+ info
->nregs
)
2172 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2173 if (regno
+ nregs
<= info
->regno
)
2175 new_mask
= (2U << (nregs
- 1)) - 1;
2176 if (regno
< info
->regno
)
2177 new_mask
>>= info
->regno
- regno
;
2179 new_mask
<<= regno
- info
->regno
;
2180 info
->mask
&= ~new_mask
;
2183 /* Return nonzero iff part of the return value is live during INSN, and
2184 it is likely spilled. This can happen when more than one insn is needed
2185 to copy the return value, e.g. when we consider to combine into the
2186 second copy insn for a complex value. */
2189 likely_spilled_retval_p (rtx insn
)
2191 rtx use
= BB_END (this_basic_block
);
2193 unsigned regno
, nregs
;
2194 /* We assume here that no machine mode needs more than
2195 32 hard registers when the value overlaps with a register
2196 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2198 struct likely_spilled_retval_info info
;
2200 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2202 reg
= XEXP (PATTERN (use
), 0);
2203 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2205 regno
= REGNO (reg
);
2206 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2209 mask
= (2U << (nregs
- 1)) - 1;
2211 /* Disregard parts of the return value that are set later. */
2215 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2217 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2220 /* Check if any of the (probably) live return value registers is
2225 if ((mask
& 1 << nregs
)
2226 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2232 /* Adjust INSN after we made a change to its destination.
2234 Changing the destination can invalidate notes that say something about
2235 the results of the insn and a LOG_LINK pointing to the insn. */
2238 adjust_for_new_dest (rtx insn
)
2240 /* For notes, be conservative and simply remove them. */
2241 remove_reg_equal_equiv_notes (insn
);
2243 /* The new insn will have a destination that was previously the destination
2244 of an insn just above it. Call distribute_links to make a LOG_LINK from
2245 the next use of that destination. */
2246 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2248 df_insn_rescan (insn
);
2251 /* Return TRUE if combine can reuse reg X in mode MODE.
2252 ADDED_SETS is nonzero if the original set is still required. */
2254 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2262 /* Allow hard registers if the new mode is legal, and occupies no more
2263 registers than the old mode. */
2264 if (regno
< FIRST_PSEUDO_REGISTER
)
2265 return (HARD_REGNO_MODE_OK (regno
, mode
)
2266 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2267 >= hard_regno_nregs
[regno
][mode
]));
2269 /* Or a pseudo that is only used once. */
2270 return (REG_N_SETS (regno
) == 1 && !added_sets
2271 && !REG_USERVAR_P (x
));
2275 /* Check whether X, the destination of a set, refers to part of
2276 the register specified by REG. */
2279 reg_subword_p (rtx x
, rtx reg
)
2281 /* Check that reg is an integer mode register. */
2282 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2285 if (GET_CODE (x
) == STRICT_LOW_PART
2286 || GET_CODE (x
) == ZERO_EXTRACT
)
2289 return GET_CODE (x
) == SUBREG
2290 && SUBREG_REG (x
) == reg
2291 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2295 /* Replace auto-increment addressing modes with explicit operations to access
2296 the same addresses without modifying the corresponding registers. */
2299 cleanup_auto_inc_dec (rtx src
, enum machine_mode mem_mode
)
2302 const RTX_CODE code
= GET_CODE (x
);
2318 /* SCRATCH must be shared because they represent distinct values. */
2321 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2326 if (shared_const_p (x
))
2331 mem_mode
= GET_MODE (x
);
2336 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2337 return gen_rtx_PLUS (GET_MODE (x
),
2338 cleanup_auto_inc_dec (XEXP (x
, 0), mem_mode
),
2339 GEN_INT (code
== PRE_INC
2340 ? GET_MODE_SIZE (mem_mode
)
2341 : -GET_MODE_SIZE (mem_mode
)));
2347 return cleanup_auto_inc_dec (code
== PRE_MODIFY
2348 ? XEXP (x
, 1) : XEXP (x
, 0),
2355 /* Copy the various flags, fields, and other information. We assume
2356 that all fields need copying, and then clear the fields that should
2357 not be copied. That is the sensible default behavior, and forces
2358 us to explicitly document why we are *not* copying a flag. */
2359 x
= shallow_copy_rtx (x
);
2361 /* We do not copy the USED flag, which is used as a mark bit during
2362 walks over the RTL. */
2363 RTX_FLAG (x
, used
) = 0;
2365 /* We do not copy FRAME_RELATED for INSNs. */
2367 RTX_FLAG (x
, frame_related
) = 0;
2369 fmt
= GET_RTX_FORMAT (code
);
2370 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2372 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), mem_mode
);
2373 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2376 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2377 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2379 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), mem_mode
);
2386 /* Auxiliary data structure for propagate_for_debug_stmt. */
2388 struct rtx_subst_pair
2394 /* DATA points to an rtx_subst_pair. Return the value that should be
2398 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2400 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2402 if (!rtx_equal_p (from
, old_rtx
))
2404 if (!pair
->adjusted
)
2406 pair
->adjusted
= true;
2408 pair
->to
= cleanup_auto_inc_dec (pair
->to
, VOIDmode
);
2410 pair
->to
= copy_rtx (pair
->to
);
2412 pair
->to
= make_compound_operation (pair
->to
, SET
);
2415 return copy_rtx (pair
->to
);
2418 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2422 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
)
2426 struct rtx_subst_pair p
;
2430 next
= NEXT_INSN (insn
);
2431 while (next
!= last
)
2434 next
= NEXT_INSN (insn
);
2435 if (DEBUG_INSN_P (insn
))
2437 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2438 dest
, propagate_for_debug_subst
, &p
);
2439 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2441 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2442 df_insn_rescan (insn
);
2447 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2448 Note that the INSN should be deleted *after* removing dead edges, so
2449 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2450 but not for a (set (pc) (label_ref FOO)). */
2453 update_cfg_for_uncondjump (rtx insn
)
2455 basic_block bb
= BLOCK_FOR_INSN (insn
);
2456 bool at_end
= (BB_END (bb
) == insn
);
2459 purge_dead_edges (bb
);
2462 if (at_end
&& EDGE_COUNT (bb
->succs
) == 1)
2466 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2468 /* Remove barriers from the footer if there are any. */
2469 for (insn
= bb
->il
.rtl
->footer
; insn
; insn
= NEXT_INSN (insn
))
2470 if (BARRIER_P (insn
))
2472 if (PREV_INSN (insn
))
2473 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2475 bb
->il
.rtl
->footer
= NEXT_INSN (insn
);
2476 if (NEXT_INSN (insn
))
2477 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2479 else if (LABEL_P (insn
))
2484 /* Try to combine the insns I0, I1 and I2 into I3.
2485 Here I0, I1 and I2 appear earlier than I3.
2486 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2489 If we are combining more than two insns and the resulting insn is not
2490 recognized, try splitting it into two insns. If that happens, I2 and I3
2491 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2492 Otherwise, I0, I1 and I2 are pseudo-deleted.
2494 Return 0 if the combination does not work. Then nothing is changed.
2495 If we did the combination, return the insn at which combine should
2498 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2499 new direct jump instruction. */
2502 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
)
2504 /* New patterns for I3 and I2, respectively. */
2505 rtx newpat
, newi2pat
= 0;
2506 rtvec newpat_vec_with_clobbers
= 0;
2507 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2508 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2510 int added_sets_0
, added_sets_1
, added_sets_2
;
2511 /* Total number of SETs to put into I3. */
2513 /* Nonzero if I2's or I1's body now appears in I3. */
2514 int i2_is_used
= 0, i1_is_used
= 0;
2515 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2516 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2517 /* Contains I3 if the destination of I3 is used in its source, which means
2518 that the old life of I3 is being killed. If that usage is placed into
2519 I2 and not in I3, a REG_DEAD note must be made. */
2520 rtx i3dest_killed
= 0;
2521 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2522 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2523 /* Copy of SET_SRC of I1, if needed. */
2525 /* Set if I2DEST was reused as a scratch register. */
2526 bool i2scratch
= false;
2527 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2528 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2529 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2530 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2531 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2532 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2533 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2534 /* Notes that must be added to REG_NOTES in I3 and I2. */
2535 rtx new_i3_notes
, new_i2_notes
;
2536 /* Notes that we substituted I3 into I2 instead of the normal case. */
2537 int i3_subst_into_i2
= 0;
2538 /* Notes that I1, I2 or I3 is a MULT operation. */
2541 int changed_i3_dest
= 0;
2547 rtx new_other_notes
;
2550 /* Only try four-insn combinations when there's high likelihood of
2551 success. Look for simple insns, such as loads of constants or
2552 binary operations involving a constant. */
2559 if (!flag_expensive_optimizations
)
2562 for (i
= 0; i
< 4; i
++)
2564 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2565 rtx set
= single_set (insn
);
2569 src
= SET_SRC (set
);
2570 if (CONSTANT_P (src
))
2575 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2577 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2578 || GET_CODE (src
) == LSHIFTRT
)
2581 if (ngood
< 2 && nshift
< 2)
2585 /* Exit early if one of the insns involved can't be used for
2587 if (cant_combine_insn_p (i3
)
2588 || cant_combine_insn_p (i2
)
2589 || (i1
&& cant_combine_insn_p (i1
))
2590 || (i0
&& cant_combine_insn_p (i0
))
2591 || likely_spilled_retval_p (i3
))
2595 undobuf
.other_insn
= 0;
2597 /* Reset the hard register usage information. */
2598 CLEAR_HARD_REG_SET (newpat_used_regs
);
2600 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2603 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2604 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2606 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2607 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2609 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2610 INSN_UID (i2
), INSN_UID (i3
));
2613 /* If multiple insns feed into one of I2 or I3, they can be in any
2614 order. To simplify the code below, reorder them in sequence. */
2615 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2616 temp
= i2
, i2
= i0
, i0
= temp
;
2617 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2618 temp
= i1
, i1
= i0
, i0
= temp
;
2619 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2620 temp
= i1
, i1
= i2
, i2
= temp
;
2622 added_links_insn
= 0;
2624 /* First check for one important special case that the code below will
2625 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2626 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2627 we may be able to replace that destination with the destination of I3.
2628 This occurs in the common code where we compute both a quotient and
2629 remainder into a structure, in which case we want to do the computation
2630 directly into the structure to avoid register-register copies.
2632 Note that this case handles both multiple sets in I2 and also cases
2633 where I2 has a number of CLOBBERs inside the PARALLEL.
2635 We make very conservative checks below and only try to handle the
2636 most common cases of this. For example, we only handle the case
2637 where I2 and I3 are adjacent to avoid making difficult register
2640 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2641 && REG_P (SET_SRC (PATTERN (i3
)))
2642 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2643 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2644 && GET_CODE (PATTERN (i2
)) == PARALLEL
2645 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2646 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2647 below would need to check what is inside (and reg_overlap_mentioned_p
2648 doesn't support those codes anyway). Don't allow those destinations;
2649 the resulting insn isn't likely to be recognized anyway. */
2650 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2651 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2652 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2653 SET_DEST (PATTERN (i3
)))
2654 && next_active_insn (i2
) == i3
)
2656 rtx p2
= PATTERN (i2
);
2658 /* Make sure that the destination of I3,
2659 which we are going to substitute into one output of I2,
2660 is not used within another output of I2. We must avoid making this:
2661 (parallel [(set (mem (reg 69)) ...)
2662 (set (reg 69) ...)])
2663 which is not well-defined as to order of actions.
2664 (Besides, reload can't handle output reloads for this.)
2666 The problem can also happen if the dest of I3 is a memory ref,
2667 if another dest in I2 is an indirect memory ref. */
2668 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2669 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2670 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2671 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2672 SET_DEST (XVECEXP (p2
, 0, i
))))
2675 if (i
== XVECLEN (p2
, 0))
2676 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2677 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2678 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2683 subst_low_luid
= DF_INSN_LUID (i2
);
2685 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2686 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2687 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2688 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2690 /* Replace the dest in I2 with our dest and make the resulting
2691 insn the new pattern for I3. Then skip to where we validate
2692 the pattern. Everything was set up above. */
2693 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2695 i3_subst_into_i2
= 1;
2696 goto validate_replacement
;
2700 /* If I2 is setting a pseudo to a constant and I3 is setting some
2701 sub-part of it to another constant, merge them by making a new
2704 && (temp
= single_set (i2
)) != 0
2705 && (CONST_INT_P (SET_SRC (temp
))
2706 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2707 && GET_CODE (PATTERN (i3
)) == SET
2708 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2709 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2710 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2712 rtx dest
= SET_DEST (PATTERN (i3
));
2716 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2718 if (CONST_INT_P (XEXP (dest
, 1))
2719 && CONST_INT_P (XEXP (dest
, 2)))
2721 width
= INTVAL (XEXP (dest
, 1));
2722 offset
= INTVAL (XEXP (dest
, 2));
2723 dest
= XEXP (dest
, 0);
2724 if (BITS_BIG_ENDIAN
)
2725 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2730 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2731 dest
= XEXP (dest
, 0);
2732 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2738 /* If this is the low part, we're done. */
2739 if (subreg_lowpart_p (dest
))
2741 /* Handle the case where inner is twice the size of outer. */
2742 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2743 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2744 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2745 /* Otherwise give up for now. */
2751 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2752 <= HOST_BITS_PER_DOUBLE_INT
))
2755 rtx inner
= SET_SRC (PATTERN (i3
));
2756 rtx outer
= SET_SRC (temp
);
2758 o
= rtx_to_double_int (outer
);
2759 i
= rtx_to_double_int (inner
);
2761 m
= double_int_mask (width
);
2762 i
= double_int_and (i
, m
);
2763 m
= double_int_lshift (m
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2764 i
= double_int_lshift (i
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2765 o
= double_int_ior (double_int_and_not (o
, m
), i
);
2769 subst_low_luid
= DF_INSN_LUID (i2
);
2770 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2771 i2dest
= SET_DEST (temp
);
2772 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2774 /* Replace the source in I2 with the new constant and make the
2775 resulting insn the new pattern for I3. Then skip to where we
2776 validate the pattern. Everything was set up above. */
2777 SUBST (SET_SRC (temp
),
2778 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2780 newpat
= PATTERN (i2
);
2782 /* The dest of I3 has been replaced with the dest of I2. */
2783 changed_i3_dest
= 1;
2784 goto validate_replacement
;
2789 /* If we have no I1 and I2 looks like:
2790 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2792 make up a dummy I1 that is
2795 (set (reg:CC X) (compare:CC Y (const_int 0)))
2797 (We can ignore any trailing CLOBBERs.)
2799 This undoes a previous combination and allows us to match a branch-and-
2802 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2803 && XVECLEN (PATTERN (i2
), 0) >= 2
2804 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2805 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2807 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2808 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2809 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2810 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2811 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2812 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2814 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2815 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2820 /* We make I1 with the same INSN_UID as I2. This gives it
2821 the same DF_INSN_LUID for value tracking. Our fake I1 will
2822 never appear in the insn stream so giving it the same INSN_UID
2823 as I2 will not cause a problem. */
2825 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2826 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2827 INSN_LOCATOR (i2
), -1, NULL_RTX
);
2829 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2830 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2831 SET_DEST (PATTERN (i1
)));
2836 /* Verify that I2 and I1 are valid for combining. */
2837 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2838 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2840 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2847 /* Record whether I2DEST is used in I2SRC and similarly for the other
2848 cases. Knowing this will help in register status updating below. */
2849 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2850 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2851 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2852 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2853 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2854 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2855 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2856 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2857 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2859 /* For the earlier insns, determine which of the subsequent ones they
2861 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2862 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2863 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2864 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2865 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2867 /* Ensure that I3's pattern can be the destination of combines. */
2868 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2869 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2870 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2871 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2878 /* See if any of the insns is a MULT operation. Unless one is, we will
2879 reject a combination that is, since it must be slower. Be conservative
2881 if (GET_CODE (i2src
) == MULT
2882 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2883 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2884 || (GET_CODE (PATTERN (i3
)) == SET
2885 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2888 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2889 We used to do this EXCEPT in one case: I3 has a post-inc in an
2890 output operand. However, that exception can give rise to insns like
2892 which is a famous insn on the PDP-11 where the value of r3 used as the
2893 source was model-dependent. Avoid this sort of thing. */
2896 if (!(GET_CODE (PATTERN (i3
)) == SET
2897 && REG_P (SET_SRC (PATTERN (i3
)))
2898 && MEM_P (SET_DEST (PATTERN (i3
)))
2899 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2900 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2901 /* It's not the exception. */
2904 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2905 if (REG_NOTE_KIND (link
) == REG_INC
2906 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2908 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2915 /* See if the SETs in I1 or I2 need to be kept around in the merged
2916 instruction: whenever the value set there is still needed past I3.
2917 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2919 For the SET in I1, we have two cases: If I1 and I2 independently
2920 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2921 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2922 in I1 needs to be kept around unless I1DEST dies or is set in either
2923 I2 or I3. The same consideration applies to I0. */
2925 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2928 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2929 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2934 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2935 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
2936 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
2940 /* We are about to copy insns for the case where they need to be kept
2941 around. Check that they can be copied in the merged instruction. */
2943 if (targetm
.cannot_copy_insn_p
2944 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2945 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2946 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2952 /* If the set in I2 needs to be kept around, we must make a copy of
2953 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2954 PATTERN (I2), we are only substituting for the original I1DEST, not into
2955 an already-substituted copy. This also prevents making self-referential
2956 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2961 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2962 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2964 i2pat
= copy_rtx (PATTERN (i2
));
2969 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2970 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2972 i1pat
= copy_rtx (PATTERN (i1
));
2977 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2978 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2980 i0pat
= copy_rtx (PATTERN (i0
));
2985 /* Substitute in the latest insn for the regs set by the earlier ones. */
2987 maxreg
= max_reg_num ();
2992 /* Many machines that don't use CC0 have insns that can both perform an
2993 arithmetic operation and set the condition code. These operations will
2994 be represented as a PARALLEL with the first element of the vector
2995 being a COMPARE of an arithmetic operation with the constant zero.
2996 The second element of the vector will set some pseudo to the result
2997 of the same arithmetic operation. If we simplify the COMPARE, we won't
2998 match such a pattern and so will generate an extra insn. Here we test
2999 for this case, where both the comparison and the operation result are
3000 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3001 I2SRC. Later we will make the PARALLEL that contains I2. */
3003 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3004 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3005 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
3006 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3008 #ifdef SELECT_CC_MODE
3010 enum machine_mode compare_mode
;
3013 newpat
= PATTERN (i3
);
3014 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
3018 #ifdef SELECT_CC_MODE
3019 /* See if a COMPARE with the operand we substituted in should be done
3020 with the mode that is currently being used. If not, do the same
3021 processing we do in `subst' for a SET; namely, if the destination
3022 is used only once, try to replace it with a register of the proper
3023 mode and also replace the COMPARE. */
3024 if (undobuf
.other_insn
== 0
3025 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
3026 &undobuf
.other_insn
))
3027 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
3029 != GET_MODE (SET_DEST (newpat
))))
3031 if (can_change_dest_mode (SET_DEST (newpat
), added_sets_2
,
3034 unsigned int regno
= REGNO (SET_DEST (newpat
));
3037 if (regno
< FIRST_PSEUDO_REGISTER
)
3038 new_dest
= gen_rtx_REG (compare_mode
, regno
);
3041 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3042 new_dest
= regno_reg_rtx
[regno
];
3045 SUBST (SET_DEST (newpat
), new_dest
);
3046 SUBST (XEXP (*cc_use
, 0), new_dest
);
3047 SUBST (SET_SRC (newpat
),
3048 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
3051 undobuf
.other_insn
= 0;
3058 /* It is possible that the source of I2 or I1 may be performing
3059 an unneeded operation, such as a ZERO_EXTEND of something
3060 that is known to have the high part zero. Handle that case
3061 by letting subst look at the innermost one of them.
3063 Another way to do this would be to have a function that tries
3064 to simplify a single insn instead of merging two or more
3065 insns. We don't do this because of the potential of infinite
3066 loops and because of the potential extra memory required.
3067 However, doing it the way we are is a bit of a kludge and
3068 doesn't catch all cases.
3070 But only do this if -fexpensive-optimizations since it slows
3071 things down and doesn't usually win.
3073 This is not done in the COMPARE case above because the
3074 unmodified I2PAT is used in the PARALLEL and so a pattern
3075 with a modified I2SRC would not match. */
3077 if (flag_expensive_optimizations
)
3079 /* Pass pc_rtx so no substitutions are done, just
3083 subst_low_luid
= DF_INSN_LUID (i1
);
3084 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
3088 subst_low_luid
= DF_INSN_LUID (i2
);
3089 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
3093 n_occurrences
= 0; /* `subst' counts here */
3094 subst_low_luid
= DF_INSN_LUID (i2
);
3096 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3097 copy of I2SRC each time we substitute it, in order to avoid creating
3098 self-referential RTL when we will be substituting I1SRC for I1DEST
3099 later. Likewise if I0 feeds into I2, either directly or indirectly
3100 through I1, and I0DEST is in I0SRC. */
3101 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
3102 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3103 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3104 && i0dest_in_i0src
));
3107 /* Record whether I2's body now appears within I3's body. */
3108 i2_is_used
= n_occurrences
;
3111 /* If we already got a failure, don't try to do more. Otherwise, try to
3112 substitute I1 if we have it. */
3114 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3116 /* Check that an autoincrement side-effect on I1 has not been lost.
3117 This happens if I1DEST is mentioned in I2 and dies there, and
3118 has disappeared from the new pattern. */
3119 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3121 && dead_or_set_p (i2
, i1dest
)
3122 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3123 /* Before we can do this substitution, we must redo the test done
3124 above (see detailed comments there) that ensures I1DEST isn't
3125 mentioned in any SETs in NEWPAT that are field assignments. */
3126 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3134 subst_low_luid
= DF_INSN_LUID (i1
);
3136 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3137 copy of I1SRC each time we substitute it, in order to avoid creating
3138 self-referential RTL when we will be substituting I0SRC for I0DEST
3140 newpat
= subst (newpat
, i1dest
, i1src
, 0,
3141 i0_feeds_i1_n
&& i0dest_in_i0src
);
3144 /* Record whether I1's body now appears within I3's body. */
3145 i1_is_used
= n_occurrences
;
3148 /* Likewise for I0 if we have it. */
3150 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3152 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3153 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3154 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3155 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3156 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3163 /* If the following substitution will modify I1SRC, make a copy of it
3164 for the case where it is substituted for I1DEST in I2PAT later. */
3165 if (i0_feeds_i1_n
&& added_sets_2
&& i1_feeds_i2_n
)
3166 i1src_copy
= copy_rtx (i1src
);
3169 subst_low_luid
= DF_INSN_LUID (i0
);
3170 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0);
3174 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3175 to count all the ways that I2SRC and I1SRC can be used. */
3176 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3177 && i2_is_used
+ added_sets_2
> 1)
3178 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3179 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3181 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3182 && (n_occurrences
+ added_sets_0
3183 + (added_sets_1
&& i0_feeds_i1_n
)
3184 + (added_sets_2
&& i0_feeds_i2_n
)
3186 /* Fail if we tried to make a new register. */
3187 || max_reg_num () != maxreg
3188 /* Fail if we couldn't do something and have a CLOBBER. */
3189 || GET_CODE (newpat
) == CLOBBER
3190 /* Fail if this new pattern is a MULT and we didn't have one before
3191 at the outer level. */
3192 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3199 /* If the actions of the earlier insns must be kept
3200 in addition to substituting them into the latest one,
3201 we must make a new PARALLEL for the latest insn
3202 to hold additional the SETs. */
3204 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3206 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3209 if (GET_CODE (newpat
) == PARALLEL
)
3211 rtvec old
= XVEC (newpat
, 0);
3212 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3213 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3214 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3215 sizeof (old
->elem
[0]) * old
->num_elem
);
3220 total_sets
= 1 + extra_sets
;
3221 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3222 XVECEXP (newpat
, 0, 0) = old
;
3226 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3232 t
= subst (t
, i0dest
, i0src
, 0, 0);
3234 XVECEXP (newpat
, 0, --total_sets
) = t
;
3240 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0,
3241 i0_feeds_i1_n
&& i0dest_in_i0src
);
3242 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3243 t
= subst (t
, i0dest
, i0src
, 0, 0);
3245 XVECEXP (newpat
, 0, --total_sets
) = t
;
3249 validate_replacement
:
3251 /* Note which hard regs this insn has as inputs. */
3252 mark_used_regs_combine (newpat
);
3254 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3255 consider splitting this pattern, we might need these clobbers. */
3256 if (i1
&& GET_CODE (newpat
) == PARALLEL
3257 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3259 int len
= XVECLEN (newpat
, 0);
3261 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3262 for (i
= 0; i
< len
; i
++)
3263 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3266 /* Is the result of combination a valid instruction? */
3267 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3269 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3270 the second SET's destination is a register that is unused and isn't
3271 marked as an instruction that might trap in an EH region. In that case,
3272 we just need the first SET. This can occur when simplifying a divmod
3273 insn. We *must* test for this case here because the code below that
3274 splits two independent SETs doesn't handle this case correctly when it
3275 updates the register status.
3277 It's pointless doing this if we originally had two sets, one from
3278 i3, and one from i2. Combining then splitting the parallel results
3279 in the original i2 again plus an invalid insn (which we delete).
3280 The net effect is only to move instructions around, which makes
3281 debug info less accurate.
3283 Also check the case where the first SET's destination is unused.
3284 That would not cause incorrect code, but does cause an unneeded
3287 if (insn_code_number
< 0
3288 && !(added_sets_2
&& i1
== 0)
3289 && GET_CODE (newpat
) == PARALLEL
3290 && XVECLEN (newpat
, 0) == 2
3291 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3292 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3293 && asm_noperands (newpat
) < 0)
3295 rtx set0
= XVECEXP (newpat
, 0, 0);
3296 rtx set1
= XVECEXP (newpat
, 0, 1);
3298 if (((REG_P (SET_DEST (set1
))
3299 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3300 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3301 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3302 && insn_nothrow_p (i3
)
3303 && !side_effects_p (SET_SRC (set1
)))
3306 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3309 else if (((REG_P (SET_DEST (set0
))
3310 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3311 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3312 && find_reg_note (i3
, REG_UNUSED
,
3313 SUBREG_REG (SET_DEST (set0
)))))
3314 && insn_nothrow_p (i3
)
3315 && !side_effects_p (SET_SRC (set0
)))
3318 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3320 if (insn_code_number
>= 0)
3321 changed_i3_dest
= 1;
3325 /* If we were combining three insns and the result is a simple SET
3326 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3327 insns. There are two ways to do this. It can be split using a
3328 machine-specific method (like when you have an addition of a large
3329 constant) or by combine in the function find_split_point. */
3331 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3332 && asm_noperands (newpat
) < 0)
3334 rtx parallel
, m_split
, *split
;
3336 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3337 use I2DEST as a scratch register will help. In the latter case,
3338 convert I2DEST to the mode of the source of NEWPAT if we can. */
3340 m_split
= combine_split_insns (newpat
, i3
);
3342 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3343 inputs of NEWPAT. */
3345 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3346 possible to try that as a scratch reg. This would require adding
3347 more code to make it work though. */
3349 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3351 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3353 /* First try to split using the original register as a
3354 scratch register. */
3355 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3356 gen_rtvec (2, newpat
,
3357 gen_rtx_CLOBBER (VOIDmode
,
3359 m_split
= combine_split_insns (parallel
, i3
);
3361 /* If that didn't work, try changing the mode of I2DEST if
3364 && new_mode
!= GET_MODE (i2dest
)
3365 && new_mode
!= VOIDmode
3366 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3368 enum machine_mode old_mode
= GET_MODE (i2dest
);
3371 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3372 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3375 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3376 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3379 parallel
= (gen_rtx_PARALLEL
3381 gen_rtvec (2, newpat
,
3382 gen_rtx_CLOBBER (VOIDmode
,
3384 m_split
= combine_split_insns (parallel
, i3
);
3387 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3391 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3392 buf
= undobuf
.undos
;
3393 undobuf
.undos
= buf
->next
;
3394 buf
->next
= undobuf
.frees
;
3395 undobuf
.frees
= buf
;
3399 i2scratch
= m_split
!= 0;
3402 /* If recog_for_combine has discarded clobbers, try to use them
3403 again for the split. */
3404 if (m_split
== 0 && newpat_vec_with_clobbers
)
3406 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3407 m_split
= combine_split_insns (parallel
, i3
);
3410 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3412 m_split
= PATTERN (m_split
);
3413 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3414 if (insn_code_number
>= 0)
3417 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3418 && (next_real_insn (i2
) == i3
3419 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3422 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3423 newi2pat
= PATTERN (m_split
);
3425 i3set
= single_set (NEXT_INSN (m_split
));
3426 i2set
= single_set (m_split
);
3428 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3430 /* If I2 or I3 has multiple SETs, we won't know how to track
3431 register status, so don't use these insns. If I2's destination
3432 is used between I2 and I3, we also can't use these insns. */
3434 if (i2_code_number
>= 0 && i2set
&& i3set
3435 && (next_real_insn (i2
) == i3
3436 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3437 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3439 if (insn_code_number
>= 0)
3442 /* It is possible that both insns now set the destination of I3.
3443 If so, we must show an extra use of it. */
3445 if (insn_code_number
>= 0)
3447 rtx new_i3_dest
= SET_DEST (i3set
);
3448 rtx new_i2_dest
= SET_DEST (i2set
);
3450 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3451 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3452 || GET_CODE (new_i3_dest
) == SUBREG
)
3453 new_i3_dest
= XEXP (new_i3_dest
, 0);
3455 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3456 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3457 || GET_CODE (new_i2_dest
) == SUBREG
)
3458 new_i2_dest
= XEXP (new_i2_dest
, 0);
3460 if (REG_P (new_i3_dest
)
3461 && REG_P (new_i2_dest
)
3462 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3463 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3467 /* If we can split it and use I2DEST, go ahead and see if that
3468 helps things be recognized. Verify that none of the registers
3469 are set between I2 and I3. */
3470 if (insn_code_number
< 0
3471 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3475 /* We need I2DEST in the proper mode. If it is a hard register
3476 or the only use of a pseudo, we can change its mode.
3477 Make sure we don't change a hard register to have a mode that
3478 isn't valid for it, or change the number of registers. */
3479 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3480 || GET_MODE (*split
) == VOIDmode
3481 || can_change_dest_mode (i2dest
, added_sets_2
,
3483 && (next_real_insn (i2
) == i3
3484 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3485 /* We can't overwrite I2DEST if its value is still used by
3487 && ! reg_referenced_p (i2dest
, newpat
))
3489 rtx newdest
= i2dest
;
3490 enum rtx_code split_code
= GET_CODE (*split
);
3491 enum machine_mode split_mode
= GET_MODE (*split
);
3492 bool subst_done
= false;
3493 newi2pat
= NULL_RTX
;
3497 /* *SPLIT may be part of I2SRC, so make sure we have the
3498 original expression around for later debug processing.
3499 We should not need I2SRC any more in other cases. */
3500 if (MAY_HAVE_DEBUG_INSNS
)
3501 i2src
= copy_rtx (i2src
);
3505 /* Get NEWDEST as a register in the proper mode. We have already
3506 validated that we can do this. */
3507 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3509 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3510 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3513 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3514 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3518 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3519 an ASHIFT. This can occur if it was inside a PLUS and hence
3520 appeared to be a memory address. This is a kludge. */
3521 if (split_code
== MULT
3522 && CONST_INT_P (XEXP (*split
, 1))
3523 && INTVAL (XEXP (*split
, 1)) > 0
3524 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3526 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3527 XEXP (*split
, 0), GEN_INT (i
)));
3528 /* Update split_code because we may not have a multiply
3530 split_code
= GET_CODE (*split
);
3533 #ifdef INSN_SCHEDULING
3534 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3535 be written as a ZERO_EXTEND. */
3536 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3538 #ifdef LOAD_EXTEND_OP
3539 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3540 what it really is. */
3541 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3543 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3544 SUBREG_REG (*split
)));
3547 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3548 SUBREG_REG (*split
)));
3552 /* Attempt to split binary operators using arithmetic identities. */
3553 if (BINARY_P (SET_SRC (newpat
))
3554 && split_mode
== GET_MODE (SET_SRC (newpat
))
3555 && ! side_effects_p (SET_SRC (newpat
)))
3557 rtx setsrc
= SET_SRC (newpat
);
3558 enum machine_mode mode
= GET_MODE (setsrc
);
3559 enum rtx_code code
= GET_CODE (setsrc
);
3560 rtx src_op0
= XEXP (setsrc
, 0);
3561 rtx src_op1
= XEXP (setsrc
, 1);
3563 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3564 if (rtx_equal_p (src_op0
, src_op1
))
3566 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3567 SUBST (XEXP (setsrc
, 0), newdest
);
3568 SUBST (XEXP (setsrc
, 1), newdest
);
3571 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3572 else if ((code
== PLUS
|| code
== MULT
)
3573 && GET_CODE (src_op0
) == code
3574 && GET_CODE (XEXP (src_op0
, 0)) == code
3575 && (INTEGRAL_MODE_P (mode
)
3576 || (FLOAT_MODE_P (mode
)
3577 && flag_unsafe_math_optimizations
)))
3579 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3580 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3581 rtx r
= XEXP (src_op0
, 1);
3584 /* Split both "((X op Y) op X) op Y" and
3585 "((X op Y) op Y) op X" as "T op T" where T is
3587 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3588 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3590 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3592 SUBST (XEXP (setsrc
, 0), newdest
);
3593 SUBST (XEXP (setsrc
, 1), newdest
);
3596 /* Split "((X op X) op Y) op Y)" as "T op T" where
3598 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3600 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3601 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3602 SUBST (XEXP (setsrc
, 0), newdest
);
3603 SUBST (XEXP (setsrc
, 1), newdest
);
3611 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3612 SUBST (*split
, newdest
);
3615 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3617 /* recog_for_combine might have added CLOBBERs to newi2pat.
3618 Make sure NEWPAT does not depend on the clobbered regs. */
3619 if (GET_CODE (newi2pat
) == PARALLEL
)
3620 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3621 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3623 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3624 if (reg_overlap_mentioned_p (reg
, newpat
))
3631 /* If the split point was a MULT and we didn't have one before,
3632 don't use one now. */
3633 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3634 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3638 /* Check for a case where we loaded from memory in a narrow mode and
3639 then sign extended it, but we need both registers. In that case,
3640 we have a PARALLEL with both loads from the same memory location.
3641 We can split this into a load from memory followed by a register-register
3642 copy. This saves at least one insn, more if register allocation can
3645 We cannot do this if the destination of the first assignment is a
3646 condition code register or cc0. We eliminate this case by making sure
3647 the SET_DEST and SET_SRC have the same mode.
3649 We cannot do this if the destination of the second assignment is
3650 a register that we have already assumed is zero-extended. Similarly
3651 for a SUBREG of such a register. */
3653 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3654 && GET_CODE (newpat
) == PARALLEL
3655 && XVECLEN (newpat
, 0) == 2
3656 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3657 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3658 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3659 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3660 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3661 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3662 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3663 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3665 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3666 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3667 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3669 && VEC_index (reg_stat_type
, reg_stat
,
3670 REGNO (temp
))->nonzero_bits
!= 0
3671 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3672 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3673 && (VEC_index (reg_stat_type
, reg_stat
,
3674 REGNO (temp
))->nonzero_bits
3675 != GET_MODE_MASK (word_mode
))))
3676 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3677 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3679 && VEC_index (reg_stat_type
, reg_stat
,
3680 REGNO (temp
))->nonzero_bits
!= 0
3681 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3682 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3683 && (VEC_index (reg_stat_type
, reg_stat
,
3684 REGNO (temp
))->nonzero_bits
3685 != GET_MODE_MASK (word_mode
)))))
3686 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3687 SET_SRC (XVECEXP (newpat
, 0, 1)))
3688 && ! find_reg_note (i3
, REG_UNUSED
,
3689 SET_DEST (XVECEXP (newpat
, 0, 0))))
3693 newi2pat
= XVECEXP (newpat
, 0, 0);
3694 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3695 newpat
= XVECEXP (newpat
, 0, 1);
3696 SUBST (SET_SRC (newpat
),
3697 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3698 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3700 if (i2_code_number
>= 0)
3701 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3703 if (insn_code_number
>= 0)
3707 /* Similarly, check for a case where we have a PARALLEL of two independent
3708 SETs but we started with three insns. In this case, we can do the sets
3709 as two separate insns. This case occurs when some SET allows two
3710 other insns to combine, but the destination of that SET is still live. */
3712 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3713 && GET_CODE (newpat
) == PARALLEL
3714 && XVECLEN (newpat
, 0) == 2
3715 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3716 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3717 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3718 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3719 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3720 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3721 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3722 XVECEXP (newpat
, 0, 0))
3723 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3724 XVECEXP (newpat
, 0, 1))
3725 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3726 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3728 /* Normally, it doesn't matter which of the two is done first,
3729 but the one that references cc0 can't be the second, and
3730 one which uses any regs/memory set in between i2 and i3 can't
3732 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3735 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3739 newi2pat
= XVECEXP (newpat
, 0, 1);
3740 newpat
= XVECEXP (newpat
, 0, 0);
3742 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3745 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3749 newi2pat
= XVECEXP (newpat
, 0, 0);
3750 newpat
= XVECEXP (newpat
, 0, 1);
3758 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3760 if (i2_code_number
>= 0)
3762 /* recog_for_combine might have added CLOBBERs to newi2pat.
3763 Make sure NEWPAT does not depend on the clobbered regs. */
3764 if (GET_CODE (newi2pat
) == PARALLEL
)
3766 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3767 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3769 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3770 if (reg_overlap_mentioned_p (reg
, newpat
))
3778 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3782 /* If it still isn't recognized, fail and change things back the way they
3784 if ((insn_code_number
< 0
3785 /* Is the result a reasonable ASM_OPERANDS? */
3786 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3792 /* If we had to change another insn, make sure it is valid also. */
3793 if (undobuf
.other_insn
)
3795 CLEAR_HARD_REG_SET (newpat_used_regs
);
3797 other_pat
= PATTERN (undobuf
.other_insn
);
3798 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3801 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3809 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3810 they are adjacent to each other or not. */
3812 rtx p
= prev_nonnote_insn (i3
);
3813 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3814 && sets_cc0_p (newi2pat
))
3822 /* Only allow this combination if insn_rtx_costs reports that the
3823 replacement instructions are cheaper than the originals. */
3824 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3830 if (MAY_HAVE_DEBUG_INSNS
)
3834 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3835 if (undo
->kind
== UNDO_MODE
)
3837 rtx reg
= *undo
->where
.r
;
3838 enum machine_mode new_mode
= GET_MODE (reg
);
3839 enum machine_mode old_mode
= undo
->old_contents
.m
;
3841 /* Temporarily revert mode back. */
3842 adjust_reg_mode (reg
, old_mode
);
3844 if (reg
== i2dest
&& i2scratch
)
3846 /* If we used i2dest as a scratch register with a
3847 different mode, substitute it for the original
3848 i2src while its original mode is temporarily
3849 restored, and then clear i2scratch so that we don't
3850 do it again later. */
3851 propagate_for_debug (i2
, i3
, reg
, i2src
);
3853 /* Put back the new mode. */
3854 adjust_reg_mode (reg
, new_mode
);
3858 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3869 last
= undobuf
.other_insn
;
3873 /* We're dealing with a reg that changed mode but not
3874 meaning, so we want to turn it into a subreg for
3875 the new mode. However, because of REG sharing and
3876 because its mode had already changed, we have to do
3877 it in two steps. First, replace any debug uses of
3878 reg, with its original mode temporarily restored,
3879 with this copy we have created; then, replace the
3880 copy with the SUBREG of the original shared reg,
3881 once again changed to the new mode. */
3882 propagate_for_debug (first
, last
, reg
, tempreg
);
3883 adjust_reg_mode (reg
, new_mode
);
3884 propagate_for_debug (first
, last
, tempreg
,
3885 lowpart_subreg (old_mode
, reg
, new_mode
));
3890 /* If we will be able to accept this, we have made a
3891 change to the destination of I3. This requires us to
3892 do a few adjustments. */
3894 if (changed_i3_dest
)
3896 PATTERN (i3
) = newpat
;
3897 adjust_for_new_dest (i3
);
3900 /* We now know that we can do this combination. Merge the insns and
3901 update the status of registers and LOG_LINKS. */
3903 if (undobuf
.other_insn
)
3907 PATTERN (undobuf
.other_insn
) = other_pat
;
3909 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3910 are still valid. Then add any non-duplicate notes added by
3911 recog_for_combine. */
3912 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3914 next
= XEXP (note
, 1);
3916 if (REG_NOTE_KIND (note
) == REG_UNUSED
3917 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3918 remove_note (undobuf
.other_insn
, note
);
3921 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3922 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3932 /* I3 now uses what used to be its destination and which is now
3933 I2's destination. This requires us to do a few adjustments. */
3934 PATTERN (i3
) = newpat
;
3935 adjust_for_new_dest (i3
);
3937 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3940 However, some later insn might be using I2's dest and have
3941 a LOG_LINK pointing at I3. We must remove this link.
3942 The simplest way to remove the link is to point it at I1,
3943 which we know will be a NOTE. */
3945 /* newi2pat is usually a SET here; however, recog_for_combine might
3946 have added some clobbers. */
3947 if (GET_CODE (newi2pat
) == PARALLEL
)
3948 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3950 ni2dest
= SET_DEST (newi2pat
);
3952 for (insn
= NEXT_INSN (i3
);
3953 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3954 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3955 insn
= NEXT_INSN (insn
))
3957 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3959 for (link
= LOG_LINKS (insn
); link
;
3960 link
= XEXP (link
, 1))
3961 if (XEXP (link
, 0) == i3
)
3962 XEXP (link
, 0) = i1
;
3970 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3971 rtx i3links
, i2links
, i1links
= 0, i0links
= 0;
3975 /* Compute which registers we expect to eliminate. newi2pat may be setting
3976 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3977 same as i3dest, in which case newi2pat may be setting i1dest. */
3978 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3979 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3982 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3983 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3986 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3987 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3991 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3993 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3994 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3996 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3998 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4000 /* Ensure that we do not have something that should not be shared but
4001 occurs multiple times in the new insns. Check this by first
4002 resetting all the `used' flags and then copying anything is shared. */
4004 reset_used_flags (i3notes
);
4005 reset_used_flags (i2notes
);
4006 reset_used_flags (i1notes
);
4007 reset_used_flags (i0notes
);
4008 reset_used_flags (newpat
);
4009 reset_used_flags (newi2pat
);
4010 if (undobuf
.other_insn
)
4011 reset_used_flags (PATTERN (undobuf
.other_insn
));
4013 i3notes
= copy_rtx_if_shared (i3notes
);
4014 i2notes
= copy_rtx_if_shared (i2notes
);
4015 i1notes
= copy_rtx_if_shared (i1notes
);
4016 i0notes
= copy_rtx_if_shared (i0notes
);
4017 newpat
= copy_rtx_if_shared (newpat
);
4018 newi2pat
= copy_rtx_if_shared (newi2pat
);
4019 if (undobuf
.other_insn
)
4020 reset_used_flags (PATTERN (undobuf
.other_insn
));
4022 INSN_CODE (i3
) = insn_code_number
;
4023 PATTERN (i3
) = newpat
;
4025 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4027 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4029 reset_used_flags (call_usage
);
4030 call_usage
= copy_rtx (call_usage
);
4034 /* I2SRC must still be meaningful at this point. Some splitting
4035 operations can invalidate I2SRC, but those operations do not
4038 replace_rtx (call_usage
, i2dest
, i2src
);
4042 replace_rtx (call_usage
, i1dest
, i1src
);
4044 replace_rtx (call_usage
, i0dest
, i0src
);
4046 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4049 if (undobuf
.other_insn
)
4050 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4052 /* We had one special case above where I2 had more than one set and
4053 we replaced a destination of one of those sets with the destination
4054 of I3. In that case, we have to update LOG_LINKS of insns later
4055 in this basic block. Note that this (expensive) case is rare.
4057 Also, in this case, we must pretend that all REG_NOTEs for I2
4058 actually came from I3, so that REG_UNUSED notes from I2 will be
4059 properly handled. */
4061 if (i3_subst_into_i2
)
4063 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4064 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4065 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4066 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4067 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4068 && ! find_reg_note (i2
, REG_UNUSED
,
4069 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4070 for (temp
= NEXT_INSN (i2
);
4071 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4072 || BB_HEAD (this_basic_block
) != temp
);
4073 temp
= NEXT_INSN (temp
))
4074 if (temp
!= i3
&& INSN_P (temp
))
4075 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
4076 if (XEXP (link
, 0) == i2
)
4077 XEXP (link
, 0) = i3
;
4082 while (XEXP (link
, 1))
4083 link
= XEXP (link
, 1);
4084 XEXP (link
, 1) = i2notes
;
4098 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4099 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4100 INSN_CODE (i2
) = i2_code_number
;
4101 PATTERN (i2
) = newi2pat
;
4105 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4106 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4107 SET_INSN_DELETED (i2
);
4114 if (MAY_HAVE_DEBUG_INSNS
)
4115 propagate_for_debug (i1
, i3
, i1dest
, i1src
);
4116 SET_INSN_DELETED (i1
);
4123 if (MAY_HAVE_DEBUG_INSNS
)
4124 propagate_for_debug (i0
, i3
, i0dest
, i0src
);
4125 SET_INSN_DELETED (i0
);
4128 /* Get death notes for everything that is now used in either I3 or
4129 I2 and used to die in a previous insn. If we built two new
4130 patterns, move from I1 to I2 then I2 to I3 so that we get the
4131 proper movement on registers that I2 modifies. */
4134 from_luid
= DF_INSN_LUID (i0
);
4136 from_luid
= DF_INSN_LUID (i1
);
4138 from_luid
= DF_INSN_LUID (i2
);
4140 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4141 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4143 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4145 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4146 elim_i2
, elim_i1
, elim_i0
);
4148 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4149 elim_i2
, elim_i1
, elim_i0
);
4151 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4152 elim_i2
, elim_i1
, elim_i0
);
4154 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4155 elim_i2
, elim_i1
, elim_i0
);
4157 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4158 elim_i2
, elim_i1
, elim_i0
);
4160 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4161 know these are REG_UNUSED and want them to go to the desired insn,
4162 so we always pass it as i3. */
4164 if (newi2pat
&& new_i2_notes
)
4165 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4169 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4172 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4173 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4174 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4175 in that case, it might delete I2. Similarly for I2 and I1.
4176 Show an additional death due to the REG_DEAD note we make here. If
4177 we discard it in distribute_notes, we will decrement it again. */
4181 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4182 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4184 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4186 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4188 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4189 elim_i2
, elim_i1
, elim_i0
);
4192 if (i2dest_in_i2src
)
4194 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4195 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4196 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4197 NULL_RTX
, NULL_RTX
);
4199 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4200 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4203 if (i1dest_in_i1src
)
4205 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4206 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4207 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4208 NULL_RTX
, NULL_RTX
);
4210 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4211 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4214 if (i0dest_in_i0src
)
4216 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4217 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4218 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4219 NULL_RTX
, NULL_RTX
);
4221 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4222 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4225 distribute_links (i3links
);
4226 distribute_links (i2links
);
4227 distribute_links (i1links
);
4228 distribute_links (i0links
);
4233 rtx i2_insn
= 0, i2_val
= 0, set
;
4235 /* The insn that used to set this register doesn't exist, and
4236 this life of the register may not exist either. See if one of
4237 I3's links points to an insn that sets I2DEST. If it does,
4238 that is now the last known value for I2DEST. If we don't update
4239 this and I2 set the register to a value that depended on its old
4240 contents, we will get confused. If this insn is used, thing
4241 will be set correctly in combine_instructions. */
4243 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4244 if ((set
= single_set (XEXP (link
, 0))) != 0
4245 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4246 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
4248 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4250 /* If the reg formerly set in I2 died only once and that was in I3,
4251 zero its use count so it won't make `reload' do any work. */
4253 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4254 && ! i2dest_in_i2src
)
4256 regno
= REGNO (i2dest
);
4257 INC_REG_N_SETS (regno
, -1);
4261 if (i1
&& REG_P (i1dest
))
4264 rtx i1_insn
= 0, i1_val
= 0, set
;
4266 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4267 if ((set
= single_set (XEXP (link
, 0))) != 0
4268 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4269 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
4271 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4273 regno
= REGNO (i1dest
);
4274 if (! added_sets_1
&& ! i1dest_in_i1src
)
4275 INC_REG_N_SETS (regno
, -1);
4278 if (i0
&& REG_P (i0dest
))
4281 rtx i0_insn
= 0, i0_val
= 0, set
;
4283 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4284 if ((set
= single_set (XEXP (link
, 0))) != 0
4285 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4286 i0_insn
= XEXP (link
, 0), i0_val
= SET_SRC (set
);
4288 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4290 regno
= REGNO (i0dest
);
4291 if (! added_sets_0
&& ! i0dest_in_i0src
)
4292 INC_REG_N_SETS (regno
, -1);
4295 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4296 been made to this insn. The order of
4297 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4298 can affect nonzero_bits of newpat */
4300 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4301 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4304 if (undobuf
.other_insn
!= NULL_RTX
)
4308 fprintf (dump_file
, "modifying other_insn ");
4309 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4311 df_insn_rescan (undobuf
.other_insn
);
4314 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4318 fprintf (dump_file
, "modifying insn i1 ");
4319 dump_insn_slim (dump_file
, i0
);
4321 df_insn_rescan (i0
);
4324 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4328 fprintf (dump_file
, "modifying insn i1 ");
4329 dump_insn_slim (dump_file
, i1
);
4331 df_insn_rescan (i1
);
4334 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4338 fprintf (dump_file
, "modifying insn i2 ");
4339 dump_insn_slim (dump_file
, i2
);
4341 df_insn_rescan (i2
);
4344 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4348 fprintf (dump_file
, "modifying insn i3 ");
4349 dump_insn_slim (dump_file
, i3
);
4351 df_insn_rescan (i3
);
4354 /* Set new_direct_jump_p if a new return or simple jump instruction
4355 has been created. Adjust the CFG accordingly. */
4357 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4359 *new_direct_jump_p
= 1;
4360 mark_jump_label (PATTERN (i3
), i3
, 0);
4361 update_cfg_for_uncondjump (i3
);
4364 if (undobuf
.other_insn
!= NULL_RTX
4365 && (returnjump_p (undobuf
.other_insn
)
4366 || any_uncondjump_p (undobuf
.other_insn
)))
4368 *new_direct_jump_p
= 1;
4369 update_cfg_for_uncondjump (undobuf
.other_insn
);
4372 /* A noop might also need cleaning up of CFG, if it comes from the
4373 simplification of a jump. */
4374 if (GET_CODE (newpat
) == SET
4375 && SET_SRC (newpat
) == pc_rtx
4376 && SET_DEST (newpat
) == pc_rtx
)
4378 *new_direct_jump_p
= 1;
4379 update_cfg_for_uncondjump (i3
);
4382 combine_successes
++;
4385 if (added_links_insn
4386 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4387 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4388 return added_links_insn
;
4390 return newi2pat
? i2
: i3
;
4393 /* Undo all the modifications recorded in undobuf. */
4398 struct undo
*undo
, *next
;
4400 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4406 *undo
->where
.r
= undo
->old_contents
.r
;
4409 *undo
->where
.i
= undo
->old_contents
.i
;
4412 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4418 undo
->next
= undobuf
.frees
;
4419 undobuf
.frees
= undo
;
4425 /* We've committed to accepting the changes we made. Move all
4426 of the undos to the free list. */
4431 struct undo
*undo
, *next
;
4433 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4436 undo
->next
= undobuf
.frees
;
4437 undobuf
.frees
= undo
;
4442 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4443 where we have an arithmetic expression and return that point. LOC will
4446 try_combine will call this function to see if an insn can be split into
4450 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4453 enum rtx_code code
= GET_CODE (x
);
4455 unsigned HOST_WIDE_INT len
= 0;
4456 HOST_WIDE_INT pos
= 0;
4458 rtx inner
= NULL_RTX
;
4460 /* First special-case some codes. */
4464 #ifdef INSN_SCHEDULING
4465 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4467 if (MEM_P (SUBREG_REG (x
)))
4470 return find_split_point (&SUBREG_REG (x
), insn
, false);
4474 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4475 using LO_SUM and HIGH. */
4476 if (GET_CODE (XEXP (x
, 0)) == CONST
4477 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4479 enum machine_mode address_mode
4480 = targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (x
));
4483 gen_rtx_LO_SUM (address_mode
,
4484 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4486 return &XEXP (XEXP (x
, 0), 0);
4490 /* If we have a PLUS whose second operand is a constant and the
4491 address is not valid, perhaps will can split it up using
4492 the machine-specific way to split large constants. We use
4493 the first pseudo-reg (one of the virtual regs) as a placeholder;
4494 it will not remain in the result. */
4495 if (GET_CODE (XEXP (x
, 0)) == PLUS
4496 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4497 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4498 MEM_ADDR_SPACE (x
)))
4500 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4501 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4505 /* This should have produced two insns, each of which sets our
4506 placeholder. If the source of the second is a valid address,
4507 we can make put both sources together and make a split point
4511 && NEXT_INSN (seq
) != NULL_RTX
4512 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4513 && NONJUMP_INSN_P (seq
)
4514 && GET_CODE (PATTERN (seq
)) == SET
4515 && SET_DEST (PATTERN (seq
)) == reg
4516 && ! reg_mentioned_p (reg
,
4517 SET_SRC (PATTERN (seq
)))
4518 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4519 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4520 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4521 && memory_address_addr_space_p
4522 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4523 MEM_ADDR_SPACE (x
)))
4525 rtx src1
= SET_SRC (PATTERN (seq
));
4526 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4528 /* Replace the placeholder in SRC2 with SRC1. If we can
4529 find where in SRC2 it was placed, that can become our
4530 split point and we can replace this address with SRC2.
4531 Just try two obvious places. */
4533 src2
= replace_rtx (src2
, reg
, src1
);
4535 if (XEXP (src2
, 0) == src1
)
4536 split
= &XEXP (src2
, 0);
4537 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4538 && XEXP (XEXP (src2
, 0), 0) == src1
)
4539 split
= &XEXP (XEXP (src2
, 0), 0);
4543 SUBST (XEXP (x
, 0), src2
);
4548 /* If that didn't work, perhaps the first operand is complex and
4549 needs to be computed separately, so make a split point there.
4550 This will occur on machines that just support REG + CONST
4551 and have a constant moved through some previous computation. */
4553 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4554 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4555 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4556 return &XEXP (XEXP (x
, 0), 0);
4559 /* If we have a PLUS whose first operand is complex, try computing it
4560 separately by making a split there. */
4561 if (GET_CODE (XEXP (x
, 0)) == PLUS
4562 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4564 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4565 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4566 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4567 return &XEXP (XEXP (x
, 0), 0);
4572 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4573 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4574 we need to put the operand into a register. So split at that
4577 if (SET_DEST (x
) == cc0_rtx
4578 && GET_CODE (SET_SRC (x
)) != COMPARE
4579 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4580 && !OBJECT_P (SET_SRC (x
))
4581 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4582 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4583 return &SET_SRC (x
);
4586 /* See if we can split SET_SRC as it stands. */
4587 split
= find_split_point (&SET_SRC (x
), insn
, true);
4588 if (split
&& split
!= &SET_SRC (x
))
4591 /* See if we can split SET_DEST as it stands. */
4592 split
= find_split_point (&SET_DEST (x
), insn
, false);
4593 if (split
&& split
!= &SET_DEST (x
))
4596 /* See if this is a bitfield assignment with everything constant. If
4597 so, this is an IOR of an AND, so split it into that. */
4598 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4599 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4600 <= HOST_BITS_PER_WIDE_INT
)
4601 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4602 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4603 && CONST_INT_P (SET_SRC (x
))
4604 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4605 + INTVAL (XEXP (SET_DEST (x
), 2)))
4606 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4607 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4609 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4610 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4611 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4612 rtx dest
= XEXP (SET_DEST (x
), 0);
4613 enum machine_mode mode
= GET_MODE (dest
);
4614 unsigned HOST_WIDE_INT mask
4615 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4618 if (BITS_BIG_ENDIAN
)
4619 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4621 or_mask
= gen_int_mode (src
<< pos
, mode
);
4624 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4627 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4629 simplify_gen_binary (IOR
, mode
,
4630 simplify_gen_binary (AND
, mode
,
4635 SUBST (SET_DEST (x
), dest
);
4637 split
= find_split_point (&SET_SRC (x
), insn
, true);
4638 if (split
&& split
!= &SET_SRC (x
))
4642 /* Otherwise, see if this is an operation that we can split into two.
4643 If so, try to split that. */
4644 code
= GET_CODE (SET_SRC (x
));
4649 /* If we are AND'ing with a large constant that is only a single
4650 bit and the result is only being used in a context where we
4651 need to know if it is zero or nonzero, replace it with a bit
4652 extraction. This will avoid the large constant, which might
4653 have taken more than one insn to make. If the constant were
4654 not a valid argument to the AND but took only one insn to make,
4655 this is no worse, but if it took more than one insn, it will
4658 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4659 && REG_P (XEXP (SET_SRC (x
), 0))
4660 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4661 && REG_P (SET_DEST (x
))
4662 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4663 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4664 && XEXP (*split
, 0) == SET_DEST (x
)
4665 && XEXP (*split
, 1) == const0_rtx
)
4667 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4668 XEXP (SET_SRC (x
), 0),
4669 pos
, NULL_RTX
, 1, 1, 0, 0);
4670 if (extraction
!= 0)
4672 SUBST (SET_SRC (x
), extraction
);
4673 return find_split_point (loc
, insn
, false);
4679 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4680 is known to be on, this can be converted into a NEG of a shift. */
4681 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4682 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4683 && 1 <= (pos
= exact_log2
4684 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4685 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4687 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4691 gen_rtx_LSHIFTRT (mode
,
4692 XEXP (SET_SRC (x
), 0),
4695 split
= find_split_point (&SET_SRC (x
), insn
, true);
4696 if (split
&& split
!= &SET_SRC (x
))
4702 inner
= XEXP (SET_SRC (x
), 0);
4704 /* We can't optimize if either mode is a partial integer
4705 mode as we don't know how many bits are significant
4707 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4708 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4712 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4718 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4719 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4721 inner
= XEXP (SET_SRC (x
), 0);
4722 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4723 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4725 if (BITS_BIG_ENDIAN
)
4726 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4727 unsignedp
= (code
== ZERO_EXTRACT
);
4735 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4737 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4739 /* For unsigned, we have a choice of a shift followed by an
4740 AND or two shifts. Use two shifts for field sizes where the
4741 constant might be too large. We assume here that we can
4742 always at least get 8-bit constants in an AND insn, which is
4743 true for every current RISC. */
4745 if (unsignedp
&& len
<= 8)
4750 (mode
, gen_lowpart (mode
, inner
),
4752 GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
)
4755 split
= find_split_point (&SET_SRC (x
), insn
, true);
4756 if (split
&& split
!= &SET_SRC (x
))
4763 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4764 gen_rtx_ASHIFT (mode
,
4765 gen_lowpart (mode
, inner
),
4766 GEN_INT (GET_MODE_BITSIZE (mode
)
4768 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4770 split
= find_split_point (&SET_SRC (x
), insn
, true);
4771 if (split
&& split
!= &SET_SRC (x
))
4776 /* See if this is a simple operation with a constant as the second
4777 operand. It might be that this constant is out of range and hence
4778 could be used as a split point. */
4779 if (BINARY_P (SET_SRC (x
))
4780 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4781 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4782 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4783 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4784 return &XEXP (SET_SRC (x
), 1);
4786 /* Finally, see if this is a simple operation with its first operand
4787 not in a register. The operation might require this operand in a
4788 register, so return it as a split point. We can always do this
4789 because if the first operand were another operation, we would have
4790 already found it as a split point. */
4791 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4792 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4793 return &XEXP (SET_SRC (x
), 0);
4799 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4800 it is better to write this as (not (ior A B)) so we can split it.
4801 Similarly for IOR. */
4802 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4805 gen_rtx_NOT (GET_MODE (x
),
4806 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4808 XEXP (XEXP (x
, 0), 0),
4809 XEXP (XEXP (x
, 1), 0))));
4810 return find_split_point (loc
, insn
, set_src
);
4813 /* Many RISC machines have a large set of logical insns. If the
4814 second operand is a NOT, put it first so we will try to split the
4815 other operand first. */
4816 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4818 rtx tem
= XEXP (x
, 0);
4819 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4820 SUBST (XEXP (x
, 1), tem
);
4826 /* Canonicalization can produce (minus A (mult B C)), where C is a
4827 constant. It may be better to try splitting (plus (mult B -C) A)
4828 instead if this isn't a multiply by a power of two. */
4829 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4830 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4831 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4833 enum machine_mode mode
= GET_MODE (x
);
4834 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4835 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4836 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4837 XEXP (XEXP (x
, 1), 0),
4838 GEN_INT (other_int
)),
4840 return find_split_point (loc
, insn
, set_src
);
4843 /* Split at a multiply-accumulate instruction. However if this is
4844 the SET_SRC, we likely do not have such an instruction and it's
4845 worthless to try this split. */
4846 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4853 /* Otherwise, select our actions depending on our rtx class. */
4854 switch (GET_RTX_CLASS (code
))
4856 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4858 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4861 /* ... fall through ... */
4863 case RTX_COMM_ARITH
:
4865 case RTX_COMM_COMPARE
:
4866 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4869 /* ... fall through ... */
4871 /* Some machines have (and (shift ...) ...) insns. If X is not
4872 an AND, but XEXP (X, 0) is, use it as our split point. */
4873 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4874 return &XEXP (x
, 0);
4876 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4882 /* Otherwise, we don't have a split point. */
4887 /* Throughout X, replace FROM with TO, and return the result.
4888 The result is TO if X is FROM;
4889 otherwise the result is X, but its contents may have been modified.
4890 If they were modified, a record was made in undobuf so that
4891 undo_all will (among other things) return X to its original state.
4893 If the number of changes necessary is too much to record to undo,
4894 the excess changes are not made, so the result is invalid.
4895 The changes already made can still be undone.
4896 undobuf.num_undo is incremented for such changes, so by testing that
4897 the caller can tell whether the result is valid.
4899 `n_occurrences' is incremented each time FROM is replaced.
4901 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4903 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4904 by copying if `n_occurrences' is nonzero. */
4907 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4909 enum rtx_code code
= GET_CODE (x
);
4910 enum machine_mode op0_mode
= VOIDmode
;
4915 /* Two expressions are equal if they are identical copies of a shared
4916 RTX or if they are both registers with the same register number
4919 #define COMBINE_RTX_EQUAL_P(X,Y) \
4921 || (REG_P (X) && REG_P (Y) \
4922 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4924 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4927 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4930 /* If X and FROM are the same register but different modes, they
4931 will not have been seen as equal above. However, the log links code
4932 will make a LOG_LINKS entry for that case. If we do nothing, we
4933 will try to rerecognize our original insn and, when it succeeds,
4934 we will delete the feeding insn, which is incorrect.
4936 So force this insn not to match in this (rare) case. */
4937 if (! in_dest
&& code
== REG
&& REG_P (from
)
4938 && reg_overlap_mentioned_p (x
, from
))
4939 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4941 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4942 of which may contain things that can be combined. */
4943 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4946 /* It is possible to have a subexpression appear twice in the insn.
4947 Suppose that FROM is a register that appears within TO.
4948 Then, after that subexpression has been scanned once by `subst',
4949 the second time it is scanned, TO may be found. If we were
4950 to scan TO here, we would find FROM within it and create a
4951 self-referent rtl structure which is completely wrong. */
4952 if (COMBINE_RTX_EQUAL_P (x
, to
))
4955 /* Parallel asm_operands need special attention because all of the
4956 inputs are shared across the arms. Furthermore, unsharing the
4957 rtl results in recognition failures. Failure to handle this case
4958 specially can result in circular rtl.
4960 Solve this by doing a normal pass across the first entry of the
4961 parallel, and only processing the SET_DESTs of the subsequent
4964 if (code
== PARALLEL
4965 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4966 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4968 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4970 /* If this substitution failed, this whole thing fails. */
4971 if (GET_CODE (new_rtx
) == CLOBBER
4972 && XEXP (new_rtx
, 0) == const0_rtx
)
4975 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4977 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4979 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4982 && GET_CODE (dest
) != CC0
4983 && GET_CODE (dest
) != PC
)
4985 new_rtx
= subst (dest
, from
, to
, 0, unique_copy
);
4987 /* If this substitution failed, this whole thing fails. */
4988 if (GET_CODE (new_rtx
) == CLOBBER
4989 && XEXP (new_rtx
, 0) == const0_rtx
)
4992 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4998 len
= GET_RTX_LENGTH (code
);
4999 fmt
= GET_RTX_FORMAT (code
);
5001 /* We don't need to process a SET_DEST that is a register, CC0,
5002 or PC, so set up to skip this common case. All other cases
5003 where we want to suppress replacing something inside a
5004 SET_SRC are handled via the IN_DEST operand. */
5006 && (REG_P (SET_DEST (x
))
5007 || GET_CODE (SET_DEST (x
)) == CC0
5008 || GET_CODE (SET_DEST (x
)) == PC
))
5011 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5014 op0_mode
= GET_MODE (XEXP (x
, 0));
5016 for (i
= 0; i
< len
; i
++)
5021 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5023 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5025 new_rtx
= (unique_copy
&& n_occurrences
5026 ? copy_rtx (to
) : to
);
5031 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0,
5034 /* If this substitution failed, this whole thing
5036 if (GET_CODE (new_rtx
) == CLOBBER
5037 && XEXP (new_rtx
, 0) == const0_rtx
)
5041 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5044 else if (fmt
[i
] == 'e')
5046 /* If this is a register being set, ignore it. */
5047 new_rtx
= XEXP (x
, i
);
5050 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5052 || code
== STRICT_LOW_PART
))
5055 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5057 /* In general, don't install a subreg involving two
5058 modes not tieable. It can worsen register
5059 allocation, and can even make invalid reload
5060 insns, since the reg inside may need to be copied
5061 from in the outside mode, and that may be invalid
5062 if it is an fp reg copied in integer mode.
5064 We allow two exceptions to this: It is valid if
5065 it is inside another SUBREG and the mode of that
5066 SUBREG and the mode of the inside of TO is
5067 tieable and it is valid if X is a SET that copies
5070 if (GET_CODE (to
) == SUBREG
5071 && ! MODES_TIEABLE_P (GET_MODE (to
),
5072 GET_MODE (SUBREG_REG (to
)))
5073 && ! (code
== SUBREG
5074 && MODES_TIEABLE_P (GET_MODE (x
),
5075 GET_MODE (SUBREG_REG (to
))))
5077 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5080 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5082 #ifdef CANNOT_CHANGE_MODE_CLASS
5085 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5086 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5089 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5092 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5096 /* If we are in a SET_DEST, suppress most cases unless we
5097 have gone inside a MEM, in which case we want to
5098 simplify the address. We assume here that things that
5099 are actually part of the destination have their inner
5100 parts in the first expression. This is true for SUBREG,
5101 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5102 things aside from REG and MEM that should appear in a
5104 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5106 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5107 || code
== ZERO_EXTRACT
))
5109 && i
== 0), unique_copy
);
5111 /* If we found that we will have to reject this combination,
5112 indicate that by returning the CLOBBER ourselves, rather than
5113 an expression containing it. This will speed things up as
5114 well as prevent accidents where two CLOBBERs are considered
5115 to be equal, thus producing an incorrect simplification. */
5117 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5120 if (GET_CODE (x
) == SUBREG
5121 && (CONST_INT_P (new_rtx
)
5122 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
5124 enum machine_mode mode
= GET_MODE (x
);
5126 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5127 GET_MODE (SUBREG_REG (x
)),
5130 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5132 else if (CONST_INT_P (new_rtx
)
5133 && GET_CODE (x
) == ZERO_EXTEND
)
5135 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5136 new_rtx
, GET_MODE (XEXP (x
, 0)));
5140 SUBST (XEXP (x
, i
), new_rtx
);
5145 /* Check if we are loading something from the constant pool via float
5146 extension; in this case we would undo compress_float_constant
5147 optimization and degenerate constant load to an immediate value. */
5148 if (GET_CODE (x
) == FLOAT_EXTEND
5149 && MEM_P (XEXP (x
, 0))
5150 && MEM_READONLY_P (XEXP (x
, 0)))
5152 rtx tmp
= avoid_constant_pool_reference (x
);
5157 /* Try to simplify X. If the simplification changed the code, it is likely
5158 that further simplification will help, so loop, but limit the number
5159 of repetitions that will be performed. */
5161 for (i
= 0; i
< 4; i
++)
5163 /* If X is sufficiently simple, don't bother trying to do anything
5165 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5166 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
5168 if (GET_CODE (x
) == code
)
5171 code
= GET_CODE (x
);
5173 /* We no longer know the original mode of operand 0 since we
5174 have changed the form of X) */
5175 op0_mode
= VOIDmode
;
5181 /* Simplify X, a piece of RTL. We just operate on the expression at the
5182 outer level; call `subst' to simplify recursively. Return the new
5185 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5186 if we are inside a SET_DEST. */
5189 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
5191 enum rtx_code code
= GET_CODE (x
);
5192 enum machine_mode mode
= GET_MODE (x
);
5196 /* If this is a commutative operation, put a constant last and a complex
5197 expression first. We don't need to do this for comparisons here. */
5198 if (COMMUTATIVE_ARITH_P (x
)
5199 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5202 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5203 SUBST (XEXP (x
, 1), temp
);
5206 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5207 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5208 things. Check for cases where both arms are testing the same
5211 Don't do anything if all operands are very simple. */
5214 && ((!OBJECT_P (XEXP (x
, 0))
5215 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5216 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5217 || (!OBJECT_P (XEXP (x
, 1))
5218 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5219 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5221 && (!OBJECT_P (XEXP (x
, 0))
5222 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5223 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5225 rtx cond
, true_rtx
, false_rtx
;
5227 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5229 /* If everything is a comparison, what we have is highly unlikely
5230 to be simpler, so don't use it. */
5231 && ! (COMPARISON_P (x
)
5232 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5234 rtx cop1
= const0_rtx
;
5235 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5237 if (cond_code
== NE
&& COMPARISON_P (cond
))
5240 /* Simplify the alternative arms; this may collapse the true and
5241 false arms to store-flag values. Be careful to use copy_rtx
5242 here since true_rtx or false_rtx might share RTL with x as a
5243 result of the if_then_else_cond call above. */
5244 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5245 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5247 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5248 is unlikely to be simpler. */
5249 if (general_operand (true_rtx
, VOIDmode
)
5250 && general_operand (false_rtx
, VOIDmode
))
5252 enum rtx_code reversed
;
5254 /* Restarting if we generate a store-flag expression will cause
5255 us to loop. Just drop through in this case. */
5257 /* If the result values are STORE_FLAG_VALUE and zero, we can
5258 just make the comparison operation. */
5259 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5260 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5262 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5263 && ((reversed
= reversed_comparison_code_parts
5264 (cond_code
, cond
, cop1
, NULL
))
5266 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5269 /* Likewise, we can make the negate of a comparison operation
5270 if the result values are - STORE_FLAG_VALUE and zero. */
5271 else if (CONST_INT_P (true_rtx
)
5272 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5273 && false_rtx
== const0_rtx
)
5274 x
= simplify_gen_unary (NEG
, mode
,
5275 simplify_gen_relational (cond_code
,
5279 else if (CONST_INT_P (false_rtx
)
5280 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5281 && true_rtx
== const0_rtx
5282 && ((reversed
= reversed_comparison_code_parts
5283 (cond_code
, cond
, cop1
, NULL
))
5285 x
= simplify_gen_unary (NEG
, mode
,
5286 simplify_gen_relational (reversed
,
5291 return gen_rtx_IF_THEN_ELSE (mode
,
5292 simplify_gen_relational (cond_code
,
5297 true_rtx
, false_rtx
);
5299 code
= GET_CODE (x
);
5300 op0_mode
= VOIDmode
;
5305 /* Try to fold this expression in case we have constants that weren't
5308 switch (GET_RTX_CLASS (code
))
5311 if (op0_mode
== VOIDmode
)
5312 op0_mode
= GET_MODE (XEXP (x
, 0));
5313 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5316 case RTX_COMM_COMPARE
:
5318 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5319 if (cmp_mode
== VOIDmode
)
5321 cmp_mode
= GET_MODE (XEXP (x
, 1));
5322 if (cmp_mode
== VOIDmode
)
5323 cmp_mode
= op0_mode
;
5325 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5326 XEXP (x
, 0), XEXP (x
, 1));
5329 case RTX_COMM_ARITH
:
5331 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5333 case RTX_BITFIELD_OPS
:
5335 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5336 XEXP (x
, 1), XEXP (x
, 2));
5345 code
= GET_CODE (temp
);
5346 op0_mode
= VOIDmode
;
5347 mode
= GET_MODE (temp
);
5350 /* First see if we can apply the inverse distributive law. */
5351 if (code
== PLUS
|| code
== MINUS
5352 || code
== AND
|| code
== IOR
|| code
== XOR
)
5354 x
= apply_distributive_law (x
);
5355 code
= GET_CODE (x
);
5356 op0_mode
= VOIDmode
;
5359 /* If CODE is an associative operation not otherwise handled, see if we
5360 can associate some operands. This can win if they are constants or
5361 if they are logically related (i.e. (a & b) & a). */
5362 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5363 || code
== AND
|| code
== IOR
|| code
== XOR
5364 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5365 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5366 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5368 if (GET_CODE (XEXP (x
, 0)) == code
)
5370 rtx other
= XEXP (XEXP (x
, 0), 0);
5371 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5372 rtx inner_op1
= XEXP (x
, 1);
5375 /* Make sure we pass the constant operand if any as the second
5376 one if this is a commutative operation. */
5377 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5379 rtx tem
= inner_op0
;
5380 inner_op0
= inner_op1
;
5383 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5384 : code
== DIV
? MULT
5386 mode
, inner_op0
, inner_op1
);
5388 /* For commutative operations, try the other pair if that one
5390 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5392 other
= XEXP (XEXP (x
, 0), 1);
5393 inner
= simplify_binary_operation (code
, mode
,
5394 XEXP (XEXP (x
, 0), 0),
5399 return simplify_gen_binary (code
, mode
, other
, inner
);
5403 /* A little bit of algebraic simplification here. */
5407 /* Ensure that our address has any ASHIFTs converted to MULT in case
5408 address-recognizing predicates are called later. */
5409 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5410 SUBST (XEXP (x
, 0), temp
);
5414 if (op0_mode
== VOIDmode
)
5415 op0_mode
= GET_MODE (SUBREG_REG (x
));
5417 /* See if this can be moved to simplify_subreg. */
5418 if (CONSTANT_P (SUBREG_REG (x
))
5419 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5420 /* Don't call gen_lowpart if the inner mode
5421 is VOIDmode and we cannot simplify it, as SUBREG without
5422 inner mode is invalid. */
5423 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5424 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5425 return gen_lowpart (mode
, SUBREG_REG (x
));
5427 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5431 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5437 /* Don't change the mode of the MEM if that would change the meaning
5439 if (MEM_P (SUBREG_REG (x
))
5440 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5441 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5442 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5444 /* Note that we cannot do any narrowing for non-constants since
5445 we might have been counting on using the fact that some bits were
5446 zero. We now do this in the SET. */
5451 temp
= expand_compound_operation (XEXP (x
, 0));
5453 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5454 replaced by (lshiftrt X C). This will convert
5455 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5457 if (GET_CODE (temp
) == ASHIFTRT
5458 && CONST_INT_P (XEXP (temp
, 1))
5459 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5460 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5461 INTVAL (XEXP (temp
, 1)));
5463 /* If X has only a single bit that might be nonzero, say, bit I, convert
5464 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5465 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5466 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5467 or a SUBREG of one since we'd be making the expression more
5468 complex if it was just a register. */
5471 && ! (GET_CODE (temp
) == SUBREG
5472 && REG_P (SUBREG_REG (temp
)))
5473 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5475 rtx temp1
= simplify_shift_const
5476 (NULL_RTX
, ASHIFTRT
, mode
,
5477 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5478 GET_MODE_BITSIZE (mode
) - 1 - i
),
5479 GET_MODE_BITSIZE (mode
) - 1 - i
);
5481 /* If all we did was surround TEMP with the two shifts, we
5482 haven't improved anything, so don't use it. Otherwise,
5483 we are better off with TEMP1. */
5484 if (GET_CODE (temp1
) != ASHIFTRT
5485 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5486 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5492 /* We can't handle truncation to a partial integer mode here
5493 because we don't know the real bitsize of the partial
5495 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5498 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5500 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5501 GET_MODE_MASK (mode
), 0));
5503 /* We can truncate a constant value and return it. */
5504 if (CONST_INT_P (XEXP (x
, 0)))
5505 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5507 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5508 whose value is a comparison can be replaced with a subreg if
5509 STORE_FLAG_VALUE permits. */
5510 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5511 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5512 && (temp
= get_last_value (XEXP (x
, 0)))
5513 && COMPARISON_P (temp
))
5514 return gen_lowpart (mode
, XEXP (x
, 0));
5518 /* (const (const X)) can become (const X). Do it this way rather than
5519 returning the inner CONST since CONST can be shared with a
5521 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5522 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5527 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5528 can add in an offset. find_split_point will split this address up
5529 again if it doesn't match. */
5530 if (GET_CODE (XEXP (x
, 0)) == HIGH
5531 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5537 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5538 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5539 bit-field and can be replaced by either a sign_extend or a
5540 sign_extract. The `and' may be a zero_extend and the two
5541 <c>, -<c> constants may be reversed. */
5542 if (GET_CODE (XEXP (x
, 0)) == XOR
5543 && CONST_INT_P (XEXP (x
, 1))
5544 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5545 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5546 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5547 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5548 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5549 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5550 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5551 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5552 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5553 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5554 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5555 == (unsigned int) i
+ 1))))
5556 return simplify_shift_const
5557 (NULL_RTX
, ASHIFTRT
, mode
,
5558 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5559 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5560 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
5561 GET_MODE_BITSIZE (mode
) - (i
+ 1));
5563 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5564 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5565 the bitsize of the mode - 1. This allows simplification of
5566 "a = (b & 8) == 0;" */
5567 if (XEXP (x
, 1) == constm1_rtx
5568 && !REG_P (XEXP (x
, 0))
5569 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5570 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5571 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5572 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5573 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5574 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5575 GET_MODE_BITSIZE (mode
) - 1),
5576 GET_MODE_BITSIZE (mode
) - 1);
5578 /* If we are adding two things that have no bits in common, convert
5579 the addition into an IOR. This will often be further simplified,
5580 for example in cases like ((a & 1) + (a & 2)), which can
5583 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5584 && (nonzero_bits (XEXP (x
, 0), mode
)
5585 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5587 /* Try to simplify the expression further. */
5588 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5589 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
5591 /* If we could, great. If not, do not go ahead with the IOR
5592 replacement, since PLUS appears in many special purpose
5593 address arithmetic instructions. */
5594 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
5600 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5601 (and <foo> (const_int pow2-1)) */
5602 if (GET_CODE (XEXP (x
, 1)) == AND
5603 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5604 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5605 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5606 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5607 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5611 /* If we have (mult (plus A B) C), apply the distributive law and then
5612 the inverse distributive law to see if things simplify. This
5613 occurs mostly in addresses, often when unrolling loops. */
5615 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5617 rtx result
= distribute_and_simplify_rtx (x
, 0);
5622 /* Try simplify a*(b/c) as (a*b)/c. */
5623 if (FLOAT_MODE_P (mode
) && flag_associative_math
5624 && GET_CODE (XEXP (x
, 0)) == DIV
)
5626 rtx tem
= simplify_binary_operation (MULT
, mode
,
5627 XEXP (XEXP (x
, 0), 0),
5630 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5635 /* If this is a divide by a power of two, treat it as a shift if
5636 its first operand is a shift. */
5637 if (CONST_INT_P (XEXP (x
, 1))
5638 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5639 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5640 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5641 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5642 || GET_CODE (XEXP (x
, 0)) == ROTATE
5643 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5644 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5648 case GT
: case GTU
: case GE
: case GEU
:
5649 case LT
: case LTU
: case LE
: case LEU
:
5650 case UNEQ
: case LTGT
:
5651 case UNGT
: case UNGE
:
5652 case UNLT
: case UNLE
:
5653 case UNORDERED
: case ORDERED
:
5654 /* If the first operand is a condition code, we can't do anything
5656 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5657 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5658 && ! CC0_P (XEXP (x
, 0))))
5660 rtx op0
= XEXP (x
, 0);
5661 rtx op1
= XEXP (x
, 1);
5662 enum rtx_code new_code
;
5664 if (GET_CODE (op0
) == COMPARE
)
5665 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5667 /* Simplify our comparison, if possible. */
5668 new_code
= simplify_comparison (code
, &op0
, &op1
);
5670 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5671 if only the low-order bit is possibly nonzero in X (such as when
5672 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5673 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5674 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5677 Remove any ZERO_EXTRACT we made when thinking this was a
5678 comparison. It may now be simpler to use, e.g., an AND. If a
5679 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5680 the call to make_compound_operation in the SET case. */
5682 if (STORE_FLAG_VALUE
== 1
5683 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5684 && op1
== const0_rtx
5685 && mode
== GET_MODE (op0
)
5686 && nonzero_bits (op0
, mode
) == 1)
5687 return gen_lowpart (mode
,
5688 expand_compound_operation (op0
));
5690 else if (STORE_FLAG_VALUE
== 1
5691 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5692 && op1
== const0_rtx
5693 && mode
== GET_MODE (op0
)
5694 && (num_sign_bit_copies (op0
, mode
)
5695 == GET_MODE_BITSIZE (mode
)))
5697 op0
= expand_compound_operation (op0
);
5698 return simplify_gen_unary (NEG
, mode
,
5699 gen_lowpart (mode
, op0
),
5703 else if (STORE_FLAG_VALUE
== 1
5704 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5705 && op1
== const0_rtx
5706 && mode
== GET_MODE (op0
)
5707 && nonzero_bits (op0
, mode
) == 1)
5709 op0
= expand_compound_operation (op0
);
5710 return simplify_gen_binary (XOR
, mode
,
5711 gen_lowpart (mode
, op0
),
5715 else if (STORE_FLAG_VALUE
== 1
5716 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5717 && op1
== const0_rtx
5718 && mode
== GET_MODE (op0
)
5719 && (num_sign_bit_copies (op0
, mode
)
5720 == GET_MODE_BITSIZE (mode
)))
5722 op0
= expand_compound_operation (op0
);
5723 return plus_constant (gen_lowpart (mode
, op0
), 1);
5726 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5728 if (STORE_FLAG_VALUE
== -1
5729 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5730 && op1
== const0_rtx
5731 && (num_sign_bit_copies (op0
, mode
)
5732 == GET_MODE_BITSIZE (mode
)))
5733 return gen_lowpart (mode
,
5734 expand_compound_operation (op0
));
5736 else if (STORE_FLAG_VALUE
== -1
5737 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5738 && op1
== const0_rtx
5739 && mode
== GET_MODE (op0
)
5740 && nonzero_bits (op0
, mode
) == 1)
5742 op0
= expand_compound_operation (op0
);
5743 return simplify_gen_unary (NEG
, mode
,
5744 gen_lowpart (mode
, op0
),
5748 else if (STORE_FLAG_VALUE
== -1
5749 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5750 && op1
== const0_rtx
5751 && mode
== GET_MODE (op0
)
5752 && (num_sign_bit_copies (op0
, mode
)
5753 == GET_MODE_BITSIZE (mode
)))
5755 op0
= expand_compound_operation (op0
);
5756 return simplify_gen_unary (NOT
, mode
,
5757 gen_lowpart (mode
, op0
),
5761 /* If X is 0/1, (eq X 0) is X-1. */
5762 else if (STORE_FLAG_VALUE
== -1
5763 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5764 && op1
== const0_rtx
5765 && mode
== GET_MODE (op0
)
5766 && nonzero_bits (op0
, mode
) == 1)
5768 op0
= expand_compound_operation (op0
);
5769 return plus_constant (gen_lowpart (mode
, op0
), -1);
5772 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5773 one bit that might be nonzero, we can convert (ne x 0) to
5774 (ashift x c) where C puts the bit in the sign bit. Remove any
5775 AND with STORE_FLAG_VALUE when we are done, since we are only
5776 going to test the sign bit. */
5777 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5778 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5779 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5780 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5781 && op1
== const0_rtx
5782 && mode
== GET_MODE (op0
)
5783 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5785 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5786 expand_compound_operation (op0
),
5787 GET_MODE_BITSIZE (mode
) - 1 - i
);
5788 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5794 /* If the code changed, return a whole new comparison. */
5795 if (new_code
!= code
)
5796 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5798 /* Otherwise, keep this operation, but maybe change its operands.
5799 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5800 SUBST (XEXP (x
, 0), op0
);
5801 SUBST (XEXP (x
, 1), op1
);
5806 return simplify_if_then_else (x
);
5812 /* If we are processing SET_DEST, we are done. */
5816 return expand_compound_operation (x
);
5819 return simplify_set (x
);
5823 return simplify_logical (x
);
5830 /* If this is a shift by a constant amount, simplify it. */
5831 if (CONST_INT_P (XEXP (x
, 1)))
5832 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5833 INTVAL (XEXP (x
, 1)));
5835 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5837 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5838 ((unsigned HOST_WIDE_INT
) 1
5839 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5851 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5854 simplify_if_then_else (rtx x
)
5856 enum machine_mode mode
= GET_MODE (x
);
5857 rtx cond
= XEXP (x
, 0);
5858 rtx true_rtx
= XEXP (x
, 1);
5859 rtx false_rtx
= XEXP (x
, 2);
5860 enum rtx_code true_code
= GET_CODE (cond
);
5861 int comparison_p
= COMPARISON_P (cond
);
5864 enum rtx_code false_code
;
5867 /* Simplify storing of the truth value. */
5868 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5869 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5870 XEXP (cond
, 0), XEXP (cond
, 1));
5872 /* Also when the truth value has to be reversed. */
5874 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5875 && (reversed
= reversed_comparison (cond
, mode
)))
5878 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5879 in it is being compared against certain values. Get the true and false
5880 comparisons and see if that says anything about the value of each arm. */
5883 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5885 && REG_P (XEXP (cond
, 0)))
5888 rtx from
= XEXP (cond
, 0);
5889 rtx true_val
= XEXP (cond
, 1);
5890 rtx false_val
= true_val
;
5893 /* If FALSE_CODE is EQ, swap the codes and arms. */
5895 if (false_code
== EQ
)
5897 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5898 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5901 /* If we are comparing against zero and the expression being tested has
5902 only a single bit that might be nonzero, that is its value when it is
5903 not equal to zero. Similarly if it is known to be -1 or 0. */
5905 if (true_code
== EQ
&& true_val
== const0_rtx
5906 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5909 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5911 else if (true_code
== EQ
&& true_val
== const0_rtx
5912 && (num_sign_bit_copies (from
, GET_MODE (from
))
5913 == GET_MODE_BITSIZE (GET_MODE (from
))))
5916 false_val
= constm1_rtx
;
5919 /* Now simplify an arm if we know the value of the register in the
5920 branch and it is used in the arm. Be careful due to the potential
5921 of locally-shared RTL. */
5923 if (reg_mentioned_p (from
, true_rtx
))
5924 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5926 pc_rtx
, pc_rtx
, 0, 0);
5927 if (reg_mentioned_p (from
, false_rtx
))
5928 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5930 pc_rtx
, pc_rtx
, 0, 0);
5932 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5933 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5935 true_rtx
= XEXP (x
, 1);
5936 false_rtx
= XEXP (x
, 2);
5937 true_code
= GET_CODE (cond
);
5940 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5941 reversed, do so to avoid needing two sets of patterns for
5942 subtract-and-branch insns. Similarly if we have a constant in the true
5943 arm, the false arm is the same as the first operand of the comparison, or
5944 the false arm is more complicated than the true arm. */
5947 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5948 && (true_rtx
== pc_rtx
5949 || (CONSTANT_P (true_rtx
)
5950 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5951 || true_rtx
== const0_rtx
5952 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5953 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5954 && !OBJECT_P (false_rtx
))
5955 || reg_mentioned_p (true_rtx
, false_rtx
)
5956 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5958 true_code
= reversed_comparison_code (cond
, NULL
);
5959 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5960 SUBST (XEXP (x
, 1), false_rtx
);
5961 SUBST (XEXP (x
, 2), true_rtx
);
5963 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5966 /* It is possible that the conditional has been simplified out. */
5967 true_code
= GET_CODE (cond
);
5968 comparison_p
= COMPARISON_P (cond
);
5971 /* If the two arms are identical, we don't need the comparison. */
5973 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5976 /* Convert a == b ? b : a to "a". */
5977 if (true_code
== EQ
&& ! side_effects_p (cond
)
5978 && !HONOR_NANS (mode
)
5979 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5980 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5982 else if (true_code
== NE
&& ! side_effects_p (cond
)
5983 && !HONOR_NANS (mode
)
5984 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5985 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5988 /* Look for cases where we have (abs x) or (neg (abs X)). */
5990 if (GET_MODE_CLASS (mode
) == MODE_INT
5992 && XEXP (cond
, 1) == const0_rtx
5993 && GET_CODE (false_rtx
) == NEG
5994 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5995 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5996 && ! side_effects_p (true_rtx
))
6001 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6005 simplify_gen_unary (NEG
, mode
,
6006 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6012 /* Look for MIN or MAX. */
6014 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6016 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6017 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6018 && ! side_effects_p (cond
))
6023 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6026 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6029 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6032 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6037 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6038 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6039 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6040 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6041 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6042 neither 1 or -1, but it isn't worth checking for. */
6044 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6046 && GET_MODE_CLASS (mode
) == MODE_INT
6047 && ! side_effects_p (x
))
6049 rtx t
= make_compound_operation (true_rtx
, SET
);
6050 rtx f
= make_compound_operation (false_rtx
, SET
);
6051 rtx cond_op0
= XEXP (cond
, 0);
6052 rtx cond_op1
= XEXP (cond
, 1);
6053 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6054 enum machine_mode m
= mode
;
6055 rtx z
= 0, c1
= NULL_RTX
;
6057 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6058 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6059 || GET_CODE (t
) == ASHIFT
6060 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6061 && rtx_equal_p (XEXP (t
, 0), f
))
6062 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6064 /* If an identity-zero op is commutative, check whether there
6065 would be a match if we swapped the operands. */
6066 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6067 || GET_CODE (t
) == XOR
)
6068 && rtx_equal_p (XEXP (t
, 1), f
))
6069 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6070 else if (GET_CODE (t
) == SIGN_EXTEND
6071 && (GET_CODE (XEXP (t
, 0)) == PLUS
6072 || GET_CODE (XEXP (t
, 0)) == MINUS
6073 || GET_CODE (XEXP (t
, 0)) == IOR
6074 || GET_CODE (XEXP (t
, 0)) == XOR
6075 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6076 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6077 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6078 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6079 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6080 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6081 && (num_sign_bit_copies (f
, GET_MODE (f
))
6083 (GET_MODE_BITSIZE (mode
)
6084 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6086 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6087 extend_op
= SIGN_EXTEND
;
6088 m
= GET_MODE (XEXP (t
, 0));
6090 else if (GET_CODE (t
) == SIGN_EXTEND
6091 && (GET_CODE (XEXP (t
, 0)) == PLUS
6092 || GET_CODE (XEXP (t
, 0)) == IOR
6093 || GET_CODE (XEXP (t
, 0)) == XOR
)
6094 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6095 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6096 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6097 && (num_sign_bit_copies (f
, GET_MODE (f
))
6099 (GET_MODE_BITSIZE (mode
)
6100 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6102 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6103 extend_op
= SIGN_EXTEND
;
6104 m
= GET_MODE (XEXP (t
, 0));
6106 else if (GET_CODE (t
) == ZERO_EXTEND
6107 && (GET_CODE (XEXP (t
, 0)) == PLUS
6108 || GET_CODE (XEXP (t
, 0)) == MINUS
6109 || GET_CODE (XEXP (t
, 0)) == IOR
6110 || GET_CODE (XEXP (t
, 0)) == XOR
6111 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6112 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6113 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6114 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6115 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6116 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6117 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6118 && ((nonzero_bits (f
, GET_MODE (f
))
6119 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6122 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6123 extend_op
= ZERO_EXTEND
;
6124 m
= GET_MODE (XEXP (t
, 0));
6126 else if (GET_CODE (t
) == ZERO_EXTEND
6127 && (GET_CODE (XEXP (t
, 0)) == PLUS
6128 || GET_CODE (XEXP (t
, 0)) == IOR
6129 || GET_CODE (XEXP (t
, 0)) == XOR
)
6130 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6131 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6132 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6133 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6134 && ((nonzero_bits (f
, GET_MODE (f
))
6135 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6138 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6139 extend_op
= ZERO_EXTEND
;
6140 m
= GET_MODE (XEXP (t
, 0));
6145 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6146 cond_op0
, cond_op1
),
6147 pc_rtx
, pc_rtx
, 0, 0);
6148 temp
= simplify_gen_binary (MULT
, m
, temp
,
6149 simplify_gen_binary (MULT
, m
, c1
,
6151 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
6152 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6154 if (extend_op
!= UNKNOWN
)
6155 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6161 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6162 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6163 negation of a single bit, we can convert this operation to a shift. We
6164 can actually do this more generally, but it doesn't seem worth it. */
6166 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6167 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6168 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6169 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6170 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6171 == GET_MODE_BITSIZE (mode
))
6172 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6174 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6175 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6177 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6178 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6179 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6180 && GET_MODE (XEXP (cond
, 0)) == mode
6181 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6182 == nonzero_bits (XEXP (cond
, 0), mode
)
6183 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6184 return XEXP (cond
, 0);
6189 /* Simplify X, a SET expression. Return the new expression. */
6192 simplify_set (rtx x
)
6194 rtx src
= SET_SRC (x
);
6195 rtx dest
= SET_DEST (x
);
6196 enum machine_mode mode
6197 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6201 /* (set (pc) (return)) gets written as (return). */
6202 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
6205 /* Now that we know for sure which bits of SRC we are using, see if we can
6206 simplify the expression for the object knowing that we only need the
6209 if (GET_MODE_CLASS (mode
) == MODE_INT
6210 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
6212 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6213 SUBST (SET_SRC (x
), src
);
6216 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6217 the comparison result and try to simplify it unless we already have used
6218 undobuf.other_insn. */
6219 if ((GET_MODE_CLASS (mode
) == MODE_CC
6220 || GET_CODE (src
) == COMPARE
6222 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6223 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6224 && COMPARISON_P (*cc_use
)
6225 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6227 enum rtx_code old_code
= GET_CODE (*cc_use
);
6228 enum rtx_code new_code
;
6230 int other_changed
= 0;
6231 enum machine_mode compare_mode
= GET_MODE (dest
);
6233 if (GET_CODE (src
) == COMPARE
)
6234 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6236 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6238 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6241 new_code
= old_code
;
6242 else if (!CONSTANT_P (tmp
))
6244 new_code
= GET_CODE (tmp
);
6245 op0
= XEXP (tmp
, 0);
6246 op1
= XEXP (tmp
, 1);
6250 rtx pat
= PATTERN (other_insn
);
6251 undobuf
.other_insn
= other_insn
;
6252 SUBST (*cc_use
, tmp
);
6254 /* Attempt to simplify CC user. */
6255 if (GET_CODE (pat
) == SET
)
6257 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6258 if (new_rtx
!= NULL_RTX
)
6259 SUBST (SET_SRC (pat
), new_rtx
);
6262 /* Convert X into a no-op move. */
6263 SUBST (SET_DEST (x
), pc_rtx
);
6264 SUBST (SET_SRC (x
), pc_rtx
);
6268 /* Simplify our comparison, if possible. */
6269 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6271 #ifdef SELECT_CC_MODE
6272 /* If this machine has CC modes other than CCmode, check to see if we
6273 need to use a different CC mode here. */
6274 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6275 compare_mode
= GET_MODE (op0
);
6277 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6280 /* If the mode changed, we have to change SET_DEST, the mode in the
6281 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6282 a hard register, just build new versions with the proper mode. If it
6283 is a pseudo, we lose unless it is only time we set the pseudo, in
6284 which case we can safely change its mode. */
6285 if (compare_mode
!= GET_MODE (dest
))
6287 if (can_change_dest_mode (dest
, 0, compare_mode
))
6289 unsigned int regno
= REGNO (dest
);
6292 if (regno
< FIRST_PSEUDO_REGISTER
)
6293 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6296 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6297 new_dest
= regno_reg_rtx
[regno
];
6300 SUBST (SET_DEST (x
), new_dest
);
6301 SUBST (XEXP (*cc_use
, 0), new_dest
);
6308 #endif /* SELECT_CC_MODE */
6310 /* If the code changed, we have to build a new comparison in
6311 undobuf.other_insn. */
6312 if (new_code
!= old_code
)
6314 int other_changed_previously
= other_changed
;
6315 unsigned HOST_WIDE_INT mask
;
6316 rtx old_cc_use
= *cc_use
;
6318 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6322 /* If the only change we made was to change an EQ into an NE or
6323 vice versa, OP0 has only one bit that might be nonzero, and OP1
6324 is zero, check if changing the user of the condition code will
6325 produce a valid insn. If it won't, we can keep the original code
6326 in that insn by surrounding our operation with an XOR. */
6328 if (((old_code
== NE
&& new_code
== EQ
)
6329 || (old_code
== EQ
&& new_code
== NE
))
6330 && ! other_changed_previously
&& op1
== const0_rtx
6331 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
6332 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6334 rtx pat
= PATTERN (other_insn
), note
= 0;
6336 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6337 && ! check_asm_operands (pat
)))
6339 *cc_use
= old_cc_use
;
6342 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6343 op0
, GEN_INT (mask
));
6349 undobuf
.other_insn
= other_insn
;
6351 /* Otherwise, if we didn't previously have a COMPARE in the
6352 correct mode, we need one. */
6353 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6355 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6358 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6360 SUBST (SET_SRC (x
), op0
);
6363 /* Otherwise, update the COMPARE if needed. */
6364 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6366 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6372 /* Get SET_SRC in a form where we have placed back any
6373 compound expressions. Then do the checks below. */
6374 src
= make_compound_operation (src
, SET
);
6375 SUBST (SET_SRC (x
), src
);
6378 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6379 and X being a REG or (subreg (reg)), we may be able to convert this to
6380 (set (subreg:m2 x) (op)).
6382 We can always do this if M1 is narrower than M2 because that means that
6383 we only care about the low bits of the result.
6385 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6386 perform a narrower operation than requested since the high-order bits will
6387 be undefined. On machine where it is defined, this transformation is safe
6388 as long as M1 and M2 have the same number of words. */
6390 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6391 && !OBJECT_P (SUBREG_REG (src
))
6392 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6394 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6395 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6396 #ifndef WORD_REGISTER_OPERATIONS
6397 && (GET_MODE_SIZE (GET_MODE (src
))
6398 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6400 #ifdef CANNOT_CHANGE_MODE_CLASS
6401 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6402 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6403 GET_MODE (SUBREG_REG (src
)),
6407 || (GET_CODE (dest
) == SUBREG
6408 && REG_P (SUBREG_REG (dest
)))))
6410 SUBST (SET_DEST (x
),
6411 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6413 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6415 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6419 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6422 && GET_CODE (src
) == SUBREG
6423 && subreg_lowpart_p (src
)
6424 && (GET_MODE_BITSIZE (GET_MODE (src
))
6425 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
6427 rtx inner
= SUBREG_REG (src
);
6428 enum machine_mode inner_mode
= GET_MODE (inner
);
6430 /* Here we make sure that we don't have a sign bit on. */
6431 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
6432 && (nonzero_bits (inner
, inner_mode
)
6433 < ((unsigned HOST_WIDE_INT
) 1
6434 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
6436 SUBST (SET_SRC (x
), inner
);
6442 #ifdef LOAD_EXTEND_OP
6443 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6444 would require a paradoxical subreg. Replace the subreg with a
6445 zero_extend to avoid the reload that would otherwise be required. */
6447 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6448 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6449 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6450 && SUBREG_BYTE (src
) == 0
6451 && (GET_MODE_SIZE (GET_MODE (src
))
6452 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6453 && MEM_P (SUBREG_REG (src
)))
6456 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6457 GET_MODE (src
), SUBREG_REG (src
)));
6463 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6464 are comparing an item known to be 0 or -1 against 0, use a logical
6465 operation instead. Check for one of the arms being an IOR of the other
6466 arm with some value. We compute three terms to be IOR'ed together. In
6467 practice, at most two will be nonzero. Then we do the IOR's. */
6469 if (GET_CODE (dest
) != PC
6470 && GET_CODE (src
) == IF_THEN_ELSE
6471 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6472 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6473 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6474 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6475 #ifdef HAVE_conditional_move
6476 && ! can_conditionally_move_p (GET_MODE (src
))
6478 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6479 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6480 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6481 && ! side_effects_p (src
))
6483 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6484 ? XEXP (src
, 1) : XEXP (src
, 2));
6485 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6486 ? XEXP (src
, 2) : XEXP (src
, 1));
6487 rtx term1
= const0_rtx
, term2
, term3
;
6489 if (GET_CODE (true_rtx
) == IOR
6490 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6491 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6492 else if (GET_CODE (true_rtx
) == IOR
6493 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6494 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6495 else if (GET_CODE (false_rtx
) == IOR
6496 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6497 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6498 else if (GET_CODE (false_rtx
) == IOR
6499 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6500 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6502 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6503 XEXP (XEXP (src
, 0), 0), true_rtx
);
6504 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6505 simplify_gen_unary (NOT
, GET_MODE (src
),
6506 XEXP (XEXP (src
, 0), 0),
6511 simplify_gen_binary (IOR
, GET_MODE (src
),
6512 simplify_gen_binary (IOR
, GET_MODE (src
),
6519 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6520 whole thing fail. */
6521 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6523 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6526 /* Convert this into a field assignment operation, if possible. */
6527 return make_field_assignment (x
);
6530 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6534 simplify_logical (rtx x
)
6536 enum machine_mode mode
= GET_MODE (x
);
6537 rtx op0
= XEXP (x
, 0);
6538 rtx op1
= XEXP (x
, 1);
6540 switch (GET_CODE (x
))
6543 /* We can call simplify_and_const_int only if we don't lose
6544 any (sign) bits when converting INTVAL (op1) to
6545 "unsigned HOST_WIDE_INT". */
6546 if (CONST_INT_P (op1
)
6547 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6548 || INTVAL (op1
) > 0))
6550 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6551 if (GET_CODE (x
) != AND
)
6558 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6559 apply the distributive law and then the inverse distributive
6560 law to see if things simplify. */
6561 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6563 rtx result
= distribute_and_simplify_rtx (x
, 0);
6567 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6569 rtx result
= distribute_and_simplify_rtx (x
, 1);
6576 /* If we have (ior (and A B) C), apply the distributive law and then
6577 the inverse distributive law to see if things simplify. */
6579 if (GET_CODE (op0
) == AND
)
6581 rtx result
= distribute_and_simplify_rtx (x
, 0);
6586 if (GET_CODE (op1
) == AND
)
6588 rtx result
= distribute_and_simplify_rtx (x
, 1);
6601 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6602 operations" because they can be replaced with two more basic operations.
6603 ZERO_EXTEND is also considered "compound" because it can be replaced with
6604 an AND operation, which is simpler, though only one operation.
6606 The function expand_compound_operation is called with an rtx expression
6607 and will convert it to the appropriate shifts and AND operations,
6608 simplifying at each stage.
6610 The function make_compound_operation is called to convert an expression
6611 consisting of shifts and ANDs into the equivalent compound expression.
6612 It is the inverse of this function, loosely speaking. */
6615 expand_compound_operation (rtx x
)
6617 unsigned HOST_WIDE_INT pos
= 0, len
;
6619 unsigned int modewidth
;
6622 switch (GET_CODE (x
))
6627 /* We can't necessarily use a const_int for a multiword mode;
6628 it depends on implicitly extending the value.
6629 Since we don't know the right way to extend it,
6630 we can't tell whether the implicit way is right.
6632 Even for a mode that is no wider than a const_int,
6633 we can't win, because we need to sign extend one of its bits through
6634 the rest of it, and we don't know which bit. */
6635 if (CONST_INT_P (XEXP (x
, 0)))
6638 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6639 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6640 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6641 reloaded. If not for that, MEM's would very rarely be safe.
6643 Reject MODEs bigger than a word, because we might not be able
6644 to reference a two-register group starting with an arbitrary register
6645 (and currently gen_lowpart might crash for a SUBREG). */
6647 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6650 /* Reject MODEs that aren't scalar integers because turning vector
6651 or complex modes into shifts causes problems. */
6653 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6656 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6657 /* If the inner object has VOIDmode (the only way this can happen
6658 is if it is an ASM_OPERANDS), we can't do anything since we don't
6659 know how much masking to do. */
6668 /* ... fall through ... */
6671 /* If the operand is a CLOBBER, just return it. */
6672 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6675 if (!CONST_INT_P (XEXP (x
, 1))
6676 || !CONST_INT_P (XEXP (x
, 2))
6677 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6680 /* Reject MODEs that aren't scalar integers because turning vector
6681 or complex modes into shifts causes problems. */
6683 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6686 len
= INTVAL (XEXP (x
, 1));
6687 pos
= INTVAL (XEXP (x
, 2));
6689 /* This should stay within the object being extracted, fail otherwise. */
6690 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6693 if (BITS_BIG_ENDIAN
)
6694 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6701 /* Convert sign extension to zero extension, if we know that the high
6702 bit is not set, as this is easier to optimize. It will be converted
6703 back to cheaper alternative in make_extraction. */
6704 if (GET_CODE (x
) == SIGN_EXTEND
6705 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6706 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6707 & ~(((unsigned HOST_WIDE_INT
)
6708 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6712 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6713 rtx temp2
= expand_compound_operation (temp
);
6715 /* Make sure this is a profitable operation. */
6716 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6717 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6719 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6720 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6726 /* We can optimize some special cases of ZERO_EXTEND. */
6727 if (GET_CODE (x
) == ZERO_EXTEND
)
6729 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6730 know that the last value didn't have any inappropriate bits
6732 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6733 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6734 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6735 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6736 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6737 return XEXP (XEXP (x
, 0), 0);
6739 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6740 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6741 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6742 && subreg_lowpart_p (XEXP (x
, 0))
6743 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6744 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6745 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6746 return SUBREG_REG (XEXP (x
, 0));
6748 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6749 is a comparison and STORE_FLAG_VALUE permits. This is like
6750 the first case, but it works even when GET_MODE (x) is larger
6751 than HOST_WIDE_INT. */
6752 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6753 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6754 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6755 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6756 <= HOST_BITS_PER_WIDE_INT
)
6757 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6758 return XEXP (XEXP (x
, 0), 0);
6760 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6761 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6762 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6763 && subreg_lowpart_p (XEXP (x
, 0))
6764 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6765 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6766 <= HOST_BITS_PER_WIDE_INT
)
6767 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6768 return SUBREG_REG (XEXP (x
, 0));
6772 /* If we reach here, we want to return a pair of shifts. The inner
6773 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6774 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6775 logical depending on the value of UNSIGNEDP.
6777 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6778 converted into an AND of a shift.
6780 We must check for the case where the left shift would have a negative
6781 count. This can happen in a case like (x >> 31) & 255 on machines
6782 that can't shift by a constant. On those machines, we would first
6783 combine the shift with the AND to produce a variable-position
6784 extraction. Then the constant of 31 would be substituted in
6785 to produce such a position. */
6787 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6788 if (modewidth
>= pos
+ len
)
6790 enum machine_mode mode
= GET_MODE (x
);
6791 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6792 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6794 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6795 tem
, modewidth
- pos
- len
);
6796 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6797 mode
, tem
, modewidth
- len
);
6799 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6800 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6801 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6804 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6806 /* Any other cases we can't handle. */
6809 /* If we couldn't do this for some reason, return the original
6811 if (GET_CODE (tem
) == CLOBBER
)
6817 /* X is a SET which contains an assignment of one object into
6818 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6819 or certain SUBREGS). If possible, convert it into a series of
6822 We half-heartedly support variable positions, but do not at all
6823 support variable lengths. */
6826 expand_field_assignment (const_rtx x
)
6829 rtx pos
; /* Always counts from low bit. */
6831 rtx mask
, cleared
, masked
;
6832 enum machine_mode compute_mode
;
6834 /* Loop until we find something we can't simplify. */
6837 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6838 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6840 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6841 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6842 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6844 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6845 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6847 inner
= XEXP (SET_DEST (x
), 0);
6848 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6849 pos
= XEXP (SET_DEST (x
), 2);
6851 /* A constant position should stay within the width of INNER. */
6852 if (CONST_INT_P (pos
)
6853 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6856 if (BITS_BIG_ENDIAN
)
6858 if (CONST_INT_P (pos
))
6859 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6861 else if (GET_CODE (pos
) == MINUS
6862 && CONST_INT_P (XEXP (pos
, 1))
6863 && (INTVAL (XEXP (pos
, 1))
6864 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6865 /* If position is ADJUST - X, new position is X. */
6866 pos
= XEXP (pos
, 0);
6868 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6869 GEN_INT (GET_MODE_BITSIZE (
6876 /* A SUBREG between two modes that occupy the same numbers of words
6877 can be done by moving the SUBREG to the source. */
6878 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6879 /* We need SUBREGs to compute nonzero_bits properly. */
6880 && nonzero_sign_valid
6881 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6882 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6883 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6884 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6886 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6888 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6895 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6896 inner
= SUBREG_REG (inner
);
6898 compute_mode
= GET_MODE (inner
);
6900 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6901 if (! SCALAR_INT_MODE_P (compute_mode
))
6903 enum machine_mode imode
;
6905 /* Don't do anything for vector or complex integral types. */
6906 if (! FLOAT_MODE_P (compute_mode
))
6909 /* Try to find an integral mode to pun with. */
6910 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6911 if (imode
== BLKmode
)
6914 compute_mode
= imode
;
6915 inner
= gen_lowpart (imode
, inner
);
6918 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6919 if (len
>= HOST_BITS_PER_WIDE_INT
)
6922 /* Now compute the equivalent expression. Make a copy of INNER
6923 for the SET_DEST in case it is a MEM into which we will substitute;
6924 we don't want shared RTL in that case. */
6925 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6926 cleared
= simplify_gen_binary (AND
, compute_mode
,
6927 simplify_gen_unary (NOT
, compute_mode
,
6928 simplify_gen_binary (ASHIFT
,
6933 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6934 simplify_gen_binary (
6936 gen_lowpart (compute_mode
, SET_SRC (x
)),
6940 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6941 simplify_gen_binary (IOR
, compute_mode
,
6948 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6949 it is an RTX that represents a variable starting position; otherwise,
6950 POS is the (constant) starting bit position (counted from the LSB).
6952 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6955 IN_DEST is nonzero if this is a reference in the destination of a
6956 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6957 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6960 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6961 ZERO_EXTRACT should be built even for bits starting at bit 0.
6963 MODE is the desired mode of the result (if IN_DEST == 0).
6965 The result is an RTX for the extraction or NULL_RTX if the target
6969 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6970 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6971 int in_dest
, int in_compare
)
6973 /* This mode describes the size of the storage area
6974 to fetch the overall value from. Within that, we
6975 ignore the POS lowest bits, etc. */
6976 enum machine_mode is_mode
= GET_MODE (inner
);
6977 enum machine_mode inner_mode
;
6978 enum machine_mode wanted_inner_mode
;
6979 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6980 enum machine_mode pos_mode
= word_mode
;
6981 enum machine_mode extraction_mode
= word_mode
;
6982 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6984 rtx orig_pos_rtx
= pos_rtx
;
6985 HOST_WIDE_INT orig_pos
;
6987 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6989 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6990 consider just the QI as the memory to extract from.
6991 The subreg adds or removes high bits; its mode is
6992 irrelevant to the meaning of this extraction,
6993 since POS and LEN count from the lsb. */
6994 if (MEM_P (SUBREG_REG (inner
)))
6995 is_mode
= GET_MODE (SUBREG_REG (inner
));
6996 inner
= SUBREG_REG (inner
);
6998 else if (GET_CODE (inner
) == ASHIFT
6999 && CONST_INT_P (XEXP (inner
, 1))
7000 && pos_rtx
== 0 && pos
== 0
7001 && len
> UINTVAL (XEXP (inner
, 1)))
7003 /* We're extracting the least significant bits of an rtx
7004 (ashift X (const_int C)), where LEN > C. Extract the
7005 least significant (LEN - C) bits of X, giving an rtx
7006 whose mode is MODE, then shift it left C times. */
7007 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7008 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7009 unsignedp
, in_dest
, in_compare
);
7011 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7014 inner_mode
= GET_MODE (inner
);
7016 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7017 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7019 /* See if this can be done without an extraction. We never can if the
7020 width of the field is not the same as that of some integer mode. For
7021 registers, we can only avoid the extraction if the position is at the
7022 low-order bit and this is either not in the destination or we have the
7023 appropriate STRICT_LOW_PART operation available.
7025 For MEM, we can avoid an extract if the field starts on an appropriate
7026 boundary and we can change the mode of the memory reference. */
7028 if (tmode
!= BLKmode
7029 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7031 && (inner_mode
== tmode
7033 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
7034 GET_MODE_BITSIZE (inner_mode
))
7035 || reg_truncated_to_mode (tmode
, inner
))
7038 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7039 || (MEM_P (inner
) && pos_rtx
== 0
7041 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7042 : BITS_PER_UNIT
)) == 0
7043 /* We can't do this if we are widening INNER_MODE (it
7044 may not be aligned, for one thing). */
7045 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
7046 && (inner_mode
== tmode
7047 || (! mode_dependent_address_p (XEXP (inner
, 0))
7048 && ! MEM_VOLATILE_P (inner
))))))
7050 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7051 field. If the original and current mode are the same, we need not
7052 adjust the offset. Otherwise, we do if bytes big endian.
7054 If INNER is not a MEM, get a piece consisting of just the field
7055 of interest (in this case POS % BITS_PER_WORD must be 0). */
7059 HOST_WIDE_INT offset
;
7061 /* POS counts from lsb, but make OFFSET count in memory order. */
7062 if (BYTES_BIG_ENDIAN
)
7063 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7065 offset
= pos
/ BITS_PER_UNIT
;
7067 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7069 else if (REG_P (inner
))
7071 if (tmode
!= inner_mode
)
7073 /* We can't call gen_lowpart in a DEST since we
7074 always want a SUBREG (see below) and it would sometimes
7075 return a new hard register. */
7078 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7080 if (WORDS_BIG_ENDIAN
7081 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7082 final_word
= ((GET_MODE_SIZE (inner_mode
)
7083 - GET_MODE_SIZE (tmode
))
7084 / UNITS_PER_WORD
) - final_word
;
7086 final_word
*= UNITS_PER_WORD
;
7087 if (BYTES_BIG_ENDIAN
&&
7088 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7089 final_word
+= (GET_MODE_SIZE (inner_mode
)
7090 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7092 /* Avoid creating invalid subregs, for example when
7093 simplifying (x>>32)&255. */
7094 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7097 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7100 new_rtx
= gen_lowpart (tmode
, inner
);
7106 new_rtx
= force_to_mode (inner
, tmode
,
7107 len
>= HOST_BITS_PER_WIDE_INT
7108 ? ~(unsigned HOST_WIDE_INT
) 0
7109 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7112 /* If this extraction is going into the destination of a SET,
7113 make a STRICT_LOW_PART unless we made a MEM. */
7116 return (MEM_P (new_rtx
) ? new_rtx
7117 : (GET_CODE (new_rtx
) != SUBREG
7118 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7119 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7124 if (CONST_INT_P (new_rtx
)
7125 || GET_CODE (new_rtx
) == CONST_DOUBLE
)
7126 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7127 mode
, new_rtx
, tmode
);
7129 /* If we know that no extraneous bits are set, and that the high
7130 bit is not set, convert the extraction to the cheaper of
7131 sign and zero extension, that are equivalent in these cases. */
7132 if (flag_expensive_optimizations
7133 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
7134 && ((nonzero_bits (new_rtx
, tmode
)
7135 & ~(((unsigned HOST_WIDE_INT
)
7136 GET_MODE_MASK (tmode
))
7140 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7141 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7143 /* Prefer ZERO_EXTENSION, since it gives more information to
7145 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
7146 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
7151 /* Otherwise, sign- or zero-extend unless we already are in the
7154 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7158 /* Unless this is a COMPARE or we have a funny memory reference,
7159 don't do anything with zero-extending field extracts starting at
7160 the low-order bit since they are simple AND operations. */
7161 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7162 && ! in_compare
&& unsignedp
)
7165 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7166 if the position is not a constant and the length is not 1. In all
7167 other cases, we would only be going outside our object in cases when
7168 an original shift would have been undefined. */
7170 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
7171 || (pos_rtx
!= 0 && len
!= 1)))
7174 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7175 and the mode for the result. */
7176 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7178 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7179 pos_mode
= mode_for_extraction (EP_insv
, 2);
7180 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7183 if (! in_dest
&& unsignedp
7184 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7186 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7187 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7188 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7191 if (! in_dest
&& ! unsignedp
7192 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7194 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7195 pos_mode
= mode_for_extraction (EP_extv
, 3);
7196 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7199 /* Never narrow an object, since that might not be safe. */
7201 if (mode
!= VOIDmode
7202 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7203 extraction_mode
= mode
;
7205 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
7206 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7207 pos_mode
= GET_MODE (pos_rtx
);
7209 /* If this is not from memory, the desired mode is the preferred mode
7210 for an extraction pattern's first input operand, or word_mode if there
7213 wanted_inner_mode
= wanted_inner_reg_mode
;
7216 /* Be careful not to go beyond the extracted object and maintain the
7217 natural alignment of the memory. */
7218 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7219 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7220 > GET_MODE_BITSIZE (wanted_inner_mode
))
7222 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7223 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7226 /* If we have to change the mode of memory and cannot, the desired mode
7227 is EXTRACTION_MODE. */
7228 if (inner_mode
!= wanted_inner_mode
7229 && (mode_dependent_address_p (XEXP (inner
, 0))
7230 || MEM_VOLATILE_P (inner
)
7232 wanted_inner_mode
= extraction_mode
;
7237 if (BITS_BIG_ENDIAN
)
7239 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7240 BITS_BIG_ENDIAN style. If position is constant, compute new
7241 position. Otherwise, build subtraction.
7242 Note that POS is relative to the mode of the original argument.
7243 If it's a MEM we need to recompute POS relative to that.
7244 However, if we're extracting from (or inserting into) a register,
7245 we want to recompute POS relative to wanted_inner_mode. */
7246 int width
= (MEM_P (inner
)
7247 ? GET_MODE_BITSIZE (is_mode
)
7248 : GET_MODE_BITSIZE (wanted_inner_mode
));
7251 pos
= width
- len
- pos
;
7254 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7255 /* POS may be less than 0 now, but we check for that below.
7256 Note that it can only be less than 0 if !MEM_P (inner). */
7259 /* If INNER has a wider mode, and this is a constant extraction, try to
7260 make it smaller and adjust the byte to point to the byte containing
7262 if (wanted_inner_mode
!= VOIDmode
7263 && inner_mode
!= wanted_inner_mode
7265 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7267 && ! mode_dependent_address_p (XEXP (inner
, 0))
7268 && ! MEM_VOLATILE_P (inner
))
7272 /* The computations below will be correct if the machine is big
7273 endian in both bits and bytes or little endian in bits and bytes.
7274 If it is mixed, we must adjust. */
7276 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7277 adjust OFFSET to compensate. */
7278 if (BYTES_BIG_ENDIAN
7279 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7280 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7282 /* We can now move to the desired byte. */
7283 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7284 * GET_MODE_SIZE (wanted_inner_mode
);
7285 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7287 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7288 && is_mode
!= wanted_inner_mode
)
7289 offset
= (GET_MODE_SIZE (is_mode
)
7290 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7292 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7295 /* If INNER is not memory, get it into the proper mode. If we are changing
7296 its mode, POS must be a constant and smaller than the size of the new
7298 else if (!MEM_P (inner
))
7300 /* On the LHS, don't create paradoxical subregs implicitely truncating
7301 the register unless TRULY_NOOP_TRUNCATION. */
7303 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner
)),
7304 GET_MODE_BITSIZE (wanted_inner_mode
)))
7307 if (GET_MODE (inner
) != wanted_inner_mode
7309 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7315 inner
= force_to_mode (inner
, wanted_inner_mode
,
7317 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7318 ? ~(unsigned HOST_WIDE_INT
) 0
7319 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7324 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7325 have to zero extend. Otherwise, we can just use a SUBREG. */
7327 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7329 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7331 /* If we know that no extraneous bits are set, and that the high
7332 bit is not set, convert extraction to cheaper one - either
7333 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7335 if (flag_expensive_optimizations
7336 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
7337 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7338 & ~(((unsigned HOST_WIDE_INT
)
7339 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7343 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7345 /* Prefer ZERO_EXTENSION, since it gives more information to
7347 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
7348 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
7353 else if (pos_rtx
!= 0
7354 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7355 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7357 /* Make POS_RTX unless we already have it and it is correct. If we don't
7358 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7360 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7361 pos_rtx
= orig_pos_rtx
;
7363 else if (pos_rtx
== 0)
7364 pos_rtx
= GEN_INT (pos
);
7366 /* Make the required operation. See if we can use existing rtx. */
7367 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7368 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7370 new_rtx
= gen_lowpart (mode
, new_rtx
);
7375 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7376 with any other operations in X. Return X without that shift if so. */
7379 extract_left_shift (rtx x
, int count
)
7381 enum rtx_code code
= GET_CODE (x
);
7382 enum machine_mode mode
= GET_MODE (x
);
7388 /* This is the shift itself. If it is wide enough, we will return
7389 either the value being shifted if the shift count is equal to
7390 COUNT or a shift for the difference. */
7391 if (CONST_INT_P (XEXP (x
, 1))
7392 && INTVAL (XEXP (x
, 1)) >= count
)
7393 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7394 INTVAL (XEXP (x
, 1)) - count
);
7398 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7399 return simplify_gen_unary (code
, mode
, tem
, mode
);
7403 case PLUS
: case IOR
: case XOR
: case AND
:
7404 /* If we can safely shift this constant and we find the inner shift,
7405 make a new operation. */
7406 if (CONST_INT_P (XEXP (x
, 1))
7407 && (UINTVAL (XEXP (x
, 1))
7408 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7409 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7410 return simplify_gen_binary (code
, mode
, tem
,
7411 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7422 /* Look at the expression rooted at X. Look for expressions
7423 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7424 Form these expressions.
7426 Return the new rtx, usually just X.
7428 Also, for machines like the VAX that don't have logical shift insns,
7429 try to convert logical to arithmetic shift operations in cases where
7430 they are equivalent. This undoes the canonicalizations to logical
7431 shifts done elsewhere.
7433 We try, as much as possible, to re-use rtl expressions to save memory.
7435 IN_CODE says what kind of expression we are processing. Normally, it is
7436 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7437 being kludges), it is MEM. When processing the arguments of a comparison
7438 or a COMPARE against zero, it is COMPARE. */
7441 make_compound_operation (rtx x
, enum rtx_code in_code
)
7443 enum rtx_code code
= GET_CODE (x
);
7444 enum machine_mode mode
= GET_MODE (x
);
7445 int mode_width
= GET_MODE_BITSIZE (mode
);
7447 enum rtx_code next_code
;
7453 /* Select the code to be used in recursive calls. Once we are inside an
7454 address, we stay there. If we have a comparison, set to COMPARE,
7455 but once inside, go back to our default of SET. */
7457 next_code
= (code
== MEM
? MEM
7458 : ((code
== PLUS
|| code
== MINUS
)
7459 && SCALAR_INT_MODE_P (mode
)) ? MEM
7460 : ((code
== COMPARE
|| COMPARISON_P (x
))
7461 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7462 : in_code
== COMPARE
? SET
: in_code
);
7464 /* Process depending on the code of this operation. If NEW is set
7465 nonzero, it will be returned. */
7470 /* Convert shifts by constants into multiplications if inside
7472 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7473 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7474 && INTVAL (XEXP (x
, 1)) >= 0)
7476 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7477 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7479 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7480 if (GET_CODE (new_rtx
) == NEG
)
7482 new_rtx
= XEXP (new_rtx
, 0);
7485 multval
= trunc_int_for_mode (multval
, mode
);
7486 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7493 lhs
= make_compound_operation (lhs
, next_code
);
7494 rhs
= make_compound_operation (rhs
, next_code
);
7495 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7496 && SCALAR_INT_MODE_P (mode
))
7498 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7500 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7502 else if (GET_CODE (lhs
) == MULT
7503 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7505 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7506 simplify_gen_unary (NEG
, mode
,
7509 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7513 SUBST (XEXP (x
, 0), lhs
);
7514 SUBST (XEXP (x
, 1), rhs
);
7517 x
= gen_lowpart (mode
, new_rtx
);
7523 lhs
= make_compound_operation (lhs
, next_code
);
7524 rhs
= make_compound_operation (rhs
, next_code
);
7525 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7526 && SCALAR_INT_MODE_P (mode
))
7528 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7530 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7532 else if (GET_CODE (rhs
) == MULT
7533 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7535 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7536 simplify_gen_unary (NEG
, mode
,
7539 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7543 SUBST (XEXP (x
, 0), lhs
);
7544 SUBST (XEXP (x
, 1), rhs
);
7547 return gen_lowpart (mode
, new_rtx
);
7550 /* If the second operand is not a constant, we can't do anything
7552 if (!CONST_INT_P (XEXP (x
, 1)))
7555 /* If the constant is a power of two minus one and the first operand
7556 is a logical right shift, make an extraction. */
7557 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7558 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7560 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7561 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7562 0, in_code
== COMPARE
);
7565 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7566 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7567 && subreg_lowpart_p (XEXP (x
, 0))
7568 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7569 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7571 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7573 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7574 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7575 0, in_code
== COMPARE
);
7577 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7578 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7579 || GET_CODE (XEXP (x
, 0)) == IOR
)
7580 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7581 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7582 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7584 /* Apply the distributive law, and then try to make extractions. */
7585 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7586 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7588 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7590 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7593 /* If we are have (and (rotate X C) M) and C is larger than the number
7594 of bits in M, this is an extraction. */
7596 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7597 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7598 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7599 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7601 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7602 new_rtx
= make_extraction (mode
, new_rtx
,
7603 (GET_MODE_BITSIZE (mode
)
7604 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7605 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7608 /* On machines without logical shifts, if the operand of the AND is
7609 a logical shift and our mask turns off all the propagated sign
7610 bits, we can replace the logical shift with an arithmetic shift. */
7611 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7612 && !have_insn_for (LSHIFTRT
, mode
)
7613 && have_insn_for (ASHIFTRT
, mode
)
7614 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7615 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7616 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7617 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7619 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7621 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7622 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7624 gen_rtx_ASHIFTRT (mode
,
7625 make_compound_operation
7626 (XEXP (XEXP (x
, 0), 0), next_code
),
7627 XEXP (XEXP (x
, 0), 1)));
7630 /* If the constant is one less than a power of two, this might be
7631 representable by an extraction even if no shift is present.
7632 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7633 we are in a COMPARE. */
7634 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7635 new_rtx
= make_extraction (mode
,
7636 make_compound_operation (XEXP (x
, 0),
7638 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7640 /* If we are in a comparison and this is an AND with a power of two,
7641 convert this into the appropriate bit extract. */
7642 else if (in_code
== COMPARE
7643 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7644 new_rtx
= make_extraction (mode
,
7645 make_compound_operation (XEXP (x
, 0),
7647 i
, NULL_RTX
, 1, 1, 0, 1);
7652 /* If the sign bit is known to be zero, replace this with an
7653 arithmetic shift. */
7654 if (have_insn_for (ASHIFTRT
, mode
)
7655 && ! have_insn_for (LSHIFTRT
, mode
)
7656 && mode_width
<= HOST_BITS_PER_WIDE_INT
7657 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7659 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7660 make_compound_operation (XEXP (x
, 0),
7666 /* ... fall through ... */
7672 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7673 this is a SIGN_EXTRACT. */
7674 if (CONST_INT_P (rhs
)
7675 && GET_CODE (lhs
) == ASHIFT
7676 && CONST_INT_P (XEXP (lhs
, 1))
7677 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7678 && INTVAL (rhs
) < mode_width
)
7680 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7681 new_rtx
= make_extraction (mode
, new_rtx
,
7682 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7683 NULL_RTX
, mode_width
- INTVAL (rhs
),
7684 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7688 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7689 If so, try to merge the shifts into a SIGN_EXTEND. We could
7690 also do this for some cases of SIGN_EXTRACT, but it doesn't
7691 seem worth the effort; the case checked for occurs on Alpha. */
7694 && ! (GET_CODE (lhs
) == SUBREG
7695 && (OBJECT_P (SUBREG_REG (lhs
))))
7696 && CONST_INT_P (rhs
)
7697 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7698 && INTVAL (rhs
) < mode_width
7699 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7700 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7701 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7702 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7707 /* Call ourselves recursively on the inner expression. If we are
7708 narrowing the object and it has a different RTL code from
7709 what it originally did, do this SUBREG as a force_to_mode. */
7711 rtx inner
= SUBREG_REG (x
), simplified
;
7713 tem
= make_compound_operation (inner
, in_code
);
7716 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7720 if (GET_CODE (tem
) != GET_CODE (inner
)
7721 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7722 && subreg_lowpart_p (x
))
7725 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7727 /* If we have something other than a SUBREG, we might have
7728 done an expansion, so rerun ourselves. */
7729 if (GET_CODE (newer
) != SUBREG
)
7730 newer
= make_compound_operation (newer
, in_code
);
7732 /* force_to_mode can expand compounds. If it just re-expanded the
7733 compound, use gen_lowpart to convert to the desired mode. */
7734 if (rtx_equal_p (newer
, x
)
7735 /* Likewise if it re-expanded the compound only partially.
7736 This happens for SUBREG of ZERO_EXTRACT if they extract
7737 the same number of bits. */
7738 || (GET_CODE (newer
) == SUBREG
7739 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7740 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7741 && GET_CODE (inner
) == AND
7742 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7743 return gen_lowpart (GET_MODE (x
), tem
);
7759 x
= gen_lowpart (mode
, new_rtx
);
7760 code
= GET_CODE (x
);
7763 /* Now recursively process each operand of this operation. */
7764 fmt
= GET_RTX_FORMAT (code
);
7765 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7768 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7769 SUBST (XEXP (x
, i
), new_rtx
);
7771 else if (fmt
[i
] == 'E')
7772 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7774 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7775 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7779 /* If this is a commutative operation, the changes to the operands
7780 may have made it noncanonical. */
7781 if (COMMUTATIVE_ARITH_P (x
)
7782 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7785 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7786 SUBST (XEXP (x
, 1), tem
);
7792 /* Given M see if it is a value that would select a field of bits
7793 within an item, but not the entire word. Return -1 if not.
7794 Otherwise, return the starting position of the field, where 0 is the
7797 *PLEN is set to the length of the field. */
7800 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7802 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7803 int pos
= m
? ctz_hwi (m
) : -1;
7807 /* Now shift off the low-order zero bits and see if we have a
7808 power of two minus 1. */
7809 len
= exact_log2 ((m
>> pos
) + 1);
7818 /* If X refers to a register that equals REG in value, replace these
7819 references with REG. */
7821 canon_reg_for_combine (rtx x
, rtx reg
)
7828 enum rtx_code code
= GET_CODE (x
);
7829 switch (GET_RTX_CLASS (code
))
7832 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7833 if (op0
!= XEXP (x
, 0))
7834 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7839 case RTX_COMM_ARITH
:
7840 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7841 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7842 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7843 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7847 case RTX_COMM_COMPARE
:
7848 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7849 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7850 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7851 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7852 GET_MODE (op0
), op0
, op1
);
7856 case RTX_BITFIELD_OPS
:
7857 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7858 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7859 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7860 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7861 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7862 GET_MODE (op0
), op0
, op1
, op2
);
7867 if (rtx_equal_p (get_last_value (reg
), x
)
7868 || rtx_equal_p (reg
, get_last_value (x
)))
7877 fmt
= GET_RTX_FORMAT (code
);
7879 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7882 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7883 if (op
!= XEXP (x
, i
))
7893 else if (fmt
[i
] == 'E')
7896 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7898 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7899 if (op
!= XVECEXP (x
, i
, j
))
7906 XVECEXP (x
, i
, j
) = op
;
7917 /* Return X converted to MODE. If the value is already truncated to
7918 MODE we can just return a subreg even though in the general case we
7919 would need an explicit truncation. */
7922 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7924 if (!CONST_INT_P (x
)
7925 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7926 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7927 GET_MODE_BITSIZE (GET_MODE (x
)))
7928 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7930 /* Bit-cast X into an integer mode. */
7931 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7932 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7933 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7937 return gen_lowpart (mode
, x
);
7940 /* See if X can be simplified knowing that we will only refer to it in
7941 MODE and will only refer to those bits that are nonzero in MASK.
7942 If other bits are being computed or if masking operations are done
7943 that select a superset of the bits in MASK, they can sometimes be
7946 Return a possibly simplified expression, but always convert X to
7947 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7949 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7950 are all off in X. This is used when X will be complemented, by either
7951 NOT, NEG, or XOR. */
7954 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7957 enum rtx_code code
= GET_CODE (x
);
7958 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7959 enum machine_mode op_mode
;
7960 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7963 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7964 code below will do the wrong thing since the mode of such an
7965 expression is VOIDmode.
7967 Also do nothing if X is a CLOBBER; this can happen if X was
7968 the return value from a call to gen_lowpart. */
7969 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7972 /* We want to perform the operation is its present mode unless we know
7973 that the operation is valid in MODE, in which case we do the operation
7975 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7976 && have_insn_for (code
, mode
))
7977 ? mode
: GET_MODE (x
));
7979 /* It is not valid to do a right-shift in a narrower mode
7980 than the one it came in with. */
7981 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7982 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7983 op_mode
= GET_MODE (x
);
7985 /* Truncate MASK to fit OP_MODE. */
7987 mask
&= GET_MODE_MASK (op_mode
);
7989 /* When we have an arithmetic operation, or a shift whose count we
7990 do not know, we need to assume that all bits up to the highest-order
7991 bit in MASK will be needed. This is how we form such a mask. */
7992 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7993 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7995 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7998 /* Determine what bits of X are guaranteed to be (non)zero. */
7999 nonzero
= nonzero_bits (x
, mode
);
8001 /* If none of the bits in X are needed, return a zero. */
8002 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8005 /* If X is a CONST_INT, return a new one. Do this here since the
8006 test below will fail. */
8007 if (CONST_INT_P (x
))
8009 if (SCALAR_INT_MODE_P (mode
))
8010 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8013 x
= GEN_INT (INTVAL (x
) & mask
);
8014 return gen_lowpart_common (mode
, x
);
8018 /* If X is narrower than MODE and we want all the bits in X's mode, just
8019 get X in the proper mode. */
8020 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8021 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8022 return gen_lowpart (mode
, x
);
8024 /* We can ignore the effect of a SUBREG if it narrows the mode or
8025 if the constant masks to zero all the bits the mode doesn't have. */
8026 if (GET_CODE (x
) == SUBREG
8027 && subreg_lowpart_p (x
)
8028 && ((GET_MODE_SIZE (GET_MODE (x
))
8029 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8031 & GET_MODE_MASK (GET_MODE (x
))
8032 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8033 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8035 /* The arithmetic simplifications here only work for scalar integer modes. */
8036 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8037 return gen_lowpart_or_truncate (mode
, x
);
8042 /* If X is a (clobber (const_int)), return it since we know we are
8043 generating something that won't match. */
8050 x
= expand_compound_operation (x
);
8051 if (GET_CODE (x
) != code
)
8052 return force_to_mode (x
, mode
, mask
, next_select
);
8056 /* Similarly for a truncate. */
8057 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8060 /* If this is an AND with a constant, convert it into an AND
8061 whose constant is the AND of that constant with MASK. If it
8062 remains an AND of MASK, delete it since it is redundant. */
8064 if (CONST_INT_P (XEXP (x
, 1)))
8066 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8067 mask
& INTVAL (XEXP (x
, 1)));
8069 /* If X is still an AND, see if it is an AND with a mask that
8070 is just some low-order bits. If so, and it is MASK, we don't
8073 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8074 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8078 /* If it remains an AND, try making another AND with the bits
8079 in the mode mask that aren't in MASK turned on. If the
8080 constant in the AND is wide enough, this might make a
8081 cheaper constant. */
8083 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8084 && GET_MODE_MASK (GET_MODE (x
)) != mask
8085 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
8087 unsigned HOST_WIDE_INT cval
8088 = UINTVAL (XEXP (x
, 1))
8089 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8090 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
8093 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8094 number, sign extend it. */
8095 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8096 && (cval
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8097 cval
|= (unsigned HOST_WIDE_INT
) -1 << width
;
8099 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8100 XEXP (x
, 0), GEN_INT (cval
));
8101 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
8102 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8112 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8113 low-order bits (as in an alignment operation) and FOO is already
8114 aligned to that boundary, mask C1 to that boundary as well.
8115 This may eliminate that PLUS and, later, the AND. */
8118 unsigned int width
= GET_MODE_BITSIZE (mode
);
8119 unsigned HOST_WIDE_INT smask
= mask
;
8121 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8122 number, sign extend it. */
8124 if (width
< HOST_BITS_PER_WIDE_INT
8125 && (smask
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8126 smask
|= (unsigned HOST_WIDE_INT
) (-1) << width
;
8128 if (CONST_INT_P (XEXP (x
, 1))
8129 && exact_log2 (- smask
) >= 0
8130 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8131 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8132 return force_to_mode (plus_constant (XEXP (x
, 0),
8133 (INTVAL (XEXP (x
, 1)) & smask
)),
8134 mode
, smask
, next_select
);
8137 /* ... fall through ... */
8140 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8141 most significant bit in MASK since carries from those bits will
8142 affect the bits we are interested in. */
8147 /* If X is (minus C Y) where C's least set bit is larger than any bit
8148 in the mask, then we may replace with (neg Y). */
8149 if (CONST_INT_P (XEXP (x
, 0))
8150 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8151 & -INTVAL (XEXP (x
, 0))))
8154 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8156 return force_to_mode (x
, mode
, mask
, next_select
);
8159 /* Similarly, if C contains every bit in the fuller_mask, then we may
8160 replace with (not Y). */
8161 if (CONST_INT_P (XEXP (x
, 0))
8162 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8164 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8165 XEXP (x
, 1), GET_MODE (x
));
8166 return force_to_mode (x
, mode
, mask
, next_select
);
8174 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8175 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8176 operation which may be a bitfield extraction. Ensure that the
8177 constant we form is not wider than the mode of X. */
8179 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8180 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8181 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8182 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8183 && CONST_INT_P (XEXP (x
, 1))
8184 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8185 + floor_log2 (INTVAL (XEXP (x
, 1))))
8186 < GET_MODE_BITSIZE (GET_MODE (x
)))
8187 && (UINTVAL (XEXP (x
, 1))
8188 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8190 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8191 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8192 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8193 XEXP (XEXP (x
, 0), 0), temp
);
8194 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8195 XEXP (XEXP (x
, 0), 1));
8196 return force_to_mode (x
, mode
, mask
, next_select
);
8200 /* For most binary operations, just propagate into the operation and
8201 change the mode if we have an operation of that mode. */
8203 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8204 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8206 /* If we ended up truncating both operands, truncate the result of the
8207 operation instead. */
8208 if (GET_CODE (op0
) == TRUNCATE
8209 && GET_CODE (op1
) == TRUNCATE
)
8211 op0
= XEXP (op0
, 0);
8212 op1
= XEXP (op1
, 0);
8215 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8216 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8218 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8219 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8223 /* For left shifts, do the same, but just for the first operand.
8224 However, we cannot do anything with shifts where we cannot
8225 guarantee that the counts are smaller than the size of the mode
8226 because such a count will have a different meaning in a
8229 if (! (CONST_INT_P (XEXP (x
, 1))
8230 && INTVAL (XEXP (x
, 1)) >= 0
8231 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
8232 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8233 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8234 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
8237 /* If the shift count is a constant and we can do arithmetic in
8238 the mode of the shift, refine which bits we need. Otherwise, use the
8239 conservative form of the mask. */
8240 if (CONST_INT_P (XEXP (x
, 1))
8241 && INTVAL (XEXP (x
, 1)) >= 0
8242 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
8243 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8244 mask
>>= INTVAL (XEXP (x
, 1));
8248 op0
= gen_lowpart_or_truncate (op_mode
,
8249 force_to_mode (XEXP (x
, 0), op_mode
,
8250 mask
, next_select
));
8252 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8253 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8257 /* Here we can only do something if the shift count is a constant,
8258 this shift constant is valid for the host, and we can do arithmetic
8261 if (CONST_INT_P (XEXP (x
, 1))
8262 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8263 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8265 rtx inner
= XEXP (x
, 0);
8266 unsigned HOST_WIDE_INT inner_mask
;
8268 /* Select the mask of the bits we need for the shift operand. */
8269 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8271 /* We can only change the mode of the shift if we can do arithmetic
8272 in the mode of the shift and INNER_MASK is no wider than the
8273 width of X's mode. */
8274 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8275 op_mode
= GET_MODE (x
);
8277 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8279 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8280 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8283 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8284 shift and AND produces only copies of the sign bit (C2 is one less
8285 than a power of two), we can do this with just a shift. */
8287 if (GET_CODE (x
) == LSHIFTRT
8288 && CONST_INT_P (XEXP (x
, 1))
8289 /* The shift puts one of the sign bit copies in the least significant
8291 && ((INTVAL (XEXP (x
, 1))
8292 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8293 >= GET_MODE_BITSIZE (GET_MODE (x
)))
8294 && exact_log2 (mask
+ 1) >= 0
8295 /* Number of bits left after the shift must be more than the mask
8297 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8298 <= GET_MODE_BITSIZE (GET_MODE (x
)))
8299 /* Must be more sign bit copies than the mask needs. */
8300 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8301 >= exact_log2 (mask
+ 1)))
8302 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8303 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
8304 - exact_log2 (mask
+ 1)));
8309 /* If we are just looking for the sign bit, we don't need this shift at
8310 all, even if it has a variable count. */
8311 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8312 && (mask
== ((unsigned HOST_WIDE_INT
) 1
8313 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8314 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8316 /* If this is a shift by a constant, get a mask that contains those bits
8317 that are not copies of the sign bit. We then have two cases: If
8318 MASK only includes those bits, this can be a logical shift, which may
8319 allow simplifications. If MASK is a single-bit field not within
8320 those bits, we are requesting a copy of the sign bit and hence can
8321 shift the sign bit to the appropriate location. */
8323 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8324 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8328 /* If the considered data is wider than HOST_WIDE_INT, we can't
8329 represent a mask for all its bits in a single scalar.
8330 But we only care about the lower bits, so calculate these. */
8332 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8334 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8336 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8337 is the number of bits a full-width mask would have set.
8338 We need only shift if these are fewer than nonzero can
8339 hold. If not, we must keep all bits set in nonzero. */
8341 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8342 < HOST_BITS_PER_WIDE_INT
)
8343 nonzero
>>= INTVAL (XEXP (x
, 1))
8344 + HOST_BITS_PER_WIDE_INT
8345 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
8349 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8350 nonzero
>>= INTVAL (XEXP (x
, 1));
8353 if ((mask
& ~nonzero
) == 0)
8355 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8356 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8357 if (GET_CODE (x
) != ASHIFTRT
)
8358 return force_to_mode (x
, mode
, mask
, next_select
);
8361 else if ((i
= exact_log2 (mask
)) >= 0)
8363 x
= simplify_shift_const
8364 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8365 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
8367 if (GET_CODE (x
) != ASHIFTRT
)
8368 return force_to_mode (x
, mode
, mask
, next_select
);
8372 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8373 even if the shift count isn't a constant. */
8375 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8376 XEXP (x
, 0), XEXP (x
, 1));
8380 /* If this is a zero- or sign-extension operation that just affects bits
8381 we don't care about, remove it. Be sure the call above returned
8382 something that is still a shift. */
8384 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8385 && CONST_INT_P (XEXP (x
, 1))
8386 && INTVAL (XEXP (x
, 1)) >= 0
8387 && (INTVAL (XEXP (x
, 1))
8388 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8389 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8390 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8391 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8398 /* If the shift count is constant and we can do computations
8399 in the mode of X, compute where the bits we care about are.
8400 Otherwise, we can't do anything. Don't change the mode of
8401 the shift or propagate MODE into the shift, though. */
8402 if (CONST_INT_P (XEXP (x
, 1))
8403 && INTVAL (XEXP (x
, 1)) >= 0)
8405 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8406 GET_MODE (x
), GEN_INT (mask
),
8408 if (temp
&& CONST_INT_P (temp
))
8410 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8411 INTVAL (temp
), next_select
));
8416 /* If we just want the low-order bit, the NEG isn't needed since it
8417 won't change the low-order bit. */
8419 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8421 /* We need any bits less significant than the most significant bit in
8422 MASK since carries from those bits will affect the bits we are
8428 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8429 same as the XOR case above. Ensure that the constant we form is not
8430 wider than the mode of X. */
8432 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8433 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8434 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8435 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8436 < GET_MODE_BITSIZE (GET_MODE (x
)))
8437 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8439 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8441 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8442 XEXP (XEXP (x
, 0), 0), temp
);
8443 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8444 temp
, XEXP (XEXP (x
, 0), 1));
8446 return force_to_mode (x
, mode
, mask
, next_select
);
8449 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8450 use the full mask inside the NOT. */
8454 op0
= gen_lowpart_or_truncate (op_mode
,
8455 force_to_mode (XEXP (x
, 0), mode
, mask
,
8457 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8458 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8462 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8463 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8464 which is equal to STORE_FLAG_VALUE. */
8465 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8466 && XEXP (x
, 1) == const0_rtx
8467 && GET_MODE (XEXP (x
, 0)) == mode
8468 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8469 && (nonzero_bits (XEXP (x
, 0), mode
)
8470 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8471 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8476 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8477 written in a narrower mode. We play it safe and do not do so. */
8480 gen_lowpart_or_truncate (GET_MODE (x
),
8481 force_to_mode (XEXP (x
, 1), mode
,
8482 mask
, next_select
)));
8484 gen_lowpart_or_truncate (GET_MODE (x
),
8485 force_to_mode (XEXP (x
, 2), mode
,
8486 mask
, next_select
)));
8493 /* Ensure we return a value of the proper mode. */
8494 return gen_lowpart_or_truncate (mode
, x
);
8497 /* Return nonzero if X is an expression that has one of two values depending on
8498 whether some other value is zero or nonzero. In that case, we return the
8499 value that is being tested, *PTRUE is set to the value if the rtx being
8500 returned has a nonzero value, and *PFALSE is set to the other alternative.
8502 If we return zero, we set *PTRUE and *PFALSE to X. */
8505 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8507 enum machine_mode mode
= GET_MODE (x
);
8508 enum rtx_code code
= GET_CODE (x
);
8509 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8510 unsigned HOST_WIDE_INT nz
;
8512 /* If we are comparing a value against zero, we are done. */
8513 if ((code
== NE
|| code
== EQ
)
8514 && XEXP (x
, 1) == const0_rtx
)
8516 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8517 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8521 /* If this is a unary operation whose operand has one of two values, apply
8522 our opcode to compute those values. */
8523 else if (UNARY_P (x
)
8524 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8526 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8527 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8528 GET_MODE (XEXP (x
, 0)));
8532 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8533 make can't possibly match and would suppress other optimizations. */
8534 else if (code
== COMPARE
)
8537 /* If this is a binary operation, see if either side has only one of two
8538 values. If either one does or if both do and they are conditional on
8539 the same value, compute the new true and false values. */
8540 else if (BINARY_P (x
))
8542 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8543 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8545 if ((cond0
!= 0 || cond1
!= 0)
8546 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8548 /* If if_then_else_cond returned zero, then true/false are the
8549 same rtl. We must copy one of them to prevent invalid rtl
8552 true0
= copy_rtx (true0
);
8553 else if (cond1
== 0)
8554 true1
= copy_rtx (true1
);
8556 if (COMPARISON_P (x
))
8558 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8560 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8565 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8566 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8569 return cond0
? cond0
: cond1
;
8572 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8573 operands is zero when the other is nonzero, and vice-versa,
8574 and STORE_FLAG_VALUE is 1 or -1. */
8576 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8577 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8579 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8581 rtx op0
= XEXP (XEXP (x
, 0), 1);
8582 rtx op1
= XEXP (XEXP (x
, 1), 1);
8584 cond0
= XEXP (XEXP (x
, 0), 0);
8585 cond1
= XEXP (XEXP (x
, 1), 0);
8587 if (COMPARISON_P (cond0
)
8588 && COMPARISON_P (cond1
)
8589 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8590 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8591 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8592 || ((swap_condition (GET_CODE (cond0
))
8593 == reversed_comparison_code (cond1
, NULL
))
8594 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8595 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8596 && ! side_effects_p (x
))
8598 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8599 *pfalse
= simplify_gen_binary (MULT
, mode
,
8601 ? simplify_gen_unary (NEG
, mode
,
8609 /* Similarly for MULT, AND and UMIN, except that for these the result
8611 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8612 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8613 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8615 cond0
= XEXP (XEXP (x
, 0), 0);
8616 cond1
= XEXP (XEXP (x
, 1), 0);
8618 if (COMPARISON_P (cond0
)
8619 && COMPARISON_P (cond1
)
8620 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8621 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8622 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8623 || ((swap_condition (GET_CODE (cond0
))
8624 == reversed_comparison_code (cond1
, NULL
))
8625 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8626 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8627 && ! side_effects_p (x
))
8629 *ptrue
= *pfalse
= const0_rtx
;
8635 else if (code
== IF_THEN_ELSE
)
8637 /* If we have IF_THEN_ELSE already, extract the condition and
8638 canonicalize it if it is NE or EQ. */
8639 cond0
= XEXP (x
, 0);
8640 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8641 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8642 return XEXP (cond0
, 0);
8643 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8645 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8646 return XEXP (cond0
, 0);
8652 /* If X is a SUBREG, we can narrow both the true and false values
8653 if the inner expression, if there is a condition. */
8654 else if (code
== SUBREG
8655 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8658 true0
= simplify_gen_subreg (mode
, true0
,
8659 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8660 false0
= simplify_gen_subreg (mode
, false0
,
8661 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8662 if (true0
&& false0
)
8670 /* If X is a constant, this isn't special and will cause confusions
8671 if we treat it as such. Likewise if it is equivalent to a constant. */
8672 else if (CONSTANT_P (x
)
8673 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8676 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8677 will be least confusing to the rest of the compiler. */
8678 else if (mode
== BImode
)
8680 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8684 /* If X is known to be either 0 or -1, those are the true and
8685 false values when testing X. */
8686 else if (x
== constm1_rtx
|| x
== const0_rtx
8687 || (mode
!= VOIDmode
8688 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
8690 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8694 /* Likewise for 0 or a single bit. */
8695 else if (SCALAR_INT_MODE_P (mode
)
8696 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8697 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8699 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8703 /* Otherwise fail; show no condition with true and false values the same. */
8704 *ptrue
= *pfalse
= x
;
8708 /* Return the value of expression X given the fact that condition COND
8709 is known to be true when applied to REG as its first operand and VAL
8710 as its second. X is known to not be shared and so can be modified in
8713 We only handle the simplest cases, and specifically those cases that
8714 arise with IF_THEN_ELSE expressions. */
8717 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8719 enum rtx_code code
= GET_CODE (x
);
8724 if (side_effects_p (x
))
8727 /* If either operand of the condition is a floating point value,
8728 then we have to avoid collapsing an EQ comparison. */
8730 && rtx_equal_p (x
, reg
)
8731 && ! FLOAT_MODE_P (GET_MODE (x
))
8732 && ! FLOAT_MODE_P (GET_MODE (val
)))
8735 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8738 /* If X is (abs REG) and we know something about REG's relationship
8739 with zero, we may be able to simplify this. */
8741 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8744 case GE
: case GT
: case EQ
:
8747 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8749 GET_MODE (XEXP (x
, 0)));
8754 /* The only other cases we handle are MIN, MAX, and comparisons if the
8755 operands are the same as REG and VAL. */
8757 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8759 if (rtx_equal_p (XEXP (x
, 0), val
))
8760 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8762 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8764 if (COMPARISON_P (x
))
8766 if (comparison_dominates_p (cond
, code
))
8767 return const_true_rtx
;
8769 code
= reversed_comparison_code (x
, NULL
);
8771 && comparison_dominates_p (cond
, code
))
8776 else if (code
== SMAX
|| code
== SMIN
8777 || code
== UMIN
|| code
== UMAX
)
8779 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8781 /* Do not reverse the condition when it is NE or EQ.
8782 This is because we cannot conclude anything about
8783 the value of 'SMAX (x, y)' when x is not equal to y,
8784 but we can when x equals y. */
8785 if ((code
== SMAX
|| code
== UMAX
)
8786 && ! (cond
== EQ
|| cond
== NE
))
8787 cond
= reverse_condition (cond
);
8792 return unsignedp
? x
: XEXP (x
, 1);
8794 return unsignedp
? x
: XEXP (x
, 0);
8796 return unsignedp
? XEXP (x
, 1) : x
;
8798 return unsignedp
? XEXP (x
, 0) : x
;
8805 else if (code
== SUBREG
)
8807 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8808 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8810 if (SUBREG_REG (x
) != r
)
8812 /* We must simplify subreg here, before we lose track of the
8813 original inner_mode. */
8814 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8815 inner_mode
, SUBREG_BYTE (x
));
8819 SUBST (SUBREG_REG (x
), r
);
8824 /* We don't have to handle SIGN_EXTEND here, because even in the
8825 case of replacing something with a modeless CONST_INT, a
8826 CONST_INT is already (supposed to be) a valid sign extension for
8827 its narrower mode, which implies it's already properly
8828 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8829 story is different. */
8830 else if (code
== ZERO_EXTEND
)
8832 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8833 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8835 if (XEXP (x
, 0) != r
)
8837 /* We must simplify the zero_extend here, before we lose
8838 track of the original inner_mode. */
8839 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8844 SUBST (XEXP (x
, 0), r
);
8850 fmt
= GET_RTX_FORMAT (code
);
8851 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8854 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8855 else if (fmt
[i
] == 'E')
8856 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8857 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8864 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8865 assignment as a field assignment. */
8868 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8870 if (x
== y
|| rtx_equal_p (x
, y
))
8873 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8876 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8877 Note that all SUBREGs of MEM are paradoxical; otherwise they
8878 would have been rewritten. */
8879 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8880 && MEM_P (SUBREG_REG (y
))
8881 && rtx_equal_p (SUBREG_REG (y
),
8882 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8885 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8886 && MEM_P (SUBREG_REG (x
))
8887 && rtx_equal_p (SUBREG_REG (x
),
8888 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8891 /* We used to see if get_last_value of X and Y were the same but that's
8892 not correct. In one direction, we'll cause the assignment to have
8893 the wrong destination and in the case, we'll import a register into this
8894 insn that might have already have been dead. So fail if none of the
8895 above cases are true. */
8899 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8900 Return that assignment if so.
8902 We only handle the most common cases. */
8905 make_field_assignment (rtx x
)
8907 rtx dest
= SET_DEST (x
);
8908 rtx src
= SET_SRC (x
);
8913 unsigned HOST_WIDE_INT len
;
8915 enum machine_mode mode
;
8917 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8918 a clear of a one-bit field. We will have changed it to
8919 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8922 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8923 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8924 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8925 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8927 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8930 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8934 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8935 && subreg_lowpart_p (XEXP (src
, 0))
8936 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8937 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8938 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8939 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8940 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8941 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8943 assign
= make_extraction (VOIDmode
, dest
, 0,
8944 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8947 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8951 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8953 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8954 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8955 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8957 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8960 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8964 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8965 SRC is an AND with all bits of that field set, then we can discard
8967 if (GET_CODE (dest
) == ZERO_EXTRACT
8968 && CONST_INT_P (XEXP (dest
, 1))
8969 && GET_CODE (src
) == AND
8970 && CONST_INT_P (XEXP (src
, 1)))
8972 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8973 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8974 unsigned HOST_WIDE_INT ze_mask
;
8976 if (width
>= HOST_BITS_PER_WIDE_INT
)
8979 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8981 /* Complete overlap. We can remove the source AND. */
8982 if ((and_mask
& ze_mask
) == ze_mask
)
8983 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8985 /* Partial overlap. We can reduce the source AND. */
8986 if ((and_mask
& ze_mask
) != and_mask
)
8988 mode
= GET_MODE (src
);
8989 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8990 gen_int_mode (and_mask
& ze_mask
, mode
));
8991 return gen_rtx_SET (VOIDmode
, dest
, src
);
8995 /* The other case we handle is assignments into a constant-position
8996 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8997 a mask that has all one bits except for a group of zero bits and
8998 OTHER is known to have zeros where C1 has ones, this is such an
8999 assignment. Compute the position and length from C1. Shift OTHER
9000 to the appropriate position, force it to the required mode, and
9001 make the extraction. Check for the AND in both operands. */
9003 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9006 rhs
= expand_compound_operation (XEXP (src
, 0));
9007 lhs
= expand_compound_operation (XEXP (src
, 1));
9009 if (GET_CODE (rhs
) == AND
9010 && CONST_INT_P (XEXP (rhs
, 1))
9011 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9012 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9013 else if (GET_CODE (lhs
) == AND
9014 && CONST_INT_P (XEXP (lhs
, 1))
9015 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9016 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9020 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9021 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
9022 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9023 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9026 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9030 /* The mode to use for the source is the mode of the assignment, or of
9031 what is inside a possible STRICT_LOW_PART. */
9032 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9033 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9035 /* Shift OTHER right POS places and make it the source, restricting it
9036 to the proper length and mode. */
9038 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9042 src
= force_to_mode (src
, mode
,
9043 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
9044 ? ~(unsigned HOST_WIDE_INT
) 0
9045 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9048 /* If SRC is masked by an AND that does not make a difference in
9049 the value being stored, strip it. */
9050 if (GET_CODE (assign
) == ZERO_EXTRACT
9051 && CONST_INT_P (XEXP (assign
, 1))
9052 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9053 && GET_CODE (src
) == AND
9054 && CONST_INT_P (XEXP (src
, 1))
9055 && UINTVAL (XEXP (src
, 1))
9056 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9057 src
= XEXP (src
, 0);
9059 return gen_rtx_SET (VOIDmode
, assign
, src
);
9062 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9066 apply_distributive_law (rtx x
)
9068 enum rtx_code code
= GET_CODE (x
);
9069 enum rtx_code inner_code
;
9070 rtx lhs
, rhs
, other
;
9073 /* Distributivity is not true for floating point as it can change the
9074 value. So we don't do it unless -funsafe-math-optimizations. */
9075 if (FLOAT_MODE_P (GET_MODE (x
))
9076 && ! flag_unsafe_math_optimizations
)
9079 /* The outer operation can only be one of the following: */
9080 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9081 && code
!= PLUS
&& code
!= MINUS
)
9087 /* If either operand is a primitive we can't do anything, so get out
9089 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9092 lhs
= expand_compound_operation (lhs
);
9093 rhs
= expand_compound_operation (rhs
);
9094 inner_code
= GET_CODE (lhs
);
9095 if (inner_code
!= GET_CODE (rhs
))
9098 /* See if the inner and outer operations distribute. */
9105 /* These all distribute except over PLUS. */
9106 if (code
== PLUS
|| code
== MINUS
)
9111 if (code
!= PLUS
&& code
!= MINUS
)
9116 /* This is also a multiply, so it distributes over everything. */
9120 /* Non-paradoxical SUBREGs distributes over all operations,
9121 provided the inner modes and byte offsets are the same, this
9122 is an extraction of a low-order part, we don't convert an fp
9123 operation to int or vice versa, this is not a vector mode,
9124 and we would not be converting a single-word operation into a
9125 multi-word operation. The latter test is not required, but
9126 it prevents generating unneeded multi-word operations. Some
9127 of the previous tests are redundant given the latter test,
9128 but are retained because they are required for correctness.
9130 We produce the result slightly differently in this case. */
9132 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
9133 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
9134 || ! subreg_lowpart_p (lhs
)
9135 || (GET_MODE_CLASS (GET_MODE (lhs
))
9136 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
9137 || (GET_MODE_SIZE (GET_MODE (lhs
))
9138 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
9139 || VECTOR_MODE_P (GET_MODE (lhs
))
9140 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
9141 /* Result might need to be truncated. Don't change mode if
9142 explicit truncation is needed. */
9143 || !TRULY_NOOP_TRUNCATION
9144 (GET_MODE_BITSIZE (GET_MODE (x
)),
9145 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
9148 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
9149 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
9150 return gen_lowpart (GET_MODE (x
), tem
);
9156 /* Set LHS and RHS to the inner operands (A and B in the example
9157 above) and set OTHER to the common operand (C in the example).
9158 There is only one way to do this unless the inner operation is
9160 if (COMMUTATIVE_ARITH_P (lhs
)
9161 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9162 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9163 else if (COMMUTATIVE_ARITH_P (lhs
)
9164 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9165 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9166 else if (COMMUTATIVE_ARITH_P (lhs
)
9167 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9168 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9169 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9170 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9174 /* Form the new inner operation, seeing if it simplifies first. */
9175 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9177 /* There is one exception to the general way of distributing:
9178 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9179 if (code
== XOR
&& inner_code
== IOR
)
9182 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9185 /* We may be able to continuing distributing the result, so call
9186 ourselves recursively on the inner operation before forming the
9187 outer operation, which we return. */
9188 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9189 apply_distributive_law (tem
), other
);
9192 /* See if X is of the form (* (+ A B) C), and if so convert to
9193 (+ (* A C) (* B C)) and try to simplify.
9195 Most of the time, this results in no change. However, if some of
9196 the operands are the same or inverses of each other, simplifications
9199 For example, (and (ior A B) (not B)) can occur as the result of
9200 expanding a bit field assignment. When we apply the distributive
9201 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9202 which then simplifies to (and (A (not B))).
9204 Note that no checks happen on the validity of applying the inverse
9205 distributive law. This is pointless since we can do it in the
9206 few places where this routine is called.
9208 N is the index of the term that is decomposed (the arithmetic operation,
9209 i.e. (+ A B) in the first example above). !N is the index of the term that
9210 is distributed, i.e. of C in the first example above. */
9212 distribute_and_simplify_rtx (rtx x
, int n
)
9214 enum machine_mode mode
;
9215 enum rtx_code outer_code
, inner_code
;
9216 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9218 /* Distributivity is not true for floating point as it can change the
9219 value. So we don't do it unless -funsafe-math-optimizations. */
9220 if (FLOAT_MODE_P (GET_MODE (x
))
9221 && ! flag_unsafe_math_optimizations
)
9224 decomposed
= XEXP (x
, n
);
9225 if (!ARITHMETIC_P (decomposed
))
9228 mode
= GET_MODE (x
);
9229 outer_code
= GET_CODE (x
);
9230 distributed
= XEXP (x
, !n
);
9232 inner_code
= GET_CODE (decomposed
);
9233 inner_op0
= XEXP (decomposed
, 0);
9234 inner_op1
= XEXP (decomposed
, 1);
9236 /* Special case (and (xor B C) (not A)), which is equivalent to
9237 (xor (ior A B) (ior A C)) */
9238 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9240 distributed
= XEXP (distributed
, 0);
9246 /* Distribute the second term. */
9247 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9248 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9252 /* Distribute the first term. */
9253 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9254 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9257 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9259 if (GET_CODE (tmp
) != outer_code
9260 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
9261 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
9267 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9268 in MODE. Return an equivalent form, if different from (and VAROP
9269 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9272 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9273 unsigned HOST_WIDE_INT constop
)
9275 unsigned HOST_WIDE_INT nonzero
;
9276 unsigned HOST_WIDE_INT orig_constop
;
9281 orig_constop
= constop
;
9282 if (GET_CODE (varop
) == CLOBBER
)
9285 /* Simplify VAROP knowing that we will be only looking at some of the
9288 Note by passing in CONSTOP, we guarantee that the bits not set in
9289 CONSTOP are not significant and will never be examined. We must
9290 ensure that is the case by explicitly masking out those bits
9291 before returning. */
9292 varop
= force_to_mode (varop
, mode
, constop
, 0);
9294 /* If VAROP is a CLOBBER, we will fail so return it. */
9295 if (GET_CODE (varop
) == CLOBBER
)
9298 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9299 to VAROP and return the new constant. */
9300 if (CONST_INT_P (varop
))
9301 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9303 /* See what bits may be nonzero in VAROP. Unlike the general case of
9304 a call to nonzero_bits, here we don't care about bits outside
9307 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9309 /* Turn off all bits in the constant that are known to already be zero.
9310 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9311 which is tested below. */
9315 /* If we don't have any bits left, return zero. */
9319 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9320 a power of two, we can replace this with an ASHIFT. */
9321 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9322 && (i
= exact_log2 (constop
)) >= 0)
9323 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9325 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9326 or XOR, then try to apply the distributive law. This may eliminate
9327 operations if either branch can be simplified because of the AND.
9328 It may also make some cases more complex, but those cases probably
9329 won't match a pattern either with or without this. */
9331 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9335 apply_distributive_law
9336 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9337 simplify_and_const_int (NULL_RTX
,
9341 simplify_and_const_int (NULL_RTX
,
9346 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9347 the AND and see if one of the operands simplifies to zero. If so, we
9348 may eliminate it. */
9350 if (GET_CODE (varop
) == PLUS
9351 && exact_log2 (constop
+ 1) >= 0)
9355 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9356 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9357 if (o0
== const0_rtx
)
9359 if (o1
== const0_rtx
)
9363 /* Make a SUBREG if necessary. If we can't make it, fail. */
9364 varop
= gen_lowpart (mode
, varop
);
9365 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9368 /* If we are only masking insignificant bits, return VAROP. */
9369 if (constop
== nonzero
)
9372 if (varop
== orig_varop
&& constop
== orig_constop
)
9375 /* Otherwise, return an AND. */
9376 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9380 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9383 Return an equivalent form, if different from X. Otherwise, return X. If
9384 X is zero, we are to always construct the equivalent form. */
9387 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9388 unsigned HOST_WIDE_INT constop
)
9390 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9395 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9396 gen_int_mode (constop
, mode
));
9397 if (GET_MODE (x
) != mode
)
9398 x
= gen_lowpart (mode
, x
);
9402 /* Given a REG, X, compute which bits in X can be nonzero.
9403 We don't care about bits outside of those defined in MODE.
9405 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9406 a shift, AND, or zero_extract, we can do better. */
9409 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9410 const_rtx known_x ATTRIBUTE_UNUSED
,
9411 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9412 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9413 unsigned HOST_WIDE_INT
*nonzero
)
9418 /* If X is a register whose nonzero bits value is current, use it.
9419 Otherwise, if X is a register whose value we can find, use that
9420 value. Otherwise, use the previously-computed global nonzero bits
9421 for this register. */
9423 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9424 if (rsp
->last_set_value
!= 0
9425 && (rsp
->last_set_mode
== mode
9426 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9427 && GET_MODE_CLASS (mode
) == MODE_INT
))
9428 && ((rsp
->last_set_label
>= label_tick_ebb_start
9429 && rsp
->last_set_label
< label_tick
)
9430 || (rsp
->last_set_label
== label_tick
9431 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9432 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9433 && REG_N_SETS (REGNO (x
)) == 1
9435 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9437 *nonzero
&= rsp
->last_set_nonzero_bits
;
9441 tem
= get_last_value (x
);
9445 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9446 /* If X is narrower than MODE and TEM is a non-negative
9447 constant that would appear negative in the mode of X,
9448 sign-extend it for use in reg_nonzero_bits because some
9449 machines (maybe most) will actually do the sign-extension
9450 and this is the conservative approach.
9452 ??? For 2.5, try to tighten up the MD files in this regard
9453 instead of this kludge. */
9455 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
9456 && CONST_INT_P (tem
)
9458 && 0 != (UINTVAL (tem
)
9459 & ((unsigned HOST_WIDE_INT
) 1
9460 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
9461 tem
= GEN_INT (UINTVAL (tem
)
9462 | ((unsigned HOST_WIDE_INT
) (-1)
9463 << GET_MODE_BITSIZE (GET_MODE (x
))));
9467 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9469 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9471 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
9472 /* We don't know anything about the upper bits. */
9473 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9480 /* Return the number of bits at the high-order end of X that are known to
9481 be equal to the sign bit. X will be used in mode MODE; if MODE is
9482 VOIDmode, X will be used in its own mode. The returned value will always
9483 be between 1 and the number of bits in MODE. */
9486 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9487 const_rtx known_x ATTRIBUTE_UNUSED
,
9488 enum machine_mode known_mode
9490 unsigned int known_ret ATTRIBUTE_UNUSED
,
9491 unsigned int *result
)
9496 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9497 if (rsp
->last_set_value
!= 0
9498 && rsp
->last_set_mode
== mode
9499 && ((rsp
->last_set_label
>= label_tick_ebb_start
9500 && rsp
->last_set_label
< label_tick
)
9501 || (rsp
->last_set_label
== label_tick
9502 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9503 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9504 && REG_N_SETS (REGNO (x
)) == 1
9506 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9508 *result
= rsp
->last_set_sign_bit_copies
;
9512 tem
= get_last_value (x
);
9516 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9517 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
9518 *result
= rsp
->sign_bit_copies
;
9523 /* Return the number of "extended" bits there are in X, when interpreted
9524 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9525 unsigned quantities, this is the number of high-order zero bits.
9526 For signed quantities, this is the number of copies of the sign bit
9527 minus 1. In both case, this function returns the number of "spare"
9528 bits. For example, if two quantities for which this function returns
9529 at least 1 are added, the addition is known not to overflow.
9531 This function will always return 0 unless called during combine, which
9532 implies that it must be called from a define_split. */
9535 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9537 if (nonzero_sign_valid
== 0)
9541 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9542 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9543 - floor_log2 (nonzero_bits (x
, mode
)))
9545 : num_sign_bit_copies (x
, mode
) - 1);
9548 /* This function is called from `simplify_shift_const' to merge two
9549 outer operations. Specifically, we have already found that we need
9550 to perform operation *POP0 with constant *PCONST0 at the outermost
9551 position. We would now like to also perform OP1 with constant CONST1
9552 (with *POP0 being done last).
9554 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9555 the resulting operation. *PCOMP_P is set to 1 if we would need to
9556 complement the innermost operand, otherwise it is unchanged.
9558 MODE is the mode in which the operation will be done. No bits outside
9559 the width of this mode matter. It is assumed that the width of this mode
9560 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9562 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9563 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9564 result is simply *PCONST0.
9566 If the resulting operation cannot be expressed as one operation, we
9567 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9570 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9572 enum rtx_code op0
= *pop0
;
9573 HOST_WIDE_INT const0
= *pconst0
;
9575 const0
&= GET_MODE_MASK (mode
);
9576 const1
&= GET_MODE_MASK (mode
);
9578 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9582 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9585 if (op1
== UNKNOWN
|| op0
== SET
)
9588 else if (op0
== UNKNOWN
)
9589 op0
= op1
, const0
= const1
;
9591 else if (op0
== op1
)
9615 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9616 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9619 /* If the two constants aren't the same, we can't do anything. The
9620 remaining six cases can all be done. */
9621 else if (const0
!= const1
)
9629 /* (a & b) | b == b */
9631 else /* op1 == XOR */
9632 /* (a ^ b) | b == a | b */
9638 /* (a & b) ^ b == (~a) & b */
9639 op0
= AND
, *pcomp_p
= 1;
9640 else /* op1 == IOR */
9641 /* (a | b) ^ b == a & ~b */
9642 op0
= AND
, const0
= ~const0
;
9647 /* (a | b) & b == b */
9649 else /* op1 == XOR */
9650 /* (a ^ b) & b) == (~a) & b */
9657 /* Check for NO-OP cases. */
9658 const0
&= GET_MODE_MASK (mode
);
9660 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9662 else if (const0
== 0 && op0
== AND
)
9664 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9670 /* ??? Slightly redundant with the above mask, but not entirely.
9671 Moving this above means we'd have to sign-extend the mode mask
9672 for the final test. */
9673 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9674 *pconst0
= trunc_int_for_mode (const0
, mode
);
9679 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9680 the shift in. The original shift operation CODE is performed on OP in
9681 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9682 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9683 result of the shift is subject to operation OUTER_CODE with operand
9686 static enum machine_mode
9687 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9688 enum machine_mode orig_mode
, enum machine_mode mode
,
9689 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9691 if (orig_mode
== mode
)
9693 gcc_assert (GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (orig_mode
));
9695 /* In general we can't perform in wider mode for right shift and rotate. */
9699 /* We can still widen if the bits brought in from the left are identical
9700 to the sign bit of ORIG_MODE. */
9701 if (num_sign_bit_copies (op
, mode
)
9702 > (unsigned) (GET_MODE_BITSIZE (mode
)
9703 - GET_MODE_BITSIZE (orig_mode
)))
9708 /* Similarly here but with zero bits. */
9709 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9710 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9713 /* We can also widen if the bits brought in will be masked off. This
9714 operation is performed in ORIG_MODE. */
9715 if (outer_code
== AND
)
9717 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9720 && GET_MODE_BITSIZE (orig_mode
) - care_bits
>= count
)
9736 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9737 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9738 simplify it. Otherwise, return a simplified value.
9740 The shift is normally computed in the widest mode we find in VAROP, as
9741 long as it isn't a different number of words than RESULT_MODE. Exceptions
9742 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9745 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9746 rtx varop
, int orig_count
)
9748 enum rtx_code orig_code
= code
;
9749 rtx orig_varop
= varop
;
9751 enum machine_mode mode
= result_mode
;
9752 enum machine_mode shift_mode
, tmode
;
9753 unsigned int mode_words
9754 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9755 /* We form (outer_op (code varop count) (outer_const)). */
9756 enum rtx_code outer_op
= UNKNOWN
;
9757 HOST_WIDE_INT outer_const
= 0;
9758 int complement_p
= 0;
9761 /* Make sure and truncate the "natural" shift on the way in. We don't
9762 want to do this inside the loop as it makes it more difficult to
9764 if (SHIFT_COUNT_TRUNCATED
)
9765 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9767 /* If we were given an invalid count, don't do anything except exactly
9768 what was requested. */
9770 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9775 /* Unless one of the branches of the `if' in this loop does a `continue',
9776 we will `break' the loop after the `if'. */
9780 /* If we have an operand of (clobber (const_int 0)), fail. */
9781 if (GET_CODE (varop
) == CLOBBER
)
9784 /* Convert ROTATERT to ROTATE. */
9785 if (code
== ROTATERT
)
9787 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9789 if (VECTOR_MODE_P (result_mode
))
9790 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9792 count
= bitsize
- count
;
9795 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9796 mode
, outer_op
, outer_const
);
9798 /* Handle cases where the count is greater than the size of the mode
9799 minus 1. For ASHIFT, use the size minus one as the count (this can
9800 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9801 take the count modulo the size. For other shifts, the result is
9804 Since these shifts are being produced by the compiler by combining
9805 multiple operations, each of which are defined, we know what the
9806 result is supposed to be. */
9808 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9810 if (code
== ASHIFTRT
)
9811 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9812 else if (code
== ROTATE
|| code
== ROTATERT
)
9813 count
%= GET_MODE_BITSIZE (shift_mode
);
9816 /* We can't simply return zero because there may be an
9824 /* If we discovered we had to complement VAROP, leave. Making a NOT
9825 here would cause an infinite loop. */
9829 /* An arithmetic right shift of a quantity known to be -1 or 0
9831 if (code
== ASHIFTRT
9832 && (num_sign_bit_copies (varop
, shift_mode
)
9833 == GET_MODE_BITSIZE (shift_mode
)))
9839 /* If we are doing an arithmetic right shift and discarding all but
9840 the sign bit copies, this is equivalent to doing a shift by the
9841 bitsize minus one. Convert it into that shift because it will often
9842 allow other simplifications. */
9844 if (code
== ASHIFTRT
9845 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9846 >= GET_MODE_BITSIZE (shift_mode
)))
9847 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9849 /* We simplify the tests below and elsewhere by converting
9850 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9851 `make_compound_operation' will convert it to an ASHIFTRT for
9852 those machines (such as VAX) that don't have an LSHIFTRT. */
9853 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9855 && ((nonzero_bits (varop
, shift_mode
)
9856 & ((unsigned HOST_WIDE_INT
) 1
9857 << (GET_MODE_BITSIZE (shift_mode
) - 1))) == 0))
9860 if (((code
== LSHIFTRT
9861 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9862 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9864 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9865 && !((nonzero_bits (varop
, shift_mode
) << count
)
9866 & GET_MODE_MASK (shift_mode
))))
9867 && !side_effects_p (varop
))
9870 switch (GET_CODE (varop
))
9876 new_rtx
= expand_compound_operation (varop
);
9877 if (new_rtx
!= varop
)
9885 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9886 minus the width of a smaller mode, we can do this with a
9887 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9888 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9889 && ! mode_dependent_address_p (XEXP (varop
, 0))
9890 && ! MEM_VOLATILE_P (varop
)
9891 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9892 MODE_INT
, 1)) != BLKmode
)
9894 new_rtx
= adjust_address_nv (varop
, tmode
,
9895 BYTES_BIG_ENDIAN
? 0
9896 : count
/ BITS_PER_UNIT
);
9898 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9899 : ZERO_EXTEND
, mode
, new_rtx
);
9906 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9907 the same number of words as what we've seen so far. Then store
9908 the widest mode in MODE. */
9909 if (subreg_lowpart_p (varop
)
9910 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9911 > GET_MODE_SIZE (GET_MODE (varop
)))
9912 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9913 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9915 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9916 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9918 varop
= SUBREG_REG (varop
);
9919 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9920 mode
= GET_MODE (varop
);
9926 /* Some machines use MULT instead of ASHIFT because MULT
9927 is cheaper. But it is still better on those machines to
9928 merge two shifts into one. */
9929 if (CONST_INT_P (XEXP (varop
, 1))
9930 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9933 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9935 GEN_INT (exact_log2 (
9936 UINTVAL (XEXP (varop
, 1)))));
9942 /* Similar, for when divides are cheaper. */
9943 if (CONST_INT_P (XEXP (varop
, 1))
9944 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9947 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9949 GEN_INT (exact_log2 (
9950 UINTVAL (XEXP (varop
, 1)))));
9956 /* If we are extracting just the sign bit of an arithmetic
9957 right shift, that shift is not needed. However, the sign
9958 bit of a wider mode may be different from what would be
9959 interpreted as the sign bit in a narrower mode, so, if
9960 the result is narrower, don't discard the shift. */
9961 if (code
== LSHIFTRT
9962 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9963 && (GET_MODE_BITSIZE (result_mode
)
9964 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9966 varop
= XEXP (varop
, 0);
9970 /* ... fall through ... */
9975 /* Here we have two nested shifts. The result is usually the
9976 AND of a new shift with a mask. We compute the result below. */
9977 if (CONST_INT_P (XEXP (varop
, 1))
9978 && INTVAL (XEXP (varop
, 1)) >= 0
9979 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9980 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9981 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9982 && !VECTOR_MODE_P (result_mode
))
9984 enum rtx_code first_code
= GET_CODE (varop
);
9985 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9986 unsigned HOST_WIDE_INT mask
;
9989 /* We have one common special case. We can't do any merging if
9990 the inner code is an ASHIFTRT of a smaller mode. However, if
9991 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9992 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9993 we can convert it to
9994 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9995 This simplifies certain SIGN_EXTEND operations. */
9996 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9997 && count
== (GET_MODE_BITSIZE (result_mode
)
9998 - GET_MODE_BITSIZE (GET_MODE (varop
))))
10000 /* C3 has the low-order C1 bits zero. */
10002 mask
= GET_MODE_MASK (mode
)
10003 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10005 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10006 XEXP (varop
, 0), mask
);
10007 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10009 count
= first_count
;
10014 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10015 than C1 high-order bits equal to the sign bit, we can convert
10016 this to either an ASHIFT or an ASHIFTRT depending on the
10019 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10021 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10022 && GET_MODE (varop
) == shift_mode
10023 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10026 varop
= XEXP (varop
, 0);
10027 count
-= first_count
;
10037 /* There are some cases we can't do. If CODE is ASHIFTRT,
10038 we can only do this if FIRST_CODE is also ASHIFTRT.
10040 We can't do the case when CODE is ROTATE and FIRST_CODE is
10043 If the mode of this shift is not the mode of the outer shift,
10044 we can't do this if either shift is a right shift or ROTATE.
10046 Finally, we can't do any of these if the mode is too wide
10047 unless the codes are the same.
10049 Handle the case where the shift codes are the same
10052 if (code
== first_code
)
10054 if (GET_MODE (varop
) != result_mode
10055 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10056 || code
== ROTATE
))
10059 count
+= first_count
;
10060 varop
= XEXP (varop
, 0);
10064 if (code
== ASHIFTRT
10065 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10066 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
10067 || (GET_MODE (varop
) != result_mode
10068 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10069 || first_code
== ROTATE
10070 || code
== ROTATE
)))
10073 /* To compute the mask to apply after the shift, shift the
10074 nonzero bits of the inner shift the same way the
10075 outer shift will. */
10077 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10080 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10083 /* Give up if we can't compute an outer operation to use. */
10085 || !CONST_INT_P (mask_rtx
)
10086 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10088 result_mode
, &complement_p
))
10091 /* If the shifts are in the same direction, we add the
10092 counts. Otherwise, we subtract them. */
10093 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10094 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10095 count
+= first_count
;
10097 count
-= first_count
;
10099 /* If COUNT is positive, the new shift is usually CODE,
10100 except for the two exceptions below, in which case it is
10101 FIRST_CODE. If the count is negative, FIRST_CODE should
10104 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10105 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10107 else if (count
< 0)
10108 code
= first_code
, count
= -count
;
10110 varop
= XEXP (varop
, 0);
10114 /* If we have (A << B << C) for any shift, we can convert this to
10115 (A << C << B). This wins if A is a constant. Only try this if
10116 B is not a constant. */
10118 else if (GET_CODE (varop
) == code
10119 && CONST_INT_P (XEXP (varop
, 0))
10120 && !CONST_INT_P (XEXP (varop
, 1)))
10122 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10125 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10132 if (VECTOR_MODE_P (mode
))
10135 /* Make this fit the case below. */
10136 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
10137 GEN_INT (GET_MODE_MASK (mode
)));
10143 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10144 with C the size of VAROP - 1 and the shift is logical if
10145 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10146 we have an (le X 0) operation. If we have an arithmetic shift
10147 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10148 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10150 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10151 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10152 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10153 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10154 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10155 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10158 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10161 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10162 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10167 /* If we have (shift (logical)), move the logical to the outside
10168 to allow it to possibly combine with another logical and the
10169 shift to combine with another shift. This also canonicalizes to
10170 what a ZERO_EXTRACT looks like. Also, some machines have
10171 (and (shift)) insns. */
10173 if (CONST_INT_P (XEXP (varop
, 1))
10174 /* We can't do this if we have (ashiftrt (xor)) and the
10175 constant has its sign bit set in shift_mode. */
10176 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10177 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10179 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10181 GEN_INT (count
))) != 0
10182 && CONST_INT_P (new_rtx
)
10183 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10184 INTVAL (new_rtx
), result_mode
, &complement_p
))
10186 varop
= XEXP (varop
, 0);
10190 /* If we can't do that, try to simplify the shift in each arm of the
10191 logical expression, make a new logical expression, and apply
10192 the inverse distributive law. This also can't be done
10193 for some (ashiftrt (xor)). */
10194 if (CONST_INT_P (XEXP (varop
, 1))
10195 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10196 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10199 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10200 XEXP (varop
, 0), count
);
10201 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10202 XEXP (varop
, 1), count
);
10204 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10206 varop
= apply_distributive_law (varop
);
10214 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10215 says that the sign bit can be tested, FOO has mode MODE, C is
10216 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10217 that may be nonzero. */
10218 if (code
== LSHIFTRT
10219 && XEXP (varop
, 1) == const0_rtx
10220 && GET_MODE (XEXP (varop
, 0)) == result_mode
10221 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10222 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10223 && STORE_FLAG_VALUE
== -1
10224 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10225 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10228 varop
= XEXP (varop
, 0);
10235 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10236 than the number of bits in the mode is equivalent to A. */
10237 if (code
== LSHIFTRT
10238 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10239 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10241 varop
= XEXP (varop
, 0);
10246 /* NEG commutes with ASHIFT since it is multiplication. Move the
10247 NEG outside to allow shifts to combine. */
10249 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10252 varop
= XEXP (varop
, 0);
10258 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10259 is one less than the number of bits in the mode is
10260 equivalent to (xor A 1). */
10261 if (code
== LSHIFTRT
10262 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10263 && XEXP (varop
, 1) == constm1_rtx
10264 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10265 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10269 varop
= XEXP (varop
, 0);
10273 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10274 that might be nonzero in BAR are those being shifted out and those
10275 bits are known zero in FOO, we can replace the PLUS with FOO.
10276 Similarly in the other operand order. This code occurs when
10277 we are computing the size of a variable-size array. */
10279 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10280 && count
< HOST_BITS_PER_WIDE_INT
10281 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10282 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10283 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10285 varop
= XEXP (varop
, 0);
10288 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10289 && count
< HOST_BITS_PER_WIDE_INT
10290 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10291 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10293 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10294 & nonzero_bits (XEXP (varop
, 1),
10297 varop
= XEXP (varop
, 1);
10301 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10303 && CONST_INT_P (XEXP (varop
, 1))
10304 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10306 GEN_INT (count
))) != 0
10307 && CONST_INT_P (new_rtx
)
10308 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10309 INTVAL (new_rtx
), result_mode
, &complement_p
))
10311 varop
= XEXP (varop
, 0);
10315 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10316 signbit', and attempt to change the PLUS to an XOR and move it to
10317 the outer operation as is done above in the AND/IOR/XOR case
10318 leg for shift(logical). See details in logical handling above
10319 for reasoning in doing so. */
10320 if (code
== LSHIFTRT
10321 && CONST_INT_P (XEXP (varop
, 1))
10322 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10323 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10325 GEN_INT (count
))) != 0
10326 && CONST_INT_P (new_rtx
)
10327 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10328 INTVAL (new_rtx
), result_mode
, &complement_p
))
10330 varop
= XEXP (varop
, 0);
10337 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10338 with C the size of VAROP - 1 and the shift is logical if
10339 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10340 we have a (gt X 0) operation. If the shift is arithmetic with
10341 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10342 we have a (neg (gt X 0)) operation. */
10344 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10345 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10346 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10347 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10348 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10349 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10350 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10353 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10356 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10357 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10364 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10365 if the truncate does not affect the value. */
10366 if (code
== LSHIFTRT
10367 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10368 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10369 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10370 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
10371 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
10373 rtx varop_inner
= XEXP (varop
, 0);
10376 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10377 XEXP (varop_inner
, 0),
10379 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10380 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10393 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10394 outer_op
, outer_const
);
10396 /* We have now finished analyzing the shift. The result should be
10397 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10398 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10399 to the result of the shift. OUTER_CONST is the relevant constant,
10400 but we must turn off all bits turned off in the shift. */
10402 if (outer_op
== UNKNOWN
10403 && orig_code
== code
&& orig_count
== count
10404 && varop
== orig_varop
10405 && shift_mode
== GET_MODE (varop
))
10408 /* Make a SUBREG if necessary. If we can't make it, fail. */
10409 varop
= gen_lowpart (shift_mode
, varop
);
10410 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10413 /* If we have an outer operation and we just made a shift, it is
10414 possible that we could have simplified the shift were it not
10415 for the outer operation. So try to do the simplification
10418 if (outer_op
!= UNKNOWN
)
10419 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10424 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10426 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10427 turn off all the bits that the shift would have turned off. */
10428 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10429 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10430 GET_MODE_MASK (result_mode
) >> orig_count
);
10432 /* Do the remainder of the processing in RESULT_MODE. */
10433 x
= gen_lowpart_or_truncate (result_mode
, x
);
10435 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10438 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10440 if (outer_op
!= UNKNOWN
)
10442 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10443 && GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10444 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10446 if (outer_op
== AND
)
10447 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10448 else if (outer_op
== SET
)
10450 /* This means that we have determined that the result is
10451 equivalent to a constant. This should be rare. */
10452 if (!side_effects_p (x
))
10453 x
= GEN_INT (outer_const
);
10455 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10456 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10458 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10459 GEN_INT (outer_const
));
10465 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10466 The result of the shift is RESULT_MODE. If we cannot simplify it,
10467 return X or, if it is NULL, synthesize the expression with
10468 simplify_gen_binary. Otherwise, return a simplified value.
10470 The shift is normally computed in the widest mode we find in VAROP, as
10471 long as it isn't a different number of words than RESULT_MODE. Exceptions
10472 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10475 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10476 rtx varop
, int count
)
10478 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10483 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10484 if (GET_MODE (x
) != result_mode
)
10485 x
= gen_lowpart (result_mode
, x
);
10490 /* Like recog, but we receive the address of a pointer to a new pattern.
10491 We try to match the rtx that the pointer points to.
10492 If that fails, we may try to modify or replace the pattern,
10493 storing the replacement into the same pointer object.
10495 Modifications include deletion or addition of CLOBBERs.
10497 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10498 the CLOBBERs are placed.
10500 The value is the final insn code from the pattern ultimately matched,
10504 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10506 rtx pat
= *pnewpat
;
10507 int insn_code_number
;
10508 int num_clobbers_to_add
= 0;
10511 rtx old_notes
, old_pat
;
10513 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10514 we use to indicate that something didn't match. If we find such a
10515 thing, force rejection. */
10516 if (GET_CODE (pat
) == PARALLEL
)
10517 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10518 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10519 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10522 old_pat
= PATTERN (insn
);
10523 old_notes
= REG_NOTES (insn
);
10524 PATTERN (insn
) = pat
;
10525 REG_NOTES (insn
) = 0;
10527 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10528 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10530 if (insn_code_number
< 0)
10531 fputs ("Failed to match this instruction:\n", dump_file
);
10533 fputs ("Successfully matched this instruction:\n", dump_file
);
10534 print_rtl_single (dump_file
, pat
);
10537 /* If it isn't, there is the possibility that we previously had an insn
10538 that clobbered some register as a side effect, but the combined
10539 insn doesn't need to do that. So try once more without the clobbers
10540 unless this represents an ASM insn. */
10542 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10543 && GET_CODE (pat
) == PARALLEL
)
10547 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10548 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10551 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10555 SUBST_INT (XVECLEN (pat
, 0), pos
);
10558 pat
= XVECEXP (pat
, 0, 0);
10560 PATTERN (insn
) = pat
;
10561 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10562 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10564 if (insn_code_number
< 0)
10565 fputs ("Failed to match this instruction:\n", dump_file
);
10567 fputs ("Successfully matched this instruction:\n", dump_file
);
10568 print_rtl_single (dump_file
, pat
);
10571 PATTERN (insn
) = old_pat
;
10572 REG_NOTES (insn
) = old_notes
;
10574 /* Recognize all noop sets, these will be killed by followup pass. */
10575 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10576 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10578 /* If we had any clobbers to add, make a new pattern than contains
10579 them. Then check to make sure that all of them are dead. */
10580 if (num_clobbers_to_add
)
10582 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10583 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10584 ? (XVECLEN (pat
, 0)
10585 + num_clobbers_to_add
)
10586 : num_clobbers_to_add
+ 1));
10588 if (GET_CODE (pat
) == PARALLEL
)
10589 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10590 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10592 XVECEXP (newpat
, 0, 0) = pat
;
10594 add_clobbers (newpat
, insn_code_number
);
10596 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10597 i
< XVECLEN (newpat
, 0); i
++)
10599 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10600 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10602 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10604 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10605 notes
= alloc_reg_note (REG_UNUSED
,
10606 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10615 return insn_code_number
;
10618 /* Like gen_lowpart_general but for use by combine. In combine it
10619 is not possible to create any new pseudoregs. However, it is
10620 safe to create invalid memory addresses, because combine will
10621 try to recognize them and all they will do is make the combine
10624 If for some reason this cannot do its job, an rtx
10625 (clobber (const_int 0)) is returned.
10626 An insn containing that will not be recognized. */
10629 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10631 enum machine_mode imode
= GET_MODE (x
);
10632 unsigned int osize
= GET_MODE_SIZE (omode
);
10633 unsigned int isize
= GET_MODE_SIZE (imode
);
10636 if (omode
== imode
)
10639 /* Return identity if this is a CONST or symbolic reference. */
10641 && (GET_CODE (x
) == CONST
10642 || GET_CODE (x
) == SYMBOL_REF
10643 || GET_CODE (x
) == LABEL_REF
))
10646 /* We can only support MODE being wider than a word if X is a
10647 constant integer or has a mode the same size. */
10648 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10649 && ! ((imode
== VOIDmode
10650 && (CONST_INT_P (x
)
10651 || GET_CODE (x
) == CONST_DOUBLE
))
10652 || isize
== osize
))
10655 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10656 won't know what to do. So we will strip off the SUBREG here and
10657 process normally. */
10658 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10660 x
= SUBREG_REG (x
);
10662 /* For use in case we fall down into the address adjustments
10663 further below, we need to adjust the known mode and size of
10664 x; imode and isize, since we just adjusted x. */
10665 imode
= GET_MODE (x
);
10667 if (imode
== omode
)
10670 isize
= GET_MODE_SIZE (imode
);
10673 result
= gen_lowpart_common (omode
, x
);
10682 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10684 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10687 /* If we want to refer to something bigger than the original memref,
10688 generate a paradoxical subreg instead. That will force a reload
10689 of the original memref X. */
10691 return gen_rtx_SUBREG (omode
, x
, 0);
10693 if (WORDS_BIG_ENDIAN
)
10694 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10696 /* Adjust the address so that the address-after-the-data is
10698 if (BYTES_BIG_ENDIAN
)
10699 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10701 return adjust_address_nv (x
, omode
, offset
);
10704 /* If X is a comparison operator, rewrite it in a new mode. This
10705 probably won't match, but may allow further simplifications. */
10706 else if (COMPARISON_P (x
))
10707 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10709 /* If we couldn't simplify X any other way, just enclose it in a
10710 SUBREG. Normally, this SUBREG won't match, but some patterns may
10711 include an explicit SUBREG or we may simplify it further in combine. */
10717 offset
= subreg_lowpart_offset (omode
, imode
);
10718 if (imode
== VOIDmode
)
10720 imode
= int_mode_for_mode (omode
);
10721 x
= gen_lowpart_common (imode
, x
);
10725 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10731 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10734 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10735 comparison code that will be tested.
10737 The result is a possibly different comparison code to use. *POP0 and
10738 *POP1 may be updated.
10740 It is possible that we might detect that a comparison is either always
10741 true or always false. However, we do not perform general constant
10742 folding in combine, so this knowledge isn't useful. Such tautologies
10743 should have been detected earlier. Hence we ignore all such cases. */
10745 static enum rtx_code
10746 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10752 enum machine_mode mode
, tmode
;
10754 /* Try a few ways of applying the same transformation to both operands. */
10757 #ifndef WORD_REGISTER_OPERATIONS
10758 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10759 so check specially. */
10760 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10761 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10762 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10763 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10764 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10765 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10766 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10767 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10768 && CONST_INT_P (XEXP (op0
, 1))
10769 && XEXP (op0
, 1) == XEXP (op1
, 1)
10770 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10771 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10772 && (INTVAL (XEXP (op0
, 1))
10773 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10774 - (GET_MODE_BITSIZE
10775 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10777 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10778 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10782 /* If both operands are the same constant shift, see if we can ignore the
10783 shift. We can if the shift is a rotate or if the bits shifted out of
10784 this shift are known to be zero for both inputs and if the type of
10785 comparison is compatible with the shift. */
10786 if (GET_CODE (op0
) == GET_CODE (op1
)
10787 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10788 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10789 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10790 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10791 || (GET_CODE (op0
) == ASHIFTRT
10792 && (code
!= GTU
&& code
!= LTU
10793 && code
!= GEU
&& code
!= LEU
)))
10794 && CONST_INT_P (XEXP (op0
, 1))
10795 && INTVAL (XEXP (op0
, 1)) >= 0
10796 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10797 && XEXP (op0
, 1) == XEXP (op1
, 1))
10799 enum machine_mode mode
= GET_MODE (op0
);
10800 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10801 int shift_count
= INTVAL (XEXP (op0
, 1));
10803 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10804 mask
&= (mask
>> shift_count
) << shift_count
;
10805 else if (GET_CODE (op0
) == ASHIFT
)
10806 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10808 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10809 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10810 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10815 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10816 SUBREGs are of the same mode, and, in both cases, the AND would
10817 be redundant if the comparison was done in the narrower mode,
10818 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10819 and the operand's possibly nonzero bits are 0xffffff01; in that case
10820 if we only care about QImode, we don't need the AND). This case
10821 occurs if the output mode of an scc insn is not SImode and
10822 STORE_FLAG_VALUE == 1 (e.g., the 386).
10824 Similarly, check for a case where the AND's are ZERO_EXTEND
10825 operations from some narrower mode even though a SUBREG is not
10828 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10829 && CONST_INT_P (XEXP (op0
, 1))
10830 && CONST_INT_P (XEXP (op1
, 1)))
10832 rtx inner_op0
= XEXP (op0
, 0);
10833 rtx inner_op1
= XEXP (op1
, 0);
10834 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10835 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10838 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10839 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10840 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10841 && (GET_MODE (SUBREG_REG (inner_op0
))
10842 == GET_MODE (SUBREG_REG (inner_op1
)))
10843 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10844 <= HOST_BITS_PER_WIDE_INT
)
10845 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10846 GET_MODE (SUBREG_REG (inner_op0
)))))
10847 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10848 GET_MODE (SUBREG_REG (inner_op1
))))))
10850 op0
= SUBREG_REG (inner_op0
);
10851 op1
= SUBREG_REG (inner_op1
);
10853 /* The resulting comparison is always unsigned since we masked
10854 off the original sign bit. */
10855 code
= unsigned_condition (code
);
10861 for (tmode
= GET_CLASS_NARROWEST_MODE
10862 (GET_MODE_CLASS (GET_MODE (op0
)));
10863 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10864 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10866 op0
= gen_lowpart (tmode
, inner_op0
);
10867 op1
= gen_lowpart (tmode
, inner_op1
);
10868 code
= unsigned_condition (code
);
10877 /* If both operands are NOT, we can strip off the outer operation
10878 and adjust the comparison code for swapped operands; similarly for
10879 NEG, except that this must be an equality comparison. */
10880 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10881 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10882 && (code
== EQ
|| code
== NE
)))
10883 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10889 /* If the first operand is a constant, swap the operands and adjust the
10890 comparison code appropriately, but don't do this if the second operand
10891 is already a constant integer. */
10892 if (swap_commutative_operands_p (op0
, op1
))
10894 tem
= op0
, op0
= op1
, op1
= tem
;
10895 code
= swap_condition (code
);
10898 /* We now enter a loop during which we will try to simplify the comparison.
10899 For the most part, we only are concerned with comparisons with zero,
10900 but some things may really be comparisons with zero but not start
10901 out looking that way. */
10903 while (CONST_INT_P (op1
))
10905 enum machine_mode mode
= GET_MODE (op0
);
10906 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10907 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10908 int equality_comparison_p
;
10909 int sign_bit_comparison_p
;
10910 int unsigned_comparison_p
;
10911 HOST_WIDE_INT const_op
;
10913 /* We only want to handle integral modes. This catches VOIDmode,
10914 CCmode, and the floating-point modes. An exception is that we
10915 can handle VOIDmode if OP0 is a COMPARE or a comparison
10918 if (GET_MODE_CLASS (mode
) != MODE_INT
10919 && ! (mode
== VOIDmode
10920 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10923 /* Get the constant we are comparing against and turn off all bits
10924 not on in our mode. */
10925 const_op
= INTVAL (op1
);
10926 if (mode
!= VOIDmode
)
10927 const_op
= trunc_int_for_mode (const_op
, mode
);
10928 op1
= GEN_INT (const_op
);
10930 /* If we are comparing against a constant power of two and the value
10931 being compared can only have that single bit nonzero (e.g., it was
10932 `and'ed with that bit), we can replace this with a comparison
10935 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10936 || code
== LT
|| code
== LTU
)
10937 && mode_width
<= HOST_BITS_PER_WIDE_INT
10938 && exact_log2 (const_op
) >= 0
10939 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10941 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10942 op1
= const0_rtx
, const_op
= 0;
10945 /* Similarly, if we are comparing a value known to be either -1 or
10946 0 with -1, change it to the opposite comparison against zero. */
10949 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10950 || code
== GEU
|| code
== LTU
)
10951 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10953 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10954 op1
= const0_rtx
, const_op
= 0;
10957 /* Do some canonicalizations based on the comparison code. We prefer
10958 comparisons against zero and then prefer equality comparisons.
10959 If we can reduce the size of a constant, we will do that too. */
10964 /* < C is equivalent to <= (C - 1) */
10968 op1
= GEN_INT (const_op
);
10970 /* ... fall through to LE case below. */
10976 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10980 op1
= GEN_INT (const_op
);
10984 /* If we are doing a <= 0 comparison on a value known to have
10985 a zero sign bit, we can replace this with == 0. */
10986 else if (const_op
== 0
10987 && mode_width
<= HOST_BITS_PER_WIDE_INT
10988 && (nonzero_bits (op0
, mode
)
10989 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10995 /* >= C is equivalent to > (C - 1). */
10999 op1
= GEN_INT (const_op
);
11001 /* ... fall through to GT below. */
11007 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11011 op1
= GEN_INT (const_op
);
11015 /* If we are doing a > 0 comparison on a value known to have
11016 a zero sign bit, we can replace this with != 0. */
11017 else if (const_op
== 0
11018 && mode_width
<= HOST_BITS_PER_WIDE_INT
11019 && (nonzero_bits (op0
, mode
)
11020 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11026 /* < C is equivalent to <= (C - 1). */
11030 op1
= GEN_INT (const_op
);
11032 /* ... fall through ... */
11035 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11036 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11037 && (unsigned HOST_WIDE_INT
) const_op
11038 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11040 const_op
= 0, op1
= const0_rtx
;
11048 /* unsigned <= 0 is equivalent to == 0 */
11052 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11053 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11054 && (unsigned HOST_WIDE_INT
) const_op
11055 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11057 const_op
= 0, op1
= const0_rtx
;
11063 /* >= C is equivalent to > (C - 1). */
11067 op1
= GEN_INT (const_op
);
11069 /* ... fall through ... */
11072 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11073 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11074 && (unsigned HOST_WIDE_INT
) const_op
11075 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11077 const_op
= 0, op1
= const0_rtx
;
11085 /* unsigned > 0 is equivalent to != 0 */
11089 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11090 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11091 && (unsigned HOST_WIDE_INT
) const_op
11092 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11094 const_op
= 0, op1
= const0_rtx
;
11103 /* Compute some predicates to simplify code below. */
11105 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11106 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11107 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11110 /* If this is a sign bit comparison and we can do arithmetic in
11111 MODE, say that we will only be needing the sign bit of OP0. */
11112 if (sign_bit_comparison_p
11113 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11114 op0
= force_to_mode (op0
, mode
,
11115 (unsigned HOST_WIDE_INT
) 1
11116 << (GET_MODE_BITSIZE (mode
) - 1),
11119 /* Now try cases based on the opcode of OP0. If none of the cases
11120 does a "continue", we exit this loop immediately after the
11123 switch (GET_CODE (op0
))
11126 /* If we are extracting a single bit from a variable position in
11127 a constant that has only a single bit set and are comparing it
11128 with zero, we can convert this into an equality comparison
11129 between the position and the location of the single bit. */
11130 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11131 have already reduced the shift count modulo the word size. */
11132 if (!SHIFT_COUNT_TRUNCATED
11133 && CONST_INT_P (XEXP (op0
, 0))
11134 && XEXP (op0
, 1) == const1_rtx
11135 && equality_comparison_p
&& const_op
== 0
11136 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11138 if (BITS_BIG_ENDIAN
)
11140 enum machine_mode new_mode
11141 = mode_for_extraction (EP_extzv
, 1);
11142 if (new_mode
== MAX_MACHINE_MODE
)
11143 i
= BITS_PER_WORD
- 1 - i
;
11147 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
11151 op0
= XEXP (op0
, 2);
11155 /* Result is nonzero iff shift count is equal to I. */
11156 code
= reverse_condition (code
);
11160 /* ... fall through ... */
11163 tem
= expand_compound_operation (op0
);
11172 /* If testing for equality, we can take the NOT of the constant. */
11173 if (equality_comparison_p
11174 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11176 op0
= XEXP (op0
, 0);
11181 /* If just looking at the sign bit, reverse the sense of the
11183 if (sign_bit_comparison_p
)
11185 op0
= XEXP (op0
, 0);
11186 code
= (code
== GE
? LT
: GE
);
11192 /* If testing for equality, we can take the NEG of the constant. */
11193 if (equality_comparison_p
11194 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11196 op0
= XEXP (op0
, 0);
11201 /* The remaining cases only apply to comparisons with zero. */
11205 /* When X is ABS or is known positive,
11206 (neg X) is < 0 if and only if X != 0. */
11208 if (sign_bit_comparison_p
11209 && (GET_CODE (XEXP (op0
, 0)) == ABS
11210 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11211 && (nonzero_bits (XEXP (op0
, 0), mode
)
11212 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11215 op0
= XEXP (op0
, 0);
11216 code
= (code
== LT
? NE
: EQ
);
11220 /* If we have NEG of something whose two high-order bits are the
11221 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11222 if (num_sign_bit_copies (op0
, mode
) >= 2)
11224 op0
= XEXP (op0
, 0);
11225 code
= swap_condition (code
);
11231 /* If we are testing equality and our count is a constant, we
11232 can perform the inverse operation on our RHS. */
11233 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11234 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11235 op1
, XEXP (op0
, 1))) != 0)
11237 op0
= XEXP (op0
, 0);
11242 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11243 a particular bit. Convert it to an AND of a constant of that
11244 bit. This will be converted into a ZERO_EXTRACT. */
11245 if (const_op
== 0 && sign_bit_comparison_p
11246 && CONST_INT_P (XEXP (op0
, 1))
11247 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11249 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11250 ((unsigned HOST_WIDE_INT
) 1
11252 - INTVAL (XEXP (op0
, 1)))));
11253 code
= (code
== LT
? NE
: EQ
);
11257 /* Fall through. */
11260 /* ABS is ignorable inside an equality comparison with zero. */
11261 if (const_op
== 0 && equality_comparison_p
)
11263 op0
= XEXP (op0
, 0);
11269 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11270 (compare FOO CONST) if CONST fits in FOO's mode and we
11271 are either testing inequality or have an unsigned
11272 comparison with ZERO_EXTEND or a signed comparison with
11273 SIGN_EXTEND. But don't do it if we don't have a compare
11274 insn of the given mode, since we'd have to revert it
11275 later on, and then we wouldn't know whether to sign- or
11277 mode
= GET_MODE (XEXP (op0
, 0));
11278 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11279 && ! unsigned_comparison_p
11280 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11281 && ((unsigned HOST_WIDE_INT
) const_op
11282 < (((unsigned HOST_WIDE_INT
) 1
11283 << (GET_MODE_BITSIZE (mode
) - 1))))
11284 && have_insn_for (COMPARE
, mode
))
11286 op0
= XEXP (op0
, 0);
11292 /* Check for the case where we are comparing A - C1 with C2, that is
11294 (subreg:MODE (plus (A) (-C1))) op (C2)
11296 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11297 comparison in the wider mode. One of the following two conditions
11298 must be true in order for this to be valid:
11300 1. The mode extension results in the same bit pattern being added
11301 on both sides and the comparison is equality or unsigned. As
11302 C2 has been truncated to fit in MODE, the pattern can only be
11305 2. The mode extension results in the sign bit being copied on
11308 The difficulty here is that we have predicates for A but not for
11309 (A - C1) so we need to check that C1 is within proper bounds so
11310 as to perturbate A as little as possible. */
11312 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11313 && subreg_lowpart_p (op0
)
11314 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
11315 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11316 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11318 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11319 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11320 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11323 && (unsigned HOST_WIDE_INT
) c1
11324 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11325 && (equality_comparison_p
|| unsigned_comparison_p
)
11326 /* (A - C1) zero-extends if it is positive and sign-extends
11327 if it is negative, C2 both zero- and sign-extends. */
11328 && ((0 == (nonzero_bits (a
, inner_mode
)
11329 & ~GET_MODE_MASK (mode
))
11331 /* (A - C1) sign-extends if it is positive and 1-extends
11332 if it is negative, C2 both sign- and 1-extends. */
11333 || (num_sign_bit_copies (a
, inner_mode
)
11334 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11337 || ((unsigned HOST_WIDE_INT
) c1
11338 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11339 /* (A - C1) always sign-extends, like C2. */
11340 && num_sign_bit_copies (a
, inner_mode
)
11341 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11342 - (mode_width
- 1))))
11344 op0
= SUBREG_REG (op0
);
11349 /* If the inner mode is narrower and we are extracting the low part,
11350 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11351 if (subreg_lowpart_p (op0
)
11352 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11353 /* Fall through */ ;
11357 /* ... fall through ... */
11360 mode
= GET_MODE (XEXP (op0
, 0));
11361 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11362 && (unsigned_comparison_p
|| equality_comparison_p
)
11363 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11364 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
11365 && have_insn_for (COMPARE
, mode
))
11367 op0
= XEXP (op0
, 0);
11373 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11374 this for equality comparisons due to pathological cases involving
11376 if (equality_comparison_p
11377 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11378 op1
, XEXP (op0
, 1))))
11380 op0
= XEXP (op0
, 0);
11385 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11386 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11387 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11389 op0
= XEXP (XEXP (op0
, 0), 0);
11390 code
= (code
== LT
? EQ
: NE
);
11396 /* We used to optimize signed comparisons against zero, but that
11397 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11398 arrive here as equality comparisons, or (GEU, LTU) are
11399 optimized away. No need to special-case them. */
11401 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11402 (eq B (minus A C)), whichever simplifies. We can only do
11403 this for equality comparisons due to pathological cases involving
11405 if (equality_comparison_p
11406 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11407 XEXP (op0
, 1), op1
)))
11409 op0
= XEXP (op0
, 0);
11414 if (equality_comparison_p
11415 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11416 XEXP (op0
, 0), op1
)))
11418 op0
= XEXP (op0
, 1);
11423 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11424 of bits in X minus 1, is one iff X > 0. */
11425 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11426 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11427 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11428 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11430 op0
= XEXP (op0
, 1);
11431 code
= (code
== GE
? LE
: GT
);
11437 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11438 if C is zero or B is a constant. */
11439 if (equality_comparison_p
11440 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11441 XEXP (op0
, 1), op1
)))
11443 op0
= XEXP (op0
, 0);
11450 case UNEQ
: case LTGT
:
11451 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11452 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11453 case UNORDERED
: case ORDERED
:
11454 /* We can't do anything if OP0 is a condition code value, rather
11455 than an actual data value. */
11457 || CC0_P (XEXP (op0
, 0))
11458 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11461 /* Get the two operands being compared. */
11462 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11463 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11465 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11467 /* Check for the cases where we simply want the result of the
11468 earlier test or the opposite of that result. */
11469 if (code
== NE
|| code
== EQ
11470 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
11471 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11472 && (STORE_FLAG_VALUE
11473 & (((unsigned HOST_WIDE_INT
) 1
11474 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
11475 && (code
== LT
|| code
== GE
)))
11477 enum rtx_code new_code
;
11478 if (code
== LT
|| code
== NE
)
11479 new_code
= GET_CODE (op0
);
11481 new_code
= reversed_comparison_code (op0
, NULL
);
11483 if (new_code
!= UNKNOWN
)
11494 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11496 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11497 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11498 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11500 op0
= XEXP (op0
, 1);
11501 code
= (code
== GE
? GT
: LE
);
11507 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11508 will be converted to a ZERO_EXTRACT later. */
11509 if (const_op
== 0 && equality_comparison_p
11510 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11511 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11513 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11514 XEXP (XEXP (op0
, 0), 1));
11515 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11519 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11520 zero and X is a comparison and C1 and C2 describe only bits set
11521 in STORE_FLAG_VALUE, we can compare with X. */
11522 if (const_op
== 0 && equality_comparison_p
11523 && mode_width
<= HOST_BITS_PER_WIDE_INT
11524 && CONST_INT_P (XEXP (op0
, 1))
11525 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11526 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11527 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11528 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11530 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11531 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11532 if ((~STORE_FLAG_VALUE
& mask
) == 0
11533 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11534 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11535 && COMPARISON_P (tem
))))
11537 op0
= XEXP (XEXP (op0
, 0), 0);
11542 /* If we are doing an equality comparison of an AND of a bit equal
11543 to the sign bit, replace this with a LT or GE comparison of
11544 the underlying value. */
11545 if (equality_comparison_p
11547 && CONST_INT_P (XEXP (op0
, 1))
11548 && mode_width
<= HOST_BITS_PER_WIDE_INT
11549 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11550 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11552 op0
= XEXP (op0
, 0);
11553 code
= (code
== EQ
? GE
: LT
);
11557 /* If this AND operation is really a ZERO_EXTEND from a narrower
11558 mode, the constant fits within that mode, and this is either an
11559 equality or unsigned comparison, try to do this comparison in
11564 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11565 -> (ne:DI (reg:SI 4) (const_int 0))
11567 unless TRULY_NOOP_TRUNCATION allows it or the register is
11568 known to hold a value of the required mode the
11569 transformation is invalid. */
11570 if ((equality_comparison_p
|| unsigned_comparison_p
)
11571 && CONST_INT_P (XEXP (op0
, 1))
11572 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11573 & GET_MODE_MASK (mode
))
11575 && const_op
>> i
== 0
11576 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11577 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
11578 GET_MODE_BITSIZE (GET_MODE (op0
)))
11579 || (REG_P (XEXP (op0
, 0))
11580 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11582 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11586 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11587 fits in both M1 and M2 and the SUBREG is either paradoxical
11588 or represents the low part, permute the SUBREG and the AND
11590 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11592 unsigned HOST_WIDE_INT c1
;
11593 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11594 /* Require an integral mode, to avoid creating something like
11596 if (SCALAR_INT_MODE_P (tmode
)
11597 /* It is unsafe to commute the AND into the SUBREG if the
11598 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11599 not defined. As originally written the upper bits
11600 have a defined value due to the AND operation.
11601 However, if we commute the AND inside the SUBREG then
11602 they no longer have defined values and the meaning of
11603 the code has been changed. */
11605 #ifdef WORD_REGISTER_OPERATIONS
11606 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11607 && mode_width
<= BITS_PER_WORD
)
11609 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11610 && subreg_lowpart_p (XEXP (op0
, 0))))
11611 && CONST_INT_P (XEXP (op0
, 1))
11612 && mode_width
<= HOST_BITS_PER_WIDE_INT
11613 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11614 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11615 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11617 && c1
!= GET_MODE_MASK (tmode
))
11619 op0
= simplify_gen_binary (AND
, tmode
,
11620 SUBREG_REG (XEXP (op0
, 0)),
11621 gen_int_mode (c1
, tmode
));
11622 op0
= gen_lowpart (mode
, op0
);
11627 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11628 if (const_op
== 0 && equality_comparison_p
11629 && XEXP (op0
, 1) == const1_rtx
11630 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11632 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11633 XEXP (XEXP (op0
, 0), 0), 1);
11634 code
= (code
== NE
? EQ
: NE
);
11638 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11639 (eq (and (lshiftrt X) 1) 0).
11640 Also handle the case where (not X) is expressed using xor. */
11641 if (const_op
== 0 && equality_comparison_p
11642 && XEXP (op0
, 1) == const1_rtx
11643 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11645 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11646 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11648 if (GET_CODE (shift_op
) == NOT
11649 || (GET_CODE (shift_op
) == XOR
11650 && CONST_INT_P (XEXP (shift_op
, 1))
11651 && CONST_INT_P (shift_count
)
11652 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11653 && (UINTVAL (XEXP (shift_op
, 1))
11654 == (unsigned HOST_WIDE_INT
) 1
11655 << INTVAL (shift_count
))))
11658 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11659 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11660 code
= (code
== NE
? EQ
: NE
);
11667 /* If we have (compare (ashift FOO N) (const_int C)) and
11668 the high order N bits of FOO (N+1 if an inequality comparison)
11669 are known to be zero, we can do this by comparing FOO with C
11670 shifted right N bits so long as the low-order N bits of C are
11672 if (CONST_INT_P (XEXP (op0
, 1))
11673 && INTVAL (XEXP (op0
, 1)) >= 0
11674 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11675 < HOST_BITS_PER_WIDE_INT
)
11676 && (((unsigned HOST_WIDE_INT
) const_op
11677 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11679 && mode_width
<= HOST_BITS_PER_WIDE_INT
11680 && (nonzero_bits (XEXP (op0
, 0), mode
)
11681 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11682 + ! equality_comparison_p
))) == 0)
11684 /* We must perform a logical shift, not an arithmetic one,
11685 as we want the top N bits of C to be zero. */
11686 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11688 temp
>>= INTVAL (XEXP (op0
, 1));
11689 op1
= gen_int_mode (temp
, mode
);
11690 op0
= XEXP (op0
, 0);
11694 /* If we are doing a sign bit comparison, it means we are testing
11695 a particular bit. Convert it to the appropriate AND. */
11696 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11697 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11699 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11700 ((unsigned HOST_WIDE_INT
) 1
11702 - INTVAL (XEXP (op0
, 1)))));
11703 code
= (code
== LT
? NE
: EQ
);
11707 /* If this an equality comparison with zero and we are shifting
11708 the low bit to the sign bit, we can convert this to an AND of the
11710 if (const_op
== 0 && equality_comparison_p
11711 && CONST_INT_P (XEXP (op0
, 1))
11712 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11714 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11720 /* If this is an equality comparison with zero, we can do this
11721 as a logical shift, which might be much simpler. */
11722 if (equality_comparison_p
&& const_op
== 0
11723 && CONST_INT_P (XEXP (op0
, 1)))
11725 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11727 INTVAL (XEXP (op0
, 1)));
11731 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11732 do the comparison in a narrower mode. */
11733 if (! unsigned_comparison_p
11734 && CONST_INT_P (XEXP (op0
, 1))
11735 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11736 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11737 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11738 MODE_INT
, 1)) != BLKmode
11739 && (((unsigned HOST_WIDE_INT
) const_op
11740 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11741 <= GET_MODE_MASK (tmode
)))
11743 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11747 /* Likewise if OP0 is a PLUS of a sign extension with a
11748 constant, which is usually represented with the PLUS
11749 between the shifts. */
11750 if (! unsigned_comparison_p
11751 && CONST_INT_P (XEXP (op0
, 1))
11752 && GET_CODE (XEXP (op0
, 0)) == PLUS
11753 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11754 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11755 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11756 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11757 MODE_INT
, 1)) != BLKmode
11758 && (((unsigned HOST_WIDE_INT
) const_op
11759 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11760 <= GET_MODE_MASK (tmode
)))
11762 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11763 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11764 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11765 add_const
, XEXP (op0
, 1));
11767 op0
= simplify_gen_binary (PLUS
, tmode
,
11768 gen_lowpart (tmode
, inner
),
11773 /* ... fall through ... */
11775 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11776 the low order N bits of FOO are known to be zero, we can do this
11777 by comparing FOO with C shifted left N bits so long as no
11778 overflow occurs. Even if the low order N bits of FOO aren't known
11779 to be zero, if the comparison is >= or < we can use the same
11780 optimization and for > or <= by setting all the low
11781 order N bits in the comparison constant. */
11782 if (CONST_INT_P (XEXP (op0
, 1))
11783 && INTVAL (XEXP (op0
, 1)) > 0
11784 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11785 && mode_width
<= HOST_BITS_PER_WIDE_INT
11786 && (((unsigned HOST_WIDE_INT
) const_op
11787 + (GET_CODE (op0
) != LSHIFTRT
11788 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11791 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11793 unsigned HOST_WIDE_INT low_bits
11794 = (nonzero_bits (XEXP (op0
, 0), mode
)
11795 & (((unsigned HOST_WIDE_INT
) 1
11796 << INTVAL (XEXP (op0
, 1))) - 1));
11797 if (low_bits
== 0 || !equality_comparison_p
)
11799 /* If the shift was logical, then we must make the condition
11801 if (GET_CODE (op0
) == LSHIFTRT
)
11802 code
= unsigned_condition (code
);
11804 const_op
<<= INTVAL (XEXP (op0
, 1));
11806 && (code
== GT
|| code
== GTU
11807 || code
== LE
|| code
== LEU
))
11809 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11810 op1
= GEN_INT (const_op
);
11811 op0
= XEXP (op0
, 0);
11816 /* If we are using this shift to extract just the sign bit, we
11817 can replace this with an LT or GE comparison. */
11819 && (equality_comparison_p
|| sign_bit_comparison_p
)
11820 && CONST_INT_P (XEXP (op0
, 1))
11821 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11823 op0
= XEXP (op0
, 0);
11824 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11836 /* Now make any compound operations involved in this comparison. Then,
11837 check for an outmost SUBREG on OP0 that is not doing anything or is
11838 paradoxical. The latter transformation must only be performed when
11839 it is known that the "extra" bits will be the same in op0 and op1 or
11840 that they don't matter. There are three cases to consider:
11842 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11843 care bits and we can assume they have any convenient value. So
11844 making the transformation is safe.
11846 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11847 In this case the upper bits of op0 are undefined. We should not make
11848 the simplification in that case as we do not know the contents of
11851 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11852 UNKNOWN. In that case we know those bits are zeros or ones. We must
11853 also be sure that they are the same as the upper bits of op1.
11855 We can never remove a SUBREG for a non-equality comparison because
11856 the sign bit is in a different place in the underlying object. */
11858 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11859 op1
= make_compound_operation (op1
, SET
);
11861 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11862 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11863 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11864 && (code
== NE
|| code
== EQ
))
11866 if (GET_MODE_SIZE (GET_MODE (op0
))
11867 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11869 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11871 if (REG_P (SUBREG_REG (op0
)))
11873 op0
= SUBREG_REG (op0
);
11874 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11877 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11878 <= HOST_BITS_PER_WIDE_INT
)
11879 && (nonzero_bits (SUBREG_REG (op0
),
11880 GET_MODE (SUBREG_REG (op0
)))
11881 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11883 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11885 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11886 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11887 op0
= SUBREG_REG (op0
), op1
= tem
;
11891 /* We now do the opposite procedure: Some machines don't have compare
11892 insns in all modes. If OP0's mode is an integer mode smaller than a
11893 word and we can't do a compare in that mode, see if there is a larger
11894 mode for which we can do the compare. There are a number of cases in
11895 which we can use the wider mode. */
11897 mode
= GET_MODE (op0
);
11898 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11899 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11900 && ! have_insn_for (COMPARE
, mode
))
11901 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11903 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11904 tmode
= GET_MODE_WIDER_MODE (tmode
))
11905 if (have_insn_for (COMPARE
, tmode
))
11909 /* If this is a test for negative, we can make an explicit
11910 test of the sign bit. Test this first so we can use
11911 a paradoxical subreg to extend OP0. */
11913 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11914 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11916 op0
= simplify_gen_binary (AND
, tmode
,
11917 gen_lowpart (tmode
, op0
),
11918 GEN_INT ((unsigned HOST_WIDE_INT
) 1
11919 << (GET_MODE_BITSIZE (mode
)
11921 code
= (code
== LT
) ? NE
: EQ
;
11925 /* If the only nonzero bits in OP0 and OP1 are those in the
11926 narrower mode and this is an equality or unsigned comparison,
11927 we can use the wider mode. Similarly for sign-extended
11928 values, in which case it is true for all comparisons. */
11929 zero_extended
= ((code
== EQ
|| code
== NE
11930 || code
== GEU
|| code
== GTU
11931 || code
== LEU
|| code
== LTU
)
11932 && (nonzero_bits (op0
, tmode
)
11933 & ~GET_MODE_MASK (mode
)) == 0
11934 && ((CONST_INT_P (op1
)
11935 || (nonzero_bits (op1
, tmode
)
11936 & ~GET_MODE_MASK (mode
)) == 0)));
11939 || ((num_sign_bit_copies (op0
, tmode
)
11940 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11941 - GET_MODE_BITSIZE (mode
)))
11942 && (num_sign_bit_copies (op1
, tmode
)
11943 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11944 - GET_MODE_BITSIZE (mode
)))))
11946 /* If OP0 is an AND and we don't have an AND in MODE either,
11947 make a new AND in the proper mode. */
11948 if (GET_CODE (op0
) == AND
11949 && !have_insn_for (AND
, mode
))
11950 op0
= simplify_gen_binary (AND
, tmode
,
11951 gen_lowpart (tmode
,
11953 gen_lowpart (tmode
,
11959 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11960 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11964 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11965 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11972 #ifdef CANONICALIZE_COMPARISON
11973 /* If this machine only supports a subset of valid comparisons, see if we
11974 can convert an unsupported one into a supported one. */
11975 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11984 /* Utility function for record_value_for_reg. Count number of
11989 enum rtx_code code
= GET_CODE (x
);
11993 if (GET_RTX_CLASS (code
) == '2'
11994 || GET_RTX_CLASS (code
) == 'c')
11996 rtx x0
= XEXP (x
, 0);
11997 rtx x1
= XEXP (x
, 1);
12000 return 1 + 2 * count_rtxs (x0
);
12002 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
12003 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
12004 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12005 return 2 + 2 * count_rtxs (x0
)
12006 + count_rtxs (x
== XEXP (x1
, 0)
12007 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12009 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
12010 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
12011 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12012 return 2 + 2 * count_rtxs (x1
)
12013 + count_rtxs (x
== XEXP (x0
, 0)
12014 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12017 fmt
= GET_RTX_FORMAT (code
);
12018 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12020 ret
+= count_rtxs (XEXP (x
, i
));
12021 else if (fmt
[i
] == 'E')
12022 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12023 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12028 /* Utility function for following routine. Called when X is part of a value
12029 being stored into last_set_value. Sets last_set_table_tick
12030 for each register mentioned. Similar to mention_regs in cse.c */
12033 update_table_tick (rtx x
)
12035 enum rtx_code code
= GET_CODE (x
);
12036 const char *fmt
= GET_RTX_FORMAT (code
);
12041 unsigned int regno
= REGNO (x
);
12042 unsigned int endregno
= END_REGNO (x
);
12045 for (r
= regno
; r
< endregno
; r
++)
12047 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
12048 rsp
->last_set_table_tick
= label_tick
;
12054 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12057 /* Check for identical subexpressions. If x contains
12058 identical subexpression we only have to traverse one of
12060 if (i
== 0 && ARITHMETIC_P (x
))
12062 /* Note that at this point x1 has already been
12064 rtx x0
= XEXP (x
, 0);
12065 rtx x1
= XEXP (x
, 1);
12067 /* If x0 and x1 are identical then there is no need to
12072 /* If x0 is identical to a subexpression of x1 then while
12073 processing x1, x0 has already been processed. Thus we
12074 are done with x. */
12075 if (ARITHMETIC_P (x1
)
12076 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12079 /* If x1 is identical to a subexpression of x0 then we
12080 still have to process the rest of x0. */
12081 if (ARITHMETIC_P (x0
)
12082 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12084 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12089 update_table_tick (XEXP (x
, i
));
12091 else if (fmt
[i
] == 'E')
12092 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12093 update_table_tick (XVECEXP (x
, i
, j
));
12096 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12097 are saying that the register is clobbered and we no longer know its
12098 value. If INSN is zero, don't update reg_stat[].last_set; this is
12099 only permitted with VALUE also zero and is used to invalidate the
12103 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12105 unsigned int regno
= REGNO (reg
);
12106 unsigned int endregno
= END_REGNO (reg
);
12108 reg_stat_type
*rsp
;
12110 /* If VALUE contains REG and we have a previous value for REG, substitute
12111 the previous value. */
12112 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12116 /* Set things up so get_last_value is allowed to see anything set up to
12118 subst_low_luid
= DF_INSN_LUID (insn
);
12119 tem
= get_last_value (reg
);
12121 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12122 it isn't going to be useful and will take a lot of time to process,
12123 so just use the CLOBBER. */
12127 if (ARITHMETIC_P (tem
)
12128 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12129 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12130 tem
= XEXP (tem
, 0);
12131 else if (count_occurrences (value
, reg
, 1) >= 2)
12133 /* If there are two or more occurrences of REG in VALUE,
12134 prevent the value from growing too much. */
12135 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12136 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12139 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12143 /* For each register modified, show we don't know its value, that
12144 we don't know about its bitwise content, that its value has been
12145 updated, and that we don't know the location of the death of the
12147 for (i
= regno
; i
< endregno
; i
++)
12149 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12152 rsp
->last_set
= insn
;
12154 rsp
->last_set_value
= 0;
12155 rsp
->last_set_mode
= VOIDmode
;
12156 rsp
->last_set_nonzero_bits
= 0;
12157 rsp
->last_set_sign_bit_copies
= 0;
12158 rsp
->last_death
= 0;
12159 rsp
->truncated_to_mode
= VOIDmode
;
12162 /* Mark registers that are being referenced in this value. */
12164 update_table_tick (value
);
12166 /* Now update the status of each register being set.
12167 If someone is using this register in this block, set this register
12168 to invalid since we will get confused between the two lives in this
12169 basic block. This makes using this register always invalid. In cse, we
12170 scan the table to invalidate all entries using this register, but this
12171 is too much work for us. */
12173 for (i
= regno
; i
< endregno
; i
++)
12175 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12176 rsp
->last_set_label
= label_tick
;
12178 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12179 rsp
->last_set_invalid
= 1;
12181 rsp
->last_set_invalid
= 0;
12184 /* The value being assigned might refer to X (like in "x++;"). In that
12185 case, we must replace it with (clobber (const_int 0)) to prevent
12187 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12188 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12190 value
= copy_rtx (value
);
12191 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12195 /* For the main register being modified, update the value, the mode, the
12196 nonzero bits, and the number of sign bit copies. */
12198 rsp
->last_set_value
= value
;
12202 enum machine_mode mode
= GET_MODE (reg
);
12203 subst_low_luid
= DF_INSN_LUID (insn
);
12204 rsp
->last_set_mode
= mode
;
12205 if (GET_MODE_CLASS (mode
) == MODE_INT
12206 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
12207 mode
= nonzero_bits_mode
;
12208 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12209 rsp
->last_set_sign_bit_copies
12210 = num_sign_bit_copies (value
, GET_MODE (reg
));
12214 /* Called via note_stores from record_dead_and_set_regs to handle one
12215 SET or CLOBBER in an insn. DATA is the instruction in which the
12216 set is occurring. */
12219 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12221 rtx record_dead_insn
= (rtx
) data
;
12223 if (GET_CODE (dest
) == SUBREG
)
12224 dest
= SUBREG_REG (dest
);
12226 if (!record_dead_insn
)
12229 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12235 /* If we are setting the whole register, we know its value. Otherwise
12236 show that we don't know the value. We can handle SUBREG in
12238 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12239 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12240 else if (GET_CODE (setter
) == SET
12241 && GET_CODE (SET_DEST (setter
)) == SUBREG
12242 && SUBREG_REG (SET_DEST (setter
)) == dest
12243 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
12244 && subreg_lowpart_p (SET_DEST (setter
)))
12245 record_value_for_reg (dest
, record_dead_insn
,
12246 gen_lowpart (GET_MODE (dest
),
12247 SET_SRC (setter
)));
12249 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12251 else if (MEM_P (dest
)
12252 /* Ignore pushes, they clobber nothing. */
12253 && ! push_operand (dest
, GET_MODE (dest
)))
12254 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12257 /* Update the records of when each REG was most recently set or killed
12258 for the things done by INSN. This is the last thing done in processing
12259 INSN in the combiner loop.
12261 We update reg_stat[], in particular fields last_set, last_set_value,
12262 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12263 last_death, and also the similar information mem_last_set (which insn
12264 most recently modified memory) and last_call_luid (which insn was the
12265 most recent subroutine call). */
12268 record_dead_and_set_regs (rtx insn
)
12273 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12275 if (REG_NOTE_KIND (link
) == REG_DEAD
12276 && REG_P (XEXP (link
, 0)))
12278 unsigned int regno
= REGNO (XEXP (link
, 0));
12279 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12281 for (i
= regno
; i
< endregno
; i
++)
12283 reg_stat_type
*rsp
;
12285 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12286 rsp
->last_death
= insn
;
12289 else if (REG_NOTE_KIND (link
) == REG_INC
)
12290 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12295 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12296 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
12298 reg_stat_type
*rsp
;
12300 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12301 rsp
->last_set_invalid
= 1;
12302 rsp
->last_set
= insn
;
12303 rsp
->last_set_value
= 0;
12304 rsp
->last_set_mode
= VOIDmode
;
12305 rsp
->last_set_nonzero_bits
= 0;
12306 rsp
->last_set_sign_bit_copies
= 0;
12307 rsp
->last_death
= 0;
12308 rsp
->truncated_to_mode
= VOIDmode
;
12311 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12313 /* We can't combine into a call pattern. Remember, though, that
12314 the return value register is set at this LUID. We could
12315 still replace a register with the return value from the
12316 wrong subroutine call! */
12317 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12320 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12323 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12324 register present in the SUBREG, so for each such SUBREG go back and
12325 adjust nonzero and sign bit information of the registers that are
12326 known to have some zero/sign bits set.
12328 This is needed because when combine blows the SUBREGs away, the
12329 information on zero/sign bits is lost and further combines can be
12330 missed because of that. */
12333 record_promoted_value (rtx insn
, rtx subreg
)
12336 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12337 enum machine_mode mode
= GET_MODE (subreg
);
12339 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
12342 for (links
= LOG_LINKS (insn
); links
;)
12344 reg_stat_type
*rsp
;
12346 insn
= XEXP (links
, 0);
12347 set
= single_set (insn
);
12349 if (! set
|| !REG_P (SET_DEST (set
))
12350 || REGNO (SET_DEST (set
)) != regno
12351 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12353 links
= XEXP (links
, 1);
12357 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12358 if (rsp
->last_set
== insn
)
12360 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12361 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12364 if (REG_P (SET_SRC (set
)))
12366 regno
= REGNO (SET_SRC (set
));
12367 links
= LOG_LINKS (insn
);
12374 /* Check if X, a register, is known to contain a value already
12375 truncated to MODE. In this case we can use a subreg to refer to
12376 the truncated value even though in the generic case we would need
12377 an explicit truncation. */
12380 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12382 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12383 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12386 || rsp
->truncation_label
< label_tick_ebb_start
)
12388 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12390 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
12391 GET_MODE_BITSIZE (truncated
)))
12396 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12397 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12398 might be able to turn a truncate into a subreg using this information.
12399 Return -1 if traversing *P is complete or 0 otherwise. */
12402 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12405 enum machine_mode truncated_mode
;
12406 reg_stat_type
*rsp
;
12408 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12410 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12411 truncated_mode
= GET_MODE (x
);
12413 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12416 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
12417 GET_MODE_BITSIZE (original_mode
)))
12420 x
= SUBREG_REG (x
);
12422 /* ??? For hard-regs we now record everything. We might be able to
12423 optimize this using last_set_mode. */
12424 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12425 truncated_mode
= GET_MODE (x
);
12429 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12430 if (rsp
->truncated_to_mode
== 0
12431 || rsp
->truncation_label
< label_tick_ebb_start
12432 || (GET_MODE_SIZE (truncated_mode
)
12433 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12435 rsp
->truncated_to_mode
= truncated_mode
;
12436 rsp
->truncation_label
= label_tick
;
12442 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12443 the modes they are used in. This can help truning TRUNCATEs into
12447 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12449 for_each_rtx (x
, record_truncated_value
, NULL
);
12452 /* Scan X for promoted SUBREGs. For each one found,
12453 note what it implies to the registers used in it. */
12456 check_promoted_subreg (rtx insn
, rtx x
)
12458 if (GET_CODE (x
) == SUBREG
12459 && SUBREG_PROMOTED_VAR_P (x
)
12460 && REG_P (SUBREG_REG (x
)))
12461 record_promoted_value (insn
, x
);
12464 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12467 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12471 check_promoted_subreg (insn
, XEXP (x
, i
));
12475 if (XVEC (x
, i
) != 0)
12476 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12477 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12483 /* Verify that all the registers and memory references mentioned in *LOC are
12484 still valid. *LOC was part of a value set in INSN when label_tick was
12485 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12486 the invalid references with (clobber (const_int 0)) and return 1. This
12487 replacement is useful because we often can get useful information about
12488 the form of a value (e.g., if it was produced by a shift that always
12489 produces -1 or 0) even though we don't know exactly what registers it
12490 was produced from. */
12493 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12496 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12497 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12502 unsigned int regno
= REGNO (x
);
12503 unsigned int endregno
= END_REGNO (x
);
12506 for (j
= regno
; j
< endregno
; j
++)
12508 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12509 if (rsp
->last_set_invalid
12510 /* If this is a pseudo-register that was only set once and not
12511 live at the beginning of the function, it is always valid. */
12512 || (! (regno
>= FIRST_PSEUDO_REGISTER
12513 && REG_N_SETS (regno
) == 1
12514 && (!REGNO_REG_SET_P
12515 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12516 && rsp
->last_set_label
> tick
))
12519 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12526 /* If this is a memory reference, make sure that there were no stores after
12527 it that might have clobbered the value. We don't have alias info, so we
12528 assume any store invalidates it. Moreover, we only have local UIDs, so
12529 we also assume that there were stores in the intervening basic blocks. */
12530 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12531 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12534 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12538 for (i
= 0; i
< len
; i
++)
12542 /* Check for identical subexpressions. If x contains
12543 identical subexpression we only have to traverse one of
12545 if (i
== 1 && ARITHMETIC_P (x
))
12547 /* Note that at this point x0 has already been checked
12548 and found valid. */
12549 rtx x0
= XEXP (x
, 0);
12550 rtx x1
= XEXP (x
, 1);
12552 /* If x0 and x1 are identical then x is also valid. */
12556 /* If x1 is identical to a subexpression of x0 then
12557 while checking x0, x1 has already been checked. Thus
12558 it is valid and so as x. */
12559 if (ARITHMETIC_P (x0
)
12560 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12563 /* If x0 is identical to a subexpression of x1 then x is
12564 valid iff the rest of x1 is valid. */
12565 if (ARITHMETIC_P (x1
)
12566 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12568 get_last_value_validate (&XEXP (x1
,
12569 x0
== XEXP (x1
, 0) ? 1 : 0),
12570 insn
, tick
, replace
);
12573 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12577 else if (fmt
[i
] == 'E')
12578 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12579 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12580 insn
, tick
, replace
) == 0)
12584 /* If we haven't found a reason for it to be invalid, it is valid. */
12588 /* Get the last value assigned to X, if known. Some registers
12589 in the value may be replaced with (clobber (const_int 0)) if their value
12590 is known longer known reliably. */
12593 get_last_value (const_rtx x
)
12595 unsigned int regno
;
12597 reg_stat_type
*rsp
;
12599 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12600 then convert it to the desired mode. If this is a paradoxical SUBREG,
12601 we cannot predict what values the "extra" bits might have. */
12602 if (GET_CODE (x
) == SUBREG
12603 && subreg_lowpart_p (x
)
12604 && (GET_MODE_SIZE (GET_MODE (x
))
12605 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
12606 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12607 return gen_lowpart (GET_MODE (x
), value
);
12613 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12614 value
= rsp
->last_set_value
;
12616 /* If we don't have a value, or if it isn't for this basic block and
12617 it's either a hard register, set more than once, or it's a live
12618 at the beginning of the function, return 0.
12620 Because if it's not live at the beginning of the function then the reg
12621 is always set before being used (is never used without being set).
12622 And, if it's set only once, and it's always set before use, then all
12623 uses must have the same last value, even if it's not from this basic
12627 || (rsp
->last_set_label
< label_tick_ebb_start
12628 && (regno
< FIRST_PSEUDO_REGISTER
12629 || REG_N_SETS (regno
) != 1
12631 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12634 /* If the value was set in a later insn than the ones we are processing,
12635 we can't use it even if the register was only set once. */
12636 if (rsp
->last_set_label
== label_tick
12637 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12640 /* If the value has all its registers valid, return it. */
12641 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12644 /* Otherwise, make a copy and replace any invalid register with
12645 (clobber (const_int 0)). If that fails for some reason, return 0. */
12647 value
= copy_rtx (value
);
12648 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12654 /* Return nonzero if expression X refers to a REG or to memory
12655 that is set in an instruction more recent than FROM_LUID. */
12658 use_crosses_set_p (const_rtx x
, int from_luid
)
12662 enum rtx_code code
= GET_CODE (x
);
12666 unsigned int regno
= REGNO (x
);
12667 unsigned endreg
= END_REGNO (x
);
12669 #ifdef PUSH_ROUNDING
12670 /* Don't allow uses of the stack pointer to be moved,
12671 because we don't know whether the move crosses a push insn. */
12672 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12675 for (; regno
< endreg
; regno
++)
12677 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12679 && rsp
->last_set_label
== label_tick
12680 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12686 if (code
== MEM
&& mem_last_set
> from_luid
)
12689 fmt
= GET_RTX_FORMAT (code
);
12691 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12696 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12697 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12700 else if (fmt
[i
] == 'e'
12701 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12707 /* Define three variables used for communication between the following
12710 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12711 static int reg_dead_flag
;
12713 /* Function called via note_stores from reg_dead_at_p.
12715 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12716 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12719 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12721 unsigned int regno
, endregno
;
12726 regno
= REGNO (dest
);
12727 endregno
= END_REGNO (dest
);
12728 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12729 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12732 /* Return nonzero if REG is known to be dead at INSN.
12734 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12735 referencing REG, it is dead. If we hit a SET referencing REG, it is
12736 live. Otherwise, see if it is live or dead at the start of the basic
12737 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12738 must be assumed to be always live. */
12741 reg_dead_at_p (rtx reg
, rtx insn
)
12746 /* Set variables for reg_dead_at_p_1. */
12747 reg_dead_regno
= REGNO (reg
);
12748 reg_dead_endregno
= END_REGNO (reg
);
12752 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12753 we allow the machine description to decide whether use-and-clobber
12754 patterns are OK. */
12755 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12757 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12758 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12762 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12763 beginning of basic block. */
12764 block
= BLOCK_FOR_INSN (insn
);
12769 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12771 return reg_dead_flag
== 1 ? 1 : 0;
12773 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12777 if (insn
== BB_HEAD (block
))
12780 insn
= PREV_INSN (insn
);
12783 /* Look at live-in sets for the basic block that we were in. */
12784 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12785 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12791 /* Note hard registers in X that are used. */
12794 mark_used_regs_combine (rtx x
)
12796 RTX_CODE code
= GET_CODE (x
);
12797 unsigned int regno
;
12810 case ADDR_DIFF_VEC
:
12813 /* CC0 must die in the insn after it is set, so we don't need to take
12814 special note of it here. */
12820 /* If we are clobbering a MEM, mark any hard registers inside the
12821 address as used. */
12822 if (MEM_P (XEXP (x
, 0)))
12823 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12828 /* A hard reg in a wide mode may really be multiple registers.
12829 If so, mark all of them just like the first. */
12830 if (regno
< FIRST_PSEUDO_REGISTER
)
12832 /* None of this applies to the stack, frame or arg pointers. */
12833 if (regno
== STACK_POINTER_REGNUM
12834 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12835 || regno
== HARD_FRAME_POINTER_REGNUM
12837 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12838 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12840 || regno
== FRAME_POINTER_REGNUM
)
12843 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12849 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12851 rtx testreg
= SET_DEST (x
);
12853 while (GET_CODE (testreg
) == SUBREG
12854 || GET_CODE (testreg
) == ZERO_EXTRACT
12855 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12856 testreg
= XEXP (testreg
, 0);
12858 if (MEM_P (testreg
))
12859 mark_used_regs_combine (XEXP (testreg
, 0));
12861 mark_used_regs_combine (SET_SRC (x
));
12869 /* Recursively scan the operands of this expression. */
12872 const char *fmt
= GET_RTX_FORMAT (code
);
12874 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12877 mark_used_regs_combine (XEXP (x
, i
));
12878 else if (fmt
[i
] == 'E')
12882 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12883 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12889 /* Remove register number REGNO from the dead registers list of INSN.
12891 Return the note used to record the death, if there was one. */
12894 remove_death (unsigned int regno
, rtx insn
)
12896 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12899 remove_note (insn
, note
);
12904 /* For each register (hardware or pseudo) used within expression X, if its
12905 death is in an instruction with luid between FROM_LUID (inclusive) and
12906 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12907 list headed by PNOTES.
12909 That said, don't move registers killed by maybe_kill_insn.
12911 This is done when X is being merged by combination into TO_INSN. These
12912 notes will then be distributed as needed. */
12915 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12920 enum rtx_code code
= GET_CODE (x
);
12924 unsigned int regno
= REGNO (x
);
12925 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12927 /* Don't move the register if it gets killed in between from and to. */
12928 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12929 && ! reg_referenced_p (x
, maybe_kill_insn
))
12933 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12934 && DF_INSN_LUID (where_dead
) >= from_luid
12935 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12937 rtx note
= remove_death (regno
, where_dead
);
12939 /* It is possible for the call above to return 0. This can occur
12940 when last_death points to I2 or I1 that we combined with.
12941 In that case make a new note.
12943 We must also check for the case where X is a hard register
12944 and NOTE is a death note for a range of hard registers
12945 including X. In that case, we must put REG_DEAD notes for
12946 the remaining registers in place of NOTE. */
12948 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12949 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12950 > GET_MODE_SIZE (GET_MODE (x
))))
12952 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12953 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12954 unsigned int ourend
= END_HARD_REGNO (x
);
12957 for (i
= deadregno
; i
< deadend
; i
++)
12958 if (i
< regno
|| i
>= ourend
)
12959 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12962 /* If we didn't find any note, or if we found a REG_DEAD note that
12963 covers only part of the given reg, and we have a multi-reg hard
12964 register, then to be safe we must check for REG_DEAD notes
12965 for each register other than the first. They could have
12966 their own REG_DEAD notes lying around. */
12967 else if ((note
== 0
12969 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12970 < GET_MODE_SIZE (GET_MODE (x
)))))
12971 && regno
< FIRST_PSEUDO_REGISTER
12972 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12974 unsigned int ourend
= END_HARD_REGNO (x
);
12975 unsigned int i
, offset
;
12979 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12983 for (i
= regno
+ offset
; i
< ourend
; i
++)
12984 move_deaths (regno_reg_rtx
[i
],
12985 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12988 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12990 XEXP (note
, 1) = *pnotes
;
12994 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13000 else if (GET_CODE (x
) == SET
)
13002 rtx dest
= SET_DEST (x
);
13004 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13006 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13007 that accesses one word of a multi-word item, some
13008 piece of everything register in the expression is used by
13009 this insn, so remove any old death. */
13010 /* ??? So why do we test for equality of the sizes? */
13012 if (GET_CODE (dest
) == ZERO_EXTRACT
13013 || GET_CODE (dest
) == STRICT_LOW_PART
13014 || (GET_CODE (dest
) == SUBREG
13015 && (((GET_MODE_SIZE (GET_MODE (dest
))
13016 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13017 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13018 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13020 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13024 /* If this is some other SUBREG, we know it replaces the entire
13025 value, so use that as the destination. */
13026 if (GET_CODE (dest
) == SUBREG
)
13027 dest
= SUBREG_REG (dest
);
13029 /* If this is a MEM, adjust deaths of anything used in the address.
13030 For a REG (the only other possibility), the entire value is
13031 being replaced so the old value is not used in this insn. */
13034 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13039 else if (GET_CODE (x
) == CLOBBER
)
13042 len
= GET_RTX_LENGTH (code
);
13043 fmt
= GET_RTX_FORMAT (code
);
13045 for (i
= 0; i
< len
; i
++)
13050 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13051 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13054 else if (fmt
[i
] == 'e')
13055 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13059 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13060 pattern of an insn. X must be a REG. */
13063 reg_bitfield_target_p (rtx x
, rtx body
)
13067 if (GET_CODE (body
) == SET
)
13069 rtx dest
= SET_DEST (body
);
13071 unsigned int regno
, tregno
, endregno
, endtregno
;
13073 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13074 target
= XEXP (dest
, 0);
13075 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13076 target
= SUBREG_REG (XEXP (dest
, 0));
13080 if (GET_CODE (target
) == SUBREG
)
13081 target
= SUBREG_REG (target
);
13083 if (!REG_P (target
))
13086 tregno
= REGNO (target
), regno
= REGNO (x
);
13087 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13088 return target
== x
;
13090 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13091 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13093 return endregno
> tregno
&& regno
< endtregno
;
13096 else if (GET_CODE (body
) == PARALLEL
)
13097 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13098 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13104 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13105 as appropriate. I3 and I2 are the insns resulting from the combination
13106 insns including FROM (I2 may be zero).
13108 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13109 not need REG_DEAD notes because they are being substituted for. This
13110 saves searching in the most common cases.
13112 Each note in the list is either ignored or placed on some insns, depending
13113 on the type of note. */
13116 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13117 rtx elim_i1
, rtx elim_i0
)
13119 rtx note
, next_note
;
13122 for (note
= notes
; note
; note
= next_note
)
13124 rtx place
= 0, place2
= 0;
13126 next_note
= XEXP (note
, 1);
13127 switch (REG_NOTE_KIND (note
))
13131 /* Doesn't matter much where we put this, as long as it's somewhere.
13132 It is preferable to keep these notes on branches, which is most
13133 likely to be i3. */
13137 case REG_VALUE_PROFILE
:
13138 /* Just get rid of this note, as it is unused later anyway. */
13141 case REG_NON_LOCAL_GOTO
:
13146 gcc_assert (i2
&& JUMP_P (i2
));
13151 case REG_EH_REGION
:
13152 /* These notes must remain with the call or trapping instruction. */
13155 else if (i2
&& CALL_P (i2
))
13159 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13160 if (may_trap_p (i3
))
13162 else if (i2
&& may_trap_p (i2
))
13164 /* ??? Otherwise assume we've combined things such that we
13165 can now prove that the instructions can't trap. Drop the
13166 note in this case. */
13172 /* These notes must remain with the call. It should not be
13173 possible for both I2 and I3 to be a call. */
13178 gcc_assert (i2
&& CALL_P (i2
));
13184 /* Any clobbers for i3 may still exist, and so we must process
13185 REG_UNUSED notes from that insn.
13187 Any clobbers from i2 or i1 can only exist if they were added by
13188 recog_for_combine. In that case, recog_for_combine created the
13189 necessary REG_UNUSED notes. Trying to keep any original
13190 REG_UNUSED notes from these insns can cause incorrect output
13191 if it is for the same register as the original i3 dest.
13192 In that case, we will notice that the register is set in i3,
13193 and then add a REG_UNUSED note for the destination of i3, which
13194 is wrong. However, it is possible to have REG_UNUSED notes from
13195 i2 or i1 for register which were both used and clobbered, so
13196 we keep notes from i2 or i1 if they will turn into REG_DEAD
13199 /* If this register is set or clobbered in I3, put the note there
13200 unless there is one already. */
13201 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13203 if (from_insn
!= i3
)
13206 if (! (REG_P (XEXP (note
, 0))
13207 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13208 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13211 /* Otherwise, if this register is used by I3, then this register
13212 now dies here, so we must put a REG_DEAD note here unless there
13214 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13215 && ! (REG_P (XEXP (note
, 0))
13216 ? find_regno_note (i3
, REG_DEAD
,
13217 REGNO (XEXP (note
, 0)))
13218 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13220 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13228 /* These notes say something about results of an insn. We can
13229 only support them if they used to be on I3 in which case they
13230 remain on I3. Otherwise they are ignored.
13232 If the note refers to an expression that is not a constant, we
13233 must also ignore the note since we cannot tell whether the
13234 equivalence is still true. It might be possible to do
13235 slightly better than this (we only have a problem if I2DEST
13236 or I1DEST is present in the expression), but it doesn't
13237 seem worth the trouble. */
13239 if (from_insn
== i3
13240 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13245 /* These notes say something about how a register is used. They must
13246 be present on any use of the register in I2 or I3. */
13247 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13250 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13259 case REG_LABEL_TARGET
:
13260 case REG_LABEL_OPERAND
:
13261 /* This can show up in several ways -- either directly in the
13262 pattern, or hidden off in the constant pool with (or without?)
13263 a REG_EQUAL note. */
13264 /* ??? Ignore the without-reg_equal-note problem for now. */
13265 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13266 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13267 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13268 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13272 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13273 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13274 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13275 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13283 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13284 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13286 if (place
&& JUMP_P (place
)
13287 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13288 && (JUMP_LABEL (place
) == NULL
13289 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13291 rtx label
= JUMP_LABEL (place
);
13294 JUMP_LABEL (place
) = XEXP (note
, 0);
13295 else if (LABEL_P (label
))
13296 LABEL_NUSES (label
)--;
13299 if (place2
&& JUMP_P (place2
)
13300 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13301 && (JUMP_LABEL (place2
) == NULL
13302 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13304 rtx label
= JUMP_LABEL (place2
);
13307 JUMP_LABEL (place2
) = XEXP (note
, 0);
13308 else if (LABEL_P (label
))
13309 LABEL_NUSES (label
)--;
13315 /* This note says something about the value of a register prior
13316 to the execution of an insn. It is too much trouble to see
13317 if the note is still correct in all situations. It is better
13318 to simply delete it. */
13322 /* If we replaced the right hand side of FROM_INSN with a
13323 REG_EQUAL note, the original use of the dying register
13324 will not have been combined into I3 and I2. In such cases,
13325 FROM_INSN is guaranteed to be the first of the combined
13326 instructions, so we simply need to search back before
13327 FROM_INSN for the previous use or set of this register,
13328 then alter the notes there appropriately.
13330 If the register is used as an input in I3, it dies there.
13331 Similarly for I2, if it is nonzero and adjacent to I3.
13333 If the register is not used as an input in either I3 or I2
13334 and it is not one of the registers we were supposed to eliminate,
13335 there are two possibilities. We might have a non-adjacent I2
13336 or we might have somehow eliminated an additional register
13337 from a computation. For example, we might have had A & B where
13338 we discover that B will always be zero. In this case we will
13339 eliminate the reference to A.
13341 In both cases, we must search to see if we can find a previous
13342 use of A and put the death note there. */
13345 && from_insn
== i2mod
13346 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13351 && CALL_P (from_insn
)
13352 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13354 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13356 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13357 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13359 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13361 && reg_overlap_mentioned_p (XEXP (note
, 0),
13363 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13364 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13371 basic_block bb
= this_basic_block
;
13373 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13375 if (!NONDEBUG_INSN_P (tem
))
13377 if (tem
== BB_HEAD (bb
))
13382 /* If the register is being set at TEM, see if that is all
13383 TEM is doing. If so, delete TEM. Otherwise, make this
13384 into a REG_UNUSED note instead. Don't delete sets to
13385 global register vars. */
13386 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13387 || !global_regs
[REGNO (XEXP (note
, 0))])
13388 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13390 rtx set
= single_set (tem
);
13391 rtx inner_dest
= 0;
13393 rtx cc0_setter
= NULL_RTX
;
13397 for (inner_dest
= SET_DEST (set
);
13398 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13399 || GET_CODE (inner_dest
) == SUBREG
13400 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13401 inner_dest
= XEXP (inner_dest
, 0))
13404 /* Verify that it was the set, and not a clobber that
13405 modified the register.
13407 CC0 targets must be careful to maintain setter/user
13408 pairs. If we cannot delete the setter due to side
13409 effects, mark the user with an UNUSED note instead
13412 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13413 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13415 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13416 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13417 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13421 /* Move the notes and links of TEM elsewhere.
13422 This might delete other dead insns recursively.
13423 First set the pattern to something that won't use
13425 rtx old_notes
= REG_NOTES (tem
);
13427 PATTERN (tem
) = pc_rtx
;
13428 REG_NOTES (tem
) = NULL
;
13430 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13431 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13432 distribute_links (LOG_LINKS (tem
));
13434 SET_INSN_DELETED (tem
);
13439 /* Delete the setter too. */
13442 PATTERN (cc0_setter
) = pc_rtx
;
13443 old_notes
= REG_NOTES (cc0_setter
);
13444 REG_NOTES (cc0_setter
) = NULL
;
13446 distribute_notes (old_notes
, cc0_setter
,
13447 cc0_setter
, NULL_RTX
,
13448 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13449 distribute_links (LOG_LINKS (cc0_setter
));
13451 SET_INSN_DELETED (cc0_setter
);
13452 if (cc0_setter
== i2
)
13459 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13461 /* If there isn't already a REG_UNUSED note, put one
13462 here. Do not place a REG_DEAD note, even if
13463 the register is also used here; that would not
13464 match the algorithm used in lifetime analysis
13465 and can cause the consistency check in the
13466 scheduler to fail. */
13467 if (! find_regno_note (tem
, REG_UNUSED
,
13468 REGNO (XEXP (note
, 0))))
13473 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13475 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13479 /* If we are doing a 3->2 combination, and we have a
13480 register which formerly died in i3 and was not used
13481 by i2, which now no longer dies in i3 and is used in
13482 i2 but does not die in i2, and place is between i2
13483 and i3, then we may need to move a link from place to
13485 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13487 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13488 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13490 rtx links
= LOG_LINKS (place
);
13491 LOG_LINKS (place
) = 0;
13492 distribute_links (links
);
13497 if (tem
== BB_HEAD (bb
))
13503 /* If the register is set or already dead at PLACE, we needn't do
13504 anything with this note if it is still a REG_DEAD note.
13505 We check here if it is set at all, not if is it totally replaced,
13506 which is what `dead_or_set_p' checks, so also check for it being
13509 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13511 unsigned int regno
= REGNO (XEXP (note
, 0));
13512 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13514 if (dead_or_set_p (place
, XEXP (note
, 0))
13515 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13517 /* Unless the register previously died in PLACE, clear
13518 last_death. [I no longer understand why this is
13520 if (rsp
->last_death
!= place
)
13521 rsp
->last_death
= 0;
13525 rsp
->last_death
= place
;
13527 /* If this is a death note for a hard reg that is occupying
13528 multiple registers, ensure that we are still using all
13529 parts of the object. If we find a piece of the object
13530 that is unused, we must arrange for an appropriate REG_DEAD
13531 note to be added for it. However, we can't just emit a USE
13532 and tag the note to it, since the register might actually
13533 be dead; so we recourse, and the recursive call then finds
13534 the previous insn that used this register. */
13536 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13537 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13539 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13543 for (i
= regno
; i
< endregno
; i
++)
13544 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13545 && ! find_regno_fusage (place
, USE
, i
))
13546 || dead_or_set_regno_p (place
, i
))
13551 /* Put only REG_DEAD notes for pieces that are
13552 not already dead or set. */
13554 for (i
= regno
; i
< endregno
;
13555 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13557 rtx piece
= regno_reg_rtx
[i
];
13558 basic_block bb
= this_basic_block
;
13560 if (! dead_or_set_p (place
, piece
)
13561 && ! reg_bitfield_target_p (piece
,
13564 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13567 distribute_notes (new_note
, place
, place
,
13568 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13571 else if (! refers_to_regno_p (i
, i
+ 1,
13572 PATTERN (place
), 0)
13573 && ! find_regno_fusage (place
, USE
, i
))
13574 for (tem
= PREV_INSN (place
); ;
13575 tem
= PREV_INSN (tem
))
13577 if (!NONDEBUG_INSN_P (tem
))
13579 if (tem
== BB_HEAD (bb
))
13583 if (dead_or_set_p (tem
, piece
)
13584 || reg_bitfield_target_p (piece
,
13587 add_reg_note (tem
, REG_UNUSED
, piece
);
13601 /* Any other notes should not be present at this point in the
13603 gcc_unreachable ();
13608 XEXP (note
, 1) = REG_NOTES (place
);
13609 REG_NOTES (place
) = note
;
13613 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13617 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13618 I3, I2, and I1 to new locations. This is also called to add a link
13619 pointing at I3 when I3's destination is changed. */
13622 distribute_links (rtx links
)
13624 rtx link
, next_link
;
13626 for (link
= links
; link
; link
= next_link
)
13632 next_link
= XEXP (link
, 1);
13634 /* If the insn that this link points to is a NOTE or isn't a single
13635 set, ignore it. In the latter case, it isn't clear what we
13636 can do other than ignore the link, since we can't tell which
13637 register it was for. Such links wouldn't be used by combine
13640 It is not possible for the destination of the target of the link to
13641 have been changed by combine. The only potential of this is if we
13642 replace I3, I2, and I1 by I3 and I2. But in that case the
13643 destination of I2 also remains unchanged. */
13645 if (NOTE_P (XEXP (link
, 0))
13646 || (set
= single_set (XEXP (link
, 0))) == 0)
13649 reg
= SET_DEST (set
);
13650 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13651 || GET_CODE (reg
) == STRICT_LOW_PART
)
13652 reg
= XEXP (reg
, 0);
13654 /* A LOG_LINK is defined as being placed on the first insn that uses
13655 a register and points to the insn that sets the register. Start
13656 searching at the next insn after the target of the link and stop
13657 when we reach a set of the register or the end of the basic block.
13659 Note that this correctly handles the link that used to point from
13660 I3 to I2. Also note that not much searching is typically done here
13661 since most links don't point very far away. */
13663 for (insn
= NEXT_INSN (XEXP (link
, 0));
13664 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13665 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13666 insn
= NEXT_INSN (insn
))
13667 if (DEBUG_INSN_P (insn
))
13669 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13671 if (reg_referenced_p (reg
, PATTERN (insn
)))
13675 else if (CALL_P (insn
)
13676 && find_reg_fusage (insn
, USE
, reg
))
13681 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13684 /* If we found a place to put the link, place it there unless there
13685 is already a link to the same insn as LINK at that point. */
13691 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13692 if (XEXP (link2
, 0) == XEXP (link
, 0))
13697 XEXP (link
, 1) = LOG_LINKS (place
);
13698 LOG_LINKS (place
) = link
;
13700 /* Set added_links_insn to the earliest insn we added a
13702 if (added_links_insn
== 0
13703 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13704 added_links_insn
= place
;
13710 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13711 Check whether the expression pointer to by LOC is a register or
13712 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13713 Otherwise return zero. */
13716 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13721 && (REG_P (x
) || MEM_P (x
))
13722 && ! reg_mentioned_p (x
, (rtx
) expr
))
13727 /* Check for any register or memory mentioned in EQUIV that is not
13728 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13729 of EXPR where some registers may have been replaced by constants. */
13732 unmentioned_reg_p (rtx equiv
, rtx expr
)
13734 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13738 dump_combine_stats (FILE *file
)
13742 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13743 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13747 dump_combine_total_stats (FILE *file
)
13751 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13752 total_attempts
, total_merges
, total_extras
, total_successes
);
13756 gate_handle_combine (void)
13758 return (optimize
> 0);
13761 /* Try combining insns through substitution. */
13762 static unsigned int
13763 rest_of_handle_combine (void)
13765 int rebuild_jump_labels_after_combine
;
13767 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13768 df_note_add_problem ();
13771 regstat_init_n_sets_and_refs ();
13773 rebuild_jump_labels_after_combine
13774 = combine_instructions (get_insns (), max_reg_num ());
13776 /* Combining insns may have turned an indirect jump into a
13777 direct jump. Rebuild the JUMP_LABEL fields of jumping
13779 if (rebuild_jump_labels_after_combine
)
13781 timevar_push (TV_JUMP
);
13782 rebuild_jump_labels (get_insns ());
13784 timevar_pop (TV_JUMP
);
13787 regstat_free_n_sets_and_refs ();
13791 struct rtl_opt_pass pass_combine
=
13795 "combine", /* name */
13796 gate_handle_combine
, /* gate */
13797 rest_of_handle_combine
, /* execute */
13800 0, /* static_pass_number */
13801 TV_COMBINE
, /* tv_id */
13802 PROP_cfglayout
, /* properties_required */
13803 0, /* properties_provided */
13804 0, /* properties_destroyed */
13805 0, /* todo_flags_start */
13807 TODO_df_finish
| TODO_verify_rtl_sharing
|
13808 TODO_ggc_collect
, /* todo_flags_finish */