1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "insn-config.h"
30 #include "insn-attr.h"
31 #include "hard-reg-set.h"
34 #include "addresses.h"
39 #include "basic-block.h"
44 #include "tree-pass.h"
47 #ifndef STACK_PUSH_CODE
48 #ifdef STACK_GROWS_DOWNWARD
49 #define STACK_PUSH_CODE PRE_DEC
51 #define STACK_PUSH_CODE PRE_INC
55 #ifndef STACK_POP_CODE
56 #ifdef STACK_GROWS_DOWNWARD
57 #define STACK_POP_CODE POST_INC
59 #define STACK_POP_CODE POST_DEC
63 #ifndef HAVE_ATTR_enabled
65 get_attr_enabled (rtx insn ATTRIBUTE_UNUSED
)
71 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
72 static void validate_replace_src_1 (rtx
*, void *);
73 static rtx
split_insn (rtx
);
75 /* Nonzero means allow operands to be volatile.
76 This should be 0 if you are generating rtl, such as if you are calling
77 the functions in optabs.c and expmed.c (most of the time).
78 This should be 1 if all valid insns need to be recognized,
79 such as in reginfo.c and final.c and reload.c.
81 init_recog and init_recog_no_volatile are responsible for setting this. */
85 struct recog_data recog_data
;
87 /* Contains a vector of operand_alternative structures for every operand.
88 Set up by preprocess_constraints. */
89 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
91 /* On return from `constrain_operands', indicate which alternative
94 int which_alternative
;
96 /* Nonzero after end of reload pass.
97 Set to 1 or 0 by toplev.c.
98 Controls the significance of (SUBREG (MEM)). */
100 int reload_completed
;
102 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
103 int epilogue_completed
;
105 /* Initialize data used by the function `recog'.
106 This must be called once in the compilation of a function
107 before any insn recognition may be done in the function. */
110 init_recog_no_volatile (void)
122 /* Check that X is an insn-body for an `asm' with operands
123 and that the operands mentioned in it are legitimate. */
126 check_asm_operands (rtx x
)
130 const char **constraints
;
133 /* Post-reload, be more strict with things. */
134 if (reload_completed
)
136 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
137 extract_insn (make_insn_raw (x
));
138 constrain_operands (1);
139 return which_alternative
>= 0;
142 noperands
= asm_noperands (x
);
148 operands
= XALLOCAVEC (rtx
, noperands
);
149 constraints
= XALLOCAVEC (const char *, noperands
);
151 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
153 for (i
= 0; i
< noperands
; i
++)
155 const char *c
= constraints
[i
];
158 if (! asm_operand_ok (operands
[i
], c
, constraints
))
165 /* Static data for the next two routines. */
167 typedef struct change_t
176 static change_t
*changes
;
177 static int changes_allocated
;
179 static int num_changes
= 0;
181 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
182 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
183 the change is simply made.
185 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
186 will be called with the address and mode as parameters. If OBJECT is
187 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
190 IN_GROUP is nonzero if this is part of a group of changes that must be
191 performed as a group. In that case, the changes will be stored. The
192 function `apply_change_group' will validate and apply the changes.
194 If IN_GROUP is zero, this is a single change. Try to recognize the insn
195 or validate the memory reference with the change applied. If the result
196 is not valid for the machine, suppress the change and return zero.
197 Otherwise, perform the change and return 1. */
200 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
204 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
207 gcc_assert (in_group
!= 0 || num_changes
== 0);
211 /* Save the information describing this change. */
212 if (num_changes
>= changes_allocated
)
214 if (changes_allocated
== 0)
215 /* This value allows for repeated substitutions inside complex
216 indexed addresses, or changes in up to 5 insns. */
217 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
219 changes_allocated
*= 2;
221 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
224 changes
[num_changes
].object
= object
;
225 changes
[num_changes
].loc
= loc
;
226 changes
[num_changes
].old
= old
;
227 changes
[num_changes
].unshare
= unshare
;
229 if (object
&& !MEM_P (object
))
231 /* Set INSN_CODE to force rerecognition of insn. Save old code in
233 changes
[num_changes
].old_code
= INSN_CODE (object
);
234 INSN_CODE (object
) = -1;
239 /* If we are making a group of changes, return 1. Otherwise, validate the
240 change group we made. */
245 return apply_change_group ();
248 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
252 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
254 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
257 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
261 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
263 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
267 /* Keep X canonicalized if some changes have made it non-canonical; only
268 modifies the operands of X, not (for example) its code. Simplifications
269 are not the job of this routine.
271 Return true if anything was changed. */
273 canonicalize_change_group (rtx insn
, rtx x
)
275 if (COMMUTATIVE_P (x
)
276 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
278 /* Oops, the caller has made X no longer canonical.
279 Let's redo the changes in the correct order. */
280 rtx tem
= XEXP (x
, 0);
281 validate_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
282 validate_change (insn
, &XEXP (x
, 1), tem
, 1);
290 /* This subroutine of apply_change_group verifies whether the changes to INSN
291 were valid; i.e. whether INSN can still be recognized. */
294 insn_invalid_p (rtx insn
)
296 rtx pat
= PATTERN (insn
);
297 int num_clobbers
= 0;
298 /* If we are before reload and the pattern is a SET, see if we can add
300 int icode
= recog (pat
, insn
,
301 (GET_CODE (pat
) == SET
302 && ! reload_completed
&& ! reload_in_progress
)
303 ? &num_clobbers
: 0);
304 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
307 /* If this is an asm and the operand aren't legal, then fail. Likewise if
308 this is not an asm and the insn wasn't recognized. */
309 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
310 || (!is_asm
&& icode
< 0))
313 /* If we have to add CLOBBERs, fail if we have to add ones that reference
314 hard registers since our callers can't know if they are live or not.
315 Otherwise, add them. */
316 if (num_clobbers
> 0)
320 if (added_clobbers_hard_reg_p (icode
))
323 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
324 XVECEXP (newpat
, 0, 0) = pat
;
325 add_clobbers (newpat
, icode
);
326 PATTERN (insn
) = pat
= newpat
;
329 /* After reload, verify that all constraints are satisfied. */
330 if (reload_completed
)
334 if (! constrain_operands (1))
338 INSN_CODE (insn
) = icode
;
342 /* Return number of changes made and not validated yet. */
344 num_changes_pending (void)
349 /* Tentatively apply the changes numbered NUM and up.
350 Return 1 if all changes are valid, zero otherwise. */
353 verify_changes (int num
)
356 rtx last_validated
= NULL_RTX
;
358 /* The changes have been applied and all INSN_CODEs have been reset to force
361 The changes are valid if we aren't given an object, or if we are
362 given a MEM and it still is a valid address, or if this is in insn
363 and it is recognized. In the latter case, if reload has completed,
364 we also require that the operands meet the constraints for
367 for (i
= num
; i
< num_changes
; i
++)
369 rtx object
= changes
[i
].object
;
371 /* If there is no object to test or if it is the same as the one we
372 already tested, ignore it. */
373 if (object
== 0 || object
== last_validated
)
378 if (! memory_address_addr_space_p (GET_MODE (object
),
380 MEM_ADDR_SPACE (object
)))
383 else if (REG_P (changes
[i
].old
)
384 && asm_noperands (PATTERN (object
)) > 0
385 && REG_EXPR (changes
[i
].old
) != NULL_TREE
386 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
387 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
389 /* Don't allow changes of hard register operands to inline
390 assemblies if they have been defined as register asm ("x"). */
393 else if (DEBUG_INSN_P (object
))
395 else if (insn_invalid_p (object
))
397 rtx pat
= PATTERN (object
);
399 /* Perhaps we couldn't recognize the insn because there were
400 extra CLOBBERs at the end. If so, try to re-recognize
401 without the last CLOBBER (later iterations will cause each of
402 them to be eliminated, in turn). But don't do this if we
403 have an ASM_OPERAND. */
404 if (GET_CODE (pat
) == PARALLEL
405 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
406 && asm_noperands (PATTERN (object
)) < 0)
410 if (XVECLEN (pat
, 0) == 2)
411 newpat
= XVECEXP (pat
, 0, 0);
417 = gen_rtx_PARALLEL (VOIDmode
,
418 rtvec_alloc (XVECLEN (pat
, 0) - 1));
419 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
420 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
423 /* Add a new change to this group to replace the pattern
424 with this new pattern. Then consider this change
425 as having succeeded. The change we added will
426 cause the entire call to fail if things remain invalid.
428 Note that this can lose if a later change than the one
429 we are processing specified &XVECEXP (PATTERN (object), 0, X)
430 but this shouldn't occur. */
432 validate_change (object
, &PATTERN (object
), newpat
, 1);
435 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
436 || GET_CODE (pat
) == VAR_LOCATION
)
437 /* If this insn is a CLOBBER or USE, it is always valid, but is
443 last_validated
= object
;
446 return (i
== num_changes
);
449 /* A group of changes has previously been issued with validate_change
450 and verified with verify_changes. Call df_insn_rescan for each of
451 the insn changed and clear num_changes. */
454 confirm_change_group (void)
457 rtx last_object
= NULL
;
459 for (i
= 0; i
< num_changes
; i
++)
461 rtx object
= changes
[i
].object
;
463 if (changes
[i
].unshare
)
464 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
466 /* Avoid unnecessary rescanning when multiple changes to same instruction
470 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
471 df_insn_rescan (last_object
);
472 last_object
= object
;
476 if (last_object
&& INSN_P (last_object
))
477 df_insn_rescan (last_object
);
481 /* Apply a group of changes previously issued with `validate_change'.
482 If all changes are valid, call confirm_change_group and return 1,
483 otherwise, call cancel_changes and return 0. */
486 apply_change_group (void)
488 if (verify_changes (0))
490 confirm_change_group ();
501 /* Return the number of changes so far in the current group. */
504 num_validated_changes (void)
509 /* Retract the changes numbered NUM and up. */
512 cancel_changes (int num
)
516 /* Back out all the changes. Do this in the opposite order in which
518 for (i
= num_changes
- 1; i
>= num
; i
--)
520 *changes
[i
].loc
= changes
[i
].old
;
521 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
522 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
527 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
531 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
532 enum machine_mode op0_mode
)
535 enum rtx_code code
= GET_CODE (x
);
538 if (SWAPPABLE_OPERANDS_P (x
)
539 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
541 validate_unshare_change (object
, loc
,
542 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
543 : swap_condition (code
),
544 GET_MODE (x
), XEXP (x
, 1),
553 /* If we have a PLUS whose second operand is now a CONST_INT, use
554 simplify_gen_binary to try to simplify it.
555 ??? We may want later to remove this, once simplification is
556 separated from this function. */
557 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
558 validate_change (object
, loc
,
560 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
563 if (CONST_INT_P (XEXP (x
, 1))
564 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
565 validate_change (object
, loc
,
567 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
568 simplify_gen_unary (NEG
,
569 GET_MODE (x
), XEXP (x
, 1),
574 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
576 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
578 /* If any of the above failed, substitute in something that
579 we know won't be recognized. */
581 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
582 validate_change (object
, loc
, new_rtx
, 1);
586 /* All subregs possible to simplify should be simplified. */
587 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
590 /* Subregs of VOIDmode operands are incorrect. */
591 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
592 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
594 validate_change (object
, loc
, new_rtx
, 1);
598 /* If we are replacing a register with memory, try to change the memory
599 to be the mode required for memory in extract operations (this isn't
600 likely to be an insertion operation; if it was, nothing bad will
601 happen, we might just fail in some cases). */
603 if (MEM_P (XEXP (x
, 0))
604 && CONST_INT_P (XEXP (x
, 1))
605 && CONST_INT_P (XEXP (x
, 2))
606 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
607 && !MEM_VOLATILE_P (XEXP (x
, 0)))
609 enum machine_mode wanted_mode
= VOIDmode
;
610 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
611 int pos
= INTVAL (XEXP (x
, 2));
613 if (GET_CODE (x
) == ZERO_EXTRACT
)
615 enum machine_mode new_mode
616 = mode_for_extraction (EP_extzv
, 1);
617 if (new_mode
!= MAX_MACHINE_MODE
)
618 wanted_mode
= new_mode
;
620 else if (GET_CODE (x
) == SIGN_EXTRACT
)
622 enum machine_mode new_mode
623 = mode_for_extraction (EP_extv
, 1);
624 if (new_mode
!= MAX_MACHINE_MODE
)
625 wanted_mode
= new_mode
;
628 /* If we have a narrower mode, we can do something. */
629 if (wanted_mode
!= VOIDmode
630 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
632 int offset
= pos
/ BITS_PER_UNIT
;
635 /* If the bytes and bits are counted differently, we
636 must adjust the offset. */
637 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
639 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
642 pos
%= GET_MODE_BITSIZE (wanted_mode
);
644 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
646 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
647 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
658 /* Replace every occurrence of FROM in X with TO. Mark each change with
659 validate_change passing OBJECT. */
662 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
669 enum machine_mode op0_mode
= VOIDmode
;
670 int prev_changes
= num_changes
;
676 fmt
= GET_RTX_FORMAT (code
);
678 op0_mode
= GET_MODE (XEXP (x
, 0));
680 /* X matches FROM if it is the same rtx or they are both referring to the
681 same register in the same mode. Avoid calling rtx_equal_p unless the
682 operands look similar. */
685 || (REG_P (x
) && REG_P (from
)
686 && GET_MODE (x
) == GET_MODE (from
)
687 && REGNO (x
) == REGNO (from
))
688 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
689 && rtx_equal_p (x
, from
)))
691 validate_unshare_change (object
, loc
, to
, 1);
695 /* Call ourself recursively to perform the replacements.
696 We must not replace inside already replaced expression, otherwise we
697 get infinite recursion for replacements like (reg X)->(subreg (reg X))
698 done by regmove, so we must special case shared ASM_OPERANDS. */
700 if (GET_CODE (x
) == PARALLEL
)
702 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
704 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
705 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
707 /* Verify that operands are really shared. */
708 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
709 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
711 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
712 from
, to
, object
, simplify
);
715 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
720 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
723 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
724 else if (fmt
[i
] == 'E')
725 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
726 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
730 /* If we didn't substitute, there is nothing more to do. */
731 if (num_changes
== prev_changes
)
734 /* Allow substituted expression to have different mode. This is used by
735 regmove to change mode of pseudo register. */
736 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
737 op0_mode
= GET_MODE (XEXP (x
, 0));
739 /* Do changes needed to keep rtx consistent. Don't do any other
740 simplifications, as it is not our job. */
742 simplify_while_replacing (loc
, to
, object
, op0_mode
);
745 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
746 with TO. After all changes have been made, validate by seeing
747 if INSN is still valid. */
750 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
752 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
753 return apply_change_group ();
756 /* Try replacing every occurrence of FROM in INSN with TO. After all
757 changes have been made, validate by seeing if INSN is still valid. */
760 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
762 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
763 return apply_change_group ();
766 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
767 is a part of INSN. After all changes have been made, validate by seeing if
769 validate_replace_rtx (from, to, insn) is equivalent to
770 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
773 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
775 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
776 return apply_change_group ();
779 /* Same as above, but do not simplify rtx afterwards. */
781 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
784 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
785 return apply_change_group ();
789 /* Try replacing every occurrence of FROM in INSN with TO. This also
790 will replace in REG_EQUAL and REG_EQUIV notes. */
793 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
796 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
797 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
798 if (REG_NOTE_KIND (note
) == REG_EQUAL
799 || REG_NOTE_KIND (note
) == REG_EQUIV
)
800 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
803 /* Function called by note_uses to replace used subexpressions. */
804 struct validate_replace_src_data
806 rtx from
; /* Old RTX */
807 rtx to
; /* New RTX */
808 rtx insn
; /* Insn in which substitution is occurring. */
812 validate_replace_src_1 (rtx
*x
, void *data
)
814 struct validate_replace_src_data
*d
815 = (struct validate_replace_src_data
*) data
;
817 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
820 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
824 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
826 struct validate_replace_src_data d
;
831 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
834 /* Try simplify INSN.
835 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
836 pattern and return true if something was simplified. */
839 validate_simplify_insn (rtx insn
)
845 pat
= PATTERN (insn
);
847 if (GET_CODE (pat
) == SET
)
849 newpat
= simplify_rtx (SET_SRC (pat
));
850 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
851 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
852 newpat
= simplify_rtx (SET_DEST (pat
));
853 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
854 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
856 else if (GET_CODE (pat
) == PARALLEL
)
857 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
859 rtx s
= XVECEXP (pat
, 0, i
);
861 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
863 newpat
= simplify_rtx (SET_SRC (s
));
864 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
865 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
866 newpat
= simplify_rtx (SET_DEST (s
));
867 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
868 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
871 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
875 /* Return 1 if the insn using CC0 set by INSN does not contain
876 any ordered tests applied to the condition codes.
877 EQ and NE tests do not count. */
880 next_insn_tests_no_inequality (rtx insn
)
882 rtx next
= next_cc0_user (insn
);
884 /* If there is no next insn, we have to take the conservative choice. */
888 return (INSN_P (next
)
889 && ! inequality_comparisons_p (PATTERN (next
)));
893 /* Return 1 if OP is a valid general operand for machine mode MODE.
894 This is either a register reference, a memory reference,
895 or a constant. In the case of a memory reference, the address
896 is checked for general validity for the target machine.
898 Register and memory references must have mode MODE in order to be valid,
899 but some constants have no machine mode and are valid for any mode.
901 If MODE is VOIDmode, OP is checked for validity for whatever mode
904 The main use of this function is as a predicate in match_operand
905 expressions in the machine description.
907 For an explanation of this function's behavior for registers of
908 class NO_REGS, see the comment for `register_operand'. */
911 general_operand (rtx op
, enum machine_mode mode
)
913 enum rtx_code code
= GET_CODE (op
);
915 if (mode
== VOIDmode
)
916 mode
= GET_MODE (op
);
918 /* Don't accept CONST_INT or anything similar
919 if the caller wants something floating. */
920 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
921 && GET_MODE_CLASS (mode
) != MODE_INT
922 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
927 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
931 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
933 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
934 && LEGITIMATE_CONSTANT_P (op
));
936 /* Except for certain constants with VOIDmode, already checked for,
937 OP's mode must match MODE if MODE specifies a mode. */
939 if (GET_MODE (op
) != mode
)
944 rtx sub
= SUBREG_REG (op
);
946 #ifdef INSN_SCHEDULING
947 /* On machines that have insn scheduling, we want all memory
948 reference to be explicit, so outlaw paradoxical SUBREGs.
949 However, we must allow them after reload so that they can
950 get cleaned up by cleanup_subreg_operands. */
951 if (!reload_completed
&& MEM_P (sub
)
952 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
955 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
956 may result in incorrect reference. We should simplify all valid
957 subregs of MEM anyway. But allow this after reload because we
958 might be called from cleanup_subreg_operands.
960 ??? This is a kludge. */
961 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
965 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
966 create such rtl, and we must reject it. */
967 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
968 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
972 code
= GET_CODE (op
);
976 /* A register whose class is NO_REGS is not a general operand. */
977 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
978 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
982 rtx y
= XEXP (op
, 0);
984 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
987 /* Use the mem's mode, since it will be reloaded thus. */
988 if (memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
995 /* Return 1 if OP is a valid memory address for a memory reference
998 The main use of this function is as a predicate in match_operand
999 expressions in the machine description. */
1002 address_operand (rtx op
, enum machine_mode mode
)
1004 return memory_address_p (mode
, op
);
1007 /* Return 1 if OP is a register reference of mode MODE.
1008 If MODE is VOIDmode, accept a register in any mode.
1010 The main use of this function is as a predicate in match_operand
1011 expressions in the machine description.
1013 As a special exception, registers whose class is NO_REGS are
1014 not accepted by `register_operand'. The reason for this change
1015 is to allow the representation of special architecture artifacts
1016 (such as a condition code register) without extending the rtl
1017 definitions. Since registers of class NO_REGS cannot be used
1018 as registers in any case where register classes are examined,
1019 it is most consistent to keep this function from accepting them. */
1022 register_operand (rtx op
, enum machine_mode mode
)
1024 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1027 if (GET_CODE (op
) == SUBREG
)
1029 rtx sub
= SUBREG_REG (op
);
1031 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1032 because it is guaranteed to be reloaded into one.
1033 Just make sure the MEM is valid in itself.
1034 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1035 but currently it does result from (SUBREG (REG)...) where the
1036 reg went on the stack.) */
1037 if (! reload_completed
&& MEM_P (sub
))
1038 return general_operand (op
, mode
);
1040 #ifdef CANNOT_CHANGE_MODE_CLASS
1042 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1043 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1044 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1045 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
)
1049 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1050 create such rtl, and we must reject it. */
1051 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1052 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1058 /* We don't consider registers whose class is NO_REGS
1059 to be a register operand. */
1061 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1062 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1065 /* Return 1 for a register in Pmode; ignore the tested mode. */
1068 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1070 return register_operand (op
, Pmode
);
1073 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1074 or a hard register. */
1077 scratch_operand (rtx op
, enum machine_mode mode
)
1079 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1082 return (GET_CODE (op
) == SCRATCH
1084 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1087 /* Return 1 if OP is a valid immediate operand for mode MODE.
1089 The main use of this function is as a predicate in match_operand
1090 expressions in the machine description. */
1093 immediate_operand (rtx op
, enum machine_mode mode
)
1095 /* Don't accept CONST_INT or anything similar
1096 if the caller wants something floating. */
1097 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1098 && GET_MODE_CLASS (mode
) != MODE_INT
1099 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1102 if (CONST_INT_P (op
)
1104 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1107 return (CONSTANT_P (op
)
1108 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1109 || GET_MODE (op
) == VOIDmode
)
1110 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1111 && LEGITIMATE_CONSTANT_P (op
));
1114 /* Returns 1 if OP is an operand that is a CONST_INT. */
1117 const_int_operand (rtx op
, enum machine_mode mode
)
1119 if (!CONST_INT_P (op
))
1122 if (mode
!= VOIDmode
1123 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1129 /* Returns 1 if OP is an operand that is a constant integer or constant
1130 floating-point number. */
1133 const_double_operand (rtx op
, enum machine_mode mode
)
1135 /* Don't accept CONST_INT or anything similar
1136 if the caller wants something floating. */
1137 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1138 && GET_MODE_CLASS (mode
) != MODE_INT
1139 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1142 return ((GET_CODE (op
) == CONST_DOUBLE
|| CONST_INT_P (op
))
1143 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1144 || GET_MODE (op
) == VOIDmode
));
1147 /* Return 1 if OP is a general operand that is not an immediate operand. */
1150 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1152 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1155 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1158 nonmemory_operand (rtx op
, enum machine_mode mode
)
1160 if (CONSTANT_P (op
))
1162 /* Don't accept CONST_INT or anything similar
1163 if the caller wants something floating. */
1164 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1165 && GET_MODE_CLASS (mode
) != MODE_INT
1166 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1169 if (CONST_INT_P (op
)
1171 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1174 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1175 || mode
== VOIDmode
)
1176 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1177 && LEGITIMATE_CONSTANT_P (op
));
1180 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1183 if (GET_CODE (op
) == SUBREG
)
1185 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1186 because it is guaranteed to be reloaded into one.
1187 Just make sure the MEM is valid in itself.
1188 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1189 but currently it does result from (SUBREG (REG)...) where the
1190 reg went on the stack.) */
1191 if (! reload_completed
&& MEM_P (SUBREG_REG (op
)))
1192 return general_operand (op
, mode
);
1193 op
= SUBREG_REG (op
);
1196 /* We don't consider registers whose class is NO_REGS
1197 to be a register operand. */
1199 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1200 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1203 /* Return 1 if OP is a valid operand that stands for pushing a
1204 value of mode MODE onto the stack.
1206 The main use of this function is as a predicate in match_operand
1207 expressions in the machine description. */
1210 push_operand (rtx op
, enum machine_mode mode
)
1212 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1214 #ifdef PUSH_ROUNDING
1215 rounded_size
= PUSH_ROUNDING (rounded_size
);
1221 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1226 if (rounded_size
== GET_MODE_SIZE (mode
))
1228 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1233 if (GET_CODE (op
) != PRE_MODIFY
1234 || GET_CODE (XEXP (op
, 1)) != PLUS
1235 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1236 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1237 #ifdef STACK_GROWS_DOWNWARD
1238 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1240 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1246 return XEXP (op
, 0) == stack_pointer_rtx
;
1249 /* Return 1 if OP is a valid operand that stands for popping a
1250 value of mode MODE off the stack.
1252 The main use of this function is as a predicate in match_operand
1253 expressions in the machine description. */
1256 pop_operand (rtx op
, enum machine_mode mode
)
1261 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1266 if (GET_CODE (op
) != STACK_POP_CODE
)
1269 return XEXP (op
, 0) == stack_pointer_rtx
;
1272 /* Return 1 if ADDR is a valid memory address
1273 for mode MODE in address space AS. */
1276 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1277 rtx addr
, addr_space_t as
)
1279 #ifdef GO_IF_LEGITIMATE_ADDRESS
1280 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1281 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1287 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1291 /* Return 1 if OP is a valid memory reference with mode MODE,
1292 including a valid address.
1294 The main use of this function is as a predicate in match_operand
1295 expressions in the machine description. */
1298 memory_operand (rtx op
, enum machine_mode mode
)
1302 if (! reload_completed
)
1303 /* Note that no SUBREG is a memory operand before end of reload pass,
1304 because (SUBREG (MEM...)) forces reloading into a register. */
1305 return MEM_P (op
) && general_operand (op
, mode
);
1307 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1311 if (GET_CODE (inner
) == SUBREG
)
1312 inner
= SUBREG_REG (inner
);
1314 return (MEM_P (inner
) && general_operand (op
, mode
));
1317 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1318 that is, a memory reference whose address is a general_operand. */
1321 indirect_operand (rtx op
, enum machine_mode mode
)
1323 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1324 if (! reload_completed
1325 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1327 int offset
= SUBREG_BYTE (op
);
1328 rtx inner
= SUBREG_REG (op
);
1330 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1333 /* The only way that we can have a general_operand as the resulting
1334 address is if OFFSET is zero and the address already is an operand
1335 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1338 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1339 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1340 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1341 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1342 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1346 && memory_operand (op
, mode
)
1347 && general_operand (XEXP (op
, 0), Pmode
));
1350 /* Return 1 if this is an ordered comparison operator (not including
1351 ORDERED and UNORDERED). */
1354 ordered_comparison_operator (rtx op
, enum machine_mode mode
)
1356 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1358 switch (GET_CODE (op
))
1376 /* Return 1 if this is a comparison operator. This allows the use of
1377 MATCH_OPERATOR to recognize all the branch insns. */
1380 comparison_operator (rtx op
, enum machine_mode mode
)
1382 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1383 && COMPARISON_P (op
));
1386 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1389 extract_asm_operands (rtx body
)
1392 switch (GET_CODE (body
))
1398 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1399 tmp
= SET_SRC (body
);
1400 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1405 tmp
= XVECEXP (body
, 0, 0);
1406 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1408 if (GET_CODE (tmp
) == SET
)
1410 tmp
= SET_SRC (tmp
);
1411 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1422 /* If BODY is an insn body that uses ASM_OPERANDS,
1423 return the number of operands (both input and output) in the insn.
1424 Otherwise return -1. */
1427 asm_noperands (const_rtx body
)
1429 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1435 if (GET_CODE (body
) == SET
)
1437 else if (GET_CODE (body
) == PARALLEL
)
1440 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1442 /* Multiple output operands, or 1 output plus some clobbers:
1444 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1445 /* Count backwards through CLOBBERs to determine number of SETs. */
1446 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1448 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1450 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1454 /* N_SETS is now number of output operands. */
1457 /* Verify that all the SETs we have
1458 came from a single original asm_operands insn
1459 (so that invalid combinations are blocked). */
1460 for (i
= 0; i
< n_sets
; i
++)
1462 rtx elt
= XVECEXP (body
, 0, i
);
1463 if (GET_CODE (elt
) != SET
)
1465 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1467 /* If these ASM_OPERANDS rtx's came from different original insns
1468 then they aren't allowed together. */
1469 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1470 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1476 /* 0 outputs, but some clobbers:
1477 body is [(asm_operands ...) (clobber (reg ...))...]. */
1478 /* Make sure all the other parallel things really are clobbers. */
1479 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1480 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1485 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1486 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1489 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1490 copy its operands (both input and output) into the vector OPERANDS,
1491 the locations of the operands within the insn into the vector OPERAND_LOCS,
1492 and the constraints for the operands into CONSTRAINTS.
1493 Write the modes of the operands into MODES.
1494 Return the assembler-template.
1496 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1497 we don't store that info. */
1500 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1501 const char **constraints
, enum machine_mode
*modes
,
1504 int nbase
= 0, n
, i
;
1507 switch (GET_CODE (body
))
1510 /* Zero output asm: BODY is (asm_operands ...). */
1515 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1516 asmop
= SET_SRC (body
);
1518 /* The output is in the SET.
1519 Its constraint is in the ASM_OPERANDS itself. */
1521 operands
[0] = SET_DEST (body
);
1523 operand_locs
[0] = &SET_DEST (body
);
1525 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1527 modes
[0] = GET_MODE (SET_DEST (body
));
1533 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1535 asmop
= XVECEXP (body
, 0, 0);
1536 if (GET_CODE (asmop
) == SET
)
1538 asmop
= SET_SRC (asmop
);
1540 /* At least one output, plus some CLOBBERs. The outputs are in
1541 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1542 for (i
= 0; i
< nparallel
; i
++)
1544 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1545 break; /* Past last SET */
1547 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1549 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1551 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1553 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1564 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1565 for (i
= 0; i
< n
; i
++)
1568 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1570 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1572 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1574 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1578 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1579 for (i
= 0; i
< n
; i
++)
1582 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1584 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1586 constraints
[nbase
+ i
] = "";
1588 modes
[nbase
+ i
] = Pmode
;
1592 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1594 return ASM_OPERANDS_TEMPLATE (asmop
);
1597 /* Check if an asm_operand matches its constraints.
1598 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1601 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1605 bool incdec_ok
= false;
1608 /* Use constrain_operands after reload. */
1609 gcc_assert (!reload_completed
);
1611 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1612 many alternatives as required to match the other operands. */
1613 if (*constraint
== '\0')
1618 char c
= *constraint
;
1635 case '0': case '1': case '2': case '3': case '4':
1636 case '5': case '6': case '7': case '8': case '9':
1637 /* If caller provided constraints pointer, look up
1638 the maching constraint. Otherwise, our caller should have
1639 given us the proper matching constraint, but we can't
1640 actually fail the check if they didn't. Indicate that
1641 results are inconclusive. */
1645 unsigned long match
;
1647 match
= strtoul (constraint
, &end
, 10);
1649 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1650 constraint
= (const char *) end
;
1656 while (ISDIGIT (*constraint
));
1663 if (address_operand (op
, VOIDmode
))
1667 case TARGET_MEM_CONSTRAINT
:
1668 case 'V': /* non-offsettable */
1669 if (memory_operand (op
, VOIDmode
))
1673 case 'o': /* offsettable */
1674 if (offsettable_nonstrict_memref_p (op
))
1679 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1680 excepting those that expand_call created. Further, on some
1681 machines which do not have generalized auto inc/dec, an inc/dec
1682 is not a memory_operand.
1684 Match any memory and hope things are resolved after reload. */
1688 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1689 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1699 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1700 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1709 if (GET_CODE (op
) == CONST_DOUBLE
1710 || (GET_CODE (op
) == CONST_VECTOR
1711 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1716 if (GET_CODE (op
) == CONST_DOUBLE
1717 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1721 if (GET_CODE (op
) == CONST_DOUBLE
1722 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1727 if (CONST_INT_P (op
)
1728 || (GET_CODE (op
) == CONST_DOUBLE
1729 && GET_MODE (op
) == VOIDmode
))
1734 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1739 if (CONST_INT_P (op
)
1740 || (GET_CODE (op
) == CONST_DOUBLE
1741 && GET_MODE (op
) == VOIDmode
))
1746 if (CONST_INT_P (op
)
1747 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1751 if (CONST_INT_P (op
)
1752 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1756 if (CONST_INT_P (op
)
1757 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1761 if (CONST_INT_P (op
)
1762 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1766 if (CONST_INT_P (op
)
1767 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1771 if (CONST_INT_P (op
)
1772 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1776 if (CONST_INT_P (op
)
1777 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1781 if (CONST_INT_P (op
)
1782 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1791 if (general_operand (op
, VOIDmode
))
1796 /* For all other letters, we first check for a register class,
1797 otherwise it is an EXTRA_CONSTRAINT. */
1798 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1801 if (GET_MODE (op
) == BLKmode
)
1803 if (register_operand (op
, VOIDmode
))
1806 #ifdef EXTRA_CONSTRAINT_STR
1807 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
))
1808 /* Every memory operand can be reloaded to fit. */
1809 result
= result
|| memory_operand (op
, VOIDmode
);
1810 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
))
1811 /* Every address operand can be reloaded to fit. */
1812 result
= result
|| address_operand (op
, VOIDmode
);
1813 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1818 len
= CONSTRAINT_LEN (c
, constraint
);
1821 while (--len
&& *constraint
);
1827 /* For operands without < or > constraints reject side-effects. */
1828 if (!incdec_ok
&& result
&& MEM_P (op
))
1829 switch (GET_CODE (XEXP (op
, 0)))
1846 /* Given an rtx *P, if it is a sum containing an integer constant term,
1847 return the location (type rtx *) of the pointer to that constant term.
1848 Otherwise, return a null pointer. */
1851 find_constant_term_loc (rtx
*p
)
1854 enum rtx_code code
= GET_CODE (*p
);
1856 /* If *P IS such a constant term, P is its location. */
1858 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1862 /* Otherwise, if not a sum, it has no constant term. */
1864 if (GET_CODE (*p
) != PLUS
)
1867 /* If one of the summands is constant, return its location. */
1869 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1870 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1873 /* Otherwise, check each summand for containing a constant term. */
1875 if (XEXP (*p
, 0) != 0)
1877 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1882 if (XEXP (*p
, 1) != 0)
1884 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1892 /* Return 1 if OP is a memory reference
1893 whose address contains no side effects
1894 and remains valid after the addition
1895 of a positive integer less than the
1896 size of the object being referenced.
1898 We assume that the original address is valid and do not check it.
1900 This uses strict_memory_address_p as a subroutine, so
1901 don't use it before reload. */
1904 offsettable_memref_p (rtx op
)
1906 return ((MEM_P (op
))
1907 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1908 MEM_ADDR_SPACE (op
)));
1911 /* Similar, but don't require a strictly valid mem ref:
1912 consider pseudo-regs valid as index or base regs. */
1915 offsettable_nonstrict_memref_p (rtx op
)
1917 return ((MEM_P (op
))
1918 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1919 MEM_ADDR_SPACE (op
)));
1922 /* Return 1 if Y is a memory address which contains no side effects
1923 and would remain valid for address space AS after the addition of
1924 a positive integer less than the size of that mode.
1926 We assume that the original address is valid and do not check it.
1927 We do check that it is valid for narrower modes.
1929 If STRICTP is nonzero, we require a strictly valid address,
1930 for the sake of use in reload.c. */
1933 offsettable_address_addr_space_p (int strictp
, enum machine_mode mode
, rtx y
,
1936 enum rtx_code ycode
= GET_CODE (y
);
1940 int (*addressp
) (enum machine_mode
, rtx
, addr_space_t
) =
1941 (strictp
? strict_memory_address_addr_space_p
1942 : memory_address_addr_space_p
);
1943 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1945 if (CONSTANT_ADDRESS_P (y
))
1948 /* Adjusting an offsettable address involves changing to a narrower mode.
1949 Make sure that's OK. */
1951 if (mode_dependent_address_p (y
))
1954 /* ??? How much offset does an offsettable BLKmode reference need?
1955 Clearly that depends on the situation in which it's being used.
1956 However, the current situation in which we test 0xffffffff is
1957 less than ideal. Caveat user. */
1959 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1961 /* If the expression contains a constant term,
1962 see if it remains valid when max possible offset is added. */
1964 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1969 *y2
= plus_constant (*y2
, mode_sz
- 1);
1970 /* Use QImode because an odd displacement may be automatically invalid
1971 for any wider mode. But it should be valid for a single byte. */
1972 good
= (*addressp
) (QImode
, y
, as
);
1974 /* In any case, restore old contents of memory. */
1979 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1982 /* The offset added here is chosen as the maximum offset that
1983 any instruction could need to add when operating on something
1984 of the specified mode. We assume that if Y and Y+c are
1985 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1986 go inside a LO_SUM here, so we do so as well. */
1987 if (GET_CODE (y
) == LO_SUM
1989 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
1990 z
= gen_rtx_LO_SUM (GET_MODE (y
), XEXP (y
, 0),
1991 plus_constant (XEXP (y
, 1), mode_sz
- 1));
1993 z
= plus_constant (y
, mode_sz
- 1);
1995 /* Use QImode because an odd displacement may be automatically invalid
1996 for any wider mode. But it should be valid for a single byte. */
1997 return (*addressp
) (QImode
, z
, as
);
2000 /* Return 1 if ADDR is an address-expression whose effect depends
2001 on the mode of the memory reference it is used in.
2003 Autoincrement addressing is a typical example of mode-dependence
2004 because the amount of the increment depends on the mode. */
2007 mode_dependent_address_p (rtx addr
)
2009 /* Auto-increment addressing with anything other than post_modify
2010 or pre_modify always introduces a mode dependency. Catch such
2011 cases now instead of deferring to the target. */
2012 if (GET_CODE (addr
) == PRE_INC
2013 || GET_CODE (addr
) == POST_INC
2014 || GET_CODE (addr
) == PRE_DEC
2015 || GET_CODE (addr
) == POST_DEC
)
2018 return targetm
.mode_dependent_address_p (addr
);
2021 /* Like extract_insn, but save insn extracted and don't extract again, when
2022 called again for the same insn expecting that recog_data still contain the
2023 valid information. This is used primary by gen_attr infrastructure that
2024 often does extract insn again and again. */
2026 extract_insn_cached (rtx insn
)
2028 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2030 extract_insn (insn
);
2031 recog_data
.insn
= insn
;
2034 /* Do cached extract_insn, constrain_operands and complain about failures.
2035 Used by insn_attrtab. */
2037 extract_constrain_insn_cached (rtx insn
)
2039 extract_insn_cached (insn
);
2040 if (which_alternative
== -1
2041 && !constrain_operands (reload_completed
))
2042 fatal_insn_not_found (insn
);
2045 /* Do cached constrain_operands and complain about failures. */
2047 constrain_operands_cached (int strict
)
2049 if (which_alternative
== -1)
2050 return constrain_operands (strict
);
2055 /* Analyze INSN and fill in recog_data. */
2058 extract_insn (rtx insn
)
2063 rtx body
= PATTERN (insn
);
2065 recog_data
.n_operands
= 0;
2066 recog_data
.n_alternatives
= 0;
2067 recog_data
.n_dups
= 0;
2068 recog_data
.is_asm
= false;
2070 switch (GET_CODE (body
))
2081 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2086 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2087 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2088 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2094 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2097 /* This insn is an `asm' with operands. */
2099 /* expand_asm_operands makes sure there aren't too many operands. */
2100 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2102 /* Now get the operand values and constraints out of the insn. */
2103 decode_asm_operands (body
, recog_data
.operand
,
2104 recog_data
.operand_loc
,
2105 recog_data
.constraints
,
2106 recog_data
.operand_mode
, NULL
);
2107 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2110 const char *p
= recog_data
.constraints
[0];
2111 recog_data
.n_alternatives
= 1;
2113 recog_data
.n_alternatives
+= (*p
++ == ',');
2115 recog_data
.is_asm
= true;
2118 fatal_insn_not_found (insn
);
2122 /* Ordinary insn: recognize it, get the operands via insn_extract
2123 and get the constraints. */
2125 icode
= recog_memoized (insn
);
2127 fatal_insn_not_found (insn
);
2129 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2130 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2131 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2133 insn_extract (insn
);
2135 for (i
= 0; i
< noperands
; i
++)
2137 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2138 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2139 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2140 /* VOIDmode match_operands gets mode from their real operand. */
2141 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2142 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2145 for (i
= 0; i
< noperands
; i
++)
2146 recog_data
.operand_type
[i
]
2147 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2148 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2151 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2153 if (INSN_CODE (insn
) < 0)
2154 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2155 recog_data
.alternative_enabled_p
[i
] = true;
2158 recog_data
.insn
= insn
;
2159 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2161 which_alternative
= i
;
2162 recog_data
.alternative_enabled_p
[i
] = get_attr_enabled (insn
);
2166 recog_data
.insn
= NULL
;
2167 which_alternative
= -1;
2170 /* After calling extract_insn, you can use this function to extract some
2171 information from the constraint strings into a more usable form.
2172 The collected data is stored in recog_op_alt. */
2174 preprocess_constraints (void)
2178 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2179 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2180 * sizeof (struct operand_alternative
)));
2182 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2185 struct operand_alternative
*op_alt
;
2186 const char *p
= recog_data
.constraints
[i
];
2188 op_alt
= recog_op_alt
[i
];
2190 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2192 op_alt
[j
].cl
= NO_REGS
;
2193 op_alt
[j
].constraint
= p
;
2194 op_alt
[j
].matches
= -1;
2195 op_alt
[j
].matched
= -1;
2197 if (!recog_data
.alternative_enabled_p
[j
])
2199 p
= skip_alternative (p
);
2203 if (*p
== '\0' || *p
== ',')
2205 op_alt
[j
].anything_ok
= 1;
2215 while (c
!= ',' && c
!= '\0');
2216 if (c
== ',' || c
== '\0')
2224 case '=': case '+': case '*': case '%':
2225 case 'E': case 'F': case 'G': case 'H':
2226 case 's': case 'i': case 'n':
2227 case 'I': case 'J': case 'K': case 'L':
2228 case 'M': case 'N': case 'O': case 'P':
2229 /* These don't say anything we care about. */
2233 op_alt
[j
].reject
+= 6;
2236 op_alt
[j
].reject
+= 600;
2239 op_alt
[j
].earlyclobber
= 1;
2242 case '0': case '1': case '2': case '3': case '4':
2243 case '5': case '6': case '7': case '8': case '9':
2246 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2247 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2252 case TARGET_MEM_CONSTRAINT
:
2253 op_alt
[j
].memory_ok
= 1;
2256 op_alt
[j
].decmem_ok
= 1;
2259 op_alt
[j
].incmem_ok
= 1;
2262 op_alt
[j
].nonoffmem_ok
= 1;
2265 op_alt
[j
].offmem_ok
= 1;
2268 op_alt
[j
].anything_ok
= 1;
2272 op_alt
[j
].is_address
= 1;
2273 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2274 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
2280 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2284 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2286 op_alt
[j
].memory_ok
= 1;
2289 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2291 op_alt
[j
].is_address
= 1;
2293 = (reg_class_subunion
2294 [(int) op_alt
[j
].cl
]
2295 [(int) base_reg_class (VOIDmode
, ADDRESS
,
2301 = (reg_class_subunion
2302 [(int) op_alt
[j
].cl
]
2303 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2306 p
+= CONSTRAINT_LEN (c
, p
);
2312 /* Check the operands of an insn against the insn's operand constraints
2313 and return 1 if they are valid.
2314 The information about the insn's operands, constraints, operand modes
2315 etc. is obtained from the global variables set up by extract_insn.
2317 WHICH_ALTERNATIVE is set to a number which indicates which
2318 alternative of constraints was matched: 0 for the first alternative,
2319 1 for the next, etc.
2321 In addition, when two operands are required to match
2322 and it happens that the output operand is (reg) while the
2323 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2324 make the output operand look like the input.
2325 This is because the output operand is the one the template will print.
2327 This is used in final, just before printing the assembler code and by
2328 the routines that determine an insn's attribute.
2330 If STRICT is a positive nonzero value, it means that we have been
2331 called after reload has been completed. In that case, we must
2332 do all checks strictly. If it is zero, it means that we have been called
2333 before reload has completed. In that case, we first try to see if we can
2334 find an alternative that matches strictly. If not, we try again, this
2335 time assuming that reload will fix up the insn. This provides a "best
2336 guess" for the alternative and is used to compute attributes of insns prior
2337 to reload. A negative value of STRICT is used for this internal call. */
2345 constrain_operands (int strict
)
2347 const char *constraints
[MAX_RECOG_OPERANDS
];
2348 int matching_operands
[MAX_RECOG_OPERANDS
];
2349 int earlyclobber
[MAX_RECOG_OPERANDS
];
2352 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2353 int funny_match_index
;
2355 which_alternative
= 0;
2356 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2359 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2361 constraints
[c
] = recog_data
.constraints
[c
];
2362 matching_operands
[c
] = -1;
2367 int seen_earlyclobber_at
= -1;
2370 funny_match_index
= 0;
2372 if (!recog_data
.alternative_enabled_p
[which_alternative
])
2376 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2377 constraints
[i
] = skip_alternative (constraints
[i
]);
2379 which_alternative
++;
2383 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2385 rtx op
= recog_data
.operand
[opno
];
2386 enum machine_mode mode
= GET_MODE (op
);
2387 const char *p
= constraints
[opno
];
2393 earlyclobber
[opno
] = 0;
2395 /* A unary operator may be accepted by the predicate, but it
2396 is irrelevant for matching constraints. */
2400 if (GET_CODE (op
) == SUBREG
)
2402 if (REG_P (SUBREG_REG (op
))
2403 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2404 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2405 GET_MODE (SUBREG_REG (op
)),
2408 op
= SUBREG_REG (op
);
2411 /* An empty constraint or empty alternative
2412 allows anything which matched the pattern. */
2413 if (*p
== 0 || *p
== ',')
2417 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2426 case '?': case '!': case '*': case '%':
2431 /* Ignore rest of this alternative as far as
2432 constraint checking is concerned. */
2435 while (*p
&& *p
!= ',');
2440 earlyclobber
[opno
] = 1;
2441 if (seen_earlyclobber_at
< 0)
2442 seen_earlyclobber_at
= opno
;
2445 case '0': case '1': case '2': case '3': case '4':
2446 case '5': case '6': case '7': case '8': case '9':
2448 /* This operand must be the same as a previous one.
2449 This kind of constraint is used for instructions such
2450 as add when they take only two operands.
2452 Note that the lower-numbered operand is passed first.
2454 If we are not testing strictly, assume that this
2455 constraint will be satisfied. */
2460 match
= strtoul (p
, &end
, 10);
2467 rtx op1
= recog_data
.operand
[match
];
2468 rtx op2
= recog_data
.operand
[opno
];
2470 /* A unary operator may be accepted by the predicate,
2471 but it is irrelevant for matching constraints. */
2473 op1
= XEXP (op1
, 0);
2475 op2
= XEXP (op2
, 0);
2477 val
= operands_match_p (op1
, op2
);
2480 matching_operands
[opno
] = match
;
2481 matching_operands
[match
] = opno
;
2486 /* If output is *x and input is *--x, arrange later
2487 to change the output to *--x as well, since the
2488 output op is the one that will be printed. */
2489 if (val
== 2 && strict
> 0)
2491 funny_match
[funny_match_index
].this_op
= opno
;
2492 funny_match
[funny_match_index
++].other
= match
;
2499 /* p is used for address_operands. When we are called by
2500 gen_reload, no one will have checked that the address is
2501 strictly valid, i.e., that all pseudos requiring hard regs
2502 have gotten them. */
2504 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2509 /* No need to check general_operand again;
2510 it was done in insn-recog.c. Well, except that reload
2511 doesn't check the validity of its replacements, but
2512 that should only matter when there's a bug. */
2514 /* Anything goes unless it is a REG and really has a hard reg
2515 but the hard reg is not in the class GENERAL_REGS. */
2519 || GENERAL_REGS
== ALL_REGS
2520 || (reload_in_progress
2521 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2522 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2525 else if (strict
< 0 || general_operand (op
, mode
))
2530 /* This is used for a MATCH_SCRATCH in the cases when
2531 we don't actually need anything. So anything goes
2536 case TARGET_MEM_CONSTRAINT
:
2537 /* Memory operands must be valid, to the extent
2538 required by STRICT. */
2542 && !strict_memory_address_addr_space_p
2543 (GET_MODE (op
), XEXP (op
, 0),
2544 MEM_ADDR_SPACE (op
)))
2547 && !memory_address_addr_space_p
2548 (GET_MODE (op
), XEXP (op
, 0),
2549 MEM_ADDR_SPACE (op
)))
2553 /* Before reload, accept what reload can turn into mem. */
2554 else if (strict
< 0 && CONSTANT_P (op
))
2556 /* During reload, accept a pseudo */
2557 else if (reload_in_progress
&& REG_P (op
)
2558 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2564 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2565 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2571 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2572 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2578 if (GET_CODE (op
) == CONST_DOUBLE
2579 || (GET_CODE (op
) == CONST_VECTOR
2580 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2586 if (GET_CODE (op
) == CONST_DOUBLE
2587 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2592 if (CONST_INT_P (op
)
2593 || (GET_CODE (op
) == CONST_DOUBLE
2594 && GET_MODE (op
) == VOIDmode
))
2597 if (CONSTANT_P (op
))
2602 if (CONST_INT_P (op
)
2603 || (GET_CODE (op
) == CONST_DOUBLE
2604 && GET_MODE (op
) == VOIDmode
))
2616 if (CONST_INT_P (op
)
2617 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2623 && ((strict
> 0 && ! offsettable_memref_p (op
))
2625 && !(CONSTANT_P (op
) || MEM_P (op
)))
2626 || (reload_in_progress
2628 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2633 if ((strict
> 0 && offsettable_memref_p (op
))
2634 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2635 /* Before reload, accept what reload can handle. */
2637 && (CONSTANT_P (op
) || MEM_P (op
)))
2638 /* During reload, accept a pseudo */
2639 || (reload_in_progress
&& REG_P (op
)
2640 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2649 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2655 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2656 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2658 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2661 #ifdef EXTRA_CONSTRAINT_STR
2662 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2665 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2666 /* Every memory operand can be reloaded to fit. */
2667 && ((strict
< 0 && MEM_P (op
))
2668 /* Before reload, accept what reload can turn
2670 || (strict
< 0 && CONSTANT_P (op
))
2671 /* During reload, accept a pseudo */
2672 || (reload_in_progress
&& REG_P (op
)
2673 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2675 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2676 /* Every address operand can be reloaded to fit. */
2683 while (p
+= len
, c
);
2685 constraints
[opno
] = p
;
2686 /* If this operand did not win somehow,
2687 this alternative loses. */
2691 /* This alternative won; the operands are ok.
2692 Change whichever operands this alternative says to change. */
2697 /* See if any earlyclobber operand conflicts with some other
2700 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2701 for (eopno
= seen_earlyclobber_at
;
2702 eopno
< recog_data
.n_operands
;
2704 /* Ignore earlyclobber operands now in memory,
2705 because we would often report failure when we have
2706 two memory operands, one of which was formerly a REG. */
2707 if (earlyclobber
[eopno
]
2708 && REG_P (recog_data
.operand
[eopno
]))
2709 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2710 if ((MEM_P (recog_data
.operand
[opno
])
2711 || recog_data
.operand_type
[opno
] != OP_OUT
)
2713 /* Ignore things like match_operator operands. */
2714 && *recog_data
.constraints
[opno
] != 0
2715 && ! (matching_operands
[opno
] == eopno
2716 && operands_match_p (recog_data
.operand
[opno
],
2717 recog_data
.operand
[eopno
]))
2718 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2719 recog_data
.operand
[eopno
]))
2724 while (--funny_match_index
>= 0)
2726 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2727 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2731 /* For operands without < or > constraints reject side-effects. */
2732 if (recog_data
.is_asm
)
2734 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2735 if (MEM_P (recog_data
.operand
[opno
]))
2736 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2744 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2745 || strchr (recog_data
.constraints
[opno
], '>')
2758 which_alternative
++;
2760 while (which_alternative
< recog_data
.n_alternatives
);
2762 which_alternative
= -1;
2763 /* If we are about to reject this, but we are not to test strictly,
2764 try a very loose test. Only return failure if it fails also. */
2766 return constrain_operands (-1);
2771 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2772 is a hard reg in class CLASS when its regno is offset by OFFSET
2773 and changed to mode MODE.
2774 If REG occupies multiple hard regs, all of them must be in CLASS. */
2777 reg_fits_class_p (rtx operand
, enum reg_class cl
, int offset
,
2778 enum machine_mode mode
)
2780 int regno
= REGNO (operand
);
2785 return (regno
< FIRST_PSEUDO_REGISTER
2786 && in_hard_reg_set_p (reg_class_contents
[(int) cl
],
2787 mode
, regno
+ offset
));
2790 /* Split single instruction. Helper function for split_all_insns and
2791 split_all_insns_noflow. Return last insn in the sequence if successful,
2792 or NULL if unsuccessful. */
2795 split_insn (rtx insn
)
2797 /* Split insns here to get max fine-grain parallelism. */
2798 rtx first
= PREV_INSN (insn
);
2799 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2800 rtx insn_set
, last_set
, note
;
2805 /* If the original instruction was a single set that was known to be
2806 equivalent to a constant, see if we can say the same about the last
2807 instruction in the split sequence. The two instructions must set
2808 the same destination. */
2809 insn_set
= single_set (insn
);
2812 last_set
= single_set (last
);
2813 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2815 note
= find_reg_equal_equiv_note (insn
);
2816 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2817 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2818 else if (CONSTANT_P (SET_SRC (insn_set
)))
2819 set_unique_reg_note (last
, REG_EQUAL
, SET_SRC (insn_set
));
2823 /* try_split returns the NOTE that INSN became. */
2824 SET_INSN_DELETED (insn
);
2826 /* ??? Coddle to md files that generate subregs in post-reload
2827 splitters instead of computing the proper hard register. */
2828 if (reload_completed
&& first
!= last
)
2830 first
= NEXT_INSN (first
);
2834 cleanup_subreg_operands (first
);
2837 first
= NEXT_INSN (first
);
2844 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2847 split_all_insns (void)
2853 blocks
= sbitmap_alloc (last_basic_block
);
2854 sbitmap_zero (blocks
);
2857 FOR_EACH_BB_REVERSE (bb
)
2860 bool finish
= false;
2862 rtl_profile_for_bb (bb
);
2863 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2865 /* Can't use `next_real_insn' because that might go across
2866 CODE_LABELS and short-out basic blocks. */
2867 next
= NEXT_INSN (insn
);
2868 finish
= (insn
== BB_END (bb
));
2871 rtx set
= single_set (insn
);
2873 /* Don't split no-op move insns. These should silently
2874 disappear later in final. Splitting such insns would
2875 break the code that handles LIBCALL blocks. */
2876 if (set
&& set_noop_p (set
))
2878 /* Nops get in the way while scheduling, so delete them
2879 now if register allocation has already been done. It
2880 is too risky to try to do this before register
2881 allocation, and there are unlikely to be very many
2882 nops then anyways. */
2883 if (reload_completed
)
2884 delete_insn_and_edges (insn
);
2888 rtx last
= split_insn (insn
);
2891 /* The split sequence may include barrier, but the
2892 BB boundary we are interested in will be set to
2895 while (BARRIER_P (last
))
2896 last
= PREV_INSN (last
);
2897 SET_BIT (blocks
, bb
->index
);
2905 default_rtl_profile ();
2907 find_many_sub_basic_blocks (blocks
);
2909 #ifdef ENABLE_CHECKING
2910 verify_flow_info ();
2913 sbitmap_free (blocks
);
2916 /* Same as split_all_insns, but do not expect CFG to be available.
2917 Used by machine dependent reorg passes. */
2920 split_all_insns_noflow (void)
2924 for (insn
= get_insns (); insn
; insn
= next
)
2926 next
= NEXT_INSN (insn
);
2929 /* Don't split no-op move insns. These should silently
2930 disappear later in final. Splitting such insns would
2931 break the code that handles LIBCALL blocks. */
2932 rtx set
= single_set (insn
);
2933 if (set
&& set_noop_p (set
))
2935 /* Nops get in the way while scheduling, so delete them
2936 now if register allocation has already been done. It
2937 is too risky to try to do this before register
2938 allocation, and there are unlikely to be very many
2941 ??? Should we use delete_insn when the CFG isn't valid? */
2942 if (reload_completed
)
2943 delete_insn_and_edges (insn
);
2952 #ifdef HAVE_peephole2
2953 struct peep2_insn_data
2959 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2960 static int peep2_current
;
2961 /* The number of instructions available to match a peep2. */
2962 int peep2_current_count
;
2964 /* A non-insn marker indicating the last insn of the block.
2965 The live_before regset for this element is correct, indicating
2966 DF_LIVE_OUT for the block. */
2967 #define PEEP2_EOB pc_rtx
2969 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2970 does not exist. Used by the recognizer to find the next insn to match
2971 in a multi-insn pattern. */
2974 peep2_next_insn (int n
)
2976 gcc_assert (n
<= peep2_current_count
);
2979 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2980 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2982 return peep2_insn_data
[n
].insn
;
2985 /* Return true if REGNO is dead before the Nth non-note insn
2989 peep2_regno_dead_p (int ofs
, int regno
)
2991 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
2993 ofs
+= peep2_current
;
2994 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2995 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2997 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
2999 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3002 /* Similarly for a REG. */
3005 peep2_reg_dead_p (int ofs
, rtx reg
)
3009 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3011 ofs
+= peep2_current
;
3012 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
3013 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
3015 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3017 regno
= REGNO (reg
);
3018 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3020 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3025 /* Try to find a hard register of mode MODE, matching the register class in
3026 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3027 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3028 in which case the only condition is that the register must be available
3029 before CURRENT_INSN.
3030 Registers that already have bits set in REG_SET will not be considered.
3032 If an appropriate register is available, it will be returned and the
3033 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3037 peep2_find_free_register (int from
, int to
, const char *class_str
,
3038 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
3040 static int search_ofs
;
3045 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3046 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3048 from
+= peep2_current
;
3049 if (from
>= MAX_INSNS_PER_PEEP2
+ 1)
3050 from
-= MAX_INSNS_PER_PEEP2
+ 1;
3051 to
+= peep2_current
;
3052 if (to
>= MAX_INSNS_PER_PEEP2
+ 1)
3053 to
-= MAX_INSNS_PER_PEEP2
+ 1;
3055 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3056 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3060 HARD_REG_SET this_live
;
3062 if (++from
>= MAX_INSNS_PER_PEEP2
+ 1)
3064 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3065 REG_SET_TO_HARD_REG_SET (this_live
, peep2_insn_data
[from
].live_before
);
3066 IOR_HARD_REG_SET (live
, this_live
);
3069 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
3070 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
3072 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3074 int raw_regno
, regno
, success
, j
;
3076 /* Distribute the free registers as much as possible. */
3077 raw_regno
= search_ofs
+ i
;
3078 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3079 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3080 #ifdef REG_ALLOC_ORDER
3081 regno
= reg_alloc_order
[raw_regno
];
3086 /* Don't allocate fixed registers. */
3087 if (fixed_regs
[regno
])
3089 /* Don't allocate global registers. */
3090 if (global_regs
[regno
])
3092 /* Make sure the register is of the right class. */
3093 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
))
3095 /* And can support the mode we need. */
3096 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3098 /* And that we don't create an extra save/restore. */
3099 if (! call_used_regs
[regno
] && ! df_regs_ever_live_p (regno
))
3101 if (! targetm
.hard_regno_scratch_ok (regno
))
3104 /* And we don't clobber traceback for noreturn functions. */
3105 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
3106 && (! reload_completed
|| frame_pointer_needed
))
3110 for (j
= hard_regno_nregs
[regno
][mode
] - 1; j
>= 0; j
--)
3112 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3113 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3121 add_to_hard_reg_set (reg_set
, mode
, regno
);
3123 /* Start the next search with the next register. */
3124 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3126 search_ofs
= raw_regno
;
3128 return gen_rtx_REG (mode
, regno
);
3136 /* Forget all currently tracked instructions, only remember current
3140 peep2_reinit_state (regset live
)
3144 /* Indicate that all slots except the last holds invalid data. */
3145 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3146 peep2_insn_data
[i
].insn
= NULL_RTX
;
3147 peep2_current_count
= 0;
3149 /* Indicate that the last slot contains live_after data. */
3150 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3151 peep2_current
= MAX_INSNS_PER_PEEP2
;
3153 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3156 /* Perform the peephole2 optimization pass. */
3159 peephole2_optimize (void)
3165 bool do_cleanup_cfg
= false;
3166 bool do_rebuild_jump_labels
= false;
3168 df_set_flags (DF_LR_RUN_DCE
);
3171 /* Initialize the regsets we're going to use. */
3172 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3173 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3174 live
= BITMAP_ALLOC (®_obstack
);
3176 FOR_EACH_BB_REVERSE (bb
)
3178 rtl_profile_for_bb (bb
);
3180 /* Start up propagation. */
3181 bitmap_copy (live
, DF_LR_OUT (bb
));
3182 df_simulate_initialize_backwards (bb
, live
);
3183 peep2_reinit_state (live
);
3185 for (insn
= BB_END (bb
); ; insn
= prev
)
3187 prev
= PREV_INSN (insn
);
3188 if (NONDEBUG_INSN_P (insn
))
3190 rtx attempt
, before_try
, x
;
3193 bool was_call
= false;
3195 /* Record this insn. */
3196 if (--peep2_current
< 0)
3197 peep2_current
= MAX_INSNS_PER_PEEP2
;
3198 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
3199 && peep2_insn_data
[peep2_current
].insn
== NULL_RTX
)
3200 peep2_current_count
++;
3201 peep2_insn_data
[peep2_current
].insn
= insn
;
3202 df_simulate_one_insn_backwards (bb
, insn
, live
);
3203 COPY_REG_SET (peep2_insn_data
[peep2_current
].live_before
, live
);
3205 if (RTX_FRAME_RELATED_P (insn
))
3207 /* If an insn has RTX_FRAME_RELATED_P set, peephole
3208 substitution would lose the
3209 REG_FRAME_RELATED_EXPR that is attached. */
3210 peep2_reinit_state (live
);
3214 /* Match the peephole. */
3215 attempt
= peephole2_insns (PATTERN (insn
), insn
, &match_len
);
3217 if (attempt
!= NULL
)
3219 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3220 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3221 cfg-related call notes. */
3222 for (i
= 0; i
<= match_len
; ++i
)
3225 rtx old_insn
, new_insn
, note
;
3227 j
= i
+ peep2_current
;
3228 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3229 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3230 old_insn
= peep2_insn_data
[j
].insn
;
3231 if (!CALL_P (old_insn
))
3236 while (new_insn
!= NULL_RTX
)
3238 if (CALL_P (new_insn
))
3240 new_insn
= NEXT_INSN (new_insn
);
3243 gcc_assert (new_insn
!= NULL_RTX
);
3245 CALL_INSN_FUNCTION_USAGE (new_insn
)
3246 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3248 for (note
= REG_NOTES (old_insn
);
3250 note
= XEXP (note
, 1))
3251 switch (REG_NOTE_KIND (note
))
3255 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3259 /* Discard all other reg notes. */
3263 /* Croak if there is another call in the sequence. */
3264 while (++i
<= match_len
)
3266 j
= i
+ peep2_current
;
3267 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3268 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3269 old_insn
= peep2_insn_data
[j
].insn
;
3270 gcc_assert (!CALL_P (old_insn
));
3275 i
= match_len
+ peep2_current
;
3276 if (i
>= MAX_INSNS_PER_PEEP2
+ 1)
3277 i
-= MAX_INSNS_PER_PEEP2
+ 1;
3279 note
= find_reg_note (peep2_insn_data
[i
].insn
,
3280 REG_EH_REGION
, NULL_RTX
);
3282 /* Replace the old sequence with the new. */
3283 attempt
= emit_insn_after_setloc (attempt
,
3284 peep2_insn_data
[i
].insn
,
3285 INSN_LOCATOR (peep2_insn_data
[i
].insn
));
3286 before_try
= PREV_INSN (insn
);
3287 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3289 /* Re-insert the EH_REGION notes. */
3290 if (note
|| (was_call
&& nonlocal_goto_handler_labels
))
3295 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3296 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3300 copy_reg_eh_region_note_backward (note
, attempt
,
3304 for (x
= attempt
; x
!= before_try
; x
= PREV_INSN (x
))
3305 if (x
!= BB_END (bb
)
3306 && (can_throw_internal (x
)
3307 || can_nonlocal_goto (x
)))
3312 nfte
= split_block (bb
, x
);
3313 flags
= (eh_edge
->flags
3314 & (EDGE_EH
| EDGE_ABNORMAL
));
3316 flags
|= EDGE_ABNORMAL_CALL
;
3317 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3320 nehe
->probability
= eh_edge
->probability
;
3322 = REG_BR_PROB_BASE
- nehe
->probability
;
3324 do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3329 /* Converting possibly trapping insn to non-trapping is
3330 possible. Zap dummy outgoing edges. */
3331 do_cleanup_cfg
|= purge_dead_edges (bb
);
3334 if (targetm
.have_conditional_execution ())
3336 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3337 peep2_insn_data
[i
].insn
= NULL_RTX
;
3338 peep2_insn_data
[peep2_current
].insn
= PEEP2_EOB
;
3339 peep2_current_count
= 0;
3343 /* Back up lifetime information past the end of the
3344 newly created sequence. */
3345 if (++i
>= MAX_INSNS_PER_PEEP2
+ 1)
3347 bitmap_copy (live
, peep2_insn_data
[i
].live_before
);
3349 /* Update life information for the new sequence. */
3356 i
= MAX_INSNS_PER_PEEP2
;
3357 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
3358 && peep2_insn_data
[i
].insn
== NULL_RTX
)
3359 peep2_current_count
++;
3360 peep2_insn_data
[i
].insn
= x
;
3362 df_simulate_one_insn_backwards (bb
, x
, live
);
3363 bitmap_copy (peep2_insn_data
[i
].live_before
,
3373 /* If we generated a jump instruction, it won't have
3374 JUMP_LABEL set. Recompute after we're done. */
3375 for (x
= attempt
; x
!= before_try
; x
= PREV_INSN (x
))
3378 do_rebuild_jump_labels
= true;
3384 if (insn
== BB_HEAD (bb
))
3389 default_rtl_profile ();
3390 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3391 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3393 if (do_rebuild_jump_labels
)
3394 rebuild_jump_labels (get_insns ());
3396 #endif /* HAVE_peephole2 */
3398 /* Common predicates for use with define_bypass. */
3400 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3401 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3402 must be either a single_set or a PARALLEL with SETs inside. */
3405 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3407 rtx out_set
, in_set
;
3408 rtx out_pat
, in_pat
;
3409 rtx out_exp
, in_exp
;
3412 in_set
= single_set (in_insn
);
3415 if (!MEM_P (SET_DEST (in_set
)))
3418 out_set
= single_set (out_insn
);
3421 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3426 out_pat
= PATTERN (out_insn
);
3428 if (GET_CODE (out_pat
) != PARALLEL
)
3431 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3433 out_exp
= XVECEXP (out_pat
, 0, i
);
3435 if (GET_CODE (out_exp
) == CLOBBER
)
3438 gcc_assert (GET_CODE (out_exp
) == SET
);
3440 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3447 in_pat
= PATTERN (in_insn
);
3448 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3450 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3452 in_exp
= XVECEXP (in_pat
, 0, i
);
3454 if (GET_CODE (in_exp
) == CLOBBER
)
3457 gcc_assert (GET_CODE (in_exp
) == SET
);
3459 if (!MEM_P (SET_DEST (in_exp
)))
3462 out_set
= single_set (out_insn
);
3465 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3470 out_pat
= PATTERN (out_insn
);
3471 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3473 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3475 out_exp
= XVECEXP (out_pat
, 0, j
);
3477 if (GET_CODE (out_exp
) == CLOBBER
)
3480 gcc_assert (GET_CODE (out_exp
) == SET
);
3482 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3492 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3493 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3494 or multiple set; IN_INSN should be single_set for truth, but for convenience
3495 of insn categorization may be any JUMP or CALL insn. */
3498 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3500 rtx out_set
, in_set
;
3502 in_set
= single_set (in_insn
);
3505 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3509 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3511 in_set
= SET_SRC (in_set
);
3513 out_set
= single_set (out_insn
);
3516 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3517 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3525 out_pat
= PATTERN (out_insn
);
3526 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3528 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3530 rtx exp
= XVECEXP (out_pat
, 0, i
);
3532 if (GET_CODE (exp
) == CLOBBER
)
3535 gcc_assert (GET_CODE (exp
) == SET
);
3537 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3538 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3547 gate_handle_peephole2 (void)
3549 return (optimize
> 0 && flag_peephole2
);
3553 rest_of_handle_peephole2 (void)
3555 #ifdef HAVE_peephole2
3556 peephole2_optimize ();
3561 struct rtl_opt_pass pass_peephole2
=
3565 "peephole2", /* name */
3566 gate_handle_peephole2
, /* gate */
3567 rest_of_handle_peephole2
, /* execute */
3570 0, /* static_pass_number */
3571 TV_PEEPHOLE2
, /* tv_id */
3572 0, /* properties_required */
3573 0, /* properties_provided */
3574 0, /* properties_destroyed */
3575 0, /* todo_flags_start */
3576 TODO_df_finish
| TODO_verify_rtl_sharing
|
3577 TODO_dump_func
/* todo_flags_finish */
3582 rest_of_handle_split_all_insns (void)
3588 struct rtl_opt_pass pass_split_all_insns
=
3592 "split1", /* name */
3594 rest_of_handle_split_all_insns
, /* execute */
3597 0, /* static_pass_number */
3598 TV_NONE
, /* tv_id */
3599 0, /* properties_required */
3600 0, /* properties_provided */
3601 0, /* properties_destroyed */
3602 0, /* todo_flags_start */
3603 TODO_dump_func
/* todo_flags_finish */
3608 rest_of_handle_split_after_reload (void)
3610 /* If optimizing, then go ahead and split insns now. */
3618 struct rtl_opt_pass pass_split_after_reload
=
3622 "split2", /* name */
3624 rest_of_handle_split_after_reload
, /* execute */
3627 0, /* static_pass_number */
3628 TV_NONE
, /* tv_id */
3629 0, /* properties_required */
3630 0, /* properties_provided */
3631 0, /* properties_destroyed */
3632 0, /* todo_flags_start */
3633 TODO_dump_func
/* todo_flags_finish */
3638 gate_handle_split_before_regstack (void)
3640 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3641 /* If flow2 creates new instructions which need splitting
3642 and scheduling after reload is not done, they might not be
3643 split until final which doesn't allow splitting
3644 if HAVE_ATTR_length. */
3645 # ifdef INSN_SCHEDULING
3646 return (optimize
&& !flag_schedule_insns_after_reload
);
3656 rest_of_handle_split_before_regstack (void)
3662 struct rtl_opt_pass pass_split_before_regstack
=
3666 "split3", /* name */
3667 gate_handle_split_before_regstack
, /* gate */
3668 rest_of_handle_split_before_regstack
, /* execute */
3671 0, /* static_pass_number */
3672 TV_NONE
, /* tv_id */
3673 0, /* properties_required */
3674 0, /* properties_provided */
3675 0, /* properties_destroyed */
3676 0, /* todo_flags_start */
3677 TODO_dump_func
/* todo_flags_finish */
3682 gate_handle_split_before_sched2 (void)
3684 #ifdef INSN_SCHEDULING
3685 return optimize
> 0 && flag_schedule_insns_after_reload
;
3692 rest_of_handle_split_before_sched2 (void)
3694 #ifdef INSN_SCHEDULING
3700 struct rtl_opt_pass pass_split_before_sched2
=
3704 "split4", /* name */
3705 gate_handle_split_before_sched2
, /* gate */
3706 rest_of_handle_split_before_sched2
, /* execute */
3709 0, /* static_pass_number */
3710 TV_NONE
, /* tv_id */
3711 0, /* properties_required */
3712 0, /* properties_provided */
3713 0, /* properties_destroyed */
3714 0, /* todo_flags_start */
3716 TODO_dump_func
/* todo_flags_finish */
3720 /* The placement of the splitting that we do for shorten_branches
3721 depends on whether regstack is used by the target or not. */
3723 gate_do_final_split (void)
3725 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS)
3732 struct rtl_opt_pass pass_split_for_shorten_branches
=
3736 "split5", /* name */
3737 gate_do_final_split
, /* gate */
3738 split_all_insns_noflow
, /* execute */
3741 0, /* static_pass_number */
3742 TV_NONE
, /* tv_id */
3743 0, /* properties_required */
3744 0, /* properties_provided */
3745 0, /* properties_destroyed */
3746 0, /* todo_flags_start */
3747 TODO_dump_func
| TODO_verify_rtl_sharing
/* todo_flags_finish */