1 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
2 Indu Bhagat <indu.bhagat@oracle.com>
5 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
6 in the correct order of the dimensions.
7 (gen_ctf_subrange_type): Refactor out handling of
8 DW_TAG_subrange_type DIE to here.
10 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
13 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
15 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
17 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
19 * config/aarch64/aarch64-sme.md
20 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
21 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
22 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
23 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
24 (early_ra::maybe_convert_to_strided_access): Remove support for
25 strided LUTI2 and LUTI4.
27 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
30 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
33 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
35 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
36 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
39 2024-03-05 Xi Ruoyao <xry111@xry111.site>
41 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
42 s9 as an alias of r22.
44 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
46 * config/avr/avr-protos.h (avr_out_insv): New proto.
47 * config/avr/avr.cc (avr_out_insv): New function.
48 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
49 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
50 * config/avr/avr.md (define_attr "adjust_len") Add insv.
51 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
52 Add constraint alternative where the 3rd operand is a power
53 of 2, and the source register may differ from the destination.
54 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
55 instructions. Set attr "length" to "insv".
56 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
58 2024-03-05 Richard Biener <rguenther@suse.de>
60 PR tree-optimization/114231
61 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
62 processing a BB SLP root.
64 2024-03-05 Jakub Jelinek <jakub@redhat.com>
66 PR rtl-optimization/114211
67 * lower-subreg.cc (resolve_simple_move): For double-word
68 rotates by BITS_PER_WORD if there is overlap between source
69 and destination use a temporary.
71 2024-03-05 Jakub Jelinek <jakub@redhat.com>
74 * gimple-lower-bitint.cc: Include stor-layout.h.
75 (mergeable_op): Return true for BIT_FIELD_REF.
76 (struct bitint_large_huge): Declare handle_bit_field_ref method.
77 (bitint_large_huge::handle_bit_field_ref): New method.
78 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
80 2024-03-05 Jakub Jelinek <jakub@redhat.com>
83 * config/i386/i386.h (enum call_saved_registers_type): Add
84 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
85 * config/i386/i386-options.cc (ix86_set_func_type): Remove
86 has_no_callee_saved_registers variable, add no_callee_saved_registers
87 instead, initialize it depending on whether it is
88 no_callee_saved_registers function or not. Don't set it if
89 no_caller_saved_registers attribute is present. Adjust users.
90 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
91 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
92 TYPE_NO_CALLEE_SAVED_REGISTERS.
93 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
95 2024-03-05 Pan Li <pan2.li@intel.com>
97 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
98 mode_size related code.
100 2024-03-05 Patrick Palka <ppalka@redhat.com>
102 * doc/invoke.texi (-Wno-global-module): Document.
104 2024-03-04 David Faust <david.faust@oracle.com>
106 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
107 * config/bpf/bpf.cc (bpf_expand_setmem): New.
108 * config/bpf/bpf.md (setmemdi): New define_expand.
110 2024-03-04 Jakub Jelinek <jakub@redhat.com>
112 PR rtl-optimization/113010
113 * combine.cc (simplify_comparison): Guard the
114 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
115 and initialize inner_mode.
117 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
119 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
121 (VMLALDAVXQ): Remove iterator.
122 (VMLALDAVXQ_P): Likewise.
123 (VMLALDAVAXQ): Likewise.
124 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
125 mode iterator attribute with V4BI mode.
126 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
127 VMLALDAVAXQ_U): Remove unused unspecs.
129 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
131 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
132 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
134 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
135 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
136 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
137 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
138 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
139 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
140 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
141 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
142 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
143 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
145 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
147 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
148 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
149 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
150 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
151 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
152 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
153 (arm_vcx1q<a>v16qi): Likewise.
154 (arm_vcx1qav16qi): Likewise.
155 (arm_vcx1qv16qi): Likewise.
156 (arm_vcx2q<a>_p_v16qi): Likewise.
157 (arm_vcx2q<a>v16qi): Likewise.
158 (arm_vcx2qav16qi): Likewise.
159 (arm_vcx2qv16qi): Likewise.
160 (arm_vcx3q<a>_p_v16qi): Likewise.
161 (arm_vcx3q<a>v16qi): Likewise.
162 (arm_vcx3qav16qi): Likewise.
163 (arm_vcx3qv16qi): Likewise.
164 (@mve_<mve_insn>q_<supf><mode>): Likewise.
165 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
166 (@mve_<mve_insn>q_<supf>v4si): Likewise.
167 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
168 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
169 (@mve_<mve_insn>q_f<mode>): Likewise.
170 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
171 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
172 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
173 (@mve_<mve_insn>q_m_f<mode>): Likewise.
174 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
175 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
176 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
177 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
178 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
179 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
180 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
181 (mve_v<absneg_str>q_f<mode>): Likewise.
182 (mve_<mve_addsubmul>q<mode>): Likewise.
183 (mve_<mve_addsubmul>q_f<mode>): Likewise.
184 (mve_vadciq_<supf>v4si): Likewise.
185 (mve_vadciq_m_<supf>v4si): Likewise.
186 (mve_vadcq_<supf>v4si): Likewise.
187 (mve_vadcq_m_<supf>v4si): Likewise.
188 (mve_vandq_<supf><mode>): Likewise.
189 (mve_vandq_f<mode>): Likewise.
190 (mve_vandq_m_<supf><mode>): Likewise.
191 (mve_vandq_m_f<mode>): Likewise.
192 (mve_vandq_s<mode>): Likewise.
193 (mve_vandq_u<mode>): Likewise.
194 (mve_vbicq_<supf><mode>): Likewise.
195 (mve_vbicq_f<mode>): Likewise.
196 (mve_vbicq_m_<supf><mode>): Likewise.
197 (mve_vbicq_m_f<mode>): Likewise.
198 (mve_vbicq_m_n_<supf><mode>): Likewise.
199 (mve_vbicq_n_<supf><mode>): Likewise.
200 (mve_vbicq_s<mode>): Likewise.
201 (mve_vbicq_u<mode>): Likewise.
202 (@mve_vclzq_s<mode>): Likewise.
203 (mve_vclzq_u<mode>): Likewise.
204 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
205 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
206 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
207 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
208 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
209 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
210 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
211 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
212 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
213 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
214 (mve_vcvtaq_<supf><mode>): Likewise.
215 (mve_vcvtaq_m_<supf><mode>): Likewise.
216 (mve_vcvtbq_f16_f32v8hf): Likewise.
217 (mve_vcvtbq_f32_f16v4sf): Likewise.
218 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
219 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
220 (mve_vcvtmq_<supf><mode>): Likewise.
221 (mve_vcvtmq_m_<supf><mode>): Likewise.
222 (mve_vcvtnq_<supf><mode>): Likewise.
223 (mve_vcvtnq_m_<supf><mode>): Likewise.
224 (mve_vcvtpq_<supf><mode>): Likewise.
225 (mve_vcvtpq_m_<supf><mode>): Likewise.
226 (mve_vcvtq_from_f_<supf><mode>): Likewise.
227 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
228 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
229 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
230 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
231 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
232 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
233 (mve_vcvtq_to_f_<supf><mode>): Likewise.
234 (mve_vcvttq_f16_f32v8hf): Likewise.
235 (mve_vcvttq_f32_f16v4sf): Likewise.
236 (mve_vcvttq_m_f16_f32v8hf): Likewise.
237 (mve_vcvttq_m_f32_f16v4sf): Likewise.
238 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
239 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
240 (mve_veorq_s><mode>): Likewise.
241 (mve_veorq_u><mode>): Likewise.
242 (mve_veorq_f<mode>): Likewise.
243 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
244 (mve_vidupq_u<mode>_insn): Likewise.
245 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
246 (mve_viwdupq_wb_u<mode>_insn): Likewise.
247 (mve_vldrbq_<supf><mode>): Likewise.
248 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
249 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
250 (mve_vldrbq_z_<supf><mode>): Likewise.
251 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
252 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
253 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
254 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
255 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
256 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
257 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
258 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
259 (mve_vldrhq_<supf><mode>): Likewise.
260 (mve_vldrhq_fv8hf): Likewise.
261 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
262 (mve_vldrhq_gather_offset_fv8hf): Likewise.
263 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
264 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
265 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
266 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
267 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
268 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
269 (mve_vldrhq_z_<supf><mode>): Likewise.
270 (mve_vldrhq_z_fv8hf): Likewise.
271 (mve_vldrwq_<supf>v4si): Likewise.
272 (mve_vldrwq_fv4sf): Likewise.
273 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
274 (mve_vldrwq_gather_base_fv4sf): Likewise.
275 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
276 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
277 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
278 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
279 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
280 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
281 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
282 (mve_vldrwq_gather_offset_fv4sf): Likewise.
283 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
284 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
285 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
286 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
287 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
288 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
289 (mve_vldrwq_z_<supf>v4si): Likewise.
290 (mve_vldrwq_z_fv4sf): Likewise.
291 (mve_vmvnq_s<mode>): Likewise.
292 (mve_vmvnq_u<mode>): Likewise.
293 (mve_vornq_<supf><mode>): Likewise.
294 (mve_vornq_f<mode>): Likewise.
295 (mve_vornq_m_<supf><mode>): Likewise.
296 (mve_vornq_m_f<mode>): Likewise.
297 (mve_vornq_s<mode>): Likewise.
298 (mve_vornq_u<mode>): Likewise.
299 (mve_vorrq_<supf><mode>): Likewise.
300 (mve_vorrq_f<mode>): Likewise.
301 (mve_vorrq_m_<supf><mode>): Likewise.
302 (mve_vorrq_m_f<mode>): Likewise.
303 (mve_vorrq_m_n_<supf><mode>): Likewise.
304 (mve_vorrq_n_<supf><mode>): Likewise.
305 (mve_vorrq_s<mode>): Likewise.
306 (mve_vorrq_s<mode>): Likewise.
307 (mve_vsbciq_<supf>v4si): Likewise.
308 (mve_vsbciq_m_<supf>v4si): Likewise.
309 (mve_vsbcq_<supf>v4si): Likewise.
310 (mve_vsbcq_m_<supf>v4si): Likewise.
311 (mve_vshlcq_<supf><mode>): Likewise.
312 (mve_vshlcq_m_<supf><mode>): Likewise.
313 (mve_vshrq_m_n_<supf><mode>): Likewise.
314 (mve_vshrq_n_<supf><mode>): Likewise.
315 (mve_vstrbq_<supf><mode>): Likewise.
316 (mve_vstrbq_p_<supf><mode>): Likewise.
317 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
318 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
319 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
320 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
321 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
322 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
323 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
324 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
325 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
326 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
327 (mve_vstrhq_<supf><mode>): Likewise.
328 (mve_vstrhq_fv8hf): Likewise.
329 (mve_vstrhq_p_<supf><mode>): Likewise.
330 (mve_vstrhq_p_fv8hf): Likewise.
331 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
332 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
333 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
334 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
335 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
336 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
337 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
338 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
339 (mve_vstrwq_<supf>v4si): Likewise.
340 (mve_vstrwq_fv4sf): Likewise.
341 (mve_vstrwq_p_<supf>v4si): Likewise.
342 (mve_vstrwq_p_fv4sf): Likewise.
343 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
344 (mve_vstrwq_scatter_base_fv4sf): Likewise.
345 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
346 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
347 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
348 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
349 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
350 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
351 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
352 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
353 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
354 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
355 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
356 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
357 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
358 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
360 2024-03-04 Marek Polacek <polacek@redhat.com>
362 * doc/extend.texi: Update [[gnu::no_dangling]].
364 2024-03-04 Andrew Stubbs <ams@baylibre.com>
366 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
367 * expr.cc (store_constructor): Likewise.
368 (do_store_flag): Likewise.
370 2024-03-04 Mark Wielaard <mark@klomp.org>
372 * common.opt.urls: Regenerate.
373 * config/avr/avr.opt.urls: Likewise.
374 * config/i386/i386.opt.urls: Likewise.
375 * config/pru/pru.opt.urls: Likewise.
376 * config/riscv/riscv.opt.urls: Likewise.
377 * config/rs6000/rs6000.opt.urls: Likewise.
379 2024-03-04 Richard Biener <rguenther@suse.de>
381 PR tree-optimization/114197
382 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
383 there are volatile bitfield accesses.
384 (pass_if_conversion::execute): Throw away result if the
385 if-converted and original loops are not nested as expected.
387 2024-03-04 Richard Biener <rguenther@suse.de>
389 PR tree-optimization/114164
390 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
391 the code generated for mask argument setup is not supported.
393 2024-03-04 Richard Biener <rguenther@suse.de>
395 PR tree-optimization/114203
396 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
397 adjustment before making the result defined at zero.
399 2024-03-04 Richard Biener <rguenther@suse.de>
401 PR tree-optimization/114192
402 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
403 appropriate def for the live out stmt in case of an alternate
406 2024-03-04 Jakub Jelinek <jakub@redhat.com>
409 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
410 unshare_expr when creating a MEM_REF from MEM_REF.
411 (bitint_large_huge::lower_stmt): Call unshare_expr.
413 2024-03-04 Jakub Jelinek <jakub@redhat.com>
416 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
417 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
420 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
423 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
424 lowpart_subreg to perform type conversion, to avoid confusion
425 over the offset to use in the call to simplify_reg_subreg.
427 2024-03-03 Greg McGary <gkm@rivosinc.com>
429 PR rtl-optimization/113010
430 * combine.cc (simplify_comparison): Simplify a SUBREG on
431 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
434 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
436 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
437 Use bool in place of int for boolean logic (if possible).
438 Move declarations to definitions (if possible).
439 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
440 * config/avr/avr-dimode.md: Same.
441 * config/avr/constraints.md: Same.
442 * config/avr/predicates.md: Same.
444 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
447 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
448 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
449 simplify insn RTX using UMUL_HIGHPART rtx_code.
450 (*umuldi3_highpart_const): Remove.
452 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
455 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
456 * config/avr/avr.cc (_reg_unused_after): Make static. And
457 add 3rd argument to skip the current insn.
458 (reg_unused_after): Adjust call of reg_unused_after.
459 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
460 unneeded frame pointer adjustments.
462 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
465 * config/avr/avr.md (define_attr "cc"): Remove.
466 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
468 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
469 its uses. Add insn argument.
470 (avr_out_plus_symbol): Remove pcc argument and its uses.
471 (avr_out_plus): Remove pcc argument and its uses.
472 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
473 (avr_out_round): Adjust call of avr_out_plus.
475 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
477 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
480 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
483 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
484 is not an insn, but e.g. a code label.
486 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
488 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
489 * config/avr/avr.cc: Use them instead of magic numbers when it
490 means a register number.
492 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
494 * config/avr/avr.cc: Adjust some comments.
496 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
499 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
500 the low part of the frame pointer with 8-bit stack pointer.
502 2024-03-01 Patrick Palka <ppalka@redhat.com>
506 * tree-inline.cc (remap_decl): Handle copy_decl returning the
508 (remap_decls): Handle remap_decl returning the original decl.
509 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
512 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
514 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
516 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
517 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
518 (movhi_internal, movqi_internal): Likewise.
519 (movsf_softfloat, movsf_hardfloat): Likewise.
520 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
521 (movdf_softfloat): Likewise.
523 2024-03-01 Marek Polacek <polacek@redhat.com>
527 * doc/extend.texi: Document gnu::no_dangling.
528 * doc/invoke.texi: Mention that gnu::no_dangling disables
529 -Wdangling-reference.
531 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
533 * config/avr/avr.opt: Overhaul help screen.
535 2024-03-01 Jakub Jelinek <jakub@redhat.com>
536 Tobias Burnus <tburnus@baylibre.com>
539 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
540 lang_hooks.decls.omp_disregard_value_expr for
541 (first)private in target regions.
543 2024-03-01 Jakub Jelinek <jakub@redhat.com>
546 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
547 n_named_args initially before INIT_CUMULATIVE_ARGS to
548 structure_value_addr_parm rather than 0, after it don't modify
549 it if strict_argument_naming and clear only if
550 !pretend_outgoing_varargs_named.
552 2024-03-01 Jakub Jelinek <jakub@redhat.com>
555 * dwarf2out.cc (should_move_die_to_comdat): Return false for
556 aggregates without DW_AT_byte_size attribute or with non-constant
559 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
561 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
562 valid values for level.
564 2024-03-01 Richard Biener <rguenther@suse.de>
567 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
568 Allow the folding if before lowering and the current IL
569 isn't supported with vcond_mask.
571 2024-03-01 xuli <xuli1@eswincomputing.com>
573 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
574 attribute to riscv_attribute_table.
575 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
576 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
577 * doc/extend.texi: Add riscv_vector_cc attribute description.
579 2024-03-01 Pan Li <pan2.li@intel.com>
582 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
583 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
584 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
585 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
586 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
587 comments for option replacement.
588 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
589 riscv_autovec_preference to rvv_vector_bits.
590 (vls_mode_valid_p): Ditto.
591 (estimated_poly_value): Ditto.
592 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
593 vector chunks and honor new option mrvv-vector-bits.
594 (riscv_override_options_internal): Update comments and rename the
596 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
597 internal option param=riscv-autovec-preference.
599 2024-03-01 Jakub Jelinek <jakub@redhat.com>
601 * function.cc (assign_parms): Only call assign_parms_setup_varargs
602 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
604 2024-03-01 Jakub Jelinek <jakub@redhat.com>
607 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
608 rhs1 of a VCE to have no underlying variable if it is a load and
611 2024-02-29 David Malcolm <dmalcolm@redhat.com>
614 * function.cc (function_name): Make param const.
615 * function.h (function_name): Likewise.
617 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
620 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
621 * config/avr/avr.opt (-mfuse-add=): New target option.
622 * common/config/avr/avr-common.cc (avr_option_optimization_table)
623 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
624 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
625 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
626 * config/avr/avr-protos.h (avr_split_tiny_move)
627 (make_avr_pass_fuse_add): New protos.
628 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
629 avr_split_tiny_move to split indirect memory accesses.
630 (gen_move_clobbercc): New define_expand helper.
631 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
632 (avr_pass_fuse_add): New class from rtl_opt_pass.
633 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
634 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
635 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
636 of PLUS addressing for AVR_TINY.
637 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
638 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
639 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
641 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
644 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
645 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
646 (avr_function_arg): Set it.
647 (avr_frame_pointer_required_p): Use it instead of .nregs.
649 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
652 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
653 static and mark with GTY.
655 2024-02-29 Xi Ruoyao <xry111@xry111.site>
657 * config/loongarch/loongarch.md
658 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
660 2024-02-29 Xi Ruoyao <xry111@xry111.site>
662 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
663 (crc): New define_int_attr.
664 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
666 (loongarch_<crc>_w_<size>_w): ... here.
668 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
671 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
672 extend the expected value if needed.
674 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
676 * config.gcc (target_gtfiles): Change coreout to btfext-out.
677 (extra_objs): Change coreout to btfext-out.
678 * config/bpf/coreout.cc: Rename to btfext-out.cc.
679 * config/bpf/btfext-out.cc: Add.
680 * config/bpf/coreout.h: Rename to btfext-out.h.
681 * config/bpf/btfext-out.h: Add.
682 * config/bpf/core-builtins.cc: Change include.
683 * config/bpf/core-builtins.h: Change include.
684 * config/bpf/t-bpf: Accomodate renamed files.
686 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
689 * config/bpf/bpf.cc (bpf_function_prologue): Define target
691 * config/bpf/coreout.cc (brf_ext_info_section)
692 (btf_ext_info): Move from coreout.h
693 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
694 (bpf_core_reloc): Rename to btf_ext_core_reloc.
695 (btf_ext): Add static variable.
696 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
697 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
698 (btf_ext_add_string, btf_funcinfo_type_callback)
699 (btf_add_func_info_for, btf_validate_funcinfo)
700 (btf_ext_info_len, output_btfext_func_info): Add function.
701 (output_btfext_header, bpf_core_reloc_add)
702 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
703 Change to support new structs.
704 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
705 Move and change in coreout.cc.
706 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
708 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
710 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
711 enabled by default for BPF.
712 (bpf_file_end): Call BTF deallocation.
713 (bpf_asm_init_sections): Correct condition.
714 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
716 (ctf_debuf_finish): Correct condition for calling
719 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
721 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
722 (traverse_btf_func_types): Define function.
723 * ctfc.h (funcs_traverse_callback): Typedef for function
725 (traverse_btf_func_types): Add prototype.
727 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
729 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
731 2024-02-28 Richard Biener <rguenther@suse.de>
733 PR tree-optimization/113831
734 PR tree-optimization/108355
735 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
738 2024-02-28 Richard Biener <rguenther@suse.de>
740 PR tree-optimization/114121
741 * tree-ssa-sccvn.h (vn_reference_s::offset,
742 vn_reference_s::max_size): New fields.
743 (vn_reference_insert_pieces): Adjust prototype.
744 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
745 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
746 size, allow using "don't know" state.
747 (vn_walk_cb_data::finish): Pass along offset/max_size.
748 (vn_reference_lookup_or_insert_for_pieces): Take offset and
749 max_size as argument and use it.
750 (vn_reference_lookup_3): Properly adjust offset and max_size
751 according to the adjusted ao_ref.
752 (vn_reference_lookup_pieces): Initialize offset and max_size.
753 (vn_reference_lookup): Likewise.
754 (vn_reference_lookup_call): Likewise.
755 (vn_reference_insert): Likewise.
756 (visit_reference_op_call): Likewise.
757 (vn_reference_insert_pieces): Take offset and max_size
758 as argument and use it.
760 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
762 PR tree-optimization/114075
763 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
766 2024-02-28 Jakub Jelinek <jakub@redhat.com>
768 PR tree-optimization/114041
769 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
770 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
772 2024-02-28 Jakub Jelinek <jakub@redhat.com>
774 PR tree-optimization/113988
775 * stor-layout.h (bitwise_mode_for_size): Declare.
776 * stor-layout.cc (bitwise_mode_for_size): New function.
777 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
778 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
779 Use BITS_PER_UNIT instead of 8.
781 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
784 * config/i386/mmx.md (V248FI): Add V2BF mode.
787 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
789 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
790 if either ref->offset is not byte aligned or ref->size is not known
791 to be equal to ref->max_size.
792 (maybe_trim_complex_store): Fix description.
793 (maybe_trim_constructor_store): Likewise.
794 (maybe_trim_partially_dead_store): Likewise.
796 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
798 * config/arm/mmintrin.h: Warn if this header is included without
799 defining __ENABLE_DEPRECATED_IWMMXT.
801 2024-02-27 Richard Biener <rguenther@suse.de>
803 PR tree-optimization/114074
804 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
805 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
806 Handle poly vs. non-poly multiplication correctly with respect
807 to undefined behavior on overflow.
809 2024-02-27 Jakub Jelinek <jakub@redhat.com>
811 PR rtl-optimization/114044
812 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
813 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
814 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
815 expand_PARITY): Declare.
816 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
817 expand_CTZ, expand_FFS, expand_PARITY): New functions.
818 (expand_POPCOUNT): Use expand_bitquery.
820 2024-02-27 Richard Biener <rguenther@suse.de>
822 PR tree-optimization/114081
823 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
824 Perform manual dominator update for prologue peeling.
825 (vect_do_peeling): Properly update dominators after adding the
826 prologue-around guard.
828 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
830 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
831 (mstrict-X): Tag as "Optimization".
833 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
835 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
836 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
838 2024-02-26 Jakub Jelinek <jakub@redhat.com>
839 H.J. Lu <hjl.tools@gmail.com>
841 PR rtl-optimization/113617
842 * varasm.cc (default_elf_select_rtx_section): For
843 references to private symbols in comdat sections
844 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
845 or .rodata.<comdat> comdat sections.
847 2024-02-26 Richard Biener <rguenther@suse.de>
849 PR tree-optimization/114099
850 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
851 Create and fill in a needed virtual LC PHI for the alternate
852 exits. Remove code dealing with that missing.
854 2024-02-26 Richard Biener <rguenther@suse.de>
856 PR tree-optimization/114068
857 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
859 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
860 on the main exit if needed. Remove band-aid for the case
863 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
866 * config/i386/i386-options.cc (ix86_set_func_type): Check
867 interrupt instead of noreturn attribute.
869 2024-02-26 Jakub Jelinek <jakub@redhat.com>
871 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
874 2024-02-26 Jakub Jelinek <jakub@redhat.com>
876 PR tree-optimization/114090
877 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
878 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
880 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
882 2024-02-26 Jakub Jelinek <jakub@redhat.com>
885 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
886 if all subtrees of var0 come from one of the op0 or op1 operands
887 and all subtrees of con0 come from the other one. Don't clear
888 variables which are never used afterwards.
890 2024-02-26 Richard Biener <rguenther@suse.de>
893 * genmatch.cc (parser::parse_c_expr): Do not record operand
894 lists but only mark operators used.
895 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
896 Properly guard the case of tcc_comparison changing the VEC_COND
899 2024-02-26 Jakub Jelinek <jakub@redhat.com>
902 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
903 to printed instruction.
905 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
908 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
909 __builtin_ia32_ldtilecfg.
910 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
911 * config/i386/i386-builtin.def (BDESC): Add
912 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
913 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
914 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
915 * config/i386/i386.md (ldtilecfg): New pattern.
916 (sttilecfg): Likewise.
918 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
920 PR tree-optimization/113205
921 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
922 the proposed layout if it does not allow a source partition with
923 layout 2 to keep that layout.
925 2024-02-24 Jakub Jelinek <jakub@redhat.com>
927 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
928 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
929 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
930 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
931 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
932 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
934 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
935 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
936 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
937 HOST_WIDE_INT_UC macros.
938 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
939 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
940 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
941 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
943 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
944 * config/i386/constraints.md (define_constraint "L"): Use
945 HOST_WIDE_INT_C macro.
946 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
948 (movl + movb peephole2): Likewise.
949 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
950 (const_32bit_mask): Likewise.
952 2024-02-24 Jakub Jelinek <jakub@redhat.com>
955 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
956 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
957 types like vector or complex types.
958 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
959 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
960 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
962 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
965 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
966 Return false if inner mode is already Pmode.
967 (rvv_builder::is_all_same_sequence): New function.
968 (expand_vec_init): Emit broadcast if sequence is all same.
970 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
973 * config/aarch64/aarch64-early-ra.cc
974 (early_ra::m_current_region): New member variable.
975 (early_ra::m_fpr_recency): Likewise.
976 (early_ra::start_new_region): Bump m_current_region.
977 (early_ra::allocate_colors): Prefer less recently used registers
978 in the event of a tie. Add a comment to explain why we prefer(ed)
979 higher-numbered registers.
980 (early_ra::find_oldest_color): Prefer less recently used registers
982 (early_ra::finalize_allocation): Update recency information for
984 (early_ra::process_blocks): Initialize m_current_region and
987 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
990 * config/aarch64/aarch64-early-ra.cc
991 (early_ra::test_strictness): New enum.
992 (early_ra::is_chain_candidate): Add a strictness parameter to
993 control whether only correctness matters, or whether both correctness
994 and heuristics should be used. Handle multiple levels of equivalence.
995 (early_ra::find_related_start): Update call accordingly.
996 (early_ra::strided_polarity_pref): Likewise.
997 (early_ra::form_chains): Likewise.
998 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
999 correctness mode rather than trying to inline the test.
1001 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1004 * config/aarch64/aarch64-early-ra.cc
1005 (early_ra::find_related_start): Account for definitions by shared
1006 registers when testing for a single register definition.
1007 (early_ra::accumulate_defs): New function.
1008 (early_ra::record_copy): If A shares B's register, fold A's
1009 definition information into B's. Fold A's use information into B's.
1011 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
1013 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
1014 if R_X86_64_CODE_6_GOTTPOFF is supported.
1015 * config.in: Regenerated.
1016 * configure: Likewise.
1017 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
1018 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
1020 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
1023 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
1024 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
1026 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1028 PR rtl-optimization/114054
1029 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
1030 temp variable instead of target parameter for result.
1032 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1034 PR tree-optimization/114040
1035 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
1036 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
1037 probability from likely to unlikely. When handling the true true
1038 store, first cast to limb_access_type and then to l's type.
1040 2024-02-23 Richard Biener <rguenther@suse.de>
1043 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
1045 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1048 * config/riscv/arch-canonicalize: Move to python3
1049 * config/riscv/multilib-generator: Likewise
1051 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1053 * doc/invoke.texi: Document -mcpu.
1055 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
1057 * configure: Regenerate.
1058 * configure.ac: Add parameter "--fatal-warnings" to assemble
1059 when checking whether the assemble support conditional branch
1062 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1065 * doc/extend.texi: (__extension__): Remove comments about scope
1066 tokens vs. two colons.
1068 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
1070 PR tree-optimization/109804
1071 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
1072 DEMANGLE_COMPONENT_UNNAMED_TYPE.
1074 2024-02-22 Richard Biener <rguenther@suse.de>
1076 PR tree-optimization/114048
1077 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
1078 can also produce -1 off.
1080 2024-02-22 Richard Biener <rguenther@suse.de>
1082 PR tree-optimization/114027
1083 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
1084 condition reduction classification only for single-element
1087 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1090 * profile-count.h (profile_count::dump): Remove overload with
1091 char * first argument.
1092 * profile-count.cc (profile_count::dump): Change overload with char *
1093 first argument which uses sprintf into the overfload with FILE *
1094 first argument and use fprintf instead. Remove overload which wrapped
1097 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1099 PR tree-optimization/113993
1100 * tree-call-cdce.cc (get_no_error_domain): Handle
1101 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
1102 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
1103 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1104 the as the F128 suffixed cases, otherwise as non-suffixed ones.
1105 Handle BUILT_IN_{EXP,POW}10L for
1106 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1109 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1111 PR tree-optimization/114038
1112 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
1113 loop exit condition if end is divisible by limb_prec.
1115 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
1117 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
1118 problem of mabi=, mno-flush-func, mexplicit-relocs;
1119 add missing leading - of mbranch-cost option.
1120 * config/mips/mips.opt.urls: Regenerate.
1122 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
1125 * config/rs6000/constraints.md (we): Update internal doc without
1126 referring to option -mpower9-vector.
1127 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
1129 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
1130 OTHER_P8_VECTOR_MASKS): Merge to ...
1131 (OTHER_VSX_VECTOR_MASKS): ... here.
1132 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
1133 some error message handlings and explicit option mask adjustments on
1134 explicit option power{8,9}-vector conflicting with other options.
1135 (rs6000_print_isa_options): Update comments.
1136 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
1137 related array items and handlings.
1138 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
1140 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
1142 * doc/extend.texi: Remove documentation referring to option
1144 * doc/invoke.texi: Remove documentation for option
1145 -mpower{8,9}-vector and adjust some documentation referring to them.
1146 * doc/md.texi: Update documentation for constraint we.
1147 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
1149 2024-02-22 Pan Li <pan2.li@intel.com>
1152 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
1153 the version to 0.12.
1155 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1157 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
1159 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1160 Robin Dapp <rdapp.gcc@gmail.com>
1162 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1163 (generic_ooo_vec_load): Ditto
1164 (generic_ooo_vec_store): Ditto
1165 (generic_ooo_vec_loadstore_seg): Ditto
1166 (generic_ooo_vec_alu): Ditto
1167 (generic_ooo_vec_fcmp): Ditto
1168 (generic_ooo_vec_imul): Ditto
1169 (generic_ooo_vec_fadd): Ditto
1170 (generic_ooo_vec_fmul): Ditto
1171 (generic_ooo_crypto): Ditto
1172 (generic_ooo_perm): Ditto
1173 (generic_ooo_vec_reduction): Ditto
1174 (generic_ooo_vec_ordered_reduction): Ditto
1175 (generic_ooo_vec_idiv): Ditto
1176 (generic_ooo_vec_float_divsqrt): Ditto
1177 (generic_ooo_vec_mask): Ditto
1178 (generic_ooo_vec_vesetvl): Ditto
1179 (generic_ooo_vec_setrm): Ditto
1180 (generic_ooo_vec_readlen): Ditto
1181 * config/riscv/riscv.md: Include generic-vector-ooo
1182 * config/riscv/generic-vector-ooo.md: New file. To here
1184 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1186 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1187 (generic_ooo_branch): Ditto
1188 * config/riscv/generic.md (generic_sfb_alu): Ditto
1189 (generic_fmul_half): Ditto
1190 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1191 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
1192 (sifive_7_popcount): Ditto
1193 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
1194 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
1195 * config/riscv/vector.md: Change rdfrm to fmove
1196 * config/riscv/zc.md: Change pushpop to load/store
1198 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
1200 * doc/invoke.texi (Warning Options): Fix typos.
1202 2024-02-21 David Faust <david.faust@oracle.com>
1204 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
1205 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
1206 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
1208 2024-02-21 Martin Jambor <mjambor@suse.cz>
1211 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
1212 initializers in the contructor.
1213 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
1214 * ipa-cp.h: New file.
1215 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
1216 (ipcp_value_source): Move to ipa-cp.h.
1217 (ipcp_value_base): Likewise.
1218 (ipcp_value): Likewise.
1219 (ipcp_lattice): Likewise.
1220 (ipcp_agg_lattice): Likewise.
1221 (ipcp_bits_lattice): Likewise.
1222 (ipcp_vr_lattice): Likewise.
1223 (ipcp_param_lattices): Likewise.
1224 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
1225 (ipa_value_from_jfunc): Adjust a check for empty lattices.
1226 (ipa_context_from_jfunc): Likewise.
1227 (ipa_agg_value_from_jfunc): Likewise.
1228 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
1229 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
1230 just in contiguous memory.
1231 (ipcp_store_vr_results): Adjust a check for empty lattices.
1232 * auto-profile.cc: Include sreal.h and ipa-cp.h.
1233 * cgraph.cc: Likewise.
1234 * cgraphclones.cc: Likewise.
1235 * cgraphunit.cc: Likewise.
1236 * config/aarch64/aarch64.cc: Likewise.
1237 * config/i386/i386-builtins.cc: Likewise.
1238 * config/i386/i386-expand.cc: Likewise.
1239 * config/i386/i386-features.cc: Likewise.
1240 * config/i386/i386-options.cc: Likewise.
1241 * config/i386/i386.cc: Likewise.
1242 * config/rs6000/rs6000.cc: Likewise.
1243 * config/s390/s390.cc: Likewise.
1244 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
1245 files to be included in gtype-desc.cc.
1246 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
1247 * ipa-devirt.cc: Likewise.
1248 * ipa-fnsummary.cc: Likewise.
1249 * ipa-icf.cc: Likewise.
1250 * ipa-inline-analysis.cc: Likewise.
1251 * ipa-inline-transform.cc: Likewise.
1252 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
1253 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
1254 * ipa-param-manipulation.cc: Likewise.
1255 * ipa-predicate.cc: Likewise.
1256 * ipa-profile.cc: Likewise.
1257 * ipa-prop.cc: Likewise.
1258 (ipa_node_params_t::duplicate): Assert new lattices remain empty
1259 instead of setting them to NULL.
1260 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
1261 * ipa-split.cc: Likewise.
1262 * ipa-sra.cc: Likewise.
1263 * ipa-strub.cc: Likewise.
1264 * ipa-utils.cc: Likewise.
1266 * toplev.cc: Likewise.
1267 * tree-ssa-ccp.cc: Likewise.
1268 * tree-ssa-sccvn.cc: Likewise.
1269 * tree-vrp.cc: Likewise.
1271 2024-02-21 Tamar Christina <tamar.christina@arm.com>
1273 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
1276 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1278 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1279 Use aarch64_gen_compare_zero_and_branch rather than emitting
1282 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1284 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
1285 Remove duplicated call.
1287 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1289 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
1290 Check that each individual piece of state is shared in the same
1291 way, rather than using an aggregate check for PSTATE.ZA.
1293 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1295 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1296 In the code that commits a lazy save, only zero ZA if the function
1297 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
1299 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1301 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
1302 directly inserting the associated sequence
1303 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1306 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1309 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
1310 fold the SVE allocation into the initial allocation if the
1311 initial allocation includes a VG save.
1313 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1316 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
1317 contain jumps even if called after initial RTL expansion.
1318 * mode-switching.cc: Include cfgbuild.h.
1319 (optimize_mode_switching): Allow the sequence returned by the
1320 emit hook to contain internal jumps. Record which blocks
1321 contain such jumps and split the blocks at the end.
1322 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
1323 non-debug insns when scanning the sequence.
1325 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
1327 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
1328 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
1330 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1332 * doc/invoke.texi (-mmcu): Add information about MCU specs.
1334 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1336 * doc/invoke.texi (-minrt): Clarify that main
1337 must take no arguments.
1339 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1341 * config/avr/builtins.def: Use function prototypes of given size
1343 * config/avr/avr.cc (avr_init_builtins): Adjust types required
1345 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
1347 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1349 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
1352 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
1354 * config/bpf/bpf.opt: Add help information for -mcpu.
1356 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
1359 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
1361 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
1363 * config/aarch64/aarch64.md (is_call): New attribute.
1364 (*and<mode>3nr_compare0): Rename to...
1365 (@aarch64_and<mode>3nr_compare0): ...this.
1366 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
1367 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
1368 * config/aarch64/aarch64-speculation.cc: Update file comment to
1369 describe the new late pass.
1370 (aarch64_do_track_speculation): Handle is_call insns like other calls.
1371 (pass_track_speculation): Add an is_late member variable.
1372 (pass_track_speculation::gate): Run the late pass for streaming-
1373 compatible functions and the early pass for other functions.
1374 (make_pass_track_speculation): Update accordingly.
1375 (make_pass_late_track_speculation): New function.
1376 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
1378 (aarch64_guard_switch_pstate_sm): Use it.
1380 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
1382 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
1383 Register these builtins with a pointer to uint64_t rather than unsigned
1386 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1389 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
1390 Conditionalize on '!TARGET_RDNA2_PLUS'.
1391 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
1392 (gcn_expand_reduc_scalar):
1393 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
1395 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1397 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
1398 '__gfx90a__' target CPU definition. Add some safeguards for the future.
1400 2024-02-19 Richard Biener <rguenther@suse.de>
1402 PR rtl-optimization/54052
1403 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
1404 local defs by LR_OUT.
1406 2024-02-19 Jakub Jelinek <jakub@redhat.com>
1408 PR tree-optimization/113967
1409 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
1410 in condition that @rpos is multiple of vector element size.
1412 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1415 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
1416 Suppress vsetvl fusion.
1418 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
1421 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
1422 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
1423 (ix86_emit_save_regs): Don't generate push2 if
1424 ix86_can_use_push2pop2 return false.
1425 (ix86_expand_epilogue): Don't generate pop2 if
1426 ix86_can_use_push2pop2 return false.
1428 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1430 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
1431 Note on complete device support.
1433 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1435 * doc/extend.texi (AVR Function Attributes): Fuse description
1436 of "signal" and "interrupt" attribute. Link pseudo instruction.
1438 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
1440 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
1441 symbol type conversions.
1442 (__cacop_d): Likewise.
1443 (__cpucfg): Likewise.
1444 (__asrtle_d): Likewise.
1445 (__asrtgt_d): Likewise.
1446 (__lddir_d): Likewise.
1447 (__ldpte_d): Likewise.
1448 (__crc_w_b_w): Likewise.
1449 (__crc_w_h_w): Likewise.
1450 (__crc_w_w_w): Likewise.
1451 (__crc_w_d_w): Likewise.
1452 (__crcc_w_b_w): Likewise.
1453 (__crcc_w_h_w): Likewise.
1454 (__crcc_w_w_w): Likewise.
1455 (__crcc_w_d_w): Likewise.
1456 (__csrrd_w): Likewise.
1457 (__csrwr_w): Likewise.
1458 (__csrxchg_w): Likewise.
1459 (__csrrd_d): Likewise.
1460 (__csrwr_d): Likewise.
1461 (__csrxchg_d): Likewise.
1462 (__iocsrrd_b): Likewise.
1463 (__iocsrrd_h): Likewise.
1464 (__iocsrrd_w): Likewise.
1465 (__iocsrrd_d): Likewise.
1466 (__iocsrwr_b): Likewise.
1467 (__iocsrwr_h): Likewise.
1468 (__iocsrwr_w): Likewise.
1469 (__iocsrwr_d): Likewise.
1470 (__frecipe_s): Likewise.
1471 (__frecipe_d): Likewise.
1472 (__frsqrte_s): Likewise.
1473 (__frsqrte_d): Likewise.
1475 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
1477 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
1478 function return value type to unsigned short.
1480 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
1482 * doc/sourcebuild.texi: add scan-assembler-bound
1484 2024-02-16 Jason Merrill <jason@redhat.com>
1486 * gdbhooks.py: Fix regex syntax.
1488 2024-02-16 Richard Biener <rguenther@suse.de>
1490 PR tree-optimization/113895
1491 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
1492 consistency checking when there are out-of-bound array
1493 accesses. Allow -1 off when from an array reference with
1496 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
1499 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
1502 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1504 * doc/sourcebuild.texi (Effective-Target Keywords, Other
1505 attribugs): Document linker_plugin.
1506 (Require Support): Document dg-require-linker-plugin.
1508 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
1511 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
1512 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
1513 (RISCV_MINOR_VERSION_BASE): Ditto.
1514 (RISCV_REVISION_VERSION_BASE): Ditto.
1515 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
1516 rather than magic number.
1517 * config/riscv/riscv.h (riscv_arch_help): New.
1518 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
1519 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
1520 --print-supported-extensions.
1521 * config/riscv/riscv.opt (march=help): New.
1522 (print-supported-extensions): New.
1523 (-print-supported-extensions): New.
1524 * doc/invoke.texi (RISC-V Options): Document -march=help.
1526 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
1529 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
1530 for indirect calls with 4 or more arguments in pac-enabled functions.
1532 2024-02-15 David Faust <david.faust@oracle.com>
1534 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
1535 use ldxb instead of ldxh.
1537 2024-02-15 Jakub Jelinek <jakub@redhat.com>
1539 PR middle-end/113921
1540 * cfgrtl.h (prepend_insn_to_edge): New declaration.
1541 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
1543 (prepend_insn_to_edge): New function.
1544 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
1545 insert_insn_on_edge.
1547 2024-02-15 Richard Biener <rguenther@suse.de>
1549 PR tree-optimization/111156
1550 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
1551 at the pattern stmt if any.
1553 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
1556 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
1557 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
1558 * config/avr/avr.cc (avr_adiw_reg_p): New function.
1559 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
1560 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
1561 * config/avr/avr.md: Same.
1562 (attr "isa") <tiny, no_tiny>: Remove.
1563 <adiw, no_adiw>: Add.
1564 (define_insn, define_insn_and_split): When an alternative has
1565 constraint "w", then set attribute "isa" to "adiw".
1566 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
1567 Built-in define __AVR_HAVE_ADIW__.
1568 * doc/invoke.texi (AVR Options): Document it.
1570 2024-02-15 Andrew Stubbs <ams@baylibre.com>
1572 * config/gcn/gcn-valu.md
1573 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
1574 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
1575 details are supported on RDNA devices.
1577 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
1579 PR middle-end/113508
1580 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
1581 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
1582 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
1583 Add sentence about what the mode m is.
1585 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
1587 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
1588 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
1591 2024-02-15 Richard Biener <rguenther@suse.de>
1593 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
1596 2024-02-15 Jakub Jelinek <jakub@redhat.com>
1598 PR tree-optimization/113567
1599 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
1600 _BitInt multiplication, division or modulo with
1601 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
1602 force the affected inputs into a new SSA_NAME.
1604 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
1607 * config/i386/mmx.md (V248FI): New mode iterator.
1609 (vec_shl_<V248FI:mode>): New expander.
1610 (vec_shl_<V24FI_32:mode>): Ditto.
1611 (vec_shr_<V248FI:mode>): Ditto.
1612 (vec_shr_<V24FI_32:mode>): Ditto.
1613 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
1614 (vec_shr_<V248FI:mode>): Ditto.
1616 2024-02-14 Jan Hubicka <jh@suse.cz>
1618 PR tree-optimization/111054
1619 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
1621 2024-02-14 Tamar Christina <tamar.christina@arm.com>
1623 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
1625 2024-02-14 Richard Biener <rguenther@suse.de>
1627 PR tree-optimization/113910
1628 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
1631 2024-02-14 Jakub Jelinek <jakub@redhat.com>
1633 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
1634 (pp_integer_with_precision): For unsigned ptrdiff_t printing
1635 with u, o or x print ptrdiff_t argument converted to
1636 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
1638 2024-02-14 Richard Biener <rguenther@suse.de>
1640 PR middle-end/113576
1641 * expr.cc (do_store_flag): For vector bool compares of vectors
1642 with padding zero that.
1643 * dojump.cc (do_compare_and_jump): Likewise.
1645 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
1647 * doc/install.texi (Prerequisites): Update gettext link.
1649 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
1652 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
1653 Return false if the incoming stack isn't 16-byte aligned.
1655 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
1657 PR middle-end/113904
1658 * omp-general.cc (struct omp_ts_info): Update for splitting of
1659 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1660 * omp-selectors.h (enum omp_tp_type): Replace
1661 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1663 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
1666 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
1667 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
1669 2024-02-13 Richard Biener <rguenther@suse.de>
1671 PR tree-optimization/113895
1672 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
1673 offset to discover constant array indices in bits, handle
1674 COMPONENT_REF to bitfields.
1676 2024-02-13 Richard Biener <rguenther@suse.de>
1678 PR tree-optimization/113831
1679 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
1682 2024-02-13 Richard Biener <rguenther@suse.de>
1684 PR tree-optimization/113902
1685 * tree-vect-loop.cc (move_early_exit_stmts): Track
1686 last_seen_vuse for VUSE updating.
1688 2024-02-13 Tamar Christina <tamar.christina@arm.com>
1690 PR tree-optimization/113734
1691 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
1692 an early break loop as partial.
1694 2024-02-13 Richard Biener <rguenther@suse.de>
1696 PR tree-optimization/113898
1697 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
1698 missing accumulated off adjustment.
1700 2024-02-13 Jakub Jelinek <jakub@redhat.com>
1702 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
1703 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
1704 it against UINT_MAX and ULONG_MAX.
1706 2024-02-13 David Malcolm <dmalcolm@redhat.com>
1708 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
1710 (emit_diagnostic_valist_meta): ...this.
1711 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
1712 (emit_diagnostic_valist_meta): ...this.
1714 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1716 PR tree-optimization/113849
1717 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
1718 fast path for widening casts where !m_upwards_2limb and lhs_type
1719 has precision which is a multiple of limb_prec.
1721 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1724 * attribs.cc (extract_attribute_substring): Remove.
1725 (lookup_scoped_attribute_spec): Don't call it.
1727 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1729 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
1730 and cast to fmt_size_t instead of %lu and cast to unsigned long.
1732 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
1734 * Makefile.in: Add no-info dependency.
1735 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
1737 * configure: Regenerate.
1739 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
1742 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
1743 available to all sub-targets.
1744 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1745 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1747 2024-02-12 Richard Biener <rguenther@suse.de>
1749 PR tree-optimization/113831
1750 PR tree-optimization/108355
1751 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
1752 we see variable array indices and get_ref_base_and_extent
1753 can resolve those to constants fix up the ops to constants
1755 (ao_ref_init_from_vn_reference): Use 'off' member for
1756 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
1757 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
1759 2024-02-12 Pan Li <pan2.li@intel.com>
1761 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
1762 Replace args to arguments for misspelled term.
1764 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
1767 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
1768 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
1769 when not linked with -mrodata-in-ram.
1771 2024-02-12 Richard Biener <rguenther@suse.de>
1773 PR tree-optimization/113863
1774 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1775 Record crossed virtual PHIs.
1776 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
1779 2024-02-10 Marek Polacek <polacek@redhat.com>
1784 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
1786 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1788 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
1789 computation of idx for i == 4 of bitint_prec_huge.
1791 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1793 PR middle-end/110754
1794 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
1795 decls create PARM_DECL with pointer to original type, set
1796 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
1797 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
1798 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
1799 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
1800 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
1801 of the var as argument.
1803 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1805 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
1806 size_t and precision 4 for ptrdiff_t. Formatting fix.
1807 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
1809 (test_pp_format): Test t and z modifiers.
1810 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
1812 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1814 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
1815 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
1816 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1817 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
1818 and casts to fmt_size_t instead of "%ld" and casts to long.
1819 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
1820 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
1821 instead of "%lu" and casts to unsigned long.
1822 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
1824 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1825 and casts to fmt_size_t instead of "%ld" and casts to long.
1826 * cfgexpand.cc (dump_stack_var_partition): Use
1827 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
1828 and casts to unsigned long.
1829 * gengtype.cc (adjust_field_rtx_def): Likewise.
1830 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1831 and casts to fmt_size_t instead of "%ld" and casts to long.
1832 * postreload-gcse.cc (dump_hash_table): Likewise.
1833 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
1834 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1835 (ggc_internal_alloc, ggc_free): Likewise.
1836 * genpreds.cc (write_lookup_constraint_1): Likewise.
1837 (write_insn_constraint_len): Likewise.
1838 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
1839 and casts to fmt_size_t instead of "%ld" and casts to long.
1840 * varasm.cc (output_constant_pool_contents): Use
1841 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
1842 * var-tracking.cc (dump_var): Likewise.
1844 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1846 PR tree-optimization/113783
1847 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
1848 through VIEW_CONVERT_EXPR for final cast checks. Handle
1849 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
1851 (gimple_lower_bitint): Don't merge mergeable operations or other
1852 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
1853 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
1856 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1858 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
1859 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
1860 HOST_SIZE_T_PRINT_HEX_PURE): Define.
1861 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
1864 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1866 PR middle-end/113415
1867 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
1868 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
1869 of hand written loop with emit_insn of copy_insn and emit original
1870 after_rtl_seq on the last edge.
1872 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1874 PR tree-optimization/113818
1875 * gimple-lower-bitint.cc (add_eh_edge): New function.
1876 (bitint_large_huge::handle_load,
1877 bitint_large_huge::lower_mergeable_stmt,
1878 bitint_large_huge::lower_muldiv_stmt): Use it.
1880 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1882 PR tree-optimization/113774
1883 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
1884 emit any comparison if m_first and low + 1 is equal to
1885 m_upwards_2limb, simplify condition for that. If not
1886 single_comparison, not m_first and we can prove that the idx <= low
1887 comparison will be always true, emit instead of idx <= low
1888 comparison low <= low such that cfg cleanup will optimize it at
1889 the end of the pass.
1891 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
1893 PR tree-optimization/113735
1894 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
1897 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1899 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
1900 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
1902 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
1906 * config/i386/constraints.md: List all constraints with j prefix.
1907 (j>): Change auto-dec to auto-inc in documentation.
1908 (je): Changed to a memory constraint with APX NDD TLS operand
1910 (jM): New memory constraint for APX NDD instructions.
1912 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
1913 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
1914 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
1915 (*add<mode>_1[SWI48]): Use je and jM.
1916 (addsi_1_zext): Use jM.
1917 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
1918 (*sub<mode>_1[SWI]): Use jM.
1919 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
1920 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
1921 (*and<dwi>3_doubleword): Likewise.
1923 (*andsi_1_zext): Likewise.
1924 (*and<mode>_1[SWI24]): Likewise.
1925 (*<code><dwi>3_doubleword[any_or]): Use rjO
1926 (*code<mode>_1[any_or SWI248]): Use jM.
1927 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
1928 * config/i386/predicates.md (apx_ndd_memory_operand): New.
1929 (apx_ndd_add_memory_operand): Likewise.
1931 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1934 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
1935 * doc/avr-mmcu.texi: Rebuild.
1937 2024-02-08 Tamar Christina <tamar.christina@arm.com>
1939 PR tree-optimization/113808
1940 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
1941 value cross iterations.
1943 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1945 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
1946 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
1948 2024-02-08 Richard Biener <rguenther@suse.de>
1950 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1951 Revert last change to dr_may_alias_p.
1953 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1955 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
1956 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
1957 Remove spec asm_misc.
1958 * config/avr/specs.h: Same.
1960 2024-02-08 Pan Li <pan2.li@intel.com>
1963 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
1964 sure the c.arg_num is >= 2 before checking.
1965 (struct build_frm_base): Ditto.
1966 (struct narrow_alu_def): Ditto.
1968 2024-02-07 Richard Biener <rguenther@suse.de>
1970 PR tree-optimization/113796
1971 * tree-if-conv.cc (combine_blocks): Wipe range-info before
1972 replacing PHIs and inserting predicates.
1974 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
1975 Uros Bizjak <ubizjak@gmail.com>
1978 * config/i386/i386-features.cc (timode_convert_cst): New helper
1979 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
1981 (timode_scalar_chain::convert_op): Use timode_convert_cst.
1982 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
1983 Use timode_convert_cst.
1985 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
1987 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
1988 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
1989 (AARCH64_FL_DEBUGv8p9): Likewise.
1990 (AARCH64_FL_FGT2): Likewise.Likewise.
1991 (AARCH64_FL_ITE): Likewise.
1992 (AARCH64_FL_PFAR): Likewise.
1993 (AARCH64_FL_PMUv3_ICNTR): Likewise.
1994 (AARCH64_FL_PMUv3_SS): Likewise.
1995 (AARCH64_FL_PMUv3p9): Likewise.
1996 (AARCH64_FL_RASv2): Likewise.
1997 (AARCH64_FL_S1PIE): Likewise.
1998 (AARCH64_FL_S1POE): Likewise.
1999 (AARCH64_FL_S2PIE): Likewise.
2000 (AARCH64_FL_S2POE): Likewise.
2001 (AARCH64_FL_SCTLR2): Likewise.
2002 (AARCH64_FL_SEBEP): Likewise.
2003 (AARCH64_FL_SPE_FDS): Likewise.
2004 (AARCH64_FL_TCR2): Likewise.
2006 2024-02-07 Richard Biener <rguenther@suse.de>
2008 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2009 Only check whether reads are in-bound in places that are not safe.
2010 Fix dependence check. Add missing newline. Clarify comments.
2012 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2014 PR tree-optimization/113750
2015 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
2016 for single predecessor when doing early break vect.
2017 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
2020 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2022 PR tree-optimization/113731
2023 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
2025 * gimple-iterator.h (gsi_move_before): Default new param to
2027 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
2030 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2032 PR tree-optimization/113756
2033 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
2034 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
2035 of lh_bits value and mask.
2037 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2039 PR tree-optimization/113753
2040 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
2041 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
2042 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
2043 so that they start with r[half_blocks_needed] lowest bit. Fix up
2044 computation of top mask for SIGNED.
2046 2024-02-07 Pan Li <pan2.li@intel.com>
2049 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
2050 the signature of func.
2051 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
2052 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
2053 overloaded func with empty args error.
2055 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
2058 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
2059 R10_REG after sorry.
2061 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
2063 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
2064 Move before new caller, and add ".default" suffix.
2065 (get_suffixed_assembler_name): New.
2066 (make_resolver_func): Use get_suffixed_assembler_name.
2067 (aarch64_generate_version_dispatcher_body): Redo name mangling.
2069 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2072 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
2073 element from std::pair<unsigned int, char> to an unnamed struct.
2074 Adjust uses of tile range variable.
2076 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2078 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
2079 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
2081 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2084 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
2085 reset maxlen to sizetype maximum.
2087 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2089 PR tree-optimization/113736
2090 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
2091 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
2093 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2095 PR tree-optimization/113759
2096 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
2097 or from_unsignedN differs from properties of typeN, update typeN
2098 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
2099 uselessly convertible to typeN, convert it using fold_convert or
2100 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
2101 (convert_plusminus_to_widen): Likewise.
2103 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
2106 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
2107 vector structure modes correctly.
2109 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
2111 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
2114 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
2117 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
2118 (x86_function_profiler): Call x86_64_select_profile_regnum to
2119 get a scratch register for large model profiling.
2121 2024-02-05 Richard Ball <richard.ball@arm.com>
2123 * config/arm/arm.cc (arm_output_mi_thunk): Emit
2124 insn for bti_c when bti is enabled.
2126 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2128 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
2131 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2133 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
2134 (neg<mode>2): Change the mode iterator from MSA to IMSA because
2135 in FP arithmetic we cannot use (0 - x) for -x.
2136 (neg<mode>2): New define_insn to implement FP vector negation,
2137 using a bnegi instruction to negate the sign bit.
2139 2024-02-05 Richard Biener <rguenther@suse.de>
2141 PR tree-optimization/113707
2142 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
2143 checking the avail set treat out-of-region defines as
2146 2024-02-05 Richard Biener <rguenther@suse.de>
2148 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
2149 the default mode when building a pointer.
2151 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2153 PR tree-optimization/113737
2154 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
2155 has just a single label, remove it and make single successor edge
2158 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2161 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2162 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
2165 2024-02-05 Richard Biener <rguenther@suse.de>
2168 * config/i386/i386-expand.cc
2169 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
2170 Use a new pseudo for the skipped number of bytes.
2172 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2174 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
2175 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
2178 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2180 * config/riscv/riscv.md: Include sifive-p400.md.
2181 * config/riscv/sifive-p400.md: New file.
2182 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2183 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2185 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
2186 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2187 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2189 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2191 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
2192 Add missing ":SI" to the match_operator.
2194 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2196 * config/xtensa/xtensa.md (SHI): New mode iterator.
2197 (2 split patterns related to constsynth):
2198 Change to also accept HImode operands.
2200 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
2202 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
2205 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2207 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
2209 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
2210 (elmsgnbit): Likewise.
2211 (neg<mode:FVEC>2): New define_insn.
2212 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
2213 are now instantiated in simd.md.
2215 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2217 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
2218 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
2221 2024-02-04 Li Wei <liwei@loongson.cn>
2223 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
2224 (loongarch_expand_vselect_vconcat): Ditto.
2225 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
2226 all 128-bit constant permutation situations.
2227 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
2228 (loongarch_is_imm_set_shuffle): Renamed function name.
2229 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
2230 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
2231 extract-even and extract-odd permutations.
2232 (loongarch_is_odd_extraction): Delete.
2233 (loongarch_is_even_extraction): Ditto.
2234 (loongarch_expand_vec_perm_const): Adjust.
2236 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2238 PR middle-end/113722
2239 * wide-int.cc (wi::bswap_large): Rename third argument from
2240 len to xlen and adjust use in safe_uhwi. Add len variable, set
2241 it to BLOCKS_NEEDED (precision) and use it for clearing of val
2242 and as canonize argument. Clear val using memset instead of
2245 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2247 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
2248 mmi.preferred_base + mmi.size - sizeof (void *).
2250 2024-02-03 Xi Ruoyao <xry111@xry111.site>
2252 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
2253 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
2254 the ODR-violating locale declaration.
2256 2024-02-02 Tamar Christina <tamar.christina@arm.com>
2258 PR tree-optimization/113588
2259 PR tree-optimization/113467
2260 * tree-vect-data-refs.cc
2261 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
2262 (vect_analyze_early_break_dependences): Update comments.
2264 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
2267 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
2268 and PA_BUILTIN_SET_FPSR builtins.
2269 * (pa_builtins_icode): Declare.
2270 * (def_builtin, pa_fpu_init_builtins): New.
2271 * (pa_init_builtins): Initialize FPU builtins.
2272 * (pa_builtin_decl, pa_expand_builtin_1): New.
2273 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
2274 PA_BUILTIN_SET_FPSR builtins.
2275 * (pa_atomic_assign_expand_fenv): New.
2276 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
2278 (get_fpsr, put_fpsr): New expanders.
2279 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
2282 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2285 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
2287 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
2289 * doc/extend.texi (Common Type Attributes): Fix typo in
2290 description of hardbool.
2292 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2294 PR tree-optimization/113692
2295 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
2296 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
2299 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2301 PR middle-end/113699
2302 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
2303 uninitialized large/huge _BitInt SSA_NAME inputs.
2305 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2307 PR middle-end/113705
2308 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
2309 around wi::to_wide in order to compare value in prec precision.
2311 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
2314 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2316 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2318 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2320 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2322 2024-02-02 Pan Li <pan2.li@intel.com>
2324 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
2325 (riscv_pass_by_reference): Ditto.
2326 (riscv_fntype_abi): Ditto.
2328 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2330 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
2331 (pre_vsetvl::cleaup): Remove vsetvl_pre.
2332 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
2334 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
2336 * config/loongarch/larchintrin.h
2337 (__frecipe_s): Update function return type.
2338 (__frecipe_d): Ditto.
2339 (__frsqrte_s): Ditto.
2340 (__frsqrte_d): Ditto.
2342 2024-02-02 Li Wei <liwei@loongson.cn>
2344 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
2345 (loongarch_vector_costs::add_stmt_cost): Adjust.
2347 2024-02-02 Xi Ruoyao <xry111@xry111.site>
2349 * config/loongarch/loongarch.md (unspec): Add
2350 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
2351 (la_pcrel64_two_parts): New define_insn.
2352 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
2353 typo in the comment.
2354 (loongarch_call_tls_get_addr): If -mcmodel=extreme
2355 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
2356 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
2357 note to allow CSE addressing __tls_get_addr.
2358 (loongarch_legitimize_tls_address): If -mcmodel=extreme
2359 -mexplicit-relocs={always,auto}, address TLS IE symbols with
2360 la_pcrel64_two_parts.
2361 (loongarch_split_symbol): If -mcmodel=extreme
2362 -mexplicit-relocs={always,auto}, address symbols with
2363 la_pcrel64_two_parts.
2364 (loongarch_output_mi_thunk): Clean up unreachable code. If
2365 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
2366 thunks with la_pcrel64_two_parts.
2368 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2370 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
2371 Add support for call36.
2373 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2375 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2376 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
2377 the macro instruction loading symbol address is not applicable.
2378 (loongarch_call_tls_get_addr): Adjust code.
2379 (loongarch_legitimize_tls_address): Likewise.
2381 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2383 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
2384 Add function declaration.
2385 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2386 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
2388 (loongarch_load_tls): Added macro support in extreme mode.
2389 (loongarch_call_tls_get_addr): Likewise.
2390 (loongarch_legitimize_tls_address): Likewise.
2391 (loongarch_force_address): Likewise.
2392 (loongarch_legitimize_move): Likewise.
2393 (loongarch_output_mi_thunk): Likewise.
2394 (loongarch_option_override_internal): Remove the code that detects
2395 explicit relocs status.
2396 (loongarch_handle_model_attribute): Likewise.
2397 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
2398 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
2399 (symbolic_off64_or_reg_operand): Likewise.
2401 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2403 * config/loongarch/loongarch.cc (loongarch_load_tls):
2404 Load all types of tls symbols through one function.
2405 (loongarch_got_load_tls_gd): Delete.
2406 (loongarch_got_load_tls_ld): Delete.
2407 (loongarch_got_load_tls_ie): Delete.
2408 (loongarch_got_load_tls_le): Delete.
2409 (loongarch_call_tls_get_addr): Modify the called function name.
2410 (loongarch_legitimize_tls_address): Likewise.
2411 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
2412 (@load_tls<mode>): New template.
2413 (@got_load_tls_ld<mode>): Delete.
2414 (@got_load_tls_le<mode>): Delete.
2415 (@got_load_tls_ie<mode>): Delete.
2417 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2419 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
2420 (loongarch_legitimize_address): Add logical transformation code.
2422 2024-02-01 Marek Polacek <polacek@redhat.com>
2424 * doc/invoke.texi: Update -Wdangling-reference documentation.
2426 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
2429 * config/i386/i386.md (*cmp<dwi>_doubleword):
2430 Do not force SUBREG pieces to pseudos.
2432 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
2434 * config/pa/pa.md (atomic_storedi_1): Fix bug in
2437 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
2439 * config/avr/avr.cc: Tabify.
2441 2024-02-01 Richard Ball <richard.ball@arm.com>
2443 PR tree-optimization/111268
2444 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
2445 Add variable-length check for vector input arguments
2448 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2450 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
2451 hard-code number of SGPR/VGPR/AVGPR registers.
2452 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
2453 SGPR/VGPR/AVGPR registers.
2455 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
2457 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
2458 attribute, and include sifive-p600.md.
2459 * config/riscv/generic-ooo.md: Update type attribute.
2460 * config/riscv/generic.md: Update type attribute.
2461 * config/riscv/sifive-7.md: Update type attribute.
2462 * config/riscv/sifive-p600.md: New file.
2463 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2464 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2466 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
2467 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2468 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
2470 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
2472 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
2473 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
2474 * config/riscv/riscv.opt: New macro for 7 new unprivileged
2476 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
2477 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
2479 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2481 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
2482 -static-libasan. Add missing whitespace.
2484 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2486 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
2487 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
2488 Don't 'define_constants'.
2490 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2492 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
2494 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2496 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
2497 [TARGET_RDNA3]: Adjust.
2499 2024-02-01 Richard Biener <rguenther@suse.de>
2501 PR tree-optimization/113693
2502 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
2503 data when available.
2505 2024-02-01 Jakub Jelinek <jakub@redhat.com>
2506 Jason Merrill <jason@redhat.com>
2509 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
2510 on variables which were promoted to TREE_STATIC.
2512 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
2513 Richard Biener <rguenther@suse.de>
2516 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
2517 information via tree_non_zero_bits to check if this operand
2518 is suitably extended for a widening (or highpart) multiplication.
2519 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
2520 isn't already of the claimed type.
2522 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2525 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2527 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2528 (generic_ooo_branch): ditto
2529 * config/riscv/generic.md (generic_sfb_alu): ditto
2530 (generic_fmul_half): ditto
2531 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2532 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2533 (sifive_7_popcount): ditto
2534 * config/riscv/vector.md: change rdfrm to fmove
2535 * config/riscv/zc.md: change pushpop to load/store
2537 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2540 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2541 Robin Dapp <rdapp.gcc@gmail.com>
2543 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2544 (generic_ooo_vec_load): ditto
2545 (generic_ooo_vec_store): ditto
2546 (generic_ooo_vec_loadstore_seg): ditto
2547 (generic_ooo_vec_alu): ditto
2548 (generic_ooo_vec_fcmp): ditto
2549 (generic_ooo_vec_imul): ditto
2550 (generic_ooo_vec_fadd): ditto
2551 (generic_ooo_vec_fmul): ditto
2552 (generic_ooo_crypto): ditto
2553 (generic_ooo_perm): ditto
2554 (generic_ooo_vec_reduction): ditto
2555 (generic_ooo_vec_ordered_reduction): ditto
2556 (generic_ooo_vec_idiv): ditto
2557 (generic_ooo_vec_float_divsqrt): ditto
2558 (generic_ooo_vec_mask): ditto
2559 (generic_ooo_vec_vesetvl): ditto
2560 (generic_ooo_vec_setrm): ditto
2561 (generic_ooo_vec_readlen): ditto
2562 * config/riscv/riscv.md: include generic-vector-ooo
2563 * config/riscv/generic-vector-ooo.md: New file. to here
2565 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2568 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2570 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2572 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2574 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2576 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2577 Robin Dapp <rdapp.gcc@gmail.com>
2579 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2580 (generic_ooo_vec_load): ditto
2581 (generic_ooo_vec_store): ditto
2582 (generic_ooo_vec_loadstore_seg): ditto
2583 (generic_ooo_vec_alu): ditto
2584 (generic_ooo_vec_fcmp): ditto
2585 (generic_ooo_vec_imul): ditto
2586 (generic_ooo_vec_fadd): ditto
2587 (generic_ooo_vec_fmul): ditto
2588 (generic_ooo_crypto): ditto
2589 (generic_ooo_perm): ditto
2590 (generic_ooo_vec_reduction): ditto
2591 (generic_ooo_vec_ordered_reduction): ditto
2592 (generic_ooo_vec_idiv): ditto
2593 (generic_ooo_vec_float_divsqrt): ditto
2594 (generic_ooo_vec_mask): ditto
2595 (generic_ooo_vec_vesetvl): ditto
2596 (generic_ooo_vec_setrm): ditto
2597 (generic_ooo_vec_readlen): ditto
2598 * config/riscv/riscv.md: include generic-vector-ooo
2599 * config/riscv/generic-vector-ooo.md: New file. to here
2601 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2603 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2604 (generic_ooo_branch): ditto
2605 * config/riscv/generic.md (generic_sfb_alu): ditto
2606 (generic_fmul_half): ditto
2607 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2608 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2609 (sifive_7_popcount): ditto
2610 * config/riscv/vector.md: change rdfrm to fmove
2611 * config/riscv/zc.md: change pushpop to load/store
2613 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
2616 * config/aarch64/aarch64-simd.md (split for movv8di):
2617 For strict aligned mode, use DImode instead of TImode.
2619 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
2621 PR middle-end/113607
2622 * match.pd: Make sure else values match when folding a
2623 vec_cond into a conditional operation.
2625 2024-01-31 Marek Polacek <polacek@redhat.com>
2627 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
2629 2024-01-31 Tamar Christina <tamar.christina@arm.com>
2630 Matthew Malcomson <matthew.malcomson@arm.com>
2633 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
2635 * builtins.cc (expand_builtin): Include HWASAN when checking for
2638 2024-01-31 Richard Biener <rguenther@suse.de>
2640 PR middle-end/110176
2641 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
2642 to match INTEGER_CST only without outstanding conversion.
2644 2024-01-31 Alex Coplan <alex.coplan@arm.com>
2647 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
2648 V16QImode for the full 16-byte FPR saves in the vector PCS case.
2650 2024-01-31 Richard Biener <rguenther@suse.de>
2652 PR tree-optimization/111444
2653 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
2654 vn_reference_lookup_2 when optimistically skipping may-defs.
2656 2024-01-31 Richard Biener <rguenther@suse.de>
2658 PR tree-optimization/113630
2659 * tree-ssa-pre.cc (compute_avail): Avoid registering a
2660 reference with a representation with not matching base
2663 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2665 PR rtl-optimization/113656
2666 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
2667 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
2669 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2672 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
2673 with BLKmode are larger than DWARF2_ADDR_SIZE.
2675 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2677 PR tree-optimization/113639
2678 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2679 For VIEW_CONVERT_EXPR set rhs1 to its operand.
2681 2024-01-31 Richard Biener <rguenther@suse.de>
2683 PR tree-optimization/113670
2684 * tree-vect-data-refs.cc (vect_check_gather_scatter):
2685 Make sure we can take the address of the reference base.
2687 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
2689 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
2690 ATA5835, ATtiny64AUTO, ATA5700M322.
2691 * doc/avr-mmcu.texi: Rebuild.
2693 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2696 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
2699 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2701 PR middle-end/112917
2702 PR middle-end/113100
2703 * builtins.cc (expand_builtin_stack_address): Use
2704 STACK_ADDRESS_OFFSET.
2705 * doc/extend.texi (__builtin_stack_address): Adjust.
2706 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
2707 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
2708 * doc/tm.texi: Rebuilt.
2710 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2713 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
2714 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
2715 (pre_vsetvl::compute_transparent): New function.
2716 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
2718 2024-01-30 Fangrui Song <maskray@google.com>
2721 * config/i386/constraints.md: Define constraint "Ws".
2722 * doc/md.texi: Document it.
2724 2024-01-30 Marek Polacek <polacek@redhat.com>
2728 * doc/invoke.texi: Update -Wdangling-reference description.
2730 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2732 * config/xtensa/constraints.md (R, T, U):
2733 Change define_constraint to define_memory_constraint.
2734 * config/xtensa/predicates.md (move_operand): Don't check that a
2735 constant pool operand size is a multiple of UNITS_PER_WORD.
2736 * config/xtensa/xtensa.cc
2737 (xtensa_lra_p, TARGET_LRA_P): Remove.
2738 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
2739 clause as it can no longer be true.
2740 (fixup_subreg_mem): Drop function.
2741 (xtensa_output_integer_literal_parts): Consider 16-bit wide
2743 (xtensa_legitimate_constant_p): Add short-circuit path for
2744 integer load instructions. Don't check that mode size is
2745 at least UNITS_PER_WORD.
2746 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
2747 rather reload_in_progress and reload_completed.
2748 (doloop_end): Drop operand 2.
2749 (movhi_internal): Add alternative loading constant from a
2751 (define_split for DI register_operand): Don't limit to
2752 !TARGET_AUTO_LITPOOLS.
2753 * config/xtensa/xtensa.opt (mlra): Change to no effect.
2755 2024-01-30 Pan Li <pan2.li@intel.com>
2757 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
2758 calculate the gpr count required by vls mode.
2759 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
2760 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
2762 (riscv_get_arg_info): Add vls mode handling.
2763 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
2765 2024-01-30 Richard Biener <rguenther@suse.de>
2767 PR tree-optimization/113659
2768 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2769 Handle main exit without virtual use.
2771 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
2773 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
2775 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
2778 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
2779 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
2780 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
2781 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
2782 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
2783 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
2785 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2788 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
2789 Mark all registers that occur in addresses as needing a GPR.
2791 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2794 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
2795 the containing insn as an extra parameter. Reset debug instructions
2796 if they reference a register that is no longer used by real insns.
2797 (early_ra::apply_allocation): Update calls accordingly.
2799 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2801 PR tree-optimization/113603
2802 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
2803 count_nonzero_bytes call refetch si using get_strinfo in case it
2804 has been unshared in the meantime.
2806 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2808 PR middle-end/101195
2809 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
2810 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
2812 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
2814 * config/riscv/thead.cc (th_print_operand_address): Change %ld
2817 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
2818 Manolis Tsamis <manolis.tsamis@vrull.eu>
2819 Philipp Tomsich <philipp.tomsich@vrull.eu>
2821 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
2822 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
2824 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
2825 Call on framework moved later.
2827 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
2829 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
2830 instruction in naked function epilogues.
2832 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
2835 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
2836 gcc_cv_as_mips_explicit_relocs.
2837 * configure: Regnerated.
2839 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
2842 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
2843 Correct generated RTL.
2844 (arm_rev16si2_alt1): Correctly handle conditional execution.
2845 (arm_rev16si2_alt2): Likewise.
2847 2024-01-29 Richard Biener <rguenther@suse.de>
2849 PR middle-end/113622
2850 * expr.cc (expand_assignment): Spill hard registers if
2851 we index them with a variable offset.
2853 2024-01-29 Richard Biener <rguenther@suse.de>
2855 PR middle-end/113622
2856 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
2857 Also allow DECL_HARD_REGISTER variables.
2859 2024-01-29 Alex Coplan <alex.coplan@arm.com>
2862 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
2863 Use iterate_safely when iterating over debug uses.
2864 (fixup_debug_uses): Likewise.
2865 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
2866 over nondebug insns instead of manually maintaining the next insn.
2867 * iterator-utils.h (class safe_iterator): New.
2868 (iterate_safely): New.
2870 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
2873 * config/i386/i386-options.cc (ix86_set_func_type): Save
2874 callee-saved registers in noreturn functions for -O0/-Og.
2876 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2879 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
2880 define for !TARGET_RDNA2_PLUS.
2882 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
2885 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
2886 workaround for right shifts.
2887 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
2888 (vect_determine_precisions_from_range): Be more selective about
2889 which codes can be narrowed based on their input and output ranges.
2890 For shifts, require at least one more bit of precision than the
2891 maximum shift amount.
2893 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2895 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
2897 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2899 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
2900 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
2903 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2906 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
2907 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
2908 (SET_SRAM_ECC_UNSET): ... this.
2909 (copy_early_debug_info): Remove gfx900 special case, now handled as
2910 part of the generic handling.
2911 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
2913 2024-01-29 Jakub Jelinek <jakub@redhat.com>
2915 PR tree-optimization/110603
2916 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
2917 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
2918 overwritten anyway). Avoid creating invalid range with minlen
2919 larger than maxlen. Formatting fix.
2921 2024-01-29 Richard Biener <rguenther@suse.de>
2924 * tree-inline.cc (initialize_inlined_parameters): Reverse
2925 the decl chain of inlined parameters.
2927 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2929 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
2930 alignment of CFString constants by setting DECL_USER_ALIGN.
2932 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2933 Jakub Jelinek <jakub@redhat.com>
2936 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
2937 and BUILT_IN_GCC_NESTED_PTR_DELETED.
2938 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
2939 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
2940 rename the library fallbacks to __gcc_nested_func_ptr_created and
2941 __gcc_nested_func_ptr_deleted.
2942 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
2943 and __gcc_nested_func_ptr_deleted.
2944 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
2945 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
2946 * tree.cc (build_common_builtin_nodes): Build the
2947 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
2948 builtins only for non-explicit.
2950 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
2952 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
2954 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2957 * config/i386/i386-options.cc (ix86_set_func_type): Don't
2958 save and restore callee saved registers for a noreturn function
2959 with nothrow or compiled with -fno-exceptions.
2961 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2965 * config/i386/i386-expand.cc (ix86_expand_call): Replace
2966 no_caller_saved_registers check with call_saved_registers check.
2967 Clobber all registers that are not used by the callee with
2968 no_callee_saved_registers attribute.
2969 * config/i386/i386-options.cc (ix86_set_func_type): Set
2970 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
2971 noreturn function. Disallow no_callee_saved_registers with
2972 interrupt or no_caller_saved_registers attributes together.
2973 (ix86_set_current_function): Replace no_caller_saved_registers
2974 check with call_saved_registers check.
2975 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
2976 (ix86_handle_call_saved_registers_attribute): This.
2977 (ix86_gnu_attributes): Add
2978 ix86_handle_call_saved_registers_attribute.
2979 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
2980 no_caller_saved_registers check with call_saved_registers check.
2981 (ix86_function_ok_for_sibcall): Don't allow callee with
2982 no_callee_saved_registers attribute when the calling function
2983 has callee-saved registers.
2984 (ix86_comp_type_attributes): Also check
2985 no_callee_saved_registers.
2986 (ix86_epilogue_uses): Replace no_caller_saved_registers check
2987 with call_saved_registers check.
2988 (ix86_hard_regno_scratch_ok): Likewise.
2989 (ix86_save_reg): Replace no_caller_saved_registers check with
2990 call_saved_registers check. Don't save any registers for
2991 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
2992 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
2993 no_callee_saved_registers attribute is called.
2994 (find_drap_reg): Replace no_caller_saved_registers check with
2995 call_saved_registers check.
2996 * config/i386/i386.h (call_saved_registers_type): New enum.
2997 (machine_function): Replace no_caller_saved_registers with
2998 call_saved_registers.
2999 * doc/extend.texi: Document no_callee_saved_registers attribute.
3001 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3003 PR tree-optimization/113614
3004 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
3005 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
3006 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
3008 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3010 PR tree-optimization/113568
3011 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
3012 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
3013 in the widening extension checks.
3015 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3017 * gimple-lower-bitint.cc (gimple_lower_bitint): For
3018 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
3020 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
3022 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
3023 the warning for an attribute-always_inline without inline declaration.
3025 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
3028 * genopinit.cc (main): Split init_all_optabs into functions
3029 of 1000 patterns each.
3031 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3033 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
3035 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
3036 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
3039 2024-01-26 Andrew Stubbs <ams@baylibre.com>
3041 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
3042 * config/gcn/gcn-valu.md (all_convert): New iterator.
3043 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
3044 define_expand, and rename the old one to ...
3045 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
3046 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
3047 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
3048 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
3049 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
3050 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
3051 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
3052 (<u>mulqihi3_scalar): Likewise.
3054 2024-01-26 Richard Biener <rguenther@suse.de>
3056 PR tree-optimization/113602
3057 * tree-data-ref.cc (dr_analyze_innermost): Fail when
3058 the base object isn't addressable.
3060 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3062 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
3063 "--amdhsa-code-object-version=" argument.
3064 (ASM_SPEC): Use it; replace previous version of it.
3066 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3068 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
3069 (pre_vsetvl::emit_vsetvl): Ditto.
3071 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3073 * config/loongarch/lasx.md (vec_extract<mode>_0):
3074 New define_insn_and_split patten.
3076 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3078 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
3080 2024-01-26 Li Wei <liwei@loongson.cn>
3082 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
3084 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3087 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
3089 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
3092 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
3093 undefined shift after the call to exact_log2.
3095 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
3098 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
3099 before taking the negative of it.
3101 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
3104 * lra-constraints.cc (curr_insn_transform): Change class even for
3105 spilled pseudo successfully matched with with NO_REGS.
3107 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
3110 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
3112 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
3115 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
3116 (aarch64_expand_epilogue): Use the new function.
3117 (aarch64_split_compare_and_swap): Likewise.
3118 (aarch64_split_atomic_op): Likewise.
3120 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
3122 PR middle-end/112971
3123 * fold-const.cc (simplify_const_binop): New function for binop
3124 simplification of two constant vectors when element-wise
3125 handling is not necessary.
3126 (const_binop): Call new function.
3128 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
3130 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
3131 * config/riscv/constraints.md: Likewise.
3132 * config/riscv/corev.def: Likewise.
3133 * config/riscv/corev.md: Likewise.
3134 * config/riscv/predicates.md: Likewise.
3135 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
3136 * config/riscv/riscv-ftypes.def: Likewise.
3137 * config/riscv/riscv.opt: Likewise.
3138 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
3139 * doc/extend.texi: Add XCVbitmanip builtin documentation.
3140 * doc/sourcebuild.texi: Likewise.
3142 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
3144 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
3146 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
3149 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
3150 (riscv_fntype_abi): Ditto.
3151 * config/riscv/riscv.opt: Ditto.
3153 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3155 PR middle-end/113574
3156 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
3157 count against TYPE_PRECISION rather than TYPE_SIZE.
3159 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3162 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
3163 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
3165 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3168 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
3169 whether each split instruction is a load that clobbers the source
3170 address. Emit that instruction last if so.
3172 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3175 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
3177 (<optab><Vnarrowq><mode>2): Use it instead of generating a
3178 paradoxical subreg for the input.
3180 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3182 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
3183 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
3184 predecessors dump information.
3186 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3188 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
3189 redundant full available computation.
3190 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3192 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3194 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
3195 * doc/rtl.texi (CONST_VECTOR): Likewise.
3197 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3199 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
3200 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
3201 (pass_vsetvl::execute): Ditto.
3202 * config/riscv/riscv.opt: Ditto.
3204 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
3206 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
3207 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
3209 2024-01-25 Richard Biener <rguenther@suse.de>
3211 PR tree-optimization/113576
3212 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
3213 exits with may_be_zero niters when its the last one.
3215 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
3217 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3218 For symbols of type tls, non-zero Offset is not generated.
3220 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
3222 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
3223 P9 with m32 and mpowerpc64.
3225 2024-01-25 liuhongt <hongtao.liu@intel.com>
3227 * config/i386/i386-options.cc (ix86_option_override_internal):
3228 Enable -mlam=u57 by default when compiled with
3229 -fsanitize=hwaddress.
3231 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
3233 * common/config/riscv/riscv-common.cc (riscv_implied_info):
3234 Remove {"ztso", "a"}.
3236 2024-01-24 Martin Jambor <mjambor@suse.cz>
3240 * cgraph.h (cgraph_edge): Add a parameter to
3241 redirect_call_stmt_to_callee.
3242 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
3243 parameter to modify_call.
3244 (ipa_release_ssas_in_hash): Declare.
3245 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
3246 parameter killed_ssas, pass it to padjs->modify_call.
3247 * ipa-param-manipulation.cc (purge_all_uses): New function.
3248 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
3249 Instead of substituting uses, invoke purge_all_uses. If
3250 hash of killed SSAs has not been provided, create a temporary one
3251 and release SSAs that have been added to it.
3252 (compare_ssa_versions): New function.
3253 (ipa_release_ssas_in_hash): Likewise.
3254 * tree-inline.cc (redirect_all_calls): Create
3255 id->killed_new_ssa_names earlier, pass it to edge redirection,
3257 (copy_body): Release SSAs in id->killed_new_ssa_names.
3259 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
3262 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
3263 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
3265 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
3268 * config/riscv/sfb.md: New splitters to rewrite single bit
3269 sign extension as the condition to SFB instructions.
3271 2024-01-24 Jan Hubicka <jh@suse.cz>
3274 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
3275 (fmin-function-alignment): New parameter.
3276 * doc/invoke.texi: (-fmin-function-alignment): Document.
3277 (-falign-functions,-falign-loops,-falign-labels): Mention that
3278 aglinments are ignored in cold code.
3279 * varasm.cc (assemble_start_function): Handle min-function-alignment.
3281 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3284 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
3286 * config/aarch64/iterators.md (VQDIV): Remove.
3287 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
3288 SVE_I_SIMD_DI): New.
3289 (VPRED, sve_lane_con): Add V4SI and V2DI.
3290 * config/aarch64/aarch64-sve.md (<optab><mode>3,
3291 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
3292 (mul<mode>3): New, split from <optab><mode>3.
3293 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
3294 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
3295 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
3296 SVE_FULL_HSDI_SIMD_DI.
3298 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3300 PR tree-optimization/113552
3301 * config/aarch64/aarch64.cc
3302 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
3304 2024-01-24 Martin Jambor <mjambor@suse.cz>
3307 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
3308 count is equal or greater than the limit. Use the limit from the
3311 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
3313 * configure.ac: Detect the explicit relocs support for
3314 mips, and define C macro MIPS_EXPLICIT_RELOCS.
3315 * config.in: Regenerated.
3316 * configure: Regenerated.
3317 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
3318 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
3319 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
3320 !TARGET_EXPLICIT_RELOCS instead of just set it.
3321 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
3322 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
3323 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
3324 and define -m(no-)explicit-relocs as aliases.
3326 2024-01-24 Alex Coplan <alex.coplan@arm.com>
3328 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
3330 (-mlate-ldp-fusion): Likewise.
3332 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3334 * tree-vect-loop.cc (vect_get_vect_def,
3335 vect_create_epilog_for_reduction): Rename main_exit_p to
3338 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3340 PR tree-optimization/113364
3341 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
3342 early exits then we must reduce from the first offset for all of them.
3344 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3347 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
3349 (get_bb_index): Ditto.
3350 (pre_vsetvl::compute_avl_def_data): Ditto.
3351 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
3352 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3354 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
3355 Richard Sandiford <richard.sandiford@arm.com>
3358 * ccmp.cc (ccmp_candidate_p): Add outer argument.
3359 Allow if the outer is true and the lhs is used more
3361 (expand_ccmp_expr): Update call to ccmp_candidate_p.
3362 * expr.h (expand_expr_real_gassign): Declare.
3363 * expr.cc (expand_expr_real_gassign): New function, split out from...
3364 (expand_expr_real_1): ...here.
3365 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
3367 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3370 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
3371 (fixup_debug_use): New.
3372 (fixup_debug_uses_trailing_add): New.
3373 (fixup_debug_uses): New. Use it ...
3374 (ldp_bb_info::fuse_pair): ... here.
3375 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
3376 fix up debug uses of the base register that are affected by
3377 folding in the trailing add insn.
3379 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3382 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
3383 Update trailing nondebug uses of the base register in the case
3384 of cancelling writeback.
3386 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3389 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
3390 (debug_insn_use_iterator): New.
3391 (set_info::first_debug_insn_use): New.
3392 (set_info::debug_insn_uses): New.
3393 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
3394 (set_info::first_debug_insn_use): New.
3395 (set_info::debug_insn_uses): New.
3397 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3400 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
3401 Don't record hazards against the opposite insn in the pair.
3403 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3406 * config/aarch64/aarch64-ldp-fusion.cc
3407 (struct stp_change_builder): New.
3408 (decide_stp_strategy): Reanme to ...
3409 (try_repurpose_store): ... this.
3410 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
3411 construct stp changes. Fix up uses when inserting new stp insns.
3413 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3416 * rtl-ssa.h: Include hash-set.h.
3417 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
3418 new_sets parameter and use it to keep track of new user-created sets.
3419 (function_info::apply_changes_to_insn): Also call add_def on new sets.
3420 (function_info::change_insns): Add hash_set to keep track of new
3421 user-created defs. Plumb it through.
3422 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
3423 apply_changes_to_insn.
3425 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3428 * rtl-ssa/accesses.cc (function_info::create_use): New.
3429 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
3430 Ensure new uses end up referring to permanent defs.
3431 * rtl-ssa/functions.h (function_info::create_use): Declare.
3433 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3436 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
3437 to finalize_new_accesses from the backwards placement loop, run it
3438 forwards in a separate loop.
3440 2024-01-23 Richard Biener <rguenther@suse.de>
3442 PR tree-optimization/113552
3443 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
3444 floor_log2 instead of exact_log2 on the number of calls.
3446 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
3447 Jakub Jelinek <jakub@redhat.com>
3449 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
3452 2024-01-23 Richard Biener <rguenther@suse.de>
3454 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3455 Separate single and multi-exit case when creating PHIs between
3456 the main and epilogue.
3458 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
3461 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
3462 MODE_single variants of functions that don't take tuple arguments.
3464 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3467 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
3468 Don't assert recog success, just punt if the writeback pair
3471 2024-01-23 Jakub Jelinek <jakub@redhat.com>
3473 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
3474 ATTRIBUTE_UNUSED to decl.
3476 2024-01-23 Richard Biener <rguenther@suse.de>
3479 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
3480 handle unexpected but bogus DIE contexts when not checking
3483 2024-01-23 Jakub Jelinek <jakub@redhat.com>
3485 PR tree-optimization/113462
3486 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
3487 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
3488 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
3489 sizes between 129 and 8192 bytes.
3491 2024-01-23 Xi Ruoyao <xry111@xry111.site>
3493 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3494 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
3495 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
3496 (loongarch_call_tls_get_addr): Do not split symbols of
3497 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
3498 EXPLICIT_RELOCS_AUTO.
3500 2024-01-23 Richard Biener <rguenther@suse.de>
3502 * alias.cc (known_base_value_p): Remove.
3503 (find_base_value): Remove PLUS/MINUS handling
3504 when both operands are not CONST_INT_P.
3506 2024-01-23 Richard Biener <rguenther@suse.de>
3508 PR rtl-optimization/113255
3509 * alias.cc (find_base_term): Remove PLUS/MINUS handling
3510 when both operands are not CONST_INT_P.
3512 2024-01-23 Richard Biener <rguenther@suse.de>
3515 * dwarf2out.cc (dwarf2out_finish): Reset all type units
3516 for the fat part of an LTO compile.
3518 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
3520 * doc/sourcebuild.texi: Add attributes for keywords.
3522 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
3525 * doc/invoke.texi (Warning Options): Correct lists of options
3526 enabled by -Wall and -Wextra by checking against common.opt
3529 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
3532 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
3533 instead of cpu_optaliases.
3534 (check_arch): Use arch_opt_alias instead of arch_optaliases.
3536 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3538 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
3539 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
3540 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
3542 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3545 * config/riscv/riscv.md: Use reg instead of subreg.
3547 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
3550 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
3551 to match the compiler default.
3552 (simple_object_copy_lto_debug_sections): Never unlink the outfile
3553 on error as the caller does so.
3554 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
3555 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
3557 2024-01-22 Richard Biener <rguenther@suse.de>
3559 PR tree-optimization/113373
3560 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3561 Create LC PHIs in the exit blocks where necessary.
3562 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
3563 to handle missing LC PHIs.
3564 (find_connected_edge): Remove.
3565 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
3567 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3569 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
3571 2024-01-22 xuli <xuli1@eswincomputing.com>
3574 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
3575 (registered_function::overloaded_hash):refactor.
3576 (resolve_overloaded_builtin):avoid internal ICE.
3578 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
3582 * calls.cc (emit_library_call_value_1): Pass valid TYPE
3584 * expr.cc (emit_push_insn): Likewise.
3586 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
3588 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
3589 correcction version of last change.
3591 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
3593 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
3594 fix bugs in signature.
3596 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
3597 Richard Biener <rguenther@suse.de>
3599 PR rtl-optimization/111267
3600 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
3601 profitable_p method to likely_profitable_p.
3602 (try_fwprop_subst_node): Update call to likely_profitable_p.
3603 Only bail-out early when !prop.likely_profitable_p for instructions
3604 that are not single sets. When comparing costs, bail-out if the
3605 cost is unchanged and !prop.likely_profitable_p.
3607 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
3610 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
3611 isn't enabled by -Wunused unless -Wextra is provided, and that
3612 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
3613 -Wunused doesn't enable -Wunused-* options documented as behaving
3614 otherwise, and list them explicitly.
3616 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
3619 * doc/invoke.texi (Warning Options): Fix broken example and
3620 clean up/reorganize the others. Also describe what the short-form
3623 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
3626 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
3627 (Warning Options): Correct/edit discussion of -Warray-parameter
3628 to make the first example less confusing, and fill in missing info.
3630 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3632 PR tree-optimization/113462
3633 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
3634 Handle rhs1 INTEGER_CST like SSA_NAME.
3636 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3638 PR tree-optimization/113491
3639 * tree-switch-conversion.cc (switch_conversion::build_constructors):
3640 If elt.index has precision higher than sizetype, fold_convert it to
3642 (switch_conversion::array_value_type): Return type if type is
3643 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
3644 (switch_conversion::build_arrays): Use unsigned_type_for rather than
3645 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
3646 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
3647 higher than sizetype, use sizetype as tidx type and fold_convert the
3648 subtraction to sizetype.
3650 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3652 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
3653 (riscv_vector_mode_supported_any_target_p): Ditto.
3655 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3658 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
3659 (TARGET_ZERO_CALL_USED_REGS): Define.
3661 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3664 * config/m68k/m68k.cc (output_andsi3): Use QImode for
3665 address adjusted for 1-byte RMW access.
3666 (output_iorsi3): Likewise.
3667 (output_xorsi3): Likewise.
3669 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3671 * doc/invoke.texi (RISC-V Options): Add list of supported
3674 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3677 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
3678 (RVV_VUNDEF): Ditto.
3679 * config/riscv/riscv-vsetvl.cc: Add timevar.
3681 2024-01-19 Richard Biener <rguenther@suse.de>
3684 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
3685 an early DIE but there should be, do not pretend there is.
3687 2024-01-19 Richard Biener <rguenther@suse.de>
3689 PR tree-optimization/113494
3690 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3691 Handle endless loop on exit. Handle re-allocated PHI.
3693 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3695 PR tree-optimization/113464
3696 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
3697 optimize loads into GIMPLE_ASM stmts.
3699 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3701 PR tree-optimization/113463
3702 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
3703 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
3706 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3708 PR tree-optimization/113459
3709 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
3710 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
3711 of SCALAR_INT_TYPE_MODE if type has BLKmode.
3712 (vn_reference_lookup_3): Likewise. Formatting fix.
3714 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3715 Richard Biener <rguenther@suse.de>
3717 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
3718 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
3719 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
3720 but adjust_address also for BLKmode mode and MEM op0.
3722 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
3724 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
3727 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3729 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
3731 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3733 * common/config/riscv/riscv-common.cc
3734 (riscv_subset_list::parse_std_ext): Remove.
3735 (riscv_subset_list::parse_multiletter_ext): Remove.
3736 * config/riscv/riscv-subset.h
3737 (riscv_subset_list::parse_std_ext): Remove.
3738 (riscv_subset_list::parse_multiletter_ext): Remove.
3740 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3742 * common/config/riscv/riscv-common.cc
3743 (riscv_subset_list::parse_single_std_ext): New parameter.
3744 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3745 (riscv_subset_list::parse_single_ext): Ditto.
3746 (riscv_subset_list::parse): Relax the order for the input of ISA
3748 * config/riscv/riscv-subset.h
3749 (riscv_subset_list::parse_single_std_ext): New parameter.
3750 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3751 (riscv_subset_list::parse_single_ext): Ditto.
3753 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3755 * common/config/riscv/riscv-common.cc
3756 (riscv_subset_list::parse_base_ext): New.
3757 (riscv_subset_list::parse): Extract part of logic into
3758 riscv_subset_list::parse_base_ext.
3759 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
3762 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3764 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
3767 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
3769 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
3772 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
3775 * doc/extend.texi (Common Variable Attributes): Explain what
3776 happens when multiple variables with cleanups are in the same scope.
3778 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3781 * doc/extend.texi (Common Function Attributes): Document that
3782 noinline also disables some interprocedural optimizations and
3783 improve flow to the part about using inline asm instead to
3784 disable calls from being optimized away completely. Remove the
3785 sentence that says noipa is mainly for internal compiler testing.
3787 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
3789 PR tree-optimization/69807
3790 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
3792 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
3795 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
3796 from x86 Windows Options.
3798 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3801 * doc/extend.texi (C Extensions): Add new section to menu.
3802 (Function Attributes): Move dangling index entries to....
3803 (Const and Volatile Functions): New section.
3805 2024-01-18 David Malcolm <dmalcolm@redhat.com>
3807 PR middle-end/112684
3808 * toplev.cc (toplev::main): Don't ICE in
3809 -fdiagnostics-generate-patch when exiting after options,
3810 since no edit context will have been created.
3812 2024-01-18 Richard Biener <rguenther@suse.de>
3814 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
3817 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3819 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
3820 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
3822 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3823 Jin Ma <jinma@linux.alibaba.com>
3824 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3825 Christoph Müllner <christoph.muellner@vrull.eu>
3827 * config/riscv/thead.cc
3828 (th_asm_output_opcode): Rewrite some instructions.
3830 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3831 Jin Ma <jinma@linux.alibaba.com>
3832 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3833 Christoph Müllner <christoph.muellner@vrull.eu>
3835 * config/riscv/riscv.md (none,thv,rvv): New attribute.
3836 (no,yes): Add an attribute to disable alternative
3837 for xtheadvector or RVV1.0.
3838 * config/riscv/vector.md:
3839 Disable alternatives that destination register overlaps
3840 source register group for xtheadvector.
3842 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3843 Jin Ma <jinma@linux.alibaba.com>
3844 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3845 Christoph Müllner <christoph.muellner@vrull.eu>
3847 * config/riscv/riscv-vector-builtins-bases.cc
3848 (class th_loadstore_width): Define new builtin bases.
3849 (class th_extract): Define new builtin bases.
3850 (BASE): Define new builtin bases.
3851 * config/riscv/riscv-vector-builtins-bases.h:
3852 Define new builtin class.
3853 * config/riscv/riscv-vector-builtins-shapes.cc
3854 (struct th_loadstore_width_def): Define new builtin shapes.
3855 (struct th_indexed_loadstore_width_def):
3856 Define new builtin shapes.
3857 (struct th_extract_def): Define new builtin shapes.
3858 (SHAPE): Define new builtin shapes.
3859 * config/riscv/riscv-vector-builtins-shapes.h:
3860 Define new builtin shapes.
3861 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
3862 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
3863 * config/riscv/riscv-vector-builtins.h
3864 (enum required_ext): Add new XTheadVector member.
3865 (struct function_group_info): Likewise.
3866 * config/riscv/t-riscv:
3867 Add thead-vector-builtins-functions.def
3868 * config/riscv/thead-vector.md
3869 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
3870 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
3871 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
3872 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
3873 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
3874 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
3875 (@pred_th_extract<mode>): Likewise.
3876 (*pred_th_extract<mode>): Likewise.
3877 * config/riscv/thead-vector-builtins-functions.def: New file.
3879 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3880 Jin Ma <jinma@linux.alibaba.com>
3881 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3882 Christoph Müllner <christoph.muellner@vrull.eu>
3884 * config.gcc: Add files for XTheadVector intrinsics.
3885 * config/riscv/autovec.md: Guard XTheadVector.
3886 * config/riscv/predicates.md: Disable immediate vl
3888 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
3889 Add pragma for XTheadVector.
3890 * config/riscv/riscv-string.cc (riscv_expand_block_move):
3892 * config/riscv/riscv-v.cc (vls_mode_valid_p):
3894 * config/riscv/riscv-vector-builtins-bases.cc:
3895 Do not normalize vsetvl instructions for XTheadVector.
3896 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
3897 New check type function.
3898 (build_one): Adjust for XTheadVector.
3899 * config/riscv/riscv-vector-switch.def (ENTRY):
3900 Disable fractional mode for the XTheadVector extension.
3901 (TUPLE_ENTRY): Likewise.
3902 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
3904 (riscv_preferred_simd_mode): Likewsie.
3905 (riscv_autovectorize_vector_modes): Likewise.
3906 (riscv_vector_mode_supported_any_target_p): Likewise.
3907 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
3908 * config/riscv/thead.cc (th_asm_output_opcode):
3909 Rewrite vsetvl instructions.
3910 * config/riscv/vector.md:
3911 Include thead-vector.md and change fractional LMUL
3913 * config/riscv/riscv_th_vector.h: New file.
3914 * config/riscv/thead-vector.md: New file.
3916 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3917 Jin Ma <jinma@linux.alibaba.com>
3918 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3919 Christoph Müllner <christoph.muellner@vrull.eu>
3921 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
3922 Add new function to add assembler insn code prefix/suffix.
3923 (th_asm_output_opcode):
3924 Add Thead function to add assembler insn code prefix/suffix.
3925 * config/riscv/riscv.cc (riscv_asm_output_opcode):
3926 Implement function to add assembler insn code prefix/suffix.
3927 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
3928 Add new function to add assembler insn code prefix/suffix.
3929 * config/riscv/thead.cc (th_asm_output_opcode):
3930 Implement Thead function to add assembler insn code
3933 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3934 Jin Ma <jinma@linux.alibaba.com>
3935 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3936 Christoph Müllner <christoph.muellner@vrull.eu>
3938 * common/config/riscv/riscv-common.cc
3939 (riscv_subset_list::parse): Add new vendor extension.
3940 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
3942 * config/riscv/riscv.opt: Add new mask.
3944 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3946 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
3947 to be conditional on macosx-version-min.
3949 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3951 * config/darwin.cc (darwin_objc1_section): Use the correct
3952 meta-data version for constant strings.
3953 (machopic_select_section): Assert if we fail to handle CFString
3954 sections as Obejctive-C meta-data or drectly.
3956 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3958 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
3959 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
3960 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
3961 versions when the object format is Mach-O.
3963 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3966 * config/darwin.cc (machopic_select_section): Handle C and C++
3968 (darwin_rename_builtins): Move this out of the CFString code.
3969 (darwin_libc_has_function): Likewise.
3970 (darwin_build_constant_cfstring): Create an anonymous var to
3972 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
3975 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
3978 * haifa-sched.cc (dep_list_size): Make global.
3979 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
3980 * sched-int.h (dep_list_size): Declare.
3982 2024-01-18 Martin Jambor <mjambor@suse.cz>
3984 PR tree-optimization/110422
3985 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
3988 2024-01-18 Richard Biener <rguenther@suse.de>
3990 PR tree-optimization/113475
3991 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
3992 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
3993 (phi_analyzer::~phi_analyzer): Deallocate and free collected
3995 (phi_analyzer::process_phi): Record allocated phi_groups.
3997 2024-01-18 Richard Biener <rguenther@suse.de>
3999 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
4000 storage for gvec_oprnds elements.
4002 2024-01-18 Richard Biener <rguenther@suse.de>
4004 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
4005 prefer all later exits we can handle.
4006 (vect_analyze_loop_form): Free the allocated loop body.
4009 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4011 * config/avr/avr-log.cc: Tabify.
4013 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4015 * config/riscv/autovec.md: Support vi variant.
4017 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4019 * config/avr/avr-devices.cc: Tabify.
4021 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4023 * config/avr/avr-c.cc: Tabify.
4025 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4027 * config/avr/driver-avr.cc: Tabify.
4029 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4031 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
4033 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4035 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
4037 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4039 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
4040 minline-strcmp, minline-strncmp, minline-strlen,
4041 -param=riscv-vector-abi): Remove Bool keywords.
4043 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4046 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
4047 support. Add missing space after , in emitted assembly in some
4048 cases. Formatting fixes.
4050 2024-01-18 Xi Ruoyao <xry111@xry111.site>
4052 * config/loongarch/loongarch.md (movsi_internal): Remove
4055 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4057 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
4058 in the diagnostic, and capitalize the device name.
4059 (print_mcu): Generate specs such that:
4060 <*check_rodata_in_ram>: New.
4061 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
4062 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
4063 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
4065 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4068 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
4069 Common and Optimization.
4071 2024-01-18 Richard Biener <rguenther@suse.de>
4073 PR tree-optimization/113431
4074 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
4075 When there is an invariant load we might not preserve
4078 2024-01-18 Richard Biener <rguenther@suse.de>
4080 PR tree-optimization/113374
4081 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
4082 * tree-vect-loop.cc (move_early_exit_stmts): Update
4084 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4085 Refactor. Preserve virtual LC PHIs on all exits.
4087 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
4089 * config/loongarch/loongarch.cc (loongarch_split_symbol):
4090 Assign the '/u' attribute to the mem.
4092 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4094 PR middle-end/110847
4095 * doc/invoke.texi (Option Summary): Document negative forms of
4096 -Wtsan and -Wxor-used-as-pow.
4097 (Warning Options): Likewise.
4099 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4102 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
4104 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4106 * doc/extend.texi (Common Function Attributes): Re-alphabetize
4108 (Common Variable Attributes): Likewise.
4109 (Common Type Attributes): Likewise.
4111 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4113 PR middle-end/111659
4114 * doc/extend.texi (Common Variable Attributes): Fix long lines
4115 in documentation of strict_flex_array + other minor copy-editing.
4116 Add a cross-reference to -Wstrict-flex-arrays.
4117 * doc/invoke.texi (Option Summary): Fix whitespace in tables
4118 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
4119 (C Dialect Options): Combine the docs for the two
4120 -fstrict-flex-arrays forms into a single entry. Note this option
4121 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
4122 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
4123 Minor copy-editing. Add cross references to the strict_flex_array
4124 attribute and -fstrict-flex-arrays option. Add note that this
4125 option depends on -ftree-vrp.
4127 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
4130 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
4131 only allow REG operands instead of allowing all.
4133 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4135 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
4136 Remove redundant checks in else condition for readablity.
4137 (earliest_fuse_vsetvl_info) Print iteration count in debug
4139 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
4140 dump details in certain cases.
4142 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4144 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
4145 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
4146 * config/riscv/riscv-vsetvl.cc
4147 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
4148 (pass_vsetvl::execute): Use vsetvl_strategy.
4150 2024-01-17 Jan Hubicka <jh@suse.cz>
4152 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
4153 accidental hack reseting offset.
4155 2024-01-17 Jan Hubicka <jh@suse.cz>
4157 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
4158 handling of X86_TUNE_AVOID_512FMA_CHAINS.
4160 2024-01-17 Jan Hubicka <jh@suse.cz>
4161 Jakub Jelinek <jakub@redhat.com>
4163 PR tree-optimization/110852
4164 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
4166 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
4167 PRED_COMBINED_VALUE_PREDICTIONS_PHI
4168 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
4169 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
4171 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4173 PR tree-optimization/113421
4174 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
4176 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
4177 formatting. Start at vop rather than cvop even if stmt is a store
4178 and needs_operand_addr.
4180 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4182 PR middle-end/113410
4183 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
4184 If access_nelts is integral with larger precision than sizetype,
4185 fold_convert it to sizetype.
4187 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4189 PR tree-optimization/113408
4190 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
4191 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
4194 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4196 PR middle-end/113406
4197 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
4198 regardless of whether is_gimple_reg_type (restype) or not.
4200 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4202 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
4203 funcions -> functions, and use were instead of was.
4204 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
4205 and guaranteee -> guarantee.
4206 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
4208 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4210 PR middle-end/113409
4211 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
4213 (omp_extract_for_data): Use build_bitint_type rather than
4214 build_nonstandard_integer_type if either iter_type or loop->v type
4216 * omp-expand.cc (expand_omp_for_generic,
4217 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
4218 BITINT_TYPE like INTEGER_TYPE.
4220 2024-01-17 Richard Biener <rguenther@suse.de>
4222 PR tree-optimization/113371
4223 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
4224 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4225 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
4226 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4228 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
4230 PR rtl-optimization/96388
4231 PR rtl-optimization/111554
4232 * sched-deps.cc (find_inc): Avoid exponential behavior.
4234 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4237 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
4238 from C++ Language Options to Warning Options. Add entry for
4240 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
4242 (Warning Options): ...to here. Minor copy-editing to fix typo
4245 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
4247 * config/mips/mips.cc (mips_compute_frame_info): If another
4248 register is used as global_pointer, mark $GP live false.
4250 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4253 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
4254 give the section a light copy-editing pass.
4256 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4258 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
4259 * config/aarch64/aarch64-tune.md: Regenerated.
4260 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
4262 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4265 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
4266 badly formed CONST expressions.
4268 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4270 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
4272 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4274 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
4275 * config/sparc/sync.md (membar_storeload): Turn into named insn
4276 and add GR712RC errata workaround.
4277 (membar_v8): Add GR712RC errata workaround.
4279 2024-01-16 Andreas Larsson <andreas@gaisler.com>
4281 * config/sparc/sync.md (*membar_storeload_leon3): Remove
4282 (*membar_storeload): Enable for LEON
4284 2024-01-16 Jakub Jelinek <jakub@redhat.com>
4286 PR tree-optimization/113372
4288 PR middle-end/110115
4289 PR middle-end/111422
4290 * cfgexpand.cc (add_scope_conflicts_2): New function.
4291 (add_scope_conflicts_1): Use it.
4293 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
4295 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
4296 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
4297 * doc/avr-mmcu.texi: Regenerate.
4299 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
4301 PR tree-optimization/113091
4302 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
4303 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
4304 scalar use with new function.
4305 (vect_bb_slp_mark_live_stmts): New function as entry to existing
4306 overriden functions with same name.
4307 (vect_slp_analyze_operations): Call new entry function to mark
4310 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4313 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
4314 for RVV in big-endian mode.
4316 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
4318 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
4319 (riscv_pass_in_vector_p): Delete.
4320 (riscv_init_cumulative_args): Delete the checking.
4321 (riscv_get_arg_info): Delete the checking.
4322 (riscv_function_value): Delete the checking.
4323 * config/riscv/riscv.h: Delete the member for checking.
4325 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4327 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
4329 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4331 * config.gcc: Include riscv_bitmanip.h.
4332 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
4333 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
4334 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
4335 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
4336 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
4337 * config/riscv/riscv-ftypes.def (2): New ftypes.
4338 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
4339 (RISCV_BUILTIN_NO_PREFIX): Likewise.
4340 * config/riscv/riscv_bitmanip.h: New file.
4342 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4344 * config.gcc: Include riscv_crypto.h.
4345 * config/riscv/riscv_crypto.h: New file.
4347 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
4349 PR middle-end/113354
4350 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
4351 in the insn if the corresponding operand does not require hard
4354 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4357 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
4358 * config/avr/driver-avr.cc (avr_no_devlib): New function.
4359 (avr_devicespecs_file): Use it to remove -nodevicelib from the
4360 options for cores only.
4361 * config/avr/avr-arch.h (avr_get_parch): New prototype.
4362 * config/avr/avr-devices.cc (avr_get_parch): New function.
4364 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4367 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
4368 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
4369 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
4371 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4374 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
4375 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
4376 * config/riscv/riscv-vector-costs.h: New function.
4378 2024-01-15 Richard Biener <rguenther@suse.de>
4380 PR tree-optimization/113385
4381 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4382 First redirect, then split the exit edge.
4384 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4386 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
4387 Remove m_num_vector_iterations.
4388 * config/riscv/riscv-vector-costs.h: Ditto.
4390 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
4393 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
4394 (-mbranch-cost): Set "Optimization" flag.
4396 2024-01-15 Jakub Jelinek <jakub@redhat.com>
4398 PR tree-optimization/113370
4399 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
4400 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
4401 set it to just prec % limb_prec.
4403 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4406 * config/riscv/vector.md: Fix ternary attributes.
4408 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
4411 * configure.ac [target=avr]: Check availability of emulations
4412 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
4413 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
4414 * configure: Regenerate.
4415 * config.in: Regenerate.
4416 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
4417 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
4418 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
4419 * config/avr/avr-arch.h (enum avr_device_specific_features):
4421 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
4423 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
4424 (avr_set_core_architecture): Set avr_arch_index.
4425 (have_avrxmega2_flmap, have_avrxmega4_flmap)
4426 (have_avrxmega3_rodata_in_flash): Set new static const bool according
4427 to configure results.
4428 (avr_rodata_in_flash_p): New function using them.
4429 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
4430 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
4431 (avr_asm_named_section): Track avr_has_rodata_p.
4432 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
4433 and not avr_rodata_in_flash_p ().
4434 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
4435 (LINK_SPEC): Add %(link_rodata_in_ram).
4436 (LINK_ARCH_SPEC): Remove.
4437 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
4438 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
4439 const bool according to configure results.
4440 (diagnose_mrodata_in_ram): New function.
4441 (print_mcu): Generate specs with the following changes:
4442 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
4443 need to extend avr/specs.h each time we add a new bell or whistle.
4444 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
4445 -m[no-]rodata-in-ram.
4446 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
4447 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
4448 <*cpp>: Add %(cpp_rodata_in_ram).
4449 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
4451 <*self_spec>: Add -mflmap or %<mflmap as needed.
4453 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
4455 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
4456 not the GPR iterator. Adjust pattern name and mode attribute
4459 2024-01-13 Jakub Jelinek <jakub@redhat.com>
4461 PR tree-optimization/113361
4462 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
4463 Fix up determination of the type for > limb_prec constants.
4465 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4467 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
4468 Add web-link to the avr-gcc wiki.
4470 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4472 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
4473 documentation for a version without argument, which is not supported.
4475 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4477 * config/arm/arm_neon.h
4478 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
4479 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
4480 (vld1_f16_x4, vld1_f32_x4): New.
4481 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
4482 (vld1_bf16_x4): New.
4483 (vld1q_types_x4): Updated to use vld1q_x4
4484 from arm_neon_builtins.def
4485 * config/arm/arm_neon_builtins.def
4486 (vld1_x4): Updated entries.
4487 (vld1q_x4): New entries, but comes from the old vld1_x4
4488 * config/arm/neon.md
4489 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
4491 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4493 * config/arm/arm_neon.h
4494 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
4495 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
4496 (vld1_f16_x3, vld1_f32_x3): New.
4497 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
4498 (vld1_bf16_x3): New.
4499 (vld1q_types_x3): Updated to use vld1q_x3 from
4500 arm_neon_builtins.def
4501 * config/arm/arm_neon_builtins.def
4502 (vld1_x3): Updated entries.
4503 (vld1q_x3): New entries, but comes from the old vld1_x2
4504 * config/arm/neon.md
4505 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
4507 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4509 * config/arm/arm_neon.h
4510 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
4511 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
4512 (vld1_f16_x2, vld1_f32_x2): New.
4513 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
4514 (vld1_bf16_x2): New.
4515 (vld1q_types_x2): Updated to use vld1q_x2 from
4516 arm_neon_builtins.def
4517 * config/arm/arm_neon_builtins.def
4518 (vld1_x2): Updated entries.
4519 (vld1q_x2): New entries, but comes from the old vld1_x2
4520 * config/arm/neon.md
4521 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4524 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4526 * config/arm/arm_neon.h
4527 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
4528 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
4529 (vst1q_f16_x4, vst1q_f32_x4): New.
4530 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
4531 (vst1q_bf16_x4): New.
4532 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
4533 * config/arm/neon.md
4534 (neon_vst1q_x4<mode>): New.
4535 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
4536 * config/arm/unspecs.md
4537 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
4539 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4541 * config/arm/arm_neon.h
4542 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
4543 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
4544 (vst1q_f16_x3, vst1q_f32_x3): New.
4545 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
4546 (vst1q_bf16_x3): New.
4547 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
4548 * config/arm/neon.md
4549 (neon_vst1q_x3<mode>): New.
4550 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
4551 * config/arm/unspecs.md
4552 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
4554 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4556 * config/arm/arm_neon.h
4557 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
4558 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
4559 (vst1q_f16_x2, vst1q_f32_x2): New.
4560 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
4561 (vst1q_bf16_x2): New.
4562 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
4563 * config/arm/neon.md
4564 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4566 * config/arm/iterators.md
4567 (VMEMX2): New mode iterator.
4568 (VMEMX2_q): New mode attribute.
4570 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4572 * config/arm/arm_neon.h
4573 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
4574 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
4575 (vst1_f16_x4, vst1_f32_x4): New.
4576 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
4577 (vst1_bf16_x4): New.
4578 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
4579 * config/arm/neon.md (vst1_x4<mode>): New.
4581 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4583 * config/arm/arm_neon.h
4584 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
4585 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
4586 (vst1_f16_x3, vst1_f32_x3): New.
4587 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
4588 (vst1_bf16_x3): New.
4589 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
4590 * config/arm/neon.md (vst1_x3<mode>): New.
4592 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4594 * config/arm/arm_neon.h
4595 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
4596 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
4597 (vst1_f16_x2, vst1_f32_x2): New.
4598 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
4599 (vst1_bf16_x2): New.
4600 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
4601 * config/arm/neon.md (vst1_x2<mode>): New.
4603 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4605 * config/arm/arm_neon.h
4606 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
4607 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
4608 (vld1q_f16_x4, vld1q_f32_x4): New.
4609 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
4610 (vld1q_bf16_x4): New.
4611 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
4612 * config/arm/neon.md
4613 (neon_vld1_x4<mode>): New.
4614 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
4615 * config/arm/unspecs.md
4616 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
4618 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4620 * config/arm/arm_neon.h
4621 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
4622 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
4623 (vld1q_f16_x3, vld1q_f32_x3): New.
4624 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
4625 (vld1q_bf16_x3): New.
4626 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
4627 * config/arm/neon.md
4628 (neon_vld1_x3<mode>): New.
4629 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
4630 * config/arm/unspecs.md
4631 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
4633 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4635 * config/arm/arm_neon.h
4636 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
4637 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
4638 (vld1q_f16_x2, vld1q_f32_x2): New.
4639 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
4640 (vld1q_bf16_x2): New.
4641 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
4642 * config/arm/neon.md (vld1_x2<mode>): New.
4644 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4646 PR tree-optimization/113287
4647 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
4649 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4651 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
4652 * tree-vect-loop.cc (vect_transform_loop): Likewise.
4654 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4656 PR tree-optimization/113178
4657 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
4660 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4662 PR tree-optimization/113237
4663 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
4664 existing LCSSA variable for exit when all exits are early break.
4666 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4668 PR tree-optimization/113137
4669 PR tree-optimization/113136
4670 PR tree-optimization/113172
4671 PR tree-optimization/113178
4672 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4673 Maintain PHIs on inverted loops.
4674 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
4675 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
4677 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
4679 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4681 PR tree-optimization/113135
4682 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
4683 dependency analysis.
4685 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
4687 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
4688 diagnostics class member name for abort of error.
4690 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4692 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
4693 format string to %s argument.
4695 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
4696 Jakub Jelinek <jakub@redhat.com>
4698 PR middle-end/113182
4699 * varasm.cc (process_pending_assemble_externals,
4700 assemble_external_libcall): Use targetm.strip_name_encoding
4701 before calling get_identifier.
4703 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4706 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
4707 New member variable.
4708 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
4710 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
4711 * config/aarch64/aarch64-simd.md
4712 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
4713 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
4714 zip2 for zero-extends to...
4715 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
4716 instruction. Fix big-endian handling.
4717 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
4718 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
4719 zip1 for zero-extends to...
4720 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
4721 Fix big-endian handling.
4722 (*aarch64_zip1_uxtl): New pattern.
4723 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
4724 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
4725 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
4726 (aarch64_gen_shareable_zero): Use it.
4727 (aarch64_split_simd_shift_p): New function.
4729 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4731 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
4732 (function_beg_insn): New macro.
4733 * function.cc (expand_function_start): Initialize function_beg_insn.
4735 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4738 * config/aarch64/aarch64-sve-builtins.h
4739 (function_builder::m_overload_names): Replace with...
4740 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
4742 (add_overloaded_function): Update accordingly, using get_identifier
4743 to get a GGC-friendly record of the name.
4745 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4748 * config/aarch64/aarch64-sve-builtins.def: Don't include
4749 aarch64-sve-builtins-sme.def.
4750 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
4751 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
4752 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
4753 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
4754 requires AARCH64_FL_SME2.
4755 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
4756 AARCH64_FL_SME adjustment here.
4757 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
4758 include SME intrinsics.
4759 (sme_function_groups): New array.
4760 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
4761 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
4763 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4766 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
4767 (struct cpu_vector_cost): Add regmove struct.
4768 (get_vector_costs): Export as global.
4769 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
4770 (costs::add_stmt_cost): Ditto.
4771 * config/riscv/riscv.cc (get_common_costs): Export global function.
4773 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4775 PR tree-optimization/113334
4776 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
4777 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
4778 to determine if number should be extended by all ones rather than zero
4781 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4783 PR tree-optimization/113330
4784 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
4787 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4789 PR tree-optimization/113323
4790 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
4791 check for lhs being large/huge _BitInt not in m_names.
4793 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4795 PR tree-optimization/113316
4796 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
4797 uninitialized large/huge _BitInt arguments to calls.
4799 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4801 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
4802 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
4803 CEIL (TYPE_PRECISION (t), limb_prec).
4804 (bitint_large_huge::handle_cast): Likewise.
4806 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
4809 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
4810 Use assemble_function_label_final () for Power ELF V1 ABI.
4811 * output.h (assemble_function_label_final): New function.
4812 * varasm.cc (assemble_function_label_raw): Use
4813 assemble_function_label_final ().
4814 (assemble_function_label_final): New function.
4816 2024-01-12 Richard Biener <rguenther@suse.de>
4818 PR middle-end/113344
4819 * match.pd ((double)float CMP (double)float -> float CMP float):
4820 Perform result type check only for vectors.
4821 * fold-const.cc (fold_binary_loc): Likewise.
4823 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4825 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
4826 (usdot_prod<mode>): Ditto.
4827 (sdot_prod<mode>): Ditto.
4828 (udot_prod<mode>): Ditto.
4830 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4833 * config/i386/i386-c.cc (ix86_target_macros_internal):
4834 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
4836 2024-01-12 Richard Biener <rguenther@suse.de>
4839 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
4840 Do not generate code when d.testing_p.
4842 2024-01-12 liuhongt <hongtao.liu@intel.com>
4845 * doc/invoke.texi (fcf-protection=): Update documents.
4847 2024-01-12 Pan Li <pan2.li@intel.com>
4849 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
4850 comments of predicate func riscv_v_ext_mode_p.
4852 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
4854 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
4855 Modify ABI-name length of vfloat16m8_t
4857 2024-01-12 Li Wei <liwei@loongson.cn>
4859 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
4862 2024-01-12 Li Wei <liwei@loongson.cn>
4864 * config/loongarch/loongarch.md (add<mode>3): Removed.
4868 (*addsi3_extended): Removed.
4869 (addsi3_extended): New.
4871 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
4873 * config/riscv/thead.md: Add limits for splits.
4875 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4877 PR middle-end/113322
4878 * expr.cc (do_store_flag): Don't try single bit tests with
4879 comparison on vector types.
4881 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4883 PR tree-optimization/113301
4884 * match.pd (`1/x`): Delay signed case until late.
4886 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4888 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
4890 (AVR Internal Options): ...this new @subsubsection.
4892 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
4894 PR rtl-optimization/112918
4895 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
4896 (in_class_p): Restrict condition for narrowing class in case of
4897 allow_all_reload_class_changes_p.
4898 (process_alt_operands): Try to match operand without and with
4899 narrowing reg class. Discourage narrowing the class. Finish insn
4900 matching only if there is no class narrowing.
4901 (curr_insn_transform): Pass true to in_class_p for reg operand win.
4903 2024-01-11 Richard Biener <rguenther@suse.de>
4905 PR tree-optimization/112505
4906 * tree-vect-loop.cc (vectorizable_induction): Reject
4907 bit-precision induction.
4909 2024-01-11 Richard Biener <rguenther@suse.de>
4911 PR tree-optimization/113126
4912 * match.pd ((double)float CMP (double)float -> float CMP float):
4913 Make sure the boolean type is the same.
4914 * fold-const.cc (fold_binary_loc): Likewise.
4916 2024-01-11 Richard Biener <rguenther@suse.de>
4918 PR tree-optimization/112636
4919 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
4920 estimate_numbers_of_iterations before querying
4921 get_max_loop_iterations_int.
4922 (pass_ch::execute): Initialize SCEV and loops appropriately.
4924 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4926 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
4928 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
4929 * doc/extend.texi (AVR Variable Attributes): Improve documentation
4930 of io, io_low and address attributes.
4931 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
4932 * doc/avr-mmcu.texi: Rebuild.
4934 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
4937 * config/loongarch/genopts/loongarch.opt.in: Mark options with
4938 the "Save" property.
4939 * config/loongarch/loongarch.opt: Same.
4940 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
4941 according to la_target.
4942 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
4943 RESTORE} for the la_target structure; Rename option conditions
4944 to have the same "la_" prefix.
4945 * config/loongarch/loongarch.h: Same.
4947 2024-01-11 Pan Li <pan2.li@intel.com>
4949 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
4950 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
4952 2024-01-11 Alex Coplan <alex.coplan@arm.com>
4955 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
4956 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
4957 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
4958 synthesize these if needed. Update caller ...
4959 (ldp_bb_info::fuse_pair): ... here.
4960 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
4961 and either insn is frame-related.
4962 (find_trailing_add): Punt on frame-related insns.
4963 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
4964 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
4966 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
4968 * config/mips/mips.cc (mips_start_function_definition):
4969 Add ATTRIBUTE_UNUSED.
4971 2024-01-11 Richard Biener <rguenther@suse.de>
4973 PR middle-end/112740
4974 * expr.cc (store_constructor): Check the integer vector
4975 mask has a single bit per element before using sign-extension
4976 to expand an uniform vector.
4978 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4980 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
4981 preempt VLS on unknown NITERS loop.
4983 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
4985 * doc/invoke.texi: Add -mevex512.
4987 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
4989 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
4990 (*nor<mode>3): Likewise.
4991 (nor<mode>3): Likewise.
4992 (*negsi2_extended): New template.
4993 (*<optab>si3_internal): Likewise.
4994 (*one_cmplsi2_internal): Likewise.
4995 (*norsi3_internal): Likewise.
4996 (*<optab>nsi_internal): Likewise.
4997 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
4998 modified bit operation to make the optimization work.
5000 2024-01-11 liuhongt <hongtao.liu@intel.com>
5003 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
5005 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5007 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
5008 (get_vector_costs): Ditto.
5009 (riscv_builtin_vectorization_cost): Ditto.
5011 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5013 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
5015 2024-01-10 Antoni Boucher <bouanto@zoho.com>
5018 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
5019 ipa_free_size_summary.
5020 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
5021 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
5022 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
5023 * ipa-prop.h (ipa_prop_cc_finalize): New function.
5024 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
5025 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
5026 ipa_sra_cc_finalize): New functions.
5027 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
5028 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
5030 Include ipa-utils.h.
5032 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
5034 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
5035 (th_int_get_save_adjustment): Likewise.
5036 (th_int_adjust_cfi_prologue): Likewise.
5037 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
5038 (TH_INT_INTERRUPT): New macro.
5039 (riscv_expand_prologue): Add the processing of XTheadInt.
5040 (riscv_expand_epilogue): Likewise.
5041 * config/riscv/riscv.h (BITSET_P): Moved to here.
5042 * config/riscv/riscv.md: New unspec.
5043 * config/riscv/thead.cc (th_int_get_mask): New function.
5044 (th_int_get_save_adjustment): Likewise.
5045 (th_int_adjust_cfi_prologue): Likewise.
5046 * config/riscv/thead.md (th_int_push): New pattern.
5047 (th_int_pop): new pattern.
5049 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5051 PR tree-optimization/112468
5052 * doc/sourcebuild.texi: Document ifn_copysign.
5053 * match.pd: Only apply transformation if target supports the IFN.
5055 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
5057 PR tree-optimization/112581
5058 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
5059 mark_ssa_maybe_undefs.
5060 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
5061 variables can not be reassociated.
5062 (init_range_entry): Check for uninitialized variables too.
5063 (init_reassoc): Call mark_ssa_maybe_undefs.
5065 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
5067 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
5068 Also handle sign extension.
5070 2024-01-10 Alex Coplan <alex.coplan@arm.com>
5072 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
5074 (-mlate-ldp-fusion): Likewise.
5076 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5078 PR tree-optimization/113287
5079 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
5080 instead of using BRANCH_EDGE to determine true edge.
5082 2024-01-10 Richard Biener <rguenther@suse.de>
5084 PR tree-optimization/113078
5085 * tree-vect-loop.cc (check_reduction_path): Canonicalize
5086 .COND_SUB to .COND_ADD.
5088 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5090 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
5091 Handle prefix mappings before calling find_opt.
5092 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
5093 "-fno-"-prefixed command-line option.
5094 * opts-common.cc (get_option_prefix_remapping): New.
5095 * opts.h (get_option_prefix_remapping): New decl.
5097 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5099 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
5100 m_urlifier to pp_output_formatted_text.
5101 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
5102 (obstack_append_string): New overload, taking a length.
5103 (urlify_quoted_string): Pass in an obstack ptr, rather than using
5104 that of the pp's buffer. Generalize to handle trailing text in
5105 the buffer beyond the run of quoted text.
5106 (class quoting_info): New.
5107 (on_begin_quote): New.
5108 (on_end_quote): New.
5109 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
5110 it to calls to on_begin_quote and on_end_quote.
5111 (struct auto_obstack): New.
5112 (quoting_info::handle_phase_3): New.
5113 (pp_output_formatted_text): Add urlifier param. Use it if there
5114 is deferred urlification. Delete m_quotes.
5115 (selftest::pp_printf_with_urlifier): Pass urlifier to
5116 pp_output_formatted_text.
5117 (selftest::test_urlification): Update results for the existing
5118 case of quoted text stradding chunks; add more such test cases.
5119 * pretty-print.h (class quoting_info): New forward decl.
5120 (chunk_info::m_quotes): New field.
5121 (pp_output_formatted_text): Add optional urlifier param.
5123 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5125 * pretty-print.cc (selftest::test_pp_format): Add selftest
5126 coverage for numbered args.
5128 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5130 PR tree-optimization/113144
5131 PR tree-optimization/113145
5132 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5133 Update all BB that the original exits dominated.
5135 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
5137 * dwarf2out.cc (modified_type_die): Extend the support of reverse
5138 storage order to enumeration types if -gstrict-dwarf is not passed.
5139 (gen_enumeration_type_die): Add REVERSE parameter and generate the
5140 DIE immediately after the existing one if it is true.
5141 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
5142 call to gen_enumeration_type_die.
5143 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
5144 first recursive call as well as the call to gen_tagged_type_die.
5145 (gen_type_die): Add REVERSE parameter and pass it in the call to
5146 gen_type_die_with_usage.
5148 2024-01-10 Jakub Jelinek <jakub@redhat.com>
5150 PR tree-optimization/113120
5151 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
5152 with root->size TYPE_PRECISION don't build anything new.
5153 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
5154 rather than build_nonstandard_integer_type.
5156 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
5158 * config/i386/i386.opt: Adjust document.
5159 * doc/invoke.texi: Add description for
5160 -mapx-inline-asm-use-gpr32.
5162 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5164 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
5165 (avg<v_double_trunc>3_floor): New pattern.
5166 (<u>avg<v_double_trunc>3_ceil): Remove.
5167 (avg<v_double_trunc>3_ceil): New pattern.
5168 (uavg<mode>3_floor): Ditto.
5169 (uavg<mode>3_ceil): Ditto.
5170 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
5171 (enum insn_type): Ditto.
5172 * config/riscv/riscv-v.cc: Ditto.
5173 * config/riscv/vector-iterators.md (ashiftrt): Remove.
5175 * config/riscv/vector.md: Add VLS modes.
5177 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5180 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
5181 (vczlsbb_char): New int attribute.
5182 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
5183 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
5184 (*vctzlsbb_zext_<mode>): Rename to ...
5185 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
5188 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5191 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
5192 of the last argument from altivec_register_operand to any_operand. If
5193 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
5194 otherwise if it doesn't satisfy altivec_register_operand, force it to
5195 REG using copy_to_mode_reg.
5197 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5199 PR middle-end/113100
5200 * builtins.cc (expand_builtin_stack_address): Guard stack point
5201 adjustment with SPARC_STACK_BOUNDARY_HACK.
5203 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5205 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
5206 argument string definitions.
5207 * config/loongarch/loongarch-str.h: Same.
5208 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
5209 as aliases to -mexplicit-relocs={always,none}
5210 * config/loongarch/loongarch.opt: Regenerate.
5211 * config/loongarch/loongarch.cc: Same.
5213 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5215 * config/loongarch/loongarch-def.h: Define constants with
5216 enums instead of Macros.
5218 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5220 * config/loongarch/genopts/loongarch-strings: Rename.
5221 * config/loongarch/genopts/loongarch.opt.in: Same.
5222 * config/loongarch/loongarch-cpu.cc: Same.
5223 * config/loongarch/loongarch-def.cc: Same.
5224 * config/loongarch/loongarch-def.h: Same.
5225 * config/loongarch/loongarch-opts.cc: Same.
5226 * config/loongarch/loongarch-opts.h: Same.
5227 * config/loongarch/loongarch-str.h: Same.
5228 * config/loongarch/loongarch.opt: Same.
5230 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5232 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
5233 variable with the common la_ prefix.
5234 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
5235 flags as saved using TargetVariable.
5236 * config/loongarch/loongarch.opt: Same.
5237 * config/loongarch/loongarch-def.h: Define evolution_set to
5238 mark changes to the -march default.
5239 * config/loongarch/loongarch-driver.cc: Same.
5240 * config/loongarch/loongarch-opts.cc: Same.
5241 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
5242 conditions around the la_target structure.
5243 * config/loongarch/loongarch.cc: Same.
5244 * config/loongarch/loongarch.md: Same.
5245 * config/loongarch/loongarch-builtins.cc: Same.
5246 * config/loongarch/loongarch-c.cc: Same.
5247 * config/loongarch/lasx.md: Same.
5248 * config/loongarch/lsx.md: Same.
5249 * config/loongarch/sync.md: Same.
5251 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
5253 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
5256 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
5258 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
5260 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5262 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
5264 (vectorizable_live_operation): Likewise.
5266 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5268 PR tree-optimization/113199
5269 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
5272 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5275 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
5276 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
5277 GTY(()) declaration before the definition, drop GTY(()) drom the
5280 2024-01-09 Richard Biener <rguenther@suse.de>
5282 PR tree-optimization/113026
5283 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
5284 redundant and wrong niter bound setting. Move niter
5285 bound adjustment down.
5287 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5289 PR middle-end/113163
5290 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
5291 Reject non-linear inductions that aren't supported.
5293 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5295 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
5296 left shift implementation strategies.
5297 (arc_shift_info): Type for each entry of the shift strategy table.
5298 (arc_shift_context_idx): Return a integer value for each code
5299 generation context, used as an index
5300 (arc_ashl_alg): Table indexed by context and shifted bit count.
5301 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
5302 left shift implementation.
5303 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
5304 provide accurate costs, when optimizing for speed or size.
5306 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5308 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
5310 2024-01-09 Julian Brown <julian@codesourcery.com>
5312 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
5313 processed out before gimplification.
5314 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
5315 * tree.def (OMP_ARRAY_SECTION): New tree code.
5317 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5319 PR tree-optimization/113210
5320 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
5321 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
5322 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
5325 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
5327 PR rtl-optimization/113140
5328 * reorg.cc (fill_slots_from_thread): If we are to branch after the
5329 last instruction of the function, create an end label.
5331 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5332 Hongtao Liu <hongtao.liu@intel.com>
5335 * config/i386/i386-expand.cc
5336 (ix86_convert_const_wide_int_to_broadcast): Allow call to
5337 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
5338 (ix86_broadcast_from_constant): Revert recent change; Return a
5339 suitable MEMREF independently of mode/target combinations.
5340 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
5341 to decide whether expansion is possible/preferrable. Only try
5342 forcing DImode constants to memory (and trying again) if calling
5343 ix86_expand_vector_init_duplicate fails with an DImode immediate
5345 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
5346 V4SImode for suitable immediate constants.
5347 <case E_V4DImode>: Try using V8SImode for suitable constants.
5348 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
5349 <case E_V2HImode>: Likewise.
5350 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
5351 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
5352 <label widen>: Handle CONT_INTs via simplify_binary_operation.
5353 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
5354 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
5355 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
5356 (ix86_expand_vector_init): Move try using a broadcast for all_same
5357 with ix86_expand_vector_init_duplicate before using constant pool.
5359 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5361 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
5363 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5365 * config/arm/arm-cpus.in (cortex-m52): New cpu.
5366 * config/arm/arm-tables.opt: Regenerate.
5367 * config/arm/arm-tune.md: Regenerate.
5369 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
5371 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
5372 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
5373 (@vec_concatz<mode>): New insn pattern.
5374 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
5375 Handle VALS containing two vectors.
5377 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5379 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
5380 (vundefined): Ditto.
5382 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
5384 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5385 Add new function_base for crypto vector.
5386 (class bitmanip): Ditto.
5387 (class b_reverse):Ditto.
5388 (class vwsll): Ditto.
5389 (class clmul): Ditto.
5390 (class vg_nhab): Ditto.
5391 (class crypto_vv):Ditto.
5392 (class crypto_vi):Ditto.
5393 (class vaeskf2_vsm3c):Ditto.
5394 (class vsm3me): Ditto.
5395 (BASE): Add BASE declaration for crypto vector.
5396 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5397 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5398 Add crypto vector intrinsic definition.
5426 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5427 Add new function_shape for crypto vector.
5428 (struct crypto_vi_def): Ditto.
5429 (struct crypto_vv_no_op_type_def): Ditto.
5430 (SHAPE): Add SHAPE declaration of crypto vector.
5431 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5432 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5433 Add new data type for crypto vector.
5434 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5435 (vuint32mf2_t): Ditto.
5436 (vuint32m1_t): Ditto.
5437 (vuint32m2_t): Ditto.
5438 (vuint32m4_t): Ditto.
5439 (vuint32m8_t): Ditto.
5440 (vuint64m1_t): Ditto.
5441 (vuint64m2_t): Ditto.
5442 (vuint64m4_t): Ditto.
5443 (vuint64m8_t): Ditto.
5444 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5445 Add new data struct for crypto vector.
5446 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5447 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5448 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5450 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
5453 * varasm.cc (assemble_function_label_raw): Do not call
5454 asan_function_start () without the current function.
5456 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
5459 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
5460 extern and kernel_helper attributed function decls.
5462 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
5464 * btfout.cc (output_btf_strs): Changed.
5466 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
5468 * config/gcn/mkoffload.cc (main): Handle gfx1100
5469 when setting the default XNACK.
5471 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
5473 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
5474 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
5475 (ASM_SPEC): Handle gfx1100.
5476 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
5477 (enum gcn_isa): Add ISA_RDNA3.
5478 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
5479 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5480 * config/gcn/gcn.cc (gcn_option_override,
5481 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
5482 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
5483 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5484 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
5486 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
5487 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
5489 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5490 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
5491 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
5492 (isa_has_combined_avgprs, main): Handle gfx1100.
5493 * config/gcn/t-omp-device (isa): Add gfx1100.
5495 2024-01-08 Richard Biener <rguenther@suse.de>
5497 * doc/invoke.texi (-mmovbe): Clarify.
5499 2024-01-08 Richard Biener <rguenther@suse.de>
5501 PR tree-optimization/113026
5502 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
5503 Avoid an epilog in more cases.
5504 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
5505 epilogues niter upper bounds and estimates.
5507 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5509 PR tree-optimization/113228
5510 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
5512 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5514 PR tree-optimization/113120
5515 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
5516 large _BitInt zero INTEGER_CST PHI argument.
5518 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5520 PR tree-optimization/113119
5521 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
5522 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
5523 is before REALPART_EXPR.
5525 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
5528 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
5529 range when diagnosing attribute "io" and "io_low" are out of range.
5530 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
5531 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
5532 in contexts other than static storage.
5533 (avr_asm_output_aligned_decl_common): Move output of decls with
5534 attribute "address", "io", and "io_low" to...
5535 (avr_output_addr_attrib): ...this new function.
5536 (avr_asm_asm_output_aligned_bss): Remove output for decls with
5537 attribute "address", "io", and "io_low".
5538 (avr_encode_section_info): Rectify handling of decls with attribute
5539 "address", "io", and "io_low".
5541 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
5543 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
5544 (elf_flags): Remove XNACK from the default value.
5545 (main): Set a default XNACK according to the arch.
5547 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
5549 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
5550 (process_asm): Don't count avgprs.
5552 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
5554 * config/i386/i386.opt: Add supported sub-features.
5555 * doc/extend.texi: Add description for target attribute.
5557 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
5559 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
5561 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
5562 Uros Bizjak <ubizjak@gmail.com>
5565 * config/i386/i386-features.cc (compute_convert_gain): Include
5566 the overhead of explicit load and store (movd) instructions when
5567 converting non-store scalar operations with memory destinations.
5568 Various indentation whitespace fixes.
5570 2024-01-07 Tamar Christina <tamar.christina@arm.com>
5572 * config/arm/neon.md (cbranch<mode>4): New.
5574 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5576 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
5578 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
5580 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
5582 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5585 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
5588 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5590 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
5591 (variable_vectorized_p): Teach loop invariant.
5592 (has_unexpected_spills_p): Ditto.
5594 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5596 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
5597 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
5598 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
5600 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
5603 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
5604 (aarch64-vect-compare-costs): ...this.
5605 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
5607 (-param=aarch64-vect-compare-costs=): ...this new param.
5608 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
5609 Don't disable it when vectorizing for Advanced SIMD only.
5610 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
5611 whenever aarch64_vect_compare_costs is true.
5613 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
5615 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
5616 Modify the method of determining the memory offset of [x]vld/[x]vst.
5617 (lasx_mxst_<lasxfmt_f>): Likewise.
5618 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
5619 (loongarch_address_insns): Likewise.
5620 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
5621 (lsx_st_<lsxfmt_f>): Likewise.
5622 * config/loongarch/predicates.md (aq10b_operand): Likewise.
5623 (aq10h_operand): Likewise.
5624 (aq10w_operand): Likewise.
5625 (aq10d_operand): Likewise.
5627 2024-01-05 Alex Coplan <alex.coplan@arm.com>
5630 * config/aarch64/aarch64-ldp-fusion.cc
5631 (ldp_bb_info::try_fuse_pair): If the second access can throw,
5632 narrow the move range to exactly that insn.
5634 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5636 * asan.cc (asan_function_start): Drop switch_to_section ().
5637 (asan_emit_stack_protection): Set .LASANPC alignment.
5638 * config/i386/i386.cc: Use assemble_function_label_raw ()
5639 instead of ASM_OUTPUT_LABEL ().
5640 * config/s390/s390.cc (s390_asm_output_function_label):
5642 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
5643 * final.cc (final_start_function_1): Drop
5644 asan_function_start ().
5645 * output.h (assemble_function_label_raw): New function.
5646 * varasm.cc (assemble_function_label_raw): Likewise.
5648 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5650 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
5651 Use ASM_OUTPUT_FUNCTION_LABEL ().
5652 * config/alpha/alpha.cc (alpha_start_function): Likewise.
5653 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5654 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
5655 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5656 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5657 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
5658 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5659 * config/ia64/ia64.cc (ia64_start_function): Likewise.
5660 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
5662 * config/microblaze/microblaze.cc (microblaze_function_prologue):
5664 * config/mips/mips.cc (mips_start_unique_function): Return the
5666 (mips_start_function_definition): Use
5667 ASM_OUTPUT_FUNCTION_LABEL ().
5668 (mips_finish_stub): Pass the tree to
5669 mips_start_function_definition ().
5670 (mips16_build_function_stub): Likewise.
5671 (mips16_build_call_stub): Likewise.
5672 (mips_output_function_prologue): Likewise.
5673 * config/pa/pa.cc (pa_output_function_label): Use
5674 ASM_OUTPUT_FUNCTION_LABEL ().
5675 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
5676 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5678 (rs6000_xcoff_declare_function_name): Likewise.
5680 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5682 PR tree-optimization/113201
5683 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
5684 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
5686 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5688 PR tree-optimization/90693
5689 * tree-ssa-math-opts.cc (match_single_bit_test): If
5690 tree_expr_nonzero_p (arg), remember it in the second argument to
5691 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
5692 arg ^ (arg - 1) > arg - 1.
5693 * internal-fn.cc (expand_POPCOUNT): If second argument to
5694 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
5695 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
5697 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
5699 * config/riscv/riscv-v.cc (expand_load_store):
5701 (expand_cond_len_op): Ditto.
5702 (expand_gather_scatter): Ditto.
5703 (expand_lanes_load_store): Ditto.
5704 (expand_fold_extract_last): Ditto.
5706 2024-01-05 Pan Li <pan2.li@intel.com>
5709 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5711 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5712 Add new function_base for crypto vector.
5713 (class bitmanip): Ditto.
5714 (class b_reverse):Ditto.
5715 (class vwsll): Ditto.
5716 (class clmul): Ditto.
5717 (class vg_nhab): Ditto.
5718 (class crypto_vv):Ditto.
5719 (class crypto_vi):Ditto.
5720 (class vaeskf2_vsm3c):Ditto.
5721 (class vsm3me): Ditto.
5722 (BASE): Add BASE declaration for crypto vector.
5723 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5724 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5725 Add crypto vector intrinsic definition.
5753 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5754 Add new function_shape for crypto vector.
5755 (struct crypto_vi_def): Ditto.
5756 (struct crypto_vv_no_op_type_def): Ditto.
5757 (SHAPE): Add SHAPE declaration of crypto vector.
5758 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5759 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5760 Add new data type for crypto vector.
5761 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5762 (vuint32mf2_t): Ditto.
5763 (vuint32m1_t): Ditto.
5764 (vuint32m2_t): Ditto.
5765 (vuint32m4_t): Ditto.
5766 (vuint32m8_t): Ditto.
5767 (vuint64m1_t): Ditto.
5768 (vuint64m2_t): Ditto.
5769 (vuint64m4_t): Ditto.
5770 (vuint64m8_t): Ditto.
5771 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5772 Add new data struct for crypto vector.
5773 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5774 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5775 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5777 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5779 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5780 Add new function_base for crypto vector.
5781 (class bitmanip): Ditto.
5782 (class b_reverse):Ditto.
5783 (class vwsll): Ditto.
5784 (class clmul): Ditto.
5785 (class vg_nhab): Ditto.
5786 (class crypto_vv):Ditto.
5787 (class crypto_vi):Ditto.
5788 (class vaeskf2_vsm3c):Ditto.
5789 (class vsm3me): Ditto.
5790 (BASE): Add BASE declaration for crypto vector.
5791 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5792 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5793 Add crypto vector intrinsic definition.
5821 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5822 Add new function_shape for crypto vector.
5823 (struct crypto_vi_def): Ditto.
5824 (struct crypto_vv_no_op_type_def): Ditto.
5825 (SHAPE): Add SHAPE declaration of crypto vector.
5826 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5827 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5828 Add new data type for crypto vector.
5829 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5830 (vuint32mf2_t): Ditto.
5831 (vuint32m1_t): Ditto.
5832 (vuint32m2_t): Ditto.
5833 (vuint32m4_t): Ditto.
5834 (vuint32m8_t): Ditto.
5835 (vuint64m1_t): Ditto.
5836 (vuint64m2_t): Ditto.
5837 (vuint64m4_t): Ditto.
5838 (vuint64m8_t): Ditto.
5839 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5840 Add new data struct for crypto vector.
5841 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5842 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5843 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5845 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5847 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5849 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
5851 PR tree-optimization/113186
5852 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
5853 Match `^` with the `==` for 1bit integral types.
5854 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
5857 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5859 * toplev.cc (general_init): Pass lang_mask to urlifier.
5861 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5863 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
5865 (diagnostic_context::make_option_url): Update for lang_mask param.
5866 * gcc-urlifier.cc: Include "opts.h" and "options.h".
5867 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
5868 (gcc_urlifier::m_lang_mask): New field.
5869 (doc_urls): Make static.
5870 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
5871 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5872 Look for an option by name before trying a binary search in
5874 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5875 (gcc_urlifier::get_url_suffix_for_option): New.
5876 (make_gcc_urlifier): Add lang_mask param.
5877 (selftest::gcc_urlifier_cc_tests): Update for above changes.
5878 Verify that a URL is found for "-fpack-struct".
5879 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
5880 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
5881 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
5882 to make_gcc_urlifier.
5883 * opts-diagnostic.h (get_option_url): Add lang_mask param.
5884 * opts.cc (get_option_html_page): Remove special-casing for
5886 (get_option_url_suffix): New.
5887 (get_option_url): Reimplement.
5888 (selftest::test_get_option_html_page): Rename to...
5889 (selftest::test_get_option_url_suffix): ...this and update for
5891 (selftest::opts_cc_tests): Update for renaming.
5892 * opts.h: Include "rich-location.h".
5893 (get_option_url_suffix): New decl.
5895 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5897 * Makefile.in (ALL_OPT_URL_FILES): New.
5898 (GCC_OBJS): Add options-urls.o.
5900 (OBJS-libcommon): Likewise.
5901 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
5902 inputs to opt-gather.awk.
5903 (options-urls.cc): New Makefile target.
5904 * opt-functions.awk (url_suffix): New function.
5905 (lang_url_suffix): New function.
5906 * options-urls-cc-gen.awk: New file.
5907 * opts.h (get_opt_url_suffix): New decl.
5909 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5911 * params.opt.urls: New file, autogenerated by
5912 regenerate-opt-urls.py.
5914 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5916 * common.opt.urls: New file, autogenerated by
5917 regenerate-opt-urls.py.
5918 * config/aarch64/aarch64.opt.urls: Likewise.
5919 * config/alpha/alpha.opt.urls: Likewise.
5920 * config/alpha/elf.opt.urls: Likewise.
5921 * config/arc/arc-tables.opt.urls: Likewise.
5922 * config/arc/arc.opt.urls: Likewise.
5923 * config/arm/arm-tables.opt.urls: Likewise.
5924 * config/arm/arm.opt.urls: Likewise.
5925 * config/arm/vxworks.opt.urls: Likewise.
5926 * config/avr/avr.opt.urls: Likewise.
5927 * config/bpf/bpf.opt.urls: Likewise.
5928 * config/c6x/c6x-tables.opt.urls: Likewise.
5929 * config/c6x/c6x.opt.urls: Likewise.
5930 * config/cris/cris.opt.urls: Likewise.
5931 * config/cris/elf.opt.urls: Likewise.
5932 * config/csky/csky.opt.urls: Likewise.
5933 * config/csky/csky_tables.opt.urls: Likewise.
5934 * config/darwin.opt.urls: Likewise.
5935 * config/dragonfly.opt.urls: Likewise.
5936 * config/epiphany/epiphany.opt.urls: Likewise.
5937 * config/fr30/fr30.opt.urls: Likewise.
5938 * config/freebsd.opt.urls: Likewise.
5939 * config/frv/frv.opt.urls: Likewise.
5940 * config/ft32/ft32.opt.urls: Likewise.
5941 * config/fused-madd.opt.urls: Likewise.
5942 * config/g.opt.urls: Likewise.
5943 * config/gcn/gcn.opt.urls: Likewise.
5944 * config/gnu-user.opt.urls: Likewise.
5945 * config/h8300/h8300.opt.urls: Likewise.
5946 * config/hpux11.opt.urls: Likewise.
5947 * config/i386/cygming.opt.urls: Likewise.
5948 * config/i386/cygwin.opt.urls: Likewise.
5949 * config/i386/djgpp.opt.urls: Likewise.
5950 * config/i386/i386.opt.urls: Likewise.
5951 * config/i386/mingw-w64.opt.urls: Likewise.
5952 * config/i386/mingw.opt.urls: Likewise.
5953 * config/i386/nto.opt.urls: Likewise.
5954 * config/ia64/ia64.opt.urls: Likewise.
5955 * config/ia64/ilp32.opt.urls: Likewise.
5956 * config/ia64/vms.opt.urls: Likewise.
5957 * config/iq2000/iq2000.opt.urls: Likewise.
5958 * config/linux-android.opt.urls: Likewise.
5959 * config/linux.opt.urls: Likewise.
5960 * config/lm32/lm32.opt.urls: Likewise.
5961 * config/loongarch/loongarch.opt.urls: Likewise.
5962 * config/lynx.opt.urls: Likewise.
5963 * config/m32c/m32c.opt.urls: Likewise.
5964 * config/m32r/m32r.opt.urls: Likewise.
5965 * config/m68k/ieee.opt.urls: Likewise.
5966 * config/m68k/m68k-tables.opt.urls: Likewise.
5967 * config/m68k/m68k.opt.urls: Likewise.
5968 * config/m68k/uclinux.opt.urls: Likewise.
5969 * config/mcore/mcore.opt.urls: Likewise.
5970 * config/microblaze/microblaze.opt.urls: Likewise.
5971 * config/mips/mips-tables.opt.urls: Likewise.
5972 * config/mips/mips.opt.urls: Likewise.
5973 * config/mips/sde.opt.urls: Likewise.
5974 * config/mmix/mmix.opt.urls: Likewise.
5975 * config/mn10300/mn10300.opt.urls: Likewise.
5976 * config/moxie/moxie.opt.urls: Likewise.
5977 * config/msp430/msp430.opt.urls: Likewise.
5978 * config/nds32/nds32-elf.opt.urls: Likewise.
5979 * config/nds32/nds32-linux.opt.urls: Likewise.
5980 * config/nds32/nds32.opt.urls: Likewise.
5981 * config/netbsd-elf.opt.urls: Likewise.
5982 * config/netbsd.opt.urls: Likewise.
5983 * config/nios2/elf.opt.urls: Likewise.
5984 * config/nios2/nios2.opt.urls: Likewise.
5985 * config/nvptx/nvptx-gen.opt.urls: Likewise.
5986 * config/nvptx/nvptx.opt.urls: Likewise.
5987 * config/openbsd.opt.urls: Likewise.
5988 * config/or1k/elf.opt.urls: Likewise.
5989 * config/or1k/or1k.opt.urls: Likewise.
5990 * config/pa/pa-hpux.opt.urls: Likewise.
5991 * config/pa/pa-hpux1010.opt.urls: Likewise.
5992 * config/pa/pa-hpux1111.opt.urls: Likewise.
5993 * config/pa/pa-hpux1131.opt.urls: Likewise.
5994 * config/pa/pa.opt.urls: Likewise.
5995 * config/pa/pa64-hpux.opt.urls: Likewise.
5996 * config/pdp11/pdp11.opt.urls: Likewise.
5997 * config/pru/pru.opt.urls: Likewise.
5998 * config/riscv/riscv.opt.urls: Likewise.
5999 * config/rl78/rl78.opt.urls: Likewise.
6000 * config/rpath.opt.urls: Likewise.
6001 * config/rs6000/476.opt.urls: Likewise.
6002 * config/rs6000/aix64.opt.urls: Likewise.
6003 * config/rs6000/darwin.opt.urls: Likewise.
6004 * config/rs6000/linux64.opt.urls: Likewise.
6005 * config/rs6000/rs6000-tables.opt.urls: Likewise.
6006 * config/rs6000/rs6000.opt.urls: Likewise.
6007 * config/rs6000/sysv4.opt.urls: Likewise.
6008 * config/rtems.opt.urls: Likewise.
6009 * config/rx/elf.opt.urls: Likewise.
6010 * config/rx/rx.opt.urls: Likewise.
6011 * config/s390/s390.opt.urls: Likewise.
6012 * config/s390/tpf.opt.urls: Likewise.
6013 * config/sh/sh.opt.urls: Likewise.
6014 * config/sh/superh.opt.urls: Likewise.
6015 * config/sol2.opt.urls: Likewise.
6016 * config/sparc/long-double-switch.opt.urls: Likewise.
6017 * config/sparc/sparc.opt.urls: Likewise.
6018 * config/stormy16/stormy16.opt.urls: Likewise.
6019 * config/v850/v850.opt.urls: Likewise.
6020 * config/vax/elf.opt.urls: Likewise.
6021 * config/vax/vax.opt.urls: Likewise.
6022 * config/visium/visium.opt.urls: Likewise.
6023 * config/vms/vms.opt.urls: Likewise.
6024 * config/vxworks-smp.opt.urls: Likewise.
6025 * config/vxworks.opt.urls: Likewise.
6026 * config/xtensa/elf.opt.urls: Likewise.
6027 * config/xtensa/uclinux.opt.urls: Likewise.
6028 * config/xtensa/xtensa.opt.urls: Likewise.
6029 * config/bfin/bfin.opt.urls: New file.
6031 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6033 * Makefile.in (OPT_URLS_HTML_DEPS): New.
6034 (regenerate-opt-urls): New target.
6035 (regenerate-opt-urls-unit-test): New target.
6036 * doc/options.texi (Option properties): Add UrlSuffix and
6037 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
6038 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
6039 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
6040 and Makefile.in's OPT_URLS_HTML_DEPS.
6041 (Anatomy of a Target Back End): Add
6042 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
6043 * regenerate-opt-urls.py: New file.
6045 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6047 * diagnostic-format-sarif.cc
6048 (sarif_builder::make_logical_location_object): Convert to...
6049 (make_sarif_logical_location_object): ...this.
6050 (sarif_builder::set_any_logical_locs_arr): Update for above
6052 (sarif_builder::make_thread_flow_location_object): Call
6053 maybe_add_sarif_properties on each diagnostic_event.
6054 * diagnostic-format-sarif.h (class logical_location): New forward
6056 (make_sarif_logical_location_object): New decl.
6057 * diagnostic-path.h (class sarif_object): New forward decl.
6058 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
6060 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
6061 Patrick Lin <patrick@andestech.com>
6062 Rufus Chen <rufus@andestech.com>
6063 Monk Chiang <monk.chiang@sifive.com>
6065 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
6066 with Nan-boxing value.
6067 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
6069 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
6070 Jeff Law <jlaw@ventanamicro.com>
6072 PR rtl-optimization/104914
6073 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
6074 a sign or zero extension is only required if the modified field
6075 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
6076 targets, don't refer to the temporarily incorrectly extended value
6077 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
6079 2024-01-04 Pan Li <pan2.li@intel.com>
6082 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6084 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6086 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6088 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6090 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
6092 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
6095 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6097 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
6098 (compute_nregs_for_mode): Refine LMUL.
6099 (max_number_of_live_regs): Ditto.
6100 (compute_estimated_lmul): Ditto.
6101 (has_unexpected_spills_p): Ditto.
6103 2024-01-04 Li Wei <liwei@loongson.cn>
6105 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
6106 Remove useless forward declaration.
6107 (loongarch_is_even_extraction): Remove useless forward declaration.
6108 (loongarch_try_expand_lsx_vshuf_const): Removed.
6109 (loongarch_expand_vec_perm_const_1): Merged.
6110 (loongarch_is_double_duplicate): Removed.
6111 (loongarch_is_center_extraction): Ditto.
6112 (loongarch_is_reversing_permutation): Ditto.
6113 (loongarch_is_di_misalign_extract): Ditto.
6114 (loongarch_is_si_misalign_extract): Ditto.
6115 (loongarch_is_lasx_lowpart_extract): Ditto.
6116 (loongarch_is_op_reverse_perm): Ditto.
6117 (loongarch_is_single_op_perm): Ditto.
6118 (loongarch_is_divisible_perm): Ditto.
6119 (loongarch_is_triple_stride_extract): Ditto.
6120 (loongarch_expand_vec_perm_const_2): Merged.
6121 (loongarch_expand_vec_perm_const): New.
6122 (loongarch_vectorize_vec_perm_const): Adjust.
6124 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
6126 * omp-general.cc: Fix comment typos and misplaced/confusing
6127 comments. Delete redundant include of omp-general.h.
6129 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6131 PR rtl-optimization/104914
6132 * config/mips/mips.md (insqisi_extended): New patterns.
6133 (inshisi_extended): Ditto.
6135 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6137 * config/mips/mips.cc (mips_insn_cost): New function.
6139 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6141 * config/mips/mips.md (perf_ratio): New attribute.
6143 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6147 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
6148 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
6149 blocks belong to infinite loop.
6150 (pre_vsetvl::emit_vsetvl): Remove fake edges.
6151 * config/riscv/t-riscv: Add a new include file.
6153 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6155 * config/riscv/vector.md: Fix indent.
6157 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6159 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
6160 OMP_CLAUSE__SIMDUID_.
6161 * tree.cc (omp_clause_num_ops): Update position of entry for
6162 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
6163 (omp_clause_code_name): Likewise.
6165 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6167 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
6168 printing of FUNC_MAP/IND_FUNC_MAP labels.
6170 2024-01-03 Jakub Jelinek <jakub@redhat.com>
6172 * gcc.cc (process_command): Update copyright notice dates.
6173 * gcov-dump.cc (print_version): Ditto.
6174 * gcov.cc (print_version): Ditto.
6175 * gcov-tool.cc (print_version): Ditto.
6176 * gengtype.cc (create_file): Ditto.
6177 * doc/cpp.texi: Bump @copying's copyright year.
6178 * doc/cppinternals.texi: Ditto.
6179 * doc/gcc.texi: Ditto.
6180 * doc/gccint.texi: Ditto.
6181 * doc/gcov.texi: Ditto.
6182 * doc/install.texi: Ditto.
6183 * doc/invoke.texi: Ditto.
6185 2024-01-03 Xi Ruoyao <xry111@xry111.site>
6187 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
6188 (fmin<mode>3): Likewise.
6189 (reduc_fmax_scal_<mode>3): New define_expand.
6190 (reduc_fmin_scal_<mode>3): Likewise.
6192 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6195 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
6196 (max_number_of_live_regs): Ditto.
6197 (has_unexpected_spills_p): Ditto.
6199 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6200 Jin Ma <jinma@linux.alibaba.com>
6201 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6202 Christoph Müllner <christoph.muellner@vrull.eu>
6204 * config/riscv/vector.md:
6205 Use vector_length_operand for vsetvl patterns.
6207 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6209 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
6210 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
6212 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
6214 * config/aarch64/aarch64-tuning-flags.def
6215 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
6216 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
6217 * config/aarch64/aarch64.cc
6218 (aarch64_override_options_internal): Set
6219 param_fully_pipelined_fma according to tuning option.
6220 * config/aarch64/tuning_models/ampere1.h: Add
6221 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
6222 * config/aarch64/tuning_models/ampere1a.h: Likewise.
6223 * config/aarch64/tuning_models/ampere1b.h: Likewise.
6225 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6227 * config/riscv/vector-crypto.md: Modify copyright year.
6229 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6231 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
6233 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
6235 * config.in: Regenerate.
6236 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
6237 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
6238 Added TLS Le Relax support.
6239 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
6240 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
6241 * configure: Regenerate.
6242 * configure.ac: Check if binutils supports TLS le relax.
6244 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6246 * config/riscv/iterators.md: Add rotate insn name.
6247 * config/riscv/riscv.md: Add new insns name for crypto vector.
6248 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
6249 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
6250 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
6252 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6255 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
6256 pointer type liveness count.
6258 Copyright (C) 2024 Free Software Foundation, Inc.
6260 Copying and distribution of this file, with or without modification,
6261 are permitted in any medium without royalty provided the copyright
6262 notice and this notice are preserved.