1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 #include "diagnostic.h"
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
143 enum mips_address_type
{
150 /* Macros to create an enumeration identifier for a function prototype. */
151 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
152 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
153 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
154 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
156 /* Classifies the prototype of a builtin function. */
157 enum mips_function_type
159 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
160 #include "config/mips/mips-ftypes.def"
161 #undef DEF_MIPS_FTYPE
165 /* Specifies how a builtin function should be converted into rtl. */
166 enum mips_builtin_type
168 /* The builtin corresponds directly to an .md pattern. The return
169 value is mapped to operand 0 and the arguments are mapped to
170 operands 1 and above. */
173 /* The builtin corresponds directly to an .md pattern. There is no return
174 value and the arguments are mapped to operands 0 and above. */
175 MIPS_BUILTIN_DIRECT_NO_TARGET
,
177 /* The builtin corresponds to a comparison instruction followed by
178 a mips_cond_move_tf_ps pattern. The first two arguments are the
179 values to compare and the second two arguments are the vector
180 operands for the movt.ps or movf.ps instruction (in assembly order). */
184 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
185 of this instruction is the result of the comparison, which has mode
186 CCV2 or CCV4. The function arguments are mapped to operands 1 and
187 above. The function's return value is an SImode boolean that is
188 true under the following conditions:
190 MIPS_BUILTIN_CMP_ANY: one of the registers is true
191 MIPS_BUILTIN_CMP_ALL: all of the registers are true
192 MIPS_BUILTIN_CMP_LOWER: the first register is true
193 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
194 MIPS_BUILTIN_CMP_ANY
,
195 MIPS_BUILTIN_CMP_ALL
,
196 MIPS_BUILTIN_CMP_UPPER
,
197 MIPS_BUILTIN_CMP_LOWER
,
199 /* As above, but the instruction only sets a single $fcc register. */
200 MIPS_BUILTIN_CMP_SINGLE
,
202 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
203 MIPS_BUILTIN_BPOSGE32
206 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
207 #define MIPS_FP_CONDITIONS(MACRO) \
225 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
226 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
227 enum mips_fp_condition
{
228 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
231 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
232 #define STRINGIFY(X) #X
233 static const char *const mips_fp_conditions
[] = {
234 MIPS_FP_CONDITIONS (STRINGIFY
)
237 /* Information about a function's frame layout. */
238 struct mips_frame_info
GTY(())
240 /* The size of the frame in bytes. */
241 HOST_WIDE_INT total_size
;
243 /* The number of bytes allocated to variables. */
244 HOST_WIDE_INT var_size
;
246 /* The number of bytes allocated to outgoing function arguments. */
247 HOST_WIDE_INT args_size
;
249 /* The number of bytes allocated to the .cprestore slot, or 0 if there
251 HOST_WIDE_INT cprestore_size
;
253 /* Bit X is set if the function saves or restores GPR X. */
256 /* Likewise FPR X. */
259 /* The number of GPRs and FPRs saved. */
263 /* The offset of the topmost GPR and FPR save slots from the top of
264 the frame, or zero if no such slots are needed. */
265 HOST_WIDE_INT gp_save_offset
;
266 HOST_WIDE_INT fp_save_offset
;
268 /* Likewise, but giving offsets from the bottom of the frame. */
269 HOST_WIDE_INT gp_sp_offset
;
270 HOST_WIDE_INT fp_sp_offset
;
272 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
273 HOST_WIDE_INT arg_pointer_offset
;
275 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
276 HOST_WIDE_INT hard_frame_pointer_offset
;
279 struct machine_function
GTY(()) {
280 /* Pseudo-reg holding the value of $28 in a mips16 function which
281 refers to GP relative global variables. */
282 rtx mips16_gp_pseudo_rtx
;
284 /* The number of extra stack bytes taken up by register varargs.
285 This area is allocated by the callee at the very top of the frame. */
288 /* Current frame information, calculated by mips_compute_frame_info. */
289 struct mips_frame_info frame
;
291 /* The register to use as the global pointer within this function. */
292 unsigned int global_pointer
;
294 /* True if mips_adjust_insn_length should ignore an instruction's
296 bool ignore_hazard_length_p
;
298 /* True if the whole function is suitable for .set noreorder and
300 bool all_noreorder_p
;
302 /* True if the function is known to have an instruction that needs $gp. */
305 /* True if we have emitted an instruction to initialize
306 mips16_gp_pseudo_rtx. */
307 bool initialized_mips16_gp_pseudo_p
;
310 /* Information about a single argument. */
313 /* True if the argument is passed in a floating-point register, or
314 would have been if we hadn't run out of registers. */
317 /* The number of words passed in registers, rounded up. */
318 unsigned int reg_words
;
320 /* For EABI, the offset of the first register from GP_ARG_FIRST or
321 FP_ARG_FIRST. For other ABIs, the offset of the first register from
322 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
323 comment for details).
325 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
327 unsigned int reg_offset
;
329 /* The number of words that must be passed on the stack, rounded up. */
330 unsigned int stack_words
;
332 /* The offset from the start of the stack overflow area of the argument's
333 first stack word. Only meaningful when STACK_WORDS is nonzero. */
334 unsigned int stack_offset
;
338 /* Information about an address described by mips_address_type.
344 REG is the base register and OFFSET is the constant offset.
347 REG is the register that contains the high part of the address,
348 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
349 is the type of OFFSET's symbol.
352 SYMBOL_TYPE is the type of symbol being referenced. */
354 struct mips_address_info
356 enum mips_address_type type
;
359 enum mips_symbol_type symbol_type
;
363 /* One stage in a constant building sequence. These sequences have
367 A = A CODE[1] VALUE[1]
368 A = A CODE[2] VALUE[2]
371 where A is an accumulator, each CODE[i] is a binary rtl operation
372 and each VALUE[i] is a constant integer. */
373 struct mips_integer_op
{
375 unsigned HOST_WIDE_INT value
;
379 /* The largest number of operations needed to load an integer constant.
380 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
381 When the lowest bit is clear, we can try, but reject a sequence with
382 an extra SLL at the end. */
383 #define MIPS_MAX_INTEGER_OPS 7
385 /* Information about a MIPS16e SAVE or RESTORE instruction. */
386 struct mips16e_save_restore_info
{
387 /* The number of argument registers saved by a SAVE instruction.
388 0 for RESTORE instructions. */
391 /* Bit X is set if the instruction saves or restores GPR X. */
394 /* The total number of bytes to allocate. */
398 /* Global variables for machine-dependent things. */
400 /* Threshold for data being put into the small data/bss area, instead
401 of the normal data area. */
402 int mips_section_threshold
= -1;
404 /* Count the number of .file directives, so that .loc is up to date. */
405 int num_source_filenames
= 0;
407 /* Name of the file containing the current function. */
408 const char *current_function_file
= "";
410 /* Count the number of sdb related labels are generated (to find block
411 start and end boundaries). */
412 int sdb_label_count
= 0;
414 /* Next label # for each statement for Silicon Graphics IRIS systems. */
417 /* Map GCC register number to debugger register number. */
418 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
419 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
421 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
426 /* The next branch instruction is a branch likely, not branch normal. */
427 int mips_branch_likely
;
429 /* The operands passed to the last cmpMM expander. */
432 /* The target cpu for code generation. */
433 enum processor_type mips_arch
;
434 const struct mips_cpu_info
*mips_arch_info
;
436 /* The target cpu for optimization and scheduling. */
437 enum processor_type mips_tune
;
438 const struct mips_cpu_info
*mips_tune_info
;
440 /* Which instruction set architecture to use. */
443 /* The architecture selected by -mipsN. */
444 static const struct mips_cpu_info
*mips_isa_info
;
446 /* Which ABI to use. */
447 int mips_abi
= MIPS_ABI_DEFAULT
;
449 /* Cost information to use. */
450 const struct mips_rtx_cost_data
*mips_cost
;
452 /* Remember the ambient target flags, excluding mips16. */
453 static int mips_base_target_flags
;
454 /* The mips16 command-line target flags only. */
455 static bool mips_base_mips16
;
456 /* Similar copies of option settings. */
457 static int mips_flag_delayed_branch
; /* flag_delayed_branch */
458 static int mips_base_schedule_insns
; /* flag_schedule_insns */
459 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
460 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
461 static int mips_base_align_loops
; /* align_loops */
462 static int mips_base_align_jumps
; /* align_jumps */
463 static int mips_base_align_functions
; /* align_functions */
465 /* The -mtext-loads setting. */
466 enum mips_code_readable_setting mips_code_readable
= CODE_READABLE_YES
;
468 /* If TRUE, we split addresses into their high and low parts in the RTL. */
469 int mips_split_addresses
;
471 /* Array giving truth value on whether or not a given hard register
472 can support a given mode. */
473 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
475 /* List of all MIPS punctuation characters used by print_operand. */
476 char mips_print_operand_punct
[256];
478 static GTY (()) int mips_output_filename_first_time
= 1;
480 /* mips_split_p[X] is true if symbols of type X can be split by
481 mips_split_symbol(). */
482 bool mips_split_p
[NUM_SYMBOL_TYPES
];
484 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
485 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
486 if they are matched by a special .md file pattern. */
487 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
489 /* Likewise for HIGHs. */
490 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
492 /* Map hard register number to register class */
493 const enum reg_class mips_regno_to_class
[] =
495 LEA_REGS
, LEA_REGS
, M16_NA_REGS
, V1_REG
,
496 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
497 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
498 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
499 M16_NA_REGS
, M16_NA_REGS
, LEA_REGS
, LEA_REGS
,
500 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
501 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
502 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
503 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
504 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
505 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
506 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
507 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
508 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
509 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
510 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
511 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
512 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
513 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
514 NO_REGS
, ALL_REGS
, ALL_REGS
, NO_REGS
,
515 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
516 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
517 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
518 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
519 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
520 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
521 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
522 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
523 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
524 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
525 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
526 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
527 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
528 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
529 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
530 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
531 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
532 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
533 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
534 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
535 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
536 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
537 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
538 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
539 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
540 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
541 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
544 /* Table of machine dependent attributes. */
545 const struct attribute_spec mips_attribute_table
[] =
547 { "long_call", 0, 0, false, true, true, NULL
},
548 { "far", 0, 0, false, true, true, NULL
},
549 { "near", 0, 0, false, true, true, NULL
},
550 /* Switch MIPS16 ASE on and off per-function. We would really like
551 to make these type attributes, but GCC doesn't provide the hooks
552 we need to support the right conversion rules. As declaration
553 attributes, they affect code generation but don't carry other
555 { "mips16", 0, 0, true, false, false, NULL
},
556 { "nomips16", 0, 0, true, false, false, NULL
},
557 { NULL
, 0, 0, false, false, false, NULL
}
560 /* A table describing all the processors gcc knows about. Names are
561 matched in the order listed. The first mention of an ISA level is
562 taken as the canonical name for that ISA.
564 To ease comparison, please keep this table in the same order
565 as gas's mips_cpu_info_table[]. Please also make sure that
566 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
567 options correctly. */
568 const struct mips_cpu_info mips_cpu_info_table
[] = {
569 /* Entries for generic ISAs */
570 { "mips1", PROCESSOR_R3000
, 1, 0 },
571 { "mips2", PROCESSOR_R6000
, 2, 0 },
572 { "mips3", PROCESSOR_R4000
, 3, 0 },
573 { "mips4", PROCESSOR_R8000
, 4, 0 },
574 /* Prefer not to use branch-likely instructions for generic MIPS32rX
575 and MIPS64rX code. The instructions were officially deprecated
576 in revisions 2 and earlier, but revision 3 is likely to downgrade
577 that to a recommendation to avoid the instructions in code that
578 isn't tuned to a specific processor. */
579 { "mips32", PROCESSOR_4KC
, 32, PTF_AVOID_BRANCHLIKELY
},
580 { "mips32r2", PROCESSOR_M4K
, 33, PTF_AVOID_BRANCHLIKELY
},
581 { "mips64", PROCESSOR_5KC
, 64, PTF_AVOID_BRANCHLIKELY
},
584 { "r3000", PROCESSOR_R3000
, 1, 0 },
585 { "r2000", PROCESSOR_R3000
, 1, 0 }, /* = r3000 */
586 { "r3900", PROCESSOR_R3900
, 1, 0 },
589 { "r6000", PROCESSOR_R6000
, 2, 0 },
592 { "r4000", PROCESSOR_R4000
, 3, 0 },
593 { "vr4100", PROCESSOR_R4100
, 3, 0 },
594 { "vr4111", PROCESSOR_R4111
, 3, 0 },
595 { "vr4120", PROCESSOR_R4120
, 3, 0 },
596 { "vr4130", PROCESSOR_R4130
, 3, 0 },
597 { "vr4300", PROCESSOR_R4300
, 3, 0 },
598 { "r4400", PROCESSOR_R4000
, 3, 0 }, /* = r4000 */
599 { "r4600", PROCESSOR_R4600
, 3, 0 },
600 { "orion", PROCESSOR_R4600
, 3, 0 }, /* = r4600 */
601 { "r4650", PROCESSOR_R4650
, 3, 0 },
604 { "r8000", PROCESSOR_R8000
, 4, 0 },
605 { "vr5000", PROCESSOR_R5000
, 4, 0 },
606 { "vr5400", PROCESSOR_R5400
, 4, 0 },
607 { "vr5500", PROCESSOR_R5500
, 4, PTF_AVOID_BRANCHLIKELY
},
608 { "rm7000", PROCESSOR_R7000
, 4, 0 },
609 { "rm9000", PROCESSOR_R9000
, 4, 0 },
612 { "4kc", PROCESSOR_4KC
, 32, 0 },
613 { "4km", PROCESSOR_4KC
, 32, 0 }, /* = 4kc */
614 { "4kp", PROCESSOR_4KP
, 32, 0 },
615 { "4ksc", PROCESSOR_4KC
, 32, 0 },
617 /* MIPS32 Release 2 */
618 { "m4k", PROCESSOR_M4K
, 33, 0 },
619 { "4kec", PROCESSOR_4KC
, 33, 0 },
620 { "4kem", PROCESSOR_4KC
, 33, 0 },
621 { "4kep", PROCESSOR_4KP
, 33, 0 },
622 { "4ksd", PROCESSOR_4KC
, 33, 0 },
624 { "24kc", PROCESSOR_24KC
, 33, 0 },
625 { "24kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
626 { "24kf", PROCESSOR_24KF2_1
, 33, 0 },
627 { "24kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
628 { "24kfx", PROCESSOR_24KF1_1
, 33, 0 },
629 { "24kx", PROCESSOR_24KF1_1
, 33, 0 },
631 { "24kec", PROCESSOR_24KC
, 33, 0 }, /* 24K with DSP */
632 { "24kef2_1", PROCESSOR_24KF2_1
, 33, 0 },
633 { "24kef", PROCESSOR_24KF2_1
, 33, 0 },
634 { "24kef1_1", PROCESSOR_24KF1_1
, 33, 0 },
635 { "24kefx", PROCESSOR_24KF1_1
, 33, 0 },
636 { "24kex", PROCESSOR_24KF1_1
, 33, 0 },
638 { "34kc", PROCESSOR_24KC
, 33, 0 }, /* 34K with MT/DSP */
639 { "34kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
640 { "34kf", PROCESSOR_24KF2_1
, 33, 0 },
641 { "34kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
642 { "34kfx", PROCESSOR_24KF1_1
, 33, 0 },
643 { "34kx", PROCESSOR_24KF1_1
, 33, 0 },
645 { "74kc", PROCESSOR_74KC
, 33, 0 }, /* 74K with DSPr2 */
646 { "74kf2_1", PROCESSOR_74KF2_1
, 33, 0 },
647 { "74kf", PROCESSOR_74KF2_1
, 33, 0 },
648 { "74kf1_1", PROCESSOR_74KF1_1
, 33, 0 },
649 { "74kfx", PROCESSOR_74KF1_1
, 33, 0 },
650 { "74kx", PROCESSOR_74KF1_1
, 33, 0 },
651 { "74kf3_2", PROCESSOR_74KF3_2
, 33, 0 },
654 { "5kc", PROCESSOR_5KC
, 64, 0 },
655 { "5kf", PROCESSOR_5KF
, 64, 0 },
656 { "20kc", PROCESSOR_20KC
, 64, PTF_AVOID_BRANCHLIKELY
},
657 { "sb1", PROCESSOR_SB1
, 64, PTF_AVOID_BRANCHLIKELY
},
658 { "sb1a", PROCESSOR_SB1A
, 64, PTF_AVOID_BRANCHLIKELY
},
659 { "sr71000", PROCESSOR_SR71000
, 64, PTF_AVOID_BRANCHLIKELY
},
662 /* Default costs. If these are used for a processor we should look
663 up the actual costs. */
664 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
665 COSTS_N_INSNS (7), /* fp_mult_sf */ \
666 COSTS_N_INSNS (8), /* fp_mult_df */ \
667 COSTS_N_INSNS (23), /* fp_div_sf */ \
668 COSTS_N_INSNS (36), /* fp_div_df */ \
669 COSTS_N_INSNS (10), /* int_mult_si */ \
670 COSTS_N_INSNS (10), /* int_mult_di */ \
671 COSTS_N_INSNS (69), /* int_div_si */ \
672 COSTS_N_INSNS (69), /* int_div_di */ \
673 2, /* branch_cost */ \
674 4 /* memory_latency */
676 /* Need to replace these with the costs of calling the appropriate
678 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
679 COSTS_N_INSNS (256), /* fp_mult_sf */ \
680 COSTS_N_INSNS (256), /* fp_mult_df */ \
681 COSTS_N_INSNS (256), /* fp_div_sf */ \
682 COSTS_N_INSNS (256) /* fp_div_df */
684 static struct mips_rtx_cost_data
const mips_rtx_cost_optimize_size
=
686 COSTS_N_INSNS (1), /* fp_add */
687 COSTS_N_INSNS (1), /* fp_mult_sf */
688 COSTS_N_INSNS (1), /* fp_mult_df */
689 COSTS_N_INSNS (1), /* fp_div_sf */
690 COSTS_N_INSNS (1), /* fp_div_df */
691 COSTS_N_INSNS (1), /* int_mult_si */
692 COSTS_N_INSNS (1), /* int_mult_di */
693 COSTS_N_INSNS (1), /* int_div_si */
694 COSTS_N_INSNS (1), /* int_div_di */
696 4 /* memory_latency */
699 static struct mips_rtx_cost_data
const mips_rtx_cost_data
[PROCESSOR_MAX
] =
702 COSTS_N_INSNS (2), /* fp_add */
703 COSTS_N_INSNS (4), /* fp_mult_sf */
704 COSTS_N_INSNS (5), /* fp_mult_df */
705 COSTS_N_INSNS (12), /* fp_div_sf */
706 COSTS_N_INSNS (19), /* fp_div_df */
707 COSTS_N_INSNS (12), /* int_mult_si */
708 COSTS_N_INSNS (12), /* int_mult_di */
709 COSTS_N_INSNS (35), /* int_div_si */
710 COSTS_N_INSNS (35), /* int_div_di */
712 4 /* memory_latency */
717 COSTS_N_INSNS (6), /* int_mult_si */
718 COSTS_N_INSNS (6), /* int_mult_di */
719 COSTS_N_INSNS (36), /* int_div_si */
720 COSTS_N_INSNS (36), /* int_div_di */
722 4 /* memory_latency */
726 COSTS_N_INSNS (36), /* int_mult_si */
727 COSTS_N_INSNS (36), /* int_mult_di */
728 COSTS_N_INSNS (37), /* int_div_si */
729 COSTS_N_INSNS (37), /* int_div_di */
731 4 /* memory_latency */
735 COSTS_N_INSNS (4), /* int_mult_si */
736 COSTS_N_INSNS (11), /* int_mult_di */
737 COSTS_N_INSNS (36), /* int_div_si */
738 COSTS_N_INSNS (68), /* int_div_di */
740 4 /* memory_latency */
743 COSTS_N_INSNS (4), /* fp_add */
744 COSTS_N_INSNS (4), /* fp_mult_sf */
745 COSTS_N_INSNS (5), /* fp_mult_df */
746 COSTS_N_INSNS (17), /* fp_div_sf */
747 COSTS_N_INSNS (32), /* fp_div_df */
748 COSTS_N_INSNS (4), /* int_mult_si */
749 COSTS_N_INSNS (11), /* int_mult_di */
750 COSTS_N_INSNS (36), /* int_div_si */
751 COSTS_N_INSNS (68), /* int_div_di */
753 4 /* memory_latency */
756 COSTS_N_INSNS (4), /* fp_add */
757 COSTS_N_INSNS (4), /* fp_mult_sf */
758 COSTS_N_INSNS (5), /* fp_mult_df */
759 COSTS_N_INSNS (17), /* fp_div_sf */
760 COSTS_N_INSNS (32), /* fp_div_df */
761 COSTS_N_INSNS (4), /* int_mult_si */
762 COSTS_N_INSNS (7), /* int_mult_di */
763 COSTS_N_INSNS (42), /* int_div_si */
764 COSTS_N_INSNS (72), /* int_div_di */
766 4 /* memory_latency */
770 COSTS_N_INSNS (5), /* int_mult_si */
771 COSTS_N_INSNS (5), /* int_mult_di */
772 COSTS_N_INSNS (41), /* int_div_si */
773 COSTS_N_INSNS (41), /* int_div_di */
775 4 /* memory_latency */
778 COSTS_N_INSNS (8), /* fp_add */
779 COSTS_N_INSNS (8), /* fp_mult_sf */
780 COSTS_N_INSNS (10), /* fp_mult_df */
781 COSTS_N_INSNS (34), /* fp_div_sf */
782 COSTS_N_INSNS (64), /* fp_div_df */
783 COSTS_N_INSNS (5), /* int_mult_si */
784 COSTS_N_INSNS (5), /* int_mult_di */
785 COSTS_N_INSNS (41), /* int_div_si */
786 COSTS_N_INSNS (41), /* int_div_di */
788 4 /* memory_latency */
791 COSTS_N_INSNS (4), /* fp_add */
792 COSTS_N_INSNS (4), /* fp_mult_sf */
793 COSTS_N_INSNS (5), /* fp_mult_df */
794 COSTS_N_INSNS (17), /* fp_div_sf */
795 COSTS_N_INSNS (32), /* fp_div_df */
796 COSTS_N_INSNS (5), /* int_mult_si */
797 COSTS_N_INSNS (5), /* int_mult_di */
798 COSTS_N_INSNS (41), /* int_div_si */
799 COSTS_N_INSNS (41), /* int_div_di */
801 4 /* memory_latency */
805 COSTS_N_INSNS (5), /* int_mult_si */
806 COSTS_N_INSNS (5), /* int_mult_di */
807 COSTS_N_INSNS (41), /* int_div_si */
808 COSTS_N_INSNS (41), /* int_div_di */
810 4 /* memory_latency */
813 COSTS_N_INSNS (8), /* fp_add */
814 COSTS_N_INSNS (8), /* fp_mult_sf */
815 COSTS_N_INSNS (10), /* fp_mult_df */
816 COSTS_N_INSNS (34), /* fp_div_sf */
817 COSTS_N_INSNS (64), /* fp_div_df */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
823 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* fp_add */
827 COSTS_N_INSNS (4), /* fp_mult_sf */
828 COSTS_N_INSNS (5), /* fp_mult_df */
829 COSTS_N_INSNS (17), /* fp_div_sf */
830 COSTS_N_INSNS (32), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
836 4 /* memory_latency */
839 COSTS_N_INSNS (6), /* fp_add */
840 COSTS_N_INSNS (6), /* fp_mult_sf */
841 COSTS_N_INSNS (7), /* fp_mult_df */
842 COSTS_N_INSNS (25), /* fp_div_sf */
843 COSTS_N_INSNS (48), /* fp_div_df */
844 COSTS_N_INSNS (5), /* int_mult_si */
845 COSTS_N_INSNS (5), /* int_mult_di */
846 COSTS_N_INSNS (41), /* int_div_si */
847 COSTS_N_INSNS (41), /* int_div_di */
849 4 /* memory_latency */
855 COSTS_N_INSNS (2), /* fp_add */
856 COSTS_N_INSNS (4), /* fp_mult_sf */
857 COSTS_N_INSNS (5), /* fp_mult_df */
858 COSTS_N_INSNS (12), /* fp_div_sf */
859 COSTS_N_INSNS (19), /* fp_div_df */
860 COSTS_N_INSNS (2), /* int_mult_si */
861 COSTS_N_INSNS (2), /* int_mult_di */
862 COSTS_N_INSNS (35), /* int_div_si */
863 COSTS_N_INSNS (35), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (3), /* fp_add */
869 COSTS_N_INSNS (5), /* fp_mult_sf */
870 COSTS_N_INSNS (6), /* fp_mult_df */
871 COSTS_N_INSNS (15), /* fp_div_sf */
872 COSTS_N_INSNS (16), /* fp_div_df */
873 COSTS_N_INSNS (17), /* int_mult_si */
874 COSTS_N_INSNS (17), /* int_mult_di */
875 COSTS_N_INSNS (38), /* int_div_si */
876 COSTS_N_INSNS (38), /* int_div_di */
878 6 /* memory_latency */
881 COSTS_N_INSNS (6), /* fp_add */
882 COSTS_N_INSNS (7), /* fp_mult_sf */
883 COSTS_N_INSNS (8), /* fp_mult_df */
884 COSTS_N_INSNS (23), /* fp_div_sf */
885 COSTS_N_INSNS (36), /* fp_div_df */
886 COSTS_N_INSNS (10), /* int_mult_si */
887 COSTS_N_INSNS (10), /* int_mult_di */
888 COSTS_N_INSNS (69), /* int_div_si */
889 COSTS_N_INSNS (69), /* int_div_di */
891 6 /* memory_latency */
903 /* The only costs that appear to be updated here are
904 integer multiplication. */
906 COSTS_N_INSNS (4), /* int_mult_si */
907 COSTS_N_INSNS (6), /* int_mult_di */
908 COSTS_N_INSNS (69), /* int_div_si */
909 COSTS_N_INSNS (69), /* int_div_di */
911 4 /* memory_latency */
923 COSTS_N_INSNS (6), /* fp_add */
924 COSTS_N_INSNS (4), /* fp_mult_sf */
925 COSTS_N_INSNS (5), /* fp_mult_df */
926 COSTS_N_INSNS (23), /* fp_div_sf */
927 COSTS_N_INSNS (36), /* fp_div_df */
928 COSTS_N_INSNS (5), /* int_mult_si */
929 COSTS_N_INSNS (5), /* int_mult_di */
930 COSTS_N_INSNS (36), /* int_div_si */
931 COSTS_N_INSNS (36), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (6), /* fp_add */
937 COSTS_N_INSNS (5), /* fp_mult_sf */
938 COSTS_N_INSNS (6), /* fp_mult_df */
939 COSTS_N_INSNS (30), /* fp_div_sf */
940 COSTS_N_INSNS (59), /* fp_div_df */
941 COSTS_N_INSNS (3), /* int_mult_si */
942 COSTS_N_INSNS (4), /* int_mult_di */
943 COSTS_N_INSNS (42), /* int_div_si */
944 COSTS_N_INSNS (74), /* int_div_di */
946 4 /* memory_latency */
949 COSTS_N_INSNS (6), /* fp_add */
950 COSTS_N_INSNS (5), /* fp_mult_sf */
951 COSTS_N_INSNS (6), /* fp_mult_df */
952 COSTS_N_INSNS (30), /* fp_div_sf */
953 COSTS_N_INSNS (59), /* fp_div_df */
954 COSTS_N_INSNS (5), /* int_mult_si */
955 COSTS_N_INSNS (9), /* int_mult_di */
956 COSTS_N_INSNS (42), /* int_div_si */
957 COSTS_N_INSNS (74), /* int_div_di */
959 4 /* memory_latency */
962 /* The only costs that are changed here are
963 integer multiplication. */
964 COSTS_N_INSNS (6), /* fp_add */
965 COSTS_N_INSNS (7), /* fp_mult_sf */
966 COSTS_N_INSNS (8), /* fp_mult_df */
967 COSTS_N_INSNS (23), /* fp_div_sf */
968 COSTS_N_INSNS (36), /* fp_div_df */
969 COSTS_N_INSNS (5), /* int_mult_si */
970 COSTS_N_INSNS (9), /* int_mult_di */
971 COSTS_N_INSNS (69), /* int_div_si */
972 COSTS_N_INSNS (69), /* int_div_di */
974 4 /* memory_latency */
980 /* The only costs that are changed here are
981 integer multiplication. */
982 COSTS_N_INSNS (6), /* fp_add */
983 COSTS_N_INSNS (7), /* fp_mult_sf */
984 COSTS_N_INSNS (8), /* fp_mult_df */
985 COSTS_N_INSNS (23), /* fp_div_sf */
986 COSTS_N_INSNS (36), /* fp_div_df */
987 COSTS_N_INSNS (3), /* int_mult_si */
988 COSTS_N_INSNS (8), /* int_mult_di */
989 COSTS_N_INSNS (69), /* int_div_si */
990 COSTS_N_INSNS (69), /* int_div_di */
992 4 /* memory_latency */
995 /* These costs are the same as the SB-1A below. */
996 COSTS_N_INSNS (4), /* fp_add */
997 COSTS_N_INSNS (4), /* fp_mult_sf */
998 COSTS_N_INSNS (4), /* fp_mult_df */
999 COSTS_N_INSNS (24), /* fp_div_sf */
1000 COSTS_N_INSNS (32), /* fp_div_df */
1001 COSTS_N_INSNS (3), /* int_mult_si */
1002 COSTS_N_INSNS (4), /* int_mult_di */
1003 COSTS_N_INSNS (36), /* int_div_si */
1004 COSTS_N_INSNS (68), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 /* These costs are the same as the SB-1 above. */
1010 COSTS_N_INSNS (4), /* fp_add */
1011 COSTS_N_INSNS (4), /* fp_mult_sf */
1012 COSTS_N_INSNS (4), /* fp_mult_df */
1013 COSTS_N_INSNS (24), /* fp_div_sf */
1014 COSTS_N_INSNS (32), /* fp_div_df */
1015 COSTS_N_INSNS (3), /* int_mult_si */
1016 COSTS_N_INSNS (4), /* int_mult_di */
1017 COSTS_N_INSNS (36), /* int_div_si */
1018 COSTS_N_INSNS (68), /* int_div_di */
1019 1, /* branch_cost */
1020 4 /* memory_latency */
1027 /* Use a hash table to keep track of implicit mips16/nomips16 attributes
1028 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1030 struct mflip_mips16_entry
GTY (()) {
1034 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1036 /* Hash table callbacks for mflip_mips16_htab. */
1039 mflip_mips16_htab_hash (const void *entry
)
1041 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1045 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1047 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1048 (const char *) name
) == 0;
1051 static GTY(()) int mips16_flipper
;
1053 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1054 for -mflip-mips16. Return true if it should use "mips16" and false if
1055 it should use "nomips16". */
1058 mflip_mips16_use_mips16_p (tree decl
)
1060 struct mflip_mips16_entry
*entry
;
1065 /* Use the opposite of the command-line setting for anonymous decls. */
1066 if (!DECL_NAME (decl
))
1067 return !mips_base_mips16
;
1069 if (!mflip_mips16_htab
)
1070 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1071 mflip_mips16_htab_eq
, NULL
);
1073 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1074 hash
= htab_hash_string (name
);
1075 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1076 entry
= (struct mflip_mips16_entry
*) *slot
;
1079 mips16_flipper
= !mips16_flipper
;
1080 entry
= GGC_NEW (struct mflip_mips16_entry
);
1082 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1085 return entry
->mips16_p
;
1088 /* Predicates to test for presence of "near" and "far"/"long_call"
1089 attributes on the given TYPE. */
1092 mips_near_type_p (const_tree type
)
1094 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1098 mips_far_type_p (const_tree type
)
1100 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1101 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1104 /* Similar predicates for "mips16"/"nomips16" attributes. */
1107 mips_mips16_decl_p (const_tree decl
)
1109 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1113 mips_nomips16_decl_p (const_tree decl
)
1115 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1118 /* Return true if function DECL is a MIPS16 function. Return the ambient
1119 setting if DECL is null. */
1122 mips_use_mips16_mode_p (tree decl
)
1126 /* Nested functions must use the same frame pointer as their
1127 parent and must therefore use the same ISA mode. */
1128 tree parent
= decl_function_context (decl
);
1131 if (mips_mips16_decl_p (decl
))
1133 if (mips_nomips16_decl_p (decl
))
1136 return mips_base_mips16
;
1139 /* Return 0 if the attributes for two types are incompatible, 1 if they
1140 are compatible, and 2 if they are nearly compatible (which causes a
1141 warning to be generated). */
1144 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1146 /* Check for mismatch of non-default calling convention. */
1147 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
1150 /* Disallow mixed near/far attributes. */
1151 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1153 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1159 /* Implement TARGET_INSERT_ATTRIBUTES. */
1162 mips_insert_attributes (tree decl
, tree
*attributes
)
1165 bool mips16_p
, nomips16_p
;
1167 /* Check for "mips16" and "nomips16" attributes. */
1168 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1169 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1170 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1173 error ("%qs attribute only applies to functions", "mips16");
1175 error ("%qs attribute only applies to functions", "nomips16");
1179 mips16_p
|= mips_mips16_decl_p (decl
);
1180 nomips16_p
|= mips_nomips16_decl_p (decl
);
1181 if (mips16_p
|| nomips16_p
)
1183 /* DECL cannot be simultaneously mips16 and nomips16. */
1184 if (mips16_p
&& nomips16_p
)
1185 error ("%qs cannot have both %<mips16%> and "
1186 "%<nomips16%> attributes",
1187 IDENTIFIER_POINTER (DECL_NAME (decl
)));
1189 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1191 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1192 "mips16" attribute, arbitrarily pick one. We must pick the same
1193 setting for duplicate declarations of a function. */
1194 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1195 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1200 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1203 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1205 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1206 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1207 error ("%qs redeclared with conflicting %qs attributes",
1208 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "mips16");
1209 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1210 error ("%qs redeclared with conflicting %qs attributes",
1211 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "nomips16");
1213 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1214 DECL_ATTRIBUTES (newdecl
));
1217 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1218 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1221 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1223 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1225 *base_ptr
= XEXP (x
, 0);
1226 *offset_ptr
= INTVAL (XEXP (x
, 1));
1235 static unsigned int mips_build_integer (struct mips_integer_op
*,
1236 unsigned HOST_WIDE_INT
);
1238 /* Subroutine of mips_build_integer (with the same interface).
1239 Assume that the final action in the sequence should be a left shift. */
1242 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1244 unsigned int i
, shift
;
1246 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1247 since signed numbers are easier to load than unsigned ones. */
1249 while ((value
& 1) == 0)
1250 value
/= 2, shift
++;
1252 i
= mips_build_integer (codes
, value
);
1253 codes
[i
].code
= ASHIFT
;
1254 codes
[i
].value
= shift
;
1259 /* As for mips_build_shift, but assume that the final action will be
1260 an IOR or PLUS operation. */
1263 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1265 unsigned HOST_WIDE_INT high
;
1268 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1269 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1271 /* The constant is too complex to load with a simple lui/ori pair
1272 so our goal is to clear as many trailing zeros as possible.
1273 In this case, we know bit 16 is set and that the low 16 bits
1274 form a negative number. If we subtract that number from VALUE,
1275 we will clear at least the lowest 17 bits, maybe more. */
1276 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1277 codes
[i
].code
= PLUS
;
1278 codes
[i
].value
= CONST_LOW_PART (value
);
1282 i
= mips_build_integer (codes
, high
);
1283 codes
[i
].code
= IOR
;
1284 codes
[i
].value
= value
& 0xffff;
1290 /* Fill CODES with a sequence of rtl operations to load VALUE.
1291 Return the number of operations needed. */
1294 mips_build_integer (struct mips_integer_op
*codes
,
1295 unsigned HOST_WIDE_INT value
)
1297 if (SMALL_OPERAND (value
)
1298 || SMALL_OPERAND_UNSIGNED (value
)
1299 || LUI_OPERAND (value
))
1301 /* The value can be loaded with a single instruction. */
1302 codes
[0].code
= UNKNOWN
;
1303 codes
[0].value
= value
;
1306 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1308 /* Either the constant is a simple LUI/ORI combination or its
1309 lowest bit is set. We don't want to shift in this case. */
1310 return mips_build_lower (codes
, value
);
1312 else if ((value
& 0xffff) == 0)
1314 /* The constant will need at least three actions. The lowest
1315 16 bits are clear, so the final action will be a shift. */
1316 return mips_build_shift (codes
, value
);
1320 /* The final action could be a shift, add or inclusive OR.
1321 Rather than use a complex condition to select the best
1322 approach, try both mips_build_shift and mips_build_lower
1323 and pick the one that gives the shortest sequence.
1324 Note that this case is only used once per constant. */
1325 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1326 unsigned int cost
, alt_cost
;
1328 cost
= mips_build_shift (codes
, value
);
1329 alt_cost
= mips_build_lower (alt_codes
, value
);
1330 if (alt_cost
< cost
)
1332 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1339 /* Return true if X is a thread-local symbol. */
1342 mips_tls_operand_p (rtx x
)
1344 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1347 /* Return true if SYMBOL_REF X is associated with a global symbol
1348 (in the STB_GLOBAL sense). */
1351 mips_global_symbol_p (const_rtx x
)
1353 const_tree
const decl
= SYMBOL_REF_DECL (x
);
1356 return !SYMBOL_REF_LOCAL_P (x
);
1358 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1359 or weak symbols. Relocations in the object file will be against
1360 the target symbol, so it's that symbol's binding that matters here. */
1361 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1364 /* Return true if SYMBOL_REF X binds locally. */
1367 mips_symbol_binds_local_p (const_rtx x
)
1369 return (SYMBOL_REF_DECL (x
)
1370 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1371 : SYMBOL_REF_LOCAL_P (x
));
1374 /* Return true if rtx constants of mode MODE should be put into a small
1378 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1380 return (!TARGET_EMBEDDED_DATA
1381 && TARGET_LOCAL_SDATA
1382 && GET_MODE_SIZE (mode
) <= mips_section_threshold
);
1385 /* Return true if X should not be moved directly into register $25.
1386 We need this because many versions of GAS will treat "la $25,foo" as
1387 part of a call sequence and so allow a global "foo" to be lazily bound. */
1390 mips_dangerous_for_la25_p (rtx x
)
1392 return (!TARGET_EXPLICIT_RELOCS
1394 && GET_CODE (x
) == SYMBOL_REF
1395 && mips_global_symbol_p (x
));
1398 /* Return the method that should be used to access SYMBOL_REF or
1399 LABEL_REF X in context CONTEXT. */
1401 static enum mips_symbol_type
1402 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1405 return SYMBOL_GOT_DISP
;
1407 if (GET_CODE (x
) == LABEL_REF
)
1409 /* LABEL_REFs are used for jump tables as well as text labels.
1410 Only return SYMBOL_PC_RELATIVE if we know the label is in
1411 the text section. */
1412 if (TARGET_MIPS16_SHORT_JUMP_TABLES
)
1413 return SYMBOL_PC_RELATIVE
;
1414 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1415 return SYMBOL_GOT_PAGE_OFST
;
1416 return SYMBOL_ABSOLUTE
;
1419 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1421 if (SYMBOL_REF_TLS_MODEL (x
))
1424 if (CONSTANT_POOL_ADDRESS_P (x
))
1426 if (TARGET_MIPS16_TEXT_LOADS
)
1427 return SYMBOL_PC_RELATIVE
;
1429 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1430 return SYMBOL_PC_RELATIVE
;
1432 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1433 return SYMBOL_GP_RELATIVE
;
1436 /* Do not use small-data accesses for weak symbols; they may end up
1439 && SYMBOL_REF_SMALL_P (x
)
1440 && !SYMBOL_REF_WEAK (x
))
1441 return SYMBOL_GP_RELATIVE
;
1443 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1446 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1448 /* There are three cases to consider:
1450 - o32 PIC (either with or without explicit relocs)
1451 - n32/n64 PIC without explicit relocs
1452 - n32/n64 PIC with explicit relocs
1454 In the first case, both local and global accesses will use an
1455 R_MIPS_GOT16 relocation. We must correctly predict which of
1456 the two semantics (local or global) the assembler and linker
1457 will apply. The choice depends on the symbol's binding rather
1458 than its visibility.
1460 In the second case, the assembler will not use R_MIPS_GOT16
1461 relocations, but it chooses between local and global accesses
1462 in the same way as for o32 PIC.
1464 In the third case we have more freedom since both forms of
1465 access will work for any kind of symbol. However, there seems
1466 little point in doing things differently. */
1467 if (mips_global_symbol_p (x
))
1468 return SYMBOL_GOT_DISP
;
1470 return SYMBOL_GOT_PAGE_OFST
;
1473 if (TARGET_MIPS16_PCREL_LOADS
&& context
!= SYMBOL_CONTEXT_CALL
)
1474 return SYMBOL_FORCE_TO_MEM
;
1475 return SYMBOL_ABSOLUTE
;
1478 /* Classify symbolic expression X, given that it appears in context
1481 static enum mips_symbol_type
1482 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1486 split_const (x
, &x
, &offset
);
1487 if (UNSPEC_ADDRESS_P (x
))
1488 return UNSPEC_ADDRESS_TYPE (x
);
1490 return mips_classify_symbol (x
, context
);
1493 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1494 is the alignment (in bytes) of SYMBOL_REF X. */
1497 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1499 /* If for some reason we can't get the alignment for the
1500 symbol, initializing this to one means we will only accept
1502 HOST_WIDE_INT align
= 1;
1505 /* Get the alignment of the symbol we're referring to. */
1506 t
= SYMBOL_REF_DECL (x
);
1508 align
= DECL_ALIGN_UNIT (t
);
1510 return offset
>= 0 && offset
< align
;
1513 /* Return true if X is a symbolic constant that can be used in context
1514 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1517 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1518 enum mips_symbol_type
*symbol_type
)
1522 split_const (x
, &x
, &offset
);
1523 if (UNSPEC_ADDRESS_P (x
))
1525 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1526 x
= UNSPEC_ADDRESS (x
);
1528 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1530 *symbol_type
= mips_classify_symbol (x
, context
);
1531 if (*symbol_type
== SYMBOL_TLS
)
1537 if (offset
== const0_rtx
)
1540 /* Check whether a nonzero offset is valid for the underlying
1542 switch (*symbol_type
)
1544 case SYMBOL_ABSOLUTE
:
1545 case SYMBOL_FORCE_TO_MEM
:
1546 case SYMBOL_32_HIGH
:
1547 case SYMBOL_64_HIGH
:
1550 /* If the target has 64-bit pointers and the object file only
1551 supports 32-bit symbols, the values of those symbols will be
1552 sign-extended. In this case we can't allow an arbitrary offset
1553 in case the 32-bit value X + OFFSET has a different sign from X. */
1554 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1555 return offset_within_block_p (x
, INTVAL (offset
));
1557 /* In other cases the relocations can handle any offset. */
1560 case SYMBOL_PC_RELATIVE
:
1561 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1562 In this case, we no longer have access to the underlying constant,
1563 but the original symbol-based access was known to be valid. */
1564 if (GET_CODE (x
) == LABEL_REF
)
1569 case SYMBOL_GP_RELATIVE
:
1570 /* Make sure that the offset refers to something within the
1571 same object block. This should guarantee that the final
1572 PC- or GP-relative offset is within the 16-bit limit. */
1573 return offset_within_block_p (x
, INTVAL (offset
));
1575 case SYMBOL_GOT_PAGE_OFST
:
1576 case SYMBOL_GOTOFF_PAGE
:
1577 /* If the symbol is global, the GOT entry will contain the symbol's
1578 address, and we will apply a 16-bit offset after loading it.
1579 If the symbol is local, the linker should provide enough local
1580 GOT entries for a 16-bit offset, but larger offsets may lead
1582 return SMALL_INT (offset
);
1586 /* There is no carry between the HI and LO REL relocations, so the
1587 offset is only valid if we know it won't lead to such a carry. */
1588 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1590 case SYMBOL_GOT_DISP
:
1591 case SYMBOL_GOTOFF_DISP
:
1592 case SYMBOL_GOTOFF_CALL
:
1593 case SYMBOL_GOTOFF_LOADGP
:
1596 case SYMBOL_GOTTPREL
:
1604 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1605 single instruction. We rely on the fact that, in the worst case,
1606 all instructions involved in a MIPS16 address calculation are usually
1610 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1614 case SYMBOL_ABSOLUTE
:
1615 /* When using 64-bit symbols, we need 5 preparatory instructions,
1618 lui $at,%highest(symbol)
1619 daddiu $at,$at,%higher(symbol)
1621 daddiu $at,$at,%hi(symbol)
1624 The final address is then $at + %lo(symbol). With 32-bit
1625 symbols we just need a preparatory lui for normal mode and
1626 a preparatory "li; sll" for MIPS16. */
1627 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1629 case SYMBOL_GP_RELATIVE
:
1630 /* Treat GP-relative accesses as taking a single instruction on
1631 MIPS16 too; the copy of $gp can often be shared. */
1634 case SYMBOL_PC_RELATIVE
:
1635 /* PC-relative constants can be only be used with addiupc,
1637 if (mode
== MAX_MACHINE_MODE
1638 || GET_MODE_SIZE (mode
) == 4
1639 || GET_MODE_SIZE (mode
) == 8)
1642 /* The constant must be loaded using addiupc first. */
1645 case SYMBOL_FORCE_TO_MEM
:
1646 /* LEAs will be converted into constant-pool references by
1648 if (mode
== MAX_MACHINE_MODE
)
1651 /* The constant must be loaded from the constant pool. */
1654 case SYMBOL_GOT_DISP
:
1655 /* The constant will have to be loaded from the GOT before it
1656 is used in an address. */
1657 if (mode
!= MAX_MACHINE_MODE
)
1662 case SYMBOL_GOT_PAGE_OFST
:
1663 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1664 the local/global classification is accurate. See override_options
1667 The worst cases are:
1669 (1) For local symbols when generating o32 or o64 code. The assembler
1675 ...and the final address will be $at + %lo(symbol).
1677 (2) For global symbols when -mxgot. The assembler will use:
1679 lui $at,%got_hi(symbol)
1682 ...and the final address will be $at + %got_lo(symbol). */
1685 case SYMBOL_GOTOFF_PAGE
:
1686 case SYMBOL_GOTOFF_DISP
:
1687 case SYMBOL_GOTOFF_CALL
:
1688 case SYMBOL_GOTOFF_LOADGP
:
1689 case SYMBOL_32_HIGH
:
1690 case SYMBOL_64_HIGH
:
1696 case SYMBOL_GOTTPREL
:
1699 /* A 16-bit constant formed by a single relocation, or a 32-bit
1700 constant formed from a high 16-bit relocation and a low 16-bit
1701 relocation. Use mips_split_p to determine which. */
1702 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1705 /* We don't treat a bare TLS symbol as a constant. */
1711 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1712 to load symbols of type TYPE into a register. Return 0 if the given
1713 type of symbol cannot be used as an immediate operand.
1715 Otherwise, return the number of instructions needed to load or store
1716 values of mode MODE to or from addresses of type TYPE. Return 0 if
1717 the given type of symbol is not valid in addresses.
1719 In both cases, treat extended MIPS16 instructions as two instructions. */
1722 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1724 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1727 /* Return true if X can not be forced into a constant pool. */
1730 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1732 return mips_tls_operand_p (*x
);
1735 /* Return true if X can not be forced into a constant pool. */
1738 mips_cannot_force_const_mem (rtx x
)
1744 /* As an optimization, reject constants that mips_legitimize_move
1747 Suppose we have a multi-instruction sequence that loads constant C
1748 into register R. If R does not get allocated a hard register, and
1749 R is used in an operand that allows both registers and memory
1750 references, reload will consider forcing C into memory and using
1751 one of the instruction's memory alternatives. Returning false
1752 here will force it to use an input reload instead. */
1753 if (GET_CODE (x
) == CONST_INT
)
1756 split_const (x
, &base
, &offset
);
1757 if (symbolic_operand (base
, VOIDmode
) && SMALL_INT (offset
))
1761 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, 0))
1767 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1768 constants when we're using a per-function constant pool. */
1771 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1772 const_rtx x ATTRIBUTE_UNUSED
)
1774 return !TARGET_MIPS16_PCREL_LOADS
;
1777 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1780 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
, int strict
)
1782 if (!HARD_REGISTER_NUM_P (regno
))
1786 regno
= reg_renumber
[regno
];
1789 /* These fake registers will be eliminated to either the stack or
1790 hard frame pointer, both of which are usually valid base registers.
1791 Reload deals with the cases where the eliminated form isn't valid. */
1792 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
1795 /* In mips16 mode, the stack pointer can only address word and doubleword
1796 values, nothing smaller. There are two problems here:
1798 (a) Instantiating virtual registers can introduce new uses of the
1799 stack pointer. If these virtual registers are valid addresses,
1800 the stack pointer should be too.
1802 (b) Most uses of the stack pointer are not made explicit until
1803 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1804 We don't know until that stage whether we'll be eliminating to the
1805 stack pointer (which needs the restriction) or the hard frame
1806 pointer (which doesn't).
1808 All in all, it seems more consistent to only enforce this restriction
1809 during and after reload. */
1810 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
1811 return !strict
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1813 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
1817 /* Return true if X is a valid base register for the given mode.
1818 Allow only hard registers if STRICT. */
1821 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, int strict
)
1823 if (!strict
&& GET_CODE (x
) == SUBREG
)
1827 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict
));
1831 /* Return true if X is a valid address for machine mode MODE. If it is,
1832 fill in INFO appropriately. STRICT is true if we should only accept
1833 hard base registers. */
1836 mips_classify_address (struct mips_address_info
*info
, rtx x
,
1837 enum machine_mode mode
, int strict
)
1839 switch (GET_CODE (x
))
1843 info
->type
= ADDRESS_REG
;
1845 info
->offset
= const0_rtx
;
1846 return mips_valid_base_register_p (info
->reg
, mode
, strict
);
1849 info
->type
= ADDRESS_REG
;
1850 info
->reg
= XEXP (x
, 0);
1851 info
->offset
= XEXP (x
, 1);
1852 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1853 && const_arith_operand (info
->offset
, VOIDmode
));
1856 info
->type
= ADDRESS_LO_SUM
;
1857 info
->reg
= XEXP (x
, 0);
1858 info
->offset
= XEXP (x
, 1);
1859 /* We have to trust the creator of the LO_SUM to do something vaguely
1860 sane. Target-independent code that creates a LO_SUM should also
1861 create and verify the matching HIGH. Target-independent code that
1862 adds an offset to a LO_SUM must prove that the offset will not
1863 induce a carry. Failure to do either of these things would be
1864 a bug, and we are not required to check for it here. The MIPS
1865 backend itself should only create LO_SUMs for valid symbolic
1866 constants, with the high part being either a HIGH or a copy
1869 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
1870 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1871 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
1872 && mips_lo_relocs
[info
->symbol_type
] != 0);
1875 /* Small-integer addresses don't occur very often, but they
1876 are legitimate if $0 is a valid base register. */
1877 info
->type
= ADDRESS_CONST_INT
;
1878 return !TARGET_MIPS16
&& SMALL_INT (x
);
1883 info
->type
= ADDRESS_SYMBOLIC
;
1884 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
1886 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
1887 && !mips_split_p
[info
->symbol_type
]);
1894 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1895 returns a nonzero value if X is a legitimate address for a memory
1896 operand of the indicated MODE. STRICT is nonzero if this function
1897 is called during reload. */
1900 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1902 struct mips_address_info addr
;
1904 return mips_classify_address (&addr
, x
, mode
, strict
);
1907 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1910 mips_stack_address_p (rtx x
, enum machine_mode mode
)
1912 struct mips_address_info addr
;
1914 return (mips_classify_address (&addr
, x
, mode
, false)
1915 && addr
.type
== ADDRESS_REG
1916 && addr
.reg
== stack_pointer_rtx
);
1919 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
1920 address instruction. */
1923 mips_lwxs_address_p (rtx addr
)
1926 && GET_CODE (addr
) == PLUS
1927 && REG_P (XEXP (addr
, 1)))
1929 rtx offset
= XEXP (addr
, 0);
1930 if (GET_CODE (offset
) == MULT
1931 && REG_P (XEXP (offset
, 0))
1932 && GET_CODE (XEXP (offset
, 1)) == CONST_INT
1933 && INTVAL (XEXP (offset
, 1)) == 4)
1939 /* Return true if a value at OFFSET bytes from BASE can be accessed
1940 using an unextended mips16 instruction. MODE is the mode of the
1943 Usually the offset in an unextended instruction is a 5-bit field.
1944 The offset is unsigned and shifted left once for HIs, twice
1945 for SIs, and so on. An exception is SImode accesses off the
1946 stack pointer, which have an 8-bit immediate field. */
1949 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
, rtx offset
)
1952 && GET_CODE (offset
) == CONST_INT
1953 && INTVAL (offset
) >= 0
1954 && (INTVAL (offset
) & (GET_MODE_SIZE (mode
) - 1)) == 0)
1956 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
1957 return INTVAL (offset
) < 256 * GET_MODE_SIZE (mode
);
1958 return INTVAL (offset
) < 32 * GET_MODE_SIZE (mode
);
1964 /* Return the number of instructions needed to load or store a value
1965 of mode MODE at X. Return 0 if X isn't valid for MODE. Assume that
1966 multiword moves may need to be split into word moves if MIGHT_SPLIT_P,
1967 otherwise assume that a single load or store is enough.
1969 For mips16 code, count extended instructions as two instructions. */
1972 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
1974 struct mips_address_info addr
;
1977 /* BLKmode is used for single unaligned loads and stores and should
1978 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
1979 meaningless, so we have to single it out as a special case one way
1981 if (mode
!= BLKmode
&& might_split_p
)
1982 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1986 if (mips_classify_address (&addr
, x
, mode
, false))
1991 && !mips16_unextended_reference_p (mode
, addr
.reg
, addr
.offset
))
1995 case ADDRESS_LO_SUM
:
1996 return (TARGET_MIPS16
? factor
* 2 : factor
);
1998 case ADDRESS_CONST_INT
:
2001 case ADDRESS_SYMBOLIC
:
2002 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2008 /* Likewise for constant X. */
2011 mips_const_insns (rtx x
)
2013 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2014 enum mips_symbol_type symbol_type
;
2017 switch (GET_CODE (x
))
2020 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2022 || !mips_split_p
[symbol_type
])
2025 /* This is simply an lui for normal mode. It is an extended
2026 "li" followed by an extended "sll" for MIPS16. */
2027 return TARGET_MIPS16
? 4 : 1;
2031 /* Unsigned 8-bit constants can be loaded using an unextended
2032 LI instruction. Unsigned 16-bit constants can be loaded
2033 using an extended LI. Negative constants must be loaded
2034 using LI and then negated. */
2035 return (INTVAL (x
) >= 0 && INTVAL (x
) < 256 ? 1
2036 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2037 : INTVAL (x
) > -256 && INTVAL (x
) < 0 ? 2
2038 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2041 return mips_build_integer (codes
, INTVAL (x
));
2045 return (!TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0);
2051 /* See if we can refer to X directly. */
2052 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2053 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2055 /* Otherwise try splitting the constant into a base and offset.
2056 16-bit offsets can be added using an extra addiu. Larger offsets
2057 must be calculated separately and then added to the base. */
2058 split_const (x
, &x
, &offset
);
2061 int n
= mips_const_insns (x
);
2064 if (SMALL_INT (offset
))
2067 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2074 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2083 /* Return the number of instructions needed to implement INSN,
2084 given that it loads from or stores to MEM. Count extended
2085 mips16 instructions as two instructions. */
2088 mips_load_store_insns (rtx mem
, rtx insn
)
2090 enum machine_mode mode
;
2094 gcc_assert (MEM_P (mem
));
2095 mode
= GET_MODE (mem
);
2097 /* Try to prove that INSN does not need to be split. */
2098 might_split_p
= true;
2099 if (GET_MODE_BITSIZE (mode
) == 64)
2101 set
= single_set (insn
);
2102 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2103 might_split_p
= false;
2106 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2110 /* Return the number of instructions needed for an integer division. */
2113 mips_idiv_insns (void)
2118 if (TARGET_CHECK_ZERO_DIV
)
2120 if (GENERATE_DIVIDE_TRAPS
)
2126 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2131 /* Emit a move from SRC to DEST. Assume that the move expanders can
2132 handle all moves if !can_create_pseudo_p (). The distinction is
2133 important because, unlike emit_move_insn, the move expanders know
2134 how to force Pmode objects into the constant pool even when the
2135 constant pool address is not itself legitimate. */
2138 mips_emit_move (rtx dest
, rtx src
)
2140 return (can_create_pseudo_p ()
2141 ? emit_move_insn (dest
, src
)
2142 : emit_move_insn_1 (dest
, src
));
2145 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2148 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2150 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2151 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2154 /* Copy VALUE to a register and return that register. If new psuedos
2155 are allowed, copy it into a new register, otherwise use DEST. */
2158 mips_force_temporary (rtx dest
, rtx value
)
2160 if (can_create_pseudo_p ())
2161 return force_reg (Pmode
, value
);
2164 mips_emit_move (copy_rtx (dest
), value
);
2169 /* If we can access small data directly (using gp-relative relocation
2170 operators) return the small data pointer, otherwise return null.
2172 For each mips16 function which refers to GP relative symbols, we
2173 use a pseudo register, initialized at the start of the function, to
2174 hold the $gp value. */
2177 mips16_gp_pseudo_reg (void)
2179 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2180 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2182 /* Don't initialize the pseudo register if we are being called from
2183 the tree optimizers' cost-calculation routines. */
2184 if (!cfun
->machine
->initialized_mips16_gp_pseudo_p
2185 && (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
))
2189 /* We want to initialize this to a value which gcc will believe
2191 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2193 push_topmost_sequence ();
2194 /* We need to emit the initialization after the FUNCTION_BEG
2195 note, so that it will be integrated. */
2196 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
2198 && NOTE_KIND (scan
) == NOTE_INSN_FUNCTION_BEG
)
2200 if (scan
== NULL_RTX
)
2201 scan
= get_insns ();
2202 insn
= emit_insn_after (insn
, scan
);
2203 pop_topmost_sequence ();
2205 cfun
->machine
->initialized_mips16_gp_pseudo_p
= true;
2208 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2211 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2212 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2213 constant in that context and can be split into a high part and a LO_SUM.
2214 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2215 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2217 TEMP is as for mips_force_temporary and is used to load the high
2218 part into a register. */
2221 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*lo_sum_out
)
2223 enum mips_symbol_context context
;
2224 enum mips_symbol_type symbol_type
;
2227 context
= (mode
== MAX_MACHINE_MODE
2228 ? SYMBOL_CONTEXT_LEA
2229 : SYMBOL_CONTEXT_MEM
);
2230 if (!mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2231 || mips_symbol_insns (symbol_type
, mode
) == 0
2232 || !mips_split_p
[symbol_type
])
2237 if (symbol_type
== SYMBOL_GP_RELATIVE
)
2239 if (!can_create_pseudo_p ())
2241 emit_insn (gen_load_const_gp (copy_rtx (temp
)));
2245 high
= mips16_gp_pseudo_reg ();
2249 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2250 high
= mips_force_temporary (temp
, high
);
2252 *lo_sum_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2258 /* Wrap symbol or label BASE in an unspec address of type SYMBOL_TYPE
2259 and add CONST_INT OFFSET to the result. */
2262 mips_unspec_address_offset (rtx base
, rtx offset
,
2263 enum mips_symbol_type symbol_type
)
2265 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2266 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2267 if (offset
!= const0_rtx
)
2268 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2269 return gen_rtx_CONST (Pmode
, base
);
2272 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2273 type SYMBOL_TYPE. */
2276 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2280 split_const (address
, &base
, &offset
);
2281 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2285 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2286 high part to BASE and return the result. Just return BASE otherwise.
2287 TEMP is available as a temporary register if needed.
2289 The returned expression can be used as the first operand to a LO_SUM. */
2292 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2293 enum mips_symbol_type symbol_type
)
2295 if (mips_split_p
[symbol_type
])
2297 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2298 addr
= mips_force_temporary (temp
, addr
);
2299 return mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2305 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2306 mips_force_temporary; it is only needed when OFFSET is not a
2310 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2312 if (!SMALL_OPERAND (offset
))
2317 /* Load the full offset into a register so that we can use
2318 an unextended instruction for the address itself. */
2319 high
= GEN_INT (offset
);
2324 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2325 high
= GEN_INT (CONST_HIGH_PART (offset
));
2326 offset
= CONST_LOW_PART (offset
);
2328 high
= mips_force_temporary (temp
, high
);
2329 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2331 return plus_constant (reg
, offset
);
2334 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2335 referencing, and TYPE is the symbol type to use (either global
2336 dynamic or local dynamic). V0 is an RTX for the return value
2337 location. The entire insn sequence is returned. */
2339 static GTY(()) rtx mips_tls_symbol
;
2342 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2344 rtx insn
, loc
, tga
, a0
;
2346 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2348 if (!mips_tls_symbol
)
2349 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2351 loc
= mips_unspec_address (sym
, type
);
2355 emit_insn (gen_rtx_SET (Pmode
, a0
,
2356 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2357 tga
= gen_const_mem (Pmode
, mips_tls_symbol
);
2358 insn
= emit_call_insn (gen_call_value (v0
, tga
, const0_rtx
, const0_rtx
));
2359 CONST_OR_PURE_CALL_P (insn
) = 1;
2360 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2361 insn
= get_insns ();
2368 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2369 return value will be a valid address and move_operand (either a REG
2373 mips_legitimize_tls_address (rtx loc
)
2375 rtx dest
, insn
, v0
, v1
, tmp1
, tmp2
, eqv
;
2376 enum tls_model model
;
2380 sorry ("MIPS16 TLS");
2381 return gen_reg_rtx (Pmode
);
2384 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2385 v1
= gen_rtx_REG (Pmode
, GP_RETURN
+ 1);
2387 model
= SYMBOL_REF_TLS_MODEL (loc
);
2388 /* Only TARGET_ABICALLS code can have more than one module; other
2389 code must be be static and should not use a GOT. All TLS models
2390 reduce to local exec in this situation. */
2391 if (!TARGET_ABICALLS
)
2392 model
= TLS_MODEL_LOCAL_EXEC
;
2396 case TLS_MODEL_GLOBAL_DYNAMIC
:
2397 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2398 dest
= gen_reg_rtx (Pmode
);
2399 emit_libcall_block (insn
, dest
, v0
, loc
);
2402 case TLS_MODEL_LOCAL_DYNAMIC
:
2403 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2404 tmp1
= gen_reg_rtx (Pmode
);
2406 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2407 share the LDM result with other LD model accesses. */
2408 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2410 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2412 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2413 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2414 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2417 case TLS_MODEL_INITIAL_EXEC
:
2418 tmp1
= gen_reg_rtx (Pmode
);
2419 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2420 if (Pmode
== DImode
)
2422 emit_insn (gen_tls_get_tp_di (v1
));
2423 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2427 emit_insn (gen_tls_get_tp_si (v1
));
2428 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2430 dest
= gen_reg_rtx (Pmode
);
2431 emit_insn (gen_add3_insn (dest
, tmp1
, v1
));
2434 case TLS_MODEL_LOCAL_EXEC
:
2435 if (Pmode
== DImode
)
2436 emit_insn (gen_tls_get_tp_di (v1
));
2438 emit_insn (gen_tls_get_tp_si (v1
));
2440 tmp1
= mips_unspec_offset_high (NULL
, v1
, loc
, SYMBOL_TPREL
);
2441 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2442 mips_unspec_address (loc
, SYMBOL_TPREL
));
2452 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2453 be legitimized in a way that the generic machinery might not expect,
2454 put the new address in *XLOC and return true. MODE is the mode of
2455 the memory being accessed. */
2458 mips_legitimize_address (rtx
*xloc
, enum machine_mode mode
)
2460 if (mips_tls_operand_p (*xloc
))
2462 *xloc
= mips_legitimize_tls_address (*xloc
);
2466 /* See if the address can split into a high part and a LO_SUM. */
2467 if (mips_split_symbol (NULL
, *xloc
, mode
, xloc
))
2470 if (GET_CODE (*xloc
) == PLUS
&& GET_CODE (XEXP (*xloc
, 1)) == CONST_INT
)
2472 /* Handle REG + CONSTANT using mips_add_offset. */
2475 reg
= XEXP (*xloc
, 0);
2476 if (!mips_valid_base_register_p (reg
, mode
, 0))
2477 reg
= copy_to_mode_reg (Pmode
, reg
);
2478 *xloc
= mips_add_offset (0, reg
, INTVAL (XEXP (*xloc
, 1)));
2486 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2489 mips_move_integer (rtx dest
, rtx temp
, unsigned HOST_WIDE_INT value
)
2491 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2492 enum machine_mode mode
;
2493 unsigned int i
, cost
;
2496 mode
= GET_MODE (dest
);
2497 cost
= mips_build_integer (codes
, value
);
2499 /* Apply each binary operation to X. Invariant: X is a legitimate
2500 source operand for a SET pattern. */
2501 x
= GEN_INT (codes
[0].value
);
2502 for (i
= 1; i
< cost
; i
++)
2504 if (!can_create_pseudo_p ())
2506 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
2510 x
= force_reg (mode
, x
);
2511 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
2514 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
2518 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2519 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2523 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
2527 /* Split moves of big integers into smaller pieces. */
2528 if (splittable_const_int_operand (src
, mode
))
2530 mips_move_integer (dest
, dest
, INTVAL (src
));
2534 /* Split moves of symbolic constants into high/low pairs. */
2535 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
2537 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
2541 if (mips_tls_operand_p (src
))
2543 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
2547 /* If we have (const (plus symbol offset)), and that expression cannot
2548 be forced into memory, load the symbol first and add in the offset.
2549 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2550 forced into memory, as it usually produces better code. */
2551 split_const (src
, &base
, &offset
);
2552 if (offset
!= const0_rtx
2553 && (targetm
.cannot_force_const_mem (src
)
2554 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
2556 base
= mips_force_temporary (dest
, base
);
2557 mips_emit_move (dest
, mips_add_offset (0, base
, INTVAL (offset
)));
2561 src
= force_const_mem (mode
, src
);
2563 /* When using explicit relocs, constant pool references are sometimes
2564 not legitimate addresses. */
2565 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
2566 mips_emit_move (dest
, src
);
2570 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2571 sequence that is valid. */
2574 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
2576 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
2578 mips_emit_move (dest
, force_reg (mode
, src
));
2582 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2583 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
2584 && REG_P (src
) && MD_REG_P (REGNO (src
))
2585 && REG_P (dest
) && GP_REG_P (REGNO (dest
)))
2587 int other_regno
= REGNO (src
) == HI_REGNUM
? LO_REGNUM
: HI_REGNUM
;
2588 if (GET_MODE_SIZE (mode
) <= 4)
2589 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode
, REGNO (dest
)),
2590 gen_rtx_REG (SImode
, REGNO (src
)),
2591 gen_rtx_REG (SImode
, other_regno
)));
2593 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode
, REGNO (dest
)),
2594 gen_rtx_REG (DImode
, REGNO (src
)),
2595 gen_rtx_REG (DImode
, other_regno
)));
2599 /* We need to deal with constants that would be legitimate
2600 immediate_operands but not legitimate move_operands. */
2601 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
2603 mips_legitimize_const_move (mode
, dest
, src
);
2604 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
2610 /* Return true if X in context CONTEXT is a small data address that can
2611 be rewritten as a LO_SUM. */
2614 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
2616 enum mips_symbol_type symbol_type
;
2618 return (TARGET_EXPLICIT_RELOCS
2619 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
2620 && symbol_type
== SYMBOL_GP_RELATIVE
);
2624 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2625 containing MEM, or null if none. */
2628 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
2630 enum mips_symbol_context context
;
2632 if (GET_CODE (*loc
) == LO_SUM
)
2637 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
2642 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
2643 return mips_rewrite_small_data_p (*loc
, context
);
2646 /* Return true if OP refers to small data symbols directly, not through
2650 mips_small_data_pattern_p (rtx op
)
2652 return for_each_rtx (&op
, mips_small_data_pattern_1
, 0);
2655 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2656 DATA is the containing MEM, or null if none. */
2659 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
2661 enum mips_symbol_context context
;
2665 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
2669 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
2670 if (mips_rewrite_small_data_p (*loc
, context
))
2671 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
2673 if (GET_CODE (*loc
) == LO_SUM
)
2679 /* If possible, rewrite OP so that it refers to small data using
2680 explicit relocations. */
2683 mips_rewrite_small_data (rtx op
)
2685 op
= copy_insn (op
);
2686 for_each_rtx (&op
, mips_rewrite_small_data_1
, 0);
2690 /* We need a lot of little routines to check constant values on the
2691 mips16. These are used to figure out how long the instruction will
2692 be. It would be much better to do this using constraints, but
2693 there aren't nearly enough letters available. */
2696 m16_check_op (rtx op
, int low
, int high
, int mask
)
2698 return (GET_CODE (op
) == CONST_INT
2699 && INTVAL (op
) >= low
2700 && INTVAL (op
) <= high
2701 && (INTVAL (op
) & mask
) == 0);
2705 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2707 return m16_check_op (op
, 0x1, 0x8, 0);
2711 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2713 return m16_check_op (op
, - 0x8, 0x7, 0);
2717 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2719 return m16_check_op (op
, - 0x7, 0x8, 0);
2723 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2725 return m16_check_op (op
, - 0x10, 0xf, 0);
2729 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2731 return m16_check_op (op
, - 0xf, 0x10, 0);
2735 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2737 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
2741 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2743 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
2747 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2749 return m16_check_op (op
, - 0x80, 0x7f, 0);
2753 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2755 return m16_check_op (op
, - 0x7f, 0x80, 0);
2759 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2761 return m16_check_op (op
, 0x0, 0xff, 0);
2765 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2767 return m16_check_op (op
, - 0xff, 0x0, 0);
2771 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2773 return m16_check_op (op
, - 0x1, 0xfe, 0);
2777 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2779 return m16_check_op (op
, 0x0, 0xff << 2, 3);
2783 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2785 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
2789 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2791 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
2795 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2797 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
2800 /* The cost of loading values from the constant pool. It should be
2801 larger than the cost of any constant we want to synthesize inline. */
2803 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2805 /* Return the cost of X when used as an operand to the MIPS16 instruction
2806 that implements CODE. Return -1 if there is no such instruction, or if
2807 X is not a valid immediate operand for it. */
2810 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
2817 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2818 other shifts are extended. The shift patterns truncate the shift
2819 count to the right size, so there are no out-of-range values. */
2820 if (IN_RANGE (x
, 1, 8))
2822 return COSTS_N_INSNS (1);
2825 if (IN_RANGE (x
, -128, 127))
2827 if (SMALL_OPERAND (x
))
2828 return COSTS_N_INSNS (1);
2832 /* Like LE, but reject the always-true case. */
2836 /* We add 1 to the immediate and use SLT. */
2839 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2842 if (IN_RANGE (x
, 0, 255))
2844 if (SMALL_OPERAND_UNSIGNED (x
))
2845 return COSTS_N_INSNS (1);
2850 /* Equality comparisons with 0 are cheap. */
2860 /* Return true if there is a non-MIPS16 instruction that implements CODE
2861 and if that instruction accepts X as an immediate operand. */
2864 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
2871 /* All shift counts are truncated to a valid constant. */
2876 /* Likewise rotates, if the target supports rotates at all. */
2882 /* These instructions take 16-bit unsigned immediates. */
2883 return SMALL_OPERAND_UNSIGNED (x
);
2888 /* These instructions take 16-bit signed immediates. */
2889 return SMALL_OPERAND (x
);
2895 /* The "immediate" forms of these instructions are really
2896 implemented as comparisons with register 0. */
2901 /* Likewise, meaning that the only valid immediate operand is 1. */
2905 /* We add 1 to the immediate and use SLT. */
2906 return SMALL_OPERAND (x
+ 1);
2909 /* Likewise SLTU, but reject the always-true case. */
2910 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
2914 /* The bit position and size are immediate operands. */
2915 return ISA_HAS_EXT_INS
;
2918 /* By default assume that $0 can be used for 0. */
2923 /* Return the cost of binary operation X, given that the instruction
2924 sequence for a word-sized or smaller operation has cost SINGLE_COST
2925 and that the sequence of a double-word operation has cost DOUBLE_COST. */
2928 mips_binary_cost (rtx x
, int single_cost
, int double_cost
)
2932 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
2937 + rtx_cost (XEXP (x
, 0), 0)
2938 + rtx_cost (XEXP (x
, 1), GET_CODE (x
)));
2941 /* Return the cost of floating-point multiplications of mode MODE. */
2944 mips_fp_mult_cost (enum machine_mode mode
)
2946 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
2949 /* Return the cost of floating-point divisions of mode MODE. */
2952 mips_fp_div_cost (enum machine_mode mode
)
2954 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
2957 /* Return the cost of sign-extending OP to mode MODE, not including the
2958 cost of OP itself. */
2961 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
2964 /* Extended loads are as cheap as unextended ones. */
2967 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
2968 /* A sign extension from SImode to DImode in 64-bit mode is free. */
2971 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
2972 /* We can use SEB or SEH. */
2973 return COSTS_N_INSNS (1);
2975 /* We need to use a shift left and a shift right. */
2976 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
2979 /* Return the cost of zero-extending OP to mode MODE, not including the
2980 cost of OP itself. */
2983 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
2986 /* Extended loads are as cheap as unextended ones. */
2989 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
2990 /* We need a shift left by 32 bits and a shift right by 32 bits. */
2991 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
2993 if (GENERATE_MIPS16E
)
2994 /* We can use ZEB or ZEH. */
2995 return COSTS_N_INSNS (1);
2998 /* We need to load 0xff or 0xffff into a register and use AND. */
2999 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3001 /* We can use ANDI. */
3002 return COSTS_N_INSNS (1);
3005 /* Implement TARGET_RTX_COSTS. */
3008 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3010 enum machine_mode mode
= GET_MODE (x
);
3011 bool float_mode_p
= FLOAT_MODE_P (mode
);
3015 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3016 appear in the instruction stream, and the cost of a comparison is
3017 really the cost of the branch or scc condition. At the time of
3018 writing, gcc only uses an explicit outer COMPARE code when optabs
3019 is testing whether a constant is expensive enough to force into a
3020 register. We want optabs to pass such constants through the MIPS
3021 expanders instead, so make all constants very cheap here. */
3022 if (outer_code
== COMPARE
)
3024 gcc_assert (CONSTANT_P (x
));
3032 /* Treat *clear_upper32-style ANDs as having zero cost in the
3033 second operand. The cost is entirely in the first operand.
3035 ??? This is needed because we would otherwise try to CSE
3036 the constant operand. Although that's the right thing for
3037 instructions that continue to be a register operation throughout
3038 compilation, it is disastrous for instructions that could
3039 later be converted into a memory operation. */
3041 && outer_code
== AND
3042 && UINTVAL (x
) == 0xffffffff)
3050 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3059 /* When not optimizing for size, we care more about the cost
3060 of hot code, and hot code is often in a loop. If a constant
3061 operand needs to be forced into a register, we will often be
3062 able to hoist the constant load out of the loop, so the load
3063 should not contribute to the cost. */
3065 || mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3077 if (force_to_mem_operand (x
, VOIDmode
))
3079 *total
= COSTS_N_INSNS (1);
3082 cost
= mips_const_insns (x
);
3085 /* If the constant is likely to be stored in a GPR, SETs of
3086 single-insn constants are as cheap as register sets; we
3087 never want to CSE them.
3089 Don't reduce the cost of storing a floating-point zero in
3090 FPRs. If we have a zero in an FPR for other reasons, we
3091 can get better cfg-cleanup and delayed-branch results by
3092 using it consistently, rather than using $0 sometimes and
3093 an FPR at other times. Also, moves between floating-point
3094 registers are sometimes cheaper than (D)MTC1 $0. */
3096 && outer_code
== SET
3097 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3099 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3100 want to CSE the constant itself. It is usually better to
3101 have N copies of the last operation in the sequence and one
3102 shared copy of the other operations. (Note that this is
3103 not true for MIPS16 code, where the final operation in the
3104 sequence is often an extended instruction.)
3106 Also, if we have a CONST_INT, we don't know whether it is
3107 for a word or doubleword operation, so we cannot rely on
3108 the result of mips_build_integer. */
3109 else if (!TARGET_MIPS16
3110 && (outer_code
== SET
|| mode
== VOIDmode
))
3112 *total
= COSTS_N_INSNS (cost
);
3115 /* The value will need to be fetched from the constant pool. */
3116 *total
= CONSTANT_POOL_COST
;
3120 /* If the address is legitimate, return the number of
3121 instructions it needs. */
3123 cost
= mips_address_insns (addr
, mode
, true);
3126 *total
= COSTS_N_INSNS (cost
+ 1);
3129 /* Check for a scaled indexed address. */
3130 if (mips_lwxs_address_p (addr
))
3132 *total
= COSTS_N_INSNS (2);
3135 /* Otherwise use the default handling. */
3139 *total
= COSTS_N_INSNS (6);
3143 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3147 /* Check for a *clear_upper32 pattern and treat it like a zero
3148 extension. See the pattern's comment for details. */
3151 && CONST_INT_P (XEXP (x
, 1))
3152 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3154 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3155 + rtx_cost (XEXP (x
, 0), 0));
3162 /* Double-word operations use two single-word operations. */
3163 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3171 if (CONSTANT_P (XEXP (x
, 1)))
3172 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3174 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3179 *total
= mips_cost
->fp_add
;
3181 *total
= COSTS_N_INSNS (4);
3185 /* Low-part immediates need an extended MIPS16 instruction. */
3186 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3187 + rtx_cost (XEXP (x
, 0), 0));
3202 /* Branch comparisons have VOIDmode, so use the first operand's
3204 mode
= GET_MODE (XEXP (x
, 0));
3205 if (FLOAT_MODE_P (mode
))
3207 *total
= mips_cost
->fp_add
;
3210 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3215 && ISA_HAS_NMADD_NMSUB
3216 && TARGET_FUSED_MADD
3217 && !HONOR_NANS (mode
)
3218 && !HONOR_SIGNED_ZEROS (mode
))
3220 /* See if we can use NMADD or NMSUB. See mips.md for the
3221 associated patterns. */
3222 rtx op0
= XEXP (x
, 0);
3223 rtx op1
= XEXP (x
, 1);
3224 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3226 *total
= (mips_fp_mult_cost (mode
)
3227 + rtx_cost (XEXP (XEXP (op0
, 0), 0), 0)
3228 + rtx_cost (XEXP (op0
, 1), 0)
3229 + rtx_cost (op1
, 0));
3232 if (GET_CODE (op1
) == MULT
)
3234 *total
= (mips_fp_mult_cost (mode
)
3236 + rtx_cost (XEXP (op1
, 0), 0)
3237 + rtx_cost (XEXP (op1
, 1), 0));
3247 && TARGET_FUSED_MADD
3248 && GET_CODE (XEXP (x
, 0)) == MULT
)
3251 *total
= mips_cost
->fp_add
;
3255 /* Double-word operations require three single-word operations and
3256 an SLTU. The MIPS16 version then needs to move the result of
3257 the SLTU from $24 to a MIPS16 register. */
3258 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3259 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4));
3264 && ISA_HAS_NMADD_NMSUB
3265 && TARGET_FUSED_MADD
3266 && !HONOR_NANS (mode
)
3267 && HONOR_SIGNED_ZEROS (mode
))
3269 /* See if we can use NMADD or NMSUB. See mips.md for the
3270 associated patterns. */
3271 rtx op
= XEXP (x
, 0);
3272 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3273 && GET_CODE (XEXP (op
, 0)) == MULT
)
3275 *total
= (mips_fp_mult_cost (mode
)
3276 + rtx_cost (XEXP (XEXP (op
, 0), 0), 0)
3277 + rtx_cost (XEXP (XEXP (op
, 0), 1), 0)
3278 + rtx_cost (XEXP (op
, 1), 0));
3284 *total
= mips_cost
->fp_add
;
3286 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3291 *total
= mips_fp_mult_cost (mode
);
3292 else if (mode
== DImode
&& !TARGET_64BIT
)
3293 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3294 where the mulsidi3 always includes an MFHI and an MFLO. */
3295 *total
= (optimize_size
3296 ? COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9)
3297 : mips_cost
->int_mult_si
* 3 + 6);
3298 else if (optimize_size
)
3299 *total
= (ISA_HAS_MUL3
? 1 : 2);
3300 else if (mode
== DImode
)
3301 *total
= mips_cost
->int_mult_di
;
3303 *total
= mips_cost
->int_mult_si
;
3307 /* Check for a reciprocal. */
3308 if (float_mode_p
&& XEXP (x
, 0) == CONST1_RTX (mode
))
3311 && flag_unsafe_math_optimizations
3312 && (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
))
3314 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3315 division as being free. */
3316 *total
= rtx_cost (XEXP (x
, 1), 0);
3321 *total
= mips_fp_div_cost (mode
) + rtx_cost (XEXP (x
, 1), 0);
3331 *total
= mips_fp_div_cost (mode
);
3340 /* It is our responsibility to make division by a power of 2
3341 as cheap as 2 register additions if we want the division
3342 expanders to be used for such operations; see the setting
3343 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3344 should always produce shorter code than using
3345 expand_sdiv2_pow2. */
3347 && CONST_INT_P (XEXP (x
, 1))
3348 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3350 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), 0);
3353 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3355 else if (mode
== DImode
)
3356 *total
= mips_cost
->int_div_di
;
3358 *total
= mips_cost
->int_div_si
;
3362 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3366 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3370 case UNSIGNED_FLOAT
:
3373 case FLOAT_TRUNCATE
:
3374 *total
= mips_cost
->fp_add
;
3382 /* Provide the costs of an addressing mode that contains ADDR.
3383 If ADDR is not a valid address, its cost is irrelevant. */
3386 mips_address_cost (rtx addr
)
3388 return mips_address_insns (addr
, SImode
, false);
3391 /* Return one word of double-word value OP, taking into account the fixed
3392 endianness of certain registers. HIGH_P is true to select the high part,
3393 false to select the low part. */
3396 mips_subword (rtx op
, int high_p
)
3398 unsigned int byte
, offset
;
3399 enum machine_mode mode
;
3401 mode
= GET_MODE (op
);
3402 if (mode
== VOIDmode
)
3405 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
3406 byte
= UNITS_PER_WORD
;
3410 if (FP_REG_RTX_P (op
))
3412 /* Paired FPRs are always ordered little-endian. */
3413 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
3414 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
3418 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
3420 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
3424 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3427 mips_split_64bit_move_p (rtx dest
, rtx src
)
3432 /* FP->FP moves can be done in a single instruction. */
3433 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
3436 /* Check for floating-point loads and stores. They can be done using
3437 ldc1 and sdc1 on MIPS II and above. */
3440 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
3442 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
3449 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3450 this function handles 64-bit moves for which mips_split_64bit_move_p
3451 holds. For 64-bit targets, this function handles 128-bit moves. */
3454 mips_split_doubleword_move (rtx dest
, rtx src
)
3456 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
3458 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
3459 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
3460 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
3461 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
3462 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
3463 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
3469 /* The operation can be split into two normal moves. Decide in
3470 which order to do them. */
3473 low_dest
= mips_subword (dest
, 0);
3474 if (REG_P (low_dest
)
3475 && reg_overlap_mentioned_p (low_dest
, src
))
3477 mips_emit_move (mips_subword (dest
, 1), mips_subword (src
, 1));
3478 mips_emit_move (low_dest
, mips_subword (src
, 0));
3482 mips_emit_move (low_dest
, mips_subword (src
, 0));
3483 mips_emit_move (mips_subword (dest
, 1), mips_subword (src
, 1));
3488 /* Return the appropriate instructions to move SRC into DEST. Assume
3489 that SRC is operand 1 and DEST is operand 0. */
3492 mips_output_move (rtx dest
, rtx src
)
3494 enum rtx_code dest_code
, src_code
;
3495 enum mips_symbol_type symbol_type
;
3498 dest_code
= GET_CODE (dest
);
3499 src_code
= GET_CODE (src
);
3500 dbl_p
= (GET_MODE_SIZE (GET_MODE (dest
)) == 8);
3502 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
3505 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
3506 || (!TARGET_MIPS16
&& src
== CONST0_RTX (GET_MODE (dest
))))
3508 if (dest_code
== REG
)
3510 if (GP_REG_P (REGNO (dest
)))
3511 return "move\t%0,%z1";
3513 if (MD_REG_P (REGNO (dest
)))
3516 if (DSP_ACC_REG_P (REGNO (dest
)))
3518 static char retval
[] = "mt__\t%z1,%q0";
3519 retval
[2] = reg_names
[REGNO (dest
)][4];
3520 retval
[3] = reg_names
[REGNO (dest
)][5];
3524 if (FP_REG_P (REGNO (dest
)))
3525 return (dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3527 if (ALL_COP_REG_P (REGNO (dest
)))
3529 static char retval
[] = "dmtc_\t%z1,%0";
3531 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
3532 return (dbl_p
? retval
: retval
+ 1);
3535 if (dest_code
== MEM
)
3536 return (dbl_p
? "sd\t%z1,%0" : "sw\t%z1,%0");
3538 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
3540 if (src_code
== REG
)
3542 if (DSP_ACC_REG_P (REGNO (src
)))
3544 static char retval
[] = "mf__\t%0,%q1";
3545 retval
[2] = reg_names
[REGNO (src
)][4];
3546 retval
[3] = reg_names
[REGNO (src
)][5];
3550 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
3551 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3553 if (FP_REG_P (REGNO (src
)))
3554 return (dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3556 if (ALL_COP_REG_P (REGNO (src
)))
3558 static char retval
[] = "dmfc_\t%0,%1";
3560 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
3561 return (dbl_p
? retval
: retval
+ 1);
3565 if (src_code
== MEM
)
3566 return (dbl_p
? "ld\t%0,%1" : "lw\t%0,%1");
3568 if (src_code
== CONST_INT
)
3570 /* Don't use the X format, because that will give out of
3571 range numbers for 64-bit hosts and 32-bit targets. */
3573 return "li\t%0,%1\t\t\t# %X1";
3575 if (INTVAL (src
) >= 0 && INTVAL (src
) <= 0xffff)
3578 if (INTVAL (src
) < 0 && INTVAL (src
) >= -0xffff)
3582 if (src_code
== HIGH
)
3583 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
3585 if (CONST_GP_P (src
))
3586 return "move\t%0,%1";
3588 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
3589 && mips_lo_relocs
[symbol_type
] != 0)
3591 /* A signed 16-bit constant formed by applying a relocation
3592 operator to a symbolic address. */
3593 gcc_assert (!mips_split_p
[symbol_type
]);
3594 return "li\t%0,%R1";
3597 if (symbolic_operand (src
, VOIDmode
))
3599 gcc_assert (TARGET_MIPS16
3600 ? TARGET_MIPS16_TEXT_LOADS
3601 : !TARGET_EXPLICIT_RELOCS
);
3602 return (dbl_p
? "dla\t%0,%1" : "la\t%0,%1");
3605 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
3607 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
3609 if (GET_MODE (dest
) == V2SFmode
)
3610 return "mov.ps\t%0,%1";
3612 return (dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3615 if (dest_code
== MEM
)
3616 return (dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0");
3618 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
3620 if (src_code
== MEM
)
3621 return (dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3623 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
3625 static char retval
[] = "l_c_\t%0,%1";
3627 retval
[1] = (dbl_p
? 'd' : 'w');
3628 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
3631 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
3633 static char retval
[] = "s_c_\t%1,%0";
3635 retval
[1] = (dbl_p
? 'd' : 'w');
3636 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
3642 /* Return true if CMP1 is a suitable second operand for relational
3643 operator CODE. See also the *sCC patterns in mips.md. */
3646 mips_relational_operand_ok_p (enum rtx_code code
, rtx cmp1
)
3652 return reg_or_0_operand (cmp1
, VOIDmode
);
3656 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
3660 return arith_operand (cmp1
, VOIDmode
);
3663 return sle_operand (cmp1
, VOIDmode
);
3666 return sleu_operand (cmp1
, VOIDmode
);
3673 /* Canonicalize LE or LEU comparisons into LT comparisons when
3674 possible to avoid extra instructions or inverting the
3678 mips_canonicalize_comparison (enum rtx_code
*code
, rtx
*cmp1
,
3679 enum machine_mode mode
)
3681 HOST_WIDE_INT plus_one
;
3683 if (mips_relational_operand_ok_p (*code
, *cmp1
))
3686 if (GET_CODE (*cmp1
) == CONST_INT
)
3690 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
3691 if (INTVAL (*cmp1
) < plus_one
)
3694 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3700 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
3704 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3715 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3716 result in TARGET. CMP0 and TARGET are register_operands that have
3717 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3718 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3721 mips_emit_int_relational (enum rtx_code code
, bool *invert_ptr
,
3722 rtx target
, rtx cmp0
, rtx cmp1
)
3724 /* First see if there is a MIPS instruction that can do this operation.
3725 If not, try doing the same for the inverse operation. If that also
3726 fails, force CMP1 into a register and try again. */
3727 if (mips_canonicalize_comparison (&code
, &cmp1
, GET_MODE (target
)))
3728 mips_emit_binary (code
, target
, cmp0
, cmp1
);
3731 enum rtx_code inv_code
= reverse_condition (code
);
3732 if (!mips_canonicalize_comparison (&inv_code
, &cmp1
, GET_MODE (target
)))
3734 cmp1
= force_reg (GET_MODE (cmp0
), cmp1
);
3735 mips_emit_int_relational (code
, invert_ptr
, target
, cmp0
, cmp1
);
3737 else if (invert_ptr
== 0)
3739 rtx inv_target
= gen_reg_rtx (GET_MODE (target
));
3740 mips_emit_binary (inv_code
, inv_target
, cmp0
, cmp1
);
3741 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
3745 *invert_ptr
= !*invert_ptr
;
3746 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
3751 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3752 The register will have the same mode as CMP0. */
3755 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
3757 if (cmp1
== const0_rtx
)
3760 if (uns_arith_operand (cmp1
, VOIDmode
))
3761 return expand_binop (GET_MODE (cmp0
), xor_optab
,
3762 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3764 return expand_binop (GET_MODE (cmp0
), sub_optab
,
3765 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3768 /* Convert *CODE into a code that can be used in a floating-point
3769 scc instruction (c.<cond>.<fmt>). Return true if the values of
3770 the condition code registers will be inverted, with 0 indicating
3771 that the condition holds. */
3774 mips_reverse_fp_cond_p (enum rtx_code
*code
)
3781 *code
= reverse_condition_maybe_unordered (*code
);
3789 /* Convert a comparison into something that can be used in a branch or
3790 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3791 being compared and *CODE is the code used to compare them.
3793 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3794 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3795 otherwise any standard branch condition can be used. The standard branch
3798 - EQ/NE between two registers.
3799 - any comparison between a register and zero. */
3802 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
3804 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) == MODE_INT
)
3806 if (!need_eq_ne_p
&& cmp_operands
[1] == const0_rtx
)
3808 *op0
= cmp_operands
[0];
3809 *op1
= cmp_operands
[1];
3811 else if (*code
== EQ
|| *code
== NE
)
3815 *op0
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3820 *op0
= cmp_operands
[0];
3821 *op1
= force_reg (GET_MODE (*op0
), cmp_operands
[1]);
3826 /* The comparison needs a separate scc instruction. Store the
3827 result of the scc in *OP0 and compare it against zero. */
3828 bool invert
= false;
3829 *op0
= gen_reg_rtx (GET_MODE (cmp_operands
[0]));
3831 mips_emit_int_relational (*code
, &invert
, *op0
,
3832 cmp_operands
[0], cmp_operands
[1]);
3833 *code
= (invert
? EQ
: NE
);
3836 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands
[0])))
3838 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
3839 mips_emit_binary (*code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3845 enum rtx_code cmp_code
;
3847 /* Floating-point tests use a separate c.cond.fmt comparison to
3848 set a condition code register. The branch or conditional move
3849 will then compare that register against zero.
3851 Set CMP_CODE to the code of the comparison instruction and
3852 *CODE to the code that the branch or move should use. */
3854 *code
= mips_reverse_fp_cond_p (&cmp_code
) ? EQ
: NE
;
3856 ? gen_reg_rtx (CCmode
)
3857 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
3859 mips_emit_binary (cmp_code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3863 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3864 Store the result in TARGET and return true if successful.
3866 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3869 mips_emit_scc (enum rtx_code code
, rtx target
)
3871 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) != MODE_INT
)
3874 target
= gen_lowpart (GET_MODE (cmp_operands
[0]), target
);
3875 if (code
== EQ
|| code
== NE
)
3877 rtx zie
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3878 mips_emit_binary (code
, target
, zie
, const0_rtx
);
3881 mips_emit_int_relational (code
, 0, target
,
3882 cmp_operands
[0], cmp_operands
[1]);
3886 /* Emit the common code for doing conditional branches.
3887 operand[0] is the label to jump to.
3888 The comparison operands are saved away by cmp{si,di,sf,df}. */
3891 gen_conditional_branch (rtx
*operands
, enum rtx_code code
)
3893 rtx op0
, op1
, condition
;
3895 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
3896 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3897 emit_jump_insn (gen_condjump (condition
, operands
[0]));
3902 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3903 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3906 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
3907 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
3912 reversed_p
= mips_reverse_fp_cond_p (&cond
);
3913 cmp_result
= gen_reg_rtx (CCV2mode
);
3914 emit_insn (gen_scc_ps (cmp_result
,
3915 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
3917 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
3920 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
3924 /* Emit the common code for conditional moves. OPERANDS is the array
3925 of operands passed to the conditional move define_expand. */
3928 gen_conditional_move (rtx
*operands
)
3933 code
= GET_CODE (operands
[1]);
3934 mips_emit_compare (&code
, &op0
, &op1
, true);
3935 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
3936 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
3937 gen_rtx_fmt_ee (code
,
3940 operands
[2], operands
[3])));
3943 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3944 the conditional_trap expander. */
3947 mips_gen_conditional_trap (rtx
*operands
)
3950 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3951 enum machine_mode mode
= GET_MODE (cmp_operands
[0]);
3953 /* MIPS conditional trap machine instructions don't have GT or LE
3954 flavors, so we must invert the comparison and convert to LT and
3955 GE, respectively. */
3958 case GT
: cmp_code
= LT
; break;
3959 case LE
: cmp_code
= GE
; break;
3960 case GTU
: cmp_code
= LTU
; break;
3961 case LEU
: cmp_code
= GEU
; break;
3964 if (cmp_code
== GET_CODE (operands
[0]))
3966 op0
= cmp_operands
[0];
3967 op1
= cmp_operands
[1];
3971 op0
= cmp_operands
[1];
3972 op1
= cmp_operands
[0];
3974 op0
= force_reg (mode
, op0
);
3975 if (!arith_operand (op1
, mode
))
3976 op1
= force_reg (mode
, op1
);
3978 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3979 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
),
3983 /* Argument support functions. */
3985 /* Initialize CUMULATIVE_ARGS for a function. */
3988 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
3989 rtx libname ATTRIBUTE_UNUSED
)
3991 static CUMULATIVE_ARGS zero_cum
;
3992 tree param
, next_param
;
3995 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
3997 /* Determine if this function has variable arguments. This is
3998 indicated by the last argument being 'void_type_mode' if there
3999 are no variable arguments. The standard MIPS calling sequence
4000 passes all arguments in the general purpose registers in this case. */
4002 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
4003 param
!= 0; param
= next_param
)
4005 next_param
= TREE_CHAIN (param
);
4006 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
4007 cum
->gp_reg_found
= 1;
4012 /* Fill INFO with information about a single argument. CUM is the
4013 cumulative state for earlier arguments. MODE is the mode of this
4014 argument and TYPE is its type (if known). NAMED is true if this
4015 is a named (fixed) argument rather than a variable one. */
4018 mips_arg_info (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4019 tree type
, int named
, struct mips_arg_info
*info
)
4021 bool doubleword_aligned_p
;
4022 unsigned int num_bytes
, num_words
, max_regs
;
4024 /* Work out the size of the argument. */
4025 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4026 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4028 /* Decide whether it should go in a floating-point register, assuming
4029 one is free. Later code checks for availability.
4031 The checks against UNITS_PER_FPVALUE handle the soft-float and
4032 single-float cases. */
4036 /* The EABI conventions have traditionally been defined in terms
4037 of TYPE_MODE, regardless of the actual type. */
4038 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4039 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4040 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4045 /* Only leading floating-point scalars are passed in
4046 floating-point registers. We also handle vector floats the same
4047 say, which is OK because they are not covered by the standard ABI. */
4048 info
->fpr_p
= (!cum
->gp_reg_found
4049 && cum
->arg_number
< 2
4050 && (type
== 0 || SCALAR_FLOAT_TYPE_P (type
)
4051 || VECTOR_FLOAT_TYPE_P (type
))
4052 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4053 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4054 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4059 /* Scalar and complex floating-point types are passed in
4060 floating-point registers. */
4061 info
->fpr_p
= (named
4062 && (type
== 0 || FLOAT_TYPE_P (type
))
4063 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4064 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4065 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4066 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4068 /* ??? According to the ABI documentation, the real and imaginary
4069 parts of complex floats should be passed in individual registers.
4070 The real and imaginary parts of stack arguments are supposed
4071 to be contiguous and there should be an extra word of padding
4074 This has two problems. First, it makes it impossible to use a
4075 single "void *" va_list type, since register and stack arguments
4076 are passed differently. (At the time of writing, MIPSpro cannot
4077 handle complex float varargs correctly.) Second, it's unclear
4078 what should happen when there is only one register free.
4080 For now, we assume that named complex floats should go into FPRs
4081 if there are two FPRs free, otherwise they should be passed in the
4082 same way as a struct containing two floats. */
4084 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4085 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4087 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4088 info
->fpr_p
= false;
4098 /* See whether the argument has doubleword alignment. */
4099 doubleword_aligned_p
= FUNCTION_ARG_BOUNDARY (mode
, type
) > BITS_PER_WORD
;
4101 /* Set REG_OFFSET to the register count we're interested in.
4102 The EABI allocates the floating-point registers separately,
4103 but the other ABIs allocate them like integer registers. */
4104 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4108 /* Advance to an even register if the argument is doubleword-aligned. */
4109 if (doubleword_aligned_p
)
4110 info
->reg_offset
+= info
->reg_offset
& 1;
4112 /* Work out the offset of a stack argument. */
4113 info
->stack_offset
= cum
->stack_words
;
4114 if (doubleword_aligned_p
)
4115 info
->stack_offset
+= info
->stack_offset
& 1;
4117 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4119 /* Partition the argument between registers and stack. */
4120 info
->reg_words
= MIN (num_words
, max_regs
);
4121 info
->stack_words
= num_words
- info
->reg_words
;
4124 /* INFO describes an argument that is passed in a single-register value.
4125 Return the register it uses, assuming that FPRs are available if
4129 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4131 if (!info
->fpr_p
|| !hard_float_p
)
4132 return GP_ARG_FIRST
+ info
->reg_offset
;
4133 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4134 /* In o32, the second argument is always passed in $f14
4135 for TARGET_DOUBLE_FLOAT, regardless of whether the
4136 first argument was a word or doubleword. */
4137 return FP_ARG_FIRST
+ 2;
4139 return FP_ARG_FIRST
+ info
->reg_offset
;
4143 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4145 return !TARGET_OLDABI
;
4148 /* Implement FUNCTION_ARG. */
4151 function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4152 tree type
, int named
)
4154 struct mips_arg_info info
;
4156 /* We will be called with a mode of VOIDmode after the last argument
4157 has been seen. Whatever we return will be passed to the call
4158 insn. If we need a mips16 fp_code, return a REG with the code
4159 stored as the mode. */
4160 if (mode
== VOIDmode
)
4162 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4163 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4169 mips_arg_info (cum
, mode
, type
, named
, &info
);
4171 /* Return straight away if the whole argument is passed on the stack. */
4172 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4176 && TREE_CODE (type
) == RECORD_TYPE
4178 && TYPE_SIZE_UNIT (type
)
4179 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
4182 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4183 structure contains a double in its entirety, then that 64-bit
4184 chunk is passed in a floating point register. */
4187 /* First check to see if there is any such field. */
4188 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4189 if (TREE_CODE (field
) == FIELD_DECL
4190 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4191 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4192 && host_integerp (bit_position (field
), 0)
4193 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4198 /* Now handle the special case by returning a PARALLEL
4199 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4200 chunks are passed in registers. */
4202 HOST_WIDE_INT bitpos
;
4205 /* assign_parms checks the mode of ENTRY_PARM, so we must
4206 use the actual mode here. */
4207 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4210 field
= TYPE_FIELDS (type
);
4211 for (i
= 0; i
< info
.reg_words
; i
++)
4215 for (; field
; field
= TREE_CHAIN (field
))
4216 if (TREE_CODE (field
) == FIELD_DECL
4217 && int_bit_position (field
) >= bitpos
)
4221 && int_bit_position (field
) == bitpos
4222 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4223 && !TARGET_SOFT_FLOAT
4224 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4225 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4227 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4230 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4231 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4233 bitpos
+= BITS_PER_WORD
;
4239 /* Handle the n32/n64 conventions for passing complex floating-point
4240 arguments in FPR pairs. The real part goes in the lower register
4241 and the imaginary part goes in the upper register. */
4244 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4247 enum machine_mode inner
;
4250 inner
= GET_MODE_INNER (mode
);
4251 reg
= FP_ARG_FIRST
+ info
.reg_offset
;
4252 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4254 /* Real part in registers, imaginary part on stack. */
4255 gcc_assert (info
.stack_words
== info
.reg_words
);
4256 return gen_rtx_REG (inner
, reg
);
4260 gcc_assert (info
.stack_words
== 0);
4261 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4262 gen_rtx_REG (inner
, reg
),
4264 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4266 reg
+ info
.reg_words
/ 2),
4267 GEN_INT (GET_MODE_SIZE (inner
)));
4268 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4272 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4275 /* Implement FUNCTION_ARG_ADVANCE. */
4278 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4279 tree type
, int named
)
4281 struct mips_arg_info info
;
4283 mips_arg_info (cum
, mode
, type
, named
, &info
);
4286 cum
->gp_reg_found
= true;
4288 /* See the comment above the cumulative args structure in mips.h
4289 for an explanation of what this code does. It assumes the O32
4290 ABI, which passes at most 2 arguments in float registers. */
4291 if (cum
->arg_number
< 2 && info
.fpr_p
)
4292 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
4294 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4295 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4296 else if (info
.reg_words
> 0)
4297 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
4299 if (info
.stack_words
> 0)
4300 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4305 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4308 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
4309 enum machine_mode mode
, tree type
, bool named
)
4311 struct mips_arg_info info
;
4313 mips_arg_info (cum
, mode
, type
, named
, &info
);
4314 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
4318 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4319 PARM_BOUNDARY bits of alignment, but will be given anything up
4320 to STACK_BOUNDARY bits if the type requires it. */
4323 function_arg_boundary (enum machine_mode mode
, tree type
)
4325 unsigned int alignment
;
4327 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
4328 if (alignment
< PARM_BOUNDARY
)
4329 alignment
= PARM_BOUNDARY
;
4330 if (alignment
> STACK_BOUNDARY
)
4331 alignment
= STACK_BOUNDARY
;
4335 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4336 upward rather than downward. In other words, return true if the
4337 first byte of the stack slot has useful data, false if the last
4341 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
4343 /* On little-endian targets, the first byte of every stack argument
4344 is passed in the first byte of the stack slot. */
4345 if (!BYTES_BIG_ENDIAN
)
4348 /* Otherwise, integral types are padded downward: the last byte of a
4349 stack argument is passed in the last byte of the stack slot. */
4351 ? (INTEGRAL_TYPE_P (type
)
4352 || POINTER_TYPE_P (type
)
4353 || FIXED_POINT_TYPE_P (type
))
4354 : (GET_MODE_CLASS (mode
) == MODE_INT
4355 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
4358 /* Big-endian o64 pads floating-point arguments downward. */
4359 if (mips_abi
== ABI_O64
)
4360 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4363 /* Other types are padded upward for o32, o64, n32 and n64. */
4364 if (mips_abi
!= ABI_EABI
)
4367 /* Arguments smaller than a stack slot are padded downward. */
4368 if (mode
!= BLKmode
)
4369 return (GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
);
4371 return (int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
));
4375 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4376 if the least significant byte of the register has useful data. Return
4377 the opposite if the most significant byte does. */
4380 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
4382 /* No shifting is required for floating-point arguments. */
4383 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4384 return !BYTES_BIG_ENDIAN
;
4386 /* Otherwise, apply the same padding to register arguments as we do
4387 to stack arguments. */
4388 return mips_pad_arg_upward (mode
, type
);
4392 /* Return nonzero when an argument must be passed by reference. */
4395 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4396 enum machine_mode mode
, const_tree type
,
4397 bool named ATTRIBUTE_UNUSED
)
4399 if (mips_abi
== ABI_EABI
)
4403 /* ??? How should SCmode be handled? */
4404 if (mode
== DImode
|| mode
== DFmode
4405 || mode
== DQmode
|| mode
== UDQmode
4406 || mode
== DAmode
|| mode
== UDAmode
)
4409 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4410 return size
== -1 || size
> UNITS_PER_WORD
;
4414 /* If we have a variable-sized parameter, we have no choice. */
4415 return targetm
.calls
.must_pass_in_stack (mode
, type
);
4420 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4421 enum machine_mode mode ATTRIBUTE_UNUSED
,
4422 const_tree type ATTRIBUTE_UNUSED
, bool named
)
4424 return mips_abi
== ABI_EABI
&& named
;
4427 /* See whether VALTYPE is a record whose fields should be returned in
4428 floating-point registers. If so, return the number of fields and
4429 list them in FIELDS (which should have two elements). Return 0
4432 For n32 & n64, a structure with one or two fields is returned in
4433 floating-point registers as long as every field has a floating-point
4437 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
4445 if (TREE_CODE (valtype
) != RECORD_TYPE
)
4449 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= TREE_CHAIN (field
))
4451 if (TREE_CODE (field
) != FIELD_DECL
)
4454 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
)
4460 fields
[i
++] = field
;
4466 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4467 a value in the most significant part of $2/$3 if:
4469 - the target is big-endian;
4471 - the value has a structure or union type (we generalize this to
4472 cover aggregates from other languages too); and
4474 - the structure is not returned in floating-point registers. */
4477 mips_return_in_msb (const_tree valtype
)
4481 return (TARGET_NEWABI
4482 && TARGET_BIG_ENDIAN
4483 && AGGREGATE_TYPE_P (valtype
)
4484 && mips_fpr_return_fields (valtype
, fields
) == 0);
4488 /* Return true if the function return value MODE will get returned in a
4489 floating-point register. */
4492 mips_return_mode_in_fpr_p (enum machine_mode mode
)
4494 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4495 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
4496 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4497 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
4500 /* Return a composite value in a pair of floating-point registers.
4501 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4502 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4505 For n32 & n64, $f0 always holds the first value and $f2 the second.
4506 Otherwise the values are packed together as closely as possible. */
4509 mips_return_fpr_pair (enum machine_mode mode
,
4510 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
4511 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
4515 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
4516 return gen_rtx_PARALLEL
4519 gen_rtx_EXPR_LIST (VOIDmode
,
4520 gen_rtx_REG (mode1
, FP_RETURN
),
4522 gen_rtx_EXPR_LIST (VOIDmode
,
4523 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
4524 GEN_INT (offset2
))));
4529 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4530 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4531 VALTYPE is null and MODE is the mode of the return value. */
4534 mips_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
4535 enum machine_mode mode
)
4542 mode
= TYPE_MODE (valtype
);
4543 unsignedp
= TYPE_UNSIGNED (valtype
);
4545 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
4546 true, we must promote the mode just as PROMOTE_MODE does. */
4547 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
4549 /* Handle structures whose fields are returned in $f0/$f2. */
4550 switch (mips_fpr_return_fields (valtype
, fields
))
4553 return gen_rtx_REG (mode
, FP_RETURN
);
4556 return mips_return_fpr_pair (mode
,
4557 TYPE_MODE (TREE_TYPE (fields
[0])),
4558 int_byte_position (fields
[0]),
4559 TYPE_MODE (TREE_TYPE (fields
[1])),
4560 int_byte_position (fields
[1]));
4563 /* If a value is passed in the most significant part of a register, see
4564 whether we have to round the mode up to a whole number of words. */
4565 if (mips_return_in_msb (valtype
))
4567 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
4568 if (size
% UNITS_PER_WORD
!= 0)
4570 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
4571 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
4575 /* For EABI, the class of return register depends entirely on MODE.
4576 For example, "struct { some_type x; }" and "union { some_type x; }"
4577 are returned in the same way as a bare "some_type" would be.
4578 Other ABIs only use FPRs for scalar, complex or vector types. */
4579 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
4580 return gen_rtx_REG (mode
, GP_RETURN
);
4585 /* Handle long doubles for n32 & n64. */
4587 return mips_return_fpr_pair (mode
,
4589 DImode
, GET_MODE_SIZE (mode
) / 2);
4591 if (mips_return_mode_in_fpr_p (mode
))
4593 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4594 return mips_return_fpr_pair (mode
,
4595 GET_MODE_INNER (mode
), 0,
4596 GET_MODE_INNER (mode
),
4597 GET_MODE_SIZE (mode
) / 2);
4599 return gen_rtx_REG (mode
, FP_RETURN
);
4603 return gen_rtx_REG (mode
, GP_RETURN
);
4606 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
4607 all BLKmode objects are returned in memory. Under the new (N32 and
4608 64-bit MIPS ABIs) small structures are returned in a register.
4609 Objects with varying size must still be returned in memory, of
4613 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
4616 return (TYPE_MODE (type
) == BLKmode
);
4618 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
4619 || (int_size_in_bytes (type
) == -1));
4623 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4624 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
4627 CUMULATIVE_ARGS local_cum
;
4628 int gp_saved
, fp_saved
;
4630 /* The caller has advanced CUM up to, but not beyond, the last named
4631 argument. Advance a local copy of CUM past the last "real" named
4632 argument, to find out how many registers are left over. */
4635 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
4637 /* Found out how many registers we need to save. */
4638 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4639 fp_saved
= (EABI_FLOAT_VARARGS_P
4640 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4649 ptr
= plus_constant (virtual_incoming_args_rtx
,
4650 REG_PARM_STACK_SPACE (cfun
->decl
)
4651 - gp_saved
* UNITS_PER_WORD
);
4652 mem
= gen_frame_mem (BLKmode
, ptr
);
4653 set_mem_alias_set (mem
, get_varargs_alias_set ());
4655 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
4660 /* We can't use move_block_from_reg, because it will use
4662 enum machine_mode mode
;
4665 /* Set OFF to the offset from virtual_incoming_args_rtx of
4666 the first float register. The FP save area lies below
4667 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4668 off
= -gp_saved
* UNITS_PER_WORD
;
4669 off
&= ~(UNITS_PER_FPVALUE
- 1);
4670 off
-= fp_saved
* UNITS_PER_FPREG
;
4672 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4674 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
4675 i
+= MAX_FPRS_PER_FMT
)
4679 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4680 mem
= gen_frame_mem (mode
, ptr
);
4681 set_mem_alias_set (mem
, get_varargs_alias_set ());
4682 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4683 off
+= UNITS_PER_HWFPVALUE
;
4687 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
4688 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
4689 + fp_saved
* UNITS_PER_FPREG
);
4692 /* Create the va_list data type.
4693 We keep 3 pointers, and two offsets.
4694 Two pointers are to the overflow area, which starts at the CFA.
4695 One of these is constant, for addressing into the GPR save area below it.
4696 The other is advanced up the stack through the overflow region.
4697 The third pointer is to the GPR save area. Since the FPR save area
4698 is just below it, we can address FPR slots off this pointer.
4699 We also keep two one-byte offsets, which are to be subtracted from the
4700 constant pointers to yield addresses in the GPR and FPR save areas.
4701 These are downcounted as float or non-float arguments are used,
4702 and when they get to zero, the argument must be obtained from the
4704 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4705 pointer is enough. It's started at the GPR save area, and is
4707 Note that the GPR save area is not constant size, due to optimization
4708 in the prologue. Hence, we can't use a design with two pointers
4709 and two offsets, although we could have designed this with two pointers
4710 and three offsets. */
4713 mips_build_builtin_va_list (void)
4715 if (EABI_FLOAT_VARARGS_P
)
4717 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
4720 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
4722 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4724 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4726 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4728 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4729 unsigned_char_type_node
);
4730 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4731 unsigned_char_type_node
);
4732 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4733 warn on every user file. */
4734 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
4735 array
= build_array_type (unsigned_char_type_node
,
4736 build_index_type (index
));
4737 f_res
= build_decl (FIELD_DECL
, get_identifier ("__reserved"), array
);
4739 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4740 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4741 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4742 DECL_FIELD_CONTEXT (f_goff
) = record
;
4743 DECL_FIELD_CONTEXT (f_foff
) = record
;
4744 DECL_FIELD_CONTEXT (f_res
) = record
;
4746 TYPE_FIELDS (record
) = f_ovfl
;
4747 TREE_CHAIN (f_ovfl
) = f_gtop
;
4748 TREE_CHAIN (f_gtop
) = f_ftop
;
4749 TREE_CHAIN (f_ftop
) = f_goff
;
4750 TREE_CHAIN (f_goff
) = f_foff
;
4751 TREE_CHAIN (f_foff
) = f_res
;
4753 layout_type (record
);
4756 else if (TARGET_IRIX
&& TARGET_IRIX6
)
4757 /* On IRIX 6, this type is 'char *'. */
4758 return build_pointer_type (char_type_node
);
4760 /* Otherwise, we use 'void *'. */
4761 return ptr_type_node
;
4764 /* Implement va_start. */
4767 mips_va_start (tree valist
, rtx nextarg
)
4769 if (EABI_FLOAT_VARARGS_P
)
4771 const CUMULATIVE_ARGS
*cum
;
4772 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4773 tree ovfl
, gtop
, ftop
, goff
, foff
;
4775 int gpr_save_area_size
;
4776 int fpr_save_area_size
;
4779 cum
= ¤t_function_args_info
;
4781 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4783 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4785 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4786 f_gtop
= TREE_CHAIN (f_ovfl
);
4787 f_ftop
= TREE_CHAIN (f_gtop
);
4788 f_goff
= TREE_CHAIN (f_ftop
);
4789 f_foff
= TREE_CHAIN (f_goff
);
4791 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4793 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4795 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4797 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4799 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4802 /* Emit code to initialize OVFL, which points to the next varargs
4803 stack argument. CUM->STACK_WORDS gives the number of stack
4804 words used by named arguments. */
4805 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4806 if (cum
->stack_words
> 0)
4807 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4808 size_int (cum
->stack_words
* UNITS_PER_WORD
));
4809 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
4810 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4812 /* Emit code to initialize GTOP, the top of the GPR save area. */
4813 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4814 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gtop
), gtop
, t
);
4815 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4817 /* Emit code to initialize FTOP, the top of the FPR save area.
4818 This address is gpr_save_area_bytes below GTOP, rounded
4819 down to the next fp-aligned boundary. */
4820 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4821 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4822 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
4824 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4825 size_int (-fpr_offset
));
4826 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ftop
), ftop
, t
);
4827 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4829 /* Emit code to initialize GOFF, the offset from GTOP of the
4830 next GPR argument. */
4831 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (goff
), goff
,
4832 build_int_cst (NULL_TREE
, gpr_save_area_size
));
4833 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4835 /* Likewise emit code to initialize FOFF, the offset from FTOP
4836 of the next FPR argument. */
4837 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (foff
), foff
,
4838 build_int_cst (NULL_TREE
, fpr_save_area_size
));
4839 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4843 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
4844 std_expand_builtin_va_start (valist
, nextarg
);
4848 /* Implement va_arg. */
4851 mips_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
4853 HOST_WIDE_INT size
, rsize
;
4857 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4860 type
= build_pointer_type (type
);
4862 size
= int_size_in_bytes (type
);
4863 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4865 if (mips_abi
!= ABI_EABI
|| !EABI_FLOAT_VARARGS_P
)
4866 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
4869 /* Not a simple merged stack. */
4871 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4872 tree ovfl
, top
, off
, align
;
4873 HOST_WIDE_INT osize
;
4876 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4877 f_gtop
= TREE_CHAIN (f_ovfl
);
4878 f_ftop
= TREE_CHAIN (f_gtop
);
4879 f_goff
= TREE_CHAIN (f_ftop
);
4880 f_foff
= TREE_CHAIN (f_goff
);
4882 /* We maintain separate pointers and offsets for floating-point
4883 and integer arguments, but we need similar code in both cases.
4886 TOP be the top of the register save area;
4887 OFF be the offset from TOP of the next register;
4888 ADDR_RTX be the address of the argument;
4889 RSIZE be the number of bytes used to store the argument
4890 when it's in the register save area;
4891 OSIZE be the number of bytes used to store it when it's
4892 in the stack overflow area; and
4893 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4895 The code we want is:
4897 1: off &= -rsize; // round down
4900 4: addr_rtx = top - off;
4905 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4906 10: addr_rtx = ovfl + PADDING;
4910 [1] and [9] can sometimes be optimized away. */
4912 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4915 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
4916 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
4918 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4920 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4923 /* When floating-point registers are saved to the stack,
4924 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4925 of the float's precision. */
4926 rsize
= UNITS_PER_HWFPVALUE
;
4928 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4929 (= PARM_BOUNDARY bits). This can be different from RSIZE
4932 (1) On 32-bit targets when TYPE is a structure such as:
4934 struct s { float f; };
4936 Such structures are passed in paired FPRs, so RSIZE
4937 will be 8 bytes. However, the structure only takes
4938 up 4 bytes of memory, so OSIZE will only be 4.
4940 (2) In combinations such as -mgp64 -msingle-float
4941 -fshort-double. Doubles passed in registers
4942 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4943 but those passed on the stack take up
4944 UNITS_PER_WORD bytes. */
4945 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
4949 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4951 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4953 if (rsize
> UNITS_PER_WORD
)
4955 /* [1] Emit code for: off &= -rsize. */
4956 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
4957 build_int_cst (NULL_TREE
, -rsize
));
4958 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (off
), off
, t
);
4959 gimplify_and_add (t
, pre_p
);
4964 /* [2] Emit code to branch if off == 0. */
4965 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
4966 build_int_cst (TREE_TYPE (off
), 0));
4967 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
4969 /* [5] Emit code for: off -= rsize. We do this as a form of
4970 post-increment not available to C. Also widen for the
4971 coming pointer arithmetic. */
4972 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
4973 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
4974 t
= fold_convert (sizetype
, t
);
4975 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
4977 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4978 the argument has RSIZE - SIZE bytes of leading padding. */
4979 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (top
), top
, t
);
4980 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
4982 u
= size_int (rsize
- size
);
4983 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
4985 COND_EXPR_THEN (addr
) = t
;
4987 if (osize
> UNITS_PER_WORD
)
4989 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4990 u
= size_int (osize
- 1);
4991 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
4992 t
= fold_convert (sizetype
, t
);
4993 u
= size_int (-osize
);
4994 t
= build2 (BIT_AND_EXPR
, sizetype
, t
, u
);
4995 t
= fold_convert (TREE_TYPE (ovfl
), t
);
4996 align
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
5001 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
5002 post-increment ovfl by osize. On big-endian machines,
5003 the argument has OSIZE - SIZE bytes of leading padding. */
5004 u
= fold_convert (TREE_TYPE (ovfl
),
5005 build_int_cst (NULL_TREE
, osize
));
5006 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5007 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5009 u
= size_int (osize
- size
);
5010 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5013 /* String [9] and [10,11] together. */
5015 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5016 COND_EXPR_ELSE (addr
) = t
;
5018 addr
= fold_convert (build_pointer_type (type
), addr
);
5019 addr
= build_va_arg_indirect_ref (addr
);
5023 addr
= build_va_arg_indirect_ref (addr
);
5028 /* We keep a list of functions for which we have already built stubs
5029 in build_mips16_call_stub. */
5033 struct mips16_stub
*next
;
5038 static struct mips16_stub
*mips16_stubs
;
5040 /* Return a two-character string representing a function floating-point
5041 return mode, used to name MIPS16 function stubs. */
5044 mips16_call_stub_mode_suffix (enum machine_mode mode
)
5048 else if (mode
== DFmode
)
5050 else if (mode
== SCmode
)
5052 else if (mode
== DCmode
)
5054 else if (mode
== V2SFmode
)
5060 /* Write instructions to move a 32-bit value between general register
5061 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5062 from GPREG to FPREG and 'f' to move in the opposite direction. */
5065 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5067 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5068 reg_names
[gpreg
], reg_names
[fpreg
]);
5071 /* Likewise for 64-bit values. */
5074 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5077 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
5078 reg_names
[gpreg
], reg_names
[fpreg
]);
5079 else if (TARGET_FLOAT64
)
5081 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5082 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5083 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
5084 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
5088 /* Move the least-significant word. */
5089 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5090 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5091 /* ...then the most significant word. */
5092 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5093 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
5097 /* Write out code to move floating-point arguments into or out of
5098 general registers. FP_CODE is the code describing which arguments
5099 are present (see the comment above the definition of CUMULATIVE_ARGS
5100 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5103 mips_output_args_xfer (int fp_code
, char direction
)
5105 unsigned int gparg
, fparg
, f
;
5106 CUMULATIVE_ARGS cum
;
5108 /* This code only works for the original 32-bit ABI and the O64 ABI. */
5109 gcc_assert (TARGET_OLDABI
);
5111 init_cumulative_args (&cum
, NULL
, NULL
);
5113 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5115 enum machine_mode mode
;
5116 struct mips_arg_info info
;
5120 else if ((f
& 3) == 2)
5125 mips_arg_info (&cum
, mode
, NULL
, true, &info
);
5126 gparg
= mips_arg_regno (&info
, false);
5127 fparg
= mips_arg_regno (&info
, true);
5130 mips_output_32bit_xfer (direction
, gparg
, fparg
);
5132 mips_output_64bit_xfer (direction
, gparg
, fparg
);
5134 function_arg_advance (&cum
, mode
, NULL
, true);
5138 /* Build a mips16 function stub. This is used for functions which
5139 take arguments in the floating point registers. It is 32-bit code
5140 that moves the floating point args into the general registers, and
5141 then jumps to the 16-bit code. */
5144 build_mips16_function_stub (void)
5147 char *secname
, *stubname
;
5148 tree stubid
, stubdecl
;
5152 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5153 fnname
= targetm
.strip_name_encoding (fnname
);
5154 secname
= (char *) alloca (strlen (fnname
) + 20);
5155 sprintf (secname
, ".mips16.fn.%s", fnname
);
5156 stubname
= (char *) alloca (strlen (fnname
) + 20);
5157 sprintf (stubname
, "__fn_stub_%s", fnname
);
5158 stubid
= get_identifier (stubname
);
5159 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
5160 build_function_type (void_type_node
, NULL_TREE
));
5161 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5162 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
, void_type_node
);
5164 fprintf (asm_out_file
, "\t# Stub function for %s (",
5165 current_function_name ());
5167 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
5169 fprintf (asm_out_file
, "%s%s",
5170 need_comma
? ", " : "",
5171 (f
& 3) == 1 ? "float" : "double");
5174 fprintf (asm_out_file
, ")\n");
5176 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5177 switch_to_section (function_section (stubdecl
));
5178 ASM_OUTPUT_ALIGN (asm_out_file
,
5179 floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
5181 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5182 within a .ent, and we cannot emit another .ent. */
5183 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5185 fputs ("\t.ent\t", asm_out_file
);
5186 assemble_name (asm_out_file
, stubname
);
5187 fputs ("\n", asm_out_file
);
5190 assemble_name (asm_out_file
, stubname
);
5191 fputs (":\n", asm_out_file
);
5193 /* Load the address of the MIPS16 function into $at. Do this first so
5194 that targets with coprocessor interlocks can use an MFC1 to fill the
5196 fprintf (asm_out_file
, "\t.set\tnoat\n");
5197 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
5198 assemble_name (asm_out_file
, fnname
);
5199 fprintf (asm_out_file
, "\n");
5201 mips_output_args_xfer (current_function_args_info
.fp_code
, 'f');
5203 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
5204 fprintf (asm_out_file
, "\t.set\tat\n");
5206 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5208 fputs ("\t.end\t", asm_out_file
);
5209 assemble_name (asm_out_file
, stubname
);
5210 fputs ("\n", asm_out_file
);
5213 switch_to_section (function_section (current_function_decl
));
5216 /* The current function is a MIPS16 function that returns a value in an FPR.
5217 Copy the return value from its soft-float to its hard-float location.
5218 libgcc2 has special non-MIPS16 helper functions for each case. */
5221 mips16_copy_fpr_return_value (void)
5223 rtx fn
, insn
, arg
, call
;
5224 tree id
, return_type
;
5225 enum machine_mode return_mode
;
5227 return_type
= DECL_RESULT (current_function_decl
);
5228 return_mode
= DECL_MODE (return_type
);
5230 id
= get_identifier (ACONCAT (("__mips16_ret_",
5231 mips16_call_stub_mode_suffix (return_mode
),
5233 fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
5234 arg
= gen_rtx_REG (return_mode
, GP_RETURN
);
5235 call
= gen_call_value_internal (arg
, fn
, const0_rtx
);
5236 insn
= emit_call_insn (call
);
5237 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), arg
);
5240 /* Build a call stub for a mips16 call. A stub is needed if we are
5241 passing any floating point values which should go into the floating
5242 point registers. If we are, and the call turns out to be to a
5243 32-bit function, the stub will be used to move the values into the
5244 floating point registers before calling the 32-bit function. The
5245 linker will magically adjust the function call to either the 16-bit
5246 function or the 32-bit stub, depending upon where the function call
5247 is actually defined.
5249 Similarly, we need a stub if the return value might come back in a
5250 floating point register.
5252 RETVAL is the location of the return value, or null if this is
5253 a call rather than a call_value. FN is the address of the
5254 function and ARG_SIZE is the size of the arguments. FP_CODE
5255 is the code built by function_arg. This function returns a nonzero
5256 value if it builds the call instruction itself. */
5259 build_mips16_call_stub (rtx retval
, rtx fn
, rtx arg_size
, int fp_code
)
5263 char *secname
, *stubname
;
5264 struct mips16_stub
*l
;
5265 tree stubid
, stubdecl
;
5270 /* We don't need to do anything if we aren't in mips16 mode, or if
5271 we were invoked with the -msoft-float option. */
5272 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
5275 /* Figure out whether the value might come back in a floating point
5278 fpret
= mips_return_mode_in_fpr_p (GET_MODE (retval
));
5280 /* We don't need to do anything if there were no floating point
5281 arguments and the value will not be returned in a floating point
5283 if (fp_code
== 0 && ! fpret
)
5286 /* We don't need to do anything if this is a call to a special
5287 mips16 support function. */
5288 if (GET_CODE (fn
) == SYMBOL_REF
5289 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
5292 /* This code will only work for o32 and o64 abis. The other ABI's
5293 require more sophisticated support. */
5294 gcc_assert (TARGET_OLDABI
);
5296 /* If we're calling via a function pointer, then we must always call
5297 via a stub. There are magic stubs provided in libgcc.a for each
5298 of the required cases. Each of them expects the function address
5299 to arrive in register $2. */
5301 if (GET_CODE (fn
) != SYMBOL_REF
)
5307 /* ??? If this code is modified to support other ABI's, we need
5308 to handle PARALLEL return values here. */
5311 sprintf (buf
, "__mips16_call_stub_%s_%d",
5312 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
5315 sprintf (buf
, "__mips16_call_stub_%d",
5318 id
= get_identifier (buf
);
5319 stub_fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
5321 mips_emit_move (gen_rtx_REG (Pmode
, 2), fn
);
5323 if (retval
== NULL_RTX
)
5324 insn
= gen_call_internal (stub_fn
, arg_size
);
5326 insn
= gen_call_value_internal (retval
, stub_fn
, arg_size
);
5327 insn
= emit_call_insn (insn
);
5329 /* Put the register usage information on the CALL. */
5330 CALL_INSN_FUNCTION_USAGE (insn
) =
5331 gen_rtx_EXPR_LIST (VOIDmode
,
5332 gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 2)),
5333 CALL_INSN_FUNCTION_USAGE (insn
));
5335 /* If we are handling a floating point return value, we need to
5336 save $18 in the function prologue. Putting a note on the
5337 call will mean that df_regs_ever_live_p ($18) will be true if the
5338 call is not eliminated, and we can check that in the prologue
5341 CALL_INSN_FUNCTION_USAGE (insn
) =
5342 gen_rtx_EXPR_LIST (VOIDmode
,
5343 gen_rtx_USE (VOIDmode
,
5344 gen_rtx_REG (word_mode
, 18)),
5345 CALL_INSN_FUNCTION_USAGE (insn
));
5347 /* Return 1 to tell the caller that we've generated the call
5352 /* We know the function we are going to call. If we have already
5353 built a stub, we don't need to do anything further. */
5355 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
5356 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
5357 if (strcmp (l
->name
, fnname
) == 0)
5362 /* Build a special purpose stub. When the linker sees a
5363 function call in mips16 code, it will check where the target
5364 is defined. If the target is a 32-bit call, the linker will
5365 search for the section defined here. It can tell which
5366 symbol this section is associated with by looking at the
5367 relocation information (the name is unreliable, since this
5368 might be a static function). If such a section is found, the
5369 linker will redirect the call to the start of the magic
5372 If the function does not return a floating point value, the
5373 special stub section is named
5376 If the function does return a floating point value, the stub
5378 .mips16.call.fp.FNNAME
5381 secname
= (char *) alloca (strlen (fnname
) + 40);
5382 sprintf (secname
, ".mips16.call.%s%s",
5385 stubname
= (char *) alloca (strlen (fnname
) + 20);
5386 sprintf (stubname
, "__call_stub_%s%s",
5389 stubid
= get_identifier (stubname
);
5390 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
5391 build_function_type (void_type_node
, NULL_TREE
));
5392 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5393 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
, void_type_node
);
5395 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
5397 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
5401 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5403 fprintf (asm_out_file
, "%s%s",
5404 need_comma
? ", " : "",
5405 (f
& 3) == 1 ? "float" : "double");
5408 fprintf (asm_out_file
, ")\n");
5410 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5411 assemble_start_function (stubdecl
, stubname
);
5413 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5415 fputs ("\t.ent\t", asm_out_file
);
5416 assemble_name (asm_out_file
, stubname
);
5417 fputs ("\n", asm_out_file
);
5419 assemble_name (asm_out_file
, stubname
);
5420 fputs (":\n", asm_out_file
);
5423 /* We build the stub code by hand. That's the only way we can
5424 do it, since we can't generate 32-bit code during a 16-bit
5429 /* Load the address of the MIPS16 function into $at. Do this
5430 first so that targets with coprocessor interlocks can use
5431 an MFC1 to fill the delay slot. */
5432 fprintf (asm_out_file
, "\t.set\tnoat\n");
5433 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
5437 mips_output_args_xfer (fp_code
, 't');
5441 /* Jump to the previously-loaded address. */
5442 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
5443 fprintf (asm_out_file
, "\t.set\tat\n");
5447 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
5448 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
5449 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
5450 switch (GET_MODE (retval
))
5453 mips_output_32bit_xfer ('f', GP_RETURN
+ 1,
5454 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
5457 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
5458 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
5460 /* On 64-bit targets, complex floats are returned in
5461 a single GPR, such that "sd" on a suitably-aligned
5462 target would store the value correctly. */
5463 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
5464 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
5465 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
5466 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
5467 reg_names
[GP_RETURN
],
5468 reg_names
[GP_RETURN
],
5469 reg_names
[GP_RETURN
+ 1]);
5474 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
5475 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
5479 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
5485 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
5488 #ifdef ASM_DECLARE_FUNCTION_SIZE
5489 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
5492 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5494 fputs ("\t.end\t", asm_out_file
);
5495 assemble_name (asm_out_file
, stubname
);
5496 fputs ("\n", asm_out_file
);
5499 /* Record this stub. */
5500 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
5501 l
->name
= xstrdup (fnname
);
5503 l
->next
= mips16_stubs
;
5507 /* If we expect a floating point return value, but we've built a
5508 stub which does not expect one, then we're in trouble. We can't
5509 use the existing stub, because it won't handle the floating point
5510 value. We can't build a new stub, because the linker won't know
5511 which stub to use for the various calls in this object file.
5512 Fortunately, this case is illegal, since it means that a function
5513 was declared in two different ways in a single compilation. */
5514 if (fpret
&& ! l
->fpret
)
5515 error ("cannot handle inconsistent calls to %qs", fnname
);
5517 if (retval
== NULL_RTX
)
5518 insn
= gen_call_internal_direct (fn
, arg_size
);
5520 insn
= gen_call_value_internal_direct (retval
, fn
, arg_size
);
5521 insn
= emit_call_insn (insn
);
5523 /* If we are calling a stub which handles a floating point return
5524 value, we need to arrange to save $18 in the prologue. We do
5525 this by marking the function call as using the register. The
5526 prologue will later see that it is used, and emit code to save
5529 CALL_INSN_FUNCTION_USAGE (insn
) =
5530 gen_rtx_EXPR_LIST (VOIDmode
,
5531 gen_rtx_USE (VOIDmode
, gen_rtx_REG (word_mode
, 18)),
5532 CALL_INSN_FUNCTION_USAGE (insn
));
5534 /* Return 1 to tell the caller that we've generated the call
5539 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5542 mips_ok_for_lazy_binding_p (rtx x
)
5544 return (TARGET_USE_GOT
5545 && GET_CODE (x
) == SYMBOL_REF
5546 && !mips_symbol_binds_local_p (x
));
5549 /* Load function address ADDR into register DEST. SIBCALL_P is true
5550 if the address is needed for a sibling call. Return true if we
5551 used an explicit lazy-binding sequence. */
5554 mips_load_call_address (rtx dest
, rtx addr
, int sibcall_p
)
5556 /* If we're generating PIC, and this call is to a global function,
5557 try to allow its address to be resolved lazily. This isn't
5558 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
5559 to the stub would be our caller's gp, not ours. */
5560 if (TARGET_EXPLICIT_RELOCS
5561 && !(sibcall_p
&& TARGET_CALL_SAVED_GP
)
5562 && mips_ok_for_lazy_binding_p (addr
))
5564 rtx high
, lo_sum_symbol
;
5566 high
= mips_unspec_offset_high (dest
, pic_offset_table_rtx
,
5567 addr
, SYMBOL_GOTOFF_CALL
);
5568 lo_sum_symbol
= mips_unspec_address (addr
, SYMBOL_GOTOFF_CALL
);
5569 if (Pmode
== SImode
)
5570 emit_insn (gen_load_callsi (dest
, high
, lo_sum_symbol
));
5572 emit_insn (gen_load_calldi (dest
, high
, lo_sum_symbol
));
5577 mips_emit_move (dest
, addr
);
5583 /* Expand a call or call_value instruction. RESULT is where the
5584 result will go (null for calls), ADDR is the address of the
5585 function, ARGS_SIZE is the size of the arguments and AUX is
5586 the value passed to us by mips_function_arg. SIBCALL_P is true
5587 if we are expanding a sibling call, false if we're expanding
5591 mips_expand_call (rtx result
, rtx addr
, rtx args_size
, rtx aux
, int sibcall_p
)
5593 rtx orig_addr
, pattern
, insn
;
5598 if (!call_insn_operand (addr
, VOIDmode
))
5600 addr
= gen_reg_rtx (Pmode
);
5601 lazy_p
= mips_load_call_address (addr
, orig_addr
, sibcall_p
);
5605 && TARGET_HARD_FLOAT_ABI
5606 && build_mips16_call_stub (result
, addr
, args_size
,
5607 aux
== 0 ? 0 : (int) GET_MODE (aux
)))
5611 pattern
= (sibcall_p
5612 ? gen_sibcall_internal (addr
, args_size
)
5613 : gen_call_internal (addr
, args_size
));
5614 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
5618 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
5619 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
5622 ? gen_sibcall_value_multiple_internal (reg1
, addr
, args_size
, reg2
)
5623 : gen_call_value_multiple_internal (reg1
, addr
, args_size
, reg2
));
5626 pattern
= (sibcall_p
5627 ? gen_sibcall_value_internal (result
, addr
, args_size
)
5628 : gen_call_value_internal (result
, addr
, args_size
));
5630 insn
= emit_call_insn (pattern
);
5632 /* Lazy-binding stubs require $gp to be valid on entry. We also pretend
5633 that they use FAKE_CALL_REGNO; see the load_call<mode> patterns for
5637 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
5638 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
5639 gen_rtx_REG (Pmode
, FAKE_CALL_REGNO
));
5644 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5647 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
5649 if (!TARGET_SIBCALLS
)
5652 /* We can't do a sibcall if the called function is a MIPS16 function
5653 because there is no direct "jx" instruction equivalent to "jalx" to
5654 switch the ISA mode. */
5655 if (mips_use_mips16_mode_p (decl
))
5658 /* ...and when -minterlink-mips16 is in effect, assume that external
5659 functions could be MIPS16 ones unless an attribute explicitly
5660 tells us otherwise. We only care about cases where the sibling
5661 and normal calls would both be direct. */
5662 if (TARGET_INTERLINK_MIPS16
5664 && DECL_EXTERNAL (decl
)
5665 && !mips_nomips16_decl_p (decl
)
5666 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
5673 /* Emit code to move general operand SRC into condition-code
5674 register DEST. SCRATCH is a scratch TFmode float register.
5681 where FP1 and FP2 are single-precision float registers
5682 taken from SCRATCH. */
5685 mips_emit_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
5689 /* Change the source to SFmode. */
5691 src
= adjust_address (src
, SFmode
, 0);
5692 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
5693 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
5695 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
5696 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
5698 mips_emit_move (copy_rtx (fp1
), src
);
5699 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
5700 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
5703 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5704 Assume that the areas do not overlap. */
5707 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
5709 HOST_WIDE_INT offset
, delta
;
5710 unsigned HOST_WIDE_INT bits
;
5712 enum machine_mode mode
;
5715 /* Work out how many bits to move at a time. If both operands have
5716 half-word alignment, it is usually better to move in half words.
5717 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5718 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5719 Otherwise move word-sized chunks. */
5720 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
5721 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
5722 bits
= BITS_PER_WORD
/ 2;
5724 bits
= BITS_PER_WORD
;
5726 mode
= mode_for_size (bits
, MODE_INT
, 0);
5727 delta
= bits
/ BITS_PER_UNIT
;
5729 /* Allocate a buffer for the temporary registers. */
5730 regs
= alloca (sizeof (rtx
) * length
/ delta
);
5732 /* Load as many BITS-sized chunks as possible. Use a normal load if
5733 the source has enough alignment, otherwise use left/right pairs. */
5734 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
5736 regs
[i
] = gen_reg_rtx (mode
);
5737 if (MEM_ALIGN (src
) >= bits
)
5738 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
5741 rtx part
= adjust_address (src
, BLKmode
, offset
);
5742 if (!mips_expand_unaligned_load (regs
[i
], part
, bits
, 0))
5747 /* Copy the chunks to the destination. */
5748 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
5749 if (MEM_ALIGN (dest
) >= bits
)
5750 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
5753 rtx part
= adjust_address (dest
, BLKmode
, offset
);
5754 if (!mips_expand_unaligned_store (part
, regs
[i
], bits
, 0))
5758 /* Mop up any left-over bytes. */
5759 if (offset
< length
)
5761 src
= adjust_address (src
, BLKmode
, offset
);
5762 dest
= adjust_address (dest
, BLKmode
, offset
);
5763 move_by_pieces (dest
, src
, length
- offset
,
5764 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
5768 #define MAX_MOVE_REGS 4
5769 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
5772 /* Helper function for doing a loop-based block operation on memory
5773 reference MEM. Each iteration of the loop will operate on LENGTH
5776 Create a new base register for use within the loop and point it to
5777 the start of MEM. Create a new memory reference that uses this
5778 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5781 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
5782 rtx
*loop_reg
, rtx
*loop_mem
)
5784 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
5786 /* Although the new mem does not refer to a known location,
5787 it does keep up to LENGTH bytes of alignment. */
5788 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
5789 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
5793 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
5794 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
5795 memory regions do not overlap. */
5798 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
)
5800 rtx label
, src_reg
, dest_reg
, final_src
;
5801 HOST_WIDE_INT leftover
;
5803 leftover
= length
% MAX_MOVE_BYTES
;
5806 /* Create registers and memory references for use within the loop. */
5807 mips_adjust_block_mem (src
, MAX_MOVE_BYTES
, &src_reg
, &src
);
5808 mips_adjust_block_mem (dest
, MAX_MOVE_BYTES
, &dest_reg
, &dest
);
5810 /* Calculate the value that SRC_REG should have after the last iteration
5812 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
5815 /* Emit the start of the loop. */
5816 label
= gen_label_rtx ();
5819 /* Emit the loop body. */
5820 mips_block_move_straight (dest
, src
, MAX_MOVE_BYTES
);
5822 /* Move on to the next block. */
5823 mips_emit_move (src_reg
, plus_constant (src_reg
, MAX_MOVE_BYTES
));
5824 mips_emit_move (dest_reg
, plus_constant (dest_reg
, MAX_MOVE_BYTES
));
5826 /* Emit the loop condition. */
5827 if (Pmode
== DImode
)
5828 emit_insn (gen_cmpdi (src_reg
, final_src
));
5830 emit_insn (gen_cmpsi (src_reg
, final_src
));
5831 emit_jump_insn (gen_bne (label
));
5833 /* Mop up any left-over bytes. */
5835 mips_block_move_straight (dest
, src
, leftover
);
5838 /* Expand a movmemsi instruction. */
5841 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
5843 if (GET_CODE (length
) == CONST_INT
)
5845 if (INTVAL (length
) <= 2 * MAX_MOVE_BYTES
)
5847 mips_block_move_straight (dest
, src
, INTVAL (length
));
5852 mips_block_move_loop (dest
, src
, INTVAL (length
));
5860 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5863 mips_expand_synci_loop (rtx begin
, rtx end
)
5865 rtx inc
, label
, cmp
, cmp_result
;
5867 /* Load INC with the cache line size (rdhwr INC,$1). */
5868 inc
= gen_reg_rtx (SImode
);
5869 emit_insn (gen_rdhwr (inc
, const1_rtx
));
5871 /* Loop back to here. */
5872 label
= gen_label_rtx ();
5875 emit_insn (gen_synci (begin
));
5877 cmp
= gen_reg_rtx (Pmode
);
5878 mips_emit_binary (GTU
, cmp
, begin
, end
);
5880 mips_emit_binary (PLUS
, begin
, begin
, inc
);
5882 cmp_result
= gen_rtx_EQ (VOIDmode
, cmp
, const0_rtx
);
5883 emit_jump_insn (gen_condjump (cmp_result
, label
));
5886 /* Return true if it is possible to use left/right accesses for a
5887 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5888 returning true, update *OP, *LEFT and *RIGHT as follows:
5890 *OP is a BLKmode reference to the whole field.
5892 *LEFT is a QImode reference to the first byte if big endian or
5893 the last byte if little endian. This address can be used in the
5894 left-side instructions (lwl, swl, ldl, sdl).
5896 *RIGHT is a QImode reference to the opposite end of the field and
5897 can be used in the patterning right-side instruction. */
5900 mips_get_unaligned_mem (rtx
*op
, unsigned int width
, int bitpos
,
5901 rtx
*left
, rtx
*right
)
5905 /* Check that the operand really is a MEM. Not all the extv and
5906 extzv predicates are checked. */
5910 /* Check that the size is valid. */
5911 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
5914 /* We can only access byte-aligned values. Since we are always passed
5915 a reference to the first byte of the field, it is not necessary to
5916 do anything with BITPOS after this check. */
5917 if (bitpos
% BITS_PER_UNIT
!= 0)
5920 /* Reject aligned bitfields: we want to use a normal load or store
5921 instead of a left/right pair. */
5922 if (MEM_ALIGN (*op
) >= width
)
5925 /* Adjust *OP to refer to the whole field. This also has the effect
5926 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
5927 *op
= adjust_address (*op
, BLKmode
, 0);
5928 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
5930 /* Get references to both ends of the field. We deliberately don't
5931 use the original QImode *OP for FIRST since the new BLKmode one
5932 might have a simpler address. */
5933 first
= adjust_address (*op
, QImode
, 0);
5934 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
5936 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
5937 be the upper word and RIGHT the lower word. */
5938 if (TARGET_BIG_ENDIAN
)
5939 *left
= first
, *right
= last
;
5941 *left
= last
, *right
= first
;
5947 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
5948 Return true on success. We only handle cases where zero_extract is
5949 equivalent to sign_extract. */
5952 mips_expand_unaligned_load (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
5954 rtx left
, right
, temp
;
5956 /* If TARGET_64BIT, the destination of a 32-bit load will be a
5957 paradoxical word_mode subreg. This is the only case in which
5958 we allow the destination to be larger than the source. */
5959 if (GET_CODE (dest
) == SUBREG
5960 && GET_MODE (dest
) == DImode
5961 && SUBREG_BYTE (dest
) == 0
5962 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
5963 dest
= SUBREG_REG (dest
);
5965 /* After the above adjustment, the destination must be the same
5966 width as the source. */
5967 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
5970 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
5973 temp
= gen_reg_rtx (GET_MODE (dest
));
5974 if (GET_MODE (dest
) == DImode
)
5976 emit_insn (gen_mov_ldl (temp
, src
, left
));
5977 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
5981 emit_insn (gen_mov_lwl (temp
, src
, left
));
5982 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
5988 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
5992 mips_expand_unaligned_store (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
5995 enum machine_mode mode
;
5997 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
6000 mode
= mode_for_size (width
, MODE_INT
, 0);
6001 src
= gen_lowpart (mode
, src
);
6005 emit_insn (gen_mov_sdl (dest
, src
, left
));
6006 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
6010 emit_insn (gen_mov_swl (dest
, src
, left
));
6011 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
6016 /* Return true if X is a MEM with the same size as MODE. */
6019 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
6026 size
= MEM_SIZE (x
);
6027 return size
&& INTVAL (size
) == GET_MODE_SIZE (mode
);
6030 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
6031 source of an "ext" instruction or the destination of an "ins"
6032 instruction. OP must be a register operand and the following
6033 conditions must hold:
6035 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
6036 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
6037 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
6039 Also reject lengths equal to a word as they are better handled
6040 by the move patterns. */
6043 mips_use_ins_ext_p (rtx op
, rtx size
, rtx position
)
6045 HOST_WIDE_INT len
, pos
;
6047 if (!ISA_HAS_EXT_INS
6048 || !register_operand (op
, VOIDmode
)
6049 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
6052 len
= INTVAL (size
);
6053 pos
= INTVAL (position
);
6055 if (len
<= 0 || len
>= GET_MODE_BITSIZE (GET_MODE (op
))
6056 || pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (op
)))
6062 /* Initialize mips_split_addresses from the associated command-line
6065 mips_split_addresses is a half-way house between explicit
6066 relocations and the traditional assembler macros. It can
6067 split absolute 32-bit symbolic constants into a high/lo_sum
6068 pair but uses macros for other sorts of access.
6070 Like explicit relocation support for REL targets, it relies
6071 on GNU extensions in the assembler and the linker.
6073 Although this code should work for -O0, it has traditionally
6074 been treated as an optimization. */
6077 mips_init_split_addresses (void)
6079 if (!TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
6080 && optimize
&& !flag_pic
6081 && !ABI_HAS_64BIT_SYMBOLS
)
6082 mips_split_addresses
= 1;
6084 mips_split_addresses
= 0;
6087 /* (Re-)Initialize information about relocs. */
6090 mips_init_relocs (void)
6092 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
6093 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
6094 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
6096 if (ABI_HAS_64BIT_SYMBOLS
)
6098 if (TARGET_EXPLICIT_RELOCS
)
6100 mips_split_p
[SYMBOL_64_HIGH
] = true;
6101 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
6102 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
6104 mips_split_p
[SYMBOL_64_MID
] = true;
6105 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
6106 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
6108 mips_split_p
[SYMBOL_64_LOW
] = true;
6109 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
6110 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
6112 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6113 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6118 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses
|| TARGET_MIPS16
)
6120 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6121 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
6122 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6124 mips_lo_relocs
[SYMBOL_32_HIGH
] = "%hi(";
6130 /* The high part is provided by a pseudo copy of $gp. */
6131 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
6132 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
6135 if (TARGET_EXPLICIT_RELOCS
)
6137 /* Small data constants are kept whole until after reload,
6138 then lowered by mips_rewrite_small_data. */
6139 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
6141 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
6144 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
6145 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
6149 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
6150 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
6155 /* The HIGH and LO_SUM are matched by special .md patterns. */
6156 mips_split_p
[SYMBOL_GOT_DISP
] = true;
6158 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
6159 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
6160 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
6162 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
6163 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
6164 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
6169 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
6171 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
6172 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
6178 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
6179 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
6180 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
6183 /* Thread-local relocation operators. */
6184 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
6185 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
6186 mips_split_p
[SYMBOL_DTPREL
] = 1;
6187 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
6188 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
6189 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
6190 mips_split_p
[SYMBOL_TPREL
] = 1;
6191 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
6192 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
6194 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
6197 /* If OP is an UNSPEC address, return the address to which it refers,
6198 otherwise return OP itself. */
6201 mips_strip_unspec_address (rtx op
)
6205 split_const (op
, &base
, &offset
);
6206 if (UNSPEC_ADDRESS_P (base
))
6207 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
6211 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6212 in context CONTEXT. RELOCS is the array of relocations to use. */
6215 print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
6216 const char **relocs
)
6218 enum mips_symbol_type symbol_type
;
6221 symbol_type
= mips_classify_symbolic_expression (op
, context
);
6222 if (relocs
[symbol_type
] == 0)
6223 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op
);
6225 fputs (relocs
[symbol_type
], file
);
6226 output_addr_const (file
, mips_strip_unspec_address (op
));
6227 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
6232 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6233 The punctuation characters are:
6235 '(' Start a nested ".set noreorder" block.
6236 ')' End a nested ".set noreorder" block.
6237 '[' Start a nested ".set noat" block.
6238 ']' End a nested ".set noat" block.
6239 '<' Start a nested ".set nomacro" block.
6240 '>' End a nested ".set nomacro" block.
6241 '*' Behave like %(%< if generating a delayed-branch sequence.
6242 '#' Print a nop if in a ".set noreorder" block.
6243 '/' Like '#', but do nothing within a delayed-branch sequence.
6244 '?' Print "l" if mips_branch_likely is true
6245 '.' Print the name of the register with a hard-wired zero (zero or $0).
6246 '@' Print the name of the assembler temporary register (at or $1).
6247 '^' Print the name of the pic call-through register (t9 or $25).
6248 '+' Print the name of the gp register (usually gp or $28).
6249 '$' Print the name of the stack pointer register (sp or $29).
6250 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6251 '-' Print ".set pop" under the same conditions for '|'.
6253 See also mips_init_print_operand_pucnt. */
6256 mips_print_operand_punctuation (FILE *file
, int ch
)
6261 if (set_noreorder
++ == 0)
6262 fputs (".set\tnoreorder\n\t", file
);
6266 gcc_assert (set_noreorder
> 0);
6267 if (--set_noreorder
== 0)
6268 fputs ("\n\t.set\treorder", file
);
6272 if (set_noat
++ == 0)
6273 fputs (".set\tnoat\n\t", file
);
6277 gcc_assert (set_noat
> 0);
6278 if (--set_noat
== 0)
6279 fputs ("\n\t.set\tat", file
);
6283 if (set_nomacro
++ == 0)
6284 fputs (".set\tnomacro\n\t", file
);
6288 gcc_assert (set_nomacro
> 0);
6289 if (--set_nomacro
== 0)
6290 fputs ("\n\t.set\tmacro", file
);
6294 if (final_sequence
!= 0)
6296 mips_print_operand_punctuation (file
, '(');
6297 mips_print_operand_punctuation (file
, '<');
6302 if (set_noreorder
!= 0)
6303 fputs ("\n\tnop", file
);
6307 /* Print an extra newline so that the delayed insn is separated
6308 from the following ones. This looks neater and is consistent
6309 with non-nop delayed sequences. */
6310 if (set_noreorder
!= 0 && final_sequence
== 0)
6311 fputs ("\n\tnop\n", file
);
6315 if (mips_branch_likely
)
6320 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
6324 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
6328 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
6332 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
6336 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
6341 fputs (".set\tpush\n\t.set\tmips2\n\t", file
);
6346 fputs ("\n\t.set\tpop", file
);
6355 /* Initialize mips_print_operand_punct. */
6358 mips_init_print_operand_punct (void)
6362 for (p
= "()[]<>*#/?.@^+$|-"; *p
; p
++)
6363 mips_print_operand_punct
[(unsigned char) *p
] = true;
6366 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6367 associated with condition CODE. Print the condition part of the
6371 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
6385 /* Conveniently, the MIPS names for these conditions are the same
6386 as their RTL equivalents. */
6387 fputs (GET_RTX_NAME (code
), file
);
6391 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
6396 /* Likewise floating-point branches. */
6399 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
6404 fputs ("c1f", file
);
6408 fputs ("c1t", file
);
6412 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
6417 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6419 'X' Print CONST_INT OP in hexadecimal format.
6420 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6421 'd' Print CONST_INT OP in decimal.
6422 'h' Print the high-part relocation associated with OP, after stripping
6424 'R' Print the low-part relocation associated with OP.
6425 'C' Print the integer branch condition for comparison OP.
6426 'N' Print the inverse of the integer branch condition for comparison OP.
6427 'F' Print the FPU branch condition for comparison OP.
6428 'W' Print the inverse of the FPU branch condition for comparison OP.
6429 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6430 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6431 't' Like 'T', but with the EQ/NE cases reversed
6432 'Y' Print mips_fp_conditions[INTVAL (OP)]
6433 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6434 'q' Print a DSP accumulator register.
6435 'D' Print the second part of a double-word register or memory operand.
6436 'L' Print the low-order register in a double-word register operand.
6437 'M' Print high-order register in a double-word register operand.
6438 'z' Print $0 if OP is zero, otherwise print OP normally. */
6441 print_operand (FILE *file
, rtx op
, int letter
)
6445 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
6447 mips_print_operand_punctuation (file
, letter
);
6452 code
= GET_CODE (op
);
6457 if (GET_CODE (op
) == CONST_INT
)
6458 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
6460 output_operand_lossage ("invalid use of '%%%c'", letter
);
6464 if (GET_CODE (op
) == CONST_INT
)
6465 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
6467 output_operand_lossage ("invalid use of '%%%c'", letter
);
6471 if (GET_CODE (op
) == CONST_INT
)
6472 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
6474 output_operand_lossage ("invalid use of '%%%c'", letter
);
6480 print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
6484 print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
6488 mips_print_int_branch_condition (file
, code
, letter
);
6492 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
6496 mips_print_float_branch_condition (file
, code
, letter
);
6500 mips_print_float_branch_condition (file
, reverse_condition (code
),
6507 int truth
= (code
== NE
) == (letter
== 'T');
6508 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
6513 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
6514 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
6516 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6523 print_operand (file
, op
, 0);
6529 if (code
== REG
&& MD_REG_P (REGNO (op
)))
6530 fprintf (file
, "$ac0");
6531 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
6532 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
6534 output_operand_lossage ("invalid use of '%%%c'", letter
);
6542 unsigned int regno
= REGNO (op
);
6543 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
6544 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
6547 fprintf (file
, "%s", reg_names
[regno
]);
6553 output_address (plus_constant (XEXP (op
, 0), 4));
6555 output_address (XEXP (op
, 0));
6559 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
6560 fputs (reg_names
[GP_REG_FIRST
], file
);
6561 else if (CONST_GP_P (op
))
6562 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
6564 output_addr_const (file
, mips_strip_unspec_address (op
));
6570 /* Output address operand X to FILE. */
6573 print_operand_address (FILE *file
, rtx x
)
6575 struct mips_address_info addr
;
6577 if (mips_classify_address (&addr
, x
, word_mode
, true))
6581 print_operand (file
, addr
.offset
, 0);
6582 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
6585 case ADDRESS_LO_SUM
:
6586 print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
6588 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
6591 case ADDRESS_CONST_INT
:
6592 output_addr_const (file
, x
);
6593 fprintf (file
, "(%s)", reg_names
[0]);
6596 case ADDRESS_SYMBOLIC
:
6597 output_addr_const (file
, mips_strip_unspec_address (x
));
6603 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
6604 FIRST is true if this is the first time handling this decl. */
6607 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
6609 default_encode_section_info (decl
, rtl
, first
);
6611 if (TREE_CODE (decl
) == FUNCTION_DECL
)
6613 rtx symbol
= XEXP (rtl
, 0);
6614 tree type
= TREE_TYPE (decl
);
6616 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
6617 || mips_far_type_p (type
))
6618 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
6622 /* Implement TARGET_SELECT_RTX_SECTION. */
6625 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
6626 unsigned HOST_WIDE_INT align
)
6628 /* ??? Consider using mergeable small data sections. */
6629 if (mips_rtx_constant_in_small_data_p (mode
))
6630 return get_named_section (NULL
, ".sdata", 0);
6632 return default_elf_select_rtx_section (mode
, x
, align
);
6635 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6637 The complication here is that, with the combination TARGET_ABICALLS
6638 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6639 therefore not be included in the read-only part of a DSO. Handle such
6640 cases by selecting a normal data section instead of a read-only one.
6641 The logic apes that in default_function_rodata_section. */
6644 mips_function_rodata_section (tree decl
)
6646 if (!TARGET_ABICALLS
|| TARGET_GPWORD
)
6647 return default_function_rodata_section (decl
);
6649 if (decl
&& DECL_SECTION_NAME (decl
))
6651 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
6652 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
6654 char *rname
= ASTRDUP (name
);
6656 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
6658 else if (flag_function_sections
&& flag_data_sections
6659 && strncmp (name
, ".text.", 6) == 0)
6661 char *rname
= ASTRDUP (name
);
6662 memcpy (rname
+ 1, "data", 4);
6663 return get_section (rname
, SECTION_WRITE
, decl
);
6666 return data_section
;
6669 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
6670 locally-defined objects go in a small data section. It also controls
6671 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
6672 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
6675 mips_in_small_data_p (const_tree decl
)
6679 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
6682 /* We don't yet generate small-data references for -mabicalls or
6683 VxWorks RTP code. See the related -G handling in override_options. */
6684 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
6687 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
6691 /* Reject anything that isn't in a known small-data section. */
6692 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
6693 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
6696 /* If a symbol is defined externally, the assembler will use the
6697 usual -G rules when deciding how to implement macros. */
6698 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
6701 else if (TARGET_EMBEDDED_DATA
)
6703 /* Don't put constants into the small data section: we want them
6704 to be in ROM rather than RAM. */
6705 if (TREE_CODE (decl
) != VAR_DECL
)
6708 if (TREE_READONLY (decl
)
6709 && !TREE_SIDE_EFFECTS (decl
)
6710 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
6714 /* Enforce -mlocal-sdata. */
6715 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
6718 /* Enforce -mextern-sdata. */
6719 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
6721 if (DECL_EXTERNAL (decl
))
6723 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
6727 size
= int_size_in_bytes (TREE_TYPE (decl
));
6728 return (size
> 0 && size
<= mips_section_threshold
);
6731 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6732 anchors for small data: the GP register acts as an anchor in that
6733 case. We also don't want to use them for PC-relative accesses,
6734 where the PC acts as an anchor. */
6737 mips_use_anchors_for_symbol_p (const_rtx symbol
)
6739 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
6741 case SYMBOL_PC_RELATIVE
:
6742 case SYMBOL_GP_RELATIVE
:
6746 return default_use_anchors_for_symbol_p (symbol
);
6750 /* The MIPS debug format wants all automatic variables and arguments
6751 to be in terms of the virtual frame pointer (stack pointer before
6752 any adjustment in the function), while the MIPS 3.0 linker wants
6753 the frame pointer to be the stack pointer after the initial
6754 adjustment. So, we do the adjustment here. The arg pointer (which
6755 is eliminated) points to the virtual frame pointer, while the frame
6756 pointer (which may be eliminated) points to the stack pointer after
6757 the initial adjustments. */
6760 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
6762 rtx offset2
= const0_rtx
;
6763 rtx reg
= eliminate_constant_term (addr
, &offset2
);
6766 offset
= INTVAL (offset2
);
6768 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
6769 || reg
== hard_frame_pointer_rtx
)
6771 offset
-= cfun
->machine
->frame
.total_size
;
6772 if (reg
== hard_frame_pointer_rtx
)
6773 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
6776 /* sdbout_parms does not want this to crash for unrecognized cases. */
6778 else if (reg
!= arg_pointer_rtx
)
6779 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6786 /* When using assembler macros, keep track of all of small-data externs
6787 so that mips_file_end can emit the appropriate declarations for them.
6789 In most cases it would be safe (though pointless) to emit .externs
6790 for other symbols too. One exception is when an object is within
6791 the -G limit but declared by the user to be in a section other
6792 than .sbss or .sdata. */
6795 mips_output_external (FILE *file
, tree decl
, const char *name
)
6797 default_elf_asm_output_external (file
, decl
, name
);
6799 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6800 set in order to avoid putting out names that are never really
6802 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
6804 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
6806 fputs ("\t.extern\t", file
);
6807 assemble_name (file
, name
);
6808 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
6809 int_size_in_bytes (TREE_TYPE (decl
)));
6811 else if (TARGET_IRIX
6812 && mips_abi
== ABI_32
6813 && TREE_CODE (decl
) == FUNCTION_DECL
)
6815 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6816 `.global name .text' directive for every used but
6817 undefined function. If we don't, the linker may perform
6818 an optimization (skipping over the insns that set $gp)
6819 when it is unsafe. */
6820 fputs ("\t.globl ", file
);
6821 assemble_name (file
, name
);
6822 fputs (" .text\n", file
);
6827 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6828 put out a MIPS ECOFF file and a stab. */
6831 mips_output_filename (FILE *stream
, const char *name
)
6834 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6836 if (write_symbols
== DWARF2_DEBUG
)
6838 else if (mips_output_filename_first_time
)
6840 mips_output_filename_first_time
= 0;
6841 num_source_filenames
+= 1;
6842 current_function_file
= name
;
6843 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
6844 output_quoted_string (stream
, name
);
6845 putc ('\n', stream
);
6848 /* If we are emitting stabs, let dbxout.c handle this (except for
6849 the mips_output_filename_first_time case). */
6850 else if (write_symbols
== DBX_DEBUG
)
6853 else if (name
!= current_function_file
6854 && strcmp (name
, current_function_file
) != 0)
6856 num_source_filenames
+= 1;
6857 current_function_file
= name
;
6858 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
6859 output_quoted_string (stream
, name
);
6860 putc ('\n', stream
);
6864 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
6867 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6872 fputs ("\t.dtprelword\t", file
);
6876 fputs ("\t.dtpreldword\t", file
);
6882 output_addr_const (file
, x
);
6883 fputs ("+0x8000", file
);
6886 /* Implement TARGET_DWARF_REGISTER_SPAN. */
6889 mips_dwarf_register_span (rtx reg
)
6892 enum machine_mode mode
;
6894 /* By default, GCC maps increasing register numbers to increasing
6895 memory locations, but paired FPRs are always little-endian,
6896 regardless of the prevailing endianness. */
6897 mode
= GET_MODE (reg
);
6898 if (FP_REG_P (REGNO (reg
))
6899 && TARGET_BIG_ENDIAN
6900 && MAX_FPRS_PER_FMT
> 1
6901 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
6903 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
6904 high
= mips_subword (reg
, true);
6905 low
= mips_subword (reg
, false);
6906 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
6912 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6913 that should be written before the opening quote, such as "\t.ascii\t"
6914 for real string data or "\t# " for a comment. */
6917 mips_output_ascii (FILE *stream
, const char *string_param
, size_t len
,
6922 register const unsigned char *string
=
6923 (const unsigned char *)string_param
;
6925 fprintf (stream
, "%s\"", prefix
);
6926 for (i
= 0; i
< len
; i
++)
6928 register int c
= string
[i
];
6932 if (c
== '\\' || c
== '\"')
6934 putc ('\\', stream
);
6942 fprintf (stream
, "\\%03o", c
);
6946 if (cur_pos
> 72 && i
+1 < len
)
6949 fprintf (stream
, "\"\n%s\"", prefix
);
6952 fprintf (stream
, "\"\n");
6955 #ifdef BSS_SECTION_ASM_OP
6956 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6957 in the use of sbss. */
6960 mips_output_aligned_bss (FILE *stream
, tree decl
, const char *name
,
6961 unsigned HOST_WIDE_INT size
, int align
)
6963 extern tree last_assemble_variable_decl
;
6965 if (mips_in_small_data_p (decl
))
6966 switch_to_section (get_named_section (NULL
, ".sbss", 0));
6968 switch_to_section (bss_section
);
6969 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
6970 last_assemble_variable_decl
= decl
;
6971 ASM_DECLARE_OBJECT_NAME (stream
, name
, decl
);
6972 ASM_OUTPUT_SKIP (stream
, size
!= 0 ? size
: 1);
6976 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6977 macros, mark the symbol as written so that mips_file_end won't emit an
6978 .extern for it. STREAM is the output file, NAME is the name of the
6979 symbol, INIT_STRING is the string that should be written before the
6980 symbol and FINAL_STRING is the string that should be written after it.
6981 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6984 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
6985 const char *final_string
, ...)
6989 fputs (init_string
, stream
);
6990 assemble_name (stream
, name
);
6991 va_start (ap
, final_string
);
6992 vfprintf (stream
, final_string
, ap
);
6995 if (!TARGET_EXPLICIT_RELOCS
)
6997 tree name_tree
= get_identifier (name
);
6998 TREE_ASM_WRITTEN (name_tree
) = 1;
7002 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7003 NAME is the name of the object and ALIGN is the required alignment
7004 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7005 alignment argument. */
7008 mips_declare_common_object (FILE *stream
, const char *name
,
7009 const char *init_string
,
7010 unsigned HOST_WIDE_INT size
,
7011 unsigned int align
, bool takes_alignment_p
)
7013 if (!takes_alignment_p
)
7015 size
+= (align
/ BITS_PER_UNIT
) - 1;
7016 size
-= size
% (align
/ BITS_PER_UNIT
);
7017 mips_declare_object (stream
, name
, init_string
,
7018 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
7021 mips_declare_object (stream
, name
, init_string
,
7022 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
7023 size
, align
/ BITS_PER_UNIT
);
7026 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7027 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7030 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
7031 unsigned HOST_WIDE_INT size
,
7034 /* If the target wants uninitialized const declarations in
7035 .rdata then don't put them in .comm. */
7036 if (TARGET_EMBEDDED_DATA
&& TARGET_UNINIT_CONST_IN_RODATA
7037 && TREE_CODE (decl
) == VAR_DECL
&& TREE_READONLY (decl
)
7038 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
7040 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
7041 targetm
.asm_out
.globalize_label (stream
, name
);
7043 switch_to_section (readonly_data_section
);
7044 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
7045 mips_declare_object (stream
, name
, "",
7046 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
7050 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
7054 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7055 extern int size_directive_output
;
7057 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7058 definitions except that it uses mips_declare_object() to emit the label. */
7061 mips_declare_object_name (FILE *stream
, const char *name
,
7062 tree decl ATTRIBUTE_UNUSED
)
7064 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7065 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
7068 size_directive_output
= 0;
7069 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
7073 size_directive_output
= 1;
7074 size
= int_size_in_bytes (TREE_TYPE (decl
));
7075 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7078 mips_declare_object (stream
, name
, "", ":\n");
7081 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7084 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
7088 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
7089 if (!flag_inhibit_size_directive
7090 && DECL_SIZE (decl
) != 0
7091 && !at_end
&& top_level
7092 && DECL_INITIAL (decl
) == error_mark_node
7093 && !size_directive_output
)
7097 size_directive_output
= 1;
7098 size
= int_size_in_bytes (TREE_TYPE (decl
));
7099 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7104 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7105 with the current ABI. */
7108 mips_mdebug_abi_name (void)
7121 return TARGET_64BIT
? "eabi64" : "eabi32";
7127 /* Implement TARGET_ASM_FILE_START. */
7130 mips_file_start (void)
7132 default_file_start ();
7136 /* Generate a special section to describe the ABI switches used to
7137 produce the resultant binary. This used to be done by the assembler
7138 setting bits in the ELF header's flags field, but we have run out of
7139 bits. GDB needs this information in order to be able to correctly
7140 debug these binaries. See the function mips_gdbarch_init() in
7141 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
7142 causes unnecessary IRIX 6 ld warnings. */
7143 /* Note - we use fprintf directly rather than calling switch_to_section
7144 because in this way we can avoid creating an allocated section. We
7145 do not want this section to take up any space in the running
7147 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
7148 mips_mdebug_abi_name ());
7150 /* There is no ELF header flag to distinguish long32 forms of the
7151 EABI from long64 forms. Emit a special section to help tools
7152 such as GDB. Do the same for o64, which is sometimes used with
7154 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
7155 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
7156 "\t.previous\n", TARGET_LONG64
? 64 : 32);
7158 #ifdef HAVE_AS_GNU_ATTRIBUTE
7159 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
7160 TARGET_HARD_FLOAT_ABI
? (TARGET_DOUBLE_FLOAT
? 1 : 2) : 3);
7164 /* Generate the pseudo ops that System V.4 wants. */
7165 if (TARGET_ABICALLS
)
7166 fprintf (asm_out_file
, "\t.abicalls\n");
7168 if (flag_verbose_asm
)
7169 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7171 mips_section_threshold
, mips_arch_info
->name
, mips_isa
);
7175 /* Make the last instruction frame related and note that it performs
7176 the operation described by FRAME_PATTERN. */
7179 mips_set_frame_expr (rtx frame_pattern
)
7183 insn
= get_last_insn ();
7184 RTX_FRAME_RELATED_P (insn
) = 1;
7185 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7191 /* Return a frame-related rtx that stores REG at MEM.
7192 REG must be a single register. */
7195 mips_frame_set (rtx mem
, rtx reg
)
7199 /* If we're saving the return address register and the dwarf return
7200 address column differs from the hard register number, adjust the
7201 note reg to refer to the former. */
7202 if (REGNO (reg
) == GP_REG_FIRST
+ 31
7203 && DWARF_FRAME_RETURN_COLUMN
!= GP_REG_FIRST
+ 31)
7204 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
7206 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
7207 RTX_FRAME_RELATED_P (set
) = 1;
7212 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7213 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7214 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7215 static const unsigned char mips16e_s2_s8_regs
[] = {
7216 30, 23, 22, 21, 20, 19, 18
7218 static const unsigned char mips16e_a0_a3_regs
[] = {
7222 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7223 ordered from the uppermost in memory to the lowest in memory. */
7224 static const unsigned char mips16e_save_restore_regs
[] = {
7225 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7228 /* Return the index of the lowest X in the range [0, SIZE) for which
7229 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7232 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
7237 for (i
= 0; i
< size
; i
++)
7238 if (BITSET_P (mask
, regs
[i
]))
7244 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7245 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7246 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7247 is true for all indexes (X, SIZE). */
7250 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
7251 unsigned int size
, unsigned int *num_regs_ptr
)
7255 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
7256 for (i
++; i
< size
; i
++)
7257 if (!BITSET_P (*mask_ptr
, regs
[i
]))
7260 *mask_ptr
|= 1 << regs
[i
];
7264 /* Return a simplified form of X using the register values in REG_VALUES.
7265 REG_VALUES[R] is the last value assigned to hard register R, or null
7266 if R has not been modified.
7268 This function is rather limited, but is good enough for our purposes. */
7271 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
7275 x
= avoid_constant_pool_reference (x
);
7279 x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
7280 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
7281 x0
, GET_MODE (XEXP (x
, 0)));
7284 if (ARITHMETIC_P (x
))
7286 x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
7287 x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
7288 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
7292 && reg_values
[REGNO (x
)]
7293 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
7294 return reg_values
[REGNO (x
)];
7299 /* Return true if (set DEST SRC) stores an argument register into its
7300 caller-allocated save slot, storing the number of that argument
7301 register in *REGNO_PTR if so. REG_VALUES is as for
7302 mips16e_collect_propagate_value. */
7305 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
7306 unsigned int *regno_ptr
)
7308 unsigned int argno
, regno
;
7309 HOST_WIDE_INT offset
, required_offset
;
7312 /* Check that this is a word-mode store. */
7313 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
7316 /* Check that the register being saved is an unmodified argument
7318 regno
= REGNO (src
);
7319 if (regno
< GP_ARG_FIRST
|| regno
> GP_ARG_LAST
|| reg_values
[regno
])
7321 argno
= regno
- GP_ARG_FIRST
;
7323 /* Check whether the address is an appropriate stack pointer or
7324 frame pointer access. */
7325 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
7326 mips_split_plus (addr
, &base
, &offset
);
7327 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
7328 if (base
== hard_frame_pointer_rtx
)
7329 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7330 else if (base
!= stack_pointer_rtx
)
7332 if (offset
!= required_offset
)
7339 /* A subroutine of mips_expand_prologue, called only when generating
7340 MIPS16e SAVE instructions. Search the start of the function for any
7341 instructions that save argument registers into their caller-allocated
7342 save slots. Delete such instructions and return a value N such that
7343 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7344 instructions redundant. */
7347 mips16e_collect_argument_saves (void)
7349 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
7350 rtx insn
, next
, set
, dest
, src
;
7351 unsigned int nargs
, regno
;
7353 push_topmost_sequence ();
7355 memset (reg_values
, 0, sizeof (reg_values
));
7356 for (insn
= get_insns (); insn
; insn
= next
)
7358 next
= NEXT_INSN (insn
);
7365 set
= PATTERN (insn
);
7366 if (GET_CODE (set
) != SET
)
7369 dest
= SET_DEST (set
);
7370 src
= SET_SRC (set
);
7371 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
7373 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
7376 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
7379 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
7380 reg_values
[REGNO (dest
)]
7381 = mips16e_collect_propagate_value (src
, reg_values
);
7385 pop_topmost_sequence ();
7390 /* Return a move between register REGNO and memory location SP + OFFSET.
7391 Make the move a load if RESTORE_P, otherwise make it a frame-related
7395 mips16e_save_restore_reg (bool restore_p
, HOST_WIDE_INT offset
,
7400 mem
= gen_frame_mem (SImode
, plus_constant (stack_pointer_rtx
, offset
));
7401 reg
= gen_rtx_REG (SImode
, regno
);
7403 ? gen_rtx_SET (VOIDmode
, reg
, mem
)
7404 : mips_frame_set (mem
, reg
));
7407 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7408 The instruction must:
7410 - Allocate or deallocate SIZE bytes in total; SIZE is known
7413 - Save or restore as many registers in *MASK_PTR as possible.
7414 The instruction saves the first registers at the top of the
7415 allocated area, with the other registers below it.
7417 - Save NARGS argument registers above the allocated area.
7419 (NARGS is always zero if RESTORE_P.)
7421 The SAVE and RESTORE instructions cannot save and restore all general
7422 registers, so there may be some registers left over for the caller to
7423 handle. Destructively modify *MASK_PTR so that it contains the registers
7424 that still need to be saved or restored. The caller can save these
7425 registers in the memory immediately below *OFFSET_PTR, which is a
7426 byte offset from the bottom of the allocated stack area. */
7429 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
7430 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
7434 HOST_WIDE_INT offset
, top_offset
;
7435 unsigned int i
, regno
;
7438 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
7440 /* Calculate the number of elements in the PARALLEL. We need one element
7441 for the stack adjustment, one for each argument register save, and one
7442 for each additional register move. */
7444 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
7445 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
7448 /* Create the final PARALLEL. */
7449 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
7452 /* Add the stack pointer adjustment. */
7453 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7454 plus_constant (stack_pointer_rtx
,
7455 restore_p
? size
: -size
));
7456 RTX_FRAME_RELATED_P (set
) = 1;
7457 XVECEXP (pattern
, 0, n
++) = set
;
7459 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7460 top_offset
= restore_p
? size
: 0;
7462 /* Save the arguments. */
7463 for (i
= 0; i
< nargs
; i
++)
7465 offset
= top_offset
+ i
* UNITS_PER_WORD
;
7466 set
= mips16e_save_restore_reg (restore_p
, offset
, GP_ARG_FIRST
+ i
);
7467 XVECEXP (pattern
, 0, n
++) = set
;
7470 /* Then fill in the other register moves. */
7471 offset
= top_offset
;
7472 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
7474 regno
= mips16e_save_restore_regs
[i
];
7475 if (BITSET_P (*mask_ptr
, regno
))
7477 offset
-= UNITS_PER_WORD
;
7478 set
= mips16e_save_restore_reg (restore_p
, offset
, regno
);
7479 XVECEXP (pattern
, 0, n
++) = set
;
7480 *mask_ptr
&= ~(1 << regno
);
7484 /* Tell the caller what offset it should use for the remaining registers. */
7485 *offset_ptr
= size
+ (offset
- top_offset
);
7487 gcc_assert (n
== XVECLEN (pattern
, 0));
7492 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7493 pointer. Return true if PATTERN matches the kind of instruction
7494 generated by mips16e_build_save_restore. If INFO is nonnull,
7495 initialize it when returning true. */
7498 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
7499 struct mips16e_save_restore_info
*info
)
7501 unsigned int i
, nargs
, mask
, extra
;
7502 HOST_WIDE_INT top_offset
, save_offset
, offset
;
7503 rtx set
, reg
, mem
, base
;
7506 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
7509 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7510 top_offset
= adjust
> 0 ? adjust
: 0;
7512 /* Interpret all other members of the PARALLEL. */
7513 save_offset
= top_offset
- UNITS_PER_WORD
;
7517 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
7519 /* Check that we have a SET. */
7520 set
= XVECEXP (pattern
, 0, n
);
7521 if (GET_CODE (set
) != SET
)
7524 /* Check that the SET is a load (if restoring) or a store
7526 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
7530 /* Check that the address is the sum of the stack pointer and a
7531 possibly-zero constant offset. */
7532 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
7533 if (base
!= stack_pointer_rtx
)
7536 /* Check that SET's other operand is a register. */
7537 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
7541 /* Check for argument saves. */
7542 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
7543 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
7545 else if (offset
== save_offset
)
7547 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
7548 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
7551 mask
|= 1 << REGNO (reg
);
7552 save_offset
-= UNITS_PER_WORD
;
7558 /* Check that the restrictions on register ranges are met. */
7560 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
7561 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
7562 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
7563 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
7567 /* Make sure that the topmost argument register is not saved twice.
7568 The checks above ensure that the same is then true for the other
7569 argument registers. */
7570 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
7573 /* Pass back information, if requested. */
7576 info
->nargs
= nargs
;
7578 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
7584 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7585 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7586 the null terminator. */
7589 mips16e_add_register_range (char *s
, unsigned int min_reg
,
7590 unsigned int max_reg
)
7592 if (min_reg
!= max_reg
)
7593 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
7595 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
7599 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7600 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7603 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
7605 static char buffer
[300];
7607 struct mips16e_save_restore_info info
;
7608 unsigned int i
, end
;
7611 /* Parse the pattern. */
7612 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
7615 /* Add the mnemonic. */
7616 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
7619 /* Save the arguments. */
7621 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
7622 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
7623 else if (info
.nargs
== 1)
7624 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
7626 /* Emit the amount of stack space to allocate or deallocate. */
7627 s
+= sprintf (s
, "%d", (int) info
.size
);
7629 /* Save or restore $16. */
7630 if (BITSET_P (info
.mask
, 16))
7631 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
7633 /* Save or restore $17. */
7634 if (BITSET_P (info
.mask
, 17))
7635 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
7637 /* Save or restore registers in the range $s2...$s8, which
7638 mips16e_s2_s8_regs lists in decreasing order. Note that this
7639 is a software register range; the hardware registers are not
7640 numbered consecutively. */
7641 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
7642 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
7644 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
7645 mips16e_s2_s8_regs
[i
]);
7647 /* Save or restore registers in the range $a0...$a3. */
7648 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
7649 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
7651 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
7652 mips16e_a0_a3_regs
[end
- 1]);
7654 /* Save or restore $31. */
7655 if (BITSET_P (info
.mask
, 31))
7656 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 31]);
7661 /* Return true if the current function has an insn that implicitly
7665 mips_function_has_gp_insn (void)
7667 /* Don't bother rechecking if we found one last time. */
7668 if (!cfun
->machine
->has_gp_insn_p
)
7672 push_topmost_sequence ();
7673 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7675 && GET_CODE (PATTERN (insn
)) != USE
7676 && GET_CODE (PATTERN (insn
)) != CLOBBER
7677 && (get_attr_got (insn
) != GOT_UNSET
7678 || small_data_pattern (PATTERN (insn
), VOIDmode
)))
7680 pop_topmost_sequence ();
7682 cfun
->machine
->has_gp_insn_p
= (insn
!= 0);
7684 return cfun
->machine
->has_gp_insn_p
;
7688 /* Return the register that should be used as the global pointer
7689 within this function. Return 0 if the function doesn't need
7690 a global pointer. */
7693 mips_global_pointer (void)
7697 /* $gp is always available unless we're using a GOT. */
7698 if (!TARGET_USE_GOT
)
7699 return GLOBAL_POINTER_REGNUM
;
7701 /* We must always provide $gp when it is used implicitly. */
7702 if (!TARGET_EXPLICIT_RELOCS
)
7703 return GLOBAL_POINTER_REGNUM
;
7705 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7707 if (current_function_profile
)
7708 return GLOBAL_POINTER_REGNUM
;
7710 /* If the function has a nonlocal goto, $gp must hold the correct
7711 global pointer for the target function. */
7712 if (current_function_has_nonlocal_goto
)
7713 return GLOBAL_POINTER_REGNUM
;
7715 /* If the gp is never referenced, there's no need to initialize it.
7716 Note that reload can sometimes introduce constant pool references
7717 into a function that otherwise didn't need them. For example,
7718 suppose we have an instruction like:
7720 (set (reg:DF R1) (float:DF (reg:SI R2)))
7722 If R2 turns out to be constant such as 1, the instruction may have a
7723 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7724 using this constant if R2 doesn't get allocated to a register.
7726 In cases like these, reload will have added the constant to the pool
7727 but no instruction will yet refer to it. */
7728 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM
)
7729 && !current_function_uses_const_pool
7730 && !mips_function_has_gp_insn ())
7733 /* We need a global pointer, but perhaps we can use a call-clobbered
7734 register instead of $gp. */
7735 if (TARGET_CALL_SAVED_GP
&& current_function_is_leaf
)
7736 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
7737 if (!df_regs_ever_live_p (regno
)
7738 && call_really_used_regs
[regno
]
7739 && !fixed_regs
[regno
]
7740 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
7743 return GLOBAL_POINTER_REGNUM
;
7746 /* Return true if the current function returns its value in a floating-point
7747 register in MIPS16 mode. */
7750 mips16_cfun_returns_in_fpr_p (void)
7752 tree return_type
= DECL_RESULT (current_function_decl
);
7753 return (TARGET_MIPS16
7754 && TARGET_HARD_FLOAT_ABI
7755 && !aggregate_value_p (return_type
, current_function_decl
)
7756 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
7760 /* Return true if the current function must save REGNO. */
7763 mips_save_reg_p (unsigned int regno
)
7765 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7766 if we have not chosen a call-clobbered substitute. */
7767 if (regno
== GLOBAL_POINTER_REGNUM
)
7768 return TARGET_CALL_SAVED_GP
&& cfun
->machine
->global_pointer
== regno
;
7770 /* Check call-saved registers. */
7771 if ((current_function_saves_all_registers
|| df_regs_ever_live_p (regno
))
7772 && !call_really_used_regs
[regno
])
7775 /* Save both registers in an FPR pair if either one is used. This is
7776 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7777 register to be used without the even register. */
7778 if (FP_REG_P (regno
)
7779 && MAX_FPRS_PER_FMT
== 2
7780 && df_regs_ever_live_p (regno
+ 1)
7781 && !call_really_used_regs
[regno
+ 1])
7784 /* We need to save the old frame pointer before setting up a new one. */
7785 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
7788 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7789 if (current_function_profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
7792 /* We need to save the incoming return address if it is ever clobbered
7793 within the function, if __builtin_eh_return is being used to set a
7794 different return address, or if a stub is being used to return a
7796 if (regno
== GP_REG_FIRST
+ 31
7797 && (df_regs_ever_live_p (regno
)
7798 || current_function_calls_eh_return
7799 || mips16_cfun_returns_in_fpr_p ()))
7805 /* Populate the current function's mips_frame_info structure.
7807 MIPS stack frames look like:
7809 +-------------------------------+
7811 | incoming stack arguments |
7813 +-------------------------------+
7815 | caller-allocated save area |
7816 A | for register arguments |
7818 +-------------------------------+ <-- incoming stack pointer
7820 | callee-allocated save area |
7821 B | for arguments that are |
7822 | split between registers and |
7825 +-------------------------------+ <-- arg_pointer_rtx
7827 C | callee-allocated save area |
7828 | for register varargs |
7830 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
7831 | | + UNITS_PER_HWFPVALUE
7834 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
7835 | | + UNITS_PER_WORD
7838 +-------------------------------+
7840 | local variables | | var_size
7842 +-------------------------------+
7844 | $gp save area | | cprestore_size
7846 P +-------------------------------+ <-- hard_frame_pointer_rtx for
7848 | outgoing stack arguments |
7850 +-------------------------------+
7852 | caller-allocated save area |
7853 | for register arguments |
7855 +-------------------------------+ <-- stack_pointer_rtx
7857 hard_frame_pointer_rtx for
7860 At least two of A, B and C will be empty.
7862 Dynamic stack allocations such as alloca insert data at point P.
7863 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7864 hard_frame_pointer_rtx unchanged. */
7867 mips_compute_frame_info (void)
7869 struct mips_frame_info
*frame
;
7870 HOST_WIDE_INT offset
, size
;
7871 unsigned int regno
, i
;
7873 frame
= &cfun
->machine
->frame
;
7874 memset (frame
, 0, sizeof (*frame
));
7875 size
= get_frame_size ();
7877 cfun
->machine
->global_pointer
= mips_global_pointer ();
7879 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
7880 area and the $gp save slot. This area isn't needed in leaf functions,
7881 but if the target-independent frame size is nonzero, we're committed
7882 to allocating it anyway. */
7883 if (size
== 0 && current_function_is_leaf
)
7885 /* The MIPS 3.0 linker does not like functions that dynamically
7886 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7887 looks like we are trying to create a second frame pointer to the
7888 function, so allocate some stack space to make it happy. */
7889 if (current_function_calls_alloca
)
7890 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
7892 frame
->args_size
= 0;
7893 frame
->cprestore_size
= 0;
7897 frame
->args_size
= current_function_outgoing_args_size
;
7898 frame
->cprestore_size
= STARTING_FRAME_OFFSET
- frame
->args_size
;
7900 offset
= frame
->args_size
+ frame
->cprestore_size
;
7902 /* Move above the local variables. */
7903 frame
->var_size
= MIPS_STACK_ALIGN (size
);
7904 offset
+= frame
->var_size
;
7906 /* Find out which GPRs we need to save. */
7907 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
7908 if (mips_save_reg_p (regno
))
7911 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
7914 /* If this function calls eh_return, we must also save and restore the
7915 EH data registers. */
7916 if (current_function_calls_eh_return
)
7917 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7920 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
7923 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
7924 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
7925 save all later registers too. */
7926 if (GENERATE_MIPS16E_SAVE_RESTORE
)
7928 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
7929 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
7930 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
7931 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
7934 /* Move above the GPR save area. */
7935 if (frame
->num_gp
> 0)
7937 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
7938 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
7941 /* Find out which FPRs we need to save. This loop must iterate over
7942 the same space as its companion in mips_for_each_saved_reg. */
7943 if (TARGET_HARD_FLOAT
)
7944 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
7945 if (mips_save_reg_p (regno
))
7947 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
7948 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
7951 /* Move above the FPR save area. */
7952 if (frame
->num_fp
> 0)
7954 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
7955 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
7958 /* Move above the callee-allocated varargs save area. */
7959 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
7960 frame
->arg_pointer_offset
= offset
;
7962 /* Move above the callee-allocated area for pretend stack arguments. */
7963 offset
+= current_function_pretend_args_size
;
7964 frame
->total_size
= offset
;
7966 /* Work out the offsets of the save areas from the top of the frame. */
7967 if (frame
->gp_sp_offset
> 0)
7968 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
7969 if (frame
->fp_sp_offset
> 0)
7970 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
7972 /* MIPS16 code offsets the frame pointer by the size of the outgoing
7973 arguments. This tends to increase the chances of using unextended
7974 instructions for local variables and incoming arguments. */
7976 frame
->hard_frame_pointer_offset
= frame
->args_size
;
7979 /* Return the style of GP load sequence that is being used for the
7980 current function. */
7982 enum mips_loadgp_style
7983 mips_current_loadgp_style (void)
7985 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== 0)
7991 if (TARGET_ABSOLUTE_ABICALLS
)
7992 return LOADGP_ABSOLUTE
;
7994 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
7997 /* Implement FRAME_POINTER_REQUIRED. */
8000 mips_frame_pointer_required (void)
8002 /* If the function contains dynamic stack allocations, we need to
8003 use the frame pointer to access the static parts of the frame. */
8004 if (current_function_calls_alloca
)
8007 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8008 reload may be unable to compute the address of a local variable,
8009 since there is no way to add a large constant to the stack pointer
8010 without using a second temporary register. */
8013 mips_compute_frame_info ();
8014 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
8021 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
8022 pointer or argument pointer. TO is either the stack pointer or
8023 hard frame pointer. */
8026 mips_initial_elimination_offset (int from
, int to
)
8028 HOST_WIDE_INT offset
;
8030 mips_compute_frame_info ();
8032 /* Set OFFSET to the offset from the soft frame pointer, which is also
8033 the offset from the end-of-prologue stack pointer. */
8036 case FRAME_POINTER_REGNUM
:
8040 case ARG_POINTER_REGNUM
:
8041 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
8048 if (to
== HARD_FRAME_POINTER_REGNUM
)
8049 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8054 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
8055 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
8058 mips_extra_live_on_entry (bitmap regs
)
8060 if (TARGET_USE_GOT
&& !TARGET_ABSOLUTE_ABICALLS
)
8061 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
8064 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
8065 back to a previous frame. */
8068 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
8073 return get_hard_reg_initial_val (Pmode
, GP_REG_FIRST
+ 31);
8076 /* Emit code to change the current function's return address to
8077 ADDRESS. SCRATCH is available as a scratch register, if needed.
8078 ADDRESS and SCRATCH are both word-mode GPRs. */
8081 mips_set_return_address (rtx address
, rtx scratch
)
8085 gcc_assert ((cfun
->machine
->frame
.mask
>> 31) & 1);
8086 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
8087 cfun
->machine
->frame
.gp_sp_offset
);
8089 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
8092 /* Restore $gp from its save slot. Valid only when using o32 or
8096 mips_restore_gp (void)
8100 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
);
8102 address
= mips_add_offset (pic_offset_table_rtx
,
8103 frame_pointer_needed
8104 ? hard_frame_pointer_rtx
8105 : stack_pointer_rtx
,
8106 current_function_outgoing_args_size
);
8108 mips_emit_move (pic_offset_table_rtx
, gen_frame_mem (Pmode
, address
));
8109 if (!TARGET_EXPLICIT_RELOCS
)
8110 emit_insn (gen_blockage ());
8113 /* A function to save or store a register. The first argument is the
8114 register and the second is the stack slot. */
8115 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
8117 /* Use FN to save or restore register REGNO. MODE is the register's
8118 mode and OFFSET is the offset of its save slot from the current
8122 mips_save_restore_reg (enum machine_mode mode
, int regno
,
8123 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
8127 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
8129 fn (gen_rtx_REG (mode
, regno
), mem
);
8133 /* Call FN for each register that is saved by the current function.
8134 SP_OFFSET is the offset of the current stack pointer from the start
8138 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
8140 enum machine_mode fpr_mode
;
8141 HOST_WIDE_INT offset
;
8144 /* Save registers starting from high to low. The debuggers prefer at least
8145 the return register be stored at func+4, and also it allows us not to
8146 need a nop in the epilogue if at least one register is reloaded in
8147 addition to return address. */
8148 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
8149 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
8150 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
8152 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
8153 offset
-= UNITS_PER_WORD
;
8156 /* This loop must iterate over the same space as its companion in
8157 mips_compute_frame_info. */
8158 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
8159 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
8160 for (regno
= (FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1);
8161 regno
>= FP_REG_FIRST
;
8162 regno
-= MAX_FPRS_PER_FMT
)
8163 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
8165 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
8166 offset
-= GET_MODE_SIZE (fpr_mode
);
8170 /* If we're generating n32 or n64 abicalls, and the current function
8171 does not use $28 as its global pointer, emit a cplocal directive.
8172 Use pic_offset_table_rtx as the argument to the directive. */
8175 mips_output_cplocal (void)
8177 if (!TARGET_EXPLICIT_RELOCS
8178 && cfun
->machine
->global_pointer
> 0
8179 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
8180 output_asm_insn (".cplocal %+", 0);
8183 /* Set up the stack and frame (if desired) for the function. */
8186 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8189 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
8191 #ifdef SDB_DEBUGGING_INFO
8192 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
8193 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
8196 /* In mips16 mode, we may need to generate a 32 bit to handle
8197 floating point arguments. The linker will arrange for any 32-bit
8198 functions to call this stub, which will then jump to the 16-bit
8201 && TARGET_HARD_FLOAT_ABI
8202 && current_function_args_info
.fp_code
!= 0)
8203 build_mips16_function_stub ();
8205 /* Select the mips16 mode for this function. */
8207 fprintf (file
, "\t.set\tmips16\n");
8209 fprintf (file
, "\t.set\tnomips16\n");
8211 if (!FUNCTION_NAME_ALREADY_DECLARED
)
8213 /* Get the function name the same way that toplev.c does before calling
8214 assemble_start_function. This is needed so that the name used here
8215 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8216 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8218 if (!flag_inhibit_size_directive
)
8220 fputs ("\t.ent\t", file
);
8221 assemble_name (file
, fnname
);
8225 assemble_name (file
, fnname
);
8226 fputs (":\n", file
);
8229 /* Stop mips_file_end from treating this function as external. */
8230 if (TARGET_IRIX
&& mips_abi
== ABI_32
)
8231 TREE_ASM_WRITTEN (DECL_NAME (cfun
->decl
)) = 1;
8233 if (!flag_inhibit_size_directive
)
8235 /* .frame FRAMEREG, FRAMESIZE, RETREG */
8237 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
8238 "# vars= " HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
8239 ", args= " HOST_WIDE_INT_PRINT_DEC
8240 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
8241 (reg_names
[(frame_pointer_needed
)
8242 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
8243 (frame_pointer_needed
8244 ? tsize
- cfun
->machine
->frame
.hard_frame_pointer_offset
8246 reg_names
[GP_REG_FIRST
+ 31],
8247 cfun
->machine
->frame
.var_size
,
8248 cfun
->machine
->frame
.num_gp
,
8249 cfun
->machine
->frame
.num_fp
,
8250 cfun
->machine
->frame
.args_size
,
8251 cfun
->machine
->frame
.cprestore_size
);
8253 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
8254 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
8255 cfun
->machine
->frame
.mask
,
8256 cfun
->machine
->frame
.gp_save_offset
);
8257 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
8258 cfun
->machine
->frame
.fmask
,
8259 cfun
->machine
->frame
.fp_save_offset
);
8262 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
8263 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
8266 if (mips_current_loadgp_style () == LOADGP_OLDABI
)
8268 /* Handle the initialization of $gp for SVR4 PIC. */
8269 if (!cfun
->machine
->all_noreorder_p
)
8270 output_asm_insn ("%(.cpload\t%^%)", 0);
8272 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8274 else if (cfun
->machine
->all_noreorder_p
)
8275 output_asm_insn ("%(%<", 0);
8277 /* Tell the assembler which register we're using as the global
8278 pointer. This is needed for thunks, since they can use either
8279 explicit relocs or assembler macros. */
8280 mips_output_cplocal ();
8283 /* Do any necessary cleanup after a function to restore stack, frame,
8286 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
8289 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8290 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8292 /* Reinstate the normal $gp. */
8293 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
8294 mips_output_cplocal ();
8296 if (cfun
->machine
->all_noreorder_p
)
8298 /* Avoid using %>%) since it adds excess whitespace. */
8299 output_asm_insn (".set\tmacro", 0);
8300 output_asm_insn (".set\treorder", 0);
8301 set_noreorder
= set_nomacro
= 0;
8304 if (!FUNCTION_NAME_ALREADY_DECLARED
&& !flag_inhibit_size_directive
)
8308 /* Get the function name the same way that toplev.c does before calling
8309 assemble_start_function. This is needed so that the name used here
8310 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8311 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8312 fputs ("\t.end\t", file
);
8313 assemble_name (file
, fnname
);
8318 /* Save register REG to MEM. Make the instruction frame-related. */
8321 mips_save_reg (rtx reg
, rtx mem
)
8323 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
8327 if (mips_split_64bit_move_p (mem
, reg
))
8328 mips_split_doubleword_move (mem
, reg
);
8330 mips_emit_move (mem
, reg
);
8332 x1
= mips_frame_set (mips_subword (mem
, 0), mips_subword (reg
, 0));
8333 x2
= mips_frame_set (mips_subword (mem
, 1), mips_subword (reg
, 1));
8334 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
8339 && REGNO (reg
) != GP_REG_FIRST
+ 31
8340 && !M16_REG_P (REGNO (reg
)))
8342 /* Save a non-mips16 register by moving it through a temporary.
8343 We don't need to do this for $31 since there's a special
8344 instruction for it. */
8345 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg
)), reg
);
8346 mips_emit_move (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
8349 mips_emit_move (mem
, reg
);
8351 mips_set_frame_expr (mips_frame_set (mem
, reg
));
8355 /* The __gnu_local_gp symbol. */
8357 static GTY(()) rtx mips_gnu_local_gp
;
8359 /* If we're generating n32 or n64 abicalls, emit instructions
8360 to set up the global pointer. */
8363 mips_emit_loadgp (void)
8365 rtx addr
, offset
, incoming_address
, base
, index
;
8367 switch (mips_current_loadgp_style ())
8369 case LOADGP_ABSOLUTE
:
8370 if (mips_gnu_local_gp
== NULL
)
8372 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
8373 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
8375 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp
));
8379 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
8380 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
8381 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
8382 emit_insn (gen_loadgp_newabi (offset
, incoming_address
));
8383 if (!TARGET_EXPLICIT_RELOCS
)
8384 emit_insn (gen_loadgp_blockage ());
8388 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
8389 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
8390 emit_insn (gen_loadgp_rtp (base
, index
));
8391 if (!TARGET_EXPLICIT_RELOCS
)
8392 emit_insn (gen_loadgp_blockage ());
8400 /* Expand the prologue into a bunch of separate insns. */
8403 mips_expand_prologue (void)
8409 if (cfun
->machine
->global_pointer
> 0)
8410 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
8412 size
= cfun
->machine
->frame
.total_size
;
8414 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8415 bytes beforehand; this is enough to cover the register save area
8416 without going out of range. */
8417 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
8419 HOST_WIDE_INT step1
;
8421 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
8423 if (GENERATE_MIPS16E_SAVE_RESTORE
)
8425 HOST_WIDE_INT offset
;
8426 unsigned int mask
, regno
;
8428 /* Try to merge argument stores into the save instruction. */
8429 nargs
= mips16e_collect_argument_saves ();
8431 /* Build the save instruction. */
8432 mask
= cfun
->machine
->frame
.mask
;
8433 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
8435 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8438 /* Check if we need to save other registers. */
8439 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
8440 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
8442 offset
-= UNITS_PER_WORD
;
8443 mips_save_restore_reg (word_mode
, regno
,
8444 offset
, mips_save_reg
);
8449 insn
= gen_add3_insn (stack_pointer_rtx
,
8452 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8454 mips_for_each_saved_reg (size
, mips_save_reg
);
8458 /* Allocate the rest of the frame. */
8461 if (SMALL_OPERAND (-size
))
8462 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
8464 GEN_INT (-size
)))) = 1;
8467 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
8470 /* There are no instructions to add or subtract registers
8471 from the stack pointer, so use the frame pointer as a
8472 temporary. We should always be using a frame pointer
8473 in this case anyway. */
8474 gcc_assert (frame_pointer_needed
);
8475 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8476 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
8477 hard_frame_pointer_rtx
,
8478 MIPS_PROLOGUE_TEMP (Pmode
)));
8479 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
8482 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
8484 MIPS_PROLOGUE_TEMP (Pmode
)));
8486 /* Describe the combined effect of the previous instructions. */
8488 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8489 plus_constant (stack_pointer_rtx
, -size
)));
8493 /* Set up the frame pointer, if we're using one. */
8494 if (frame_pointer_needed
)
8496 HOST_WIDE_INT offset
;
8498 offset
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8501 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8502 RTX_FRAME_RELATED_P (insn
) = 1;
8504 else if (SMALL_OPERAND (offset
))
8506 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
8507 stack_pointer_rtx
, GEN_INT (offset
));
8508 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8512 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
8513 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8514 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
8515 hard_frame_pointer_rtx
,
8516 MIPS_PROLOGUE_TEMP (Pmode
)));
8518 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
8519 plus_constant (stack_pointer_rtx
, offset
)));
8523 mips_emit_loadgp ();
8525 /* If generating o32/o64 abicalls, save $gp on the stack. */
8526 if (TARGET_ABICALLS
&& TARGET_OLDABI
&& !current_function_is_leaf
)
8527 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size
)));
8529 /* If we are profiling, make sure no instructions are scheduled before
8530 the call to mcount. */
8532 if (current_function_profile
)
8533 emit_insn (gen_blockage ());
8536 /* Emit instructions to restore register REG from slot MEM. */
8539 mips_restore_reg (rtx reg
, rtx mem
)
8541 /* There's no mips16 instruction to load $31 directly. Load into
8542 $7 instead and adjust the return insn appropriately. */
8543 if (TARGET_MIPS16
&& REGNO (reg
) == GP_REG_FIRST
+ 31)
8544 reg
= gen_rtx_REG (GET_MODE (reg
), 7);
8546 if (TARGET_MIPS16
&& !M16_REG_P (REGNO (reg
)))
8548 /* Can't restore directly; move through a temporary. */
8549 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
8550 mips_emit_move (reg
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
8553 mips_emit_move (reg
, mem
);
8557 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
8558 if this epilogue precedes a sibling call, false if it is for a normal
8559 "epilogue" pattern. */
8562 mips_expand_epilogue (int sibcall_p
)
8564 HOST_WIDE_INT step1
, step2
;
8567 if (!sibcall_p
&& mips_can_use_return_insn ())
8569 emit_jump_insn (gen_return ());
8573 /* In mips16 mode, if the return value should go into a floating-point
8574 register, we need to call a helper routine to copy it over. */
8575 if (mips16_cfun_returns_in_fpr_p ())
8576 mips16_copy_fpr_return_value ();
8578 /* Split the frame into two. STEP1 is the amount of stack we should
8579 deallocate before restoring the registers. STEP2 is the amount we
8580 should deallocate afterwards.
8582 Start off by assuming that no registers need to be restored. */
8583 step1
= cfun
->machine
->frame
.total_size
;
8586 /* Work out which register holds the frame address. */
8587 if (!frame_pointer_needed
)
8588 base
= stack_pointer_rtx
;
8591 base
= hard_frame_pointer_rtx
;
8592 step1
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8595 /* If we need to restore registers, deallocate as much stack as
8596 possible in the second step without going out of range. */
8597 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
8599 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
8603 /* Set TARGET to BASE + STEP1. */
8609 /* Get an rtx for STEP1 that we can add to BASE. */
8610 adjust
= GEN_INT (step1
);
8611 if (!SMALL_OPERAND (step1
))
8613 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
8614 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
8617 /* Normal mode code can copy the result straight into $sp. */
8619 target
= stack_pointer_rtx
;
8621 emit_insn (gen_add3_insn (target
, base
, adjust
));
8624 /* Copy TARGET into the stack pointer. */
8625 if (target
!= stack_pointer_rtx
)
8626 mips_emit_move (stack_pointer_rtx
, target
);
8628 /* If we're using addressing macros, $gp is implicitly used by all
8629 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8631 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
8632 emit_insn (gen_blockage ());
8634 if (GENERATE_MIPS16E_SAVE_RESTORE
&& cfun
->machine
->frame
.mask
!= 0)
8636 unsigned int regno
, mask
;
8637 HOST_WIDE_INT offset
;
8640 /* Generate the restore instruction. */
8641 mask
= cfun
->machine
->frame
.mask
;
8642 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
8644 /* Restore any other registers manually. */
8645 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
8646 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
8648 offset
-= UNITS_PER_WORD
;
8649 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
8652 /* Restore the remaining registers and deallocate the final bit
8654 emit_insn (restore
);
8658 /* Restore the registers. */
8659 mips_for_each_saved_reg (cfun
->machine
->frame
.total_size
- step2
,
8662 /* Deallocate the final bit of the frame. */
8664 emit_insn (gen_add3_insn (stack_pointer_rtx
,
8669 /* Add in the __builtin_eh_return stack adjustment. We need to
8670 use a temporary in mips16 code. */
8671 if (current_function_calls_eh_return
)
8675 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
8676 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
8677 MIPS_EPILOGUE_TEMP (Pmode
),
8678 EH_RETURN_STACKADJ_RTX
));
8679 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
8682 emit_insn (gen_add3_insn (stack_pointer_rtx
,
8684 EH_RETURN_STACKADJ_RTX
));
8689 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8690 path will restore the return address into $7 rather than $31. */
8692 && !GENERATE_MIPS16E_SAVE_RESTORE
8693 && (cfun
->machine
->frame
.mask
& RA_MASK
) != 0)
8694 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
8695 GP_REG_FIRST
+ 7)));
8697 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
8698 GP_REG_FIRST
+ 31)));
8702 /* Return nonzero if this function is known to have a null epilogue.
8703 This allows the optimizer to omit jumps to jumps if no stack
8707 mips_can_use_return_insn (void)
8709 if (! reload_completed
)
8712 if (current_function_profile
)
8715 /* In mips16 mode, a function that returns a floating point value
8716 needs to arrange to copy the return value into the floating point
8718 if (mips16_cfun_returns_in_fpr_p ())
8721 return cfun
->machine
->frame
.total_size
== 0;
8724 /* Return true if register REGNO can store a value of mode MODE.
8725 The result of this function is cached in mips_hard_regno_mode_ok. */
8728 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
8731 enum mode_class
class;
8733 if (mode
== CCV2mode
)
8736 && (regno
- ST_REG_FIRST
) % 2 == 0);
8738 if (mode
== CCV4mode
)
8741 && (regno
- ST_REG_FIRST
) % 4 == 0);
8746 return regno
== FPSW_REGNUM
;
8748 return (ST_REG_P (regno
)
8750 || FP_REG_P (regno
));
8753 size
= GET_MODE_SIZE (mode
);
8754 class = GET_MODE_CLASS (mode
);
8756 if (GP_REG_P (regno
))
8757 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
8759 if (FP_REG_P (regno
)
8760 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
8761 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
8763 /* Allow TFmode for CCmode reloads. */
8764 if (mode
== TFmode
&& ISA_HAS_8CC
)
8767 if (class == MODE_FLOAT
8768 || class == MODE_COMPLEX_FLOAT
8769 || class == MODE_VECTOR_FLOAT
)
8770 return size
<= UNITS_PER_FPVALUE
;
8772 /* Allow integer modes that fit into a single register. We need
8773 to put integers into FPRs when using instructions like CVT
8774 and TRUNC. There's no point allowing sizes smaller than a word,
8775 because the FPU has no appropriate load/store instructions. */
8776 if (class == MODE_INT
)
8777 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
8780 if (ACC_REG_P (regno
)
8781 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
8783 if (size
<= UNITS_PER_WORD
)
8786 if (size
<= UNITS_PER_WORD
* 2)
8787 return (DSP_ACC_REG_P (regno
)
8788 ? ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0
8789 : regno
== MD_REG_FIRST
);
8792 if (ALL_COP_REG_P (regno
))
8793 return class == MODE_INT
&& size
<= UNITS_PER_WORD
;
8798 /* Implement HARD_REGNO_NREGS. */
8801 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
8803 if (ST_REG_P (regno
))
8804 /* The size of FP status registers is always 4, because they only hold
8805 CCmode values, and CCmode is always considered to be 4 bytes wide. */
8806 return (GET_MODE_SIZE (mode
) + 3) / 4;
8808 if (FP_REG_P (regno
))
8809 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
8811 /* All other registers are word-sized. */
8812 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8815 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
8816 in mips_hard_regno_nregs. */
8819 mips_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
8825 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) class]);
8826 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
8828 size
= MIN (size
, 4);
8829 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
8831 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
8833 size
= MIN (size
, UNITS_PER_FPREG
);
8834 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
8836 if (!hard_reg_set_empty_p (left
))
8837 size
= MIN (size
, UNITS_PER_WORD
);
8838 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
8841 /* Return true if registers of class CLASS cannot change from mode FROM
8845 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED
,
8846 enum machine_mode to ATTRIBUTE_UNUSED
,
8847 enum reg_class
class)
8849 /* There are several problems with changing the modes of values
8850 in floating-point registers:
8852 - When a multi-word value is stored in paired floating-point
8853 registers, the first register always holds the low word.
8854 We therefore can't allow FPRs to change between single-word
8855 and multi-word modes on big-endian targets.
8857 - GCC assumes that each word of a multiword register can be accessed
8858 individually using SUBREGs. This is not true for floating-point
8859 registers if they are bigger than a word.
8861 - Loading a 32-bit value into a 64-bit floating-point register
8862 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8863 We can't allow FPRs to change from SImode to to a wider mode on
8866 - If the FPU has already interpreted a value in one format, we must
8867 not ask it to treat the value as having a different format.
8869 We therefore only allow changes between 4-byte and smaller integer
8870 values, all of which have the "W" format as far as the FPU is
8872 return (reg_classes_intersect_p (FP_REGS
, class)
8873 && (GET_MODE_CLASS (from
) != MODE_INT
8874 || GET_MODE_CLASS (to
) != MODE_INT
8875 || GET_MODE_SIZE (from
) > 4
8876 || GET_MODE_SIZE (to
) > 4));
8879 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
8882 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
8887 return TARGET_HARD_FLOAT
;
8890 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
8893 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
8900 /* Implement PREFERRED_RELOAD_CLASS. */
8903 mips_preferred_reload_class (rtx x
, enum reg_class
class)
8905 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, class))
8908 if (reg_class_subset_p (FP_REGS
, class)
8909 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
8912 if (reg_class_subset_p (GR_REGS
, class))
8915 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, class))
8921 /* Return a number assessing the cost of moving a register in class
8922 FROM to class TO. The classes are expressed using the enumeration
8923 values such as `GENERAL_REGS'. A value of 2 is the default; other
8924 values are interpreted relative to that.
8926 It is not required that the cost always equal 2 when FROM is the
8927 same as TO; on some machines it is expensive to move between
8928 registers if they are not general registers.
8930 If reload sees an insn consisting of a single `set' between two
8931 hard registers, and if `REGISTER_MOVE_COST' applied to their
8932 classes returns a value of 2, reload does not check to ensure that
8933 the constraints of the insn are met. Setting a cost of other than
8934 2 will allow reload to verify that the constraints are met. You
8935 should do this if the `movM' pattern's constraints do not allow
8938 ??? We make the cost of moving from HI/LO into general
8939 registers the same as for one of moving general registers to
8940 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8941 pseudo to HI/LO. This might hurt optimizations though, it
8942 isn't clear if it is wise. And it might not work in all cases. We
8943 could solve the DImode LO reg problem by using a multiply, just
8944 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8945 problem by using divide instructions. divu puts the remainder in
8946 the HI reg, so doing a divide by -1 will move the value in the HI
8947 reg for all values except -1. We could handle that case by using a
8948 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8949 a compare/branch to test the input value to see which instruction
8950 we need to use. This gets pretty messy, but it is feasible. */
8953 mips_register_move_cost (enum machine_mode mode
,
8954 enum reg_class to
, enum reg_class from
)
8958 if (reg_class_subset_p (from
, GENERAL_REGS
)
8959 && reg_class_subset_p (to
, GENERAL_REGS
))
8961 if (reg_class_subset_p (from
, M16_REGS
)
8962 || reg_class_subset_p (to
, M16_REGS
))
8968 else if (reg_class_subset_p (from
, GENERAL_REGS
))
8970 if (reg_class_subset_p (to
, GENERAL_REGS
))
8972 if (reg_class_subset_p (to
, FP_REGS
))
8974 if (reg_class_subset_p (to
, ALL_COP_AND_GR_REGS
))
8976 if (reg_class_subset_p (to
, ACC_REGS
))
8979 else if (reg_class_subset_p (to
, GENERAL_REGS
))
8981 if (reg_class_subset_p (from
, FP_REGS
))
8983 if (reg_class_subset_p (from
, ST_REGS
))
8984 /* LUI followed by MOVF. */
8986 if (reg_class_subset_p (from
, ALL_COP_AND_GR_REGS
))
8988 if (reg_class_subset_p (from
, ACC_REGS
))
8991 else if (reg_class_subset_p (from
, FP_REGS
))
8993 if (reg_class_subset_p (to
, FP_REGS
)
8994 && mips_mode_ok_for_mov_fmt_p (mode
))
8996 if (reg_class_subset_p (to
, ST_REGS
))
8997 /* An expensive sequence. */
9004 /* This function returns the register class required for a secondary
9005 register when copying between one of the registers in CLASS, and X,
9006 using MODE. If IN_P is nonzero, the copy is going from X to the
9007 register, otherwise the register is the source. A return value of
9008 NO_REGS means that no secondary register is required. */
9011 mips_secondary_reload_class (enum reg_class
class,
9012 enum machine_mode mode
, rtx x
, int in_p
)
9016 /* If X is a constant that cannot be loaded into $25, it must be loaded
9017 into some other GPR. No other register class allows a direct move. */
9018 if (mips_dangerous_for_la25_p (x
))
9019 return reg_class_subset_p (class, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
9021 regno
= true_regnum (x
);
9024 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9025 if (!reg_class_subset_p (class, M16_REGS
) && !M16_REG_P (regno
))
9028 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9029 if (in_p
? reg_classes_intersect_p (class, ACC_REGS
) : ACC_REG_P (regno
))
9035 /* Copying from accumulator registers to anywhere other than a general
9036 register requires a temporary general register. */
9037 if (reg_class_subset_p (class, ACC_REGS
))
9038 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
9039 if (ACC_REG_P (regno
))
9040 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
9042 /* We can only copy a value to a condition code register from a
9043 floating point register, and even then we require a scratch
9044 floating point register. We can only copy a value out of a
9045 condition code register into a general register. */
9046 if (reg_class_subset_p (class, ST_REGS
))
9050 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
9052 if (ST_REG_P (regno
))
9056 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
9059 if (reg_class_subset_p (class, FP_REGS
))
9062 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
9063 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9064 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9067 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
9068 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9071 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (x
))
9072 /* We can force the constant to memory and use lwc1
9073 and ldc1. As above, we will use pairs of lwc1s if
9074 ldc1 is not supported. */
9077 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
9078 /* In this case we can use mov.fmt. */
9081 /* Otherwise, we need to reload through an integer register. */
9084 if (FP_REG_P (regno
))
9085 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
9090 /* SImode values are represented as sign-extended to DImode. */
9093 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
9095 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
9102 mips_valid_pointer_mode (enum machine_mode mode
)
9104 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9107 /* Target hook for vector_mode_supported_p. */
9110 mips_vector_mode_supported_p (enum machine_mode mode
)
9115 return TARGET_PAIRED_SINGLE_FLOAT
;
9132 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9135 mips_scalar_mode_supported_p (enum machine_mode mode
)
9137 if (ALL_FIXED_POINT_MODE_P (mode
)
9138 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
9141 return default_scalar_mode_supported_p (mode
);
9143 /* This function does three things:
9145 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9146 - Register the mips16 hardware floating point stubs.
9147 - Register the gofast functions if selected using --enable-gofast. */
9149 #include "config/gofast.h"
9152 mips_init_libfuncs (void)
9154 if (TARGET_FIX_VR4120
)
9156 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
9157 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
9160 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
9162 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
9163 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
9164 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
9165 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
9167 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
9168 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
9169 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
9170 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
9171 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
9172 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
9173 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
9175 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
9176 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
9177 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
9179 if (TARGET_DOUBLE_FLOAT
)
9181 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
9182 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
9183 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
9184 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
9186 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
9187 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
9188 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
9189 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
9190 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
9191 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
9192 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
9194 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__mips16_extendsfdf2");
9195 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__mips16_truncdfsf2");
9197 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__mips16_fix_truncdfsi");
9198 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__mips16_floatsidf");
9199 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__mips16_floatunsidf");
9203 gofast_maybe_init_libfuncs ();
9206 /* Return the length of INSN. LENGTH is the initial length computed by
9207 attributes in the machine-description file. */
9210 mips_adjust_insn_length (rtx insn
, int length
)
9212 /* A unconditional jump has an unfilled delay slot if it is not part
9213 of a sequence. A conditional jump normally has a delay slot, but
9214 does not on MIPS16. */
9215 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
9218 /* See how many nops might be needed to avoid hardware hazards. */
9219 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
9220 switch (get_attr_hazard (insn
))
9234 /* All MIPS16 instructions are a measly two bytes. */
9242 /* Return an asm sequence to start a noat block and load the address
9243 of a label into $1. */
9246 mips_output_load_label (void)
9248 if (TARGET_EXPLICIT_RELOCS
)
9252 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9255 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9258 if (ISA_HAS_LOAD_DELAY
)
9259 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9260 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9264 if (Pmode
== DImode
)
9265 return "%[dla\t%@,%0";
9267 return "%[la\t%@,%0";
9271 /* Return the assembly code for INSN, which has the operands given by
9272 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9273 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9274 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9275 version of BRANCH_IF_TRUE. */
9278 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
9279 const char *branch_if_true
,
9280 const char *branch_if_false
)
9282 unsigned int length
;
9283 rtx taken
, not_taken
;
9285 length
= get_attr_length (insn
);
9288 /* Just a simple conditional branch. */
9289 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9290 return branch_if_true
;
9293 /* Generate a reversed branch around a direct jump. This fallback does
9294 not use branch-likely instructions. */
9295 mips_branch_likely
= false;
9296 not_taken
= gen_label_rtx ();
9297 taken
= operands
[1];
9299 /* Generate the reversed branch to NOT_TAKEN. */
9300 operands
[1] = not_taken
;
9301 output_asm_insn (branch_if_false
, operands
);
9303 /* If INSN has a delay slot, we must provide delay slots for both the
9304 branch to NOT_TAKEN and the conditional jump. We must also ensure
9305 that INSN's delay slot is executed in the appropriate cases. */
9308 /* This first delay slot will always be executed, so use INSN's
9309 delay slot if is not annulled. */
9310 if (!INSN_ANNULLED_BRANCH_P (insn
))
9312 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9313 asm_out_file
, optimize
, 1, NULL
);
9314 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9317 output_asm_insn ("nop", 0);
9318 fprintf (asm_out_file
, "\n");
9321 /* Output the unconditional branch to TAKEN. */
9323 output_asm_insn ("j\t%0%/", &taken
);
9326 output_asm_insn (mips_output_load_label (), &taken
);
9327 output_asm_insn ("jr\t%@%]%/", 0);
9330 /* Now deal with its delay slot; see above. */
9333 /* This delay slot will only be executed if the branch is taken.
9334 Use INSN's delay slot if is annulled. */
9335 if (INSN_ANNULLED_BRANCH_P (insn
))
9337 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9338 asm_out_file
, optimize
, 1, NULL
);
9339 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9342 output_asm_insn ("nop", 0);
9343 fprintf (asm_out_file
, "\n");
9346 /* Output NOT_TAKEN. */
9347 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
9348 CODE_LABEL_NUMBER (not_taken
));
9352 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9353 if some ordered condition is true. The condition is given by
9354 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9355 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9356 its second is always zero. */
9359 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
9361 const char *branch
[2];
9363 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9364 Make BRANCH[0] branch on the inverse condition. */
9365 switch (GET_CODE (operands
[0]))
9367 /* These cases are equivalent to comparisons against zero. */
9369 inverted_p
= !inverted_p
;
9372 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%1");
9373 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%1");
9376 /* These cases are always true or always false. */
9378 inverted_p
= !inverted_p
;
9381 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%1");
9382 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%1");
9386 branch
[!inverted_p
] = MIPS_BRANCH ("b%C0z", "%2,%1");
9387 branch
[inverted_p
] = MIPS_BRANCH ("b%N0z", "%2,%1");
9390 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
9393 /* Used to output div or ddiv instruction DIVISION, which has the operands
9394 given by OPERANDS. Add in a divide-by-zero check if needed.
9396 When working around R4000 and R4400 errata, we need to make sure that
9397 the division is not immediately followed by a shift[1][2]. We also
9398 need to stop the division from being put into a branch delay slot[3].
9399 The easiest way to avoid both problems is to add a nop after the
9400 division. When a divide-by-zero check is needed, this nop can be
9401 used to fill the branch delay slot.
9403 [1] If a double-word or a variable shift executes immediately
9404 after starting an integer division, the shift may give an
9405 incorrect result. See quotations of errata #16 and #28 from
9406 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9407 in mips.md for details.
9409 [2] A similar bug to [1] exists for all revisions of the
9410 R4000 and the R4400 when run in an MC configuration.
9411 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9413 "19. In this following sequence:
9415 ddiv (or ddivu or div or divu)
9416 dsll32 (or dsrl32, dsra32)
9418 if an MPT stall occurs, while the divide is slipping the cpu
9419 pipeline, then the following double shift would end up with an
9422 Workaround: The compiler needs to avoid generating any
9423 sequence with divide followed by extended double shift."
9425 This erratum is also present in "MIPS R4400MC Errata, Processor
9426 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9427 & 3.0" as errata #10 and #4, respectively.
9429 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9430 (also valid for MIPS R4000MC processors):
9432 "52. R4000SC: This bug does not apply for the R4000PC.
9434 There are two flavors of this bug:
9436 1) If the instruction just after divide takes an RF exception
9437 (tlb-refill, tlb-invalid) and gets an instruction cache
9438 miss (both primary and secondary) and the line which is
9439 currently in secondary cache at this index had the first
9440 data word, where the bits 5..2 are set, then R4000 would
9441 get a wrong result for the div.
9446 ------------------- # end-of page. -tlb-refill
9451 ------------------- # end-of page. -tlb-invalid
9454 2) If the divide is in the taken branch delay slot, where the
9455 target takes RF exception and gets an I-cache miss for the
9456 exception vector or where I-cache miss occurs for the
9457 target address, under the above mentioned scenarios, the
9458 div would get wrong results.
9461 j r2 # to next page mapped or unmapped
9462 div r8,r9 # this bug would be there as long
9463 # as there is an ICache miss and
9464 nop # the "data pattern" is present
9467 beq r0, r0, NextPage # to Next page
9471 This bug is present for div, divu, ddiv, and ddivu
9474 Workaround: For item 1), OS could make sure that the next page
9475 after the divide instruction is also mapped. For item 2), the
9476 compiler could make sure that the divide instruction is not in
9477 the branch delay slot."
9479 These processors have PRId values of 0x00004220 and 0x00004300 for
9480 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9483 mips_output_division (const char *division
, rtx
*operands
)
9488 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
9490 output_asm_insn (s
, operands
);
9493 if (TARGET_CHECK_ZERO_DIV
)
9497 output_asm_insn (s
, operands
);
9498 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
9500 else if (GENERATE_DIVIDE_TRAPS
)
9502 output_asm_insn (s
, operands
);
9507 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
9508 output_asm_insn (s
, operands
);
9509 s
= "break\t7%)\n1:";
9515 /* Return true if INSN is a multiply-add or multiply-subtract
9516 instruction and PREV assigns to the accumulator operand. */
9519 mips_linked_madd_p (rtx prev
, rtx insn
)
9523 x
= single_set (insn
);
9529 if (GET_CODE (x
) == PLUS
9530 && GET_CODE (XEXP (x
, 0)) == MULT
9531 && reg_set_p (XEXP (x
, 1), prev
))
9534 if (GET_CODE (x
) == MINUS
9535 && GET_CODE (XEXP (x
, 1)) == MULT
9536 && reg_set_p (XEXP (x
, 0), prev
))
9542 /* Implements a store data bypass check. We need this because the cprestore
9543 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9544 default routine to abort. We just return false for that case. */
9545 /* ??? Should try to give a better result here than assuming false. */
9548 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
9550 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
9553 return ! store_data_bypass_p (out_insn
, in_insn
);
9556 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9557 dependencies have no cost, except on the 20Kc where output-dependence
9558 is treated like input-dependence. */
9561 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
9562 rtx dep ATTRIBUTE_UNUSED
, int cost
)
9564 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
9567 if (REG_NOTE_KIND (link
) != 0)
9572 /* Return the number of instructions that can be issued per cycle. */
9575 mips_issue_rate (void)
9579 case PROCESSOR_74KC
:
9580 case PROCESSOR_74KF2_1
:
9581 case PROCESSOR_74KF1_1
:
9582 case PROCESSOR_74KF3_2
:
9583 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9584 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9585 but in reality only a maximum of 3 insns can be issued as the
9586 floating point load/stores also require a slot in the AGEN pipe. */
9589 case PROCESSOR_20KC
:
9590 case PROCESSOR_R4130
:
9591 case PROCESSOR_R5400
:
9592 case PROCESSOR_R5500
:
9593 case PROCESSOR_R7000
:
9594 case PROCESSOR_R9000
:
9598 case PROCESSOR_SB1A
:
9599 /* This is actually 4, but we get better performance if we claim 3.
9600 This is partly because of unwanted speculative code motion with the
9601 larger number, and partly because in most common cases we can't
9602 reach the theoretical max of 4. */
9610 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9611 be as wide as the scheduling freedom in the DFA. */
9614 mips_multipass_dfa_lookahead (void)
9616 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9623 /* Remove the instruction at index LOWER from ready queue READY and
9624 reinsert it in front of the instruction at index HIGHER. LOWER must
9628 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
9633 new_head
= ready
[lower
];
9634 for (i
= lower
; i
< higher
; i
++)
9635 ready
[i
] = ready
[i
+ 1];
9636 ready
[i
] = new_head
;
9639 /* If the priority of the instruction at POS2 in the ready queue READY
9640 is within LIMIT units of that of the instruction at POS1, swap the
9641 instructions if POS2 is not already less than POS1. */
9644 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
9647 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
9651 ready
[pos1
] = ready
[pos2
];
9656 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9657 that may clobber hi or lo. */
9659 static rtx mips_macc_chains_last_hilo
;
9661 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9662 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9665 mips_macc_chains_record (rtx insn
)
9667 if (get_attr_may_clobber_hilo (insn
))
9668 mips_macc_chains_last_hilo
= insn
;
9671 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9672 has NREADY elements, looking for a multiply-add or multiply-subtract
9673 instruction that is cumulative with mips_macc_chains_last_hilo.
9674 If there is one, promote it ahead of anything else that might
9675 clobber hi or lo. */
9678 mips_macc_chains_reorder (rtx
*ready
, int nready
)
9682 if (mips_macc_chains_last_hilo
!= 0)
9683 for (i
= nready
- 1; i
>= 0; i
--)
9684 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
9686 for (j
= nready
- 1; j
> i
; j
--)
9687 if (recog_memoized (ready
[j
]) >= 0
9688 && get_attr_may_clobber_hilo (ready
[j
]))
9690 mips_promote_ready (ready
, i
, j
);
9697 /* The last instruction to be scheduled. */
9699 static rtx vr4130_last_insn
;
9701 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9702 points to an rtx that is initially an instruction. Nullify the rtx
9703 if the instruction uses the value of register X. */
9706 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
9708 rtx
*insn_ptr
= data
;
9711 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
9715 /* Return true if there is true register dependence between vr4130_last_insn
9719 vr4130_true_reg_dependence_p (rtx insn
)
9721 note_stores (PATTERN (vr4130_last_insn
),
9722 vr4130_true_reg_dependence_p_1
, &insn
);
9726 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9727 the ready queue and that INSN2 is the instruction after it, return
9728 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9729 in which INSN1 and INSN2 can probably issue in parallel, but for
9730 which (INSN2, INSN1) should be less sensitive to instruction
9731 alignment than (INSN1, INSN2). See 4130.md for more details. */
9734 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
9736 sd_iterator_def sd_it
;
9739 /* Check for the following case:
9741 1) there is some other instruction X with an anti dependence on INSN1;
9742 2) X has a higher priority than INSN2; and
9743 3) X is an arithmetic instruction (and thus has no unit restrictions).
9745 If INSN1 is the last instruction blocking X, it would better to
9746 choose (INSN1, X) over (INSN2, INSN1). */
9747 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
9748 if (DEP_TYPE (dep
) == REG_DEP_ANTI
9749 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
9750 && recog_memoized (DEP_CON (dep
)) >= 0
9751 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
9754 if (vr4130_last_insn
!= 0
9755 && recog_memoized (insn1
) >= 0
9756 && recog_memoized (insn2
) >= 0)
9758 /* See whether INSN1 and INSN2 use different execution units,
9759 or if they are both ALU-type instructions. If so, they can
9760 probably execute in parallel. */
9761 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
9762 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
9763 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
9765 /* If only one of the instructions has a dependence on
9766 vr4130_last_insn, prefer to schedule the other one first. */
9767 bool dep1
= vr4130_true_reg_dependence_p (insn1
);
9768 bool dep2
= vr4130_true_reg_dependence_p (insn2
);
9772 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9773 is not an ALU-type instruction and if INSN1 uses the same
9774 execution unit. (Note that if this condition holds, we already
9775 know that INSN2 uses a different execution unit.) */
9776 if (class1
!= VR4130_CLASS_ALU
9777 && recog_memoized (vr4130_last_insn
) >= 0
9778 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
9785 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9786 queue with at least two instructions. Swap the first two if
9787 vr4130_swap_insns_p says that it could be worthwhile. */
9790 vr4130_reorder (rtx
*ready
, int nready
)
9792 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
9793 mips_promote_ready (ready
, nready
- 2, nready
- 1);
9796 /* Record whether last 74k AGEN instruction was a load or store. */
9798 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
9800 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
9801 resets to TYPE_UNKNOWN state. */
9804 mips_74k_agen_init (rtx insn
)
9806 if (!insn
|| !NONJUMP_INSN_P (insn
))
9807 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
9808 else if (USEFUL_INSN_P (insn
))
9810 enum attr_type type
= get_attr_type (insn
);
9811 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
9812 mips_last_74k_agen_insn
= type
;
9816 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
9817 loads to be grouped together, and multiple stores to be grouped
9818 together. Swap things around in the ready queue to make this happen. */
9821 mips_74k_agen_reorder (rtx
*ready
, int nready
)
9824 int store_pos
, load_pos
;
9829 for (i
= nready
- 1; i
>= 0; i
--)
9831 rtx insn
= ready
[i
];
9832 if (USEFUL_INSN_P (insn
))
9833 switch (get_attr_type (insn
))
9836 if (store_pos
== -1)
9850 if (load_pos
== -1 || store_pos
== -1)
9853 switch (mips_last_74k_agen_insn
)
9856 /* Prefer to schedule loads since they have a higher latency. */
9858 /* Swap loads to the front of the queue. */
9859 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
9862 /* Swap stores to the front of the queue. */
9863 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
9870 /* Implement TARGET_SCHED_INIT. */
9873 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9874 int max_ready ATTRIBUTE_UNUSED
)
9876 mips_macc_chains_last_hilo
= 0;
9877 vr4130_last_insn
= 0;
9878 mips_74k_agen_init (NULL_RTX
);
9881 /* Implement TARGET_SCHED_REORDER and TARG_SCHED_REORDER2. */
9884 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9885 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
9887 if (!reload_completed
9890 mips_macc_chains_reorder (ready
, *nreadyp
);
9891 if (reload_completed
9893 && !TARGET_VR4130_ALIGN
9895 vr4130_reorder (ready
, *nreadyp
);
9897 mips_74k_agen_reorder (ready
, *nreadyp
);
9898 return mips_issue_rate ();
9901 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9904 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9908 mips_74k_agen_init (insn
);
9909 switch (GET_CODE (PATTERN (insn
)))
9913 /* Don't count USEs and CLOBBERs against the issue rate. */
9918 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9919 mips_macc_chains_record (insn
);
9920 vr4130_last_insn
= insn
;
9926 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9927 return the first operand of the associated "pref" or "prefx" insn. */
9930 mips_prefetch_cookie (rtx write
, rtx locality
)
9932 /* store_streamed / load_streamed. */
9933 if (INTVAL (locality
) <= 0)
9934 return GEN_INT (INTVAL (write
) + 4);
9937 if (INTVAL (locality
) <= 2)
9940 /* store_retained / load_retained. */
9941 return GEN_INT (INTVAL (write
) + 6);
9944 /* MIPS builtin function support. */
9946 struct builtin_description
9948 /* The code of the main .md file instruction. See mips_builtin_type
9949 for more information. */
9950 enum insn_code icode
;
9952 /* The floating-point comparison code to use with ICODE, if any. */
9953 enum mips_fp_condition cond
;
9955 /* The name of the builtin function. */
9958 /* Specifies how the function should be expanded. */
9959 enum mips_builtin_type builtin_type
;
9961 /* The function's prototype. */
9962 enum mips_function_type function_type
;
9964 /* The target flags required for this function. */
9968 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9969 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9970 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9971 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9972 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9974 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9976 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9977 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9978 "__builtin_mips_" #INSN "_" #COND "_s", \
9979 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9980 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9981 "__builtin_mips_" #INSN "_" #COND "_d", \
9982 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9984 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9985 The lower and upper forms require TARGET_FLAGS while the any and all
9986 forms require MASK_MIPS3D. */
9987 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9988 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9989 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9990 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9991 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9992 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9993 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9994 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9995 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9996 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9997 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9998 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9999 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10001 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10002 require MASK_MIPS3D. */
10003 #define CMP_4S_BUILTINS(INSN, COND) \
10004 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10005 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10006 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10008 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10009 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10010 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10013 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10014 instruction requires TARGET_FLAGS. */
10015 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10016 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10017 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10018 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10020 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10021 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10022 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10025 /* Define all the builtins related to c.cond.fmt condition COND. */
10026 #define CMP_BUILTINS(COND) \
10027 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10028 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10029 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10030 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10031 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10032 CMP_4S_BUILTINS (c, COND), \
10033 CMP_4S_BUILTINS (cabs, COND)
10035 static const struct builtin_description mips_bdesc
[] =
10037 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10038 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10039 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10040 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10041 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, MASK_PAIRED_SINGLE_FLOAT
),
10042 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10043 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10044 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10046 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
10047 MASK_PAIRED_SINGLE_FLOAT
),
10048 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10049 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10050 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10051 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10053 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10054 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10055 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10056 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10057 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10058 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10060 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10061 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10062 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10063 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10064 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10065 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10067 MIPS_FP_CONDITIONS (CMP_BUILTINS
)
10070 /* Builtin functions for the SB-1 processor. */
10072 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10074 static const struct builtin_description sb1_bdesc
[] =
10076 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
)
10079 /* Builtin functions for DSP ASE. */
10081 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10082 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10083 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10084 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10085 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10087 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10088 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10089 builtin_description fields. */
10090 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10091 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10092 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10094 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10095 branch instruction. TARGET_FLAGS is a builtin_description field. */
10096 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10097 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10098 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10100 static const struct builtin_description dsp_bdesc
[] =
10102 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10103 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10104 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10105 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10106 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10107 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10108 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10109 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10110 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10111 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10112 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10113 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10114 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10115 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, MASK_DSP
),
10116 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, MASK_DSP
),
10117 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10118 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10119 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10120 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10121 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10122 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10123 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10124 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10125 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10126 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10127 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10128 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10129 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10130 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10131 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10132 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10133 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10134 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10135 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10136 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10137 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10138 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10139 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10140 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10141 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10142 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10143 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10144 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10145 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10146 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10147 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, MASK_DSP
),
10148 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, MASK_DSP
),
10149 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10150 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10151 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10152 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10153 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10154 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10155 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10156 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10157 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10158 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10159 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10160 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10161 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, MASK_DSP
),
10162 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10163 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10164 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10165 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10166 BPOSGE_BUILTIN (32, MASK_DSP
),
10168 /* The following are for the MIPS DSP ASE REV 2. */
10169 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, MASK_DSPR2
),
10170 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10171 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10172 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10173 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10174 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10175 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10176 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10177 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10178 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10179 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10180 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10181 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10182 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10183 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10184 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10185 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10186 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10187 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10188 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10189 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10190 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSPR2
),
10191 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10192 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10193 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10194 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10195 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10196 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10197 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10198 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10199 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10200 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10201 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10202 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
)
10205 static const struct builtin_description dsp_32only_bdesc
[] =
10207 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10208 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10209 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10210 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10211 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10212 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10213 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10214 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10215 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10216 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10217 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10218 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10219 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10220 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10221 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10222 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10223 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10224 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10225 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10226 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10227 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10229 /* The following are for the MIPS DSP ASE REV 2. */
10230 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10231 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10232 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10233 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10234 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10235 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10236 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10237 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, MASK_DSPR2
),
10238 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, MASK_DSPR2
),
10239 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10240 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10241 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10242 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10243 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10244 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
)
10247 /* This helps provide a mapping from builtin function codes to bdesc
10252 /* The builtin function table that this entry describes. */
10253 const struct builtin_description
*bdesc
;
10255 /* The number of entries in the builtin function table. */
10258 /* The target processor that supports these builtin functions.
10259 PROCESSOR_MAX means we enable them for all processors. */
10260 enum processor_type proc
;
10262 /* If the target has these flags, this builtin function table
10263 will not be supported. */
10264 int unsupported_target_flags
;
10267 static const struct bdesc_map bdesc_arrays
[] =
10269 { mips_bdesc
, ARRAY_SIZE (mips_bdesc
), PROCESSOR_MAX
, 0 },
10270 { sb1_bdesc
, ARRAY_SIZE (sb1_bdesc
), PROCESSOR_SB1
, 0 },
10271 { dsp_bdesc
, ARRAY_SIZE (dsp_bdesc
), PROCESSOR_MAX
, 0 },
10272 { dsp_32only_bdesc
, ARRAY_SIZE (dsp_32only_bdesc
), PROCESSOR_MAX
,
10276 /* MODE is a vector mode whose elements have type TYPE. Return the type
10277 of the vector itself. */
10280 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
10282 static tree types
[(int) MAX_MACHINE_MODE
];
10284 if (types
[(int) mode
] == NULL_TREE
)
10285 types
[(int) mode
] = build_vector_type_for_mode (type
, mode
);
10286 return types
[(int) mode
];
10289 /* Source-level argument types. */
10290 #define MIPS_ATYPE_VOID void_type_node
10291 #define MIPS_ATYPE_INT integer_type_node
10292 #define MIPS_ATYPE_POINTER ptr_type_node
10294 /* Standard mode-based argument types. */
10295 #define MIPS_ATYPE_SI intSI_type_node
10296 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10297 #define MIPS_ATYPE_DI intDI_type_node
10298 #define MIPS_ATYPE_SF float_type_node
10299 #define MIPS_ATYPE_DF double_type_node
10301 /* Vector argument types. */
10302 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10303 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10304 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10306 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10307 their associated MIPS_ATYPEs. */
10308 #define MIPS_FTYPE_ATYPES1(A, B) \
10309 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10311 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10312 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10314 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10315 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10317 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10318 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10321 /* Return the function type associated with function prototype TYPE. */
10324 mips_build_function_type (enum mips_function_type type
)
10326 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
10328 if (types
[(int) type
] == NULL_TREE
)
10331 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10332 case MIPS_FTYPE_NAME##NUM ARGS: \
10333 types[(int) type] \
10334 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10337 #include "config/mips/mips-ftypes.def"
10338 #undef DEF_MIPS_FTYPE
10340 gcc_unreachable ();
10343 return types
[(int) type
];
10346 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10349 mips_init_builtins (void)
10351 const struct builtin_description
*d
;
10352 const struct bdesc_map
*m
;
10353 unsigned int offset
;
10355 /* Iterate through all of the bdesc arrays, initializing all of the
10356 builtin functions. */
10359 for (m
= bdesc_arrays
; m
< &bdesc_arrays
[ARRAY_SIZE (bdesc_arrays
)]; m
++)
10361 if ((m
->proc
== PROCESSOR_MAX
|| (m
->proc
== mips_arch
))
10362 && (m
->unsupported_target_flags
& target_flags
) == 0)
10363 for (d
= m
->bdesc
; d
< &m
->bdesc
[m
->size
]; d
++)
10364 if ((d
->target_flags
& target_flags
) == d
->target_flags
)
10365 add_builtin_function (d
->name
,
10366 mips_build_function_type (d
->function_type
),
10367 d
- m
->bdesc
+ offset
,
10368 BUILT_IN_MD
, NULL
, NULL
);
10373 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
10374 suitable for input operand OP of instruction ICODE. Return the value. */
10377 mips_prepare_builtin_arg (enum insn_code icode
,
10378 unsigned int op
, tree exp
, unsigned int argnum
)
10381 enum machine_mode mode
;
10383 value
= expand_normal (CALL_EXPR_ARG (exp
, argnum
));
10384 mode
= insn_data
[icode
].operand
[op
].mode
;
10385 if (!insn_data
[icode
].operand
[op
].predicate (value
, mode
))
10387 value
= copy_to_mode_reg (mode
, value
);
10388 /* Check the predicate again. */
10389 if (!insn_data
[icode
].operand
[op
].predicate (value
, mode
))
10391 error ("invalid argument to builtin function");
10399 /* Return an rtx suitable for output operand OP of instruction ICODE.
10400 If TARGET is non-null, try to use it where possible. */
10403 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
10405 enum machine_mode mode
;
10407 mode
= insn_data
[icode
].operand
[op
].mode
;
10408 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
10409 target
= gen_reg_rtx (mode
);
10414 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10415 .md pattern and CALL is the function expr with arguments. TARGET,
10416 if nonnull, suggests a good place to put the result.
10417 HAS_TARGET indicates the function must return something. */
10420 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
10423 rtx ops
[MAX_RECOG_OPERANDS
];
10429 /* We save target to ops[0]. */
10430 ops
[0] = mips_prepare_builtin_target (icode
, 0, target
);
10434 /* We need to test if the arglist is not zero. Some instructions have extra
10435 clobber registers. */
10436 for (; i
< insn_data
[icode
].n_operands
&& i
<= call_expr_nargs (exp
); i
++, j
++)
10437 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, exp
, j
);
10442 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
10446 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
10450 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
10454 gcc_unreachable ();
10459 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10460 function (TYPE says which). EXP is the tree for the function
10461 function, ICODE is the instruction that should be used to compare
10462 the first two arguments, and COND is the condition it should test.
10463 TARGET, if nonnull, suggests a good place to put the result. */
10466 mips_expand_builtin_movtf (enum mips_builtin_type type
,
10467 enum insn_code icode
, enum mips_fp_condition cond
,
10468 rtx target
, tree exp
)
10470 rtx cmp_result
, op0
, op1
;
10472 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10473 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 0);
10474 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 1);
10475 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
10477 icode
= CODE_FOR_mips_cond_move_tf_ps
;
10478 target
= mips_prepare_builtin_target (icode
, 0, target
);
10479 if (type
== MIPS_BUILTIN_MOVT
)
10481 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 2);
10482 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 3);
10486 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 2);
10487 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 3);
10489 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
10493 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10494 into TARGET otherwise. Return TARGET. */
10497 mips_builtin_branch_and_move (rtx condition
, rtx target
,
10498 rtx value_if_true
, rtx value_if_false
)
10500 rtx true_label
, done_label
;
10502 true_label
= gen_label_rtx ();
10503 done_label
= gen_label_rtx ();
10505 /* First assume that CONDITION is false. */
10506 mips_emit_move (target
, value_if_false
);
10508 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10509 emit_jump_insn (gen_condjump (condition
, true_label
));
10510 emit_jump_insn (gen_jump (done_label
));
10513 /* Fix TARGET if CONDITION is true. */
10514 emit_label (true_label
);
10515 mips_emit_move (target
, value_if_true
);
10517 emit_label (done_label
);
10521 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10522 of the comparison instruction and COND is the condition it should test.
10523 EXP is the function call and arguments and TARGET, if nonnull,
10524 suggests a good place to put the boolean result. */
10527 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
10528 enum insn_code icode
, enum mips_fp_condition cond
,
10529 rtx target
, tree exp
)
10531 rtx offset
, condition
, cmp_result
, ops
[MAX_RECOG_OPERANDS
];
10535 if (target
== 0 || GET_MODE (target
) != SImode
)
10536 target
= gen_reg_rtx (SImode
);
10538 /* Prepare the operands to the comparison. */
10539 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10540 for (i
= 1; i
< insn_data
[icode
].n_operands
- 1; i
++, j
++)
10541 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, exp
, j
);
10543 switch (insn_data
[icode
].n_operands
)
10546 emit_insn (GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2], GEN_INT (cond
)));
10550 emit_insn (GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2],
10551 ops
[3], ops
[4], GEN_INT (cond
)));
10555 gcc_unreachable ();
10558 /* If the comparison sets more than one register, we define the result
10559 to be 0 if all registers are false and -1 if all registers are true.
10560 The value of the complete result is indeterminate otherwise. */
10561 switch (builtin_type
)
10563 case MIPS_BUILTIN_CMP_ALL
:
10564 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
10565 return mips_builtin_branch_and_move (condition
, target
,
10566 const0_rtx
, const1_rtx
);
10568 case MIPS_BUILTIN_CMP_UPPER
:
10569 case MIPS_BUILTIN_CMP_LOWER
:
10570 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
10571 condition
= gen_single_cc (cmp_result
, offset
);
10572 return mips_builtin_branch_and_move (condition
, target
,
10573 const1_rtx
, const0_rtx
);
10576 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
10577 return mips_builtin_branch_and_move (condition
, target
,
10578 const1_rtx
, const0_rtx
);
10582 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10583 suggests a good place to put the boolean result. */
10586 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
10588 rtx condition
, cmp_result
;
10591 if (target
== 0 || GET_MODE (target
) != SImode
)
10592 target
= gen_reg_rtx (SImode
);
10594 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
10596 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
10601 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
10602 return mips_builtin_branch_and_move (condition
, target
,
10603 const1_rtx
, const0_rtx
);
10606 /* EXP is a CALL_EXPR that calls the function described by BDESC.
10607 Expand the call and return an rtx for its return value.
10608 TARGET, if nonnull, suggests a good place to put this value. */
10611 mips_expand_builtin_1 (const struct builtin_description
*bdesc
,
10612 tree exp
, rtx target
)
10614 switch (bdesc
->builtin_type
)
10616 case MIPS_BUILTIN_DIRECT
:
10617 return mips_expand_builtin_direct (bdesc
->icode
, target
, exp
, true);
10619 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
10620 return mips_expand_builtin_direct (bdesc
->icode
, target
, exp
, false);
10622 case MIPS_BUILTIN_MOVT
:
10623 case MIPS_BUILTIN_MOVF
:
10624 return mips_expand_builtin_movtf (bdesc
->builtin_type
, bdesc
->icode
,
10625 bdesc
->cond
, target
, exp
);
10627 case MIPS_BUILTIN_CMP_ANY
:
10628 case MIPS_BUILTIN_CMP_ALL
:
10629 case MIPS_BUILTIN_CMP_UPPER
:
10630 case MIPS_BUILTIN_CMP_LOWER
:
10631 case MIPS_BUILTIN_CMP_SINGLE
:
10632 return mips_expand_builtin_compare (bdesc
->builtin_type
, bdesc
->icode
,
10633 bdesc
->cond
, target
, exp
);
10635 case MIPS_BUILTIN_BPOSGE32
:
10636 return mips_expand_builtin_bposge (bdesc
->builtin_type
, target
);
10638 gcc_unreachable ();
10641 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10644 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10645 enum machine_mode mode ATTRIBUTE_UNUSED
,
10646 int ignore ATTRIBUTE_UNUSED
)
10649 unsigned int fcode
;
10650 const struct bdesc_map
*m
;
10652 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10653 fcode
= DECL_FUNCTION_CODE (fndecl
);
10657 error ("built-in function %qs not supported for MIPS16",
10658 IDENTIFIER_POINTER (DECL_NAME (fndecl
)));
10662 for (m
= bdesc_arrays
; m
< &bdesc_arrays
[ARRAY_SIZE (bdesc_arrays
)]; m
++)
10664 if (fcode
< m
->size
)
10665 return mips_expand_builtin_1 (m
->bdesc
+ fcode
, exp
, target
);
10668 gcc_unreachable ();
10671 /* An entry in the mips16 constant pool. VALUE is the pool constant,
10672 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10674 struct mips16_constant
{
10675 struct mips16_constant
*next
;
10678 enum machine_mode mode
;
10681 /* Information about an incomplete mips16 constant pool. FIRST is the
10682 first constant, HIGHEST_ADDRESS is the highest address that the first
10683 byte of the pool can have, and INSN_ADDRESS is the current instruction
10686 struct mips16_constant_pool
{
10687 struct mips16_constant
*first
;
10688 int highest_address
;
10692 /* Add constant VALUE to POOL and return its label. MODE is the
10693 value's mode (used for CONST_INTs, etc.). */
10696 add_constant (struct mips16_constant_pool
*pool
,
10697 rtx value
, enum machine_mode mode
)
10699 struct mips16_constant
**p
, *c
;
10700 bool first_of_size_p
;
10702 /* See whether the constant is already in the pool. If so, return the
10703 existing label, otherwise leave P pointing to the place where the
10704 constant should be added.
10706 Keep the pool sorted in increasing order of mode size so that we can
10707 reduce the number of alignments needed. */
10708 first_of_size_p
= true;
10709 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
10711 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
10712 return (*p
)->label
;
10713 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
10715 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
10716 first_of_size_p
= false;
10719 /* In the worst case, the constant needed by the earliest instruction
10720 will end up at the end of the pool. The entire pool must then be
10721 accessible from that instruction.
10723 When adding the first constant, set the pool's highest address to
10724 the address of the first out-of-range byte. Adjust this address
10725 downwards each time a new constant is added. */
10726 if (pool
->first
== 0)
10727 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
10728 is the address of the instruction with the lowest two bits clear.
10729 The base PC value for ld has the lowest three bits clear. Assume
10730 the worst case here. */
10731 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
10732 pool
->highest_address
-= GET_MODE_SIZE (mode
);
10733 if (first_of_size_p
)
10734 /* Take into account the worst possible padding due to alignment. */
10735 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
10737 /* Create a new entry. */
10738 c
= (struct mips16_constant
*) xmalloc (sizeof *c
);
10741 c
->label
= gen_label_rtx ();
10748 /* Output constant VALUE after instruction INSN and return the last
10749 instruction emitted. MODE is the mode of the constant. */
10752 dump_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
10754 if (SCALAR_INT_MODE_P (mode
)
10755 || ALL_SCALAR_FRACT_MODE_P (mode
)
10756 || ALL_SCALAR_ACCUM_MODE_P (mode
))
10758 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
10759 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
10762 if (SCALAR_FLOAT_MODE_P (mode
))
10763 return emit_insn_after (gen_consttable_float (value
), insn
);
10765 if (VECTOR_MODE_P (mode
))
10769 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
10770 insn
= dump_constants_1 (GET_MODE_INNER (mode
),
10771 CONST_VECTOR_ELT (value
, i
), insn
);
10775 gcc_unreachable ();
10779 /* Dump out the constants in CONSTANTS after INSN. */
10782 dump_constants (struct mips16_constant
*constants
, rtx insn
)
10784 struct mips16_constant
*c
, *next
;
10788 for (c
= constants
; c
!= NULL
; c
= next
)
10790 /* If necessary, increase the alignment of PC. */
10791 if (align
< GET_MODE_SIZE (c
->mode
))
10793 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
10794 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
10796 align
= GET_MODE_SIZE (c
->mode
);
10798 insn
= emit_label_after (c
->label
, insn
);
10799 insn
= dump_constants_1 (c
->mode
, c
->value
, insn
);
10805 emit_barrier_after (insn
);
10808 /* Return the length of instruction INSN. */
10811 mips16_insn_length (rtx insn
)
10815 rtx body
= PATTERN (insn
);
10816 if (GET_CODE (body
) == ADDR_VEC
)
10817 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
10818 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
10819 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
10821 return get_attr_length (insn
);
10824 /* If *X is a symbolic constant that refers to the constant pool, add
10825 the constant to POOL and rewrite *X to use the constant's label. */
10828 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
10830 rtx base
, offset
, label
;
10832 split_const (*x
, &base
, &offset
);
10833 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
10835 label
= add_constant (pool
, get_pool_constant (base
),
10836 get_pool_mode (base
));
10837 base
= gen_rtx_LABEL_REF (Pmode
, label
);
10838 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
10842 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10843 INSN is the instruction we're rewriting and POOL points to the current
10845 struct mips16_rewrite_pool_refs_info
{
10847 struct mips16_constant_pool
*pool
;
10850 /* Rewrite *X so that constant pool references refer to the constant's
10851 label instead. DATA points to a mips16_rewrite_pool_refs_info
10855 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
10857 struct mips16_rewrite_pool_refs_info
*info
= data
;
10859 if (force_to_mem_operand (*x
, Pmode
))
10861 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
10862 validate_change (info
->insn
, x
, mem
, false);
10867 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
10871 if (TARGET_MIPS16_TEXT_LOADS
)
10872 mips16_rewrite_pool_constant (info
->pool
, x
);
10874 return GET_CODE (*x
) == CONST
? -1 : 0;
10877 /* Build MIPS16 constant pools. */
10880 mips16_lay_out_constants (void)
10882 struct mips16_constant_pool pool
;
10883 struct mips16_rewrite_pool_refs_info info
;
10886 if (!TARGET_MIPS16_PCREL_LOADS
)
10890 memset (&pool
, 0, sizeof (pool
));
10891 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10893 /* Rewrite constant pool references in INSN. */
10898 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
10901 pool
.insn_address
+= mips16_insn_length (insn
);
10903 if (pool
.first
!= NULL
)
10905 /* If there are no natural barriers between the first user of
10906 the pool and the highest acceptable address, we'll need to
10907 create a new instruction to jump around the constant pool.
10908 In the worst case, this instruction will be 4 bytes long.
10910 If it's too late to do this transformation after INSN,
10911 do it immediately before INSN. */
10912 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
10916 label
= gen_label_rtx ();
10918 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
10919 JUMP_LABEL (jump
) = label
;
10920 LABEL_NUSES (label
) = 1;
10921 barrier
= emit_barrier_after (jump
);
10923 emit_label_after (label
, barrier
);
10924 pool
.insn_address
+= 4;
10927 /* See whether the constant pool is now out of range of the first
10928 user. If so, output the constants after the previous barrier.
10929 Note that any instructions between BARRIER and INSN (inclusive)
10930 will use negative offsets to refer to the pool. */
10931 if (pool
.insn_address
> pool
.highest_address
)
10933 dump_constants (pool
.first
, barrier
);
10937 else if (BARRIER_P (insn
))
10941 dump_constants (pool
.first
, get_last_insn ());
10944 /* A temporary variable used by for_each_rtx callbacks, etc. */
10945 static rtx mips_sim_insn
;
10947 /* A structure representing the state of the processor pipeline.
10948 Used by the mips_sim_* family of functions. */
10950 /* The maximum number of instructions that can be issued in a cycle.
10951 (Caches mips_issue_rate.) */
10952 unsigned int issue_rate
;
10954 /* The current simulation time. */
10957 /* How many more instructions can be issued in the current cycle. */
10958 unsigned int insns_left
;
10960 /* LAST_SET[X].INSN is the last instruction to set register X.
10961 LAST_SET[X].TIME is the time at which that instruction was issued.
10962 INSN is null if no instruction has yet set register X. */
10966 } last_set
[FIRST_PSEUDO_REGISTER
];
10968 /* The pipeline's current DFA state. */
10972 /* Reset STATE to the initial simulation state. */
10975 mips_sim_reset (struct mips_sim
*state
)
10978 state
->insns_left
= state
->issue_rate
;
10979 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
10980 state_reset (state
->dfa_state
);
10983 /* Initialize STATE before its first use. DFA_STATE points to an
10984 allocated but uninitialized DFA state. */
10987 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
10989 state
->issue_rate
= mips_issue_rate ();
10990 state
->dfa_state
= dfa_state
;
10991 mips_sim_reset (state
);
10994 /* Advance STATE by one clock cycle. */
10997 mips_sim_next_cycle (struct mips_sim
*state
)
11000 state
->insns_left
= state
->issue_rate
;
11001 state_transition (state
->dfa_state
, 0);
11004 /* Advance simulation state STATE until instruction INSN can read
11008 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
11012 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)); i
++)
11013 if (state
->last_set
[REGNO (reg
) + i
].insn
!= 0)
11017 t
= state
->last_set
[REGNO (reg
) + i
].time
;
11018 t
+= insn_latency (state
->last_set
[REGNO (reg
) + i
].insn
, insn
);
11019 while (state
->time
< t
)
11020 mips_sim_next_cycle (state
);
11024 /* A for_each_rtx callback. If *X is a register, advance simulation state
11025 DATA until mips_sim_insn can read the register's value. */
11028 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
11031 mips_sim_wait_reg (data
, mips_sim_insn
, *x
);
11035 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
11038 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
11040 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
11043 /* Advance simulation state STATE until all of INSN's register
11044 dependencies are satisfied. */
11047 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
11049 mips_sim_insn
= insn
;
11050 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
11053 /* Advance simulation state STATE until the units required by
11054 instruction INSN are available. */
11057 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
11061 tmp_state
= alloca (state_size ());
11062 while (state
->insns_left
== 0
11063 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
11064 state_transition (tmp_state
, insn
) >= 0))
11065 mips_sim_next_cycle (state
);
11068 /* Advance simulation state STATE until INSN is ready to issue. */
11071 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
11073 mips_sim_wait_regs (state
, insn
);
11074 mips_sim_wait_units (state
, insn
);
11077 /* mips_sim_insn has just set X. Update the LAST_SET array
11078 in simulation state DATA. */
11081 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
11083 struct mips_sim
*state
;
11088 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (x
), GET_MODE (x
)); i
++)
11090 state
->last_set
[REGNO (x
) + i
].insn
= mips_sim_insn
;
11091 state
->last_set
[REGNO (x
) + i
].time
= state
->time
;
11095 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11096 can issue immediately (i.e., that mips_sim_wait_insn has already
11100 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
11102 state_transition (state
->dfa_state
, insn
);
11103 state
->insns_left
--;
11105 mips_sim_insn
= insn
;
11106 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
11109 /* Simulate issuing a NOP in state STATE. */
11112 mips_sim_issue_nop (struct mips_sim
*state
)
11114 if (state
->insns_left
== 0)
11115 mips_sim_next_cycle (state
);
11116 state
->insns_left
--;
11119 /* Update simulation state STATE so that it's ready to accept the instruction
11120 after INSN. INSN should be part of the main rtl chain, not a member of a
11124 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
11126 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11128 mips_sim_issue_nop (state
);
11130 switch (GET_CODE (SEQ_BEGIN (insn
)))
11134 /* We can't predict the processor state after a call or label. */
11135 mips_sim_reset (state
);
11139 /* The delay slots of branch likely instructions are only executed
11140 when the branch is taken. Therefore, if the caller has simulated
11141 the delay slot instruction, STATE does not really reflect the state
11142 of the pipeline for the instruction after the delay slot. Also,
11143 branch likely instructions tend to incur a penalty when not taken,
11144 so there will probably be an extra delay between the branch and
11145 the instruction after the delay slot. */
11146 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
11147 mips_sim_reset (state
);
11155 /* The VR4130 pipeline issues aligned pairs of instructions together,
11156 but it stalls the second instruction if it depends on the first.
11157 In order to cut down the amount of logic required, this dependence
11158 check is not based on a full instruction decode. Instead, any non-SPECIAL
11159 instruction is assumed to modify the register specified by bits 20-16
11160 (which is usually the "rt" field).
11162 In beq, beql, bne and bnel instructions, the rt field is actually an
11163 input, so we can end up with a false dependence between the branch
11164 and its delay slot. If this situation occurs in instruction INSN,
11165 try to avoid it by swapping rs and rt. */
11168 vr4130_avoid_branch_rt_conflict (rtx insn
)
11172 first
= SEQ_BEGIN (insn
);
11173 second
= SEQ_END (insn
);
11175 && NONJUMP_INSN_P (second
)
11176 && GET_CODE (PATTERN (first
)) == SET
11177 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
11178 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
11180 /* Check for the right kind of condition. */
11181 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
11182 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
11183 && REG_P (XEXP (cond
, 0))
11184 && REG_P (XEXP (cond
, 1))
11185 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
11186 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
11188 /* SECOND mentions the rt register but not the rs register. */
11189 rtx tmp
= XEXP (cond
, 0);
11190 XEXP (cond
, 0) = XEXP (cond
, 1);
11191 XEXP (cond
, 1) = tmp
;
11196 /* Implement -mvr4130-align. Go through each basic block and simulate the
11197 processor pipeline. If we find that a pair of instructions could execute
11198 in parallel, and the first of those instruction is not 8-byte aligned,
11199 insert a nop to make it aligned. */
11202 vr4130_align_insns (void)
11204 struct mips_sim state
;
11205 rtx insn
, subinsn
, last
, last2
, next
;
11210 /* LAST is the last instruction before INSN to have a nonzero length.
11211 LAST2 is the last such instruction before LAST. */
11215 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11218 mips_sim_init (&state
, alloca (state_size ()));
11219 for (insn
= get_insns (); insn
!= 0; insn
= next
)
11221 unsigned int length
;
11223 next
= NEXT_INSN (insn
);
11225 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11226 This isn't really related to the alignment pass, but we do it on
11227 the fly to avoid a separate instruction walk. */
11228 vr4130_avoid_branch_rt_conflict (insn
);
11230 if (USEFUL_INSN_P (insn
))
11231 FOR_EACH_SUBINSN (subinsn
, insn
)
11233 mips_sim_wait_insn (&state
, subinsn
);
11235 /* If we want this instruction to issue in parallel with the
11236 previous one, make sure that the previous instruction is
11237 aligned. There are several reasons why this isn't worthwhile
11238 when the second instruction is a call:
11240 - Calls are less likely to be performance critical,
11241 - There's a good chance that the delay slot can execute
11242 in parallel with the call.
11243 - The return address would then be unaligned.
11245 In general, if we're going to insert a nop between instructions
11246 X and Y, it's better to insert it immediately after X. That
11247 way, if the nop makes Y aligned, it will also align any labels
11248 between X and Y. */
11249 if (state
.insns_left
!= state
.issue_rate
11250 && !CALL_P (subinsn
))
11252 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
11254 /* SUBINSN is the first instruction in INSN and INSN is
11255 aligned. We want to align the previous instruction
11256 instead, so insert a nop between LAST2 and LAST.
11258 Note that LAST could be either a single instruction
11259 or a branch with a delay slot. In the latter case,
11260 LAST, like INSN, is already aligned, but the delay
11261 slot must have some extra delay that stops it from
11262 issuing at the same time as the branch. We therefore
11263 insert a nop before the branch in order to align its
11265 emit_insn_after (gen_nop (), last2
);
11268 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
11270 /* SUBINSN is the delay slot of INSN, but INSN is
11271 currently unaligned. Insert a nop between
11272 LAST and INSN to align it. */
11273 emit_insn_after (gen_nop (), last
);
11277 mips_sim_issue_insn (&state
, subinsn
);
11279 mips_sim_finish_insn (&state
, insn
);
11281 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11282 length
= get_attr_length (insn
);
11285 /* If the instruction is an asm statement or multi-instruction
11286 mips.md patern, the length is only an estimate. Insert an
11287 8 byte alignment after it so that the following instructions
11288 can be handled correctly. */
11289 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
11290 && (recog_memoized (insn
) < 0 || length
>= 8))
11292 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
11293 next
= NEXT_INSN (next
);
11294 mips_sim_next_cycle (&state
);
11297 else if (length
& 4)
11298 aligned_p
= !aligned_p
;
11303 /* See whether INSN is an aligned label. */
11304 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
11310 /* Subroutine of mips_reorg. If there is a hazard between INSN
11311 and a previous instruction, avoid it by inserting nops after
11314 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
11315 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
11316 before using the value of that register. *HILO_DELAY counts the
11317 number of instructions since the last hilo hazard (that is,
11318 the number of instructions since the last mflo or mfhi).
11320 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
11321 for the next instruction.
11323 LO_REG is an rtx for the LO register, used in dependence checking. */
11326 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
11327 rtx
*delayed_reg
, rtx lo_reg
)
11330 int nops
, ninsns
, hazard_set
;
11332 if (!INSN_P (insn
))
11335 pattern
= PATTERN (insn
);
11337 /* Do not put the whole function in .set noreorder if it contains
11338 an asm statement. We don't know whether there will be hazards
11339 between the asm statement and the gcc-generated code. */
11340 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
11341 cfun
->machine
->all_noreorder_p
= false;
11343 /* Ignore zero-length instructions (barriers and the like). */
11344 ninsns
= get_attr_length (insn
) / 4;
11348 /* Work out how many nops are needed. Note that we only care about
11349 registers that are explicitly mentioned in the instruction's pattern.
11350 It doesn't matter that calls use the argument registers or that they
11351 clobber hi and lo. */
11352 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
11353 nops
= 2 - *hilo_delay
;
11354 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
11359 /* Insert the nops between this instruction and the previous one.
11360 Each new nop takes us further from the last hilo hazard. */
11361 *hilo_delay
+= nops
;
11363 emit_insn_after (gen_hazard_nop (), after
);
11365 /* Set up the state for the next instruction. */
11366 *hilo_delay
+= ninsns
;
11368 if (INSN_CODE (insn
) >= 0)
11369 switch (get_attr_hazard (insn
))
11379 hazard_set
= (int) get_attr_hazard_set (insn
);
11380 if (hazard_set
== 0)
11381 set
= single_set (insn
);
11384 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
11385 set
= XVECEXP (PATTERN (insn
), 0, hazard_set
- 1);
11387 gcc_assert (set
&& GET_CODE (set
) == SET
);
11388 *delayed_reg
= SET_DEST (set
);
11394 /* Go through the instruction stream and insert nops where necessary.
11395 See if the whole function can then be put into .set noreorder &
11399 mips_avoid_hazards (void)
11401 rtx insn
, last_insn
, lo_reg
, delayed_reg
;
11404 /* Force all instructions to be split into their final form. */
11405 split_all_insns_noflow ();
11407 /* Recalculate instruction lengths without taking nops into account. */
11408 cfun
->machine
->ignore_hazard_length_p
= true;
11409 shorten_branches (get_insns ());
11411 cfun
->machine
->all_noreorder_p
= true;
11413 /* Profiled functions can't be all noreorder because the profiler
11414 support uses assembler macros. */
11415 if (current_function_profile
)
11416 cfun
->machine
->all_noreorder_p
= false;
11418 /* Code compiled with -mfix-vr4120 can't be all noreorder because
11419 we rely on the assembler to work around some errata. */
11420 if (TARGET_FIX_VR4120
)
11421 cfun
->machine
->all_noreorder_p
= false;
11423 /* The same is true for -mfix-vr4130 if we might generate mflo or
11424 mfhi instructions. Note that we avoid using mflo and mfhi if
11425 the VR4130 macc and dmacc instructions are available instead;
11426 see the *mfhilo_{si,di}_macc patterns. */
11427 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
11428 cfun
->machine
->all_noreorder_p
= false;
11433 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
11435 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
11438 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
11439 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
11440 mips_avoid_hazard (last_insn
, XVECEXP (PATTERN (insn
), 0, i
),
11441 &hilo_delay
, &delayed_reg
, lo_reg
);
11443 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
11444 &delayed_reg
, lo_reg
);
11451 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
11456 mips16_lay_out_constants ();
11457 if (TARGET_EXPLICIT_RELOCS
)
11459 if (mips_flag_delayed_branch
)
11460 dbr_schedule (get_insns ());
11461 mips_avoid_hazards ();
11462 if (TUNE_MIPS4130
&& TARGET_VR4130_ALIGN
)
11463 vr4130_align_insns ();
11467 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
11468 in order to avoid duplicating too much logic from elsewhere. */
11471 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11472 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11475 rtx
this, temp1
, temp2
, insn
, fnaddr
;
11476 bool use_sibcall_p
;
11478 /* Pretend to be a post-reload pass while generating rtl. */
11479 reload_completed
= 1;
11481 /* Mark the end of the (empty) prologue. */
11482 emit_note (NOTE_INSN_PROLOGUE_END
);
11484 /* Determine if we can use a sibcall to call FUNCTION directly. */
11485 fnaddr
= XEXP (DECL_RTL (function
), 0);
11486 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
11487 && const_call_insn_operand (fnaddr
, Pmode
));
11489 /* Determine if we need to load FNADDR from the GOT. */
11490 if (!use_sibcall_p
)
11491 switch (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))
11493 case SYMBOL_GOT_PAGE_OFST
:
11494 case SYMBOL_GOT_DISP
:
11495 /* Pick a global pointer. Use a call-clobbered register if
11496 TARGET_CALL_SAVED_GP. */
11497 cfun
->machine
->global_pointer
=
11498 TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
11499 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11501 /* Set up the global pointer for n32 or n64 abicalls. */
11502 mips_emit_loadgp ();
11509 /* We need two temporary registers in some cases. */
11510 temp1
= gen_rtx_REG (Pmode
, 2);
11511 temp2
= gen_rtx_REG (Pmode
, 3);
11513 /* Find out which register contains the "this" pointer. */
11514 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11515 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
11517 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
11519 /* Add DELTA to THIS. */
11522 rtx offset
= GEN_INT (delta
);
11523 if (!SMALL_OPERAND (delta
))
11525 mips_emit_move (temp1
, offset
);
11528 emit_insn (gen_add3_insn (this, this, offset
));
11531 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
11532 if (vcall_offset
!= 0)
11536 /* Set TEMP1 to *THIS. */
11537 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this));
11539 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
11540 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
11542 /* Load the offset and add it to THIS. */
11543 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
11544 emit_insn (gen_add3_insn (this, this, temp1
));
11547 /* Jump to the target function. Use a sibcall if direct jumps are
11548 allowed, otherwise load the address into a register first. */
11551 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
11552 SIBLING_CALL_P (insn
) = 1;
11556 /* This is messy. gas treats "la $25,foo" as part of a call
11557 sequence and may allow a global "foo" to be lazily bound.
11558 The general move patterns therefore reject this combination.
11560 In this context, lazy binding would actually be OK
11561 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
11562 TARGET_CALL_SAVED_GP; see mips_load_call_address.
11563 We must therefore load the address via a temporary
11564 register if mips_dangerous_for_la25_p.
11566 If we jump to the temporary register rather than $25, the assembler
11567 can use the move insn to fill the jump's delay slot. */
11568 if (TARGET_USE_PIC_FN_ADDR_REG
11569 && !mips_dangerous_for_la25_p (fnaddr
))
11570 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11571 mips_load_call_address (temp1
, fnaddr
, true);
11573 if (TARGET_USE_PIC_FN_ADDR_REG
11574 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
11575 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
11576 emit_jump_insn (gen_indirect_jump (temp1
));
11579 /* Run just enough of rest_of_compilation. This sequence was
11580 "borrowed" from alpha.c. */
11581 insn
= get_insns ();
11582 insn_locators_alloc ();
11583 split_all_insns_noflow ();
11584 mips16_lay_out_constants ();
11585 shorten_branches (insn
);
11586 final_start_function (insn
, file
, 1);
11587 final (insn
, file
, 1);
11588 final_end_function ();
11590 /* Clean up the vars set above. Note that final_end_function resets
11591 the global pointer for us. */
11592 reload_completed
= 0;
11595 static GTY(()) int was_mips16_p
= -1;
11597 /* Set up the target-dependent global state so that it matches the
11598 current function's ISA mode. */
11601 mips_set_mips16_mode (int mips16_p
)
11603 if (mips16_p
== was_mips16_p
)
11606 /* Restore base settings of various flags. */
11607 target_flags
= mips_base_target_flags
;
11608 flag_delayed_branch
= mips_flag_delayed_branch
;
11609 flag_schedule_insns
= mips_base_schedule_insns
;
11610 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
11611 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
11612 align_loops
= mips_base_align_loops
;
11613 align_jumps
= mips_base_align_jumps
;
11614 align_functions
= mips_base_align_functions
;
11618 /* Select mips16 instruction set. */
11619 target_flags
|= MASK_MIPS16
;
11621 /* Don't run the scheduler before reload, since it tends to
11622 increase register pressure. */
11623 flag_schedule_insns
= 0;
11625 /* Don't do hot/cold partitioning. The constant layout code expects
11626 the whole function to be in a single section. */
11627 flag_reorder_blocks_and_partition
= 0;
11629 /* Don't move loop invariants, because it tends to increase
11630 register pressure. It also introduces an extra move in cases
11631 where the constant is the first operand in a two-operand binary
11632 instruction, or when it forms a register argument to a functon
11634 flag_move_loop_invariants
= 0;
11636 /* Silently disable -mexplicit-relocs since it doesn't apply
11637 to mips16 code. Even so, it would overly pedantic to warn
11638 about "-mips16 -mexplicit-relocs", especially given that
11639 we use a %gprel() operator. */
11640 target_flags
&= ~MASK_EXPLICIT_RELOCS
;
11642 /* Experiments suggest we get the best overall results from using
11643 the range of an unextended lw or sw. Code that makes heavy use
11644 of byte or short accesses can do better with ranges of 0...31
11645 and 0...63 respectively, but most code is sensitive to the range
11646 of lw and sw instead. */
11647 targetm
.min_anchor_offset
= 0;
11648 targetm
.max_anchor_offset
= 127;
11650 if (flag_pic
|| TARGET_ABICALLS
)
11651 sorry ("MIPS16 PIC");
11655 /* Reset to select base non-mips16 ISA. */
11656 target_flags
&= ~MASK_MIPS16
;
11658 /* When using explicit relocs, we call dbr_schedule from within
11660 if (TARGET_EXPLICIT_RELOCS
)
11661 flag_delayed_branch
= 0;
11663 /* Provide default values for align_* for 64-bit targets. */
11666 if (align_loops
== 0)
11668 if (align_jumps
== 0)
11670 if (align_functions
== 0)
11671 align_functions
= 8;
11674 targetm
.min_anchor_offset
= -32768;
11675 targetm
.max_anchor_offset
= 32767;
11678 /* (Re)initialize mips target internals for new ISA. */
11679 mips_init_split_addresses ();
11680 mips_init_relocs ();
11682 if (was_mips16_p
>= 0)
11683 /* Reinitialize target-dependent state. */
11686 was_mips16_p
= TARGET_MIPS16
;
11689 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
11690 function should use the MIPS16 ISA and switch modes accordingly. */
11693 mips_set_current_function (tree fndecl
)
11695 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
11698 /* Allocate a chunk of memory for per-function machine-dependent data. */
11699 static struct machine_function
*
11700 mips_init_machine_status (void)
11702 return ((struct machine_function
*)
11703 ggc_alloc_cleared (sizeof (struct machine_function
)));
11706 /* Return the processor associated with the given ISA level, or null
11707 if the ISA isn't valid. */
11709 static const struct mips_cpu_info
*
11710 mips_cpu_info_from_isa (int isa
)
11714 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
11715 if (mips_cpu_info_table
[i
].isa
== isa
)
11716 return mips_cpu_info_table
+ i
;
11721 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
11722 with a final "000" replaced by "k". Ignore case.
11724 Note: this function is shared between GCC and GAS. */
11727 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
11729 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
11730 given
++, canonical
++;
11732 return ((*given
== 0 && *canonical
== 0)
11733 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
11737 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
11738 CPU name. We've traditionally allowed a lot of variation here.
11740 Note: this function is shared between GCC and GAS. */
11743 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
11745 /* First see if the name matches exactly, or with a final "000"
11746 turned into "k". */
11747 if (mips_strict_matching_cpu_name_p (canonical
, given
))
11750 /* If not, try comparing based on numerical designation alone.
11751 See if GIVEN is an unadorned number, or 'r' followed by a number. */
11752 if (TOLOWER (*given
) == 'r')
11754 if (!ISDIGIT (*given
))
11757 /* Skip over some well-known prefixes in the canonical name,
11758 hoping to find a number there too. */
11759 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
11761 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
11763 else if (TOLOWER (canonical
[0]) == 'r')
11766 return mips_strict_matching_cpu_name_p (canonical
, given
);
11770 /* Return the mips_cpu_info entry for the processor or ISA given
11771 by CPU_STRING. Return null if the string isn't recognized.
11773 A similar function exists in GAS. */
11775 static const struct mips_cpu_info
*
11776 mips_parse_cpu (const char *cpu_string
)
11781 /* In the past, we allowed upper-case CPU names, but it doesn't
11782 work well with the multilib machinery. */
11783 for (s
= cpu_string
; *s
!= 0; s
++)
11786 warning (0, "the cpu name must be lower case");
11790 /* 'from-abi' selects the most compatible architecture for the given
11791 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
11792 EABIs, we have to decide whether we're using the 32-bit or 64-bit
11793 version. Look first at the -mgp options, if given, otherwise base
11794 the choice on MASK_64BIT in TARGET_DEFAULT. */
11795 if (strcasecmp (cpu_string
, "from-abi") == 0)
11796 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
11797 : ABI_NEEDS_64BIT_REGS
? 3
11798 : (TARGET_64BIT
? 3 : 1));
11800 /* 'default' has traditionally been a no-op. Probably not very useful. */
11801 if (strcasecmp (cpu_string
, "default") == 0)
11804 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
11805 if (mips_matching_cpu_name_p (mips_cpu_info_table
[i
].name
, cpu_string
))
11806 return mips_cpu_info_table
+ i
;
11812 /* Set up globals to generate code for the ISA or processor
11813 described by INFO. */
11816 mips_set_architecture (const struct mips_cpu_info
*info
)
11820 mips_arch_info
= info
;
11821 mips_arch
= info
->cpu
;
11822 mips_isa
= info
->isa
;
11827 /* Likewise for tuning. */
11830 mips_set_tune (const struct mips_cpu_info
*info
)
11834 mips_tune_info
= info
;
11835 mips_tune
= info
->cpu
;
11839 /* Implement TARGET_HANDLE_OPTION. */
11842 mips_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
11847 if (strcmp (arg
, "32") == 0)
11849 else if (strcmp (arg
, "o64") == 0)
11850 mips_abi
= ABI_O64
;
11851 else if (strcmp (arg
, "n32") == 0)
11852 mips_abi
= ABI_N32
;
11853 else if (strcmp (arg
, "64") == 0)
11855 else if (strcmp (arg
, "eabi") == 0)
11856 mips_abi
= ABI_EABI
;
11863 return mips_parse_cpu (arg
) != 0;
11866 mips_isa_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
11867 return mips_isa_info
!= 0;
11869 case OPT_mno_flush_func
:
11870 mips_cache_flush_func
= NULL
;
11873 case OPT_mcode_readable_
:
11874 if (strcmp (arg
, "yes") == 0)
11875 mips_code_readable
= CODE_READABLE_YES
;
11876 else if (strcmp (arg
, "pcrel") == 0)
11877 mips_code_readable
= CODE_READABLE_PCREL
;
11878 else if (strcmp (arg
, "no") == 0)
11879 mips_code_readable
= CODE_READABLE_NO
;
11889 /* Set up the threshold for data to go into the small data area, instead
11890 of the normal data area, and detect any conflicts in the switches. */
11893 override_options (void)
11895 int i
, start
, regno
;
11896 enum machine_mode mode
;
11898 #ifdef SUBTARGET_OVERRIDE_OPTIONS
11899 SUBTARGET_OVERRIDE_OPTIONS
;
11902 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
11904 /* The following code determines the architecture and register size.
11905 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
11906 The GAS and GCC code should be kept in sync as much as possible. */
11908 if (mips_arch_string
!= 0)
11909 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
11911 if (mips_isa_info
!= 0)
11913 if (mips_arch_info
== 0)
11914 mips_set_architecture (mips_isa_info
);
11915 else if (mips_arch_info
->isa
!= mips_isa_info
->isa
)
11916 error ("-%s conflicts with the other architecture options, "
11917 "which specify a %s processor",
11918 mips_isa_info
->name
,
11919 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
11922 if (mips_arch_info
== 0)
11924 #ifdef MIPS_CPU_STRING_DEFAULT
11925 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
11927 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
11931 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
11932 error ("-march=%s is not compatible with the selected ABI",
11933 mips_arch_info
->name
);
11935 /* Optimize for mips_arch, unless -mtune selects a different processor. */
11936 if (mips_tune_string
!= 0)
11937 mips_set_tune (mips_parse_cpu (mips_tune_string
));
11939 if (mips_tune_info
== 0)
11940 mips_set_tune (mips_arch_info
);
11942 /* Set cost structure for the processor. */
11944 mips_cost
= &mips_rtx_cost_optimize_size
;
11946 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
11948 /* If the user hasn't specified a branch cost, use the processor's
11950 if (mips_branch_cost
== 0)
11951 mips_branch_cost
= mips_cost
->branch_cost
;
11953 if ((target_flags_explicit
& MASK_64BIT
) != 0)
11955 /* The user specified the size of the integer registers. Make sure
11956 it agrees with the ABI and ISA. */
11957 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
11958 error ("-mgp64 used with a 32-bit processor");
11959 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
11960 error ("-mgp32 used with a 64-bit ABI");
11961 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
11962 error ("-mgp64 used with a 32-bit ABI");
11966 /* Infer the integer register size from the ABI and processor.
11967 Restrict ourselves to 32-bit registers if that's all the
11968 processor has, or if the ABI cannot handle 64-bit registers. */
11969 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
11970 target_flags
&= ~MASK_64BIT
;
11972 target_flags
|= MASK_64BIT
;
11975 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
11977 /* Really, -mfp32 and -mfp64 are ornamental options. There's
11978 only one right answer here. */
11979 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
11980 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
11981 else if (!TARGET_64BIT
&& TARGET_FLOAT64
11982 && !(ISA_HAS_MXHC1
&& mips_abi
== ABI_32
))
11983 error ("-mgp32 and -mfp64 can only be combined if the target"
11984 " supports the mfhc1 and mthc1 instructions");
11985 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
11986 error ("unsupported combination: %s", "-mfp64 -msingle-float");
11990 /* -msingle-float selects 32-bit float registers. Otherwise the
11991 float registers should be the same size as the integer ones. */
11992 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
11993 target_flags
|= MASK_FLOAT64
;
11995 target_flags
&= ~MASK_FLOAT64
;
11998 /* End of code shared with GAS. */
12000 if ((target_flags_explicit
& MASK_LONG64
) == 0)
12002 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
12003 target_flags
|= MASK_LONG64
;
12005 target_flags
&= ~MASK_LONG64
;
12008 if (!TARGET_OLDABI
)
12009 flag_pcc_struct_return
= 0;
12011 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
12013 /* If neither -mbranch-likely nor -mno-branch-likely was given
12014 on the command line, set MASK_BRANCHLIKELY based on the target
12015 architecture and tuning flags. Annulled delay slots are a
12016 size win, so we only consider the processor-specific tuning
12017 for !optimize_size. */
12018 if (ISA_HAS_BRANCHLIKELY
12020 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
12021 target_flags
|= MASK_BRANCHLIKELY
;
12023 target_flags
&= ~MASK_BRANCHLIKELY
;
12025 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
12026 warning (0, "the %qs architecture does not support branch-likely"
12027 " instructions", mips_arch_info
->name
);
12029 /* The effect of -mabicalls isn't defined for the EABI. */
12030 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
12032 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12033 target_flags
&= ~MASK_ABICALLS
;
12036 /* MIPS16 cannot generate PIC yet. */
12037 if (TARGET_MIPS16
&& (flag_pic
|| TARGET_ABICALLS
))
12039 sorry ("MIPS16 PIC");
12040 target_flags
&= ~MASK_ABICALLS
;
12041 flag_pic
= flag_pie
= flag_shlib
= 0;
12044 if (TARGET_ABICALLS
)
12045 /* We need to set flag_pic for executables as well as DSOs
12046 because we may reference symbols that are not defined in
12047 the final executable. (MIPS does not use things like
12048 copy relocs, for example.)
12050 Also, there is a body of code that uses __PIC__ to distinguish
12051 between -mabicalls and -mno-abicalls code. */
12054 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12055 faster code, but at the expense of more nops. Enable it at -O3 and
12057 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
12058 target_flags
|= MASK_VR4130_ALIGN
;
12060 /* Prefer a call to memcpy over inline code when optimizing for size,
12061 though see MOVE_RATIO in mips.h. */
12062 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
12063 target_flags
|= MASK_MEMCPY
;
12065 /* If we have a nonzero small-data limit, check that the -mgpopt
12066 setting is consistent with the other target flags. */
12067 if (mips_section_threshold
> 0)
12071 if (!TARGET_MIPS16
&& !TARGET_EXPLICIT_RELOCS
)
12072 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12074 TARGET_LOCAL_SDATA
= false;
12075 TARGET_EXTERN_SDATA
= false;
12079 if (TARGET_VXWORKS_RTP
)
12080 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12082 if (TARGET_ABICALLS
)
12083 warning (0, "cannot use small-data accesses for %qs",
12088 #ifdef MIPS_TFMODE_FORMAT
12089 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
12092 /* Make sure that the user didn't turn off paired single support when
12093 MIPS-3D support is requested. */
12094 if (TARGET_MIPS3D
&& (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
12095 && !TARGET_PAIRED_SINGLE_FLOAT
)
12096 error ("-mips3d requires -mpaired-single");
12098 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12100 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
12102 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12103 and TARGET_HARD_FLOAT_ABI are both true. */
12104 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
12105 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
12107 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12109 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_MIPS64
)
12110 error ("-mips3d/-mpaired-single must be used with -mips64");
12112 /* If TARGET_DSPR2, enable MASK_DSP. */
12114 target_flags
|= MASK_DSP
;
12116 mips_init_print_operand_punct ();
12118 /* Set up array to map GCC register number to debug register number.
12119 Ignore the special purpose register numbers. */
12121 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12123 mips_dbx_regno
[i
] = INVALID_REGNUM
;
12124 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
12125 mips_dwarf_regno
[i
] = i
;
12127 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
12130 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
12131 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
12132 mips_dbx_regno
[i
] = i
+ start
;
12134 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
12135 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
12136 mips_dbx_regno
[i
] = i
+ start
;
12138 /* HI and LO debug registers use big-endian ordering. */
12139 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
12140 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
12141 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
12142 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
12143 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
12145 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
12146 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
12149 /* Set up mips_hard_regno_mode_ok. */
12150 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
12151 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12152 mips_hard_regno_mode_ok
[(int)mode
][regno
]
12153 = mips_hard_regno_mode_ok_p (regno
, mode
);
12155 /* Function to allocate machine-dependent function status. */
12156 init_machine_status
= &mips_init_machine_status
;
12158 /* Default to working around R4000 errata only if the processor
12159 was selected explicitly. */
12160 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
12161 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
12162 target_flags
|= MASK_FIX_R4000
;
12164 /* Default to working around R4400 errata only if the processor
12165 was selected explicitly. */
12166 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
12167 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
12168 target_flags
|= MASK_FIX_R4400
;
12170 /* Save base state of options. */
12171 mips_base_mips16
= TARGET_MIPS16
;
12172 mips_base_target_flags
= target_flags
;
12173 mips_flag_delayed_branch
= flag_delayed_branch
;
12174 mips_base_schedule_insns
= flag_schedule_insns
;
12175 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
12176 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
12177 mips_base_align_loops
= align_loops
;
12178 mips_base_align_jumps
= align_jumps
;
12179 mips_base_align_functions
= align_functions
;
12181 /* Now select the mips16 or 32-bit instruction set, as requested. */
12182 mips_set_mips16_mode (mips_base_mips16
);
12185 /* Swap the register information for registers I and I + 1, which
12186 currently have the wrong endianness. Note that the registers'
12187 fixedness and call-clobberedness might have been set on the
12191 mips_swap_registers (unsigned int i
)
12196 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12197 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12199 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
12200 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
12201 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
12202 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
12208 /* Implement CONDITIONAL_REGISTER_USAGE. */
12211 mips_conditional_register_usage (void)
12217 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
12218 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12220 if (!TARGET_HARD_FLOAT
)
12224 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
12225 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12226 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
12227 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12229 else if (! ISA_HAS_8CC
)
12233 /* We only have a single condition code register. We
12234 implement this by hiding all the condition code registers,
12235 and generating RTL that refers directly to ST_REG_FIRST. */
12236 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
12237 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12239 /* In mips16 mode, we permit the $t temporary registers to be used
12240 for reload. We prohibit the unused $s registers, since they
12241 are caller saved, and saving them via a mips16 register would
12242 probably waste more time than just reloading the value. */
12245 fixed_regs
[18] = call_used_regs
[18] = 1;
12246 fixed_regs
[19] = call_used_regs
[19] = 1;
12247 fixed_regs
[20] = call_used_regs
[20] = 1;
12248 fixed_regs
[21] = call_used_regs
[21] = 1;
12249 fixed_regs
[22] = call_used_regs
[22] = 1;
12250 fixed_regs
[23] = call_used_regs
[23] = 1;
12251 fixed_regs
[26] = call_used_regs
[26] = 1;
12252 fixed_regs
[27] = call_used_regs
[27] = 1;
12253 fixed_regs
[30] = call_used_regs
[30] = 1;
12255 /* fp20-23 are now caller saved. */
12256 if (mips_abi
== ABI_64
)
12259 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
12260 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
12262 /* Odd registers from fp21 to fp31 are now caller saved. */
12263 if (mips_abi
== ABI_N32
)
12266 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
12267 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
12269 /* Make sure that double-register accumulator values are correctly
12270 ordered for the current endianness. */
12271 if (TARGET_LITTLE_ENDIAN
)
12274 mips_swap_registers (MD_REG_FIRST
);
12275 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
12276 mips_swap_registers (regno
);
12280 /* On the mips16, we want to allocate $24 (T_REG) before other
12281 registers for instructions for which it is possible. This helps
12282 avoid shuffling registers around in order to set up for an xor,
12283 encouraging the compiler to use a cmp instead. */
12286 mips_order_regs_for_local_alloc (void)
12290 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12291 reg_alloc_order
[i
] = i
;
12295 /* It really doesn't matter where we put register 0, since it is
12296 a fixed register anyhow. */
12297 reg_alloc_order
[0] = 24;
12298 reg_alloc_order
[24] = 0;
12302 /* Initialize the GCC target structure. */
12303 #undef TARGET_ASM_ALIGNED_HI_OP
12304 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
12305 #undef TARGET_ASM_ALIGNED_SI_OP
12306 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
12307 #undef TARGET_ASM_ALIGNED_DI_OP
12308 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
12310 #undef TARGET_ASM_FUNCTION_PROLOGUE
12311 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
12312 #undef TARGET_ASM_FUNCTION_EPILOGUE
12313 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
12314 #undef TARGET_ASM_SELECT_RTX_SECTION
12315 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
12316 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
12317 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
12319 #undef TARGET_SCHED_INIT
12320 #define TARGET_SCHED_INIT mips_sched_init
12321 #undef TARGET_SCHED_REORDER
12322 #define TARGET_SCHED_REORDER mips_sched_reorder
12323 #undef TARGET_SCHED_REORDER2
12324 #define TARGET_SCHED_REORDER2 mips_sched_reorder
12325 #undef TARGET_SCHED_VARIABLE_ISSUE
12326 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
12327 #undef TARGET_SCHED_ADJUST_COST
12328 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
12329 #undef TARGET_SCHED_ISSUE_RATE
12330 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
12331 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12332 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12333 mips_multipass_dfa_lookahead
12335 #undef TARGET_DEFAULT_TARGET_FLAGS
12336 #define TARGET_DEFAULT_TARGET_FLAGS \
12338 | TARGET_CPU_DEFAULT \
12339 | TARGET_ENDIAN_DEFAULT \
12340 | TARGET_FP_EXCEPTIONS_DEFAULT \
12341 | MASK_CHECK_ZERO_DIV \
12343 #undef TARGET_HANDLE_OPTION
12344 #define TARGET_HANDLE_OPTION mips_handle_option
12346 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12347 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
12349 #undef TARGET_INSERT_ATTRIBUTES
12350 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
12351 #undef TARGET_MERGE_DECL_ATTRIBUTES
12352 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
12353 #undef TARGET_SET_CURRENT_FUNCTION
12354 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
12356 #undef TARGET_VALID_POINTER_MODE
12357 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
12358 #undef TARGET_RTX_COSTS
12359 #define TARGET_RTX_COSTS mips_rtx_costs
12360 #undef TARGET_ADDRESS_COST
12361 #define TARGET_ADDRESS_COST mips_address_cost
12363 #undef TARGET_IN_SMALL_DATA_P
12364 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
12366 #undef TARGET_MACHINE_DEPENDENT_REORG
12367 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
12369 #undef TARGET_ASM_FILE_START
12370 #define TARGET_ASM_FILE_START mips_file_start
12371 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12372 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12374 #undef TARGET_INIT_LIBFUNCS
12375 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
12377 #undef TARGET_BUILD_BUILTIN_VA_LIST
12378 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
12379 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12380 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
12382 #undef TARGET_PROMOTE_FUNCTION_ARGS
12383 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
12384 #undef TARGET_PROMOTE_FUNCTION_RETURN
12385 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
12386 #undef TARGET_PROMOTE_PROTOTYPES
12387 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
12389 #undef TARGET_RETURN_IN_MEMORY
12390 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
12391 #undef TARGET_RETURN_IN_MSB
12392 #define TARGET_RETURN_IN_MSB mips_return_in_msb
12394 #undef TARGET_ASM_OUTPUT_MI_THUNK
12395 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
12396 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12397 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12399 #undef TARGET_SETUP_INCOMING_VARARGS
12400 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
12401 #undef TARGET_STRICT_ARGUMENT_NAMING
12402 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
12403 #undef TARGET_MUST_PASS_IN_STACK
12404 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12405 #undef TARGET_PASS_BY_REFERENCE
12406 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
12407 #undef TARGET_CALLEE_COPIES
12408 #define TARGET_CALLEE_COPIES mips_callee_copies
12409 #undef TARGET_ARG_PARTIAL_BYTES
12410 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
12412 #undef TARGET_MODE_REP_EXTENDED
12413 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
12415 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12416 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
12418 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12419 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
12421 #undef TARGET_INIT_BUILTINS
12422 #define TARGET_INIT_BUILTINS mips_init_builtins
12423 #undef TARGET_EXPAND_BUILTIN
12424 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
12426 #undef TARGET_HAVE_TLS
12427 #define TARGET_HAVE_TLS HAVE_AS_TLS
12429 #undef TARGET_CANNOT_FORCE_CONST_MEM
12430 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
12432 #undef TARGET_ENCODE_SECTION_INFO
12433 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
12435 #undef TARGET_ATTRIBUTE_TABLE
12436 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
12437 /* All our function attributes are related to how out-of-line copies should
12438 be compiled or called. They don't in themselves prevent inlining. */
12439 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
12440 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
12442 #undef TARGET_EXTRA_LIVE_ON_ENTRY
12443 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
12445 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12446 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
12447 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
12448 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
12450 #undef TARGET_COMP_TYPE_ATTRIBUTES
12451 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
12453 #ifdef HAVE_AS_DTPRELWORD
12454 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12455 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
12457 #undef TARGET_DWARF_REGISTER_SPAN
12458 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
12460 struct gcc_target targetm
= TARGET_INITIALIZER
;
12462 #include "gt-mips.h"